1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
95 #include "stor-layout.h"
97 #include "cfgcleanup.h"
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
100 #include "insn-attr.h"
101 #include "rtlhooks-def.h"
103 #include "tree-pass.h"
104 #include "valtrack.h"
105 #include "rtl-iter.h"
106 #include "print-rtl.h"
108 /* Number of attempts to combine instructions in this function. */
110 static int combine_attempts
;
112 /* Number of attempts that got as far as substitution in this function. */
114 static int combine_merges
;
116 /* Number of instructions combined with added SETs in this function. */
118 static int combine_extras
;
120 /* Number of instructions combined in this function. */
122 static int combine_successes
;
124 /* Totals over entire compilation. */
126 static int total_attempts
, total_merges
, total_extras
, total_successes
;
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
135 static rtx_insn
*i2mod
;
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
139 static rtx i2mod_old_rhs
;
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143 static rtx i2mod_new_rhs
;
145 struct reg_stat_type
{
146 /* Record last point of death of (hard or pseudo) register n. */
147 rtx_insn
*last_death
;
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
202 int last_set_table_tick
;
204 /* Record the value of label_tick when the value for register n is placed in
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
214 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
215 char last_set_sign_bit_copies
;
216 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
222 char last_set_invalid
;
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
234 If an entry is zero, it means that we don't know anything special. */
236 unsigned char sign_bit_copies
;
238 unsigned HOST_WIDE_INT nonzero_bits
;
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
244 int truncation_label
;
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
251 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
255 static vec
<reg_stat_type
> reg_stat
;
257 /* One plus the highest pseudo for which we track REG_N_SETS.
258 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
259 but during combine_split_insns new pseudos can be created. As we don't have
260 updated DF information in that case, it is hard to initialize the array
261 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
262 so instead of growing the arrays, just assume all newly created pseudos
263 during combine might be set multiple times. */
265 static unsigned int reg_n_sets_max
;
267 /* Record the luid of the last insn that invalidated memory
268 (anything that writes memory, and subroutine calls, but not pushes). */
270 static int mem_last_set
;
272 /* Record the luid of the last CALL_INSN
273 so we can tell whether a potential combination crosses any calls. */
275 static int last_call_luid
;
277 /* When `subst' is called, this is the insn that is being modified
278 (by combining in a previous insn). The PATTERN of this insn
279 is still the old pattern partially modified and it should not be
280 looked at, but this may be used to examine the successors of the insn
281 to judge whether a simplification is valid. */
283 static rtx_insn
*subst_insn
;
285 /* This is the lowest LUID that `subst' is currently dealing with.
286 get_last_value will not return a value if the register was set at or
287 after this LUID. If not for this mechanism, we could get confused if
288 I2 or I1 in try_combine were an insn that used the old value of a register
289 to obtain a new value. In that case, we might erroneously get the
290 new value of the register when we wanted the old one. */
292 static int subst_low_luid
;
294 /* This contains any hard registers that are used in newpat; reg_dead_at_p
295 must consider all these registers to be always live. */
297 static HARD_REG_SET newpat_used_regs
;
299 /* This is an insn to which a LOG_LINKS entry has been added. If this
300 insn is the earlier than I2 or I3, combine should rescan starting at
303 static rtx_insn
*added_links_insn
;
305 /* Basic block in which we are performing combines. */
306 static basic_block this_basic_block
;
307 static bool optimize_this_for_speed_p
;
310 /* Length of the currently allocated uid_insn_cost array. */
312 static int max_uid_known
;
314 /* The following array records the insn_rtx_cost for every insn
315 in the instruction stream. */
317 static int *uid_insn_cost
;
319 /* The following array records the LOG_LINKS for every insn in the
320 instruction stream as struct insn_link pointers. */
325 struct insn_link
*next
;
328 static struct insn_link
**uid_log_links
;
331 insn_uid_check (const_rtx insn
)
333 int uid
= INSN_UID (insn
);
334 gcc_checking_assert (uid
<= max_uid_known
);
338 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
339 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
341 #define FOR_EACH_LOG_LINK(L, INSN) \
342 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
344 /* Links for LOG_LINKS are allocated from this obstack. */
346 static struct obstack insn_link_obstack
;
348 /* Allocate a link. */
350 static inline struct insn_link
*
351 alloc_insn_link (rtx_insn
*insn
, unsigned int regno
, struct insn_link
*next
)
354 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
355 sizeof (struct insn_link
));
362 /* Incremented for each basic block. */
364 static int label_tick
;
366 /* Reset to label_tick for each extended basic block in scanning order. */
368 static int label_tick_ebb_start
;
370 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
371 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
373 static machine_mode nonzero_bits_mode
;
375 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
376 be safely used. It is zero while computing them and after combine has
377 completed. This former test prevents propagating values based on
378 previously set values, which can be incorrect if a variable is modified
381 static int nonzero_sign_valid
;
384 /* Record one modification to rtl structure
385 to be undone by storing old_contents into *where. */
387 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
393 union { rtx r
; int i
; machine_mode m
; struct insn_link
*l
; } old_contents
;
394 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
397 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
398 num_undo says how many are currently recorded.
400 other_insn is nonzero if we have modified some other insn in the process
401 of working on subst_insn. It must be verified too. */
407 rtx_insn
*other_insn
;
410 static struct undobuf undobuf
;
412 /* Number of times the pseudo being substituted for
413 was found and replaced. */
415 static int n_occurrences
;
417 static rtx
reg_nonzero_bits_for_combine (const_rtx
, machine_mode
, const_rtx
,
419 unsigned HOST_WIDE_INT
,
420 unsigned HOST_WIDE_INT
*);
421 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, machine_mode
, const_rtx
,
423 unsigned int, unsigned int *);
424 static void do_SUBST (rtx
*, rtx
);
425 static void do_SUBST_INT (int *, int);
426 static void init_reg_last (void);
427 static void setup_incoming_promotions (rtx_insn
*);
428 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
429 static int cant_combine_insn_p (rtx_insn
*);
430 static int can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
431 rtx_insn
*, rtx_insn
*, rtx
*, rtx
*);
432 static int combinable_i3pat (rtx_insn
*, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
433 static int contains_muldiv (rtx
);
434 static rtx_insn
*try_combine (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
436 static void undo_all (void);
437 static void undo_commit (void);
438 static rtx
*find_split_point (rtx
*, rtx_insn
*, bool);
439 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
440 static rtx
combine_simplify_rtx (rtx
, machine_mode
, int, int);
441 static rtx
simplify_if_then_else (rtx
);
442 static rtx
simplify_set (rtx
);
443 static rtx
simplify_logical (rtx
);
444 static rtx
expand_compound_operation (rtx
);
445 static const_rtx
expand_field_assignment (const_rtx
);
446 static rtx
make_extraction (machine_mode
, rtx
, HOST_WIDE_INT
,
447 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
448 static rtx
extract_left_shift (rtx
, int);
449 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
450 unsigned HOST_WIDE_INT
*);
451 static rtx
canon_reg_for_combine (rtx
, rtx
);
452 static rtx
force_to_mode (rtx
, machine_mode
,
453 unsigned HOST_WIDE_INT
, int);
454 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
455 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
456 static int rtx_equal_for_field_assignment_p (rtx
, rtx
, bool = false);
457 static rtx
make_field_assignment (rtx
);
458 static rtx
apply_distributive_law (rtx
);
459 static rtx
distribute_and_simplify_rtx (rtx
, int);
460 static rtx
simplify_and_const_int_1 (machine_mode
, rtx
,
461 unsigned HOST_WIDE_INT
);
462 static rtx
simplify_and_const_int (rtx
, machine_mode
, rtx
,
463 unsigned HOST_WIDE_INT
);
464 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
465 HOST_WIDE_INT
, machine_mode
, int *);
466 static rtx
simplify_shift_const_1 (enum rtx_code
, machine_mode
, rtx
, int);
467 static rtx
simplify_shift_const (rtx
, enum rtx_code
, machine_mode
, rtx
,
469 static int recog_for_combine (rtx
*, rtx_insn
*, rtx
*);
470 static rtx
gen_lowpart_for_combine (machine_mode
, rtx
);
471 static enum rtx_code
simplify_compare_const (enum rtx_code
, machine_mode
,
473 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
474 static void update_table_tick (rtx
);
475 static void record_value_for_reg (rtx
, rtx_insn
*, rtx
);
476 static void check_promoted_subreg (rtx_insn
*, rtx
);
477 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
478 static void record_dead_and_set_regs (rtx_insn
*);
479 static int get_last_value_validate (rtx
*, rtx_insn
*, int, int);
480 static rtx
get_last_value (const_rtx
);
481 static int use_crosses_set_p (const_rtx
, int);
482 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
483 static int reg_dead_at_p (rtx
, rtx_insn
*);
484 static void move_deaths (rtx
, rtx
, int, rtx_insn
*, rtx
*);
485 static int reg_bitfield_target_p (rtx
, rtx
);
486 static void distribute_notes (rtx
, rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx
, rtx
, rtx
);
487 static void distribute_links (struct insn_link
*);
488 static void mark_used_regs_combine (rtx
);
489 static void record_promoted_value (rtx_insn
*, rtx
);
490 static bool unmentioned_reg_p (rtx
, rtx
);
491 static void record_truncated_values (rtx
*, void *);
492 static bool reg_truncated_to_mode (machine_mode
, const_rtx
);
493 static rtx
gen_lowpart_or_truncate (machine_mode
, rtx
);
496 /* It is not safe to use ordinary gen_lowpart in combine.
497 See comments in gen_lowpart_for_combine. */
498 #undef RTL_HOOKS_GEN_LOWPART
499 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
501 /* Our implementation of gen_lowpart never emits a new pseudo. */
502 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
503 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
505 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
506 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
508 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
509 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
511 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
512 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
514 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
517 /* Convenience wrapper for the canonicalize_comparison target hook.
518 Target hooks cannot use enum rtx_code. */
520 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
521 bool op0_preserve_value
)
523 int code_int
= (int)*code
;
524 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
525 *code
= (enum rtx_code
)code_int
;
528 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
529 PATTERN can not be split. Otherwise, it returns an insn sequence.
530 This is a wrapper around split_insns which ensures that the
531 reg_stat vector is made larger if the splitter creates a new
535 combine_split_insns (rtx pattern
, rtx_insn
*insn
)
540 ret
= split_insns (pattern
, insn
);
541 nregs
= max_reg_num ();
542 if (nregs
> reg_stat
.length ())
543 reg_stat
.safe_grow_cleared (nregs
);
547 /* This is used by find_single_use to locate an rtx in LOC that
548 contains exactly one use of DEST, which is typically either a REG
549 or CC0. It returns a pointer to the innermost rtx expression
550 containing DEST. Appearances of DEST that are being used to
551 totally replace it are not counted. */
554 find_single_use_1 (rtx dest
, rtx
*loc
)
557 enum rtx_code code
= GET_CODE (x
);
573 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
574 of a REG that occupies all of the REG, the insn uses DEST if
575 it is mentioned in the destination or the source. Otherwise, we
576 need just check the source. */
577 if (GET_CODE (SET_DEST (x
)) != CC0
578 && GET_CODE (SET_DEST (x
)) != PC
579 && !REG_P (SET_DEST (x
))
580 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
581 && REG_P (SUBREG_REG (SET_DEST (x
)))
582 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
583 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
584 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
585 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
588 return find_single_use_1 (dest
, &SET_SRC (x
));
592 return find_single_use_1 (dest
, &XEXP (x
, 0));
598 /* If it wasn't one of the common cases above, check each expression and
599 vector of this code. Look for a unique usage of DEST. */
601 fmt
= GET_RTX_FORMAT (code
);
602 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
606 if (dest
== XEXP (x
, i
)
607 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
608 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
611 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
614 result
= this_result
;
615 else if (this_result
)
616 /* Duplicate usage. */
619 else if (fmt
[i
] == 'E')
623 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
625 if (XVECEXP (x
, i
, j
) == dest
627 && REG_P (XVECEXP (x
, i
, j
))
628 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
631 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
634 result
= this_result
;
635 else if (this_result
)
645 /* See if DEST, produced in INSN, is used only a single time in the
646 sequel. If so, return a pointer to the innermost rtx expression in which
649 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
651 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
652 care about REG_DEAD notes or LOG_LINKS.
654 Otherwise, we find the single use by finding an insn that has a
655 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
656 only referenced once in that insn, we know that it must be the first
657 and last insn referencing DEST. */
660 find_single_use (rtx dest
, rtx_insn
*insn
, rtx_insn
**ploc
)
665 struct insn_link
*link
;
669 next
= NEXT_INSN (insn
);
671 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
674 result
= find_single_use_1 (dest
, &PATTERN (next
));
683 bb
= BLOCK_FOR_INSN (insn
);
684 for (next
= NEXT_INSN (insn
);
685 next
&& BLOCK_FOR_INSN (next
) == bb
;
686 next
= NEXT_INSN (next
))
687 if (NONDEBUG_INSN_P (next
) && dead_or_set_p (next
, dest
))
689 FOR_EACH_LOG_LINK (link
, next
)
690 if (link
->insn
== insn
&& link
->regno
== REGNO (dest
))
695 result
= find_single_use_1 (dest
, &PATTERN (next
));
705 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
706 insn. The substitution can be undone by undo_all. If INTO is already
707 set to NEWVAL, do not record this change. Because computing NEWVAL might
708 also call SUBST, we have to compute it before we put anything into
712 do_SUBST (rtx
*into
, rtx newval
)
717 if (oldval
== newval
)
720 /* We'd like to catch as many invalid transformations here as
721 possible. Unfortunately, there are way too many mode changes
722 that are perfectly valid, so we'd waste too much effort for
723 little gain doing the checks here. Focus on catching invalid
724 transformations involving integer constants. */
725 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
726 && CONST_INT_P (newval
))
728 /* Sanity check that we're replacing oldval with a CONST_INT
729 that is a valid sign-extension for the original mode. */
730 gcc_assert (INTVAL (newval
)
731 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
733 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
734 CONST_INT is not valid, because after the replacement, the
735 original mode would be gone. Unfortunately, we can't tell
736 when do_SUBST is called to replace the operand thereof, so we
737 perform this test on oldval instead, checking whether an
738 invalid replacement took place before we got here. */
739 gcc_assert (!(GET_CODE (oldval
) == SUBREG
740 && CONST_INT_P (SUBREG_REG (oldval
))));
741 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
742 && CONST_INT_P (XEXP (oldval
, 0))));
746 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
748 buf
= XNEW (struct undo
);
750 buf
->kind
= UNDO_RTX
;
752 buf
->old_contents
.r
= oldval
;
755 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
758 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
760 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
761 for the value of a HOST_WIDE_INT value (including CONST_INT) is
765 do_SUBST_INT (int *into
, int newval
)
770 if (oldval
== newval
)
774 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
776 buf
= XNEW (struct undo
);
778 buf
->kind
= UNDO_INT
;
780 buf
->old_contents
.i
= oldval
;
783 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
786 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
788 /* Similar to SUBST, but just substitute the mode. This is used when
789 changing the mode of a pseudo-register, so that any other
790 references to the entry in the regno_reg_rtx array will change as
794 do_SUBST_MODE (rtx
*into
, machine_mode newval
)
797 machine_mode oldval
= GET_MODE (*into
);
799 if (oldval
== newval
)
803 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
805 buf
= XNEW (struct undo
);
807 buf
->kind
= UNDO_MODE
;
809 buf
->old_contents
.m
= oldval
;
810 adjust_reg_mode (*into
, newval
);
812 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
815 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
817 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
820 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
823 struct insn_link
* oldval
= *into
;
825 if (oldval
== newval
)
829 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
831 buf
= XNEW (struct undo
);
833 buf
->kind
= UNDO_LINKS
;
835 buf
->old_contents
.l
= oldval
;
838 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
841 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
843 /* Subroutine of try_combine. Determine whether the replacement patterns
844 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
845 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
846 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
847 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
848 of all the instructions can be estimated and the replacements are more
849 expensive than the original sequence. */
852 combine_validate_cost (rtx_insn
*i0
, rtx_insn
*i1
, rtx_insn
*i2
, rtx_insn
*i3
,
853 rtx newpat
, rtx newi2pat
, rtx newotherpat
)
855 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
856 int new_i2_cost
, new_i3_cost
;
857 int old_cost
, new_cost
;
859 /* Lookup the original insn_rtx_costs. */
860 i2_cost
= INSN_COST (i2
);
861 i3_cost
= INSN_COST (i3
);
865 i1_cost
= INSN_COST (i1
);
868 i0_cost
= INSN_COST (i0
);
869 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
870 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
874 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
875 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
881 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
882 i1_cost
= i0_cost
= 0;
885 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
887 if (old_cost
&& i1
&& INSN_UID (i1
) == INSN_UID (i2
))
891 /* Calculate the replacement insn_rtx_costs. */
892 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
895 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
896 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
897 ? new_i2_cost
+ new_i3_cost
: 0;
901 new_cost
= new_i3_cost
;
905 if (undobuf
.other_insn
)
907 int old_other_cost
, new_other_cost
;
909 old_other_cost
= INSN_COST (undobuf
.other_insn
);
910 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
911 if (old_other_cost
> 0 && new_other_cost
> 0)
913 old_cost
+= old_other_cost
;
914 new_cost
+= new_other_cost
;
920 /* Disallow this combination if both new_cost and old_cost are greater than
921 zero, and new_cost is greater than old cost. */
922 int reject
= old_cost
> 0 && new_cost
> old_cost
;
926 fprintf (dump_file
, "%s combination of insns ",
927 reject
? "rejecting" : "allowing");
929 fprintf (dump_file
, "%d, ", INSN_UID (i0
));
930 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
931 fprintf (dump_file
, "%d, ", INSN_UID (i1
));
932 fprintf (dump_file
, "%d and %d\n", INSN_UID (i2
), INSN_UID (i3
));
934 fprintf (dump_file
, "original costs ");
936 fprintf (dump_file
, "%d + ", i0_cost
);
937 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
938 fprintf (dump_file
, "%d + ", i1_cost
);
939 fprintf (dump_file
, "%d + %d = %d\n", i2_cost
, i3_cost
, old_cost
);
942 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
943 new_i2_cost
, new_i3_cost
, new_cost
);
945 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
951 /* Update the uid_insn_cost array with the replacement costs. */
952 INSN_COST (i2
) = new_i2_cost
;
953 INSN_COST (i3
) = new_i3_cost
;
965 /* Delete any insns that copy a register to itself. */
968 delete_noop_moves (void)
970 rtx_insn
*insn
, *next
;
973 FOR_EACH_BB_FN (bb
, cfun
)
975 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
977 next
= NEXT_INSN (insn
);
978 if (INSN_P (insn
) && noop_move_p (insn
))
981 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
983 delete_insn_and_edges (insn
);
990 /* Return false if we do not want to (or cannot) combine DEF. */
992 can_combine_def_p (df_ref def
)
994 /* Do not consider if it is pre/post modification in MEM. */
995 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
998 unsigned int regno
= DF_REF_REGNO (def
);
1000 /* Do not combine frame pointer adjustments. */
1001 if ((regno
== FRAME_POINTER_REGNUM
1002 && (!reload_completed
|| frame_pointer_needed
))
1003 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1004 && regno
== HARD_FRAME_POINTER_REGNUM
1005 && (!reload_completed
|| frame_pointer_needed
))
1006 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1007 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
]))
1013 /* Return false if we do not want to (or cannot) combine USE. */
1015 can_combine_use_p (df_ref use
)
1017 /* Do not consider the usage of the stack pointer by function call. */
1018 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1024 /* Fill in log links field for all insns. */
1027 create_log_links (void)
1030 rtx_insn
**next_use
;
1034 next_use
= XCNEWVEC (rtx_insn
*, max_reg_num ());
1036 /* Pass through each block from the end, recording the uses of each
1037 register and establishing log links when def is encountered.
1038 Note that we do not clear next_use array in order to save time,
1039 so we have to test whether the use is in the same basic block as def.
1041 There are a few cases below when we do not consider the definition or
1042 usage -- these are taken from original flow.c did. Don't ask me why it is
1043 done this way; I don't know and if it works, I don't want to know. */
1045 FOR_EACH_BB_FN (bb
, cfun
)
1047 FOR_BB_INSNS_REVERSE (bb
, insn
)
1049 if (!NONDEBUG_INSN_P (insn
))
1052 /* Log links are created only once. */
1053 gcc_assert (!LOG_LINKS (insn
));
1055 FOR_EACH_INSN_DEF (def
, insn
)
1057 unsigned int regno
= DF_REF_REGNO (def
);
1060 if (!next_use
[regno
])
1063 if (!can_combine_def_p (def
))
1066 use_insn
= next_use
[regno
];
1067 next_use
[regno
] = NULL
;
1069 if (BLOCK_FOR_INSN (use_insn
) != bb
)
1074 We don't build a LOG_LINK for hard registers contained
1075 in ASM_OPERANDs. If these registers get replaced,
1076 we might wind up changing the semantics of the insn,
1077 even if reload can make what appear to be valid
1078 assignments later. */
1079 if (regno
< FIRST_PSEUDO_REGISTER
1080 && asm_noperands (PATTERN (use_insn
)) >= 0)
1083 /* Don't add duplicate links between instructions. */
1084 struct insn_link
*links
;
1085 FOR_EACH_LOG_LINK (links
, use_insn
)
1086 if (insn
== links
->insn
&& regno
== links
->regno
)
1090 LOG_LINKS (use_insn
)
1091 = alloc_insn_link (insn
, regno
, LOG_LINKS (use_insn
));
1094 FOR_EACH_INSN_USE (use
, insn
)
1095 if (can_combine_use_p (use
))
1096 next_use
[DF_REF_REGNO (use
)] = insn
;
1103 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1104 true if we found a LOG_LINK that proves that A feeds B. This only works
1105 if there are no instructions between A and B which could have a link
1106 depending on A, since in that case we would not record a link for B.
1107 We also check the implicit dependency created by a cc0 setter/user
1111 insn_a_feeds_b (rtx_insn
*a
, rtx_insn
*b
)
1113 struct insn_link
*links
;
1114 FOR_EACH_LOG_LINK (links
, b
)
1115 if (links
->insn
== a
)
1117 if (HAVE_cc0
&& sets_cc0_p (a
))
1122 /* Main entry point for combiner. F is the first insn of the function.
1123 NREGS is the first unused pseudo-reg number.
1125 Return nonzero if the combiner has turned an indirect jump
1126 instruction into a direct jump. */
1128 combine_instructions (rtx_insn
*f
, unsigned int nregs
)
1130 rtx_insn
*insn
, *next
;
1132 struct insn_link
*links
, *nextlinks
;
1134 basic_block last_bb
;
1136 int new_direct_jump_p
= 0;
1138 for (first
= f
; first
&& !NONDEBUG_INSN_P (first
); )
1139 first
= NEXT_INSN (first
);
1143 combine_attempts
= 0;
1146 combine_successes
= 0;
1148 rtl_hooks
= combine_rtl_hooks
;
1150 reg_stat
.safe_grow_cleared (nregs
);
1152 init_recog_no_volatile ();
1154 /* Allocate array for insn info. */
1155 max_uid_known
= get_max_uid ();
1156 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1157 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1158 gcc_obstack_init (&insn_link_obstack
);
1160 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1162 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1163 problems when, for example, we have j <<= 1 in a loop. */
1165 nonzero_sign_valid
= 0;
1166 label_tick
= label_tick_ebb_start
= 1;
1168 /* Scan all SETs and see if we can deduce anything about what
1169 bits are known to be zero for some registers and how many copies
1170 of the sign bit are known to exist for those registers.
1172 Also set any known values so that we can use it while searching
1173 for what bits are known to be set. */
1175 setup_incoming_promotions (first
);
1176 /* Allow the entry block and the first block to fall into the same EBB.
1177 Conceptually the incoming promotions are assigned to the entry block. */
1178 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1180 create_log_links ();
1181 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1183 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1188 if (!single_pred_p (this_basic_block
)
1189 || single_pred (this_basic_block
) != last_bb
)
1190 label_tick_ebb_start
= label_tick
;
1191 last_bb
= this_basic_block
;
1193 FOR_BB_INSNS (this_basic_block
, insn
)
1194 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1198 subst_low_luid
= DF_INSN_LUID (insn
);
1201 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1203 record_dead_and_set_regs (insn
);
1206 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1207 if (REG_NOTE_KIND (links
) == REG_INC
)
1208 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1211 /* Record the current insn_rtx_cost of this instruction. */
1212 if (NONJUMP_INSN_P (insn
))
1213 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1214 optimize_this_for_speed_p
);
1217 fprintf (dump_file
, "insn_cost %d for ", INSN_COST (insn
));
1218 dump_insn_slim (dump_file
, insn
);
1223 nonzero_sign_valid
= 1;
1225 /* Now scan all the insns in forward order. */
1226 label_tick
= label_tick_ebb_start
= 1;
1228 setup_incoming_promotions (first
);
1229 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1230 int max_combine
= PARAM_VALUE (PARAM_MAX_COMBINE_INSNS
);
1232 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1234 rtx_insn
*last_combined_insn
= NULL
;
1235 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1240 if (!single_pred_p (this_basic_block
)
1241 || single_pred (this_basic_block
) != last_bb
)
1242 label_tick_ebb_start
= label_tick
;
1243 last_bb
= this_basic_block
;
1245 rtl_profile_for_bb (this_basic_block
);
1246 for (insn
= BB_HEAD (this_basic_block
);
1247 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1248 insn
= next
? next
: NEXT_INSN (insn
))
1251 if (!NONDEBUG_INSN_P (insn
))
1254 while (last_combined_insn
1255 && (!NONDEBUG_INSN_P (last_combined_insn
)
1256 || last_combined_insn
->deleted ()))
1257 last_combined_insn
= PREV_INSN (last_combined_insn
);
1258 if (last_combined_insn
== NULL_RTX
1259 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1260 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1261 last_combined_insn
= insn
;
1263 /* See if we know about function return values before this
1264 insn based upon SUBREG flags. */
1265 check_promoted_subreg (insn
, PATTERN (insn
));
1267 /* See if we can find hardregs and subreg of pseudos in
1268 narrower modes. This could help turning TRUNCATEs
1270 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1272 /* Try this insn with each insn it links back to. */
1274 FOR_EACH_LOG_LINK (links
, insn
)
1275 if ((next
= try_combine (insn
, links
->insn
, NULL
,
1276 NULL
, &new_direct_jump_p
,
1277 last_combined_insn
)) != 0)
1279 statistics_counter_event (cfun
, "two-insn combine", 1);
1283 /* Try each sequence of three linked insns ending with this one. */
1285 if (max_combine
>= 3)
1286 FOR_EACH_LOG_LINK (links
, insn
)
1288 rtx_insn
*link
= links
->insn
;
1290 /* If the linked insn has been replaced by a note, then there
1291 is no point in pursuing this chain any further. */
1295 FOR_EACH_LOG_LINK (nextlinks
, link
)
1296 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1297 NULL
, &new_direct_jump_p
,
1298 last_combined_insn
)) != 0)
1300 statistics_counter_event (cfun
, "three-insn combine", 1);
1305 /* Try to combine a jump insn that uses CC0
1306 with a preceding insn that sets CC0, and maybe with its
1307 logical predecessor as well.
1308 This is how we make decrement-and-branch insns.
1309 We need this special code because data flow connections
1310 via CC0 do not get entered in LOG_LINKS. */
1314 && (prev
= prev_nonnote_insn (insn
)) != 0
1315 && NONJUMP_INSN_P (prev
)
1316 && sets_cc0_p (PATTERN (prev
)))
1318 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1320 last_combined_insn
)) != 0)
1323 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1324 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1325 NULL
, &new_direct_jump_p
,
1326 last_combined_insn
)) != 0)
1330 /* Do the same for an insn that explicitly references CC0. */
1331 if (HAVE_cc0
&& NONJUMP_INSN_P (insn
)
1332 && (prev
= prev_nonnote_insn (insn
)) != 0
1333 && NONJUMP_INSN_P (prev
)
1334 && sets_cc0_p (PATTERN (prev
))
1335 && GET_CODE (PATTERN (insn
)) == SET
1336 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1338 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1340 last_combined_insn
)) != 0)
1343 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1344 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1345 NULL
, &new_direct_jump_p
,
1346 last_combined_insn
)) != 0)
1350 /* Finally, see if any of the insns that this insn links to
1351 explicitly references CC0. If so, try this insn, that insn,
1352 and its predecessor if it sets CC0. */
1355 FOR_EACH_LOG_LINK (links
, insn
)
1356 if (NONJUMP_INSN_P (links
->insn
)
1357 && GET_CODE (PATTERN (links
->insn
)) == SET
1358 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1359 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1360 && NONJUMP_INSN_P (prev
)
1361 && sets_cc0_p (PATTERN (prev
))
1362 && (next
= try_combine (insn
, links
->insn
,
1363 prev
, NULL
, &new_direct_jump_p
,
1364 last_combined_insn
)) != 0)
1368 /* Try combining an insn with two different insns whose results it
1370 if (max_combine
>= 3)
1371 FOR_EACH_LOG_LINK (links
, insn
)
1372 for (nextlinks
= links
->next
; nextlinks
;
1373 nextlinks
= nextlinks
->next
)
1374 if ((next
= try_combine (insn
, links
->insn
,
1375 nextlinks
->insn
, NULL
,
1377 last_combined_insn
)) != 0)
1380 statistics_counter_event (cfun
, "three-insn combine", 1);
1384 /* Try four-instruction combinations. */
1385 if (max_combine
>= 4)
1386 FOR_EACH_LOG_LINK (links
, insn
)
1388 struct insn_link
*next1
;
1389 rtx_insn
*link
= links
->insn
;
1391 /* If the linked insn has been replaced by a note, then there
1392 is no point in pursuing this chain any further. */
1396 FOR_EACH_LOG_LINK (next1
, link
)
1398 rtx_insn
*link1
= next1
->insn
;
1401 /* I0 -> I1 -> I2 -> I3. */
1402 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1403 if ((next
= try_combine (insn
, link
, link1
,
1406 last_combined_insn
)) != 0)
1408 statistics_counter_event (cfun
, "four-insn combine", 1);
1411 /* I0, I1 -> I2, I2 -> I3. */
1412 for (nextlinks
= next1
->next
; nextlinks
;
1413 nextlinks
= nextlinks
->next
)
1414 if ((next
= try_combine (insn
, link
, link1
,
1417 last_combined_insn
)) != 0)
1419 statistics_counter_event (cfun
, "four-insn combine", 1);
1424 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1426 rtx_insn
*link1
= next1
->insn
;
1429 /* I0 -> I2; I1, I2 -> I3. */
1430 FOR_EACH_LOG_LINK (nextlinks
, link
)
1431 if ((next
= try_combine (insn
, link
, link1
,
1434 last_combined_insn
)) != 0)
1436 statistics_counter_event (cfun
, "four-insn combine", 1);
1439 /* I0 -> I1; I1, I2 -> I3. */
1440 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1441 if ((next
= try_combine (insn
, link
, link1
,
1444 last_combined_insn
)) != 0)
1446 statistics_counter_event (cfun
, "four-insn combine", 1);
1452 /* Try this insn with each REG_EQUAL note it links back to. */
1453 FOR_EACH_LOG_LINK (links
, insn
)
1456 rtx_insn
*temp
= links
->insn
;
1457 if ((set
= single_set (temp
)) != 0
1458 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1459 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1460 /* Avoid using a register that may already been marked
1461 dead by an earlier instruction. */
1462 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1463 && (GET_MODE (note
) == VOIDmode
1464 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1465 : (GET_MODE (SET_DEST (set
)) == GET_MODE (note
)
1466 && (GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
1467 || (GET_MODE (XEXP (SET_DEST (set
), 0))
1468 == GET_MODE (note
))))))
1470 /* Temporarily replace the set's source with the
1471 contents of the REG_EQUAL note. The insn will
1472 be deleted or recognized by try_combine. */
1473 rtx orig_src
= SET_SRC (set
);
1474 rtx orig_dest
= SET_DEST (set
);
1475 if (GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
)
1476 SET_DEST (set
) = XEXP (SET_DEST (set
), 0);
1477 SET_SRC (set
) = note
;
1479 i2mod_old_rhs
= copy_rtx (orig_src
);
1480 i2mod_new_rhs
= copy_rtx (note
);
1481 next
= try_combine (insn
, i2mod
, NULL
, NULL
,
1483 last_combined_insn
);
1487 statistics_counter_event (cfun
, "insn-with-note combine", 1);
1490 SET_SRC (set
) = orig_src
;
1491 SET_DEST (set
) = orig_dest
;
1496 record_dead_and_set_regs (insn
);
1503 default_rtl_profile ();
1505 new_direct_jump_p
|= purge_all_dead_edges ();
1506 delete_noop_moves ();
1509 obstack_free (&insn_link_obstack
, NULL
);
1510 free (uid_log_links
);
1511 free (uid_insn_cost
);
1512 reg_stat
.release ();
1515 struct undo
*undo
, *next
;
1516 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1524 total_attempts
+= combine_attempts
;
1525 total_merges
+= combine_merges
;
1526 total_extras
+= combine_extras
;
1527 total_successes
+= combine_successes
;
1529 nonzero_sign_valid
= 0;
1530 rtl_hooks
= general_rtl_hooks
;
1532 /* Make recognizer allow volatile MEMs again. */
1535 return new_direct_jump_p
;
1538 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1541 init_reg_last (void)
1546 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1547 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1550 /* Set up any promoted values for incoming argument registers. */
1553 setup_incoming_promotions (rtx_insn
*first
)
1556 bool strictly_local
= false;
1558 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1559 arg
= DECL_CHAIN (arg
))
1561 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1563 machine_mode mode1
, mode2
, mode3
, mode4
;
1565 /* Only continue if the incoming argument is in a register. */
1569 /* Determine, if possible, whether all call sites of the current
1570 function lie within the current compilation unit. (This does
1571 take into account the exporting of a function via taking its
1572 address, and so forth.) */
1573 strictly_local
= cgraph_node::local_info (current_function_decl
)->local
;
1575 /* The mode and signedness of the argument before any promotions happen
1576 (equal to the mode of the pseudo holding it at that stage). */
1577 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1578 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1580 /* The mode and signedness of the argument after any source language and
1581 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1582 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1583 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1585 /* The mode and signedness of the argument as it is actually passed,
1586 see assign_parm_setup_reg in function.c. */
1587 mode3
= promote_function_mode (TREE_TYPE (arg
), mode1
, &uns3
,
1588 TREE_TYPE (cfun
->decl
), 0);
1590 /* The mode of the register in which the argument is being passed. */
1591 mode4
= GET_MODE (reg
);
1593 /* Eliminate sign extensions in the callee when:
1594 (a) A mode promotion has occurred; */
1597 /* (b) The mode of the register is the same as the mode of
1598 the argument as it is passed; */
1601 /* (c) There's no language level extension; */
1604 /* (c.1) All callers are from the current compilation unit. If that's
1605 the case we don't have to rely on an ABI, we only have to know
1606 what we're generating right now, and we know that we will do the
1607 mode1 to mode2 promotion with the given sign. */
1608 else if (!strictly_local
)
1610 /* (c.2) The combination of the two promotions is useful. This is
1611 true when the signs match, or if the first promotion is unsigned.
1612 In the later case, (sign_extend (zero_extend x)) is the same as
1613 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1619 /* Record that the value was promoted from mode1 to mode3,
1620 so that any sign extension at the head of the current
1621 function may be eliminated. */
1622 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1623 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1624 record_value_for_reg (reg
, first
, x
);
1628 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1629 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1630 because some machines (maybe most) will actually do the sign-extension and
1631 this is the conservative approach.
1633 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1637 sign_extend_short_imm (rtx src
, machine_mode mode
, unsigned int prec
)
1639 scalar_int_mode int_mode
;
1640 if (CONST_INT_P (src
)
1641 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
1642 && GET_MODE_PRECISION (int_mode
) < prec
1644 && val_signbit_known_set_p (int_mode
, INTVAL (src
)))
1645 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (int_mode
));
1650 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1654 update_rsp_from_reg_equal (reg_stat_type
*rsp
, rtx_insn
*insn
, const_rtx set
,
1657 rtx reg_equal_note
= insn
? find_reg_equal_equiv_note (insn
) : NULL_RTX
;
1658 unsigned HOST_WIDE_INT bits
= 0;
1659 rtx reg_equal
= NULL
, src
= SET_SRC (set
);
1660 unsigned int num
= 0;
1663 reg_equal
= XEXP (reg_equal_note
, 0);
1665 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
1667 src
= sign_extend_short_imm (src
, GET_MODE (x
), BITS_PER_WORD
);
1669 reg_equal
= sign_extend_short_imm (reg_equal
, GET_MODE (x
), BITS_PER_WORD
);
1672 /* Don't call nonzero_bits if it cannot change anything. */
1673 if (rsp
->nonzero_bits
!= HOST_WIDE_INT_M1U
)
1675 bits
= nonzero_bits (src
, nonzero_bits_mode
);
1676 if (reg_equal
&& bits
)
1677 bits
&= nonzero_bits (reg_equal
, nonzero_bits_mode
);
1678 rsp
->nonzero_bits
|= bits
;
1681 /* Don't call num_sign_bit_copies if it cannot change anything. */
1682 if (rsp
->sign_bit_copies
!= 1)
1684 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1685 if (reg_equal
&& num
!= GET_MODE_PRECISION (GET_MODE (x
)))
1687 unsigned int numeq
= num_sign_bit_copies (reg_equal
, GET_MODE (x
));
1688 if (num
== 0 || numeq
> num
)
1691 if (rsp
->sign_bit_copies
== 0 || num
< rsp
->sign_bit_copies
)
1692 rsp
->sign_bit_copies
= num
;
1696 /* Called via note_stores. If X is a pseudo that is narrower than
1697 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1699 If we are setting only a portion of X and we can't figure out what
1700 portion, assume all bits will be used since we don't know what will
1703 Similarly, set how many bits of X are known to be copies of the sign bit
1704 at all locations in the function. This is the smallest number implied
1708 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1710 rtx_insn
*insn
= (rtx_insn
*) data
;
1711 scalar_int_mode mode
;
1714 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1715 /* If this register is undefined at the start of the file, we can't
1716 say what its contents were. */
1717 && ! REGNO_REG_SET_P
1718 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1719 && is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
)
1720 && HWI_COMPUTABLE_MODE_P (mode
))
1722 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1724 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1726 rsp
->nonzero_bits
= GET_MODE_MASK (mode
);
1727 rsp
->sign_bit_copies
= 1;
1731 /* If this register is being initialized using itself, and the
1732 register is uninitialized in this basic block, and there are
1733 no LOG_LINKS which set the register, then part of the
1734 register is uninitialized. In that case we can't assume
1735 anything about the number of nonzero bits.
1737 ??? We could do better if we checked this in
1738 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1739 could avoid making assumptions about the insn which initially
1740 sets the register, while still using the information in other
1741 insns. We would have to be careful to check every insn
1742 involved in the combination. */
1745 && reg_referenced_p (x
, PATTERN (insn
))
1746 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1749 struct insn_link
*link
;
1751 FOR_EACH_LOG_LINK (link
, insn
)
1752 if (dead_or_set_p (link
->insn
, x
))
1756 rsp
->nonzero_bits
= GET_MODE_MASK (mode
);
1757 rsp
->sign_bit_copies
= 1;
1762 /* If this is a complex assignment, see if we can convert it into a
1763 simple assignment. */
1764 set
= expand_field_assignment (set
);
1766 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1767 set what we know about X. */
1769 if (SET_DEST (set
) == x
1770 || (paradoxical_subreg_p (SET_DEST (set
))
1771 && SUBREG_REG (SET_DEST (set
)) == x
))
1772 update_rsp_from_reg_equal (rsp
, insn
, set
, x
);
1775 rsp
->nonzero_bits
= GET_MODE_MASK (mode
);
1776 rsp
->sign_bit_copies
= 1;
1781 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1782 optionally insns that were previously combined into I3 or that will be
1783 combined into the merger of INSN and I3. The order is PRED, PRED2,
1784 INSN, SUCC, SUCC2, I3.
1786 Return 0 if the combination is not allowed for any reason.
1788 If the combination is allowed, *PDEST will be set to the single
1789 destination of INSN and *PSRC to the single source, and this function
1793 can_combine_p (rtx_insn
*insn
, rtx_insn
*i3
, rtx_insn
*pred ATTRIBUTE_UNUSED
,
1794 rtx_insn
*pred2 ATTRIBUTE_UNUSED
, rtx_insn
*succ
, rtx_insn
*succ2
,
1795 rtx
*pdest
, rtx
*psrc
)
1802 bool all_adjacent
= true;
1803 int (*is_volatile_p
) (const_rtx
);
1809 if (next_active_insn (succ2
) != i3
)
1810 all_adjacent
= false;
1811 if (next_active_insn (succ
) != succ2
)
1812 all_adjacent
= false;
1814 else if (next_active_insn (succ
) != i3
)
1815 all_adjacent
= false;
1816 if (next_active_insn (insn
) != succ
)
1817 all_adjacent
= false;
1819 else if (next_active_insn (insn
) != i3
)
1820 all_adjacent
= false;
1822 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1823 or a PARALLEL consisting of such a SET and CLOBBERs.
1825 If INSN has CLOBBER parallel parts, ignore them for our processing.
1826 By definition, these happen during the execution of the insn. When it
1827 is merged with another insn, all bets are off. If they are, in fact,
1828 needed and aren't also supplied in I3, they may be added by
1829 recog_for_combine. Otherwise, it won't match.
1831 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1834 Get the source and destination of INSN. If more than one, can't
1837 if (GET_CODE (PATTERN (insn
)) == SET
)
1838 set
= PATTERN (insn
);
1839 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1840 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1842 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1844 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1846 switch (GET_CODE (elt
))
1848 /* This is important to combine floating point insns
1849 for the SH4 port. */
1851 /* Combining an isolated USE doesn't make sense.
1852 We depend here on combinable_i3pat to reject them. */
1853 /* The code below this loop only verifies that the inputs of
1854 the SET in INSN do not change. We call reg_set_between_p
1855 to verify that the REG in the USE does not change between
1857 If the USE in INSN was for a pseudo register, the matching
1858 insn pattern will likely match any register; combining this
1859 with any other USE would only be safe if we knew that the
1860 used registers have identical values, or if there was
1861 something to tell them apart, e.g. different modes. For
1862 now, we forgo such complicated tests and simply disallow
1863 combining of USES of pseudo registers with any other USE. */
1864 if (REG_P (XEXP (elt
, 0))
1865 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1867 rtx i3pat
= PATTERN (i3
);
1868 int i
= XVECLEN (i3pat
, 0) - 1;
1869 unsigned int regno
= REGNO (XEXP (elt
, 0));
1873 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1875 if (GET_CODE (i3elt
) == USE
1876 && REG_P (XEXP (i3elt
, 0))
1877 && (REGNO (XEXP (i3elt
, 0)) == regno
1878 ? reg_set_between_p (XEXP (elt
, 0),
1879 PREV_INSN (insn
), i3
)
1880 : regno
>= FIRST_PSEUDO_REGISTER
))
1887 /* We can ignore CLOBBERs. */
1892 /* Ignore SETs whose result isn't used but not those that
1893 have side-effects. */
1894 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1895 && insn_nothrow_p (insn
)
1896 && !side_effects_p (elt
))
1899 /* If we have already found a SET, this is a second one and
1900 so we cannot combine with this insn. */
1908 /* Anything else means we can't combine. */
1914 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1915 so don't do anything with it. */
1916 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1925 /* The simplification in expand_field_assignment may call back to
1926 get_last_value, so set safe guard here. */
1927 subst_low_luid
= DF_INSN_LUID (insn
);
1929 set
= expand_field_assignment (set
);
1930 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1932 /* Do not eliminate user-specified register if it is in an
1933 asm input because we may break the register asm usage defined
1934 in GCC manual if allow to do so.
1935 Be aware that this may cover more cases than we expect but this
1936 should be harmless. */
1937 if (REG_P (dest
) && REG_USERVAR_P (dest
) && HARD_REGISTER_P (dest
)
1938 && extract_asm_operands (PATTERN (i3
)))
1941 /* Don't eliminate a store in the stack pointer. */
1942 if (dest
== stack_pointer_rtx
1943 /* Don't combine with an insn that sets a register to itself if it has
1944 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1945 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1946 /* Can't merge an ASM_OPERANDS. */
1947 || GET_CODE (src
) == ASM_OPERANDS
1948 /* Can't merge a function call. */
1949 || GET_CODE (src
) == CALL
1950 /* Don't eliminate a function call argument. */
1952 && (find_reg_fusage (i3
, USE
, dest
)
1954 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1955 && global_regs
[REGNO (dest
)])))
1956 /* Don't substitute into an incremented register. */
1957 || FIND_REG_INC_NOTE (i3
, dest
)
1958 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1959 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1960 /* Don't substitute into a non-local goto, this confuses CFG. */
1961 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1962 /* Make sure that DEST is not used after INSN but before SUCC, or
1963 after SUCC and before SUCC2, or after SUCC2 but before I3. */
1966 && (reg_used_between_p (dest
, succ2
, i3
)
1967 || reg_used_between_p (dest
, succ
, succ2
)))
1968 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))
1970 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1971 that case SUCC is not in the insn stream, so use SUCC2
1972 instead for this test. */
1973 && reg_used_between_p (dest
, insn
,
1975 && INSN_UID (succ
) == INSN_UID (succ2
)
1977 /* Make sure that the value that is to be substituted for the register
1978 does not use any registers whose values alter in between. However,
1979 If the insns are adjacent, a use can't cross a set even though we
1980 think it might (this can happen for a sequence of insns each setting
1981 the same destination; last_set of that register might point to
1982 a NOTE). If INSN has a REG_EQUIV note, the register is always
1983 equivalent to the memory so the substitution is valid even if there
1984 are intervening stores. Also, don't move a volatile asm or
1985 UNSPEC_VOLATILE across any other insns. */
1988 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1989 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1990 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1991 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1992 /* Don't combine across a CALL_INSN, because that would possibly
1993 change whether the life span of some REGs crosses calls or not,
1994 and it is a pain to update that information.
1995 Exception: if source is a constant, moving it later can't hurt.
1996 Accept that as a special case. */
1997 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
2000 /* DEST must either be a REG or CC0. */
2003 /* If register alignment is being enforced for multi-word items in all
2004 cases except for parameters, it is possible to have a register copy
2005 insn referencing a hard register that is not allowed to contain the
2006 mode being copied and which would not be valid as an operand of most
2007 insns. Eliminate this problem by not combining with such an insn.
2009 Also, on some machines we don't want to extend the life of a hard
2013 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
2014 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
2015 /* Don't extend the life of a hard register unless it is
2016 user variable (if we have few registers) or it can't
2017 fit into the desired register (meaning something special
2019 Also avoid substituting a return register into I3, because
2020 reload can't handle a conflict with constraints of other
2022 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
2023 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
2026 else if (GET_CODE (dest
) != CC0
)
2030 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
2031 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
2032 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
2034 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
2036 /* If the clobber represents an earlyclobber operand, we must not
2037 substitute an expression containing the clobbered register.
2038 As we do not analyze the constraint strings here, we have to
2039 make the conservative assumption. However, if the register is
2040 a fixed hard reg, the clobber cannot represent any operand;
2041 we leave it up to the machine description to either accept or
2042 reject use-and-clobber patterns. */
2044 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
2045 || !fixed_regs
[REGNO (reg
)])
2046 if (reg_overlap_mentioned_p (reg
, src
))
2050 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2051 or not), reject, unless nothing volatile comes between it and I3 */
2053 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
2055 /* Make sure neither succ nor succ2 contains a volatile reference. */
2056 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
2058 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
2060 /* We'll check insns between INSN and I3 below. */
2063 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2064 to be an explicit register variable, and was chosen for a reason. */
2066 if (GET_CODE (src
) == ASM_OPERANDS
2067 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
2070 /* If INSN contains volatile references (specifically volatile MEMs),
2071 we cannot combine across any other volatile references.
2072 Even if INSN doesn't contain volatile references, any intervening
2073 volatile insn might affect machine state. */
2075 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
2079 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
2080 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
2083 /* If INSN contains an autoincrement or autodecrement, make sure that
2084 register is not used between there and I3, and not already used in
2085 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2086 Also insist that I3 not be a jump; if it were one
2087 and the incremented register were spilled, we would lose. */
2090 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2091 if (REG_NOTE_KIND (link
) == REG_INC
2093 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
2094 || (pred
!= NULL_RTX
2095 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
2096 || (pred2
!= NULL_RTX
2097 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
2098 || (succ
!= NULL_RTX
2099 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
2100 || (succ2
!= NULL_RTX
2101 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
2102 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
2105 /* Don't combine an insn that follows a CC0-setting insn.
2106 An insn that uses CC0 must not be separated from the one that sets it.
2107 We do, however, allow I2 to follow a CC0-setting insn if that insn
2108 is passed as I1; in that case it will be deleted also.
2109 We also allow combining in this case if all the insns are adjacent
2110 because that would leave the two CC0 insns adjacent as well.
2111 It would be more logical to test whether CC0 occurs inside I1 or I2,
2112 but that would be much slower, and this ought to be equivalent. */
2116 p
= prev_nonnote_insn (insn
);
2117 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2122 /* If we get here, we have passed all the tests and the combination is
2131 /* LOC is the location within I3 that contains its pattern or the component
2132 of a PARALLEL of the pattern. We validate that it is valid for combining.
2134 One problem is if I3 modifies its output, as opposed to replacing it
2135 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2136 doing so would produce an insn that is not equivalent to the original insns.
2140 (set (reg:DI 101) (reg:DI 100))
2141 (set (subreg:SI (reg:DI 101) 0) <foo>)
2143 This is NOT equivalent to:
2145 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2146 (set (reg:DI 101) (reg:DI 100))])
2148 Not only does this modify 100 (in which case it might still be valid
2149 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2151 We can also run into a problem if I2 sets a register that I1
2152 uses and I1 gets directly substituted into I3 (not via I2). In that
2153 case, we would be getting the wrong value of I2DEST into I3, so we
2154 must reject the combination. This case occurs when I2 and I1 both
2155 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2156 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2157 of a SET must prevent combination from occurring. The same situation
2158 can occur for I0, in which case I0_NOT_IN_SRC is set.
2160 Before doing the above check, we first try to expand a field assignment
2161 into a set of logical operations.
2163 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2164 we place a register that is both set and used within I3. If more than one
2165 such register is detected, we fail.
2167 Return 1 if the combination is valid, zero otherwise. */
2170 combinable_i3pat (rtx_insn
*i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2171 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2175 if (GET_CODE (x
) == SET
)
2178 rtx dest
= SET_DEST (set
);
2179 rtx src
= SET_SRC (set
);
2180 rtx inner_dest
= dest
;
2183 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2184 || GET_CODE (inner_dest
) == SUBREG
2185 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2186 inner_dest
= XEXP (inner_dest
, 0);
2188 /* Check for the case where I3 modifies its output, as discussed
2189 above. We don't want to prevent pseudos from being combined
2190 into the address of a MEM, so only prevent the combination if
2191 i1 or i2 set the same MEM. */
2192 if ((inner_dest
!= dest
&&
2193 (!MEM_P (inner_dest
)
2194 || rtx_equal_p (i2dest
, inner_dest
)
2195 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2196 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2197 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2198 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2199 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2201 /* This is the same test done in can_combine_p except we can't test
2202 all_adjacent; we don't have to, since this instruction will stay
2203 in place, thus we are not considering increasing the lifetime of
2206 Also, if this insn sets a function argument, combining it with
2207 something that might need a spill could clobber a previous
2208 function argument; the all_adjacent test in can_combine_p also
2209 checks this; here, we do a more specific test for this case. */
2211 || (REG_P (inner_dest
)
2212 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2213 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2214 GET_MODE (inner_dest
))))
2215 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2216 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2219 /* If DEST is used in I3, it is being killed in this insn, so
2220 record that for later. We have to consider paradoxical
2221 subregs here, since they kill the whole register, but we
2222 ignore partial subregs, STRICT_LOW_PART, etc.
2223 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2224 STACK_POINTER_REGNUM, since these are always considered to be
2225 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2227 if (GET_CODE (subdest
) == SUBREG
2228 && (GET_MODE_SIZE (GET_MODE (subdest
))
2229 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2230 subdest
= SUBREG_REG (subdest
);
2233 && reg_referenced_p (subdest
, PATTERN (i3
))
2234 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2235 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2236 || REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
)
2237 && (FRAME_POINTER_REGNUM
== ARG_POINTER_REGNUM
2238 || (REGNO (subdest
) != ARG_POINTER_REGNUM
2239 || ! fixed_regs
[REGNO (subdest
)]))
2240 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2242 if (*pi3dest_killed
)
2245 *pi3dest_killed
= subdest
;
2249 else if (GET_CODE (x
) == PARALLEL
)
2253 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2254 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2255 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2262 /* Return 1 if X is an arithmetic expression that contains a multiplication
2263 and division. We don't count multiplications by powers of two here. */
2266 contains_muldiv (rtx x
)
2268 switch (GET_CODE (x
))
2270 case MOD
: case DIV
: case UMOD
: case UDIV
:
2274 return ! (CONST_INT_P (XEXP (x
, 1))
2275 && pow2p_hwi (UINTVAL (XEXP (x
, 1))));
2278 return contains_muldiv (XEXP (x
, 0))
2279 || contains_muldiv (XEXP (x
, 1));
2282 return contains_muldiv (XEXP (x
, 0));
2288 /* Determine whether INSN can be used in a combination. Return nonzero if
2289 not. This is used in try_combine to detect early some cases where we
2290 can't perform combinations. */
2293 cant_combine_insn_p (rtx_insn
*insn
)
2298 /* If this isn't really an insn, we can't do anything.
2299 This can occur when flow deletes an insn that it has merged into an
2300 auto-increment address. */
2301 if (!NONDEBUG_INSN_P (insn
))
2304 /* Never combine loads and stores involving hard regs that are likely
2305 to be spilled. The register allocator can usually handle such
2306 reg-reg moves by tying. If we allow the combiner to make
2307 substitutions of likely-spilled regs, reload might die.
2308 As an exception, we allow combinations involving fixed regs; these are
2309 not available to the register allocator so there's no risk involved. */
2311 set
= single_set (insn
);
2314 src
= SET_SRC (set
);
2315 dest
= SET_DEST (set
);
2316 if (GET_CODE (src
) == SUBREG
)
2317 src
= SUBREG_REG (src
);
2318 if (GET_CODE (dest
) == SUBREG
)
2319 dest
= SUBREG_REG (dest
);
2320 if (REG_P (src
) && REG_P (dest
)
2321 && ((HARD_REGISTER_P (src
)
2322 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2323 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2324 || (HARD_REGISTER_P (dest
)
2325 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2326 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2332 struct likely_spilled_retval_info
2334 unsigned regno
, nregs
;
2338 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2339 hard registers that are known to be written to / clobbered in full. */
2341 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2343 struct likely_spilled_retval_info
*const info
=
2344 (struct likely_spilled_retval_info
*) data
;
2345 unsigned regno
, nregs
;
2348 if (!REG_P (XEXP (set
, 0)))
2351 if (regno
>= info
->regno
+ info
->nregs
)
2353 nregs
= REG_NREGS (x
);
2354 if (regno
+ nregs
<= info
->regno
)
2356 new_mask
= (2U << (nregs
- 1)) - 1;
2357 if (regno
< info
->regno
)
2358 new_mask
>>= info
->regno
- regno
;
2360 new_mask
<<= regno
- info
->regno
;
2361 info
->mask
&= ~new_mask
;
2364 /* Return nonzero iff part of the return value is live during INSN, and
2365 it is likely spilled. This can happen when more than one insn is needed
2366 to copy the return value, e.g. when we consider to combine into the
2367 second copy insn for a complex value. */
2370 likely_spilled_retval_p (rtx_insn
*insn
)
2372 rtx_insn
*use
= BB_END (this_basic_block
);
2375 unsigned regno
, nregs
;
2376 /* We assume here that no machine mode needs more than
2377 32 hard registers when the value overlaps with a register
2378 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2380 struct likely_spilled_retval_info info
;
2382 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2384 reg
= XEXP (PATTERN (use
), 0);
2385 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2387 regno
= REGNO (reg
);
2388 nregs
= REG_NREGS (reg
);
2391 mask
= (2U << (nregs
- 1)) - 1;
2393 /* Disregard parts of the return value that are set later. */
2397 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2399 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2402 /* Check if any of the (probably) live return value registers is
2407 if ((mask
& 1 << nregs
)
2408 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2414 /* Adjust INSN after we made a change to its destination.
2416 Changing the destination can invalidate notes that say something about
2417 the results of the insn and a LOG_LINK pointing to the insn. */
2420 adjust_for_new_dest (rtx_insn
*insn
)
2422 /* For notes, be conservative and simply remove them. */
2423 remove_reg_equal_equiv_notes (insn
);
2425 /* The new insn will have a destination that was previously the destination
2426 of an insn just above it. Call distribute_links to make a LOG_LINK from
2427 the next use of that destination. */
2429 rtx set
= single_set (insn
);
2432 rtx reg
= SET_DEST (set
);
2434 while (GET_CODE (reg
) == ZERO_EXTRACT
2435 || GET_CODE (reg
) == STRICT_LOW_PART
2436 || GET_CODE (reg
) == SUBREG
)
2437 reg
= XEXP (reg
, 0);
2438 gcc_assert (REG_P (reg
));
2440 distribute_links (alloc_insn_link (insn
, REGNO (reg
), NULL
));
2442 df_insn_rescan (insn
);
2445 /* Return TRUE if combine can reuse reg X in mode MODE.
2446 ADDED_SETS is nonzero if the original set is still required. */
2448 can_change_dest_mode (rtx x
, int added_sets
, machine_mode mode
)
2456 /* Allow hard registers if the new mode is legal, and occupies no more
2457 registers than the old mode. */
2458 if (regno
< FIRST_PSEUDO_REGISTER
)
2459 return (HARD_REGNO_MODE_OK (regno
, mode
)
2460 && REG_NREGS (x
) >= hard_regno_nregs
[regno
][mode
]);
2462 /* Or a pseudo that is only used once. */
2463 return (regno
< reg_n_sets_max
2464 && REG_N_SETS (regno
) == 1
2466 && !REG_USERVAR_P (x
));
2470 /* Check whether X, the destination of a set, refers to part of
2471 the register specified by REG. */
2474 reg_subword_p (rtx x
, rtx reg
)
2476 /* Check that reg is an integer mode register. */
2477 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2480 if (GET_CODE (x
) == STRICT_LOW_PART
2481 || GET_CODE (x
) == ZERO_EXTRACT
)
2484 return GET_CODE (x
) == SUBREG
2485 && SUBREG_REG (x
) == reg
2486 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2489 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2490 Note that the INSN should be deleted *after* removing dead edges, so
2491 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2492 but not for a (set (pc) (label_ref FOO)). */
2495 update_cfg_for_uncondjump (rtx_insn
*insn
)
2497 basic_block bb
= BLOCK_FOR_INSN (insn
);
2498 gcc_assert (BB_END (bb
) == insn
);
2500 purge_dead_edges (bb
);
2503 if (EDGE_COUNT (bb
->succs
) == 1)
2507 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2509 /* Remove barriers from the footer if there are any. */
2510 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2511 if (BARRIER_P (insn
))
2513 if (PREV_INSN (insn
))
2514 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2516 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2517 if (NEXT_INSN (insn
))
2518 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2520 else if (LABEL_P (insn
))
2525 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2526 by an arbitrary number of CLOBBERs. */
2528 is_parallel_of_n_reg_sets (rtx pat
, int n
)
2530 if (GET_CODE (pat
) != PARALLEL
)
2533 int len
= XVECLEN (pat
, 0);
2538 for (i
= 0; i
< n
; i
++)
2539 if (GET_CODE (XVECEXP (pat
, 0, i
)) != SET
2540 || !REG_P (SET_DEST (XVECEXP (pat
, 0, i
))))
2542 for ( ; i
< len
; i
++)
2543 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
2544 || XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
2550 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2551 CLOBBERs), can be split into individual SETs in that order, without
2552 changing semantics. */
2554 can_split_parallel_of_n_reg_sets (rtx_insn
*insn
, int n
)
2556 if (!insn_nothrow_p (insn
))
2559 rtx pat
= PATTERN (insn
);
2562 for (i
= 0; i
< n
; i
++)
2564 if (side_effects_p (SET_SRC (XVECEXP (pat
, 0, i
))))
2567 rtx reg
= SET_DEST (XVECEXP (pat
, 0, i
));
2569 for (j
= i
+ 1; j
< n
; j
++)
2570 if (reg_referenced_p (reg
, XVECEXP (pat
, 0, j
)))
2577 /* Try to combine the insns I0, I1 and I2 into I3.
2578 Here I0, I1 and I2 appear earlier than I3.
2579 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2582 If we are combining more than two insns and the resulting insn is not
2583 recognized, try splitting it into two insns. If that happens, I2 and I3
2584 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2585 Otherwise, I0, I1 and I2 are pseudo-deleted.
2587 Return 0 if the combination does not work. Then nothing is changed.
2588 If we did the combination, return the insn at which combine should
2591 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2592 new direct jump instruction.
2594 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2595 been I3 passed to an earlier try_combine within the same basic
2599 try_combine (rtx_insn
*i3
, rtx_insn
*i2
, rtx_insn
*i1
, rtx_insn
*i0
,
2600 int *new_direct_jump_p
, rtx_insn
*last_combined_insn
)
2602 /* New patterns for I3 and I2, respectively. */
2603 rtx newpat
, newi2pat
= 0;
2604 rtvec newpat_vec_with_clobbers
= 0;
2605 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2606 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2608 int added_sets_0
, added_sets_1
, added_sets_2
;
2609 /* Total number of SETs to put into I3. */
2611 /* Nonzero if I2's or I1's body now appears in I3. */
2612 int i2_is_used
= 0, i1_is_used
= 0;
2613 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2614 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2615 /* Contains I3 if the destination of I3 is used in its source, which means
2616 that the old life of I3 is being killed. If that usage is placed into
2617 I2 and not in I3, a REG_DEAD note must be made. */
2618 rtx i3dest_killed
= 0;
2619 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2620 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2621 /* Copy of SET_SRC of I1 and I0, if needed. */
2622 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2623 /* Set if I2DEST was reused as a scratch register. */
2624 bool i2scratch
= false;
2625 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2626 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2627 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2628 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2629 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2630 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2631 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2632 /* Notes that must be added to REG_NOTES in I3 and I2. */
2633 rtx new_i3_notes
, new_i2_notes
;
2634 /* Notes that we substituted I3 into I2 instead of the normal case. */
2635 int i3_subst_into_i2
= 0;
2636 /* Notes that I1, I2 or I3 is a MULT operation. */
2639 int changed_i3_dest
= 0;
2642 rtx_insn
*temp_insn
;
2644 struct insn_link
*link
;
2646 rtx new_other_notes
;
2649 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2651 if (i1
== i2
|| i0
== i2
|| (i0
&& i0
== i1
))
2654 /* Only try four-insn combinations when there's high likelihood of
2655 success. Look for simple insns, such as loads of constants or
2656 binary operations involving a constant. */
2664 if (!flag_expensive_optimizations
)
2667 for (i
= 0; i
< 4; i
++)
2669 rtx_insn
*insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2670 rtx set
= single_set (insn
);
2674 src
= SET_SRC (set
);
2675 if (CONSTANT_P (src
))
2680 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2682 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2683 || GET_CODE (src
) == LSHIFTRT
)
2687 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2688 are likely manipulating its value. Ideally we'll be able to combine
2689 all four insns into a bitfield insertion of some kind.
2691 Note the source in I0 might be inside a sign/zero extension and the
2692 memory modes in I0 and I3 might be different. So extract the address
2693 from the destination of I3 and search for it in the source of I0.
2695 In the event that there's a match but the source/dest do not actually
2696 refer to the same memory, the worst that happens is we try some
2697 combinations that we wouldn't have otherwise. */
2698 if ((set0
= single_set (i0
))
2699 /* Ensure the source of SET0 is a MEM, possibly buried inside
2701 && (GET_CODE (SET_SRC (set0
)) == MEM
2702 || ((GET_CODE (SET_SRC (set0
)) == ZERO_EXTEND
2703 || GET_CODE (SET_SRC (set0
)) == SIGN_EXTEND
)
2704 && GET_CODE (XEXP (SET_SRC (set0
), 0)) == MEM
))
2705 && (set3
= single_set (i3
))
2706 /* Ensure the destination of SET3 is a MEM. */
2707 && GET_CODE (SET_DEST (set3
)) == MEM
2708 /* Would it be better to extract the base address for the MEM
2709 in SET3 and look for that? I don't have cases where it matters
2710 but I could envision such cases. */
2711 && rtx_referenced_p (XEXP (SET_DEST (set3
), 0), SET_SRC (set0
)))
2714 if (ngood
< 2 && nshift
< 2)
2718 /* Exit early if one of the insns involved can't be used for
2721 || (i1
&& CALL_P (i1
))
2722 || (i0
&& CALL_P (i0
))
2723 || cant_combine_insn_p (i3
)
2724 || cant_combine_insn_p (i2
)
2725 || (i1
&& cant_combine_insn_p (i1
))
2726 || (i0
&& cant_combine_insn_p (i0
))
2727 || likely_spilled_retval_p (i3
))
2731 undobuf
.other_insn
= 0;
2733 /* Reset the hard register usage information. */
2734 CLEAR_HARD_REG_SET (newpat_used_regs
);
2736 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2739 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2740 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2742 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2743 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2745 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2746 INSN_UID (i2
), INSN_UID (i3
));
2749 /* If multiple insns feed into one of I2 or I3, they can be in any
2750 order. To simplify the code below, reorder them in sequence. */
2751 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2753 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2755 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2758 added_links_insn
= 0;
2760 /* First check for one important special case that the code below will
2761 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2762 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2763 we may be able to replace that destination with the destination of I3.
2764 This occurs in the common code where we compute both a quotient and
2765 remainder into a structure, in which case we want to do the computation
2766 directly into the structure to avoid register-register copies.
2768 Note that this case handles both multiple sets in I2 and also cases
2769 where I2 has a number of CLOBBERs inside the PARALLEL.
2771 We make very conservative checks below and only try to handle the
2772 most common cases of this. For example, we only handle the case
2773 where I2 and I3 are adjacent to avoid making difficult register
2776 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2777 && REG_P (SET_SRC (PATTERN (i3
)))
2778 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2779 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2780 && GET_CODE (PATTERN (i2
)) == PARALLEL
2781 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2782 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2783 below would need to check what is inside (and reg_overlap_mentioned_p
2784 doesn't support those codes anyway). Don't allow those destinations;
2785 the resulting insn isn't likely to be recognized anyway. */
2786 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2787 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2788 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2789 SET_DEST (PATTERN (i3
)))
2790 && next_active_insn (i2
) == i3
)
2792 rtx p2
= PATTERN (i2
);
2794 /* Make sure that the destination of I3,
2795 which we are going to substitute into one output of I2,
2796 is not used within another output of I2. We must avoid making this:
2797 (parallel [(set (mem (reg 69)) ...)
2798 (set (reg 69) ...)])
2799 which is not well-defined as to order of actions.
2800 (Besides, reload can't handle output reloads for this.)
2802 The problem can also happen if the dest of I3 is a memory ref,
2803 if another dest in I2 is an indirect memory ref.
2805 Neither can this PARALLEL be an asm. We do not allow combining
2806 that usually (see can_combine_p), so do not here either. */
2808 for (i
= 0; ok
&& i
< XVECLEN (p2
, 0); i
++)
2810 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2811 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2812 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2813 SET_DEST (XVECEXP (p2
, 0, i
))))
2815 else if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2816 && GET_CODE (SET_SRC (XVECEXP (p2
, 0, i
))) == ASM_OPERANDS
)
2821 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2822 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2823 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2828 subst_low_luid
= DF_INSN_LUID (i2
);
2830 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2831 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2832 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2833 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2835 /* Replace the dest in I2 with our dest and make the resulting
2836 insn the new pattern for I3. Then skip to where we validate
2837 the pattern. Everything was set up above. */
2838 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2840 i3_subst_into_i2
= 1;
2841 goto validate_replacement
;
2845 /* If I2 is setting a pseudo to a constant and I3 is setting some
2846 sub-part of it to another constant, merge them by making a new
2849 && (temp_expr
= single_set (i2
)) != 0
2850 && CONST_SCALAR_INT_P (SET_SRC (temp_expr
))
2851 && GET_CODE (PATTERN (i3
)) == SET
2852 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2853 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp_expr
)))
2855 rtx dest
= SET_DEST (PATTERN (i3
));
2859 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2861 if (CONST_INT_P (XEXP (dest
, 1))
2862 && CONST_INT_P (XEXP (dest
, 2)))
2864 width
= INTVAL (XEXP (dest
, 1));
2865 offset
= INTVAL (XEXP (dest
, 2));
2866 dest
= XEXP (dest
, 0);
2867 if (BITS_BIG_ENDIAN
)
2868 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2873 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2874 dest
= XEXP (dest
, 0);
2875 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2881 /* If this is the low part, we're done. */
2882 if (subreg_lowpart_p (dest
))
2884 /* Handle the case where inner is twice the size of outer. */
2885 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp_expr
)))
2886 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2887 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2888 /* Otherwise give up for now. */
2895 rtx inner
= SET_SRC (PATTERN (i3
));
2896 rtx outer
= SET_SRC (temp_expr
);
2899 = wi::insert (rtx_mode_t (outer
, GET_MODE (SET_DEST (temp_expr
))),
2900 rtx_mode_t (inner
, GET_MODE (dest
)),
2905 subst_low_luid
= DF_INSN_LUID (i2
);
2906 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2907 i2dest
= SET_DEST (temp_expr
);
2908 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2910 /* Replace the source in I2 with the new constant and make the
2911 resulting insn the new pattern for I3. Then skip to where we
2912 validate the pattern. Everything was set up above. */
2913 SUBST (SET_SRC (temp_expr
),
2914 immed_wide_int_const (o
, GET_MODE (SET_DEST (temp_expr
))));
2916 newpat
= PATTERN (i2
);
2918 /* The dest of I3 has been replaced with the dest of I2. */
2919 changed_i3_dest
= 1;
2920 goto validate_replacement
;
2924 /* If we have no I1 and I2 looks like:
2925 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2927 make up a dummy I1 that is
2930 (set (reg:CC X) (compare:CC Y (const_int 0)))
2932 (We can ignore any trailing CLOBBERs.)
2934 This undoes a previous combination and allows us to match a branch-and-
2937 if (!HAVE_cc0
&& i1
== 0
2938 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2939 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2941 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2942 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2943 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2944 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1)))
2945 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2946 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2948 /* We make I1 with the same INSN_UID as I2. This gives it
2949 the same DF_INSN_LUID for value tracking. Our fake I1 will
2950 never appear in the insn stream so giving it the same INSN_UID
2951 as I2 will not cause a problem. */
2953 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2954 XVECEXP (PATTERN (i2
), 0, 1), INSN_LOCATION (i2
),
2956 INSN_UID (i1
) = INSN_UID (i2
);
2958 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2959 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2960 SET_DEST (PATTERN (i1
)));
2961 unsigned int regno
= REGNO (SET_DEST (PATTERN (i1
)));
2962 SUBST_LINK (LOG_LINKS (i2
),
2963 alloc_insn_link (i1
, regno
, LOG_LINKS (i2
)));
2966 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2967 make those two SETs separate I1 and I2 insns, and make an I0 that is
2969 if (!HAVE_cc0
&& i0
== 0
2970 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2971 && can_split_parallel_of_n_reg_sets (i2
, 2)
2972 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2973 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2975 /* If there is no I1, there is no I0 either. */
2978 /* We make I1 with the same INSN_UID as I2. This gives it
2979 the same DF_INSN_LUID for value tracking. Our fake I1 will
2980 never appear in the insn stream so giving it the same INSN_UID
2981 as I2 will not cause a problem. */
2983 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2984 XVECEXP (PATTERN (i2
), 0, 0), INSN_LOCATION (i2
),
2986 INSN_UID (i1
) = INSN_UID (i2
);
2988 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 1));
2991 /* Verify that I2 and I1 are valid for combining. */
2992 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL
, NULL
, &i2dest
, &i2src
)
2993 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL
, i2
, NULL
,
2995 || (i0
&& ! can_combine_p (i0
, i3
, NULL
, NULL
, i1
, i2
,
3002 /* Record whether I2DEST is used in I2SRC and similarly for the other
3003 cases. Knowing this will help in register status updating below. */
3004 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
3005 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
3006 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
3007 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
3008 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
3009 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
3010 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
3011 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
3012 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
3014 /* For the earlier insns, determine which of the subsequent ones they
3016 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
3017 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
3018 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
3019 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
3020 && reg_overlap_mentioned_p (i0dest
, i2src
))));
3022 /* Ensure that I3's pattern can be the destination of combines. */
3023 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
3024 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
3025 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
3026 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
3033 /* See if any of the insns is a MULT operation. Unless one is, we will
3034 reject a combination that is, since it must be slower. Be conservative
3036 if (GET_CODE (i2src
) == MULT
3037 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
3038 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
3039 || (GET_CODE (PATTERN (i3
)) == SET
3040 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
3043 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3044 We used to do this EXCEPT in one case: I3 has a post-inc in an
3045 output operand. However, that exception can give rise to insns like
3047 which is a famous insn on the PDP-11 where the value of r3 used as the
3048 source was model-dependent. Avoid this sort of thing. */
3051 if (!(GET_CODE (PATTERN (i3
)) == SET
3052 && REG_P (SET_SRC (PATTERN (i3
)))
3053 && MEM_P (SET_DEST (PATTERN (i3
)))
3054 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
3055 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
3056 /* It's not the exception. */
3061 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
3062 if (REG_NOTE_KIND (link
) == REG_INC
3063 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
3065 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
3072 /* See if the SETs in I1 or I2 need to be kept around in the merged
3073 instruction: whenever the value set there is still needed past I3.
3074 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3076 For the SET in I1, we have two cases: if I1 and I2 independently feed
3077 into I3, the set in I1 needs to be kept around unless I1DEST dies
3078 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3079 in I1 needs to be kept around unless I1DEST dies or is set in either
3080 I2 or I3. The same considerations apply to I0. */
3082 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
3085 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
3086 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
3091 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
3092 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
3093 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3094 && dead_or_set_p (i2
, i0dest
)));
3098 /* We are about to copy insns for the case where they need to be kept
3099 around. Check that they can be copied in the merged instruction. */
3101 if (targetm
.cannot_copy_insn_p
3102 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
3103 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
3104 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
3110 /* If the set in I2 needs to be kept around, we must make a copy of
3111 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3112 PATTERN (I2), we are only substituting for the original I1DEST, not into
3113 an already-substituted copy. This also prevents making self-referential
3114 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3119 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
3120 i2pat
= gen_rtx_SET (i2dest
, copy_rtx (i2src
));
3122 i2pat
= copy_rtx (PATTERN (i2
));
3127 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
3128 i1pat
= gen_rtx_SET (i1dest
, copy_rtx (i1src
));
3130 i1pat
= copy_rtx (PATTERN (i1
));
3135 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
3136 i0pat
= gen_rtx_SET (i0dest
, copy_rtx (i0src
));
3138 i0pat
= copy_rtx (PATTERN (i0
));
3143 /* Substitute in the latest insn for the regs set by the earlier ones. */
3145 maxreg
= max_reg_num ();
3149 /* Many machines that don't use CC0 have insns that can both perform an
3150 arithmetic operation and set the condition code. These operations will
3151 be represented as a PARALLEL with the first element of the vector
3152 being a COMPARE of an arithmetic operation with the constant zero.
3153 The second element of the vector will set some pseudo to the result
3154 of the same arithmetic operation. If we simplify the COMPARE, we won't
3155 match such a pattern and so will generate an extra insn. Here we test
3156 for this case, where both the comparison and the operation result are
3157 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3158 I2SRC. Later we will make the PARALLEL that contains I2. */
3160 if (!HAVE_cc0
&& i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3161 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3162 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
3163 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3166 rtx
*cc_use_loc
= NULL
;
3167 rtx_insn
*cc_use_insn
= NULL
;
3168 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
3169 machine_mode compare_mode
, orig_compare_mode
;
3170 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
3171 scalar_int_mode mode
;
3173 newpat
= PATTERN (i3
);
3174 newpat_dest
= SET_DEST (newpat
);
3175 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
3177 if (undobuf
.other_insn
== 0
3178 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
3181 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
3182 if (is_a
<scalar_int_mode
> (GET_MODE (i2dest
), &mode
))
3183 compare_code
= simplify_compare_const (compare_code
, mode
,
3185 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
3188 /* Do the rest only if op1 is const0_rtx, which may be the
3189 result of simplification. */
3190 if (op1
== const0_rtx
)
3192 /* If a single use of the CC is found, prepare to modify it
3193 when SELECT_CC_MODE returns a new CC-class mode, or when
3194 the above simplify_compare_const() returned a new comparison
3195 operator. undobuf.other_insn is assigned the CC use insn
3196 when modifying it. */
3199 #ifdef SELECT_CC_MODE
3200 machine_mode new_mode
3201 = SELECT_CC_MODE (compare_code
, op0
, op1
);
3202 if (new_mode
!= orig_compare_mode
3203 && can_change_dest_mode (SET_DEST (newpat
),
3204 added_sets_2
, new_mode
))
3206 unsigned int regno
= REGNO (newpat_dest
);
3207 compare_mode
= new_mode
;
3208 if (regno
< FIRST_PSEUDO_REGISTER
)
3209 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3212 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3213 newpat_dest
= regno_reg_rtx
[regno
];
3217 /* Cases for modifying the CC-using comparison. */
3218 if (compare_code
!= orig_compare_code
3219 /* ??? Do we need to verify the zero rtx? */
3220 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
3222 /* Replace cc_use_loc with entire new RTX. */
3224 gen_rtx_fmt_ee (compare_code
, compare_mode
,
3225 newpat_dest
, const0_rtx
));
3226 undobuf
.other_insn
= cc_use_insn
;
3228 else if (compare_mode
!= orig_compare_mode
)
3230 /* Just replace the CC reg with a new mode. */
3231 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3232 undobuf
.other_insn
= cc_use_insn
;
3236 /* Now we modify the current newpat:
3237 First, SET_DEST(newpat) is updated if the CC mode has been
3238 altered. For targets without SELECT_CC_MODE, this should be
3240 if (compare_mode
!= orig_compare_mode
)
3241 SUBST (SET_DEST (newpat
), newpat_dest
);
3242 /* This is always done to propagate i2src into newpat. */
3243 SUBST (SET_SRC (newpat
),
3244 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3245 /* Create new version of i2pat if needed; the below PARALLEL
3246 creation needs this to work correctly. */
3247 if (! rtx_equal_p (i2src
, op0
))
3248 i2pat
= gen_rtx_SET (i2dest
, op0
);
3253 if (i2_is_used
== 0)
3255 /* It is possible that the source of I2 or I1 may be performing
3256 an unneeded operation, such as a ZERO_EXTEND of something
3257 that is known to have the high part zero. Handle that case
3258 by letting subst look at the inner insns.
3260 Another way to do this would be to have a function that tries
3261 to simplify a single insn instead of merging two or more
3262 insns. We don't do this because of the potential of infinite
3263 loops and because of the potential extra memory required.
3264 However, doing it the way we are is a bit of a kludge and
3265 doesn't catch all cases.
3267 But only do this if -fexpensive-optimizations since it slows
3268 things down and doesn't usually win.
3270 This is not done in the COMPARE case above because the
3271 unmodified I2PAT is used in the PARALLEL and so a pattern
3272 with a modified I2SRC would not match. */
3274 if (flag_expensive_optimizations
)
3276 /* Pass pc_rtx so no substitutions are done, just
3280 subst_low_luid
= DF_INSN_LUID (i1
);
3281 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3284 subst_low_luid
= DF_INSN_LUID (i2
);
3285 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3288 n_occurrences
= 0; /* `subst' counts here */
3289 subst_low_luid
= DF_INSN_LUID (i2
);
3291 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3292 copy of I2SRC each time we substitute it, in order to avoid creating
3293 self-referential RTL when we will be substituting I1SRC for I1DEST
3294 later. Likewise if I0 feeds into I2, either directly or indirectly
3295 through I1, and I0DEST is in I0SRC. */
3296 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3297 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3298 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3299 && i0dest_in_i0src
));
3302 /* Record whether I2's body now appears within I3's body. */
3303 i2_is_used
= n_occurrences
;
3306 /* If we already got a failure, don't try to do more. Otherwise, try to
3307 substitute I1 if we have it. */
3309 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3311 /* Check that an autoincrement side-effect on I1 has not been lost.
3312 This happens if I1DEST is mentioned in I2 and dies there, and
3313 has disappeared from the new pattern. */
3314 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3316 && dead_or_set_p (i2
, i1dest
)
3317 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3318 /* Before we can do this substitution, we must redo the test done
3319 above (see detailed comments there) that ensures I1DEST isn't
3320 mentioned in any SETs in NEWPAT that are field assignments. */
3321 || !combinable_i3pat (NULL
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3329 subst_low_luid
= DF_INSN_LUID (i1
);
3331 /* If the following substitution will modify I1SRC, make a copy of it
3332 for the case where it is substituted for I1DEST in I2PAT later. */
3333 if (added_sets_2
&& i1_feeds_i2_n
)
3334 i1src_copy
= copy_rtx (i1src
);
3336 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3337 copy of I1SRC each time we substitute it, in order to avoid creating
3338 self-referential RTL when we will be substituting I0SRC for I0DEST
3340 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3341 i0_feeds_i1_n
&& i0dest_in_i0src
);
3344 /* Record whether I1's body now appears within I3's body. */
3345 i1_is_used
= n_occurrences
;
3348 /* Likewise for I0 if we have it. */
3350 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3352 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3353 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3354 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3355 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3356 || !combinable_i3pat (NULL
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3363 /* If the following substitution will modify I0SRC, make a copy of it
3364 for the case where it is substituted for I0DEST in I1PAT later. */
3365 if (added_sets_1
&& i0_feeds_i1_n
)
3366 i0src_copy
= copy_rtx (i0src
);
3367 /* And a copy for I0DEST in I2PAT substitution. */
3368 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3369 || (i0_feeds_i2_n
)))
3370 i0src_copy2
= copy_rtx (i0src
);
3373 subst_low_luid
= DF_INSN_LUID (i0
);
3374 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3378 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3379 to count all the ways that I2SRC and I1SRC can be used. */
3380 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3381 && i2_is_used
+ added_sets_2
> 1)
3382 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3383 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3385 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3386 && (n_occurrences
+ added_sets_0
3387 + (added_sets_1
&& i0_feeds_i1_n
)
3388 + (added_sets_2
&& i0_feeds_i2_n
)
3390 /* Fail if we tried to make a new register. */
3391 || max_reg_num () != maxreg
3392 /* Fail if we couldn't do something and have a CLOBBER. */
3393 || GET_CODE (newpat
) == CLOBBER
3394 /* Fail if this new pattern is a MULT and we didn't have one before
3395 at the outer level. */
3396 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3403 /* If the actions of the earlier insns must be kept
3404 in addition to substituting them into the latest one,
3405 we must make a new PARALLEL for the latest insn
3406 to hold additional the SETs. */
3408 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3410 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3413 if (GET_CODE (newpat
) == PARALLEL
)
3415 rtvec old
= XVEC (newpat
, 0);
3416 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3417 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3418 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3419 sizeof (old
->elem
[0]) * old
->num_elem
);
3424 total_sets
= 1 + extra_sets
;
3425 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3426 XVECEXP (newpat
, 0, 0) = old
;
3430 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3436 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3438 XVECEXP (newpat
, 0, --total_sets
) = t
;
3444 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3445 i0_feeds_i1_n
&& i0dest_in_i0src
);
3446 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3447 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3449 XVECEXP (newpat
, 0, --total_sets
) = t
;
3453 validate_replacement
:
3455 /* Note which hard regs this insn has as inputs. */
3456 mark_used_regs_combine (newpat
);
3458 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3459 consider splitting this pattern, we might need these clobbers. */
3460 if (i1
&& GET_CODE (newpat
) == PARALLEL
3461 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3463 int len
= XVECLEN (newpat
, 0);
3465 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3466 for (i
= 0; i
< len
; i
++)
3467 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3470 /* We have recognized nothing yet. */
3471 insn_code_number
= -1;
3473 /* See if this is a PARALLEL of two SETs where one SET's destination is
3474 a register that is unused and this isn't marked as an instruction that
3475 might trap in an EH region. In that case, we just need the other SET.
3476 We prefer this over the PARALLEL.
3478 This can occur when simplifying a divmod insn. We *must* test for this
3479 case here because the code below that splits two independent SETs doesn't
3480 handle this case correctly when it updates the register status.
3482 It's pointless doing this if we originally had two sets, one from
3483 i3, and one from i2. Combining then splitting the parallel results
3484 in the original i2 again plus an invalid insn (which we delete).
3485 The net effect is only to move instructions around, which makes
3486 debug info less accurate. */
3488 if (!(added_sets_2
&& i1
== 0)
3489 && is_parallel_of_n_reg_sets (newpat
, 2)
3490 && asm_noperands (newpat
) < 0)
3492 rtx set0
= XVECEXP (newpat
, 0, 0);
3493 rtx set1
= XVECEXP (newpat
, 0, 1);
3494 rtx oldpat
= newpat
;
3496 if (((REG_P (SET_DEST (set1
))
3497 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3498 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3499 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3500 && insn_nothrow_p (i3
)
3501 && !side_effects_p (SET_SRC (set1
)))
3504 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3507 else if (((REG_P (SET_DEST (set0
))
3508 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3509 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3510 && find_reg_note (i3
, REG_UNUSED
,
3511 SUBREG_REG (SET_DEST (set0
)))))
3512 && insn_nothrow_p (i3
)
3513 && !side_effects_p (SET_SRC (set0
)))
3516 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3518 if (insn_code_number
>= 0)
3519 changed_i3_dest
= 1;
3522 if (insn_code_number
< 0)
3526 /* Is the result of combination a valid instruction? */
3527 if (insn_code_number
< 0)
3528 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3530 /* If we were combining three insns and the result is a simple SET
3531 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3532 insns. There are two ways to do this. It can be split using a
3533 machine-specific method (like when you have an addition of a large
3534 constant) or by combine in the function find_split_point. */
3536 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3537 && asm_noperands (newpat
) < 0)
3539 rtx parallel
, *split
;
3540 rtx_insn
*m_split_insn
;
3542 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3543 use I2DEST as a scratch register will help. In the latter case,
3544 convert I2DEST to the mode of the source of NEWPAT if we can. */
3546 m_split_insn
= combine_split_insns (newpat
, i3
);
3548 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3549 inputs of NEWPAT. */
3551 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3552 possible to try that as a scratch reg. This would require adding
3553 more code to make it work though. */
3555 if (m_split_insn
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3557 machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3559 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3560 (temporarily, until we are committed to this instruction
3561 combination) does not work: for example, any call to nonzero_bits
3562 on the register (from a splitter in the MD file, for example)
3563 will get the old information, which is invalid.
3565 Since nowadays we can create registers during combine just fine,
3566 we should just create a new one here, not reuse i2dest. */
3568 /* First try to split using the original register as a
3569 scratch register. */
3570 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3571 gen_rtvec (2, newpat
,
3572 gen_rtx_CLOBBER (VOIDmode
,
3574 m_split_insn
= combine_split_insns (parallel
, i3
);
3576 /* If that didn't work, try changing the mode of I2DEST if
3578 if (m_split_insn
== 0
3579 && new_mode
!= GET_MODE (i2dest
)
3580 && new_mode
!= VOIDmode
3581 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3583 machine_mode old_mode
= GET_MODE (i2dest
);
3586 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3587 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3590 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3591 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3594 parallel
= (gen_rtx_PARALLEL
3596 gen_rtvec (2, newpat
,
3597 gen_rtx_CLOBBER (VOIDmode
,
3599 m_split_insn
= combine_split_insns (parallel
, i3
);
3601 if (m_split_insn
== 0
3602 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3606 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3607 buf
= undobuf
.undos
;
3608 undobuf
.undos
= buf
->next
;
3609 buf
->next
= undobuf
.frees
;
3610 undobuf
.frees
= buf
;
3614 i2scratch
= m_split_insn
!= 0;
3617 /* If recog_for_combine has discarded clobbers, try to use them
3618 again for the split. */
3619 if (m_split_insn
== 0 && newpat_vec_with_clobbers
)
3621 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3622 m_split_insn
= combine_split_insns (parallel
, i3
);
3625 if (m_split_insn
&& NEXT_INSN (m_split_insn
) == NULL_RTX
)
3627 rtx m_split_pat
= PATTERN (m_split_insn
);
3628 insn_code_number
= recog_for_combine (&m_split_pat
, i3
, &new_i3_notes
);
3629 if (insn_code_number
>= 0)
3630 newpat
= m_split_pat
;
3632 else if (m_split_insn
&& NEXT_INSN (NEXT_INSN (m_split_insn
)) == NULL_RTX
3633 && (next_nonnote_nondebug_insn (i2
) == i3
3634 || ! use_crosses_set_p (PATTERN (m_split_insn
), DF_INSN_LUID (i2
))))
3637 rtx newi3pat
= PATTERN (NEXT_INSN (m_split_insn
));
3638 newi2pat
= PATTERN (m_split_insn
);
3640 i3set
= single_set (NEXT_INSN (m_split_insn
));
3641 i2set
= single_set (m_split_insn
);
3643 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3645 /* If I2 or I3 has multiple SETs, we won't know how to track
3646 register status, so don't use these insns. If I2's destination
3647 is used between I2 and I3, we also can't use these insns. */
3649 if (i2_code_number
>= 0 && i2set
&& i3set
3650 && (next_nonnote_nondebug_insn (i2
) == i3
3651 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3652 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3654 if (insn_code_number
>= 0)
3657 /* It is possible that both insns now set the destination of I3.
3658 If so, we must show an extra use of it. */
3660 if (insn_code_number
>= 0)
3662 rtx new_i3_dest
= SET_DEST (i3set
);
3663 rtx new_i2_dest
= SET_DEST (i2set
);
3665 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3666 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3667 || GET_CODE (new_i3_dest
) == SUBREG
)
3668 new_i3_dest
= XEXP (new_i3_dest
, 0);
3670 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3671 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3672 || GET_CODE (new_i2_dest
) == SUBREG
)
3673 new_i2_dest
= XEXP (new_i2_dest
, 0);
3675 if (REG_P (new_i3_dest
)
3676 && REG_P (new_i2_dest
)
3677 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
)
3678 && REGNO (new_i2_dest
) < reg_n_sets_max
)
3679 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3683 /* If we can split it and use I2DEST, go ahead and see if that
3684 helps things be recognized. Verify that none of the registers
3685 are set between I2 and I3. */
3686 if (insn_code_number
< 0
3687 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3688 && (!HAVE_cc0
|| REG_P (i2dest
))
3689 /* We need I2DEST in the proper mode. If it is a hard register
3690 or the only use of a pseudo, we can change its mode.
3691 Make sure we don't change a hard register to have a mode that
3692 isn't valid for it, or change the number of registers. */
3693 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3694 || GET_MODE (*split
) == VOIDmode
3695 || can_change_dest_mode (i2dest
, added_sets_2
,
3697 && (next_nonnote_nondebug_insn (i2
) == i3
3698 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3699 /* We can't overwrite I2DEST if its value is still used by
3701 && ! reg_referenced_p (i2dest
, newpat
))
3703 rtx newdest
= i2dest
;
3704 enum rtx_code split_code
= GET_CODE (*split
);
3705 machine_mode split_mode
= GET_MODE (*split
);
3706 bool subst_done
= false;
3707 newi2pat
= NULL_RTX
;
3711 /* *SPLIT may be part of I2SRC, so make sure we have the
3712 original expression around for later debug processing.
3713 We should not need I2SRC any more in other cases. */
3714 if (MAY_HAVE_DEBUG_INSNS
)
3715 i2src
= copy_rtx (i2src
);
3719 /* Get NEWDEST as a register in the proper mode. We have already
3720 validated that we can do this. */
3721 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3723 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3724 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3727 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3728 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3732 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3733 an ASHIFT. This can occur if it was inside a PLUS and hence
3734 appeared to be a memory address. This is a kludge. */
3735 if (split_code
== MULT
3736 && CONST_INT_P (XEXP (*split
, 1))
3737 && INTVAL (XEXP (*split
, 1)) > 0
3738 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3740 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3741 XEXP (*split
, 0), GEN_INT (i
)));
3742 /* Update split_code because we may not have a multiply
3744 split_code
= GET_CODE (*split
);
3747 /* Similarly for (plus (mult FOO (const_int pow2))). */
3748 if (split_code
== PLUS
3749 && GET_CODE (XEXP (*split
, 0)) == MULT
3750 && CONST_INT_P (XEXP (XEXP (*split
, 0), 1))
3751 && INTVAL (XEXP (XEXP (*split
, 0), 1)) > 0
3752 && (i
= exact_log2 (UINTVAL (XEXP (XEXP (*split
, 0), 1)))) >= 0)
3754 rtx nsplit
= XEXP (*split
, 0);
3755 SUBST (XEXP (*split
, 0), gen_rtx_ASHIFT (GET_MODE (nsplit
),
3756 XEXP (nsplit
, 0), GEN_INT (i
)));
3757 /* Update split_code because we may not have a multiply
3759 split_code
= GET_CODE (*split
);
3762 #ifdef INSN_SCHEDULING
3763 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3764 be written as a ZERO_EXTEND. */
3765 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3767 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3768 what it really is. */
3769 if (load_extend_op (GET_MODE (SUBREG_REG (*split
)))
3771 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3772 SUBREG_REG (*split
)));
3774 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3775 SUBREG_REG (*split
)));
3779 /* Attempt to split binary operators using arithmetic identities. */
3780 if (BINARY_P (SET_SRC (newpat
))
3781 && split_mode
== GET_MODE (SET_SRC (newpat
))
3782 && ! side_effects_p (SET_SRC (newpat
)))
3784 rtx setsrc
= SET_SRC (newpat
);
3785 machine_mode mode
= GET_MODE (setsrc
);
3786 enum rtx_code code
= GET_CODE (setsrc
);
3787 rtx src_op0
= XEXP (setsrc
, 0);
3788 rtx src_op1
= XEXP (setsrc
, 1);
3790 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3791 if (rtx_equal_p (src_op0
, src_op1
))
3793 newi2pat
= gen_rtx_SET (newdest
, src_op0
);
3794 SUBST (XEXP (setsrc
, 0), newdest
);
3795 SUBST (XEXP (setsrc
, 1), newdest
);
3798 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3799 else if ((code
== PLUS
|| code
== MULT
)
3800 && GET_CODE (src_op0
) == code
3801 && GET_CODE (XEXP (src_op0
, 0)) == code
3802 && (INTEGRAL_MODE_P (mode
)
3803 || (FLOAT_MODE_P (mode
)
3804 && flag_unsafe_math_optimizations
)))
3806 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3807 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3808 rtx r
= XEXP (src_op0
, 1);
3811 /* Split both "((X op Y) op X) op Y" and
3812 "((X op Y) op Y) op X" as "T op T" where T is
3814 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3815 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3817 newi2pat
= gen_rtx_SET (newdest
, XEXP (src_op0
, 0));
3818 SUBST (XEXP (setsrc
, 0), newdest
);
3819 SUBST (XEXP (setsrc
, 1), newdest
);
3822 /* Split "((X op X) op Y) op Y)" as "T op T" where
3824 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3826 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3827 newi2pat
= gen_rtx_SET (newdest
, tmp
);
3828 SUBST (XEXP (setsrc
, 0), newdest
);
3829 SUBST (XEXP (setsrc
, 1), newdest
);
3837 newi2pat
= gen_rtx_SET (newdest
, *split
);
3838 SUBST (*split
, newdest
);
3841 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3843 /* recog_for_combine might have added CLOBBERs to newi2pat.
3844 Make sure NEWPAT does not depend on the clobbered regs. */
3845 if (GET_CODE (newi2pat
) == PARALLEL
)
3846 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3847 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3849 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3850 if (reg_overlap_mentioned_p (reg
, newpat
))
3857 /* If the split point was a MULT and we didn't have one before,
3858 don't use one now. */
3859 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3860 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3864 /* Check for a case where we loaded from memory in a narrow mode and
3865 then sign extended it, but we need both registers. In that case,
3866 we have a PARALLEL with both loads from the same memory location.
3867 We can split this into a load from memory followed by a register-register
3868 copy. This saves at least one insn, more if register allocation can
3871 We cannot do this if the destination of the first assignment is a
3872 condition code register or cc0. We eliminate this case by making sure
3873 the SET_DEST and SET_SRC have the same mode.
3875 We cannot do this if the destination of the second assignment is
3876 a register that we have already assumed is zero-extended. Similarly
3877 for a SUBREG of such a register. */
3879 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3880 && GET_CODE (newpat
) == PARALLEL
3881 && XVECLEN (newpat
, 0) == 2
3882 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3883 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3884 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3885 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3886 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3887 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3888 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3889 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3891 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3892 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3893 && ! (temp_expr
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3895 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3896 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3897 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3898 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3899 != GET_MODE_MASK (word_mode
))))
3900 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3901 && (temp_expr
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3903 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3904 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3905 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3906 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3907 != GET_MODE_MASK (word_mode
)))))
3908 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3909 SET_SRC (XVECEXP (newpat
, 0, 1)))
3910 && ! find_reg_note (i3
, REG_UNUSED
,
3911 SET_DEST (XVECEXP (newpat
, 0, 0))))
3915 newi2pat
= XVECEXP (newpat
, 0, 0);
3916 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3917 newpat
= XVECEXP (newpat
, 0, 1);
3918 SUBST (SET_SRC (newpat
),
3919 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3920 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3922 if (i2_code_number
>= 0)
3923 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3925 if (insn_code_number
>= 0)
3929 /* Similarly, check for a case where we have a PARALLEL of two independent
3930 SETs but we started with three insns. In this case, we can do the sets
3931 as two separate insns. This case occurs when some SET allows two
3932 other insns to combine, but the destination of that SET is still live.
3934 Also do this if we started with two insns and (at least) one of the
3935 resulting sets is a noop; this noop will be deleted later. */
3937 else if (insn_code_number
< 0 && asm_noperands (newpat
) < 0
3938 && GET_CODE (newpat
) == PARALLEL
3939 && XVECLEN (newpat
, 0) == 2
3940 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3941 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3942 && (i1
|| set_noop_p (XVECEXP (newpat
, 0, 0))
3943 || set_noop_p (XVECEXP (newpat
, 0, 1)))
3944 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3945 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3946 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3947 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3948 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3949 XVECEXP (newpat
, 0, 0))
3950 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3951 XVECEXP (newpat
, 0, 1))
3952 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3953 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3955 rtx set0
= XVECEXP (newpat
, 0, 0);
3956 rtx set1
= XVECEXP (newpat
, 0, 1);
3958 /* Normally, it doesn't matter which of the two is done first,
3959 but the one that references cc0 can't be the second, and
3960 one which uses any regs/memory set in between i2 and i3 can't
3961 be first. The PARALLEL might also have been pre-existing in i3,
3962 so we need to make sure that we won't wrongly hoist a SET to i2
3963 that would conflict with a death note present in there. */
3964 if (!use_crosses_set_p (SET_SRC (set1
), DF_INSN_LUID (i2
))
3965 && !(REG_P (SET_DEST (set1
))
3966 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
3967 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
3968 && find_reg_note (i2
, REG_DEAD
,
3969 SUBREG_REG (SET_DEST (set1
))))
3970 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set0
))
3971 /* If I3 is a jump, ensure that set0 is a jump so that
3972 we do not create invalid RTL. */
3973 && (!JUMP_P (i3
) || SET_DEST (set0
) == pc_rtx
)
3979 else if (!use_crosses_set_p (SET_SRC (set0
), DF_INSN_LUID (i2
))
3980 && !(REG_P (SET_DEST (set0
))
3981 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
3982 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
3983 && find_reg_note (i2
, REG_DEAD
,
3984 SUBREG_REG (SET_DEST (set0
))))
3985 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set1
))
3986 /* If I3 is a jump, ensure that set1 is a jump so that
3987 we do not create invalid RTL. */
3988 && (!JUMP_P (i3
) || SET_DEST (set1
) == pc_rtx
)
4000 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
4002 if (i2_code_number
>= 0)
4004 /* recog_for_combine might have added CLOBBERs to newi2pat.
4005 Make sure NEWPAT does not depend on the clobbered regs. */
4006 if (GET_CODE (newi2pat
) == PARALLEL
)
4008 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
4009 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
4011 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
4012 if (reg_overlap_mentioned_p (reg
, newpat
))
4020 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
4024 /* If it still isn't recognized, fail and change things back the way they
4026 if ((insn_code_number
< 0
4027 /* Is the result a reasonable ASM_OPERANDS? */
4028 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
4034 /* If we had to change another insn, make sure it is valid also. */
4035 if (undobuf
.other_insn
)
4037 CLEAR_HARD_REG_SET (newpat_used_regs
);
4039 other_pat
= PATTERN (undobuf
.other_insn
);
4040 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
4043 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
4050 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4051 they are adjacent to each other or not. */
4054 rtx_insn
*p
= prev_nonnote_insn (i3
);
4055 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
4056 && sets_cc0_p (newi2pat
))
4063 /* Only allow this combination if insn_rtx_costs reports that the
4064 replacement instructions are cheaper than the originals. */
4065 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
4071 if (MAY_HAVE_DEBUG_INSNS
)
4075 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
4076 if (undo
->kind
== UNDO_MODE
)
4078 rtx reg
= *undo
->where
.r
;
4079 machine_mode new_mode
= GET_MODE (reg
);
4080 machine_mode old_mode
= undo
->old_contents
.m
;
4082 /* Temporarily revert mode back. */
4083 adjust_reg_mode (reg
, old_mode
);
4085 if (reg
== i2dest
&& i2scratch
)
4087 /* If we used i2dest as a scratch register with a
4088 different mode, substitute it for the original
4089 i2src while its original mode is temporarily
4090 restored, and then clear i2scratch so that we don't
4091 do it again later. */
4092 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
4095 /* Put back the new mode. */
4096 adjust_reg_mode (reg
, new_mode
);
4100 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
4101 rtx_insn
*first
, *last
;
4106 last
= last_combined_insn
;
4111 last
= undobuf
.other_insn
;
4113 if (DF_INSN_LUID (last
)
4114 < DF_INSN_LUID (last_combined_insn
))
4115 last
= last_combined_insn
;
4118 /* We're dealing with a reg that changed mode but not
4119 meaning, so we want to turn it into a subreg for
4120 the new mode. However, because of REG sharing and
4121 because its mode had already changed, we have to do
4122 it in two steps. First, replace any debug uses of
4123 reg, with its original mode temporarily restored,
4124 with this copy we have created; then, replace the
4125 copy with the SUBREG of the original shared reg,
4126 once again changed to the new mode. */
4127 propagate_for_debug (first
, last
, reg
, tempreg
,
4129 adjust_reg_mode (reg
, new_mode
);
4130 propagate_for_debug (first
, last
, tempreg
,
4131 lowpart_subreg (old_mode
, reg
, new_mode
),
4137 /* If we will be able to accept this, we have made a
4138 change to the destination of I3. This requires us to
4139 do a few adjustments. */
4141 if (changed_i3_dest
)
4143 PATTERN (i3
) = newpat
;
4144 adjust_for_new_dest (i3
);
4147 /* We now know that we can do this combination. Merge the insns and
4148 update the status of registers and LOG_LINKS. */
4150 if (undobuf
.other_insn
)
4154 PATTERN (undobuf
.other_insn
) = other_pat
;
4156 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4157 ensure that they are still valid. Then add any non-duplicate
4158 notes added by recog_for_combine. */
4159 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
4161 next
= XEXP (note
, 1);
4163 if ((REG_NOTE_KIND (note
) == REG_DEAD
4164 && !reg_referenced_p (XEXP (note
, 0),
4165 PATTERN (undobuf
.other_insn
)))
4166 ||(REG_NOTE_KIND (note
) == REG_UNUSED
4167 && !reg_set_p (XEXP (note
, 0),
4168 PATTERN (undobuf
.other_insn
)))
4169 /* Simply drop equal note since it may be no longer valid
4170 for other_insn. It may be possible to record that CC
4171 register is changed and only discard those notes, but
4172 in practice it's unnecessary complication and doesn't
4173 give any meaningful improvement.
4176 || REG_NOTE_KIND (note
) == REG_EQUAL
4177 || REG_NOTE_KIND (note
) == REG_EQUIV
)
4178 remove_note (undobuf
.other_insn
, note
);
4181 distribute_notes (new_other_notes
, undobuf
.other_insn
,
4182 undobuf
.other_insn
, NULL
, NULL_RTX
, NULL_RTX
,
4189 struct insn_link
*link
;
4192 /* I3 now uses what used to be its destination and which is now
4193 I2's destination. This requires us to do a few adjustments. */
4194 PATTERN (i3
) = newpat
;
4195 adjust_for_new_dest (i3
);
4197 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4200 However, some later insn might be using I2's dest and have
4201 a LOG_LINK pointing at I3. We must remove this link.
4202 The simplest way to remove the link is to point it at I1,
4203 which we know will be a NOTE. */
4205 /* newi2pat is usually a SET here; however, recog_for_combine might
4206 have added some clobbers. */
4207 if (GET_CODE (newi2pat
) == PARALLEL
)
4208 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
4210 ni2dest
= SET_DEST (newi2pat
);
4212 for (insn
= NEXT_INSN (i3
);
4213 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4214 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
4215 insn
= NEXT_INSN (insn
))
4217 if (NONDEBUG_INSN_P (insn
)
4218 && reg_referenced_p (ni2dest
, PATTERN (insn
)))
4220 FOR_EACH_LOG_LINK (link
, insn
)
4221 if (link
->insn
== i3
)
4230 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
4231 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4234 /* Compute which registers we expect to eliminate. newi2pat may be setting
4235 either i3dest or i2dest, so we must check it. */
4236 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4237 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4240 /* For i1, we need to compute both local elimination and global
4241 elimination information with respect to newi2pat because i1dest
4242 may be the same as i3dest, in which case newi2pat may be setting
4243 i1dest. Global information is used when distributing REG_DEAD
4244 note for i2 and i3, in which case it does matter if newi2pat sets
4247 Local information is used when distributing REG_DEAD note for i1,
4248 in which case it doesn't matter if newi2pat sets i1dest or not.
4249 See PR62151, if we have four insns combination:
4251 i1: r1 <- i1src (using r0)
4253 i2: r0 <- i2src (using r1)
4254 i3: r3 <- i3src (using r0)
4256 From i1's point of view, r0 is eliminated, no matter if it is set
4257 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4258 should be discarded.
4260 Note local information only affects cases in forms like "I1->I2->I3",
4261 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4262 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4264 rtx local_elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4267 rtx elim_i1
= (local_elim_i1
== 0
4268 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4270 /* Same case as i1. */
4271 rtx local_elim_i0
= (i0
== 0 || i0dest_in_i0src
|| !i0dest_killed
4273 rtx elim_i0
= (local_elim_i0
== 0
4274 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4277 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4279 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4280 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4282 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4284 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4286 /* Ensure that we do not have something that should not be shared but
4287 occurs multiple times in the new insns. Check this by first
4288 resetting all the `used' flags and then copying anything is shared. */
4290 reset_used_flags (i3notes
);
4291 reset_used_flags (i2notes
);
4292 reset_used_flags (i1notes
);
4293 reset_used_flags (i0notes
);
4294 reset_used_flags (newpat
);
4295 reset_used_flags (newi2pat
);
4296 if (undobuf
.other_insn
)
4297 reset_used_flags (PATTERN (undobuf
.other_insn
));
4299 i3notes
= copy_rtx_if_shared (i3notes
);
4300 i2notes
= copy_rtx_if_shared (i2notes
);
4301 i1notes
= copy_rtx_if_shared (i1notes
);
4302 i0notes
= copy_rtx_if_shared (i0notes
);
4303 newpat
= copy_rtx_if_shared (newpat
);
4304 newi2pat
= copy_rtx_if_shared (newi2pat
);
4305 if (undobuf
.other_insn
)
4306 reset_used_flags (PATTERN (undobuf
.other_insn
));
4308 INSN_CODE (i3
) = insn_code_number
;
4309 PATTERN (i3
) = newpat
;
4311 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4313 for (rtx link
= CALL_INSN_FUNCTION_USAGE (i3
); link
;
4314 link
= XEXP (link
, 1))
4318 /* I2SRC must still be meaningful at this point. Some
4319 splitting operations can invalidate I2SRC, but those
4320 operations do not apply to calls. */
4322 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4326 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4329 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4334 if (undobuf
.other_insn
)
4335 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4337 /* We had one special case above where I2 had more than one set and
4338 we replaced a destination of one of those sets with the destination
4339 of I3. In that case, we have to update LOG_LINKS of insns later
4340 in this basic block. Note that this (expensive) case is rare.
4342 Also, in this case, we must pretend that all REG_NOTEs for I2
4343 actually came from I3, so that REG_UNUSED notes from I2 will be
4344 properly handled. */
4346 if (i3_subst_into_i2
)
4348 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4349 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4350 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4351 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4352 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4353 && ! find_reg_note (i2
, REG_UNUSED
,
4354 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4355 for (temp_insn
= NEXT_INSN (i2
);
4357 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4358 || BB_HEAD (this_basic_block
) != temp_insn
);
4359 temp_insn
= NEXT_INSN (temp_insn
))
4360 if (temp_insn
!= i3
&& NONDEBUG_INSN_P (temp_insn
))
4361 FOR_EACH_LOG_LINK (link
, temp_insn
)
4362 if (link
->insn
== i2
)
4368 while (XEXP (link
, 1))
4369 link
= XEXP (link
, 1);
4370 XEXP (link
, 1) = i2notes
;
4377 LOG_LINKS (i3
) = NULL
;
4379 LOG_LINKS (i2
) = NULL
;
4384 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4385 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4387 INSN_CODE (i2
) = i2_code_number
;
4388 PATTERN (i2
) = newi2pat
;
4392 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4393 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4395 SET_INSN_DELETED (i2
);
4400 LOG_LINKS (i1
) = NULL
;
4402 if (MAY_HAVE_DEBUG_INSNS
)
4403 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4405 SET_INSN_DELETED (i1
);
4410 LOG_LINKS (i0
) = NULL
;
4412 if (MAY_HAVE_DEBUG_INSNS
)
4413 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4415 SET_INSN_DELETED (i0
);
4418 /* Get death notes for everything that is now used in either I3 or
4419 I2 and used to die in a previous insn. If we built two new
4420 patterns, move from I1 to I2 then I2 to I3 so that we get the
4421 proper movement on registers that I2 modifies. */
4424 from_luid
= DF_INSN_LUID (i0
);
4426 from_luid
= DF_INSN_LUID (i1
);
4428 from_luid
= DF_INSN_LUID (i2
);
4430 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4431 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4433 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4435 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL
,
4436 elim_i2
, elim_i1
, elim_i0
);
4438 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL
,
4439 elim_i2
, elim_i1
, elim_i0
);
4441 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL
,
4442 elim_i2
, local_elim_i1
, local_elim_i0
);
4444 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL
,
4445 elim_i2
, elim_i1
, local_elim_i0
);
4447 distribute_notes (midnotes
, NULL
, i3
, newi2pat
? i2
: NULL
,
4448 elim_i2
, elim_i1
, elim_i0
);
4450 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4451 know these are REG_UNUSED and want them to go to the desired insn,
4452 so we always pass it as i3. */
4454 if (newi2pat
&& new_i2_notes
)
4455 distribute_notes (new_i2_notes
, i2
, i2
, NULL
, NULL_RTX
, NULL_RTX
,
4459 distribute_notes (new_i3_notes
, i3
, i3
, NULL
, NULL_RTX
, NULL_RTX
,
4462 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4463 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4464 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4465 in that case, it might delete I2. Similarly for I2 and I1.
4466 Show an additional death due to the REG_DEAD note we make here. If
4467 we discard it in distribute_notes, we will decrement it again. */
4471 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4472 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4473 distribute_notes (new_note
, NULL
, i2
, NULL
, elim_i2
,
4476 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4477 elim_i2
, elim_i1
, elim_i0
);
4480 if (i2dest_in_i2src
)
4482 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4483 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4484 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4485 NULL_RTX
, NULL_RTX
);
4487 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4488 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4491 if (i1dest_in_i1src
)
4493 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4494 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4495 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4496 NULL_RTX
, NULL_RTX
);
4498 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4499 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4502 if (i0dest_in_i0src
)
4504 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4505 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4506 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4507 NULL_RTX
, NULL_RTX
);
4509 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4510 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4513 distribute_links (i3links
);
4514 distribute_links (i2links
);
4515 distribute_links (i1links
);
4516 distribute_links (i0links
);
4520 struct insn_link
*link
;
4521 rtx_insn
*i2_insn
= 0;
4522 rtx i2_val
= 0, set
;
4524 /* The insn that used to set this register doesn't exist, and
4525 this life of the register may not exist either. See if one of
4526 I3's links points to an insn that sets I2DEST. If it does,
4527 that is now the last known value for I2DEST. If we don't update
4528 this and I2 set the register to a value that depended on its old
4529 contents, we will get confused. If this insn is used, thing
4530 will be set correctly in combine_instructions. */
4531 FOR_EACH_LOG_LINK (link
, i3
)
4532 if ((set
= single_set (link
->insn
)) != 0
4533 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4534 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4536 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4538 /* If the reg formerly set in I2 died only once and that was in I3,
4539 zero its use count so it won't make `reload' do any work. */
4541 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4542 && ! i2dest_in_i2src
4543 && REGNO (i2dest
) < reg_n_sets_max
)
4544 INC_REG_N_SETS (REGNO (i2dest
), -1);
4547 if (i1
&& REG_P (i1dest
))
4549 struct insn_link
*link
;
4550 rtx_insn
*i1_insn
= 0;
4551 rtx i1_val
= 0, set
;
4553 FOR_EACH_LOG_LINK (link
, i3
)
4554 if ((set
= single_set (link
->insn
)) != 0
4555 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4556 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4558 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4561 && ! i1dest_in_i1src
4562 && REGNO (i1dest
) < reg_n_sets_max
)
4563 INC_REG_N_SETS (REGNO (i1dest
), -1);
4566 if (i0
&& REG_P (i0dest
))
4568 struct insn_link
*link
;
4569 rtx_insn
*i0_insn
= 0;
4570 rtx i0_val
= 0, set
;
4572 FOR_EACH_LOG_LINK (link
, i3
)
4573 if ((set
= single_set (link
->insn
)) != 0
4574 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4575 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4577 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4580 && ! i0dest_in_i0src
4581 && REGNO (i0dest
) < reg_n_sets_max
)
4582 INC_REG_N_SETS (REGNO (i0dest
), -1);
4585 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4586 been made to this insn. The order is important, because newi2pat
4587 can affect nonzero_bits of newpat. */
4589 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4590 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4593 if (undobuf
.other_insn
!= NULL_RTX
)
4597 fprintf (dump_file
, "modifying other_insn ");
4598 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4600 df_insn_rescan (undobuf
.other_insn
);
4603 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4607 fprintf (dump_file
, "modifying insn i0 ");
4608 dump_insn_slim (dump_file
, i0
);
4610 df_insn_rescan (i0
);
4613 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4617 fprintf (dump_file
, "modifying insn i1 ");
4618 dump_insn_slim (dump_file
, i1
);
4620 df_insn_rescan (i1
);
4623 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4627 fprintf (dump_file
, "modifying insn i2 ");
4628 dump_insn_slim (dump_file
, i2
);
4630 df_insn_rescan (i2
);
4633 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4637 fprintf (dump_file
, "modifying insn i3 ");
4638 dump_insn_slim (dump_file
, i3
);
4640 df_insn_rescan (i3
);
4643 /* Set new_direct_jump_p if a new return or simple jump instruction
4644 has been created. Adjust the CFG accordingly. */
4645 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4647 *new_direct_jump_p
= 1;
4648 mark_jump_label (PATTERN (i3
), i3
, 0);
4649 update_cfg_for_uncondjump (i3
);
4652 if (undobuf
.other_insn
!= NULL_RTX
4653 && (returnjump_p (undobuf
.other_insn
)
4654 || any_uncondjump_p (undobuf
.other_insn
)))
4656 *new_direct_jump_p
= 1;
4657 update_cfg_for_uncondjump (undobuf
.other_insn
);
4660 if (GET_CODE (PATTERN (i3
)) == TRAP_IF
4661 && XEXP (PATTERN (i3
), 0) == const1_rtx
)
4663 basic_block bb
= BLOCK_FOR_INSN (i3
);
4665 remove_edge (split_block (bb
, i3
));
4666 emit_barrier_after_bb (bb
);
4667 *new_direct_jump_p
= 1;
4670 if (undobuf
.other_insn
4671 && GET_CODE (PATTERN (undobuf
.other_insn
)) == TRAP_IF
4672 && XEXP (PATTERN (undobuf
.other_insn
), 0) == const1_rtx
)
4674 basic_block bb
= BLOCK_FOR_INSN (undobuf
.other_insn
);
4676 remove_edge (split_block (bb
, undobuf
.other_insn
));
4677 emit_barrier_after_bb (bb
);
4678 *new_direct_jump_p
= 1;
4681 /* A noop might also need cleaning up of CFG, if it comes from the
4682 simplification of a jump. */
4684 && GET_CODE (newpat
) == SET
4685 && SET_SRC (newpat
) == pc_rtx
4686 && SET_DEST (newpat
) == pc_rtx
)
4688 *new_direct_jump_p
= 1;
4689 update_cfg_for_uncondjump (i3
);
4692 if (undobuf
.other_insn
!= NULL_RTX
4693 && JUMP_P (undobuf
.other_insn
)
4694 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4695 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4696 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4698 *new_direct_jump_p
= 1;
4699 update_cfg_for_uncondjump (undobuf
.other_insn
);
4702 combine_successes
++;
4705 if (added_links_insn
4706 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4707 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4708 return added_links_insn
;
4710 return newi2pat
? i2
: i3
;
4713 /* Get a marker for undoing to the current state. */
4716 get_undo_marker (void)
4718 return undobuf
.undos
;
4721 /* Undo the modifications up to the marker. */
4724 undo_to_marker (void *marker
)
4726 struct undo
*undo
, *next
;
4728 for (undo
= undobuf
.undos
; undo
!= marker
; undo
= next
)
4736 *undo
->where
.r
= undo
->old_contents
.r
;
4739 *undo
->where
.i
= undo
->old_contents
.i
;
4742 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4745 *undo
->where
.l
= undo
->old_contents
.l
;
4751 undo
->next
= undobuf
.frees
;
4752 undobuf
.frees
= undo
;
4755 undobuf
.undos
= (struct undo
*) marker
;
4758 /* Undo all the modifications recorded in undobuf. */
4766 /* We've committed to accepting the changes we made. Move all
4767 of the undos to the free list. */
4772 struct undo
*undo
, *next
;
4774 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4777 undo
->next
= undobuf
.frees
;
4778 undobuf
.frees
= undo
;
4783 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4784 where we have an arithmetic expression and return that point. LOC will
4787 try_combine will call this function to see if an insn can be split into
4791 find_split_point (rtx
*loc
, rtx_insn
*insn
, bool set_src
)
4794 enum rtx_code code
= GET_CODE (x
);
4796 unsigned HOST_WIDE_INT len
= 0;
4797 HOST_WIDE_INT pos
= 0;
4799 rtx inner
= NULL_RTX
;
4800 scalar_int_mode mode
, inner_mode
;
4802 /* First special-case some codes. */
4806 #ifdef INSN_SCHEDULING
4807 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4809 if (MEM_P (SUBREG_REG (x
)))
4812 return find_split_point (&SUBREG_REG (x
), insn
, false);
4815 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4816 using LO_SUM and HIGH. */
4817 if (HAVE_lo_sum
&& (GET_CODE (XEXP (x
, 0)) == CONST
4818 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
))
4820 machine_mode address_mode
= get_address_mode (x
);
4823 gen_rtx_LO_SUM (address_mode
,
4824 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4826 return &XEXP (XEXP (x
, 0), 0);
4829 /* If we have a PLUS whose second operand is a constant and the
4830 address is not valid, perhaps will can split it up using
4831 the machine-specific way to split large constants. We use
4832 the first pseudo-reg (one of the virtual regs) as a placeholder;
4833 it will not remain in the result. */
4834 if (GET_CODE (XEXP (x
, 0)) == PLUS
4835 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4836 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4837 MEM_ADDR_SPACE (x
)))
4839 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4840 rtx_insn
*seq
= combine_split_insns (gen_rtx_SET (reg
, XEXP (x
, 0)),
4843 /* This should have produced two insns, each of which sets our
4844 placeholder. If the source of the second is a valid address,
4845 we can make put both sources together and make a split point
4849 && NEXT_INSN (seq
) != NULL_RTX
4850 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4851 && NONJUMP_INSN_P (seq
)
4852 && GET_CODE (PATTERN (seq
)) == SET
4853 && SET_DEST (PATTERN (seq
)) == reg
4854 && ! reg_mentioned_p (reg
,
4855 SET_SRC (PATTERN (seq
)))
4856 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4857 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4858 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4859 && memory_address_addr_space_p
4860 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4861 MEM_ADDR_SPACE (x
)))
4863 rtx src1
= SET_SRC (PATTERN (seq
));
4864 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4866 /* Replace the placeholder in SRC2 with SRC1. If we can
4867 find where in SRC2 it was placed, that can become our
4868 split point and we can replace this address with SRC2.
4869 Just try two obvious places. */
4871 src2
= replace_rtx (src2
, reg
, src1
);
4873 if (XEXP (src2
, 0) == src1
)
4874 split
= &XEXP (src2
, 0);
4875 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4876 && XEXP (XEXP (src2
, 0), 0) == src1
)
4877 split
= &XEXP (XEXP (src2
, 0), 0);
4881 SUBST (XEXP (x
, 0), src2
);
4886 /* If that didn't work, perhaps the first operand is complex and
4887 needs to be computed separately, so make a split point there.
4888 This will occur on machines that just support REG + CONST
4889 and have a constant moved through some previous computation. */
4891 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4892 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4893 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4894 return &XEXP (XEXP (x
, 0), 0);
4897 /* If we have a PLUS whose first operand is complex, try computing it
4898 separately by making a split there. */
4899 if (GET_CODE (XEXP (x
, 0)) == PLUS
4900 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4902 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4903 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4904 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4905 return &XEXP (XEXP (x
, 0), 0);
4909 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4910 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4911 we need to put the operand into a register. So split at that
4914 if (SET_DEST (x
) == cc0_rtx
4915 && GET_CODE (SET_SRC (x
)) != COMPARE
4916 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4917 && !OBJECT_P (SET_SRC (x
))
4918 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4919 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4920 return &SET_SRC (x
);
4922 /* See if we can split SET_SRC as it stands. */
4923 split
= find_split_point (&SET_SRC (x
), insn
, true);
4924 if (split
&& split
!= &SET_SRC (x
))
4927 /* See if we can split SET_DEST as it stands. */
4928 split
= find_split_point (&SET_DEST (x
), insn
, false);
4929 if (split
&& split
!= &SET_DEST (x
))
4932 /* See if this is a bitfield assignment with everything constant. If
4933 so, this is an IOR of an AND, so split it into that. */
4934 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4935 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (SET_DEST (x
), 0)),
4937 && HWI_COMPUTABLE_MODE_P (inner_mode
)
4938 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4939 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4940 && CONST_INT_P (SET_SRC (x
))
4941 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4942 + INTVAL (XEXP (SET_DEST (x
), 2)))
4943 <= GET_MODE_PRECISION (inner_mode
))
4944 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4946 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4947 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4948 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4949 rtx dest
= XEXP (SET_DEST (x
), 0);
4950 unsigned HOST_WIDE_INT mask
4951 = (HOST_WIDE_INT_1U
<< len
) - 1;
4954 if (BITS_BIG_ENDIAN
)
4955 pos
= GET_MODE_PRECISION (inner_mode
) - len
- pos
;
4957 or_mask
= gen_int_mode (src
<< pos
, inner_mode
);
4960 simplify_gen_binary (IOR
, inner_mode
, dest
, or_mask
));
4963 rtx negmask
= gen_int_mode (~(mask
<< pos
), inner_mode
);
4965 simplify_gen_binary (IOR
, inner_mode
,
4966 simplify_gen_binary (AND
, inner_mode
,
4971 SUBST (SET_DEST (x
), dest
);
4973 split
= find_split_point (&SET_SRC (x
), insn
, true);
4974 if (split
&& split
!= &SET_SRC (x
))
4978 /* Otherwise, see if this is an operation that we can split into two.
4979 If so, try to split that. */
4980 code
= GET_CODE (SET_SRC (x
));
4985 /* If we are AND'ing with a large constant that is only a single
4986 bit and the result is only being used in a context where we
4987 need to know if it is zero or nonzero, replace it with a bit
4988 extraction. This will avoid the large constant, which might
4989 have taken more than one insn to make. If the constant were
4990 not a valid argument to the AND but took only one insn to make,
4991 this is no worse, but if it took more than one insn, it will
4994 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4995 && REG_P (XEXP (SET_SRC (x
), 0))
4996 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4997 && REG_P (SET_DEST (x
))
4998 && (split
= find_single_use (SET_DEST (x
), insn
, NULL
)) != 0
4999 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
5000 && XEXP (*split
, 0) == SET_DEST (x
)
5001 && XEXP (*split
, 1) == const0_rtx
)
5003 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
5004 XEXP (SET_SRC (x
), 0),
5005 pos
, NULL_RTX
, 1, 1, 0, 0);
5006 if (extraction
!= 0)
5008 SUBST (SET_SRC (x
), extraction
);
5009 return find_split_point (loc
, insn
, false);
5015 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5016 is known to be on, this can be converted into a NEG of a shift. */
5017 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
5018 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
5019 && 1 <= (pos
= exact_log2
5020 (nonzero_bits (XEXP (SET_SRC (x
), 0),
5021 GET_MODE (XEXP (SET_SRC (x
), 0))))))
5023 machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
5027 gen_rtx_LSHIFTRT (mode
,
5028 XEXP (SET_SRC (x
), 0),
5031 split
= find_split_point (&SET_SRC (x
), insn
, true);
5032 if (split
&& split
!= &SET_SRC (x
))
5038 inner
= XEXP (SET_SRC (x
), 0);
5040 /* We can't optimize if either mode is a partial integer
5041 mode as we don't know how many bits are significant
5043 if (!is_int_mode (GET_MODE (inner
), &inner_mode
)
5044 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
5048 len
= GET_MODE_PRECISION (inner_mode
);
5054 if (is_a
<scalar_int_mode
> (GET_MODE (XEXP (SET_SRC (x
), 0)),
5056 && CONST_INT_P (XEXP (SET_SRC (x
), 1))
5057 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
5059 inner
= XEXP (SET_SRC (x
), 0);
5060 len
= INTVAL (XEXP (SET_SRC (x
), 1));
5061 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
5063 if (BITS_BIG_ENDIAN
)
5064 pos
= GET_MODE_PRECISION (inner_mode
) - len
- pos
;
5065 unsignedp
= (code
== ZERO_EXTRACT
);
5074 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
))
5075 && is_a
<scalar_int_mode
> (GET_MODE (SET_SRC (x
)), &mode
))
5077 /* For unsigned, we have a choice of a shift followed by an
5078 AND or two shifts. Use two shifts for field sizes where the
5079 constant might be too large. We assume here that we can
5080 always at least get 8-bit constants in an AND insn, which is
5081 true for every current RISC. */
5083 if (unsignedp
&& len
<= 8)
5085 unsigned HOST_WIDE_INT mask
5086 = (HOST_WIDE_INT_1U
<< len
) - 1;
5090 (mode
, gen_lowpart (mode
, inner
),
5092 gen_int_mode (mask
, mode
)));
5094 split
= find_split_point (&SET_SRC (x
), insn
, true);
5095 if (split
&& split
!= &SET_SRC (x
))
5102 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
5103 gen_rtx_ASHIFT (mode
,
5104 gen_lowpart (mode
, inner
),
5105 GEN_INT (GET_MODE_PRECISION (mode
)
5107 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
5109 split
= find_split_point (&SET_SRC (x
), insn
, true);
5110 if (split
&& split
!= &SET_SRC (x
))
5115 /* See if this is a simple operation with a constant as the second
5116 operand. It might be that this constant is out of range and hence
5117 could be used as a split point. */
5118 if (BINARY_P (SET_SRC (x
))
5119 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
5120 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
5121 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
5122 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
5123 return &XEXP (SET_SRC (x
), 1);
5125 /* Finally, see if this is a simple operation with its first operand
5126 not in a register. The operation might require this operand in a
5127 register, so return it as a split point. We can always do this
5128 because if the first operand were another operation, we would have
5129 already found it as a split point. */
5130 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
5131 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
5132 return &XEXP (SET_SRC (x
), 0);
5138 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5139 it is better to write this as (not (ior A B)) so we can split it.
5140 Similarly for IOR. */
5141 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
5144 gen_rtx_NOT (GET_MODE (x
),
5145 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
5147 XEXP (XEXP (x
, 0), 0),
5148 XEXP (XEXP (x
, 1), 0))));
5149 return find_split_point (loc
, insn
, set_src
);
5152 /* Many RISC machines have a large set of logical insns. If the
5153 second operand is a NOT, put it first so we will try to split the
5154 other operand first. */
5155 if (GET_CODE (XEXP (x
, 1)) == NOT
)
5157 rtx tem
= XEXP (x
, 0);
5158 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5159 SUBST (XEXP (x
, 1), tem
);
5165 /* Canonicalization can produce (minus A (mult B C)), where C is a
5166 constant. It may be better to try splitting (plus (mult B -C) A)
5167 instead if this isn't a multiply by a power of two. */
5168 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
5169 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
5170 && !pow2p_hwi (INTVAL (XEXP (XEXP (x
, 1), 1))))
5172 machine_mode mode
= GET_MODE (x
);
5173 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
5174 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
5175 SUBST (*loc
, gen_rtx_PLUS (mode
,
5177 XEXP (XEXP (x
, 1), 0),
5178 gen_int_mode (other_int
,
5181 return find_split_point (loc
, insn
, set_src
);
5184 /* Split at a multiply-accumulate instruction. However if this is
5185 the SET_SRC, we likely do not have such an instruction and it's
5186 worthless to try this split. */
5188 && (GET_CODE (XEXP (x
, 0)) == MULT
5189 || (GET_CODE (XEXP (x
, 0)) == ASHIFT
5190 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
5197 /* Otherwise, select our actions depending on our rtx class. */
5198 switch (GET_RTX_CLASS (code
))
5200 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5202 split
= find_split_point (&XEXP (x
, 2), insn
, false);
5207 case RTX_COMM_ARITH
:
5209 case RTX_COMM_COMPARE
:
5210 split
= find_split_point (&XEXP (x
, 1), insn
, false);
5215 /* Some machines have (and (shift ...) ...) insns. If X is not
5216 an AND, but XEXP (X, 0) is, use it as our split point. */
5217 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
5218 return &XEXP (x
, 0);
5220 split
= find_split_point (&XEXP (x
, 0), insn
, false);
5226 /* Otherwise, we don't have a split point. */
5231 /* Throughout X, replace FROM with TO, and return the result.
5232 The result is TO if X is FROM;
5233 otherwise the result is X, but its contents may have been modified.
5234 If they were modified, a record was made in undobuf so that
5235 undo_all will (among other things) return X to its original state.
5237 If the number of changes necessary is too much to record to undo,
5238 the excess changes are not made, so the result is invalid.
5239 The changes already made can still be undone.
5240 undobuf.num_undo is incremented for such changes, so by testing that
5241 the caller can tell whether the result is valid.
5243 `n_occurrences' is incremented each time FROM is replaced.
5245 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5247 IN_COND is nonzero if we are at the top level of a condition.
5249 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5250 by copying if `n_occurrences' is nonzero. */
5253 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
5255 enum rtx_code code
= GET_CODE (x
);
5256 machine_mode op0_mode
= VOIDmode
;
5261 /* Two expressions are equal if they are identical copies of a shared
5262 RTX or if they are both registers with the same register number
5265 #define COMBINE_RTX_EQUAL_P(X,Y) \
5267 || (REG_P (X) && REG_P (Y) \
5268 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5270 /* Do not substitute into clobbers of regs -- this will never result in
5272 if (GET_CODE (x
) == CLOBBER
&& REG_P (XEXP (x
, 0)))
5275 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
5278 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
5281 /* If X and FROM are the same register but different modes, they
5282 will not have been seen as equal above. However, the log links code
5283 will make a LOG_LINKS entry for that case. If we do nothing, we
5284 will try to rerecognize our original insn and, when it succeeds,
5285 we will delete the feeding insn, which is incorrect.
5287 So force this insn not to match in this (rare) case. */
5288 if (! in_dest
&& code
== REG
&& REG_P (from
)
5289 && reg_overlap_mentioned_p (x
, from
))
5290 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
5292 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5293 of which may contain things that can be combined. */
5294 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
5297 /* It is possible to have a subexpression appear twice in the insn.
5298 Suppose that FROM is a register that appears within TO.
5299 Then, after that subexpression has been scanned once by `subst',
5300 the second time it is scanned, TO may be found. If we were
5301 to scan TO here, we would find FROM within it and create a
5302 self-referent rtl structure which is completely wrong. */
5303 if (COMBINE_RTX_EQUAL_P (x
, to
))
5306 /* Parallel asm_operands need special attention because all of the
5307 inputs are shared across the arms. Furthermore, unsharing the
5308 rtl results in recognition failures. Failure to handle this case
5309 specially can result in circular rtl.
5311 Solve this by doing a normal pass across the first entry of the
5312 parallel, and only processing the SET_DESTs of the subsequent
5315 if (code
== PARALLEL
5316 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5317 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5319 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
5321 /* If this substitution failed, this whole thing fails. */
5322 if (GET_CODE (new_rtx
) == CLOBBER
5323 && XEXP (new_rtx
, 0) == const0_rtx
)
5326 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5328 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5330 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5333 && GET_CODE (dest
) != CC0
5334 && GET_CODE (dest
) != PC
)
5336 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
5338 /* If this substitution failed, this whole thing fails. */
5339 if (GET_CODE (new_rtx
) == CLOBBER
5340 && XEXP (new_rtx
, 0) == const0_rtx
)
5343 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5349 len
= GET_RTX_LENGTH (code
);
5350 fmt
= GET_RTX_FORMAT (code
);
5352 /* We don't need to process a SET_DEST that is a register, CC0,
5353 or PC, so set up to skip this common case. All other cases
5354 where we want to suppress replacing something inside a
5355 SET_SRC are handled via the IN_DEST operand. */
5357 && (REG_P (SET_DEST (x
))
5358 || GET_CODE (SET_DEST (x
)) == CC0
5359 || GET_CODE (SET_DEST (x
)) == PC
))
5362 /* Trying to simplify the operands of a widening MULT is not likely
5363 to create RTL matching a machine insn. */
5365 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5366 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
5367 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
5368 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
5369 && REG_P (XEXP (XEXP (x
, 0), 0))
5370 && REG_P (XEXP (XEXP (x
, 1), 0))
5375 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5378 op0_mode
= GET_MODE (XEXP (x
, 0));
5380 for (i
= 0; i
< len
; i
++)
5385 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5387 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5389 new_rtx
= (unique_copy
&& n_occurrences
5390 ? copy_rtx (to
) : to
);
5395 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5398 /* If this substitution failed, this whole thing
5400 if (GET_CODE (new_rtx
) == CLOBBER
5401 && XEXP (new_rtx
, 0) == const0_rtx
)
5405 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5408 else if (fmt
[i
] == 'e')
5410 /* If this is a register being set, ignore it. */
5411 new_rtx
= XEXP (x
, i
);
5414 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5416 || code
== STRICT_LOW_PART
))
5419 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5421 /* In general, don't install a subreg involving two
5422 modes not tieable. It can worsen register
5423 allocation, and can even make invalid reload
5424 insns, since the reg inside may need to be copied
5425 from in the outside mode, and that may be invalid
5426 if it is an fp reg copied in integer mode.
5428 We allow two exceptions to this: It is valid if
5429 it is inside another SUBREG and the mode of that
5430 SUBREG and the mode of the inside of TO is
5431 tieable and it is valid if X is a SET that copies
5434 if (GET_CODE (to
) == SUBREG
5435 && ! MODES_TIEABLE_P (GET_MODE (to
),
5436 GET_MODE (SUBREG_REG (to
)))
5437 && ! (code
== SUBREG
5438 && MODES_TIEABLE_P (GET_MODE (x
),
5439 GET_MODE (SUBREG_REG (to
))))
5443 && XEXP (x
, 0) == cc0_rtx
))))
5444 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5448 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5449 && simplify_subreg_regno (REGNO (to
), GET_MODE (to
),
5452 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5454 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5458 /* If we are in a SET_DEST, suppress most cases unless we
5459 have gone inside a MEM, in which case we want to
5460 simplify the address. We assume here that things that
5461 are actually part of the destination have their inner
5462 parts in the first expression. This is true for SUBREG,
5463 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5464 things aside from REG and MEM that should appear in a
5466 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5468 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5469 || code
== ZERO_EXTRACT
))
5472 code
== IF_THEN_ELSE
&& i
== 0,
5475 /* If we found that we will have to reject this combination,
5476 indicate that by returning the CLOBBER ourselves, rather than
5477 an expression containing it. This will speed things up as
5478 well as prevent accidents where two CLOBBERs are considered
5479 to be equal, thus producing an incorrect simplification. */
5481 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5484 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5486 machine_mode mode
= GET_MODE (x
);
5488 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5489 GET_MODE (SUBREG_REG (x
)),
5492 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5494 else if (CONST_SCALAR_INT_P (new_rtx
)
5495 && GET_CODE (x
) == ZERO_EXTEND
)
5497 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5498 new_rtx
, GET_MODE (XEXP (x
, 0)));
5502 SUBST (XEXP (x
, i
), new_rtx
);
5507 /* Check if we are loading something from the constant pool via float
5508 extension; in this case we would undo compress_float_constant
5509 optimization and degenerate constant load to an immediate value. */
5510 if (GET_CODE (x
) == FLOAT_EXTEND
5511 && MEM_P (XEXP (x
, 0))
5512 && MEM_READONLY_P (XEXP (x
, 0)))
5514 rtx tmp
= avoid_constant_pool_reference (x
);
5519 /* Try to simplify X. If the simplification changed the code, it is likely
5520 that further simplification will help, so loop, but limit the number
5521 of repetitions that will be performed. */
5523 for (i
= 0; i
< 4; i
++)
5525 /* If X is sufficiently simple, don't bother trying to do anything
5527 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5528 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5530 if (GET_CODE (x
) == code
)
5533 code
= GET_CODE (x
);
5535 /* We no longer know the original mode of operand 0 since we
5536 have changed the form of X) */
5537 op0_mode
= VOIDmode
;
5543 /* If X is a commutative operation whose operands are not in the canonical
5544 order, use substitutions to swap them. */
5547 maybe_swap_commutative_operands (rtx x
)
5549 if (COMMUTATIVE_ARITH_P (x
)
5550 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5552 rtx temp
= XEXP (x
, 0);
5553 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5554 SUBST (XEXP (x
, 1), temp
);
5558 /* Simplify X, a piece of RTL. We just operate on the expression at the
5559 outer level; call `subst' to simplify recursively. Return the new
5562 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5563 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5567 combine_simplify_rtx (rtx x
, machine_mode op0_mode
, int in_dest
,
5570 enum rtx_code code
= GET_CODE (x
);
5571 machine_mode mode
= GET_MODE (x
);
5572 scalar_int_mode int_mode
;
5576 /* If this is a commutative operation, put a constant last and a complex
5577 expression first. We don't need to do this for comparisons here. */
5578 maybe_swap_commutative_operands (x
);
5580 /* Try to fold this expression in case we have constants that weren't
5583 switch (GET_RTX_CLASS (code
))
5586 if (op0_mode
== VOIDmode
)
5587 op0_mode
= GET_MODE (XEXP (x
, 0));
5588 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5591 case RTX_COMM_COMPARE
:
5593 machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5594 if (cmp_mode
== VOIDmode
)
5596 cmp_mode
= GET_MODE (XEXP (x
, 1));
5597 if (cmp_mode
== VOIDmode
)
5598 cmp_mode
= op0_mode
;
5600 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5601 XEXP (x
, 0), XEXP (x
, 1));
5604 case RTX_COMM_ARITH
:
5606 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5608 case RTX_BITFIELD_OPS
:
5610 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5611 XEXP (x
, 1), XEXP (x
, 2));
5620 code
= GET_CODE (temp
);
5621 op0_mode
= VOIDmode
;
5622 mode
= GET_MODE (temp
);
5625 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5626 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5627 things. Check for cases where both arms are testing the same
5630 Don't do anything if all operands are very simple. */
5633 && ((!OBJECT_P (XEXP (x
, 0))
5634 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5635 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5636 || (!OBJECT_P (XEXP (x
, 1))
5637 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5638 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5640 && (!OBJECT_P (XEXP (x
, 0))
5641 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5642 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5644 rtx cond
, true_rtx
, false_rtx
;
5646 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5648 /* If everything is a comparison, what we have is highly unlikely
5649 to be simpler, so don't use it. */
5650 && ! (COMPARISON_P (x
)
5651 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5653 rtx cop1
= const0_rtx
;
5654 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5656 if (cond_code
== NE
&& COMPARISON_P (cond
))
5659 /* Simplify the alternative arms; this may collapse the true and
5660 false arms to store-flag values. Be careful to use copy_rtx
5661 here since true_rtx or false_rtx might share RTL with x as a
5662 result of the if_then_else_cond call above. */
5663 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5664 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5666 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5667 is unlikely to be simpler. */
5668 if (general_operand (true_rtx
, VOIDmode
)
5669 && general_operand (false_rtx
, VOIDmode
))
5671 enum rtx_code reversed
;
5673 /* Restarting if we generate a store-flag expression will cause
5674 us to loop. Just drop through in this case. */
5676 /* If the result values are STORE_FLAG_VALUE and zero, we can
5677 just make the comparison operation. */
5678 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5679 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5681 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5682 && ((reversed
= reversed_comparison_code_parts
5683 (cond_code
, cond
, cop1
, NULL
))
5685 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5688 /* Likewise, we can make the negate of a comparison operation
5689 if the result values are - STORE_FLAG_VALUE and zero. */
5690 else if (CONST_INT_P (true_rtx
)
5691 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5692 && false_rtx
== const0_rtx
)
5693 x
= simplify_gen_unary (NEG
, mode
,
5694 simplify_gen_relational (cond_code
,
5698 else if (CONST_INT_P (false_rtx
)
5699 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5700 && true_rtx
== const0_rtx
5701 && ((reversed
= reversed_comparison_code_parts
5702 (cond_code
, cond
, cop1
, NULL
))
5704 x
= simplify_gen_unary (NEG
, mode
,
5705 simplify_gen_relational (reversed
,
5710 return gen_rtx_IF_THEN_ELSE (mode
,
5711 simplify_gen_relational (cond_code
,
5716 true_rtx
, false_rtx
);
5718 code
= GET_CODE (x
);
5719 op0_mode
= VOIDmode
;
5724 /* First see if we can apply the inverse distributive law. */
5725 if (code
== PLUS
|| code
== MINUS
5726 || code
== AND
|| code
== IOR
|| code
== XOR
)
5728 x
= apply_distributive_law (x
);
5729 code
= GET_CODE (x
);
5730 op0_mode
= VOIDmode
;
5733 /* If CODE is an associative operation not otherwise handled, see if we
5734 can associate some operands. This can win if they are constants or
5735 if they are logically related (i.e. (a & b) & a). */
5736 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5737 || code
== AND
|| code
== IOR
|| code
== XOR
5738 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5739 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5740 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5742 if (GET_CODE (XEXP (x
, 0)) == code
)
5744 rtx other
= XEXP (XEXP (x
, 0), 0);
5745 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5746 rtx inner_op1
= XEXP (x
, 1);
5749 /* Make sure we pass the constant operand if any as the second
5750 one if this is a commutative operation. */
5751 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5752 std::swap (inner_op0
, inner_op1
);
5753 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5754 : code
== DIV
? MULT
5756 mode
, inner_op0
, inner_op1
);
5758 /* For commutative operations, try the other pair if that one
5760 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5762 other
= XEXP (XEXP (x
, 0), 1);
5763 inner
= simplify_binary_operation (code
, mode
,
5764 XEXP (XEXP (x
, 0), 0),
5769 return simplify_gen_binary (code
, mode
, other
, inner
);
5773 /* A little bit of algebraic simplification here. */
5777 /* Ensure that our address has any ASHIFTs converted to MULT in case
5778 address-recognizing predicates are called later. */
5779 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5780 SUBST (XEXP (x
, 0), temp
);
5784 if (op0_mode
== VOIDmode
)
5785 op0_mode
= GET_MODE (SUBREG_REG (x
));
5787 /* See if this can be moved to simplify_subreg. */
5788 if (CONSTANT_P (SUBREG_REG (x
))
5789 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5790 /* Don't call gen_lowpart if the inner mode
5791 is VOIDmode and we cannot simplify it, as SUBREG without
5792 inner mode is invalid. */
5793 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5794 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5795 return gen_lowpart (mode
, SUBREG_REG (x
));
5797 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5801 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5806 /* If op is known to have all lower bits zero, the result is zero. */
5807 scalar_int_mode int_mode
, int_op0_mode
;
5809 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
5810 && is_a
<scalar_int_mode
> (op0_mode
, &int_op0_mode
)
5811 && (GET_MODE_PRECISION (int_mode
)
5812 < GET_MODE_PRECISION (int_op0_mode
))
5813 && (subreg_lowpart_offset (int_mode
, int_op0_mode
)
5815 && HWI_COMPUTABLE_MODE_P (int_op0_mode
)
5816 && (nonzero_bits (SUBREG_REG (x
), int_op0_mode
)
5817 & GET_MODE_MASK (int_mode
)) == 0)
5818 return CONST0_RTX (int_mode
);
5821 /* Don't change the mode of the MEM if that would change the meaning
5823 if (MEM_P (SUBREG_REG (x
))
5824 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5825 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5826 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5827 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5829 /* Note that we cannot do any narrowing for non-constants since
5830 we might have been counting on using the fact that some bits were
5831 zero. We now do this in the SET. */
5836 temp
= expand_compound_operation (XEXP (x
, 0));
5838 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5839 replaced by (lshiftrt X C). This will convert
5840 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5842 if (GET_CODE (temp
) == ASHIFTRT
5843 && CONST_INT_P (XEXP (temp
, 1))
5844 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5845 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5846 INTVAL (XEXP (temp
, 1)));
5848 /* If X has only a single bit that might be nonzero, say, bit I, convert
5849 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5850 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5851 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5852 or a SUBREG of one since we'd be making the expression more
5853 complex if it was just a register. */
5856 && ! (GET_CODE (temp
) == SUBREG
5857 && REG_P (SUBREG_REG (temp
)))
5858 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
5859 && (i
= exact_log2 (nonzero_bits (temp
, int_mode
))) >= 0)
5861 rtx temp1
= simplify_shift_const
5862 (NULL_RTX
, ASHIFTRT
, int_mode
,
5863 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
, temp
,
5864 GET_MODE_PRECISION (int_mode
) - 1 - i
),
5865 GET_MODE_PRECISION (int_mode
) - 1 - i
);
5867 /* If all we did was surround TEMP with the two shifts, we
5868 haven't improved anything, so don't use it. Otherwise,
5869 we are better off with TEMP1. */
5870 if (GET_CODE (temp1
) != ASHIFTRT
5871 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5872 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5878 /* We can't handle truncation to a partial integer mode here
5879 because we don't know the real bitsize of the partial
5881 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5884 if (HWI_COMPUTABLE_MODE_P (mode
))
5886 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5887 GET_MODE_MASK (mode
), 0));
5889 /* We can truncate a constant value and return it. */
5890 if (CONST_INT_P (XEXP (x
, 0)))
5891 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5893 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5894 whose value is a comparison can be replaced with a subreg if
5895 STORE_FLAG_VALUE permits. */
5896 if (HWI_COMPUTABLE_MODE_P (mode
)
5897 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5898 && (temp
= get_last_value (XEXP (x
, 0)))
5899 && COMPARISON_P (temp
))
5900 return gen_lowpart (mode
, XEXP (x
, 0));
5904 /* (const (const X)) can become (const X). Do it this way rather than
5905 returning the inner CONST since CONST can be shared with a
5907 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5908 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5912 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5913 can add in an offset. find_split_point will split this address up
5914 again if it doesn't match. */
5915 if (HAVE_lo_sum
&& GET_CODE (XEXP (x
, 0)) == HIGH
5916 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5921 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5922 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5923 bit-field and can be replaced by either a sign_extend or a
5924 sign_extract. The `and' may be a zero_extend and the two
5925 <c>, -<c> constants may be reversed. */
5926 if (GET_CODE (XEXP (x
, 0)) == XOR
5927 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
5928 && CONST_INT_P (XEXP (x
, 1))
5929 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5930 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5931 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5932 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5933 && HWI_COMPUTABLE_MODE_P (int_mode
)
5934 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5935 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5936 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5937 == (HOST_WIDE_INT_1U
<< (i
+ 1)) - 1))
5938 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5939 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5940 == (unsigned int) i
+ 1))))
5941 return simplify_shift_const
5942 (NULL_RTX
, ASHIFTRT
, int_mode
,
5943 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
5944 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5945 GET_MODE_PRECISION (int_mode
) - (i
+ 1)),
5946 GET_MODE_PRECISION (int_mode
) - (i
+ 1));
5948 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5949 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5950 the bitsize of the mode - 1. This allows simplification of
5951 "a = (b & 8) == 0;" */
5952 if (XEXP (x
, 1) == constm1_rtx
5953 && !REG_P (XEXP (x
, 0))
5954 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5955 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5956 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
5957 && nonzero_bits (XEXP (x
, 0), int_mode
) == 1)
5958 return simplify_shift_const
5959 (NULL_RTX
, ASHIFTRT
, int_mode
,
5960 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
5961 gen_rtx_XOR (int_mode
, XEXP (x
, 0),
5963 GET_MODE_PRECISION (int_mode
) - 1),
5964 GET_MODE_PRECISION (int_mode
) - 1);
5966 /* If we are adding two things that have no bits in common, convert
5967 the addition into an IOR. This will often be further simplified,
5968 for example in cases like ((a & 1) + (a & 2)), which can
5971 if (HWI_COMPUTABLE_MODE_P (mode
)
5972 && (nonzero_bits (XEXP (x
, 0), mode
)
5973 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5975 /* Try to simplify the expression further. */
5976 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5977 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
5979 /* If we could, great. If not, do not go ahead with the IOR
5980 replacement, since PLUS appears in many special purpose
5981 address arithmetic instructions. */
5982 if (GET_CODE (temp
) != CLOBBER
5983 && (GET_CODE (temp
) != IOR
5984 || ((XEXP (temp
, 0) != XEXP (x
, 0)
5985 || XEXP (temp
, 1) != XEXP (x
, 1))
5986 && (XEXP (temp
, 0) != XEXP (x
, 1)
5987 || XEXP (temp
, 1) != XEXP (x
, 0)))))
5991 /* Canonicalize x + x into x << 1. */
5992 if (GET_MODE_CLASS (mode
) == MODE_INT
5993 && rtx_equal_p (XEXP (x
, 0), XEXP (x
, 1))
5994 && !side_effects_p (XEXP (x
, 0)))
5995 return simplify_gen_binary (ASHIFT
, mode
, XEXP (x
, 0), const1_rtx
);
6000 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6001 (and <foo> (const_int pow2-1)) */
6002 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
6003 && GET_CODE (XEXP (x
, 1)) == AND
6004 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
6005 && pow2p_hwi (-UINTVAL (XEXP (XEXP (x
, 1), 1)))
6006 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
6007 return simplify_and_const_int (NULL_RTX
, int_mode
, XEXP (x
, 0),
6008 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
6012 /* If we have (mult (plus A B) C), apply the distributive law and then
6013 the inverse distributive law to see if things simplify. This
6014 occurs mostly in addresses, often when unrolling loops. */
6016 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
6018 rtx result
= distribute_and_simplify_rtx (x
, 0);
6023 /* Try simplify a*(b/c) as (a*b)/c. */
6024 if (FLOAT_MODE_P (mode
) && flag_associative_math
6025 && GET_CODE (XEXP (x
, 0)) == DIV
)
6027 rtx tem
= simplify_binary_operation (MULT
, mode
,
6028 XEXP (XEXP (x
, 0), 0),
6031 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
6036 /* If this is a divide by a power of two, treat it as a shift if
6037 its first operand is a shift. */
6038 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
6039 && CONST_INT_P (XEXP (x
, 1))
6040 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
6041 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
6042 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6043 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
6044 || GET_CODE (XEXP (x
, 0)) == ROTATE
6045 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
6046 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, int_mode
,
6051 case GT
: case GTU
: case GE
: case GEU
:
6052 case LT
: case LTU
: case LE
: case LEU
:
6053 case UNEQ
: case LTGT
:
6054 case UNGT
: case UNGE
:
6055 case UNLT
: case UNLE
:
6056 case UNORDERED
: case ORDERED
:
6057 /* If the first operand is a condition code, we can't do anything
6059 if (GET_CODE (XEXP (x
, 0)) == COMPARE
6060 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
6061 && ! CC0_P (XEXP (x
, 0))))
6063 rtx op0
= XEXP (x
, 0);
6064 rtx op1
= XEXP (x
, 1);
6065 enum rtx_code new_code
;
6067 if (GET_CODE (op0
) == COMPARE
)
6068 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
6070 /* Simplify our comparison, if possible. */
6071 new_code
= simplify_comparison (code
, &op0
, &op1
);
6073 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6074 if only the low-order bit is possibly nonzero in X (such as when
6075 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6076 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6077 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6080 Remove any ZERO_EXTRACT we made when thinking this was a
6081 comparison. It may now be simpler to use, e.g., an AND. If a
6082 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6083 the call to make_compound_operation in the SET case.
6085 Don't apply these optimizations if the caller would
6086 prefer a comparison rather than a value.
6087 E.g., for the condition in an IF_THEN_ELSE most targets need
6088 an explicit comparison. */
6093 else if (STORE_FLAG_VALUE
== 1
6095 && is_int_mode (mode
, &int_mode
)
6096 && op1
== const0_rtx
6097 && int_mode
== GET_MODE (op0
)
6098 && nonzero_bits (op0
, int_mode
) == 1)
6099 return gen_lowpart (int_mode
,
6100 expand_compound_operation (op0
));
6102 else if (STORE_FLAG_VALUE
== 1
6104 && is_int_mode (mode
, &int_mode
)
6105 && op1
== const0_rtx
6106 && int_mode
== GET_MODE (op0
)
6107 && (num_sign_bit_copies (op0
, int_mode
)
6108 == GET_MODE_PRECISION (int_mode
)))
6110 op0
= expand_compound_operation (op0
);
6111 return simplify_gen_unary (NEG
, int_mode
,
6112 gen_lowpart (int_mode
, op0
),
6116 else if (STORE_FLAG_VALUE
== 1
6118 && is_int_mode (mode
, &int_mode
)
6119 && op1
== const0_rtx
6120 && int_mode
== GET_MODE (op0
)
6121 && nonzero_bits (op0
, int_mode
) == 1)
6123 op0
= expand_compound_operation (op0
);
6124 return simplify_gen_binary (XOR
, int_mode
,
6125 gen_lowpart (int_mode
, op0
),
6129 else if (STORE_FLAG_VALUE
== 1
6131 && is_int_mode (mode
, &int_mode
)
6132 && op1
== const0_rtx
6133 && int_mode
== GET_MODE (op0
)
6134 && (num_sign_bit_copies (op0
, int_mode
)
6135 == GET_MODE_PRECISION (int_mode
)))
6137 op0
= expand_compound_operation (op0
);
6138 return plus_constant (int_mode
, gen_lowpart (int_mode
, op0
), 1);
6141 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6146 else if (STORE_FLAG_VALUE
== -1
6148 && is_int_mode (mode
, &int_mode
)
6149 && op1
== const0_rtx
6150 && int_mode
== GET_MODE (op0
)
6151 && (num_sign_bit_copies (op0
, int_mode
)
6152 == GET_MODE_PRECISION (int_mode
)))
6153 return gen_lowpart (int_mode
, expand_compound_operation (op0
));
6155 else if (STORE_FLAG_VALUE
== -1
6157 && is_int_mode (mode
, &int_mode
)
6158 && op1
== const0_rtx
6159 && int_mode
== GET_MODE (op0
)
6160 && nonzero_bits (op0
, int_mode
) == 1)
6162 op0
= expand_compound_operation (op0
);
6163 return simplify_gen_unary (NEG
, int_mode
,
6164 gen_lowpart (int_mode
, op0
),
6168 else if (STORE_FLAG_VALUE
== -1
6170 && is_int_mode (mode
, &int_mode
)
6171 && op1
== const0_rtx
6172 && int_mode
== GET_MODE (op0
)
6173 && (num_sign_bit_copies (op0
, int_mode
)
6174 == GET_MODE_PRECISION (int_mode
)))
6176 op0
= expand_compound_operation (op0
);
6177 return simplify_gen_unary (NOT
, int_mode
,
6178 gen_lowpart (int_mode
, op0
),
6182 /* If X is 0/1, (eq X 0) is X-1. */
6183 else if (STORE_FLAG_VALUE
== -1
6185 && is_int_mode (mode
, &int_mode
)
6186 && op1
== const0_rtx
6187 && int_mode
== GET_MODE (op0
)
6188 && nonzero_bits (op0
, int_mode
) == 1)
6190 op0
= expand_compound_operation (op0
);
6191 return plus_constant (int_mode
, gen_lowpart (int_mode
, op0
), -1);
6194 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6195 one bit that might be nonzero, we can convert (ne x 0) to
6196 (ashift x c) where C puts the bit in the sign bit. Remove any
6197 AND with STORE_FLAG_VALUE when we are done, since we are only
6198 going to test the sign bit. */
6200 && is_int_mode (mode
, &int_mode
)
6201 && HWI_COMPUTABLE_MODE_P (int_mode
)
6202 && val_signbit_p (int_mode
, STORE_FLAG_VALUE
)
6203 && op1
== const0_rtx
6204 && int_mode
== GET_MODE (op0
)
6205 && (i
= exact_log2 (nonzero_bits (op0
, int_mode
))) >= 0)
6207 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6208 expand_compound_operation (op0
),
6209 GET_MODE_PRECISION (int_mode
) - 1 - i
);
6210 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
6216 /* If the code changed, return a whole new comparison.
6217 We also need to avoid using SUBST in cases where
6218 simplify_comparison has widened a comparison with a CONST_INT,
6219 since in that case the wider CONST_INT may fail the sanity
6220 checks in do_SUBST. */
6221 if (new_code
!= code
6222 || (CONST_INT_P (op1
)
6223 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
6224 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
6225 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
6227 /* Otherwise, keep this operation, but maybe change its operands.
6228 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6229 SUBST (XEXP (x
, 0), op0
);
6230 SUBST (XEXP (x
, 1), op1
);
6235 return simplify_if_then_else (x
);
6241 /* If we are processing SET_DEST, we are done. */
6245 return expand_compound_operation (x
);
6248 return simplify_set (x
);
6252 return simplify_logical (x
);
6259 /* If this is a shift by a constant amount, simplify it. */
6260 if (CONST_INT_P (XEXP (x
, 1)))
6261 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
6262 INTVAL (XEXP (x
, 1)));
6264 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
6266 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
6268 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
6280 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6283 simplify_if_then_else (rtx x
)
6285 machine_mode mode
= GET_MODE (x
);
6286 rtx cond
= XEXP (x
, 0);
6287 rtx true_rtx
= XEXP (x
, 1);
6288 rtx false_rtx
= XEXP (x
, 2);
6289 enum rtx_code true_code
= GET_CODE (cond
);
6290 int comparison_p
= COMPARISON_P (cond
);
6293 enum rtx_code false_code
;
6295 scalar_int_mode int_mode
, inner_mode
;
6297 /* Simplify storing of the truth value. */
6298 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
6299 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
6300 XEXP (cond
, 0), XEXP (cond
, 1));
6302 /* Also when the truth value has to be reversed. */
6304 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
6305 && (reversed
= reversed_comparison (cond
, mode
)))
6308 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6309 in it is being compared against certain values. Get the true and false
6310 comparisons and see if that says anything about the value of each arm. */
6313 && ((false_code
= reversed_comparison_code (cond
, NULL
))
6315 && REG_P (XEXP (cond
, 0)))
6318 rtx from
= XEXP (cond
, 0);
6319 rtx true_val
= XEXP (cond
, 1);
6320 rtx false_val
= true_val
;
6323 /* If FALSE_CODE is EQ, swap the codes and arms. */
6325 if (false_code
== EQ
)
6327 swapped
= 1, true_code
= EQ
, false_code
= NE
;
6328 std::swap (true_rtx
, false_rtx
);
6331 scalar_int_mode from_mode
;
6332 if (is_a
<scalar_int_mode
> (GET_MODE (from
), &from_mode
))
6334 /* If we are comparing against zero and the expression being
6335 tested has only a single bit that might be nonzero, that is
6336 its value when it is not equal to zero. Similarly if it is
6337 known to be -1 or 0. */
6339 && true_val
== const0_rtx
6340 && pow2p_hwi (nzb
= nonzero_bits (from
, from_mode
)))
6343 false_val
= gen_int_mode (nzb
, from_mode
);
6345 else if (true_code
== EQ
6346 && true_val
== const0_rtx
6347 && (num_sign_bit_copies (from
, from_mode
)
6348 == GET_MODE_PRECISION (from_mode
)))
6351 false_val
= constm1_rtx
;
6355 /* Now simplify an arm if we know the value of the register in the
6356 branch and it is used in the arm. Be careful due to the potential
6357 of locally-shared RTL. */
6359 if (reg_mentioned_p (from
, true_rtx
))
6360 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6362 pc_rtx
, pc_rtx
, 0, 0, 0);
6363 if (reg_mentioned_p (from
, false_rtx
))
6364 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6366 pc_rtx
, pc_rtx
, 0, 0, 0);
6368 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6369 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6371 true_rtx
= XEXP (x
, 1);
6372 false_rtx
= XEXP (x
, 2);
6373 true_code
= GET_CODE (cond
);
6376 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6377 reversed, do so to avoid needing two sets of patterns for
6378 subtract-and-branch insns. Similarly if we have a constant in the true
6379 arm, the false arm is the same as the first operand of the comparison, or
6380 the false arm is more complicated than the true arm. */
6383 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6384 && (true_rtx
== pc_rtx
6385 || (CONSTANT_P (true_rtx
)
6386 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6387 || true_rtx
== const0_rtx
6388 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6389 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6390 && !OBJECT_P (false_rtx
))
6391 || reg_mentioned_p (true_rtx
, false_rtx
)
6392 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6394 true_code
= reversed_comparison_code (cond
, NULL
);
6395 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6396 SUBST (XEXP (x
, 1), false_rtx
);
6397 SUBST (XEXP (x
, 2), true_rtx
);
6399 std::swap (true_rtx
, false_rtx
);
6402 /* It is possible that the conditional has been simplified out. */
6403 true_code
= GET_CODE (cond
);
6404 comparison_p
= COMPARISON_P (cond
);
6407 /* If the two arms are identical, we don't need the comparison. */
6409 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6412 /* Convert a == b ? b : a to "a". */
6413 if (true_code
== EQ
&& ! side_effects_p (cond
)
6414 && !HONOR_NANS (mode
)
6415 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6416 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6418 else if (true_code
== NE
&& ! side_effects_p (cond
)
6419 && !HONOR_NANS (mode
)
6420 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6421 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6424 /* Look for cases where we have (abs x) or (neg (abs X)). */
6426 if (GET_MODE_CLASS (mode
) == MODE_INT
6428 && XEXP (cond
, 1) == const0_rtx
6429 && GET_CODE (false_rtx
) == NEG
6430 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6431 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6432 && ! side_effects_p (true_rtx
))
6437 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6441 simplify_gen_unary (NEG
, mode
,
6442 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6448 /* Look for MIN or MAX. */
6450 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6452 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6453 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6454 && ! side_effects_p (cond
))
6459 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6462 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6465 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6468 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6473 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6474 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6475 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6476 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6477 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6478 neither 1 or -1, but it isn't worth checking for. */
6480 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6482 && is_int_mode (mode
, &int_mode
)
6483 && ! side_effects_p (x
))
6485 rtx t
= make_compound_operation (true_rtx
, SET
);
6486 rtx f
= make_compound_operation (false_rtx
, SET
);
6487 rtx cond_op0
= XEXP (cond
, 0);
6488 rtx cond_op1
= XEXP (cond
, 1);
6489 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6490 machine_mode m
= int_mode
;
6491 rtx z
= 0, c1
= NULL_RTX
;
6493 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6494 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6495 || GET_CODE (t
) == ASHIFT
6496 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6497 && rtx_equal_p (XEXP (t
, 0), f
))
6498 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6500 /* If an identity-zero op is commutative, check whether there
6501 would be a match if we swapped the operands. */
6502 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6503 || GET_CODE (t
) == XOR
)
6504 && rtx_equal_p (XEXP (t
, 1), f
))
6505 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6506 else if (GET_CODE (t
) == SIGN_EXTEND
6507 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6508 && (GET_CODE (XEXP (t
, 0)) == PLUS
6509 || GET_CODE (XEXP (t
, 0)) == MINUS
6510 || GET_CODE (XEXP (t
, 0)) == IOR
6511 || GET_CODE (XEXP (t
, 0)) == XOR
6512 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6513 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6514 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6515 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6516 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6517 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6518 && (num_sign_bit_copies (f
, GET_MODE (f
))
6520 (GET_MODE_PRECISION (int_mode
)
6521 - GET_MODE_PRECISION (inner_mode
))))
6523 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6524 extend_op
= SIGN_EXTEND
;
6527 else if (GET_CODE (t
) == SIGN_EXTEND
6528 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6529 && (GET_CODE (XEXP (t
, 0)) == PLUS
6530 || GET_CODE (XEXP (t
, 0)) == IOR
6531 || GET_CODE (XEXP (t
, 0)) == XOR
)
6532 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6533 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6534 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6535 && (num_sign_bit_copies (f
, GET_MODE (f
))
6537 (GET_MODE_PRECISION (int_mode
)
6538 - GET_MODE_PRECISION (inner_mode
))))
6540 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6541 extend_op
= SIGN_EXTEND
;
6544 else if (GET_CODE (t
) == ZERO_EXTEND
6545 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6546 && (GET_CODE (XEXP (t
, 0)) == PLUS
6547 || GET_CODE (XEXP (t
, 0)) == MINUS
6548 || GET_CODE (XEXP (t
, 0)) == IOR
6549 || GET_CODE (XEXP (t
, 0)) == XOR
6550 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6551 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6552 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6553 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6554 && HWI_COMPUTABLE_MODE_P (int_mode
)
6555 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6556 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6557 && ((nonzero_bits (f
, GET_MODE (f
))
6558 & ~GET_MODE_MASK (inner_mode
))
6561 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6562 extend_op
= ZERO_EXTEND
;
6565 else if (GET_CODE (t
) == ZERO_EXTEND
6566 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6567 && (GET_CODE (XEXP (t
, 0)) == PLUS
6568 || GET_CODE (XEXP (t
, 0)) == IOR
6569 || GET_CODE (XEXP (t
, 0)) == XOR
)
6570 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6571 && HWI_COMPUTABLE_MODE_P (int_mode
)
6572 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6573 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6574 && ((nonzero_bits (f
, GET_MODE (f
))
6575 & ~GET_MODE_MASK (inner_mode
))
6578 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6579 extend_op
= ZERO_EXTEND
;
6585 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6586 cond_op0
, cond_op1
),
6587 pc_rtx
, pc_rtx
, 0, 0, 0);
6588 temp
= simplify_gen_binary (MULT
, m
, temp
,
6589 simplify_gen_binary (MULT
, m
, c1
,
6591 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6592 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6594 if (extend_op
!= UNKNOWN
)
6595 temp
= simplify_gen_unary (extend_op
, int_mode
, temp
, m
);
6601 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6602 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6603 negation of a single bit, we can convert this operation to a shift. We
6604 can actually do this more generally, but it doesn't seem worth it. */
6607 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6608 && XEXP (cond
, 1) == const0_rtx
6609 && false_rtx
== const0_rtx
6610 && CONST_INT_P (true_rtx
)
6611 && ((1 == nonzero_bits (XEXP (cond
, 0), int_mode
)
6612 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6613 || ((num_sign_bit_copies (XEXP (cond
, 0), int_mode
)
6614 == GET_MODE_PRECISION (int_mode
))
6615 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6617 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6618 gen_lowpart (int_mode
, XEXP (cond
, 0)), i
);
6620 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6621 non-zero bit in A is C1. */
6622 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6623 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6624 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6625 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (cond
, 0)), &inner_mode
)
6626 && (UINTVAL (true_rtx
) & GET_MODE_MASK (int_mode
))
6627 == nonzero_bits (XEXP (cond
, 0), inner_mode
)
6628 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (int_mode
))) >= 0)
6630 rtx val
= XEXP (cond
, 0);
6631 if (inner_mode
== int_mode
)
6633 else if (GET_MODE_PRECISION (inner_mode
) < GET_MODE_PRECISION (int_mode
))
6634 return simplify_gen_unary (ZERO_EXTEND
, int_mode
, val
, inner_mode
);
6640 /* Simplify X, a SET expression. Return the new expression. */
6643 simplify_set (rtx x
)
6645 rtx src
= SET_SRC (x
);
6646 rtx dest
= SET_DEST (x
);
6648 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6649 rtx_insn
*other_insn
;
6651 scalar_int_mode int_mode
;
6653 /* (set (pc) (return)) gets written as (return). */
6654 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6657 /* Now that we know for sure which bits of SRC we are using, see if we can
6658 simplify the expression for the object knowing that we only need the
6661 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6663 src
= force_to_mode (src
, mode
, HOST_WIDE_INT_M1U
, 0);
6664 SUBST (SET_SRC (x
), src
);
6667 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6668 the comparison result and try to simplify it unless we already have used
6669 undobuf.other_insn. */
6670 if ((GET_MODE_CLASS (mode
) == MODE_CC
6671 || GET_CODE (src
) == COMPARE
6673 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6674 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6675 && COMPARISON_P (*cc_use
)
6676 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6678 enum rtx_code old_code
= GET_CODE (*cc_use
);
6679 enum rtx_code new_code
;
6681 int other_changed
= 0;
6682 rtx inner_compare
= NULL_RTX
;
6683 machine_mode compare_mode
= GET_MODE (dest
);
6685 if (GET_CODE (src
) == COMPARE
)
6687 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6688 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6690 inner_compare
= op0
;
6691 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6695 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6697 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6700 new_code
= old_code
;
6701 else if (!CONSTANT_P (tmp
))
6703 new_code
= GET_CODE (tmp
);
6704 op0
= XEXP (tmp
, 0);
6705 op1
= XEXP (tmp
, 1);
6709 rtx pat
= PATTERN (other_insn
);
6710 undobuf
.other_insn
= other_insn
;
6711 SUBST (*cc_use
, tmp
);
6713 /* Attempt to simplify CC user. */
6714 if (GET_CODE (pat
) == SET
)
6716 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6717 if (new_rtx
!= NULL_RTX
)
6718 SUBST (SET_SRC (pat
), new_rtx
);
6721 /* Convert X into a no-op move. */
6722 SUBST (SET_DEST (x
), pc_rtx
);
6723 SUBST (SET_SRC (x
), pc_rtx
);
6727 /* Simplify our comparison, if possible. */
6728 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6730 #ifdef SELECT_CC_MODE
6731 /* If this machine has CC modes other than CCmode, check to see if we
6732 need to use a different CC mode here. */
6733 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6734 compare_mode
= GET_MODE (op0
);
6735 else if (inner_compare
6736 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6737 && new_code
== old_code
6738 && op0
== XEXP (inner_compare
, 0)
6739 && op1
== XEXP (inner_compare
, 1))
6740 compare_mode
= GET_MODE (inner_compare
);
6742 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6744 /* If the mode changed, we have to change SET_DEST, the mode in the
6745 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6746 a hard register, just build new versions with the proper mode. If it
6747 is a pseudo, we lose unless it is only time we set the pseudo, in
6748 which case we can safely change its mode. */
6749 if (!HAVE_cc0
&& compare_mode
!= GET_MODE (dest
))
6751 if (can_change_dest_mode (dest
, 0, compare_mode
))
6753 unsigned int regno
= REGNO (dest
);
6756 if (regno
< FIRST_PSEUDO_REGISTER
)
6757 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6760 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6761 new_dest
= regno_reg_rtx
[regno
];
6764 SUBST (SET_DEST (x
), new_dest
);
6765 SUBST (XEXP (*cc_use
, 0), new_dest
);
6771 #endif /* SELECT_CC_MODE */
6773 /* If the code changed, we have to build a new comparison in
6774 undobuf.other_insn. */
6775 if (new_code
!= old_code
)
6777 int other_changed_previously
= other_changed
;
6778 unsigned HOST_WIDE_INT mask
;
6779 rtx old_cc_use
= *cc_use
;
6781 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6785 /* If the only change we made was to change an EQ into an NE or
6786 vice versa, OP0 has only one bit that might be nonzero, and OP1
6787 is zero, check if changing the user of the condition code will
6788 produce a valid insn. If it won't, we can keep the original code
6789 in that insn by surrounding our operation with an XOR. */
6791 if (((old_code
== NE
&& new_code
== EQ
)
6792 || (old_code
== EQ
&& new_code
== NE
))
6793 && ! other_changed_previously
&& op1
== const0_rtx
6794 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6795 && pow2p_hwi (mask
= nonzero_bits (op0
, GET_MODE (op0
))))
6797 rtx pat
= PATTERN (other_insn
), note
= 0;
6799 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6800 && ! check_asm_operands (pat
)))
6802 *cc_use
= old_cc_use
;
6805 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
6813 undobuf
.other_insn
= other_insn
;
6815 /* Don't generate a compare of a CC with 0, just use that CC. */
6816 if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6818 SUBST (SET_SRC (x
), op0
);
6821 /* Otherwise, if we didn't previously have the same COMPARE we
6822 want, create it from scratch. */
6823 else if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
6824 || XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6826 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6832 /* Get SET_SRC in a form where we have placed back any
6833 compound expressions. Then do the checks below. */
6834 src
= make_compound_operation (src
, SET
);
6835 SUBST (SET_SRC (x
), src
);
6838 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6839 and X being a REG or (subreg (reg)), we may be able to convert this to
6840 (set (subreg:m2 x) (op)).
6842 We can always do this if M1 is narrower than M2 because that means that
6843 we only care about the low bits of the result.
6845 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6846 perform a narrower operation than requested since the high-order bits will
6847 be undefined. On machine where it is defined, this transformation is safe
6848 as long as M1 and M2 have the same number of words. */
6850 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6851 && !OBJECT_P (SUBREG_REG (src
))
6852 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6854 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6855 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6856 && (WORD_REGISTER_OPERATIONS
|| !paradoxical_subreg_p (src
))
6857 #ifdef CANNOT_CHANGE_MODE_CLASS
6858 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6859 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6860 GET_MODE (SUBREG_REG (src
)),
6864 || (GET_CODE (dest
) == SUBREG
6865 && REG_P (SUBREG_REG (dest
)))))
6867 SUBST (SET_DEST (x
),
6868 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6870 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6872 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6875 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6878 && GET_CODE (src
) == SUBREG
6879 && subreg_lowpart_p (src
)
6880 && (GET_MODE_PRECISION (GET_MODE (src
))
6881 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6883 rtx inner
= SUBREG_REG (src
);
6884 machine_mode inner_mode
= GET_MODE (inner
);
6886 /* Here we make sure that we don't have a sign bit on. */
6887 if (val_signbit_known_clear_p (GET_MODE (src
),
6888 nonzero_bits (inner
, inner_mode
)))
6890 SUBST (SET_SRC (x
), inner
);
6895 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6896 would require a paradoxical subreg. Replace the subreg with a
6897 zero_extend to avoid the reload that would otherwise be required. */
6899 enum rtx_code extend_op
;
6900 if (paradoxical_subreg_p (src
)
6901 && MEM_P (SUBREG_REG (src
))
6902 && (extend_op
= load_extend_op (GET_MODE (SUBREG_REG (src
)))) != UNKNOWN
)
6905 gen_rtx_fmt_e (extend_op
, GET_MODE (src
), SUBREG_REG (src
)));
6910 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6911 are comparing an item known to be 0 or -1 against 0, use a logical
6912 operation instead. Check for one of the arms being an IOR of the other
6913 arm with some value. We compute three terms to be IOR'ed together. In
6914 practice, at most two will be nonzero. Then we do the IOR's. */
6916 if (GET_CODE (dest
) != PC
6917 && GET_CODE (src
) == IF_THEN_ELSE
6918 && is_int_mode (GET_MODE (src
), &int_mode
)
6919 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6920 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6921 && int_mode
== GET_MODE (XEXP (XEXP (src
, 0), 0))
6922 && (!HAVE_conditional_move
6923 || ! can_conditionally_move_p (int_mode
))
6924 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0), int_mode
)
6925 == GET_MODE_PRECISION (int_mode
))
6926 && ! side_effects_p (src
))
6928 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6929 ? XEXP (src
, 1) : XEXP (src
, 2));
6930 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6931 ? XEXP (src
, 2) : XEXP (src
, 1));
6932 rtx term1
= const0_rtx
, term2
, term3
;
6934 if (GET_CODE (true_rtx
) == IOR
6935 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6936 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6937 else if (GET_CODE (true_rtx
) == IOR
6938 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6939 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6940 else if (GET_CODE (false_rtx
) == IOR
6941 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6942 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6943 else if (GET_CODE (false_rtx
) == IOR
6944 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6945 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6947 term2
= simplify_gen_binary (AND
, int_mode
,
6948 XEXP (XEXP (src
, 0), 0), true_rtx
);
6949 term3
= simplify_gen_binary (AND
, int_mode
,
6950 simplify_gen_unary (NOT
, int_mode
,
6951 XEXP (XEXP (src
, 0), 0),
6956 simplify_gen_binary (IOR
, int_mode
,
6957 simplify_gen_binary (IOR
, int_mode
,
6964 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6965 whole thing fail. */
6966 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6968 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6971 /* Convert this into a field assignment operation, if possible. */
6972 return make_field_assignment (x
);
6975 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6979 simplify_logical (rtx x
)
6981 rtx op0
= XEXP (x
, 0);
6982 rtx op1
= XEXP (x
, 1);
6983 scalar_int_mode mode
;
6985 switch (GET_CODE (x
))
6988 /* We can call simplify_and_const_int only if we don't lose
6989 any (sign) bits when converting INTVAL (op1) to
6990 "unsigned HOST_WIDE_INT". */
6991 if (is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
)
6992 && CONST_INT_P (op1
)
6993 && (HWI_COMPUTABLE_MODE_P (mode
)
6994 || INTVAL (op1
) > 0))
6996 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6997 if (GET_CODE (x
) != AND
)
7004 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7005 apply the distributive law and then the inverse distributive
7006 law to see if things simplify. */
7007 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
7009 rtx result
= distribute_and_simplify_rtx (x
, 0);
7013 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
7015 rtx result
= distribute_and_simplify_rtx (x
, 1);
7022 /* If we have (ior (and A B) C), apply the distributive law and then
7023 the inverse distributive law to see if things simplify. */
7025 if (GET_CODE (op0
) == AND
)
7027 rtx result
= distribute_and_simplify_rtx (x
, 0);
7032 if (GET_CODE (op1
) == AND
)
7034 rtx result
= distribute_and_simplify_rtx (x
, 1);
7047 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7048 operations" because they can be replaced with two more basic operations.
7049 ZERO_EXTEND is also considered "compound" because it can be replaced with
7050 an AND operation, which is simpler, though only one operation.
7052 The function expand_compound_operation is called with an rtx expression
7053 and will convert it to the appropriate shifts and AND operations,
7054 simplifying at each stage.
7056 The function make_compound_operation is called to convert an expression
7057 consisting of shifts and ANDs into the equivalent compound expression.
7058 It is the inverse of this function, loosely speaking. */
7061 expand_compound_operation (rtx x
)
7063 unsigned HOST_WIDE_INT pos
= 0, len
;
7065 unsigned int modewidth
;
7067 scalar_int_mode inner_mode
;
7069 switch (GET_CODE (x
))
7075 /* We can't necessarily use a const_int for a multiword mode;
7076 it depends on implicitly extending the value.
7077 Since we don't know the right way to extend it,
7078 we can't tell whether the implicit way is right.
7080 Even for a mode that is no wider than a const_int,
7081 we can't win, because we need to sign extend one of its bits through
7082 the rest of it, and we don't know which bit. */
7083 if (CONST_INT_P (XEXP (x
, 0)))
7086 /* Reject modes that aren't scalar integers because turning vector
7087 or complex modes into shifts causes problems. */
7088 if (!is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
))
7091 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7092 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7093 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7094 reloaded. If not for that, MEM's would very rarely be safe.
7096 Reject modes bigger than a word, because we might not be able
7097 to reference a two-register group starting with an arbitrary register
7098 (and currently gen_lowpart might crash for a SUBREG). */
7100 if (GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7103 len
= GET_MODE_PRECISION (inner_mode
);
7104 /* If the inner object has VOIDmode (the only way this can happen
7105 is if it is an ASM_OPERANDS), we can't do anything since we don't
7106 know how much masking to do. */
7118 /* If the operand is a CLOBBER, just return it. */
7119 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
7122 if (!CONST_INT_P (XEXP (x
, 1))
7123 || !CONST_INT_P (XEXP (x
, 2)))
7126 /* Reject modes that aren't scalar integers because turning vector
7127 or complex modes into shifts causes problems. */
7128 if (!is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
))
7131 len
= INTVAL (XEXP (x
, 1));
7132 pos
= INTVAL (XEXP (x
, 2));
7134 /* This should stay within the object being extracted, fail otherwise. */
7135 if (len
+ pos
> GET_MODE_PRECISION (inner_mode
))
7138 if (BITS_BIG_ENDIAN
)
7139 pos
= GET_MODE_PRECISION (inner_mode
) - len
- pos
;
7146 /* Convert sign extension to zero extension, if we know that the high
7147 bit is not set, as this is easier to optimize. It will be converted
7148 back to cheaper alternative in make_extraction. */
7149 if (GET_CODE (x
) == SIGN_EXTEND
7150 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7151 && ((nonzero_bits (XEXP (x
, 0), inner_mode
)
7152 & ~(((unsigned HOST_WIDE_INT
) GET_MODE_MASK (inner_mode
)) >> 1))
7155 machine_mode mode
= GET_MODE (x
);
7156 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, XEXP (x
, 0));
7157 rtx temp2
= expand_compound_operation (temp
);
7159 /* Make sure this is a profitable operation. */
7160 if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7161 > set_src_cost (temp2
, mode
, optimize_this_for_speed_p
))
7163 else if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7164 > set_src_cost (temp
, mode
, optimize_this_for_speed_p
))
7170 /* We can optimize some special cases of ZERO_EXTEND. */
7171 if (GET_CODE (x
) == ZERO_EXTEND
)
7173 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7174 know that the last value didn't have any inappropriate bits
7176 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7177 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7178 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7179 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
7180 & ~GET_MODE_MASK (inner_mode
)) == 0)
7181 return XEXP (XEXP (x
, 0), 0);
7183 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7184 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7185 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7186 && subreg_lowpart_p (XEXP (x
, 0))
7187 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7188 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
7189 & ~GET_MODE_MASK (inner_mode
)) == 0)
7190 return SUBREG_REG (XEXP (x
, 0));
7192 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7193 is a comparison and STORE_FLAG_VALUE permits. This is like
7194 the first case, but it works even when GET_MODE (x) is larger
7195 than HOST_WIDE_INT. */
7196 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7197 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7198 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
7199 && GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
7200 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (inner_mode
)) == 0)
7201 return XEXP (XEXP (x
, 0), 0);
7203 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7204 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7205 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7206 && subreg_lowpart_p (XEXP (x
, 0))
7207 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
7208 && GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
7209 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (inner_mode
)) == 0)
7210 return SUBREG_REG (XEXP (x
, 0));
7214 /* If we reach here, we want to return a pair of shifts. The inner
7215 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7216 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7217 logical depending on the value of UNSIGNEDP.
7219 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7220 converted into an AND of a shift.
7222 We must check for the case where the left shift would have a negative
7223 count. This can happen in a case like (x >> 31) & 255 on machines
7224 that can't shift by a constant. On those machines, we would first
7225 combine the shift with the AND to produce a variable-position
7226 extraction. Then the constant of 31 would be substituted in
7227 to produce such a position. */
7229 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
7230 if (modewidth
>= pos
+ len
)
7232 machine_mode mode
= GET_MODE (x
);
7233 tem
= gen_lowpart (mode
, XEXP (x
, 0));
7234 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
7236 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
7237 tem
, modewidth
- pos
- len
);
7238 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
7239 mode
, tem
, modewidth
- len
);
7241 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
7242 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
7243 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7246 (HOST_WIDE_INT_1U
<< len
) - 1);
7248 /* Any other cases we can't handle. */
7251 /* If we couldn't do this for some reason, return the original
7253 if (GET_CODE (tem
) == CLOBBER
)
7259 /* X is a SET which contains an assignment of one object into
7260 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7261 or certain SUBREGS). If possible, convert it into a series of
7264 We half-heartedly support variable positions, but do not at all
7265 support variable lengths. */
7268 expand_field_assignment (const_rtx x
)
7271 rtx pos
; /* Always counts from low bit. */
7273 rtx mask
, cleared
, masked
;
7274 scalar_int_mode compute_mode
;
7276 /* Loop until we find something we can't simplify. */
7279 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
7280 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
7282 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
7283 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
7284 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
7286 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
7287 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
7289 inner
= XEXP (SET_DEST (x
), 0);
7290 len
= INTVAL (XEXP (SET_DEST (x
), 1));
7291 pos
= XEXP (SET_DEST (x
), 2);
7293 /* A constant position should stay within the width of INNER. */
7294 if (CONST_INT_P (pos
)
7295 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
7298 if (BITS_BIG_ENDIAN
)
7300 if (CONST_INT_P (pos
))
7301 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
7303 else if (GET_CODE (pos
) == MINUS
7304 && CONST_INT_P (XEXP (pos
, 1))
7305 && (INTVAL (XEXP (pos
, 1))
7306 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
7307 /* If position is ADJUST - X, new position is X. */
7308 pos
= XEXP (pos
, 0);
7311 HOST_WIDE_INT prec
= GET_MODE_PRECISION (GET_MODE (inner
));
7312 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
7313 gen_int_mode (prec
- len
,
7320 /* A SUBREG between two modes that occupy the same numbers of words
7321 can be done by moving the SUBREG to the source. */
7322 else if (GET_CODE (SET_DEST (x
)) == SUBREG
7323 /* We need SUBREGs to compute nonzero_bits properly. */
7324 && nonzero_sign_valid
7325 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
7326 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
7327 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
7328 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
7330 x
= gen_rtx_SET (SUBREG_REG (SET_DEST (x
)),
7332 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
7339 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7340 inner
= SUBREG_REG (inner
);
7342 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7343 if (!is_a
<scalar_int_mode
> (GET_MODE (inner
), &compute_mode
))
7345 /* Don't do anything for vector or complex integral types. */
7346 if (! FLOAT_MODE_P (GET_MODE (inner
)))
7349 /* Try to find an integral mode to pun with. */
7350 if (!int_mode_for_size (GET_MODE_BITSIZE (GET_MODE (inner
)), 0)
7351 .exists (&compute_mode
))
7354 inner
= gen_lowpart (compute_mode
, inner
);
7357 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7358 if (len
>= HOST_BITS_PER_WIDE_INT
)
7361 /* Don't try to compute in too wide unsupported modes. */
7362 if (!targetm
.scalar_mode_supported_p (compute_mode
))
7365 /* Now compute the equivalent expression. Make a copy of INNER
7366 for the SET_DEST in case it is a MEM into which we will substitute;
7367 we don't want shared RTL in that case. */
7368 mask
= gen_int_mode ((HOST_WIDE_INT_1U
<< len
) - 1,
7370 cleared
= simplify_gen_binary (AND
, compute_mode
,
7371 simplify_gen_unary (NOT
, compute_mode
,
7372 simplify_gen_binary (ASHIFT
,
7377 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7378 simplify_gen_binary (
7380 gen_lowpart (compute_mode
, SET_SRC (x
)),
7384 x
= gen_rtx_SET (copy_rtx (inner
),
7385 simplify_gen_binary (IOR
, compute_mode
,
7392 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7393 it is an RTX that represents the (variable) starting position; otherwise,
7394 POS is the (constant) starting bit position. Both are counted from the LSB.
7396 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7398 IN_DEST is nonzero if this is a reference in the destination of a SET.
7399 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7400 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7403 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7404 ZERO_EXTRACT should be built even for bits starting at bit 0.
7406 MODE is the desired mode of the result (if IN_DEST == 0).
7408 The result is an RTX for the extraction or NULL_RTX if the target
7412 make_extraction (machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7413 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7414 int in_dest
, int in_compare
)
7416 /* This mode describes the size of the storage area
7417 to fetch the overall value from. Within that, we
7418 ignore the POS lowest bits, etc. */
7419 machine_mode is_mode
= GET_MODE (inner
);
7420 machine_mode inner_mode
;
7421 machine_mode wanted_inner_mode
;
7422 machine_mode wanted_inner_reg_mode
= word_mode
;
7423 machine_mode pos_mode
= word_mode
;
7424 machine_mode extraction_mode
= word_mode
;
7426 rtx orig_pos_rtx
= pos_rtx
;
7427 HOST_WIDE_INT orig_pos
;
7429 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7430 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7432 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7434 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7435 consider just the QI as the memory to extract from.
7436 The subreg adds or removes high bits; its mode is
7437 irrelevant to the meaning of this extraction,
7438 since POS and LEN count from the lsb. */
7439 if (MEM_P (SUBREG_REG (inner
)))
7440 is_mode
= GET_MODE (SUBREG_REG (inner
));
7441 inner
= SUBREG_REG (inner
);
7443 else if (GET_CODE (inner
) == ASHIFT
7444 && CONST_INT_P (XEXP (inner
, 1))
7445 && pos_rtx
== 0 && pos
== 0
7446 && len
> UINTVAL (XEXP (inner
, 1)))
7448 /* We're extracting the least significant bits of an rtx
7449 (ashift X (const_int C)), where LEN > C. Extract the
7450 least significant (LEN - C) bits of X, giving an rtx
7451 whose mode is MODE, then shift it left C times. */
7452 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7453 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7454 unsignedp
, in_dest
, in_compare
);
7456 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7458 else if (GET_CODE (inner
) == TRUNCATE
)
7459 inner
= XEXP (inner
, 0);
7461 inner_mode
= GET_MODE (inner
);
7463 /* See if this can be done without an extraction. We never can if the
7464 width of the field is not the same as that of some integer mode. For
7465 registers, we can only avoid the extraction if the position is at the
7466 low-order bit and this is either not in the destination or we have the
7467 appropriate STRICT_LOW_PART operation available.
7469 For MEM, we can avoid an extract if the field starts on an appropriate
7470 boundary and we can change the mode of the memory reference. */
7472 scalar_int_mode tmode
;
7473 if (int_mode_for_size (len
, 1).exists (&tmode
)
7474 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7476 && (pos
== 0 || REG_P (inner
))
7477 && (inner_mode
== tmode
7479 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7480 || reg_truncated_to_mode (tmode
, inner
))
7483 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7484 || (MEM_P (inner
) && pos_rtx
== 0
7486 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7487 : BITS_PER_UNIT
)) == 0
7488 /* We can't do this if we are widening INNER_MODE (it
7489 may not be aligned, for one thing). */
7490 && !paradoxical_subreg_p (tmode
, inner_mode
)
7491 && (inner_mode
== tmode
7492 || (! mode_dependent_address_p (XEXP (inner
, 0),
7493 MEM_ADDR_SPACE (inner
))
7494 && ! MEM_VOLATILE_P (inner
))))))
7496 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7497 field. If the original and current mode are the same, we need not
7498 adjust the offset. Otherwise, we do if bytes big endian.
7500 If INNER is not a MEM, get a piece consisting of just the field
7501 of interest (in this case POS % BITS_PER_WORD must be 0). */
7505 HOST_WIDE_INT offset
;
7507 /* POS counts from lsb, but make OFFSET count in memory order. */
7508 if (BYTES_BIG_ENDIAN
)
7509 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7511 offset
= pos
/ BITS_PER_UNIT
;
7513 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7515 else if (REG_P (inner
))
7517 if (tmode
!= inner_mode
)
7519 /* We can't call gen_lowpart in a DEST since we
7520 always want a SUBREG (see below) and it would sometimes
7521 return a new hard register. */
7525 = subreg_offset_from_lsb (tmode
, inner_mode
, pos
);
7527 /* Avoid creating invalid subregs, for example when
7528 simplifying (x>>32)&255. */
7529 if (!validate_subreg (tmode
, inner_mode
, inner
, offset
))
7532 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, offset
);
7535 new_rtx
= gen_lowpart (tmode
, inner
);
7541 new_rtx
= force_to_mode (inner
, tmode
,
7542 len
>= HOST_BITS_PER_WIDE_INT
7544 : (HOST_WIDE_INT_1U
<< len
) - 1, 0);
7546 /* If this extraction is going into the destination of a SET,
7547 make a STRICT_LOW_PART unless we made a MEM. */
7550 return (MEM_P (new_rtx
) ? new_rtx
7551 : (GET_CODE (new_rtx
) != SUBREG
7552 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7553 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7558 if (CONST_SCALAR_INT_P (new_rtx
))
7559 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7560 mode
, new_rtx
, tmode
);
7562 /* If we know that no extraneous bits are set, and that the high
7563 bit is not set, convert the extraction to the cheaper of
7564 sign and zero extension, that are equivalent in these cases. */
7565 if (flag_expensive_optimizations
7566 && (HWI_COMPUTABLE_MODE_P (tmode
)
7567 && ((nonzero_bits (new_rtx
, tmode
)
7568 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7571 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7572 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7574 /* Prefer ZERO_EXTENSION, since it gives more information to
7576 if (set_src_cost (temp
, mode
, optimize_this_for_speed_p
)
7577 <= set_src_cost (temp1
, mode
, optimize_this_for_speed_p
))
7582 /* Otherwise, sign- or zero-extend unless we already are in the
7585 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7589 /* Unless this is a COMPARE or we have a funny memory reference,
7590 don't do anything with zero-extending field extracts starting at
7591 the low-order bit since they are simple AND operations. */
7592 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7593 && ! in_compare
&& unsignedp
)
7596 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7597 if the position is not a constant and the length is not 1. In all
7598 other cases, we would only be going outside our object in cases when
7599 an original shift would have been undefined. */
7601 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7602 || (pos_rtx
!= 0 && len
!= 1)))
7605 enum extraction_pattern pattern
= (in_dest
? EP_insv
7606 : unsignedp
? EP_extzv
: EP_extv
);
7608 /* If INNER is not from memory, we want it to have the mode of a register
7609 extraction pattern's structure operand, or word_mode if there is no
7610 such pattern. The same applies to extraction_mode and pos_mode
7611 and their respective operands.
7613 For memory, assume that the desired extraction_mode and pos_mode
7614 are the same as for a register operation, since at present we don't
7615 have named patterns for aligned memory structures. */
7616 struct extraction_insn insn
;
7617 if (get_best_reg_extraction_insn (&insn
, pattern
,
7618 GET_MODE_BITSIZE (inner_mode
), mode
))
7620 wanted_inner_reg_mode
= insn
.struct_mode
;
7621 pos_mode
= insn
.pos_mode
;
7622 extraction_mode
= insn
.field_mode
;
7625 /* Never narrow an object, since that might not be safe. */
7627 if (mode
!= VOIDmode
7628 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7629 extraction_mode
= mode
;
7632 wanted_inner_mode
= wanted_inner_reg_mode
;
7635 /* Be careful not to go beyond the extracted object and maintain the
7636 natural alignment of the memory. */
7637 wanted_inner_mode
= smallest_int_mode_for_size (len
);
7638 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7639 > GET_MODE_BITSIZE (wanted_inner_mode
))
7640 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
).require ();
7645 if (BITS_BIG_ENDIAN
)
7647 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7648 BITS_BIG_ENDIAN style. If position is constant, compute new
7649 position. Otherwise, build subtraction.
7650 Note that POS is relative to the mode of the original argument.
7651 If it's a MEM we need to recompute POS relative to that.
7652 However, if we're extracting from (or inserting into) a register,
7653 we want to recompute POS relative to wanted_inner_mode. */
7654 int width
= (MEM_P (inner
)
7655 ? GET_MODE_BITSIZE (is_mode
)
7656 : GET_MODE_BITSIZE (wanted_inner_mode
));
7659 pos
= width
- len
- pos
;
7662 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7663 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7665 /* POS may be less than 0 now, but we check for that below.
7666 Note that it can only be less than 0 if !MEM_P (inner). */
7669 /* If INNER has a wider mode, and this is a constant extraction, try to
7670 make it smaller and adjust the byte to point to the byte containing
7672 if (wanted_inner_mode
!= VOIDmode
7673 && inner_mode
!= wanted_inner_mode
7675 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7677 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7678 && ! MEM_VOLATILE_P (inner
))
7682 /* The computations below will be correct if the machine is big
7683 endian in both bits and bytes or little endian in bits and bytes.
7684 If it is mixed, we must adjust. */
7686 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7687 adjust OFFSET to compensate. */
7688 if (BYTES_BIG_ENDIAN
7689 && paradoxical_subreg_p (is_mode
, inner_mode
))
7690 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7692 /* We can now move to the desired byte. */
7693 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7694 * GET_MODE_SIZE (wanted_inner_mode
);
7695 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7697 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7698 && is_mode
!= wanted_inner_mode
)
7699 offset
= (GET_MODE_SIZE (is_mode
)
7700 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7702 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7705 /* If INNER is not memory, get it into the proper mode. If we are changing
7706 its mode, POS must be a constant and smaller than the size of the new
7708 else if (!MEM_P (inner
))
7710 /* On the LHS, don't create paradoxical subregs implicitely truncating
7711 the register unless TRULY_NOOP_TRUNCATION. */
7713 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7717 if (GET_MODE (inner
) != wanted_inner_mode
7719 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7725 inner
= force_to_mode (inner
, wanted_inner_mode
,
7727 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7729 : (((HOST_WIDE_INT_1U
<< len
) - 1)
7734 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7735 have to zero extend. Otherwise, we can just use a SUBREG. */
7737 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7739 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7740 GET_MODE (pos_rtx
));
7742 /* If we know that no extraneous bits are set, and that the high
7743 bit is not set, convert extraction to cheaper one - either
7744 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7746 if (flag_expensive_optimizations
7747 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7748 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7749 & ~(((unsigned HOST_WIDE_INT
)
7750 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7754 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7755 GET_MODE (pos_rtx
));
7757 /* Prefer ZERO_EXTENSION, since it gives more information to
7759 if (set_src_cost (temp1
, pos_mode
, optimize_this_for_speed_p
)
7760 < set_src_cost (temp
, pos_mode
, optimize_this_for_speed_p
))
7766 /* Make POS_RTX unless we already have it and it is correct. If we don't
7767 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7769 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7770 pos_rtx
= orig_pos_rtx
;
7772 else if (pos_rtx
== 0)
7773 pos_rtx
= GEN_INT (pos
);
7775 /* Make the required operation. See if we can use existing rtx. */
7776 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7777 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7779 new_rtx
= gen_lowpart (mode
, new_rtx
);
7784 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7785 with any other operations in X. Return X without that shift if so. */
7788 extract_left_shift (rtx x
, int count
)
7790 enum rtx_code code
= GET_CODE (x
);
7791 machine_mode mode
= GET_MODE (x
);
7797 /* This is the shift itself. If it is wide enough, we will return
7798 either the value being shifted if the shift count is equal to
7799 COUNT or a shift for the difference. */
7800 if (CONST_INT_P (XEXP (x
, 1))
7801 && INTVAL (XEXP (x
, 1)) >= count
)
7802 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7803 INTVAL (XEXP (x
, 1)) - count
);
7807 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7808 return simplify_gen_unary (code
, mode
, tem
, mode
);
7812 case PLUS
: case IOR
: case XOR
: case AND
:
7813 /* If we can safely shift this constant and we find the inner shift,
7814 make a new operation. */
7815 if (CONST_INT_P (XEXP (x
, 1))
7816 && (UINTVAL (XEXP (x
, 1))
7817 & (((HOST_WIDE_INT_1U
<< count
)) - 1)) == 0
7818 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7820 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
7821 return simplify_gen_binary (code
, mode
, tem
,
7822 gen_int_mode (val
, mode
));
7833 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7834 level of the expression and MODE is its mode. IN_CODE is as for
7835 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7836 that should be used when recursing on operands of *X_PTR.
7838 There are two possible actions:
7840 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7841 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7843 - Return a new rtx, which the caller returns directly. */
7846 make_compound_operation_int (machine_mode mode
, rtx
*x_ptr
,
7847 enum rtx_code in_code
,
7848 enum rtx_code
*next_code_ptr
)
7851 enum rtx_code next_code
= *next_code_ptr
;
7852 enum rtx_code code
= GET_CODE (x
);
7853 int mode_width
= GET_MODE_PRECISION (mode
);
7858 scalar_int_mode inner_mode
;
7859 bool equality_comparison
= false;
7863 equality_comparison
= true;
7867 /* Process depending on the code of this operation. If NEW is set
7868 nonzero, it will be returned. */
7873 /* Convert shifts by constants into multiplications if inside
7875 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7876 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7877 && INTVAL (XEXP (x
, 1)) >= 0)
7879 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7880 HOST_WIDE_INT multval
= HOST_WIDE_INT_1
<< count
;
7882 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7883 if (GET_CODE (new_rtx
) == NEG
)
7885 new_rtx
= XEXP (new_rtx
, 0);
7888 multval
= trunc_int_for_mode (multval
, mode
);
7889 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
7896 lhs
= make_compound_operation (lhs
, next_code
);
7897 rhs
= make_compound_operation (rhs
, next_code
);
7898 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
)
7900 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7902 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7904 else if (GET_CODE (lhs
) == MULT
7905 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7907 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7908 simplify_gen_unary (NEG
, mode
,
7911 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7915 SUBST (XEXP (x
, 0), lhs
);
7916 SUBST (XEXP (x
, 1), rhs
);
7918 maybe_swap_commutative_operands (x
);
7924 lhs
= make_compound_operation (lhs
, next_code
);
7925 rhs
= make_compound_operation (rhs
, next_code
);
7926 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
)
7928 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7930 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7932 else if (GET_CODE (rhs
) == MULT
7933 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7935 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7936 simplify_gen_unary (NEG
, mode
,
7939 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7943 SUBST (XEXP (x
, 0), lhs
);
7944 SUBST (XEXP (x
, 1), rhs
);
7949 /* If the second operand is not a constant, we can't do anything
7951 if (!CONST_INT_P (XEXP (x
, 1)))
7954 /* If the constant is a power of two minus one and the first operand
7955 is a logical right shift, make an extraction. */
7956 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7957 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7959 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7960 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7961 0, in_code
== COMPARE
);
7964 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7965 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7966 && subreg_lowpart_p (XEXP (x
, 0))
7967 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (XEXP (x
, 0))),
7969 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7970 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7972 rtx inner_x0
= SUBREG_REG (XEXP (x
, 0));
7973 new_rtx
= make_compound_operation (XEXP (inner_x0
, 0), next_code
);
7974 new_rtx
= make_extraction (inner_mode
, new_rtx
, 0,
7976 i
, 1, 0, in_code
== COMPARE
);
7978 /* If we narrowed the mode when dropping the subreg, then we lose. */
7979 if (GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (mode
))
7982 /* If that didn't give anything, see if the AND simplifies on
7984 if (!new_rtx
&& i
>= 0)
7986 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7987 new_rtx
= make_extraction (mode
, new_rtx
, 0, NULL_RTX
, i
, 1,
7988 0, in_code
== COMPARE
);
7991 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7992 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7993 || GET_CODE (XEXP (x
, 0)) == IOR
)
7994 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7995 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7996 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7998 /* Apply the distributive law, and then try to make extractions. */
7999 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
8000 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
8002 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
8004 new_rtx
= make_compound_operation (new_rtx
, in_code
);
8007 /* If we are have (and (rotate X C) M) and C is larger than the number
8008 of bits in M, this is an extraction. */
8010 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
8011 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8012 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
8013 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
8015 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
8016 new_rtx
= make_extraction (mode
, new_rtx
,
8017 (GET_MODE_PRECISION (mode
)
8018 - INTVAL (XEXP (XEXP (x
, 0), 1))),
8019 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
8022 /* On machines without logical shifts, if the operand of the AND is
8023 a logical shift and our mask turns off all the propagated sign
8024 bits, we can replace the logical shift with an arithmetic shift. */
8025 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8026 && !have_insn_for (LSHIFTRT
, mode
)
8027 && have_insn_for (ASHIFTRT
, mode
)
8028 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8029 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8030 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8031 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8033 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
8035 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
8036 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
8038 gen_rtx_ASHIFTRT (mode
,
8039 make_compound_operation
8040 (XEXP (XEXP (x
, 0), 0), next_code
),
8041 XEXP (XEXP (x
, 0), 1)));
8044 /* If the constant is one less than a power of two, this might be
8045 representable by an extraction even if no shift is present.
8046 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8047 we are in a COMPARE. */
8048 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8049 new_rtx
= make_extraction (mode
,
8050 make_compound_operation (XEXP (x
, 0),
8052 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
8054 /* If we are in a comparison and this is an AND with a power of two,
8055 convert this into the appropriate bit extract. */
8056 else if (in_code
== COMPARE
8057 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
8058 && (equality_comparison
|| i
< GET_MODE_PRECISION (mode
) - 1))
8059 new_rtx
= make_extraction (mode
,
8060 make_compound_operation (XEXP (x
, 0),
8062 i
, NULL_RTX
, 1, 1, 0, 1);
8064 /* If the one operand is a paradoxical subreg of a register or memory and
8065 the constant (limited to the smaller mode) has only zero bits where
8066 the sub expression has known zero bits, this can be expressed as
8068 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
)
8072 sub
= XEXP (XEXP (x
, 0), 0);
8073 machine_mode sub_mode
= GET_MODE (sub
);
8074 if ((REG_P (sub
) || MEM_P (sub
))
8075 && GET_MODE_PRECISION (sub_mode
) < mode_width
)
8077 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (sub_mode
);
8078 unsigned HOST_WIDE_INT mask
;
8080 /* original AND constant with all the known zero bits set */
8081 mask
= UINTVAL (XEXP (x
, 1)) | (~nonzero_bits (sub
, sub_mode
));
8082 if ((mask
& mode_mask
) == mode_mask
)
8084 new_rtx
= make_compound_operation (sub
, next_code
);
8085 new_rtx
= make_extraction (mode
, new_rtx
, 0, 0,
8086 GET_MODE_PRECISION (sub_mode
),
8087 1, 0, in_code
== COMPARE
);
8095 /* If the sign bit is known to be zero, replace this with an
8096 arithmetic shift. */
8097 if (have_insn_for (ASHIFTRT
, mode
)
8098 && ! have_insn_for (LSHIFTRT
, mode
)
8099 && mode_width
<= HOST_BITS_PER_WIDE_INT
8100 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
8102 new_rtx
= gen_rtx_ASHIFTRT (mode
,
8103 make_compound_operation (XEXP (x
, 0),
8115 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8116 this is a SIGN_EXTRACT. */
8117 if (CONST_INT_P (rhs
)
8118 && GET_CODE (lhs
) == ASHIFT
8119 && CONST_INT_P (XEXP (lhs
, 1))
8120 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
8121 && INTVAL (XEXP (lhs
, 1)) >= 0
8122 && INTVAL (rhs
) < mode_width
)
8124 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
8125 new_rtx
= make_extraction (mode
, new_rtx
,
8126 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
8127 NULL_RTX
, mode_width
- INTVAL (rhs
),
8128 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8132 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8133 If so, try to merge the shifts into a SIGN_EXTEND. We could
8134 also do this for some cases of SIGN_EXTRACT, but it doesn't
8135 seem worth the effort; the case checked for occurs on Alpha. */
8138 && ! (GET_CODE (lhs
) == SUBREG
8139 && (OBJECT_P (SUBREG_REG (lhs
))))
8140 && CONST_INT_P (rhs
)
8141 && INTVAL (rhs
) >= 0
8142 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
8143 && INTVAL (rhs
) < mode_width
8144 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
8145 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
8146 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
8147 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8152 /* Call ourselves recursively on the inner expression. If we are
8153 narrowing the object and it has a different RTL code from
8154 what it originally did, do this SUBREG as a force_to_mode. */
8156 rtx inner
= SUBREG_REG (x
), simplified
;
8157 enum rtx_code subreg_code
= in_code
;
8159 /* If the SUBREG is masking of a logical right shift,
8160 make an extraction. */
8161 if (GET_CODE (inner
) == LSHIFTRT
8162 && is_a
<scalar_int_mode
> (GET_MODE (inner
), &inner_mode
)
8163 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (inner_mode
)
8164 && CONST_INT_P (XEXP (inner
, 1))
8165 && UINTVAL (XEXP (inner
, 1)) < GET_MODE_PRECISION (inner_mode
)
8166 && subreg_lowpart_p (x
))
8168 new_rtx
= make_compound_operation (XEXP (inner
, 0), next_code
);
8169 int width
= GET_MODE_PRECISION (inner_mode
)
8170 - INTVAL (XEXP (inner
, 1));
8171 if (width
> mode_width
)
8173 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (inner
, 1),
8174 width
, 1, 0, in_code
== COMPARE
);
8178 /* If in_code is COMPARE, it isn't always safe to pass it through
8179 to the recursive make_compound_operation call. */
8180 if (subreg_code
== COMPARE
8181 && (!subreg_lowpart_p (x
)
8182 || GET_CODE (inner
) == SUBREG
8183 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8184 is (const_int 0), rather than
8185 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8186 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8187 for non-equality comparisons against 0 is not equivalent
8188 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8189 || (GET_CODE (inner
) == AND
8190 && CONST_INT_P (XEXP (inner
, 1))
8191 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8192 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
8193 >= GET_MODE_BITSIZE (mode
) - 1)))
8196 tem
= make_compound_operation (inner
, subreg_code
);
8199 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
8203 if (GET_CODE (tem
) != GET_CODE (inner
)
8204 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8205 && subreg_lowpart_p (x
))
8208 = force_to_mode (tem
, mode
, HOST_WIDE_INT_M1U
, 0);
8210 /* If we have something other than a SUBREG, we might have
8211 done an expansion, so rerun ourselves. */
8212 if (GET_CODE (newer
) != SUBREG
)
8213 newer
= make_compound_operation (newer
, in_code
);
8215 /* force_to_mode can expand compounds. If it just re-expanded the
8216 compound, use gen_lowpart to convert to the desired mode. */
8217 if (rtx_equal_p (newer
, x
)
8218 /* Likewise if it re-expanded the compound only partially.
8219 This happens for SUBREG of ZERO_EXTRACT if they extract
8220 the same number of bits. */
8221 || (GET_CODE (newer
) == SUBREG
8222 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
8223 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
8224 && GET_CODE (inner
) == AND
8225 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
8226 return gen_lowpart (GET_MODE (x
), tem
);
8241 *x_ptr
= gen_lowpart (mode
, new_rtx
);
8242 *next_code_ptr
= next_code
;
8246 /* Look at the expression rooted at X. Look for expressions
8247 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8248 Form these expressions.
8250 Return the new rtx, usually just X.
8252 Also, for machines like the VAX that don't have logical shift insns,
8253 try to convert logical to arithmetic shift operations in cases where
8254 they are equivalent. This undoes the canonicalizations to logical
8255 shifts done elsewhere.
8257 We try, as much as possible, to re-use rtl expressions to save memory.
8259 IN_CODE says what kind of expression we are processing. Normally, it is
8260 SET. In a memory address it is MEM. When processing the arguments of
8261 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8262 precisely it is an equality comparison against zero. */
8265 make_compound_operation (rtx x
, enum rtx_code in_code
)
8267 enum rtx_code code
= GET_CODE (x
);
8270 enum rtx_code next_code
;
8273 /* Select the code to be used in recursive calls. Once we are inside an
8274 address, we stay there. If we have a comparison, set to COMPARE,
8275 but once inside, go back to our default of SET. */
8277 next_code
= (code
== MEM
? MEM
8278 : ((code
== COMPARE
|| COMPARISON_P (x
))
8279 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
8280 : in_code
== COMPARE
|| in_code
== EQ
? SET
: in_code
);
8282 scalar_int_mode mode
;
8283 if (is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
))
8285 rtx new_rtx
= make_compound_operation_int (mode
, &x
, in_code
,
8289 code
= GET_CODE (x
);
8292 /* Now recursively process each operand of this operation. We need to
8293 handle ZERO_EXTEND specially so that we don't lose track of the
8295 if (code
== ZERO_EXTEND
)
8297 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8298 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8299 new_rtx
, GET_MODE (XEXP (x
, 0)));
8302 SUBST (XEXP (x
, 0), new_rtx
);
8306 fmt
= GET_RTX_FORMAT (code
);
8307 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
8310 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
8311 SUBST (XEXP (x
, i
), new_rtx
);
8313 else if (fmt
[i
] == 'E')
8314 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8316 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
8317 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
8320 maybe_swap_commutative_operands (x
);
8324 /* Given M see if it is a value that would select a field of bits
8325 within an item, but not the entire word. Return -1 if not.
8326 Otherwise, return the starting position of the field, where 0 is the
8329 *PLEN is set to the length of the field. */
8332 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
8334 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8335 int pos
= m
? ctz_hwi (m
) : -1;
8339 /* Now shift off the low-order zero bits and see if we have a
8340 power of two minus 1. */
8341 len
= exact_log2 ((m
>> pos
) + 1);
8350 /* If X refers to a register that equals REG in value, replace these
8351 references with REG. */
8353 canon_reg_for_combine (rtx x
, rtx reg
)
8360 enum rtx_code code
= GET_CODE (x
);
8361 switch (GET_RTX_CLASS (code
))
8364 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8365 if (op0
!= XEXP (x
, 0))
8366 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
8371 case RTX_COMM_ARITH
:
8372 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8373 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8374 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8375 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
8379 case RTX_COMM_COMPARE
:
8380 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8381 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8382 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8383 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
8384 GET_MODE (op0
), op0
, op1
);
8388 case RTX_BITFIELD_OPS
:
8389 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8390 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8391 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
8392 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
8393 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
8394 GET_MODE (op0
), op0
, op1
, op2
);
8400 if (rtx_equal_p (get_last_value (reg
), x
)
8401 || rtx_equal_p (reg
, get_last_value (x
)))
8410 fmt
= GET_RTX_FORMAT (code
);
8412 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8415 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
8416 if (op
!= XEXP (x
, i
))
8426 else if (fmt
[i
] == 'E')
8429 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8431 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8432 if (op
!= XVECEXP (x
, i
, j
))
8439 XVECEXP (x
, i
, j
) = op
;
8450 /* Return X converted to MODE. If the value is already truncated to
8451 MODE we can just return a subreg even though in the general case we
8452 would need an explicit truncation. */
8455 gen_lowpart_or_truncate (machine_mode mode
, rtx x
)
8457 if (!CONST_INT_P (x
)
8458 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
8459 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8460 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8462 /* Bit-cast X into an integer mode. */
8463 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8464 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)).require (), x
);
8465 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
).require (),
8469 return gen_lowpart (mode
, x
);
8472 /* See if X can be simplified knowing that we will only refer to it in
8473 MODE and will only refer to those bits that are nonzero in MASK.
8474 If other bits are being computed or if masking operations are done
8475 that select a superset of the bits in MASK, they can sometimes be
8478 Return a possibly simplified expression, but always convert X to
8479 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8481 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8482 are all off in X. This is used when X will be complemented, by either
8483 NOT, NEG, or XOR. */
8486 force_to_mode (rtx x
, machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8489 enum rtx_code code
= GET_CODE (x
);
8490 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8491 machine_mode op_mode
;
8492 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
8495 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8496 code below will do the wrong thing since the mode of such an
8497 expression is VOIDmode.
8499 Also do nothing if X is a CLOBBER; this can happen if X was
8500 the return value from a call to gen_lowpart. */
8501 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8504 /* We want to perform the operation in its present mode unless we know
8505 that the operation is valid in MODE, in which case we do the operation
8507 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8508 && have_insn_for (code
, mode
))
8509 ? mode
: GET_MODE (x
));
8511 /* It is not valid to do a right-shift in a narrower mode
8512 than the one it came in with. */
8513 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8514 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
8515 op_mode
= GET_MODE (x
);
8517 /* Truncate MASK to fit OP_MODE. */
8519 mask
&= GET_MODE_MASK (op_mode
);
8521 /* When we have an arithmetic operation, or a shift whose count we
8522 do not know, we need to assume that all bits up to the highest-order
8523 bit in MASK will be needed. This is how we form such a mask. */
8524 if (mask
& (HOST_WIDE_INT_1U
<< (HOST_BITS_PER_WIDE_INT
- 1)))
8525 fuller_mask
= HOST_WIDE_INT_M1U
;
8527 fuller_mask
= ((HOST_WIDE_INT_1U
<< (floor_log2 (mask
) + 1))
8530 /* Determine what bits of X are guaranteed to be (non)zero. */
8531 nonzero
= nonzero_bits (x
, mode
);
8533 /* If none of the bits in X are needed, return a zero. */
8534 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8537 /* If X is a CONST_INT, return a new one. Do this here since the
8538 test below will fail. */
8539 if (CONST_INT_P (x
))
8541 if (SCALAR_INT_MODE_P (mode
))
8542 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8545 x
= GEN_INT (INTVAL (x
) & mask
);
8546 return gen_lowpart_common (mode
, x
);
8550 /* If X is narrower than MODE and we want all the bits in X's mode, just
8551 get X in the proper mode. */
8552 if (paradoxical_subreg_p (mode
, GET_MODE (x
))
8553 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8554 return gen_lowpart (mode
, x
);
8556 /* We can ignore the effect of a SUBREG if it narrows the mode or
8557 if the constant masks to zero all the bits the mode doesn't have. */
8558 if (GET_CODE (x
) == SUBREG
8559 && subreg_lowpart_p (x
)
8560 && ((GET_MODE_SIZE (GET_MODE (x
))
8561 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8563 & GET_MODE_MASK (GET_MODE (x
))
8564 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8565 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8567 /* The arithmetic simplifications here only work for scalar integer modes. */
8568 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8569 return gen_lowpart_or_truncate (mode
, x
);
8574 /* If X is a (clobber (const_int)), return it since we know we are
8575 generating something that won't match. */
8582 x
= expand_compound_operation (x
);
8583 if (GET_CODE (x
) != code
)
8584 return force_to_mode (x
, mode
, mask
, next_select
);
8588 /* Similarly for a truncate. */
8589 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8592 /* If this is an AND with a constant, convert it into an AND
8593 whose constant is the AND of that constant with MASK. If it
8594 remains an AND of MASK, delete it since it is redundant. */
8596 if (CONST_INT_P (XEXP (x
, 1)))
8598 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8599 mask
& INTVAL (XEXP (x
, 1)));
8601 /* If X is still an AND, see if it is an AND with a mask that
8602 is just some low-order bits. If so, and it is MASK, we don't
8605 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8606 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8610 /* If it remains an AND, try making another AND with the bits
8611 in the mode mask that aren't in MASK turned on. If the
8612 constant in the AND is wide enough, this might make a
8613 cheaper constant. */
8615 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8616 && GET_MODE_MASK (GET_MODE (x
)) != mask
8617 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8619 unsigned HOST_WIDE_INT cval
8620 = UINTVAL (XEXP (x
, 1))
8621 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8624 y
= simplify_gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0),
8625 gen_int_mode (cval
, GET_MODE (x
)));
8626 if (set_src_cost (y
, GET_MODE (x
), optimize_this_for_speed_p
)
8627 < set_src_cost (x
, GET_MODE (x
), optimize_this_for_speed_p
))
8637 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8638 low-order bits (as in an alignment operation) and FOO is already
8639 aligned to that boundary, mask C1 to that boundary as well.
8640 This may eliminate that PLUS and, later, the AND. */
8643 unsigned int width
= GET_MODE_PRECISION (mode
);
8644 unsigned HOST_WIDE_INT smask
= mask
;
8646 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8647 number, sign extend it. */
8649 if (width
< HOST_BITS_PER_WIDE_INT
8650 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8651 smask
|= HOST_WIDE_INT_M1U
<< width
;
8653 if (CONST_INT_P (XEXP (x
, 1))
8654 && pow2p_hwi (- smask
)
8655 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8656 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8657 return force_to_mode (plus_constant (GET_MODE (x
), XEXP (x
, 0),
8658 (INTVAL (XEXP (x
, 1)) & smask
)),
8659 mode
, smask
, next_select
);
8665 /* Substituting into the operands of a widening MULT is not likely to
8666 create RTL matching a machine insn. */
8668 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
8669 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
8670 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
8671 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
8672 && REG_P (XEXP (XEXP (x
, 0), 0))
8673 && REG_P (XEXP (XEXP (x
, 1), 0)))
8674 return gen_lowpart_or_truncate (mode
, x
);
8676 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8677 most significant bit in MASK since carries from those bits will
8678 affect the bits we are interested in. */
8683 /* If X is (minus C Y) where C's least set bit is larger than any bit
8684 in the mask, then we may replace with (neg Y). */
8685 if (CONST_INT_P (XEXP (x
, 0))
8686 && least_bit_hwi (UINTVAL (XEXP (x
, 0))) > mask
)
8688 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8690 return force_to_mode (x
, mode
, mask
, next_select
);
8693 /* Similarly, if C contains every bit in the fuller_mask, then we may
8694 replace with (not Y). */
8695 if (CONST_INT_P (XEXP (x
, 0))
8696 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8698 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8699 XEXP (x
, 1), GET_MODE (x
));
8700 return force_to_mode (x
, mode
, mask
, next_select
);
8708 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8709 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8710 operation which may be a bitfield extraction. Ensure that the
8711 constant we form is not wider than the mode of X. */
8713 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8714 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8715 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8716 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8717 && CONST_INT_P (XEXP (x
, 1))
8718 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8719 + floor_log2 (INTVAL (XEXP (x
, 1))))
8720 < GET_MODE_PRECISION (GET_MODE (x
)))
8721 && (UINTVAL (XEXP (x
, 1))
8722 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8724 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8725 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8727 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8728 XEXP (XEXP (x
, 0), 0), temp
);
8729 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8730 XEXP (XEXP (x
, 0), 1));
8731 return force_to_mode (x
, mode
, mask
, next_select
);
8735 /* For most binary operations, just propagate into the operation and
8736 change the mode if we have an operation of that mode. */
8738 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8739 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8741 /* If we ended up truncating both operands, truncate the result of the
8742 operation instead. */
8743 if (GET_CODE (op0
) == TRUNCATE
8744 && GET_CODE (op1
) == TRUNCATE
)
8746 op0
= XEXP (op0
, 0);
8747 op1
= XEXP (op1
, 0);
8750 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8751 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8753 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8754 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8758 /* For left shifts, do the same, but just for the first operand.
8759 However, we cannot do anything with shifts where we cannot
8760 guarantee that the counts are smaller than the size of the mode
8761 because such a count will have a different meaning in a
8764 if (! (CONST_INT_P (XEXP (x
, 1))
8765 && INTVAL (XEXP (x
, 1)) >= 0
8766 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8767 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8768 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8769 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8772 /* If the shift count is a constant and we can do arithmetic in
8773 the mode of the shift, refine which bits we need. Otherwise, use the
8774 conservative form of the mask. */
8775 if (CONST_INT_P (XEXP (x
, 1))
8776 && INTVAL (XEXP (x
, 1)) >= 0
8777 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8778 && HWI_COMPUTABLE_MODE_P (op_mode
))
8779 mask
>>= INTVAL (XEXP (x
, 1));
8783 op0
= gen_lowpart_or_truncate (op_mode
,
8784 force_to_mode (XEXP (x
, 0), op_mode
,
8785 mask
, next_select
));
8787 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8788 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8792 /* Here we can only do something if the shift count is a constant,
8793 this shift constant is valid for the host, and we can do arithmetic
8796 if (CONST_INT_P (XEXP (x
, 1))
8797 && INTVAL (XEXP (x
, 1)) >= 0
8798 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8799 && HWI_COMPUTABLE_MODE_P (op_mode
))
8801 rtx inner
= XEXP (x
, 0);
8802 unsigned HOST_WIDE_INT inner_mask
;
8804 /* Select the mask of the bits we need for the shift operand. */
8805 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8807 /* We can only change the mode of the shift if we can do arithmetic
8808 in the mode of the shift and INNER_MASK is no wider than the
8809 width of X's mode. */
8810 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8811 op_mode
= GET_MODE (x
);
8813 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8815 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8816 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8819 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8820 shift and AND produces only copies of the sign bit (C2 is one less
8821 than a power of two), we can do this with just a shift. */
8823 if (GET_CODE (x
) == LSHIFTRT
8824 && CONST_INT_P (XEXP (x
, 1))
8825 /* The shift puts one of the sign bit copies in the least significant
8827 && ((INTVAL (XEXP (x
, 1))
8828 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8829 >= GET_MODE_PRECISION (GET_MODE (x
)))
8830 && pow2p_hwi (mask
+ 1)
8831 /* Number of bits left after the shift must be more than the mask
8833 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8834 <= GET_MODE_PRECISION (GET_MODE (x
)))
8835 /* Must be more sign bit copies than the mask needs. */
8836 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8837 >= exact_log2 (mask
+ 1)))
8838 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8839 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8840 - exact_log2 (mask
+ 1)));
8845 /* If we are just looking for the sign bit, we don't need this shift at
8846 all, even if it has a variable count. */
8847 if (val_signbit_p (GET_MODE (x
), mask
))
8848 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8850 /* If this is a shift by a constant, get a mask that contains those bits
8851 that are not copies of the sign bit. We then have two cases: If
8852 MASK only includes those bits, this can be a logical shift, which may
8853 allow simplifications. If MASK is a single-bit field not within
8854 those bits, we are requesting a copy of the sign bit and hence can
8855 shift the sign bit to the appropriate location. */
8857 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8858 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8862 /* If the considered data is wider than HOST_WIDE_INT, we can't
8863 represent a mask for all its bits in a single scalar.
8864 But we only care about the lower bits, so calculate these. */
8866 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8868 nonzero
= HOST_WIDE_INT_M1U
;
8870 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8871 is the number of bits a full-width mask would have set.
8872 We need only shift if these are fewer than nonzero can
8873 hold. If not, we must keep all bits set in nonzero. */
8875 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8876 < HOST_BITS_PER_WIDE_INT
)
8877 nonzero
>>= INTVAL (XEXP (x
, 1))
8878 + HOST_BITS_PER_WIDE_INT
8879 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8883 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8884 nonzero
>>= INTVAL (XEXP (x
, 1));
8887 if ((mask
& ~nonzero
) == 0)
8889 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8890 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8891 if (GET_CODE (x
) != ASHIFTRT
)
8892 return force_to_mode (x
, mode
, mask
, next_select
);
8895 else if ((i
= exact_log2 (mask
)) >= 0)
8897 x
= simplify_shift_const
8898 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8899 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
8901 if (GET_CODE (x
) != ASHIFTRT
)
8902 return force_to_mode (x
, mode
, mask
, next_select
);
8906 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8907 even if the shift count isn't a constant. */
8909 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8910 XEXP (x
, 0), XEXP (x
, 1));
8914 /* If this is a zero- or sign-extension operation that just affects bits
8915 we don't care about, remove it. Be sure the call above returned
8916 something that is still a shift. */
8918 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8919 && CONST_INT_P (XEXP (x
, 1))
8920 && INTVAL (XEXP (x
, 1)) >= 0
8921 && (INTVAL (XEXP (x
, 1))
8922 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8923 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8924 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8925 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8932 /* If the shift count is constant and we can do computations
8933 in the mode of X, compute where the bits we care about are.
8934 Otherwise, we can't do anything. Don't change the mode of
8935 the shift or propagate MODE into the shift, though. */
8936 if (CONST_INT_P (XEXP (x
, 1))
8937 && INTVAL (XEXP (x
, 1)) >= 0)
8939 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8941 gen_int_mode (mask
, GET_MODE (x
)),
8943 if (temp
&& CONST_INT_P (temp
))
8944 x
= simplify_gen_binary (code
, GET_MODE (x
),
8945 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8946 INTVAL (temp
), next_select
),
8952 /* If we just want the low-order bit, the NEG isn't needed since it
8953 won't change the low-order bit. */
8955 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8957 /* We need any bits less significant than the most significant bit in
8958 MASK since carries from those bits will affect the bits we are
8964 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8965 same as the XOR case above. Ensure that the constant we form is not
8966 wider than the mode of X. */
8968 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8969 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8970 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8971 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8972 < GET_MODE_PRECISION (GET_MODE (x
)))
8973 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8975 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8977 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8978 XEXP (XEXP (x
, 0), 0), temp
);
8979 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8980 temp
, XEXP (XEXP (x
, 0), 1));
8982 return force_to_mode (x
, mode
, mask
, next_select
);
8985 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8986 use the full mask inside the NOT. */
8990 op0
= gen_lowpart_or_truncate (op_mode
,
8991 force_to_mode (XEXP (x
, 0), mode
, mask
,
8993 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8994 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8998 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8999 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9000 which is equal to STORE_FLAG_VALUE. */
9001 if ((mask
& ~STORE_FLAG_VALUE
) == 0
9002 && XEXP (x
, 1) == const0_rtx
9003 && GET_MODE (XEXP (x
, 0)) == mode
9004 && pow2p_hwi (nonzero_bits (XEXP (x
, 0), mode
))
9005 && (nonzero_bits (XEXP (x
, 0), mode
)
9006 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
9007 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
9012 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9013 written in a narrower mode. We play it safe and do not do so. */
9015 op0
= gen_lowpart_or_truncate (GET_MODE (x
),
9016 force_to_mode (XEXP (x
, 1), mode
,
9017 mask
, next_select
));
9018 op1
= gen_lowpart_or_truncate (GET_MODE (x
),
9019 force_to_mode (XEXP (x
, 2), mode
,
9020 mask
, next_select
));
9021 if (op0
!= XEXP (x
, 1) || op1
!= XEXP (x
, 2))
9022 x
= simplify_gen_ternary (IF_THEN_ELSE
, GET_MODE (x
),
9023 GET_MODE (XEXP (x
, 0)), XEXP (x
, 0),
9031 /* Ensure we return a value of the proper mode. */
9032 return gen_lowpart_or_truncate (mode
, x
);
9035 /* Return nonzero if X is an expression that has one of two values depending on
9036 whether some other value is zero or nonzero. In that case, we return the
9037 value that is being tested, *PTRUE is set to the value if the rtx being
9038 returned has a nonzero value, and *PFALSE is set to the other alternative.
9040 If we return zero, we set *PTRUE and *PFALSE to X. */
9043 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
9045 machine_mode mode
= GET_MODE (x
);
9046 enum rtx_code code
= GET_CODE (x
);
9047 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
9048 unsigned HOST_WIDE_INT nz
;
9049 scalar_int_mode int_mode
;
9051 /* If we are comparing a value against zero, we are done. */
9052 if ((code
== NE
|| code
== EQ
)
9053 && XEXP (x
, 1) == const0_rtx
)
9055 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
9056 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
9060 /* If this is a unary operation whose operand has one of two values, apply
9061 our opcode to compute those values. */
9062 else if (UNARY_P (x
)
9063 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
9065 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
9066 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
9067 GET_MODE (XEXP (x
, 0)));
9071 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9072 make can't possibly match and would suppress other optimizations. */
9073 else if (code
== COMPARE
)
9076 /* If this is a binary operation, see if either side has only one of two
9077 values. If either one does or if both do and they are conditional on
9078 the same value, compute the new true and false values. */
9079 else if (BINARY_P (x
))
9081 rtx op0
= XEXP (x
, 0);
9082 rtx op1
= XEXP (x
, 1);
9083 cond0
= if_then_else_cond (op0
, &true0
, &false0
);
9084 cond1
= if_then_else_cond (op1
, &true1
, &false1
);
9086 if ((cond0
!= 0 && cond1
!= 0 && !rtx_equal_p (cond0
, cond1
))
9087 && (REG_P (op0
) || REG_P (op1
)))
9089 /* Try to enable a simplification by undoing work done by
9090 if_then_else_cond if it converted a REG into something more
9095 true0
= false0
= op0
;
9100 true1
= false1
= op1
;
9104 if ((cond0
!= 0 || cond1
!= 0)
9105 && ! (cond0
!= 0 && cond1
!= 0 && !rtx_equal_p (cond0
, cond1
)))
9107 /* If if_then_else_cond returned zero, then true/false are the
9108 same rtl. We must copy one of them to prevent invalid rtl
9111 true0
= copy_rtx (true0
);
9112 else if (cond1
== 0)
9113 true1
= copy_rtx (true1
);
9115 if (COMPARISON_P (x
))
9117 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
9119 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
9124 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
9125 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
9128 return cond0
? cond0
: cond1
;
9131 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9132 operands is zero when the other is nonzero, and vice-versa,
9133 and STORE_FLAG_VALUE is 1 or -1. */
9135 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9136 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
9138 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9140 rtx op0
= XEXP (XEXP (x
, 0), 1);
9141 rtx op1
= XEXP (XEXP (x
, 1), 1);
9143 cond0
= XEXP (XEXP (x
, 0), 0);
9144 cond1
= XEXP (XEXP (x
, 1), 0);
9146 if (COMPARISON_P (cond0
)
9147 && COMPARISON_P (cond1
)
9148 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9149 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9150 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9151 || ((swap_condition (GET_CODE (cond0
))
9152 == reversed_comparison_code (cond1
, NULL
))
9153 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9154 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9155 && ! side_effects_p (x
))
9157 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
9158 *pfalse
= simplify_gen_binary (MULT
, mode
,
9160 ? simplify_gen_unary (NEG
, mode
,
9168 /* Similarly for MULT, AND and UMIN, except that for these the result
9170 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9171 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
9172 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9174 cond0
= XEXP (XEXP (x
, 0), 0);
9175 cond1
= XEXP (XEXP (x
, 1), 0);
9177 if (COMPARISON_P (cond0
)
9178 && COMPARISON_P (cond1
)
9179 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9180 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9181 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9182 || ((swap_condition (GET_CODE (cond0
))
9183 == reversed_comparison_code (cond1
, NULL
))
9184 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9185 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9186 && ! side_effects_p (x
))
9188 *ptrue
= *pfalse
= const0_rtx
;
9194 else if (code
== IF_THEN_ELSE
)
9196 /* If we have IF_THEN_ELSE already, extract the condition and
9197 canonicalize it if it is NE or EQ. */
9198 cond0
= XEXP (x
, 0);
9199 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
9200 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
9201 return XEXP (cond0
, 0);
9202 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
9204 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
9205 return XEXP (cond0
, 0);
9211 /* If X is a SUBREG, we can narrow both the true and false values
9212 if the inner expression, if there is a condition. */
9213 else if (code
== SUBREG
9214 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
9217 true0
= simplify_gen_subreg (mode
, true0
,
9218 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9219 false0
= simplify_gen_subreg (mode
, false0
,
9220 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9221 if (true0
&& false0
)
9229 /* If X is a constant, this isn't special and will cause confusions
9230 if we treat it as such. Likewise if it is equivalent to a constant. */
9231 else if (CONSTANT_P (x
)
9232 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
9235 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9236 will be least confusing to the rest of the compiler. */
9237 else if (mode
== BImode
)
9239 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
9243 /* If X is known to be either 0 or -1, those are the true and
9244 false values when testing X. */
9245 else if (x
== constm1_rtx
|| x
== const0_rtx
9246 || (is_a
<scalar_int_mode
> (mode
, &int_mode
)
9247 && (num_sign_bit_copies (x
, int_mode
)
9248 == GET_MODE_PRECISION (int_mode
))))
9250 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
9254 /* Likewise for 0 or a single bit. */
9255 else if (HWI_COMPUTABLE_MODE_P (mode
)
9256 && pow2p_hwi (nz
= nonzero_bits (x
, mode
)))
9258 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
9262 /* Otherwise fail; show no condition with true and false values the same. */
9263 *ptrue
= *pfalse
= x
;
9267 /* Return the value of expression X given the fact that condition COND
9268 is known to be true when applied to REG as its first operand and VAL
9269 as its second. X is known to not be shared and so can be modified in
9272 We only handle the simplest cases, and specifically those cases that
9273 arise with IF_THEN_ELSE expressions. */
9276 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
9278 enum rtx_code code
= GET_CODE (x
);
9282 if (side_effects_p (x
))
9285 /* If either operand of the condition is a floating point value,
9286 then we have to avoid collapsing an EQ comparison. */
9288 && rtx_equal_p (x
, reg
)
9289 && ! FLOAT_MODE_P (GET_MODE (x
))
9290 && ! FLOAT_MODE_P (GET_MODE (val
)))
9293 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
9296 /* If X is (abs REG) and we know something about REG's relationship
9297 with zero, we may be able to simplify this. */
9299 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
9302 case GE
: case GT
: case EQ
:
9305 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
9307 GET_MODE (XEXP (x
, 0)));
9312 /* The only other cases we handle are MIN, MAX, and comparisons if the
9313 operands are the same as REG and VAL. */
9315 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
9317 if (rtx_equal_p (XEXP (x
, 0), val
))
9319 std::swap (val
, reg
);
9320 cond
= swap_condition (cond
);
9323 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
9325 if (COMPARISON_P (x
))
9327 if (comparison_dominates_p (cond
, code
))
9328 return const_true_rtx
;
9330 code
= reversed_comparison_code (x
, NULL
);
9332 && comparison_dominates_p (cond
, code
))
9337 else if (code
== SMAX
|| code
== SMIN
9338 || code
== UMIN
|| code
== UMAX
)
9340 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
9342 /* Do not reverse the condition when it is NE or EQ.
9343 This is because we cannot conclude anything about
9344 the value of 'SMAX (x, y)' when x is not equal to y,
9345 but we can when x equals y. */
9346 if ((code
== SMAX
|| code
== UMAX
)
9347 && ! (cond
== EQ
|| cond
== NE
))
9348 cond
= reverse_condition (cond
);
9353 return unsignedp
? x
: XEXP (x
, 1);
9355 return unsignedp
? x
: XEXP (x
, 0);
9357 return unsignedp
? XEXP (x
, 1) : x
;
9359 return unsignedp
? XEXP (x
, 0) : x
;
9366 else if (code
== SUBREG
)
9368 machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
9369 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
9371 if (SUBREG_REG (x
) != r
)
9373 /* We must simplify subreg here, before we lose track of the
9374 original inner_mode. */
9375 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
9376 inner_mode
, SUBREG_BYTE (x
));
9380 SUBST (SUBREG_REG (x
), r
);
9385 /* We don't have to handle SIGN_EXTEND here, because even in the
9386 case of replacing something with a modeless CONST_INT, a
9387 CONST_INT is already (supposed to be) a valid sign extension for
9388 its narrower mode, which implies it's already properly
9389 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9390 story is different. */
9391 else if (code
== ZERO_EXTEND
)
9393 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
9394 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
9396 if (XEXP (x
, 0) != r
)
9398 /* We must simplify the zero_extend here, before we lose
9399 track of the original inner_mode. */
9400 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
9405 SUBST (XEXP (x
, 0), r
);
9411 fmt
= GET_RTX_FORMAT (code
);
9412 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9415 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
9416 else if (fmt
[i
] == 'E')
9417 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9418 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
9425 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9426 assignment as a field assignment. */
9429 rtx_equal_for_field_assignment_p (rtx x
, rtx y
, bool widen_x
)
9431 if (widen_x
&& GET_MODE (x
) != GET_MODE (y
))
9433 if (paradoxical_subreg_p (GET_MODE (x
), GET_MODE (y
)))
9435 if (BYTES_BIG_ENDIAN
!= WORDS_BIG_ENDIAN
)
9437 /* For big endian, adjust the memory offset. */
9438 if (BYTES_BIG_ENDIAN
)
9439 x
= adjust_address_nv (x
, GET_MODE (y
),
9440 -subreg_lowpart_offset (GET_MODE (x
),
9443 x
= adjust_address_nv (x
, GET_MODE (y
), 0);
9446 if (x
== y
|| rtx_equal_p (x
, y
))
9449 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
9452 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9453 Note that all SUBREGs of MEM are paradoxical; otherwise they
9454 would have been rewritten. */
9455 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
9456 && MEM_P (SUBREG_REG (y
))
9457 && rtx_equal_p (SUBREG_REG (y
),
9458 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
9461 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
9462 && MEM_P (SUBREG_REG (x
))
9463 && rtx_equal_p (SUBREG_REG (x
),
9464 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
9467 /* We used to see if get_last_value of X and Y were the same but that's
9468 not correct. In one direction, we'll cause the assignment to have
9469 the wrong destination and in the case, we'll import a register into this
9470 insn that might have already have been dead. So fail if none of the
9471 above cases are true. */
9475 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9476 Return that assignment if so.
9478 We only handle the most common cases. */
9481 make_field_assignment (rtx x
)
9483 rtx dest
= SET_DEST (x
);
9484 rtx src
= SET_SRC (x
);
9489 unsigned HOST_WIDE_INT len
;
9492 /* All the rules in this function are specific to scalar integers. */
9493 scalar_int_mode mode
;
9494 if (!is_a
<scalar_int_mode
> (GET_MODE (dest
), &mode
))
9497 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9498 a clear of a one-bit field. We will have changed it to
9499 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9502 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9503 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9504 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9505 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9507 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9510 return gen_rtx_SET (assign
, const0_rtx
);
9514 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9515 && subreg_lowpart_p (XEXP (src
, 0))
9516 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
9517 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
9518 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9519 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9520 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9521 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9523 assign
= make_extraction (VOIDmode
, dest
, 0,
9524 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9527 return gen_rtx_SET (assign
, const0_rtx
);
9531 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9533 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9534 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9535 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9537 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9540 return gen_rtx_SET (assign
, const1_rtx
);
9544 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9545 SRC is an AND with all bits of that field set, then we can discard
9547 if (GET_CODE (dest
) == ZERO_EXTRACT
9548 && CONST_INT_P (XEXP (dest
, 1))
9549 && GET_CODE (src
) == AND
9550 && CONST_INT_P (XEXP (src
, 1)))
9552 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9553 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9554 unsigned HOST_WIDE_INT ze_mask
;
9556 if (width
>= HOST_BITS_PER_WIDE_INT
)
9559 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9561 /* Complete overlap. We can remove the source AND. */
9562 if ((and_mask
& ze_mask
) == ze_mask
)
9563 return gen_rtx_SET (dest
, XEXP (src
, 0));
9565 /* Partial overlap. We can reduce the source AND. */
9566 if ((and_mask
& ze_mask
) != and_mask
)
9568 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9569 gen_int_mode (and_mask
& ze_mask
, mode
));
9570 return gen_rtx_SET (dest
, src
);
9574 /* The other case we handle is assignments into a constant-position
9575 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9576 a mask that has all one bits except for a group of zero bits and
9577 OTHER is known to have zeros where C1 has ones, this is such an
9578 assignment. Compute the position and length from C1. Shift OTHER
9579 to the appropriate position, force it to the required mode, and
9580 make the extraction. Check for the AND in both operands. */
9582 /* One or more SUBREGs might obscure the constant-position field
9583 assignment. The first one we are likely to encounter is an outer
9584 narrowing SUBREG, which we can just strip for the purposes of
9585 identifying the constant-field assignment. */
9586 scalar_int_mode src_mode
= mode
;
9587 if (GET_CODE (src
) == SUBREG
9588 && subreg_lowpart_p (src
)
9589 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (src
)), &src_mode
))
9590 src
= SUBREG_REG (src
);
9592 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9595 rhs
= expand_compound_operation (XEXP (src
, 0));
9596 lhs
= expand_compound_operation (XEXP (src
, 1));
9598 if (GET_CODE (rhs
) == AND
9599 && CONST_INT_P (XEXP (rhs
, 1))
9600 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9601 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9602 /* The second SUBREG that might get in the way is a paradoxical
9603 SUBREG around the first operand of the AND. We want to
9604 pretend the operand is as wide as the destination here. We
9605 do this by adjusting the MEM to wider mode for the sole
9606 purpose of the call to rtx_equal_for_field_assignment_p. Also
9607 note this trick only works for MEMs. */
9608 else if (GET_CODE (rhs
) == AND
9609 && paradoxical_subreg_p (XEXP (rhs
, 0))
9610 && MEM_P (SUBREG_REG (XEXP (rhs
, 0)))
9611 && CONST_INT_P (XEXP (rhs
, 1))
9612 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs
, 0)),
9614 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9615 else if (GET_CODE (lhs
) == AND
9616 && CONST_INT_P (XEXP (lhs
, 1))
9617 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9618 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9619 /* The second SUBREG that might get in the way is a paradoxical
9620 SUBREG around the first operand of the AND. We want to
9621 pretend the operand is as wide as the destination here. We
9622 do this by adjusting the MEM to wider mode for the sole
9623 purpose of the call to rtx_equal_for_field_assignment_p. Also
9624 note this trick only works for MEMs. */
9625 else if (GET_CODE (lhs
) == AND
9626 && paradoxical_subreg_p (XEXP (lhs
, 0))
9627 && MEM_P (SUBREG_REG (XEXP (lhs
, 0)))
9628 && CONST_INT_P (XEXP (lhs
, 1))
9629 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs
, 0)),
9631 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9635 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (mode
), &len
);
9637 || pos
+ len
> GET_MODE_PRECISION (mode
)
9638 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
9639 || (c1
& nonzero_bits (other
, mode
)) != 0)
9642 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9646 /* The mode to use for the source is the mode of the assignment, or of
9647 what is inside a possible STRICT_LOW_PART. */
9648 machine_mode new_mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9649 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9651 /* Shift OTHER right POS places and make it the source, restricting it
9652 to the proper length and mode. */
9654 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9655 src_mode
, other
, pos
),
9657 src
= force_to_mode (src
, new_mode
,
9658 len
>= HOST_BITS_PER_WIDE_INT
9660 : (HOST_WIDE_INT_1U
<< len
) - 1,
9663 /* If SRC is masked by an AND that does not make a difference in
9664 the value being stored, strip it. */
9665 if (GET_CODE (assign
) == ZERO_EXTRACT
9666 && CONST_INT_P (XEXP (assign
, 1))
9667 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9668 && GET_CODE (src
) == AND
9669 && CONST_INT_P (XEXP (src
, 1))
9670 && UINTVAL (XEXP (src
, 1))
9671 == (HOST_WIDE_INT_1U
<< INTVAL (XEXP (assign
, 1))) - 1)
9672 src
= XEXP (src
, 0);
9674 return gen_rtx_SET (assign
, src
);
9677 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9681 apply_distributive_law (rtx x
)
9683 enum rtx_code code
= GET_CODE (x
);
9684 enum rtx_code inner_code
;
9685 rtx lhs
, rhs
, other
;
9688 /* Distributivity is not true for floating point as it can change the
9689 value. So we don't do it unless -funsafe-math-optimizations. */
9690 if (FLOAT_MODE_P (GET_MODE (x
))
9691 && ! flag_unsafe_math_optimizations
)
9694 /* The outer operation can only be one of the following: */
9695 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9696 && code
!= PLUS
&& code
!= MINUS
)
9702 /* If either operand is a primitive we can't do anything, so get out
9704 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9707 lhs
= expand_compound_operation (lhs
);
9708 rhs
= expand_compound_operation (rhs
);
9709 inner_code
= GET_CODE (lhs
);
9710 if (inner_code
!= GET_CODE (rhs
))
9713 /* See if the inner and outer operations distribute. */
9720 /* These all distribute except over PLUS. */
9721 if (code
== PLUS
|| code
== MINUS
)
9726 if (code
!= PLUS
&& code
!= MINUS
)
9731 /* This is also a multiply, so it distributes over everything. */
9734 /* This used to handle SUBREG, but this turned out to be counter-
9735 productive, since (subreg (op ...)) usually is not handled by
9736 insn patterns, and this "optimization" therefore transformed
9737 recognizable patterns into unrecognizable ones. Therefore the
9738 SUBREG case was removed from here.
9740 It is possible that distributing SUBREG over arithmetic operations
9741 leads to an intermediate result than can then be optimized further,
9742 e.g. by moving the outer SUBREG to the other side of a SET as done
9743 in simplify_set. This seems to have been the original intent of
9744 handling SUBREGs here.
9746 However, with current GCC this does not appear to actually happen,
9747 at least on major platforms. If some case is found where removing
9748 the SUBREG case here prevents follow-on optimizations, distributing
9749 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9755 /* Set LHS and RHS to the inner operands (A and B in the example
9756 above) and set OTHER to the common operand (C in the example).
9757 There is only one way to do this unless the inner operation is
9759 if (COMMUTATIVE_ARITH_P (lhs
)
9760 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9761 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9762 else if (COMMUTATIVE_ARITH_P (lhs
)
9763 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9764 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9765 else if (COMMUTATIVE_ARITH_P (lhs
)
9766 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9767 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9768 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9769 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9773 /* Form the new inner operation, seeing if it simplifies first. */
9774 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9776 /* There is one exception to the general way of distributing:
9777 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9778 if (code
== XOR
&& inner_code
== IOR
)
9781 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9784 /* We may be able to continuing distributing the result, so call
9785 ourselves recursively on the inner operation before forming the
9786 outer operation, which we return. */
9787 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9788 apply_distributive_law (tem
), other
);
9791 /* See if X is of the form (* (+ A B) C), and if so convert to
9792 (+ (* A C) (* B C)) and try to simplify.
9794 Most of the time, this results in no change. However, if some of
9795 the operands are the same or inverses of each other, simplifications
9798 For example, (and (ior A B) (not B)) can occur as the result of
9799 expanding a bit field assignment. When we apply the distributive
9800 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9801 which then simplifies to (and (A (not B))).
9803 Note that no checks happen on the validity of applying the inverse
9804 distributive law. This is pointless since we can do it in the
9805 few places where this routine is called.
9807 N is the index of the term that is decomposed (the arithmetic operation,
9808 i.e. (+ A B) in the first example above). !N is the index of the term that
9809 is distributed, i.e. of C in the first example above. */
9811 distribute_and_simplify_rtx (rtx x
, int n
)
9814 enum rtx_code outer_code
, inner_code
;
9815 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9817 /* Distributivity is not true for floating point as it can change the
9818 value. So we don't do it unless -funsafe-math-optimizations. */
9819 if (FLOAT_MODE_P (GET_MODE (x
))
9820 && ! flag_unsafe_math_optimizations
)
9823 decomposed
= XEXP (x
, n
);
9824 if (!ARITHMETIC_P (decomposed
))
9827 mode
= GET_MODE (x
);
9828 outer_code
= GET_CODE (x
);
9829 distributed
= XEXP (x
, !n
);
9831 inner_code
= GET_CODE (decomposed
);
9832 inner_op0
= XEXP (decomposed
, 0);
9833 inner_op1
= XEXP (decomposed
, 1);
9835 /* Special case (and (xor B C) (not A)), which is equivalent to
9836 (xor (ior A B) (ior A C)) */
9837 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9839 distributed
= XEXP (distributed
, 0);
9845 /* Distribute the second term. */
9846 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9847 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9851 /* Distribute the first term. */
9852 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9853 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9856 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9858 if (GET_CODE (tmp
) != outer_code
9859 && (set_src_cost (tmp
, mode
, optimize_this_for_speed_p
)
9860 < set_src_cost (x
, mode
, optimize_this_for_speed_p
)))
9866 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9867 in MODE. Return an equivalent form, if different from (and VAROP
9868 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9871 simplify_and_const_int_1 (machine_mode mode
, rtx varop
,
9872 unsigned HOST_WIDE_INT constop
)
9874 unsigned HOST_WIDE_INT nonzero
;
9875 unsigned HOST_WIDE_INT orig_constop
;
9880 orig_constop
= constop
;
9881 if (GET_CODE (varop
) == CLOBBER
)
9884 /* Simplify VAROP knowing that we will be only looking at some of the
9887 Note by passing in CONSTOP, we guarantee that the bits not set in
9888 CONSTOP are not significant and will never be examined. We must
9889 ensure that is the case by explicitly masking out those bits
9890 before returning. */
9891 varop
= force_to_mode (varop
, mode
, constop
, 0);
9893 /* If VAROP is a CLOBBER, we will fail so return it. */
9894 if (GET_CODE (varop
) == CLOBBER
)
9897 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9898 to VAROP and return the new constant. */
9899 if (CONST_INT_P (varop
))
9900 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9902 /* See what bits may be nonzero in VAROP. Unlike the general case of
9903 a call to nonzero_bits, here we don't care about bits outside
9906 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9908 /* Turn off all bits in the constant that are known to already be zero.
9909 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9910 which is tested below. */
9914 /* If we don't have any bits left, return zero. */
9918 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9919 a power of two, we can replace this with an ASHIFT. */
9920 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9921 && (i
= exact_log2 (constop
)) >= 0)
9922 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9924 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9925 or XOR, then try to apply the distributive law. This may eliminate
9926 operations if either branch can be simplified because of the AND.
9927 It may also make some cases more complex, but those cases probably
9928 won't match a pattern either with or without this. */
9930 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9934 apply_distributive_law
9935 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9936 simplify_and_const_int (NULL_RTX
,
9940 simplify_and_const_int (NULL_RTX
,
9945 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9946 the AND and see if one of the operands simplifies to zero. If so, we
9947 may eliminate it. */
9949 if (GET_CODE (varop
) == PLUS
9950 && pow2p_hwi (constop
+ 1))
9954 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9955 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9956 if (o0
== const0_rtx
)
9958 if (o1
== const0_rtx
)
9962 /* Make a SUBREG if necessary. If we can't make it, fail. */
9963 varop
= gen_lowpart (mode
, varop
);
9964 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9967 /* If we are only masking insignificant bits, return VAROP. */
9968 if (constop
== nonzero
)
9971 if (varop
== orig_varop
&& constop
== orig_constop
)
9974 /* Otherwise, return an AND. */
9975 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9979 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9982 Return an equivalent form, if different from X. Otherwise, return X. If
9983 X is zero, we are to always construct the equivalent form. */
9986 simplify_and_const_int (rtx x
, machine_mode mode
, rtx varop
,
9987 unsigned HOST_WIDE_INT constop
)
9989 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9994 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9995 gen_int_mode (constop
, mode
));
9996 if (GET_MODE (x
) != mode
)
9997 x
= gen_lowpart (mode
, x
);
10001 /* Given a REG, X, compute which bits in X can be nonzero.
10002 We don't care about bits outside of those defined in MODE.
10004 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10005 a shift, AND, or zero_extract, we can do better. */
10008 reg_nonzero_bits_for_combine (const_rtx x
, machine_mode mode
,
10009 const_rtx known_x ATTRIBUTE_UNUSED
,
10010 machine_mode known_mode ATTRIBUTE_UNUSED
,
10011 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
10012 unsigned HOST_WIDE_INT
*nonzero
)
10015 reg_stat_type
*rsp
;
10017 /* If X is a register whose nonzero bits value is current, use it.
10018 Otherwise, if X is a register whose value we can find, use that
10019 value. Otherwise, use the previously-computed global nonzero bits
10020 for this register. */
10022 rsp
= ®_stat
[REGNO (x
)];
10023 if (rsp
->last_set_value
!= 0
10024 && (rsp
->last_set_mode
== mode
10025 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
10026 && GET_MODE_CLASS (mode
) == MODE_INT
))
10027 && ((rsp
->last_set_label
>= label_tick_ebb_start
10028 && rsp
->last_set_label
< label_tick
)
10029 || (rsp
->last_set_label
== label_tick
10030 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
10031 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10032 && REGNO (x
) < reg_n_sets_max
10033 && REG_N_SETS (REGNO (x
)) == 1
10034 && !REGNO_REG_SET_P
10035 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
10038 /* Note that, even if the precision of last_set_mode is lower than that
10039 of mode, record_value_for_reg invoked nonzero_bits on the register
10040 with nonzero_bits_mode (because last_set_mode is necessarily integral
10041 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10042 are all valid, hence in mode too since nonzero_bits_mode is defined
10043 to the largest HWI_COMPUTABLE_MODE_P mode. */
10044 *nonzero
&= rsp
->last_set_nonzero_bits
;
10048 tem
= get_last_value (x
);
10051 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
10052 tem
= sign_extend_short_imm (tem
, GET_MODE (x
),
10053 GET_MODE_PRECISION (mode
));
10058 if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
10060 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
10062 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
10063 /* We don't know anything about the upper bits. */
10064 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
10072 /* Return the number of bits at the high-order end of X that are known to
10073 be equal to the sign bit. X will be used in mode MODE; if MODE is
10074 VOIDmode, X will be used in its own mode. The returned value will always
10075 be between 1 and the number of bits in MODE. */
10078 reg_num_sign_bit_copies_for_combine (const_rtx x
, machine_mode mode
,
10079 const_rtx known_x ATTRIBUTE_UNUSED
,
10080 machine_mode known_mode
10082 unsigned int known_ret ATTRIBUTE_UNUSED
,
10083 unsigned int *result
)
10086 reg_stat_type
*rsp
;
10088 rsp
= ®_stat
[REGNO (x
)];
10089 if (rsp
->last_set_value
!= 0
10090 && rsp
->last_set_mode
== mode
10091 && ((rsp
->last_set_label
>= label_tick_ebb_start
10092 && rsp
->last_set_label
< label_tick
)
10093 || (rsp
->last_set_label
== label_tick
10094 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
10095 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10096 && REGNO (x
) < reg_n_sets_max
10097 && REG_N_SETS (REGNO (x
)) == 1
10098 && !REGNO_REG_SET_P
10099 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
10102 *result
= rsp
->last_set_sign_bit_copies
;
10106 tem
= get_last_value (x
);
10110 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
10111 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
10112 *result
= rsp
->sign_bit_copies
;
10117 /* Return the number of "extended" bits there are in X, when interpreted
10118 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10119 unsigned quantities, this is the number of high-order zero bits.
10120 For signed quantities, this is the number of copies of the sign bit
10121 minus 1. In both case, this function returns the number of "spare"
10122 bits. For example, if two quantities for which this function returns
10123 at least 1 are added, the addition is known not to overflow.
10125 This function will always return 0 unless called during combine, which
10126 implies that it must be called from a define_split. */
10129 extended_count (const_rtx x
, machine_mode mode
, int unsignedp
)
10131 if (nonzero_sign_valid
== 0)
10134 scalar_int_mode int_mode
;
10136 ? (is_a
<scalar_int_mode
> (mode
, &int_mode
)
10137 && HWI_COMPUTABLE_MODE_P (int_mode
)
10138 ? (unsigned int) (GET_MODE_PRECISION (int_mode
) - 1
10139 - floor_log2 (nonzero_bits (x
, int_mode
)))
10141 : num_sign_bit_copies (x
, mode
) - 1);
10144 /* This function is called from `simplify_shift_const' to merge two
10145 outer operations. Specifically, we have already found that we need
10146 to perform operation *POP0 with constant *PCONST0 at the outermost
10147 position. We would now like to also perform OP1 with constant CONST1
10148 (with *POP0 being done last).
10150 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10151 the resulting operation. *PCOMP_P is set to 1 if we would need to
10152 complement the innermost operand, otherwise it is unchanged.
10154 MODE is the mode in which the operation will be done. No bits outside
10155 the width of this mode matter. It is assumed that the width of this mode
10156 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10158 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10159 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10160 result is simply *PCONST0.
10162 If the resulting operation cannot be expressed as one operation, we
10163 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10166 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, machine_mode mode
, int *pcomp_p
)
10168 enum rtx_code op0
= *pop0
;
10169 HOST_WIDE_INT const0
= *pconst0
;
10171 const0
&= GET_MODE_MASK (mode
);
10172 const1
&= GET_MODE_MASK (mode
);
10174 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10178 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10181 if (op1
== UNKNOWN
|| op0
== SET
)
10184 else if (op0
== UNKNOWN
)
10185 op0
= op1
, const0
= const1
;
10187 else if (op0
== op1
)
10211 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10212 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
10215 /* If the two constants aren't the same, we can't do anything. The
10216 remaining six cases can all be done. */
10217 else if (const0
!= const1
)
10225 /* (a & b) | b == b */
10227 else /* op1 == XOR */
10228 /* (a ^ b) | b == a | b */
10234 /* (a & b) ^ b == (~a) & b */
10235 op0
= AND
, *pcomp_p
= 1;
10236 else /* op1 == IOR */
10237 /* (a | b) ^ b == a & ~b */
10238 op0
= AND
, const0
= ~const0
;
10243 /* (a | b) & b == b */
10245 else /* op1 == XOR */
10246 /* (a ^ b) & b) == (~a) & b */
10253 /* Check for NO-OP cases. */
10254 const0
&= GET_MODE_MASK (mode
);
10256 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
10258 else if (const0
== 0 && op0
== AND
)
10260 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
10266 /* ??? Slightly redundant with the above mask, but not entirely.
10267 Moving this above means we'd have to sign-extend the mode mask
10268 for the final test. */
10269 if (op0
!= UNKNOWN
&& op0
!= NEG
)
10270 *pconst0
= trunc_int_for_mode (const0
, mode
);
10275 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10276 the shift in. The original shift operation CODE is performed on OP in
10277 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10278 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10279 result of the shift is subject to operation OUTER_CODE with operand
10282 static machine_mode
10283 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
10284 machine_mode orig_mode
, machine_mode mode
,
10285 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
10287 if (orig_mode
== mode
)
10289 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
10291 /* In general we can't perform in wider mode for right shift and rotate. */
10295 /* We can still widen if the bits brought in from the left are identical
10296 to the sign bit of ORIG_MODE. */
10297 if (num_sign_bit_copies (op
, mode
)
10298 > (unsigned) (GET_MODE_PRECISION (mode
)
10299 - GET_MODE_PRECISION (orig_mode
)))
10304 /* Similarly here but with zero bits. */
10305 if (HWI_COMPUTABLE_MODE_P (mode
)
10306 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
10309 /* We can also widen if the bits brought in will be masked off. This
10310 operation is performed in ORIG_MODE. */
10311 if (outer_code
== AND
)
10313 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
10316 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
10325 gcc_unreachable ();
10332 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10333 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10334 if we cannot simplify it. Otherwise, return a simplified value.
10336 The shift is normally computed in the widest mode we find in VAROP, as
10337 long as it isn't a different number of words than RESULT_MODE. Exceptions
10338 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10341 simplify_shift_const_1 (enum rtx_code code
, machine_mode result_mode
,
10342 rtx varop
, int orig_count
)
10344 enum rtx_code orig_code
= code
;
10345 rtx orig_varop
= varop
;
10347 machine_mode mode
= result_mode
;
10348 machine_mode shift_mode
;
10349 scalar_int_mode tmode
, inner_mode
;
10350 unsigned int mode_words
10351 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
10352 /* We form (outer_op (code varop count) (outer_const)). */
10353 enum rtx_code outer_op
= UNKNOWN
;
10354 HOST_WIDE_INT outer_const
= 0;
10355 int complement_p
= 0;
10358 /* Make sure and truncate the "natural" shift on the way in. We don't
10359 want to do this inside the loop as it makes it more difficult to
10361 if (SHIFT_COUNT_TRUNCATED
)
10362 orig_count
&= GET_MODE_UNIT_BITSIZE (mode
) - 1;
10364 /* If we were given an invalid count, don't do anything except exactly
10365 what was requested. */
10367 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_UNIT_PRECISION (mode
))
10370 count
= orig_count
;
10372 /* Unless one of the branches of the `if' in this loop does a `continue',
10373 we will `break' the loop after the `if'. */
10377 /* If we have an operand of (clobber (const_int 0)), fail. */
10378 if (GET_CODE (varop
) == CLOBBER
)
10381 /* Convert ROTATERT to ROTATE. */
10382 if (code
== ROTATERT
)
10384 unsigned int bitsize
= GET_MODE_UNIT_PRECISION (result_mode
);
10386 count
= bitsize
- count
;
10389 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
10390 mode
, outer_op
, outer_const
);
10391 machine_mode shift_unit_mode
= GET_MODE_INNER (shift_mode
);
10393 /* Handle cases where the count is greater than the size of the mode
10394 minus 1. For ASHIFT, use the size minus one as the count (this can
10395 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10396 take the count modulo the size. For other shifts, the result is
10399 Since these shifts are being produced by the compiler by combining
10400 multiple operations, each of which are defined, we know what the
10401 result is supposed to be. */
10403 if (count
> (GET_MODE_PRECISION (shift_unit_mode
) - 1))
10405 if (code
== ASHIFTRT
)
10406 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10407 else if (code
== ROTATE
|| code
== ROTATERT
)
10408 count
%= GET_MODE_PRECISION (shift_unit_mode
);
10411 /* We can't simply return zero because there may be an
10413 varop
= const0_rtx
;
10419 /* If we discovered we had to complement VAROP, leave. Making a NOT
10420 here would cause an infinite loop. */
10424 if (shift_mode
== shift_unit_mode
)
10426 /* An arithmetic right shift of a quantity known to be -1 or 0
10428 if (code
== ASHIFTRT
10429 && (num_sign_bit_copies (varop
, shift_unit_mode
)
10430 == GET_MODE_PRECISION (shift_unit_mode
)))
10436 /* If we are doing an arithmetic right shift and discarding all but
10437 the sign bit copies, this is equivalent to doing a shift by the
10438 bitsize minus one. Convert it into that shift because it will
10439 often allow other simplifications. */
10441 if (code
== ASHIFTRT
10442 && (count
+ num_sign_bit_copies (varop
, shift_unit_mode
)
10443 >= GET_MODE_PRECISION (shift_unit_mode
)))
10444 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10446 /* We simplify the tests below and elsewhere by converting
10447 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10448 `make_compound_operation' will convert it to an ASHIFTRT for
10449 those machines (such as VAX) that don't have an LSHIFTRT. */
10450 if (code
== ASHIFTRT
10451 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10452 && val_signbit_known_clear_p (shift_unit_mode
,
10453 nonzero_bits (varop
,
10457 if (((code
== LSHIFTRT
10458 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10459 && !(nonzero_bits (varop
, shift_unit_mode
) >> count
))
10461 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10462 && !((nonzero_bits (varop
, shift_unit_mode
) << count
)
10463 & GET_MODE_MASK (shift_unit_mode
))))
10464 && !side_effects_p (varop
))
10465 varop
= const0_rtx
;
10468 switch (GET_CODE (varop
))
10474 new_rtx
= expand_compound_operation (varop
);
10475 if (new_rtx
!= varop
)
10483 /* The following rules apply only to scalars. */
10484 if (shift_mode
!= shift_unit_mode
)
10487 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10488 minus the width of a smaller mode, we can do this with a
10489 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10490 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10491 && ! mode_dependent_address_p (XEXP (varop
, 0),
10492 MEM_ADDR_SPACE (varop
))
10493 && ! MEM_VOLATILE_P (varop
)
10494 && (int_mode_for_size (GET_MODE_BITSIZE (mode
) - count
, 1)
10497 new_rtx
= adjust_address_nv (varop
, tmode
,
10498 BYTES_BIG_ENDIAN
? 0
10499 : count
/ BITS_PER_UNIT
);
10501 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
10502 : ZERO_EXTEND
, mode
, new_rtx
);
10509 /* The following rules apply only to scalars. */
10510 if (shift_mode
!= shift_unit_mode
)
10513 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10514 the same number of words as what we've seen so far. Then store
10515 the widest mode in MODE. */
10516 if (subreg_lowpart_p (varop
)
10517 && is_int_mode (GET_MODE (SUBREG_REG (varop
)), &inner_mode
)
10518 && GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (GET_MODE (varop
))
10519 && (unsigned int) ((GET_MODE_SIZE (inner_mode
)
10520 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
10522 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
)
10524 varop
= SUBREG_REG (varop
);
10525 if (GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (mode
))
10532 /* Some machines use MULT instead of ASHIFT because MULT
10533 is cheaper. But it is still better on those machines to
10534 merge two shifts into one. */
10535 if (CONST_INT_P (XEXP (varop
, 1))
10536 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10539 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10541 GEN_INT (exact_log2 (
10542 UINTVAL (XEXP (varop
, 1)))));
10548 /* Similar, for when divides are cheaper. */
10549 if (CONST_INT_P (XEXP (varop
, 1))
10550 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10553 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10555 GEN_INT (exact_log2 (
10556 UINTVAL (XEXP (varop
, 1)))));
10562 /* If we are extracting just the sign bit of an arithmetic
10563 right shift, that shift is not needed. However, the sign
10564 bit of a wider mode may be different from what would be
10565 interpreted as the sign bit in a narrower mode, so, if
10566 the result is narrower, don't discard the shift. */
10567 if (code
== LSHIFTRT
10568 && count
== (GET_MODE_UNIT_BITSIZE (result_mode
) - 1)
10569 && (GET_MODE_UNIT_BITSIZE (result_mode
)
10570 >= GET_MODE_UNIT_BITSIZE (GET_MODE (varop
))))
10572 varop
= XEXP (varop
, 0);
10581 /* The following rules apply only to scalars. */
10582 if (shift_mode
!= shift_unit_mode
)
10585 /* Here we have two nested shifts. The result is usually the
10586 AND of a new shift with a mask. We compute the result below. */
10587 if (CONST_INT_P (XEXP (varop
, 1))
10588 && INTVAL (XEXP (varop
, 1)) >= 0
10589 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
10590 && HWI_COMPUTABLE_MODE_P (result_mode
)
10591 && HWI_COMPUTABLE_MODE_P (mode
))
10593 enum rtx_code first_code
= GET_CODE (varop
);
10594 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10595 unsigned HOST_WIDE_INT mask
;
10598 /* We have one common special case. We can't do any merging if
10599 the inner code is an ASHIFTRT of a smaller mode. However, if
10600 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10601 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10602 we can convert it to
10603 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10604 This simplifies certain SIGN_EXTEND operations. */
10605 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10606 && count
== (GET_MODE_PRECISION (result_mode
)
10607 - GET_MODE_PRECISION (GET_MODE (varop
))))
10609 /* C3 has the low-order C1 bits zero. */
10611 mask
= GET_MODE_MASK (mode
)
10612 & ~((HOST_WIDE_INT_1U
<< first_count
) - 1);
10614 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10615 XEXP (varop
, 0), mask
);
10616 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10618 count
= first_count
;
10623 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10624 than C1 high-order bits equal to the sign bit, we can convert
10625 this to either an ASHIFT or an ASHIFTRT depending on the
10628 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10630 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10631 && GET_MODE (varop
) == shift_mode
10632 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10635 varop
= XEXP (varop
, 0);
10636 count
-= first_count
;
10646 /* There are some cases we can't do. If CODE is ASHIFTRT,
10647 we can only do this if FIRST_CODE is also ASHIFTRT.
10649 We can't do the case when CODE is ROTATE and FIRST_CODE is
10652 If the mode of this shift is not the mode of the outer shift,
10653 we can't do this if either shift is a right shift or ROTATE.
10655 Finally, we can't do any of these if the mode is too wide
10656 unless the codes are the same.
10658 Handle the case where the shift codes are the same
10661 if (code
== first_code
)
10663 if (GET_MODE (varop
) != result_mode
10664 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10665 || code
== ROTATE
))
10668 count
+= first_count
;
10669 varop
= XEXP (varop
, 0);
10673 if (code
== ASHIFTRT
10674 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10675 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10676 || (GET_MODE (varop
) != result_mode
10677 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10678 || first_code
== ROTATE
10679 || code
== ROTATE
)))
10682 /* To compute the mask to apply after the shift, shift the
10683 nonzero bits of the inner shift the same way the
10684 outer shift will. */
10686 mask_rtx
= gen_int_mode (nonzero_bits (varop
, GET_MODE (varop
)),
10690 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10693 /* Give up if we can't compute an outer operation to use. */
10695 || !CONST_INT_P (mask_rtx
)
10696 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10698 result_mode
, &complement_p
))
10701 /* If the shifts are in the same direction, we add the
10702 counts. Otherwise, we subtract them. */
10703 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10704 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10705 count
+= first_count
;
10707 count
-= first_count
;
10709 /* If COUNT is positive, the new shift is usually CODE,
10710 except for the two exceptions below, in which case it is
10711 FIRST_CODE. If the count is negative, FIRST_CODE should
10714 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10715 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10717 else if (count
< 0)
10718 code
= first_code
, count
= -count
;
10720 varop
= XEXP (varop
, 0);
10724 /* If we have (A << B << C) for any shift, we can convert this to
10725 (A << C << B). This wins if A is a constant. Only try this if
10726 B is not a constant. */
10728 else if (GET_CODE (varop
) == code
10729 && CONST_INT_P (XEXP (varop
, 0))
10730 && !CONST_INT_P (XEXP (varop
, 1)))
10732 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10733 sure the result will be masked. See PR70222. */
10734 if (code
== LSHIFTRT
10735 && mode
!= result_mode
10736 && !merge_outer_ops (&outer_op
, &outer_const
, AND
,
10737 GET_MODE_MASK (result_mode
)
10738 >> orig_count
, result_mode
,
10741 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10742 up outer sign extension (often left and right shift) is
10743 hardly more efficient than the original. See PR70429. */
10744 if (code
== ASHIFTRT
&& mode
!= result_mode
)
10747 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10750 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10757 /* The following rules apply only to scalars. */
10758 if (shift_mode
!= shift_unit_mode
)
10761 /* Make this fit the case below. */
10762 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10768 /* The following rules apply only to scalars. */
10769 if (shift_mode
!= shift_unit_mode
)
10772 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10773 with C the size of VAROP - 1 and the shift is logical if
10774 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10775 we have an (le X 0) operation. If we have an arithmetic shift
10776 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10777 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10779 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10780 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10781 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10782 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10783 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10784 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10787 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10790 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10791 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10796 /* If we have (shift (logical)), move the logical to the outside
10797 to allow it to possibly combine with another logical and the
10798 shift to combine with another shift. This also canonicalizes to
10799 what a ZERO_EXTRACT looks like. Also, some machines have
10800 (and (shift)) insns. */
10802 if (CONST_INT_P (XEXP (varop
, 1))
10803 /* We can't do this if we have (ashiftrt (xor)) and the
10804 constant has its sign bit set in shift_mode with shift_mode
10805 wider than result_mode. */
10806 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10807 && result_mode
!= shift_mode
10808 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10810 && (new_rtx
= simplify_const_binary_operation
10811 (code
, result_mode
,
10812 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10813 GEN_INT (count
))) != 0
10814 && CONST_INT_P (new_rtx
)
10815 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10816 INTVAL (new_rtx
), result_mode
, &complement_p
))
10818 varop
= XEXP (varop
, 0);
10822 /* If we can't do that, try to simplify the shift in each arm of the
10823 logical expression, make a new logical expression, and apply
10824 the inverse distributive law. This also can't be done for
10825 (ashiftrt (xor)) where we've widened the shift and the constant
10826 changes the sign bit. */
10827 if (CONST_INT_P (XEXP (varop
, 1))
10828 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10829 && result_mode
!= shift_mode
10830 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10833 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10834 XEXP (varop
, 0), count
);
10835 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10836 XEXP (varop
, 1), count
);
10838 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10840 varop
= apply_distributive_law (varop
);
10848 /* The following rules apply only to scalars. */
10849 if (shift_mode
!= shift_unit_mode
)
10852 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10853 says that the sign bit can be tested, FOO has mode MODE, C is
10854 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10855 that may be nonzero. */
10856 if (code
== LSHIFTRT
10857 && XEXP (varop
, 1) == const0_rtx
10858 && GET_MODE (XEXP (varop
, 0)) == result_mode
10859 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10860 && HWI_COMPUTABLE_MODE_P (result_mode
)
10861 && STORE_FLAG_VALUE
== -1
10862 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10863 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10866 varop
= XEXP (varop
, 0);
10873 /* The following rules apply only to scalars. */
10874 if (shift_mode
!= shift_unit_mode
)
10877 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10878 than the number of bits in the mode is equivalent to A. */
10879 if (code
== LSHIFTRT
10880 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10881 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10883 varop
= XEXP (varop
, 0);
10888 /* NEG commutes with ASHIFT since it is multiplication. Move the
10889 NEG outside to allow shifts to combine. */
10891 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10894 varop
= XEXP (varop
, 0);
10900 /* The following rules apply only to scalars. */
10901 if (shift_mode
!= shift_unit_mode
)
10904 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10905 is one less than the number of bits in the mode is
10906 equivalent to (xor A 1). */
10907 if (code
== LSHIFTRT
10908 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10909 && XEXP (varop
, 1) == constm1_rtx
10910 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10911 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10915 varop
= XEXP (varop
, 0);
10919 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10920 that might be nonzero in BAR are those being shifted out and those
10921 bits are known zero in FOO, we can replace the PLUS with FOO.
10922 Similarly in the other operand order. This code occurs when
10923 we are computing the size of a variable-size array. */
10925 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10926 && count
< HOST_BITS_PER_WIDE_INT
10927 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10928 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10929 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10931 varop
= XEXP (varop
, 0);
10934 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10935 && count
< HOST_BITS_PER_WIDE_INT
10936 && HWI_COMPUTABLE_MODE_P (result_mode
)
10937 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10939 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10940 & nonzero_bits (XEXP (varop
, 1),
10943 varop
= XEXP (varop
, 1);
10947 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10949 && CONST_INT_P (XEXP (varop
, 1))
10950 && (new_rtx
= simplify_const_binary_operation
10951 (ASHIFT
, result_mode
,
10952 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10953 GEN_INT (count
))) != 0
10954 && CONST_INT_P (new_rtx
)
10955 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10956 INTVAL (new_rtx
), result_mode
, &complement_p
))
10958 varop
= XEXP (varop
, 0);
10962 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10963 signbit', and attempt to change the PLUS to an XOR and move it to
10964 the outer operation as is done above in the AND/IOR/XOR case
10965 leg for shift(logical). See details in logical handling above
10966 for reasoning in doing so. */
10967 if (code
== LSHIFTRT
10968 && CONST_INT_P (XEXP (varop
, 1))
10969 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10970 && (new_rtx
= simplify_const_binary_operation
10971 (code
, result_mode
,
10972 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10973 GEN_INT (count
))) != 0
10974 && CONST_INT_P (new_rtx
)
10975 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10976 INTVAL (new_rtx
), result_mode
, &complement_p
))
10978 varop
= XEXP (varop
, 0);
10985 /* The following rules apply only to scalars. */
10986 if (shift_mode
!= shift_unit_mode
)
10989 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10990 with C the size of VAROP - 1 and the shift is logical if
10991 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10992 we have a (gt X 0) operation. If the shift is arithmetic with
10993 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10994 we have a (neg (gt X 0)) operation. */
10996 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10997 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10998 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10999 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
11000 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
11001 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
11002 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
11005 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
11008 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
11009 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
11016 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11017 if the truncate does not affect the value. */
11018 if (code
== LSHIFTRT
11019 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
11020 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
11021 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
11022 >= (GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (varop
, 0)))
11023 - GET_MODE_UNIT_PRECISION (GET_MODE (varop
)))))
11025 rtx varop_inner
= XEXP (varop
, 0);
11028 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
11029 XEXP (varop_inner
, 0),
11031 (count
+ INTVAL (XEXP (varop_inner
, 1))));
11032 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
11045 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
11046 outer_op
, outer_const
);
11048 /* We have now finished analyzing the shift. The result should be
11049 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11050 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11051 to the result of the shift. OUTER_CONST is the relevant constant,
11052 but we must turn off all bits turned off in the shift. */
11054 if (outer_op
== UNKNOWN
11055 && orig_code
== code
&& orig_count
== count
11056 && varop
== orig_varop
11057 && shift_mode
== GET_MODE (varop
))
11060 /* Make a SUBREG if necessary. If we can't make it, fail. */
11061 varop
= gen_lowpart (shift_mode
, varop
);
11062 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
11065 /* If we have an outer operation and we just made a shift, it is
11066 possible that we could have simplified the shift were it not
11067 for the outer operation. So try to do the simplification
11070 if (outer_op
!= UNKNOWN
)
11071 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
11076 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
11078 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11079 turn off all the bits that the shift would have turned off. */
11080 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
11081 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
11082 GET_MODE_MASK (result_mode
) >> orig_count
);
11084 /* Do the remainder of the processing in RESULT_MODE. */
11085 x
= gen_lowpart_or_truncate (result_mode
, x
);
11087 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11090 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
11092 if (outer_op
!= UNKNOWN
)
11094 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
11095 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
11096 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
11098 if (outer_op
== AND
)
11099 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
11100 else if (outer_op
== SET
)
11102 /* This means that we have determined that the result is
11103 equivalent to a constant. This should be rare. */
11104 if (!side_effects_p (x
))
11105 x
= GEN_INT (outer_const
);
11107 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
11108 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
11110 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
11111 GEN_INT (outer_const
));
11117 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11118 The result of the shift is RESULT_MODE. If we cannot simplify it,
11119 return X or, if it is NULL, synthesize the expression with
11120 simplify_gen_binary. Otherwise, return a simplified value.
11122 The shift is normally computed in the widest mode we find in VAROP, as
11123 long as it isn't a different number of words than RESULT_MODE. Exceptions
11124 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11127 simplify_shift_const (rtx x
, enum rtx_code code
, machine_mode result_mode
,
11128 rtx varop
, int count
)
11130 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
11135 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
11136 if (GET_MODE (x
) != result_mode
)
11137 x
= gen_lowpart (result_mode
, x
);
11142 /* A subroutine of recog_for_combine. See there for arguments and
11146 recog_for_combine_1 (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11148 rtx pat
= *pnewpat
;
11149 rtx pat_without_clobbers
;
11150 int insn_code_number
;
11151 int num_clobbers_to_add
= 0;
11153 rtx notes
= NULL_RTX
;
11154 rtx old_notes
, old_pat
;
11157 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11158 we use to indicate that something didn't match. If we find such a
11159 thing, force rejection. */
11160 if (GET_CODE (pat
) == PARALLEL
)
11161 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
11162 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
11163 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
11166 old_pat
= PATTERN (insn
);
11167 old_notes
= REG_NOTES (insn
);
11168 PATTERN (insn
) = pat
;
11169 REG_NOTES (insn
) = NULL_RTX
;
11171 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11172 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11174 if (insn_code_number
< 0)
11175 fputs ("Failed to match this instruction:\n", dump_file
);
11177 fputs ("Successfully matched this instruction:\n", dump_file
);
11178 print_rtl_single (dump_file
, pat
);
11181 /* If it isn't, there is the possibility that we previously had an insn
11182 that clobbered some register as a side effect, but the combined
11183 insn doesn't need to do that. So try once more without the clobbers
11184 unless this represents an ASM insn. */
11186 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
11187 && GET_CODE (pat
) == PARALLEL
)
11191 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
11192 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
11195 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
11199 SUBST_INT (XVECLEN (pat
, 0), pos
);
11202 pat
= XVECEXP (pat
, 0, 0);
11204 PATTERN (insn
) = pat
;
11205 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11206 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11208 if (insn_code_number
< 0)
11209 fputs ("Failed to match this instruction:\n", dump_file
);
11211 fputs ("Successfully matched this instruction:\n", dump_file
);
11212 print_rtl_single (dump_file
, pat
);
11216 pat_without_clobbers
= pat
;
11218 PATTERN (insn
) = old_pat
;
11219 REG_NOTES (insn
) = old_notes
;
11221 /* Recognize all noop sets, these will be killed by followup pass. */
11222 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
11223 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
11225 /* If we had any clobbers to add, make a new pattern than contains
11226 them. Then check to make sure that all of them are dead. */
11227 if (num_clobbers_to_add
)
11229 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
11230 rtvec_alloc (GET_CODE (pat
) == PARALLEL
11231 ? (XVECLEN (pat
, 0)
11232 + num_clobbers_to_add
)
11233 : num_clobbers_to_add
+ 1));
11235 if (GET_CODE (pat
) == PARALLEL
)
11236 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11237 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
11239 XVECEXP (newpat
, 0, 0) = pat
;
11241 add_clobbers (newpat
, insn_code_number
);
11243 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
11244 i
< XVECLEN (newpat
, 0); i
++)
11246 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
11247 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
11249 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
11251 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
11252 notes
= alloc_reg_note (REG_UNUSED
,
11253 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
11259 if (insn_code_number
>= 0
11260 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
11262 old_pat
= PATTERN (insn
);
11263 old_notes
= REG_NOTES (insn
);
11264 old_icode
= INSN_CODE (insn
);
11265 PATTERN (insn
) = pat
;
11266 REG_NOTES (insn
) = notes
;
11267 INSN_CODE (insn
) = insn_code_number
;
11269 /* Allow targets to reject combined insn. */
11270 if (!targetm
.legitimate_combined_insn (insn
))
11272 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11273 fputs ("Instruction not appropriate for target.",
11276 /* Callers expect recog_for_combine to strip
11277 clobbers from the pattern on failure. */
11278 pat
= pat_without_clobbers
;
11281 insn_code_number
= -1;
11284 PATTERN (insn
) = old_pat
;
11285 REG_NOTES (insn
) = old_notes
;
11286 INSN_CODE (insn
) = old_icode
;
11292 return insn_code_number
;
11295 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11296 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11297 Return whether anything was so changed. */
11300 change_zero_ext (rtx pat
)
11302 bool changed
= false;
11303 rtx
*src
= &SET_SRC (pat
);
11305 subrtx_ptr_iterator::array_type array
;
11306 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11309 scalar_int_mode mode
, inner_mode
;
11310 if (!is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
))
11314 if (GET_CODE (x
) == ZERO_EXTRACT
11315 && CONST_INT_P (XEXP (x
, 1))
11316 && CONST_INT_P (XEXP (x
, 2))
11317 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
)
11318 && GET_MODE_PRECISION (inner_mode
) <= GET_MODE_PRECISION (mode
))
11320 size
= INTVAL (XEXP (x
, 1));
11322 int start
= INTVAL (XEXP (x
, 2));
11323 if (BITS_BIG_ENDIAN
)
11324 start
= GET_MODE_PRECISION (inner_mode
) - size
- start
;
11327 x
= gen_rtx_LSHIFTRT (inner_mode
, XEXP (x
, 0), GEN_INT (start
));
11330 if (mode
!= inner_mode
)
11331 x
= gen_lowpart_SUBREG (mode
, x
);
11333 else if (GET_CODE (x
) == ZERO_EXTEND
11334 && GET_CODE (XEXP (x
, 0)) == SUBREG
11335 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x
, 0))))
11336 && !paradoxical_subreg_p (XEXP (x
, 0))
11337 && subreg_lowpart_p (XEXP (x
, 0)))
11339 size
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
11340 x
= SUBREG_REG (XEXP (x
, 0));
11341 if (GET_MODE (x
) != mode
)
11342 x
= gen_lowpart_SUBREG (mode
, x
);
11344 else if (GET_CODE (x
) == ZERO_EXTEND
11345 && REG_P (XEXP (x
, 0))
11346 && HARD_REGISTER_P (XEXP (x
, 0))
11347 && can_change_dest_mode (XEXP (x
, 0), 0, mode
))
11349 size
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
11350 x
= gen_rtx_REG (mode
, REGNO (XEXP (x
, 0)));
11355 if (!(GET_CODE (x
) == LSHIFTRT
11356 && CONST_INT_P (XEXP (x
, 1))
11357 && size
+ INTVAL (XEXP (x
, 1)) == GET_MODE_PRECISION (mode
)))
11359 wide_int mask
= wi::mask (size
, false, GET_MODE_PRECISION (mode
));
11360 x
= gen_rtx_AND (mode
, x
, immed_wide_int_const (mask
, mode
));
11368 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11369 maybe_swap_commutative_operands (**iter
);
11371 rtx
*dst
= &SET_DEST (pat
);
11372 scalar_int_mode mode
;
11373 if (GET_CODE (*dst
) == ZERO_EXTRACT
11374 && REG_P (XEXP (*dst
, 0))
11375 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (*dst
, 0)), &mode
)
11376 && CONST_INT_P (XEXP (*dst
, 1))
11377 && CONST_INT_P (XEXP (*dst
, 2)))
11379 rtx reg
= XEXP (*dst
, 0);
11380 int width
= INTVAL (XEXP (*dst
, 1));
11381 int offset
= INTVAL (XEXP (*dst
, 2));
11382 int reg_width
= GET_MODE_PRECISION (mode
);
11383 if (BITS_BIG_ENDIAN
)
11384 offset
= reg_width
- width
- offset
;
11387 wide_int mask
= wi::shifted_mask (offset
, width
, true, reg_width
);
11388 wide_int mask2
= wi::shifted_mask (offset
, width
, false, reg_width
);
11389 x
= gen_rtx_AND (mode
, reg
, immed_wide_int_const (mask
, mode
));
11391 y
= gen_rtx_ASHIFT (mode
, SET_SRC (pat
), GEN_INT (offset
));
11394 z
= gen_rtx_AND (mode
, y
, immed_wide_int_const (mask2
, mode
));
11395 w
= gen_rtx_IOR (mode
, x
, z
);
11396 SUBST (SET_DEST (pat
), reg
);
11397 SUBST (SET_SRC (pat
), w
);
11405 /* Like recog, but we receive the address of a pointer to a new pattern.
11406 We try to match the rtx that the pointer points to.
11407 If that fails, we may try to modify or replace the pattern,
11408 storing the replacement into the same pointer object.
11410 Modifications include deletion or addition of CLOBBERs. If the
11411 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11412 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11413 (and undo if that fails).
11415 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11416 the CLOBBERs are placed.
11418 The value is the final insn code from the pattern ultimately matched,
11422 recog_for_combine (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11424 rtx pat
= *pnewpat
;
11425 int insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11426 if (insn_code_number
>= 0 || check_asm_operands (pat
))
11427 return insn_code_number
;
11429 void *marker
= get_undo_marker ();
11430 bool changed
= false;
11432 if (GET_CODE (pat
) == SET
)
11433 changed
= change_zero_ext (pat
);
11434 else if (GET_CODE (pat
) == PARALLEL
)
11437 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11439 rtx set
= XVECEXP (pat
, 0, i
);
11440 if (GET_CODE (set
) == SET
)
11441 changed
|= change_zero_ext (set
);
11447 insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11449 if (insn_code_number
< 0)
11450 undo_to_marker (marker
);
11453 return insn_code_number
;
11456 /* Like gen_lowpart_general but for use by combine. In combine it
11457 is not possible to create any new pseudoregs. However, it is
11458 safe to create invalid memory addresses, because combine will
11459 try to recognize them and all they will do is make the combine
11462 If for some reason this cannot do its job, an rtx
11463 (clobber (const_int 0)) is returned.
11464 An insn containing that will not be recognized. */
11467 gen_lowpart_for_combine (machine_mode omode
, rtx x
)
11469 machine_mode imode
= GET_MODE (x
);
11470 unsigned int osize
= GET_MODE_SIZE (omode
);
11471 unsigned int isize
= GET_MODE_SIZE (imode
);
11474 if (omode
== imode
)
11477 /* We can only support MODE being wider than a word if X is a
11478 constant integer or has a mode the same size. */
11479 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
11480 && ! (CONST_SCALAR_INT_P (x
) || isize
== osize
))
11483 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11484 won't know what to do. So we will strip off the SUBREG here and
11485 process normally. */
11486 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
11488 x
= SUBREG_REG (x
);
11490 /* For use in case we fall down into the address adjustments
11491 further below, we need to adjust the known mode and size of
11492 x; imode and isize, since we just adjusted x. */
11493 imode
= GET_MODE (x
);
11495 if (imode
== omode
)
11498 isize
= GET_MODE_SIZE (imode
);
11501 result
= gen_lowpart_common (omode
, x
);
11510 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11512 if (MEM_VOLATILE_P (x
)
11513 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
11516 /* If we want to refer to something bigger than the original memref,
11517 generate a paradoxical subreg instead. That will force a reload
11518 of the original memref X. */
11519 if (paradoxical_subreg_p (omode
, imode
))
11520 return gen_rtx_SUBREG (omode
, x
, 0);
11522 if (WORDS_BIG_ENDIAN
)
11523 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
11525 /* Adjust the address so that the address-after-the-data is
11527 if (BYTES_BIG_ENDIAN
)
11528 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
11530 return adjust_address_nv (x
, omode
, offset
);
11533 /* If X is a comparison operator, rewrite it in a new mode. This
11534 probably won't match, but may allow further simplifications. */
11535 else if (COMPARISON_P (x
))
11536 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
11538 /* If we couldn't simplify X any other way, just enclose it in a
11539 SUBREG. Normally, this SUBREG won't match, but some patterns may
11540 include an explicit SUBREG or we may simplify it further in combine. */
11545 if (imode
== VOIDmode
)
11547 imode
= int_mode_for_mode (omode
).require ();
11548 x
= gen_lowpart_common (imode
, x
);
11552 res
= lowpart_subreg (omode
, x
, imode
);
11558 return gen_rtx_CLOBBER (omode
, const0_rtx
);
11561 /* Try to simplify a comparison between OP0 and a constant OP1,
11562 where CODE is the comparison code that will be tested, into a
11563 (CODE OP0 const0_rtx) form.
11565 The result is a possibly different comparison code to use.
11566 *POP1 may be updated. */
11568 static enum rtx_code
11569 simplify_compare_const (enum rtx_code code
, machine_mode mode
,
11570 rtx op0
, rtx
*pop1
)
11572 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11573 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
11575 /* Get the constant we are comparing against and turn off all bits
11576 not on in our mode. */
11577 if (mode
!= VOIDmode
)
11578 const_op
= trunc_int_for_mode (const_op
, mode
);
11580 /* If we are comparing against a constant power of two and the value
11581 being compared can only have that single bit nonzero (e.g., it was
11582 `and'ed with that bit), we can replace this with a comparison
11585 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
11586 || code
== LT
|| code
== LTU
)
11587 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11588 && pow2p_hwi (const_op
& GET_MODE_MASK (mode
))
11589 && (nonzero_bits (op0
, mode
)
11590 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (mode
))))
11592 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
11596 /* Similarly, if we are comparing a value known to be either -1 or
11597 0 with -1, change it to the opposite comparison against zero. */
11599 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
11600 || code
== GEU
|| code
== LTU
)
11601 && num_sign_bit_copies (op0
, mode
) == mode_width
)
11603 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
11607 /* Do some canonicalizations based on the comparison code. We prefer
11608 comparisons against zero and then prefer equality comparisons.
11609 If we can reduce the size of a constant, we will do that too. */
11613 /* < C is equivalent to <= (C - 1) */
11618 /* ... fall through to LE case below. */
11619 gcc_fallthrough ();
11625 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11632 /* If we are doing a <= 0 comparison on a value known to have
11633 a zero sign bit, we can replace this with == 0. */
11634 else if (const_op
== 0
11635 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11636 && (nonzero_bits (op0
, mode
)
11637 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
11643 /* >= C is equivalent to > (C - 1). */
11648 /* ... fall through to GT below. */
11649 gcc_fallthrough ();
11655 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11662 /* If we are doing a > 0 comparison on a value known to have
11663 a zero sign bit, we can replace this with != 0. */
11664 else if (const_op
== 0
11665 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11666 && (nonzero_bits (op0
, mode
)
11667 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
11673 /* < C is equivalent to <= (C - 1). */
11678 /* ... fall through ... */
11680 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11681 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11682 && (unsigned HOST_WIDE_INT
) const_op
11683 == HOST_WIDE_INT_1U
<< (mode_width
- 1))
11693 /* unsigned <= 0 is equivalent to == 0 */
11696 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11697 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11698 && (unsigned HOST_WIDE_INT
) const_op
11699 == (HOST_WIDE_INT_1U
<< (mode_width
- 1)) - 1)
11707 /* >= C is equivalent to > (C - 1). */
11712 /* ... fall through ... */
11715 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11716 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11717 && (unsigned HOST_WIDE_INT
) const_op
11718 == HOST_WIDE_INT_1U
<< (mode_width
- 1))
11728 /* unsigned > 0 is equivalent to != 0 */
11731 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11732 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11733 && (unsigned HOST_WIDE_INT
) const_op
11734 == (HOST_WIDE_INT_1U
<< (mode_width
- 1)) - 1)
11745 *pop1
= GEN_INT (const_op
);
11749 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11750 comparison code that will be tested.
11752 The result is a possibly different comparison code to use. *POP0 and
11753 *POP1 may be updated.
11755 It is possible that we might detect that a comparison is either always
11756 true or always false. However, we do not perform general constant
11757 folding in combine, so this knowledge isn't useful. Such tautologies
11758 should have been detected earlier. Hence we ignore all such cases. */
11760 static enum rtx_code
11761 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
11767 scalar_int_mode mode
, inner_mode
;
11768 machine_mode tmode
;
11770 /* Try a few ways of applying the same transformation to both operands. */
11773 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11774 so check specially. */
11775 if (!WORD_REGISTER_OPERATIONS
11776 && code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
11777 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
11778 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11779 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
11780 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
11781 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
11782 && is_a
<scalar_int_mode
> (GET_MODE (op0
), &mode
)
11783 && (is_a
<scalar_int_mode
>
11784 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))), &inner_mode
))
11785 && inner_mode
== GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0)))
11786 && CONST_INT_P (XEXP (op0
, 1))
11787 && XEXP (op0
, 1) == XEXP (op1
, 1)
11788 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11789 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11790 && (INTVAL (XEXP (op0
, 1))
11791 == (GET_MODE_PRECISION (mode
)
11792 - GET_MODE_PRECISION (inner_mode
))))
11794 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11795 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11798 /* If both operands are the same constant shift, see if we can ignore the
11799 shift. We can if the shift is a rotate or if the bits shifted out of
11800 this shift are known to be zero for both inputs and if the type of
11801 comparison is compatible with the shift. */
11802 if (GET_CODE (op0
) == GET_CODE (op1
)
11803 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
11804 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11805 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11806 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11807 || (GET_CODE (op0
) == ASHIFTRT
11808 && (code
!= GTU
&& code
!= LTU
11809 && code
!= GEU
&& code
!= LEU
)))
11810 && CONST_INT_P (XEXP (op0
, 1))
11811 && INTVAL (XEXP (op0
, 1)) >= 0
11812 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11813 && XEXP (op0
, 1) == XEXP (op1
, 1))
11815 machine_mode mode
= GET_MODE (op0
);
11816 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11817 int shift_count
= INTVAL (XEXP (op0
, 1));
11819 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
11820 mask
&= (mask
>> shift_count
) << shift_count
;
11821 else if (GET_CODE (op0
) == ASHIFT
)
11822 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11824 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11825 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11826 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11831 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11832 SUBREGs are of the same mode, and, in both cases, the AND would
11833 be redundant if the comparison was done in the narrower mode,
11834 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11835 and the operand's possibly nonzero bits are 0xffffff01; in that case
11836 if we only care about QImode, we don't need the AND). This case
11837 occurs if the output mode of an scc insn is not SImode and
11838 STORE_FLAG_VALUE == 1 (e.g., the 386).
11840 Similarly, check for a case where the AND's are ZERO_EXTEND
11841 operations from some narrower mode even though a SUBREG is not
11844 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11845 && CONST_INT_P (XEXP (op0
, 1))
11846 && CONST_INT_P (XEXP (op1
, 1)))
11848 rtx inner_op0
= XEXP (op0
, 0);
11849 rtx inner_op1
= XEXP (op1
, 0);
11850 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11851 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11854 if (paradoxical_subreg_p (inner_op0
)
11855 && GET_CODE (inner_op1
) == SUBREG
11856 && (GET_MODE (SUBREG_REG (inner_op0
))
11857 == GET_MODE (SUBREG_REG (inner_op1
)))
11858 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11859 <= HOST_BITS_PER_WIDE_INT
)
11860 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11861 GET_MODE (SUBREG_REG (inner_op0
)))))
11862 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11863 GET_MODE (SUBREG_REG (inner_op1
))))))
11865 op0
= SUBREG_REG (inner_op0
);
11866 op1
= SUBREG_REG (inner_op1
);
11868 /* The resulting comparison is always unsigned since we masked
11869 off the original sign bit. */
11870 code
= unsigned_condition (code
);
11876 FOR_EACH_MODE_UNTIL (tmode
, GET_MODE (op0
))
11877 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11879 op0
= gen_lowpart_or_truncate (tmode
, inner_op0
);
11880 op1
= gen_lowpart_or_truncate (tmode
, inner_op1
);
11881 code
= unsigned_condition (code
);
11890 /* If both operands are NOT, we can strip off the outer operation
11891 and adjust the comparison code for swapped operands; similarly for
11892 NEG, except that this must be an equality comparison. */
11893 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11894 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
11895 && (code
== EQ
|| code
== NE
)))
11896 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
11902 /* If the first operand is a constant, swap the operands and adjust the
11903 comparison code appropriately, but don't do this if the second operand
11904 is already a constant integer. */
11905 if (swap_commutative_operands_p (op0
, op1
))
11907 std::swap (op0
, op1
);
11908 code
= swap_condition (code
);
11911 /* We now enter a loop during which we will try to simplify the comparison.
11912 For the most part, we only are concerned with comparisons with zero,
11913 but some things may really be comparisons with zero but not start
11914 out looking that way. */
11916 while (CONST_INT_P (op1
))
11918 machine_mode mode
= GET_MODE (op0
);
11919 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11920 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11921 int equality_comparison_p
;
11922 int sign_bit_comparison_p
;
11923 int unsigned_comparison_p
;
11924 HOST_WIDE_INT const_op
;
11926 /* We only want to handle integral modes. This catches VOIDmode,
11927 CCmode, and the floating-point modes. An exception is that we
11928 can handle VOIDmode if OP0 is a COMPARE or a comparison
11931 if (GET_MODE_CLASS (mode
) != MODE_INT
11932 && ! (mode
== VOIDmode
11933 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
11936 /* Try to simplify the compare to constant, possibly changing the
11937 comparison op, and/or changing op1 to zero. */
11938 code
= simplify_compare_const (code
, mode
, op0
, &op1
);
11939 const_op
= INTVAL (op1
);
11941 /* Compute some predicates to simplify code below. */
11943 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11944 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11945 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11948 /* If this is a sign bit comparison and we can do arithmetic in
11949 MODE, say that we will only be needing the sign bit of OP0. */
11950 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
11951 op0
= force_to_mode (op0
, mode
,
11953 << (GET_MODE_PRECISION (mode
) - 1),
11956 /* Now try cases based on the opcode of OP0. If none of the cases
11957 does a "continue", we exit this loop immediately after the
11960 switch (GET_CODE (op0
))
11963 /* If we are extracting a single bit from a variable position in
11964 a constant that has only a single bit set and are comparing it
11965 with zero, we can convert this into an equality comparison
11966 between the position and the location of the single bit. */
11967 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11968 have already reduced the shift count modulo the word size. */
11969 if (!SHIFT_COUNT_TRUNCATED
11970 && CONST_INT_P (XEXP (op0
, 0))
11971 && XEXP (op0
, 1) == const1_rtx
11972 && equality_comparison_p
&& const_op
== 0
11973 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11975 if (BITS_BIG_ENDIAN
)
11976 i
= BITS_PER_WORD
- 1 - i
;
11978 op0
= XEXP (op0
, 2);
11982 /* Result is nonzero iff shift count is equal to I. */
11983 code
= reverse_condition (code
);
11990 tem
= expand_compound_operation (op0
);
11999 /* If testing for equality, we can take the NOT of the constant. */
12000 if (equality_comparison_p
12001 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
12003 op0
= XEXP (op0
, 0);
12008 /* If just looking at the sign bit, reverse the sense of the
12010 if (sign_bit_comparison_p
)
12012 op0
= XEXP (op0
, 0);
12013 code
= (code
== GE
? LT
: GE
);
12019 /* If testing for equality, we can take the NEG of the constant. */
12020 if (equality_comparison_p
12021 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
12023 op0
= XEXP (op0
, 0);
12028 /* The remaining cases only apply to comparisons with zero. */
12032 /* When X is ABS or is known positive,
12033 (neg X) is < 0 if and only if X != 0. */
12035 if (sign_bit_comparison_p
12036 && (GET_CODE (XEXP (op0
, 0)) == ABS
12037 || (mode_width
<= HOST_BITS_PER_WIDE_INT
12038 && (nonzero_bits (XEXP (op0
, 0), mode
)
12039 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
12042 op0
= XEXP (op0
, 0);
12043 code
= (code
== LT
? NE
: EQ
);
12047 /* If we have NEG of something whose two high-order bits are the
12048 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12049 if (num_sign_bit_copies (op0
, mode
) >= 2)
12051 op0
= XEXP (op0
, 0);
12052 code
= swap_condition (code
);
12058 /* If we are testing equality and our count is a constant, we
12059 can perform the inverse operation on our RHS. */
12060 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12061 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
12062 op1
, XEXP (op0
, 1))) != 0)
12064 op0
= XEXP (op0
, 0);
12069 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12070 a particular bit. Convert it to an AND of a constant of that
12071 bit. This will be converted into a ZERO_EXTRACT. */
12072 if (const_op
== 0 && sign_bit_comparison_p
12073 && CONST_INT_P (XEXP (op0
, 1))
12074 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12076 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12079 - INTVAL (XEXP (op0
, 1)))));
12080 code
= (code
== LT
? NE
: EQ
);
12084 /* Fall through. */
12087 /* ABS is ignorable inside an equality comparison with zero. */
12088 if (const_op
== 0 && equality_comparison_p
)
12090 op0
= XEXP (op0
, 0);
12096 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12097 (compare FOO CONST) if CONST fits in FOO's mode and we
12098 are either testing inequality or have an unsigned
12099 comparison with ZERO_EXTEND or a signed comparison with
12100 SIGN_EXTEND. But don't do it if we don't have a compare
12101 insn of the given mode, since we'd have to revert it
12102 later on, and then we wouldn't know whether to sign- or
12104 mode
= GET_MODE (XEXP (op0
, 0));
12105 if (GET_MODE_CLASS (mode
) == MODE_INT
12106 && ! unsigned_comparison_p
12107 && HWI_COMPUTABLE_MODE_P (mode
)
12108 && trunc_int_for_mode (const_op
, mode
) == const_op
12109 && have_insn_for (COMPARE
, mode
))
12111 op0
= XEXP (op0
, 0);
12117 /* Check for the case where we are comparing A - C1 with C2, that is
12119 (subreg:MODE (plus (A) (-C1))) op (C2)
12121 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12122 comparison in the wider mode. One of the following two conditions
12123 must be true in order for this to be valid:
12125 1. The mode extension results in the same bit pattern being added
12126 on both sides and the comparison is equality or unsigned. As
12127 C2 has been truncated to fit in MODE, the pattern can only be
12130 2. The mode extension results in the sign bit being copied on
12133 The difficulty here is that we have predicates for A but not for
12134 (A - C1) so we need to check that C1 is within proper bounds so
12135 as to perturbate A as little as possible. */
12137 if (mode_width
<= HOST_BITS_PER_WIDE_INT
12138 && subreg_lowpart_p (op0
)
12139 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
12140 && GET_CODE (SUBREG_REG (op0
)) == PLUS
12141 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
12143 machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
12144 rtx a
= XEXP (SUBREG_REG (op0
), 0);
12145 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
12148 && (unsigned HOST_WIDE_INT
) c1
12149 < HOST_WIDE_INT_1U
<< (mode_width
- 1)
12150 && (equality_comparison_p
|| unsigned_comparison_p
)
12151 /* (A - C1) zero-extends if it is positive and sign-extends
12152 if it is negative, C2 both zero- and sign-extends. */
12153 && ((0 == (nonzero_bits (a
, inner_mode
)
12154 & ~GET_MODE_MASK (mode
))
12156 /* (A - C1) sign-extends if it is positive and 1-extends
12157 if it is negative, C2 both sign- and 1-extends. */
12158 || (num_sign_bit_copies (a
, inner_mode
)
12159 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12162 || ((unsigned HOST_WIDE_INT
) c1
12163 < HOST_WIDE_INT_1U
<< (mode_width
- 2)
12164 /* (A - C1) always sign-extends, like C2. */
12165 && num_sign_bit_copies (a
, inner_mode
)
12166 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12167 - (mode_width
- 1))))
12169 op0
= SUBREG_REG (op0
);
12174 /* If the inner mode is narrower and we are extracting the low part,
12175 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12176 if (paradoxical_subreg_p (op0
))
12178 else if (subreg_lowpart_p (op0
)
12179 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
12180 && is_int_mode (GET_MODE (SUBREG_REG (op0
)), &inner_mode
)
12181 && (code
== NE
|| code
== EQ
)
12182 && GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
12183 && !paradoxical_subreg_p (op0
)
12184 && (nonzero_bits (SUBREG_REG (op0
), inner_mode
)
12185 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12187 /* Remove outer subregs that don't do anything. */
12188 tem
= gen_lowpart (inner_mode
, op1
);
12190 if ((nonzero_bits (tem
, inner_mode
)
12191 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12193 op0
= SUBREG_REG (op0
);
12205 mode
= GET_MODE (XEXP (op0
, 0));
12206 if (GET_MODE_CLASS (mode
) == MODE_INT
12207 && (unsigned_comparison_p
|| equality_comparison_p
)
12208 && HWI_COMPUTABLE_MODE_P (mode
)
12209 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
12211 && have_insn_for (COMPARE
, mode
))
12213 op0
= XEXP (op0
, 0);
12219 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12220 this for equality comparisons due to pathological cases involving
12222 if (equality_comparison_p
12223 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
12224 op1
, XEXP (op0
, 1))))
12226 op0
= XEXP (op0
, 0);
12231 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12232 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
12233 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
12235 op0
= XEXP (XEXP (op0
, 0), 0);
12236 code
= (code
== LT
? EQ
: NE
);
12242 /* We used to optimize signed comparisons against zero, but that
12243 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12244 arrive here as equality comparisons, or (GEU, LTU) are
12245 optimized away. No need to special-case them. */
12247 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12248 (eq B (minus A C)), whichever simplifies. We can only do
12249 this for equality comparisons due to pathological cases involving
12251 if (equality_comparison_p
12252 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
12253 XEXP (op0
, 1), op1
)))
12255 op0
= XEXP (op0
, 0);
12260 if (equality_comparison_p
12261 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
12262 XEXP (op0
, 0), op1
)))
12264 op0
= XEXP (op0
, 1);
12269 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12270 of bits in X minus 1, is one iff X > 0. */
12271 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
12272 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12273 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
12274 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12276 op0
= XEXP (op0
, 1);
12277 code
= (code
== GE
? LE
: GT
);
12283 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12284 if C is zero or B is a constant. */
12285 if (equality_comparison_p
12286 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
12287 XEXP (op0
, 1), op1
)))
12289 op0
= XEXP (op0
, 0);
12296 case UNEQ
: case LTGT
:
12297 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
12298 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
12299 case UNORDERED
: case ORDERED
:
12300 /* We can't do anything if OP0 is a condition code value, rather
12301 than an actual data value. */
12303 || CC0_P (XEXP (op0
, 0))
12304 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
12307 /* Get the two operands being compared. */
12308 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
12309 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
12311 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
12313 /* Check for the cases where we simply want the result of the
12314 earlier test or the opposite of that result. */
12315 if (code
== NE
|| code
== EQ
12316 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
12317 && (code
== LT
|| code
== GE
)))
12319 enum rtx_code new_code
;
12320 if (code
== LT
|| code
== NE
)
12321 new_code
= GET_CODE (op0
);
12323 new_code
= reversed_comparison_code (op0
, NULL
);
12325 if (new_code
!= UNKNOWN
)
12336 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12338 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
12339 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
12340 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12342 op0
= XEXP (op0
, 1);
12343 code
= (code
== GE
? GT
: LE
);
12349 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12350 will be converted to a ZERO_EXTRACT later. */
12351 if (const_op
== 0 && equality_comparison_p
12352 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12353 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
12355 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
12356 XEXP (XEXP (op0
, 0), 1));
12357 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12361 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12362 zero and X is a comparison and C1 and C2 describe only bits set
12363 in STORE_FLAG_VALUE, we can compare with X. */
12364 if (const_op
== 0 && equality_comparison_p
12365 && mode_width
<= HOST_BITS_PER_WIDE_INT
12366 && CONST_INT_P (XEXP (op0
, 1))
12367 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
12368 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12369 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
12370 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
12372 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12373 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
12374 if ((~STORE_FLAG_VALUE
& mask
) == 0
12375 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
12376 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
12377 && COMPARISON_P (tem
))))
12379 op0
= XEXP (XEXP (op0
, 0), 0);
12384 /* If we are doing an equality comparison of an AND of a bit equal
12385 to the sign bit, replace this with a LT or GE comparison of
12386 the underlying value. */
12387 if (equality_comparison_p
12389 && CONST_INT_P (XEXP (op0
, 1))
12390 && mode_width
<= HOST_BITS_PER_WIDE_INT
12391 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12392 == HOST_WIDE_INT_1U
<< (mode_width
- 1)))
12394 op0
= XEXP (op0
, 0);
12395 code
= (code
== EQ
? GE
: LT
);
12399 /* If this AND operation is really a ZERO_EXTEND from a narrower
12400 mode, the constant fits within that mode, and this is either an
12401 equality or unsigned comparison, try to do this comparison in
12406 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12407 -> (ne:DI (reg:SI 4) (const_int 0))
12409 unless TRULY_NOOP_TRUNCATION allows it or the register is
12410 known to hold a value of the required mode the
12411 transformation is invalid. */
12412 if ((equality_comparison_p
|| unsigned_comparison_p
)
12413 && CONST_INT_P (XEXP (op0
, 1))
12414 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
12415 & GET_MODE_MASK (mode
))
12417 && const_op
>> i
== 0
12418 && int_mode_for_size (i
, 1).exists (&tmode
))
12420 op0
= gen_lowpart_or_truncate (tmode
, XEXP (op0
, 0));
12424 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12425 fits in both M1 and M2 and the SUBREG is either paradoxical
12426 or represents the low part, permute the SUBREG and the AND
12428 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
12429 && CONST_INT_P (XEXP (op0
, 1)))
12431 unsigned HOST_WIDE_INT c1
= INTVAL (XEXP (op0
, 1));
12432 /* Require an integral mode, to avoid creating something like
12434 if ((is_a
<scalar_int_mode
>
12435 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))), &tmode
))
12436 /* It is unsafe to commute the AND into the SUBREG if the
12437 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12438 not defined. As originally written the upper bits
12439 have a defined value due to the AND operation.
12440 However, if we commute the AND inside the SUBREG then
12441 they no longer have defined values and the meaning of
12442 the code has been changed.
12443 Also C1 should not change value in the smaller mode,
12444 see PR67028 (a positive C1 can become negative in the
12445 smaller mode, so that the AND does no longer mask the
12447 && ((WORD_REGISTER_OPERATIONS
12448 && mode_width
> GET_MODE_PRECISION (tmode
)
12449 && mode_width
<= BITS_PER_WORD
12450 && trunc_int_for_mode (c1
, tmode
) == (HOST_WIDE_INT
) c1
)
12451 || (mode_width
<= GET_MODE_PRECISION (tmode
)
12452 && subreg_lowpart_p (XEXP (op0
, 0))))
12453 && mode_width
<= HOST_BITS_PER_WIDE_INT
12454 && HWI_COMPUTABLE_MODE_P (tmode
)
12455 && (c1
& ~mask
) == 0
12456 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
12458 && c1
!= GET_MODE_MASK (tmode
))
12460 op0
= simplify_gen_binary (AND
, tmode
,
12461 SUBREG_REG (XEXP (op0
, 0)),
12462 gen_int_mode (c1
, tmode
));
12463 op0
= gen_lowpart (mode
, op0
);
12468 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12469 if (const_op
== 0 && equality_comparison_p
12470 && XEXP (op0
, 1) == const1_rtx
12471 && GET_CODE (XEXP (op0
, 0)) == NOT
)
12473 op0
= simplify_and_const_int (NULL_RTX
, mode
,
12474 XEXP (XEXP (op0
, 0), 0), 1);
12475 code
= (code
== NE
? EQ
: NE
);
12479 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12480 (eq (and (lshiftrt X) 1) 0).
12481 Also handle the case where (not X) is expressed using xor. */
12482 if (const_op
== 0 && equality_comparison_p
12483 && XEXP (op0
, 1) == const1_rtx
12484 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
12486 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
12487 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
12489 if (GET_CODE (shift_op
) == NOT
12490 || (GET_CODE (shift_op
) == XOR
12491 && CONST_INT_P (XEXP (shift_op
, 1))
12492 && CONST_INT_P (shift_count
)
12493 && HWI_COMPUTABLE_MODE_P (mode
)
12494 && (UINTVAL (XEXP (shift_op
, 1))
12495 == HOST_WIDE_INT_1U
12496 << INTVAL (shift_count
))))
12499 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
12500 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12501 code
= (code
== NE
? EQ
: NE
);
12508 /* If we have (compare (ashift FOO N) (const_int C)) and
12509 the high order N bits of FOO (N+1 if an inequality comparison)
12510 are known to be zero, we can do this by comparing FOO with C
12511 shifted right N bits so long as the low-order N bits of C are
12513 if (CONST_INT_P (XEXP (op0
, 1))
12514 && INTVAL (XEXP (op0
, 1)) >= 0
12515 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
12516 < HOST_BITS_PER_WIDE_INT
)
12517 && (((unsigned HOST_WIDE_INT
) const_op
12518 & ((HOST_WIDE_INT_1U
<< INTVAL (XEXP (op0
, 1)))
12520 && mode_width
<= HOST_BITS_PER_WIDE_INT
12521 && (nonzero_bits (XEXP (op0
, 0), mode
)
12522 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
12523 + ! equality_comparison_p
))) == 0)
12525 /* We must perform a logical shift, not an arithmetic one,
12526 as we want the top N bits of C to be zero. */
12527 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
12529 temp
>>= INTVAL (XEXP (op0
, 1));
12530 op1
= gen_int_mode (temp
, mode
);
12531 op0
= XEXP (op0
, 0);
12535 /* If we are doing a sign bit comparison, it means we are testing
12536 a particular bit. Convert it to the appropriate AND. */
12537 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12538 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12540 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12543 - INTVAL (XEXP (op0
, 1)))));
12544 code
= (code
== LT
? NE
: EQ
);
12548 /* If this an equality comparison with zero and we are shifting
12549 the low bit to the sign bit, we can convert this to an AND of the
12551 if (const_op
== 0 && equality_comparison_p
12552 && CONST_INT_P (XEXP (op0
, 1))
12553 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12555 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
12561 /* If this is an equality comparison with zero, we can do this
12562 as a logical shift, which might be much simpler. */
12563 if (equality_comparison_p
&& const_op
== 0
12564 && CONST_INT_P (XEXP (op0
, 1)))
12566 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
12568 INTVAL (XEXP (op0
, 1)));
12572 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12573 do the comparison in a narrower mode. */
12574 if (! unsigned_comparison_p
12575 && CONST_INT_P (XEXP (op0
, 1))
12576 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12577 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
12578 && (int_mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)), 1)
12580 && (((unsigned HOST_WIDE_INT
) const_op
12581 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12582 <= GET_MODE_MASK (tmode
)))
12584 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
12588 /* Likewise if OP0 is a PLUS of a sign extension with a
12589 constant, which is usually represented with the PLUS
12590 between the shifts. */
12591 if (! unsigned_comparison_p
12592 && CONST_INT_P (XEXP (op0
, 1))
12593 && GET_CODE (XEXP (op0
, 0)) == PLUS
12594 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12595 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
12596 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
12597 && (int_mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)), 1)
12599 && (((unsigned HOST_WIDE_INT
) const_op
12600 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12601 <= GET_MODE_MASK (tmode
)))
12603 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
12604 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
12605 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
12606 add_const
, XEXP (op0
, 1));
12608 op0
= simplify_gen_binary (PLUS
, tmode
,
12609 gen_lowpart (tmode
, inner
),
12616 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12617 the low order N bits of FOO are known to be zero, we can do this
12618 by comparing FOO with C shifted left N bits so long as no
12619 overflow occurs. Even if the low order N bits of FOO aren't known
12620 to be zero, if the comparison is >= or < we can use the same
12621 optimization and for > or <= by setting all the low
12622 order N bits in the comparison constant. */
12623 if (CONST_INT_P (XEXP (op0
, 1))
12624 && INTVAL (XEXP (op0
, 1)) > 0
12625 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12626 && mode_width
<= HOST_BITS_PER_WIDE_INT
12627 && (((unsigned HOST_WIDE_INT
) const_op
12628 + (GET_CODE (op0
) != LSHIFTRT
12629 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
12632 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
12634 unsigned HOST_WIDE_INT low_bits
12635 = (nonzero_bits (XEXP (op0
, 0), mode
)
12636 & ((HOST_WIDE_INT_1U
12637 << INTVAL (XEXP (op0
, 1))) - 1));
12638 if (low_bits
== 0 || !equality_comparison_p
)
12640 /* If the shift was logical, then we must make the condition
12642 if (GET_CODE (op0
) == LSHIFTRT
)
12643 code
= unsigned_condition (code
);
12645 const_op
= (unsigned HOST_WIDE_INT
) const_op
12646 << INTVAL (XEXP (op0
, 1));
12648 && (code
== GT
|| code
== GTU
12649 || code
== LE
|| code
== LEU
))
12651 |= ((HOST_WIDE_INT_1
<< INTVAL (XEXP (op0
, 1))) - 1);
12652 op1
= GEN_INT (const_op
);
12653 op0
= XEXP (op0
, 0);
12658 /* If we are using this shift to extract just the sign bit, we
12659 can replace this with an LT or GE comparison. */
12661 && (equality_comparison_p
|| sign_bit_comparison_p
)
12662 && CONST_INT_P (XEXP (op0
, 1))
12663 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12665 op0
= XEXP (op0
, 0);
12666 code
= (code
== NE
|| code
== GT
? LT
: GE
);
12678 /* Now make any compound operations involved in this comparison. Then,
12679 check for an outmost SUBREG on OP0 that is not doing anything or is
12680 paradoxical. The latter transformation must only be performed when
12681 it is known that the "extra" bits will be the same in op0 and op1 or
12682 that they don't matter. There are three cases to consider:
12684 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12685 care bits and we can assume they have any convenient value. So
12686 making the transformation is safe.
12688 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12689 In this case the upper bits of op0 are undefined. We should not make
12690 the simplification in that case as we do not know the contents of
12693 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12694 In that case we know those bits are zeros or ones. We must also be
12695 sure that they are the same as the upper bits of op1.
12697 We can never remove a SUBREG for a non-equality comparison because
12698 the sign bit is in a different place in the underlying object. */
12700 rtx_code op0_mco_code
= SET
;
12701 if (op1
== const0_rtx
)
12702 op0_mco_code
= code
== NE
|| code
== EQ
? EQ
: COMPARE
;
12704 op0
= make_compound_operation (op0
, op0_mco_code
);
12705 op1
= make_compound_operation (op1
, SET
);
12707 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
12708 && is_int_mode (GET_MODE (op0
), &mode
)
12709 && is_int_mode (GET_MODE (SUBREG_REG (op0
)), &inner_mode
)
12710 && (code
== NE
|| code
== EQ
))
12712 if (paradoxical_subreg_p (op0
))
12714 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12716 if (REG_P (SUBREG_REG (op0
)))
12718 op0
= SUBREG_REG (op0
);
12719 op1
= gen_lowpart (inner_mode
, op1
);
12722 else if (GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
12723 && (nonzero_bits (SUBREG_REG (op0
), inner_mode
)
12724 & ~GET_MODE_MASK (mode
)) == 0)
12726 tem
= gen_lowpart (inner_mode
, op1
);
12728 if ((nonzero_bits (tem
, inner_mode
) & ~GET_MODE_MASK (mode
)) == 0)
12729 op0
= SUBREG_REG (op0
), op1
= tem
;
12733 /* We now do the opposite procedure: Some machines don't have compare
12734 insns in all modes. If OP0's mode is an integer mode smaller than a
12735 word and we can't do a compare in that mode, see if there is a larger
12736 mode for which we can do the compare. There are a number of cases in
12737 which we can use the wider mode. */
12739 if (is_int_mode (GET_MODE (op0
), &mode
)
12740 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
12741 && ! have_insn_for (COMPARE
, mode
))
12742 FOR_EACH_WIDER_MODE (tmode
, mode
)
12744 if (!HWI_COMPUTABLE_MODE_P (tmode
))
12746 if (have_insn_for (COMPARE
, tmode
))
12750 /* If this is a test for negative, we can make an explicit
12751 test of the sign bit. Test this first so we can use
12752 a paradoxical subreg to extend OP0. */
12754 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
12755 && HWI_COMPUTABLE_MODE_P (mode
))
12757 unsigned HOST_WIDE_INT sign
12758 = HOST_WIDE_INT_1U
<< (GET_MODE_BITSIZE (mode
) - 1);
12759 op0
= simplify_gen_binary (AND
, tmode
,
12760 gen_lowpart (tmode
, op0
),
12761 gen_int_mode (sign
, tmode
));
12762 code
= (code
== LT
) ? NE
: EQ
;
12766 /* If the only nonzero bits in OP0 and OP1 are those in the
12767 narrower mode and this is an equality or unsigned comparison,
12768 we can use the wider mode. Similarly for sign-extended
12769 values, in which case it is true for all comparisons. */
12770 zero_extended
= ((code
== EQ
|| code
== NE
12771 || code
== GEU
|| code
== GTU
12772 || code
== LEU
|| code
== LTU
)
12773 && (nonzero_bits (op0
, tmode
)
12774 & ~GET_MODE_MASK (mode
)) == 0
12775 && ((CONST_INT_P (op1
)
12776 || (nonzero_bits (op1
, tmode
)
12777 & ~GET_MODE_MASK (mode
)) == 0)));
12780 || ((num_sign_bit_copies (op0
, tmode
)
12781 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12782 - GET_MODE_PRECISION (mode
)))
12783 && (num_sign_bit_copies (op1
, tmode
)
12784 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12785 - GET_MODE_PRECISION (mode
)))))
12787 /* If OP0 is an AND and we don't have an AND in MODE either,
12788 make a new AND in the proper mode. */
12789 if (GET_CODE (op0
) == AND
12790 && !have_insn_for (AND
, mode
))
12791 op0
= simplify_gen_binary (AND
, tmode
,
12792 gen_lowpart (tmode
,
12794 gen_lowpart (tmode
,
12800 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
,
12802 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
,
12807 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
,
12809 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
,
12818 /* We may have changed the comparison operands. Re-canonicalize. */
12819 if (swap_commutative_operands_p (op0
, op1
))
12821 std::swap (op0
, op1
);
12822 code
= swap_condition (code
);
12825 /* If this machine only supports a subset of valid comparisons, see if we
12826 can convert an unsupported one into a supported one. */
12827 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
12835 /* Utility function for record_value_for_reg. Count number of
12840 enum rtx_code code
= GET_CODE (x
);
12844 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
12845 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
12847 rtx x0
= XEXP (x
, 0);
12848 rtx x1
= XEXP (x
, 1);
12851 return 1 + 2 * count_rtxs (x0
);
12853 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
12854 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
12855 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12856 return 2 + 2 * count_rtxs (x0
)
12857 + count_rtxs (x
== XEXP (x1
, 0)
12858 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12860 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
12861 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
12862 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12863 return 2 + 2 * count_rtxs (x1
)
12864 + count_rtxs (x
== XEXP (x0
, 0)
12865 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12868 fmt
= GET_RTX_FORMAT (code
);
12869 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12871 ret
+= count_rtxs (XEXP (x
, i
));
12872 else if (fmt
[i
] == 'E')
12873 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12874 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12879 /* Utility function for following routine. Called when X is part of a value
12880 being stored into last_set_value. Sets last_set_table_tick
12881 for each register mentioned. Similar to mention_regs in cse.c */
12884 update_table_tick (rtx x
)
12886 enum rtx_code code
= GET_CODE (x
);
12887 const char *fmt
= GET_RTX_FORMAT (code
);
12892 unsigned int regno
= REGNO (x
);
12893 unsigned int endregno
= END_REGNO (x
);
12896 for (r
= regno
; r
< endregno
; r
++)
12898 reg_stat_type
*rsp
= ®_stat
[r
];
12899 rsp
->last_set_table_tick
= label_tick
;
12905 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12908 /* Check for identical subexpressions. If x contains
12909 identical subexpression we only have to traverse one of
12911 if (i
== 0 && ARITHMETIC_P (x
))
12913 /* Note that at this point x1 has already been
12915 rtx x0
= XEXP (x
, 0);
12916 rtx x1
= XEXP (x
, 1);
12918 /* If x0 and x1 are identical then there is no need to
12923 /* If x0 is identical to a subexpression of x1 then while
12924 processing x1, x0 has already been processed. Thus we
12925 are done with x. */
12926 if (ARITHMETIC_P (x1
)
12927 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12930 /* If x1 is identical to a subexpression of x0 then we
12931 still have to process the rest of x0. */
12932 if (ARITHMETIC_P (x0
)
12933 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12935 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12940 update_table_tick (XEXP (x
, i
));
12942 else if (fmt
[i
] == 'E')
12943 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12944 update_table_tick (XVECEXP (x
, i
, j
));
12947 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12948 are saying that the register is clobbered and we no longer know its
12949 value. If INSN is zero, don't update reg_stat[].last_set; this is
12950 only permitted with VALUE also zero and is used to invalidate the
12954 record_value_for_reg (rtx reg
, rtx_insn
*insn
, rtx value
)
12956 unsigned int regno
= REGNO (reg
);
12957 unsigned int endregno
= END_REGNO (reg
);
12959 reg_stat_type
*rsp
;
12961 /* If VALUE contains REG and we have a previous value for REG, substitute
12962 the previous value. */
12963 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12967 /* Set things up so get_last_value is allowed to see anything set up to
12969 subst_low_luid
= DF_INSN_LUID (insn
);
12970 tem
= get_last_value (reg
);
12972 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12973 it isn't going to be useful and will take a lot of time to process,
12974 so just use the CLOBBER. */
12978 if (ARITHMETIC_P (tem
)
12979 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12980 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12981 tem
= XEXP (tem
, 0);
12982 else if (count_occurrences (value
, reg
, 1) >= 2)
12984 /* If there are two or more occurrences of REG in VALUE,
12985 prevent the value from growing too much. */
12986 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12987 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12990 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12994 /* For each register modified, show we don't know its value, that
12995 we don't know about its bitwise content, that its value has been
12996 updated, and that we don't know the location of the death of the
12998 for (i
= regno
; i
< endregno
; i
++)
13000 rsp
= ®_stat
[i
];
13003 rsp
->last_set
= insn
;
13005 rsp
->last_set_value
= 0;
13006 rsp
->last_set_mode
= VOIDmode
;
13007 rsp
->last_set_nonzero_bits
= 0;
13008 rsp
->last_set_sign_bit_copies
= 0;
13009 rsp
->last_death
= 0;
13010 rsp
->truncated_to_mode
= VOIDmode
;
13013 /* Mark registers that are being referenced in this value. */
13015 update_table_tick (value
);
13017 /* Now update the status of each register being set.
13018 If someone is using this register in this block, set this register
13019 to invalid since we will get confused between the two lives in this
13020 basic block. This makes using this register always invalid. In cse, we
13021 scan the table to invalidate all entries using this register, but this
13022 is too much work for us. */
13024 for (i
= regno
; i
< endregno
; i
++)
13026 rsp
= ®_stat
[i
];
13027 rsp
->last_set_label
= label_tick
;
13029 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
13030 rsp
->last_set_invalid
= 1;
13032 rsp
->last_set_invalid
= 0;
13035 /* The value being assigned might refer to X (like in "x++;"). In that
13036 case, we must replace it with (clobber (const_int 0)) to prevent
13038 rsp
= ®_stat
[regno
];
13039 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
13041 value
= copy_rtx (value
);
13042 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
13046 /* For the main register being modified, update the value, the mode, the
13047 nonzero bits, and the number of sign bit copies. */
13049 rsp
->last_set_value
= value
;
13053 machine_mode mode
= GET_MODE (reg
);
13054 subst_low_luid
= DF_INSN_LUID (insn
);
13055 rsp
->last_set_mode
= mode
;
13056 if (GET_MODE_CLASS (mode
) == MODE_INT
13057 && HWI_COMPUTABLE_MODE_P (mode
))
13058 mode
= nonzero_bits_mode
;
13059 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
13060 rsp
->last_set_sign_bit_copies
13061 = num_sign_bit_copies (value
, GET_MODE (reg
));
13065 /* Called via note_stores from record_dead_and_set_regs to handle one
13066 SET or CLOBBER in an insn. DATA is the instruction in which the
13067 set is occurring. */
13070 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
13072 rtx_insn
*record_dead_insn
= (rtx_insn
*) data
;
13074 if (GET_CODE (dest
) == SUBREG
)
13075 dest
= SUBREG_REG (dest
);
13077 if (!record_dead_insn
)
13080 record_value_for_reg (dest
, NULL
, NULL_RTX
);
13086 /* If we are setting the whole register, we know its value. Otherwise
13087 show that we don't know the value. We can handle SUBREG in
13089 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
13090 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
13091 else if (GET_CODE (setter
) == SET
13092 && GET_CODE (SET_DEST (setter
)) == SUBREG
13093 && SUBREG_REG (SET_DEST (setter
)) == dest
13094 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
13095 && subreg_lowpart_p (SET_DEST (setter
)))
13096 record_value_for_reg (dest
, record_dead_insn
,
13097 gen_lowpart (GET_MODE (dest
),
13098 SET_SRC (setter
)));
13100 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
13102 else if (MEM_P (dest
)
13103 /* Ignore pushes, they clobber nothing. */
13104 && ! push_operand (dest
, GET_MODE (dest
)))
13105 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
13108 /* Update the records of when each REG was most recently set or killed
13109 for the things done by INSN. This is the last thing done in processing
13110 INSN in the combiner loop.
13112 We update reg_stat[], in particular fields last_set, last_set_value,
13113 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13114 last_death, and also the similar information mem_last_set (which insn
13115 most recently modified memory) and last_call_luid (which insn was the
13116 most recent subroutine call). */
13119 record_dead_and_set_regs (rtx_insn
*insn
)
13124 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
13126 if (REG_NOTE_KIND (link
) == REG_DEAD
13127 && REG_P (XEXP (link
, 0)))
13129 unsigned int regno
= REGNO (XEXP (link
, 0));
13130 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
13132 for (i
= regno
; i
< endregno
; i
++)
13134 reg_stat_type
*rsp
;
13136 rsp
= ®_stat
[i
];
13137 rsp
->last_death
= insn
;
13140 else if (REG_NOTE_KIND (link
) == REG_INC
)
13141 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
13146 hard_reg_set_iterator hrsi
;
13147 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
13149 reg_stat_type
*rsp
;
13151 rsp
= ®_stat
[i
];
13152 rsp
->last_set_invalid
= 1;
13153 rsp
->last_set
= insn
;
13154 rsp
->last_set_value
= 0;
13155 rsp
->last_set_mode
= VOIDmode
;
13156 rsp
->last_set_nonzero_bits
= 0;
13157 rsp
->last_set_sign_bit_copies
= 0;
13158 rsp
->last_death
= 0;
13159 rsp
->truncated_to_mode
= VOIDmode
;
13162 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
13164 /* We can't combine into a call pattern. Remember, though, that
13165 the return value register is set at this LUID. We could
13166 still replace a register with the return value from the
13167 wrong subroutine call! */
13168 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
13171 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
13174 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13175 register present in the SUBREG, so for each such SUBREG go back and
13176 adjust nonzero and sign bit information of the registers that are
13177 known to have some zero/sign bits set.
13179 This is needed because when combine blows the SUBREGs away, the
13180 information on zero/sign bits is lost and further combines can be
13181 missed because of that. */
13184 record_promoted_value (rtx_insn
*insn
, rtx subreg
)
13186 struct insn_link
*links
;
13188 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
13189 machine_mode mode
= GET_MODE (subreg
);
13191 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
13194 for (links
= LOG_LINKS (insn
); links
;)
13196 reg_stat_type
*rsp
;
13198 insn
= links
->insn
;
13199 set
= single_set (insn
);
13201 if (! set
|| !REG_P (SET_DEST (set
))
13202 || REGNO (SET_DEST (set
)) != regno
13203 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
13205 links
= links
->next
;
13209 rsp
= ®_stat
[regno
];
13210 if (rsp
->last_set
== insn
)
13212 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
13213 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
13216 if (REG_P (SET_SRC (set
)))
13218 regno
= REGNO (SET_SRC (set
));
13219 links
= LOG_LINKS (insn
);
13226 /* Check if X, a register, is known to contain a value already
13227 truncated to MODE. In this case we can use a subreg to refer to
13228 the truncated value even though in the generic case we would need
13229 an explicit truncation. */
13232 reg_truncated_to_mode (machine_mode mode
, const_rtx x
)
13234 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
13235 machine_mode truncated
= rsp
->truncated_to_mode
;
13238 || rsp
->truncation_label
< label_tick_ebb_start
)
13240 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
13242 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
13247 /* If X is a hard reg or a subreg record the mode that the register is
13248 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
13249 to turn a truncate into a subreg using this information. Return true
13250 if traversing X is complete. */
13253 record_truncated_value (rtx x
)
13255 machine_mode truncated_mode
;
13256 reg_stat_type
*rsp
;
13258 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
13260 machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
13261 truncated_mode
= GET_MODE (x
);
13263 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
13266 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
13269 x
= SUBREG_REG (x
);
13271 /* ??? For hard-regs we now record everything. We might be able to
13272 optimize this using last_set_mode. */
13273 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
13274 truncated_mode
= GET_MODE (x
);
13278 rsp
= ®_stat
[REGNO (x
)];
13279 if (rsp
->truncated_to_mode
== 0
13280 || rsp
->truncation_label
< label_tick_ebb_start
13281 || (GET_MODE_SIZE (truncated_mode
)
13282 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
13284 rsp
->truncated_to_mode
= truncated_mode
;
13285 rsp
->truncation_label
= label_tick
;
13291 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13292 the modes they are used in. This can help truning TRUNCATEs into
13296 record_truncated_values (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
13298 subrtx_var_iterator::array_type array
;
13299 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
13300 if (record_truncated_value (*iter
))
13301 iter
.skip_subrtxes ();
13304 /* Scan X for promoted SUBREGs. For each one found,
13305 note what it implies to the registers used in it. */
13308 check_promoted_subreg (rtx_insn
*insn
, rtx x
)
13310 if (GET_CODE (x
) == SUBREG
13311 && SUBREG_PROMOTED_VAR_P (x
)
13312 && REG_P (SUBREG_REG (x
)))
13313 record_promoted_value (insn
, x
);
13316 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
13319 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
13323 check_promoted_subreg (insn
, XEXP (x
, i
));
13327 if (XVEC (x
, i
) != 0)
13328 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13329 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
13335 /* Verify that all the registers and memory references mentioned in *LOC are
13336 still valid. *LOC was part of a value set in INSN when label_tick was
13337 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13338 the invalid references with (clobber (const_int 0)) and return 1. This
13339 replacement is useful because we often can get useful information about
13340 the form of a value (e.g., if it was produced by a shift that always
13341 produces -1 or 0) even though we don't know exactly what registers it
13342 was produced from. */
13345 get_last_value_validate (rtx
*loc
, rtx_insn
*insn
, int tick
, int replace
)
13348 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
13349 int len
= GET_RTX_LENGTH (GET_CODE (x
));
13354 unsigned int regno
= REGNO (x
);
13355 unsigned int endregno
= END_REGNO (x
);
13358 for (j
= regno
; j
< endregno
; j
++)
13360 reg_stat_type
*rsp
= ®_stat
[j
];
13361 if (rsp
->last_set_invalid
13362 /* If this is a pseudo-register that was only set once and not
13363 live at the beginning of the function, it is always valid. */
13364 || (! (regno
>= FIRST_PSEUDO_REGISTER
13365 && regno
< reg_n_sets_max
13366 && REG_N_SETS (regno
) == 1
13367 && (!REGNO_REG_SET_P
13368 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
13370 && rsp
->last_set_label
> tick
))
13373 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13380 /* If this is a memory reference, make sure that there were no stores after
13381 it that might have clobbered the value. We don't have alias info, so we
13382 assume any store invalidates it. Moreover, we only have local UIDs, so
13383 we also assume that there were stores in the intervening basic blocks. */
13384 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
13385 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
13388 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13392 for (i
= 0; i
< len
; i
++)
13396 /* Check for identical subexpressions. If x contains
13397 identical subexpression we only have to traverse one of
13399 if (i
== 1 && ARITHMETIC_P (x
))
13401 /* Note that at this point x0 has already been checked
13402 and found valid. */
13403 rtx x0
= XEXP (x
, 0);
13404 rtx x1
= XEXP (x
, 1);
13406 /* If x0 and x1 are identical then x is also valid. */
13410 /* If x1 is identical to a subexpression of x0 then
13411 while checking x0, x1 has already been checked. Thus
13412 it is valid and so as x. */
13413 if (ARITHMETIC_P (x0
)
13414 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13417 /* If x0 is identical to a subexpression of x1 then x is
13418 valid iff the rest of x1 is valid. */
13419 if (ARITHMETIC_P (x1
)
13420 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13422 get_last_value_validate (&XEXP (x1
,
13423 x0
== XEXP (x1
, 0) ? 1 : 0),
13424 insn
, tick
, replace
);
13427 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
13431 else if (fmt
[i
] == 'E')
13432 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13433 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
13434 insn
, tick
, replace
) == 0)
13438 /* If we haven't found a reason for it to be invalid, it is valid. */
13442 /* Get the last value assigned to X, if known. Some registers
13443 in the value may be replaced with (clobber (const_int 0)) if their value
13444 is known longer known reliably. */
13447 get_last_value (const_rtx x
)
13449 unsigned int regno
;
13451 reg_stat_type
*rsp
;
13453 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13454 then convert it to the desired mode. If this is a paradoxical SUBREG,
13455 we cannot predict what values the "extra" bits might have. */
13456 if (GET_CODE (x
) == SUBREG
13457 && subreg_lowpart_p (x
)
13458 && !paradoxical_subreg_p (x
)
13459 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
13460 return gen_lowpart (GET_MODE (x
), value
);
13466 rsp
= ®_stat
[regno
];
13467 value
= rsp
->last_set_value
;
13469 /* If we don't have a value, or if it isn't for this basic block and
13470 it's either a hard register, set more than once, or it's a live
13471 at the beginning of the function, return 0.
13473 Because if it's not live at the beginning of the function then the reg
13474 is always set before being used (is never used without being set).
13475 And, if it's set only once, and it's always set before use, then all
13476 uses must have the same last value, even if it's not from this basic
13480 || (rsp
->last_set_label
< label_tick_ebb_start
13481 && (regno
< FIRST_PSEUDO_REGISTER
13482 || regno
>= reg_n_sets_max
13483 || REG_N_SETS (regno
) != 1
13485 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
13488 /* If the value was set in a later insn than the ones we are processing,
13489 we can't use it even if the register was only set once. */
13490 if (rsp
->last_set_label
== label_tick
13491 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
13494 /* If fewer bits were set than what we are asked for now, we cannot use
13496 if (GET_MODE_PRECISION (rsp
->last_set_mode
)
13497 < GET_MODE_PRECISION (GET_MODE (x
)))
13500 /* If the value has all its registers valid, return it. */
13501 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
13504 /* Otherwise, make a copy and replace any invalid register with
13505 (clobber (const_int 0)). If that fails for some reason, return 0. */
13507 value
= copy_rtx (value
);
13508 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
13514 /* Return nonzero if expression X refers to a REG or to memory
13515 that is set in an instruction more recent than FROM_LUID. */
13518 use_crosses_set_p (const_rtx x
, int from_luid
)
13522 enum rtx_code code
= GET_CODE (x
);
13526 unsigned int regno
= REGNO (x
);
13527 unsigned endreg
= END_REGNO (x
);
13529 #ifdef PUSH_ROUNDING
13530 /* Don't allow uses of the stack pointer to be moved,
13531 because we don't know whether the move crosses a push insn. */
13532 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
13535 for (; regno
< endreg
; regno
++)
13537 reg_stat_type
*rsp
= ®_stat
[regno
];
13539 && rsp
->last_set_label
== label_tick
13540 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
13546 if (code
== MEM
&& mem_last_set
> from_luid
)
13549 fmt
= GET_RTX_FORMAT (code
);
13551 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13556 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13557 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
13560 else if (fmt
[i
] == 'e'
13561 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
13567 /* Define three variables used for communication between the following
13570 static unsigned int reg_dead_regno
, reg_dead_endregno
;
13571 static int reg_dead_flag
;
13573 /* Function called via note_stores from reg_dead_at_p.
13575 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13576 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13579 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
13581 unsigned int regno
, endregno
;
13586 regno
= REGNO (dest
);
13587 endregno
= END_REGNO (dest
);
13588 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
13589 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
13592 /* Return nonzero if REG is known to be dead at INSN.
13594 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13595 referencing REG, it is dead. If we hit a SET referencing REG, it is
13596 live. Otherwise, see if it is live or dead at the start of the basic
13597 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13598 must be assumed to be always live. */
13601 reg_dead_at_p (rtx reg
, rtx_insn
*insn
)
13606 /* Set variables for reg_dead_at_p_1. */
13607 reg_dead_regno
= REGNO (reg
);
13608 reg_dead_endregno
= END_REGNO (reg
);
13612 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13613 we allow the machine description to decide whether use-and-clobber
13614 patterns are OK. */
13615 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
13617 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13618 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
13622 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13623 beginning of basic block. */
13624 block
= BLOCK_FOR_INSN (insn
);
13629 if (find_regno_note (insn
, REG_UNUSED
, reg_dead_regno
))
13632 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
13634 return reg_dead_flag
== 1 ? 1 : 0;
13636 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
13640 if (insn
== BB_HEAD (block
))
13643 insn
= PREV_INSN (insn
);
13646 /* Look at live-in sets for the basic block that we were in. */
13647 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13648 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
13654 /* Note hard registers in X that are used. */
13657 mark_used_regs_combine (rtx x
)
13659 RTX_CODE code
= GET_CODE (x
);
13660 unsigned int regno
;
13671 case ADDR_DIFF_VEC
:
13673 /* CC0 must die in the insn after it is set, so we don't need to take
13674 special note of it here. */
13679 /* If we are clobbering a MEM, mark any hard registers inside the
13680 address as used. */
13681 if (MEM_P (XEXP (x
, 0)))
13682 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
13687 /* A hard reg in a wide mode may really be multiple registers.
13688 If so, mark all of them just like the first. */
13689 if (regno
< FIRST_PSEUDO_REGISTER
)
13691 /* None of this applies to the stack, frame or arg pointers. */
13692 if (regno
== STACK_POINTER_REGNUM
13693 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13694 && regno
== HARD_FRAME_POINTER_REGNUM
)
13695 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
13696 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
13697 || regno
== FRAME_POINTER_REGNUM
)
13700 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
13706 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13708 rtx testreg
= SET_DEST (x
);
13710 while (GET_CODE (testreg
) == SUBREG
13711 || GET_CODE (testreg
) == ZERO_EXTRACT
13712 || GET_CODE (testreg
) == STRICT_LOW_PART
)
13713 testreg
= XEXP (testreg
, 0);
13715 if (MEM_P (testreg
))
13716 mark_used_regs_combine (XEXP (testreg
, 0));
13718 mark_used_regs_combine (SET_SRC (x
));
13726 /* Recursively scan the operands of this expression. */
13729 const char *fmt
= GET_RTX_FORMAT (code
);
13731 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13734 mark_used_regs_combine (XEXP (x
, i
));
13735 else if (fmt
[i
] == 'E')
13739 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13740 mark_used_regs_combine (XVECEXP (x
, i
, j
));
13746 /* Remove register number REGNO from the dead registers list of INSN.
13748 Return the note used to record the death, if there was one. */
13751 remove_death (unsigned int regno
, rtx_insn
*insn
)
13753 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
13756 remove_note (insn
, note
);
13761 /* For each register (hardware or pseudo) used within expression X, if its
13762 death is in an instruction with luid between FROM_LUID (inclusive) and
13763 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13764 list headed by PNOTES.
13766 That said, don't move registers killed by maybe_kill_insn.
13768 This is done when X is being merged by combination into TO_INSN. These
13769 notes will then be distributed as needed. */
13772 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx_insn
*to_insn
,
13777 enum rtx_code code
= GET_CODE (x
);
13781 unsigned int regno
= REGNO (x
);
13782 rtx_insn
*where_dead
= reg_stat
[regno
].last_death
;
13784 /* Don't move the register if it gets killed in between from and to. */
13785 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
13786 && ! reg_referenced_p (x
, maybe_kill_insn
))
13790 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
13791 && DF_INSN_LUID (where_dead
) >= from_luid
13792 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
13794 rtx note
= remove_death (regno
, where_dead
);
13796 /* It is possible for the call above to return 0. This can occur
13797 when last_death points to I2 or I1 that we combined with.
13798 In that case make a new note.
13800 We must also check for the case where X is a hard register
13801 and NOTE is a death note for a range of hard registers
13802 including X. In that case, we must put REG_DEAD notes for
13803 the remaining registers in place of NOTE. */
13805 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
13806 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13807 > GET_MODE_SIZE (GET_MODE (x
))))
13809 unsigned int deadregno
= REGNO (XEXP (note
, 0));
13810 unsigned int deadend
= END_REGNO (XEXP (note
, 0));
13811 unsigned int ourend
= END_REGNO (x
);
13814 for (i
= deadregno
; i
< deadend
; i
++)
13815 if (i
< regno
|| i
>= ourend
)
13816 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
13819 /* If we didn't find any note, or if we found a REG_DEAD note that
13820 covers only part of the given reg, and we have a multi-reg hard
13821 register, then to be safe we must check for REG_DEAD notes
13822 for each register other than the first. They could have
13823 their own REG_DEAD notes lying around. */
13824 else if ((note
== 0
13826 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13827 < GET_MODE_SIZE (GET_MODE (x
)))))
13828 && regno
< FIRST_PSEUDO_REGISTER
13829 && REG_NREGS (x
) > 1)
13831 unsigned int ourend
= END_REGNO (x
);
13832 unsigned int i
, offset
;
13836 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
13840 for (i
= regno
+ offset
; i
< ourend
; i
++)
13841 move_deaths (regno_reg_rtx
[i
],
13842 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13845 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13847 XEXP (note
, 1) = *pnotes
;
13851 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13857 else if (GET_CODE (x
) == SET
)
13859 rtx dest
= SET_DEST (x
);
13861 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13863 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13864 that accesses one word of a multi-word item, some
13865 piece of everything register in the expression is used by
13866 this insn, so remove any old death. */
13867 /* ??? So why do we test for equality of the sizes? */
13869 if (GET_CODE (dest
) == ZERO_EXTRACT
13870 || GET_CODE (dest
) == STRICT_LOW_PART
13871 || (GET_CODE (dest
) == SUBREG
13872 && (((GET_MODE_SIZE (GET_MODE (dest
))
13873 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13874 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13875 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13877 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13881 /* If this is some other SUBREG, we know it replaces the entire
13882 value, so use that as the destination. */
13883 if (GET_CODE (dest
) == SUBREG
)
13884 dest
= SUBREG_REG (dest
);
13886 /* If this is a MEM, adjust deaths of anything used in the address.
13887 For a REG (the only other possibility), the entire value is
13888 being replaced so the old value is not used in this insn. */
13891 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13896 else if (GET_CODE (x
) == CLOBBER
)
13899 len
= GET_RTX_LENGTH (code
);
13900 fmt
= GET_RTX_FORMAT (code
);
13902 for (i
= 0; i
< len
; i
++)
13907 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13908 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13911 else if (fmt
[i
] == 'e')
13912 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13916 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13917 pattern of an insn. X must be a REG. */
13920 reg_bitfield_target_p (rtx x
, rtx body
)
13924 if (GET_CODE (body
) == SET
)
13926 rtx dest
= SET_DEST (body
);
13928 unsigned int regno
, tregno
, endregno
, endtregno
;
13930 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13931 target
= XEXP (dest
, 0);
13932 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13933 target
= SUBREG_REG (XEXP (dest
, 0));
13937 if (GET_CODE (target
) == SUBREG
)
13938 target
= SUBREG_REG (target
);
13940 if (!REG_P (target
))
13943 tregno
= REGNO (target
), regno
= REGNO (x
);
13944 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13945 return target
== x
;
13947 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13948 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13950 return endregno
> tregno
&& regno
< endtregno
;
13953 else if (GET_CODE (body
) == PARALLEL
)
13954 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13955 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13961 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13962 as appropriate. I3 and I2 are the insns resulting from the combination
13963 insns including FROM (I2 may be zero).
13965 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13966 not need REG_DEAD notes because they are being substituted for. This
13967 saves searching in the most common cases.
13969 Each note in the list is either ignored or placed on some insns, depending
13970 on the type of note. */
13973 distribute_notes (rtx notes
, rtx_insn
*from_insn
, rtx_insn
*i3
, rtx_insn
*i2
,
13974 rtx elim_i2
, rtx elim_i1
, rtx elim_i0
)
13976 rtx note
, next_note
;
13978 rtx_insn
*tem_insn
;
13980 for (note
= notes
; note
; note
= next_note
)
13982 rtx_insn
*place
= 0, *place2
= 0;
13984 next_note
= XEXP (note
, 1);
13985 switch (REG_NOTE_KIND (note
))
13989 /* Doesn't matter much where we put this, as long as it's somewhere.
13990 It is preferable to keep these notes on branches, which is most
13991 likely to be i3. */
13995 case REG_NON_LOCAL_GOTO
:
14000 gcc_assert (i2
&& JUMP_P (i2
));
14005 case REG_EH_REGION
:
14006 /* These notes must remain with the call or trapping instruction. */
14009 else if (i2
&& CALL_P (i2
))
14013 gcc_assert (cfun
->can_throw_non_call_exceptions
);
14014 if (may_trap_p (i3
))
14016 else if (i2
&& may_trap_p (i2
))
14018 /* ??? Otherwise assume we've combined things such that we
14019 can now prove that the instructions can't trap. Drop the
14020 note in this case. */
14024 case REG_ARGS_SIZE
:
14025 /* ??? How to distribute between i3-i1. Assume i3 contains the
14026 entire adjustment. Assert i3 contains at least some adjust. */
14027 if (!noop_move_p (i3
))
14029 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
14030 /* fixup_args_size_notes looks at REG_NORETURN note,
14031 so ensure the note is placed there first. */
14035 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
14036 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
14040 XEXP (n
, 1) = REG_NOTES (i3
);
14041 REG_NOTES (i3
) = n
;
14045 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
14046 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14047 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14048 gcc_assert (old_size
!= args_size
14050 && !ACCUMULATE_OUTGOING_ARGS
14051 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
14058 case REG_CALL_DECL
:
14059 /* These notes must remain with the call. It should not be
14060 possible for both I2 and I3 to be a call. */
14065 gcc_assert (i2
&& CALL_P (i2
));
14071 /* Any clobbers for i3 may still exist, and so we must process
14072 REG_UNUSED notes from that insn.
14074 Any clobbers from i2 or i1 can only exist if they were added by
14075 recog_for_combine. In that case, recog_for_combine created the
14076 necessary REG_UNUSED notes. Trying to keep any original
14077 REG_UNUSED notes from these insns can cause incorrect output
14078 if it is for the same register as the original i3 dest.
14079 In that case, we will notice that the register is set in i3,
14080 and then add a REG_UNUSED note for the destination of i3, which
14081 is wrong. However, it is possible to have REG_UNUSED notes from
14082 i2 or i1 for register which were both used and clobbered, so
14083 we keep notes from i2 or i1 if they will turn into REG_DEAD
14086 /* If this register is set or clobbered in I3, put the note there
14087 unless there is one already. */
14088 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
14090 if (from_insn
!= i3
)
14093 if (! (REG_P (XEXP (note
, 0))
14094 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
14095 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
14098 /* Otherwise, if this register is used by I3, then this register
14099 now dies here, so we must put a REG_DEAD note here unless there
14101 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
14102 && ! (REG_P (XEXP (note
, 0))
14103 ? find_regno_note (i3
, REG_DEAD
,
14104 REGNO (XEXP (note
, 0)))
14105 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
14107 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
14115 /* These notes say something about results of an insn. We can
14116 only support them if they used to be on I3 in which case they
14117 remain on I3. Otherwise they are ignored.
14119 If the note refers to an expression that is not a constant, we
14120 must also ignore the note since we cannot tell whether the
14121 equivalence is still true. It might be possible to do
14122 slightly better than this (we only have a problem if I2DEST
14123 or I1DEST is present in the expression), but it doesn't
14124 seem worth the trouble. */
14126 if (from_insn
== i3
14127 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
14132 /* These notes say something about how a register is used. They must
14133 be present on any use of the register in I2 or I3. */
14134 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
14137 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
14146 case REG_LABEL_TARGET
:
14147 case REG_LABEL_OPERAND
:
14148 /* This can show up in several ways -- either directly in the
14149 pattern, or hidden off in the constant pool with (or without?)
14150 a REG_EQUAL note. */
14151 /* ??? Ignore the without-reg_equal-note problem for now. */
14152 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
14153 || ((tem_note
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
14154 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14155 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0)))
14159 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
14160 || ((tem_note
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
14161 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14162 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0))))
14170 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14171 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14173 if (place
&& JUMP_P (place
)
14174 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14175 && (JUMP_LABEL (place
) == NULL
14176 || JUMP_LABEL (place
) == XEXP (note
, 0)))
14178 rtx label
= JUMP_LABEL (place
);
14181 JUMP_LABEL (place
) = XEXP (note
, 0);
14182 else if (LABEL_P (label
))
14183 LABEL_NUSES (label
)--;
14186 if (place2
&& JUMP_P (place2
)
14187 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14188 && (JUMP_LABEL (place2
) == NULL
14189 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
14191 rtx label
= JUMP_LABEL (place2
);
14194 JUMP_LABEL (place2
) = XEXP (note
, 0);
14195 else if (LABEL_P (label
))
14196 LABEL_NUSES (label
)--;
14202 /* This note says something about the value of a register prior
14203 to the execution of an insn. It is too much trouble to see
14204 if the note is still correct in all situations. It is better
14205 to simply delete it. */
14209 /* If we replaced the right hand side of FROM_INSN with a
14210 REG_EQUAL note, the original use of the dying register
14211 will not have been combined into I3 and I2. In such cases,
14212 FROM_INSN is guaranteed to be the first of the combined
14213 instructions, so we simply need to search back before
14214 FROM_INSN for the previous use or set of this register,
14215 then alter the notes there appropriately.
14217 If the register is used as an input in I3, it dies there.
14218 Similarly for I2, if it is nonzero and adjacent to I3.
14220 If the register is not used as an input in either I3 or I2
14221 and it is not one of the registers we were supposed to eliminate,
14222 there are two possibilities. We might have a non-adjacent I2
14223 or we might have somehow eliminated an additional register
14224 from a computation. For example, we might have had A & B where
14225 we discover that B will always be zero. In this case we will
14226 eliminate the reference to A.
14228 In both cases, we must search to see if we can find a previous
14229 use of A and put the death note there. */
14232 && from_insn
== i2mod
14233 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
14234 tem_insn
= from_insn
;
14238 && CALL_P (from_insn
)
14239 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
14241 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
14243 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
14244 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14246 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
14248 && reg_overlap_mentioned_p (XEXP (note
, 0),
14250 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
14251 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
14254 /* If the new I2 sets the same register that is marked dead
14255 in the note, we do not know where to put the note.
14257 if (i2
!= 0 && reg_set_p (XEXP (note
, 0), PATTERN (i2
)))
14263 basic_block bb
= this_basic_block
;
14265 for (tem_insn
= PREV_INSN (tem_insn
); place
== 0; tem_insn
= PREV_INSN (tem_insn
))
14267 if (!NONDEBUG_INSN_P (tem_insn
))
14269 if (tem_insn
== BB_HEAD (bb
))
14274 /* If the register is being set at TEM_INSN, see if that is all
14275 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14276 into a REG_UNUSED note instead. Don't delete sets to
14277 global register vars. */
14278 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
14279 || !global_regs
[REGNO (XEXP (note
, 0))])
14280 && reg_set_p (XEXP (note
, 0), PATTERN (tem_insn
)))
14282 rtx set
= single_set (tem_insn
);
14283 rtx inner_dest
= 0;
14284 rtx_insn
*cc0_setter
= NULL
;
14287 for (inner_dest
= SET_DEST (set
);
14288 (GET_CODE (inner_dest
) == STRICT_LOW_PART
14289 || GET_CODE (inner_dest
) == SUBREG
14290 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
14291 inner_dest
= XEXP (inner_dest
, 0))
14294 /* Verify that it was the set, and not a clobber that
14295 modified the register.
14297 CC0 targets must be careful to maintain setter/user
14298 pairs. If we cannot delete the setter due to side
14299 effects, mark the user with an UNUSED note instead
14302 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
14303 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
14305 || (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
14306 || ((cc0_setter
= prev_cc0_setter (tem_insn
)) != NULL
14307 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))))
14309 /* Move the notes and links of TEM_INSN elsewhere.
14310 This might delete other dead insns recursively.
14311 First set the pattern to something that won't use
14313 rtx old_notes
= REG_NOTES (tem_insn
);
14315 PATTERN (tem_insn
) = pc_rtx
;
14316 REG_NOTES (tem_insn
) = NULL
;
14318 distribute_notes (old_notes
, tem_insn
, tem_insn
, NULL
,
14319 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14320 distribute_links (LOG_LINKS (tem_insn
));
14322 unsigned int regno
= REGNO (XEXP (note
, 0));
14323 reg_stat_type
*rsp
= ®_stat
[regno
];
14324 if (rsp
->last_set
== tem_insn
)
14325 record_value_for_reg (XEXP (note
, 0), NULL
, NULL_RTX
);
14327 SET_INSN_DELETED (tem_insn
);
14328 if (tem_insn
== i2
)
14331 /* Delete the setter too. */
14334 PATTERN (cc0_setter
) = pc_rtx
;
14335 old_notes
= REG_NOTES (cc0_setter
);
14336 REG_NOTES (cc0_setter
) = NULL
;
14338 distribute_notes (old_notes
, cc0_setter
,
14340 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14341 distribute_links (LOG_LINKS (cc0_setter
));
14343 SET_INSN_DELETED (cc0_setter
);
14344 if (cc0_setter
== i2
)
14350 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
14352 /* If there isn't already a REG_UNUSED note, put one
14353 here. Do not place a REG_DEAD note, even if
14354 the register is also used here; that would not
14355 match the algorithm used in lifetime analysis
14356 and can cause the consistency check in the
14357 scheduler to fail. */
14358 if (! find_regno_note (tem_insn
, REG_UNUSED
,
14359 REGNO (XEXP (note
, 0))))
14364 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem_insn
))
14365 || (CALL_P (tem_insn
)
14366 && find_reg_fusage (tem_insn
, USE
, XEXP (note
, 0))))
14370 /* If we are doing a 3->2 combination, and we have a
14371 register which formerly died in i3 and was not used
14372 by i2, which now no longer dies in i3 and is used in
14373 i2 but does not die in i2, and place is between i2
14374 and i3, then we may need to move a link from place to
14376 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
14378 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
14379 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14381 struct insn_link
*links
= LOG_LINKS (place
);
14382 LOG_LINKS (place
) = NULL
;
14383 distribute_links (links
);
14388 if (tem_insn
== BB_HEAD (bb
))
14394 /* If the register is set or already dead at PLACE, we needn't do
14395 anything with this note if it is still a REG_DEAD note.
14396 We check here if it is set at all, not if is it totally replaced,
14397 which is what `dead_or_set_p' checks, so also check for it being
14400 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
14402 unsigned int regno
= REGNO (XEXP (note
, 0));
14403 reg_stat_type
*rsp
= ®_stat
[regno
];
14405 if (dead_or_set_p (place
, XEXP (note
, 0))
14406 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
14408 /* Unless the register previously died in PLACE, clear
14409 last_death. [I no longer understand why this is
14411 if (rsp
->last_death
!= place
)
14412 rsp
->last_death
= 0;
14416 rsp
->last_death
= place
;
14418 /* If this is a death note for a hard reg that is occupying
14419 multiple registers, ensure that we are still using all
14420 parts of the object. If we find a piece of the object
14421 that is unused, we must arrange for an appropriate REG_DEAD
14422 note to be added for it. However, we can't just emit a USE
14423 and tag the note to it, since the register might actually
14424 be dead; so we recourse, and the recursive call then finds
14425 the previous insn that used this register. */
14427 if (place
&& REG_NREGS (XEXP (note
, 0)) > 1)
14429 unsigned int endregno
= END_REGNO (XEXP (note
, 0));
14430 bool all_used
= true;
14433 for (i
= regno
; i
< endregno
; i
++)
14434 if ((! refers_to_regno_p (i
, PATTERN (place
))
14435 && ! find_regno_fusage (place
, USE
, i
))
14436 || dead_or_set_regno_p (place
, i
))
14444 /* Put only REG_DEAD notes for pieces that are
14445 not already dead or set. */
14447 for (i
= regno
; i
< endregno
;
14448 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
14450 rtx piece
= regno_reg_rtx
[i
];
14451 basic_block bb
= this_basic_block
;
14453 if (! dead_or_set_p (place
, piece
)
14454 && ! reg_bitfield_target_p (piece
,
14457 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
14460 distribute_notes (new_note
, place
, place
,
14461 NULL
, NULL_RTX
, NULL_RTX
,
14464 else if (! refers_to_regno_p (i
, PATTERN (place
))
14465 && ! find_regno_fusage (place
, USE
, i
))
14466 for (tem_insn
= PREV_INSN (place
); ;
14467 tem_insn
= PREV_INSN (tem_insn
))
14469 if (!NONDEBUG_INSN_P (tem_insn
))
14471 if (tem_insn
== BB_HEAD (bb
))
14475 if (dead_or_set_p (tem_insn
, piece
)
14476 || reg_bitfield_target_p (piece
,
14477 PATTERN (tem_insn
)))
14479 add_reg_note (tem_insn
, REG_UNUSED
, piece
);
14492 /* Any other notes should not be present at this point in the
14494 gcc_unreachable ();
14499 XEXP (note
, 1) = REG_NOTES (place
);
14500 REG_NOTES (place
) = note
;
14504 add_shallow_copy_of_reg_note (place2
, note
);
14508 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14509 I3, I2, and I1 to new locations. This is also called to add a link
14510 pointing at I3 when I3's destination is changed. */
14513 distribute_links (struct insn_link
*links
)
14515 struct insn_link
*link
, *next_link
;
14517 for (link
= links
; link
; link
= next_link
)
14519 rtx_insn
*place
= 0;
14523 next_link
= link
->next
;
14525 /* If the insn that this link points to is a NOTE, ignore it. */
14526 if (NOTE_P (link
->insn
))
14530 rtx pat
= PATTERN (link
->insn
);
14531 if (GET_CODE (pat
) == SET
)
14533 else if (GET_CODE (pat
) == PARALLEL
)
14536 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
14538 set
= XVECEXP (pat
, 0, i
);
14539 if (GET_CODE (set
) != SET
)
14542 reg
= SET_DEST (set
);
14543 while (GET_CODE (reg
) == ZERO_EXTRACT
14544 || GET_CODE (reg
) == STRICT_LOW_PART
14545 || GET_CODE (reg
) == SUBREG
)
14546 reg
= XEXP (reg
, 0);
14551 if (REGNO (reg
) == link
->regno
)
14554 if (i
== XVECLEN (pat
, 0))
14560 reg
= SET_DEST (set
);
14562 while (GET_CODE (reg
) == ZERO_EXTRACT
14563 || GET_CODE (reg
) == STRICT_LOW_PART
14564 || GET_CODE (reg
) == SUBREG
)
14565 reg
= XEXP (reg
, 0);
14567 /* A LOG_LINK is defined as being placed on the first insn that uses
14568 a register and points to the insn that sets the register. Start
14569 searching at the next insn after the target of the link and stop
14570 when we reach a set of the register or the end of the basic block.
14572 Note that this correctly handles the link that used to point from
14573 I3 to I2. Also note that not much searching is typically done here
14574 since most links don't point very far away. */
14576 for (insn
= NEXT_INSN (link
->insn
);
14577 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
14578 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
14579 insn
= NEXT_INSN (insn
))
14580 if (DEBUG_INSN_P (insn
))
14582 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
14584 if (reg_referenced_p (reg
, PATTERN (insn
)))
14588 else if (CALL_P (insn
)
14589 && find_reg_fusage (insn
, USE
, reg
))
14594 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
14597 /* If we found a place to put the link, place it there unless there
14598 is already a link to the same insn as LINK at that point. */
14602 struct insn_link
*link2
;
14604 FOR_EACH_LOG_LINK (link2
, place
)
14605 if (link2
->insn
== link
->insn
&& link2
->regno
== link
->regno
)
14610 link
->next
= LOG_LINKS (place
);
14611 LOG_LINKS (place
) = link
;
14613 /* Set added_links_insn to the earliest insn we added a
14615 if (added_links_insn
== 0
14616 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
14617 added_links_insn
= place
;
14623 /* Check for any register or memory mentioned in EQUIV that is not
14624 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14625 of EXPR where some registers may have been replaced by constants. */
14628 unmentioned_reg_p (rtx equiv
, rtx expr
)
14630 subrtx_iterator::array_type array
;
14631 FOR_EACH_SUBRTX (iter
, array
, equiv
, NONCONST
)
14633 const_rtx x
= *iter
;
14634 if ((REG_P (x
) || MEM_P (x
))
14635 && !reg_mentioned_p (x
, expr
))
14641 DEBUG_FUNCTION
void
14642 dump_combine_stats (FILE *file
)
14646 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14647 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
14651 dump_combine_total_stats (FILE *file
)
14655 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14656 total_attempts
, total_merges
, total_extras
, total_successes
);
14659 /* Try combining insns through substitution. */
14660 static unsigned int
14661 rest_of_handle_combine (void)
14663 int rebuild_jump_labels_after_combine
;
14665 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
14666 df_note_add_problem ();
14669 regstat_init_n_sets_and_refs ();
14670 reg_n_sets_max
= max_reg_num ();
14672 rebuild_jump_labels_after_combine
14673 = combine_instructions (get_insns (), max_reg_num ());
14675 /* Combining insns may have turned an indirect jump into a
14676 direct jump. Rebuild the JUMP_LABEL fields of jumping
14678 if (rebuild_jump_labels_after_combine
)
14680 if (dom_info_available_p (CDI_DOMINATORS
))
14681 free_dominance_info (CDI_DOMINATORS
);
14682 timevar_push (TV_JUMP
);
14683 rebuild_jump_labels (get_insns ());
14685 timevar_pop (TV_JUMP
);
14688 regstat_free_n_sets_and_refs ();
14694 const pass_data pass_data_combine
=
14696 RTL_PASS
, /* type */
14697 "combine", /* name */
14698 OPTGROUP_NONE
, /* optinfo_flags */
14699 TV_COMBINE
, /* tv_id */
14700 PROP_cfglayout
, /* properties_required */
14701 0, /* properties_provided */
14702 0, /* properties_destroyed */
14703 0, /* todo_flags_start */
14704 TODO_df_finish
, /* todo_flags_finish */
14707 class pass_combine
: public rtl_opt_pass
14710 pass_combine (gcc::context
*ctxt
)
14711 : rtl_opt_pass (pass_data_combine
, ctxt
)
14714 /* opt_pass methods: */
14715 virtual bool gate (function
*) { return (optimize
> 0); }
14716 virtual unsigned int execute (function
*)
14718 return rest_of_handle_combine ();
14721 }; // class pass_combine
14723 } // anon namespace
14726 make_pass_combine (gcc::context
*ctxt
)
14728 return new pass_combine (ctxt
);