gcc/config/mn10300/mn10300.c

   1 /* Subroutines for insn-output.c for Matsushita MN10300 series
   2    Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001
   3    Free Software Foundation, Inc.
   4    Contributed by Jeff Law (law@cygnus.com).
   5
   6 This file is part of GNU CC.
   7
   8 GNU CC is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 2, or (at your option)
  11 any later version.
  12
  13 GNU CC is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GNU CC; see the file COPYING.  If not, write to
  20 the Free Software Foundation, 59 Temple Place - Suite 330,
  21 Boston, MA 02111-1307, USA.  */
  22
  23 #include "config.h"
  24 #include "system.h"
  25 #include "rtl.h"
  26 #include "tree.h"
  27 #include "regs.h"
  28 #include "hard-reg-set.h"
  29 #include "real.h"
  30 #include "insn-config.h"
  31 #include "conditions.h"
  32 #include "output.h"
  33 #include "insn-attr.h"
  34 #include "flags.h"
  35 #include "recog.h"
  36 #include "expr.h"
  37 #include "optabs.h"
  38 #include "function.h"
  39 #include "obstack.h"
  40 #include "toplev.h"
  41 #include "tm_p.h"
  42 #include "target.h"
  43 #include "target-def.h"
  44
  45 /* The size of the callee register save area.  Right now we save everything
  46    on entry since it costs us nothing in code size.  It does cost us from a
  47    speed standpoint, so we want to optimize this sooner or later.  */
  48 #define REG_SAVE_BYTES (4 * regs_ever_live[2] \
  49                         + 4 * regs_ever_live[3] \
  50                         + 4 * regs_ever_live[6] \
  51                         + 4 * regs_ever_live[7] \
  52                         + 16 * (regs_ever_live[14] || regs_ever_live[15] \
  53                                 || regs_ever_live[16] || regs_ever_live[17]))
  54 \f
  55 /* Initialize the GCC target structure.  */
  56
  57 struct gcc_target targetm = TARGET_INITIALIZER;
  58 \f
  59 void
  60 asm_file_start (file)
  61      FILE *file;
  62 {
  63   fprintf (file, "#\tGCC For the Matsushita MN10300\n");
  64   if (optimize)
  65     fprintf (file, "# -O%d\n", optimize);
  66   else
  67     fprintf (file, "\n\n");
  68
  69   if (TARGET_AM33)
  70     fprintf (file, "\t.am33\n");
  71   output_file_directive (file, main_input_filename);
  72 }
  73 \f
  74
  75 /* Print operand X using operand code CODE to assembly language output file
  76    FILE.  */
  77
  78 void
  79 print_operand (file, x, code)
  80      FILE *file;
  81      rtx x;
  82      int code;
  83 {
  84   switch (code)
  85     {
  86       case 'b':
  87       case 'B':
  88         /* These are normal and reversed branches.  */
  89         switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x)))
  90           {
  91           case NE:
  92             fprintf (file, "ne");
  93             break;
  94           case EQ:
  95             fprintf (file, "eq");
  96             break;
  97           case GE:
  98             fprintf (file, "ge");
  99             break;
 100           case GT:
 101             fprintf (file, "gt");
 102             break;
 103           case LE:
 104             fprintf (file, "le");
 105             break;
 106           case LT:
 107             fprintf (file, "lt");
 108             break;
 109           case GEU:
 110             fprintf (file, "cc");
 111             break;
 112           case GTU:
 113             fprintf (file, "hi");
 114             break;
 115           case LEU:
 116             fprintf (file, "ls");
 117             break;
 118           case LTU:
 119             fprintf (file, "cs");
 120             break;
 121           default:
 122             abort ();
 123           }
 124         break;
 125       case 'C':
 126         /* This is used for the operand to a call instruction;
 127            if it's a REG, enclose it in parens, else output
 128            the operand normally.  */
 129         if (GET_CODE (x) == REG)
 130           {
 131             fputc ('(', file);
 132             print_operand (file, x, 0);
 133             fputc (')', file);
 134           }
 135         else
 136           print_operand (file, x, 0);
 137         break;
 138
 139       /* These are the least significant word in a 64bit value.  */
 140       case 'L':
 141         switch (GET_CODE (x))
 142           {
 143           case MEM:
 144             fputc ('(', file);
 145             output_address (XEXP (x, 0));
 146             fputc (')', file);
 147             break;
 148
 149           case REG:
 150             fprintf (file, "%s", reg_names[REGNO (x)]);
 151             break;
 152
 153           case SUBREG:
 154             fprintf (file, "%s", reg_names[subreg_regno (x)]);
 155             break;
 156
 157           case CONST_DOUBLE:
 158               {
 159                 long val[2];
 160                 REAL_VALUE_TYPE rv;
 161
 162                 switch (GET_MODE (x))
 163                   {
 164                     case DFmode:
 165                       REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
 166                       REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
 167                       fprintf (file, "0x%lx", val[0]);
 168                       break;;
 169                     case SFmode:
 170                       REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
 171                       REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]);
 172                       fprintf (file, "0x%lx", val[0]);
 173                       break;;
 174                     case VOIDmode:
 175                     case DImode:
 176                       print_operand_address (file,
 177                                              GEN_INT (CONST_DOUBLE_LOW (x)));
 178                       break;
 179                     default:
 180                       break;
 181                   }
 182                 break;
 183               }
 184
 185           case CONST_INT:
 186             {
 187               rtx low, high;
 188               split_double (x, &low, &high);
 189               fprintf (file, "%ld", (long)INTVAL (low));
 190               break;
 191             }
 192
 193           default:
 194             abort ();
 195           }
 196         break;
 197
 198       /* Similarly, but for the most significant word.  */
 199       case 'H':
 200         switch (GET_CODE (x))
 201           {
 202           case MEM:
 203             fputc ('(', file);
 204             x = adjust_address (x, SImode, 4);
 205             output_address (XEXP (x, 0));
 206             fputc (')', file);
 207             break;
 208
 209           case REG:
 210             fprintf (file, "%s", reg_names[REGNO (x) + 1]);
 211             break;
 212
 213           case SUBREG:
 214             fprintf (file, "%s", reg_names[subreg_regno (x) + 1]);
 215             break;
 216
 217           case CONST_DOUBLE:
 218               {
 219                 long val[2];
 220                 REAL_VALUE_TYPE rv;
 221
 222                 switch (GET_MODE (x))
 223                   {
 224                     case DFmode:
 225                       REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
 226                       REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
 227                       fprintf (file, "0x%lx", val[1]);
 228                       break;;
 229                     case SFmode:
 230                       abort ();
 231                     case VOIDmode:
 232                     case DImode:
 233                       print_operand_address (file,
 234                                              GEN_INT (CONST_DOUBLE_HIGH (x)));
 235                       break;
 236                     default:
 237                       break;
 238                   }
 239                 break;
 240               }
 241
 242           case CONST_INT:
 243             {
 244               rtx low, high;
 245               split_double (x, &low, &high);
 246               fprintf (file, "%ld", (long)INTVAL (high));
 247               break;
 248             }
 249
 250           default:
 251             abort ();
 252           }
 253         break;
 254
 255       case 'A':
 256         fputc ('(', file);
 257         if (GET_CODE (XEXP (x, 0)) == REG)
 258           output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), GEN_INT (0)));
 259         else
 260           output_address (XEXP (x, 0));
 261         fputc (')', file);
 262         break;
 263
 264       case 'N':
 265         output_address (GEN_INT ((~INTVAL (x)) & 0xff));
 266         break;
 267
 268       /* For shift counts.  The hardware ignores the upper bits of
 269          any immediate, but the assembler will flag an out of range
 270          shift count as an error.  So we mask off the high bits
 271          of the immediate here.  */
 272       case 'S':
 273         if (GET_CODE (x) == CONST_INT)
 274           {
 275             fprintf (file, "%d", INTVAL (x) & 0x1f);
 276             break;
 277           }
 278         /* FALL THROUGH */
 279
 280       default:
 281         switch (GET_CODE (x))
 282           {
 283           case MEM:
 284             fputc ('(', file);
 285             output_address (XEXP (x, 0));
 286             fputc (')', file);
 287             break;
 288
 289           case PLUS:
 290             output_address (x);
 291             break;
 292
 293           case REG:
 294             fprintf (file, "%s", reg_names[REGNO (x)]);
 295             break;
 296
 297           case SUBREG:
 298             fprintf (file, "%s", reg_names[subreg_regno (x)]);
 299             break;
 300
 301           /* This will only be single precision....  */
 302           case CONST_DOUBLE:
 303             {
 304               unsigned long val;
 305               REAL_VALUE_TYPE rv;
 306
 307               REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
 308               REAL_VALUE_TO_TARGET_SINGLE (rv, val);
 309               fprintf (file, "0x%lx", val);
 310               break;
 311             }
 312
 313           case CONST_INT:
 314           case SYMBOL_REF:
 315           case CONST:
 316           case LABEL_REF:
 317           case CODE_LABEL:
 318             print_operand_address (file, x);
 319             break;
 320           default:
 321             abort ();
 322           }
 323         break;
 324    }
 325 }
 326
 327 /* Output assembly language output for the address ADDR to FILE.  */
 328
 329 void
 330 print_operand_address (file, addr)
 331      FILE *file;
 332      rtx addr;
 333 {
 334   switch (GET_CODE (addr))
 335     {
 336     case POST_INC:
 337       print_operand_address (file, XEXP (addr, 0));
 338       fputc ('+', file);
 339       break;
 340     case REG:
 341       print_operand (file, addr, 0);
 342       break;
 343     case PLUS:
 344       {
 345         rtx base, index;
 346         if (REG_P (XEXP (addr, 0))
 347             && REG_OK_FOR_BASE_P (XEXP (addr, 0)))
 348           base = XEXP (addr, 0), index = XEXP (addr, 1);
 349         else if (REG_P (XEXP (addr, 1))
 350             && REG_OK_FOR_BASE_P (XEXP (addr, 1)))
 351           base = XEXP (addr, 1), index = XEXP (addr, 0);
 352         else
 353           abort ();
 354         print_operand (file, index, 0);
 355         fputc (',', file);
 356         print_operand (file, base, 0);;
 357         break;
 358       }
 359     case SYMBOL_REF:
 360       output_addr_const (file, addr);
 361       break;
 362     default:
 363       output_addr_const (file, addr);
 364       break;
 365     }
 366 }
 367
 368 /* Print a set of registers in the format required by "movm" and "ret".
 369    Register K is saved if bit K of MASK is set.  The data and address
 370    registers can be stored individually, but the extended registers cannot.
 371    We assume that the mask alread takes that into account.  For instance,
 372    bits 14 to 17 must have the same value. */
 373
 374 void
 375 mn10300_print_reg_list (file, mask)
 376      FILE *file;
 377      int mask;
 378 {
 379   int need_comma;
 380   int i;
 381
 382   need_comma = 0;
 383   fputc ('[', file);
 384
 385   for (i = 0; i < FIRST_EXTENDED_REGNUM; i++)
 386     if ((mask & (1 << i)) != 0)
 387       {
 388         if (need_comma)
 389           fputc (',', file);
 390         fputs (reg_names [i], file);
 391         need_comma = 1;
 392       }
 393
 394   if ((mask & 0x3c000) != 0)
 395     {
 396       if ((mask & 0x3c000) != 0x3c000)
 397         abort();
 398       if (need_comma)
 399         fputc (',', file);
 400       fputs ("exreg1", file);
 401       need_comma = 1;
 402     }
 403
 404   fputc (']', file);
 405 }
 406
 407 int
 408 can_use_return_insn ()
 409 {
 410   /* size includes the fixed stack space needed for function calls.  */
 411   int size = get_frame_size () + current_function_outgoing_args_size;
 412
 413   /* And space for the return pointer.  */
 414   size += current_function_outgoing_args_size ? 4 : 0;
 415
 416   return (reload_completed
 417           && size == 0
 418           && !regs_ever_live[2]
 419           && !regs_ever_live[3]
 420           && !regs_ever_live[6]
 421           && !regs_ever_live[7]
 422           && !regs_ever_live[14]
 423           && !regs_ever_live[15]
 424           && !regs_ever_live[16]
 425           && !regs_ever_live[17]
 426           && !frame_pointer_needed);
 427 }
 428
 429 /* Returns the set of live, callee-saved registers as a bitmask.  The
 430    callee-saved extended registers cannot be stored individually, so
 431    all of them will be included in the mask if any one of them is used. */
 432
 433 int
 434 mn10300_get_live_callee_saved_regs ()
 435 {
 436   int mask;
 437   int i;
 438
 439   mask = 0;
 440   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
 441     if (regs_ever_live[i] && ! call_used_regs[i])
 442       mask |= (1 << i);
 443   if ((mask & 0x3c000) != 0)
 444     mask |= 0x3c000;
 445
 446   return mask;
 447 }
 448
 449 /* Generate an instruction that pushes several registers onto the stack.
 450    Register K will be saved if bit K in MASK is set.  The function does
 451    nothing if MASK is zero.
 452
 453    To be compatible with the "movm" instruction, the lowest-numbered
 454    register must be stored in the lowest slot.  If MASK is the set
 455    { R1,...,RN }, where R1...RN are ordered least first, the generated
 456    instruction will have the form:
 457
 458        (parallel
 459          (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4)))
 460          (set (mem:SI (plus:SI (reg:SI 9)
 461                                (const_int -1*4)))
 462               (reg:SI RN))
 463          ...
 464          (set (mem:SI (plus:SI (reg:SI 9)
 465                                (const_int -N*4)))
 466               (reg:SI R1))) */
 467
 468 void
 469 mn10300_gen_multiple_store (mask)
 470      int mask;
 471 {
 472   if (mask != 0)
 473     {
 474       int i;
 475       int count;
 476       rtx par;
 477       int pari;
 478
 479       /* Count how many registers need to be saved. */
 480       count = 0;
 481       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
 482         if ((mask & (1 << i)) != 0)
 483           count += 1;
 484
 485       /* We need one PARALLEL element to update the stack pointer and
 486          an additional element for each register that is stored. */
 487       par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
 488
 489       /* Create the instruction that updates the stack pointer. */
 490       XVECEXP (par, 0, 0)
 491         = gen_rtx_SET (SImode,
 492                        stack_pointer_rtx,
 493                        gen_rtx_PLUS (SImode,
 494                                      stack_pointer_rtx,
 495                                      GEN_INT (-count * 4)));
 496
 497       /* Create each store. */
 498       pari = 1;
 499       for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
 500         if ((mask & (1 << i)) != 0)
 501           {
 502             rtx address = gen_rtx_PLUS (SImode,
 503                                         stack_pointer_rtx,
 504                                         GEN_INT (-pari * 4));
 505             XVECEXP(par, 0, pari)
 506               = gen_rtx_SET (VOIDmode,
 507                              gen_rtx_MEM (SImode, address),
 508                              gen_rtx_REG (SImode, i));
 509             pari += 1;
 510           }
 511
 512       par = emit_insn (par);
 513       RTX_FRAME_RELATED_P (par) = 1;
 514     }
 515 }
 516
 517 void
 518 expand_prologue ()
 519 {
 520   HOST_WIDE_INT size;
 521
 522   /* SIZE includes the fixed stack space needed for function calls.  */
 523   size = get_frame_size () + current_function_outgoing_args_size;
 524   size += (current_function_outgoing_args_size ? 4 : 0);
 525
 526   /* If this is an old-style varargs function, then its arguments
 527      need to be flushed back to the stack.  */
 528   if (current_function_varargs)
 529     {
 530       emit_move_insn (gen_rtx_MEM (SImode,
 531                                    plus_constant (stack_pointer_rtx, 4)),
 532                       gen_rtx_REG (SImode, 0));
 533       emit_move_insn (gen_rtx_MEM (SImode,
 534                                    plus_constant (stack_pointer_rtx, 8)),
 535                       gen_rtx_REG (SImode, 1));
 536     }
 537
 538   /* If we use any of the callee-saved registers, save them now. */
 539   mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ());
 540
 541   /* Now put the frame pointer into the frame pointer register.  */
 542   if (frame_pointer_needed)
 543     emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
 544
 545   /* Allocate stack for this frame.  */
 546   if (size)
 547     emit_insn (gen_addsi3 (stack_pointer_rtx,
 548                            stack_pointer_rtx,
 549                            GEN_INT (-size)));
 550 }
 551
 552 void
 553 expand_epilogue ()
 554 {
 555   HOST_WIDE_INT size;
 556
 557   /* SIZE includes the fixed stack space needed for function calls.  */
 558   size = get_frame_size () + current_function_outgoing_args_size;
 559   size += (current_function_outgoing_args_size ? 4 : 0);
 560
 561   /* Maybe cut back the stack, except for the register save area.
 562
 563      If the frame pointer exists, then use the frame pointer to
 564      cut back the stack.
 565
 566      If the stack size + register save area is more than 255 bytes,
 567      then the stack must be cut back here since the size + register
 568      save size is too big for a ret/retf instruction.
 569
 570      Else leave it alone, it will be cut back as part of the
 571      ret/retf instruction, or there wasn't any stack to begin with.
 572
 573      Under no circumstanes should the register save area be
 574      deallocated here, that would leave a window where an interrupt
 575      could occur and trash the register save area.  */
 576   if (frame_pointer_needed)
 577     {
 578       emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
 579       size = 0;
 580     }
 581   else if (size + REG_SAVE_BYTES > 255)
 582     {
 583       emit_insn (gen_addsi3 (stack_pointer_rtx,
 584                              stack_pointer_rtx,
 585                              GEN_INT (size)));
 586       size = 0;
 587     }
 588
 589   /* Adjust the stack and restore callee-saved registers, if any.  */
 590   if (size || regs_ever_live[2] || regs_ever_live[3]
 591       || regs_ever_live[6] || regs_ever_live[7]
 592       || regs_ever_live[14] || regs_ever_live[15]
 593       || regs_ever_live[16] || regs_ever_live[17]
 594       || frame_pointer_needed)
 595     emit_jump_insn (gen_return_internal_regs
 596                     (GEN_INT (size + REG_SAVE_BYTES)));
 597   else
 598     emit_jump_insn (gen_return_internal ());
 599 }
 600
 601 /* Update the condition code from the insn.  */
 602
 603 void
 604 notice_update_cc (body, insn)
 605      rtx body;
 606      rtx insn;
 607 {
 608   switch (get_attr_cc (insn))
 609     {
 610     case CC_NONE:
 611       /* Insn does not affect CC at all.  */
 612       break;
 613
 614     case CC_NONE_0HIT:
 615       /* Insn does not change CC, but the 0'th operand has been changed.  */
 616       if (cc_status.value1 != 0
 617           && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
 618         cc_status.value1 = 0;
 619       break;
 620
 621     case CC_SET_ZN:
 622       /* Insn sets the Z,N flags of CC to recog_data.operand[0].
 623          V,C are unusable.  */
 624       CC_STATUS_INIT;
 625       cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE;
 626       cc_status.value1 = recog_data.operand[0];
 627       break;
 628
 629     case CC_SET_ZNV:
 630       /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
 631          C is unusable.  */
 632       CC_STATUS_INIT;
 633       cc_status.flags |= CC_NO_CARRY;
 634       cc_status.value1 = recog_data.operand[0];
 635       break;
 636
 637     case CC_COMPARE:
 638       /* The insn is a compare instruction.  */
 639       CC_STATUS_INIT;
 640       cc_status.value1 = SET_SRC (body);
 641       break;
 642
 643     case CC_INVERT:
 644       /* The insn is a compare instruction.  */
 645       CC_STATUS_INIT;
 646       cc_status.value1 = SET_SRC (body);
 647       cc_status.flags |= CC_INVERTED;
 648       break;
 649
 650     case CC_CLOBBER:
 651       /* Insn doesn't leave CC in a usable state.  */
 652       CC_STATUS_INIT;
 653       break;
 654
 655     default:
 656       abort ();
 657     }
 658 }
 659
 660 /* Recognise the PARALLEL rtx generated by mn10300_gen_multiple_store().
 661    This function is for MATCH_PARALLEL and so assumes OP is known to be
 662    parallel.  If OP is a multiple store, return a mask indicating which
 663    registers it saves.  Return 0 otherwise.  */
 664
 665 int
 666 store_multiple_operation (op, mode)
 667      rtx op;
 668      enum machine_mode mode ATTRIBUTE_UNUSED;
 669 {
 670   int count;
 671   int mask;
 672   int i;
 673   unsigned int last;
 674   rtx elt;
 675
 676   count = XVECLEN (op, 0);
 677   if (count < 2)
 678     return 0;
 679
 680   /* Check that first instruction has the form (set (sp) (plus A B)) */
 681   elt = XVECEXP (op, 0, 0);
 682   if (GET_CODE (elt) != SET
 683       || GET_CODE (SET_DEST (elt)) != REG
 684       || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM
 685       || GET_CODE (SET_SRC (elt)) != PLUS)
 686     return 0;
 687
 688   /* Check that A is the stack pointer and B is the expected stack size.
 689      For OP to match, each subsequent instruction should push a word onto
 690      the stack.  We therefore expect the first instruction to create
 691      COUNT-1 stack slots. */
 692   elt = SET_SRC (elt);
 693   if (GET_CODE (XEXP (elt, 0)) != REG
 694       || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
 695       || GET_CODE (XEXP (elt, 1)) != CONST_INT
 696       || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4)
 697     return 0;
 698
 699   /* Now go through the rest of the vector elements.  They must be
 700      ordered so that the first instruction stores the highest-numbered
 701      register to the highest stack slot and that subsequent instructions
 702      store a lower-numbered register to the slot below.
 703
 704      LAST keeps track of the smallest-numbered register stored so far.
 705      MASK is the set of stored registers. */
 706   last = FIRST_PSEUDO_REGISTER;
 707   mask = 0;
 708   for (i = 1; i < count; i++)
 709     {
 710       /* Check that element i is a (set (mem M) R) and that R is valid. */
 711       elt = XVECEXP (op, 0, i);
 712       if (GET_CODE (elt) != SET
 713           || GET_CODE (SET_DEST (elt)) != MEM
 714           || GET_CODE (SET_SRC (elt)) != REG
 715           || REGNO (SET_SRC (elt)) >= last)
 716         return 0;
 717
 718       /* R was OK, so provisionally add it to MASK.  We return 0 in any
 719          case if the rest of the instruction has a flaw. */
 720       last = REGNO (SET_SRC (elt));
 721       mask |= (1 << last);
 722
 723       /* Check that M has the form (plus (sp) (const_int -I*4)) */
 724       elt = XEXP (SET_DEST (elt), 0);
 725       if (GET_CODE (elt) != PLUS
 726           || GET_CODE (XEXP (elt, 0)) != REG
 727           || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
 728           || GET_CODE (XEXP (elt, 1)) != CONST_INT
 729           || INTVAL (XEXP (elt, 1)) != -i * 4)
 730         return 0;
 731     }
 732
 733   /* All or none of the callee-saved extended registers must be in the set. */
 734   if ((mask & 0x3c000) != 0
 735       && (mask & 0x3c000) != 0x3c000)
 736     return 0;
 737
 738   return mask;
 739 }
 740
 741 /* Return true if OP is a valid call operand.  */
 742
 743 int
 744 call_address_operand (op, mode)
 745      rtx op;
 746      enum machine_mode mode ATTRIBUTE_UNUSED;
 747 {
 748   return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
 749 }
 750
 751 /* What (if any) secondary registers are needed to move IN with mode
 752    MODE into a register in register class CLASS.
 753
 754    We might be able to simplify this.  */
 755 enum reg_class
 756 secondary_reload_class (class, mode, in)
 757      enum reg_class class;
 758      enum machine_mode mode;
 759      rtx in;
 760 {
 761   /* Memory loads less than a full word wide can't have an
 762      address or stack pointer destination.  They must use
 763      a data register as an intermediate register.  */
 764   if ((GET_CODE (in) == MEM
 765        || (GET_CODE (in) == REG
 766            && REGNO (in) >= FIRST_PSEUDO_REGISTER)
 767        || (GET_CODE (in) == SUBREG
 768            && GET_CODE (SUBREG_REG (in)) == REG
 769            && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER))
 770       && (mode == QImode || mode == HImode)
 771       && (class == ADDRESS_REGS || class == SP_REGS
 772           || class == SP_OR_ADDRESS_REGS))
 773     {
 774       if (TARGET_AM33)
 775         return DATA_OR_EXTENDED_REGS;
 776       return DATA_REGS;
 777     }
 778
 779   /* We can't directly load sp + const_int into a data register;
 780      we must use an address register as an intermediate.  */
 781   if (class != SP_REGS
 782       && class != ADDRESS_REGS
 783       && class != SP_OR_ADDRESS_REGS
 784       && class != SP_OR_EXTENDED_REGS
 785       && class != ADDRESS_OR_EXTENDED_REGS
 786       && class != SP_OR_ADDRESS_OR_EXTENDED_REGS
 787       && (in == stack_pointer_rtx
 788           || (GET_CODE (in) == PLUS
 789               && (XEXP (in, 0) == stack_pointer_rtx
 790                   || XEXP (in, 1) == stack_pointer_rtx))))
 791     return ADDRESS_REGS;
 792
 793   if (GET_CODE (in) == PLUS
 794       && (XEXP (in, 0) == stack_pointer_rtx
 795           || XEXP (in, 1) == stack_pointer_rtx))
 796     {
 797       if (TARGET_AM33)
 798         return DATA_OR_EXTENDED_REGS;
 799       return DATA_REGS;
 800     }
 801
 802   /* Otherwise assume no secondary reloads are needed.  */
 803   return NO_REGS;
 804 }
 805
 806 int
 807 initial_offset (from, to)
 808      int from, to;
 809 {
 810   /* The difference between the argument pointer and the frame pointer
 811      is the size of the callee register save area.  */
 812   if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
 813     {
 814       if (regs_ever_live[2] || regs_ever_live[3]
 815           || regs_ever_live[6] || regs_ever_live[7]
 816           || regs_ever_live[14] || regs_ever_live[15]
 817           || regs_ever_live[16] || regs_ever_live[17]
 818           || frame_pointer_needed)
 819         return REG_SAVE_BYTES;
 820       else
 821         return 0;
 822     }
 823
 824   /* The difference between the argument pointer and the stack pointer is
 825      the sum of the size of this function's frame, the callee register save
 826      area, and the fixed stack space needed for function calls (if any).  */
 827   if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
 828     {
 829       if (regs_ever_live[2] || regs_ever_live[3]
 830           || regs_ever_live[6] || regs_ever_live[7]
 831           || regs_ever_live[14] || regs_ever_live[15]
 832           || regs_ever_live[16] || regs_ever_live[17]
 833           || frame_pointer_needed)
 834         return (get_frame_size () + REG_SAVE_BYTES
 835                 + (current_function_outgoing_args_size
 836                    ? current_function_outgoing_args_size + 4 : 0));
 837       else
 838         return (get_frame_size ()
 839                 + (current_function_outgoing_args_size
 840                    ? current_function_outgoing_args_size + 4 : 0));
 841     }
 842
 843   /* The difference between the frame pointer and stack pointer is the sum
 844      of the size of this function's frame and the fixed stack space needed
 845      for function calls (if any).  */
 846   if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
 847     return (get_frame_size ()
 848             + (current_function_outgoing_args_size
 849                ? current_function_outgoing_args_size + 4 : 0));
 850
 851   abort ();
 852 }
 853
 854 /* Flush the argument registers to the stack for a stdarg function;
 855    return the new argument pointer.  */
 856 rtx
 857 mn10300_builtin_saveregs ()
 858 {
 859   rtx offset, mem;
 860   tree fntype = TREE_TYPE (current_function_decl);
 861   int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
 862                    && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
 863                        != void_type_node)))
 864                 ? UNITS_PER_WORD : 0);
 865   int set = get_varargs_alias_set ();
 866
 867   if (argadj)
 868     offset = plus_constant (current_function_arg_offset_rtx, argadj);
 869   else
 870     offset = current_function_arg_offset_rtx;
 871
 872   mem = gen_rtx_MEM (SImode, current_function_internal_arg_pointer);
 873   set_mem_alias_set (mem, set);
 874   emit_move_insn (mem, gen_rtx_REG (SImode, 0));
 875
 876   mem = gen_rtx_MEM (SImode,
 877                      plus_constant (current_function_internal_arg_pointer, 4));
 878   set_mem_alias_set (mem, set);
 879   emit_move_insn (mem, gen_rtx_REG (SImode, 1));
 880
 881   return copy_to_reg (expand_binop (Pmode, add_optab,
 882                                     current_function_internal_arg_pointer,
 883                                     offset, 0, 0, OPTAB_LIB_WIDEN));
 884 }
 885
 886 void
 887 mn10300_va_start (stdarg_p, valist, nextarg)
 888      int stdarg_p;
 889      tree valist;
 890      rtx nextarg;
 891 {
 892   if (stdarg_p)
 893     nextarg = expand_builtin_saveregs ();
 894
 895   std_expand_builtin_va_start (stdarg_p, valist, nextarg);
 896 }
 897
 898 rtx
 899 mn10300_va_arg (valist, type)
 900      tree valist, type;
 901 {
 902   HOST_WIDE_INT align, rsize;
 903   tree t, ptr, pptr;
 904
 905   /* Compute the rounded size of the type.  */
 906   align = PARM_BOUNDARY / BITS_PER_UNIT;
 907   rsize = (((int_size_in_bytes (type) + align - 1) / align) * align);
 908
 909   t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
 910              build_int_2 ((rsize > 8 ? 4 : rsize), 0));
 911   TREE_SIDE_EFFECTS (t) = 1;
 912
 913   ptr = build_pointer_type (type);
 914
 915   /* "Large" types are passed by reference.  */
 916   if (rsize > 8)
 917     {
 918       pptr = build_pointer_type (ptr);
 919       t = build1 (NOP_EXPR, pptr, t);
 920       TREE_SIDE_EFFECTS (t) = 1;
 921
 922       t = build1 (INDIRECT_REF, ptr, t);
 923       TREE_SIDE_EFFECTS (t) = 1;
 924     }
 925   else
 926     {
 927       t = build1 (NOP_EXPR, ptr, t);
 928       TREE_SIDE_EFFECTS (t) = 1;
 929     }
 930
 931   /* Calculate!  */
 932   return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
 933 }
 934
 935 /* Return an RTX to represent where a value with mode MODE will be returned
 936    from a function.  If the result is 0, the argument is pushed.  */
 937
 938 rtx
 939 function_arg (cum, mode, type, named)
 940      CUMULATIVE_ARGS *cum;
 941      enum machine_mode mode;
 942      tree type;
 943      int named ATTRIBUTE_UNUSED;
 944 {
 945   rtx result = 0;
 946   int size, align;
 947
 948   /* We only support using 2 data registers as argument registers.  */
 949   int nregs = 2;
 950
 951   /* Figure out the size of the object to be passed.  */
 952   if (mode == BLKmode)
 953     size = int_size_in_bytes (type);
 954   else
 955     size = GET_MODE_SIZE (mode);
 956
 957   /* Figure out the alignment of the object to be passed.  */
 958   align = size;
 959
 960   cum->nbytes = (cum->nbytes + 3) & ~3;
 961
 962   /* Don't pass this arg via a register if all the argument registers
 963      are used up.  */
 964   if (cum->nbytes > nregs * UNITS_PER_WORD)
 965     return 0;
 966
 967   /* Don't pass this arg via a register if it would be split between
 968      registers and memory.  */
 969   if (type == NULL_TREE
 970       && cum->nbytes + size > nregs * UNITS_PER_WORD)
 971     return 0;
 972
 973   switch (cum->nbytes / UNITS_PER_WORD)
 974     {
 975     case 0:
 976       result = gen_rtx_REG (mode, 0);
 977       break;
 978     case 1:
 979       result = gen_rtx_REG (mode, 1);
 980       break;
 981     default:
 982       result = 0;
 983     }
 984
 985   return result;
 986 }
 987
 988 /* Return the number of registers to use for an argument passed partially
 989    in registers and partially in memory.  */
 990
 991 int
 992 function_arg_partial_nregs (cum, mode, type, named)
 993      CUMULATIVE_ARGS *cum;
 994      enum machine_mode mode;
 995      tree type;
 996      int named ATTRIBUTE_UNUSED;
 997 {
 998   int size, align;
 999
1000   /* We only support using 2 data registers as argument registers.  */
1001   int nregs = 2;
1002
1003   /* Figure out the size of the object to be passed.  */
1004   if (mode == BLKmode)
1005     size = int_size_in_bytes (type);
1006   else
1007     size = GET_MODE_SIZE (mode);
1008
1009   /* Figure out the alignment of the object to be passed.  */
1010   align = size;
1011
1012   cum->nbytes = (cum->nbytes + 3) & ~3;
1013
1014   /* Don't pass this arg via a register if all the argument registers
1015      are used up.  */
1016   if (cum->nbytes > nregs * UNITS_PER_WORD)
1017     return 0;
1018
1019   if (cum->nbytes + size <= nregs * UNITS_PER_WORD)
1020     return 0;
1021
1022   /* Don't pass this arg via a register if it would be split between
1023      registers and memory.  */
1024   if (type == NULL_TREE
1025       && cum->nbytes + size > nregs * UNITS_PER_WORD)
1026     return 0;
1027
1028   return (nregs * UNITS_PER_WORD - cum->nbytes) / UNITS_PER_WORD;
1029 }
1030
1031 /* Output a tst insn.  */
1032 char *
1033 output_tst (operand, insn)
1034      rtx operand, insn;
1035 {
1036   rtx temp;
1037   int past_call = 0;
1038
1039   /* We can save a byte if we can find a register which has the value
1040      zero in it.  */
1041   temp = PREV_INSN (insn);
1042   while (optimize && temp)
1043     {
1044       rtx set;
1045
1046       /* We allow the search to go through call insns.  We record
1047          the fact that we've past a CALL_INSN and reject matches which
1048          use call clobbered registers.  */
1049       if (GET_CODE (temp) == CODE_LABEL
1050           || GET_CODE (temp) == JUMP_INSN
1051           || GET_CODE (temp) == BARRIER)
1052         break;
1053
1054       if (GET_CODE (temp) == CALL_INSN)
1055         past_call = 1;
1056
1057       if (GET_CODE (temp) == NOTE)
1058         {
1059           temp = PREV_INSN (temp);
1060           continue;
1061         }
1062
1063       /* It must be an insn, see if it is a simple set. */
1064       set = single_set (temp);
1065       if (!set)
1066         {
1067           temp = PREV_INSN (temp);
1068           continue;
1069         }
1070
1071       /* Are we setting a data register to zero (this does not win for
1072          address registers)?
1073
1074          If it's a call clobbered register, have we past a call?
1075
1076          Make sure the register we find isn't the same as ourself;
1077          the mn10300 can't encode that.
1078
1079          ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN
1080          so the code to detect calls here isn't doing anything useful.  */
1081       if (REG_P (SET_DEST (set))
1082           && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1083           && !reg_set_between_p (SET_DEST (set), temp, insn)
1084           && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1085               == REGNO_REG_CLASS (REGNO (operand)))
1086           && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS
1087           && REGNO (SET_DEST (set)) != REGNO (operand)
1088           && (!past_call
1089               || !call_used_regs[REGNO (SET_DEST (set))]))
1090         {
1091           rtx xoperands[2];
1092           xoperands[0] = operand;
1093           xoperands[1] = SET_DEST (set);
1094
1095           output_asm_insn ("cmp %1,%0", xoperands);
1096           return "";
1097         }
1098
1099       if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS
1100           && REG_P (SET_DEST (set))
1101           && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1102           && !reg_set_between_p (SET_DEST (set), temp, insn)
1103           && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1104               != REGNO_REG_CLASS (REGNO (operand)))
1105           && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS
1106           && REGNO (SET_DEST (set)) != REGNO (operand)
1107           && (!past_call
1108               || !call_used_regs[REGNO (SET_DEST (set))]))
1109         {
1110           rtx xoperands[2];
1111           xoperands[0] = operand;
1112           xoperands[1] = SET_DEST (set);
1113
1114           output_asm_insn ("cmp %1,%0", xoperands);
1115           return "";
1116         }
1117       temp = PREV_INSN (temp);
1118     }
1119   return "cmp 0,%0";
1120 }
1121
1122 int
1123 impossible_plus_operand (op, mode)
1124      rtx op;
1125      enum machine_mode mode ATTRIBUTE_UNUSED;
1126 {
1127   if (GET_CODE (op) != PLUS)
1128     return 0;
1129
1130   if (XEXP (op, 0) == stack_pointer_rtx
1131       || XEXP (op, 1) == stack_pointer_rtx)
1132     return 1;
1133
1134   return 0;
1135 }
1136
1137 /* Return 1 if X is a CONST_INT that is only 8 bits wide.  This is used
1138    for the btst insn which may examine memory or a register (the memory
1139    variant only allows an unsigned 8 bit integer).  */
1140 int
1141 const_8bit_operand (op, mode)
1142     register rtx op;
1143     enum machine_mode mode ATTRIBUTE_UNUSED;
1144 {
1145   return (GET_CODE (op) == CONST_INT
1146           && INTVAL (op) >= 0
1147           && INTVAL (op) < 256);
1148 }
1149
1150 /* Similarly, but when using a zero_extract pattern for a btst where
1151    the source operand might end up in memory.  */
1152 int
1153 mask_ok_for_mem_btst (len, bit)
1154      int len;
1155      int bit;
1156 {
1157   int mask = 0;
1158
1159   while (len > 0)
1160     {
1161       mask |= (1 << bit);
1162       bit++;
1163       len--;
1164     }
1165
1166   /* MASK must bit into an 8bit value.  */
1167   return (((mask & 0xff) == mask)
1168           || ((mask & 0xff00) == mask)
1169           || ((mask & 0xff0000) == mask)
1170           || ((mask & 0xff000000) == mask));
1171 }
1172
1173 /* Return 1 if X contains a symbolic expression.  We know these
1174    expressions will have one of a few well defined forms, so
1175    we need only check those forms.  */
1176 int
1177 symbolic_operand (op, mode)
1178      register rtx op;
1179      enum machine_mode mode ATTRIBUTE_UNUSED;
1180 {
1181   switch (GET_CODE (op))
1182     {
1183     case SYMBOL_REF:
1184     case LABEL_REF:
1185       return 1;
1186     case CONST:
1187       op = XEXP (op, 0);
1188       return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1189                || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1190               && GET_CODE (XEXP (op, 1)) == CONST_INT);
1191     default:
1192       return 0;
1193     }
1194 }
1195
1196 /* Try machine dependent ways of modifying an illegitimate address
1197    to be legitimate.  If we find one, return the new valid address.
1198    This macro is used in only one place: `memory_address' in explow.c.
1199
1200    OLDX is the address as it was before break_out_memory_refs was called.
1201    In some cases it is useful to look at this to decide what needs to be done.
1202
1203    MODE and WIN are passed so that this macro can use
1204    GO_IF_LEGITIMATE_ADDRESS.
1205
1206    Normally it is always safe for this macro to do nothing.  It exists to
1207    recognize opportunities to optimize the output.
1208
1209    But on a few ports with segmented architectures and indexed addressing
1210    (mn10300, hppa) it is used to rewrite certain problematical addresses.  */
1211 rtx
1212 legitimize_address (x, oldx, mode)
1213      rtx x;
1214      rtx oldx ATTRIBUTE_UNUSED;
1215      enum machine_mode mode ATTRIBUTE_UNUSED;
1216 {
1217   /* Uh-oh.  We might have an address for x[n-100000].  This needs
1218      special handling to avoid creating an indexed memory address
1219      with x-100000 as the base.  */
1220   if (GET_CODE (x) == PLUS
1221       && symbolic_operand (XEXP (x, 1), VOIDmode))
1222     {
1223       /* Ugly.  We modify things here so that the address offset specified
1224          by the index expression is computed first, then added to x to form
1225          the entire address.  */
1226
1227       rtx regx1, regy1, regy2, y;
1228
1229       /* Strip off any CONST.  */
1230       y = XEXP (x, 1);
1231       if (GET_CODE (y) == CONST)
1232         y = XEXP (y, 0);
1233
1234       if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1235         {
1236           regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1237           regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1238           regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1239           regx1 = force_reg (Pmode,
1240                              gen_rtx (GET_CODE (y), Pmode, regx1, regy2));
1241           return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1242         }
1243     }
1244   return x;
1245 }
1246
1247 int
1248 mn10300_address_cost (x, unsig)
1249      rtx x;
1250      int *unsig;
1251 {
1252   int _s = 0;
1253   if (unsig == 0)
1254     unsig = &_s;
1255
1256   switch (GET_CODE (x))
1257     {
1258     case REG:
1259       switch (REGNO_REG_CLASS (REGNO (x)))
1260         {
1261         case SP_REGS:
1262           *unsig = 1;
1263           return 0;
1264
1265         case ADDRESS_REGS:
1266           return 1;
1267
1268         case DATA_REGS:
1269         case EXTENDED_REGS:
1270           return 3;
1271
1272         case NO_REGS:
1273           return 5;
1274
1275         default:
1276           abort ();
1277         }
1278
1279     case PLUS:
1280     case MINUS:
1281     case ASHIFT:
1282     case AND:
1283     case IOR:
1284       return (mn10300_address_cost (XEXP (x, 0), unsig)
1285               + mn10300_address_cost (XEXP (x, 1), unsig));
1286
1287     case EXPR_LIST:
1288     case SUBREG:
1289     case MEM:
1290       return ADDRESS_COST (XEXP (x, 0));
1291
1292     case ZERO_EXTEND:
1293       *unsig = 1;
1294       return mn10300_address_cost (XEXP (x, 0), unsig);
1295
1296     case CONST_INT:
1297       if (INTVAL (x) == 0)
1298         return 0;
1299       if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100)
1300         return 1;
1301       if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000)
1302         return 3;
1303       if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000)
1304         return 5;
1305       return 7;
1306
1307     case CONST:
1308     case SYMBOL_REF:
1309     case LABEL_REF:
1310       return 8;
1311
1312     case ADDRESSOF:
1313       switch (GET_CODE (XEXP (x, 0)))
1314         {
1315         case MEM:
1316           return ADDRESS_COST (XEXP (x, 0));
1317
1318         case REG:
1319           return 1;
1320
1321         default:
1322           abort ();
1323         }
1324
1325     default:
1326       abort ();
1327
1328     }
1329 }