1 ;; FR30 machine description.
2 ;; Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc.
3 ;; Contributed by Cygnus Solutions.
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
27 (define_attr "length" "" (const_int 2))
29 ;; Used to distinguish between small memory model targets and big mode targets.
31 (define_attr "size" "small,big"
32 (const (if_then_else (symbol_ref "TARGET_SMALL_MODEL")
33 (const_string "small")
34 (const_string "big"))))
37 ;; Define an attribute to be used by the delay slot code.
38 ;; An instruction by default is considered to be 'delyabable'
39 ;; that is, it can be placed into a delay slot, but it is not
40 ;; itself an delyaed branch type instruction. An instruction
41 ;; whoes type is 'delayed' is one which has a delay slot, and
42 ;; an instruction whoes delay_type is 'other' is one which does
43 ;; not have a delay slot, nor can it be placed into a delay slot.
45 (define_attr "delay_type" "delayable,delayed,other" (const_string "delayable"))
48 ;;{{{ Delay Slot Specifications
50 (define_delay (eq_attr "delay_type" "delayed")
51 [(and (eq_attr "delay_type" "delayable")
52 (eq_attr "length" "2"))
62 ;; Wrap moves in define_expand to prevent memory->memory moves from being
63 ;; generated at the RTL level, which generates better code for most machines
64 ;; which can't do mem->mem moves.
66 ;; If operand 0 is a `subreg' with mode M of a register whose own mode is wider
67 ;; than M, the effect of this instruction is to store the specified value in
68 ;; the part of the register that corresponds to mode M. The effect on the rest
69 ;; of the register is undefined.
71 ;; This class of patterns is special in several ways. First of all, each of
72 ;; these names *must* be defined, because there is no other way to copy a datum
73 ;; from one place to another.
75 ;; Second, these patterns are not used solely in the RTL generation pass. Even
76 ;; the reload pass can generate move insns to copy values from stack slots into
77 ;; temporary registers. When it does so, one of the operands is a hard
78 ;; register and the other is an operand that can need to be reloaded into a
81 ;; Therefore, when given such a pair of operands, the pattern must
82 ;; generate RTL which needs no reloading and needs no temporary
83 ;; registers--no registers other than the operands. For example, if
84 ;; you support the pattern with a `define_expand', then in such a
85 ;; case the `define_expand' mustn't call `force_reg' or any other such
86 ;; function which might generate new pseudo registers.
88 ;; This requirement exists even for subword modes on a RISC machine
89 ;; where fetching those modes from memory normally requires several
90 ;; insns and some temporary registers. Look in `spur.md' to see how
91 ;; the requirement can be satisfied.
93 ;; During reload a memory reference with an invalid address may be passed as an
94 ;; operand. Such an address will be replaced with a valid address later in the
95 ;; reload pass. In this case, nothing may be done with the address except to
96 ;; use it as it stands. If it is copied, it will not be replaced with a valid
97 ;; address. No attempt should be made to make such an address into a valid
98 ;; address and no routine (such as `change_address') that will do so may be
99 ;; called. Note that `general_operand' will fail when applied to such an
102 ;; The global variable `reload_in_progress' (which must be explicitly declared
103 ;; if required) can be used to determine whether such special handling is
106 ;; The variety of operands that have reloads depends on the rest of
107 ;; the machine description, but typically on a RISC machine these can
108 ;; only be pseudo registers that did not get hard registers, while on
109 ;; other machines explicit memory references will get optional
112 ;; If a scratch register is required to move an object to or from memory, it
113 ;; can be allocated using `gen_reg_rtx' prior to reload. But this is
114 ;; impossible during and after reload. If there are cases needing scratch
115 ;; registers after reload, you must define `SECONDARY_INPUT_RELOAD_CLASS' and
116 ;; perhaps also `SECONDARY_OUTPUT_RELOAD_CLASS' to detect them, and provide
117 ;; patterns `reload_inM' or `reload_outM' to handle them.
119 ;; The constraints on a `moveM' must permit moving any hard register to any
120 ;; other hard register provided that `HARD_REGNO_MODE_OK' permits mode M in
121 ;; both registers and `REGISTER_MOVE_COST' applied to their classes returns a
124 ;; It is obligatory to support floating point `moveM' instructions
125 ;; into and out of any registers that can hold fixed point values,
126 ;; because unions and structures (which have modes `SImode' or
127 ;; `DImode') can be in those registers and they may have floating
130 ;; There may also be a need to support fixed point `moveM' instructions in and
131 ;; out of floating point registers. Unfortunately, I have forgotten why this
132 ;; was so, and I don't know whether it is still true. If `HARD_REGNO_MODE_OK'
133 ;; rejects fixed point values in floating point registers, then the constraints
134 ;; of the fixed point `moveM' instructions must be designed to avoid ever
135 ;; trying to reload into a floating point register.
140 ;; Push a register onto the stack
141 (define_insn "movsi_push"
142 [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
143 (match_operand:SI 0 "register_operand" "a"))]
148 ;; Pop a register off the stack
149 (define_insn "movsi_pop"
150 [(set:SI (match_operand:SI 0 "register_operand" "=a")
151 (mem:SI (post_inc:SI (reg:SI 15))))]
159 (define_expand "movqi"
160 [(set (match_operand:QI 0 "general_operand" "")
161 (match_operand:QI 1 "general_operand" ""))]
165 if (!reload_in_progress
167 && GET_CODE (operands[0]) == MEM
168 && (GET_CODE (operands[1]) == MEM
169 || immediate_operand (operands[1], QImode)))
170 operands[1] = copy_to_mode_reg (QImode, operands[1]);
173 (define_insn "movqi_unsigned_register_load"
174 [(set (match_operand:SI 0 "register_operand" "=r")
175 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
180 (define_expand "movqi_signed_register_load"
181 [(set (match_operand:SI 0 "register_operand" "")
182 (sign_extend:SI (match_operand:QI 1 "memory_operand" "")))]
185 emit_insn (gen_movqi_unsigned_register_load (operands[0], operands[1]));
186 emit_insn (gen_extendqisi2 (operands[0], operands[0]));
191 (define_insn "*movqi_internal"
192 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,red,m,r")
193 (match_operand:QI 1 "general_operand" "i,red,r,rm"))]
205 (define_expand "movhi"
206 [(set (match_operand:HI 0 "general_operand" "")
207 (match_operand:HI 1 "general_operand" ""))]
211 if (!reload_in_progress
213 && GET_CODE (operands[0]) == MEM
214 && (GET_CODE (operands[1]) == MEM
215 || immediate_operand (operands[1], HImode)))
216 operands[1] = copy_to_mode_reg (HImode, operands[1]);
219 (define_insn "movhi_unsigned_register_load"
220 [(set (match_operand:SI 0 "register_operand" "=r")
221 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
226 (define_expand "movhi_signed_register_load"
227 [(set (match_operand:SI 0 "register_operand" "")
228 (sign_extend:SI (match_operand:HI 1 "memory_operand" "")))]
231 emit_insn (gen_movhi_unsigned_register_load (operands[0], operands[1]));
232 emit_insn (gen_extendhisi2 (operands[0], operands[0]));
237 (define_insn "*movhi_internal"
238 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,red,m,r")
239 (match_operand:HI 1 "general_operand" "L,M,n,red,r,rm"))]
248 [(set_attr "length" "*,4,6,*,*,*")]
254 ;; If the destination is a MEM and the source is a
255 ;; MEM or an CONST_INT move the source into a register.
256 (define_expand "movsi"
257 [(set (match_operand:SI 0 "nonimmediate_operand" "")
258 (match_operand:SI 1 "general_operand" ""))]
261 if (!reload_in_progress
263 && GET_CODE(operands[0]) == MEM
264 && (GET_CODE (operands[1]) == MEM
265 || immediate_operand (operands[1], SImode)))
266 operands[1] = copy_to_mode_reg (SImode, operands[1]);
270 ;; We can do some clever tricks when loading certain immediate
271 ;; values. We implement these tricks as define_splits, rather
272 ;; than putting the code into the define_expand "movsi" above,
273 ;; because if we put them there, they will be evaluated at RTL
274 ;; generation time and then the combiner pass will come along
275 ;; and replace the multiple insns that have been generated with
276 ;; the original, slower, load insns. (The combiner pass only
277 ;; cares about reducing the number of instructions, it does not
278 ;; care about instruction lengths or speeds). Splits are
279 ;; evaluated after the combine pass and before the scheduling
280 ;; passes, so that they are the perfect place to put this
283 ;; XXX we probably ought to implement these for QI and HI mode
286 ;; If we are loading a small negative constant we can save space
287 ;; and time by loading the positive value and then sign extending it.
289 [(set (match_operand:SI 0 "register_operand" "")
290 (match_operand:SI 1 "immediate_operand" ""))]
291 "INTVAL (operands[1]) <= -1 && INTVAL (operands[1]) >= -128"
292 [(set:SI (match_dup 0) (match_dup 2))
293 (set:SI (match_dup 0) (sign_extend:SI (subreg:QI (match_dup 0) 0)))]
295 operands[2] = GEN_INT (INTVAL (operands[1]) & 0xff);
299 ;; If we are loading a large negative constant, one which does
300 ;; not have any of its bottom 24 bit set, then we can save time
301 ;; and space by loading the byte value and shifting it into place.
303 [(set (match_operand:SI 0 "register_operand" "")
304 (match_operand:SI 1 "immediate_operand" ""))]
305 "(INTVAL (operands[1]) < 0) && ((INTVAL (operands[1]) & 0x00ffffff) == 0)"
306 [(set:SI (match_dup 0) (match_dup 2))
307 (parallel [(set:SI (match_dup 0) (ashift:SI (match_dup 0) (const_int 24)))
308 (clobber (reg:CC 16))])]
310 HOST_WIDE_INT val = INTVAL (operands[1]);
311 operands[2] = GEN_INT (val >> 24);
315 ;; If we are loading a large positive constant, one which has bits
316 ;; in the top byte set, but whoes set bits all lie within an 8 bit
317 ;; range, then we can save time and space by loading the byte value
318 ;; and shifting it into place.
320 [(set (match_operand:SI 0 "register_operand" "")
321 (match_operand:SI 1 "immediate_operand" ""))]
322 "(INTVAL (operands[1]) > 0x00ffffff)
323 && ((INTVAL (operands[1]) >> exact_log2 (INTVAL (operands[1]) & (- INTVAL (operands[1])))) < 0x100)"
324 [(set:SI (match_dup 0) (match_dup 2))
325 (parallel [(set:SI (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))
326 (clobber (reg:CC 16))])]
328 HOST_WIDE_INT val = INTVAL (operands[1]);
329 int shift = exact_log2 (val & ( - val));
330 operands[2] = GEN_INT (val >> shift);
331 operands[3] = GEN_INT (shift);
335 ;; When TARGET_SMALL_MODEL is defined we assume that all symbolic
336 ;; values are addresses which will fit in 20 bits.
338 (define_insn "movsi_internal"
339 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,red,m,r")
340 (match_operand:SI 1 "general_operand" "L,M,n,i,rde,r,rm"))]
344 switch (which_alternative)
346 case 0: return \"ldi:8 \\t#%1, %0\";
347 case 1: return \"ldi:20\\t#%1, %0\";
348 case 2: return \"ldi:32\\t#%1, %0\";
349 case 3: if (TARGET_SMALL_MODEL)
350 return \"ldi:20\\t%1, %0\";
352 return \"ldi:32\\t%1, %0\";
353 case 4: return \"mov \\t%1, %0\";
354 case 5: return \"st \\t%1, %0\";
355 case 6: return \"ld \\t%1, %0\";
359 [(set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 4)
360 (eq_attr "alternative" "2") (const_int 6)
361 (eq_attr "alternative" "3")
362 (if_then_else (eq_attr "size" "small")
371 ;; Note - the FR30 does not have an 8 byte load/store instruction
372 ;; but we have to support this pattern because some other patterns
373 ;; (eg muldisi2) can produce a DImode result.
374 ;; (This code is stolen from the M32R port.)
376 (define_expand "movdi"
377 [(set (match_operand:DI 0 "general_operand" "")
378 (match_operand:DI 1 "general_operand" ""))]
381 /* Everything except mem = const or mem = mem can be done easily. */
383 if (GET_CODE (operands[0]) == MEM)
384 operands[1] = force_reg (DImode, operands[1]);
387 ;; We use an insn and a split so that we can generate
388 ;; RTL rather than text from fr30_move_double().
390 (define_insn "*movdi_insn"
391 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,m,r")
392 (match_operand:DI 1 "di_operand" "r,m,r,nF"))]
393 "register_operand (operands[0], DImode) || register_operand (operands[1], DImode)"
395 [(set_attr "length" "4,8,12,12")]
399 [(set (match_operand:DI 0 "nonimmediate_di_operand" "")
400 (match_operand:DI 1 "di_operand" ""))]
403 "operands[2] = fr30_move_double (operands);")
406 ;;{{{ Load & Store Multiple Registers
408 ;; The load multiple and store multiple patterns are implemented
409 ;; as peepholes because the only time they are expected to occur
410 ;; is during function prologues and epilogues.
413 [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
414 (match_operand:SI 0 "high_register_operand" "h"))
415 (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
416 (match_operand:SI 1 "high_register_operand" "h"))
417 (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
418 (match_operand:SI 2 "high_register_operand" "h"))
419 (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
420 (match_operand:SI 3 "high_register_operand" "h"))]
421 "fr30_check_multiple_regs (operands, 4, 1)"
422 "stm1 (%0, %1, %2, %3)"
423 [(set_attr "delay_type" "other")]
427 [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
428 (match_operand:SI 0 "high_register_operand" "h"))
429 (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
430 (match_operand:SI 1 "high_register_operand" "h"))
431 (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
432 (match_operand:SI 2 "high_register_operand" "h"))]
433 "fr30_check_multiple_regs (operands, 3, 1)"
435 [(set_attr "delay_type" "other")]
439 [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
440 (match_operand:SI 0 "high_register_operand" "h"))
441 (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
442 (match_operand:SI 1 "high_register_operand" "h"))]
443 "fr30_check_multiple_regs (operands, 2, 1)"
445 [(set_attr "delay_type" "other")]
449 [(set:SI (match_operand:SI 0 "high_register_operand" "h")
450 (mem:SI (post_inc:SI (reg:SI 15))))
451 (set:SI (match_operand:SI 1 "high_register_operand" "h")
452 (mem:SI (post_inc:SI (reg:SI 15))))
453 (set:SI (match_operand:SI 2 "high_register_operand" "h")
454 (mem:SI (post_inc:SI (reg:SI 15))))
455 (set:SI (match_operand:SI 3 "high_register_operand" "h")
456 (mem:SI (post_inc:SI (reg:SI 15))))]
457 "fr30_check_multiple_regs (operands, 4, 0)"
458 "ldm1 (%0, %1, %2, %3)"
459 [(set_attr "delay_type" "other")]
463 [(set:SI (match_operand:SI 0 "high_register_operand" "h")
464 (mem:SI (post_inc:SI (reg:SI 15))))
465 (set:SI (match_operand:SI 1 "high_register_operand" "h")
466 (mem:SI (post_inc:SI (reg:SI 15))))
467 (set:SI (match_operand:SI 2 "high_register_operand" "h")
468 (mem:SI (post_inc:SI (reg:SI 15))))]
469 "fr30_check_multiple_regs (operands, 3, 0)"
471 [(set_attr "delay_type" "other")]
475 [(set:SI (match_operand:SI 0 "high_register_operand" "h")
476 (mem:SI (post_inc:SI (reg:SI 15))))
477 (set:SI (match_operand:SI 1 "high_register_operand" "h")
478 (mem:SI (post_inc:SI (reg:SI 15))))]
479 "fr30_check_multiple_regs (operands, 2, 0)"
481 [(set_attr "delay_type" "other")]
485 [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
486 (match_operand:SI 0 "low_register_operand" "l"))
487 (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
488 (match_operand:SI 1 "low_register_operand" "l"))
489 (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
490 (match_operand:SI 2 "low_register_operand" "l"))
491 (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
492 (match_operand:SI 3 "low_register_operand" "l"))]
493 "fr30_check_multiple_regs (operands, 4, 1)"
494 "stm0 (%0, %1, %2, %3)"
495 [(set_attr "delay_type" "other")]
499 [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
500 (match_operand:SI 0 "low_register_operand" "l"))
501 (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
502 (match_operand:SI 1 "low_register_operand" "l"))
503 (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
504 (match_operand:SI 2 "low_register_operand" "l"))]
505 "fr30_check_multiple_regs (operands, 3, 1)"
507 [(set_attr "delay_type" "other")]
511 [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
512 (match_operand:SI 0 "low_register_operand" "l"))
513 (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
514 (match_operand:SI 1 "low_register_operand" "l"))]
515 "fr30_check_multiple_regs (operands, 2, 1)"
517 [(set_attr "delay_type" "other")]
521 ;;{{{ Floating Point Moves
523 ;; Note - Patterns for SF mode moves are compulsory, but
524 ;; patterns for DF are optional, as GCC can synthesise them.
526 (define_expand "movsf"
527 [(set (match_operand:SF 0 "general_operand" "")
528 (match_operand:SF 1 "general_operand" ""))]
531 if (!reload_in_progress && !reload_completed
532 && memory_operand (operands[0], SFmode)
533 && memory_operand (operands[1], SFmode))
534 operands[1] = copy_to_mode_reg (SFmode, operands[1]);
538 (define_insn "*movsf_internal"
539 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,red,m,r")
540 (match_operand:SF 1 "general_operand" "Fn,i,rde,r,rm"))]
544 switch (which_alternative)
546 case 0: return \"ldi:32\\t%1, %0\";
547 case 1: if (TARGET_SMALL_MODEL)
548 return \"ldi:20\\t%1, %0\";
550 return \"ldi:32\\t%1, %0\";
551 case 2: return \"mov \\t%1, %0\";
552 case 3: return \"st \\t%1, %0\";
553 case 4: return \"ld \\t%1, %0\";
557 [(set (attr "length") (cond [(eq_attr "alternative" "0") (const_int 6)
558 (eq_attr "alternative" "1")
559 (if_then_else (eq_attr "size" "small")
565 (define_insn "*movsf_constant_store"
566 [(set (match_operand:SF 0 "memory_operand" "=m")
567 (match_operand:SF 1 "immediate_operand" "F"))]
572 const char * tmp_reg;
573 static char buffer[100];
576 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
578 if (REAL_VALUES_EQUAL (d, dconst0))
579 ldi_instr = \"ldi:8\";
581 ldi_instr = \"ldi:32\";
583 tmp_reg = reg_names [COMPILER_SCRATCH_REGISTER];
585 sprintf (buffer, \"%s\\t#%%1, %s\\t;\\n\\tst\\t%s, %%0\\t; Created by movsf_constant_store\",
586 ldi_instr, tmp_reg, tmp_reg);
590 [(set_attr "length" "8")]
598 ;; Signed conversions from a smaller integer to a larger integer
600 (define_insn "extendqisi2"
601 [(set (match_operand:SI 0 "register_operand" "=r")
602 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
607 (define_insn "extendhisi2"
608 [(set (match_operand:SI 0 "register_operand" "=r")
609 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
614 ;; Unsigned conversions from a smaller integer to a larger integer
616 (define_insn "zero_extendqisi2"
617 [(set (match_operand:SI 0 "register_operand" "=r")
618 (zero_extend:SI (match_operand:QI 1 "register_operand" "0")))]
623 (define_insn "zero_extendhisi2"
624 [(set (match_operand:SI 0 "register_operand" "=r")
625 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
635 ;; This is a special pattern just for adjusting the stack size.
636 (define_insn "add_to_stack"
639 (match_operand:SI 0 "stack_add_operand" "i")))]
644 ;; We need some trickery to be able to handle the addition of
645 ;; large (ie outside +/- 16) constants. We need to be able to
646 ;; handle this because reload assumes that it can generate add
647 ;; instructions with arbitary sized constants.
648 (define_expand "addsi3"
649 [(set (match_operand:SI 0 "register_operand" "")
650 (plus:SI (match_operand:SI 1 "register_operand" "")
651 (match_operand:SI 2 "nonmemory_operand" "")))]
654 if ( GET_CODE (operands[2]) == REG
655 || GET_CODE (operands[2]) == SUBREG)
656 emit_insn (gen_addsi_regs (operands[0], operands[1], operands[2]));
657 else if (GET_CODE (operands[2]) != CONST_INT)
658 emit_insn (gen_addsi_big_int (operands[0], operands[1], operands[2]));
659 else if ( (REGNO (operands[1]) != FRAME_POINTER_REGNUM)
660 && (REGNO (operands[1]) != ARG_POINTER_REGNUM)
661 && (INTVAL (operands[2]) >= -16)
662 && (INTVAL (operands[2]) <= 15))
663 emit_insn (gen_addsi_small_int (operands[0], operands[1], operands[2]));
665 emit_insn (gen_addsi_big_int (operands[0], operands[1], operands[2]));
670 (define_insn "addsi_regs"
671 [(set (match_operand:SI 0 "register_operand" "=r")
672 (plus:SI (match_operand:SI 1 "register_operand" "%0")
673 (match_operand:SI 2 "register_operand" "r")))]
678 ;; Do not allow an eliminable register in the source register. It
679 ;; might be eliminated in favour of the stack pointer, probably
680 ;; increasing the offset, and so rendering the instruction illegal.
681 (define_insn "addsi_small_int"
682 [(set (match_operand:SI 0 "register_operand" "=r,r")
683 (plus:SI (match_operand:SI 1 "register_operand" "0,0")
684 (match_operand:SI 2 "add_immediate_operand" "I,J")))]
685 " (REGNO (operands[1]) != FRAME_POINTER_REGNUM)
686 && (REGNO (operands[1]) != ARG_POINTER_REGNUM)"
692 (define_expand "addsi_big_int"
693 [(set (match_operand:SI 0 "register_operand" "")
694 (plus:SI (match_operand:SI 1 "register_operand" "")
695 (match_operand:SI 2 "immediate_operand" "")))]
698 /* Cope with the possibility that ops 0 and 1 are the same register. */
699 if (REGNO (operands[0]) == REGNO (operands[1]))
701 if (reload_in_progress || reload_completed)
703 rtx reg = gen_rtx_REG (SImode, 0/*COMPILER_SCRATCH_REGISTER*/);
705 emit_insn (gen_movsi (reg, operands[2]));
706 emit_insn (gen_addsi_regs (operands[0], operands[0], reg));
710 operands[2] = force_reg (SImode, operands[2]);
711 emit_insn (gen_addsi_regs (operands[0], operands[0], operands[2]));
716 emit_insn (gen_movsi (operands[0], operands[2]));
717 emit_insn (gen_addsi_regs (operands[0], operands[0], operands[1]));
723 (define_insn "*addsi_for_reload"
724 [(set (match_operand:SI 0 "register_operand" "=&r,r,r")
725 (plus:SI (match_operand:SI 1 "register_operand" "r,r,r")
726 (match_operand:SI 2 "immediate_operand" "L,M,n")))]
727 "reload_in_progress || reload_completed"
729 ldi:8\\t#%2, %0 \\n\\taddn\\t%1, %0
730 ldi:20\\t#%2, %0 \\n\\taddn\\t%1, %0
731 ldi:32\\t#%2, %0 \\n\\taddn\\t%1, %0"
732 [(set_attr "length" "4,6,8")]
738 (define_insn "subsi3"
739 [(set (match_operand:SI 0 "register_operand" "=r")
740 (minus:SI (match_operand:SI 1 "register_operand" "0")
741 (match_operand:SI 2 "register_operand" "r")))]
749 ;; Signed multiplication producing 64 bit results from 32 bit inputs
750 (define_insn "mulsidi3"
751 [(set (match_operand:DI 0 "register_operand" "=r")
752 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%r"))
753 (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))
754 (clobber (reg:CC 16))]
756 "mul %2, %1\\n\\tmov\\tmdh, %0\\n\\tmov\\tmdl, %p0"
757 [(set_attr "length" "6")]
760 ;; Unsigned multiplication producing 64 bit results from 32 bit inputs
761 (define_insn "umulsidi3"
762 [(set (match_operand:DI 0 "register_operand" "=r")
763 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r"))
764 (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))
765 (clobber (reg:CC 16))]
767 "mulu %2, %1\\n\\tmov\\tmdh, %0\\n\\tmov\\tmdl, %p0"
768 [(set_attr "length" "6")]
771 ;; Signed multiplication producing 32 bit result from 16 bit inputs
772 (define_insn "mulhisi3"
773 [(set (match_operand:SI 0 "register_operand" "=r")
774 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%r"))
775 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))
776 (clobber (reg:CC 16))]
778 "mulh %2, %1\\n\\tmov\\tmdl, %0"
779 [(set_attr "length" "4")]
782 ;; Unsigned multiplication producing 32 bit result from 16 bit inputs
783 (define_insn "umulhisi3"
784 [(set (match_operand:SI 0 "register_operand" "=r")
785 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%r"))
786 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))
787 (clobber (reg:CC 16))]
789 "muluh %2, %1\\n\\tmov\\tmdl, %0"
790 [(set_attr "length" "4")]
793 ;; Signed multiplication producing 32 bit result from 32 bit inputs
794 (define_insn "mulsi3"
795 [(set (match_operand:SI 0 "register_operand" "=r")
796 (mult:SI (match_operand:SI 1 "register_operand" "%r")
797 (match_operand:SI 2 "register_operand" "r")))
798 (clobber (reg:CC 16))]
800 "mul %2, %1\\n\\tmov\\tmdl, %0"
801 [(set_attr "length" "4")]
807 (define_expand "negsi2"
808 [(set (match_operand:SI 0 "register_operand" "")
809 (neg:SI (match_operand:SI 1 "register_operand" "")))]
812 if (REGNO (operands[0]) == REGNO (operands[1]))
814 if (reload_in_progress || reload_completed)
816 rtx reg = gen_rtx_REG (SImode, 0/*COMPILER_SCRATCH_REGISTER*/);
818 emit_insn (gen_movsi (reg, GEN_INT (0)));
819 emit_insn (gen_subsi3 (reg, reg, operands[0]));
820 emit_insn (gen_movsi (operands[0], reg));
824 rtx reg = gen_reg_rtx (SImode);
826 emit_insn (gen_movsi (reg, GEN_INT (0)));
827 emit_insn (gen_subsi3 (reg, reg, operands[0]));
828 emit_insn (gen_movsi (operands[0], reg));
833 emit_insn (gen_movsi_internal (operands[0], GEN_INT (0)));
834 emit_insn (gen_subsi3 (operands[0], operands[0], operands[1]));
845 ;; Arithmetic Shift Left
846 (define_insn "ashlsi3"
847 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
848 (ashift:SI (match_operand:SI 1 "register_operand" "0,0,0")
849 (match_operand:SI 2 "nonmemory_operand" "r,I,K")))
850 (clobber (reg:CC 16))]
858 ;; Arithmetic Shift Right
859 (define_insn "ashrsi3"
860 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
861 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,0")
862 (match_operand:SI 2 "nonmemory_operand" "r,I,K")))
863 (clobber (reg:CC 16))]
871 ;; Logical Shift Right
872 (define_insn "lshrsi3"
873 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
874 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,0")
875 (match_operand:SI 2 "nonmemory_operand" "r,I,K")))
876 (clobber (reg:CC 16))]
885 ;;{{{ Logical Operations
887 ;; Logical AND, 32 bit integers
888 (define_insn "andsi3"
889 [(set (match_operand:SI 0 "register_operand" "=r")
890 (and:SI (match_operand:SI 1 "register_operand" "%r")
891 (match_operand:SI 2 "register_operand" "0")))
892 (clobber (reg:CC 16))]
897 ;; Inclusive OR, 32 bit integers
898 (define_insn "iorsi3"
899 [(set (match_operand:SI 0 "register_operand" "=r")
900 (ior:SI (match_operand:SI 1 "register_operand" "%r")
901 (match_operand:SI 2 "register_operand" "0")))
902 (clobber (reg:CC 16))]
907 ;; Exclusive OR, 32 bit integers
908 (define_insn "xorsi3"
909 [(set (match_operand:SI 0 "register_operand" "=r")
910 (xor:SI (match_operand:SI 1 "register_operand" "%r")
911 (match_operand:SI 2 "register_operand" "0")))
912 (clobber (reg:CC 16))]
917 ;; One's complement, 32 bit integers
918 (define_expand "one_cmplsi2"
919 [(set (match_operand:SI 0 "register_operand" "")
920 (not:SI (match_operand:SI 1 "register_operand" "")))]
923 if (REGNO (operands[0]) == REGNO (operands[1]))
925 if (reload_in_progress || reload_completed)
927 rtx reg = gen_rtx_REG (SImode, 0/*COMPILER_SCRATCH_REGISTER*/);
929 emit_insn (gen_movsi (reg, GEN_INT (-1)));
930 emit_insn (gen_xorsi3 (operands[0], operands[0], reg));
934 rtx reg = gen_reg_rtx (SImode);
936 emit_insn (gen_movsi (reg, GEN_INT (-1)));
937 emit_insn (gen_xorsi3 (operands[0], operands[0], reg));
942 emit_insn (gen_movsi_internal (operands[0], GEN_INT (-1)));
943 emit_insn (gen_xorsi3 (operands[0], operands[1], operands[0]));
952 ;; Note, we store the operands in the comparison insns, and use them later
953 ;; when generating the branch or scc operation.
955 ;; First the routines called by the machine independent part of the compiler
956 (define_expand "cmpsi"
958 (compare:CC (match_operand:SI 0 "register_operand" "")
959 (match_operand:SI 1 "nonmemory_operand" "")))]
962 fr30_compare_op0 = operands[0];
963 fr30_compare_op1 = operands[1];
968 ;; Now, the actual comparisons, generated by the branch and/or scc operations
970 (define_insn "*cmpsi_internal"
972 (compare:CC (match_operand:SI 0 "register_operand" "r,r,r")
973 (match_operand:SI 1 "nonmemory_operand" "r,I,J")))]
984 ;; Define_expands called by the machine independent part of the compiler
985 ;; to allocate a new comparison register
989 (compare:CC (match_dup 1)
992 (if_then_else (eq:CC (reg:CC 16)
994 (label_ref (match_operand 0 "" ""))
998 operands[1] = fr30_compare_op0;
999 operands[2] = fr30_compare_op1;
1003 (define_expand "bne"
1005 (compare:CC (match_dup 1)
1008 (if_then_else (ne:CC (reg:CC 16)
1010 (label_ref (match_operand 0 "" ""))
1014 operands[1] = fr30_compare_op0;
1015 operands[2] = fr30_compare_op1;
1019 (define_expand "blt"
1021 (compare:CC (match_dup 1)
1024 (if_then_else (lt:CC (reg:CC 16)
1026 (label_ref (match_operand 0 "" ""))
1030 operands[1] = fr30_compare_op0;
1031 operands[2] = fr30_compare_op1;
1035 (define_expand "ble"
1037 (compare:CC (match_dup 1)
1040 (if_then_else (le:CC (reg:CC 16)
1042 (label_ref (match_operand 0 "" ""))
1046 operands[1] = fr30_compare_op0;
1047 operands[2] = fr30_compare_op1;
1051 (define_expand "bgt"
1053 (compare:CC (match_dup 1)
1056 (if_then_else (gt:CC (reg:CC 16)
1058 (label_ref (match_operand 0 "" ""))
1062 operands[1] = fr30_compare_op0;
1063 operands[2] = fr30_compare_op1;
1067 (define_expand "bge"
1069 (compare:CC (match_dup 1)
1072 (if_then_else (ge:CC (reg:CC 16)
1074 (label_ref (match_operand 0 "" ""))
1078 operands[1] = fr30_compare_op0;
1079 operands[2] = fr30_compare_op1;
1083 (define_expand "bltu"
1085 (compare:CC (match_dup 1)
1088 (if_then_else (ltu:CC (reg:CC 16)
1090 (label_ref (match_operand 0 "" ""))
1094 operands[1] = fr30_compare_op0;
1095 operands[2] = fr30_compare_op1;
1099 (define_expand "bleu"
1101 (compare:CC (match_dup 1)
1104 (if_then_else (leu:CC (reg:CC 16)
1106 (label_ref (match_operand 0 "" ""))
1110 operands[1] = fr30_compare_op0;
1111 operands[2] = fr30_compare_op1;
1115 (define_expand "bgtu"
1117 (compare:CC (match_dup 1)
1120 (if_then_else (gtu:CC (reg:CC 16)
1122 (label_ref (match_operand 0 "" ""))
1126 operands[1] = fr30_compare_op0;
1127 operands[2] = fr30_compare_op1;
1131 (define_expand "bgeu"
1133 (compare:CC (match_dup 1)
1136 (if_then_else (geu:CC (reg:CC 16)
1138 (label_ref (match_operand 0 "" ""))
1142 operands[1] = fr30_compare_op0;
1143 operands[2] = fr30_compare_op1;
1147 ;; Actual branches. We must allow for the (label_ref) and the (pc) to be
1148 ;; swapped. If they are swapped, it reverses the sense of the branch.
1150 ;; This pattern matches the (branch-if-true) branches generated above.
1151 ;; It generates two different instruction sequences depending upon how
1152 ;; far away the destination is.
1154 ;; The calculation for the instruction length is derived as follows:
1155 ;; The branch instruction has a 9 bit signed displacement so we have
1156 ;; this inequality for the displacement:
1160 ;; -256 + 256 <= pc + 256 < 256 + 256
1162 ;; 0 <= pc + 256 < 512
1164 ;; if we consider the displacement as an unsigned value, then negative
1165 ;; displacements become very large positive displacements, and the
1166 ;; inequality becomes:
1170 ;; In order to allow for the fact that the real branch instruction works
1171 ;; from pc + 2, we increase the offset to 258.
1173 ;; Note - we do not have to worry about whether the branch is delayed or
1174 ;; not, as branch shortening happens after delay slot reorganisation.
1176 (define_insn "*branch_true"
1178 (if_then_else (match_operator:CC 0 "comparison_operator"
1181 (label_ref (match_operand 1 "" ""))
1186 if (get_attr_length (insn) == 2)
1187 return \"b%b0%#\\t%l1\";
1190 static char buffer [100];
1191 const char * tmp_reg;
1194 tmp_reg = reg_names [COMPILER_SCRATCH_REGISTER];
1196 ldi_insn = TARGET_SMALL_MODEL ? \"ldi:20\" : \"ldi:32\";
1198 /* The code produced here is, for say the EQ case:
1206 \"b%%B0\\t1f\\t;\\n\\t%s\\t%%l1, %s\\t;\\n\\tjmp%%#\\t@%s\\t;\\n1:\",
1207 ldi_insn, tmp_reg, tmp_reg);
1212 [(set (attr "length") (if_then_else
1221 (if_then_else (eq_attr "size" "small")
1224 (set_attr "delay_type" "delayed")]
1228 ;; This pattern is a duplicate of the previous one, except that the
1229 ;; branch occurs if the test is false, so the %B operator is used.
1230 (define_insn "*branch_false"
1232 (if_then_else (match_operator:CC 0 "comparison_operator"
1236 (label_ref (match_operand 1 "" ""))))]
1240 if (get_attr_length (insn) == 2)
1241 return \"b%B0%#\\t%l1 \";
1244 static char buffer [100];
1245 const char * tmp_reg;
1248 tmp_reg = reg_names [COMPILER_SCRATCH_REGISTER];
1250 ldi_insn = TARGET_SMALL_MODEL ? \"ldi:20\" : \"ldi:32\";
1253 \"b%%b0\\t1f\\t;\\n\\t%s\\t%%l1, %s\\t;\\n\\tjmp%%#\\t@%s\\t;\\n1:\",
1254 ldi_insn, tmp_reg, tmp_reg);
1259 [(set (attr "length") (if_then_else (ltu (plus (minus (match_dup 1) (pc))
1263 (if_then_else (eq_attr "size" "small")
1266 (set_attr "delay_type" "delayed")]
1272 ;; Subroutine call instruction returning no value. Operand 0 is the function
1273 ;; to call; operand 1 is the number of bytes of arguments pushed (in mode
1274 ;; `SImode', except it is normally a `const_int'); operand 2 is the number of
1275 ;; registers used as operands.
1278 [(call (match_operand 0 "call_operand" "Qm")
1279 (match_operand 1 "" "g"))
1280 (clobber (reg:SI 17))]
1283 [(set_attr "delay_type" "delayed")]
1286 ;; Subroutine call instruction returning a value. Operand 0 is the hard
1287 ;; register in which the value is returned. There are three more operands, the
1288 ;; same as the three operands of the `call' instruction (but with numbers
1289 ;; increased by one).
1291 ;; Subroutines that return `BLKmode' objects use the `call' insn.
1293 (define_insn "call_value"
1294 [(set (match_operand 0 "register_operand" "=r")
1295 (call (match_operand 1 "call_operand" "Qm")
1296 (match_operand 2 "" "g")))
1297 (clobber (reg:SI 17))]
1300 [(set_attr "delay_type" "delayed")]
1303 ;; Normal unconditional jump.
1304 ;; For a description of the computation of the length
1305 ;; attribute see the branch patterns above.
1307 [(set (pc) (label_ref (match_operand 0 "" "")))
1308 (clobber (reg:SI 0))]
1312 if (get_attr_length (insn) == 2)
1313 return \"bra%#\\t%0\";
1316 static char buffer [100];
1317 const char * tmp_reg;
1320 tmp_reg = reg_names [COMPILER_SCRATCH_REGISTER];
1322 ldi_insn = TARGET_SMALL_MODEL ? \"ldi:20\" : \"ldi:32\";
1324 sprintf (buffer, \"%s\\t%%0, %s\\t;\\n\\tjmp%%#\\t@%s\\t;\",
1325 ldi_insn, tmp_reg, tmp_reg);
1330 [(set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1334 (if_then_else (eq_attr "size" "small")
1337 (set_attr "delay_type" "delayed")]
1340 ;; Indirect jump through a register
1341 (define_insn "indirect_jump"
1342 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "r"))]
1343 "GET_CODE (operands[0]) != MEM || GET_CODE (XEXP (operands[0], 0)) != PLUS"
1345 [(set_attr "delay_type" "delayed")]
1348 (define_insn "tablejump"
1349 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1350 (use (label_ref (match_operand 1 "" "")))]
1353 [(set_attr "delay_type" "delayed")]
1357 ;;{{{ Function Prologues and Epilogues
1359 ;; Called after register allocation to add any instructions needed for the
1360 ;; prologue. Using a prologue insn is favored compared to putting all of the
1361 ;; instructions in output_function_prologue(), since it allows the scheduler
1362 ;; to intermix instructions with the saves of the caller saved registers. In
1363 ;; some cases, it might be necessary to emit a barrier instruction as the last
1364 ;; insn to prevent such scheduling.
1365 (define_expand "prologue"
1366 [(clobber (const_int 0))]
1369 fr30_expand_prologue ();
1374 ;; Called after register allocation to add any instructions needed for the
1375 ;; epilogue. Using a epilogue insn is favored compared to putting all of the
1376 ;; instructions in output_function_epilogue(), since it allows the scheduler
1377 ;; to intermix instructions with the restores of the caller saved registers.
1378 ;; In some cases, it might be necessary to emit a barrier instruction as the
1379 ;; first insn to prevent such scheduling.
1380 (define_expand "epilogue"
1384 fr30_expand_epilogue ();
1389 (define_insn "return_from_func"
1394 [(set_attr "delay_type" "delayed")]
1397 (define_insn "leave_func"
1398 [(set (reg:SI 15) (reg:SI 14))
1399 (set (reg:SI 14) (mem:SI (post_inc:SI (reg:SI 15))))]
1404 (define_insn "enter_func"
1405 [(set:SI (mem:SI (minus:SI (reg:SI 15)
1409 (minus:SI (reg:SI 15)
1412 (minus:SI (reg:SI 15)
1413 (match_operand 0 "immediate_operand" "i")))]
1416 [(set_attr "delay_type" "other")]
1422 ;; No operation, needed in case the user uses -g but not -O.
1429 ;; Pseudo instruction that prevents the scheduler from moving code above this
1431 (define_insn "blockage"
1432 [(unspec_volatile [(const_int 0)] 0)]
1435 [(set_attr "length" "0")]