| blob | a62f679ad2e02ea791e5d326d800046eba0d8f0b |
1 ;; -*- Mode: Scheme -*-
2 ;; Machine description for GNU compiler,
3 ;; for ATMEL AVR micro controllers.
4 ;; Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
5 ;; Contributed by Denis Chertykov (denisc@overta.ru)
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; any later version.
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
24 ;; Special characters after '%':
25 ;; A No effect (add 0).
26 ;; B Add 1 to REG number, MEM address or CONST_INT.
27 ;; C Add 2.
28 ;; D Add 3.
29 ;; j Branch condition.
30 ;; k Reverse branch condition.
31 ;; o Displacement for (mem (plus (reg) (const_int))) operands.
32 ;; ~ Output 'r' if not AVR_MEGA.
34 ;; UNSPEC usage:
35 ;; 0 Length of a string, see "strlenhi".
36 ;; 1 Read from a word address in program memory, see "casesi".
38 ;; Condition code settings.
39 (define_attr "cc" "none,set_czn,set_zn,set_n,compare,clobber"
40 (const_string "none"))
42 (define_attr "type" "branch,branch1,arith"
43 (const_string "arith"))
45 (define_attr "mcu_enhanced" "yes,no"
46 (const (if_then_else (symbol_ref "AVR_ENHANCED")
47 (const_string "yes")
48 (const_string "no"))))
50 (define_attr "mcu_mega" "yes,no"
51 (const (if_then_else (symbol_ref "AVR_MEGA")
52 (const_string "yes")
53 (const_string "no"))))
56 ;; The size of instructions in bytes.
57 ;; XXX may depend from "cc"
59 (define_attr "length" ""
60 (cond [(eq_attr "type" "branch")
61 (if_then_else (and (ge (minus (pc) (match_dup 0))
62 (const_int -63))
63 (le (minus (pc) (match_dup 0))
64 (const_int 62)))
65 (const_int 1)
66 (if_then_else (and (ge (minus (pc) (match_dup 0))
67 (const_int -2045))
68 (le (minus (pc) (match_dup 0))
69 (const_int 2045)))
70 (const_int 2)
71 (const_int 2)))
72 (eq_attr "type" "branch1")
73 (if_then_else (and (ge (minus (pc) (match_dup 0))
74 (const_int -62))
75 (le (minus (pc) (match_dup 0))
76 (const_int 61)))
77 (const_int 2)
78 (if_then_else (and (ge (minus (pc) (match_dup 0))
79 (const_int -2044))
80 (le (minus (pc) (match_dup 0))
81 (const_int 2043)))
82 (const_int 3)
83 (const_int 3)))]
84 (const_int 2)))
86 (define_insn "*pop1"
87 [(set (reg:HI 32) (plus:HI (reg:HI 32) (const_int 1)))]
88 ""
89 "pop __tmp_reg__"
90 [(set_attr "length" "1")])
92 (define_insn "*pop2"
93 [(set (reg:HI 32) (plus:HI (reg:HI 32) (const_int 2)))]
94 ""
95 "pop __tmp_reg__
96 pop __tmp_reg__"
97 [(set_attr "length" "2")])
99 (define_insn "*pop3"
100 [(set (reg:HI 32) (plus:HI (reg:HI 32) (const_int 3)))]
101 ""
102 "pop __tmp_reg__
103 pop __tmp_reg__
104 pop __tmp_reg__"
105 [(set_attr "length" "3")])
107 (define_insn "*pop4"
108 [(set (reg:HI 32) (plus:HI (reg:HI 32) (const_int 4)))]
109 ""
110 "pop __tmp_reg__
111 pop __tmp_reg__
112 pop __tmp_reg__
113 pop __tmp_reg__"
114 [(set_attr "length" "4")])
116 (define_insn "*pop5"
117 [(set (reg:HI 32) (plus:HI (reg:HI 32) (const_int 5)))]
118 ""
119 "pop __tmp_reg__
120 pop __tmp_reg__
121 pop __tmp_reg__
122 pop __tmp_reg__
123 pop __tmp_reg__"
124 [(set_attr "length" "5")])
126 (define_insn "*pushqi"
127 [(set (mem:QI (post_dec (reg:HI 32)))
128 (match_operand:QI 0 "nonmemory_operand" "r,L"))]
129 "(operands[0] == const0_rtx || register_operand (operands[0], QImode))"
130 "@
131 push %0
132 push __zero_reg__"
133 [(set_attr "length" "1,1")])
136 (define_insn "*pushhi"
137 [(set (mem:HI (post_dec (reg:HI 32)))
138 (match_operand:HI 0 "nonmemory_operand" "r,L"))]
139 "(operands[0] == const0_rtx || register_operand (operands[0], HImode))"
140 "@
141 push %B0\;push %A0
142 push __zero_reg__\;push __zero_reg__"
143 [(set_attr "length" "2,2")])
145 (define_insn "*pushsi"
146 [(set (mem:SI (post_dec (reg:HI 32)))
147 (match_operand:SI 0 "nonmemory_operand" "r,L"))]
148 "(operands[0] == const0_rtx || register_operand (operands[0], SImode))"
149 "@
150 push %D0\;push %C0\;push %B0\;push %A0
151 push __zero_reg__\;push __zero_reg__\;push __zero_reg__\;push __zero_reg__"
152 [(set_attr "length" "4,4")])
154 (define_insn "*pushsf"
155 [(set (mem:SF (post_dec (reg:HI 32)))
156 (match_operand:SF 0 "register_operand" "r"))]
157 ""
158 "push %D0
159 push %C0
160 push %B0
161 push %A0"
162 [(set_attr "length" "4")])
164 ;;========================================================================
165 ;; move byte
166 ;; The last alternative (any immediate constant to any register) is
167 ;; very expensive. It should be optimized by peephole2 if a scratch
168 ;; register is available, but then that register could just as well be
169 ;; allocated for the variable we are loading. But, most of NO_LD_REGS
170 ;; are call-saved registers, and most of LD_REGS are call-used registers,
171 ;; so this may still be a win for registers live across function calls.
173 (define_expand "movqi"
174 [(set (match_operand:QI 0 "nonimmediate_operand" "")
175 (match_operand:QI 1 "general_operand" ""))]
176 ""
177 "/* One of the ops has to be in a register */
178 if (!register_operand(operand0, QImode)
179 && ! (register_operand(operand1, QImode) || const0_rtx == operand1))
180 operands[1] = copy_to_mode_reg(QImode, operand1);
181 ")
183 (define_insn "*movqi"
184 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,d,Qm,r,q,r,*r")
185 (match_operand:QI 1 "general_operand" "r,i,rL,Qm,r,q,i"))]
186 "(register_operand (operands[0],QImode)
187 || register_operand (operands[1], QImode) || const0_rtx == operands[1])"
188 "* return output_movqi (insn, operands, NULL);"
189 [(set_attr "length" "1,1,5,5,1,1,4")
190 (set_attr "cc" "none,none,clobber,clobber,none,none,clobber")])
192 ;; This is used in peephole2 to optimize loading immediate constants
193 ;; if a scratch register from LD_REGS happens to be available.
195 (define_insn "*reload_inqi"
196 [(set (match_operand:QI 0 "register_operand" "=l")
197 (match_operand:QI 1 "immediate_operand" "i"))
198 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
199 "reload_completed"
200 "ldi %2,lo8(%1)
201 mov %0,%2"
202 [(set_attr "length" "2")
203 (set_attr "cc" "none")])
205 (define_peephole2
206 [(match_scratch:QI 2 "d")
207 (set (match_operand:QI 0 "register_operand" "")
208 (match_operand:QI 1 "immediate_operand" ""))]
209 "(operands[1] != const0_rtx
210 && test_hard_reg_class (NO_LD_REGS, operands[0]))"
211 [(parallel [(set (match_dup 0) (match_dup 1))
212 (clobber (match_dup 2))])]
213 "if (!avr_peep2_scratch_safe (operands[2]))
214 FAIL;")
216 ;;============================================================================
217 ;; move word (16 bit)
219 (define_expand "movhi"
220 [(set (match_operand:HI 0 "nonimmediate_operand" "")
221 (match_operand:HI 1 "general_operand" ""))]
222 ""
223 "
224 {
225 /* One of the ops has to be in a register */
226 if (!register_operand(operand0, HImode)
227 && !(register_operand(operand1, HImode) || const0_rtx == operands[1]))
228 {
229 operands[1] = copy_to_mode_reg(HImode, operand1);
230 }
231 }")
234 (define_peephole2
235 [(match_scratch:QI 2 "d")
236 (set (match_operand:HI 0 "register_operand" "")
237 (match_operand:HI 1 "immediate_operand" ""))]
238 "(operands[1] != const0_rtx
239 && test_hard_reg_class (NO_LD_REGS, operands[0]))"
240 [(parallel [(set (match_dup 0) (match_dup 1))
241 (clobber (match_dup 2))])]
242 "if (!avr_peep2_scratch_safe (operands[2]))
243 FAIL;")
245 ;; '*' because it is not used in rtl generation, only in above peephole
246 (define_insn "*reload_inhi"
247 [(set (match_operand:HI 0 "register_operand" "=r")
248 (match_operand:HI 1 "immediate_operand" "i"))
249 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
250 "reload_completed"
251 "* return output_reload_inhi (insn, operands, NULL);"
252 [(set_attr "length" "4")
253 (set_attr "cc" "none")])
255 (define_insn "*movhi"
256 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,d,*r,q,r")
257 (match_operand:HI 1 "general_operand" "r,m,rL,i,i,r,q"))]
258 "(register_operand (operands[0],HImode)
259 || register_operand (operands[1],HImode) || const0_rtx == operands[1])"
260 "* return output_movhi (insn, operands, NULL);"
261 [(set_attr "length" "2,6,7,2,6,5,2")
262 (set_attr "cc" "none,clobber,clobber,none,clobber,none,none")])
264 ;;==========================================================================
265 ;; move double word (32 bit)
267 (define_expand "movsi"
268 [(set (match_operand:SI 0 "nonimmediate_operand" "")
269 (match_operand:SI 1 "general_operand" ""))]
270 ""
271 "
272 {
273 /* One of the ops has to be in a register. */
274 if (!register_operand (operand0, SImode)
275 && !(register_operand (operand1, SImode) || const0_rtx == operand1))
276 {
277 operands[1] = copy_to_mode_reg (SImode, operand1);
278 }
279 }")
283 (define_peephole2
284 [(match_scratch:QI 2 "d")
285 (set (match_operand:SI 0 "register_operand" "")
286 (match_operand:SI 1 "immediate_operand" ""))]
287 "(operands[1] != const0_rtx
288 && test_hard_reg_class (NO_LD_REGS, operands[0]))"
289 [(parallel [(set (match_dup 0) (match_dup 1))
290 (clobber (match_dup 2))])]
291 "if (!avr_peep2_scratch_safe (operands[2]))
292 FAIL;")
294 ;; '*' because it is not used in rtl generation.
295 (define_insn "*reload_insi"
296 [(set (match_operand:SI 0 "register_operand" "=r")
297 (match_operand:SI 1 "immediate_operand" "i"))
298 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
299 "reload_completed"
300 "* return output_reload_insisf (insn, operands, NULL);"
301 [(set_attr "length" "8")
302 (set_attr "cc" "none")])
305 (define_insn "*movsi"
306 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,Qm,!d,r")
307 (match_operand:SI 1 "general_operand" "r,L,Qm,rL,i,i"))]
308 "(register_operand (operands[0],SImode)
309 || register_operand (operands[1],SImode) || const0_rtx == operands[1])"
310 "* return output_movsisf (insn, operands, NULL);"
311 [(set_attr "length" "4,4,8,9,4,10")
312 (set_attr "cc" "none,set_zn,clobber,clobber,none,clobber")])
314 ;; fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
315 ;; move floating point numbers (32 bit)
317 (define_expand "movsf"
318 [(set (match_operand:SF 0 "nonimmediate_operand" "")
319 (match_operand:SF 1 "general_operand" ""))]
320 ""
321 "
322 {
323 /* One of the ops has to be in a register. */
324 if (!register_operand (operand1, SFmode)
325 && !register_operand (operand0, SFmode))
326 {
327 operands[1] = copy_to_mode_reg (SFmode, operand1);
328 }
329 }")
331 (define_insn "*movsf"
332 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,Qm,!d,r")
333 (match_operand:SF 1 "general_operand" "r,G,Qm,r,F,F"))]
334 "register_operand (operands[0], SFmode)
335 || register_operand (operands[1], SFmode)"
336 "* return output_movsisf (insn, operands, NULL);"
337 [(set_attr "length" "4,4,8,9,4,10")
338 (set_attr "cc" "none,set_zn,clobber,clobber,none,clobber")])
340 ;;=========================================================================
341 ;; move string (like memcpy)
343 (define_expand "movstrhi"
344 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
345 (match_operand:BLK 1 "memory_operand" ""))
346 (use (match_operand:HI 2 "const_int_operand" ""))
347 (use (match_operand:HI 3 "const_int_operand" ""))
348 (clobber (match_dup 4))
349 (clobber (match_dup 5))
350 (clobber (match_dup 6))])]
351 ""
352 "{
353 rtx addr0, addr1;
354 int cnt8;
356 if (GET_CODE (operands[2]) != CONST_INT)
357 FAIL;
358 cnt8 = byte_immediate_operand (operands[2], GET_MODE (operands[2]));
359 operands[2] = copy_to_mode_reg (cnt8 ? QImode : HImode, operands[2]);
360 operands[4] = operands[2];
362 addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
363 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
365 operands[5] = addr0;
366 operands[6] = addr1;
368 operands[0] = gen_rtx (MEM, BLKmode, addr0);
369 operands[1] = gen_rtx (MEM, BLKmode, addr1);
370 }")
372 (define_insn "*movstrqi_insn"
373 [(set (mem:BLK (match_operand:HI 0 "register_operand" "e"))
374 (mem:BLK (match_operand:HI 1 "register_operand" "e")))
375 (use (match_operand:QI 2 "register_operand" "r"))
376 (use (match_operand:QI 3 "const_int_operand" "i"))
377 (clobber (match_dup 2))
378 (clobber (match_dup 0))
379 (clobber (match_dup 1))]
380 ""
381 "ld __tmp_reg__,%a1+
382 st %a0+,__tmp_reg__
383 dec %2
384 brne _PC_-8"
385 [(set_attr "length" "4")
386 (set_attr "cc" "clobber")])
388 (define_insn "*movstrhi"
389 [(set (mem:BLK (match_operand:HI 0 "register_operand" "e,e"))
390 (mem:BLK (match_operand:HI 1 "register_operand" "e,e")))
391 (use (match_operand:HI 2 "register_operand" "!w,d"))
392 (use (match_operand:HI 3 "const_int_operand" ""))
393 (clobber (match_dup 2))
394 (clobber (match_dup 0))
395 (clobber (match_dup 1))]
396 ""
397 "*{
398 if (which_alternative==0)
399 return (AS2 (ld,__tmp_reg__,%a1+) CR_TAB
400 AS2 (st,%a0+,__tmp_reg__) CR_TAB
401 AS2 (sbiw,%A2,1) CR_TAB
402 AS1 (brne,_PC_-8));
403 else
404 return (AS2 (ld,__tmp_reg__,%a1+) CR_TAB
405 AS2 (st,%a0+,__tmp_reg__) CR_TAB
406 AS2 (subi,%A2,1) CR_TAB
407 AS2 (sbci,%B2,0) CR_TAB
408 AS1 (brne,_PC_-10));
409 }"
410 [(set_attr "length" "4,5")
411 (set_attr "cc" "clobber,clobber")])
413 ;; =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0
414 ;; memset (%0, 0, %1)
416 (define_expand "clrstrhi"
417 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
418 (const_int 0))
419 (use (match_operand:HI 1 "const_int_operand" ""))
420 (use (match_operand:HI 2 "const_int_operand" "n"))
421 (clobber (match_dup 3))
422 (clobber (match_dup 4))])]
423 ""
424 "{
425 rtx addr0;
426 int cnt8;
428 if (GET_CODE (operands[1]) != CONST_INT)
429 FAIL;
431 cnt8 = byte_immediate_operand (operands[1], GET_MODE (operands[1]));
432 operands[1] = copy_to_mode_reg (cnt8 ? QImode : HImode, operands[1]);
433 operands[3] = operands[1];
435 addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
436 operands[4] = addr0;
438 operands[0] = gen_rtx (MEM, BLKmode, addr0);
439 }")
441 (define_insn "*clrstrqi"
442 [(set (mem:BLK (match_operand:HI 0 "register_operand" "e"))
443 (const_int 0))
444 (use (match_operand:QI 1 "register_operand" "r"))
445 (use (match_operand:QI 2 "const_int_operand" "n"))
446 (clobber (match_dup 1))
447 (clobber (match_dup 0))]
448 ""
449 "st %a0+,__zero_reg__
450 dec %1
451 brne _PC_-6"
452 [(set_attr "length" "3")
453 (set_attr "cc" "clobber")])
455 (define_insn "*clrstrhi"
456 [(set (mem:BLK (match_operand:HI 0 "register_operand" "e,e"))
457 (const_int 0))
458 (use (match_operand:HI 1 "register_operand" "!w,d"))
459 (use (match_operand:HI 2 "const_int_operand" "n,n"))
460 (clobber (match_dup 1))
461 (clobber (match_dup 0))]
462 ""
463 "*{
464 if (which_alternative==0)
465 return (AS2 (st,%a0+,__zero_reg__) CR_TAB
466 AS2 (sbiw,%A1,1) CR_TAB
467 AS1 (brne,_PC_-6));
468 else
469 return (AS2 (st,%a0+,__zero_reg__) CR_TAB
470 AS2 (subi,%A1,1) CR_TAB
471 AS2 (sbci,%B1,0) CR_TAB
472 AS1 (brne,_PC_-8));
473 }"
474 [(set_attr "length" "3,4")
475 (set_attr "cc" "clobber,clobber")])
477 (define_expand "strlenhi"
478 [(set (match_dup 4)
479 (unspec:HI [(match_operand:BLK 1 "memory_operand" "")
480 (match_operand:QI 2 "const_int_operand" "")
481 (match_operand:HI 3 "immediate_operand" "")] 0))
482 (set (match_dup 4) (plus:HI (match_dup 4)
483 (const_int -1)))
484 (set (match_operand:HI 0 "register_operand" "")
485 (minus:HI (match_dup 4)
486 (match_dup 5)))]
487 ""
488 "{
489 rtx addr;
490 if (! (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0))
491 FAIL;
492 addr = copy_to_mode_reg (Pmode, XEXP (operands[1],0));
493 operands[1] = gen_rtx (MEM, BLKmode, addr);
494 operands[5] = addr;
495 operands[4] = gen_reg_rtx (HImode);
496 }")
498 (define_insn "*strlenhi"
499 [(set (match_operand:HI 0 "register_operand" "=e")
500 (unspec:HI [(mem:BLK (match_operand:HI 1 "register_operand" "%0"))
501 (const_int 0)
502 (match_operand:HI 2 "immediate_operand" "i")] 0))]
503 ""
504 "ld __tmp_reg__,%a0+
505 tst __tmp_reg__
506 brne _PC_-6"
507 [(set_attr "length" "3")
508 (set_attr "cc" "clobber")])
510 ;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
511 ; add bytes
513 (define_insn "addqi3"
514 [(set (match_operand:QI 0 "register_operand" "=r,d,r,r")
515 (plus:QI (match_operand:QI 1 "register_operand" "%0,0,0,0")
516 (match_operand:QI 2 "nonmemory_operand" "r,i,P,N")))]
517 ""
518 "@
519 add %0,%2
520 subi %0,lo8(-(%2))
521 inc %0
522 dec %0"
523 [(set_attr "length" "1,1,1,1")
524 (set_attr "cc" "set_czn,set_czn,set_zn,set_zn")])
527 (define_expand "addhi3"
528 [(set (match_operand:HI 0 "register_operand" "")
529 (plus:HI (match_operand:HI 1 "register_operand" "")
530 (match_operand:HI 2 "nonmemory_operand" "")))]
531 ""
532 "
533 {
534 if (GET_CODE (operands[2]) == CONST_INT)
535 {
536 short tmp = INTVAL (operands[2]);
537 operands[2] = GEN_INT(tmp);
538 }
539 }")
542 (define_insn "*addhi3_zero_extend"
543 [(set (match_operand:HI 0 "register_operand" "=r")
544 (plus:HI (zero_extend:HI
545 (match_operand:QI 1 "register_operand" "r"))
546 (match_operand:HI 2 "register_operand" "0")))]
547 ""
548 "add %A0,%1
549 adc %B0,__zero_reg__"
550 [(set_attr "length" "2")
551 (set_attr "cc" "set_n")])
553 (define_insn "*addhi3_zero_extend1"
554 [(set (match_operand:HI 0 "register_operand" "=r")
555 (plus:HI (match_operand:HI 1 "register_operand" "%0")
556 (zero_extend:HI
557 (match_operand:QI 2 "register_operand" "r"))))]
558 ""
559 "add %A0,%2
560 adc %B0,__zero_reg__"
561 [(set_attr "length" "2")
562 (set_attr "cc" "set_n")])
564 (define_insn "*addhi3_zero_extend2"
565 [(set (match_operand:HI 0 "register_operand" "=r")
566 (plus:HI
567 (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
568 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
569 ""
570 "add %0,%2
571 mov %B0,__zero_reg__
572 adc %B0,__zero_reg__"
573 [(set_attr "length" "3")
574 (set_attr "cc" "set_n")])
576 (define_insn "*addhi3"
577 [(set (match_operand:HI 0 "register_operand" "=r,!w,!w,d,r,r")
578 (plus:HI
579 (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0")
580 (match_operand:HI 2 "nonmemory_operand" "r,I,J,i,P,N")))]
581 ""
582 "@
583 add %A0,%A2\;adc %B0,%B2
584 adiw %A0,%2
585 sbiw %A0,%n2
586 subi %A0,lo8(-(%2))\;sbci %B0,hi8(-(%2))
587 sec\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__
588 sec\;sbc %A0,__zero_reg__\;sbc %B0,__zero_reg__"
589 [(set_attr "length" "2,1,1,2,3,3")
590 (set_attr "cc" "set_n,set_czn,set_czn,set_czn,set_n,set_n")])
592 (define_insn "addsi3"
593 [(set (match_operand:SI 0 "register_operand" "=r,!w,!w,d,r,r")
594 (plus:SI
595 (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
596 (match_operand:SI 2 "nonmemory_operand" "r,I,J,i,P,N")))]
597 ""
598 "@
599 add %A0,%A2\;adc %B0,%B2\;adc %C0,%C2\;adc %D0,%D2
600 adiw %0,%2\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
601 sbiw %0,%n2\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__
602 subi %0,lo8(-(%2))\;sbci %B0,hi8(-(%2))\;sbci %C0,hlo8(-(%2))\;sbci %D0,hhi8(-(%2))
603 sec\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
604 sec\;sbc %A0,__zero_reg__\;sbc %B0,__zero_reg__\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__"
605 [(set_attr "length" "4,3,3,4,5,5")
606 (set_attr "cc" "set_n,set_n,set_czn,set_czn,set_n,set_n")])
608 ;-----------------------------------------------------------------------------
609 ; sub bytes
610 (define_insn "subqi3"
611 [(set (match_operand:QI 0 "register_operand" "=r,d")
612 (minus:QI (match_operand:QI 1 "register_operand" "0,0")
613 (match_operand:QI 2 "nonmemory_operand" "r,i")))]
614 ""
615 "@
616 sub %0,%2
617 subi %0,lo8(%2)"
618 [(set_attr "length" "1,1")
619 (set_attr "cc" "set_czn,set_czn")])
621 (define_insn "subhi3"
622 [(set (match_operand:HI 0 "register_operand" "=r,d")
623 (minus:HI (match_operand:HI 1 "register_operand" "0,0")
624 (match_operand:HI 2 "nonmemory_operand" "r,i")))]
625 ""
626 "@
627 sub %A0,%A2\;sbc %B0,%B2
628 subi %A0,lo8(%2)\;sbci %B0,hi8(%2)"
629 [(set_attr "length" "2,2")
630 (set_attr "cc" "set_czn,set_czn")])
632 (define_insn "subsi3"
633 [(set (match_operand:SI 0 "register_operand" "=r,d")
634 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
635 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
636 ""
637 "@
638 sub %0,%2\;sbc %B0,%B2\;sbc %C0,%C2\;sbc %D0,%D2
639 subi %A0,lo8(%2)\;sbci %B0,hi8(%2)\;sbci %C0,hlo8(%2)\;sbci %D0,hhi8(%2)"
640 [(set_attr "length" "4,4")
641 (set_attr "cc" "set_czn,set_czn")])
643 ;******************************************************************************
644 ; mul
646 (define_expand "mulqi3"
647 [(set (match_operand:QI 0 "register_operand" "")
648 (mult:QI (match_operand:QI 1 "register_operand" "")
649 (match_operand:QI 2 "register_operand" "")))]
650 ""
651 "{
652 if (!AVR_ENHANCED)
653 {
654 emit_insn (gen_mulqi3_call (operands[0], operands[1], operands[2]));
655 DONE;
656 }
657 }")
659 (define_insn "*mulqi3_enh"
660 [(set (match_operand:QI 0 "register_operand" "=r")
661 (mult:QI (match_operand:QI 1 "register_operand" "r")
662 (match_operand:QI 2 "register_operand" "r")))]
663 "AVR_ENHANCED"
664 "mul %1,%2
665 mov %0,r0
666 clr r1"
667 [(set_attr "length" "3")
668 (set_attr "cc" "clobber")])
670 (define_expand "mulqi3_call"
671 [(set (reg:QI 24) (match_operand:QI 1 "register_operand" ""))
672 (set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
673 (parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
674 (clobber (reg:QI 22))])
675 (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))]
676 ""
677 "")
679 (define_insn "*mulqi3_call"
680 [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
681 (clobber (reg:QI 22))]
682 "!AVR_ENHANCED"
683 "%~call __mulqi3"
684 [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
685 (const_int 1)
686 (const_int 2)))
687 (set_attr "cc" "clobber")])
689 (define_insn "mulqihi3"
690 [(set (match_operand:HI 0 "register_operand" "=r")
691 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "d"))
692 (sign_extend:HI (match_operand:QI 2 "register_operand" "d"))))]
693 "AVR_ENHANCED"
694 "muls %1,%2
695 movw %0,r0
696 clr r1"
697 [(set_attr "length" "3")
698 (set_attr "cc" "clobber")])
700 (define_insn "umulqihi3"
701 [(set (match_operand:HI 0 "register_operand" "=r")
702 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
703 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
704 "AVR_ENHANCED"
705 "mul %1,%2
706 movw %0,r0
707 clr r1"
708 [(set_attr "length" "3")
709 (set_attr "cc" "clobber")])
711 (define_expand "mulhi3"
712 [(set (match_operand:HI 0 "register_operand" "")
713 (mult:HI (match_operand:HI 1 "register_operand" "")
714 (match_operand:HI 2 "register_operand" "")))]
715 ""
716 "
717 {
718 if (!AVR_ENHANCED)
719 {
720 emit_insn (gen_mulhi3_call (operands[0], operands[1], operands[2]));
721 DONE;
722 }
723 }")
725 (define_insn "*mulhi3_enh"
726 [(set (match_operand:HI 0 "register_operand" "=&r")
727 (mult:HI (match_operand:HI 1 "register_operand" "r")
728 (match_operand:HI 2 "register_operand" "r")))]
729 "AVR_ENHANCED"
730 "mul %A1,%A2
731 movw %0,r0
732 mul %A1,%B2
733 add %B0,r0
734 mul %B1,%A2
735 add %B0,r0
736 clr r1"
737 [(set_attr "length" "7")
738 (set_attr "cc" "clobber")])
740 (define_expand "mulhi3_call"
741 [(set (reg:HI 24) (match_operand:HI 1 "register_operand" ""))
742 (set (reg:HI 22) (match_operand:HI 2 "register_operand" ""))
743 (parallel [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
744 (clobber (reg:HI 22))
745 (clobber (reg:QI 21))])
746 (set (match_operand:HI 0 "register_operand" "") (reg:HI 24))]
747 ""
748 "")
750 (define_insn "*mulhi3_call"
751 [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
752 (clobber (reg:HI 22))
753 (clobber (reg:QI 21))]
754 "!AVR_ENHANCED"
755 "%~call __mulhi3"
756 [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
757 (const_int 1)
758 (const_int 2)))
759 (set_attr "cc" "clobber")])
761 ;; Operand 2 (reg:SI 18) not clobbered on the enhanced core.
762 ;; All call-used registers clobbered otherwise - normal library call.
763 (define_expand "mulsi3"
764 [(set (reg:SI 22) (match_operand:SI 1 "register_operand" ""))
765 (set (reg:SI 18) (match_operand:SI 2 "register_operand" ""))
766 (parallel [(set (reg:SI 22) (mult:SI (reg:SI 22) (reg:SI 18)))
767 (clobber (reg:HI 26))
768 (clobber (reg:HI 30))])
769 (set (match_operand:SI 0 "register_operand" "") (reg:SI 22))]
770 "AVR_ENHANCED"
771 "")
773 (define_insn "*mulsi3_call"
774 [(set (reg:SI 22) (mult:SI (reg:SI 22) (reg:SI 18)))
775 (clobber (reg:HI 26))
776 (clobber (reg:HI 30))]
777 "AVR_ENHANCED"
778 "%~call __mulsi3"
779 [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
780 (const_int 1)
781 (const_int 2)))
782 (set_attr "cc" "clobber")])
784 ; / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / %
785 ; divmod
787 ;; Generate libgcc.S calls ourselves, because:
788 ;; - we know exactly which registers are clobbered (for QI and HI
789 ;; modes, some of the call-used registers are preserved)
790 ;; - we get both the quotient and the remainder at no extra cost
792 (define_expand "divmodqi4"
793 [(set (reg:QI 24) (match_operand:QI 1 "register_operand" ""))
794 (set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
795 (parallel [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
796 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
797 (clobber (reg:QI 22))
798 (clobber (reg:QI 23))])
799 (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))
800 (set (match_operand:QI 3 "register_operand" "") (reg:QI 25))]
801 ""
802 "")
804 (define_insn "*divmodqi4_call"
805 [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
806 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
807 (clobber (reg:QI 22))
808 (clobber (reg:QI 23))]
809 ""
810 "%~call __divmodqi4"
811 [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
812 (const_int 1)
813 (const_int 2)))
814 (set_attr "cc" "clobber")])
816 (define_expand "udivmodqi4"
817 [(set (reg:QI 24) (match_operand:QI 1 "register_operand" ""))
818 (set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
819 (parallel [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
820 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
821 (clobber (reg:QI 23))])
822 (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))
823 (set (match_operand:QI 3 "register_operand" "") (reg:QI 25))]
824 ""
825 "")
827 (define_insn "*udivmodqi4_call"
828 [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
829 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
830 (clobber (reg:QI 23))]
831 ""
832 "%~call __udivmodqi4"
833 [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
834 (const_int 1)
835 (const_int 2)))
836 (set_attr "cc" "clobber")])
838 (define_expand "divmodhi4"
839 [(set (reg:HI 24) (match_operand:HI 1 "register_operand" ""))
840 (set (reg:HI 22) (match_operand:HI 2 "register_operand" ""))
841 (parallel [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
842 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
843 (clobber (reg:HI 26))
844 (clobber (reg:QI 21))])
845 (set (match_operand:HI 0 "register_operand" "") (reg:HI 22))
846 (set (match_operand:HI 3 "register_operand" "") (reg:HI 24))]
847 ""
848 "")
850 (define_insn "*divmodhi4_call"
851 [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
852 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
853 (clobber (reg:HI 26))
854 (clobber (reg:QI 21))]
855 ""
856 "%~call __divmodhi4"
857 [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
858 (const_int 1)
859 (const_int 2)))
860 (set_attr "cc" "clobber")])
862 (define_expand "udivmodhi4"
863 [(set (reg:HI 24) (match_operand:HI 1 "register_operand" ""))
864 (set (reg:HI 22) (match_operand:HI 2 "register_operand" ""))
865 (parallel [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
866 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
867 (clobber (reg:HI 26))
868 (clobber (reg:QI 21))])
869 (set (match_operand:HI 0 "register_operand" "") (reg:HI 22))
870 (set (match_operand:HI 3 "register_operand" "") (reg:HI 24))]
871 ""
872 "")
874 (define_insn "*udivmodhi4_call"
875 [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
876 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
877 (clobber (reg:HI 26))
878 (clobber (reg:QI 21))]
879 ""
880 "%~call __udivmodhi4"
881 [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
882 (const_int 1)
883 (const_int 2)))
884 (set_attr "cc" "clobber")])
886 (define_expand "divmodsi4"
887 [(set (reg:SI 22) (match_operand:SI 1 "register_operand" ""))
888 (set (reg:SI 18) (match_operand:SI 2 "register_operand" ""))
889 (parallel [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
890 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
891 (clobber (reg:HI 26))
892 (clobber (reg:HI 30))])
893 (set (match_operand:SI 0 "register_operand" "") (reg:SI 18))
894 (set (match_operand:SI 3 "register_operand" "") (reg:SI 22))]
895 ""
896 "")
898 (define_insn "*divmodsi4_call"
899 [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
900 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
901 (clobber (reg:HI 26))
902 (clobber (reg:HI 30))]
903 ""
904 "%~call __divmodsi4"
905 [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
906 (const_int 1)
907 (const_int 2)))
908 (set_attr "cc" "clobber")])
910 (define_expand "udivmodsi4"
911 [(set (reg:SI 22) (match_operand:SI 1 "register_operand" ""))
912 (set (reg:SI 18) (match_operand:SI 2 "register_operand" ""))
913 (parallel [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
914 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
915 (clobber (reg:HI 26))
916 (clobber (reg:HI 30))])
917 (set (match_operand:SI 0 "register_operand" "") (reg:SI 18))
918 (set (match_operand:SI 3 "register_operand" "") (reg:SI 22))]
919 ""
920 "")
922 (define_insn "*udivmodsi4_call"
923 [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
924 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
925 (clobber (reg:HI 26))
926 (clobber (reg:HI 30))]
927 ""
928 "%~call __udivmodsi4"
929 [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
930 (const_int 1)
931 (const_int 2)))
932 (set_attr "cc" "clobber")])
934 ;&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
935 ; and
937 (define_insn "andqi3"
938 [(set (match_operand:QI 0 "register_operand" "=r,d")
939 (and:QI (match_operand:QI 1 "register_operand" "%0,0")
940 (match_operand:QI 2 "nonmemory_operand" "r,i")))]
941 ""
942 "@
943 and %0,%2
944 andi %0,lo8(%2)"
945 [(set_attr "length" "1,1")
946 (set_attr "cc" "set_zn,set_zn")])
948 (define_insn "andhi3"
949 [(set (match_operand:HI 0 "register_operand" "=r,d,r")
950 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0")
951 (match_operand:HI 2 "nonmemory_operand" "r,i,M")))
952 (clobber (match_scratch:QI 3 "=X,X,&d"))]
953 ""
954 "*{
955 if (which_alternative==0)
956 return (AS2 (and,%A0,%A2) CR_TAB
957 AS2 (and,%B0,%B2));
958 else if (which_alternative==1)
959 {
960 if (GET_CODE (operands[2]) == CONST_INT)
961 {
962 int mask = INTVAL (operands[2]);
963 if ((mask & 0xff) != 0xff)
964 output_asm_insn (AS2 (andi,%A0,lo8(%2)), operands);
965 if ((mask & 0xff00) != 0xff00)
966 output_asm_insn (AS2 (andi,%B0,hi8(%2)), operands);
967 return \"\";
968 }
969 return (AS2 (andi,%A0,lo8(%2)) CR_TAB
970 AS2 (andi,%B0,hi8(%2)));
971 }
972 return (AS2 (ldi,%3,lo8(%2)) CR_TAB
973 AS2 (and,%A0,%3) CR_TAB
974 AS1 (clr,%B0));
975 }"
976 [(set_attr "length" "2,2,3")
977 (set_attr "cc" "set_n,clobber,set_n")])
979 (define_insn "andsi3"
980 [(set (match_operand:SI 0 "register_operand" "=r,d")
981 (and:SI (match_operand:SI 1 "register_operand" "%0,0")
982 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
983 ""
984 "*{
985 if (which_alternative==0)
986 return (AS2 (and, %0,%2) CR_TAB
987 AS2 (and, %B0,%B2) CR_TAB
988 AS2 (and, %C0,%C2) CR_TAB
989 AS2 (and, %D0,%D2));
990 else if (which_alternative==1)
991 {
992 if (GET_CODE (operands[2]) == CONST_INT)
993 {
994 HOST_WIDE_INT mask = INTVAL (operands[2]);
995 if ((mask & 0xff) != 0xff)
996 output_asm_insn (AS2 (andi,%A0,lo8(%2)), operands);
997 if ((mask & 0xff00) != 0xff00)
998 output_asm_insn (AS2 (andi,%B0,hi8(%2)), operands);
999 if ((mask & 0xff0000UL) != 0xff0000UL)
1000 output_asm_insn (AS2 (andi,%C0,hlo8(%2)), operands);
1001 if ((mask & 0xff000000UL) != 0xff000000UL)
1002 output_asm_insn (AS2 (andi,%D0,hhi8(%2)), operands);
1003 return \"\";
1004 }
1005 return (AS2 (andi, %A0,lo8(%2)) CR_TAB
1006 AS2 (andi, %B0,hi8(%2)) CR_TAB
1007 AS2 (andi, %C0,hlo8(%2)) CR_TAB
1008 AS2 (andi, %D0,hhi8(%2)));
1009 }
1010 return \"bug\";
1011 }"
1012 [(set_attr "length" "4,4")
1013 (set_attr "cc" "set_n,set_n")])
1015 ;;|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1016 ;; ior
1018 (define_insn "iorqi3"
1019 [(set (match_operand:QI 0 "register_operand" "=r,d")
1020 (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
1021 (match_operand:QI 2 "nonmemory_operand" "r,i")))]
1022 ""
1023 "@
1024 or %0,%2
1025 ori %0,lo8(%2)"
1026 [(set_attr "length" "1,1")
1027 (set_attr "cc" "set_zn,set_zn")])
1029 (define_insn "iorhi3"
1030 [(set (match_operand:HI 0 "register_operand" "=r,d")
1031 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
1032 (match_operand:HI 2 "nonmemory_operand" "r,i")))]
1033 ""
1034 "*{
1035 if (which_alternative==0)
1036 return (AS2 (or,%A0,%A2) CR_TAB
1037 AS2 (or,%B0,%B2));
1038 if (GET_CODE (operands[2]) == CONST_INT)
1039 {
1040 int mask = INTVAL (operands[2]);
1041 if (mask & 0xff)
1042 output_asm_insn (AS2 (ori,%A0,lo8(%2)), operands);
1043 if (mask & 0xff00)
1044 output_asm_insn (AS2 (ori,%B0,hi8(%2)), operands);
1045 return \"\";
1046 }
1047 return (AS2 (ori,%0,lo8(%2)) CR_TAB
1048 AS2 (ori,%B0,hi8(%2)));
1049 }"
1050 [(set_attr "length" "2,2")
1051 (set_attr "cc" "set_n,clobber")])
1053 (define_insn "*iorhi3_clobber"
1054 [(set (match_operand:HI 0 "register_operand" "=r,r")
1055 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
1056 (match_operand:HI 2 "immediate_operand" "M,i")))
1057 (clobber (match_scratch:QI 3 "=&d,&d"))]
1058 ""
1059 "@
1060 ldi %3,lo8(%2)\;or %A0,%3
1061 ldi %3,lo8(%2)\;or %A0,%3\;ldi %3,hi8(%2)\;or %B0,%3"
1062 [(set_attr "length" "2,4")
1063 (set_attr "cc" "clobber,set_n")])
1065 (define_insn "iorsi3"
1066 [(set (match_operand:SI 0 "register_operand" "=r,d")
1067 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
1068 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
1069 ""
1070 "*{
1071 if (which_alternative==0)
1072 return (AS2 (or, %0,%2) CR_TAB
1073 AS2 (or, %B0,%B2) CR_TAB
1074 AS2 (or, %C0,%C2) CR_TAB
1075 AS2 (or, %D0,%D2));
1076 if (GET_CODE (operands[2]) == CONST_INT)
1077 {
1078 HOST_WIDE_INT mask = INTVAL (operands[2]);
1079 if (mask & 0xff)
1080 output_asm_insn (AS2 (ori,%A0,lo8(%2)), operands);
1081 if (mask & 0xff00)
1082 output_asm_insn (AS2 (ori,%B0,hi8(%2)), operands);
1083 if (mask & 0xff0000UL)
1084 output_asm_insn (AS2 (ori,%C0,hlo8(%2)), operands);
1085 if (mask & 0xff000000UL)
1086 output_asm_insn (AS2 (ori,%D0,hhi8(%2)), operands);
1087 return \"\";
1088 }
1089 return (AS2 (ori, %A0,lo8(%2)) CR_TAB
1090 AS2 (ori, %B0,hi8(%2)) CR_TAB
1091 AS2 (ori, %C0,hlo8(%2)) CR_TAB
1092 AS2 (ori, %D0,hhi8(%2)));
1093 }"
1094 [(set_attr "length" "4,4")
1095 (set_attr "cc" "set_n,clobber")])
1097 (define_insn "*iorsi3_clobber"
1098 [(set (match_operand:SI 0 "register_operand" "=r,r")
1099 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
1100 (match_operand:SI 2 "immediate_operand" "M,i")))
1101 (clobber (match_scratch:QI 3 "=&d,&d"))]
1102 ""
1103 "@
1104 ldi %3,lo8(%2)\;or %A0,%3
1105 ldi %3,lo8(%2)\;or %A0,%3\;ldi %3,hi8(%2)\;or %B0,%3\;ldi %3,hlo8(%2)\;or %C0,%3\;ldi %3,hhi8(%2)\;or %D0,%3"
1106 [(set_attr "length" "2,8")
1107 (set_attr "cc" "clobber,set_n")])
1109 ;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1110 ;; xor
1112 (define_insn "xorqi3"
1113 [(set (match_operand:QI 0 "register_operand" "=r")
1114 (xor:QI (match_operand:QI 1 "register_operand" "%0")
1115 (match_operand:QI 2 "register_operand" "r")))]
1116 ""
1117 "eor %0,%2"
1118 [(set_attr "length" "1")
1119 (set_attr "cc" "set_zn")])
1121 (define_insn "xorhi3"
1122 [(set (match_operand:HI 0 "register_operand" "=r")
1123 (xor:HI (match_operand:HI 1 "register_operand" "%0")
1124 (match_operand:HI 2 "register_operand" "r")))]
1125 ""
1126 "eor %0,%2
1127 eor %B0,%B2"
1128 [(set_attr "length" "2")
1129 (set_attr "cc" "set_n")])
1131 (define_insn "xorsi3"
1132 [(set (match_operand:SI 0 "register_operand" "=r")
1133 (xor:SI (match_operand:SI 1 "register_operand" "%0")
1134 (match_operand:SI 2 "register_operand" "r")))]
1135 ""
1136 "eor %0,%2
1137 eor %B0,%B2
1138 eor %C0,%C2
1139 eor %D0,%D2"
1140 [(set_attr "length" "4")
1141 (set_attr "cc" "set_n")])
1143 ;;<< << << << << << << << << << << << << << << << << << << << << << << << << <<
1144 ;; arithmetic shift left
1146 (define_insn "ashlqi3"
1147 [(set (match_operand:QI 0 "register_operand" "=r,r,r,!d,r,r")
1148 (ashift:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0")
1149 (match_operand:QI 2 "general_operand" "r,P,K,n,n,Qm")))]
1150 ""
1151 "* return ashlqi3_out (insn, operands, NULL);"
1152 [(set_attr "length" "5,1,2,4,6,9")
1153 (set_attr "cc" "clobber,set_czn,set_czn,set_czn,set_czn,clobber")])
1155 (define_insn "ashlhi3"
1156 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
1157 (ashift:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0,0")
1158 (match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
1159 ""
1160 "* return ashlhi3_out (insn, operands, NULL);"
1161 [(set_attr "length" "6,2,2,4,10,10")
1162 (set_attr "cc" "clobber,set_n,clobber,set_n,clobber,clobber")])
1164 (define_insn "ashlsi3"
1165 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
1166 (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r,0,0,0")
1167 (match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
1168 ""
1169 "* return ashlsi3_out (insn, operands, NULL);"
1170 [(set_attr "length" "8,4,4,8,10,12")
1171 (set_attr "cc" "clobber,set_n,clobber,set_n,clobber,clobber")])
1173 ;; Optimize if a scratch register from LD_REGS happens to be available.
1175 (define_peephole2
1176 [(match_scratch:QI 3 "d")
1177 (set (match_operand:HI 0 "register_operand" "")
1178 (ashift:HI (match_operand:HI 1 "register_operand" "")
1179 (match_operand:QI 2 "const_int_operand" "")))]
1180 ""
1181 [(parallel [(set (match_dup 0) (ashift:HI (match_dup 1) (match_dup 2)))
1182 (clobber (match_dup 3))])]
1183 "if (!avr_peep2_scratch_safe (operands[3]))
1184 FAIL;")
1186 (define_insn "*ashlhi3_const"
1187 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
1188 (ashift:HI (match_operand:HI 1 "register_operand" "0,r,0,0")
1189 (match_operand:QI 2 "const_int_operand" "P,O,K,n")))
1190 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
1191 "reload_completed"
1192 "* return ashlhi3_out (insn, operands, NULL);"
1193 [(set_attr "length" "2,2,4,10")
1194 (set_attr "cc" "set_n,clobber,set_n,clobber")])
1196 (define_peephole2
1197 [(match_scratch:QI 3 "d")
1198 (set (match_operand:SI 0 "register_operand" "")
1199 (ashift:SI (match_operand:SI 1 "register_operand" "")
1200 (match_operand:QI 2 "const_int_operand" "")))]
1201 ""
1202 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
1203 (clobber (match_dup 3))])]
1204 "if (!avr_peep2_scratch_safe (operands[3]))
1205 FAIL;")
1207 (define_insn "*ashlsi3_const"
1208 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1209 (ashift:SI (match_operand:SI 1 "register_operand" "0,r,0")
1210 (match_operand:QI 2 "const_int_operand" "P,O,n")))
1211 (clobber (match_scratch:QI 3 "=X,X,&d"))]
1212 "reload_completed"
1213 "* return ashlsi3_out (insn, operands, NULL);"
1214 [(set_attr "length" "4,4,10")
1215 (set_attr "cc" "set_n,clobber,clobber")])
1217 ;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
1218 ;; arithmetic shift right
1220 (define_insn "ashrqi3"
1221 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
1222 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0")
1223 (match_operand:QI 2 "general_operand" "r,P,K,n,Qm")))]
1224 ""
1225 "* return ashrqi3_out (insn, operands, NULL);"
1226 [(set_attr "length" "5,1,2,5,9")
1227 (set_attr "cc" "clobber,clobber,clobber,clobber,clobber")])
1229 (define_insn "ashrhi3"
1230 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
1231 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0,0")
1232 (match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
1233 ""
1234 "* return ashrhi3_out (insn, operands, NULL);"
1235 [(set_attr "length" "6,2,4,4,10,10")
1236 (set_attr "cc" "clobber,clobber,set_n,clobber,clobber,clobber")])
1238 (define_insn "ashrsi3"
1239 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
1240 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0,0,0")
1241 (match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
1242 ""
1243 "* return ashrsi3_out (insn, operands, NULL);"
1244 [(set_attr "length" "8,4,6,8,10,12")
1245 (set_attr "cc" "clobber,clobber,set_n,clobber,clobber,clobber")])
1247 ;; Optimize if a scratch register from LD_REGS happens to be available.
1249 (define_peephole2
1250 [(match_scratch:QI 3 "d")
1251 (set (match_operand:HI 0 "register_operand" "")
1252 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
1253 (match_operand:QI 2 "const_int_operand" "")))]
1254 ""
1255 [(parallel [(set (match_dup 0) (ashiftrt:HI (match_dup 1) (match_dup 2)))
1256 (clobber (match_dup 3))])]
1257 "if (!avr_peep2_scratch_safe (operands[3]))
1258 FAIL;")
1260 (define_insn "*ashrhi3_const"
1261 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
1262 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,r,0,0")
1263 (match_operand:QI 2 "const_int_operand" "P,O,K,n")))
1264 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
1265 "reload_completed"
1266 "* return ashrhi3_out (insn, operands, NULL);"
1267 [(set_attr "length" "2,4,4,10")
1268 (set_attr "cc" "clobber,set_n,clobber,clobber")])
1270 (define_peephole2
1271 [(match_scratch:QI 3 "d")
1272 (set (match_operand:SI 0 "register_operand" "")
1273 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
1274 (match_operand:QI 2 "const_int_operand" "")))]
1275 ""
1276 [(parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (match_dup 2)))
1277 (clobber (match_dup 3))])]
1278 "if (!avr_peep2_scratch_safe (operands[3]))
1279 FAIL;")
1281 (define_insn "*ashrsi3_const"
1282 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1283 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,r,0")
1284 (match_operand:QI 2 "const_int_operand" "P,O,n")))
1285 (clobber (match_scratch:QI 3 "=X,X,&d"))]
1286 "reload_completed"
1287 "* return ashrsi3_out (insn, operands, NULL);"
1288 [(set_attr "length" "4,4,10")
1289 (set_attr "cc" "clobber,set_n,clobber")])
1291 ;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
1292 ;; logical shift right
1294 (define_insn "lshrqi3"
1295 [(set (match_operand:QI 0 "register_operand" "=r,r,r,!d,r,r")
1296 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0")
1297 (match_operand:QI 2 "general_operand" "r,P,K,n,n,Qm")))]
1298 ""
1299 "* return lshrqi3_out (insn, operands, NULL);"
1300 [(set_attr "length" "5,1,2,4,6,9")
1301 (set_attr "cc" "clobber,set_czn,set_czn,set_czn,set_czn,clobber")])
1303 (define_insn "lshrhi3"
1304 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
1305 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0,0")
1306 (match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
1307 ""
1308 "* return lshrhi3_out (insn, operands, NULL);"
1309 [(set_attr "length" "6,2,2,4,10,10")
1310 (set_attr "cc" "clobber,clobber,clobber,clobber,clobber,clobber")])
1312 (define_insn "lshrsi3"
1313 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
1314 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0,0,0")
1315 (match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
1316 ""
1317 "* return lshrsi3_out (insn, operands, NULL);"
1318 [(set_attr "length" "8,4,4,8,10,12")
1319 (set_attr "cc" "clobber,clobber,clobber,clobber,clobber,clobber")])
1321 ;; Optimize if a scratch register from LD_REGS happens to be available.
1323 (define_peephole2
1324 [(match_scratch:QI 3 "d")
1325 (set (match_operand:HI 0 "register_operand" "")
1326 (lshiftrt:HI (match_operand:HI 1 "register_operand" "")
1327 (match_operand:QI 2 "const_int_operand" "")))]
1328 ""
1329 [(parallel [(set (match_dup 0) (lshiftrt:HI (match_dup 1) (match_dup 2)))
1330 (clobber (match_dup 3))])]
1331 "if (!avr_peep2_scratch_safe (operands[3]))
1332 FAIL;")
1334 (define_insn "*lshrhi3_const"
1335 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
1336 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,r,0,0")
1337 (match_operand:QI 2 "const_int_operand" "P,O,K,n")))
1338 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
1339 "reload_completed"
1340 "* return lshrhi3_out (insn, operands, NULL);"
1341 [(set_attr "length" "2,2,4,10")
1342 (set_attr "cc" "clobber,clobber,clobber,clobber")])
1344 (define_peephole2
1345 [(match_scratch:QI 3 "d")
1346 (set (match_operand:SI 0 "register_operand" "")
1347 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
1348 (match_operand:QI 2 "const_int_operand" "")))]
1349 ""
1350 [(parallel [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (match_dup 2)))
1351 (clobber (match_dup 3))])]
1352 "if (!avr_peep2_scratch_safe (operands[3]))
1353 FAIL;")
1355 (define_insn "*lshrsi3_const"
1356 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1357 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,r,0")
1358 (match_operand:QI 2 "const_int_operand" "P,O,n")))
1359 (clobber (match_scratch:QI 3 "=X,X,&d"))]
1360 "reload_completed"
1361 "* return lshrsi3_out (insn, operands, NULL);"
1362 [(set_attr "length" "4,4,10")
1363 (set_attr "cc" "clobber,clobber,clobber")])
1365 ;; abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x)
1366 ;; abs
1368 (define_insn "absqi2"
1369 [(set (match_operand:QI 0 "register_operand" "=r")
1370 (abs:QI (match_operand:QI 1 "register_operand" "0")))]
1371 ""
1372 "sbrc %0,7
1373 neg %0"
1374 [(set_attr "length" "2")
1375 (set_attr "cc" "clobber")])
1378 (define_insn "abssf2"
1379 [(set (match_operand:SF 0 "register_operand" "=d,r")
1380 (abs:SF (match_operand:SF 1 "register_operand" "0,0")))]
1381 ""
1382 "@
1383 andi %D0,0x7f
1384 clt\;bld %D0,7"
1385 [(set_attr "length" "1,2")
1386 (set_attr "cc" "set_n,clobber")])
1388 ;; 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x
1389 ;; neg
1391 (define_insn "negqi2"
1392 [(set (match_operand:QI 0 "register_operand" "=r")
1393 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
1394 ""
1395 "neg %0"
1396 [(set_attr "length" "1")
1397 (set_attr "cc" "set_zn")])
1399 (define_insn "neghi2"
1400 [(set (match_operand:HI 0 "register_operand" "=!d,r,&r")
1401 (neg:HI (match_operand:HI 1 "register_operand" "0,0,r")))]
1402 ""
1403 "@
1404 com %B0\;neg %A0\;sbci %B0,lo8(-1)
1405 com %B0\;neg %A0\;sbc %B0,__zero_reg__\;inc %B0
1406 clr %A0\;clr %B0\;sub %A0,%A1\;sbc %B0,%B1"
1407 [(set_attr "length" "3,4,4")
1408 (set_attr "cc" "set_czn,set_n,set_czn")])
1410 (define_insn "negsi2"
1411 [(set (match_operand:SI 0 "register_operand" "=!d,r,&r")
1412 (neg:SI (match_operand:SI 1 "register_operand" "0,0,r")))]
1413 ""
1414 "@
1415 com %D0\;com %C0\;com %B0\;neg %A0\;sbci %B0,lo8(-1)\;sbci %C0,lo8(-1)\;sbci %D0,lo8(-1)
1416 com %D0\;com %C0\;com %B0\;com %A0\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
1417 clr %A0\;clr %B0\;{clr %C0\;clr %D0|movw %C0,%A0}\;sub %A0,%A1\;sbc %B0,%B1\;sbc %C0,%C1\;sbc %D0,%D1"
1418 [(set_attr_alternative "length"
1419 [(const_int 7)
1420 (const_int 8)
1421 (if_then_else (eq_attr "mcu_enhanced" "yes")
1422 (const_int 7)
1423 (const_int 8))])
1424 (set_attr "cc" "set_czn,set_n,set_czn")])
1426 (define_insn "negsf2"
1427 [(set (match_operand:SF 0 "register_operand" "=d,r")
1428 (neg:SF (match_operand:SF 1 "register_operand" "0,0")))]
1429 ""
1430 "@
1431 subi %D0,0x80
1432 bst %D0,7\;com %D0\;bld %D0,7\;com %D0"
1433 [(set_attr "length" "1,4")
1434 (set_attr "cc" "set_n,set_n")])
1436 ;; !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1437 ;; not
1439 (define_insn "one_cmplqi2"
1440 [(set (match_operand:QI 0 "register_operand" "=r")
1441 (not:QI (match_operand:QI 1 "register_operand" "0")))]
1442 ""
1443 "com %0"
1444 [(set_attr "length" "1")
1445 (set_attr "cc" "set_czn")])
1447 (define_insn "one_cmplhi2"
1448 [(set (match_operand:HI 0 "register_operand" "=r")
1449 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1450 ""
1451 "com %0
1452 com %B0"
1453 [(set_attr "length" "2")
1454 (set_attr "cc" "set_n")])
1456 (define_insn "one_cmplsi2"
1457 [(set (match_operand:SI 0 "register_operand" "=r")
1458 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1459 ""
1460 "com %0
1461 com %B0
1462 com %C0
1463 com %D0"
1464 [(set_attr "length" "4")
1465 (set_attr "cc" "set_n")])
1467 ;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x
1468 ;; sign extend
1470 (define_insn "extendqihi2"
1471 [(set (match_operand:HI 0 "register_operand" "=r,r")
1472 (sign_extend:HI (match_operand:QI 1 "register_operand" "0,*r")))]
1473 ""
1474 "@
1475 clr %B0\;sbrc %0,7\;com %B0
1476 mov %A0,%A1\;clr %B0\;sbrc %A0,7\;com %B0"
1477 [(set_attr "length" "3,4")
1478 (set_attr "cc" "set_n,set_n")])
1480 (define_insn "extendqisi2"
1481 [(set (match_operand:SI 0 "register_operand" "=r,r")
1482 (sign_extend:SI (match_operand:QI 1 "register_operand" "0,*r")))]
1483 ""
1484 "@
1485 clr %B0\;sbrc %A0,7\;com %B0\;mov %C0,%B0\;mov %D0,%B0
1486 mov %A0,%A1\;clr %B0\;sbrc %A0,7\;com %B0\;mov %C0,%B0\;mov %D0,%B0"
1487 [(set_attr "length" "5,6")
1488 (set_attr "cc" "set_n,set_n")])
1490 (define_insn "extendhisi2"
1491 [(set (match_operand:SI 0 "register_operand" "=r,&r")
1492 (sign_extend:SI (match_operand:HI 1 "register_operand" "0,*r")))]
1493 ""
1494 "@
1495 clr %C0\;sbrc %B0,7\;com %C0\;mov %D0,%C0
1496 {mov %A0,%A1\;mov %B0,%B1|movw %A0,%A1}\;clr %C0\;sbrc %B0,7\;com %C0\;mov %D0,%C0"
1497 [(set_attr_alternative "length"
1498 [(const_int 4)
1499 (if_then_else (eq_attr "mcu_enhanced" "yes")
1500 (const_int 5)
1501 (const_int 6))])
1502 (set_attr "cc" "set_n,set_n")])
1504 ;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x
1505 ;; zero extend
1507 (define_insn "zero_extendqihi2"
1508 [(set (match_operand:HI 0 "register_operand" "=r,r")
1509 (zero_extend:HI (match_operand:QI 1 "register_operand" "0,*r")))]
1510 ""
1511 "@
1512 clr %B0
1513 mov %A0,%A1\;clr %B0"
1514 [(set_attr "length" "1,2")
1515 (set_attr "cc" "set_n,set_n")])
1517 (define_insn "zero_extendqisi2"
1518 [(set (match_operand:SI 0 "register_operand" "=r,r")
1519 (zero_extend:SI (match_operand:QI 1 "register_operand" "0,*r")))]
1520 ""
1521 "@
1522 clr %B0\;clr %C0\;clr %D0
1523 mov %A0,%A1\;clr %B0\;clr %C0\;clr %D0"
1524 [(set_attr "length" "3,4")
1525 (set_attr "cc" "set_n,set_n")])
1527 (define_insn "zero_extendhisi2"
1528 [(set (match_operand:SI 0 "register_operand" "=r,&r")
1529 (zero_extend:SI (match_operand:HI 1 "register_operand" "0,*r")))]
1530 ""
1531 "@
1532 clr %C0\;clr %D0
1533 {mov %A0,%A1\;mov %B0,%B1|movw %A0,%A1}\;clr %C0\;clr %D0"
1534 [(set_attr_alternative "length"
1535 [(const_int 2)
1536 (if_then_else (eq_attr "mcu_enhanced" "yes")
1537 (const_int 3)
1538 (const_int 4))])
1539 (set_attr "cc" "set_n,set_n")])
1541 ;;<=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=>
1542 ;; compare
1544 (define_insn "tstqi"
1545 [(set (cc0)
1546 (match_operand:QI 0 "register_operand" "r"))]
1547 ""
1548 "tst %0"
1549 [(set_attr "cc" "compare")
1550 (set_attr "length" "1")])
1552 (define_insn "*negated_tstqi"
1553 [(set (cc0)
1554 (neg:QI (match_operand:QI 0 "register_operand" "r")))]
1555 ""
1556 "cp __zero_reg__,%0"
1557 [(set_attr "cc" "compare")
1558 (set_attr "length" "1")])
1560 (define_insn "tsthi"
1561 [(set (cc0)
1562 (match_operand:HI 0 "register_operand" "!w,r"))]
1563 ""
1564 "* return out_tsthi (insn,NULL);"
1565 [(set_attr "cc" "compare,compare")
1566 (set_attr "length" "1,2")])
1568 (define_insn "*negated_tsthi"
1569 [(set (cc0)
1570 (neg:HI (match_operand:HI 0 "register_operand" "r")))]
1571 ""
1572 "cp __zero_reg__,%A0
1573 cpc __zero_reg__,%B0"
1574 [(set_attr "cc" "compare")
1575 (set_attr "length" "2")])
1577 (define_insn "tstsi"
1578 [(set (cc0)
1579 (match_operand:SI 0 "register_operand" "r"))]
1580 ""
1581 "* return out_tstsi (insn,NULL);"
1582 [(set_attr "cc" "compare")
1583 (set_attr "length" "4")])
1585 (define_insn "*negated_tstsi"
1586 [(set (cc0)
1587 (neg:SI (match_operand:SI 0 "register_operand" "r")))]
1588 ""
1589 "cp __zero_reg__,%A0
1590 cpc __zero_reg__,%B0
1591 cpc __zero_reg__,%C0
1592 cpc __zero_reg__,%D0"
1593 [(set_attr "cc" "compare")
1594 (set_attr "length" "4")])
1597 (define_insn "cmpqi"
1598 [(set (cc0)
1599 (compare (match_operand:QI 0 "register_operand" "r,d")
1600 (match_operand:QI 1 "nonmemory_operand" "r,i")))]
1601 ""
1602 "@
1603 cp %0,%1
1604 cpi %0,lo8(%1)"
1605 [(set_attr "cc" "compare,compare")
1606 (set_attr "length" "1,1")])
1608 (define_insn "*cmpqi_sign_extend"
1609 [(set (cc0)
1610 (compare (sign_extend:HI
1611 (match_operand:QI 0 "register_operand" "d"))
1612 (match_operand:HI 1 "immediate_operand" "M")))]
1613 ""
1614 "cpi %0,lo8(%1)"
1615 [(set_attr "cc" "compare")
1616 (set_attr "length" "1")])
1618 (define_insn "cmphi"
1619 [(set (cc0)
1620 (compare (match_operand:HI 0 "register_operand" "r,d,d,r,r")
1621 (match_operand:HI 1 "nonmemory_operand" "r,M,i,M,i")))
1622 (clobber (match_scratch:QI 2 "=X,X,&d,&d,&d"))]
1623 ""
1624 "*{
1625 switch (which_alternative)
1626 {
1627 case 0:
1628 return (AS2 (cp,%A0,%A1) CR_TAB
1629 AS2 (cpc,%B0,%B1));
1630 case 1:
1631 if (reg_unused_after (insn, operands[0])
1632 && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 63
1633 && test_hard_reg_class (ADDW_REGS, operands[0]))
1634 return AS2 (sbiw,%0,%1);
1635 else
1636 return (AS2 (cpi,%0,%1) CR_TAB
1637 AS2 (cpc,%B0,__zero_reg__));
1638 case 2:
1639 if (reg_unused_after (insn, operands[0]))
1640 return (AS2 (subi,%0,lo8(%1)) CR_TAB
1641 AS2 (sbci,%B0,hi8(%1)));
1642 else
1643 return (AS2 (ldi, %2,hi8(%1)) CR_TAB
1644 AS2 (cpi, %A0,lo8(%1)) CR_TAB
1645 AS2 (cpc, %B0,%2));
1646 case 3:
1647 return (AS2 (ldi, %2,lo8(%1)) CR_TAB
1648 AS2 (cp, %A0,%2) CR_TAB
1649 AS2 (cpc, %B0,__zero_reg__));
1651 case 4:
1652 return (AS2 (ldi, %2,lo8(%1)) CR_TAB
1653 AS2 (cp, %A0,%2) CR_TAB
1654 AS2 (ldi, %2,hi8(%1)) CR_TAB
1655 AS2 (cpc, %B0,%2));
1656 }
1657 return \"bug\";
1658 }"
1659 [(set_attr "cc" "compare,compare,compare,compare,compare")
1660 (set_attr "length" "2,2,3,3,4")])
1663 (define_insn "cmpsi"
1664 [(set (cc0)
1665 (compare (match_operand:SI 0 "register_operand" "r,d,d,r,r")
1666 (match_operand:SI 1 "nonmemory_operand" "r,M,i,M,i")))
1667 (clobber (match_scratch:QI 2 "=X,X,&d,&d,&d"))]
1668 ""
1669 "*{
1670 switch (which_alternative)
1671 {
1672 case 0:
1673 return (AS2 (cp,%A0,%A1) CR_TAB
1674 AS2 (cpc,%B0,%B1) CR_TAB
1675 AS2 (cpc,%C0,%C1) CR_TAB
1676 AS2 (cpc,%D0,%D1));
1677 case 1:
1678 if (reg_unused_after (insn, operands[0])
1679 && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 63
1680 && test_hard_reg_class (ADDW_REGS, operands[0]))
1681 return (AS2 (sbiw,%0,%1) CR_TAB
1682 AS2 (cpc,%C0,__zero_reg__) CR_TAB
1683 AS2 (cpc,%D0,__zero_reg__));
1684 else
1685 return (AS2 (cpi,%A0,lo8(%1)) CR_TAB
1686 AS2 (cpc,%B0,__zero_reg__) CR_TAB
1687 AS2 (cpc,%C0,__zero_reg__) CR_TAB
1688 AS2 (cpc,%D0,__zero_reg__));
1689 case 2:
1690 if (reg_unused_after (insn, operands[0]))
1691 return (AS2 (subi,%A0,lo8(%1)) CR_TAB
1692 AS2 (sbci,%B0,hi8(%1)) CR_TAB
1693 AS2 (sbci,%C0,hlo8(%1)) CR_TAB
1694 AS2 (sbci,%D0,hhi8(%1)));
1695 else
1696 return (AS2 (cpi, %A0,lo8(%1)) CR_TAB
1697 AS2 (ldi, %2,hi8(%1)) CR_TAB
1698 AS2 (cpc, %B0,%2) CR_TAB
1699 AS2 (ldi, %2,hlo8(%1)) CR_TAB
1700 AS2 (cpc, %C0,%2) CR_TAB
1701 AS2 (ldi, %2,hhi8(%1)) CR_TAB
1702 AS2 (cpc, %D0,%2));
1703 case 3:
1704 return (AS2 (ldi,%2,lo8(%1)) CR_TAB
1705 AS2 (cp,%A0,%2) CR_TAB
1706 AS2 (cpc,%B0,__zero_reg__) CR_TAB
1707 AS2 (cpc,%C0,__zero_reg__) CR_TAB
1708 AS2 (cpc,%D0,__zero_reg__));
1709 case 4:
1710 return (AS2 (ldi, %2,lo8(%1)) CR_TAB
1711 AS2 (cp, %A0,%2) CR_TAB
1712 AS2 (ldi, %2,hi8(%1)) CR_TAB
1713 AS2 (cpc, %B0,%2) CR_TAB
1714 AS2 (ldi, %2,hlo8(%1)) CR_TAB
1715 AS2 (cpc, %C0,%2) CR_TAB
1716 AS2 (ldi, %2,hhi8(%1)) CR_TAB
1717 AS2 (cpc, %D0,%2));
1718 }
1719 return \"bug\";
1720 }"
1721 [(set_attr "cc" "compare,compare,compare,compare,compare")
1722 (set_attr "length" "4,4,7,5,8")])
1724 ;; ----------------------------------------------------------------------
1725 ;; JUMP INSTRUCTIONS
1726 ;; ----------------------------------------------------------------------
1727 ;; Conditional jump instructions
1729 (define_expand "beq"
1730 [(set (pc)
1731 (if_then_else (eq (cc0) (const_int 0))
1732 (label_ref (match_operand 0 "" ""))
1733 (pc)))]
1734 ""
1735 "")
1737 (define_expand "bne"
1738 [(set (pc)
1739 (if_then_else (ne (cc0) (const_int 0))
1740 (label_ref (match_operand 0 "" ""))
1741 (pc)))]
1742 ""
1743 "")
1745 (define_expand "bge"
1746 [(set (pc)
1747 (if_then_else (ge (cc0) (const_int 0))
1748 (label_ref (match_operand 0 "" ""))
1749 (pc)))]
1750 ""
1751 "")
1753 (define_expand "bgeu"
1754 [(set (pc)
1755 (if_then_else (geu (cc0) (const_int 0))
1756 (label_ref (match_operand 0 "" ""))
1757 (pc)))]
1758 ""
1759 "")
1761 (define_expand "blt"
1762 [(set (pc)
1763 (if_then_else (lt (cc0) (const_int 0))
1764 (label_ref (match_operand 0 "" ""))
1765 (pc)))]
1766 ""
1767 "")
1769 (define_expand "bltu"
1770 [(set (pc)
1771 (if_then_else (ltu (cc0) (const_int 0))
1772 (label_ref (match_operand 0 "" ""))
1773 (pc)))]
1774 ""
1775 "")
1779 /****************************************************************
1780 AVR not have following conditional jumps: LE,LEU,GT,GTU.
1781 Convert them all to proper jumps.
1782 *****************************************************************/
1784 (define_expand "ble"
1785 [(set (pc)
1786 (if_then_else (le (cc0) (const_int 0))
1787 (label_ref (match_operand 0 "" ""))
1788 (pc)))]
1789 ""
1790 "")
1792 (define_expand "bleu"
1793 [(set (pc)
1794 (if_then_else (leu (cc0) (const_int 0))
1795 (label_ref (match_operand 0 "" ""))
1796 (pc)))]
1797 ""
1798 "")
1800 (define_expand "bgt"
1801 [(set (pc)
1802 (if_then_else (gt (cc0) (const_int 0))
1803 (label_ref (match_operand 0 "" ""))
1804 (pc)))]
1805 ""
1806 "")
1808 (define_expand "bgtu"
1809 [(set (pc)
1810 (if_then_else (gtu (cc0) (const_int 0))
1811 (label_ref (match_operand 0 "" ""))
1812 (pc)))]
1813 ""
1814 "")
1816 (define_insn "*sbrx_branch"
1817 [(set (pc)
1818 (if_then_else
1819 (match_operator 0 "comparison_operator"
1820 [(zero_extract
1821 (match_operand:QI 1 "register_operand" "r")
1822 (const_int 1)
1823 (match_operand 2 "immediate_operand" "n"))
1824 (const_int 0)])
1825 (label_ref (match_operand 3 "" ""))
1826 (pc)))]
1827 "(GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE)"
1828 "* {
1829 int comp = ((get_attr_length (insn) == 4)
1830 ? reverse_condition (GET_CODE (operands[0]))
1831 : GET_CODE (operands[0]));
1832 if (comp == EQ)
1833 output_asm_insn (AS2 (sbrs,%1,%2), operands);
1834 else
1835 output_asm_insn (AS2 (sbrc,%1,%2), operands);
1836 if (get_attr_length (insn) != 4)
1837 return AS1 (rjmp,%3);
1838 return (AS1 (rjmp,_PC_+4) CR_TAB
1839 AS1 (jmp,%3));
1840 }"
1841 [(set (attr "length")
1842 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
1843 (le (minus (pc) (match_dup 3)) (const_int 2046)))
1844 (const_int 2)
1845 (if_then_else (eq_attr "mcu_mega" "no")
1846 (const_int 2)
1847 (const_int 4))))
1848 (set_attr "cc" "clobber")])
1850 (define_insn "*sbrx_and_branchsi"
1851 [(set (pc)
1852 (if_then_else
1853 (match_operator 0 "comparison_operator"
1854 [(and:SI
1855 (match_operand:SI 1 "register_operand" "r")
1856 (match_operand:SI 2 "immediate_operand" "n"))
1857 (const_int 0)])
1858 (label_ref (match_operand 3 "" ""))
1859 (pc)))]
1860 "(GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE)
1861 && mask_one_bit_p(INTVAL (operands[2]))"
1862 "* {
1863 int comp = ((get_attr_length (insn) == 4)
1864 ? reverse_condition (GET_CODE (operands[0]))
1865 : GET_CODE (operands[0]));
1866 int bit = mask_one_bit_p(INTVAL (operands[2])) - 1;
1867 static char buf[] = \"sbrc %A1,0\";
1868 buf[3] = (comp == EQ ? 's' : 'c');
1869 buf[6] = bit / 8 + 'A';
1870 buf[9] = bit % 8 + '0';
1871 output_asm_insn (buf, operands);
1873 if (get_attr_length (insn) != 4)
1874 return AS1 (rjmp,%3);
1875 return (AS1 (rjmp,_PC_+4) CR_TAB
1876 AS1 (jmp,%3));
1877 }"
1878 [(set (attr "length")
1879 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
1880 (le (minus (pc) (match_dup 3)) (const_int 2046)))
1881 (const_int 2)
1882 (if_then_else (eq_attr "mcu_mega" "no")
1883 (const_int 2)
1884 (const_int 4))))
1885 (set_attr "cc" "clobber")])
1887 (define_insn "*sbrx_and_branchhi"
1888 [(set (pc)
1889 (if_then_else
1890 (match_operator 0 "comparison_operator"
1891 [(and:HI
1892 (match_operand:HI 1 "register_operand" "r")
1893 (match_operand:HI 2 "immediate_operand" "n"))
1894 (const_int 0)])
1895 (label_ref (match_operand 3 "" ""))
1896 (pc)))]
1897 "(GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE)
1898 && mask_one_bit_p(INTVAL (operands[2]))"
1899 "* {
1900 int comp = ((get_attr_length (insn) == 4)
1901 ? reverse_condition (GET_CODE (operands[0]))
1902 : GET_CODE (operands[0]));
1903 int bit = mask_one_bit_p(INTVAL (operands[2])) - 1;
1904 static char buf[] = \"sbrc %A1,0\";
1905 buf[3] = (comp == EQ ? 's' : 'c');
1906 buf[6] = bit / 8 + 'A';
1907 buf[9] = bit % 8 + '0';
1908 output_asm_insn (buf, operands);
1910 if (get_attr_length (insn) != 4)
1911 return AS1 (rjmp,%3);
1912 return (AS1 (rjmp,_PC_+4) CR_TAB
1913 AS1 (jmp,%3));
1914 }"
1915 [(set (attr "length")
1916 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
1917 (le (minus (pc) (match_dup 3)) (const_int 2046)))
1918 (const_int 2)
1919 (if_then_else (eq_attr "mcu_mega" "no")
1920 (const_int 2)
1921 (const_int 4))))
1922 (set_attr "cc" "clobber")])
1924 ;; ************************************************************************
1925 ;; Implementation of conditional jumps here.
1926 ;; Compare with 0 (test) jumps
1927 ;; ************************************************************************
1929 (define_insn "branch"
1930 [(set (pc)
1931 (if_then_else (match_operator 1 "comparison_operator"
1932 [(cc0)
1933 (const_int 0)])
1934 (label_ref (match_operand 0 "" ""))
1935 (pc)))]
1936 "! (GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GTU
1937 || GET_CODE (operands[1]) == LE || GET_CODE (operands[1]) == LEU)"
1938 "*
1939 return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);"
1940 [(set_attr "type" "branch")
1941 (set_attr "cc" "clobber")])
1943 (define_insn "difficult_branch"
1944 [(set (pc)
1945 (if_then_else (match_operator 1 "comparison_operator"
1946 [(cc0)
1947 (const_int 0)])
1948 (label_ref (match_operand 0 "" ""))
1949 (pc)))]
1950 "(GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GTU
1951 || GET_CODE (operands[1]) == LE || GET_CODE (operands[1]) == LEU)"
1952 "*
1953 return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);"
1954 [(set_attr "type" "branch1")
1955 (set_attr "cc" "clobber")])
1957 ;; revers branch
1959 (define_insn "rvbranch"
1960 [(set (pc)
1961 (if_then_else (match_operator 1 "comparison_operator" [(cc0)
1962 (const_int 0)])
1963 (pc)
1964 (label_ref (match_operand 0 "" ""))))]
1965 "! (GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GTU
1966 || GET_CODE (operands[1]) == LE || GET_CODE (operands[1]) == LEU)"
1967 "*
1968 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);"
1969 [(set_attr "type" "branch1")
1970 (set_attr "cc" "clobber")])
1972 (define_insn "difficult_rvbranch"
1973 [(set (pc)
1974 (if_then_else (match_operator 1 "comparison_operator" [(cc0)
1975 (const_int 0)])
1976 (pc)
1977 (label_ref (match_operand 0 "" ""))))]
1978 "(GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GTU
1979 || GET_CODE (operands[1]) == LE || GET_CODE (operands[1]) == LEU)"
1980 "*
1981 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);"
1982 [(set_attr "type" "branch")
1983 (set_attr "cc" "clobber")])
1985 ;; **************************************************************************
1986 ;; Unconditional and other jump instructions.
1988 (define_insn "jump"
1989 [(set (pc)
1990 (label_ref (match_operand 0 "" "")))]
1991 ""
1992 "*{
1993 if (AVR_MEGA && get_attr_length (insn) != 1)
1994 return AS1 (jmp,%0);
1995 return AS1 (rjmp,%0);
1996 }"
1997 [(set (attr "length")
1998 (if_then_else (and (ge (minus (pc) (match_dup 0)) (const_int -2047))
1999 (le (minus (pc) (match_dup 0)) (const_int 2047)))
2000 (const_int 1)
2001 (const_int 2)))
2002 (set_attr "cc" "none")])
2004 ;; call
2006 (define_expand "call"
2007 [(call (match_operand:HI 0 "call_insn_operand" "")
2008 (match_operand:HI 1 "general_operand" ""))]
2009 ;; Operand 1 not used on the AVR.
2010 ""
2011 "")
2013 ;; call value
2015 (define_expand "call_value"
2016 [(set (match_operand 0 "register_operand" "")
2017 (call (match_operand:HI 1 "call_insn_operand" "")
2018 (match_operand:HI 2 "general_operand" "")))]
2019 ;; Operand 2 not used on the AVR.
2020 ""
2021 "")
2023 (define_insn "call_insn"
2024 [(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "!z,*r,i"))
2025 (match_operand:HI 1 "general_operand" "X,X,X"))]
2026 ;; We don't need in saving Z register because r30,r31 is a call used registers
2027 ;; Operand 1 not used on the AVR.
2028 "(register_operand (operands[0], HImode) || CONSTANT_P (operands[0]))"
2029 "*{
2030 if (which_alternative==0)
2031 return \"icall\";
2032 else if (which_alternative==1)
2033 {
2034 if (AVR_ENHANCED)
2035 return (AS2 (movw, r30, %0) CR_TAB
2036 \"icall\");
2037 else
2038 return (AS2 (mov, r30, %A0) CR_TAB
2039 AS2 (mov, r31, %B0) CR_TAB
2040 \"icall\");
2041 }
2042 return AS1(%~call,%c0);
2043 }"
2044 [(set_attr "cc" "clobber,clobber,clobber")
2045 (set_attr_alternative "length"
2046 [(const_int 1)
2047 (if_then_else (eq_attr "mcu_enhanced" "yes")
2048 (const_int 2)
2049 (const_int 3))
2050 (if_then_else (eq_attr "mcu_mega" "yes")
2051 (const_int 2)
2052 (const_int 1))])])
2054 (define_insn "call_value_insn"
2055 [(set (match_operand 0 "register_operand" "=r,r,r")
2056 (call (mem:HI (match_operand:HI 1 "nonmemory_operand" "!z,*r,i"))
2057 ;; We don't need in saving Z register because r30,r31 is a call used registers
2058 (match_operand:HI 2 "general_operand" "X,X,X")))]
2059 ;; Operand 2 not used on the AVR.
2060 "(register_operand (operands[0], VOIDmode) || CONSTANT_P (operands[0]))"
2061 "*
2062 {
2063 if (which_alternative==0)
2064 return \"icall\";
2065 else if (which_alternative==1)
2066 {
2067 if (AVR_ENHANCED)
2068 return (AS2 (movw, r30, %1) CR_TAB
2069 \"icall\");
2070 else
2071 return (AS2 (mov, r30, %A1) CR_TAB
2072 AS2 (mov, r31, %B1) CR_TAB
2073 \"icall\");
2074 }
2075 return AS1(%~call,%c1);
2076 }"
2077 [(set_attr "cc" "clobber,clobber,clobber")
2078 (set_attr_alternative "length"
2079 [(const_int 1)
2080 (if_then_else (eq_attr "mcu_enhanced" "yes")
2081 (const_int 2)
2082 (const_int 3))
2083 (if_then_else (eq_attr "mcu_mega" "yes")
2084 (const_int 2)
2085 (const_int 1))])])
2087 (define_insn "nop"
2088 [(const_int 0)]
2089 ""
2090 "nop"
2091 [(set_attr "cc" "none")
2092 (set_attr "length" "1")])
2094 ; indirect jump
2095 (define_insn "indirect_jump"
2096 [(set (pc) (match_operand:HI 0 "register_operand" "!z,*r"))]
2097 ""
2098 "@
2099 ijmp
2100 push %A0\;push %B0\;ret"
2101 [(set_attr "length" "1,3")
2102 (set_attr "cc" "none,none")])
2104 ;; table jump
2106 ;; Table made from "rjmp" instructions for <=8K devices.
2107 (define_insn "*tablejump_rjmp"
2108 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "!z,*r")] 1))
2109 (use (label_ref (match_operand 1 "" "")))
2110 (clobber (match_dup 0))]
2111 "!AVR_MEGA"
2112 "@
2113 ijmp
2114 push %A0\;push %B0\;ret"
2115 [(set_attr "length" "1,3")
2116 (set_attr "cc" "none,none")])
2118 ;; Not a prologue, but similar idea - move the common piece of code to libgcc.
2119 (define_insn "*tablejump_lib"
2120 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")] 1))
2121 (use (label_ref (match_operand 1 "" "")))
2122 (clobber (match_dup 0))]
2123 "AVR_MEGA && TARGET_CALL_PROLOGUES"
2124 "jmp __tablejump2__"
2125 [(set_attr "length" "2")
2126 (set_attr "cc" "clobber")])
2128 (define_insn "*tablejump_enh"
2129 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")] 1))
2130 (use (label_ref (match_operand 1 "" "")))
2131 (clobber (match_dup 0))]
2132 "AVR_MEGA && AVR_ENHANCED"
2133 "lsl r30
2134 rol r31
2135 lpm __tmp_reg__,Z+
2136 lpm r31,Z
2137 mov r30,__tmp_reg__
2138 ijmp"
2139 [(set_attr "length" "6")
2140 (set_attr "cc" "clobber")])
2142 (define_insn "*tablejump"
2143 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")] 1))
2144 (use (label_ref (match_operand 1 "" "")))
2145 (clobber (match_dup 0))]
2146 "AVR_MEGA"
2147 "lsl r30
2148 rol r31
2149 lpm
2150 inc r30
2151 push r0
2152 lpm
2153 push r0
2154 ret"
2155 [(set_attr "length" "8")
2156 (set_attr "cc" "clobber")])
2158 (define_expand "casesi"
2159 [(set (match_dup 6)
2160 (minus:HI (subreg:HI (match_operand:SI 0 "register_operand" "") 0)
2161 (match_operand:HI 1 "register_operand" "")))
2162 (parallel [(set (cc0)
2163 (compare (match_dup 6)
2164 (match_operand:HI 2 "register_operand" "")))
2165 (clobber (match_scratch:QI 9 ""))])
2167 (set (pc)
2168 (if_then_else (gtu (cc0)
2169 (const_int 0))
2170 (label_ref (match_operand 4 "" ""))
2171 (pc)))
2173 (set (match_dup 6)
2174 (plus:HI (match_dup 6) (label_ref (match_operand:HI 3 "" ""))))
2176 (parallel [(set (pc) (unspec:HI [(match_dup 6)] 1))
2177 (use (label_ref (match_dup 3)))
2178 (clobber (match_dup 6))])]
2179 ""
2180 "
2181 {
2182 operands[6] = gen_reg_rtx (HImode);
2183 }")
2186 ;; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2187 ;; This instructin sets Z flag
2189 (define_insn "sez"
2190 [(set (cc0) (const_int 0))]
2191 ""
2192 "sez"
2193 [(set_attr "length" "1")
2194 (set_attr "cc" "compare")])
2197 ;; ************************* Peepholes ********************************
2199 (define_peephole
2200 [(set (match_operand:SI 0 "register_operand" "")
2201 (plus:SI (match_dup 0)
2202 (const_int -1)))
2203 (parallel
2204 [(set (cc0)
2205 (compare (match_dup 0)
2206 (const_int -1)))
2207 (clobber (match_operand:QI 1 "register_operand" ""))])
2208 (set (pc)
2209 (if_then_else (ne (cc0) (const_int 0))
2210 (label_ref (match_operand 2 "" ""))
2211 (pc)))]
2212 "(test_hard_reg_class (LD_REGS, operands[0])
2213 && test_hard_reg_class (LD_REGS, operands[1]))"
2214 "*
2215 {
2216 if (test_hard_reg_class (ADDW_REGS, operands[0]))
2217 output_asm_insn (AS2 (sbiw,%0,1) CR_TAB
2218 AS2 (sbc,%C0,__zero_reg__) CR_TAB
2219 AS2 (sbc,%D0,__zero_reg__) \"\\n\", operands);
2220 else
2221 output_asm_insn (AS2 (subi,%A0,1) CR_TAB
2222 AS2 (sbc,%B0,__zero_reg__) CR_TAB
2223 AS2 (sbc,%C0,__zero_reg__) CR_TAB
2224 AS2 (sbc,%D0,__zero_reg__) \"\\n\", operands);
2225 switch (avr_jump_mode (operands[2],insn))
2226 {
2227 case 1:
2228 return AS1 (brcc,%2);
2229 case 2:
2230 return (AS1 (brcs,_PC_+2) CR_TAB
2231 AS1 (rjmp,%2));
2232 }
2233 return (AS1 (brcs,_PC_+4) CR_TAB
2234 AS1 (jmp,%2));
2235 }")
2237 (define_peephole
2238 [(set (match_operand:HI 0 "register_operand" "")
2239 (plus:HI (match_dup 0)
2240 (const_int -1)))
2241 (parallel
2242 [(set (cc0)
2243 (compare (match_dup 0)
2244 (const_int 65535)))
2245 (clobber (match_operand:QI 1 "register_operand" ""))])
2246 (set (pc)
2247 (if_then_else (ne (cc0) (const_int 0))
2248 (label_ref (match_operand 2 "" ""))
2249 (pc)))]
2250 "(test_hard_reg_class (LD_REGS, operands[0])
2251 && test_hard_reg_class (LD_REGS, operands[1]))"
2252 "*
2253 {
2254 if (test_hard_reg_class (ADDW_REGS, operands[0]))
2255 output_asm_insn (AS2 (sbiw,%0,1), operands);
2256 else
2257 output_asm_insn (AS2 (subi,%A0,1) CR_TAB
2258 AS2 (sbc,%B0,__zero_reg__) \"\\n\", operands);
2259 switch (avr_jump_mode (operands[2],insn))
2260 {
2261 case 1:
2262 return AS1 (brcc,%2);
2263 case 2:
2264 return (AS1 (brcs,_PC_+2) CR_TAB
2265 AS1 (rjmp,%2));
2266 }
2267 return (AS1 (brcs,_PC_+4) CR_TAB
2268 AS1 (jmp,%2));
2269 }")
2271 (define_peephole
2272 [(set (match_operand:QI 0 "register_operand" "")
2273 (plus:QI (match_dup 0)
2274 (const_int -1)))
2275 (set (cc0)
2276 (compare (match_dup 0)
2277 (const_int -1)))
2278 (set (pc)
2279 (if_then_else (ne (cc0) (const_int 0))
2280 (label_ref (match_operand 1 "" ""))
2281 (pc)))]
2282 "test_hard_reg_class (LD_REGS, operands[0])"
2283 "*
2284 {
2285 output_asm_insn (AS2 (subi,%A0,1), operands);
2286 switch (avr_jump_mode (operands[1],insn))
2287 {
2288 case 1:
2289 return AS1 (brcc,%1);
2290 case 2:
2291 return (AS1 (brcs,_PC_+2) CR_TAB
2292 AS1 (rjmp,%1));
2293 }
2294 return (AS1 (brcs,_PC_+4) CR_TAB
2295 AS1 (jmp,%1));
2296 }")
2298 (define_peephole
2299 [(set (cc0) (match_operand:QI 0 "register_operand" ""))
2300 (set (pc)
2301 (if_then_else (lt (cc0) (const_int 0))
2302 (label_ref (match_operand 1 "" ""))
2303 (pc)))]
2304 "jump_over_one_insn_p (insn, operands[1])"
2305 "sbrs %0,7")
2307 (define_peephole
2308 [(set (cc0) (match_operand:QI 0 "register_operand" ""))
2309 (set (pc)
2310 (if_then_else (ge (cc0) (const_int 0))
2311 (label_ref (match_operand 1 "" ""))
2312 (pc)))]
2313 "jump_over_one_insn_p (insn, operands[1])"
2314 "sbrc %0,7")
2316 (define_peephole
2317 [(set (cc0) (match_operand:HI 0 "register_operand" ""))
2318 (set (pc)
2319 (if_then_else (lt (cc0) (const_int 0))
2320 (label_ref (match_operand 1 "" ""))
2321 (pc)))]
2322 "jump_over_one_insn_p (insn, operands[1])"
2323 "sbrs %B0,7")
2325 (define_peephole
2326 [(set (cc0) (match_operand:HI 0 "register_operand" ""))
2327 (set (pc)
2328 (if_then_else (ge (cc0) (const_int 0))
2329 (label_ref (match_operand 1 "" ""))
2330 (pc)))]
2331 "jump_over_one_insn_p (insn, operands[1])"
2332 "sbrc %B0,7")
2334 (define_peephole
2335 [(set (cc0) (match_operand:SI 0 "register_operand" ""))
2336 (set (pc)
2337 (if_then_else (lt (cc0) (const_int 0))
2338 (label_ref (match_operand 1 "" ""))
2339 (pc)))]
2340 "jump_over_one_insn_p (insn, operands[1])"
2341 "sbrs %D0,7")
2343 (define_peephole
2344 [(set (cc0) (match_operand:SI 0 "register_operand" ""))
2345 (set (pc)
2346 (if_then_else (ge (cc0) (const_int 0))
2347 (label_ref (match_operand 1 "" ""))
2348 (pc)))]
2349 "jump_over_one_insn_p (insn, operands[1])"
2350 "sbrc %D0,7")
2352 (define_peephole
2353 [(set (cc0) (match_operand:QI 0 "register_operand" ""))
2354 (set (pc)
2355 (if_then_else (eq (cc0) (const_int 0))
2356 (label_ref (match_operand 1 "" ""))
2357 (pc)))]
2358 "jump_over_one_insn_p (insn, operands[1])"
2359 "cpse %0,__zero_reg__")
2361 (define_peephole
2362 [(set (cc0)
2363 (compare (match_operand:QI 0 "register_operand" "")
2364 (match_operand:QI 1 "register_operand" "")))
2365 (set (pc)
2366 (if_then_else (eq (cc0) (const_int 0))
2367 (label_ref (match_operand 2 "" ""))
2368 (pc)))]
2369 "jump_over_one_insn_p (insn, operands[2])"
2370 "cpse %0,%1")