1 /* Perform simple optimizations to clean up the result of reload.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
41 #include "dominance.h"
45 #include "cfgcleanup.h"
46 #include "basic-block.h"
50 #include "diagnostic-core.h"
54 #include "tree-pass.h"
58 static int reload_cse_noop_set_p (rtx
);
59 static bool reload_cse_simplify (rtx_insn
*, rtx
);
60 static void reload_cse_regs_1 (void);
61 static int reload_cse_simplify_set (rtx
, rtx_insn
*);
62 static int reload_cse_simplify_operands (rtx_insn
*, rtx
);
64 static void reload_combine (void);
65 static void reload_combine_note_use (rtx
*, rtx_insn
*, int, rtx
);
66 static void reload_combine_note_store (rtx
, const_rtx
, void *);
68 static bool reload_cse_move2add (rtx_insn
*);
69 static void move2add_note_store (rtx
, const_rtx
, void *);
71 /* Call cse / combine like post-reload optimization phases.
72 FIRST is the first instruction. */
75 reload_cse_regs (rtx_insn
*first ATTRIBUTE_UNUSED
)
80 moves_converted
= reload_cse_move2add (first
);
81 if (flag_expensive_optimizations
)
89 /* See whether a single set SET is a noop. */
91 reload_cse_noop_set_p (rtx set
)
93 if (cselib_reg_set_mode (SET_DEST (set
)) != GET_MODE (SET_DEST (set
)))
96 return rtx_equal_for_cselib_p (SET_DEST (set
), SET_SRC (set
));
99 /* Try to simplify INSN. Return true if the CFG may have changed. */
101 reload_cse_simplify (rtx_insn
*insn
, rtx testreg
)
103 rtx body
= PATTERN (insn
);
104 basic_block insn_bb
= BLOCK_FOR_INSN (insn
);
105 unsigned insn_bb_succs
= EDGE_COUNT (insn_bb
->succs
);
107 if (GET_CODE (body
) == SET
)
111 /* Simplify even if we may think it is a no-op.
112 We may think a memory load of a value smaller than WORD_SIZE
113 is redundant because we haven't taken into account possible
114 implicit extension. reload_cse_simplify_set() will bring
115 this out, so it's safer to simplify before we delete. */
116 count
+= reload_cse_simplify_set (body
, insn
);
118 if (!count
&& reload_cse_noop_set_p (body
))
120 rtx value
= SET_DEST (body
);
122 && ! REG_FUNCTION_VALUE_P (value
))
124 if (check_for_inc_dec (insn
))
125 delete_insn_and_edges (insn
);
126 /* We're done with this insn. */
131 apply_change_group ();
133 reload_cse_simplify_operands (insn
, testreg
);
135 else if (GET_CODE (body
) == PARALLEL
)
139 rtx value
= NULL_RTX
;
141 /* Registers mentioned in the clobber list for an asm cannot be reused
142 within the body of the asm. Invalidate those registers now so that
143 we don't try to substitute values for them. */
144 if (asm_noperands (body
) >= 0)
146 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
148 rtx part
= XVECEXP (body
, 0, i
);
149 if (GET_CODE (part
) == CLOBBER
&& REG_P (XEXP (part
, 0)))
150 cselib_invalidate_rtx (XEXP (part
, 0));
154 /* If every action in a PARALLEL is a noop, we can delete
155 the entire PARALLEL. */
156 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
158 rtx part
= XVECEXP (body
, 0, i
);
159 if (GET_CODE (part
) == SET
)
161 if (! reload_cse_noop_set_p (part
))
163 if (REG_P (SET_DEST (part
))
164 && REG_FUNCTION_VALUE_P (SET_DEST (part
)))
168 value
= SET_DEST (part
);
171 else if (GET_CODE (part
) != CLOBBER
)
177 if (check_for_inc_dec (insn
))
178 delete_insn_and_edges (insn
);
179 /* We're done with this insn. */
183 /* It's not a no-op, but we can try to simplify it. */
184 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
185 if (GET_CODE (XVECEXP (body
, 0, i
)) == SET
)
186 count
+= reload_cse_simplify_set (XVECEXP (body
, 0, i
), insn
);
189 apply_change_group ();
191 reload_cse_simplify_operands (insn
, testreg
);
195 return (EDGE_COUNT (insn_bb
->succs
) != insn_bb_succs
);
198 /* Do a very simple CSE pass over the hard registers.
200 This function detects no-op moves where we happened to assign two
201 different pseudo-registers to the same hard register, and then
202 copied one to the other. Reload will generate a useless
203 instruction copying a register to itself.
205 This function also detects cases where we load a value from memory
206 into two different registers, and (if memory is more expensive than
207 registers) changes it to simply copy the first register into the
210 Another optimization is performed that scans the operands of each
211 instruction to see whether the value is already available in a
212 hard register. It then replaces the operand with the hard register
213 if possible, much like an optional reload would. */
216 reload_cse_regs_1 (void)
218 bool cfg_changed
= false;
221 rtx testreg
= gen_rtx_REG (VOIDmode
, -1);
223 cselib_init (CSELIB_RECORD_MEMORY
);
224 init_alias_analysis ();
226 FOR_EACH_BB_FN (bb
, cfun
)
227 FOR_BB_INSNS (bb
, insn
)
230 cfg_changed
|= reload_cse_simplify (insn
, testreg
);
232 cselib_process_insn (insn
);
236 end_alias_analysis ();
242 /* Try to simplify a single SET instruction. SET is the set pattern.
243 INSN is the instruction it came from.
244 This function only handles one case: if we set a register to a value
245 which is not a register, we try to find that value in some other register
246 and change the set into a register copy. */
249 reload_cse_simplify_set (rtx set
, rtx_insn
*insn
)
257 struct elt_loc_list
*l
;
258 #ifdef LOAD_EXTEND_OP
259 enum rtx_code extend_op
= UNKNOWN
;
261 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
263 dreg
= true_regnum (SET_DEST (set
));
268 if (side_effects_p (src
) || true_regnum (src
) >= 0)
271 dclass
= REGNO_REG_CLASS (dreg
);
273 #ifdef LOAD_EXTEND_OP
274 /* When replacing a memory with a register, we need to honor assumptions
275 that combine made wrt the contents of sign bits. We'll do this by
276 generating an extend instruction instead of a reg->reg copy. Thus
277 the destination must be a register that we can widen. */
279 && GET_MODE_BITSIZE (GET_MODE (src
)) < BITS_PER_WORD
280 && (extend_op
= LOAD_EXTEND_OP (GET_MODE (src
))) != UNKNOWN
281 && !REG_P (SET_DEST (set
)))
285 val
= cselib_lookup (src
, GET_MODE (SET_DEST (set
)), 0, VOIDmode
);
289 /* If memory loads are cheaper than register copies, don't change them. */
291 old_cost
= memory_move_cost (GET_MODE (src
), dclass
, true);
292 else if (REG_P (src
))
293 old_cost
= register_move_cost (GET_MODE (src
),
294 REGNO_REG_CLASS (REGNO (src
)), dclass
);
296 old_cost
= set_src_cost (src
, speed
);
298 for (l
= val
->locs
; l
; l
= l
->next
)
300 rtx this_rtx
= l
->loc
;
303 if (CONSTANT_P (this_rtx
) && ! references_value_p (this_rtx
, 0))
305 #ifdef LOAD_EXTEND_OP
306 if (extend_op
!= UNKNOWN
)
310 if (!CONST_SCALAR_INT_P (this_rtx
))
316 result
= wide_int::from (std::make_pair (this_rtx
,
318 BITS_PER_WORD
, UNSIGNED
);
321 result
= wide_int::from (std::make_pair (this_rtx
,
323 BITS_PER_WORD
, SIGNED
);
328 this_rtx
= immed_wide_int_const (result
, word_mode
);
331 this_cost
= set_src_cost (this_rtx
, speed
);
333 else if (REG_P (this_rtx
))
335 #ifdef LOAD_EXTEND_OP
336 if (extend_op
!= UNKNOWN
)
338 this_rtx
= gen_rtx_fmt_e (extend_op
, word_mode
, this_rtx
);
339 this_cost
= set_src_cost (this_rtx
, speed
);
343 this_cost
= register_move_cost (GET_MODE (this_rtx
),
344 REGNO_REG_CLASS (REGNO (this_rtx
)),
350 /* If equal costs, prefer registers over anything else. That
351 tends to lead to smaller instructions on some machines. */
352 if (this_cost
< old_cost
353 || (this_cost
== old_cost
355 && !REG_P (SET_SRC (set
))))
357 #ifdef LOAD_EXTEND_OP
358 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set
))) < BITS_PER_WORD
359 && extend_op
!= UNKNOWN
360 #ifdef CANNOT_CHANGE_MODE_CLASS
361 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set
)),
363 REGNO_REG_CLASS (REGNO (SET_DEST (set
))))
367 rtx wide_dest
= gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
)));
368 ORIGINAL_REGNO (wide_dest
) = ORIGINAL_REGNO (SET_DEST (set
));
369 validate_change (insn
, &SET_DEST (set
), wide_dest
, 1);
373 validate_unshare_change (insn
, &SET_SRC (set
), this_rtx
, 1);
374 old_cost
= this_cost
, did_change
= 1;
381 /* Try to replace operands in INSN with equivalent values that are already
382 in registers. This can be viewed as optional reloading.
384 For each non-register operand in the insn, see if any hard regs are
385 known to be equivalent to that operand. Record the alternatives which
386 can accept these hard registers. Among all alternatives, select the
387 ones which are better or equal to the one currently matching, where
388 "better" is in terms of '?' and '!' constraints. Among the remaining
389 alternatives, select the one which replaces most operands with
393 reload_cse_simplify_operands (rtx_insn
*insn
, rtx testreg
)
397 /* For each operand, all registers that are equivalent to it. */
398 HARD_REG_SET equiv_regs
[MAX_RECOG_OPERANDS
];
400 const char *constraints
[MAX_RECOG_OPERANDS
];
402 /* Vector recording how bad an alternative is. */
403 int *alternative_reject
;
404 /* Vector recording how many registers can be introduced by choosing
406 int *alternative_nregs
;
407 /* Array of vectors recording, for each operand and each alternative,
408 which hard register to substitute, or -1 if the operand should be
410 int *op_alt_regno
[MAX_RECOG_OPERANDS
];
411 /* Array of alternatives, sorted in order of decreasing desirability. */
412 int *alternative_order
;
414 extract_constrain_insn (insn
);
416 if (recog_data
.n_alternatives
== 0 || recog_data
.n_operands
== 0)
419 alternative_reject
= XALLOCAVEC (int, recog_data
.n_alternatives
);
420 alternative_nregs
= XALLOCAVEC (int, recog_data
.n_alternatives
);
421 alternative_order
= XALLOCAVEC (int, recog_data
.n_alternatives
);
422 memset (alternative_reject
, 0, recog_data
.n_alternatives
* sizeof (int));
423 memset (alternative_nregs
, 0, recog_data
.n_alternatives
* sizeof (int));
425 /* For each operand, find out which regs are equivalent. */
426 for (i
= 0; i
< recog_data
.n_operands
; i
++)
429 struct elt_loc_list
*l
;
432 CLEAR_HARD_REG_SET (equiv_regs
[i
]);
434 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
435 right, so avoid the problem here. Likewise if we have a constant
436 and the insn pattern doesn't tell us the mode we need. */
437 if (LABEL_P (recog_data
.operand
[i
])
438 || (CONSTANT_P (recog_data
.operand
[i
])
439 && recog_data
.operand_mode
[i
] == VOIDmode
))
442 op
= recog_data
.operand
[i
];
443 #ifdef LOAD_EXTEND_OP
445 && GET_MODE_BITSIZE (GET_MODE (op
)) < BITS_PER_WORD
446 && LOAD_EXTEND_OP (GET_MODE (op
)) != UNKNOWN
)
448 rtx set
= single_set (insn
);
450 /* We might have multiple sets, some of which do implicit
451 extension. Punt on this for now. */
454 /* If the destination is also a MEM or a STRICT_LOW_PART, no
456 Also, if there is an explicit extension, we don't have to
457 worry about an implicit one. */
458 else if (MEM_P (SET_DEST (set
))
459 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
460 || GET_CODE (SET_SRC (set
)) == ZERO_EXTEND
461 || GET_CODE (SET_SRC (set
)) == SIGN_EXTEND
)
462 ; /* Continue ordinary processing. */
463 #ifdef CANNOT_CHANGE_MODE_CLASS
464 /* If the register cannot change mode to word_mode, it follows that
465 it cannot have been used in word_mode. */
466 else if (REG_P (SET_DEST (set
))
467 && CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set
)),
469 REGNO_REG_CLASS (REGNO (SET_DEST (set
)))))
470 ; /* Continue ordinary processing. */
472 /* If this is a straight load, make the extension explicit. */
473 else if (REG_P (SET_DEST (set
))
474 && recog_data
.n_operands
== 2
475 && SET_SRC (set
) == op
476 && SET_DEST (set
) == recog_data
.operand
[1-i
])
478 validate_change (insn
, recog_data
.operand_loc
[i
],
479 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (op
)),
482 validate_change (insn
, recog_data
.operand_loc
[1-i
],
483 gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
))),
485 if (! apply_change_group ())
487 return reload_cse_simplify_operands (insn
, testreg
);
490 /* ??? There might be arithmetic operations with memory that are
491 safe to optimize, but is it worth the trouble? */
494 #endif /* LOAD_EXTEND_OP */
495 if (side_effects_p (op
))
497 v
= cselib_lookup (op
, recog_data
.operand_mode
[i
], 0, VOIDmode
);
501 for (l
= v
->locs
; l
; l
= l
->next
)
503 SET_HARD_REG_BIT (equiv_regs
[i
], REGNO (l
->loc
));
506 alternative_mask preferred
= get_preferred_alternatives (insn
);
507 for (i
= 0; i
< recog_data
.n_operands
; i
++)
513 op_alt_regno
[i
] = XALLOCAVEC (int, recog_data
.n_alternatives
);
514 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
515 op_alt_regno
[i
][j
] = -1;
517 p
= constraints
[i
] = recog_data
.constraints
[i
];
518 mode
= recog_data
.operand_mode
[i
];
520 /* Add the reject values for each alternative given by the constraints
529 alternative_reject
[j
] += 3;
531 alternative_reject
[j
] += 300;
534 /* We won't change operands which are already registers. We
535 also don't want to modify output operands. */
536 regno
= true_regnum (recog_data
.operand
[i
]);
538 || constraints
[i
][0] == '='
539 || constraints
[i
][0] == '+')
542 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
544 enum reg_class rclass
= NO_REGS
;
546 if (! TEST_HARD_REG_BIT (equiv_regs
[i
], regno
))
549 SET_REGNO_RAW (testreg
, regno
);
550 PUT_MODE (testreg
, mode
);
552 /* We found a register equal to this operand. Now look for all
553 alternatives that can accept this register and have not been
554 assigned a register they can use yet. */
564 rclass
= reg_class_subunion
[rclass
][GENERAL_REGS
];
569 = (reg_class_subunion
571 [reg_class_for_constraint (lookup_constraint (p
))]);
575 /* See if REGNO fits this alternative, and set it up as the
576 replacement register if we don't have one for this
577 alternative yet and the operand being replaced is not
578 a cheap CONST_INT. */
579 if (op_alt_regno
[i
][j
] == -1
580 && TEST_BIT (preferred
, j
)
581 && reg_fits_class_p (testreg
, rclass
, 0, mode
)
582 && (!CONST_INT_P (recog_data
.operand
[i
])
583 || (set_src_cost (recog_data
.operand
[i
],
584 optimize_bb_for_speed_p
585 (BLOCK_FOR_INSN (insn
)))
586 > set_src_cost (testreg
,
587 optimize_bb_for_speed_p
588 (BLOCK_FOR_INSN (insn
))))))
590 alternative_nregs
[j
]++;
591 op_alt_regno
[i
][j
] = regno
;
597 p
+= CONSTRAINT_LEN (c
, p
);
605 /* Record all alternatives which are better or equal to the currently
606 matching one in the alternative_order array. */
607 for (i
= j
= 0; i
< recog_data
.n_alternatives
; i
++)
608 if (alternative_reject
[i
] <= alternative_reject
[which_alternative
])
609 alternative_order
[j
++] = i
;
610 recog_data
.n_alternatives
= j
;
612 /* Sort it. Given a small number of alternatives, a dumb algorithm
613 won't hurt too much. */
614 for (i
= 0; i
< recog_data
.n_alternatives
- 1; i
++)
617 int best_reject
= alternative_reject
[alternative_order
[i
]];
618 int best_nregs
= alternative_nregs
[alternative_order
[i
]];
621 for (j
= i
+ 1; j
< recog_data
.n_alternatives
; j
++)
623 int this_reject
= alternative_reject
[alternative_order
[j
]];
624 int this_nregs
= alternative_nregs
[alternative_order
[j
]];
626 if (this_reject
< best_reject
627 || (this_reject
== best_reject
&& this_nregs
> best_nregs
))
630 best_reject
= this_reject
;
631 best_nregs
= this_nregs
;
635 tmp
= alternative_order
[best
];
636 alternative_order
[best
] = alternative_order
[i
];
637 alternative_order
[i
] = tmp
;
640 /* Substitute the operands as determined by op_alt_regno for the best
642 j
= alternative_order
[0];
644 for (i
= 0; i
< recog_data
.n_operands
; i
++)
646 machine_mode mode
= recog_data
.operand_mode
[i
];
647 if (op_alt_regno
[i
][j
] == -1)
650 validate_change (insn
, recog_data
.operand_loc
[i
],
651 gen_rtx_REG (mode
, op_alt_regno
[i
][j
]), 1);
654 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
656 int op
= recog_data
.dup_num
[i
];
657 machine_mode mode
= recog_data
.operand_mode
[op
];
659 if (op_alt_regno
[op
][j
] == -1)
662 validate_change (insn
, recog_data
.dup_loc
[i
],
663 gen_rtx_REG (mode
, op_alt_regno
[op
][j
]), 1);
666 return apply_change_group ();
669 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
671 This code might also be useful when reload gave up on reg+reg addressing
672 because of clashes between the return register and INDEX_REG_CLASS. */
674 /* The maximum number of uses of a register we can keep track of to
675 replace them with reg+reg addressing. */
676 #define RELOAD_COMBINE_MAX_USES 16
678 /* Describes a recorded use of a register. */
681 /* The insn where a register has been used. */
683 /* Points to the memory reference enclosing the use, if any, NULL_RTX
686 /* Location of the register within INSN. */
688 /* The reverse uid of the insn. */
692 /* If the register is used in some unknown fashion, USE_INDEX is negative.
693 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
694 indicates where it is first set or clobbered.
695 Otherwise, USE_INDEX is the index of the last encountered use of the
696 register (which is first among these we have seen since we scan backwards).
697 USE_RUID indicates the first encountered, i.e. last, of these uses.
698 If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS
699 with a constant offset; OFFSET contains this constant in that case.
700 STORE_RUID is always meaningful if we only want to use a value in a
701 register in a different place: it denotes the next insn in the insn
702 stream (i.e. the last encountered) that sets or clobbers the register.
703 REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */
706 struct reg_use reg_use
[RELOAD_COMBINE_MAX_USES
];
712 bool all_offsets_match
;
713 } reg_state
[FIRST_PSEUDO_REGISTER
];
715 /* Reverse linear uid. This is increased in reload_combine while scanning
716 the instructions from last to first. It is used to set last_label_ruid
717 and the store_ruid / use_ruid fields in reg_state. */
718 static int reload_combine_ruid
;
720 /* The RUID of the last label we encountered in reload_combine. */
721 static int last_label_ruid
;
723 /* The RUID of the last jump we encountered in reload_combine. */
724 static int last_jump_ruid
;
726 /* The register numbers of the first and last index register. A value of
727 -1 in LAST_INDEX_REG indicates that we've previously computed these
728 values and found no suitable index registers. */
729 static int first_index_reg
= -1;
730 static int last_index_reg
;
732 #define LABEL_LIVE(LABEL) \
733 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
735 /* Subroutine of reload_combine_split_ruids, called to fix up a single
736 ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */
739 reload_combine_split_one_ruid (int *pruid
, int split_ruid
)
741 if (*pruid
> split_ruid
)
745 /* Called when we insert a new insn in a position we've already passed in
746 the scan. Examine all our state, increasing all ruids that are higher
747 than SPLIT_RUID by one in order to make room for a new insn. */
750 reload_combine_split_ruids (int split_ruid
)
754 reload_combine_split_one_ruid (&reload_combine_ruid
, split_ruid
);
755 reload_combine_split_one_ruid (&last_label_ruid
, split_ruid
);
756 reload_combine_split_one_ruid (&last_jump_ruid
, split_ruid
);
758 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
760 int j
, idx
= reg_state
[i
].use_index
;
761 reload_combine_split_one_ruid (®_state
[i
].use_ruid
, split_ruid
);
762 reload_combine_split_one_ruid (®_state
[i
].store_ruid
, split_ruid
);
763 reload_combine_split_one_ruid (®_state
[i
].real_store_ruid
,
767 for (j
= idx
; j
< RELOAD_COMBINE_MAX_USES
; j
++)
769 reload_combine_split_one_ruid (®_state
[i
].reg_use
[j
].ruid
,
775 /* Called when we are about to rescan a previously encountered insn with
776 reload_combine_note_use after modifying some part of it. This clears all
777 information about uses in that particular insn. */
780 reload_combine_purge_insn_uses (rtx_insn
*insn
)
784 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
786 int j
, k
, idx
= reg_state
[i
].use_index
;
789 j
= k
= RELOAD_COMBINE_MAX_USES
;
792 if (reg_state
[i
].reg_use
[j
].insn
!= insn
)
796 reg_state
[i
].reg_use
[k
] = reg_state
[i
].reg_use
[j
];
799 reg_state
[i
].use_index
= k
;
803 /* Called when we need to forget about all uses of REGNO after an insn
804 which is identified by RUID. */
807 reload_combine_purge_reg_uses_after_ruid (unsigned regno
, int ruid
)
809 int j
, k
, idx
= reg_state
[regno
].use_index
;
812 j
= k
= RELOAD_COMBINE_MAX_USES
;
815 if (reg_state
[regno
].reg_use
[j
].ruid
>= ruid
)
819 reg_state
[regno
].reg_use
[k
] = reg_state
[regno
].reg_use
[j
];
822 reg_state
[regno
].use_index
= k
;
825 /* Find the use of REGNO with the ruid that is highest among those
826 lower than RUID_LIMIT, and return it if it is the only use of this
827 reg in the insn. Return NULL otherwise. */
829 static struct reg_use
*
830 reload_combine_closest_single_use (unsigned regno
, int ruid_limit
)
832 int i
, best_ruid
= 0;
833 int use_idx
= reg_state
[regno
].use_index
;
834 struct reg_use
*retval
;
839 for (i
= use_idx
; i
< RELOAD_COMBINE_MAX_USES
; i
++)
841 struct reg_use
*use
= reg_state
[regno
].reg_use
+ i
;
842 int this_ruid
= use
->ruid
;
843 if (this_ruid
>= ruid_limit
)
845 if (this_ruid
> best_ruid
)
847 best_ruid
= this_ruid
;
850 else if (this_ruid
== best_ruid
)
853 if (last_label_ruid
>= best_ruid
)
858 /* After we've moved an add insn, fix up any debug insns that occur
859 between the old location of the add and the new location. REG is
860 the destination register of the add insn; REPLACEMENT is the
861 SET_SRC of the add. FROM and TO specify the range in which we
862 should make this change on debug insns. */
865 fixup_debug_insns (rtx reg
, rtx replacement
, rtx_insn
*from
, rtx_insn
*to
)
868 for (insn
= from
; insn
!= to
; insn
= NEXT_INSN (insn
))
872 if (!DEBUG_INSN_P (insn
))
875 t
= INSN_VAR_LOCATION_LOC (insn
);
876 t
= simplify_replace_rtx (t
, reg
, replacement
);
877 validate_change (insn
, &INSN_VAR_LOCATION_LOC (insn
), t
, 0);
881 /* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG
882 with SRC in the insn described by USE, taking costs into account. Return
883 true if we made the replacement. */
886 try_replace_in_use (struct reg_use
*use
, rtx reg
, rtx src
)
888 rtx_insn
*use_insn
= use
->insn
;
889 rtx mem
= use
->containing_mem
;
890 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn
));
894 addr_space_t as
= MEM_ADDR_SPACE (mem
);
895 rtx oldaddr
= XEXP (mem
, 0);
896 rtx newaddr
= NULL_RTX
;
897 int old_cost
= address_cost (oldaddr
, GET_MODE (mem
), as
, speed
);
900 newaddr
= simplify_replace_rtx (oldaddr
, reg
, src
);
901 if (memory_address_addr_space_p (GET_MODE (mem
), newaddr
, as
))
903 XEXP (mem
, 0) = newaddr
;
904 new_cost
= address_cost (newaddr
, GET_MODE (mem
), as
, speed
);
905 XEXP (mem
, 0) = oldaddr
;
906 if (new_cost
<= old_cost
907 && validate_change (use_insn
,
908 &XEXP (mem
, 0), newaddr
, 0))
914 rtx new_set
= single_set (use_insn
);
916 && REG_P (SET_DEST (new_set
))
917 && GET_CODE (SET_SRC (new_set
)) == PLUS
918 && REG_P (XEXP (SET_SRC (new_set
), 0))
919 && CONSTANT_P (XEXP (SET_SRC (new_set
), 1)))
922 int old_cost
= set_src_cost (SET_SRC (new_set
), speed
);
924 gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set
), 0), reg
));
925 new_src
= simplify_replace_rtx (SET_SRC (new_set
), reg
, src
);
927 if (set_src_cost (new_src
, speed
) <= old_cost
928 && validate_change (use_insn
, &SET_SRC (new_set
),
936 /* Called by reload_combine when scanning INSN. This function tries to detect
937 patterns where a constant is added to a register, and the result is used
939 Return true if no further processing is needed on INSN; false if it wasn't
940 recognized and should be handled normally. */
943 reload_combine_recognize_const_pattern (rtx_insn
*insn
)
945 int from_ruid
= reload_combine_ruid
;
946 rtx set
, pat
, reg
, src
, addreg
;
950 rtx_insn
*add_moved_after_insn
= NULL
;
951 int add_moved_after_ruid
= 0;
952 int clobbered_regno
= -1;
954 set
= single_set (insn
);
958 reg
= SET_DEST (set
);
961 || hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] != 1
962 || GET_MODE (reg
) != Pmode
963 || reg
== stack_pointer_rtx
)
968 /* We look for a REG1 = REG2 + CONSTANT insn, followed by either
969 uses of REG1 inside an address, or inside another add insn. If
970 possible and profitable, merge the addition into subsequent
972 if (GET_CODE (src
) != PLUS
973 || !REG_P (XEXP (src
, 0))
974 || !CONSTANT_P (XEXP (src
, 1)))
977 addreg
= XEXP (src
, 0);
978 must_move_add
= rtx_equal_p (reg
, addreg
);
980 pat
= PATTERN (insn
);
981 if (must_move_add
&& set
!= pat
)
983 /* We have to be careful when moving the add; apart from the
984 single_set there may also be clobbers. Recognize one special
985 case, that of one clobber alongside the set (likely a clobber
986 of the CC register). */
987 gcc_assert (GET_CODE (PATTERN (insn
)) == PARALLEL
);
988 if (XVECLEN (pat
, 0) != 2 || XVECEXP (pat
, 0, 0) != set
989 || GET_CODE (XVECEXP (pat
, 0, 1)) != CLOBBER
990 || !REG_P (XEXP (XVECEXP (pat
, 0, 1), 0)))
992 clobbered_regno
= REGNO (XEXP (XVECEXP (pat
, 0, 1), 0));
997 use
= reload_combine_closest_single_use (regno
, from_ruid
);
1000 /* Start the search for the next use from here. */
1001 from_ruid
= use
->ruid
;
1003 if (use
&& GET_MODE (*use
->usep
) == Pmode
)
1005 bool delete_add
= false;
1006 rtx_insn
*use_insn
= use
->insn
;
1007 int use_ruid
= use
->ruid
;
1009 /* Avoid moving the add insn past a jump. */
1010 if (must_move_add
&& use_ruid
<= last_jump_ruid
)
1013 /* If the add clobbers another hard reg in parallel, don't move
1014 it past a real set of this hard reg. */
1015 if (must_move_add
&& clobbered_regno
>= 0
1016 && reg_state
[clobbered_regno
].real_store_ruid
>= use_ruid
)
1020 /* Do not separate cc0 setter and cc0 user on HAVE_cc0 targets. */
1021 if (must_move_add
&& sets_cc0_p (PATTERN (use_insn
)))
1025 gcc_assert (reg_state
[regno
].store_ruid
<= use_ruid
);
1026 /* Avoid moving a use of ADDREG past a point where it is stored. */
1027 if (reg_state
[REGNO (addreg
)].store_ruid
> use_ruid
)
1030 /* We also must not move the addition past an insn that sets
1031 the same register, unless we can combine two add insns. */
1032 if (must_move_add
&& reg_state
[regno
].store_ruid
== use_ruid
)
1034 if (use
->containing_mem
== NULL_RTX
)
1040 if (try_replace_in_use (use
, reg
, src
))
1042 reload_combine_purge_insn_uses (use_insn
);
1043 reload_combine_note_use (&PATTERN (use_insn
), use_insn
,
1044 use_ruid
, NULL_RTX
);
1048 fixup_debug_insns (reg
, src
, insn
, use_insn
);
1054 add_moved_after_insn
= use_insn
;
1055 add_moved_after_ruid
= use_ruid
;
1060 /* If we get here, we couldn't handle this use. */
1066 if (!must_move_add
|| add_moved_after_insn
== NULL_RTX
)
1067 /* Process the add normally. */
1070 fixup_debug_insns (reg
, src
, insn
, add_moved_after_insn
);
1072 reorder_insns (insn
, insn
, add_moved_after_insn
);
1073 reload_combine_purge_reg_uses_after_ruid (regno
, add_moved_after_ruid
);
1074 reload_combine_split_ruids (add_moved_after_ruid
- 1);
1075 reload_combine_note_use (&PATTERN (insn
), insn
,
1076 add_moved_after_ruid
, NULL_RTX
);
1077 reg_state
[regno
].store_ruid
= add_moved_after_ruid
;
1082 /* Called by reload_combine when scanning INSN. Try to detect a pattern we
1083 can handle and improve. Return true if no further processing is needed on
1084 INSN; false if it wasn't recognized and should be handled normally. */
1087 reload_combine_recognize_pattern (rtx_insn
*insn
)
1092 set
= single_set (insn
);
1093 if (set
== NULL_RTX
)
1096 reg
= SET_DEST (set
);
1097 src
= SET_SRC (set
);
1099 || hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] != 1)
1102 regno
= REGNO (reg
);
1104 /* Look for (set (REGX) (CONST_INT))
1105 (set (REGX) (PLUS (REGX) (REGY)))
1107 ... (MEM (REGX)) ...
1109 (set (REGZ) (CONST_INT))
1111 ... (MEM (PLUS (REGZ) (REGY)))... .
1113 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
1114 and that we know all uses of REGX before it dies.
1115 Also, explicitly check that REGX != REGY; our life information
1116 does not yet show whether REGY changes in this insn. */
1118 if (GET_CODE (src
) == PLUS
1119 && reg_state
[regno
].all_offsets_match
1120 && last_index_reg
!= -1
1121 && REG_P (XEXP (src
, 1))
1122 && rtx_equal_p (XEXP (src
, 0), reg
)
1123 && !rtx_equal_p (XEXP (src
, 1), reg
)
1124 && reg_state
[regno
].use_index
>= 0
1125 && reg_state
[regno
].use_index
< RELOAD_COMBINE_MAX_USES
1126 && last_label_ruid
< reg_state
[regno
].use_ruid
)
1128 rtx base
= XEXP (src
, 1);
1129 rtx_insn
*prev
= prev_nonnote_nondebug_insn (insn
);
1130 rtx prev_set
= prev
? single_set (prev
) : NULL_RTX
;
1131 rtx index_reg
= NULL_RTX
;
1132 rtx reg_sum
= NULL_RTX
;
1135 /* Now we need to set INDEX_REG to an index register (denoted as
1136 REGZ in the illustration above) and REG_SUM to the expression
1137 register+register that we want to use to substitute uses of REG
1138 (typically in MEMs) with. First check REG and BASE for being
1139 index registers; we can use them even if they are not dead. */
1140 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], regno
)
1141 || TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
1149 /* Otherwise, look for a free index register. Since we have
1150 checked above that neither REG nor BASE are index registers,
1151 if we find anything at all, it will be different from these
1153 for (i
= first_index_reg
; i
<= last_index_reg
; i
++)
1155 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], i
)
1156 && reg_state
[i
].use_index
== RELOAD_COMBINE_MAX_USES
1157 && reg_state
[i
].store_ruid
<= reg_state
[regno
].use_ruid
1158 && (call_used_regs
[i
] || df_regs_ever_live_p (i
))
1159 && (!frame_pointer_needed
|| i
!= HARD_FRAME_POINTER_REGNUM
)
1160 && !fixed_regs
[i
] && !global_regs
[i
]
1161 && hard_regno_nregs
[i
][GET_MODE (reg
)] == 1
1162 && targetm
.hard_regno_scratch_ok (i
))
1164 index_reg
= gen_rtx_REG (GET_MODE (reg
), i
);
1165 reg_sum
= gen_rtx_PLUS (GET_MODE (reg
), index_reg
, base
);
1171 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
1172 (REGY), i.e. BASE, is not clobbered before the last use we'll
1176 && CONST_INT_P (SET_SRC (prev_set
))
1177 && rtx_equal_p (SET_DEST (prev_set
), reg
)
1178 && (reg_state
[REGNO (base
)].store_ruid
1179 <= reg_state
[regno
].use_ruid
))
1181 /* Change destination register and, if necessary, the constant
1182 value in PREV, the constant loading instruction. */
1183 validate_change (prev
, &SET_DEST (prev_set
), index_reg
, 1);
1184 if (reg_state
[regno
].offset
!= const0_rtx
)
1185 validate_change (prev
,
1186 &SET_SRC (prev_set
),
1187 GEN_INT (INTVAL (SET_SRC (prev_set
))
1188 + INTVAL (reg_state
[regno
].offset
)),
1191 /* Now for every use of REG that we have recorded, replace REG
1193 for (i
= reg_state
[regno
].use_index
;
1194 i
< RELOAD_COMBINE_MAX_USES
; i
++)
1195 validate_unshare_change (reg_state
[regno
].reg_use
[i
].insn
,
1196 reg_state
[regno
].reg_use
[i
].usep
,
1197 /* Each change must have its own
1201 if (apply_change_group ())
1203 struct reg_use
*lowest_ruid
= NULL
;
1205 /* For every new use of REG_SUM, we have to record the use
1206 of BASE therein, i.e. operand 1. */
1207 for (i
= reg_state
[regno
].use_index
;
1208 i
< RELOAD_COMBINE_MAX_USES
; i
++)
1210 struct reg_use
*use
= reg_state
[regno
].reg_use
+ i
;
1211 reload_combine_note_use (&XEXP (*use
->usep
, 1), use
->insn
,
1212 use
->ruid
, use
->containing_mem
);
1213 if (lowest_ruid
== NULL
|| use
->ruid
< lowest_ruid
->ruid
)
1217 fixup_debug_insns (reg
, reg_sum
, insn
, lowest_ruid
->insn
);
1219 /* Delete the reg-reg addition. */
1222 if (reg_state
[regno
].offset
!= const0_rtx
)
1223 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
1225 remove_reg_equal_equiv_notes (prev
);
1227 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
1236 reload_combine (void)
1238 rtx_insn
*insn
, *prev
;
1241 int min_labelno
, n_labels
;
1242 HARD_REG_SET ever_live_at_start
, *label_live
;
1244 /* To avoid wasting too much time later searching for an index register,
1245 determine the minimum and maximum index register numbers. */
1246 if (INDEX_REG_CLASS
== NO_REGS
)
1247 last_index_reg
= -1;
1248 else if (first_index_reg
== -1 && last_index_reg
== 0)
1250 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1251 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], r
))
1253 if (first_index_reg
== -1)
1254 first_index_reg
= r
;
1259 /* If no index register is available, we can quit now. Set LAST_INDEX_REG
1260 to -1 so we'll know to quit early the next time we get here. */
1261 if (first_index_reg
== -1)
1263 last_index_reg
= -1;
1268 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
1269 information is a bit fuzzy immediately after reload, but it's
1270 still good enough to determine which registers are live at a jump
1272 min_labelno
= get_first_label_num ();
1273 n_labels
= max_label_num () - min_labelno
;
1274 label_live
= XNEWVEC (HARD_REG_SET
, n_labels
);
1275 CLEAR_HARD_REG_SET (ever_live_at_start
);
1277 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
1279 insn
= BB_HEAD (bb
);
1283 bitmap live_in
= df_get_live_in (bb
);
1285 REG_SET_TO_HARD_REG_SET (live
, live_in
);
1286 compute_use_by_pseudos (&live
, live_in
);
1287 COPY_HARD_REG_SET (LABEL_LIVE (insn
), live
);
1288 IOR_HARD_REG_SET (ever_live_at_start
, live
);
1292 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
1293 last_label_ruid
= last_jump_ruid
= reload_combine_ruid
= 0;
1294 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1296 reg_state
[r
].store_ruid
= 0;
1297 reg_state
[r
].real_store_ruid
= 0;
1299 reg_state
[r
].use_index
= -1;
1301 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1304 for (insn
= get_last_insn (); insn
; insn
= prev
)
1306 bool control_flow_insn
;
1309 prev
= PREV_INSN (insn
);
1311 /* We cannot do our optimization across labels. Invalidating all the use
1312 information we have would be costly, so we just note where the label
1313 is and then later disable any optimization that would cross it. */
1315 last_label_ruid
= reload_combine_ruid
;
1316 else if (BARRIER_P (insn
))
1318 /* Crossing a barrier resets all the use information. */
1319 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1320 if (! fixed_regs
[r
])
1321 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1323 else if (INSN_P (insn
) && volatile_insn_p (PATTERN (insn
)))
1324 /* Optimizations across insns being marked as volatile must be
1325 prevented. All the usage information is invalidated
1327 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1329 && reg_state
[r
].use_index
!= RELOAD_COMBINE_MAX_USES
)
1330 reg_state
[r
].use_index
= -1;
1332 if (! NONDEBUG_INSN_P (insn
))
1335 reload_combine_ruid
++;
1337 control_flow_insn
= control_flow_insn_p (insn
);
1338 if (control_flow_insn
)
1339 last_jump_ruid
= reload_combine_ruid
;
1341 if (reload_combine_recognize_const_pattern (insn
)
1342 || reload_combine_recognize_pattern (insn
))
1345 note_stores (PATTERN (insn
), reload_combine_note_store
, NULL
);
1351 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1352 if (call_used_regs
[r
])
1354 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1355 reg_state
[r
].store_ruid
= reload_combine_ruid
;
1358 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
;
1359 link
= XEXP (link
, 1))
1361 rtx setuse
= XEXP (link
, 0);
1362 rtx usage_rtx
= XEXP (setuse
, 0);
1363 if ((GET_CODE (setuse
) == USE
|| GET_CODE (setuse
) == CLOBBER
)
1364 && REG_P (usage_rtx
))
1367 unsigned int start_reg
= REGNO (usage_rtx
);
1368 unsigned int num_regs
1369 = hard_regno_nregs
[start_reg
][GET_MODE (usage_rtx
)];
1370 unsigned int end_reg
= start_reg
+ num_regs
- 1;
1371 for (i
= start_reg
; i
<= end_reg
; i
++)
1372 if (GET_CODE (XEXP (link
, 0)) == CLOBBER
)
1374 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
1375 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1378 reg_state
[i
].use_index
= -1;
1383 if (control_flow_insn
&& !ANY_RETURN_P (PATTERN (insn
)))
1385 /* Non-spill registers might be used at the call destination in
1386 some unknown fashion, so we have to mark the unknown use. */
1389 if ((condjump_p (insn
) || condjump_in_parallel_p (insn
))
1390 && JUMP_LABEL (insn
))
1392 if (ANY_RETURN_P (JUMP_LABEL (insn
)))
1395 live
= &LABEL_LIVE (JUMP_LABEL (insn
));
1398 live
= &ever_live_at_start
;
1401 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1402 if (TEST_HARD_REG_BIT (*live
, r
))
1403 reg_state
[r
].use_index
= -1;
1406 reload_combine_note_use (&PATTERN (insn
), insn
, reload_combine_ruid
,
1409 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
1411 if (REG_NOTE_KIND (note
) == REG_INC
&& REG_P (XEXP (note
, 0)))
1413 int regno
= REGNO (XEXP (note
, 0));
1414 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
1415 reg_state
[regno
].real_store_ruid
= reload_combine_ruid
;
1416 reg_state
[regno
].use_index
= -1;
1424 /* Check if DST is a register or a subreg of a register; if it is,
1425 update store_ruid, real_store_ruid and use_index in the reg_state
1426 structure accordingly. Called via note_stores from reload_combine. */
1429 reload_combine_note_store (rtx dst
, const_rtx set
, void *data ATTRIBUTE_UNUSED
)
1433 machine_mode mode
= GET_MODE (dst
);
1435 if (GET_CODE (dst
) == SUBREG
)
1437 regno
= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
1438 GET_MODE (SUBREG_REG (dst
)),
1441 dst
= SUBREG_REG (dst
);
1444 /* Some targets do argument pushes without adding REG_INC notes. */
1448 dst
= XEXP (dst
, 0);
1449 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_INC
1450 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
1451 || GET_CODE (dst
) == PRE_MODIFY
|| GET_CODE (dst
) == POST_MODIFY
)
1453 regno
= REGNO (XEXP (dst
, 0));
1454 mode
= GET_MODE (XEXP (dst
, 0));
1455 for (i
= hard_regno_nregs
[regno
][mode
] - 1 + regno
; i
>= regno
; i
--)
1457 /* We could probably do better, but for now mark the register
1458 as used in an unknown fashion and set/clobbered at this
1460 reg_state
[i
].use_index
= -1;
1461 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1462 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1471 regno
+= REGNO (dst
);
1473 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
1474 careful with registers / register parts that are not full words.
1475 Similarly for ZERO_EXTRACT. */
1476 if (GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
1477 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
1479 for (i
= hard_regno_nregs
[regno
][mode
] - 1 + regno
; i
>= regno
; i
--)
1481 reg_state
[i
].use_index
= -1;
1482 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1483 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1488 for (i
= hard_regno_nregs
[regno
][mode
] - 1 + regno
; i
>= regno
; i
--)
1490 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1491 if (GET_CODE (set
) == SET
)
1492 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1493 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
1498 /* XP points to a piece of rtl that has to be checked for any uses of
1500 *XP is the pattern of INSN, or a part of it.
1501 Called from reload_combine, and recursively by itself. */
1503 reload_combine_note_use (rtx
*xp
, rtx_insn
*insn
, int ruid
, rtx containing_mem
)
1506 enum rtx_code code
= x
->code
;
1509 rtx offset
= const0_rtx
; /* For the REG case below. */
1514 if (REG_P (SET_DEST (x
)))
1516 reload_combine_note_use (&SET_SRC (x
), insn
, ruid
, NULL_RTX
);
1522 /* If this is the USE of a return value, we can't change it. */
1523 if (REG_P (XEXP (x
, 0)) && REG_FUNCTION_VALUE_P (XEXP (x
, 0)))
1525 /* Mark the return register as used in an unknown fashion. */
1526 rtx reg
= XEXP (x
, 0);
1527 int regno
= REGNO (reg
);
1528 int nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
1530 while (--nregs
>= 0)
1531 reg_state
[regno
+ nregs
].use_index
= -1;
1537 if (REG_P (SET_DEST (x
)))
1539 /* No spurious CLOBBERs of pseudo registers may remain. */
1540 gcc_assert (REGNO (SET_DEST (x
)) < FIRST_PSEUDO_REGISTER
);
1546 /* We are interested in (plus (reg) (const_int)) . */
1547 if (!REG_P (XEXP (x
, 0))
1548 || !CONST_INT_P (XEXP (x
, 1)))
1550 offset
= XEXP (x
, 1);
1555 int regno
= REGNO (x
);
1559 /* No spurious USEs of pseudo registers may remain. */
1560 gcc_assert (regno
< FIRST_PSEUDO_REGISTER
);
1562 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
1564 /* We can't substitute into multi-hard-reg uses. */
1567 while (--nregs
>= 0)
1568 reg_state
[regno
+ nregs
].use_index
= -1;
1572 /* We may be called to update uses in previously seen insns.
1573 Don't add uses beyond the last store we saw. */
1574 if (ruid
< reg_state
[regno
].store_ruid
)
1577 /* If this register is already used in some unknown fashion, we
1579 If we decrement the index from zero to -1, we can't store more
1580 uses, so this register becomes used in an unknown fashion. */
1581 use_index
= --reg_state
[regno
].use_index
;
1585 if (use_index
== RELOAD_COMBINE_MAX_USES
- 1)
1587 /* This is the first use of this register we have seen since we
1588 marked it as dead. */
1589 reg_state
[regno
].offset
= offset
;
1590 reg_state
[regno
].all_offsets_match
= true;
1591 reg_state
[regno
].use_ruid
= ruid
;
1595 if (reg_state
[regno
].use_ruid
> ruid
)
1596 reg_state
[regno
].use_ruid
= ruid
;
1598 if (! rtx_equal_p (offset
, reg_state
[regno
].offset
))
1599 reg_state
[regno
].all_offsets_match
= false;
1602 reg_state
[regno
].reg_use
[use_index
].insn
= insn
;
1603 reg_state
[regno
].reg_use
[use_index
].ruid
= ruid
;
1604 reg_state
[regno
].reg_use
[use_index
].containing_mem
= containing_mem
;
1605 reg_state
[regno
].reg_use
[use_index
].usep
= xp
;
1617 /* Recursively process the components of X. */
1618 fmt
= GET_RTX_FORMAT (code
);
1619 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1622 reload_combine_note_use (&XEXP (x
, i
), insn
, ruid
, containing_mem
);
1623 else if (fmt
[i
] == 'E')
1625 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1626 reload_combine_note_use (&XVECEXP (x
, i
, j
), insn
, ruid
,
1632 /* See if we can reduce the cost of a constant by replacing a move
1633 with an add. We track situations in which a register is set to a
1634 constant or to a register plus a constant. */
1635 /* We cannot do our optimization across labels. Invalidating all the
1636 information about register contents we have would be costly, so we
1637 use move2add_last_label_luid to note where the label is and then
1638 later disable any optimization that would cross it.
1639 reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n]
1640 are only valid if reg_set_luid[n] is greater than
1641 move2add_last_label_luid.
1642 For a set that established a new (potential) base register with
1643 non-constant value, we use move2add_luid from the place where the
1644 setting insn is encountered; registers based off that base then
1645 get the same reg_set_luid. Constants all get
1646 move2add_last_label_luid + 1 as their reg_set_luid. */
1647 static int reg_set_luid
[FIRST_PSEUDO_REGISTER
];
1649 /* If reg_base_reg[n] is negative, register n has been set to
1650 reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n].
1651 If reg_base_reg[n] is non-negative, register n has been set to the
1652 sum of reg_offset[n] and the value of register reg_base_reg[n]
1653 before reg_set_luid[n], calculated in mode reg_mode[n] .
1654 For multi-hard-register registers, all but the first one are
1655 recorded as BLKmode in reg_mode. Setting reg_mode to VOIDmode
1656 marks it as invalid. */
1657 static HOST_WIDE_INT reg_offset
[FIRST_PSEUDO_REGISTER
];
1658 static int reg_base_reg
[FIRST_PSEUDO_REGISTER
];
1659 static rtx reg_symbol_ref
[FIRST_PSEUDO_REGISTER
];
1660 static machine_mode reg_mode
[FIRST_PSEUDO_REGISTER
];
1662 /* move2add_luid is linearly increased while scanning the instructions
1663 from first to last. It is used to set reg_set_luid in
1664 reload_cse_move2add and move2add_note_store. */
1665 static int move2add_luid
;
1667 /* move2add_last_label_luid is set whenever a label is found. Labels
1668 invalidate all previously collected reg_offset data. */
1669 static int move2add_last_label_luid
;
1671 /* ??? We don't know how zero / sign extension is handled, hence we
1672 can't go from a narrower to a wider mode. */
1673 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
1674 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
1675 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
1676 && TRULY_NOOP_TRUNCATION_MODES_P (OUTMODE, INMODE)))
1678 /* Record that REG is being set to a value with the mode of REG. */
1681 move2add_record_mode (rtx reg
)
1684 machine_mode mode
= GET_MODE (reg
);
1686 if (GET_CODE (reg
) == SUBREG
)
1688 regno
= subreg_regno (reg
);
1689 nregs
= subreg_nregs (reg
);
1691 else if (REG_P (reg
))
1693 regno
= REGNO (reg
);
1694 nregs
= hard_regno_nregs
[regno
][mode
];
1698 for (int i
= nregs
- 1; i
> 0; i
--)
1699 reg_mode
[regno
+ i
] = BLKmode
;
1700 reg_mode
[regno
] = mode
;
1703 /* Record that REG is being set to the sum of SYM and OFF. */
1706 move2add_record_sym_value (rtx reg
, rtx sym
, rtx off
)
1708 int regno
= REGNO (reg
);
1710 move2add_record_mode (reg
);
1711 reg_set_luid
[regno
] = move2add_luid
;
1712 reg_base_reg
[regno
] = -1;
1713 reg_symbol_ref
[regno
] = sym
;
1714 reg_offset
[regno
] = INTVAL (off
);
1717 /* Check if REGNO contains a valid value in MODE. */
1720 move2add_valid_value_p (int regno
, machine_mode mode
)
1722 if (reg_set_luid
[regno
] <= move2add_last_label_luid
)
1725 if (mode
!= reg_mode
[regno
])
1727 if (!MODES_OK_FOR_MOVE2ADD (mode
, reg_mode
[regno
]))
1729 /* The value loaded into regno in reg_mode[regno] is also valid in
1730 mode after truncation only if (REG:mode regno) is the lowpart of
1731 (REG:reg_mode[regno] regno). Now, for big endian, the starting
1732 regno of the lowpart might be different. */
1733 int s_off
= subreg_lowpart_offset (mode
, reg_mode
[regno
]);
1734 s_off
= subreg_regno_offset (regno
, reg_mode
[regno
], s_off
, mode
);
1736 /* We could in principle adjust regno, check reg_mode[regno] to be
1737 BLKmode, and return s_off to the caller (vs. -1 for failure),
1738 but we currently have no callers that could make use of this
1743 for (int i
= hard_regno_nregs
[regno
][mode
] - 1; i
> 0; i
--)
1744 if (reg_mode
[regno
+ i
] != BLKmode
)
1749 /* This function is called with INSN that sets REG to (SYM + OFF),
1750 while REG is known to already have value (SYM + offset).
1751 This function tries to change INSN into an add instruction
1752 (set (REG) (plus (REG) (OFF - offset))) using the known value.
1753 It also updates the information about REG's known value.
1754 Return true if we made a change. */
1757 move2add_use_add2_insn (rtx reg
, rtx sym
, rtx off
, rtx_insn
*insn
)
1759 rtx pat
= PATTERN (insn
);
1760 rtx src
= SET_SRC (pat
);
1761 int regno
= REGNO (reg
);
1762 rtx new_src
= gen_int_mode (UINTVAL (off
) - reg_offset
[regno
],
1764 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
1765 bool changed
= false;
1767 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1768 use (set (reg) (reg)) instead.
1769 We don't delete this insn, nor do we convert it into a
1770 note, to avoid losing register notes or the return
1771 value flag. jump2 already knows how to get rid of
1773 if (new_src
== const0_rtx
)
1775 /* If the constants are different, this is a
1776 truncation, that, if turned into (set (reg)
1777 (reg)), would be discarded. Maybe we should
1778 try a truncMN pattern? */
1779 if (INTVAL (off
) == reg_offset
[regno
])
1780 changed
= validate_change (insn
, &SET_SRC (pat
), reg
, 0);
1784 struct full_rtx_costs oldcst
, newcst
;
1785 rtx tem
= gen_rtx_PLUS (GET_MODE (reg
), reg
, new_src
);
1787 get_full_set_rtx_cost (pat
, &oldcst
);
1788 SET_SRC (pat
) = tem
;
1789 get_full_set_rtx_cost (pat
, &newcst
);
1790 SET_SRC (pat
) = src
;
1792 if (costs_lt_p (&newcst
, &oldcst
, speed
)
1793 && have_add2_insn (reg
, new_src
))
1794 changed
= validate_change (insn
, &SET_SRC (pat
), tem
, 0);
1795 else if (sym
== NULL_RTX
&& GET_MODE (reg
) != BImode
)
1797 machine_mode narrow_mode
;
1798 for (narrow_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
1799 narrow_mode
!= VOIDmode
1800 && narrow_mode
!= GET_MODE (reg
);
1801 narrow_mode
= GET_MODE_WIDER_MODE (narrow_mode
))
1803 if (have_insn_for (STRICT_LOW_PART
, narrow_mode
)
1804 && ((reg_offset
[regno
] & ~GET_MODE_MASK (narrow_mode
))
1805 == (INTVAL (off
) & ~GET_MODE_MASK (narrow_mode
))))
1807 rtx narrow_reg
= gen_lowpart_common (narrow_mode
, reg
);
1808 rtx narrow_src
= gen_int_mode (INTVAL (off
),
1811 = gen_rtx_SET (VOIDmode
,
1812 gen_rtx_STRICT_LOW_PART (VOIDmode
,
1815 get_full_set_rtx_cost (new_set
, &newcst
);
1816 if (costs_lt_p (&newcst
, &oldcst
, speed
))
1818 changed
= validate_change (insn
, &PATTERN (insn
),
1827 move2add_record_sym_value (reg
, sym
, off
);
1832 /* This function is called with INSN that sets REG to (SYM + OFF),
1833 but REG doesn't have known value (SYM + offset). This function
1834 tries to find another register which is known to already have
1835 value (SYM + offset) and change INSN into an add instruction
1836 (set (REG) (plus (the found register) (OFF - offset))) if such
1837 a register is found. It also updates the information about
1839 Return true iff we made a change. */
1842 move2add_use_add3_insn (rtx reg
, rtx sym
, rtx off
, rtx_insn
*insn
)
1844 rtx pat
= PATTERN (insn
);
1845 rtx src
= SET_SRC (pat
);
1846 int regno
= REGNO (reg
);
1848 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
1850 bool changed
= false;
1851 struct full_rtx_costs oldcst
, newcst
, mincst
;
1854 init_costs_to_max (&mincst
);
1855 get_full_set_rtx_cost (pat
, &oldcst
);
1857 plus_expr
= gen_rtx_PLUS (GET_MODE (reg
), reg
, const0_rtx
);
1858 SET_SRC (pat
) = plus_expr
;
1860 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1861 if (move2add_valid_value_p (i
, GET_MODE (reg
))
1862 && reg_base_reg
[i
] < 0
1863 && reg_symbol_ref
[i
] != NULL_RTX
1864 && rtx_equal_p (sym
, reg_symbol_ref
[i
]))
1866 rtx new_src
= gen_int_mode (UINTVAL (off
) - reg_offset
[i
],
1868 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1869 use (set (reg) (reg)) instead.
1870 We don't delete this insn, nor do we convert it into a
1871 note, to avoid losing register notes or the return
1872 value flag. jump2 already knows how to get rid of
1874 if (new_src
== const0_rtx
)
1876 init_costs_to_zero (&mincst
);
1882 XEXP (plus_expr
, 1) = new_src
;
1883 get_full_set_rtx_cost (pat
, &newcst
);
1885 if (costs_lt_p (&newcst
, &mincst
, speed
))
1892 SET_SRC (pat
) = src
;
1894 if (costs_lt_p (&mincst
, &oldcst
, speed
))
1898 tem
= gen_rtx_REG (GET_MODE (reg
), min_regno
);
1901 rtx new_src
= gen_int_mode (UINTVAL (off
) - reg_offset
[min_regno
],
1903 tem
= gen_rtx_PLUS (GET_MODE (reg
), tem
, new_src
);
1905 if (validate_change (insn
, &SET_SRC (pat
), tem
, 0))
1908 reg_set_luid
[regno
] = move2add_luid
;
1909 move2add_record_sym_value (reg
, sym
, off
);
1913 /* Convert move insns with constant inputs to additions if they are cheaper.
1914 Return true if any changes were made. */
1916 reload_cse_move2add (rtx_insn
*first
)
1920 bool changed
= false;
1922 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
1924 reg_set_luid
[i
] = 0;
1926 reg_base_reg
[i
] = 0;
1927 reg_symbol_ref
[i
] = NULL_RTX
;
1928 reg_mode
[i
] = VOIDmode
;
1931 move2add_last_label_luid
= 0;
1933 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
), move2add_luid
++)
1939 move2add_last_label_luid
= move2add_luid
;
1940 /* We're going to increment move2add_luid twice after a
1941 label, so that we can use move2add_last_label_luid + 1 as
1942 the luid for constants. */
1946 if (! INSN_P (insn
))
1948 pat
= PATTERN (insn
);
1949 /* For simplicity, we only perform this optimization on
1950 straightforward SETs. */
1951 if (GET_CODE (pat
) == SET
1952 && REG_P (SET_DEST (pat
)))
1954 rtx reg
= SET_DEST (pat
);
1955 int regno
= REGNO (reg
);
1956 rtx src
= SET_SRC (pat
);
1958 /* Check if we have valid information on the contents of this
1959 register in the mode of REG. */
1960 if (move2add_valid_value_p (regno
, GET_MODE (reg
))
1961 && dbg_cnt (cse2_move2add
))
1963 /* Try to transform (set (REGX) (CONST_INT A))
1965 (set (REGX) (CONST_INT B))
1967 (set (REGX) (CONST_INT A))
1969 (set (REGX) (plus (REGX) (CONST_INT B-A)))
1971 (set (REGX) (CONST_INT A))
1973 (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
1976 if (CONST_INT_P (src
)
1977 && reg_base_reg
[regno
] < 0
1978 && reg_symbol_ref
[regno
] == NULL_RTX
)
1980 changed
|= move2add_use_add2_insn (reg
, NULL_RTX
, src
, insn
);
1984 /* Try to transform (set (REGX) (REGY))
1985 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1988 (set (REGX) (PLUS (REGX) (CONST_INT B)))
1991 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1993 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
1994 else if (REG_P (src
)
1995 && reg_set_luid
[regno
] == reg_set_luid
[REGNO (src
)]
1996 && reg_base_reg
[regno
] == reg_base_reg
[REGNO (src
)]
1997 && move2add_valid_value_p (REGNO (src
), GET_MODE (reg
)))
1999 rtx_insn
*next
= next_nonnote_nondebug_insn (insn
);
2002 set
= single_set (next
);
2004 && SET_DEST (set
) == reg
2005 && GET_CODE (SET_SRC (set
)) == PLUS
2006 && XEXP (SET_SRC (set
), 0) == reg
2007 && CONST_INT_P (XEXP (SET_SRC (set
), 1)))
2009 rtx src3
= XEXP (SET_SRC (set
), 1);
2010 unsigned HOST_WIDE_INT added_offset
= UINTVAL (src3
);
2011 HOST_WIDE_INT base_offset
= reg_offset
[REGNO (src
)];
2012 HOST_WIDE_INT regno_offset
= reg_offset
[regno
];
2014 gen_int_mode (added_offset
2018 bool success
= false;
2019 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
2021 if (new_src
== const0_rtx
)
2022 /* See above why we create (set (reg) (reg)) here. */
2024 = validate_change (next
, &SET_SRC (set
), reg
, 0);
2027 rtx old_src
= SET_SRC (set
);
2028 struct full_rtx_costs oldcst
, newcst
;
2029 rtx tem
= gen_rtx_PLUS (GET_MODE (reg
), reg
, new_src
);
2031 get_full_set_rtx_cost (set
, &oldcst
);
2032 SET_SRC (set
) = tem
;
2033 get_full_set_src_cost (tem
, &newcst
);
2034 SET_SRC (set
) = old_src
;
2035 costs_add_n_insns (&oldcst
, 1);
2037 if (costs_lt_p (&newcst
, &oldcst
, speed
)
2038 && have_add2_insn (reg
, new_src
))
2040 rtx newpat
= gen_rtx_SET (VOIDmode
, reg
, tem
);
2042 = validate_change (next
, &PATTERN (next
),
2050 move2add_record_mode (reg
);
2052 = trunc_int_for_mode (added_offset
+ base_offset
,
2060 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
2062 (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B))))
2064 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
2066 (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */
2067 if ((GET_CODE (src
) == SYMBOL_REF
2068 || (GET_CODE (src
) == CONST
2069 && GET_CODE (XEXP (src
, 0)) == PLUS
2070 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == SYMBOL_REF
2071 && CONST_INT_P (XEXP (XEXP (src
, 0), 1))))
2072 && dbg_cnt (cse2_move2add
))
2076 if (GET_CODE (src
) == SYMBOL_REF
)
2083 sym
= XEXP (XEXP (src
, 0), 0);
2084 off
= XEXP (XEXP (src
, 0), 1);
2087 /* If the reg already contains the value which is sum of
2088 sym and some constant value, we can use an add2 insn. */
2089 if (move2add_valid_value_p (regno
, GET_MODE (reg
))
2090 && reg_base_reg
[regno
] < 0
2091 && reg_symbol_ref
[regno
] != NULL_RTX
2092 && rtx_equal_p (sym
, reg_symbol_ref
[regno
]))
2093 changed
|= move2add_use_add2_insn (reg
, sym
, off
, insn
);
2095 /* Otherwise, we have to find a register whose value is sum
2096 of sym and some constant value. */
2098 changed
|= move2add_use_add3_insn (reg
, sym
, off
, insn
);
2104 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
2106 if (REG_NOTE_KIND (note
) == REG_INC
2107 && REG_P (XEXP (note
, 0)))
2109 /* Reset the information about this register. */
2110 int regno
= REGNO (XEXP (note
, 0));
2111 if (regno
< FIRST_PSEUDO_REGISTER
)
2113 move2add_record_mode (XEXP (note
, 0));
2114 reg_mode
[regno
] = VOIDmode
;
2118 note_stores (PATTERN (insn
), move2add_note_store
, insn
);
2120 /* If INSN is a conditional branch, we try to extract an
2121 implicit set out of it. */
2122 if (any_condjump_p (insn
))
2124 rtx cnd
= fis_get_condition (insn
);
2127 && GET_CODE (cnd
) == NE
2128 && REG_P (XEXP (cnd
, 0))
2129 && !reg_set_p (XEXP (cnd
, 0), insn
)
2130 /* The following two checks, which are also in
2131 move2add_note_store, are intended to reduce the
2132 number of calls to gen_rtx_SET to avoid memory
2133 allocation if possible. */
2134 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd
, 0)))
2135 && hard_regno_nregs
[REGNO (XEXP (cnd
, 0))][GET_MODE (XEXP (cnd
, 0))] == 1
2136 && CONST_INT_P (XEXP (cnd
, 1)))
2139 gen_rtx_SET (VOIDmode
, XEXP (cnd
, 0), XEXP (cnd
, 1));
2140 move2add_note_store (SET_DEST (implicit_set
), implicit_set
, insn
);
2144 /* If this is a CALL_INSN, all call used registers are stored with
2148 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
2150 if (call_used_regs
[i
])
2151 /* Reset the information about this register. */
2152 reg_mode
[i
] = VOIDmode
;
2159 /* SET is a SET or CLOBBER that sets DST. DATA is the insn which
2161 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
2162 Called from reload_cse_move2add via note_stores. */
2165 move2add_note_store (rtx dst
, const_rtx set
, void *data
)
2167 rtx_insn
*insn
= (rtx_insn
*) data
;
2168 unsigned int regno
= 0;
2169 machine_mode mode
= GET_MODE (dst
);
2171 /* Some targets do argument pushes without adding REG_INC notes. */
2175 dst
= XEXP (dst
, 0);
2176 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_INC
2177 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
)
2178 reg_mode
[REGNO (XEXP (dst
, 0))] = VOIDmode
;
2182 if (GET_CODE (dst
) == SUBREG
)
2183 regno
= subreg_regno (dst
);
2184 else if (REG_P (dst
))
2185 regno
= REGNO (dst
);
2189 if (SCALAR_INT_MODE_P (mode
)
2190 && GET_CODE (set
) == SET
)
2192 rtx note
, sym
= NULL_RTX
;
2195 note
= find_reg_equal_equiv_note (insn
);
2196 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
2198 sym
= XEXP (note
, 0);
2201 else if (note
&& GET_CODE (XEXP (note
, 0)) == CONST
2202 && GET_CODE (XEXP (XEXP (note
, 0), 0)) == PLUS
2203 && GET_CODE (XEXP (XEXP (XEXP (note
, 0), 0), 0)) == SYMBOL_REF
2204 && CONST_INT_P (XEXP (XEXP (XEXP (note
, 0), 0), 1)))
2206 sym
= XEXP (XEXP (XEXP (note
, 0), 0), 0);
2207 off
= XEXP (XEXP (XEXP (note
, 0), 0), 1);
2210 if (sym
!= NULL_RTX
)
2212 move2add_record_sym_value (dst
, sym
, off
);
2217 if (SCALAR_INT_MODE_P (mode
)
2218 && GET_CODE (set
) == SET
2219 && GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
2220 && GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
)
2222 rtx src
= SET_SRC (set
);
2224 unsigned HOST_WIDE_INT offset
;
2227 switch (GET_CODE (src
))
2230 if (REG_P (XEXP (src
, 0)))
2232 base_reg
= XEXP (src
, 0);
2234 if (CONST_INT_P (XEXP (src
, 1)))
2235 offset
= UINTVAL (XEXP (src
, 1));
2236 else if (REG_P (XEXP (src
, 1))
2237 && move2add_valid_value_p (REGNO (XEXP (src
, 1)), mode
))
2239 if (reg_base_reg
[REGNO (XEXP (src
, 1))] < 0
2240 && reg_symbol_ref
[REGNO (XEXP (src
, 1))] == NULL_RTX
)
2241 offset
= reg_offset
[REGNO (XEXP (src
, 1))];
2242 /* Maybe the first register is known to be a
2244 else if (move2add_valid_value_p (REGNO (base_reg
), mode
)
2245 && reg_base_reg
[REGNO (base_reg
)] < 0
2246 && reg_symbol_ref
[REGNO (base_reg
)] == NULL_RTX
)
2248 offset
= reg_offset
[REGNO (base_reg
)];
2249 base_reg
= XEXP (src
, 1);
2268 /* Start tracking the register as a constant. */
2269 reg_base_reg
[regno
] = -1;
2270 reg_symbol_ref
[regno
] = NULL_RTX
;
2271 reg_offset
[regno
] = INTVAL (SET_SRC (set
));
2272 /* We assign the same luid to all registers set to constants. */
2273 reg_set_luid
[regno
] = move2add_last_label_luid
+ 1;
2274 move2add_record_mode (dst
);
2281 base_regno
= REGNO (base_reg
);
2282 /* If information about the base register is not valid, set it
2283 up as a new base register, pretending its value is known
2284 starting from the current insn. */
2285 if (!move2add_valid_value_p (base_regno
, mode
))
2287 reg_base_reg
[base_regno
] = base_regno
;
2288 reg_symbol_ref
[base_regno
] = NULL_RTX
;
2289 reg_offset
[base_regno
] = 0;
2290 reg_set_luid
[base_regno
] = move2add_luid
;
2291 gcc_assert (GET_MODE (base_reg
) == mode
);
2292 move2add_record_mode (base_reg
);
2295 /* Copy base information from our base register. */
2296 reg_set_luid
[regno
] = reg_set_luid
[base_regno
];
2297 reg_base_reg
[regno
] = reg_base_reg
[base_regno
];
2298 reg_symbol_ref
[regno
] = reg_symbol_ref
[base_regno
];
2300 /* Compute the sum of the offsets or constants. */
2302 = trunc_int_for_mode (offset
+ reg_offset
[base_regno
], mode
);
2304 move2add_record_mode (dst
);
2309 /* Invalidate the contents of the register. */
2310 move2add_record_mode (dst
);
2311 reg_mode
[regno
] = VOIDmode
;
2317 const pass_data pass_data_postreload_cse
=
2319 RTL_PASS
, /* type */
2320 "postreload", /* name */
2321 OPTGROUP_NONE
, /* optinfo_flags */
2322 TV_RELOAD_CSE_REGS
, /* tv_id */
2323 0, /* properties_required */
2324 0, /* properties_provided */
2325 0, /* properties_destroyed */
2326 0, /* todo_flags_start */
2327 TODO_df_finish
, /* todo_flags_finish */
2330 class pass_postreload_cse
: public rtl_opt_pass
2333 pass_postreload_cse (gcc::context
*ctxt
)
2334 : rtl_opt_pass (pass_data_postreload_cse
, ctxt
)
2337 /* opt_pass methods: */
2338 virtual bool gate (function
*) { return (optimize
> 0 && reload_completed
); }
2340 virtual unsigned int execute (function
*);
2342 }; // class pass_postreload_cse
2345 pass_postreload_cse::execute (function
*fun
)
2347 if (!dbg_cnt (postreload_cse
))
2350 /* Do a very simple CSE pass over just the hard registers. */
2351 reload_cse_regs (get_insns ());
2352 /* Reload_cse_regs can eliminate potentially-trapping MEMs.
2353 Remove any EH edges associated with them. */
2354 if (fun
->can_throw_non_call_exceptions
2355 && purge_all_dead_edges ())
2364 make_pass_postreload_cse (gcc::context
*ctxt
)
2366 return new pass_postreload_cse (ctxt
);