Daily bump.
[official-gcc.git] / gcc / regclass.c
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1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
11 version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
23 /* This file contains two passes of the compiler: reg_scan and reg_class.
24 It also defines some tables of information about the hardware registers
25 and a function init_reg_sets to initialize the tables. */
27 #include "config.h"
28 #include "system.h"
29 #include "coretypes.h"
30 #include "tm.h"
31 #include "hard-reg-set.h"
32 #include "rtl.h"
33 #include "expr.h"
34 #include "tm_p.h"
35 #include "flags.h"
36 #include "basic-block.h"
37 #include "regs.h"
38 #include "addresses.h"
39 #include "function.h"
40 #include "insn-config.h"
41 #include "recog.h"
42 #include "reload.h"
43 #include "real.h"
44 #include "toplev.h"
45 #include "output.h"
46 #include "ggc.h"
47 #include "timevar.h"
48 #include "hashtab.h"
49 #include "target.h"
50 #include "tree-pass.h"
51 #include "df.h"
53 /* Maximum register number used in this function, plus one. */
55 int max_regno;
57 static void init_reg_sets_1 (void);
58 static void init_reg_autoinc (void);
60 /* If we have auto-increment or auto-decrement and we can have secondary
61 reloads, we are not allowed to use classes requiring secondary
62 reloads for pseudos auto-incremented since reload can't handle it. */
63 /* We leave it to target hooks to decide if we have secondary reloads, so
64 assume that we might have them. */
65 #if defined(AUTO_INC_DEC) /* */
66 #define FORBIDDEN_INC_DEC_CLASSES
67 #endif
69 /* Register tables used by many passes. */
71 /* Indexed by hard register number, contains 1 for registers
72 that are fixed use (stack pointer, pc, frame pointer, etc.).
73 These are the registers that cannot be used to allocate
74 a pseudo reg for general use. */
76 char fixed_regs[FIRST_PSEUDO_REGISTER];
78 /* Same info as a HARD_REG_SET. */
80 HARD_REG_SET fixed_reg_set;
82 /* Data for initializing the above. */
84 static const char initial_fixed_regs[] = FIXED_REGISTERS;
86 /* Indexed by hard register number, contains 1 for registers
87 that are fixed use or are clobbered by function calls.
88 These are the registers that cannot be used to allocate
89 a pseudo reg whose life crosses calls unless we are able
90 to save/restore them across the calls. */
92 char call_used_regs[FIRST_PSEUDO_REGISTER];
94 /* Same info as a HARD_REG_SET. */
96 HARD_REG_SET call_used_reg_set;
98 /* HARD_REG_SET of registers we want to avoid caller saving. */
99 HARD_REG_SET losing_caller_save_reg_set;
101 /* Data for initializing the above. */
103 static const char initial_call_used_regs[] = CALL_USED_REGISTERS;
105 /* This is much like call_used_regs, except it doesn't have to
106 be a superset of FIXED_REGISTERS. This vector indicates
107 what is really call clobbered, and is used when defining
108 regs_invalidated_by_call. */
110 #ifdef CALL_REALLY_USED_REGISTERS
111 char call_really_used_regs[] = CALL_REALLY_USED_REGISTERS;
112 #endif
114 #ifdef CALL_REALLY_USED_REGISTERS
115 #define CALL_REALLY_USED_REGNO_P(X) call_really_used_regs[X]
116 #else
117 #define CALL_REALLY_USED_REGNO_P(X) call_used_regs[X]
118 #endif
121 /* Indexed by hard register number, contains 1 for registers that are
122 fixed use or call used registers that cannot hold quantities across
123 calls even if we are willing to save and restore them. call fixed
124 registers are a subset of call used registers. */
126 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
128 /* The same info as a HARD_REG_SET. */
130 HARD_REG_SET call_fixed_reg_set;
132 /* Indexed by hard register number, contains 1 for registers
133 that are being used for global register decls.
134 These must be exempt from ordinary flow analysis
135 and are also considered fixed. */
137 char global_regs[FIRST_PSEUDO_REGISTER];
139 /* Contains 1 for registers that are set or clobbered by calls. */
140 /* ??? Ideally, this would be just call_used_regs plus global_regs, but
141 for someone's bright idea to have call_used_regs strictly include
142 fixed_regs. Which leaves us guessing as to the set of fixed_regs
143 that are actually preserved. We know for sure that those associated
144 with the local stack frame are safe, but scant others. */
146 HARD_REG_SET regs_invalidated_by_call;
148 /* Table of register numbers in the order in which to try to use them. */
149 #ifdef REG_ALLOC_ORDER
150 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
152 /* The inverse of reg_alloc_order. */
153 int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
154 #endif
156 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
158 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
160 /* The same information, but as an array of unsigned ints. We copy from
161 these unsigned ints to the table above. We do this so the tm.h files
162 do not have to be aware of the wordsize for machines with <= 64 regs.
163 Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
165 #define N_REG_INTS \
166 ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32)
168 static const unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
169 = REG_CLASS_CONTENTS;
171 /* For each reg class, number of regs it contains. */
173 unsigned int reg_class_size[N_REG_CLASSES];
175 /* For each reg class, table listing all the containing classes. */
177 static enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
179 /* For each reg class, table listing all the classes contained in it. */
181 static enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
183 /* For each pair of reg classes,
184 a largest reg class contained in their union. */
186 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
188 /* For each pair of reg classes,
189 the smallest reg class containing their union. */
191 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
193 /* Array containing all of the register names. */
195 const char * reg_names[] = REGISTER_NAMES;
197 /* Array containing all of the register class names. */
199 const char * reg_class_names[] = REG_CLASS_NAMES;
201 /* For each hard register, the widest mode object that it can contain.
202 This will be a MODE_INT mode if the register can hold integers. Otherwise
203 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
204 register. */
206 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
208 /* 1 if there is a register of given mode. */
210 bool have_regs_of_mode [MAX_MACHINE_MODE];
212 /* 1 if class does contain register of given mode. */
214 static char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE];
216 typedef unsigned short move_table[N_REG_CLASSES];
218 /* Maximum cost of moving from a register in one class to a register in
219 another class. Based on REGISTER_MOVE_COST. */
221 static move_table *move_cost[MAX_MACHINE_MODE];
223 /* Similar, but here we don't have to move if the first index is a subset
224 of the second so in that case the cost is zero. */
226 static move_table *may_move_in_cost[MAX_MACHINE_MODE];
228 /* Similar, but here we don't have to move if the first index is a superset
229 of the second so in that case the cost is zero. */
231 static move_table *may_move_out_cost[MAX_MACHINE_MODE];
233 /* Keep track of the last mode we initialized move costs for. */
234 static int last_mode_for_init_move_cost;
236 #ifdef FORBIDDEN_INC_DEC_CLASSES
238 /* These are the classes that regs which are auto-incremented or decremented
239 cannot be put in. */
241 static int forbidden_inc_dec_class[N_REG_CLASSES];
243 /* Indexed by n, is nonzero if (REG n) is used in an auto-inc or auto-dec
244 context. */
246 static char *in_inc_dec;
248 #endif /* FORBIDDEN_INC_DEC_CLASSES */
250 /* Sample MEM values for use by memory_move_secondary_cost. */
252 static GTY(()) rtx top_of_stack[MAX_MACHINE_MODE];
254 /* No more global register variables may be declared; true once
255 regclass has been initialized. */
257 static int no_global_reg_vars = 0;
259 /* Specify number of hard registers given machine mode occupy. */
260 unsigned char hard_regno_nregs[FIRST_PSEUDO_REGISTER][MAX_MACHINE_MODE];
262 /* Given a register bitmap, turn on the bits in a HARD_REG_SET that
263 correspond to the hard registers, if any, set in that map. This
264 could be done far more efficiently by having all sorts of special-cases
265 with moving single words, but probably isn't worth the trouble. */
267 void
268 reg_set_to_hard_reg_set (HARD_REG_SET *to, const_bitmap from)
270 unsigned i;
271 bitmap_iterator bi;
273 EXECUTE_IF_SET_IN_BITMAP (from, 0, i, bi)
275 if (i >= FIRST_PSEUDO_REGISTER)
276 return;
277 SET_HARD_REG_BIT (*to, i);
282 /* Function called only once to initialize the above data on reg usage.
283 Once this is done, various switches may override. */
285 void
286 init_reg_sets (void)
288 int i, j;
290 /* First copy the register information from the initial int form into
291 the regsets. */
293 for (i = 0; i < N_REG_CLASSES; i++)
295 CLEAR_HARD_REG_SET (reg_class_contents[i]);
297 /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */
298 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
299 if (int_reg_class_contents[i][j / 32]
300 & ((unsigned) 1 << (j % 32)))
301 SET_HARD_REG_BIT (reg_class_contents[i], j);
304 /* Sanity check: make sure the target macros FIXED_REGISTERS and
305 CALL_USED_REGISTERS had the right number of initializers. */
306 gcc_assert (sizeof fixed_regs == sizeof initial_fixed_regs);
307 gcc_assert (sizeof call_used_regs == sizeof initial_call_used_regs);
309 memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs);
310 memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs);
311 memset (global_regs, 0, sizeof global_regs);
314 /* Initialize may_move_cost and friends for mode M. */
316 static void
317 init_move_cost (enum machine_mode m)
319 static unsigned short last_move_cost[N_REG_CLASSES][N_REG_CLASSES];
320 bool all_match = true;
321 unsigned int i, j;
323 gcc_assert (have_regs_of_mode[m]);
324 for (i = 0; i < N_REG_CLASSES; i++)
325 if (contains_reg_of_mode[i][m])
326 for (j = 0; j < N_REG_CLASSES; j++)
328 int cost;
329 if (!contains_reg_of_mode[j][m])
330 cost = 65535;
331 else
333 cost = REGISTER_MOVE_COST (m, i, j);
334 gcc_assert (cost < 65535);
336 all_match &= (last_move_cost[i][j] == cost);
337 last_move_cost[i][j] = cost;
339 if (all_match && last_mode_for_init_move_cost != -1)
341 move_cost[m] = move_cost[last_mode_for_init_move_cost];
342 may_move_in_cost[m] = may_move_in_cost[last_mode_for_init_move_cost];
343 may_move_out_cost[m] = may_move_out_cost[last_mode_for_init_move_cost];
344 return;
346 last_mode_for_init_move_cost = m;
347 move_cost[m] = (move_table *)xmalloc (sizeof (move_table)
348 * N_REG_CLASSES);
349 may_move_in_cost[m] = (move_table *)xmalloc (sizeof (move_table)
350 * N_REG_CLASSES);
351 may_move_out_cost[m] = (move_table *)xmalloc (sizeof (move_table)
352 * N_REG_CLASSES);
353 for (i = 0; i < N_REG_CLASSES; i++)
354 if (contains_reg_of_mode[i][m])
355 for (j = 0; j < N_REG_CLASSES; j++)
357 int cost;
358 enum reg_class *p1, *p2;
360 if (last_move_cost[i][j] == 65535)
362 move_cost[m][i][j] = 65535;
363 may_move_in_cost[m][i][j] = 65535;
364 may_move_out_cost[m][i][j] = 65535;
366 else
368 cost = last_move_cost[i][j];
370 for (p2 = &reg_class_subclasses[j][0];
371 *p2 != LIM_REG_CLASSES; p2++)
372 if (*p2 != i && contains_reg_of_mode[*p2][m])
373 cost = MAX (cost, move_cost[m][i][*p2]);
375 for (p1 = &reg_class_subclasses[i][0];
376 *p1 != LIM_REG_CLASSES; p1++)
377 if (*p1 != j && contains_reg_of_mode[*p1][m])
378 cost = MAX (cost, move_cost[m][*p1][j]);
380 gcc_assert (cost <= 65535);
381 move_cost[m][i][j] = cost;
383 if (reg_class_subset_p (i, j))
384 may_move_in_cost[m][i][j] = 0;
385 else
386 may_move_in_cost[m][i][j] = cost;
388 if (reg_class_subset_p (j, i))
389 may_move_out_cost[m][i][j] = 0;
390 else
391 may_move_out_cost[m][i][j] = cost;
394 else
395 for (j = 0; j < N_REG_CLASSES; j++)
397 move_cost[m][i][j] = 65535;
398 may_move_in_cost[m][i][j] = 65535;
399 may_move_out_cost[m][i][j] = 65535;
403 /* We need to save copies of some of the register information which
404 can be munged by command-line switches so we can restore it during
405 subsequent back-end reinitialization. */
407 static char saved_fixed_regs[FIRST_PSEUDO_REGISTER];
408 static char saved_call_used_regs[FIRST_PSEUDO_REGISTER];
409 #ifdef CALL_REALLY_USED_REGISTERS
410 static char saved_call_really_used_regs[FIRST_PSEUDO_REGISTER];
411 #endif
412 static const char *saved_reg_names[FIRST_PSEUDO_REGISTER];
414 /* Save the register information. */
416 void
417 save_register_info (void)
419 /* Sanity check: make sure the target macros FIXED_REGISTERS and
420 CALL_USED_REGISTERS had the right number of initializers. */
421 gcc_assert (sizeof fixed_regs == sizeof saved_fixed_regs);
422 gcc_assert (sizeof call_used_regs == sizeof saved_call_used_regs);
423 memcpy (saved_fixed_regs, fixed_regs, sizeof fixed_regs);
424 memcpy (saved_call_used_regs, call_used_regs, sizeof call_used_regs);
426 /* Likewise for call_really_used_regs. */
427 #ifdef CALL_REALLY_USED_REGISTERS
428 gcc_assert (sizeof call_really_used_regs
429 == sizeof saved_call_really_used_regs);
430 memcpy (saved_call_really_used_regs, call_really_used_regs,
431 sizeof call_really_used_regs);
432 #endif
434 /* And similarly for reg_names. */
435 gcc_assert (sizeof reg_names == sizeof saved_reg_names);
436 memcpy (saved_reg_names, reg_names, sizeof reg_names);
439 /* Restore the register information. */
441 static void
442 restore_register_info (void)
444 memcpy (fixed_regs, saved_fixed_regs, sizeof fixed_regs);
445 memcpy (call_used_regs, saved_call_used_regs, sizeof call_used_regs);
447 #ifdef CALL_REALLY_USED_REGISTERS
448 memcpy (call_really_used_regs, saved_call_really_used_regs,
449 sizeof call_really_used_regs);
450 #endif
452 memcpy (reg_names, saved_reg_names, sizeof reg_names);
455 /* After switches have been processed, which perhaps alter
456 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
458 static void
459 init_reg_sets_1 (void)
461 unsigned int i, j;
462 unsigned int /* enum machine_mode */ m;
464 restore_register_info ();
466 #ifdef REG_ALLOC_ORDER
467 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
468 inv_reg_alloc_order[reg_alloc_order[i]] = i;
469 #endif
471 /* This macro allows the fixed or call-used registers
472 and the register classes to depend on target flags. */
474 #ifdef CONDITIONAL_REGISTER_USAGE
475 CONDITIONAL_REGISTER_USAGE;
476 #endif
478 /* Compute number of hard regs in each class. */
480 memset (reg_class_size, 0, sizeof reg_class_size);
481 for (i = 0; i < N_REG_CLASSES; i++)
482 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
483 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
484 reg_class_size[i]++;
486 /* Initialize the table of subunions.
487 reg_class_subunion[I][J] gets the largest-numbered reg-class
488 that is contained in the union of classes I and J. */
490 memset (reg_class_subunion, 0, sizeof reg_class_subunion);
491 for (i = 0; i < N_REG_CLASSES; i++)
493 for (j = 0; j < N_REG_CLASSES; j++)
495 HARD_REG_SET c;
496 int k;
498 COPY_HARD_REG_SET (c, reg_class_contents[i]);
499 IOR_HARD_REG_SET (c, reg_class_contents[j]);
500 for (k = 0; k < N_REG_CLASSES; k++)
501 if (hard_reg_set_subset_p (reg_class_contents[k], c)
502 && !hard_reg_set_subset_p (reg_class_contents[k],
503 reg_class_contents
504 [(int) reg_class_subunion[i][j]]))
505 reg_class_subunion[i][j] = (enum reg_class) k;
509 /* Initialize the table of superunions.
510 reg_class_superunion[I][J] gets the smallest-numbered reg-class
511 containing the union of classes I and J. */
513 memset (reg_class_superunion, 0, sizeof reg_class_superunion);
514 for (i = 0; i < N_REG_CLASSES; i++)
516 for (j = 0; j < N_REG_CLASSES; j++)
518 HARD_REG_SET c;
519 int k;
521 COPY_HARD_REG_SET (c, reg_class_contents[i]);
522 IOR_HARD_REG_SET (c, reg_class_contents[j]);
523 for (k = 0; k < N_REG_CLASSES; k++)
524 if (hard_reg_set_subset_p (c, reg_class_contents[k]))
525 break;
527 reg_class_superunion[i][j] = (enum reg_class) k;
531 /* Initialize the tables of subclasses and superclasses of each reg class.
532 First clear the whole table, then add the elements as they are found. */
534 for (i = 0; i < N_REG_CLASSES; i++)
536 for (j = 0; j < N_REG_CLASSES; j++)
538 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
539 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
543 for (i = 0; i < N_REG_CLASSES; i++)
545 if (i == (int) NO_REGS)
546 continue;
548 for (j = i + 1; j < N_REG_CLASSES; j++)
549 if (hard_reg_set_subset_p (reg_class_contents[i],
550 reg_class_contents[j]))
552 /* Reg class I is a subclass of J.
553 Add J to the table of superclasses of I. */
554 enum reg_class *p;
556 p = &reg_class_superclasses[i][0];
557 while (*p != LIM_REG_CLASSES) p++;
558 *p = (enum reg_class) j;
559 /* Add I to the table of superclasses of J. */
560 p = &reg_class_subclasses[j][0];
561 while (*p != LIM_REG_CLASSES) p++;
562 *p = (enum reg_class) i;
566 /* Initialize "constant" tables. */
568 CLEAR_HARD_REG_SET (fixed_reg_set);
569 CLEAR_HARD_REG_SET (call_used_reg_set);
570 CLEAR_HARD_REG_SET (call_fixed_reg_set);
571 CLEAR_HARD_REG_SET (regs_invalidated_by_call);
572 CLEAR_HARD_REG_SET (losing_caller_save_reg_set);
574 memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs);
576 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
578 /* call_used_regs must include fixed_regs. */
579 gcc_assert (!fixed_regs[i] || call_used_regs[i]);
580 #ifdef CALL_REALLY_USED_REGISTERS
581 /* call_used_regs must include call_really_used_regs. */
582 gcc_assert (!call_really_used_regs[i] || call_used_regs[i]);
583 #endif
585 if (fixed_regs[i])
586 SET_HARD_REG_BIT (fixed_reg_set, i);
588 if (call_used_regs[i])
589 SET_HARD_REG_BIT (call_used_reg_set, i);
590 if (call_fixed_regs[i])
591 SET_HARD_REG_BIT (call_fixed_reg_set, i);
592 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
593 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
595 /* There are a couple of fixed registers that we know are safe to
596 exclude from being clobbered by calls:
598 The frame pointer is always preserved across calls. The arg pointer
599 is if it is fixed. The stack pointer usually is, unless
600 RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present.
601 If we are generating PIC code, the PIC offset table register is
602 preserved across calls, though the target can override that. */
604 if (i == STACK_POINTER_REGNUM)
606 else if (global_regs[i])
607 SET_HARD_REG_BIT (regs_invalidated_by_call, i);
608 else if (i == FRAME_POINTER_REGNUM)
610 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
611 else if (i == HARD_FRAME_POINTER_REGNUM)
613 #endif
614 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
615 else if (i == ARG_POINTER_REGNUM && fixed_regs[i])
617 #endif
618 #ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
619 else if (i == (unsigned) PIC_OFFSET_TABLE_REGNUM && fixed_regs[i])
621 #endif
622 else if (CALL_REALLY_USED_REGNO_P (i))
623 SET_HARD_REG_BIT (regs_invalidated_by_call, i);
626 /* Preserve global registers if called more than once. */
627 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
629 if (global_regs[i])
631 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
632 SET_HARD_REG_BIT (fixed_reg_set, i);
633 SET_HARD_REG_BIT (call_used_reg_set, i);
634 SET_HARD_REG_BIT (call_fixed_reg_set, i);
638 memset (have_regs_of_mode, 0, sizeof (have_regs_of_mode));
639 memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode));
640 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++)
642 HARD_REG_SET ok_regs;
643 CLEAR_HARD_REG_SET (ok_regs);
644 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
645 if (!fixed_regs [j] && HARD_REGNO_MODE_OK (j, m))
646 SET_HARD_REG_BIT (ok_regs, j);
648 for (i = 0; i < N_REG_CLASSES; i++)
649 if ((unsigned) CLASS_MAX_NREGS (i, m) <= reg_class_size[i]
650 && hard_reg_set_intersect_p (ok_regs, reg_class_contents[i]))
652 contains_reg_of_mode [i][m] = 1;
653 have_regs_of_mode [m] = 1;
657 /* Reset move_cost and friends, making sure we only free shared
658 table entries once. */
659 for (i = 0; i < MAX_MACHINE_MODE; i++)
660 if (move_cost[i])
662 for (j = 0; j < i && move_cost[i] != move_cost[j]; j++)
664 if (i == j)
666 free (move_cost[i]);
667 free (may_move_in_cost[i]);
668 free (may_move_out_cost[i]);
671 memset (move_cost, 0, sizeof move_cost);
672 memset (may_move_in_cost, 0, sizeof may_move_in_cost);
673 memset (may_move_out_cost, 0, sizeof may_move_out_cost);
674 last_mode_for_init_move_cost = -1;
677 /* Compute the table of register modes.
678 These values are used to record death information for individual registers
679 (as opposed to a multi-register mode).
680 This function might be invoked more than once, if the target has support
681 for changing register usage conventions on a per-function basis.
684 void
685 init_reg_modes_target (void)
687 int i, j;
689 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
690 for (j = 0; j < MAX_MACHINE_MODE; j++)
691 hard_regno_nregs[i][j] = HARD_REGNO_NREGS(i, (enum machine_mode)j);
693 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
695 reg_raw_mode[i] = choose_hard_reg_mode (i, 1, false);
697 /* If we couldn't find a valid mode, just use the previous mode.
698 ??? One situation in which we need to do this is on the mips where
699 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
700 to use DF mode for the even registers and VOIDmode for the odd
701 (for the cpu models where the odd ones are inaccessible). */
702 if (reg_raw_mode[i] == VOIDmode)
703 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
707 /* Finish initializing the register sets and initialize the register modes.
708 This function might be invoked more than once, if the target has support
709 for changing register usage conventions on a per-function basis.
712 void
713 init_regs (void)
715 /* This finishes what was started by init_reg_sets, but couldn't be done
716 until after register usage was specified. */
717 init_reg_sets_1 ();
719 init_reg_autoinc ();
722 /* Initialize some fake stack-frame MEM references for use in
723 memory_move_secondary_cost. */
725 void
726 init_fake_stack_mems (void)
729 int i;
731 for (i = 0; i < MAX_MACHINE_MODE; i++)
732 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
737 /* Compute extra cost of moving registers to/from memory due to reloads.
738 Only needed if secondary reloads are required for memory moves. */
741 memory_move_secondary_cost (enum machine_mode mode, enum reg_class class, int in)
743 enum reg_class altclass;
744 int partial_cost = 0;
745 /* We need a memory reference to feed to SECONDARY... macros. */
746 /* mem may be unused even if the SECONDARY_ macros are defined. */
747 rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode];
750 altclass = secondary_reload_class (in ? 1 : 0, class, mode, mem);
752 if (altclass == NO_REGS)
753 return 0;
755 if (in)
756 partial_cost = REGISTER_MOVE_COST (mode, altclass, class);
757 else
758 partial_cost = REGISTER_MOVE_COST (mode, class, altclass);
760 if (class == altclass)
761 /* This isn't simply a copy-to-temporary situation. Can't guess
762 what it is, so MEMORY_MOVE_COST really ought not to be calling
763 here in that case.
765 I'm tempted to put in an assert here, but returning this will
766 probably only give poor estimates, which is what we would've
767 had before this code anyways. */
768 return partial_cost;
770 /* Check if the secondary reload register will also need a
771 secondary reload. */
772 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
775 /* Return a machine mode that is legitimate for hard reg REGNO and large
776 enough to save nregs. If we can't find one, return VOIDmode.
777 If CALL_SAVED is true, only consider modes that are call saved. */
779 enum machine_mode
780 choose_hard_reg_mode (unsigned int regno ATTRIBUTE_UNUSED,
781 unsigned int nregs, bool call_saved)
783 unsigned int /* enum machine_mode */ m;
784 enum machine_mode found_mode = VOIDmode, mode;
786 /* We first look for the largest integer mode that can be validly
787 held in REGNO. If none, we look for the largest floating-point mode.
788 If we still didn't find a valid mode, try CCmode. */
790 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
791 mode != VOIDmode;
792 mode = GET_MODE_WIDER_MODE (mode))
793 if ((unsigned) hard_regno_nregs[regno][mode] == nregs
794 && HARD_REGNO_MODE_OK (regno, mode)
795 && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
796 found_mode = mode;
798 if (found_mode != VOIDmode)
799 return found_mode;
801 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
802 mode != VOIDmode;
803 mode = GET_MODE_WIDER_MODE (mode))
804 if ((unsigned) hard_regno_nregs[regno][mode] == nregs
805 && HARD_REGNO_MODE_OK (regno, mode)
806 && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
807 found_mode = mode;
809 if (found_mode != VOIDmode)
810 return found_mode;
812 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT);
813 mode != VOIDmode;
814 mode = GET_MODE_WIDER_MODE (mode))
815 if ((unsigned) hard_regno_nregs[regno][mode] == nregs
816 && HARD_REGNO_MODE_OK (regno, mode)
817 && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
818 found_mode = mode;
820 if (found_mode != VOIDmode)
821 return found_mode;
823 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT);
824 mode != VOIDmode;
825 mode = GET_MODE_WIDER_MODE (mode))
826 if ((unsigned) hard_regno_nregs[regno][mode] == nregs
827 && HARD_REGNO_MODE_OK (regno, mode)
828 && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
829 found_mode = mode;
831 if (found_mode != VOIDmode)
832 return found_mode;
834 /* Iterate over all of the CCmodes. */
835 for (m = (unsigned int) CCmode; m < (unsigned int) NUM_MACHINE_MODES; ++m)
837 mode = (enum machine_mode) m;
838 if ((unsigned) hard_regno_nregs[regno][mode] == nregs
839 && HARD_REGNO_MODE_OK (regno, mode)
840 && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
841 return mode;
844 /* We can't find a mode valid for this register. */
845 return VOIDmode;
848 /* Specify the usage characteristics of the register named NAME.
849 It should be a fixed register if FIXED and a
850 call-used register if CALL_USED. */
852 void
853 fix_register (const char *name, int fixed, int call_used)
855 int i;
857 /* Decode the name and update the primary form of
858 the register info. */
860 if ((i = decode_reg_name (name)) >= 0)
862 if ((i == STACK_POINTER_REGNUM
863 #ifdef HARD_FRAME_POINTER_REGNUM
864 || i == HARD_FRAME_POINTER_REGNUM
865 #else
866 || i == FRAME_POINTER_REGNUM
867 #endif
869 && (fixed == 0 || call_used == 0))
871 static const char * const what_option[2][2] = {
872 { "call-saved", "call-used" },
873 { "no-such-option", "fixed" }};
875 error ("can't use '%s' as a %s register", name,
876 what_option[fixed][call_used]);
878 else
880 fixed_regs[i] = fixed;
881 call_used_regs[i] = call_used;
882 #ifdef CALL_REALLY_USED_REGISTERS
883 if (fixed == 0)
884 call_really_used_regs[i] = call_used;
885 #endif
888 else
890 warning (0, "unknown register name: %s", name);
894 /* Mark register number I as global. */
896 void
897 globalize_reg (int i)
899 if (fixed_regs[i] == 0 && no_global_reg_vars)
900 error ("global register variable follows a function definition");
902 if (global_regs[i])
904 warning (0, "register used for two global register variables");
905 return;
908 if (call_used_regs[i] && ! fixed_regs[i])
909 warning (0, "call-clobbered register used for global register variable");
911 global_regs[i] = 1;
913 /* If we're globalizing the frame pointer, we need to set the
914 appropriate regs_invalidated_by_call bit, even if it's already
915 set in fixed_regs. */
916 if (i != STACK_POINTER_REGNUM)
917 SET_HARD_REG_BIT (regs_invalidated_by_call, i);
919 /* If already fixed, nothing else to do. */
920 if (fixed_regs[i])
921 return;
923 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
924 #ifdef CALL_REALLY_USED_REGISTERS
925 call_really_used_regs[i] = 1;
926 #endif
928 SET_HARD_REG_BIT (fixed_reg_set, i);
929 SET_HARD_REG_BIT (call_used_reg_set, i);
930 SET_HARD_REG_BIT (call_fixed_reg_set, i);
933 /* Now the data and code for the `regclass' pass, which happens
934 just before local-alloc. */
936 /* The `costs' struct records the cost of using a hard register of each class
937 and of using memory for each pseudo. We use this data to set up
938 register class preferences. */
940 struct costs
942 int cost[N_REG_CLASSES];
943 int mem_cost;
946 /* Structure used to record preferences of given pseudo. */
947 struct reg_pref
949 /* (enum reg_class) prefclass is the preferred class. May be
950 NO_REGS if no class is better than memory. */
951 char prefclass;
953 /* altclass is a register class that we should use for allocating
954 pseudo if no register in the preferred class is available.
955 If no register in this class is available, memory is preferred.
957 It might appear to be more general to have a bitmask of classes here,
958 but since it is recommended that there be a class corresponding to the
959 union of most major pair of classes, that generality is not required. */
960 char altclass;
963 /* Record the cost of each class for each pseudo. */
965 static struct costs *costs;
967 /* Initialized once, and used to initialize cost values for each insn. */
969 static struct costs init_cost;
971 /* Record preferences of each pseudo.
972 This is available after `regclass' is run. */
974 static struct reg_pref *reg_pref;
976 /* Frequency of executions of current insn. */
978 static int frequency;
980 static rtx scan_one_insn (rtx, int);
981 static void record_operand_costs (rtx, struct costs *, struct reg_pref *);
982 static void dump_regclass (FILE *);
983 static void record_reg_classes (int, int, rtx *, enum machine_mode *,
984 const char **, rtx, struct costs *,
985 struct reg_pref *);
986 static int copy_cost (rtx, enum machine_mode, enum reg_class, int,
987 secondary_reload_info *);
988 static void record_address_regs (enum machine_mode, rtx, int, enum rtx_code,
989 enum rtx_code, int);
990 #ifdef FORBIDDEN_INC_DEC_CLASSES
991 static int auto_inc_dec_reg_p (rtx, enum machine_mode);
992 #endif
993 static void reg_scan_mark_refs (rtx, rtx);
995 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */
997 static inline bool
998 ok_for_index_p_nonstrict (rtx reg)
1000 unsigned regno = REGNO (reg);
1001 return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno);
1004 /* A version of regno_ok_for_base_p for use during regclass, when all pseudos
1005 should count as OK. Arguments as for regno_ok_for_base_p. */
1007 static inline bool
1008 ok_for_base_p_nonstrict (rtx reg, enum machine_mode mode,
1009 enum rtx_code outer_code, enum rtx_code index_code)
1011 unsigned regno = REGNO (reg);
1012 if (regno >= FIRST_PSEUDO_REGISTER)
1013 return true;
1015 return ok_for_base_p_1 (regno, mode, outer_code, index_code);
1018 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
1019 This function is sometimes called before the info has been computed.
1020 When that happens, just return GENERAL_REGS, which is innocuous. */
1022 enum reg_class
1023 reg_preferred_class (int regno)
1025 if (reg_pref == 0)
1026 return GENERAL_REGS;
1027 return (enum reg_class) reg_pref[regno].prefclass;
1030 enum reg_class
1031 reg_alternate_class (int regno)
1033 if (reg_pref == 0)
1034 return ALL_REGS;
1036 return (enum reg_class) reg_pref[regno].altclass;
1039 /* Initialize some global data for this pass. */
1041 static unsigned int
1042 regclass_init (void)
1044 int i;
1046 if (df)
1047 df_compute_regs_ever_live (true);
1049 init_cost.mem_cost = 10000;
1050 for (i = 0; i < N_REG_CLASSES; i++)
1051 init_cost.cost[i] = 10000;
1053 /* This prevents dump_flow_info from losing if called
1054 before regclass is run. */
1055 reg_pref = NULL;
1057 /* No more global register variables may be declared. */
1058 no_global_reg_vars = 1;
1059 return 1;
1062 struct rtl_opt_pass pass_regclass_init =
1065 RTL_PASS,
1066 "regclass", /* name */
1067 NULL, /* gate */
1068 regclass_init, /* execute */
1069 NULL, /* sub */
1070 NULL, /* next */
1071 0, /* static_pass_number */
1072 0, /* tv_id */
1073 0, /* properties_required */
1074 0, /* properties_provided */
1075 0, /* properties_destroyed */
1076 0, /* todo_flags_start */
1077 0 /* todo_flags_finish */
1083 /* Dump register costs. */
1084 static void
1085 dump_regclass (FILE *dump)
1087 int i;
1088 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1090 int /* enum reg_class */ class;
1091 if (REG_N_REFS (i))
1093 fprintf (dump, " Register %i costs:", i);
1094 for (class = 0; class < (int) N_REG_CLASSES; class++)
1095 if (contains_reg_of_mode [(enum reg_class) class][PSEUDO_REGNO_MODE (i)]
1096 #ifdef FORBIDDEN_INC_DEC_CLASSES
1097 && (!in_inc_dec[i]
1098 || !forbidden_inc_dec_class[(enum reg_class) class])
1099 #endif
1100 #ifdef CANNOT_CHANGE_MODE_CLASS
1101 && ! invalid_mode_change_p (i, (enum reg_class) class,
1102 PSEUDO_REGNO_MODE (i))
1103 #endif
1105 fprintf (dump, " %s:%i", reg_class_names[class],
1106 costs[i].cost[(enum reg_class) class]);
1107 fprintf (dump, " MEM:%i\n", costs[i].mem_cost);
1113 /* Calculate the costs of insn operands. */
1115 static void
1116 record_operand_costs (rtx insn, struct costs *op_costs,
1117 struct reg_pref *reg_pref)
1119 const char *constraints[MAX_RECOG_OPERANDS];
1120 enum machine_mode modes[MAX_RECOG_OPERANDS];
1121 int i;
1123 for (i = 0; i < recog_data.n_operands; i++)
1125 constraints[i] = recog_data.constraints[i];
1126 modes[i] = recog_data.operand_mode[i];
1129 /* If we get here, we are set up to record the costs of all the
1130 operands for this insn. Start by initializing the costs.
1131 Then handle any address registers. Finally record the desired
1132 classes for any pseudos, doing it twice if some pair of
1133 operands are commutative. */
1135 for (i = 0; i < recog_data.n_operands; i++)
1137 op_costs[i] = init_cost;
1139 if (GET_CODE (recog_data.operand[i]) == SUBREG)
1140 recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]);
1142 if (MEM_P (recog_data.operand[i]))
1143 record_address_regs (GET_MODE (recog_data.operand[i]),
1144 XEXP (recog_data.operand[i], 0),
1145 0, MEM, SCRATCH, frequency * 2);
1146 else if (constraints[i][0] == 'p'
1147 || EXTRA_ADDRESS_CONSTRAINT (constraints[i][0], constraints[i]))
1148 record_address_regs (VOIDmode, recog_data.operand[i], 0, ADDRESS,
1149 SCRATCH, frequency * 2);
1152 /* Check for commutative in a separate loop so everything will
1153 have been initialized. We must do this even if one operand
1154 is a constant--see addsi3 in m68k.md. */
1156 for (i = 0; i < (int) recog_data.n_operands - 1; i++)
1157 if (constraints[i][0] == '%')
1159 const char *xconstraints[MAX_RECOG_OPERANDS];
1160 int j;
1162 /* Handle commutative operands by swapping the constraints.
1163 We assume the modes are the same. */
1165 for (j = 0; j < recog_data.n_operands; j++)
1166 xconstraints[j] = constraints[j];
1168 xconstraints[i] = constraints[i+1];
1169 xconstraints[i+1] = constraints[i];
1170 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
1171 recog_data.operand, modes,
1172 xconstraints, insn, op_costs, reg_pref);
1175 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
1176 recog_data.operand, modes,
1177 constraints, insn, op_costs, reg_pref);
1180 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
1181 time it would save code to put a certain register in a certain class.
1182 PASS, when nonzero, inhibits some optimizations which need only be done
1183 once.
1184 Return the last insn processed, so that the scan can be continued from
1185 there. */
1187 static rtx
1188 scan_one_insn (rtx insn, int pass ATTRIBUTE_UNUSED)
1190 enum rtx_code pat_code;
1191 rtx set, note;
1192 int i, j;
1193 struct costs op_costs[MAX_RECOG_OPERANDS];
1195 if (!INSN_P (insn))
1196 return insn;
1198 pat_code = GET_CODE (PATTERN (insn));
1199 if (pat_code == USE
1200 || pat_code == CLOBBER
1201 || pat_code == ASM_INPUT
1202 || pat_code == ADDR_VEC
1203 || pat_code == ADDR_DIFF_VEC)
1204 return insn;
1206 set = single_set (insn);
1207 extract_insn (insn);
1209 /* If this insn loads a parameter from its stack slot, then
1210 it represents a savings, rather than a cost, if the
1211 parameter is stored in memory. Record this fact. */
1213 if (set != 0 && REG_P (SET_DEST (set))
1214 && MEM_P (SET_SRC (set))
1215 && (note = find_reg_note (insn, REG_EQUIV,
1216 NULL_RTX)) != 0
1217 && MEM_P (XEXP (note, 0)))
1219 costs[REGNO (SET_DEST (set))].mem_cost
1220 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
1221 GENERAL_REGS, 1)
1222 * frequency);
1223 record_address_regs (GET_MODE (SET_SRC (set)), XEXP (SET_SRC (set), 0),
1224 0, MEM, SCRATCH, frequency * 2);
1225 return insn;
1228 record_operand_costs (insn, op_costs, reg_pref);
1230 /* Now add the cost for each operand to the total costs for
1231 its register. */
1233 for (i = 0; i < recog_data.n_operands; i++)
1234 if (REG_P (recog_data.operand[i])
1235 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER)
1237 int regno = REGNO (recog_data.operand[i]);
1238 struct costs *p = &costs[regno], *q = &op_costs[i];
1240 p->mem_cost += q->mem_cost * frequency;
1241 for (j = 0; j < N_REG_CLASSES; j++)
1242 p->cost[j] += q->cost[j] * frequency;
1245 return insn;
1248 /* Initialize information about which register classes can be used for
1249 pseudos that are auto-incremented or auto-decremented. */
1251 static void
1252 init_reg_autoinc (void)
1254 #ifdef FORBIDDEN_INC_DEC_CLASSES
1255 int i;
1257 memset (forbidden_inc_dec_class, 0, sizeof forbidden_inc_dec_class);
1258 for (i = 0; i < N_REG_CLASSES; i++)
1260 rtx r = gen_rtx_raw_REG (VOIDmode, 0);
1261 enum machine_mode m;
1262 int j;
1264 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
1265 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
1267 SET_REGNO (r, j);
1269 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
1270 m = (enum machine_mode) ((int) m + 1))
1271 if (HARD_REGNO_MODE_OK (j, m))
1273 /* ??? There are two assumptions here; that the base class does not
1274 depend on the exact outer code (POST_INC vs. PRE_INC etc.), and
1275 that it does not depend on the machine mode of the memory
1276 reference. */
1277 enum reg_class base_class
1278 = base_reg_class (VOIDmode, POST_INC, SCRATCH);
1280 PUT_MODE (r, m);
1282 /* If a register is not directly suitable for an
1283 auto-increment or decrement addressing mode and
1284 requires secondary reloads, disallow its class from
1285 being used in such addresses. */
1287 if ((secondary_reload_class (0, base_class, m, r)
1288 || secondary_reload_class (1, base_class, m, r))
1289 && ! auto_inc_dec_reg_p (r, m))
1290 forbidden_inc_dec_class[i] = 1;
1294 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1297 /* This is a pass of the compiler that scans all instructions
1298 and calculates the preferred class for each pseudo-register.
1299 This information can be accessed later by calling `reg_preferred_class'.
1300 This pass comes just before local register allocation. */
1302 void
1303 regclass (rtx f, int nregs)
1305 rtx insn;
1306 int i;
1307 int pass;
1308 max_regno = max_reg_num ();
1310 init_recog ();
1312 reg_renumber = xmalloc (max_regno * sizeof (short));
1313 reg_pref = XCNEWVEC (struct reg_pref, max_regno);
1314 memset (reg_renumber, -1, max_regno * sizeof (short));
1316 costs = XNEWVEC (struct costs, nregs);
1318 #ifdef FORBIDDEN_INC_DEC_CLASSES
1320 in_inc_dec = XNEWVEC (char, nregs);
1322 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1324 /* Normally we scan the insns once and determine the best class to use for
1325 each register. However, if -fexpensive_optimizations are on, we do so
1326 twice, the second time using the tentative best classes to guide the
1327 selection. */
1329 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
1331 basic_block bb;
1333 if (dump_file)
1334 fprintf (dump_file, "\n\nPass %i\n\n",pass);
1335 /* Zero out our accumulation of the cost of each class for each reg. */
1337 memset (costs, 0, nregs * sizeof (struct costs));
1339 #ifdef FORBIDDEN_INC_DEC_CLASSES
1340 memset (in_inc_dec, 0, nregs);
1341 #endif
1343 /* Scan the instructions and record each time it would
1344 save code to put a certain register in a certain class. */
1346 if (!optimize)
1348 frequency = REG_FREQ_MAX;
1349 for (insn = f; insn; insn = NEXT_INSN (insn))
1350 insn = scan_one_insn (insn, pass);
1352 else
1353 FOR_EACH_BB (bb)
1355 /* Show that an insn inside a loop is likely to be executed three
1356 times more than insns outside a loop. This is much more
1357 aggressive than the assumptions made elsewhere and is being
1358 tried as an experiment. */
1359 frequency = REG_FREQ_FROM_BB (bb);
1360 for (insn = BB_HEAD (bb); ; insn = NEXT_INSN (insn))
1362 insn = scan_one_insn (insn, pass);
1363 if (insn == BB_END (bb))
1364 break;
1368 /* Now for each register look at how desirable each class is
1369 and find which class is preferred. Store that in
1370 `prefclass'. Record in `altclass' the largest register
1371 class any of whose registers is better than memory. */
1373 if (dump_file)
1375 dump_regclass (dump_file);
1376 fprintf (dump_file,"\n");
1378 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1380 int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1381 enum reg_class best = ALL_REGS, alt = NO_REGS;
1382 /* This is an enum reg_class, but we call it an int
1383 to save lots of casts. */
1384 int class;
1385 struct costs *p = &costs[i];
1387 if (regno_reg_rtx[i] == NULL)
1388 continue;
1390 /* In non-optimizing compilation REG_N_REFS is not initialized
1391 yet. */
1392 if (optimize && !REG_N_REFS (i) && !REG_N_SETS (i))
1393 continue;
1395 for (class = (int) ALL_REGS - 1; class > 0; class--)
1397 /* Ignore classes that are too small for this operand or
1398 invalid for an operand that was auto-incremented. */
1399 if (!contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)]
1400 #ifdef FORBIDDEN_INC_DEC_CLASSES
1401 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1402 #endif
1403 #ifdef CANNOT_CHANGE_MODE_CLASS
1404 || invalid_mode_change_p (i, (enum reg_class) class,
1405 PSEUDO_REGNO_MODE (i))
1406 #endif
1409 else if (p->cost[class] < best_cost)
1411 best_cost = p->cost[class];
1412 best = (enum reg_class) class;
1414 else if (p->cost[class] == best_cost)
1415 best = reg_class_subunion[(int) best][class];
1418 /* If no register class is better than memory, use memory. */
1419 if (p->mem_cost < best_cost)
1420 best = NO_REGS;
1422 /* Record the alternate register class; i.e., a class for which
1423 every register in it is better than using memory. If adding a
1424 class would make a smaller class (i.e., no union of just those
1425 classes exists), skip that class. The major unions of classes
1426 should be provided as a register class. Don't do this if we
1427 will be doing it again later. */
1429 if ((pass == 1 || dump_file) || ! flag_expensive_optimizations)
1430 for (class = 0; class < N_REG_CLASSES; class++)
1431 if (p->cost[class] < p->mem_cost
1432 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1433 > reg_class_size[(int) alt])
1434 #ifdef FORBIDDEN_INC_DEC_CLASSES
1435 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1436 #endif
1437 #ifdef CANNOT_CHANGE_MODE_CLASS
1438 && ! invalid_mode_change_p (i, (enum reg_class) class,
1439 PSEUDO_REGNO_MODE (i))
1440 #endif
1442 alt = reg_class_subunion[(int) alt][class];
1444 /* If we don't add any classes, nothing to try. */
1445 if (alt == best)
1446 alt = NO_REGS;
1448 if (dump_file
1449 && (reg_pref[i].prefclass != (int) best
1450 || reg_pref[i].altclass != (int) alt))
1452 fprintf (dump_file, " Register %i", i);
1453 if (alt == ALL_REGS || best == ALL_REGS)
1454 fprintf (dump_file, " pref %s\n", reg_class_names[(int) best]);
1455 else if (alt == NO_REGS)
1456 fprintf (dump_file, " pref %s or none\n", reg_class_names[(int) best]);
1457 else
1458 fprintf (dump_file, " pref %s, else %s\n",
1459 reg_class_names[(int) best],
1460 reg_class_names[(int) alt]);
1463 /* We cast to (int) because (char) hits bugs in some compilers. */
1464 reg_pref[i].prefclass = (int) best;
1465 reg_pref[i].altclass = (int) alt;
1469 #ifdef FORBIDDEN_INC_DEC_CLASSES
1470 free (in_inc_dec);
1471 #endif
1472 free (costs);
1475 /* Record the cost of using memory or registers of various classes for
1476 the operands in INSN.
1478 N_ALTS is the number of alternatives.
1480 N_OPS is the number of operands.
1482 OPS is an array of the operands.
1484 MODES are the modes of the operands, in case any are VOIDmode.
1486 CONSTRAINTS are the constraints to use for the operands. This array
1487 is modified by this procedure.
1489 This procedure works alternative by alternative. For each alternative
1490 we assume that we will be able to allocate all pseudos to their ideal
1491 register class and calculate the cost of using that alternative. Then
1492 we compute for each operand that is a pseudo-register, the cost of
1493 having the pseudo allocated to each register class and using it in that
1494 alternative. To this cost is added the cost of the alternative.
1496 The cost of each class for this insn is its lowest cost among all the
1497 alternatives. */
1499 static void
1500 record_reg_classes (int n_alts, int n_ops, rtx *ops,
1501 enum machine_mode *modes, const char **constraints,
1502 rtx insn, struct costs *op_costs,
1503 struct reg_pref *reg_pref)
1505 int alt;
1506 int i, j;
1507 rtx set;
1509 /* Process each alternative, each time minimizing an operand's cost with
1510 the cost for each operand in that alternative. */
1512 for (alt = 0; alt < n_alts; alt++)
1514 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1515 int alt_fail = 0;
1516 int alt_cost = 0;
1517 enum reg_class classes[MAX_RECOG_OPERANDS];
1518 int allows_mem[MAX_RECOG_OPERANDS];
1519 int class;
1521 for (i = 0; i < n_ops; i++)
1523 const char *p = constraints[i];
1524 rtx op = ops[i];
1525 enum machine_mode mode = modes[i];
1526 int allows_addr = 0;
1527 int win = 0;
1528 unsigned char c;
1530 /* Initially show we know nothing about the register class. */
1531 classes[i] = NO_REGS;
1532 allows_mem[i] = 0;
1534 /* If this operand has no constraints at all, we can conclude
1535 nothing about it since anything is valid. */
1537 if (*p == 0)
1539 if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1540 memset (&this_op_costs[i], 0, sizeof this_op_costs[i]);
1542 continue;
1545 /* If this alternative is only relevant when this operand
1546 matches a previous operand, we do different things depending
1547 on whether this operand is a pseudo-reg or not. We must process
1548 any modifiers for the operand before we can make this test. */
1550 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
1551 p++;
1553 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1555 /* Copy class and whether memory is allowed from the matching
1556 alternative. Then perform any needed cost computations
1557 and/or adjustments. */
1558 j = p[0] - '0';
1559 classes[i] = classes[j];
1560 allows_mem[i] = allows_mem[j];
1562 if (!REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER)
1564 /* If this matches the other operand, we have no added
1565 cost and we win. */
1566 if (rtx_equal_p (ops[j], op))
1567 win = 1;
1569 /* If we can put the other operand into a register, add to
1570 the cost of this alternative the cost to copy this
1571 operand to the register used for the other operand. */
1573 else if (classes[j] != NO_REGS)
1575 alt_cost += copy_cost (op, mode, classes[j], 1, NULL);
1576 win = 1;
1579 else if (!REG_P (ops[j])
1580 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1582 /* This op is a pseudo but the one it matches is not. */
1584 /* If we can't put the other operand into a register, this
1585 alternative can't be used. */
1587 if (classes[j] == NO_REGS)
1588 alt_fail = 1;
1590 /* Otherwise, add to the cost of this alternative the cost
1591 to copy the other operand to the register used for this
1592 operand. */
1594 else
1595 alt_cost += copy_cost (ops[j], mode, classes[j], 1, NULL);
1597 else
1599 /* The costs of this operand are not the same as the other
1600 operand since move costs are not symmetric. Moreover,
1601 if we cannot tie them, this alternative needs to do a
1602 copy, which is one instruction. */
1604 struct costs *pp = &this_op_costs[i];
1605 move_table *intable = NULL;
1606 move_table *outtable = NULL;
1607 int op_class = (int) classes[i];
1609 if (!move_cost[mode])
1610 init_move_cost (mode);
1611 intable = may_move_in_cost[mode];
1612 outtable = may_move_out_cost[mode];
1614 /* The loop is performance critical, so unswitch it manually.
1616 switch (recog_data.operand_type[i])
1618 case OP_INOUT:
1619 for (class = 0; class < N_REG_CLASSES; class++)
1620 pp->cost[class] = (intable[class][op_class]
1621 + outtable[op_class][class]);
1622 break;
1623 case OP_IN:
1624 for (class = 0; class < N_REG_CLASSES; class++)
1625 pp->cost[class] = intable[class][op_class];
1626 break;
1627 case OP_OUT:
1628 for (class = 0; class < N_REG_CLASSES; class++)
1629 pp->cost[class] = outtable[op_class][class];
1630 break;
1633 /* If the alternative actually allows memory, make things
1634 a bit cheaper since we won't need an extra insn to
1635 load it. */
1637 pp->mem_cost
1638 = ((recog_data.operand_type[i] != OP_IN
1639 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1640 : 0)
1641 + (recog_data.operand_type[i] != OP_OUT
1642 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1643 : 0) - allows_mem[i]);
1645 /* If we have assigned a class to this register in our
1646 first pass, add a cost to this alternative corresponding
1647 to what we would add if this register were not in the
1648 appropriate class. */
1650 if (reg_pref && reg_pref[REGNO (op)].prefclass != NO_REGS)
1651 alt_cost
1652 += (may_move_in_cost[mode]
1653 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1654 [(int) classes[i]]);
1656 if (REGNO (ops[i]) != REGNO (ops[j])
1657 && ! find_reg_note (insn, REG_DEAD, op))
1658 alt_cost += 2;
1660 /* This is in place of ordinary cost computation
1661 for this operand, so skip to the end of the
1662 alternative (should be just one character). */
1663 while (*p && *p++ != ',')
1666 constraints[i] = p;
1667 continue;
1671 /* Scan all the constraint letters. See if the operand matches
1672 any of the constraints. Collect the valid register classes
1673 and see if this operand accepts memory. */
1675 while ((c = *p))
1677 switch (c)
1679 case ',':
1680 break;
1681 case '*':
1682 /* Ignore the next letter for this pass. */
1683 c = *++p;
1684 break;
1686 case '?':
1687 alt_cost += 2;
1688 case '!': case '#': case '&':
1689 case '0': case '1': case '2': case '3': case '4':
1690 case '5': case '6': case '7': case '8': case '9':
1691 break;
1693 case 'p':
1694 allows_addr = 1;
1695 win = address_operand (op, GET_MODE (op));
1696 /* We know this operand is an address, so we want it to be
1697 allocated to a register that can be the base of an
1698 address, i.e. BASE_REG_CLASS. */
1699 classes[i]
1700 = reg_class_subunion[(int) classes[i]]
1701 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1702 break;
1704 case 'm': case 'o': case 'V':
1705 /* It doesn't seem worth distinguishing between offsettable
1706 and non-offsettable addresses here. */
1707 allows_mem[i] = 1;
1708 if (MEM_P (op))
1709 win = 1;
1710 break;
1712 case '<':
1713 if (MEM_P (op)
1714 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1715 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1716 win = 1;
1717 break;
1719 case '>':
1720 if (MEM_P (op)
1721 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1722 || GET_CODE (XEXP (op, 0)) == POST_INC))
1723 win = 1;
1724 break;
1726 case 'E':
1727 case 'F':
1728 if (GET_CODE (op) == CONST_DOUBLE
1729 || (GET_CODE (op) == CONST_VECTOR
1730 && (GET_MODE_CLASS (GET_MODE (op))
1731 == MODE_VECTOR_FLOAT)))
1732 win = 1;
1733 break;
1735 case 'G':
1736 case 'H':
1737 if (GET_CODE (op) == CONST_DOUBLE
1738 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p))
1739 win = 1;
1740 break;
1742 case 's':
1743 if (GET_CODE (op) == CONST_INT
1744 || (GET_CODE (op) == CONST_DOUBLE
1745 && GET_MODE (op) == VOIDmode))
1746 break;
1747 case 'i':
1748 if (CONSTANT_P (op)
1749 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)))
1750 win = 1;
1751 break;
1753 case 'n':
1754 if (GET_CODE (op) == CONST_INT
1755 || (GET_CODE (op) == CONST_DOUBLE
1756 && GET_MODE (op) == VOIDmode))
1757 win = 1;
1758 break;
1760 case 'I':
1761 case 'J':
1762 case 'K':
1763 case 'L':
1764 case 'M':
1765 case 'N':
1766 case 'O':
1767 case 'P':
1768 if (GET_CODE (op) == CONST_INT
1769 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p))
1770 win = 1;
1771 break;
1773 case 'X':
1774 win = 1;
1775 break;
1777 case 'g':
1778 if (MEM_P (op)
1779 || (CONSTANT_P (op)
1780 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))))
1781 win = 1;
1782 allows_mem[i] = 1;
1783 case 'r':
1784 classes[i]
1785 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1786 break;
1788 default:
1789 if (REG_CLASS_FROM_CONSTRAINT (c, p) != NO_REGS)
1790 classes[i]
1791 = reg_class_subunion[(int) classes[i]]
1792 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1793 #ifdef EXTRA_CONSTRAINT_STR
1794 else if (EXTRA_CONSTRAINT_STR (op, c, p))
1795 win = 1;
1797 if (EXTRA_MEMORY_CONSTRAINT (c, p))
1799 /* Every MEM can be reloaded to fit. */
1800 allows_mem[i] = 1;
1801 if (MEM_P (op))
1802 win = 1;
1804 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1806 /* Every address can be reloaded to fit. */
1807 allows_addr = 1;
1808 if (address_operand (op, GET_MODE (op)))
1809 win = 1;
1810 /* We know this operand is an address, so we want it to
1811 be allocated to a register that can be the base of an
1812 address, i.e. BASE_REG_CLASS. */
1813 classes[i]
1814 = reg_class_subunion[(int) classes[i]]
1815 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1817 #endif
1818 break;
1820 p += CONSTRAINT_LEN (c, p);
1821 if (c == ',')
1822 break;
1825 constraints[i] = p;
1827 /* How we account for this operand now depends on whether it is a
1828 pseudo register or not. If it is, we first check if any
1829 register classes are valid. If not, we ignore this alternative,
1830 since we want to assume that all pseudos get allocated for
1831 register preferencing. If some register class is valid, compute
1832 the costs of moving the pseudo into that class. */
1834 if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1836 if (classes[i] == NO_REGS)
1838 /* We must always fail if the operand is a REG, but
1839 we did not find a suitable class.
1841 Otherwise we may perform an uninitialized read
1842 from this_op_costs after the `continue' statement
1843 below. */
1844 alt_fail = 1;
1846 else
1848 struct costs *pp = &this_op_costs[i];
1849 move_table *intable = NULL;
1850 move_table *outtable = NULL;
1851 int op_class = (int) classes[i];
1853 if (!move_cost[mode])
1854 init_move_cost (mode);
1855 intable = may_move_in_cost[mode];
1856 outtable = may_move_out_cost[mode];
1858 /* The loop is performance critical, so unswitch it manually.
1860 switch (recog_data.operand_type[i])
1862 case OP_INOUT:
1863 for (class = 0; class < N_REG_CLASSES; class++)
1864 pp->cost[class] = (intable[class][op_class]
1865 + outtable[op_class][class]);
1866 break;
1867 case OP_IN:
1868 for (class = 0; class < N_REG_CLASSES; class++)
1869 pp->cost[class] = intable[class][op_class];
1870 break;
1871 case OP_OUT:
1872 for (class = 0; class < N_REG_CLASSES; class++)
1873 pp->cost[class] = outtable[op_class][class];
1874 break;
1877 /* If the alternative actually allows memory, make things
1878 a bit cheaper since we won't need an extra insn to
1879 load it. */
1881 pp->mem_cost
1882 = ((recog_data.operand_type[i] != OP_IN
1883 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1884 : 0)
1885 + (recog_data.operand_type[i] != OP_OUT
1886 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1887 : 0) - allows_mem[i]);
1889 /* If we have assigned a class to this register in our
1890 first pass, add a cost to this alternative corresponding
1891 to what we would add if this register were not in the
1892 appropriate class. */
1894 if (reg_pref && reg_pref[REGNO (op)].prefclass != NO_REGS)
1895 alt_cost
1896 += (may_move_in_cost[mode]
1897 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1898 [(int) classes[i]]);
1902 /* Otherwise, if this alternative wins, either because we
1903 have already determined that or if we have a hard register of
1904 the proper class, there is no cost for this alternative. */
1906 else if (win
1907 || (REG_P (op)
1908 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1911 /* If registers are valid, the cost of this alternative includes
1912 copying the object to and/or from a register. */
1914 else if (classes[i] != NO_REGS)
1916 if (recog_data.operand_type[i] != OP_OUT)
1917 alt_cost += copy_cost (op, mode, classes[i], 1, NULL);
1919 if (recog_data.operand_type[i] != OP_IN)
1920 alt_cost += copy_cost (op, mode, classes[i], 0, NULL);
1923 /* The only other way this alternative can be used is if this is a
1924 constant that could be placed into memory. */
1926 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i]))
1927 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1928 else
1929 alt_fail = 1;
1932 if (alt_fail)
1933 continue;
1935 /* Finally, update the costs with the information we've calculated
1936 about this alternative. */
1938 for (i = 0; i < n_ops; i++)
1939 if (REG_P (ops[i])
1940 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1942 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1943 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1945 pp->mem_cost = MIN (pp->mem_cost,
1946 (qq->mem_cost + alt_cost) * scale);
1948 for (class = 0; class < N_REG_CLASSES; class++)
1949 pp->cost[class] = MIN (pp->cost[class],
1950 (qq->cost[class] + alt_cost) * scale);
1954 /* If this insn is a single set copying operand 1 to operand 0
1955 and one operand is a pseudo with the other a hard reg or a pseudo
1956 that prefers a register that is in its own register class then
1957 we may want to adjust the cost of that register class to -1.
1959 Avoid the adjustment if the source does not die to avoid stressing of
1960 register allocator by preferrencing two colliding registers into single
1961 class.
1963 Also avoid the adjustment if a copy between registers of the class
1964 is expensive (ten times the cost of a default copy is considered
1965 arbitrarily expensive). This avoids losing when the preferred class
1966 is very expensive as the source of a copy instruction. */
1968 if ((set = single_set (insn)) != 0
1969 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1970 && REG_P (ops[0]) && REG_P (ops[1])
1971 && find_regno_note (insn, REG_DEAD, REGNO (ops[1])))
1972 for (i = 0; i <= 1; i++)
1973 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1975 unsigned int regno = REGNO (ops[!i]);
1976 enum machine_mode mode = GET_MODE (ops[!i]);
1977 int class;
1979 if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0
1980 && reg_pref[regno].prefclass != NO_REGS)
1982 enum reg_class pref = reg_pref[regno].prefclass;
1984 if ((reg_class_size[(unsigned char) pref]
1985 == (unsigned) CLASS_MAX_NREGS (pref, mode))
1986 && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2)
1987 op_costs[i].cost[(unsigned char) pref] = -1;
1989 else if (regno < FIRST_PSEUDO_REGISTER)
1990 for (class = 0; class < N_REG_CLASSES; class++)
1991 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1992 && reg_class_size[class] == (unsigned) CLASS_MAX_NREGS (class, mode))
1994 if (reg_class_size[class] == 1)
1995 op_costs[i].cost[class] = -1;
1996 else if (in_hard_reg_set_p (reg_class_contents[class],
1997 mode, regno))
1998 op_costs[i].cost[class] = -1;
2003 /* Compute the cost of loading X into (if TO_P is nonzero) or from (if
2004 TO_P is zero) a register of class CLASS in mode MODE.
2006 X must not be a pseudo. */
2008 static int
2009 copy_cost (rtx x, enum machine_mode mode, enum reg_class class, int to_p,
2010 secondary_reload_info *prev_sri)
2012 enum reg_class secondary_class = NO_REGS;
2013 secondary_reload_info sri;
2015 /* If X is a SCRATCH, there is actually nothing to move since we are
2016 assuming optimal allocation. */
2018 if (GET_CODE (x) == SCRATCH)
2019 return 0;
2021 /* Get the class we will actually use for a reload. */
2022 class = PREFERRED_RELOAD_CLASS (x, class);
2024 /* If we need a secondary reload for an intermediate, the
2025 cost is that to load the input into the intermediate register, then
2026 to copy it. */
2028 sri.prev_sri = prev_sri;
2029 sri.extra_cost = 0;
2030 secondary_class = targetm.secondary_reload (to_p, x, class, mode, &sri);
2032 if (!move_cost[mode])
2033 init_move_cost (mode);
2035 if (secondary_class != NO_REGS)
2036 return (move_cost[mode][(int) secondary_class][(int) class]
2037 + sri.extra_cost
2038 + copy_cost (x, mode, secondary_class, to_p, &sri));
2040 /* For memory, use the memory move cost, for (hard) registers, use the
2041 cost to move between the register classes, and use 2 for everything
2042 else (constants). */
2044 if (MEM_P (x) || class == NO_REGS)
2045 return sri.extra_cost + MEMORY_MOVE_COST (mode, class, to_p);
2047 else if (REG_P (x))
2048 return (sri.extra_cost
2049 + move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class]);
2051 else
2052 /* If this is a constant, we may eventually want to call rtx_cost here. */
2053 return sri.extra_cost + COSTS_N_INSNS (1);
2056 /* Record the pseudo registers we must reload into hard registers
2057 in a subexpression of a memory address, X.
2059 If CONTEXT is 0, we are looking at the base part of an address, otherwise we
2060 are looking at the index part.
2062 MODE is the mode of the memory reference; OUTER_CODE and INDEX_CODE
2063 give the context that the rtx appears in. These three arguments are
2064 passed down to base_reg_class.
2066 SCALE is twice the amount to multiply the cost by (it is twice so we
2067 can represent half-cost adjustments). */
2069 static void
2070 record_address_regs (enum machine_mode mode, rtx x, int context,
2071 enum rtx_code outer_code, enum rtx_code index_code,
2072 int scale)
2074 enum rtx_code code = GET_CODE (x);
2075 enum reg_class class;
2077 if (context == 1)
2078 class = INDEX_REG_CLASS;
2079 else
2080 class = base_reg_class (mode, outer_code, index_code);
2082 switch (code)
2084 case CONST_INT:
2085 case CONST:
2086 case CC0:
2087 case PC:
2088 case SYMBOL_REF:
2089 case LABEL_REF:
2090 return;
2092 case PLUS:
2093 /* When we have an address that is a sum,
2094 we must determine whether registers are "base" or "index" regs.
2095 If there is a sum of two registers, we must choose one to be
2096 the "base". Luckily, we can use the REG_POINTER to make a good
2097 choice most of the time. We only need to do this on machines
2098 that can have two registers in an address and where the base
2099 and index register classes are different.
2101 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
2102 that seems bogus since it should only be set when we are sure
2103 the register is being used as a pointer. */
2106 rtx arg0 = XEXP (x, 0);
2107 rtx arg1 = XEXP (x, 1);
2108 enum rtx_code code0 = GET_CODE (arg0);
2109 enum rtx_code code1 = GET_CODE (arg1);
2111 /* Look inside subregs. */
2112 if (code0 == SUBREG)
2113 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
2114 if (code1 == SUBREG)
2115 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
2117 /* If this machine only allows one register per address, it must
2118 be in the first operand. */
2120 if (MAX_REGS_PER_ADDRESS == 1)
2121 record_address_regs (mode, arg0, 0, PLUS, code1, scale);
2123 /* If index and base registers are the same on this machine, just
2124 record registers in any non-constant operands. We assume here,
2125 as well as in the tests below, that all addresses are in
2126 canonical form. */
2128 else if (INDEX_REG_CLASS == base_reg_class (VOIDmode, PLUS, SCRATCH))
2130 record_address_regs (mode, arg0, context, PLUS, code1, scale);
2131 if (! CONSTANT_P (arg1))
2132 record_address_regs (mode, arg1, context, PLUS, code0, scale);
2135 /* If the second operand is a constant integer, it doesn't change
2136 what class the first operand must be. */
2138 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
2139 record_address_regs (mode, arg0, context, PLUS, code1, scale);
2141 /* If the second operand is a symbolic constant, the first operand
2142 must be an index register. */
2144 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
2145 record_address_regs (mode, arg0, 1, PLUS, code1, scale);
2147 /* If both operands are registers but one is already a hard register
2148 of index or reg-base class, give the other the class that the
2149 hard register is not. */
2151 else if (code0 == REG && code1 == REG
2152 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
2153 && (ok_for_base_p_nonstrict (arg0, mode, PLUS, REG)
2154 || ok_for_index_p_nonstrict (arg0)))
2155 record_address_regs (mode, arg1,
2156 ok_for_base_p_nonstrict (arg0, mode, PLUS, REG)
2157 ? 1 : 0,
2158 PLUS, REG, scale);
2159 else if (code0 == REG && code1 == REG
2160 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
2161 && (ok_for_base_p_nonstrict (arg1, mode, PLUS, REG)
2162 || ok_for_index_p_nonstrict (arg1)))
2163 record_address_regs (mode, arg0,
2164 ok_for_base_p_nonstrict (arg1, mode, PLUS, REG)
2165 ? 1 : 0,
2166 PLUS, REG, scale);
2168 /* If one operand is known to be a pointer, it must be the base
2169 with the other operand the index. Likewise if the other operand
2170 is a MULT. */
2172 else if ((code0 == REG && REG_POINTER (arg0))
2173 || code1 == MULT)
2175 record_address_regs (mode, arg0, 0, PLUS, code1, scale);
2176 record_address_regs (mode, arg1, 1, PLUS, code0, scale);
2178 else if ((code1 == REG && REG_POINTER (arg1))
2179 || code0 == MULT)
2181 record_address_regs (mode, arg0, 1, PLUS, code1, scale);
2182 record_address_regs (mode, arg1, 0, PLUS, code0, scale);
2185 /* Otherwise, count equal chances that each might be a base
2186 or index register. This case should be rare. */
2188 else
2190 record_address_regs (mode, arg0, 0, PLUS, code1, scale / 2);
2191 record_address_regs (mode, arg0, 1, PLUS, code1, scale / 2);
2192 record_address_regs (mode, arg1, 0, PLUS, code0, scale / 2);
2193 record_address_regs (mode, arg1, 1, PLUS, code0, scale / 2);
2196 break;
2198 /* Double the importance of a pseudo register that is incremented
2199 or decremented, since it would take two extra insns
2200 if it ends up in the wrong place. */
2201 case POST_MODIFY:
2202 case PRE_MODIFY:
2203 record_address_regs (mode, XEXP (x, 0), 0, code,
2204 GET_CODE (XEXP (XEXP (x, 1), 1)), 2 * scale);
2205 if (REG_P (XEXP (XEXP (x, 1), 1)))
2206 record_address_regs (mode, XEXP (XEXP (x, 1), 1), 1, code, REG,
2207 2 * scale);
2208 break;
2210 case POST_INC:
2211 case PRE_INC:
2212 case POST_DEC:
2213 case PRE_DEC:
2214 /* Double the importance of a pseudo register that is incremented
2215 or decremented, since it would take two extra insns
2216 if it ends up in the wrong place. If the operand is a pseudo,
2217 show it is being used in an INC_DEC context. */
2219 #ifdef FORBIDDEN_INC_DEC_CLASSES
2220 if (REG_P (XEXP (x, 0))
2221 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
2222 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
2223 #endif
2225 record_address_regs (mode, XEXP (x, 0), 0, code, SCRATCH, 2 * scale);
2226 break;
2228 case REG:
2230 struct costs *pp = &costs[REGNO (x)];
2231 int i;
2233 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
2235 if (!move_cost[Pmode])
2236 init_move_cost (Pmode);
2237 for (i = 0; i < N_REG_CLASSES; i++)
2238 pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2;
2240 break;
2242 default:
2244 const char *fmt = GET_RTX_FORMAT (code);
2245 int i;
2246 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2247 if (fmt[i] == 'e')
2248 record_address_regs (mode, XEXP (x, i), context, code, SCRATCH,
2249 scale);
2254 #ifdef FORBIDDEN_INC_DEC_CLASSES
2256 /* Return 1 if REG is valid as an auto-increment memory reference
2257 to an object of MODE. */
2259 static int
2260 auto_inc_dec_reg_p (rtx reg, enum machine_mode mode)
2262 if (HAVE_POST_INCREMENT
2263 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
2264 return 1;
2266 if (HAVE_POST_DECREMENT
2267 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
2268 return 1;
2270 if (HAVE_PRE_INCREMENT
2271 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
2272 return 1;
2274 if (HAVE_PRE_DECREMENT
2275 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
2276 return 1;
2278 return 0;
2280 #endif
2282 /* Free up the space allocated by allocate_reg_info. */
2283 void
2284 free_reg_info (void)
2286 if (reg_pref)
2288 free (reg_pref);
2289 reg_pref = NULL;
2292 if (reg_renumber)
2294 free (reg_renumber);
2295 reg_renumber = NULL;
2300 /* This is the `regscan' pass of the compiler, run just before cse and
2301 again just before loop. It finds the first and last use of each
2302 pseudo-register. */
2304 void
2305 reg_scan (rtx f, unsigned int nregs ATTRIBUTE_UNUSED)
2307 rtx insn;
2309 timevar_push (TV_REG_SCAN);
2311 for (insn = f; insn; insn = NEXT_INSN (insn))
2312 if (INSN_P (insn))
2314 reg_scan_mark_refs (PATTERN (insn), insn);
2315 if (REG_NOTES (insn))
2316 reg_scan_mark_refs (REG_NOTES (insn), insn);
2319 timevar_pop (TV_REG_SCAN);
2323 /* X is the expression to scan. INSN is the insn it appears in.
2324 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2325 We should only record information for REGs with numbers
2326 greater than or equal to MIN_REGNO. */
2328 static void
2329 reg_scan_mark_refs (rtx x, rtx insn)
2331 enum rtx_code code;
2332 rtx dest;
2333 rtx note;
2335 if (!x)
2336 return;
2337 code = GET_CODE (x);
2338 switch (code)
2340 case CONST:
2341 case CONST_INT:
2342 case CONST_DOUBLE:
2343 case CONST_FIXED:
2344 case CONST_VECTOR:
2345 case CC0:
2346 case PC:
2347 case SYMBOL_REF:
2348 case LABEL_REF:
2349 case ADDR_VEC:
2350 case ADDR_DIFF_VEC:
2351 case REG:
2352 return;
2354 case EXPR_LIST:
2355 if (XEXP (x, 0))
2356 reg_scan_mark_refs (XEXP (x, 0), insn);
2357 if (XEXP (x, 1))
2358 reg_scan_mark_refs (XEXP (x, 1), insn);
2359 break;
2361 case INSN_LIST:
2362 if (XEXP (x, 1))
2363 reg_scan_mark_refs (XEXP (x, 1), insn);
2364 break;
2366 case CLOBBER:
2367 if (MEM_P (XEXP (x, 0)))
2368 reg_scan_mark_refs (XEXP (XEXP (x, 0), 0), insn);
2369 break;
2371 case SET:
2372 /* Count a set of the destination if it is a register. */
2373 for (dest = SET_DEST (x);
2374 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2375 || GET_CODE (dest) == ZERO_EXTEND;
2376 dest = XEXP (dest, 0))
2379 /* If this is setting a pseudo from another pseudo or the sum of a
2380 pseudo and a constant integer and the other pseudo is known to be
2381 a pointer, set the destination to be a pointer as well.
2383 Likewise if it is setting the destination from an address or from a
2384 value equivalent to an address or to the sum of an address and
2385 something else.
2387 But don't do any of this if the pseudo corresponds to a user
2388 variable since it should have already been set as a pointer based
2389 on the type. */
2391 if (REG_P (SET_DEST (x))
2392 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2393 /* If the destination pseudo is set more than once, then other
2394 sets might not be to a pointer value (consider access to a
2395 union in two threads of control in the presence of global
2396 optimizations). So only set REG_POINTER on the destination
2397 pseudo if this is the only set of that pseudo. */
2398 && DF_REG_DEF_COUNT (REGNO (SET_DEST (x))) == 1
2399 && ! REG_USERVAR_P (SET_DEST (x))
2400 && ! REG_POINTER (SET_DEST (x))
2401 && ((REG_P (SET_SRC (x))
2402 && REG_POINTER (SET_SRC (x)))
2403 || ((GET_CODE (SET_SRC (x)) == PLUS
2404 || GET_CODE (SET_SRC (x)) == LO_SUM)
2405 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2406 && REG_P (XEXP (SET_SRC (x), 0))
2407 && REG_POINTER (XEXP (SET_SRC (x), 0)))
2408 || GET_CODE (SET_SRC (x)) == CONST
2409 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2410 || GET_CODE (SET_SRC (x)) == LABEL_REF
2411 || (GET_CODE (SET_SRC (x)) == HIGH
2412 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2413 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2414 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2415 || ((GET_CODE (SET_SRC (x)) == PLUS
2416 || GET_CODE (SET_SRC (x)) == LO_SUM)
2417 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2418 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2419 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2420 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2421 && (GET_CODE (XEXP (note, 0)) == CONST
2422 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2423 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2424 REG_POINTER (SET_DEST (x)) = 1;
2426 /* If this is setting a register from a register or from a simple
2427 conversion of a register, propagate REG_EXPR. */
2428 if (REG_P (dest) && !REG_ATTRS (dest))
2430 rtx src = SET_SRC (x);
2432 while (GET_CODE (src) == SIGN_EXTEND
2433 || GET_CODE (src) == ZERO_EXTEND
2434 || GET_CODE (src) == TRUNCATE
2435 || (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)))
2436 src = XEXP (src, 0);
2438 set_reg_attrs_from_value (dest, src);
2441 /* ... fall through ... */
2443 default:
2445 const char *fmt = GET_RTX_FORMAT (code);
2446 int i;
2447 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2449 if (fmt[i] == 'e')
2450 reg_scan_mark_refs (XEXP (x, i), insn);
2451 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2453 int j;
2454 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2455 reg_scan_mark_refs (XVECEXP (x, i, j), insn);
2462 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2463 is also in C2. */
2466 reg_class_subset_p (enum reg_class c1, enum reg_class c2)
2468 return (c1 == c2
2469 || c2 == ALL_REGS
2470 || hard_reg_set_subset_p (reg_class_contents[(int) c1],
2471 reg_class_contents[(int) c2]));
2474 /* Return nonzero if there is a register that is in both C1 and C2. */
2477 reg_classes_intersect_p (enum reg_class c1, enum reg_class c2)
2479 return (c1 == c2
2480 || c1 == ALL_REGS
2481 || c2 == ALL_REGS
2482 || hard_reg_set_intersect_p (reg_class_contents[(int) c1],
2483 reg_class_contents[(int) c2]));
2486 #ifdef CANNOT_CHANGE_MODE_CLASS
2488 struct subregs_of_mode_node
2490 unsigned int block;
2491 unsigned char modes[MAX_MACHINE_MODE];
2494 static htab_t subregs_of_mode;
2496 static hashval_t
2497 som_hash (const void *x)
2499 const struct subregs_of_mode_node *a = x;
2500 return a->block;
2503 static int
2504 som_eq (const void *x, const void *y)
2506 const struct subregs_of_mode_node *a = x;
2507 const struct subregs_of_mode_node *b = y;
2508 return a->block == b->block;
2512 static void
2513 record_subregs_of_mode (rtx subreg)
2515 struct subregs_of_mode_node dummy, *node;
2516 enum machine_mode mode;
2517 unsigned int regno;
2518 void **slot;
2520 if (!REG_P (SUBREG_REG (subreg)))
2521 return;
2523 regno = REGNO (SUBREG_REG (subreg));
2524 mode = GET_MODE (subreg);
2526 if (regno < FIRST_PSEUDO_REGISTER)
2527 return;
2529 dummy.block = regno & -8;
2530 slot = htab_find_slot_with_hash (subregs_of_mode, &dummy,
2531 dummy.block, INSERT);
2532 node = *slot;
2533 if (node == NULL)
2535 node = XCNEW (struct subregs_of_mode_node);
2536 node->block = regno & -8;
2537 *slot = node;
2540 node->modes[mode] |= 1 << (regno & 7);
2544 /* Call record_subregs_of_mode for all the subregs in X. */
2546 static void
2547 find_subregs_of_mode (rtx x)
2549 enum rtx_code code = GET_CODE (x);
2550 const char * const fmt = GET_RTX_FORMAT (code);
2551 int i;
2553 if (code == SUBREG)
2554 record_subregs_of_mode (x);
2556 /* Time for some deep diving. */
2557 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2559 if (fmt[i] == 'e')
2560 find_subregs_of_mode (XEXP (x, i));
2561 else if (fmt[i] == 'E')
2563 int j;
2564 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2565 find_subregs_of_mode (XVECEXP (x, i, j));
2570 static unsigned int
2571 init_subregs_of_mode (void)
2573 basic_block bb;
2574 rtx insn;
2576 if (subregs_of_mode)
2577 htab_empty (subregs_of_mode);
2578 else
2579 subregs_of_mode = htab_create (100, som_hash, som_eq, free);
2581 FOR_EACH_BB (bb)
2582 FOR_BB_INSNS (bb, insn)
2583 if (INSN_P (insn))
2584 find_subregs_of_mode (PATTERN (insn));
2586 return 0;
2590 /* Set bits in *USED which correspond to registers which can't change
2591 their mode from FROM to any mode in which REGNO was encountered. */
2593 void
2594 cannot_change_mode_set_regs (HARD_REG_SET *used, enum machine_mode from,
2595 unsigned int regno)
2597 struct subregs_of_mode_node dummy, *node;
2598 enum machine_mode to;
2599 unsigned char mask;
2600 unsigned int i;
2602 gcc_assert (subregs_of_mode);
2603 dummy.block = regno & -8;
2604 node = htab_find_with_hash (subregs_of_mode, &dummy, dummy.block);
2605 if (node == NULL)
2606 return;
2608 mask = 1 << (regno & 7);
2609 for (to = VOIDmode; to < NUM_MACHINE_MODES; to++)
2610 if (node->modes[to] & mask)
2611 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2612 if (!TEST_HARD_REG_BIT (*used, i)
2613 && REG_CANNOT_CHANGE_MODE_P (i, from, to))
2614 SET_HARD_REG_BIT (*used, i);
2617 /* Return 1 if REGNO has had an invalid mode change in CLASS from FROM
2618 mode. */
2620 bool
2621 invalid_mode_change_p (unsigned int regno,
2622 enum reg_class class ATTRIBUTE_UNUSED,
2623 enum machine_mode from)
2625 struct subregs_of_mode_node dummy, *node;
2626 enum machine_mode to;
2627 unsigned char mask;
2629 gcc_assert (subregs_of_mode);
2630 dummy.block = regno & -8;
2631 node = htab_find_with_hash (subregs_of_mode, &dummy, dummy.block);
2632 if (node == NULL)
2633 return false;
2635 mask = 1 << (regno & 7);
2636 for (to = VOIDmode; to < NUM_MACHINE_MODES; to++)
2637 if (node->modes[to] & mask)
2638 if (CANNOT_CHANGE_MODE_CLASS (from, to, class))
2639 return true;
2641 return false;
2644 static unsigned int
2645 finish_subregs_of_mode (void)
2647 htab_delete (subregs_of_mode);
2648 subregs_of_mode = 0;
2649 return 0;
2651 #else
2652 static unsigned int
2653 init_subregs_of_mode (void)
2655 return 0;
2657 static unsigned int
2658 finish_subregs_of_mode (void)
2660 return 0;
2663 #endif /* CANNOT_CHANGE_MODE_CLASS */
2665 static bool
2666 gate_subregs_of_mode_init (void)
2668 #ifdef CANNOT_CHANGE_MODE_CLASS
2669 return true;
2670 #else
2671 return false;
2672 #endif
2675 struct rtl_opt_pass pass_subregs_of_mode_init =
2678 RTL_PASS,
2679 "subregs_of_mode_init", /* name */
2680 gate_subregs_of_mode_init, /* gate */
2681 init_subregs_of_mode, /* execute */
2682 NULL, /* sub */
2683 NULL, /* next */
2684 0, /* static_pass_number */
2685 0, /* tv_id */
2686 0, /* properties_required */
2687 0, /* properties_provided */
2688 0, /* properties_destroyed */
2689 0, /* todo_flags_start */
2690 0 /* todo_flags_finish */
2694 struct rtl_opt_pass pass_subregs_of_mode_finish =
2697 RTL_PASS,
2698 "subregs_of_mode_finish", /* name */
2699 gate_subregs_of_mode_init, /* gate */
2700 finish_subregs_of_mode, /* execute */
2701 NULL, /* sub */
2702 NULL, /* next */
2703 0, /* static_pass_number */
2704 0, /* tv_id */
2705 0, /* properties_required */
2706 0, /* properties_provided */
2707 0, /* properties_destroyed */
2708 0, /* todo_flags_start */
2709 0 /* todo_flags_finish */
2715 #include "gt-regclass.h"