1 # Copyright
(C
) 1999-2023 Free Software Foundation
, Inc.
3 # This
program is free software
; you can redistribute it and
/or modify
4 # it under the terms of the GNU General Public License as published by
5 # the Free Software Foundation
; either version
3 of the License
, or
6 #
(at your option
) any later version.
8 # This
program is distributed in the hope that it will be useful
,
9 # but WITHOUT
ANY WARRANTY
; without even the implied warranty of
10 # MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the
11 # GNU General Public License
for more details.
13 # You should have received a copy of the GNU General Public License
14 # along with GCC
; see the file COPYING3.
If not see
15 #
<http
://www.gnu.org
/licenses
/>.
17 # Please email
any bugs
, comments
, and
/or additions to this file to
:
18 # gcc
-patches@gcc.gnu.org
20 # This file defines procs
for determining features supported by the target.
22 # Try to
compile the code given by CONTENTS into an output file of
23 # type TYPE
, where TYPE is as
for target_compile.
Return a list
24 # whose first element contains the compiler messages and whose
25 # second element is the
name of the output file.
27 # BASENAME is a prefix to use
for source and output files.
28 #
If ARGS is not empty
, its first element is a string that
29 # should be added to the command line.
31 # Assume by default that CONTENTS is C code.
32 # Otherwise
, code should contain
:
33 #
"/* Assembly" for assembly code,
36 #
"! Fortran" for Fortran code,
38 #
"// ObjC++" for ObjC++
41 # and
"(* Modula-2" for Modula-2
42 #
If the tool is ObjC
/ObjC
++ then we overide the extension to .m
/.mm to
43 # allow
for ObjC
/ObjC
++ specific flags.
45 proc check_compile
{basename type contents
args} {
47 verbose
"check_compile tool: $tool for $basename"
49 # Save additional_sources to avoid compiling testsuite
's sources
50 # against check_compile's source.
51 global additional_sources
52 if [info exists additional_sources
] {
53 set tmp_additional_sources
"$additional_sources"
54 set additional_sources
""
57 if { [llength $
args] > 0 } {
58 set options
[list
"additional_flags=[lindex $args 0]"]
62 # Silence
"command-line option [...] is valid for [...] but not for [...]"
63 # that we may easily run into here
, if more than one language is involved.
64 lappend options additional_flags
=-Wno
-complain
-wrong
-lang
66 switch -glob
-- $contents
{
67 "*/\\* Assembly*" { set src ${basename}[pid].S }
68 "*! Fortran*" { set src ${basename}[pid].f90 }
69 "*// C++*" { set src ${basename}[pid].cc }
70 "*// D*" { set src ${basename}[pid].d }
71 "*// ObjC++*" { set src ${basename}[pid].mm }
72 "*/\\* ObjC*" { set src ${basename}[pid].m }
73 "*// Go*" { set src ${basename}[pid].go }
74 "*// Rust*" { set src ${basename}[pid].rs }
75 "*(\\* Modula-2*" { set src ${basename}[pid].mod }
78 "objc" { set src ${basename}[pid].m }
79 "obj-c++" { set src ${basename}[pid].mm }
80 default
{ set src $
{basename
}[pid
].c
}
85 set compile_type $type
87 assembly
{ set output $
{basename
}[pid
].s
}
88 object
{ set output $
{basename
}[pid
].o
}
89 executable
{ set output $
{basename
}[pid
].exe
}
92 set output $
{basename
}[pid
].s
93 lappend options
"additional_flags=-fdump-$type"
94 set compile_type assembly
100 global compiler_flags
101 set save_compiler_flags $compiler_flags
102 set lines
[$
{tool
}_target_compile $src $output $compile_type
"$options"]
103 set compiler_flags $save_compiler_flags
106 set scan_output $output
107 # Don
't try folding this into the switch above; calling "glob" before the
108 # file is created won't work.
109 if [regexp
"rtl-(.*)" $type dummy rtl_type] {
110 set scan_output
"[glob $src.\[0-9\]\[0-9\]\[0-9\]r.$rtl_type]"
112 } elseif
[regexp
"tree-(.*)" $type dummy tree_type] {
113 set scan_output
"[glob $src.\[0-9\]\[0-9\]\[0-9\]t.$tree_type]"
117 # Restore additional_sources.
118 if [info exists additional_sources
] {
119 set additional_sources
"$tmp_additional_sources"
122 return [list $lines $scan_output
]
125 proc current_target_name
{ } {
127 if [info exists target_info
(target
,name)] {
128 set answer $target_info
(target
,name)
135 # Implement an effective
-target check
for property PROP by invoking
136 # the Tcl command
ARGS and seeing
if it returns true.
138 proc check_cached_effective_target
{ prop
args } {
141 set target
[current_target_name
]
142 if {![info exists et_cache
($prop
,$target
)]} {
143 verbose
"check_cached_effective_target $prop: checking $target" 2
144 if {[string is true
-strict $
args] ||
[string is false
-strict $
args]} {
145 error
{check_cached_effective_target condition already evaluated
; did you pass
[...
] instead of the expected
{...
}?
}
147 set code
[catch
{uplevel eval $
args} result
]
148 if {$code
!= 0 && $code
!= 2} {
149 return -code $code $result
151 set et_cache
($prop
,$target
) $result
154 set value $et_cache
($prop
,$target
)
155 verbose
"check_cached_effective_target $prop: returning $value for $target" 2
159 # Implements a version of check_cached_effective_target that also takes et_index
160 # into account when creating the
key for the
cache.
161 proc check_cached_effective_target_indexed
{ prop
args } {
163 set key "$et_index $prop"
164 verbose
"check_cached_effective_target_index $prop: returning $key" 2
166 return [check_cached_effective_target $
key [list uplevel eval $
args]]
169 # Clear effective
-target
cache. This is useful after testing
170 # effective
-target features and overriding TEST_ALWAYS_FLAGS and
/or
172 #
If one changes ALWAYS_CXXFLAGS or TEST_ALWAYS_FLAGS
then they should
173 #
do a clear_effective_target_cache at the end as the target
cache can
174 # make decisions based upon the flags
, and those decisions need to be
175 # redone when the flags change. An example of this is the
176 # asan_init
/asan_finish pair.
178 proc clear_effective_target_cache
{ } {
183 # Like check_compile
, but
delete the output file and
return true
if the
184 # compiler printed no messages.
185 proc check_no_compiler_messages_nocache
{args} {
186 set result
[eval check_compile $
args]
187 set lines
[lindex $result
0]
188 set output
[lindex $result
1]
189 remote_file build
delete $output
190 return [string match
"" $lines]
193 # Like check_no_compiler_messages_nocache
, but
cache the result.
194 # PROP is the
property we
're checking, and doubles as a prefix for
195 # temporary filenames.
196 proc check_no_compiler_messages {prop args} {
197 return [check_cached_effective_target $prop {
198 eval [list check_no_compiler_messages_nocache $prop] $args
202 # Like check_compile, but return true if the compiler printed no
203 # messages and if the contents of the output file satisfy PATTERN.
204 # If PATTERN has the form "!REGEXP", the contents satisfy it if they
205 # don't match regular expression REGEXP
, otherwise they satisfy it
206 #
if they
do match regular expression PATTERN.
(PATTERN can start
207 # with something like
"[!]" if the regular expression needs to match
208 #
"!" as the first character.)
210 #
Delete the output file before returning. The other arguments are
211 # as
for check_compile.
212 proc check_no_messages_and_pattern_nocache
{basename pattern
args} {
215 set result
[eval
[list check_compile $basename
] $
args]
216 set lines
[lindex $result
0]
217 set output
[lindex $result
1]
220 if { [string match
"" $lines] } {
221 set chan
[open
"$output"]
222 set invert
[regexp
{^
!(.
*)} $pattern dummy pattern
]
223 set ok
[expr
{ [regexp $pattern
[read $chan
]] != $invert
}]
227 remote_file build
delete $output
231 # Like check_no_messages_and_pattern_nocache
, but
cache the result.
232 # PROP is the
property we
're checking, and doubles as a prefix for
233 # temporary filenames.
234 proc check_no_messages_and_pattern {prop pattern args} {
235 return [check_cached_effective_target $prop {
236 eval [list check_no_messages_and_pattern_nocache $prop $pattern] $args
240 # Try to compile and run an executable from code CONTENTS. Return true
241 # if the compiler reports no messages and if execution "passes" in the
242 # usual DejaGNU sense. The arguments are as for check_compile, with
243 # TYPE implicitly being "executable".
244 proc check_runtime_nocache {basename contents args} {
247 set result [eval [list check_compile $basename executable $contents] $args]
248 set lines [lindex $result 0]
249 set output [lindex $result 1]
252 if { [string match "" $lines] } {
253 # No error messages, everything is OK.
254 set result [remote_load target "./$output" "" ""]
255 set status [lindex $result 0]
256 verbose "check_runtime_nocache $basename: status is <$status>" 2
257 if { $status == "pass" } {
261 remote_file build delete $output
265 # Like check_runtime_nocache, but cache the result. PROP is the
266 # property we're checking
, and doubles as a prefix
for temporary
268 proc check_runtime
{prop
args} {
271 return [check_cached_effective_target $prop
{
272 eval
[list check_runtime_nocache $prop
] $
args
276 #
Return 1 if GCC was configured with $pattern.
277 proc check_configured_with
{ pattern
} {
280 set options
[list
"additional_flags=-v"]
281 set gcc_output
[$
{tool
}_target_compile
"" "" "none" $options]
282 if { [ regexp
"Configured with: \[^\n\]*$pattern" $gcc_output ] } {
283 verbose
"Matched: $pattern" 2
287 verbose
"Failed to match: $pattern" 2
291 ###############################
292 # proc check_weak_available
{ }
293 ###############################
295 # weak symbols are only supported in some configs
/object formats
296 # this proc returns
1 if they
're supported, 0 if they're not
, or
-1 if unsure
298 proc check_weak_available
{ } {
301 # All mips targets should support it
303 if { [ string first
"mips" $target_cpu ] >= 0 } {
307 # All AIX targets should support it
309 if { [istarget
*-*-aix
*] } {
313 # All solaris2 targets should support it
315 if { [istarget
*-*-solaris2
*] } {
319 # Windows targets Cygwin and MingW32 support it
321 if { [istarget
*-*-cygwin
*] ||
[istarget
*-*-mingw
*] } {
325 # nvptx
(nearly
) supports it
327 if { [istarget nvptx
-*-*] } {
331 # pdp11 doesn
't support it
333 if { [istarget pdp11*-*-*] } {
337 # VxWorks hardly supports it (vx7 RTPs only)
339 if { [istarget *-*-vxworks*] } {
343 # ELF and ECOFF support it. a.out does with gas/gld but may also with
344 # other linkers, so we should try it
346 set objformat [gcc_target_object_format]
354 unknown { return -1 }
359 # return options to add to enable weak undefined symbols.
361 proc add_options_for_weak_undefined { flags } {
362 if { [istarget *-*-darwin*] } {
363 lappend flags "-Wl,-undefined,dynamic_lookup"
364 if { [istarget *-*-darwin\[89\]*] } {
365 lappend flags "-Wl,-flat_namespace"
371 # return 1 if weak undefined symbols are supported.
373 proc check_effective_target_weak_undefined { } {
374 if { [istarget hppa*-*-hpux*] } {
377 return [check_runtime weak_undefined {
378 extern void foo () __attribute__((weak));
379 int main (void) { if (foo) return 1; return 0; }
380 } [add_options_for_weak_undefined ""]]
383 ###############################
384 # proc check_weak_override_available { }
385 ###############################
387 # Like check_weak_available, but return 0 if weak symbol definitions
388 # cannot be overridden.
390 proc check_weak_override_available { } {
391 if { [istarget *-*-mingw*] } {
394 return [check_weak_available]
397 # Return 1 if VMA is equal to LMA for the .data section, 0
398 # otherwise. Cache the result.
400 proc check_effective_target_vma_equals_lma { } {
403 return [check_cached_effective_target vma_equals_lma {
404 set src vma_equals_lma[pid].c
405 set exe vma_equals_lma[pid].exe
406 verbose "check_effective_target_vma_equals_lma compiling testfile $src" 2
407 set f [open $src "w"]
408 puts $f "#ifdef __cplusplus\nextern \"C\"\n#endif\n"
409 puts $f "int foo = 42; void main() {}"
411 set lines [${tool}_target_compile $src $exe executable ""]
414 if [string match "" $lines] then {
417 set objdump_name [find_binutils_prog objdump]
418 set output [remote_exec host "$objdump_name" "--section-headers --section=.data $exe"]
419 set output [lindex $output 1]
421 remote_file build delete $exe
423 # Example output of objdump:
424 #vma_equals_lma9059.exe: file format elf32-littlearm
427 #Idx Name Size VMA LMA File off Algn
428 # 6 .data 00000558 20000000 08002658 00020000 2**3
429 # CONTENTS, ALLOC, LOAD, DATA
431 # Capture LMA and VMA columns for .data section
432 if ![ regexp {\d*\d+\s+\.data\s+\d+\s+(\d+)\s+(\d+)} $output dummy vma lma ] {
433 verbose "Could not parse objdump output" 2
436 return [string equal $vma $lma]
439 remote_file build delete $exe
440 verbose "Could not determine if VMA is equal to LMA. Assuming not equal." 2
446 # The "noinit" attribute is only supported by some targets.
447 # This proc returns 1 if it's supported
, 0 if it
's not.
449 proc check_effective_target_noinit { } {
450 if { [istarget arm*-*-eabi]
451 || [istarget msp430-*-*] } {
458 # The "persistent" attribute is only supported by some targets.
459 # This proc returns 1 if it's supported
, 0 if it
's not.
461 proc check_effective_target_persistent { } {
462 if { [istarget arm*-*-eabi]
463 || [istarget msp430-*-*] } {
470 ###############################
471 # proc check_visibility_available { what_kind }
472 ###############################
474 # The visibility attribute is only support in some object formats
475 # This proc returns 1 if it is supported, 0 if not.
476 # The argument is the kind of visibility, default/protected/hidden/internal.
478 proc check_visibility_available { what_kind } {
479 if [string match "" $what_kind] { set what_kind "hidden" }
481 return [check_no_compiler_messages visibility_available_$what_kind object "
482 void f() __attribute__((visibility(\"$what_kind\")));
487 ###############################
488 # proc check_alias_available { }
489 ###############################
491 # Determine if the target toolchain supports the alias attribute.
493 # Returns 2 if the target supports aliases. Returns 1 if the target
494 # only supports weak aliased. Returns 0 if the target does not
495 # support aliases at all. Returns -1 if support for aliases could not
498 proc check_alias_available { } {
501 return [check_cached_effective_target alias_available {
504 verbose "check_alias_available compiling testfile $src" 2
505 set f [open $src "w"]
506 # Compile a small test program. The definition of "g" is
507 # necessary to keep the Solaris assembler from complaining
509 puts $f "#ifdef __cplusplus\nextern \"C\"\n#endif\n"
510 puts $f "void g() {} void f() __attribute__((alias(\"g\")));"
512 set lines [${tool}_target_compile $src $obj object ""]
514 remote_file build delete $obj
516 if [string match "" $lines] then {
517 # No error messages, everything is OK.
520 if [regexp "alias definitions not supported" $lines] {
521 verbose "check_alias_available target does not support aliases" 2
523 set objformat [gcc_target_object_format]
525 if { $objformat == "elf" } {
526 verbose "check_alias_available but target uses ELF format, so it ought to" 2
532 if [regexp "only weak aliases are supported" $lines] {
533 verbose "check_alias_available target supports only weak aliases" 2
543 # Returns 1 if the target toolchain supports strong aliases, 0 otherwise.
545 proc check_effective_target_alias { } {
546 if { [check_alias_available] < 2 } {
553 # Returns 1 if the target uses the ELF object format, 0 otherwise.
555 proc check_effective_target_elf { } {
556 if { [gcc_target_object_format] == "elf" } {
563 # Returns 1 if the target toolchain supports ifunc, 0 otherwise.
565 proc check_ifunc_available { } {
566 return [check_no_compiler_messages ifunc_available object {
571 typedef void F (void);
572 F* g (void) { return &f_; }
573 void f () __attribute__ ((ifunc ("g")));
580 # Returns true if --gc-sections is supported on the target.
582 proc check_gc_sections_available { } {
585 return [check_cached_effective_target gc_sections_available {
586 # Some targets don't support gc
-sections despite whatever
's
587 # advertised by ld's options.
588 if { [istarget alpha
*-*-*]
589 ||
[istarget ia64
-*-*] } {
593 # elf2flt uses
-q
(--emit
-relocs
), which is incompatible with
595 if { [board_info target
exists ldflags
]
596 && [regexp
" -elf2flt\[ =\]" " [board_info target ldflags] "] } {
600 # VxWorks kernel modules are relocatable objects linked with
-r
,
601 #
while RTP executables are linked with
-q
(--emit
-relocs
).
602 # Both of these options are incompatible with
--gc
-sections.
603 if { [istarget
*-*-vxworks
*] } {
607 # Check
if the
ld used by gcc supports
--gc
-sections.
608 set options
[list
"additional_flags=-print-prog-name=ld"]
609 set gcc_ld
[lindex
[$
{tool
}_target_compile
"" "" "none" $options] 0]
610 set ld_output
[remote_exec host
"$gcc_ld" "--help"]
611 if { [ string first
"--gc-sections" $ld_output ] >= 0 } {
619 # Returns
1 if "dot" is supported on the host.
621 proc check_dot_available
{ } {
622 verbose
"check_dot_available" 2
624 set status [remote_exec host
"dot" "-V"]
625 verbose
" status: $status" 2
626 if { [lindex $
status 0] != 0 } {
632 #
Return 1 if according to target_info struct and explicit target list
633 # target is supposed to support trampolines.
635 proc check_effective_target_trampolines
{ } {
636 if [target_info
exists gcc
,no_trampolines
] {
639 if { [istarget avr
-*-*]
640 ||
[istarget msp430
-*-*]
641 ||
[istarget nvptx
-*-*]
642 ||
[istarget pru
-*-*]
643 ||
[istarget bpf
-*-*] } {
649 #
Return 1 if target has limited stack size.
651 proc check_effective_target_stack_size
{ } {
652 #
For nvptx target
, stack size limits are relevant
for execution only.
653 if { [istarget nvptx
-*-*] } {
654 # Find
'dg-do-what' in an outer frame.
657 upvar $level dg
-do-what dg
-do-what
658 if [info exists dg
-do-what
] then break
661 verbose
"check_effective_target_stack_size: found dg-do-what at level $level" 2
663 if { ![string equal
[lindex $
{dg
-do-what
} 0] run
] } {
668 if [target_info
exists gcc
,stack_size
] {
674 #
Return the value attribute of an effective target
, otherwise
return 0.
676 proc dg
-effective
-target
-value
{ effective_target
} {
677 if { "$effective_target" == "stack_size" } {
678 if [check_effective_target_stack_size
] {
679 return [target_info gcc
,stack_size
]
686 #
Return 1 if signal.h is supported.
688 proc check_effective_target_signal
{ } {
689 if [target_info
exists gcc
,signal_suppress
] {
695 #
Return 1 if according to target_info struct and explicit target list
696 # target disables
-fdelete
-null
-pointer
-checks. Targets should
return 0
697 #
if they simply default to
-fno
-delete-null
-pointer
-checks but obey
698 #
-fdelete
-null
-pointer
-checks when passed explicitly
(and tests that
699 # depend
on this option should
do that
).
701 proc check_effective_target_keeps_null_pointer_checks
{ } {
702 if [target_info
exists keeps_null_pointer_checks
] {
705 if { [istarget msp430
-*-*]
706 ||
[istarget avr
-*-*] } {
712 #
Return the autofdo profile wrapper
714 # Linux by default allows
516KB of perf event buffers
715 # in
/proc
/sys
/kernel
/perf_event_mlock_kb
716 # Each individual perf tries to grab it
717 # This causes problems with parallel test suite runs. Instead
718 #
limit us to
8 pages
(32K
), which should be good enough
719 #
for the small test programs. With the default settings
720 # this allows parallelism of
16 and higher of parallel gcc
-auto
-profile
721 proc profopt
-perf
-wrapper
{ } {
723 return "$srcdir/../config/i386/gcc-auto-profile --all -m8 "
726 #
Return true
if profiling is supported
on the target.
728 proc check_profiling_available
{ test_what
} {
729 verbose
"Profiling argument is <$test_what>" 1
731 # These conditions depend
on the
argument so examine them before
732 # looking at the
cache variable.
734 # Tree profiling requires TLS runtime support.
735 if { $test_what
== "-fprofile-generate" } {
736 if { ![check_effective_target_tls_runtime
] } {
741 if { $test_what
== "-fauto-profile" } {
742 if { !([istarget i?
86-*-linux
*] ||
[istarget x86_64
-*-linux
*]) } {
743 verbose
"autofdo only supported on linux"
746 # not cross compiling?
748 verbose
"autofdo not supported for non native builds"
751 set event
[profopt
-perf
-wrapper
]
753 verbose
"autofdo not supported"
757 set status [remote_exec host
"$srcdir/../config/i386/gcc-auto-profile" "-m8 true -v >/dev/null"]
758 if { [lindex $
status 0] != 0 } {
759 verbose
"autofdo not supported because perf does not work"
763 # no good way to check this in advance
-- check later instead.
764 #
set status [remote_exec host
"create_gcov" "2>/dev/null"]
765 #
if { [lindex $
status 0] != 255 } {
766 # verbose
"autofdo not supported due to missing create_gcov"
771 # Support
for -p
on solaris2 relies
on mcrt1.o which comes with the
772 # vendor compiler. We cannot reliably predict the directory where the
773 # vendor compiler
(and thus mcrt1.o
) is installed so we can
't
774 # necessarily find mcrt1.o even if we have it.
775 if { [istarget *-*-solaris2*] && $test_what == "-p" } {
779 # We don't yet support profiling
for MIPS16.
780 if { [istarget mips
*-*-*]
781 && ![check_effective_target_nomips16
]
782 && ($test_what
== "-p" || $test_what == "-pg") } {
786 # MinGW does not support
-p.
787 if { [istarget
*-*-mingw
*] && $test_what
== "-p" } {
791 # cygwin does not support
-p.
792 if { [istarget
*-*-cygwin
*] && $test_what
== "-p" } {
796 # uClibc does not have gcrt1.o.
797 if { [check_effective_target_uclibc
]
798 && ($test_what
== "-p" || $test_what == "-pg") } {
802 # Now examine the
cache variable.
803 set profiling_working \
804 [check_cached_effective_target profiling_available
{
805 # Some targets don
't have any implementation of __bb_init_func or are
806 # missing other needed machinery.
807 if {[istarget aarch64*-*-elf]
808 || [istarget am3*-*-linux*]
809 || [istarget amdgcn-*-*]
810 || [istarget arm*-*-eabi*]
811 || [istarget arm*-*-elf]
812 || [istarget arm*-*-symbianelf*]
813 || [istarget avr-*-*]
814 || [istarget bfin-*-*]
815 || [istarget cris-*-*]
816 || [istarget csky-*-elf*]
817 || [istarget fido-*-elf]
818 || [istarget h8300-*-*]
819 || [istarget lm32-*-*]
820 || [istarget m32c-*-elf]
821 || [istarget m68k-*-elf]
822 || [istarget m68k-*-uclinux*]
823 || [istarget mips*-*-elf*]
824 || [istarget mmix-*-*]
825 || [istarget mn10300-*-elf*]
826 || [istarget moxie-*-elf*]
827 || [istarget msp430-*-*]
828 || [istarget nds32*-*-elf]
829 || [istarget nios2-*-elf]
830 || [istarget nvptx-*-*]
831 || [istarget powerpc-*-eabi*]
832 || [istarget powerpc-*-elf]
833 || [istarget pru-*-*]
835 || [istarget tic6x-*-elf]
836 || [istarget visium-*-*]
837 || [istarget xstormy16-*]
838 || [istarget xtensa*-*-elf]
839 || [istarget *-*-rtems*]
840 || [istarget *-*-vxworks*] } {
847 # -pg link test result can't be cached since it may change between
849 if { $profiling_working
== 1
850 && ![check_no_compiler_messages_nocache profiling executable
{
851 int main
() { return 0; } } "-pg"] } {
852 set profiling_working
0
855 return $profiling_working
858 # Check to see
if a target is
"freestanding". This is as per the definition
859 # in Section
4 of C99 standard. Effectively
, it is a target which supports no
860 # extra headers or libraries other than what is considered essential.
861 proc check_effective_target_freestanding
{ } {
862 if { [istarget nvptx
-*-*] } {
868 # Check to see that file I
/O functions are available.
869 proc check_effective_target_fileio
{ } {
870 return [check_no_compiler_messages fileio_available executable
{
873 char
*n
= tmpnam
(NULL
);
874 FILE
*f
= fopen
(n
, "w");
881 #
Return 1 if target has packed layout of structure members by
882 # default
, 0 otherwise. Note that this is slightly different than
883 # whether the target has
"natural alignment": both attributes may be
886 proc check_effective_target_default_packed
{ } {
887 return [check_no_compiler_messages default_packed assembly
{
888 struct x
{ char a
; long b
; } c
;
889 int s
[sizeof
(c
) == sizeof
(char
) + sizeof
(long
) ?
1 : -1];
893 #
Return 1 if target has PCC_BITFIELD_TYPE_MATTERS defined. See
894 # documentation
, where the test also comes from.
896 proc check_effective_target_pcc_bitfield_type_matters
{ } {
897 # PCC_BITFIELD_TYPE_MATTERS isn
't just about unnamed or empty
898 # bitfields, but let's stick to the example code from the docs.
899 return [check_no_compiler_messages pcc_bitfield_type_matters assembly
{
900 struct foo1
{ char x
; char
:0; char y
; };
901 struct foo2
{ char x
; int :0; char y
; };
902 int s
[sizeof
(struct foo1
) != sizeof
(struct foo2
) ?
1 : -1];
906 # Add to FLAGS all the target
-specific flags needed to use thread
-local storage.
908 proc add_options_for_tls
{ flags
} {
909 #
On AIX
, __tls_get_addr
/___tls_get_addr only lives in
910 # libthread
, so always pass
-pthread
for native TLS.
911 # Need to duplicate native TLS check from
912 # check_effective_target_tls_native to avoid recursion.
913 if { ([istarget powerpc
-ibm
-aix
*]) &&
914 [check_no_messages_and_pattern tls_native
"!emutls" assembly {
916 int f
(void
) { return i
; }
917 void g
(int j
) { i
= j
; }
919 return "-pthread [g++_link_flags [get_multilibs "-pthread"] ] $flags "
924 #
Return 1 if indirect jumps are supported
, 0 otherwise.
926 proc check_effective_target_indirect_jumps
{} {
927 if { [istarget nvptx
-*-*] ||
[istarget bpf
-*-*] } {
933 #
Return 1 if nonlocal
goto is supported
, 0 otherwise.
935 proc check_effective_target_nonlocal_goto
{} {
936 if { [istarget nvptx
-*-*] ||
[istarget bpf
-*-*] } {
942 #
Return 1 if global constructors are supported
, 0 otherwise.
944 proc check_effective_target_global_constructor
{} {
945 if { [istarget nvptx
-*-*]
946 ||
[istarget bpf
-*-*] } {
952 #
Return 1 if taking label
values is supported
, 0 otherwise.
954 proc check_effective_target_label_values
{} {
955 if { [istarget nvptx
-*-*] ||
[target_info
exists gcc
,no_label_values
] } {
962 #
Return 1 if builtin_return_address and builtin_frame_address are
963 # supported
, 0 otherwise.
965 proc check_effective_target_return_address
{} {
966 if { [istarget nvptx
-*-*] } {
969 # No notion of
return address in eBPF.
970 if { [istarget bpf
-*-*] } {
973 # It could be supported
on amdgcn
, but isn
't yet.
974 if { [istarget amdgcn*-*-*] } {
980 # Return 1 if the assembler does not verify function types against
981 # calls, 0 otherwise. Such verification will typically show up problems
982 # with K&R C function declarations.
984 proc check_effective_target_untyped_assembly {} {
985 if { [istarget nvptx-*-*] } {
991 # Return 1 if alloca is supported, 0 otherwise.
993 proc check_effective_target_alloca {} {
994 if { [istarget bpf-*-*] } {
997 if { [istarget nvptx-*-*] } {
998 return [check_no_compiler_messages alloca assembly {
1000 void g (int n) { f (__builtin_alloca (n)); }
1006 # Return 1 if thread local storage (TLS) is supported, 0 otherwise.
1008 proc check_effective_target_tls {} {
1009 return [check_no_compiler_messages tls assembly {
1011 int f (void) { return i; }
1012 void g (int j) { i = j; }
1016 # Return 1 if *native* thread local storage (TLS) is supported, 0 otherwise.
1018 proc check_effective_target_tls_native {} {
1019 # VxWorks uses emulated TLS machinery, but with non-standard helper
1020 # functions, so we fail to automatically detect it.
1021 if { [istarget *-*-vxworks*] } {
1025 return [check_no_messages_and_pattern tls_native "!emutls" assembly {
1027 int f (void) { return i; }
1028 void g (int j) { i = j; }
1032 # Return 1 if *emulated* thread local storage (TLS) is supported, 0 otherwise.
1034 proc check_effective_target_tls_emulated {} {
1035 # VxWorks uses emulated TLS machinery, but with non-standard helper
1036 # functions, so we fail to automatically detect it.
1037 if { [istarget *-*-vxworks*] } {
1041 return [check_no_messages_and_pattern tls_emulated "emutls" assembly {
1043 int f (void) { return i; }
1044 void g (int j) { i = j; }
1048 # Return 1 if TLS executables can run correctly, 0 otherwise.
1050 proc check_effective_target_tls_runtime {} {
1051 return [check_runtime tls_runtime {
1052 __thread int thr __attribute__((tls_model("global-dynamic"))) = 0;
1053 int main (void) { return thr; }
1054 } [add_options_for_tls ""]]
1057 # Return 1 if atomic compare-and-swap is supported on 'int'
1059 proc check_effective_target_cas_char {} {
1060 return [check_no_compiler_messages cas_char assembly {
1061 #ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
1067 proc check_effective_target_cas_int {} {
1068 return [check_no_compiler_messages cas_int assembly {
1069 #if __INT_MAX__ == 0x7fff && __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2
1071 #elif __INT_MAX__ == 0x7fffffff && __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
1079 # Return 1 if -ffunction-sections is supported, 0 otherwise.
1081 proc check_effective_target_function_sections {} {
1082 # Darwin has its own scheme and silently accepts -ffunction-sections.
1083 if { [istarget *-*-darwin*] } {
1087 return [check_no_compiler_messages functionsections assembly {
1089 } "-ffunction-sections"]
1092 # Return 1 if instruction scheduling is available, 0 otherwise.
1094 proc check_effective_target_scheduling {} {
1095 return [check_no_compiler_messages scheduling object {
1097 } "-fschedule-insns"]
1100 # Return 1 if trapping arithmetic is available, 0 otherwise.
1102 proc check_effective_target_trapping {} {
1103 return [check_no_compiler_messages trapping object {
1104 int add (int a, int b) { return a + b; }
1108 # Return 1 if compilation with -fgraphite is error-free for trivial
1109 # code, 0 otherwise.
1111 proc check_effective_target_fgraphite {} {
1112 return [check_no_compiler_messages fgraphite object {
1117 # Return 1 if compiled with --enable-offload-targets=
1118 # This affects host compilation as ENABLE_OFFLOAD then evaluates to true.
1119 proc check_effective_target_offloading_enabled {} {
1120 return [check_configured_with "--enable-offload-targets"]
1123 # Return 1 if compilation with -fopenacc is error-free for trivial
1124 # code, 0 otherwise.
1126 proc check_effective_target_fopenacc {} {
1127 # nvptx/amdgcn can be built with the device-side bits of openacc, but it
1128 # does not make sense to test it as an openacc host.
1129 if [istarget nvptx-*-*] { return 0 }
1130 if [istarget amdgcn-*-*] { return 0 }
1132 return [check_no_compiler_messages fopenacc object {
1137 # Return 1 if compilation with -fopenmp is error-free for trivial
1138 # code, 0 otherwise.
1140 proc check_effective_target_fopenmp {} {
1141 # nvptx/amdgcn can be built with the device-side bits of libgomp, but it
1142 # does not make sense to test it as an openmp host.
1143 if [istarget nvptx-*-*] { return 0 }
1144 if [istarget amdgcn-*-*] { return 0 }
1146 return [check_no_compiler_messages fopenmp object {
1151 # Return 1 if compilation with -fgnu-tm is error-free for trivial
1152 # code, 0 otherwise.
1154 proc check_effective_target_fgnu_tm {} {
1155 return [check_no_compiler_messages fgnu_tm object {
1160 # Return 1 if the target supports mmap, 0 otherwise.
1162 proc check_effective_target_mmap {} {
1163 return [check_function_available "mmap"]
1166 # Return 1 if the target supports sysconf, 0 otherwise.
1168 proc check_effective_target_sysconf {} {
1169 # VxWorks has sysconf in rtp mode only, but our way to test can't
1170 # tell kernel
mode doesn
't, as we're doing partial links
for
1171 # kernel modules. We can tell by checking
for a declaration
, or
1172 #
for some sysconf parm
, because configurations that don
't offer
1173 # sysconf don't have either.
1174 if { [istarget
*-*-vxworks
*] } {
1175 return [check_no_compiler_messages sysconfdecl assembly
{
1177 int f
() { return sysconf
(_SC_PAGESIZE
); }
1180 return [check_function_available
"sysconf"]
1183 #
Return 1 if the target supports dlopen
, 0 otherwise.
1184 proc check_effective_target_dlopen
{} {
1185 return [check_no_compiler_messages dlopen executable
{
1187 int main
(void
) { dlopen
("dummy.so", RTLD_NOW); }
1188 } [add_options_for_dlopen
""]]
1191 proc add_options_for_dlopen
{ flags
} {
1192 return "$flags -ldl"
1195 #
Return 1 if the target supports clone
, 0 otherwise.
1196 proc check_effective_target_clone
{} {
1197 return [check_function_available
"clone"]
1200 #
Return 1 if the target supports posix_memalign
, 0 otherwise.
1201 proc check_effective_target_posix_memalign
{} {
1202 if { [istarget
*-*-vxworks
*] } {
1203 # VxWorks doesn
't have posix_memalign but our way to test
1204 # can't tell as we
're doing partial links for kernel modules.
1207 return [check_function_available "posix_memalign"]
1210 # Return 1 if the target supports setrlimit, 0 otherwise.
1211 proc check_effective_target_setrlimit {} {
1212 # Darwin has non-posix compliant RLIMIT_AS
1213 if { [istarget *-*-darwin*] } {
1216 return [check_function_available "setrlimit"]
1219 # Return 1 if the target supports gettimeofday, 0 otherwise.
1220 proc check_effective_target_gettimeofday {} {
1221 return [check_function_available "gettimeofday"]
1224 # Return 1 if the target supports swapcontext, 0 otherwise.
1225 proc check_effective_target_swapcontext {} {
1226 return [check_no_compiler_messages swapcontext executable {
1227 #include <ucontext.h>
1230 ucontext_t orig_context,child_context;
1231 if (swapcontext(&child_context, &orig_context) < 0) { }
1236 # Return 1 if the target supports POSIX threads, 0 otherwise.
1237 proc check_effective_target_pthread {} {
1238 return [check_no_compiler_messages pthread object {
1239 #include <pthread.h>
1244 # Return 1 if the target supports both Unix and internet sockets, 0 otherwise.
1245 proc check_effective_target_sockets {} {
1246 return [check_no_compiler_messages socket executable {
1247 #include <sys/socket.h>
1249 #include <netinet/in.h>
1251 socket(AF_UNIX, SOCK_STREAM, 0);
1252 socket(AF_INET, SOCK_DGRAM, 0);
1258 # Return 1 if compilation with -mpe-aligned-commons is error-free
1259 # for trivial code, 0 otherwise.
1261 proc check_effective_target_pe_aligned_commons {} {
1262 if { [istarget *-*-cygwin*] || [istarget *-*-mingw*] } {
1263 return [check_no_compiler_messages pe_aligned_commons object {
1265 } "-mpe-aligned-commons"]
1270 # Return 1 if the target supports -static
1271 proc check_effective_target_static {} {
1272 if { [istarget arm*-*-uclinuxfdpiceabi] } {
1275 return [check_no_compiler_messages static executable {
1276 int main (void) { return 0; }
1280 # Return 1 if the target supports -fstack-protector
1281 proc check_effective_target_fstack_protector {} {
1282 if { [istarget hppa*-*-*] } {
1285 return [check_runtime fstack_protector {
1287 int main (int argc, char *argv[]) {
1289 return !strcpy (buf, strrchr (argv[0], '/'));
1291 } "-fstack-protector"]
1294 # Return 1 if the target supports -fstack-check or -fstack-check=$stack_kind
1295 proc check_stack_check_available { stack_kind } {
1296 if [string match "" $stack_kind] then {
1297 set stack_opt "-fstack-check"
1298 } else { set stack_opt "-fstack-check=$stack_kind" }
1300 return [check_no_compiler_messages stack_check_$stack_kind executable {
1301 int main (void) { return 0; }
1305 # Return 1 if compilation with -freorder-blocks-and-partition is error-free
1306 # for trivial code, 0 otherwise. As some targets (ARM for example) only
1307 # warn when -fprofile-use is also supplied we test that combination too.
1309 proc check_effective_target_freorder {} {
1310 if { [check_no_compiler_messages freorder object {
1312 } "-freorder-blocks-and-partition"]
1313 && [check_no_compiler_messages fprofile_use_freorder object {
1315 } "-fprofile-use -freorder-blocks-and-partition -Wno-missing-profile"] } {
1321 # Return 1 if -fpic and -fPIC are supported, as in no warnings or errors
1322 # emitted, 0 otherwise. Whether a shared library can actually be built is
1323 # out of scope for this test.
1325 proc check_effective_target_fpic { } {
1326 # Note that M68K has a multilib that supports -fpic but not
1327 # -fPIC, so we need to check both. We test with a program that
1328 # requires GOT references.
1329 foreach arg {fpic fPIC} {
1330 if [check_no_compiler_messages $arg object {
1331 extern int foo (void); extern int bar;
1332 int baz (void) { return foo () + bar; }
1340 # On AArch64, if -fpic is not supported, then we will fall back to -fPIC
1341 # silently. So, we can't rely
on above
"check_effective_target_fpic" as it
1342 # assumes compiler will give warning
if -fpic not supported. Here we check
1343 # whether binutils supports those new
-fpic relocation modifiers
, and assume
1344 #
-fpic is supported
if there is binutils support. GCC configuration will
1345 # enable
-fpic
for AArch64 in this case.
1347 #
"check_effective_target_aarch64_small_fpic" is dedicated for checking small
1348 # memory
model -fpic relocation types.
1350 proc check_effective_target_aarch64_small_fpic
{ } {
1351 if { [istarget aarch64
*-*-*] } {
1352 return [check_no_compiler_messages aarch64_small_fpic object
{
1353 void foo
(void
) { asm
("ldr x0, [x2, #:gotpage_lo15:globalsym]"); }
1360 #
On AArch64
, instruction sequence
for TLS LE under
-mtls
-size
=32 will utilize
1361 # the relocation modifier
"tprel_g0_nc" together with MOVK, it's only supported
1362 # in binutils since
2015-03-04 as PR gas
/17843.
1364 # This test directive make sure binutils support all features needed by TLS LE
1365 # under
-mtls
-size
=32 on AArch64.
1367 proc check_effective_target_aarch64_tlsle32
{ } {
1368 if { [istarget aarch64
*-*-*] } {
1369 return [check_no_compiler_messages aarch64_tlsle32 object
{
1370 void foo
(void
) { asm
("movk x1,#:tprel_g0_nc:t1"); }
1377 #
Return 1 if -shared is supported
, as in no warnings or errors
1378 # emitted
, 0 otherwise.
1380 proc check_effective_target_shared
{ } {
1381 # Note that M68K has a multilib that supports
-fpic but not
1382 #
-fPIC
, so we need to check both. We test with a
program that
1383 # requires GOT references.
1384 return [check_no_compiler_messages shared executable
{
1385 extern
int foo
(void
); extern
int bar
;
1386 int baz
(void
) { return foo
() + bar
; }
1390 #
Return 1 if -pie
, -fpie and
-fPIE are supported
, 0 otherwise.
1392 proc check_effective_target_pie
{ } {
1393 if { [istarget
*-*-darwin\
[912\
]*]
1394 ||
[istarget
*-*-dragonfly
*]
1395 ||
[istarget
*-*-freebsd
*]
1396 ||
[istarget
*-*-linux
*]
1397 ||
[istarget arm
*-*-uclinuxfdpiceabi
]
1398 ||
[istarget
*-*-gnu
*]
1399 ||
[istarget
*-*-amdhsa
]} {
1402 if { [istarget
*-*-solaris2.1\
[1-9\
]*] } {
1403 # Full PIE support was added in Solaris
11.3, but gcc errors out
1404 #
if missing
, so check
for that.
1405 return [check_no_compiler_messages pie executable
{
1406 int main
(void
) { return 0; }
1412 #
Return true
if the target supports
-mpaired
-single
(as used
on MIPS
).
1414 proc check_effective_target_mpaired_single
{ args } {
1415 return [check_no_compiler_messages mpaired_single object
{
1420 #
Return true
if the target has access to FPU instructions.
1422 proc check_effective_target_hard_float
{ } {
1423 # This should work
on cores that only have single
-precision
,
1424 # and should also correctly handle legacy cores that had thumb1 and
1425 # lacked FP support
for that
, but had it in Arm state.
1426 if { [istarget arm
*-*-*] } {
1427 return [check_no_compiler_messages hard_float assembly
{
1429 #error __arm_soft_float
1434 if { [istarget loongarch
*-*-*] } {
1435 return [check_no_compiler_messages hard_float assembly
{
1436 #
if (defined __loongarch_soft_float
)
1437 #error __loongarch_soft_float
1442 if { [istarget mips
*-*-*] } {
1443 return [check_no_compiler_messages hard_float assembly
{
1444 #
if (defined __mips_soft_float || defined __mips16
)
1445 #error __mips_soft_float || __mips16
1450 # This proc is actually checking the availabilty of FPU
1451 # support
for doubles
, so
on the RX we must fail
if the
1452 #
64-bit double multilib has been selected.
1453 if { [istarget rx
-*-*] } {
1455 #
return [check_no_compiler_messages hard_float assembly
{
1456 #
if defined __RX_64_BIT_DOUBLES__
1457 #error __RX_64_BIT_DOUBLES__
1462 # The generic test doesn
't work for C-SKY because some cores have
1463 # hard float for single precision only.
1464 if { [istarget csky*-*-*] } {
1465 return [check_no_compiler_messages hard_float assembly {
1466 #if defined __csky_soft_float__
1467 #error __csky_soft_float__
1472 # The generic test equates hard_float with "no call for adding doubles".
1473 return [check_no_messages_and_pattern hard_float "!\\(call" rtl-expand {
1474 double a (double b, double c) { return b + c; }
1478 # Return true if the target is a 64-bit MIPS target.
1480 proc check_effective_target_mips64 { } {
1481 return [check_no_compiler_messages mips64 assembly {
1488 # Return true if the target is a MIPS target that does not produce
1491 proc check_effective_target_nomips16 { } {
1492 return [check_no_compiler_messages nomips16 object {
1496 /* A cheap way of testing for -mflip-mips16. */
1497 void foo (void) { asm ("addiu $20,$20,1"); }
1498 void bar (void) { asm ("addiu $20,$20,1"); }
1503 # Add the options needed for MIPS16 function attributes. At the moment,
1504 # we don't support MIPS16 PIC.
1506 proc add_options_for_mips16_attribute
{ flags
} {
1507 return "$flags -mno-abicalls -fno-pic -DMIPS16=__attribute__((mips16))"
1510 #
Return true
if we can force a
mode that allows MIPS16 code generation.
1511 # We don
't support MIPS16 PIC, and only support MIPS16 -mhard-float
1514 proc check_effective_target_mips16_attribute { } {
1515 return [check_no_compiler_messages mips16_attribute assembly {
1519 #if defined __mips_hard_float \
1520 && (!defined _ABIO32 || _MIPS_SIM != _ABIO32) \
1521 && (!defined _ABIO64 || _MIPS_SIM != _ABIO64)
1522 #error __mips_hard_float && (!_ABIO32 || !_ABIO64)
1524 } [add_options_for_mips16_attribute ""]]
1527 # Return 1 if the target supports long double larger than double when
1528 # using the new ABI, 0 otherwise.
1530 proc check_effective_target_mips_newabi_large_long_double { } {
1531 return [check_no_compiler_messages mips_newabi_large_long_double object {
1532 int dummy[sizeof(long double) > sizeof(double) ? 1 : -1];
1536 # Return true if the target is a MIPS target that has access
1537 # to the LL and SC instructions.
1539 proc check_effective_target_mips_llsc { } {
1540 if { ![istarget mips*-*-*] } {
1543 # Assume that these instructions are always implemented for
1544 # non-elf* targets, via emulation if necessary.
1545 if { ![istarget *-*-elf*] } {
1548 # Otherwise assume LL/SC support for everything but MIPS I.
1549 return [check_no_compiler_messages mips_llsc assembly {
1556 # Return true if the target is a MIPS target that uses in-place relocations.
1558 proc check_effective_target_mips_rel { } {
1559 if { ![istarget mips*-*-*] } {
1562 return [check_no_compiler_messages mips_rel object {
1563 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1564 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1565 #error _ABIN32 && (_ABIN32 || _ABI64)
1570 # Return true if the target is a MIPS target that uses the EABI.
1572 proc check_effective_target_mips_eabi { } {
1573 if { ![istarget mips*-*-*] } {
1576 return [check_no_compiler_messages mips_eabi object {
1583 # Return 1 if the current multilib does not generate PIC by default.
1585 proc check_effective_target_nonpic { } {
1586 return [check_no_compiler_messages nonpic assembly {
1593 # Return 1 if the current multilib generates PIE by default.
1595 proc check_effective_target_pie_enabled { } {
1596 return [check_no_compiler_messages pie_enabled assembly {
1603 # Return 1 if the target generates -fstack-protector by default.
1605 proc check_effective_target_fstack_protector_enabled {} {
1606 return [ check_no_compiler_messages fstack_protector_enabled assembly {
1607 #if !defined(__SSP__) && !defined(__SSP_ALL__) && \
1608 !defined(__SSP_STRONG__) && !defined(__SSP_EXPICIT__)
1614 # Return 1 if the target does not use a status wrapper.
1616 proc check_effective_target_unwrapped { } {
1617 if { [target_info needs_status_wrapper] != "" \
1618 && [target_info needs_status_wrapper] != "0" } {
1624 # Return true if iconv is supported on the target. In particular IBM1047.
1626 proc check_iconv_available { test_what } {
1629 # If the tool configuration file has not set libiconv, try "-liconv"
1630 if { ![info exists libiconv] } {
1631 set libiconv "-liconv"
1633 set test_what [lindex $test_what 1]
1634 return [check_runtime_nocache $test_what [subst {
1640 cd = iconv_open ("$test_what", "UTF-8");
1641 if (cd == (iconv_t) -1)
1648 # Return true if the atomic library is supported on the target.
1649 proc check_effective_target_libatomic_available { } {
1650 return [check_no_compiler_messages libatomic_available executable {
1651 int main (void) { return 0; }
1655 # Return 1 if an ASCII locale is supported on this host, 0 otherwise.
1657 proc check_ascii_locale_available { } {
1661 # Return true if named sections are supported on this target.
1663 proc check_named_sections_available { } {
1664 return [check_no_compiler_messages named_sections assembly {
1665 int __attribute__ ((section("whatever"))) foo;
1669 # Return true if the "naked" function attribute is supported on this target.
1671 proc check_effective_target_naked_functions { } {
1672 return [check_no_compiler_messages naked_functions assembly {
1673 void f() __attribute__((naked));
1677 # Return 1 if the target supports Fortran real kinds larger than real(8),
1680 # When the target name changes, replace the cached result.
1682 proc check_effective_target_fortran_large_real { } {
1683 return [check_no_compiler_messages fortran_large_real executable {
1685 integer,parameter :: k = selected_real_kind (precision (0.0_8) + 1)
1692 # Return 1 if the target supports Fortran real kind real(16),
1693 # 0 otherwise. Contrary to check_effective_target_fortran_large_real
1694 # this checks for Real(16) only; the other returned real(10) if
1695 # both real(10) and real(16) are available.
1697 # When the target name changes, replace the cached result.
1699 proc check_effective_target_fortran_real_16 { } {
1700 return [check_no_compiler_messages fortran_real_16 executable {
1708 # Return 1 if the target supports Fortran real kind 10,
1709 # 0 otherwise. Contrary to check_effective_target_fortran_large_real
1710 # this checks for real(10) only.
1712 # When the target name changes, replace the cached result.
1714 proc check_effective_target_fortran_real_10 { } {
1715 return [check_no_compiler_messages fortran_real_10 executable {
1723 # Return 1 if the target supports Fortran real kind C_FLOAT128,
1724 # 0 otherwise. This differs from check_effective_target_fortran_real_16
1725 # because _Float128 has the additional requirement that it be the
1726 # 128-bit IEEE encoding; even if _Float128 is available in C, it may not
1727 # have a corresponding Fortran kind on targets (PowerPC) that use some
1728 # other encoding for long double/TFmode/real(16).
1729 proc check_effective_target_fortran_real_c_float128 { } {
1730 return [check_no_compiler_messages fortran_real_c_float128 executable {
1733 real(kind=c_float128) :: x
1739 # Return 1 if the target supports Fortran's IEEE modules
,
1742 # When the target
name changes
, replace the cached result.
1744 proc check_effective_target_fortran_ieee
{ flags
} {
1745 return [check_no_compiler_messages fortran_ieee executable
{
1747 use
, intrinsic
:: ieee_features
1753 #
Return 1 if the target supports
SQRT for the
largest floating
-point
1754 # type.
(Some targets lack the libm support
for this FP type.
)
1755 #
On most targets
, this check effectively checks either whether sqrtl is
1756 # available or
on __float128 systems whether libquadmath is installed
,
1757 # which provides sqrtq.
1759 # When the target
name changes
, replace the cached result.
1761 proc check_effective_target_fortran_largest_fp_has_sqrt
{ } {
1762 return [check_no_compiler_messages fortran_largest_fp_has_sqrt executable
{
1764 use iso_fortran_env
, only
: real_kinds
1765 integer,parameter
:: maxFP
= real_kinds
(ubound
(real_kinds
,dim
=1))
1766 real
(kind
=maxFP
), volatile
:: x
1774 #
Return 1 if the target supports Fortran
integer kinds larger than
1775 #
integer(8), 0 otherwise.
1777 # When the target
name changes
, replace the cached result.
1779 proc check_effective_target_fortran_large_int
{ } {
1780 return [check_no_compiler_messages fortran_large_int executable
{
1782 integer,parameter
:: k
= selected_int_kind
(range
(0_8
) + 1)
1783 integer(kind
=k
) :: i
1788 #
Return 1 if the target supports Fortran
integer(16), 0 otherwise.
1790 # When the target
name changes
, replace the cached result.
1792 proc check_effective_target_fortran_integer_16
{ } {
1793 return [check_no_compiler_messages fortran_integer_16 executable
{
1800 #
Return 1 if we can statically link libgfortran
, 0 otherwise.
1802 # When the target
name changes
, replace the cached result.
1804 proc check_effective_target_static_libgfortran
{ } {
1805 return [check_no_compiler_messages static_libgfortran executable
{
1812 #
Return 1 if we can use the
-rdynamic option
, 0 otherwise.
1814 proc check_effective_target_rdynamic
{ } {
1815 return [check_no_compiler_messages rdynamic executable
{
1816 int main
() { return 0; }
1820 proc check_linker_plugin_available
{ } {
1821 return [check_no_compiler_messages_nocache linker_plugin executable
{
1822 int main
() { return 0; }
1823 } "-flto -fuse-linker-plugin"]
1826 #
Return 1 if the we can build a vector example with proper
-march flags
1827 # and the current target can
execute it
, 0 otherwise.
Cache the result.
1829 proc check_effective_target_riscv_vector_hw
{ } {
1831 return [check_runtime riscv_vector_hw32
{
1834 asm
("vsetivli zero,8,e16,m1,ta,ma");
1835 asm
("vadd.vv v8,v8,v16" : : : "v8");
1838 } ""] || [check_runtime riscv_vector_hw64 {
1841 asm
("vsetivli zero,8,e16,m1,ta,ma");
1842 asm
("vadd.vv v8,v8,v16" : : : "v8");
1848 #
Return 1 if the we can build a Zvfh vector example with proper
-march flags
1849 # and the current target can
execute it
, 0 otherwise.
Cache the result.
1851 proc check_effective_target_riscv_zvfh_hw
{ } {
1852 if ![check_effective_target_riscv_vector_hw
] then {
1856 return [check_runtime riscv_zvfh_hw32
{
1859 asm
("vsetivli zero,8,e16,m1,ta,ma");
1860 asm
("vfadd.vv v8,v8,v16" : : : "v8");
1863 } "-march=rv32gcv_zvfh -mabi=ilp32d"]
1864 ||
[check_runtime riscv_zvfh_hw64
{
1867 asm
("vsetivli zero,8,e16,m1,ta,ma");
1868 asm
("vfadd.vv v8,v8,v16" : : : "v8");
1871 } "-march=rv64gcv_zvfh -mabi=lp64d"]
1875 #
Return 1 if the target is RV32
, 0 otherwise.
Cache the result.
1877 proc check_effective_target_rv32
{ } {
1878 # Check that we are compiling
for RV32 by checking the xlen size.
1879 return [check_no_compiler_messages riscv_rv32 assembly
{
1880 #
if !defined
(__riscv_xlen
)
1881 #error
"__riscv_xlen not defined!"
1883 #
if __riscv_xlen
!= 32
1890 #
Return 1 if the target is RV64
, 0 otherwise.
Cache the result.
1892 proc check_effective_target_rv64
{ } {
1893 # Check that we are compiling
for RV64 by checking the xlen size.
1894 return [check_no_compiler_messages riscv_rv64 assembly
{
1895 #
if !defined
(__riscv_xlen
)
1896 #error
"__riscv_xlen not defined!"
1898 #
if __riscv_xlen
!= 64
1905 #
Return 1 if the target abi is __riscv_float_abi_soft
, 0 otherwise.
1908 proc check_effective_target_rv_float_abi_soft
{ } {
1909 # Check that we are compiling
for RV64 by checking the xlen size.
1910 return [check_no_compiler_messages riscv_riscv_float_abi_soft assembly
{
1911 #ifndef __riscv_float_abi_soft
1912 #error
"Not __riscv_float_abi_soft"
1917 #
Return 1 if the target arch supports the atomic extension
, 0 otherwise.
1920 proc check_effective_target_riscv_a
{ } {
1921 return [check_no_compiler_messages riscv_ext_a assembly
{
1923 #error
"Not __riscv_a"
1928 #
Return 1 if the target arch supports the double precision floating point
1929 # extension
, 0 otherwise.
Cache the result.
1931 proc check_effective_target_riscv_d
{ } {
1932 return [check_no_compiler_messages riscv_ext_d assembly
{
1934 #error
"Not __riscv_d"
1939 #
Return 1 if the target arch supports the vector extension
, 0 otherwise.
1942 proc check_effective_target_riscv_v
{ } {
1943 return [check_no_compiler_messages riscv_ext_v assembly
{
1945 #error
"Not __riscv_v"
1950 #
Return 1 if the target arch supports the Zvfh extension
, 0 otherwise.
1953 proc check_effective_target_riscv_zvfh
{ } {
1954 return [check_no_compiler_messages riscv_ext_zvfh assembly
{
1955 #ifndef __riscv_zvfh
1956 #error
"Not __riscv_zvfh"
1961 #
Return 1 if the target arch supports half float
, 0 otherwise.
1962 # Note
, this differs from the test performed by
1963 #
/* dg
-skip
-if "" { *-*-* } { "*" } { "-march=rv*zfh*" } */
1964 # in that it takes default behaviour into account.
1967 proc check_effective_target_riscv_zfh
{ } {
1968 return [check_no_compiler_messages riscv_ext_zfh assembly
{
1970 #error
"Not __riscv_zfh"
1975 #
Return 1 if the target arch supports the TSO memory ordering extension
,
1976 #
0 otherwise.
Cache the result.
1978 proc check_effective_target_riscv_ztso
{ } {
1979 return [check_no_compiler_messages riscv_ext_ztso assembly
{
1980 #ifndef __riscv_ztso
1981 #error
"Not __riscv_ztso"
1986 #
Return 1 if we can
execute code when using dg
-add
-options riscv_v
1988 proc check_effective_target_riscv_v_ok
{ } {
1989 #
If the target already supports v without
any added options
,
1990 # we may assume we can
execute just fine.
1991 if { [check_effective_target_riscv_v
] } {
1995 # check
if we can
execute vector insns with the given hardware or
1997 set gcc_march
[regsub
{[[:alnum
:]]*} [riscv_get_arch
] &v
]
1998 if { [check_runtime $
{gcc_march
}_exec
{
1999 int main
() { asm
("vsetivli t0, 9, e8, m1, tu, ma"); return 0; } } "-march=${gcc_march}"] } {
2003 # Possible future extensions
: If the target is a simulator
, dg
-add
-options
2004 # might change its config to make it allow vector insns
, or we might use
2005 # options to
set special elf flags
/ sections to effect that.
2010 #
Return 1 if we can
execute code when using dg
-add
-options riscv_zfh
2012 proc check_effective_target_riscv_zfh_ok
{ } {
2013 #
If the target already supports zfh without
any added options
,
2014 # we may assume we can
execute just fine.
2015 # ??? Other cases we should
consider:
2016 #
- target
/ simulator already supports zfh extension
- test
for that.
2017 #
- target is a simulator
, and dg
-add
-options knows how to enable zfh support in that simulator
2018 if { [check_effective_target_riscv_zfh
] } {
2022 # check
if we can
execute zfh insns with the given hardware or
2024 set gcc_march
[riscv_get_arch
]
2025 if { [check_runtime $
{gcc_march
}_zfh_exec
{
2026 int main
() { asm
("feq.h a3,fa5,fa4"); return 0; } } "-march=${gcc_march}_zfh"] } {
2030 # Possible future extensions
: If the target is a simulator
, dg
-add
-options
2031 # might change its config to make it allow half float insns
, or we might
2032 # use options to
set special elf flags
/ sections to effect that.
2037 #
Return 1 if we can
execute code when using dg
-add
-options riscv_zvfh
2039 proc check_effective_target_riscv_zvfh_ok
{ } {
2040 #
If the target already supports v without
any added options
,
2041 # we may assume we can
execute just fine.
2042 if { [check_effective_target_riscv_zvfh
] } {
2046 # check
if we can
execute vector insns with the given hardware or
2048 set gcc_march
[regsub
{[[:alnum
:]]*} [riscv_get_arch
] &v
]
2049 if { [check_runtime $
{gcc_march
}_exec
{
2052 asm
("vsetivli zero,8,e16,m1,ta,ma");
2053 asm
("vfadd.vv v8,v8,v16" : : : "v8");
2055 } } "-march=${gcc_march}"] } {
2062 proc riscv_get_arch
{ } {
2064 # ???
do we neeed to add more extensions to the list below?
2065 foreach ext
{ i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvfh ztso
} {
2066 if { [check_no_compiler_messages riscv_ext_$ext assembly
[string map
[list DEF __riscv_$ext
] {
2071 if { [string length $ext
] > 1 } {
2074 set gcc_march $gcc_march$ext
2076 if { [string equal $gcc_march
"imafd"] } {
2080 if { [check_effective_target_rv32
] } {
2081 set gcc_march rv32$gcc_march
2082 } elseif
{ [check_effective_target_rv64
] } {
2083 set gcc_march rv64$gcc_march
2090 proc add_options_for_riscv_a
{ flags
} {
2091 if { [lsearch $flags
-march
=*] >= 0 } {
2092 #
If there are multiple
-march flags
, we have to adjust all of them.
2093 set expanded_flags
[regsub
-all
-- {((?
:^|
[[:space
:]])-march
=rv
[[:digit
:]]*)g
+} $flags
\\1imafd
]
2094 return [regsub
-all
-- {((?
:^|
[[:space
:]])-march
=rv
[[:digit
:]]*[b
-eg
-rt
-wy
]*)a
*} $expanded_flags
\\1a
]
2096 if { [check_effective_target_riscv_a
] } {
2099 return "$flags -march=[regsub {(rv[[:digit:]]*[b-eg-rt-wy]*)a*} [riscv_get_arch] &a]"
2102 proc add_options_for_riscv_d
{ flags
} {
2103 if { [lsearch $flags
-march
=*] >= 0 } {
2104 #
If there are multiple
-march flags
, we have to adjust all of them.
2105 return [regsub
-all
-- {((?
:^|
[[:space
:]])-march
=rv
[[:digit
:]]*[a
-ce
-rt
-wy
]*)d
*} $flags
\\1d
]
2107 if { [check_effective_target_riscv_d
] } {
2110 return "$flags -march=[regsub {[[:alnum:]]*} [riscv_get_arch] &d]"
2113 proc add_options_for_riscv_v
{ flags
} {
2114 if { [lsearch $flags
-march
=*] >= 0 } {
2115 #
If there are multiple
-march flags
, we have to adjust all of them.
2116 return [regsub
-all
-- {((?
:^|
[[:space
:]])-march
=rv
[[:digit
:]]*[a
-rt
-uwy
]*)v
*} $flags
\\1v
]
2118 if { [check_effective_target_riscv_v
] } {
2121 return "$flags -march=[regsub {[[:alnum:]]*} [riscv_get_arch] &v]"
2124 proc add_options_for_riscv_zfh
{ flags
} {
2125 if { [lsearch $flags
-march
=*] >= 0 } {
2126 #
If there are multiple
-march flags
, we have to adjust all of them.
2127 set flags
[regsub
-all
-- {(?
:^|
[[:space
:]])-march
=[[:alnum
:]_.
]*} $flags
&_zfh
]
2128 return [regsub
-all
-- {((?
:^|
[[:space
:]])-march
=[[:alnum
:]_.
]*_zfh
[[:alnum
:]_.
]*)_zfh
} $flags
\\1 ]
2130 if { [check_effective_target_riscv_zfh
] } {
2133 return "$flags -march=[riscv_get_arch]_zfh"
2136 proc add_options_for_riscv_ztso
{ flags
} {
2137 if { [lsearch $flags
-march
=*] >= 0 } {
2138 #
If there are multiple
-march flags
, we have to adjust all of them.
2139 set flags
[regsub
-all
-- {(?
:^|
[[:space
:]])-march
=[[:alnum
:]_.
]*} $flags
&_ztso
]
2140 return [regsub
-all
-- {((?
:^|
[[:space
:]])-march
=[[:alnum
:]_.
]*_ztso
[[:alnum
:]_.
]*)_ztso
} $flags
\\1 ]
2142 if { [check_effective_target_riscv_ztso
] } {
2145 return "$flags -march=[riscv_get_arch]_ztso"
2148 proc add_options_for_riscv_zvfh
{ flags
} {
2149 if { [lsearch $flags
-march
=*] >= 0 } {
2150 #
If there are multiple
-march flags
, we have to adjust all of them.
2151 set flags
[regsub
-all
-- {(?
:^|
[[:space
:]])-march
=[[:alnum
:]_.
]*} $flags
&_zvfh
]
2152 return [regsub
-all
-- {((?
:^|
[[:space
:]])-march
=[[:alnum
:]_.
]*_zvfh
[[:alnum
:]_.
]*)_zvfh
} $flags
\\1 ]
2154 if { [check_effective_target_riscv_zvfh
] } {
2157 return "$flags -march=[riscv_get_arch]_zvfh"
2160 #
Return 1 if the target OS supports running SSE executables
, 0
2161 # otherwise.
Cache the result.
2163 proc check_sse_os_support_available
{ } {
2164 return [check_cached_effective_target sse_os_support_available
{
2165 #
If this is not the right target
then we can skip the test.
2166 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
2174 #
Return 1 if the target OS supports running AVX executables
, 0
2175 # otherwise.
Cache the result.
2177 proc check_avx_os_support_available
{ } {
2178 return [check_cached_effective_target avx_os_support_available
{
2179 #
If this is not the right target
then we can skip the test.
2180 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
2183 # Check that OS has AVX and SSE saving enabled.
2184 check_runtime_nocache avx_os_support_available
{
2187 unsigned
int eax
, edx
;
2189 asm
("xgetbv" : "=a" (eax), "=d" (edx) : "c" (0));
2190 return (eax
& 0x06) != 0x06;
2197 #
Return 1 if the target OS supports running AVX executables
, 0
2198 # otherwise.
Cache the result.
2200 proc check_avx512_os_support_available
{ } {
2201 return [check_cached_effective_target avx512_os_support_available
{
2202 #
If this is not the right target
then we can skip the test.
2203 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
2206 # Check that OS has AVX512
, AVX and SSE saving enabled.
2207 check_runtime_nocache avx512_os_support_available
{
2210 unsigned
int eax
, edx
;
2212 asm
("xgetbv" : "=a" (eax), "=d" (edx) : "c" (0));
2213 return (eax
& 0xe6) != 0xe6;
2220 #
Return 1 if the target supports executing SSE instructions
, 0
2221 # otherwise.
Cache the result.
2223 proc check_sse_hw_available
{ } {
2224 return [check_cached_effective_target sse_hw_available
{
2225 #
If this is not the right target
then we can skip the test.
2226 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
2229 check_runtime_nocache sse_hw_available
{
2233 unsigned
int eax
, ebx
, ecx
, edx
;
2234 if (!__get_cpuid
(1, &eax
, &ebx
, &ecx
, &edx
))
2237 return !(edx
& bit_SSE
);
2244 #
Return 1 if the target supports executing SSE2 instructions
, 0
2245 # otherwise.
Cache the result.
2247 proc check_sse2_hw_available
{ } {
2248 return [check_cached_effective_target sse2_hw_available
{
2249 #
If this is not the right target
then we can skip the test.
2250 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
2253 check_runtime_nocache sse2_hw_available
{
2257 unsigned
int eax
, ebx
, ecx
, edx
;
2258 if (!__get_cpuid
(1, &eax
, &ebx
, &ecx
, &edx
))
2261 return !(edx
& bit_SSE2
);
2268 #
Return 1 if the target supports executing SSE4 instructions
, 0
2269 # otherwise.
Cache the result.
2271 proc check_sse4_hw_available
{ } {
2272 return [check_cached_effective_target sse4_hw_available
{
2273 #
If this is not the right target
then we can skip the test.
2274 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
2277 check_runtime_nocache sse4_hw_available
{
2281 unsigned
int eax
, ebx
, ecx
, edx
;
2282 if (!__get_cpuid
(1, &eax
, &ebx
, &ecx
, &edx
))
2285 return !(ecx
& bit_SSE4_2
);
2292 #
Return 1 if the target supports executing AVX instructions
, 0
2293 # otherwise.
Cache the result.
2295 proc check_avx_hw_available
{ } {
2296 return [check_cached_effective_target avx_hw_available
{
2297 #
If this is not the right target
then we can skip the test.
2298 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
2301 check_runtime_nocache avx_hw_available
{
2305 unsigned
int eax
, ebx
, ecx
, edx
;
2306 if (!__get_cpuid
(1, &eax
, &ebx
, &ecx
, &edx
))
2309 return ((ecx
& (bit_AVX | bit_OSXSAVE
))
2310 != (bit_AVX | bit_OSXSAVE
));
2317 #
Return 1 if the target supports executing AVX2 instructions
, 0
2318 # otherwise.
Cache the result.
2320 proc check_avx2_hw_available
{ } {
2321 return [check_cached_effective_target avx2_hw_available
{
2322 #
If this is not the right target
then we can skip the test.
2323 if { !([istarget x86_64
-*-*] ||
[istarget i?
86-*-*]) } {
2326 check_runtime_nocache avx2_hw_available
{
2331 unsigned
int eax
, ebx
, ecx
, edx
;
2333 if (__get_cpuid_max
(0, NULL
) < 7)
2336 __cpuid
(1, eax
, ebx
, ecx
, edx
);
2338 if (!(ecx
& bit_OSXSAVE
))
2341 __cpuid_count
(7, 0, eax
, ebx
, ecx
, edx
);
2343 return !(ebx
& bit_AVX2
);
2350 #
Return 1 if the target supports executing AVX512 foundation instructions
, 0
2351 # otherwise.
Cache the result.
2353 proc check_avx512f_hw_available
{ } {
2354 return [check_cached_effective_target avx512f_hw_available
{
2355 #
If this is not the right target
then we can skip the test.
2356 if { !([istarget x86_64
-*-*] ||
[istarget i?
86-*-*]) } {
2359 check_runtime_nocache avx512f_hw_available
{
2364 unsigned
int eax
, ebx
, ecx
, edx
;
2366 if (__get_cpuid_max
(0, NULL
) < 7)
2369 __cpuid
(1, eax
, ebx
, ecx
, edx
);
2371 if (!(ecx
& bit_OSXSAVE
))
2374 __cpuid_count
(7, 0, eax
, ebx
, ecx
, edx
);
2376 return !(ebx
& bit_AVX512F
);
2383 #
Return 1 if the target supports running SSE executables
, 0 otherwise.
2385 proc check_effective_target_sse_runtime
{ } {
2386 if { [check_effective_target_sse
]
2387 && [check_sse_hw_available
]
2388 && [check_sse_os_support_available
] } {
2394 #
Return 1 if the target supports running SSE2 executables
, 0 otherwise.
2396 proc check_effective_target_sse2_runtime
{ } {
2397 if { [check_effective_target_sse2
]
2398 && [check_sse2_hw_available
]
2399 && [check_sse_os_support_available
] } {
2405 #
Return 1 if the target supports running SSE4 executables
, 0 otherwise.
2407 proc check_effective_target_sse4_runtime
{ } {
2408 if { [check_effective_target_sse4
]
2409 && [check_sse4_hw_available
]
2410 && [check_sse_os_support_available
] } {
2416 #
Return 1 if the target supports running AVX executables
, 0 otherwise.
2418 proc check_effective_target_avx_runtime
{ } {
2419 if { [check_effective_target_avx
]
2420 && [check_avx_hw_available
]
2421 && [check_avx_os_support_available
] } {
2427 #
Return 1 if the target supports running AVX2 executables
, 0 otherwise.
2429 proc check_effective_target_avx2_runtime
{ } {
2430 if { [check_effective_target_avx2
]
2431 && [check_avx2_hw_available
]
2432 && [check_avx_os_support_available
] } {
2438 #
Return 1 if the target supports running AVX512f executables
, 0 otherwise.
2440 proc check_effective_target_avx512f_runtime
{ } {
2441 if { [check_effective_target_avx512f
]
2442 && [check_avx512f_hw_available
]
2443 && [check_avx512_os_support_available
] } {
2449 #
Return 1 if bmi2 instructions can be compiled.
2450 proc check_effective_target_bmi2
{ } {
2451 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
2454 return [check_no_compiler_messages bmi2 object
{
2456 _bzhi_u32
(unsigned
int __X
, unsigned
int __Y
)
2458 return __builtin_ia32_bzhi_si
(__X
, __Y
);
2463 #
Return 1 if the target supports executing MIPS Paired
-Single instructions
,
2464 #
0 otherwise.
Cache the result.
2466 proc check_mpaired_single_hw_available
{ } {
2467 return [check_cached_effective_target mpaired_single_hw_available
{
2468 #
If this is not the right target
then we can skip the test.
2469 if { !([istarget mips
*-*-*]) } {
2472 check_runtime_nocache mpaired_single_hw_available
{
2475 asm volatile
("pll.ps $f2,$f4,$f6");
2483 #
Return 1 if the target supports executing Loongson vector instructions
,
2484 #
0 otherwise.
Cache the result.
2486 proc check_mips_loongson_mmi_hw_available
{ } {
2487 return [check_cached_effective_target mips_loongson_mmi_hw_available
{
2488 #
If this is not the right target
then we can skip the test.
2489 if { !([istarget mips
*-*-*]) } {
2492 check_runtime_nocache mips_loongson_mmi_hw_available
{
2493 #
include <loongson
-mmiintrin.h
>
2496 asm volatile
("paddw $f2,$f4,$f6");
2504 #
Return 1 if the target supports executing MIPS MSA instructions
, 0
2505 # otherwise.
Cache the result.
2507 proc check_mips_msa_hw_available
{ } {
2508 return [check_cached_effective_target mips_msa_hw_available
{
2509 #
If this is not the right target
then we can skip the test.
2510 if { !([istarget mips
*-*-*]) } {
2513 check_runtime_nocache mips_msa_hw_available
{
2514 #
if !defined
(__mips_msa
)
2515 #error
"MSA NOT AVAIL"
2517 #
if !(((__mips
== 64) ||
(__mips
== 32)) && (__mips_isa_rev
>= 2))
2518 #error
"MSA NOT AVAIL FOR ISA REV < 2"
2520 #
if !defined
(__mips_hard_float
)
2521 #error
"MSA HARD_FLOAT REQUIRED"
2523 #
if __mips_fpr
!= 64
2524 #error
"MSA 64-bit FPR REQUIRED"
2530 v8i16 v
= __builtin_msa_ldi_h
(0);
2540 #
Return 1 if the target supports running MIPS Paired
-Single
2541 # executables
, 0 otherwise.
2543 proc check_effective_target_mpaired_single_runtime
{ } {
2544 if { [check_effective_target_mpaired_single
"-mpaired-single"]
2545 && [check_mpaired_single_hw_available
] } {
2551 #
Return 1 if the target supports running Loongson executables
, 0 otherwise.
2553 proc check_effective_target_mips_loongson_mmi_runtime
{ } {
2554 if { [check_effective_target_mips_loongson_mmi
"-mloongson-mmi"]
2555 && [check_mips_loongson_mmi_hw_available
] } {
2561 #
Return 1 if the target supports running MIPS MSA executables
, 0 otherwise.
2563 proc check_effective_target_mips_msa_runtime
{ } {
2564 if { [check_effective_target_mips_msa
"-mmsa"]
2565 && [check_mips_msa_hw_available
] } {
2571 #
Return 1 if we are compiling
for 64-bit PowerPC but we
do not use direct
2572 #
move instructions
for moves from GPR to FPR.
2574 proc check_effective_target_powerpc64_no_dm
{ } {
2575 # The
"mulld" checks if we are generating PowerPC64 code. The "lfd"
2576 # checks
if we
do not use direct moves
, but use the old
-fashioned
2577 # slower
move-via
-the
-stack.
2578 return [check_no_messages_and_pattern powerpc64_no_dm \
2579 {\mmulld\M.
*\mlfd
} assembly
{
2580 double f
(long long x
) { return x
*x
; }
2584 #
Return 1 if the target supports the __builtin_cpu_supports built
-in
,
2585 # including having a new enough library to support the test.
Cache the result.
2586 # Require at least a power7 to run
on.
2588 proc check_ppc_cpu_supports_hw_available
{ } {
2589 return [check_cached_effective_target ppc_cpu_supports_hw_available
{
2590 # Some simulators are known to not support VSX
/power8 instructions.
2591 #
For now
, disable
on Darwin
2592 if { [istarget powerpc
-*-eabi
]
2593 ||
[istarget powerpc
*-*-eabispe
]
2594 ||
[istarget
*-*-darwin
*]} {
2598 check_runtime_nocache ppc_cpu_supports_hw_available
{
2602 asm volatile
("xxlor vs0,vs0,vs0");
2604 asm volatile
("xxlor 0,0,0");
2606 if (!__builtin_cpu_supports
("vsx"))
2615 #
Return 1 if the target supports executing
750CL paired
-single instructions
, 0
2616 # otherwise.
Cache the result.
2618 proc check_750cl_hw_available
{ } {
2619 return [check_cached_effective_target
750cl_hw_available
{
2620 #
If this is not the right target
then we can skip the test.
2621 if { ![istarget powerpc
-*paired
*] } {
2624 check_runtime_nocache
750cl_hw_available
{
2628 asm volatile
("ps_mul v0,v0,v0");
2630 asm volatile
("ps_mul 0,0,0");
2639 #
Return 1 if the target supports executing power8 vector instructions
, 0
2640 # otherwise.
Cache the result.
2642 proc check_p8vector_hw_available
{ } {
2643 return [check_cached_effective_target p8vector_hw_available
{
2644 # Some simulators are known to not support VSX
/power8 instructions.
2645 #
For now
, disable
on Darwin
2646 if { [istarget powerpc
-*-eabi
]
2647 ||
[istarget powerpc
*-*-eabispe
]
2648 ||
[istarget
*-*-darwin
*]} {
2651 set options
"-mpower8-vector"
2652 check_runtime_nocache p8vector_hw_available
{
2656 asm volatile
("xxlorc vs0,vs0,vs0");
2658 asm volatile
("xxlorc 0,0,0");
2667 #
Return 1 if the target supports executing power9 vector instructions
, 0
2668 # otherwise.
Cache the result.
2670 proc check_p9vector_hw_available
{ } {
2671 return [check_cached_effective_target p9vector_hw_available
{
2672 # Some simulators are known to not support VSX
/power8
/power9
2673 # instructions.
For now
, disable
on Darwin.
2674 if { [istarget powerpc
-*-eabi
]
2675 ||
[istarget powerpc
*-*-eabispe
]
2676 ||
[istarget
*-*-darwin
*]} {
2679 set options
"-mpower9-vector"
2680 check_runtime_nocache p9vector_hw_available
{
2684 vector double v
= (vector double
) { 0.0, 0.0 };
2685 asm
("xsxexpdp %0,%1" : "+r" (e) : "wa" (v));
2693 #
Return 1 if the PowerPC target generates PC
-relative instructions
2694 # automatically
for targets that support PC
-relative instructions.
2695 proc check_effective_target_powerpc_pcrel
{ } {
2696 return [check_no_messages_and_pattern powerpc_pcrel \
2697 {\mpla\M
} assembly
{
2698 static unsigned short s
;
2699 unsigned short
*p_foo
(void
) { return &s
; }
2700 } {-O2
-mcpu
=power10
}]
2703 #
Return 1 if the PowerPC target generates prefixed instructions automatically
2704 #
for targets that support prefixed instructions.
2705 proc check_effective_target_powerpc_prefixed_addr
{ } {
2706 return [check_no_messages_and_pattern powerpc_prefixed_addr \
2707 {\mplwz\M
} assembly
{
2708 unsigned
int foo
(unsigned
int *p
) { return p
[0x12345]; }
2709 } {-O2
-mcpu
=power10
}]
2712 #
Return 1 if the target supports executing power9 modulo instructions
, 0
2713 # otherwise.
Cache the result.
2715 proc check_p9modulo_hw_available
{ } {
2716 return [check_cached_effective_target p9modulo_hw_available
{
2717 # Some simulators are known to not support VSX
/power8
/power9
2718 # instructions.
For now
, disable
on Darwin.
2719 if { [istarget powerpc
-*-eabi
]
2720 ||
[istarget powerpc
*-*-eabispe
]
2721 ||
[istarget
*-*-darwin
*]} {
2724 set options
"-mmodulo"
2725 check_runtime_nocache p9modulo_hw_available
{
2728 int i
= 5, j
= 3, r
= -1;
2729 asm
("modsw %0,%1,%2" : "+r" (r) : "r" (i), "r" (j));
2738 #
Return 1 if the target supports executing power10 instructions
, 0 otherwise.
2739 #
Cache the result. It is assumed that
if a simulator does not support the
2740 # power10 instructions
, that it will generate an error and this test will fail.
2742 proc check_power10_hw_available
{ } {
2743 return [check_cached_effective_target power10_hw_available
{
2744 check_runtime_nocache power10_hw_available
{
2747 /* Set e first and use
+r to check
if pli actually works.
*/
2749 asm
("pli %0,%1" : "+r" (e) : "n" (0x12345));
2758 #
Return 1 if the target supports executing MMA instructions
, 0 otherwise.
2759 #
Cache the result. It is assumed that
if a simulator does not support the
2760 # MMA instructions
, that it will generate an error and this test will fail.
2762 proc check_ppc_mma_hw_available
{ } {
2763 return [check_cached_effective_target ppc_mma_hw_available
{
2764 check_runtime_nocache ppc_mma_hw_available
{
2765 #
include <altivec.h
>
2766 typedef double v4sf_t __attribute__
((vector_size
(16)));
2773 __builtin_mma_xxsetaccz
(&acc0
);
2774 __builtin_mma_disassemble_acc
(result
, &acc0
);
2775 if (result
[0][0] != 0.0)
2783 #
Return 1 if the target supports executing __float128
on PowerPC via software
2784 # emulation
, 0 otherwise.
Cache the result.
2786 proc check_ppc_float128_sw_available
{ } {
2787 return [check_cached_effective_target ppc_float128_sw_available
{
2788 # Some simulators are known to not support VSX
/power8
/power9
2789 # instructions.
For now
, disable
on Darwin and VxWorks.
2790 if { [istarget
*-*-vxworks
*]
2791 ||
[istarget powerpc
-*-eabi
]
2792 ||
[istarget powerpc
*-*-eabispe
]
2793 ||
[istarget
*-*-darwin
*]} {
2796 set options
"-mfloat128 -mvsx"
2797 check_runtime_nocache ppc_float128_sw_available
{
2798 volatile __float128 x
= 1.0q
;
2799 volatile __float128 y
= 2.0q
;
2802 __float128 z
= x
+ y
;
2810 #
Return 1 if the target supports executing __float128
on PowerPC via power9
2811 # hardware instructions
, 0 otherwise.
Cache the result.
2813 proc check_ppc_float128_hw_available
{ } {
2814 return [check_cached_effective_target ppc_float128_hw_available
{
2815 # Some simulators are known to not support VSX
/power8
/power9
2816 # instructions.
For now
, disable
on Darwin.
2817 if { [istarget
*-*-vxworks
*]
2818 ||
[istarget powerpc
-*-eabi
]
2819 ||
[istarget powerpc
*-*-eabispe
]
2820 ||
[istarget
*-*-darwin
*]} {
2823 set options
"-mfloat128 -mvsx -mfloat128-hardware -mpower9-vector"
2824 check_runtime_nocache ppc_float128_hw_available
{
2825 volatile __float128 x
= 1.0q
;
2826 volatile __float128 y
= 2.0q
;
2829 __float128 z
= x
+ y
;
2830 __float128 w
= -1.0q
;
2832 __asm__
("xsaddqp %0,%1,%2" : "+v" (w) : "v" (x), "v" (y));
2833 return ((z
!= 3.0q
) ||
(z
!= w
));
2840 # See
if the __ieee128 keyword is understood.
2841 proc check_effective_target_ppc_ieee128_ok
{ } {
2842 return [check_cached_effective_target ppc_ieee128_ok
{
2843 # disable
on AIX and VxWorks.
2844 if { [istarget
*-*-aix
*]
2845 ||
[istarget
*-*-vxworks
*]} {
2848 set options
"-mfloat128"
2849 check_runtime_nocache ppc_ieee128_ok
{
2860 # Check
if GCC and GLIBC supports explicitly specifying that the long double
2861 # format uses the IBM
128-bit extended double format. Under little endian
2862 # PowerPC Linux
, you need GLIBC
2.32 or later to be able to use a different
2863 # long double format
for running a
program than the
system default.
2865 proc check_effective_target_long_double_ibm128
{ } {
2866 return [check_runtime_nocache long_double_ibm128
{
2869 /* use volatile to prevent optimization.
*/
2870 volatile __ibm128 a
= (__ibm128
) 3.0;
2871 volatile long double one
= 1.0L;
2872 volatile long double two
= 2.0L;
2873 volatile long double b
;
2879 if (sizeof
(long double
) != 16)
2882 /* eliminate removing volatile cast warning.
*/
2885 if (memcmp
(&a2
, &b2
, 16) != 0)
2887 sprintf
(buffer
, "%lg", b);
2888 return strcmp
(buffer
, "3") != 0;
2890 } [add_options_for_long_double_ibm128
""]]
2893 #
Return the appropriate options to specify that long double uses the IBM
2894 #
128-bit format
on PowerPC.
2896 proc add_options_for_long_double_ibm128
{ flags
} {
2897 if { [istarget powerpc
*-*-*] } {
2898 return "$flags -mlong-double-128 -Wno-psabi -mabi=ibmlongdouble"
2903 # Check
if GCC and GLIBC supports explicitly specifying that the long double
2904 # format uses the IEEE
128-bit format. Under little endian PowerPC Linux
, you
2905 # need GLIBC
2.32 or later to be able to use a different long double format
for
2906 # running a
program than the
system default.
2908 proc check_effective_target_long_double_ieee128
{ } {
2909 return [check_runtime_nocache long_double_ieee128
{
2912 /* use volatile to prevent optimization.
*/
2913 volatile _Float128 a
= 3.0f128
;
2914 volatile long double one
= 1.0L;
2915 volatile long double two
= 2.0L;
2916 volatile long double b
;
2922 if (sizeof
(long double
) != 16)
2925 /* eliminate removing volatile cast warning.
*/
2928 if (memcmp
(&a2
, &b2
, 16) != 0)
2930 sprintf
(buffer
, "%lg", b);
2931 return strcmp
(buffer
, "3") != 0;
2933 } [add_options_for_long_double_ieee128
""]]
2936 #
Return the appropriate options to specify that long double uses the IBM
2937 #
128-bit format
on PowerPC.
2938 proc add_options_for_long_double_ieee128
{ flags
} {
2939 if { [istarget powerpc
*-*-*] } {
2940 return "$flags -mlong-double-128 -Wno-psabi -mabi=ieeelongdouble"
2945 # Check
if GCC and GLIBC supports explicitly specifying that the long double
2946 # format uses the IEEE
64-bit. Under little endian PowerPC Linux
, you need
2947 # GLIBC
2.32 or later to be able to use a different long double format
for
2948 # running a
program than the
system default.
2950 proc check_effective_target_long_double_64bit
{ } {
2951 return [check_runtime_nocache long_double_64bit
{
2954 /* use volatile to prevent optimization.
*/
2955 volatile double a
= 3.0;
2956 volatile long double one
= 1.0L;
2957 volatile long double two
= 2.0L;
2958 volatile long double b
;
2964 if (sizeof
(long double
) != 8)
2967 /* eliminate removing volatile cast warning.
*/
2970 if (memcmp
(&a2
, &b2
, 16) != 0)
2972 sprintf
(buffer
, "%lg", b);
2973 return strcmp
(buffer
, "3") != 0;
2975 } [add_options_for_ppc_long_double_override_64bit
""]]
2978 #
Return the appropriate options to specify that long double uses the IEEE
2979 #
64-bit format
on PowerPC.
2981 proc add_options_for_long_double_64bit
{ flags
} {
2982 if { [istarget powerpc
*-*-*] } {
2983 return "$flags -mlong-double-64"
2988 #
Return 1 if the target supports executing VSX instructions
, 0
2989 # otherwise.
Cache the result.
2991 proc check_vsx_hw_available
{ } {
2992 return [check_cached_effective_target vsx_hw_available
{
2993 # Some simulators are known to not support VSX instructions.
2994 #
For now
, disable
on Darwin
2995 if { [istarget powerpc
-*-eabi
]
2996 ||
[istarget powerpc
*-*-eabispe
]
2997 ||
[istarget
*-*-darwin
*]} {
3001 check_runtime_nocache vsx_hw_available
{
3005 asm volatile
("xxlor vs0,vs0,vs0");
3007 asm volatile
("xxlor 0,0,0");
3016 #
Return 1 if the target supports executing AltiVec instructions
, 0
3017 # otherwise.
Cache the result.
3019 proc check_vmx_hw_available
{ } {
3020 return [check_cached_effective_target vmx_hw_available
{
3021 # Some simulators are known to not support VMX instructions.
3022 if { [istarget powerpc
-*-eabi
] ||
[istarget powerpc
*-*-eabispe
] } {
3025 # Most targets don
't require special flags for this test case, but
3026 # Darwin does. Just to be sure, make sure VSX is not enabled for
3027 # the altivec tests.
3028 if { [istarget *-*-darwin*]
3029 || [istarget *-*-aix*] } {
3030 set options "-maltivec -mno-vsx"
3032 set options "-mno-vsx"
3034 check_runtime_nocache vmx_hw_available {
3038 asm volatile ("vor v0,v0,v0");
3040 asm volatile ("vor 0,0,0");
3049 proc check_ppc_recip_hw_available { } {
3050 return [check_cached_effective_target ppc_recip_hw_available {
3051 # Some simulators may not support FRE/FRES/FRSQRTE/FRSQRTES
3052 # For now, disable on Darwin
3053 if { [istarget powerpc-*-eabi] || [istarget powerpc*-*-eabispe] || [istarget *-*-darwin*]} {
3056 set options "-mpowerpc-gfxopt -mpowerpc-gpopt -mpopcntb"
3057 check_runtime_nocache ppc_recip_hw_available {
3058 volatile double d_recip, d_rsqrt, d_four = 4.0;
3059 volatile float f_recip, f_rsqrt, f_four = 4.0f;
3062 asm volatile ("fres %0,%1" : "=f" (f_recip) : "f" (f_four));
3063 asm volatile ("fre %0,%1" : "=d" (d_recip) : "d" (d_four));
3064 asm volatile ("frsqrtes %0,%1" : "=f" (f_rsqrt) : "f" (f_four));
3065 asm volatile ("frsqrte %0,%1" : "=f" (d_rsqrt) : "d" (d_four));
3073 # Return 1 if the target supports executing AltiVec and Cell PPU
3074 # instructions, 0 otherwise. Cache the result.
3076 proc check_effective_target_cell_hw { } {
3077 return [check_cached_effective_target cell_hw_available {
3078 # Some simulators are known to not support VMX and PPU instructions.
3079 if { [istarget powerpc-*-eabi*] } {
3082 # Most targets don't require special flags
for this test
3083 # case
, but Darwin and AIX
do.
3084 if { [istarget
*-*-darwin
*]
3085 ||
[istarget
*-*-aix
*] } {
3086 set options
"-maltivec -mcpu=cell"
3088 set options
"-mcpu=cell"
3090 check_runtime_nocache cell_hw_available
{
3094 asm volatile
("vor v0,v0,v0");
3095 asm volatile
("lvlx v0,r0,r0");
3097 asm volatile
("vor 0,0,0");
3098 asm volatile
("lvlx 0,0,0");
3107 #
Return 1 if the target supports executing
64-bit instructions
, 0
3108 # otherwise.
Cache the result.
3110 proc check_effective_target_powerpc64
{ } {
3111 global powerpc64_available_saved
3114 if [info exists powerpc64_available_saved
] {
3115 verbose
"check_effective_target_powerpc64 returning saved $powerpc64_available_saved" 2
3117 set powerpc64_available_saved
0
3119 # Some simulators are known to not support powerpc64 instructions.
3120 if { [istarget powerpc
-*-eabi
*] ||
[istarget powerpc
-ibm
-aix
*] } {
3121 verbose
"check_effective_target_powerpc64 returning 0" 2
3122 return $powerpc64_available_saved
3125 #
Set up
, compile, and
execute a test
program containing a
64-bit
3126 # instruction.
Include the current process ID in the file
3127 # names to prevent conflicts with invocations
for multiple
3132 set f
[open $src
"w"]
3133 puts $f
"int main() {"
3134 puts $f
"#ifdef __MACH__"
3135 puts $f
" asm volatile (\"extsw r0,r0\");"
3137 puts $f
" asm volatile (\"extsw 0,0\");"
3139 puts $f
" return 0; }"
3142 set opts
"additional_flags=-mcpu=G5"
3144 verbose
"check_effective_target_powerpc64 compiling testfile $src" 2
3145 set lines
[$
{tool
}_target_compile $src $exe executable
"$opts"]
3148 if [string match
"" $lines] then {
3149 # No error message
, compilation succeeded.
3150 set result
[$
{tool
}_load
"./$exe" "" ""]
3151 set status [lindex $result
0]
3152 remote_file build
delete $exe
3153 verbose
"check_effective_target_powerpc64 testfile status is <$status>" 2
3155 if { $
status == "pass" } then {
3156 set powerpc64_available_saved
1
3159 verbose
"check_effective_target_powerpc64 testfile compilation failed" 2
3163 return $powerpc64_available_saved
3166 # GCC
3.4.0 for powerpc64
-*-linux
* included an ABI fix
for passing
3167 # complex float arguments. This affects gfortran tests that
call cabsf
3168 # in libm built by an earlier compiler.
Return 0 if libm uses the same
3169 #
argument passing as the compiler under test
, 1 otherwise.
3171 proc check_effective_target_broken_cplxf_arg
{ } {
3172 # Skip the work
for targets known not to be affected.
3173 if { ![istarget powerpc
*-*-linux
*] ||
![is
-effective
-target lp64
] } {
3177 return [check_cached_effective_target broken_cplxf_arg
{
3178 check_runtime_nocache broken_cplxf_arg
{
3179 #
include <complex.h
>
3180 extern void abort
(void
);
3181 float fabsf
(float
);
3182 float cabsf
(_Complex float
);
3189 if (fabsf
(f
- 5.0) > 0.0001)
3190 /* Yes
, it
's broken. */
3192 /* All fine, not broken. */
3199 # Return 1 is this is a TI C6X target supporting C67X instructions
3200 proc check_effective_target_ti_c67x { } {
3201 return [check_no_compiler_messages ti_c67x assembly {
3202 #if !defined(_TMS320C6700)
3203 #error !_TMS320C6700
3208 # Return 1 is this is a TI C6X target supporting C64X+ instructions
3209 proc check_effective_target_ti_c64xp { } {
3210 return [check_no_compiler_messages ti_c64xp assembly {
3211 #if !defined(_TMS320C6400_PLUS)
3212 #error !_TMS320C6400_PLUS
3217 # Check if a -march=... option is given, as part of (earlier) options.
3218 proc check_effective_target_march_option { } {
3219 return [check-flags [list "" { *-*-* } { "-march=*" } { "" } ]]
3222 proc check_alpha_max_hw_available { } {
3223 return [check_runtime alpha_max_hw_available {
3224 int main() { return __builtin_alpha_amask(1<<8) != 0; }
3228 # Returns true iff the FUNCTION is available on the target system.
3229 # (This is essentially a Tcl implementation of Autoconf's
3232 proc check_function_available
{ function
} {
3233 return [check_no_compiler_messages $
{function
}_available \
3239 int main
() { $function
(); }
3243 # Returns true iff
"fork" is available on the target system.
3245 proc check_fork_available
{} {
3246 if { [istarget
*-*-vxworks
*] } {
3247 # VxWorks doesn
't have fork but our way to test can't
3248 # tell as we
're doing partial links for kernel modules.
3251 if { [istarget cris-*-*] } {
3252 # Compiling and linking works, and an executable running e.g.
3253 # gcc.dg/torture/ftrapv-1.c works on now-historical hardware,
3254 # but the GNU simulator emits an error for the fork syscall.
3255 return [check_effective_target_hw]
3257 return [check_function_available "fork"]
3260 # Returns true iff "mkfifo" is available on the target system.
3262 proc check_mkfifo_available {} {
3263 if { [istarget *-*-cygwin*] } {
3264 # Cygwin has mkfifo, but support is incomplete.
3268 return [check_function_available "mkfifo"]
3271 # Returns true iff "__cxa_atexit" is used on the target system.
3273 proc check_cxa_atexit_available { } {
3274 return [check_cached_effective_target cxa_atexit_available {
3275 if { [istarget *-*-vxworks] } {
3276 # vxworks doesn't have __cxa_atexit but subsequent test passes.
3279 check_runtime_nocache cxa_atexit_available
{
3282 static unsigned
int count;
3299 Y
() { f
(); count = 2; }
3308 int main
() { return 0; }
3314 proc check_effective_target_objc2
{ } {
3315 return [check_no_compiler_messages objc2 object
{
3324 proc check_effective_target_next_runtime
{ } {
3325 return [check_no_compiler_messages objc2 object
{
3326 #ifdef __NEXT_RUNTIME__
3329 #error
!__NEXT_RUNTIME__
3334 #
Return 1 if we
're generating code for big-endian memory order.
3336 proc check_effective_target_be { } {
3337 return [check_no_compiler_messages be object {
3338 int dummy[__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ ? 1 : -1];
3342 # Return 1 if we're generating code
for little
-endian memory order.
3344 proc check_effective_target_le
{ } {
3345 return [check_no_compiler_messages le object
{
3346 int dummy
[__BYTE_ORDER__
== __ORDER_LITTLE_ENDIAN__ ?
1 : -1];
3350 #
Return 1 if we can link a
program with
2+GB of data.
3352 proc check_effective_target_two_plus_gigs
{ } {
3353 return [check_no_compiler_messages two_plus_gigs executable
{
3354 char dummy
[0x80000000];
3355 int main
() { return 0; }
3359 #
Return 1 if we
're generating 32-bit code using default options, 0
3362 proc check_effective_target_ilp32 { } {
3363 return [check_no_compiler_messages ilp32 object {
3364 int dummy[sizeof (int) == 4
3365 && sizeof (void *) == 4
3366 && sizeof (long) == 4 ? 1 : -1];
3370 # Return 1 if we're generating ia32 code using default options
, 0
3373 proc check_effective_target_ia32
{ } {
3374 return [check_no_compiler_messages ia32 object
{
3375 int dummy
[sizeof
(int) == 4
3376 && sizeof
(void
*) == 4
3377 && sizeof
(long
) == 4 ?
1 : -1] = { __i386__
};
3381 #
Return 1 if we
're generating x32 code using default options, 0
3384 proc check_effective_target_x32 { } {
3385 return [check_no_compiler_messages x32 object {
3386 int dummy[sizeof (int) == 4
3387 && sizeof (void *) == 4
3388 && sizeof (long) == 4 ? 1 : -1] = { __x86_64__ };
3392 # Return 1 if we're generating
32-bit integers using default
3393 # options
, 0 otherwise.
3395 proc check_effective_target_int32
{ } {
3396 return [check_no_compiler_messages int32 object
{
3397 int dummy
[sizeof
(int) == 4 ?
1 : -1];
3401 #
Return 1 if we
're generating 32-bit or larger integers using default
3402 # options, 0 otherwise.
3404 proc check_effective_target_int32plus { } {
3405 return [check_no_compiler_messages int32plus object {
3406 int dummy[sizeof (int) >= 4 ? 1 : -1];
3410 # Return 1 if we're generating
64-bit long long using default options
,
3413 proc check_effective_target_longlong64
{ } {
3414 return [check_no_compiler_messages longlong64 object
{
3415 int dummy
[sizeof
(long long
) == 8 ?
1 : -1];
3419 #
Return 1 if we
're generating 32-bit or larger pointers using default
3420 # options, 0 otherwise.
3422 proc check_effective_target_ptr32plus { } {
3423 # The msp430 has 16-bit or 20-bit pointers. The 20-bit pointer is stored
3424 # in a 32-bit slot when in memory, so sizeof(void *) returns 4, but it
3425 # cannot really hold a 32-bit address, so we always return false here.
3426 if { [istarget msp430-*-*] } {
3430 return [check_no_compiler_messages ptr32plus object {
3431 int dummy[sizeof (void *) >= 4 ? 1 : -1];
3435 # Return 1 if we support 16-bit or larger array and structure sizes
3436 # using default options, 0 otherwise.
3437 # This implies at least a 20-bit address space, as no targets have an address
3438 # space between 16 and 20 bits.
3440 proc check_effective_target_size20plus { } {
3441 return [check_no_compiler_messages size20plus object {
3446 # Return 1 if target supports function pointers, 0 otherwise.
3448 proc check_effective_target_function_pointers { } {
3449 if { [istarget pru-*-*] } {
3450 return [check_no_compiler_messages func_ptr_avail assembly {
3451 #ifdef __PRU_EABI_GNU__
3459 # Return 1 if target supports arbitrarily large return values, 0 otherwise.
3461 proc check_effective_target_large_return_values { } {
3462 if { [istarget pru-*-*] } {
3463 return [check_no_compiler_messages large_return_values assembly {
3464 #ifdef __PRU_EABI_GNU__
3471 # Return 1 if we support 20-bit or larger array and structure sizes
3472 # using default options, 0 otherwise.
3473 # This implies at least a 24-bit address space, as no targets have an address
3474 # space between 20 and 24 bits.
3476 proc check_effective_target_size24plus { } {
3477 return [check_no_compiler_messages size24plus object {
3478 char dummy[524289L];
3482 # Return 1 if we support 24-bit or larger array and structure sizes
3483 # using default options, 0 otherwise.
3484 # This implies at least a 32-bit address space, as no targets have an address
3485 # space between 24 and 32 bits.
3487 proc check_effective_target_size32plus { } {
3488 return [check_no_compiler_messages size32plus object {
3489 char dummy[16777217L];
3493 # Returns 1 if we're generating
16-bit or smaller integers with the
3494 # default options
, 0 otherwise.
3496 proc check_effective_target_int16
{ } {
3497 return [check_no_compiler_messages int16 object
{
3498 int dummy
[sizeof
(int) < 4 ?
1 : -1];
3502 #
Return 1 if we
're generating 64-bit code using default options, 0
3505 proc check_effective_target_lp64 { } {
3506 return [check_no_compiler_messages lp64 object {
3507 int dummy[sizeof (int) == 4
3508 && sizeof (void *) == 8
3509 && sizeof (long) == 8 ? 1 : -1];
3513 # Return 1 if we're generating
64-bit code using default llp64 options
,
3516 proc check_effective_target_llp64
{ } {
3517 return [check_no_compiler_messages llp64 object
{
3518 int dummy
[sizeof
(int) == 4
3519 && sizeof
(void
*) == 8
3520 && sizeof
(long long
) == 8
3521 && sizeof
(long
) == 4 ?
1 : -1];
3525 #
Return 1 if long and
int have different sizes
,
3528 proc check_effective_target_long_neq_int
{ } {
3529 return [check_no_compiler_messages long_ne_int object
{
3530 int dummy
[sizeof
(int) != sizeof
(long
) ?
1 : -1];
3534 #
Return 1 if int size is equal to float size
,
3537 proc check_effective_target_int_eq_float
{ } {
3538 return [check_no_compiler_messages int_eq_float object
{
3539 int dummy
[sizeof
(int) >= sizeof
(float
) ?
1 : -1];
3543 #
Return 1 if short size is equal to
int size
,
3546 proc check_effective_target_short_eq_int
{ } {
3547 return [check_no_compiler_messages short_eq_int object
{
3548 int dummy
[sizeof
(short
) == sizeof
(int) ?
1 : -1];
3552 #
Return 1 if pointer size is equal to short size
,
3555 proc check_effective_target_ptr_eq_short
{ } {
3556 return [check_no_compiler_messages ptr_eq_short object
{
3557 int dummy
[sizeof
(void
*) == sizeof
(short
) ?
1 : -1];
3561 #
Return 1 if pointer size is equal to long size
,
3564 proc check_effective_target_ptr_eq_long
{ } {
3565 # sizeof
(void
*) == 4 for msp430
-elf
-mlarge which is equal to
3566 # sizeof
(long
). Avoid false positive.
3567 if { [istarget msp430
-*-*] } {
3570 return [check_no_compiler_messages ptr_eq_long object
{
3571 int dummy
[sizeof
(void
*) == sizeof
(long
) ?
1 : -1];
3575 #
Return 1 if the target supports long double larger than double
,
3578 proc check_effective_target_large_long_double
{ } {
3579 return [check_no_compiler_messages large_long_double object
{
3580 int dummy
[sizeof
(long double
) > sizeof
(double
) ?
1 : -1];
3584 #
Return 1 if the target supports double larger than float
,
3587 proc check_effective_target_large_double
{ } {
3588 return [check_no_compiler_messages large_double object
{
3589 int dummy
[sizeof
(double
) > sizeof
(float
) ?
1 : -1];
3593 #
Return 1 if the target supports long double of
128 bits
,
3596 proc check_effective_target_longdouble128
{ } {
3597 return [check_no_compiler_messages longdouble128 object
{
3598 int dummy
[sizeof
(long double
) == 16 ?
1 : -1];
3602 #
Return 1 if the target supports long double of
64 bits
,
3605 proc check_effective_target_longdouble64
{ } {
3606 return [check_no_compiler_messages longdouble64 object
{
3607 int dummy
[sizeof
(long double
) == 8 ?
1 : -1];
3611 #
Return 1 if the target supports double of
64 bits
,
3614 proc check_effective_target_double64
{ } {
3615 return [check_no_compiler_messages double64 object
{
3616 int dummy
[sizeof
(double
) == 8 ?
1 : -1];
3620 #
Return 1 if the target supports double of at least
64 bits
,
3623 proc check_effective_target_double64plus
{ } {
3624 return [check_no_compiler_messages double64plus object
{
3625 int dummy
[sizeof
(double
) >= 8 ?
1 : -1];
3629 #
Return 1 if the target supports
'w' suffix
on floating constant
3632 proc check_effective_target_has_w_floating_suffix
{ } {
3634 if [check_effective_target_c
++] {
3635 append opts
"-std=gnu++03"
3637 return [check_no_compiler_messages w_fp_suffix object
{
3642 #
Return 1 if the target supports
'q' suffix
on floating constant
3645 proc check_effective_target_has_q_floating_suffix
{ } {
3647 if [check_effective_target_c
++] {
3648 append opts
"-std=gnu++03"
3650 return [check_no_compiler_messages q_fp_suffix object
{
3655 #
Return 1 if the target supports the _FloatN
/ _FloatNx type
3656 # indicated in the function
name, 0 otherwise.
3658 proc check_effective_target_float16
{} {
3659 return [check_no_compiler_messages_nocache float16 object
{
3660 _Float16 foo
(_Float16 x
) { return x
; }
3661 } [add_options_for_float16
""]]
3664 proc check_effective_target_float32
{} {
3665 return [check_no_compiler_messages_nocache float32 object
{
3667 } [add_options_for_float32
""]]
3670 proc check_effective_target_float64
{} {
3671 return [check_no_compiler_messages_nocache float64 object
{
3673 } [add_options_for_float64
""]]
3676 proc check_effective_target_float128
{} {
3677 return [check_no_compiler_messages_nocache float128 object
{
3679 } [add_options_for_float128
""]]
3682 proc check_effective_target_float32x
{} {
3683 return [check_no_compiler_messages_nocache float32x object
{
3685 } [add_options_for_float32x
""]]
3688 proc check_effective_target_float64x
{} {
3689 return [check_no_compiler_messages_nocache float64x object
{
3691 } [add_options_for_float64x
""]]
3694 proc check_effective_target_float128x
{} {
3695 return [check_no_compiler_messages_nocache float128x object
{
3697 } [add_options_for_float128x
""]]
3700 # Likewise
, but runtime support
for any special options used as well
3701 # as
compile-time support is required.
3703 proc check_effective_target_float16_runtime
{} {
3704 return [check_effective_target_float16
]
3707 proc check_effective_target_float32_runtime
{} {
3708 return [check_effective_target_float32
]
3711 proc check_effective_target_float64_runtime
{} {
3712 return [check_effective_target_float64
]
3715 proc check_effective_target_float128_runtime
{} {
3716 if { ![check_effective_target_float128
] } {
3719 if { [istarget powerpc
*-*-*] } {
3720 return [check_effective_target_base_quadfloat_support
]
3725 proc check_effective_target_float32x_runtime
{} {
3726 return [check_effective_target_float32x
]
3729 proc check_effective_target_float64x_runtime
{} {
3730 if { ![check_effective_target_float64x
] } {
3733 if { [istarget powerpc
*-*-*] } {
3734 return [check_effective_target_base_quadfloat_support
]
3739 proc check_effective_target_float128x_runtime
{} {
3740 return [check_effective_target_float128x
]
3743 #
Return 1 if the target hardware supports
any options added
for
3744 # _FloatN and _FloatNx types
, 0 otherwise.
3746 proc check_effective_target_floatn_nx_runtime
{} {
3747 if { [istarget powerpc
*-*-aix
*] } {
3750 if { [istarget powerpc
*-*-*] } {
3751 return [check_effective_target_base_quadfloat_support
]
3756 # Add options needed to use the _FloatN
/ _FloatNx type indicated in
3757 # the function
name.
3759 proc add_options_for_float16
{ flags
} {
3760 if { [istarget arm
*-*-*] } {
3761 return "$flags -mfp16-format=ieee"
3763 if { [istarget i?
86-*-*] ||
[istarget x86_64
-*-*] } {
3764 return "$flags -msse2"
3769 proc add_options_for_float32
{ flags
} {
3773 proc add_options_for_float64
{ flags
} {
3777 proc add_options_for_float128
{ flags
} {
3778 return [add_options_for___float128
"$flags"]
3781 proc add_options_for_float32x
{ flags
} {
3785 proc add_options_for_float64x
{ flags
} {
3786 return [add_options_for___float128
"$flags"]
3789 proc add_options_for_float128x
{ flags
} {
3793 #
Return 1 if the target supports __float128
,
3796 proc check_effective_target___float128
{ } {
3797 if { [istarget powerpc
*-*-*] } {
3798 return [check_ppc_float128_sw_available
]
3800 if { [istarget ia64
-*-*]
3801 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*] } {
3807 proc add_options_for___float128
{ flags
} {
3808 if { [istarget powerpc
*-*-linux
*] } {
3809 return "$flags -mfloat128 -mvsx"
3814 #
Return 1 if the target supports
any special run
-time requirements
3815 #
for __float128 or _Float128
,
3818 proc check_effective_target_base_quadfloat_support
{ } {
3819 if { [istarget powerpc
*-*-*] } {
3820 return [check_vsx_hw_available
]
3825 #
Return 1 if the target supports the __bf16 type
, 0 otherwise.
3827 proc check_effective_target_bfloat16
{} {
3828 return [check_no_compiler_messages_nocache bfloat16 object
{
3829 __bf16 foo
(__bf16 x
) { return x
+ x
; }
3830 } [add_options_for_bfloat16
""]]
3833 proc check_effective_target_bfloat16_runtime
{} {
3834 return [check_effective_target_bfloat16
]
3837 proc add_options_for_bfloat16
{ flags
} {
3841 #
Return 1 if the target supports all four forms of fused multiply
-add
3842 #
(fma
, fms
, fnma
, and fnms
) for both float and double.
3844 proc check_effective_target_scalar_all_fma
{ } {
3845 return [istarget aarch64
*-*-*]
3848 #
Return 1 if the target supports compiling fixed
-point
,
3851 proc check_effective_target_fixed_point
{ } {
3852 return [check_no_compiler_messages fixed_point object
{
3853 _Sat _Fract x
; _Sat _Accum y
;
3857 #
Return 1 if the target supports _BitInt
(N
), 0 otherwise.
3859 proc check_effective_target_bitint
{ } {
3860 return [check_no_compiler_messages bitint object
{
3861 _BitInt
(2) a
= 1wb
;
3862 unsigned _BitInt
(__BITINT_MAXWIDTH__
) b
= 0uwb
;
3866 #
Return 1 if the target supports _BitInt
(128), 0 otherwise.
3868 proc check_effective_target_bitint128
{ } {
3869 return [check_no_compiler_messages bitint128 object
{
3870 _BitInt
(2) a
= 1wb
;
3871 unsigned _BitInt
(128) b
= 0uwb
;
3875 #
Return 1 if the target supports _BitInt
(575), 0 otherwise.
3877 proc check_effective_target_bitint575
{ } {
3878 return [check_no_compiler_messages bitint575 object
{
3879 _BitInt
(2) a
= 1wb
;
3880 unsigned _BitInt
(575) b
= 0uwb
;
3884 #
Return 1 if the target supports compiling decimal floating point
,
3887 proc check_effective_target_dfp_nocache
{ } {
3888 verbose
"check_effective_target_dfp_nocache: compiling source" 2
3889 set ret
[check_no_compiler_messages_nocache dfp object
{
3890 float x __attribute__
((mode(DD
)));
3892 verbose
"check_effective_target_dfp_nocache: returning $ret" 2
3896 proc check_effective_target_dfprt_nocache
{ } {
3897 return [check_runtime_nocache dfprt
{
3898 typedef float d64 __attribute__
((mode(DD
)));
3899 d64 x
= 1.2df
, y
= 2.3dd
, z
;
3900 int main
() { z
= x
+ y
; return 0; }
3904 #
Return 1 if the target supports compiling Decimal Floating Point
,
3907 # This won
't change for different subtargets so cache the result.
3909 proc check_effective_target_dfp { } {
3910 return [check_cached_effective_target dfp {
3911 check_effective_target_dfp_nocache
3915 # Return 1 if the target supports linking and executing Decimal Floating
3916 # Point, 0 otherwise.
3918 # This won't change
for different subtargets so
cache the result.
3920 proc check_effective_target_dfprt
{ } {
3921 return [check_cached_effective_target dfprt
{
3922 check_effective_target_dfprt_nocache
3926 #
Return 1 if the target uses the BID format
for Decimal Floating
3927 # Point
, 0 otherwise.
3929 proc check_effective_target_dfp_bid
{ } {
3930 if { [istarget aarch64
*-*-*]
3931 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]} {
3937 #
Return 1 iff target has unsigned plain
'char' by default.
3939 proc check_effective_target_unsigned_char
{} {
3940 return [check_no_compiler_messages unsigned_char assembly
{
3945 proc check_effective_target_powerpc_popcntb_ok
{ } {
3946 return [check_cached_effective_target powerpc_popcntb_ok
{
3948 # Disable
on Darwin.
3949 if { [istarget powerpc
-*-eabi
] ||
[istarget powerpc
*-*-eabispe
] ||
[istarget
*-*-darwin
*]} {
3952 check_runtime_nocache powerpc_popcntb_ok
{
3954 volatile
int a
= 0x12345678;
3957 asm volatile
("popcntb %0,%1" : "=r" (r) : "r" (a));
3965 #
Return 1 if the target supports executing DFP hardware instructions
,
3966 #
0 otherwise.
Cache the result.
3968 proc check_dfp_hw_available
{ } {
3969 return [check_cached_effective_target dfp_hw_available
{
3970 #
For now
, disable
on Darwin
3971 if { [istarget powerpc
-*-eabi
] ||
[istarget powerpc
*-*-eabispe
] ||
[istarget
*-*-darwin
*]} {
3974 check_runtime_nocache dfp_hw_available
{
3975 volatile _Decimal64 r
;
3976 volatile _Decimal64 a
= 4.0DD
;
3977 volatile _Decimal64 b
= 2.0DD
;
3980 asm volatile
("dadd %0,%1,%2" : "=d" (r) : "d" (a), "d" (b));
3981 asm volatile
("dsub %0,%1,%2" : "=d" (r) : "d" (a), "d" (b));
3982 asm volatile
("dmul %0,%1,%2" : "=d" (r) : "d" (a), "d" (b));
3983 asm volatile
("ddiv %0,%1,%2" : "=d" (r) : "d" (a), "d" (b));
3986 } "-mcpu=power6 -mhard-float"
3991 #
Return 1 if the target supports compiling and assembling UCN
, 0 otherwise.
3993 proc check_effective_target_ucn_nocache
{ } {
3994 #
-std
=c99 is only valid
for C
3995 if [check_effective_target_c
] {
3996 set ucnopts
"-std=c99"
4000 verbose
"check_effective_target_ucn_nocache: compiling source" 2
4001 set ret
[check_no_compiler_messages_nocache ucn object
{
4004 verbose
"check_effective_target_ucn_nocache: returning $ret" 2
4008 #
Return 1 if the target supports compiling and assembling UCN
, 0 otherwise.
4010 # This won
't change for different subtargets, so cache the result.
4012 proc check_effective_target_ucn { } {
4013 return [check_cached_effective_target ucn {
4014 check_effective_target_ucn_nocache
4018 # Return 1 if the target needs a command line argument to enable a SIMD
4021 proc check_effective_target_vect_cmdline_needed { } {
4022 global et_vect_cmdline_needed_target_name
4024 if { ![info exists et_vect_cmdline_needed_target_name] } {
4025 set et_vect_cmdline_needed_target_name ""
4028 # If the target has changed since we set the cached value, clear it.
4029 set current_target [current_target_name]
4030 if { $current_target != $et_vect_cmdline_needed_target_name } {
4031 verbose "check_effective_target_vect_cmdline_needed: `$et_vect_cmdline_needed_target_name' `$current_target
'" 2
4032 set et_vect_cmdline_needed_target_name $current_target
4033 if { [info exists et_vect_cmdline_needed_saved] } {
4034 verbose "check_effective_target_vect_cmdline_needed: removing cached result" 2
4035 unset et_vect_cmdline_needed_saved
4039 return [check_cached_effective_target vect_cmdline_needed {
4040 if { [istarget alpha*-*-*]
4041 || [istarget ia64-*-*]
4042 || (([istarget i?86-*-*] || [istarget x86_64-*-*])
4043 && ![is-effective-target ia32])
4044 || ([istarget powerpc*-*-*]
4045 && ([check_effective_target_powerpc_spe]
4046 || [check_effective_target_powerpc_altivec]))
4047 || ([istarget sparc*-*-*] && [check_effective_target_sparc_vis])
4048 || ([istarget arm*-*-*] && [check_effective_target_arm_neon])
4049 || [istarget aarch64*-*-*]
4050 || [istarget amdgcn*-*-*]
4051 || [istarget riscv*-*-*]} {
4058 # Return 1 if the target supports hardware vectors of int, 0 otherwise.
4060 # This won't change
for different subtargets so
cache the result.
4062 proc check_effective_target_vect_int
{ } {
4063 return [check_cached_effective_target_indexed vect_int
{
4065 [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
4066 ||
([istarget powerpc
*-*-*]
4067 && ![istarget powerpc
-*-linux
*paired
*])
4068 ||
[istarget amdgcn
-*-*]
4069 ||
[istarget sparc
*-*-*]
4070 ||
[istarget alpha
*-*-*]
4071 ||
[istarget ia64
-*-*]
4072 ||
[istarget aarch64
*-*-*]
4073 ||
[is
-effective
-target arm_neon
]
4074 ||
([istarget mips
*-*-*]
4075 && ([et
-is
-effective
-target mips_loongson_mmi
]
4076 ||
[et
-is
-effective
-target mips_msa
]))
4077 ||
([istarget s390
*-*-*]
4078 && [check_effective_target_s390_vx
])
4079 ||
([istarget riscv
*-*-*]
4080 && [check_effective_target_riscv_v
])
4084 #
Return 1 if the target supports hardware vectorization of complex additions of
4085 # byte
, 0 otherwise.
4087 # This won
't change for different subtargets so cache the result.
4089 proc check_effective_target_vect_complex_add_byte { } {
4090 return [check_cached_effective_target_indexed vect_complex_add_byte {
4092 ([check_effective_target_aarch64_sve2]
4093 && [check_effective_target_aarch64_little_endian])
4094 || ([check_effective_target_arm_v8_1m_mve_fp_ok]
4095 && [check_effective_target_arm_little_endian])
4099 # Return 1 if the target supports hardware vectorization of complex additions of
4100 # short, 0 otherwise.
4102 # This won't change
for different subtargets so
cache the result.
4104 proc check_effective_target_vect_complex_add_short
{ } {
4105 return [check_cached_effective_target_indexed vect_complex_add_short
{
4107 ([check_effective_target_aarch64_sve2
]
4108 && [check_effective_target_aarch64_little_endian
])
4109 ||
([check_effective_target_arm_v8_1m_mve_fp_ok
]
4110 && [check_effective_target_arm_little_endian
])
4114 #
Return 1 if the target supports hardware vectorization of complex additions of
4117 # This won
't change for different subtargets so cache the result.
4119 proc check_effective_target_vect_complex_add_int { } {
4120 return [check_cached_effective_target_indexed vect_complex_add_int {
4122 ([check_effective_target_aarch64_sve2]
4123 && [check_effective_target_aarch64_little_endian])
4124 || ([check_effective_target_arm_v8_1m_mve_fp_ok]
4125 && [check_effective_target_arm_little_endian])
4129 # Return 1 if the target supports hardware vectorization of complex additions of
4130 # long, 0 otherwise.
4132 # This won't change
for different subtargets so
cache the result.
4134 proc check_effective_target_vect_complex_add_long
{ } {
4135 return [check_cached_effective_target_indexed vect_complex_add_long
{
4137 ([check_effective_target_aarch64_sve2
]
4138 && [check_effective_target_aarch64_little_endian
])
4139 ||
([check_effective_target_arm_v8_1m_mve_fp_ok
]
4140 && [check_effective_target_arm_little_endian
])
4144 #
Return 1 if the target supports hardware vectorization of complex additions of
4145 # half
, 0 otherwise.
4147 # This won
't change for different subtargets so cache the result.
4149 proc check_effective_target_vect_complex_add_half { } {
4150 return [check_cached_effective_target_indexed vect_complex_add_half {
4152 ([check_effective_target_arm_v8_3a_fp16_complex_neon_ok]
4153 && ([check_effective_target_aarch64_little_endian]
4154 || [check_effective_target_arm_little_endian]))
4155 || ([check_effective_target_aarch64_sve2]
4156 && [check_effective_target_aarch64_little_endian])
4157 || ([check_effective_target_arm_v8_1m_mve_fp_ok]
4158 && [check_effective_target_arm_little_endian])
4162 # Return 1 if the target supports hardware vectorization of complex additions of
4163 # float, 0 otherwise.
4165 # This won't change
for different subtargets so
cache the result.
4167 proc check_effective_target_vect_complex_add_float
{ } {
4168 return [check_cached_effective_target_indexed vect_complex_add_float
{
4170 ([check_effective_target_arm_v8_3a_complex_neon_ok
]
4171 && ([check_effective_target_aarch64_little_endian
]
4172 ||
[check_effective_target_arm_little_endian
]))
4173 ||
([check_effective_target_aarch64_sve2
]
4174 && [check_effective_target_aarch64_little_endian
])
4175 ||
([check_effective_target_arm_v8_1m_mve_fp_ok
]
4176 && [check_effective_target_arm_little_endian
])
4180 #
Return 1 if the target supports hardware vectorization of complex additions of
4181 # double
, 0 otherwise.
4183 # This won
't change for different subtargets so cache the result.
4185 proc check_effective_target_vect_complex_add_double { } {
4186 return [check_cached_effective_target_indexed vect_complex_add_double {
4188 (([check_effective_target_arm_v8_3a_complex_neon_ok]
4189 && [check_effective_target_aarch64_little_endian])
4190 || ([check_effective_target_aarch64_sve2]
4191 && [check_effective_target_aarch64_little_endian]))
4195 # Return 1 if the target supports signed int->float conversion
4198 proc check_effective_target_vect_intfloat_cvt { } {
4199 return [check_cached_effective_target_indexed vect_intfloat_cvt {
4200 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
4201 || ([istarget powerpc*-*-*]
4202 && ![istarget powerpc-*-linux*paired*])
4203 || [is-effective-target arm_neon]
4204 || ([istarget mips*-*-*]
4205 && [et-is-effective-target mips_msa])
4206 || [istarget amdgcn-*-*]
4207 || ([istarget s390*-*-*]
4208 && [check_effective_target_s390_vxe2])
4209 || ([istarget riscv*-*-*]
4210 && [check_effective_target_riscv_v]) }}]
4213 # Return 1 if the target supports signed double->int conversion
4216 proc check_effective_target_vect_doubleint_cvt { } {
4217 return [check_cached_effective_target_indexed vect_doubleint_cvt {
4218 expr { (([istarget i?86-*-*] || [istarget x86_64-*-*])
4219 && [check_no_compiler_messages vect_doubleint_cvt assembly {
4220 #ifdef __tune_atom__
4221 # error No double vectorizer support.
4224 || [istarget aarch64*-*-*]
4225 || ([istarget powerpc*-*-*] && [check_vsx_hw_available])
4226 || ([istarget mips*-*-*]
4227 && [et-is-effective-target mips_msa])
4228 || ([istarget s390*-*-*]
4229 && [check_effective_target_s390_vx])
4230 || ([istarget riscv*-*-*]
4231 && [check_effective_target_riscv_v]) }}]
4234 # Return 1 if the target supports signed int->double conversion
4237 proc check_effective_target_vect_intdouble_cvt { } {
4238 return [check_cached_effective_target_indexed vect_intdouble_cvt {
4239 expr { (([istarget i?86-*-*] || [istarget x86_64-*-*])
4240 && [check_no_compiler_messages vect_intdouble_cvt assembly {
4241 #ifdef __tune_atom__
4242 # error No double vectorizer support.
4245 || [istarget aarch64*-*-*]
4246 || ([istarget powerpc*-*-*] && [check_vsx_hw_available])
4247 || ([istarget mips*-*-*]
4248 && [et-is-effective-target mips_msa])
4249 || ([istarget s390*-*-*]
4250 && [check_effective_target_s390_vx])
4251 || ([istarget riscv*-*-*]
4252 && [check_effective_target_riscv_v]) }}]
4255 #Return 1 if we're supporting __int128
for target
, 0 otherwise.
4257 proc check_effective_target_int128
{ } {
4258 return [check_no_compiler_messages int128 object
{
4260 #ifndef __SIZEOF_INT128__
4269 #
Return 1 if the target supports unsigned
int->float conversion
4272 proc check_effective_target_vect_uintfloat_cvt
{ } {
4273 return [check_cached_effective_target_indexed vect_uintfloat_cvt
{
4274 expr
{ [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
4275 ||
([istarget powerpc
*-*-*]
4276 && ![istarget powerpc
-*-linux
*paired
*])
4277 ||
[istarget aarch64
*-*-*]
4278 ||
[is
-effective
-target arm_neon
]
4279 ||
([istarget mips
*-*-*]
4280 && [et
-is
-effective
-target mips_msa
])
4281 ||
[istarget amdgcn
-*-*]
4282 ||
([istarget s390
*-*-*]
4283 && [check_effective_target_s390_vxe2
])
4284 ||
([istarget riscv
*-*-*]
4285 && [check_effective_target_riscv_v
]) }}]
4289 #
Return 1 if the target supports signed float
->int conversion
4292 proc check_effective_target_vect_floatint_cvt
{ } {
4293 return [check_cached_effective_target_indexed vect_floatint_cvt
{
4294 expr
{ [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
4295 ||
([istarget powerpc
*-*-*]
4296 && ![istarget powerpc
-*-linux
*paired
*])
4297 ||
[is
-effective
-target arm_neon
]
4298 ||
([istarget mips
*-*-*]
4299 && [et
-is
-effective
-target mips_msa
])
4300 ||
[istarget amdgcn
-*-*]
4301 ||
([istarget s390
*-*-*]
4302 && [check_effective_target_s390_vxe2
])
4303 ||
([istarget riscv
*-*-*]
4304 && [check_effective_target_riscv_v
]) }}]
4307 #
Return 1 if the target supports unsigned float
->int conversion
4310 proc check_effective_target_vect_floatuint_cvt
{ } {
4311 return [check_cached_effective_target_indexed vect_floatuint_cvt
{
4312 expr
{ ([istarget powerpc
*-*-*]
4313 && ![istarget powerpc
-*-linux
*paired
*])
4314 ||
[is
-effective
-target arm_neon
]
4315 ||
([istarget mips
*-*-*]
4316 && [et
-is
-effective
-target mips_msa
])
4317 ||
[istarget amdgcn
-*-*]
4318 ||
([istarget s390
*-*-*]
4319 && [check_effective_target_s390_vxe2
])
4320 ||
([istarget riscv
*-*-*]
4321 && [check_effective_target_riscv_v
]) }}]
4324 #
Return 1 if the target supports vector
integer char
-> long long extend optab
4327 proc check_effective_target_vect_ext_char_longlong
{ } {
4328 return [check_cached_effective_target_indexed vect_ext_char_longlong
{
4329 expr
{ ([istarget riscv
*-*-*]
4330 && [check_effective_target_riscv_v
]) }}]
4333 #
Return 1 if peeling
for alignment might be profitable
on the target
4336 proc check_effective_target_vect_peeling_profitable
{ } {
4337 return [check_cached_effective_target_indexed vect_peeling_profitable
{
4338 expr
{ ([istarget s390
*-*-*]
4339 && [check_effective_target_s390_vx
])
4340 ||
[check_effective_target_vect_element_align_preferred
] }}]
4343 #
Return 1 if the target supports #pragma omp declare simd
, 0 otherwise.
4345 # This won
't change for different subtargets so cache the result.
4347 proc check_effective_target_vect_simd_clones { } {
4348 # On i?86/x86_64 #pragma omp declare simd builds a sse2, avx,
4349 # avx2 and avx512f clone. Only the right clone for the
4350 # specified arch will be chosen, but still we need to at least
4351 # be able to assemble avx512f.
4352 return [check_cached_effective_target_indexed vect_simd_clones {
4353 expr { (([istarget i?86-*-*] || [istarget x86_64-*-*])
4354 && [check_effective_target_avx512f])
4355 || [istarget amdgcn-*-*] }}]
4358 # Return 1 if this is a AArch64 target supporting big endian
4359 proc check_effective_target_aarch64_big_endian { } {
4360 return [check_no_compiler_messages aarch64_big_endian assembly {
4361 #if !defined(__aarch64__) || !defined(__AARCH64EB__)
4362 #error !__aarch64__ || !__AARCH64EB__
4367 # Return 1 if this is a AArch64 target supporting little endian
4368 proc check_effective_target_aarch64_little_endian { } {
4369 if { ![istarget aarch64*-*-*] } {
4373 return [check_no_compiler_messages aarch64_little_endian assembly {
4374 #if !defined(__aarch64__) || defined(__AARCH64EB__)
4380 # Return 1 if this is an AArch64 target supporting SVE.
4381 proc check_effective_target_aarch64_sve { } {
4382 if { ![istarget aarch64*-*-*] } {
4385 return [check_no_compiler_messages aarch64_sve assembly {
4386 #if !defined (__ARM_FEATURE_SVE)
4392 # Return 1 if this is an AArch64 target supporting SVE2.
4393 proc check_effective_target_aarch64_sve2 { } {
4394 if { ![istarget aarch64*-*-*] } {
4397 return [check_no_compiler_messages aarch64_sve2 assembly {
4398 #if !defined (__ARM_FEATURE_SVE2)
4404 # Return 1 if this is an AArch64 target only supporting SVE (not SVE2).
4405 proc check_effective_target_aarch64_sve1_only { } {
4406 return [expr { [check_effective_target_aarch64_sve]
4407 && ![check_effective_target_aarch64_sve2] }]
4410 # Return the size in bits of an SVE vector, or 0 if the size is variable.
4411 proc aarch64_sve_bits { } {
4412 return [check_cached_effective_target aarch64_sve_bits {
4415 set src dummy[pid].c
4416 set f [open $src "w"]
4417 puts $f "int bits = __ARM_FEATURE_SVE_BITS;"
4419 set output [${tool}_target_compile $src "" preprocess ""]
4422 regsub {.*bits = ([^;]*);.*} $output {\1} bits
4427 # Return 1 if this is a compiler supporting ARC atomic operations
4428 proc check_effective_target_arc_atomic { } {
4429 return [check_no_compiler_messages arc_atomic assembly {
4430 #if !defined(__ARC_ATOMIC__)
4436 # Return 1 if this is an arm target using 32-bit instructions
4437 proc check_effective_target_arm32 { } {
4438 if { ![istarget arm*-*-*] } {
4442 return [check_no_compiler_messages arm32 assembly {
4443 #if !defined(__arm__) || (defined(__thumb__) && !defined(__thumb2__))
4444 #error !__arm || __thumb__ && !__thumb2__
4449 # Return 1 if this is an arm target not using Thumb
4450 proc check_effective_target_arm_nothumb { } {
4451 if { ![istarget arm*-*-*] } {
4455 return [check_no_compiler_messages arm_nothumb assembly {
4456 #if !defined(__arm__) || (defined(__thumb__) || defined(__thumb2__))
4457 #error !__arm__ || __thumb || __thumb2__
4462 # Return 1 if this is a little-endian ARM target
4463 proc check_effective_target_arm_little_endian { } {
4464 if { ![istarget arm*-*-*] } {
4468 return [check_no_compiler_messages arm_little_endian assembly {
4469 #if !defined(__arm__) || !defined(__ARMEL__)
4470 #error !__arm__ || !__ARMEL__
4475 # Return 1 if this is an ARM target that only supports aligned vector accesses
4476 proc check_effective_target_arm_vect_no_misalign { } {
4477 if { ![istarget arm*-*-*] } {
4481 return [check_no_compiler_messages arm_vect_no_misalign assembly {
4482 #if !defined(__arm__) \
4483 || (defined(__ARM_FEATURE_UNALIGNED) \
4484 && defined(__ARMEL__))
4485 #error !__arm__ || (__ARMEL__ && __ARM_FEATURE_UNALIGNED)
4491 # Return 1 if this is an ARM target supporting -mfloat-abi=soft. Some
4492 # multilibs may be incompatible with this option.
4494 proc check_effective_target_arm_soft_ok { } {
4495 return [check_no_compiler_messages arm_soft_ok object {
4498 int main (void) { return 0; }
4499 } "-mfloat-abi=soft"]
4502 # Return 1 if this is an ARM target supporting -mfloat-abi=soft even
4503 # for linking. Some multilibs may be incompatible with this option,
4504 # and some linkers may reject incompatible options.
4506 proc check_effective_target_arm_soft_ok_link { } {
4507 return [check_no_compiler_messages arm_soft_ok_link executable {
4510 int main (void) { return 0; }
4511 } "-mfloat-abi=soft"]
4514 # Return 1 if this is an ARM target supporting -mfpu=vfp with an
4517 proc check_effective_target_arm_vfp_ok_nocache { } {
4518 global et_arm_vfp_flags
4519 set et_arm_vfp_flags ""
4520 if { [check_effective_target_arm32] } {
4521 foreach flags {"-mfpu=vfp" "-mfpu=vfp -mfloat-abi=softfp" "-mfpu=vfp -mfloat-abi=hard"} {
4522 if { [check_no_compiler_messages_nocache arm_vfp_ok object {
4524 #error __ARM_FP not defined
4527 set et_arm_vfp_flags $flags
4536 proc check_effective_target_arm_vfp_ok { } {
4537 return [check_cached_effective_target arm_vfp_ok \
4538 check_effective_target_arm_vfp_ok_nocache]
4541 # Add the options needed to compile code with -mfpu=vfp. We need either
4542 # -mfloat-abi=softfp or -mfloat-abi=hard, but if one is already
4543 # specified by the multilib, use it.
4545 proc add_options_for_arm_vfp { flags } {
4546 if { ! [check_effective_target_arm_vfp_ok] } {
4549 global et_arm_vfp_flags
4550 return "$flags $et_arm_vfp_flags"
4553 # Return 1 if this is an ARM target supporting -mfpu=vfp3
4554 # -mfloat-abi=softfp.
4556 proc check_effective_target_arm_vfp3_ok { } {
4557 if { [check_effective_target_arm32] } {
4558 return [check_no_compiler_messages arm_vfp3_ok object {
4560 } "-mfpu=vfp3 -mfloat-abi=softfp"]
4566 # Return 1 if this is an ARM target supporting -mfpu=fp-armv8
4567 # -mfloat-abi=softfp.
4568 proc check_effective_target_arm_v8_vfp_ok {} {
4569 if { [check_effective_target_arm32] } {
4570 return [check_no_compiler_messages arm_v8_vfp_ok object {
4573 __asm__ volatile ("vrinta.f32.f32 s0, s0");
4576 } "-mfpu=fp-armv8 -mfloat-abi=softfp"]
4582 # Return 1 if this is an ARM target supporting -mfpu=vfp
4583 # -mfloat-abi=hard. Some multilibs may be incompatible with these
4586 proc check_effective_target_arm_hard_vfp_ok { } {
4587 if { [check_effective_target_arm32]
4588 && ! [check-flags [list "" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" }]] } {
4589 return [check_no_compiler_messages arm_hard_vfp_ok executable {
4590 int main() { return 0;}
4591 } "-mfpu=vfp -mfloat-abi=hard"]
4597 # Return 1 if this is an ARM target defining __ARM_FP. We may need
4598 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
4599 # incompatible with these options. Also set et_arm_fp_flags to the
4600 # best options to add.
4602 proc check_effective_target_arm_fp_ok_nocache { } {
4603 global et_arm_fp_flags
4604 set et_arm_fp_flags ""
4605 if { [check_effective_target_arm32] } {
4606 foreach flags {"" "-mfloat-abi=softfp" "-mfloat-abi=hard"} {
4607 if { [check_no_compiler_messages_nocache arm_fp_ok object {
4609 #error __ARM_FP not defined
4612 set et_arm_fp_flags $flags
4621 proc check_effective_target_arm_fp_ok { } {
4622 return [check_cached_effective_target arm_fp_ok \
4623 check_effective_target_arm_fp_ok_nocache]
4626 # Add the options needed to define __ARM_FP. We need either
4627 # -mfloat-abi=softfp or -mfloat-abi=hard, but if one is already
4628 # specified by the multilib, use it.
4630 proc add_options_for_arm_fp { flags } {
4631 if { ! [check_effective_target_arm_fp_ok] } {
4634 global et_arm_fp_flags
4635 return "$flags $et_arm_fp_flags"
4638 # Return 1 if this is an ARM target defining __ARM_FP with
4639 # double-precision support. We may need -mfloat-abi=softfp or
4640 # equivalent options. Some multilibs may be incompatible with these
4641 # options. Also set et_arm_fp_dp_flags to the best options to add.
4643 proc check_effective_target_arm_fp_dp_ok_nocache { } {
4644 global et_arm_fp_dp_flags
4645 set et_arm_fp_dp_flags ""
4646 if { [check_effective_target_arm32] } {
4647 foreach flags {"" "-mfloat-abi=softfp" "-mfloat-abi=hard"} {
4648 if { [check_no_compiler_messages_nocache arm_fp_dp_ok object {
4650 #error __ARM_FP not defined
4652 #if ((__ARM_FP & 8) == 0)
4653 #error __ARM_FP indicates that double-precision is not supported
4656 set et_arm_fp_dp_flags $flags
4665 proc check_effective_target_arm_fp_dp_ok { } {
4666 return [check_cached_effective_target arm_fp_dp_ok \
4667 check_effective_target_arm_fp_dp_ok_nocache]
4670 # Add the options needed to define __ARM_FP with double-precision
4671 # support. We need either -mfloat-abi=softfp or -mfloat-abi=hard, but
4672 # if one is already specified by the multilib, use it.
4674 proc add_options_for_arm_fp_dp { flags } {
4675 if { ! [check_effective_target_arm_fp_dp_ok] } {
4678 global et_arm_fp_dp_flags
4679 return "$flags $et_arm_fp_dp_flags"
4682 # Return 1 if this is an ARM target that supports DSP multiply with
4683 # current multilib flags.
4685 proc check_effective_target_arm_dsp { } {
4686 return [check_no_compiler_messages arm_dsp assembly {
4687 #ifndef __ARM_FEATURE_DSP
4690 #include <arm_acle.h>
4695 # Return 1 if this is an ARM target that supports unaligned word/halfword
4696 # load/store instructions.
4698 proc check_effective_target_arm_unaligned { } {
4699 return [check_no_compiler_messages arm_unaligned assembly {
4700 #ifndef __ARM_FEATURE_UNALIGNED
4701 #error no unaligned support
4707 # Return 1 if this is an ARM target supporting -mfpu=crypto-neon-fp-armv8
4708 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
4709 # incompatible with these options. Also set et_arm_crypto_flags to the
4710 # best options to add.
4712 proc check_effective_target_arm_crypto_ok_nocache { } {
4713 global et_arm_crypto_flags
4714 set et_arm_crypto_flags ""
4715 if { [check_effective_target_arm_v8_neon_ok] } {
4716 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=crypto-neon-fp-armv8" "-mfpu=crypto-neon-fp-armv8 -mfloat-abi=softfp"} {
4717 if { [check_no_compiler_messages_nocache arm_crypto_ok object {
4718 #include "arm_neon.h"
4720 foo (uint8x16_t a, uint8x16_t b)
4722 return vaeseq_u8 (a, b);
4725 set et_arm_crypto_flags $flags
4734 # Return 1 if this is an ARM target supporting -mfpu=crypto-neon-fp-armv8
4736 proc check_effective_target_arm_crypto_ok { } {
4737 return [check_cached_effective_target arm_crypto_ok \
4738 check_effective_target_arm_crypto_ok_nocache]
4741 # Add options for crypto extensions.
4742 proc add_options_for_arm_crypto { flags } {
4743 if { ! [check_effective_target_arm_crypto_ok] } {
4746 global et_arm_crypto_flags
4747 return "$flags $et_arm_crypto_flags"
4750 # Add the options needed for NEON. We need either -mfloat-abi=softfp
4751 # or -mfloat-abi=hard, but if one is already specified by the
4752 # multilib, use it. Similarly, if a -mfpu option already enables
4753 # NEON, do not add -mfpu=neon.
4755 proc add_options_for_arm_neon { flags } {
4756 if { ! [check_effective_target_arm_neon_ok] } {
4759 global et_arm_neon_flags
4760 return "$flags $et_arm_neon_flags"
4763 proc add_options_for_arm_v8_vfp { flags } {
4764 if { ! [check_effective_target_arm_v8_vfp_ok] } {
4767 return "$flags -mfpu=fp-armv8 -mfloat-abi=softfp"
4770 proc add_options_for_arm_v8_neon { flags } {
4771 if { ! [check_effective_target_arm_v8_neon_ok] } {
4774 global et_arm_v8_neon_flags
4775 return "$flags $et_arm_v8_neon_flags -march=armv8-a"
4778 # Add the options needed for ARMv8.1 Adv.SIMD. Also adds the ARMv8 NEON
4779 # options for AArch64 and for ARM.
4781 proc add_options_for_arm_v8_1a_neon { flags } {
4782 if { ! [check_effective_target_arm_v8_1a_neon_ok] } {
4785 global et_arm_v8_1a_neon_flags
4786 return "$flags $et_arm_v8_1a_neon_flags"
4789 # Add the options needed for ARMv8.2 with the scalar FP16 extension.
4790 # Also adds the ARMv8 FP options for ARM and for AArch64.
4792 proc add_options_for_arm_v8_2a_fp16_scalar { flags } {
4793 if { ! [check_effective_target_arm_v8_2a_fp16_scalar_ok] } {
4796 global et_arm_v8_2a_fp16_scalar_flags
4797 return "$flags $et_arm_v8_2a_fp16_scalar_flags"
4800 # Add the options needed for ARMv8.2 with the FP16 extension. Also adds
4801 # the ARMv8 NEON options for ARM and for AArch64.
4803 proc add_options_for_arm_v8_2a_fp16_neon { flags } {
4804 if { ! [check_effective_target_arm_v8_2a_fp16_neon_ok] } {
4807 global et_arm_v8_2a_fp16_neon_flags
4808 return "$flags $et_arm_v8_2a_fp16_neon_flags"
4811 proc add_options_for_arm_crc { flags } {
4812 if { ! [check_effective_target_arm_crc_ok] } {
4815 global et_arm_crc_flags
4816 return "$flags $et_arm_crc_flags"
4819 # Add the options needed for NEON. We need either -mfloat-abi=softfp
4820 # or -mfloat-abi=hard, but if one is already specified by the
4821 # multilib, use it. Similarly, if a -mfpu option already enables
4822 # NEON, do not add -mfpu=neon.
4824 proc add_options_for_arm_neonv2 { flags } {
4825 if { ! [check_effective_target_arm_neonv2_ok] } {
4828 global et_arm_neonv2_flags
4829 return "$flags $et_arm_neonv2_flags"
4832 # Add the options needed for vfp3.
4833 proc add_options_for_arm_vfp3 { flags } {
4834 if { ! [check_effective_target_arm_vfp3_ok] } {
4837 return "$flags -mfpu=vfp3 -mfloat-abi=softfp"
4840 # Return 1 if this is an ARM target supporting -mfpu=neon
4841 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
4842 # incompatible with these options. Also set et_arm_neon_flags to the
4843 # best options to add.
4845 proc check_effective_target_arm_neon_ok_nocache { } {
4846 global et_arm_neon_flags
4847 set et_arm_neon_flags ""
4848 if { [check_effective_target_arm32] } {
4849 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon" "-mfpu=neon -mfloat-abi=softfp" "-mfpu=neon -mfloat-abi=softfp -march=armv7-a" "-mfloat-abi=hard" "-mfpu=neon -mfloat-abi=hard" "-mfpu=neon -mfloat-abi=hard -march=armv7-a"} {
4850 if { [check_no_compiler_messages_nocache arm_neon_ok object {
4851 #include <arm_neon.h>
4853 #ifndef __ARM_NEON__
4856 /* Avoid the case where a test adds -mfpu=neon, but the toolchain is
4857 configured for -mcpu=arm926ej-s, for example. */
4858 #if __ARM_ARCH < 7 || __ARM_ARCH_PROFILE == 'M
'
4859 #error Architecture does not support NEON.
4862 set et_arm_neon_flags $flags
4871 proc check_effective_target_arm_neon_ok { } {
4872 return [check_cached_effective_target arm_neon_ok \
4873 check_effective_target_arm_neon_ok_nocache]
4877 # Return 1 if this is an ARM target supporting the SIMD32 intrinsics
4878 # from arm_acle.h. Some multilibs may be incompatible with these options.
4879 # Also set et_arm_simd32_flags to the best options to add.
4880 # arm_acle.h includes stdint.h which can cause trouble with incompatible
4881 # -mfloat-abi= options.
4883 proc check_effective_target_arm_simd32_ok_nocache { } {
4884 global et_arm_simd32_flags
4885 set et_arm_simd32_flags ""
4886 foreach flags {"" "-march=armv6" "-march=armv6 -mfloat-abi=softfp" "-march=armv6 -mfloat-abi=hard"} {
4887 if { [check_no_compiler_messages_nocache arm_simd32_ok object {
4888 #include <arm_acle.h>
4890 #ifndef __ARM_FEATURE_SIMD32
4894 set et_arm_simd32_flags $flags
4902 proc check_effective_target_arm_simd32_ok { } {
4903 return [check_cached_effective_target arm_simd32_ok \
4904 check_effective_target_arm_simd32_ok_nocache]
4907 proc add_options_for_arm_simd32 { flags } {
4908 if { ! [check_effective_target_arm_simd32_ok] } {
4911 global et_arm_simd32_flags
4912 return "$flags $et_arm_simd32_flags"
4915 # Return 1 if this is an ARM target supporting the __ssat and __usat
4916 # saturation intrinsics from arm_acle.h. Some multilibs may be
4917 # incompatible with these options. Also set et_arm_sat_flags to the
4918 # best options to add. arm_acle.h includes stdint.h which can cause
4919 # trouble with incompatible -mfloat-abi= options.
4921 proc check_effective_target_arm_sat_ok_nocache { } {
4922 global et_arm_sat_flags
4923 set et_arm_sat_flags ""
4924 foreach flags {"" "-march=armv6" "-march=armv6 -mfloat-abi=softfp" "-march=armv6 -mfloat-abi=hard -mfpu=vfp"} {
4925 if { [check_no_compiler_messages_nocache et_arm_sat_flags object {
4926 #include <arm_acle.h>
4928 #ifndef __ARM_FEATURE_SAT
4932 set et_arm_sat_flags $flags
4940 proc check_effective_target_arm_sat_ok { } {
4941 return [check_cached_effective_target et_arm_sat_flags \
4942 check_effective_target_arm_sat_ok_nocache]
4945 proc add_options_for_arm_sat { flags } {
4946 if { ! [check_effective_target_arm_sat_ok] } {
4949 global et_arm_sat_flags
4950 return "$flags $et_arm_sat_flags"
4953 # Return 1 if this is an ARM target supporting the DSP intrinsics from
4954 # arm_acle.h. Some multilibs may be incompatible with these options.
4955 # Also set et_arm_dsp_flags to the best options to add.
4956 # arm_acle.h includes stdint.h which can cause trouble with incompatible
4957 # -mfloat-abi= options.
4958 # check_effective_target_arm_dsp also exists, which checks the current
4959 # multilib, without trying other options.
4961 proc check_effective_target_arm_dsp_ok_nocache { } {
4962 global et_arm_dsp_flags
4963 set et_arm_dsp_flags ""
4964 foreach flags {"" "-march=armv5te" "-march=armv5te -mfloat-abi=softfp" "-march=armv5te -mfloat-abi=hard"} {
4965 if { [check_no_compiler_messages_nocache et_arm_dsp_ok object {
4966 #include <arm_acle.h>
4968 #ifndef __ARM_FEATURE_DSP
4972 set et_arm_dsp_flags $flags
4980 proc check_effective_target_arm_dsp_ok { } {
4981 return [check_cached_effective_target et_arm_dsp_flags \
4982 check_effective_target_arm_dsp_ok_nocache]
4985 proc add_options_for_arm_dsp { flags } {
4986 if { ! [check_effective_target_arm_dsp_ok] } {
4989 global et_arm_dsp_flags
4990 return "$flags $et_arm_dsp_flags"
4993 # Return 1 if this is an ARM target supporting -mfpu=neon without any
4994 # -mfloat-abi= option. Useful in tests where add_options is not
4995 # supported (such as lto tests).
4997 proc check_effective_target_arm_neon_ok_no_float_abi_nocache { } {
4998 if { [check_effective_target_arm32] } {
4999 foreach flags {"-mfpu=neon"} {
5000 if { [check_no_compiler_messages_nocache arm_neon_ok_no_float_abi object {
5001 #include <arm_neon.h>
5003 #ifndef __ARM_NEON__
5006 /* Avoid the case where a test adds -mfpu=neon, but the toolchain is
5007 configured for -mcpu=arm926ej-s, for example. */
5008 #if __ARM_ARCH < 7 || __ARM_ARCH_PROFILE == 'M
'
5009 #error Architecture does not support NEON.
5020 proc check_effective_target_arm_neon_ok_no_float_abi { } {
5021 return [check_cached_effective_target arm_neon_ok_no_float_abi \
5022 check_effective_target_arm_neon_ok_no_float_abi_nocache]
5025 proc check_effective_target_arm_crc_ok_nocache { } {
5026 global et_arm_crc_flags
5027 set et_arm_crc_flags "-march=armv8-a+crc"
5028 return [check_no_compiler_messages_nocache arm_crc_ok object {
5029 #if !defined (__ARM_FEATURE_CRC32)
5032 #include <arm_acle.h>
5033 } "$et_arm_crc_flags"]
5036 proc check_effective_target_arm_crc_ok { } {
5037 return [check_cached_effective_target arm_crc_ok \
5038 check_effective_target_arm_crc_ok_nocache]
5041 # Return 1 if this is an ARM target supporting -mfpu=neon-fp16
5042 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
5043 # incompatible with these options. Also set et_arm_neon_fp16_flags to
5044 # the best options to add.
5046 proc check_effective_target_arm_neon_fp16_ok_nocache { } {
5047 global et_arm_neon_fp16_flags
5048 global et_arm_neon_flags
5049 set et_arm_neon_fp16_flags ""
5050 if { [check_effective_target_arm32]
5051 && [check_effective_target_arm_neon_ok] } {
5052 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp16"
5053 "-mfpu=neon-fp16 -mfloat-abi=softfp"
5054 "-mfp16-format=ieee"
5055 "-mfloat-abi=softfp -mfp16-format=ieee"
5056 "-mfpu=neon-fp16 -mfp16-format=ieee"
5057 "-mfpu=neon-fp16 -mfloat-abi=softfp -mfp16-format=ieee"} {
5058 if { [check_no_compiler_messages_nocache arm_neon_fp16_ok object {
5059 #include "arm_neon.h"
5061 foo (float32x4_t arg)
5063 return vcvt_f16_f32 (arg);
5065 } "$et_arm_neon_flags $flags"] } {
5066 set et_arm_neon_fp16_flags [concat $et_arm_neon_flags $flags]
5075 proc check_effective_target_arm_neon_fp16_ok { } {
5076 return [check_cached_effective_target arm_neon_fp16_ok \
5077 check_effective_target_arm_neon_fp16_ok_nocache]
5080 # Return 1 if this is an ARM target supporting -mfpu=neon-fp16
5081 # and -mfloat-abi=softfp together. Some multilibs may be
5082 # incompatible with these options. Also set et_arm_neon_softfp_fp16_flags to
5083 # the best options to add.
5085 proc check_effective_target_arm_neon_softfp_fp16_ok_nocache { } {
5086 global et_arm_neon_softfp_fp16_flags
5087 global et_arm_neon_flags
5088 set et_arm_neon_softfp_fp16_flags ""
5089 if { [check_effective_target_arm32]
5090 && [check_effective_target_arm_neon_ok] } {
5091 foreach flags {"-mfpu=neon-fp16 -mfloat-abi=softfp"
5092 "-mfpu=neon-fp16 -mfloat-abi=softfp -mfp16-format=ieee"} {
5093 if { [check_no_compiler_messages_nocache arm_neon_softfp_fp16_ok object {
5094 #include "arm_neon.h"
5096 foo (float32x4_t arg)
5098 return vcvt_f16_f32 (arg);
5100 } "$et_arm_neon_flags $flags"] } {
5101 set et_arm_neon_softfp_fp16_flags [concat $et_arm_neon_flags $flags]
5110 proc check_effective_target_arm_neon_softfp_fp16_ok { } {
5111 return [check_cached_effective_target arm_neon_softfp_fp16_ok \
5112 check_effective_target_arm_neon_softfp_fp16_ok_nocache]
5117 proc check_effective_target_arm_neon_fp16_hw { } {
5118 if {! [check_effective_target_arm_neon_fp16_ok] } {
5121 global et_arm_neon_fp16_flags
5122 check_runtime arm_neon_fp16_hw {
5124 main (int argc, char **argv)
5126 asm ("vcvt.f32.f16 q1, d0");
5129 } $et_arm_neon_fp16_flags
5132 proc add_options_for_arm_neon_fp16 { flags } {
5133 if { ! [check_effective_target_arm_neon_fp16_ok] } {
5136 global et_arm_neon_fp16_flags
5137 return "$flags $et_arm_neon_fp16_flags"
5140 proc add_options_for_arm_neon_softfp_fp16 { flags } {
5141 if { ! [check_effective_target_arm_neon_softfp_fp16_ok] } {
5144 global et_arm_neon_softfp_fp16_flags
5145 return "$flags $et_arm_neon_softfp_fp16_flags"
5148 proc add_options_for_aarch64_sve { flags } {
5149 if { ![istarget aarch64*-*-*] || [check_effective_target_aarch64_sve] } {
5152 return "$flags -march=armv8.2-a+sve"
5155 # Return 1 if this is an ARM target supporting the FP16 alternative
5156 # format. Some multilibs may be incompatible with the options needed. Also
5157 # set et_arm_neon_fp16_flags to the best options to add.
5159 proc check_effective_target_arm_fp16_alternative_ok_nocache { } {
5160 if { [istarget *-*-vxworks7*] } {
5161 # Not supported by the target system.
5164 global et_arm_neon_fp16_flags
5165 set et_arm_neon_fp16_flags ""
5166 if { [check_effective_target_arm32] } {
5167 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp16"
5168 "-mfpu=neon-fp16 -mfloat-abi=softfp"} {
5169 if { [check_no_compiler_messages_nocache \
5170 arm_fp16_alternative_ok object {
5171 #if !defined (__ARM_FP16_FORMAT_ALTERNATIVE)
5172 #error __ARM_FP16_FORMAT_ALTERNATIVE not defined
5174 } "$flags -mfp16-format=alternative"] } {
5175 set et_arm_neon_fp16_flags "$flags -mfp16-format=alternative"
5184 proc check_effective_target_arm_fp16_alternative_ok { } {
5185 return [check_cached_effective_target arm_fp16_alternative_ok \
5186 check_effective_target_arm_fp16_alternative_ok_nocache]
5189 # Return 1 if this is an ARM target supports specifying the FP16 none
5190 # format. Some multilibs may be incompatible with the options needed.
5192 proc check_effective_target_arm_fp16_none_ok_nocache { } {
5193 if { [check_effective_target_arm32] } {
5194 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp16"
5195 "-mfpu=neon-fp16 -mfloat-abi=softfp"} {
5196 if { [check_no_compiler_messages_nocache \
5197 arm_fp16_none_ok object {
5198 #if defined (__ARM_FP16_FORMAT_ALTERNATIVE)
5199 #error __ARM_FP16_FORMAT_ALTERNATIVE defined
5201 #if defined (__ARM_FP16_FORMAT_IEEE)
5202 #error __ARM_FP16_FORMAT_IEEE defined
5204 } "$flags -mfp16-format=none"] } {
5213 proc check_effective_target_arm_fp16_none_ok { } {
5214 return [check_cached_effective_target arm_fp16_none_ok \
5215 check_effective_target_arm_fp16_none_ok_nocache]
5218 # Return 1 if this is an ARM target supporting -mfpu=neon-fp-armv8
5219 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
5220 # incompatible with these options. Also set et_arm_v8_neon_flags to the
5221 # best options to add.
5223 proc check_effective_target_arm_v8_neon_ok_nocache { } {
5224 global et_arm_v8_neon_flags
5225 set et_arm_v8_neon_flags ""
5226 if { [check_effective_target_arm32] } {
5227 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp-armv8" "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} {
5228 if { [check_no_compiler_messages_nocache arm_v8_neon_ok object {
5230 #error not armv8 or later
5232 #include "arm_neon.h"
5236 __asm__ volatile ("vrintn.f32 q0, q0");
5238 } "$flags -march=armv8-a"] } {
5239 set et_arm_v8_neon_flags $flags
5248 proc check_effective_target_arm_v8_neon_ok { } {
5249 return [check_cached_effective_target arm_v8_neon_ok \
5250 check_effective_target_arm_v8_neon_ok_nocache]
5253 # Return 1 if this is an ARM target supporting -mfpu=neon-vfpv4
5254 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
5255 # incompatible with these options. Also set et_arm_neonv2_flags to the
5256 # best options to add.
5258 proc check_effective_target_arm_neonv2_ok_nocache { } {
5259 global et_arm_neonv2_flags
5260 global et_arm_neon_flags
5261 set et_arm_neonv2_flags ""
5262 if { [check_effective_target_arm32]
5263 && [check_effective_target_arm_neon_ok] } {
5264 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-vfpv4" "-mfpu=neon-vfpv4 -mfloat-abi=softfp"} {
5265 if { [check_no_compiler_messages_nocache arm_neonv2_ok object {
5266 #include "arm_neon.h"
5268 foo (float32x2_t a, float32x2_t b, float32x2_t c)
5270 return vfma_f32 (a, b, c);
5272 } "$et_arm_neon_flags $flags"] } {
5273 set et_arm_neonv2_flags [concat $et_arm_neon_flags $flags]
5282 proc check_effective_target_arm_neonv2_ok { } {
5283 return [check_cached_effective_target arm_neonv2_ok \
5284 check_effective_target_arm_neonv2_ok_nocache]
5287 # Add the options needed for VFP FP16 support. We need either
5288 # -mfloat-abi=softfp or -mfloat-abi=hard. If one is already specified by
5289 # the multilib, use it.
5291 proc add_options_for_arm_fp16 { flags } {
5292 if { ! [check_effective_target_arm_fp16_ok] } {
5295 global et_arm_fp16_flags
5296 return "$flags $et_arm_fp16_flags"
5299 # Add the options needed to enable support for IEEE format
5300 # half-precision support. This is valid for ARM targets.
5302 proc add_options_for_arm_fp16_ieee { flags } {
5303 if { ! [check_effective_target_arm_fp16_ok] } {
5306 global et_arm_fp16_flags
5307 return "$flags $et_arm_fp16_flags -mfp16-format=ieee"
5310 # Add the options needed to enable support for ARM Alternative format
5311 # half-precision support. This is valid for ARM targets.
5313 proc add_options_for_arm_fp16_alternative { flags } {
5314 if { ! [check_effective_target_arm_fp16_ok] } {
5317 global et_arm_fp16_flags
5318 return "$flags $et_arm_fp16_flags -mfp16-format=alternative"
5321 # Return 1 if this is an ARM target that can support a VFP fp16 variant.
5322 # Skip multilibs that are incompatible with these options and set
5323 # et_arm_fp16_flags to the best options to add. This test is valid for
5326 proc check_effective_target_arm_fp16_ok_nocache { } {
5327 global et_arm_fp16_flags
5328 set et_arm_fp16_flags ""
5329 if { ! [check_effective_target_arm32] } {
5333 [list "" { *-*-* } { "-mfpu=*" } \
5334 { "-mfpu=*fp16*" "-mfpu=*fpv[4-9]*" \
5335 "-mfpu=*fpv[1-9][0-9]*" "-mfpu=*fp-armv8*" } ]] {
5336 # Multilib flags would override -mfpu.
5339 if [check-flags [list "" { *-*-* } { "-mfloat-abi=soft" } { "" } ]] {
5340 # Must generate floating-point instructions.
5343 if [check_effective_target_arm_hf_eabi] {
5344 # Use existing float-abi and force an fpu which supports fp16
5345 set et_arm_fp16_flags "-mfpu=vfpv4"
5348 if [check-flags [list "" { *-*-* } { "-mfpu=*" } { "" } ]] {
5349 # The existing -mfpu value is OK; use it, but add softfp.
5350 set et_arm_fp16_flags "-mfloat-abi=softfp"
5353 # Add -mfpu for a VFP fp16 variant since there is no preprocessor
5354 # macro to check for this support.
5355 set flags "-mfpu=vfpv4 -mfloat-abi=softfp"
5356 if { [check_no_compiler_messages_nocache arm_fp16_ok assembly {
5359 set et_arm_fp16_flags "$flags"
5366 proc check_effective_target_arm_fp16_ok { } {
5367 return [check_cached_effective_target arm_fp16_ok \
5368 check_effective_target_arm_fp16_ok_nocache]
5371 # Return 1 if the target supports executing VFP FP16 instructions, 0
5372 # otherwise. This test is valid for ARM only.
5374 proc check_effective_target_arm_fp16_hw { } {
5375 if {! [check_effective_target_arm_fp16_ok] } {
5378 global et_arm_fp16_flags
5379 check_runtime arm_fp16_hw {
5381 main (int argc, char **argv)
5385 asm ("vcvtb.f32.f16 %0, %1"
5386 : "=w" (r) : "w" (a)
5387 : /* No clobbers. */);
5388 return (r == 1.0) ? 0 : 1;
5390 } "$et_arm_fp16_flags -mfp16-format=ieee"
5393 # Creates a series of routines that return 1 if the given architecture
5394 # can be selected and a routine to give the flags to select that architecture
5395 # Note: Extra flags may be added to disable options from newer compilers
5396 # (Thumb in particular - but others may be added in the future).
5397 # Warning: Do not use check_effective_target_arm_arch_*_ok for architecture
5398 # extension (eg. ARMv8.1-A) since there is no macro defined for them. See
5399 # how only __ARM_ARCH_8A__ is checked for ARMv8.1-A.
5400 # Usage: /* { dg-require-effective-target arm_arch_v5_ok } */
5401 # /* { dg-add-options arm_arch_v5t } */
5402 # /* { dg-require-effective-target arm_arch_v5t_multilib } */
5403 foreach { armfunc armflag armdefs } {
5404 v4 "-march=armv4 -marm" __ARM_ARCH_4__
5405 v4t "-march=armv4t -mfloat-abi=softfp" __ARM_ARCH_4T__
5406 v4t_arm "-march=armv4t -marm" "__ARM_ARCH_4T__ && !__thumb__"
5407 v4t_thumb "-march=armv4t -mthumb -mfloat-abi=softfp" "__ARM_ARCH_4T__ && __thumb__"
5408 v5t "-march=armv5t -mfloat-abi=softfp" __ARM_ARCH_5T__
5409 v5t_arm "-march=armv5t -marm" "__ARM_ARCH_5T__ && !__thumb__"
5410 v5t_thumb "-march=armv5t -mthumb -mfloat-abi=softfp" "__ARM_ARCH_5T__ && __thumb__"
5411 v5te "-march=armv5te+fp -mfloat-abi=softfp" __ARM_ARCH_5TE__
5412 v5te_arm "-march=armv5te+fp -marm" "__ARM_ARCH_5TE__ && !__thumb__"
5413 v5te_thumb "-march=armv5te+fp -mthumb -mfloat-abi=softfp" "__ARM_ARCH_5TE__ && __thumb__"
5414 xscale_arm "-mcpu=xscale -mfloat-abi=soft -marm" "__XSCALE__ && !__thumb__"
5415 v6 "-march=armv6+fp -mfloat-abi=softfp" __ARM_ARCH_6__
5416 v6_arm "-march=armv6+fp -marm" "__ARM_ARCH_6__ && !__thumb__"
5417 v6_thumb "-march=armv6+fp -mthumb -mfloat-abi=softfp" "__ARM_ARCH_6__ && __thumb__"
5418 v6k "-march=armv6k+fp -mfloat-abi=softfp" __ARM_ARCH_6K__
5419 v6k_arm "-march=armv6k+fp -marm" "__ARM_ARCH_6K__ && !__thumb__"
5420 v6k_thumb "-march=armv6k+fp -mthumb -mfloat-abi=softfp" "__ARM_ARCH_6K__ && __thumb__"
5421 v6t2 "-march=armv6t2+fp" __ARM_ARCH_6T2__
5422 v6z "-march=armv6z+fp -mfloat-abi=softfp" __ARM_ARCH_6Z__
5423 v6z_arm "-march=armv6z+fp -marm" "__ARM_ARCH_6Z__ && !__thumb__"
5424 v6z_thumb "-march=armv6z+fp -mthumb -mfloat-abi=softfp" "__ARM_ARCH_6Z__ && __thumb__"
5425 v6m "-march=armv6-m -mthumb -mfloat-abi=soft" __ARM_ARCH_6M__
5426 v7a "-march=armv7-a+fp" __ARM_ARCH_7A__
5427 v7a_arm "-march=armv7-a+fp -marm" "__ARM_ARCH_7A__ && !__thumb__"
5428 v7a_neon "-march=armv7-a+simd -mfpu=auto -mfloat-abi=softfp" "__ARM_ARCH_7A__ && __ARM_NEON__"
5429 v7r "-march=armv7-r+fp" __ARM_ARCH_7R__
5430 v7m "-march=armv7-m -mthumb -mfloat-abi=soft" __ARM_ARCH_7M__
5431 v7em "-march=armv7e-m+fp -mthumb" __ARM_ARCH_7EM__
5432 v7ve "-march=armv7ve+fp -marm"
5433 "__ARM_ARCH_7A__ && __ARM_FEATURE_IDIV"
5434 v8a "-march=armv8-a+simd" __ARM_ARCH_8A__
5435 v8a_hard "-march=armv8-a+simd -mfpu=auto -mfloat-abi=hard" __ARM_ARCH_8A__
5436 v8_1a "-march=armv8.1-a+simd" __ARM_ARCH_8A__
5437 v8_2a "-march=armv8.2-a+simd" __ARM_ARCH_8A__
5438 v8r "-march=armv8-r+fp.sp" __ARM_ARCH_8R__
5439 v8m_base "-march=armv8-m.base -mthumb -mfloat-abi=soft"
5440 __ARM_ARCH_8M_BASE__
5441 v8m_main "-march=armv8-m.main+fp -mthumb" __ARM_ARCH_8M_MAIN__
5442 v8_1m_main "-march=armv8.1-m.main+fp -mthumb" __ARM_ARCH_8M_MAIN__
5443 v9a "-march=armv9-a+simd" __ARM_ARCH_9A__ } {
5444 eval [string map [list FUNC $armfunc FLAG $armflag DEFS $armdefs ] {
5445 proc check_effective_target_arm_arch_FUNC_ok { } {
5446 return [check_no_compiler_messages arm_arch_FUNC_ok assembly {
5458 proc add_options_for_arm_arch_FUNC { flags } {
5459 return "$flags FLAG"
5462 proc check_effective_target_arm_arch_FUNC_link { } {
5463 return [check_no_compiler_messages arm_arch_FUNC_link executable {
5466 int main (void) { return 0; }
5467 } [add_options_for_arm_arch_FUNC ""]]
5470 proc check_effective_target_arm_arch_FUNC_multilib { } {
5471 return [check_runtime arm_arch_FUNC_multilib {
5477 } [add_options_for_arm_arch_FUNC ""]]
5482 # Return 1 if GCC was configured with --with-mode=
5483 proc check_effective_target_default_mode { } {
5485 return [check_configured_with "with-mode="]
5488 # Return 1 if this is an ARM target where -marm causes ARM to be
5491 proc check_effective_target_arm_arm_ok { } {
5492 return [check_no_compiler_messages arm_arm_ok assembly {
5493 #if !defined (__arm__) || defined (__thumb__) || defined (__thumb2__)
5494 #error !__arm__ || __thumb__ || __thumb2__
5500 # Return 1 is this is an ARM target where -mthumb causes Thumb-1 to be
5503 proc check_effective_target_arm_thumb1_ok { } {
5504 return [check_no_compiler_messages arm_thumb1_ok assembly {
5505 #if !defined(__arm__) || !defined(__thumb__) || defined(__thumb2__)
5506 #error !__arm__ || !__thumb__ || __thumb2__
5508 int foo (int i) { return i; }
5512 # Return 1 is this is an ARM target where -mthumb causes Thumb-2 to be
5515 proc check_effective_target_arm_thumb2_ok { } {
5516 return [check_no_compiler_messages arm_thumb2_ok assembly {
5517 #if !defined(__thumb2__)
5520 int foo (int i) { return i; }
5524 # Return 1 if this is an ARM target where Thumb-1 is used without options
5525 # added by the test.
5527 proc check_effective_target_arm_thumb1 { } {
5528 return [check_no_compiler_messages arm_thumb1 assembly {
5529 #if !defined(__arm__) || !defined(__thumb__) || defined(__thumb2__)
5530 #error !__arm__ || !__thumb__ || __thumb2__
5536 # Return 1 if this is an ARM target where Thumb-2 is used without options
5537 # added by the test.
5539 proc check_effective_target_arm_thumb2 { } {
5540 return [check_no_compiler_messages arm_thumb2 assembly {
5541 #if !defined(__thumb2__)
5548 # Return 1 if this is an ARM target where conditional execution is available.
5550 proc check_effective_target_arm_cond_exec { } {
5551 return [check_no_compiler_messages arm_cond_exec assembly {
5552 #if defined(__arm__) && defined(__thumb__) && !defined(__thumb2__)
5559 # Return 1 if this is an ARM cortex-M profile cpu
5561 proc check_effective_target_arm_cortex_m { } {
5562 if { ![istarget arm*-*-*] } {
5565 return [check_no_compiler_messages arm_cortex_m assembly {
5566 #if defined(__ARM_ARCH_ISA_ARM)
5567 #error __ARM_ARCH_ISA_ARM is defined
5573 # Return 1 if this is an ARM target where -mthumb causes Thumb-1 to be
5574 # used and MOVT/MOVW instructions to be available.
5576 proc check_effective_target_arm_thumb1_movt_ok {} {
5577 if [check_effective_target_arm_thumb1_ok] {
5578 return [check_no_compiler_messages arm_movt object {
5582 asm ("movt r0, #42");
5590 # Return 1 if this is an ARM target where -mthumb causes Thumb-1 to be
5591 # used and CBZ and CBNZ instructions are available.
5593 proc check_effective_target_arm_thumb1_cbz_ok {} {
5594 if [check_effective_target_arm_thumb1_ok] {
5595 return [check_no_compiler_messages arm_movt object {
5599 asm ("cbz r0, 2f\n2:");
5607 # Return 1 if this is an Arm target which supports the Armv6t2 extensions.
5608 # This can be either in Arm state or in Thumb state.
5610 proc check_effective_target_arm_arch_v6t2_hw {} {
5611 if [check_effective_target_arm_arch_v6t2_ok] {
5612 return [check_runtime arm_arch_v6t2 {
5616 asm ("bfc r0, #1, #2");
5619 } [add_options_for_arm_arch_v6t2 ""]]
5625 # Return 1 if this is an ARM target where ARMv8-M Security Extensions is
5628 proc check_effective_target_arm_cmse_ok {} {
5629 return [check_no_compiler_messages arm_cmse object {
5638 # Return 1 if the target supports executing CMSE instructions, 0
5639 # otherwise. Cache the result.
5641 proc check_effective_target_arm_cmse_hw { } {
5642 return [check_runtime arm_cmse_hw_available {
5646 asm ("ldr\t%0, =0xe000ed44\n" \
5648 "sg" : "=l" (id_pfr1));
5649 /* Exit with code 0 iff security extension is available. */
5650 return !(id_pfr1 & 0xf0);
5655 # Return 1 if the target supports executing MVE instructions, 0
5658 proc check_effective_target_arm_mve_hw {} {
5659 return [check_runtime arm_mve_hw_available {
5665 asm ("sqrshrl %Q1, %R1, #64, %2"
5667 : "0" (a), "r" (b));
5670 } [add_options_for_arm_v8_1m_mve_fp ""]]
5673 # Return 1 if this is an ARM target where ARMv8-M Security Extensions with
5674 # clearing instructions (clrm, vscclrm, vstr/vldr with FPCXT) is available.
5676 proc check_effective_target_arm_cmse_clear_ok {} {
5677 return [check_no_compiler_messages arm_cmse_clear object {
5681 asm ("clrm {r1, r2}");
5686 # Return 1 if this is an ARM target supporting
5687 # -mbranch-protection=standard, 0 otherwise.
5689 proc check_effective_target_mbranch_protection_ok {} {
5691 return [check_no_compiler_messages mbranch_protection_ok object {
5692 int main (void) { return 0; }
5693 } "-mbranch-protection=standard"]
5696 # Return 1 if the target supports executing PACBTI instructions, 0
5699 proc check_effective_target_arm_pacbti_hw {} {
5700 return [check_runtime arm_pacbti_hw_available {
5701 __attribute__ ((naked)) int
5704 asm ("pac r12, lr, sp");
5706 asm ("autg r12, lr, sp");
5709 } "-march=armv8.1-m.main+pacbti+fp -mbranch-protection=standard -mthumb -mfloat-abi=hard"]
5712 # Return 1 if this compilation turns on string_ops_prefer_neon on.
5714 proc check_effective_target_arm_tune_string_ops_prefer_neon { } {
5715 return [check_no_messages_and_pattern arm_tune_string_ops_prefer_neon "@string_ops_prefer_neon:\t1" assembly {
5716 int foo (void) { return 0; }
5717 } "-O2 -mprint-tune-info" ]
5720 # Return 1 if the target supports executing NEON instructions, 0
5721 # otherwise. Cache the result.
5723 proc check_effective_target_arm_neon_hw { } {
5724 return [check_runtime arm_neon_hw_available {
5728 long long a = 0, b = 1;
5729 asm ("vorr %P0, %P1, %P2"
5731 : "0" (a), "w" (b));
5734 } [add_options_for_arm_neon ""]]
5737 # Return true if this is an AArch64 target that can run SVE code.
5739 proc check_effective_target_aarch64_sve_hw { } {
5740 if { ![istarget aarch64*-*-*] } {
5743 return [check_runtime aarch64_sve_hw_available {
5747 asm volatile ("ptrue p0.b");
5750 } [add_options_for_aarch64_sve ""]]
5753 # Return true if this is an AArch64 target that can run SVE2 code.
5755 proc check_effective_target_aarch64_sve2_hw { } {
5756 if { ![istarget aarch64*-*-*] } {
5759 return [check_runtime aarch64_sve2_hw_available {
5763 asm volatile ("addp z0.b, p0/m, z0.b, z1.b");
5769 # Return true if this is an AArch64 target that can run SVE code and
5770 # if its SVE vectors have exactly BITS bits.
5772 proc aarch64_sve_hw_bits { bits } {
5773 if { ![check_effective_target_aarch64_sve_hw] } {
5776 return [check_runtime aarch64_sve${bits}_hw [subst {
5781 asm volatile ("cntd %0" : "=r" (res));
5782 if (res * 64 != $bits)
5786 }] [add_options_for_aarch64_sve ""]]
5789 # Return true if this is an AArch64 target that can run SVE code and
5790 # if its SVE vectors have exactly 256 bits.
5792 foreach N { 128 256 512 1024 2048 } {
5793 eval [string map [list N $N] {
5794 proc check_effective_target_aarch64_sveN_hw { } {
5795 return [aarch64_sve_hw_bits N]
5800 proc check_effective_target_arm_neonv2_hw { } {
5801 return [check_runtime arm_neon_hwv2_available {
5802 #include "arm_neon.h"
5806 float32x2_t a, b, c;
5807 asm ("vfma.f32 %P0, %P1, %P2"
5809 : "w" (b), "w" (c));
5812 } [add_options_for_arm_neonv2 ""]]
5815 # ID_AA64PFR1_EL1.BT using bits[3:0] == 1 implies BTI implimented.
5816 proc check_effective_target_aarch64_bti_hw { } {
5817 if { ![istarget aarch64*-*-*] } {
5820 return [check_runtime aarch64_bti_hw_available {
5825 asm volatile ("mrs %0, id_aa64pfr1_el1" : "=r" (a));
5826 return !((a & 0xf) == 1);
5831 # Return 1 if the target supports executing the armv8.3-a FJCVTZS
5833 proc check_effective_target_aarch64_fjcvtzs_hw { } {
5834 if { ![istarget aarch64*-*-*] } {
5837 return [check_runtime aarch64_fjcvtzs_hw_available {
5843 asm volatile ("fjcvtzs %w0, %d1"
5846 : /* No clobbers. */);
5849 } "-march=armv8.3-a" ]
5852 # Return 1 if GCC was configured with --enable-standard-branch-protection
5853 proc check_effective_target_default_branch_protection { } {
5854 return [check_configured_with "enable-standard-branch-protection"]
5857 # Return 1 if this is an ARM target supporting -mfloat-abi=softfp.
5859 proc check_effective_target_arm_softfp_ok { } {
5860 return [check_no_compiler_messages arm_softfp_ok object {
5863 int main (void) { return 0; }
5864 } "-mfloat-abi=softfp"]
5867 # Return 1 if this is an ARM target supporting -mfloat-abi=hard.
5869 proc check_effective_target_arm_hard_ok { } {
5870 return [check_no_compiler_messages arm_hard_ok object {
5873 int main (void) { return 0; }
5874 } "-mfloat-abi=hard"]
5877 # Return 1 if this is an ARM target supporting MVE.
5878 proc check_effective_target_arm_mve { } {
5879 if { ![istarget arm*-*-*] } {
5882 return [check_no_compiler_messages arm_mve assembly {
5883 #if !defined (__ARM_FEATURE_MVE)
5889 # Return 1 if the target supports ARMv8.1-M MVE with floating point
5890 # instructions, 0 otherwise. The test is valid for ARM.
5891 # Record the command line options needed.
5893 proc check_effective_target_arm_v8_1m_mve_fp_ok_nocache { } {
5894 global et_arm_v8_1m_mve_fp_flags
5895 set et_arm_v8_1m_mve_fp_flags ""
5897 if { ![istarget arm*-*-*] } {
5901 # Iterate through sets of options to find the compiler flags that
5902 # need to be added to the -march option.
5903 foreach flags {"" "-mfloat-abi=softfp -mfpu=auto -march=armv8.1-m.main+mve.fp" "-mfloat-abi=hard -mfpu=auto -march=armv8.1-m.main+mve.fp"} {
5904 if { [check_no_compiler_messages_nocache \
5905 arm_v8_1m_mve_fp_ok object {
5906 #include <arm_mve.h>
5907 #if !(__ARM_FEATURE_MVE & 2)
5908 #error "__ARM_FEATURE_MVE for floating point not defined"
5910 #if __ARM_BIG_ENDIAN
5911 #error "MVE intrinsics are not supported in Big-Endian mode."
5913 } "$flags -mthumb"] } {
5914 set et_arm_v8_1m_mve_fp_flags "$flags -mthumb --save-temps"
5922 proc check_effective_target_arm_v8_1m_mve_fp_ok { } {
5923 return [check_cached_effective_target arm_v8_1m_mve_fp_ok \
5924 check_effective_target_arm_v8_1m_mve_fp_ok_nocache]
5927 proc add_options_for_arm_v8_1m_mve_fp { flags } {
5928 if { ! [check_effective_target_arm_v8_1m_mve_fp_ok] } {
5931 global et_arm_v8_1m_mve_fp_flags
5932 return "$flags $et_arm_v8_1m_mve_fp_flags"
5935 # Return 1 if the target supports the ARMv8.1 Adv.SIMD extension, 0
5936 # otherwise. The test is valid for AArch64 and ARM. Record the command
5937 # line options needed.
5939 proc check_effective_target_arm_v8_1a_neon_ok_nocache { } {
5940 global et_arm_v8_1a_neon_flags
5941 set et_arm_v8_1a_neon_flags ""
5943 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
5947 # Iterate through sets of options to find the compiler flags that
5948 # need to be added to the -march option. Start with the empty set
5949 # since AArch64 only needs the -march setting.
5950 foreach flags {"" "-mfpu=neon-fp-armv8" "-mfloat-abi=softfp" \
5951 "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} {
5952 foreach arches { "-march=armv8-a+rdma" "-march=armv8.1-a" } {
5953 if { [check_no_compiler_messages_nocache arm_v8_1a_neon_ok object {
5954 #if !defined (__ARM_FEATURE_QRDMX)
5955 #error "__ARM_FEATURE_QRDMX not defined"
5957 } "$flags $arches"] } {
5958 set et_arm_v8_1a_neon_flags "$flags $arches"
5967 proc check_effective_target_arm_v8_1a_neon_ok { } {
5968 return [check_cached_effective_target arm_v8_1a_neon_ok \
5969 check_effective_target_arm_v8_1a_neon_ok_nocache]
5972 # Return 1 if the target supports ARMv8.2 scalar FP16 arithmetic
5973 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
5974 # Record the command line options needed.
5976 proc check_effective_target_arm_v8_2a_fp16_scalar_ok_nocache { } {
5977 global et_arm_v8_2a_fp16_scalar_flags
5978 set et_arm_v8_2a_fp16_scalar_flags ""
5980 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
5984 # Iterate through sets of options to find the compiler flags that
5985 # need to be added to the -march option.
5986 foreach flags {"" "-mfpu=fp-armv8" "-mfloat-abi=softfp" \
5987 "-mfpu=fp-armv8 -mfloat-abi=softfp"} {
5988 if { [check_no_compiler_messages_nocache \
5989 arm_v8_2a_fp16_scalar_ok object {
5990 #if !defined (__ARM_FEATURE_FP16_SCALAR_ARITHMETIC)
5991 #error "__ARM_FEATURE_FP16_SCALAR_ARITHMETIC not defined"
5993 } "$flags -march=armv8.2-a+fp16"] } {
5994 set et_arm_v8_2a_fp16_scalar_flags "$flags -march=armv8.2-a+fp16"
6002 proc check_effective_target_arm_v8_2a_fp16_scalar_ok { } {
6003 return [check_cached_effective_target arm_v8_2a_fp16_scalar_ok \
6004 check_effective_target_arm_v8_2a_fp16_scalar_ok_nocache]
6007 # Return 1 if the target supports ARMv8.2 Adv.SIMD FP16 arithmetic
6008 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
6009 # Record the command line options needed.
6011 proc check_effective_target_arm_v8_2a_fp16_neon_ok_nocache { } {
6012 global et_arm_v8_2a_fp16_neon_flags
6013 set et_arm_v8_2a_fp16_neon_flags ""
6015 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
6019 # Iterate through sets of options to find the compiler flags that
6020 # need to be added to the -march option.
6021 foreach flags {"" "-mfpu=neon-fp-armv8" "-mfloat-abi=softfp" \
6022 "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} {
6023 if { [check_no_compiler_messages_nocache \
6024 arm_v8_2a_fp16_neon_ok object {
6025 #if !defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
6026 #error "__ARM_FEATURE_FP16_VECTOR_ARITHMETIC not defined"
6028 } "$flags -march=armv8.2-a+fp16"] } {
6029 set et_arm_v8_2a_fp16_neon_flags "$flags -march=armv8.2-a+fp16"
6037 proc check_effective_target_arm_v8_2a_fp16_neon_ok { } {
6038 return [check_cached_effective_target arm_v8_2a_fp16_neon_ok \
6039 check_effective_target_arm_v8_2a_fp16_neon_ok_nocache]
6042 # Return 1 if the target supports ARMv8.2 Adv.SIMD Dot Product
6043 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
6044 # Record the command line options needed.
6046 proc check_effective_target_arm_v8_2a_dotprod_neon_ok_nocache { } {
6047 global et_arm_v8_2a_dotprod_neon_flags
6048 set et_arm_v8_2a_dotprod_neon_flags ""
6050 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
6054 # Iterate through sets of options to find the compiler flags that
6055 # need to be added to the -march option.
6056 foreach flags {"" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" "-mfloat-abi=hard -mfpu=neon-fp-armv8"} {
6057 if { [check_no_compiler_messages_nocache \
6058 arm_v8_2a_dotprod_neon_ok object {
6060 #if !defined (__ARM_FEATURE_DOTPROD)
6061 #error "__ARM_FEATURE_DOTPROD not defined"
6063 } "$flags -march=armv8.2-a+dotprod"] } {
6064 set et_arm_v8_2a_dotprod_neon_flags "$flags -march=armv8.2-a+dotprod"
6072 # Return 1 if the target supports ARMv8.1-M MVE
6073 # instructions, 0 otherwise. The test is valid for ARM.
6074 # Record the command line options needed.
6076 proc check_effective_target_arm_v8_1m_mve_ok_nocache { } {
6077 global et_arm_v8_1m_mve_flags
6078 set et_arm_v8_1m_mve_flags ""
6080 if { ![istarget arm*-*-*] } {
6084 # Iterate through sets of options to find the compiler flags that
6085 # need to be added to the -march option.
6086 foreach flags {"" "-mfloat-abi=softfp -mfpu=auto -march=armv8.1-m.main+mve" "-mfloat-abi=hard -mfpu=auto -march=armv8.1-m.main+mve"} {
6087 if { [check_no_compiler_messages_nocache \
6088 arm_v8_1m_mve_ok object {
6089 #if !defined (__ARM_FEATURE_MVE)
6090 #error "__ARM_FEATURE_MVE not defined"
6092 #if __ARM_BIG_ENDIAN
6093 #error "MVE intrinsics are not supported in Big-Endian mode."
6095 #include <arm_mve.h>
6096 } "$flags -mthumb"] } {
6097 set et_arm_v8_1m_mve_flags "$flags -mthumb --save-temps"
6105 proc check_effective_target_arm_v8_1m_mve_ok { } {
6106 return [check_cached_effective_target arm_v8_1m_mve_ok \
6107 check_effective_target_arm_v8_1m_mve_ok_nocache]
6110 proc add_options_for_arm_v8_1m_mve { flags } {
6111 if { ! [check_effective_target_arm_v8_1m_mve_ok] } {
6114 global et_arm_v8_1m_mve_flags
6115 return "$flags $et_arm_v8_1m_mve_flags"
6118 proc check_effective_target_arm_v8_2a_dotprod_neon_ok { } {
6119 return [check_cached_effective_target arm_v8_2a_dotprod_neon_ok \
6120 check_effective_target_arm_v8_2a_dotprod_neon_ok_nocache]
6123 proc add_options_for_arm_v8_2a_dotprod_neon { flags } {
6124 if { ! [check_effective_target_arm_v8_2a_dotprod_neon_ok] } {
6127 global et_arm_v8_2a_dotprod_neon_flags
6128 return "$flags $et_arm_v8_2a_dotprod_neon_flags"
6131 # Return 1 if the target supports ARMv8.2+i8mm Adv.SIMD Dot Product
6132 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
6133 # Record the command line options needed.
6135 proc check_effective_target_arm_v8_2a_i8mm_ok_nocache { } {
6136 global et_arm_v8_2a_i8mm_flags
6137 set et_arm_v8_2a_i8mm_flags ""
6139 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
6143 # Iterate through sets of options to find the compiler flags that
6144 # need to be added to the -march option.
6145 foreach flags {"" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" "-mfloat-abi=hard -mfpu=neon-fp-armv8" } {
6146 if { [check_no_compiler_messages_nocache \
6147 arm_v8_2a_i8mm_ok object {
6148 #include <arm_neon.h>
6149 #if !defined (__ARM_FEATURE_MATMUL_INT8)
6150 #error "__ARM_FEATURE_MATMUL_INT8 not defined"
6152 } "$flags -march=armv8.2-a+i8mm"] } {
6153 set et_arm_v8_2a_i8mm_flags "$flags -march=armv8.2-a+i8mm"
6161 proc check_effective_target_arm_v8_2a_i8mm_ok { } {
6162 return [check_cached_effective_target arm_v8_2a_i8mm_ok \
6163 check_effective_target_arm_v8_2a_i8mm_ok_nocache]
6166 proc add_options_for_arm_v8_2a_i8mm { flags } {
6167 if { ! [check_effective_target_arm_v8_2a_i8mm_ok] } {
6170 global et_arm_v8_2a_i8mm_flags
6171 return "$flags $et_arm_v8_2a_i8mm_flags"
6174 # Return 1 if the target supports FP16 VFMAL and VFMSL
6175 # instructions, 0 otherwise.
6176 # Record the command line options needed.
6178 proc check_effective_target_arm_fp16fml_neon_ok_nocache { } {
6179 global et_arm_fp16fml_neon_flags
6180 set et_arm_fp16fml_neon_flags ""
6182 if { ![istarget arm*-*-*] } {
6186 # Iterate through sets of options to find the compiler flags that
6187 # need to be added to the -march option.
6188 foreach flags {"" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" "-mfloat-abi=hard -mfpu=neon-fp-armv8"} {
6189 if { [check_no_compiler_messages_nocache \
6190 arm_fp16fml_neon_ok assembly {
6191 #include <arm_neon.h>
6193 foo (float32x2_t r, float16x4_t a, float16x4_t b)
6195 return vfmlal_high_f16 (r, a, b);
6197 } "$flags -march=armv8.2-a+fp16fml"] } {
6198 set et_arm_fp16fml_neon_flags "$flags -march=armv8.2-a+fp16fml"
6206 proc check_effective_target_arm_fp16fml_neon_ok { } {
6207 return [check_cached_effective_target arm_fp16fml_neon_ok \
6208 check_effective_target_arm_fp16fml_neon_ok_nocache]
6211 proc add_options_for_arm_fp16fml_neon { flags } {
6212 if { ! [check_effective_target_arm_fp16fml_neon_ok] } {
6215 global et_arm_fp16fml_neon_flags
6216 return "$flags $et_arm_fp16fml_neon_flags"
6219 # Return 1 if the target supports BFloat16 SIMD instructions, 0 otherwise.
6220 # The test is valid for ARM and for AArch64.
6222 proc check_effective_target_arm_v8_2a_bf16_neon_ok_nocache { } {
6223 global et_arm_v8_2a_bf16_neon_flags
6224 set et_arm_v8_2a_bf16_neon_flags ""
6226 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
6230 foreach flags {"" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" "-mfloat-abi=hard -mfpu=neon-fp-armv8" } {
6231 if { [check_no_compiler_messages_nocache arm_v8_2a_bf16_neon_ok object {
6232 #include <arm_neon.h>
6233 #if !defined (__ARM_FEATURE_BF16_VECTOR_ARITHMETIC)
6234 #error "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC not defined"
6236 } "$flags -march=armv8.2-a+bf16"] } {
6237 set et_arm_v8_2a_bf16_neon_flags "$flags -march=armv8.2-a+bf16"
6245 proc check_effective_target_arm_v8_2a_bf16_neon_ok { } {
6246 return [check_cached_effective_target arm_v8_2a_bf16_neon_ok \
6247 check_effective_target_arm_v8_2a_bf16_neon_ok_nocache]
6250 proc add_options_for_arm_v8_2a_bf16_neon { flags } {
6251 if { ! [check_effective_target_arm_v8_2a_bf16_neon_ok] } {
6254 global et_arm_v8_2a_bf16_neon_flags
6255 return "$flags $et_arm_v8_2a_bf16_neon_flags"
6258 # A series of routines are created to 1) check if a given architecture is
6259 # effective (check_effective_target_*_ok) and then 2) give the corresponding
6260 # flags that enable the architecture (add_options_for_*).
6261 # The series includes:
6262 # arm_v8m_main_cde: Armv8-m CDE (Custom Datapath Extension).
6263 # arm_v8m_main_cde_fp: Armv8-m CDE with FP registers.
6264 # arm_v8_1m_main_cde_mve: Armv8.1-m CDE with MVE.
6265 # arm_v8_1m_main_cde_mve_fp: Armv8.1-m CDE with MVE with FP support.
6267 # /* { dg-require-effective-target arm_v8m_main_cde_ok } */
6268 # /* { dg-add-options arm_v8m_main_cde } */
6269 # The tests are valid for Arm.
6271 foreach { armfunc armflag armdef arminc } {
6273 "-march=armv8-m.main+cdecp0+cdecp6 -mthumb"
6274 "defined (__ARM_FEATURE_CDE)"
6277 "-march=armv8-m.main+fp+cdecp0+cdecp6 -mthumb -mfpu=auto"
6278 "defined (__ARM_FEATURE_CDE) && defined (__ARM_FP)"
6280 arm_v8_1m_main_cde_mve
6281 "-march=armv8.1-m.main+mve+cdecp0+cdecp6 -mthumb -mfpu=auto"
6282 "defined (__ARM_FEATURE_CDE) && defined (__ARM_FEATURE_MVE)"
6283 "#include <arm_mve.h>"
6284 arm_v8_1m_main_cde_mve_fp
6285 "-march=armv8.1-m.main+mve.fp+cdecp0+cdecp6 -mthumb -mfpu=auto"
6286 "defined (__ARM_FEATURE_CDE) || __ARM_FEATURE_MVE == 3"
6287 "#include <arm_mve.h>"
6289 eval [string map [list FUNC $armfunc FLAG $armflag DEF $armdef INC $arminc ] {
6290 proc check_effective_target_FUNC_ok_nocache { } {
6291 global et_FUNC_flags
6292 set et_FUNC_flags ""
6294 if { ![istarget arm*-*-*] } {
6298 if { [check_no_compiler_messages_nocache FUNC_ok assembly {
6302 #include <arm_cde.h>
6305 set et_FUNC_flags "FLAG"
6312 proc check_effective_target_FUNC_ok { } {
6313 return [check_cached_effective_target FUNC_ok \
6314 check_effective_target_FUNC_ok_nocache]
6317 proc add_options_for_FUNC { flags } {
6318 if { ! [check_effective_target_FUNC_ok] } {
6321 global et_FUNC_flags
6322 return "$flags $et_FUNC_flags"
6325 proc check_effective_target_FUNC_link { } {
6326 if { ! [check_effective_target_FUNC_ok] } {
6329 return [check_no_compiler_messages FUNC_link executable {
6333 #include <arm_cde.h>
6340 } [add_options_for_FUNC ""]]
6343 proc check_effective_target_FUNC_multilib { } {
6344 if { ! [check_effective_target_FUNC_ok] } {
6347 return [check_runtime FUNC_multilib {
6351 #include <arm_cde.h>
6358 } [add_options_for_FUNC ""]]
6363 # Return 1 if the target supports executing ARMv8 NEON instructions, 0
6366 proc check_effective_target_arm_v8_neon_hw { } {
6367 return [check_runtime arm_v8_neon_hw_available {
6368 #include "arm_neon.h"
6372 float32x2_t a = { 1.0f, 2.0f };
6373 #ifdef __ARM_ARCH_ISA_A64
6374 asm ("frinta %0.2s, %1.2s"
6378 asm ("vrinta.f32 %P0, %P1"
6382 return a[0] == 2.0f;
6384 } [add_options_for_arm_v8_neon ""]]
6387 # Return 1 if the target supports executing the ARMv8.1 Adv.SIMD extension, 0
6388 # otherwise. The test is valid for AArch64 and ARM.
6390 proc check_effective_target_arm_v8_1a_neon_hw { } {
6391 if { ![check_effective_target_arm_v8_1a_neon_ok] } {
6394 return [check_runtime arm_v8_1a_neon_hw_available {
6398 #ifdef __ARM_ARCH_ISA_A64
6399 __Int32x2_t a = {0, 1};
6400 __Int32x2_t b = {0, 2};
6403 asm ("sqrdmlah %0.2s, %1.2s, %2.2s"
6406 : /* No clobbers. */);
6410 __simd64_int32_t a = {0, 1};
6411 __simd64_int32_t b = {0, 2};
6412 __simd64_int32_t result;
6414 asm ("vqrdmlah.s32 %P0, %P1, %P2"
6417 : /* No clobbers. */);
6422 } [add_options_for_arm_v8_1a_neon ""]]
6425 # Return 1 if the target supports executing floating point instructions from
6426 # ARMv8.2 with the FP16 extension, 0 otherwise. The test is valid for ARM and
6429 proc check_effective_target_arm_v8_2a_fp16_scalar_hw { } {
6430 if { ![check_effective_target_arm_v8_2a_fp16_scalar_ok] } {
6433 return [check_runtime arm_v8_2a_fp16_scalar_hw_available {
6440 #ifdef __ARM_ARCH_ISA_A64
6442 asm ("fabs %h0, %h1"
6445 : /* No clobbers. */);
6449 asm ("vabs.f16 %0, %1"
6452 : /* No clobbers. */);
6456 return (result == 1.0) ? 0 : 1;
6458 } [add_options_for_arm_v8_2a_fp16_scalar ""]]
6461 # Return 1 if the target supports executing Adv.SIMD instructions from ARMv8.2
6462 # with the FP16 extension, 0 otherwise. The test is valid for ARM and for
6465 proc check_effective_target_arm_v8_2a_fp16_neon_hw { } {
6466 if { ![check_effective_target_arm_v8_2a_fp16_neon_ok] } {
6469 return [check_runtime arm_v8_2a_fp16_neon_hw_available {
6473 #ifdef __ARM_ARCH_ISA_A64
6475 __Float16x4_t a = {1.0, -1.0, 1.0, -1.0};
6476 __Float16x4_t result;
6478 asm ("fabs %0.4h, %1.4h"
6481 : /* No clobbers. */);
6485 __simd64_float16_t a = {1.0, -1.0, 1.0, -1.0};
6486 __simd64_float16_t result;
6488 asm ("vabs.f16 %P0, %P1"
6491 : /* No clobbers. */);
6495 return (result[0] == 1.0) ? 0 : 1;
6497 } [add_options_for_arm_v8_2a_fp16_neon ""]]
6500 # Return 1 if the target supports executing AdvSIMD instructions from ARMv8.2
6501 # with the Dot Product extension, 0 otherwise. The test is valid for ARM and for
6504 proc check_effective_target_arm_v8_2a_dotprod_neon_hw { } {
6505 if { ![check_effective_target_arm_v8_2a_dotprod_neon_ok] } {
6508 return [check_runtime arm_v8_2a_dotprod_neon_hw_available {
6509 #include "arm_neon.h"
6514 uint32x2_t results = {0,0};
6515 uint8x8_t a = {1,1,1,1,2,2,2,2};
6516 uint8x8_t b = {2,2,2,2,3,3,3,3};
6518 #ifdef __ARM_ARCH_ISA_A64
6519 asm ("udot %0.2s, %1.8b, %2.8b"
6522 : /* No clobbers. */);
6525 asm ("vudot.u8 %P0, %P1, %P2"
6528 : /* No clobbers. */);
6531 return (results[0] == 8 && results[1] == 24) ? 1 : 0;
6533 } [add_options_for_arm_v8_2a_dotprod_neon ""]]
6536 # Return 1 if the target supports executing AdvSIMD instructions from ARMv8.2
6537 # with the i8mm extension, 0 otherwise. The test is valid for ARM and for
6540 proc check_effective_target_arm_v8_2a_i8mm_neon_hw { } {
6541 if { ![check_effective_target_arm_v8_2a_i8mm_ok] } {
6544 return [check_runtime arm_v8_2a_i8mm_neon_hw_available {
6545 #include "arm_neon.h"
6550 uint32x2_t results = {0,0};
6551 uint8x8_t a = {1,1,1,1,2,2,2,2};
6552 int8x8_t b = {2,2,2,2,3,3,3,3};
6554 #ifdef __ARM_ARCH_ISA_A64
6555 asm ("usdot %0.2s, %1.8b, %2.8b"
6558 : /* No clobbers. */);
6561 asm ("vusdot.u8 %P0, %P1, %P2"
6564 : /* No clobbers. */);
6567 return (vget_lane_u32 (results, 0) == 8
6568 && vget_lane_u32 (results, 1) == 24) ? 1 : 0;
6570 } [add_options_for_arm_v8_2a_i8mm ""]]
6573 # Return 1 if this is a ARM target with NEON enabled.
6575 proc check_effective_target_arm_neon { } {
6576 if { [check_effective_target_arm32] } {
6577 return [check_no_compiler_messages arm_neon object {
6578 #ifndef __ARM_NEON__
6589 proc check_effective_target_arm_neonv2 { } {
6590 if { [check_effective_target_arm32] } {
6591 return [check_no_compiler_messages arm_neon object {
6592 #ifndef __ARM_NEON__
6595 #ifndef __ARM_FEATURE_FMA
6607 # Return 1 if this is an ARM target with load acquire and store release
6608 # instructions for 8-, 16- and 32-bit types.
6610 proc check_effective_target_arm_acq_rel { } {
6611 return [check_no_compiler_messages arm_acq_rel object {
6613 load_acquire_store_release (void)
6615 asm ("lda r0, [r1]\n\t"
6621 : : : "r0", "memory");
6626 # Add the options needed for MIPS Paired-Single.
6628 proc add_options_for_mpaired_single { flags } {
6629 if { ! [check_effective_target_mpaired_single "-mpaired-single"] } {
6632 return "$flags -mpaired-single"
6635 # Add the options needed for MIPS SIMD Architecture.
6637 proc add_options_for_mips_msa { flags } {
6638 if { ! [check_effective_target_mips_msa "-mmsa"] } {
6641 return "$flags -mmsa"
6644 # Add the options needed for MIPS Loongson MMI Architecture.
6646 proc add_options_for_mips_loongson_mmi { flags } {
6647 if { ! [check_effective_target_mips_loongson_mmi "-mloongson-mmi"] } {
6650 return "$flags -mloongson-mmi"
6654 # Return 1 if this a Loongson-2E or -2F target using an ABI that supports
6655 # the Loongson vector modes.
6657 proc check_effective_target_mips_loongson_mmi { args } {
6658 return [check_no_compiler_messages loongson assembly {
6659 #if !defined(__mips_loongson_mmi)
6660 #error !__mips_loongson_mmi
6662 #if !defined(__mips_loongson_vector_rev)
6663 #error !__mips_loongson_vector_rev
6668 # Return 1 if this is a MIPS target that supports the legacy NAN.
6670 proc check_effective_target_mips_nanlegacy { } {
6671 return [check_no_compiler_messages nanlegacy assembly {
6673 int main () { return 0; }
6677 # Return 1 if an MSA program can be compiled to object
6679 proc check_effective_target_mips_msa { args } {
6680 if ![check_effective_target_nomips16] {
6683 return [check_no_compiler_messages msa object {
6684 #if !defined(__mips_msa)
6685 #error "MSA NOT AVAIL"
6687 #if !(((__mips == 64) || (__mips == 32)) && (__mips_isa_rev >= 2))
6688 #error "MSA NOT AVAIL FOR ISA REV < 2"
6690 #if !defined(__mips_hard_float)
6691 #error "MSA HARD_FLOAT REQUIRED"
6693 #if __mips_fpr != 64
6694 #error "MSA 64-bit FPR REQUIRED"
6700 v8i16 v = __builtin_msa_ldi_h (1);
6708 # Return 1 if this is an ARM target that adheres to the ABI for the ARM
6711 proc check_effective_target_arm_eabi { } {
6712 return [check_no_compiler_messages arm_eabi object {
6713 #ifndef __ARM_EABI__
6721 # Return 1 if this is an ARM target that adheres to the hard-float variant of
6722 # the ABI for the ARM Architecture (e.g. -mfloat-abi=hard).
6724 proc check_effective_target_arm_hf_eabi { } {
6725 return [check_no_compiler_messages arm_hf_eabi object {
6726 #if !defined(__ARM_EABI__) || !defined(__ARM_PCS_VFP)
6727 #error not hard-float EABI
6734 # Return 1 if this is an ARM target uses emulated floating point
6737 proc check_effective_target_arm_softfloat { } {
6738 return [check_no_compiler_messages arm_softfloat object {
6739 #if !defined(__SOFTFP__)
6740 #error not soft-float EABI
6747 # Return 1 if this is an ARM target supporting -mcpu=iwmmxt.
6748 # Some multilibs may be incompatible with this option.
6750 proc check_effective_target_arm_iwmmxt_ok { } {
6751 if { [check_effective_target_arm32] } {
6752 return [check_no_compiler_messages arm_iwmmxt_ok object {
6760 # Return true if LDRD/STRD instructions are prefered over LDM/STM instructions
6761 # for an ARM target.
6762 proc check_effective_target_arm_prefer_ldrd_strd { } {
6763 if { ![check_effective_target_arm32] } {
6767 return [check_no_messages_and_pattern arm_prefer_ldrd_strd "strd\tr" assembly {
6768 void foo (void) { __asm__ ("" ::: "r4", "r5"); }
6772 # Return true if LDRD/STRD instructions are available on this target.
6773 proc check_effective_target_arm_ldrd_strd_ok { } {
6774 if { ![check_effective_target_arm32] } {
6778 return [check_no_compiler_messages arm_ldrd_strd_ok object {
6781 __UINT64_TYPE__ a = 1, b = 10;
6782 __UINT64_TYPE__ *c = &b;
6783 // `a` will be in a valid register since it's a DImode quantity.
6792 #
Return 1 if this is a PowerPC target supporting
-meabi.
6794 proc check_effective_target_powerpc_eabi_ok
{ } {
6795 if { [istarget powerpc
*-*-*] } {
6796 return [check_no_compiler_messages powerpc_eabi_ok object
{
6804 #
Return 1 if this is a PowerPC target with floating
-point registers.
6806 proc check_effective_target_powerpc_fprs
{ } {
6807 if { [istarget powerpc
*-*-*]
6808 ||
[istarget rs6000
-*-*] } {
6809 return [check_no_compiler_messages powerpc_fprs object
{
6821 #
Return 1 if this is a PowerPC target with hardware double
-precision
6824 proc check_effective_target_powerpc_hard_double
{ } {
6825 if { [istarget powerpc
*-*-*]
6826 ||
[istarget rs6000
-*-*] } {
6827 return [check_no_compiler_messages powerpc_hard_double object
{
6839 #
Return 1 if this is a PowerPC target with hardware floating point
sqrt.
6841 proc check_effective_target_powerpc_sqrt
{ } {
6842 # We need to be PowerPC
, and we need to have hardware fp enabled.
6843 if {![check_effective_target_powerpc_fprs
]} {
6847 return [check_no_compiler_messages powerpc_sqrt object
{
6851 #error _ARCH_PPCSQ is not defined
6857 #
Return 1 if this is a PowerPC target supporting
-maltivec.
6859 proc check_effective_target_powerpc_altivec_ok
{ } {
6860 # Not PowerPC
, then not ok
6861 if { !([istarget powerpc
*-*-*] ||
[istarget rs6000
-*-*]) } { return 0 }
6863 # Paired Single
, then not ok
6864 if { [istarget powerpc
-*-linux
*paired
*] } { return 0 }
6866 # AltiVec is not supported
on AIX before
5.3.
6867 if { [istarget powerpc
*-*-aix4
*]
6868 ||
[istarget powerpc
*-*-aix5.1
*]
6869 ||
[istarget powerpc
*-*-aix5.2
*] } { return 0 }
6871 #
Return true iff compiling with
-maltivec does not error.
6872 return [check_no_compiler_messages powerpc_altivec_ok object
{
6877 #
Return 1 if this is a PowerPC target supporting
-mpower8
-vector
6879 proc check_effective_target_powerpc_p8vector_ok
{ } {
6880 if { ([istarget powerpc
*-*-*]
6881 && ![istarget powerpc
-*-linux
*paired
*])
6882 ||
[istarget rs6000
-*-*] } {
6883 # AltiVec is not supported
on AIX before
5.3.
6884 if { [istarget powerpc
*-*-aix4
*]
6885 ||
[istarget powerpc
*-*-aix5.1
*]
6886 ||
[istarget powerpc
*-*-aix5.2
*] } {
6889 # Darwin doesn
't run on power8, so far.
6890 if { [istarget *-*-darwin*] } {
6893 return [check_no_compiler_messages powerpc_p8vector_ok object {
6895 asm volatile ("xxlorc 0,0,0");
6898 } "-mpower8-vector"]
6904 # Return 1 if this is a PowerPC target supporting -mpower9-vector
6906 proc check_effective_target_powerpc_p9vector_ok { } {
6907 if { ([istarget powerpc*-*-*]
6908 && ![istarget powerpc-*-linux*paired*])
6909 || [istarget rs6000-*-*] } {
6910 # AltiVec is not supported on AIX before 5.3.
6911 if { [istarget powerpc*-*-aix4*]
6912 || [istarget powerpc*-*-aix5.1*]
6913 || [istarget powerpc*-*-aix5.2*] } {
6916 # Darwin doesn't run
on power9
, so far.
6917 if { [istarget
*-*-darwin
*] } {
6920 return [check_no_compiler_messages powerpc_p9vector_ok object
{
6923 vector double v
= (vector double
) { 0.0, 0.0 };
6924 asm
("xsxexpdp %0,%1" : "+r" (e) : "wa" (v));
6927 } "-mpower9-vector"]
6933 #
Return 1 if this is a PowerPC target supporting
-mmodulo
6935 proc check_effective_target_powerpc_p9modulo_ok
{ } {
6936 if { ([istarget powerpc
*-*-*]
6937 && ![istarget powerpc
-*-linux
*paired
*])
6938 ||
[istarget rs6000
-*-*] } {
6939 # AltiVec is not supported
on AIX before
5.3.
6940 if { [istarget powerpc
*-*-aix4
*]
6941 ||
[istarget powerpc
*-*-aix5.1
*]
6942 ||
[istarget powerpc
*-*-aix5.2
*] } {
6945 return [check_no_compiler_messages powerpc_p9modulo_ok object
{
6947 int i
= 5, j
= 3, r
= -1;
6948 asm
("modsw %0,%1,%2" : "+r" (r) : "r" (i), "r" (j));
6957 #
return 1 if our compiler returns the ARCH_PWR defines with the options
6958 # as provided by the test.
6959 proc check_effective_target_has_arch_pwr5
{ } {
6960 return [check_no_compiler_messages_nocache arch_pwr5 assembly
{
6964 #error does not have power5 support.
6966 /* "has power5 support" */
6969 } [current_compiler_flags
]]
6972 proc check_effective_target_has_arch_pwr6
{ } {
6973 return [check_no_compiler_messages_nocache arch_pwr6 assembly
{
6977 #error does not have power6 support.
6979 /* "has power6 support" */
6982 } [current_compiler_flags
]]
6985 proc check_effective_target_has_arch_pwr7
{ } {
6986 return [check_no_compiler_messages_nocache arch_pwr7 assembly
{
6990 #error does not have power7 support.
6992 /* "has power7 support" */
6995 } [current_compiler_flags
]]
6998 proc check_effective_target_has_arch_pwr8
{ } {
6999 return [check_no_compiler_messages_nocache arch_pwr8 assembly
{
7003 #error does not have power8 support.
7005 /* "has power8 support" */
7008 } [current_compiler_flags
]]
7011 proc check_effective_target_has_arch_pwr9
{ } {
7012 return [check_no_compiler_messages_nocache arch_pwr9 assembly
{
7016 #error does not have power9 support.
7018 /* "has power9 support" */
7021 } [current_compiler_flags
]]
7024 proc check_effective_target_has_arch_pwr10
{ } {
7025 return [check_no_compiler_messages_nocache arch_pwr10 assembly
{
7029 #error does not have power10 support.
7031 /* "has power10 support" */
7034 } [current_compiler_flags
]]
7037 proc check_effective_target_has_arch_ppc64
{ } {
7038 return [check_no_compiler_messages_nocache arch_ppc64 assembly
{
7042 #error does not have ppc64 support.
7044 /* "has ppc64 support" */
7047 } [current_compiler_flags
]]
7050 #
Return 1 if this is a PowerPC target supporting
-mcpu
=power10.
7051 #
Limit this to
64-bit linux systems
for now until other targets support
7054 proc check_effective_target_power10_ok
{ } {
7055 if { ([istarget powerpc64
*-*-linux
*]) } {
7056 return [check_no_compiler_messages power10_ok object
{
7059 asm
("pli %0,%1" : "=r" (e) : "n" (0x12345));
7068 #
Return 1 if this is a PowerPC target supporting
-mfloat128 via either
7069 # software emulation
on power7
/power8 systems or hardware support
on power9.
7071 proc check_effective_target_powerpc_float128_sw_ok
{ } {
7072 if { ([istarget powerpc
*-*-*]
7073 && ![istarget powerpc
-*-linux
*paired
*])
7074 ||
[istarget rs6000
-*-*] } {
7075 # AltiVec is not supported
on AIX before
5.3.
7076 if { [istarget powerpc
*-*-aix4
*]
7077 ||
[istarget powerpc
*-*-aix5.1
*]
7078 ||
[istarget powerpc
*-*-aix5.2
*] } {
7081 # Darwin doesn
't have VSX, so no soft support for float128.
7082 if { [istarget *-*-darwin*] } {
7085 return [check_no_compiler_messages powerpc_float128_sw_ok object {
7086 volatile __float128 x = 1.0q;
7087 volatile __float128 y = 2.0q;
7089 __float128 z = x + y;
7092 } "-mfloat128 -mvsx"]
7098 # Return 1 if this is a PowerPC target supporting -mfloat128 via hardware
7099 # support on power9.
7101 proc check_effective_target_powerpc_float128_hw_ok { } {
7102 if { ([istarget powerpc*-*-*]
7103 && ![istarget powerpc-*-linux*paired*])
7104 || [istarget rs6000-*-*] } {
7105 # AltiVec is not supported on AIX before 5.3.
7106 if { [istarget powerpc*-*-aix4*]
7107 || [istarget powerpc*-*-aix5.1*]
7108 || [istarget powerpc*-*-aix5.2*] } {
7111 # Darwin doesn't run
on any machine with float128 h
/w so far.
7112 if { [istarget
*-*-darwin
*] } {
7115 return [check_no_compiler_messages powerpc_float128_hw_ok object
{
7116 volatile __float128 x
= 1.0q
;
7117 volatile __float128 y
= 2.0q
;
7120 __asm__
("xsaddqp %0,%1,%2" : "=v" (z) : "v" (x), "v" (y));
7123 } "-mfloat128-hardware"]
7129 #
Return 1 if current options
define float128
, 0 otherwise.
7131 proc check_effective_target_ppc_float128
{ } {
7132 return [check_no_compiler_messages_nocache ppc_float128 object
{
7135 #ifndef __FLOAT128__
7142 #
Return 1 if current options generate float128 insns
, 0 otherwise.
7144 proc check_effective_target_ppc_float128_insns
{ } {
7145 return [check_no_compiler_messages_nocache ppc_float128 object
{
7148 #ifndef __FLOAT128_HARDWARE__
7155 #
Return 1 if current options generate VSX instructions
, 0 otherwise.
7157 proc check_effective_target_powerpc_vsx
{ } {
7158 return [check_no_compiler_messages_nocache powerpc_vsx object
{
7168 #
Return 1 if this is a PowerPC target supporting
-mvsx
7170 proc check_effective_target_powerpc_vsx_ok
{ } {
7171 if { ([istarget powerpc
*-*-*]
7172 && ![istarget powerpc
-*-linux
*paired
*])
7173 ||
[istarget rs6000
-*-*] } {
7174 # VSX is not supported
on AIX before
7.1.
7175 if { [istarget powerpc
*-*-aix4
*]
7176 ||
[istarget powerpc
*-*-aix5
*]
7177 ||
[istarget powerpc
*-*-aix6
*] } {
7180 # Darwin doesn
't have VSX, even if it's used with an assembler
7181 # which recognises the insns.
7182 if { [istarget
*-*-darwin
*] } {
7185 return [check_no_compiler_messages powerpc_vsx_ok object
{
7187 asm volatile
("xxlor 0,0,0");
7196 #
Return 1 if this is a PowerPC target supporting
-mhtm
7198 proc check_effective_target_powerpc_htm_ok
{ } {
7199 if { ([istarget powerpc
*-*-*]
7200 && ![istarget powerpc
-*-linux
*paired
*])
7201 ||
[istarget rs6000
-*-*] } {
7202 # HTM is not supported
on AIX yet.
7203 if { [istarget powerpc
*-*-aix
*] } {
7206 return [check_no_compiler_messages powerpc_htm_ok object
{
7208 asm volatile
("tbegin. 0");
7217 #
Return 1 if the target supports executing HTM hardware instructions
,
7218 #
0 otherwise.
Cache the result.
7220 proc check_htm_hw_available
{ } {
7221 return [check_cached_effective_target htm_hw_available
{
7222 #
For now
, disable
on Darwin
7223 if { [istarget powerpc
-*-eabi
] ||
[istarget powerpc
*-*-eabispe
] ||
[istarget
*-*-darwin
*]} {
7226 check_runtime_nocache htm_hw_available
{
7236 #
Return 1 if this is a PowerPC target supporting
-mcpu
=cell.
7238 proc check_effective_target_powerpc_ppu_ok
{ } {
7239 if [check_effective_target_powerpc_altivec_ok
] {
7240 return [check_no_compiler_messages cell_asm_available object
{
7243 asm volatile
("lvlx v0,v0,v0");
7245 asm volatile
("lvlx 0,0,0");
7255 #
Return 1 if this is a PowerPC target that supports SPU.
7257 proc check_effective_target_powerpc_spu
{ } {
7258 if { [istarget powerpc
*-*-linux
*] } {
7259 return [check_effective_target_powerpc_altivec_ok
]
7265 #
Return 1 if this is a PowerPC SPE target. The check includes options
7266 # specified by dg
-options
for this test
, so don
't cache the result.
7268 proc check_effective_target_powerpc_spe_nocache { } {
7269 if { [istarget powerpc*-*-*] } {
7270 return [check_no_compiler_messages_nocache powerpc_spe object {
7276 } [current_compiler_flags]]
7282 # Return 1 if this is a PowerPC target with SPE enabled.
7284 proc check_effective_target_powerpc_spe { } {
7285 if { [istarget powerpc*-*-*] } {
7286 return [check_no_compiler_messages powerpc_spe object {
7298 # Return 1 if this is a PowerPC target with Altivec enabled.
7300 proc check_effective_target_powerpc_altivec { } {
7301 if { [istarget powerpc*-*-*] } {
7302 return [check_no_compiler_messages powerpc_altivec object {
7314 # Return 1 if this is a PowerPC 405 target. The check includes options
7315 # specified by dg-options for this test, so don't
cache the result.
7317 proc check_effective_target_powerpc_405_nocache
{ } {
7318 if { [istarget powerpc
*-*-*] ||
[istarget rs6000
-*-*] } {
7319 return [check_no_compiler_messages_nocache powerpc_405 object
{
7325 } [current_compiler_flags
]]
7331 #
Return 1 if this is a PowerPC target using the ELFv2 ABI.
7333 proc check_effective_target_powerpc_elfv2
{ } {
7334 if { [istarget powerpc
*-*-*] } {
7335 return [check_no_compiler_messages powerpc_elfv2 object
{
7337 #error not ELF v2 ABI
7347 #
Return 1 if this is a PowerPC target supporting
-mrop
-protect
7349 proc check_effective_target_rop_ok
{ } {
7350 return [check_effective_target_power10_ok
] && [check_effective_target_powerpc_elfv2
]
7353 # The VxWorks SPARC simulator accepts only EM_SPARC executables and
7354 # chokes
on EM_SPARC32PLUS or EM_SPARCV9 executables.
Return 1 if the
7355 # test environment appears to run executables
on such a simulator.
7357 proc check_effective_target_ultrasparc_hw
{ } {
7358 return [check_runtime ultrasparc_hw
{
7359 int main
() { return 0; }
7360 } "-mcpu=ultrasparc"]
7363 #
Return 1 if the test environment supports executing UltraSPARC VIS2
7364 # instructions. We check this by attempting
: "bmask %g0, %g0, %g0"
7366 proc check_effective_target_ultrasparc_vis2_hw
{ } {
7367 return [check_runtime ultrasparc_vis2_hw
{
7368 int main
() { __asm__
(".word 0x81b00320"); return 0; }
7369 } "-mcpu=ultrasparc3"]
7372 #
Return 1 if the test environment supports executing UltraSPARC VIS3
7373 # instructions. We check this by attempting
: "addxc %g0, %g0, %g0"
7375 proc check_effective_target_ultrasparc_vis3_hw
{ } {
7376 return [check_runtime ultrasparc_vis3_hw
{
7377 int main
() { __asm__
(".word 0x81b00220"); return 0; }
7381 #
Return 1 if this is a SPARC
-V9 target.
7383 proc check_effective_target_sparc_v9
{ } {
7384 if { [istarget sparc
*-*-*] } {
7385 return [check_no_compiler_messages sparc_v9 object
{
7387 asm volatile
("return %i7+8");
7396 #
Return 1 if this is a SPARC target with VIS enabled.
7398 proc check_effective_target_sparc_vis
{ } {
7399 if { [istarget sparc
*-*-*] } {
7400 return [check_no_compiler_messages sparc_vis object
{
7412 #
Return 1 if the target supports hardware vector shift operation.
7414 proc check_effective_target_vect_shift
{ } {
7415 return [check_cached_effective_target_indexed vect_shift
{
7416 expr
{([istarget powerpc
*-*-*]
7417 && ![istarget powerpc
-*-linux
*paired
*])
7418 ||
[istarget ia64
-*-*]
7419 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
7420 ||
[istarget aarch64
*-*-*]
7421 ||
[is
-effective
-target arm_neon
]
7422 ||
([istarget mips
*-*-*]
7423 && ([et
-is
-effective
-target mips_msa
]
7424 ||
[et
-is
-effective
-target mips_loongson_mmi
]))
7425 ||
([istarget s390
*-*-*]
7426 && [check_effective_target_s390_vx
])
7427 ||
[istarget amdgcn
-*-*]
7428 ||
([istarget riscv
*-*-*]
7429 && [check_effective_target_riscv_v
]) }}]
7432 #
Return 1 if the target supports hardware vector shift by register operation.
7434 proc check_effective_target_vect_var_shift
{ } {
7435 return [check_cached_effective_target_indexed vect_var_shift
{
7436 expr
{(([istarget i?
86-*-*] ||
[istarget x86_64
-*-*])
7437 && [check_avx2_available
])
7438 ||
[istarget aarch64
*-*-*]
7439 ||
([istarget riscv
*-*-*]
7440 && [check_effective_target_riscv_v
])
7444 proc check_effective_target_whole_vector_shift
{ } {
7445 if { [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
7446 ||
[istarget ia64
-*-*]
7447 ||
[istarget aarch64
*-*-*]
7448 ||
[istarget powerpc64
*-*-*]
7449 ||
([is
-effective
-target arm_neon
]
7450 && [check_effective_target_arm_little_endian
])
7451 ||
([istarget mips
*-*-*]
7452 && [et
-is
-effective
-target mips_loongson_mmi
])
7453 ||
([istarget s390
*-*-*]
7454 && [check_effective_target_s390_vx
])
7455 ||
[istarget amdgcn
-*-*]
7456 ||
([istarget riscv
*-*-*]
7457 && [check_effective_target_riscv_v
]) } {
7463 verbose
"check_effective_target_vect_long: returning $answer" 2
7467 #
Return 1 if the target supports vector bswap operations.
7469 proc check_effective_target_vect_bswap
{ } {
7470 return [check_cached_effective_target_indexed vect_bswap
{
7471 expr
{ ([istarget aarch64
*-*-*]
7472 ||
[is
-effective
-target arm_neon
]
7473 ||
[istarget amdgcn
-*-*])
7474 ||
([istarget s390
*-*-*]
7475 && [check_effective_target_s390_vx
]) }}]
7478 #
Return 1 if the target supports comparison of
bool vectors
for at
7479 # least one vector length.
7481 proc check_effective_target_vect_bool_cmp
{ } {
7482 return [check_cached_effective_target_indexed vect_bool_cmp
{
7483 expr
{ [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
7484 ||
[istarget aarch64
*-*-*]
7485 ||
[is
-effective
-target arm_neon
]
7486 ||
([istarget riscv
*-*-*]
7487 && [check_effective_target_riscv_v
]) }}]
7490 #
Return 1 if the target supports addition of char vectors
for at least
7491 # one vector length.
7493 proc check_effective_target_vect_char_add
{ } {
7494 return [check_cached_effective_target_indexed vect_char_add
{
7496 [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
7497 ||
([istarget powerpc
*-*-*]
7498 && ![istarget powerpc
-*-linux
*paired
*])
7499 ||
[istarget amdgcn
-*-*]
7500 ||
[istarget ia64
-*-*]
7501 ||
[istarget aarch64
*-*-*]
7502 ||
[is
-effective
-target arm_neon
]
7503 ||
([istarget mips
*-*-*]
7504 && ([et
-is
-effective
-target mips_loongson_mmi
]
7505 ||
[et
-is
-effective
-target mips_msa
]))
7506 ||
([istarget s390
*-*-*]
7507 && [check_effective_target_s390_vx
])
7508 ||
([istarget riscv
*-*-*]
7509 && [check_effective_target_riscv_v
])
7513 #
Return 1 if the target supports hardware vector shift operation
for char.
7515 proc check_effective_target_vect_shift_char
{ } {
7516 return [check_cached_effective_target_indexed vect_shift_char
{
7517 expr
{ ([istarget powerpc
*-*-*]
7518 && ![istarget powerpc
-*-linux
*paired
*])
7519 ||
[is
-effective
-target arm_neon
]
7520 ||
([istarget mips
*-*-*]
7521 && [et
-is
-effective
-target mips_msa
])
7522 ||
([istarget s390
*-*-*]
7523 && [check_effective_target_s390_vx
])
7524 ||
[istarget amdgcn
-*-*]
7525 ||
([istarget riscv
*-*-*]
7526 && [check_effective_target_riscv_v
]) }}]
7529 #
Return 1 if the target supports hardware vectors of long
, 0 otherwise.
7531 # This can change
for different subtargets so
do not
cache the result.
7533 proc check_effective_target_vect_long
{ } {
7534 if { [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
7535 ||
(([istarget powerpc
*-*-*]
7536 && ![istarget powerpc
-*-linux
*paired
*])
7537 && [check_effective_target_ilp32
])
7538 ||
[is
-effective
-target arm_neon
]
7539 ||
([istarget sparc
*-*-*] && [check_effective_target_ilp32
])
7540 ||
[istarget aarch64
*-*-*]
7541 ||
([istarget mips
*-*-*]
7542 && [et
-is
-effective
-target mips_msa
])
7543 ||
([istarget s390
*-*-*]
7544 && [check_effective_target_s390_vx
])
7545 ||
[istarget amdgcn
-*-*]
7546 ||
([istarget riscv
*-*-*]
7547 && [check_effective_target_riscv_v
]) } {
7553 verbose
"check_effective_target_vect_long: returning $answer" 2
7557 #
Return 1 if the target supports hardware vectors of float when
7558 #
-funsafe
-math
-optimizations is enabled
, 0 otherwise.
7560 # This won
't change for different subtargets so cache the result.
7562 proc check_effective_target_vect_float { } {
7563 return [check_cached_effective_target_indexed vect_float {
7564 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
7565 || [istarget powerpc*-*-*]
7566 || [istarget mips-sde-elf]
7567 || [istarget mipsisa64*-*-*]
7568 || [istarget ia64-*-*]
7569 || [istarget aarch64*-*-*]
7570 || ([istarget mips*-*-*]
7571 && [et-is-effective-target mips_msa])
7572 || [is-effective-target arm_neon]
7573 || ([istarget s390*-*-*]
7574 && [check_effective_target_s390_vxe])
7575 || [istarget amdgcn-*-*]
7576 || ([istarget riscv*-*-*]
7577 && [check_effective_target_riscv_v]) }}]
7580 # Return 1 if the target supports hardware vectors of float without
7581 # -funsafe-math-optimizations being enabled, 0 otherwise.
7583 proc check_effective_target_vect_float_strict { } {
7584 return [expr { [check_effective_target_vect_float]
7585 && ![istarget arm*-*-*] }]
7588 # Return 1 if the target supports hardware vectors of double, 0 otherwise.
7590 # This won't change
for different subtargets so
cache the result.
7592 proc check_effective_target_vect_double
{ } {
7593 return [check_cached_effective_target_indexed vect_double
{
7594 expr
{ (([istarget i?
86-*-*] ||
[istarget x86_64
-*-*])
7595 && [check_no_compiler_messages vect_double assembly
{
7596 #ifdef __tune_atom__
7597 # error No double vectorizer support.
7600 ||
[istarget aarch64
*-*-*]
7601 ||
([istarget powerpc
*-*-*] && [check_vsx_hw_available
])
7602 ||
([istarget mips
*-*-*]
7603 && [et
-is
-effective
-target mips_msa
])
7604 ||
([istarget s390
*-*-*]
7605 && [check_effective_target_s390_vx
])
7606 ||
[istarget amdgcn
-*-*]
7607 ||
([istarget riscv
*-*-*]
7608 && [check_effective_target_riscv_v
])} }]
7611 #
Return 1 if the target supports conditional addition
, subtraction
,
7612 # multiplication
, division
, minimum and maximum
on vectors of double
,
7613 # via the cond_ optabs.
Return 0 otherwise.
7615 proc check_effective_target_vect_double_cond_arith
{ } {
7616 return [expr
{ [check_effective_target_aarch64_sve
]
7617 ||
[check_effective_target_riscv_v
] }]
7620 #
Return 1 if the target supports hardware vectors of long long
, 0 otherwise.
7622 # This won
't change for different subtargets so cache the result.
7624 proc check_effective_target_vect_long_long { } {
7625 return [check_cached_effective_target_indexed vect_long_long {
7626 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
7627 || ([istarget mips*-*-*]
7628 && [et-is-effective-target mips_msa])
7629 || ([istarget s390*-*-*]
7630 && [check_effective_target_s390_vx])
7631 || ([istarget powerpc*-*-*]
7632 && ![istarget powerpc-*-linux*paired*]
7633 && [check_effective_target_has_arch_pwr8])
7634 || [istarget aarch64*-*-*]
7635 || ([istarget riscv*-*-*]
7636 && [check_effective_target_riscv_v])}}]
7640 # Return 1 if the target plus current options does not support a vector
7641 # max instruction on "int", 0 otherwise.
7643 # This won't change
for different subtargets so
cache the result.
7645 proc check_effective_target_vect_no_int_min_max
{ } {
7646 return [check_cached_effective_target_indexed vect_no_int_min_max
{
7647 expr
{ [istarget sparc
*-*-*]
7648 ||
[istarget alpha
*-*-*]
7649 ||
([istarget mips
*-*-*]
7650 && [et
-is
-effective
-target mips_loongson_mmi
]) }}]
7653 #
Return 1 if the target plus current options does not support a vector
7654 # add instruction
on "int", 0 otherwise.
7656 # This won
't change for different subtargets so cache the result.
7658 proc check_effective_target_vect_no_int_add { } {
7659 # Alpha only supports vector add on V8QI and V4HI.
7660 return [check_cached_effective_target_indexed vect_no_int_add {
7661 expr { [istarget alpha*-*-*] }}]
7664 # Return 1 if the target plus current options does not support vector
7665 # bitwise instructions, 0 otherwise.
7667 # This won't change
for different subtargets so
cache the result.
7669 proc check_effective_target_vect_no_bitwise
{ } {
7670 return [check_cached_effective_target_indexed vect_no_bitwise
{ return 0 }]
7673 #
Return 1 if the target plus current options supports vector permutation
,
7676 # This won
't change for different subtargets so cache the result.
7678 proc check_effective_target_vect_perm { } {
7679 return [check_cached_effective_target_indexed vect_perm {
7680 expr { [is-effective-target arm_neon]
7681 || [istarget aarch64*-*-*]
7682 || [istarget powerpc*-*-*]
7683 || [istarget i?86-*-*] || [istarget x86_64-*-*]
7684 || ([istarget mips*-*-*]
7685 && ([et-is-effective-target mpaired_single]
7686 || [et-is-effective-target mips_msa]))
7687 || ([istarget s390*-*-*]
7688 && [check_effective_target_s390_vx])
7689 || [istarget amdgcn-*-*]
7690 || ([istarget riscv*-*-*]
7691 && [check_effective_target_riscv_v]) }}]
7694 # Return 1 if, for some VF:
7696 # - the target's default vector size is VF
* ELEMENT_BITS bits
7698 #
- it is possible to implement the equivalent of
:
7700 #
int<ELEMENT_BITS
>_t s1
[COUNT][COUNT * VF
], s2
[COUNT * VF
];
7701 #
for (int i
= 0; i
< COUNT; ++i
)
7702 #
for (int j
= 0; j
< COUNT * VF
; ++j
)
7703 # s1
[i
][j
] = s2
[j
- j
% COUNT + i
]
7705 # using only a single
2-vector permute
for each vector in s1.
7707 # E.g.
for COUNT == 3 and vector length
4, the two arrays would be
:
7709 # s2 | a0 a1 a2 a3 | b0 b1 b2 b3 | c0 c1 c2 c3
7710 #
------+-------------+-------------+------------
7711 # s1
[0] | a0 a0 a0 a3 | a3 a3 b2 b2 | b2 c1 c1 c1
7712 # s1
[1] | a1 a1 a1 b0 | b0 b0 b3 b3 | b3 c2 c2 c2
7713 # s1
[2] | a2 a2 a2 b1 | b1 b1 c0 c0 | c0 c3 c3 c3
7715 # Each s1 permute requires only two of a
, b and c.
7717 # The distance between the start of vector n in s1
[0] and the start
7718 # of vector n in s2 is
:
7720 # A
= (n
* VF
) % COUNT
7722 # The corresponding value
for the end of vector n is
:
7724 # B
= (n
* VF
+ VF
- 1) % COUNT
7726 # Subtracting i from each value gives the corresponding difference
7727 #
for s1
[i
]. The condition being tested by this function is false
7728 # iff A
- i
> 0 and B
- i
< 0 for some i and n
, such that the first
7729 # element
for s1
[i
] comes from vector n
- 1 of s2 and the last element
7730 # comes from vector n
+ 1 of s2. The condition is therefore true iff
7731 # A
<= B
for all n. This is turn means the condition is true iff
:
7733 #
(n
* VF
) % COUNT + (VF
- 1) % COUNT < COUNT
7735 #
for all n.
COUNT - (n
* VF
) % COUNT is bounded by gcd
(VF
, COUNT),
7736 # and will be that value
for at least one n in
[0, COUNT), so we want
:
7738 #
(VF
- 1) % COUNT < gcd
(VF
, COUNT)
7740 proc vect_perm_supported
{ count element_bits
} {
7741 set vector_bits
[lindex
[available_vector_sizes
] 0]
7742 # The number of vectors has to be a power of
2 when permuting
7743 #
variable-length vectors.
7744 if { $vector_bits
<= 0 && ($
count & -$
count) != $
count } {
7747 set vf
[expr
{ $vector_bits
/ $element_bits
}]
7749 # Compute gcd
(VF
, COUNT).
7752 while { $temp1
> 0 } {
7753 set temp2
[expr
{ $gcd
% $temp1
}]
7757 return [expr
{ ($vf
- 1) % $
count < $gcd
}]
7760 #
Return 1 if the target supports SLP permutation of
3 vectors when each
7761 # element has
32 bits.
7763 proc check_effective_target_vect_perm3_int
{ } {
7764 return [expr
{ [check_effective_target_vect_perm
]
7765 && [vect_perm_supported
3 32] }]
7768 #
Return 1 if the target plus current options supports vector permutation
7769 #
on byte
-sized elements
, 0 otherwise.
7771 # This won
't change for different subtargets so cache the result.
7773 proc check_effective_target_vect_perm_byte { } {
7774 return [check_cached_effective_target_indexed vect_perm_byte {
7775 expr { ([is-effective-target arm_neon]
7776 && [is-effective-target arm_little_endian])
7777 || ([istarget aarch64*-*-*]
7778 && [is-effective-target aarch64_little_endian])
7779 || [istarget powerpc*-*-*]
7780 || ([istarget mips-*.*]
7781 && [et-is-effective-target mips_msa])
7782 || ([istarget s390*-*-*]
7783 && [check_effective_target_s390_vx])
7784 || [istarget amdgcn-*-*]
7785 || ([istarget riscv*-*-*]
7786 && [check_effective_target_riscv_v]) }}]
7789 # Return 1 if the target supports SLP permutation of 3 vectors when each
7790 # element has 8 bits.
7792 proc check_effective_target_vect_perm3_byte { } {
7793 return [expr { [check_effective_target_vect_perm_byte]
7794 && [vect_perm_supported 3 8] }]
7797 # Return 1 if the target plus current options supports vector permutation
7798 # on short-sized elements, 0 otherwise.
7800 # This won't change
for different subtargets so
cache the result.
7802 proc check_effective_target_vect_perm_short
{ } {
7803 return [check_cached_effective_target_indexed vect_perm_short
{
7804 expr
{ ([is
-effective
-target arm_neon
]
7805 && [is
-effective
-target arm_little_endian
])
7806 ||
([istarget aarch64
*-*-*]
7807 && [is
-effective
-target aarch64_little_endian
])
7808 ||
[istarget powerpc
*-*-*]
7809 ||
(([istarget i?
86-*-*] ||
[istarget x86_64
-*-*])
7810 && [check_ssse3_available
])
7811 ||
([istarget mips
*-*-*]
7812 && [et
-is
-effective
-target mips_msa
])
7813 ||
([istarget s390
*-*-*]
7814 && [check_effective_target_s390_vx
])
7815 ||
[istarget amdgcn
-*-*]
7816 ||
([istarget riscv
*-*-*]
7817 && [check_effective_target_riscv_v
]) }}]
7820 #
Return 1 if the target supports SLP permutation of
3 vectors when each
7821 # element has
16 bits.
7823 proc check_effective_target_vect_perm3_short
{ } {
7824 return [expr
{ [check_effective_target_vect_perm_short
]
7825 && [vect_perm_supported
3 16] }]
7828 #
Return 1 if the target plus current options supports folding of
7829 # copysign into XORSIGN.
7831 # This won
't change for different subtargets so cache the result.
7833 proc check_effective_target_xorsign { } {
7834 return [check_cached_effective_target_indexed xorsign {
7835 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
7836 || [istarget aarch64*-*-*] || [istarget arm*-*-*] }}]
7839 # Return 1 if the target plus current options supports a vector
7840 # widening summation of *short* args into *int* result, 0 otherwise.
7842 # This won't change
for different subtargets so
cache the result.
7844 proc check_effective_target_vect_widen_sum_hi_to_si_pattern
{ } {
7845 return [check_cached_effective_target_indexed vect_widen_sum_hi_to_si_pattern
{
7846 expr
{ [istarget powerpc
*-*-*]
7847 ||
([istarget aarch64
*-*-*]
7848 && ![check_effective_target_aarch64_sve
])
7849 ||
[is
-effective
-target arm_neon
]
7850 ||
[istarget ia64
-*-*] }}]
7853 #
Return 1 if the target plus current options supports a vector
7854 # widening summation of
*short
* args into
*int* result
, 0 otherwise.
7855 # A target can also support this widening summation
if it can support
7856 # promotion
(unpacking
) from shorts to ints.
7858 # This won
't change for different subtargets so cache the result.
7860 proc check_effective_target_vect_widen_sum_hi_to_si { } {
7861 return [check_cached_effective_target_indexed vect_widen_sum_hi_to_si {
7862 expr { [check_effective_target_vect_unpack]
7863 || [istarget powerpc*-*-*]
7864 || [istarget ia64-*-*]
7865 || [istarget riscv*-*-*] }}]
7868 # Return 1 if the target plus current options supports a vector
7869 # widening summation of *char* args into *short* result, 0 otherwise.
7870 # A target can also support this widening summation if it can support
7871 # promotion (unpacking) from chars to shorts.
7873 # This won't change
for different subtargets so
cache the result.
7875 proc check_effective_target_vect_widen_sum_qi_to_hi
{ } {
7876 return [check_cached_effective_target_indexed vect_widen_sum_qi_to_hi
{
7877 expr
{ [check_effective_target_vect_unpack
]
7878 ||
[is
-effective
-target arm_neon
]
7879 ||
[istarget ia64
-*-*]
7880 ||
[istarget riscv
*-*-*] }}]
7883 #
Return 1 if the target plus current options supports a vector
7884 # widening summation of
*char
* args into
*int* result
, 0 otherwise.
7886 # This won
't change for different subtargets so cache the result.
7888 proc check_effective_target_vect_widen_sum_qi_to_si { } {
7889 return [check_cached_effective_target_indexed vect_widen_sum_qi_to_si {
7890 expr { [istarget powerpc*-*-*]
7891 || [istarget riscv*-*-*] }}]
7894 # Return 1 if the target plus current options supports a vector
7895 # widening multiplication of *char* args into *short* result, 0 otherwise.
7896 # A target can also support this widening multplication if it can support
7897 # promotion (unpacking) from chars to shorts, and vect_short_mult (non-widening
7898 # multiplication of shorts).
7900 # This won't change
for different subtargets so
cache the result.
7903 proc check_effective_target_vect_widen_mult_qi_to_hi
{ } {
7904 return [check_cached_effective_target_indexed vect_widen_mult_qi_to_hi
{
7905 expr
{ ([check_effective_target_vect_unpack
]
7906 && [check_effective_target_vect_short_mult
])
7907 ||
([istarget powerpc
*-*-*]
7908 ||
([istarget aarch64
*-*-*]
7909 && ![check_effective_target_aarch64_sve
])
7910 ||
[is
-effective
-target arm_neon
]
7911 ||
([istarget s390
*-*-*]
7912 && [check_effective_target_s390_vx
]))
7913 ||
[istarget amdgcn
-*-*] }}]
7916 #
Return 1 if the target plus current options supports a vector
7917 # widening multiplication of
*short
* args into
*int* result
, 0 otherwise.
7918 # A target can also support this widening multplication
if it can support
7919 # promotion
(unpacking
) from shorts to ints
, and vect_int_mult
(non
-widening
7920 # multiplication of ints
).
7922 # This won
't change for different subtargets so cache the result.
7925 proc check_effective_target_vect_widen_mult_hi_to_si { } {
7926 return [check_cached_effective_target_indexed vect_widen_mult_hi_to_si {
7927 expr { ([check_effective_target_vect_unpack]
7928 && [check_effective_target_vect_int_mult])
7929 || ([istarget powerpc*-*-*]
7930 || [istarget ia64-*-*]
7931 || ([istarget aarch64*-*-*]
7932 && ![check_effective_target_aarch64_sve])
7933 || [istarget i?86-*-*] || [istarget x86_64-*-*]
7934 || [is-effective-target arm_neon]
7935 || ([istarget s390*-*-*]
7936 && [check_effective_target_s390_vx]))
7937 || [istarget amdgcn-*-*] }}]
7940 # Return 1 if the target plus current options supports a vector
7941 # widening multiplication of *char* args into *short* result, 0 otherwise.
7943 # This won't change
for different subtargets so
cache the result.
7945 proc check_effective_target_vect_widen_mult_qi_to_hi_pattern
{ } {
7946 return [check_cached_effective_target_indexed vect_widen_mult_qi_to_hi_pattern
{
7947 expr
{ [istarget powerpc
*-*-*]
7948 ||
([is
-effective
-target arm_neon
]
7949 && [check_effective_target_arm_little_endian
])
7950 ||
([istarget s390
*-*-*]
7951 && [check_effective_target_s390_vx
])
7952 ||
[istarget amdgcn
-*-*] }}]
7955 #
Return 1 if the target plus current options supports a vector
7956 # widening multiplication of
*short
* args into
*int* result
, 0 otherwise.
7958 # This won
't change for different subtargets so cache the result.
7960 proc check_effective_target_vect_widen_mult_hi_to_si_pattern { } {
7961 return [check_cached_effective_target_indexed vect_widen_mult_hi_to_si_pattern {
7962 expr { [istarget powerpc*-*-*]
7963 || [istarget ia64-*-*]
7964 || [istarget i?86-*-*] || [istarget x86_64-*-*]
7965 || ([is-effective-target arm_neon]
7966 && [check_effective_target_arm_little_endian])
7967 || ([istarget s390*-*-*]
7968 && [check_effective_target_s390_vx])
7969 || [istarget amdgcn-*-*] }}]
7972 # Return 1 if the target plus current options supports a vector
7973 # widening multiplication of *int* args into *long* result, 0 otherwise.
7975 # This won't change
for different subtargets so
cache the result.
7977 proc check_effective_target_vect_widen_mult_si_to_di_pattern
{ } {
7978 return [check_cached_effective_target_indexed vect_widen_mult_si_to_di_pattern
{
7979 expr
{ [istarget ia64
-*-*]
7980 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
7981 ||
([istarget s390
*-*-*]
7982 && [check_effective_target_s390_vx
]) }}]
7985 #
Return 1 if the target plus current options supports a vector
7986 # widening shift
, 0 otherwise.
7988 # This won
't change for different subtargets so cache the result.
7990 proc check_effective_target_vect_widen_shift { } {
7991 return [check_cached_effective_target_indexed vect_widen_shift {
7992 expr { [is-effective-target arm_neon] }}]
7995 # Return 1 if the target plus current options supports a vector
7996 # dot-product of signed chars, 0 otherwise.
7998 # This won't change
for different subtargets so
cache the result.
8000 proc check_effective_target_vect_sdot_qi
{ } {
8001 return [check_cached_effective_target_indexed vect_sdot_qi
{
8002 expr
{ [istarget ia64
-*-*]
8003 ||
[istarget aarch64
*-*-*]
8004 ||
[istarget arm
*-*-*]
8005 ||
([istarget mips
*-*-*]
8006 && [et
-is
-effective
-target mips_msa
])
8007 ||
([istarget riscv
*-*-*]
8008 && [check_effective_target_riscv_v
]) }}]
8011 #
Return 1 if the target plus current options supports a vector
8012 # dot
-product of unsigned chars
, 0 otherwise.
8014 # This won
't change for different subtargets so cache the result.
8016 proc check_effective_target_vect_udot_qi { } {
8017 return [check_cached_effective_target_indexed vect_udot_qi {
8018 expr { [istarget powerpc*-*-*]
8019 || [istarget aarch64*-*-*]
8020 || [istarget arm*-*-*]
8021 || [istarget ia64-*-*]
8022 || ([istarget mips*-*-*]
8023 && [et-is-effective-target mips_msa])
8024 || ([istarget riscv*-*-*]
8025 && [check_effective_target_riscv_v]) }}]
8028 # Return 1 if the target plus current options supports a vector
8029 # dot-product where one operand of the multiply is signed char
8030 # and the other unsigned chars, 0 otherwise.
8032 # This won't change
for different subtargets so
cache the result.
8034 proc check_effective_target_vect_usdot_qi
{ } {
8035 return [check_cached_effective_target_indexed vect_usdot_qi
{
8036 expr
{ [istarget aarch64
*-*-*]
8037 ||
[istarget arm
*-*-*] }}]
8041 #
Return 1 if the target plus current options supports a vector
8042 # dot
-product of signed shorts
, 0 otherwise.
8044 # This won
't change for different subtargets so cache the result.
8046 proc check_effective_target_vect_sdot_hi { } {
8047 return [check_cached_effective_target_indexed vect_sdot_hi {
8048 expr { ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*])
8049 || [istarget ia64-*-*]
8050 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8051 || ([istarget mips*-*-*]
8052 && [et-is-effective-target mips_msa])
8053 || ([istarget riscv*-*-*]
8054 && [check_effective_target_riscv_v]) }}]
8057 # Return 1 if the target plus current options supports a vector
8058 # dot-product of unsigned shorts, 0 otherwise.
8060 # This won't change
for different subtargets so
cache the result.
8062 proc check_effective_target_vect_udot_hi
{ } {
8063 return [check_cached_effective_target_indexed vect_udot_hi
{
8064 expr
{ ([istarget powerpc
*-*-*] && ![istarget powerpc
-*-linux
*paired
*])
8065 ||
([istarget mips
*-*-*]
8066 && [et
-is
-effective
-target mips_msa
])
8067 ||
([istarget riscv
*-*-*]
8068 && [check_effective_target_riscv_v
]) }}]
8071 #
Return 1 if the target plus current options supports a vector
8072 # sad operation of unsigned chars
, 0 otherwise.
8074 # This won
't change for different subtargets so cache the result.
8076 proc check_effective_target_vect_usad_char { } {
8077 return [check_cached_effective_target_indexed vect_usad_char {
8078 expr { [istarget i?86-*-*]
8079 || [istarget x86_64-*-*]
8080 || ([istarget aarch64*-*-*]
8081 && ![check_effective_target_aarch64_sve])
8082 || ([istarget powerpc*-*-*]
8083 && [check_p9vector_hw_available])
8084 || ([istarget riscv*-*-*]
8085 && [check_effective_target_riscv_v]) }}]
8088 # Return 1 if the target plus current options supports both signed
8089 # and unsigned average operations on vectors of bytes.
8091 proc check_effective_target_vect_avg_qi {} {
8092 return [expr { ([istarget aarch64*-*-*]
8093 && ![check_effective_target_aarch64_sve1_only])
8094 || ([istarget riscv*-*-*]
8095 && [check_effective_target_riscv_v]) }]
8098 # Return 1 if the target plus current options supports both signed
8099 # and unsigned multiply-high-with-round-and-scale operations
8100 # on vectors of half-words.
8102 proc check_effective_target_vect_mulhrs_hi {} {
8103 return [expr { [istarget aarch64*-*-*]
8104 && [check_effective_target_aarch64_sve2] }]
8107 # Return 1 if the target plus current options supports signed division
8108 # by power-of-2 operations on vectors of 4-byte integers.
8110 proc check_effective_target_vect_sdiv_pow2_si {} {
8111 return [expr { ([istarget aarch64*-*-*]
8112 && [check_effective_target_aarch64_sve]) }]
8115 # Return 1 if the target plus current options supports a vector
8116 # demotion (packing) of shorts (to chars) and ints (to shorts)
8117 # using modulo arithmetic, 0 otherwise.
8119 # This won't change
for different subtargets so
cache the result.
8121 proc check_effective_target_vect_pack_trunc
{ } {
8122 return [check_cached_effective_target_indexed vect_pack_trunc
{
8123 expr
{ ([istarget powerpc
*-*-*] && ![istarget powerpc
-*-linux
*paired
*])
8124 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
8125 ||
[istarget aarch64
*-*-*]
8126 ||
([istarget arm
*-*-*] && [check_effective_target_arm_neon_ok
]
8127 && [check_effective_target_arm_little_endian
])
8128 ||
([istarget mips
*-*-*]
8129 && [et
-is
-effective
-target mips_msa
])
8130 ||
([istarget s390
*-*-*]
8131 && [check_effective_target_s390_vx
])
8132 ||
[istarget amdgcn
*-*-*]
8133 ||
([istarget riscv
*-*-*]
8134 && [check_effective_target_riscv_v
]) }}]
8137 #
Return 1 if the target plus current options supports a vector
8138 # promotion
(unpacking
) of chars
(to shorts
) and shorts
(to ints
), 0 otherwise.
8140 # This won
't change for different subtargets so cache the result.
8142 proc check_effective_target_vect_unpack { } {
8143 return [check_cached_effective_target_indexed vect_unpack {
8144 expr { ([istarget powerpc*-*-*] && ![istarget powerpc-*paired*])
8145 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8146 || [istarget ia64-*-*]
8147 || [istarget aarch64*-*-*]
8148 || ([istarget mips*-*-*]
8149 && [et-is-effective-target mips_msa])
8150 || ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok]
8151 && [check_effective_target_arm_little_endian])
8152 || ([istarget s390*-*-*]
8153 && [check_effective_target_s390_vx])
8154 || [istarget amdgcn*-*-*]
8155 || ([istarget riscv*-*-*]
8156 && [check_effective_target_riscv_v]) }}]
8159 # Return 1 if the target plus current options does not guarantee
8160 # that its STACK_BOUNDARY is >= the reguired vector alignment.
8162 # This won't change
for different subtargets so
cache the result.
8164 proc check_effective_target_unaligned_stack
{ } {
8165 return [check_cached_effective_target_indexed unaligned_stack
{ expr
0 }]
8168 #
Return 1 if the target plus current options does not support a vector
8169 # alignment mechanism
, 0 otherwise.
8171 # This won
't change for different subtargets so cache the result.
8173 proc check_effective_target_vect_no_align { } {
8174 return [check_cached_effective_target_indexed vect_no_align {
8175 expr { [istarget mipsisa64*-*-*]
8176 || [istarget mips-sde-elf]
8177 || [istarget sparc*-*-*]
8178 || [istarget ia64-*-*]
8179 || [check_effective_target_arm_vect_no_misalign]
8180 || ([istarget powerpc*-*-*] && [check_p8vector_hw_available])
8181 || ([istarget mips*-*-*]
8182 && [et-is-effective-target mips_loongson_mmi]) }}]
8185 # Return 1 if the target supports a vector misalign access, 0 otherwise.
8187 # This won't change
for different subtargets so
cache the result.
8189 proc check_effective_target_vect_hw_misalign
{ } {
8190 return [check_cached_effective_target_indexed vect_hw_misalign
{
8191 if { [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
8192 ||
([istarget powerpc
*-*-*] && [check_p8vector_hw_available
])
8193 ||
[istarget aarch64
*-*-*]
8194 ||
([istarget mips
*-*-*] && [et
-is
-effective
-target mips_msa
])
8195 ||
([istarget s390
*-*-*]
8196 && [check_effective_target_s390_vx
])
8197 ||
([istarget riscv
*-*-*]) } {
8200 if { [istarget arm
*-*-*]
8201 && ![check_effective_target_arm_vect_no_misalign
] } {
8209 #
Return 1 if arrays are aligned to the vector alignment
8210 # boundary
, 0 otherwise.
8212 proc check_effective_target_vect_aligned_arrays
{ } {
8213 set et_vect_aligned_arrays
0
8214 if { (([istarget i?
86-*-*] ||
[istarget x86_64
-*-*])
8215 && !([is
-effective
-target ia32
]
8216 ||
([check_avx_available
] && ![check_prefer_avx128
]))) } {
8217 set et_vect_aligned_arrays
1
8220 verbose
"check_effective_target_vect_aligned_arrays:\
8221 returning $et_vect_aligned_arrays
" 2
8222 return $et_vect_aligned_arrays
8225 #
Return 1 if the biggest alignment required by target is
1 * BITS_PER_UNIT.
8226 # In such case the target does not impose
any alignment constraints.
8228 proc check_effective_target_no_alignment_constraints
{ } {
8229 return [check_runtime_nocache no_alignment_constraints
{
8233 return __BIGGEST_ALIGNMENT__
== 1 ?
0 : 1;
8238 #
Return 1 if types of size
32 bit or less are naturally aligned
8239 #
(aligned to their type
-size
), 0 otherwise.
8241 # This won
't change for different subtargets so cache the result.
8243 proc check_effective_target_natural_alignment_32 { } {
8244 # FIXME: 32bit powerpc: guaranteed only if MASK_ALIGN_NATURAL/POWER.
8245 # FIXME: m68k has -malign-int
8246 return [check_cached_effective_target_indexed natural_alignment_32 {
8247 if { ([istarget *-*-darwin*] && [is-effective-target lp64])
8248 || [istarget avr-*-*]
8249 || [istarget m68k-*-linux*]
8250 || [istarget pru-*-*]
8251 || [istarget stormy16-*-*]
8252 || [istarget rl78-*-*]
8253 || [istarget pdp11-*-*]
8254 || [istarget msp430-*-*]
8255 || [istarget m32c-*-*]
8256 || [istarget cris-*-*] } {
8264 # Return 1 if types of size 64 bit or less are naturally aligned (aligned to their
8265 # type-size), 0 otherwise.
8267 # This won't change
for different subtargets so
cache the result.
8269 proc check_effective_target_natural_alignment_64
{ } {
8270 return [check_cached_effective_target_indexed natural_alignment_64
{
8271 expr
{ [is
-effective
-target natural_alignment_32
]
8272 && [is
-effective
-target lp64
] && ![istarget
*-*-darwin
*] }
8276 #
Return 1 if all vector types are naturally aligned
(aligned to their
8277 # type
-size
), 0 otherwise.
8279 proc check_effective_target_vect_natural_alignment
{ } {
8280 set et_vect_natural_alignment
1
8281 if { [check_effective_target_arm_eabi
]
8282 ||
[istarget nvptx
-*-*]
8283 ||
[istarget s390
*-*-*]
8284 ||
[istarget amdgcn
-*-*] } {
8285 set et_vect_natural_alignment
0
8287 verbose
"check_effective_target_vect_natural_alignment:\
8288 returning $et_vect_natural_alignment
" 2
8289 return $et_vect_natural_alignment
8292 #
Return true
if the target supports the check_raw_ptrs and check_war_ptrs
8293 # optabs
on vectors.
8295 proc check_effective_target_vect_check_ptrs
{ } {
8296 return [check_effective_target_aarch64_sve2
]
8299 #
Return true
if fully
-masked loops are supported.
8301 proc check_effective_target_vect_fully_masked
{ } {
8302 return [expr
{ [check_effective_target_aarch64_sve
]
8303 ||
[istarget amdgcn
*-*-*]
8304 ||
[check_effective_target_riscv_v
] }]
8307 #
Return true
if the target supports the @code
{len_load
} and
8308 # @code
{len_store
} optabs.
8310 proc check_effective_target_vect_len_load_store
{ } {
8311 return [expr
{ [check_effective_target_has_arch_pwr9
]
8312 ||
[check_effective_target_s390_vx
]
8313 ||
[check_effective_target_riscv_v
] }]
8316 #
Return the value of parameter vect
-partial
-vector
-usage specified
for
8317 # target by checking the output of
"-Q --help=params". Return zero if
8318 # the desirable pattern isn
't found.
8320 proc check_vect_partial_vector_usage { } {
8323 return [check_cached_effective_target vect_partial_vector_usage {
8324 set result [check_compile vect_partial_vector_usage assembly {
8326 } "-Q --help=params" ]
8328 # Get compiler emitted messages and delete generated file.
8329 set lines [lindex $result 0]
8330 set output [lindex $result 1]
8331 remote_file build delete $output
8333 set pattern {=vect-partial-vector-usage=<0,2>\s+([0-2])}
8334 # Capture the usage value to val, set it to zero if not found.
8335 if { ![regexp $pattern $lines whole val] } then {
8343 # Return true if the target supports loop vectorization with partial vectors
8344 # and @code{vect-partial-vector-usage} is set to 1.
8346 proc check_effective_target_vect_partial_vectors_usage_1 { } {
8347 return [expr { ([check_effective_target_vect_fully_masked]
8348 || [check_effective_target_vect_len_load_store])
8349 && [check_vect_partial_vector_usage] == 1 }]
8352 # Return true if the target supports loop vectorization with partial vectors
8353 # and @code{vect-partial-vector-usage} is set to 2.
8355 proc check_effective_target_vect_partial_vectors_usage_2 { } {
8356 return [expr { ([check_effective_target_vect_fully_masked]
8357 || [check_effective_target_vect_len_load_store])
8358 && [check_vect_partial_vector_usage] == 2 }]
8361 # Return true if the target supports loop vectorization with partial vectors
8362 # and @code{vect-partial-vector-usage} is nonzero.
8364 proc check_effective_target_vect_partial_vectors { } {
8365 return [expr { ([check_effective_target_vect_fully_masked]
8366 || [check_effective_target_vect_len_load_store])
8367 && [check_vect_partial_vector_usage] != 0 }]
8370 # Return 1 if the target doesn't prefer
any alignment beyond element
8371 # alignment during vectorization.
8373 proc check_effective_target_vect_element_align_preferred
{ } {
8374 return [expr
{ ([check_effective_target_aarch64_sve
]
8375 && [check_effective_target_vect_variable_length
])
8376 ||
[check_effective_target_riscv_v
] }]
8379 #
Return true
if vectorization of v2qi
/v4qi
/v8qi
/v16qi
/v2hi store is enabed.
8380 #
Return zero
if the desirable pattern isn
't found.
8381 # It's used by Warray
-bounds
/Wstringop
-overflow testcases which are
8382 # regressed by O2 vectorization
, refer to PR102697
/PR102462
/PR102706
8383 proc check_vect_slp_store_usage
{ pattern macro
} {
8386 set result
[check_compile slp_aligned_store_usage assembly
{
8387 extern void sink
(void
* );
8388 #
define Ac8
(AC8
){ 0, 1, 2, 3, 4, 5, 6, 7 }
8389 #
define Ac16
(AC16
){ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }
8391 typedef struct AC16
{ char a
[16]; } AC16
;
8392 extern char a16
[16];
8399 typedef struct AC8
{ char a
[8]; } AC8
;
8413 extern void sink
(void
*);
8417 struct A1 a
= { 0, { } };
8434 #
define Ac4
(AC4
){ 0, 1, 2, 3 }
8435 typedef struct AC4
{ char a
[4]; } AC4
;
8483 *(short
*) (b
+ 2) = 1;
8492 foo4_2
(struct Ax
*p
)
8498 struct A
{ int i
; };
8499 struct B
{ int j
; struct A a
[4]; };
8506 char cbuf2
[2 * sizeof
(struct C
)] = { };
8510 struct C
*p
= (struct C
*)&cbuf2
;
8517 struct A
{ int i
; };
8518 struct B
{ int j
; struct A a
[2]; };
8525 char cbuf2
[2 * sizeof
(struct C
)] = { };
8529 struct C
*p
= (struct C
*)&cbuf2
;
8535 } "-O2 -fopt-info-all -D$macro" ]
8537 #
Get compiler emitted messages and
delete generated file.
8538 set lines
[lindex $result
0]
8539 set output
[lindex $result
1]
8540 remote_file build
delete $output
8542 # Check pattern exits in lines
, set it to zero
if not found.
8543 if { [regexp $pattern $lines
] } then {
8550 #
Return the true
if target support vectorization of
2-byte char stores
8551 # with
2-byte aligned address at plain O2.
8552 # NB
: This target should be removed after real issues are fixed
for
8553 #
-Wstringop
-overflow with O2 vect. Be careful
if you want to reuse
8554 # this target since tests in check_vect_slp_store_usage
8555 # is the exact match of relative testcases
8556 proc check_effective_target_vect_slp_v2qi_store_align
{ } {
8557 set pattern
{add new stmt
: MEM
<vector\
(2\
) char
>}
8558 set macro
"TEST_V2QI"
8559 return [check_cached_effective_target vect_slp_v2qi_store_align
{
8560 expr
[check_vect_slp_store_usage $pattern $macro
] }]
8563 #
Return the true
if target support vectorization of
2-byte char stores
8564 # with unaligned address at plain O2.
8565 proc check_effective_target_vect_slp_v2qi_store_unalign
{ } {
8566 set pattern
{add new stmt
: MEM
<vector\
(2\
) char
>}
8567 set macro
"TEST_V2QI_2"
8568 return [check_cached_effective_target vect_slp_v2qi_store_unalign
{
8569 expr
[check_vect_slp_store_usage $pattern $macro
] }]
8572 #
Return the true
if target support vectorization of
4-byte char stores
8573 # with
4-byte aligned address at plain O2.
8574 # NB
: This target should be removed after real issues are fixed
for
8575 #
-Wstringop
-overflow with O2 vect. Be careful
if you want to reuse
8576 # this target since tests in check_vect_slp_store_usage
8577 # is the exact match of relative testcases
8578 proc check_effective_target_vect_slp_v4qi_store_align
{ } {
8579 set pattern
{add new stmt
: MEM
<vector\
(4\
) char
>}
8580 set macro
"TEST_V4QI"
8581 return [check_cached_effective_target vect_slp_v4qi_store_align
{
8582 expr
[check_vect_slp_store_usage $pattern $macro
] }]
8585 #
Return the true
if target support vectorization of
4-byte char stores
8586 # with unaligned address at plain O2.
8587 proc check_effective_target_vect_slp_v4qi_store_unalign
{ } {
8588 set pattern
{add new stmt
: MEM
<vector\
(4\
) char
>}
8589 set macro
"TEST_V4QI_2"
8590 return [check_cached_effective_target vect_slp_v4qi_store_unalign
{
8591 expr
[check_vect_slp_store_usage $pattern $macro
] }]
8594 #
Return the true
if target support block
move for
8595 #
8-byte aligned
4-byte size struct initialization.
8596 proc check_effective_target_struct_4char_block_move
{ } {
8597 set pattern
{not vectorized
: more than one data ref in stmt
:}
8598 set macro
"TEST_V4QI_3"
8599 return [check_cached_effective_target struct_4char_block_move
{
8600 expr
[check_vect_slp_store_usage $pattern $macro
] }]
8603 #
Return the true
if target support vectorization of
4-byte char stores
8604 # with unaligned address or store them with a constant pool at plain O2.
8605 proc check_effective_target_vect_slp_v4qi_store_unalign_1
{ } {
8606 set pattern
{add new stmt
: MEM
<vector\
(4\
) char
>}
8607 set macro
"TEST_V4QI_3"
8608 return [check_cached_effective_target vect_slp_v4qi_store_unalign_1
{
8609 expr
{ [check_vect_slp_store_usage $pattern $macro
]
8610 ||
[check_effective_target_struct_4char_block_move
] } }]
8613 #
Return the true
if target support block
move for
8614 #
8-byte aligned
8-byte size struct initialization.
8615 proc check_effective_target_struct_8char_block_move
{ } {
8616 set pattern
{not vectorized
: more than one data ref in stmt
:}
8617 set macro
"TEST_V8QI"
8618 return [check_cached_effective_target struct_8char_block_move
{
8619 expr
[check_vect_slp_store_usage $pattern $macro
] }]
8622 #
Return the true
if target support vectorization of
8-byte char stores
8623 # with unaligned address or store them with a constant pool at plain O2.
8624 # NB
: This target should be removed after real issues are fixed
for
8625 #
-Wstringop
-overflow with O2 vect. Be careful
if you want to reuse
8626 # this target since tests in check_vect_slp_store_usage
8627 # is the exact match of relative testcases
8628 proc check_effective_target_vect_slp_v8qi_store_unalign_1
{ } {
8629 set pattern
{add new stmt
: MEM
<vector\
(8\
) char
>}
8630 set macro
"TEST_V8QI"
8631 return [check_cached_effective_target vect_slp_v8qi_store_unalign_1
{
8632 expr
{ [check_vect_slp_store_usage $pattern $macro
]
8633 ||
[check_effective_target_struct_8char_block_move
] } }]
8636 #
Return the true
if target support block
move for
8637 #
8-byte aligned
16-byte size struct initialization.
8638 proc check_effective_target_struct_16char_block_move
{ } {
8639 set pattern
{not vectorized
: more than one data ref in stmt
:}
8640 set macro
"TEST_V16QI"
8641 return [check_cached_effective_target struct_16char_block_move
{
8642 expr
[check_vect_slp_store_usage $pattern $macro
] }]
8645 #
Return the true
if target support vectorization of
16-byte char stores
8646 # with unaligned address or store them with a constant pool at plain O2.
8647 # NB
: This target should be removed after real issues are fixed
for
8648 #
-Wstringop
-overflow with O2 vect. Be careful
if you want to reuse
8649 # this target since tests in check_vect_slp_store_usage
8650 # is the exact match of relative testcases
8651 proc check_effective_target_vect_slp_v16qi_store_unalign_1
{ } {
8652 set pattern
{add new stmt
: MEM
<vector\
(16\
) char
>}
8653 set macro
"TEST_V16QI"
8654 return [check_cached_effective_target vect_slp_v16qi_store_unalign_1
{
8655 expr
{ [check_vect_slp_store_usage $pattern $macro
]
8656 ||
[check_effective_target_struct_16char_block_move
] } }]
8659 #
Return the true
if target support vectorization of
4-byte short stores
8660 # with unaligned address at plain O2.
8661 # NB
: This target should be removed after real issues are fixed
for
8662 #
-Wstringop
-overflow with O2 vect. Be careful
if you want to reuse
8663 # this target since tests in check_vect_slp_store_usage
8664 # is the exact match of relative testcases
8665 proc check_effective_target_vect_slp_v2hi_store_unalign
{ } {
8666 set pattern
{add new stmt
: MEM
<vector\
(2\
) short
int>}
8667 set macro
"TEST_V2HI"
8668 return [check_cached_effective_target vect_slp_v2hi_store_unalign
{
8669 expr
[check_vect_slp_store_usage $pattern $macro
] }]
8672 #
Return the true
if target support vectorization of
4-byte short stores
8673 # with
4-byte aligned address at plain O2.
8674 proc check_effective_target_vect_slp_v2hi_store_align
{ } {
8675 set pattern
{add new stmt
: MEM
<vector\
(2\
) short
int>}
8676 set macro
"TEST_V2HI_2"
8677 return [check_cached_effective_target vect_slp_v2hi_store_align
{
8678 expr
[check_vect_slp_store_usage $pattern $macro
] }]
8681 #
Return the true
if target support vectorization of
8-byte short stores
8682 # with unaligned address at plain O2.
8683 # NB
: This target should be removed after real issues are fixed
for
8684 #
-Wstringop
-overflow with O2 vect. Be careful
if you want to reuse
8685 # this target since tests in check_vect_slp_store_usage
8686 # is the exact match of relative testcases
8687 proc check_effective_target_vect_slp_v4hi_store_unalign
{ } {
8688 set pattern
{add new stmt
: MEM
<vector\
(4\
) short
int>}
8689 set macro
"TEST_V4HI"
8690 return [check_cached_effective_target vect_slp_v4hi_store_unalign
{
8691 expr
[check_vect_slp_store_usage $pattern $macro
] }]
8694 #
Return the true
if target support vectorization of
8-byte
int stores
8695 # with
8-byte aligned address at plain O2.
8696 # NB
: This target should be removed after real issues are fixed
for
8697 #
-Wstringop
-overflow with O2 vect. Be careful
if you want to reuse
8698 # this target since tests in check_vect_slp_store_usage
8699 # is the exact match of relative testcases
8700 proc check_effective_target_vect_slp_v2si_store_align
{ } {
8701 set pattern
{add new stmt
: MEM
<vector\
(2\
) int>}
8702 set macro
"TEST_V2SI"
8703 return [check_cached_effective_target vect_slp_v2si_store_align
{
8704 expr
[check_vect_slp_store_usage $pattern $macro
] }]
8707 #
Return the true
if target support vectorization of
16-byte
int stores
8708 # with unaligned address at plain O2.
8709 # NB
: This target should be removed after real issues are fixed
for
8710 #
-Wstringop
-overflow with O2 vect. Be careful
if you want to reuse
8711 # this target since tests in check_vect_slp_store_usage
8712 # is the exact match of relative testcases
8713 proc check_effective_target_vect_slp_v4si_store_unalign
{ } {
8714 set pattern
{add new stmt
: MEM
<vector\
(4\
) int>}
8715 set macro
"TEST_V4SI"
8716 return [check_cached_effective_target vect_slp_v4si_store_unalign
{
8717 expr
[check_vect_slp_store_usage $pattern $macro
] }]
8720 #
Return 1 if we can align stack data to the preferred vector alignment.
8722 proc check_effective_target_vect_align_stack_vars
{ } {
8723 if { [check_effective_target_aarch64_sve
] } {
8724 return [check_effective_target_vect_variable_length
]
8729 #
Return 1 if vector alignment
(for types of size
32 bit or less
) is reachable
, 0 otherwise.
8731 proc check_effective_target_vector_alignment_reachable
{ } {
8732 set et_vector_alignment_reachable
0
8733 if { [check_effective_target_vect_aligned_arrays
]
8734 ||
[check_effective_target_natural_alignment_32
] } {
8735 set et_vector_alignment_reachable
1
8737 verbose
"check_effective_target_vector_alignment_reachable:\
8738 returning $et_vector_alignment_reachable
" 2
8739 return $et_vector_alignment_reachable
8742 #
Return 1 if vector alignment
for 64 bit is reachable
, 0 otherwise.
8744 proc check_effective_target_vector_alignment_reachable_for_64bit
{ } {
8745 set et_vector_alignment_reachable_for_64bit
0
8746 if { [check_effective_target_vect_aligned_arrays
]
8747 ||
[check_effective_target_natural_alignment_64
] } {
8748 set et_vector_alignment_reachable_for_64bit
1
8750 verbose
"check_effective_target_vector_alignment_reachable_for_64bit:\
8751 returning $et_vector_alignment_reachable_for_64bit
" 2
8752 return $et_vector_alignment_reachable_for_64bit
8755 #
Return 1 if the target only requires element alignment
for vector accesses
8757 proc check_effective_target_vect_element_align
{ } {
8758 return [check_cached_effective_target_indexed vect_element_align
{
8759 expr
{ ([istarget arm
*-*-*]
8760 && ![check_effective_target_arm_vect_no_misalign
])
8761 ||
[check_effective_target_vect_hw_misalign
]
8762 ||
[istarget amdgcn
-*-*] }}]
8765 #
Return 1 if we expect to see unaligned accesses in at least some
8768 proc check_effective_target_vect_unaligned_possible
{ } {
8769 return [expr
{ ![check_effective_target_vect_element_align_preferred
]
8770 && (![check_effective_target_vect_no_align
]
8771 ||
[check_effective_target_vect_hw_misalign
]) }]
8774 #
Return 1 if the target supports vector LOAD_LANES operations
, 0 otherwise.
8776 proc check_effective_target_vect_load_lanes
{ } {
8777 # We don
't support load_lanes correctly on big-endian arm.
8778 return [check_cached_effective_target vect_load_lanes {
8779 expr { ([check_effective_target_arm_little_endian]
8780 && [check_effective_target_arm_neon_ok])
8781 || [istarget aarch64*-*-*]
8782 || [istarget riscv*-*-*] }}]
8785 # Return 1 if the target supports vector masked loads.
8787 proc check_effective_target_vect_masked_load { } {
8788 return [expr { [check_avx_available]
8789 || [check_effective_target_aarch64_sve]
8790 || [istarget amdgcn*-*-*]
8791 || [check_effective_target_riscv_v] } ]
8794 # Return 1 if the target supports vector masked stores.
8796 proc check_effective_target_vect_masked_store { } {
8797 return [expr { [check_avx_available]
8798 || [check_effective_target_aarch64_sve]
8799 || [istarget amdgcn*-*-*]
8800 || [check_effective_target_riscv_v] }]
8803 # Return 1 if the target supports vector gather loads via internal functions.
8805 proc check_effective_target_vect_gather_load_ifn { } {
8806 return [expr { [check_effective_target_aarch64_sve]
8807 || [istarget amdgcn*-*-*]
8808 || [check_effective_target_riscv_v] }]
8811 # Return 1 if the target supports vector scatter stores.
8813 proc check_effective_target_vect_scatter_store { } {
8814 return [expr { [check_effective_target_aarch64_sve]
8815 || [istarget amdgcn*-*-*]
8816 || [check_effective_target_riscv_v] }]
8819 # Return 1 if the target supports vector conditional operations, 0 otherwise.
8821 proc check_effective_target_vect_condition { } {
8822 return [check_cached_effective_target_indexed vect_condition {
8823 expr { [istarget aarch64*-*-*]
8824 || [istarget powerpc*-*-*]
8825 || [istarget ia64-*-*]
8826 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8827 || ([istarget mips*-*-*]
8828 && [et-is-effective-target mips_msa])
8829 || ([istarget arm*-*-*]
8830 && [check_effective_target_arm_neon_ok])
8831 || ([istarget s390*-*-*]
8832 && [check_effective_target_s390_vx])
8833 || [istarget amdgcn-*-*]
8834 || ([istarget riscv*-*-*]
8835 && [check_effective_target_riscv_v]) }}]
8838 # Return 1 if the target supports vector conditional operations where
8839 # the comparison has different type from the lhs, 0 otherwise.
8841 proc check_effective_target_vect_cond_mixed { } {
8842 return [check_cached_effective_target_indexed vect_cond_mixed {
8843 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
8844 || [istarget aarch64*-*-*]
8845 || [istarget powerpc*-*-*]
8846 || ([istarget arm*-*-*]
8847 && [check_effective_target_arm_neon_ok])
8848 || ([istarget mips*-*-*]
8849 && [et-is-effective-target mips_msa])
8850 || ([istarget s390*-*-*]
8851 && [check_effective_target_s390_vx])
8852 || [istarget amdgcn-*-*]
8853 || ([istarget riscv*-*-*]
8854 && [check_effective_target_riscv_v]) }}]
8857 # Return 1 if the target supports vector char multiplication, 0 otherwise.
8859 proc check_effective_target_vect_char_mult { } {
8860 return [check_cached_effective_target_indexed vect_char_mult {
8861 expr { [istarget aarch64*-*-*]
8862 || [istarget ia64-*-*]
8863 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8864 || [check_effective_target_arm32]
8865 || [check_effective_target_powerpc_altivec]
8866 || ([istarget mips*-*-*]
8867 && [et-is-effective-target mips_msa])
8868 || ([istarget s390*-*-*]
8869 && [check_effective_target_s390_vx])
8870 || [istarget amdgcn-*-*]
8871 || ([istarget riscv*-*-*]
8872 && [check_effective_target_riscv_v]) }}]
8875 # Return 1 if the target supports vector short multiplication, 0 otherwise.
8877 proc check_effective_target_vect_short_mult { } {
8878 return [check_cached_effective_target_indexed vect_short_mult {
8879 expr { [istarget ia64-*-*]
8880 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8881 || [istarget powerpc*-*-*]
8882 || [istarget aarch64*-*-*]
8883 || [check_effective_target_arm32]
8884 || ([istarget mips*-*-*]
8885 && ([et-is-effective-target mips_msa]
8886 || [et-is-effective-target mips_loongson_mmi]))
8887 || ([istarget s390*-*-*]
8888 && [check_effective_target_s390_vx])
8889 || [istarget amdgcn-*-*]
8890 || ([istarget riscv*-*-*]
8891 && [check_effective_target_riscv_v]) }}]
8894 # Return 1 if the target supports vector int multiplication, 0 otherwise.
8896 proc check_effective_target_vect_int_mult { } {
8897 return [check_cached_effective_target_indexed vect_int_mult {
8898 expr { ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*])
8899 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8900 || [istarget ia64-*-*]
8901 || [istarget aarch64*-*-*]
8902 || ([istarget mips*-*-*]
8903 && [et-is-effective-target mips_msa])
8904 || [check_effective_target_arm32]
8905 || ([istarget s390*-*-*]
8906 && [check_effective_target_s390_vx])
8907 || [istarget amdgcn-*-*]
8908 || ([istarget riscv*-*-*]
8909 && [check_effective_target_riscv_v]) }}]
8912 # Return 1 if the target supports 64 bit hardware vector
8913 # multiplication of long operands with a long result, 0 otherwise.
8915 # This can change for different subtargets so do not cache the result.
8917 proc check_effective_target_vect_long_mult { } {
8918 if { [istarget i?86-*-*] || [istarget x86_64-*-*]
8919 || (([istarget powerpc*-*-*]
8920 && ![istarget powerpc-*-linux*paired*])
8921 && [check_effective_target_ilp32])
8922 || [is-effective-target arm_neon]
8923 || ([istarget sparc*-*-*] && [check_effective_target_ilp32])
8924 || [istarget aarch64*-*-*]
8925 || ([istarget mips*-*-*]
8926 && [et-is-effective-target mips_msa])
8927 || ([istarget riscv*-*-*]
8928 && [check_effective_target_riscv_v]) } {
8934 verbose "check_effective_target_vect_long_mult: returning $answer" 2
8938 # Return 1 if the target supports vector int modulus, 0 otherwise.
8940 proc check_effective_target_vect_int_mod { } {
8941 return [check_cached_effective_target_indexed vect_int_mod {
8942 expr { ([istarget powerpc*-*-*]
8943 && [check_effective_target_has_arch_pwr10])
8944 || [istarget amdgcn-*-*]
8945 || ([istarget loongarch*-*-*]
8946 && [check_effective_target_loongarch_sx])
8947 || ([istarget riscv*-*-*]
8948 && [check_effective_target_riscv_v]) }}]
8951 # Return 1 if the target supports vector even/odd elements extraction, 0 otherwise.
8953 proc check_effective_target_vect_extract_even_odd { } {
8954 return [check_cached_effective_target_indexed extract_even_odd {
8955 expr { [istarget aarch64*-*-*]
8956 || [istarget powerpc*-*-*]
8957 || [is-effective-target arm_neon]
8958 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8959 || [istarget ia64-*-*]
8960 || ([istarget mips*-*-*]
8961 && ([et-is-effective-target mips_msa]
8962 || [et-is-effective-target mpaired_single]))
8963 || ([istarget s390*-*-*]
8964 && [check_effective_target_s390_vx])
8965 || ([istarget riscv*-*-*]
8966 && [check_effective_target_riscv_v]) }}]
8969 # Return 1 if the target supports vector interleaving, 0 otherwise.
8971 proc check_effective_target_vect_interleave { } {
8972 return [check_cached_effective_target_indexed vect_interleave {
8973 expr { [istarget aarch64*-*-*]
8974 || [istarget powerpc*-*-*]
8975 || [is-effective-target arm_neon]
8976 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8977 || [istarget ia64-*-*]
8978 || ([istarget mips*-*-*]
8979 && ([et-is-effective-target mpaired_single]
8980 || [et-is-effective-target mips_msa]))
8981 || ([istarget s390*-*-*]
8982 && [check_effective_target_s390_vx])
8983 || ([istarget riscv*-*-*]
8984 && [check_effective_target_riscv_v]) }}]
8987 foreach N {2 3 4 5 6 7 8} {
8988 eval [string map [list N $N] {
8989 # Return 1 if the target supports 2-vector interleaving
8990 proc check_effective_target_vect_stridedN { } {
8991 return [check_cached_effective_target_indexed vect_stridedN {
8993 && [check_effective_target_vect_interleave]
8994 && [check_effective_target_vect_extract_even_odd] } {
8997 if { ([istarget arm*-*-*]
8998 || [istarget aarch64*-*-*]) && N >= 2 && N <= 4 } {
9001 if { ([istarget riscv*-*-*]) && N >= 2 && N <= 8 } {
9004 if [check_effective_target_vect_fully_masked] {
9013 # Return the list of vector sizes (in bits) that each target supports.
9014 # A vector length of "0" indicates variable-length vectors.
9016 proc available_vector_sizes { } {
9018 if { [istarget aarch64*-*-*] } {
9019 if { [check_effective_target_aarch64_sve] } {
9020 lappend result [aarch64_sve_bits]
9022 lappend result 128 64
9023 } elseif { [istarget arm*-*-*]
9024 && [check_effective_target_arm_neon_ok] } {
9025 lappend result 128 64
9026 } elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
9027 if { [check_avx_available] && ![check_prefer_avx128] } {
9031 if { ![is-effective-target ia32] } {
9035 } elseif { [istarget sparc*-*-*] } {
9037 } elseif { [istarget amdgcn*-*-*] } {
9038 # 6 different lane counts, and 4 element sizes
9039 lappend result 4096 2048 1024 512 256 128 64 32 16 8 4 2
9040 } elseif { [istarget riscv*-*-*] } {
9041 if { [check_effective_target_riscv_v] } {
9042 lappend result 0 32 64 128 256 512 1024
9046 # The traditional default asumption.
9052 # Return 1 if the target supports multiple vector sizes
9054 proc check_effective_target_vect_multiple_sizes { } {
9055 return [expr { [llength [available_vector_sizes]] > 1 }]
9058 # Return true if variable-length vectors are supported.
9060 proc check_effective_target_vect_variable_length { } {
9061 return [expr { [lindex [available_vector_sizes] 0] == 0 }]
9064 # Return 1 if the target supports vectors of 1024 bits.
9066 proc check_effective_target_vect1024 { } {
9067 return [expr { [lsearch -exact [available_vector_sizes] 1024] >= 0 }]
9070 # Return 1 if the target supports vectors of 512 bits.
9072 proc check_effective_target_vect512 { } {
9073 return [expr { [lsearch -exact [available_vector_sizes] 512] >= 0 }]
9076 # Return 1 if the target supports vectors of 256 bits.
9078 proc check_effective_target_vect256 { } {
9079 return [expr { [lsearch -exact [available_vector_sizes] 256] >= 0 }]
9082 # Return 1 if the target supports vectors of 128 bits.
9084 proc check_effective_target_vect128 { } {
9085 return [expr { [lsearch -exact [available_vector_sizes] 128] >= 0 }]
9088 # Return 1 if the target supports vectors of 64 bits.
9090 proc check_effective_target_vect64 { } {
9091 return [expr { [lsearch -exact [available_vector_sizes] 64] >= 0 }]
9094 # Return 1 if the target supports vectors of 32 bits.
9096 proc check_effective_target_vect32 { } {
9097 return [expr { [lsearch -exact [available_vector_sizes] 32] >= 0 }]
9100 # Return 1 if the target supports vector copysignf calls.
9102 proc check_effective_target_vect_call_copysignf { } {
9103 return [check_cached_effective_target_indexed vect_call_copysignf {
9104 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
9105 || [istarget powerpc*-*-*]
9106 || [istarget aarch64*-*-*]
9107 || [istarget amdgcn-*-*]
9108 || ([istarget riscv*-*-*]
9109 && [check_effective_target_riscv_v]) }}]
9112 # Return 1 if the target supports hardware square root instructions.
9114 proc check_effective_target_sqrt_insn { } {
9115 return [check_cached_effective_target sqrt_insn {
9116 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
9117 || [check_effective_target_powerpc_sqrt]
9118 || [istarget aarch64*-*-*]
9119 || ([istarget arm*-*-*] && [check_effective_target_arm_vfp_ok])
9120 || ([istarget s390*-*-*]
9121 && [check_effective_target_s390_vx])
9122 || [istarget amdgcn-*-*] }}]
9125 # Return any additional options to enable square root intructions.
9127 proc add_options_for_sqrt_insn { flags } {
9128 if { [istarget amdgcn*-*-*] } {
9129 return "$flags -ffast-math"
9131 if { [istarget arm*-*-*] } {
9132 return [add_options_for_arm_vfp "$flags"]
9137 # Return 1 if the target supports vector sqrtf calls.
9139 proc check_effective_target_vect_call_sqrtf { } {
9140 return [check_cached_effective_target_indexed vect_call_sqrtf {
9141 expr { [istarget aarch64*-*-*]
9142 || [istarget i?86-*-*] || [istarget x86_64-*-*]
9143 || ([istarget powerpc*-*-*] && [check_vsx_hw_available])
9144 || ([istarget s390*-*-*]
9145 && [check_effective_target_s390_vx])
9146 || [istarget amdgcn-*-*]
9147 || ([istarget riscv*-*-*]
9148 && [check_effective_target_riscv_v]) }}]
9151 # Return 1 if the target supports vector lrint calls.
9153 proc check_effective_target_vect_call_lrint { } {
9154 set et_vect_call_lrint 0
9155 if { (([istarget i?86-*-*] || [istarget x86_64-*-*])
9156 && [check_effective_target_ilp32])
9157 || [istarget amdgcn-*-*] } {
9158 set et_vect_call_lrint 1
9161 verbose "check_effective_target_vect_call_lrint: returning $et_vect_call_lrint" 2
9162 return $et_vect_call_lrint
9165 # Return 1 if the target supports vector btrunc calls.
9167 proc check_effective_target_vect_call_btrunc { } {
9168 return [check_cached_effective_target_indexed vect_call_btrunc {
9169 expr { [istarget aarch64*-*-*]
9170 || [istarget amdgcn-*-*] }}]
9173 # Return 1 if the target supports vector btruncf calls.
9175 proc check_effective_target_vect_call_btruncf { } {
9176 return [check_cached_effective_target_indexed vect_call_btruncf {
9177 expr { [istarget aarch64*-*-*]
9178 || [istarget amdgcn-*-*] }}]
9181 # Return 1 if the target supports vector ceil calls.
9183 proc check_effective_target_vect_call_ceil { } {
9184 return [check_cached_effective_target_indexed vect_call_ceil {
9185 expr { [istarget aarch64*-*-*]
9186 || [istarget amdgcn-*-*] }}]
9189 # Return 1 if the target supports vector ceilf calls.
9191 proc check_effective_target_vect_call_ceilf { } {
9192 return [check_cached_effective_target_indexed vect_call_ceilf {
9193 expr { [istarget aarch64*-*-*]
9194 || [istarget amdgcn-*-*] }}]
9197 # Return 1 if the target supports vector floor calls.
9199 proc check_effective_target_vect_call_floor { } {
9200 return [check_cached_effective_target_indexed vect_call_floor {
9201 expr { [istarget aarch64*-*-*]
9202 || [istarget amdgcn-*-*] }}]
9205 # Return 1 if the target supports vector floorf calls.
9207 proc check_effective_target_vect_call_floorf { } {
9208 return [check_cached_effective_target_indexed vect_call_floorf {
9209 expr { [istarget aarch64*-*-*]
9210 || [istarget amdgcn-*-*] }}]
9213 # Return 1 if the target supports vector lceil calls.
9215 proc check_effective_target_vect_call_lceil { } {
9216 return [check_cached_effective_target_indexed vect_call_lceil {
9217 expr { [istarget aarch64*-*-*] }}]
9220 # Return 1 if the target supports vector lfloor calls.
9222 proc check_effective_target_vect_call_lfloor { } {
9223 return [check_cached_effective_target_indexed vect_call_lfloor {
9224 expr { [istarget aarch64*-*-*] }}]
9227 # Return 1 if the target supports vector nearbyint calls.
9229 proc check_effective_target_vect_call_nearbyint { } {
9230 return [check_cached_effective_target_indexed vect_call_nearbyint {
9231 expr { [istarget aarch64*-*-*] }}]
9234 # Return 1 if the target supports vector nearbyintf calls.
9236 proc check_effective_target_vect_call_nearbyintf { } {
9237 return [check_cached_effective_target_indexed vect_call_nearbyintf {
9238 expr { [istarget aarch64*-*-*] }}]
9241 # Return 1 if the target supports vector round calls.
9243 proc check_effective_target_vect_call_round { } {
9244 return [check_cached_effective_target_indexed vect_call_round {
9245 expr { [istarget aarch64*-*-*] }}]
9248 # Return 1 if the target supports vector roundf calls.
9250 proc check_effective_target_vect_call_roundf { } {
9251 return [check_cached_effective_target_indexed vect_call_roundf {
9252 expr { [istarget aarch64*-*-*] }}]
9255 # Return 1 if the target supports AND, OR and XOR reduction.
9257 proc check_effective_target_vect_logical_reduc { } {
9258 return [expr { [check_effective_target_aarch64_sve]
9259 || [istarget amdgcn-*-*]
9260 || [check_effective_target_riscv_v] }]
9263 # Return 1 if the target supports the fold_extract_last optab.
9265 proc check_effective_target_vect_fold_extract_last { } {
9266 return [expr { [check_effective_target_aarch64_sve]
9267 || [istarget amdgcn*-*-*]
9268 || [check_effective_target_riscv_v] }]
9271 # Return 1 if the target supports section-anchors
9273 proc check_effective_target_section_anchors { } {
9274 return [check_cached_effective_target section_anchors {
9275 expr { [istarget powerpc*-*-*]
9276 || [istarget arm*-*-*]
9277 || [istarget aarch64*-*-*] }}]
9280 # Return 1 if the target supports atomic operations on "int_128" values.
9282 proc check_effective_target_sync_int_128 { } {
9286 # Return 1 if the target supports atomic operations on "int_128" values
9287 # and can execute them.
9288 # This requires support for both compare-and-swap and true atomic loads.
9290 proc check_effective_target_sync_int_128_runtime { } {
9294 # Return 1 if the target supports atomic operations on "long long".
9296 # Note: 32bit x86 targets require -march=pentium in dg-options.
9297 # Note: 32bit s390 targets require -mzarch in dg-options.
9299 proc check_effective_target_sync_long_long { } {
9300 if { [istarget i?86-*-*] || [istarget x86_64-*-*]
9301 || [istarget aarch64*-*-*]
9302 || [istarget arm*-*-*]
9303 || [istarget alpha*-*-*]
9304 || ([istarget sparc*-*-*] && [check_effective_target_lp64])
9305 || [istarget s390*-*-*] } {
9312 # Return 1 if the target supports popcount on long.
9314 proc check_effective_target_popcountl { } {
9315 return [check_no_messages_and_pattern popcountl "!\\(call" rtl-expand {
9318 return __builtin_popcountl (b);
9323 # Return 1 if the target supports popcount on long long.
9325 proc check_effective_target_popcountll { } {
9326 return [check_no_messages_and_pattern popcountll "!\\(call" rtl-expand {
9327 int foo (long long b)
9329 return __builtin_popcountll (b);
9335 # Return 1 if the target supports popcount on int.
9337 proc check_effective_target_popcount { } {
9338 return [check_no_messages_and_pattern popcount "!\\(call" rtl-expand {
9341 return __builtin_popcount (b);
9346 # Return 1 if the target supports clz on int.
9348 proc check_effective_target_clz { } {
9349 return [check_no_messages_and_pattern clz "!\\(call" rtl-expand {
9352 return __builtin_clz (b);
9357 # Return 1 if the target supports clz on long.
9359 proc check_effective_target_clzl { } {
9360 return [check_no_messages_and_pattern clzl "!\\(call" rtl-expand {
9363 return __builtin_clzl (b);
9368 # Return 1 if the target supports clz on long long.
9370 proc check_effective_target_clzll { } {
9371 return [check_no_messages_and_pattern clzll "!\\(call" rtl-expand {
9372 int foo (long long b)
9374 return __builtin_clzll (b);
9379 # Return 1 if the target supports ctz on int.
9381 proc check_effective_target_ctz { } {
9382 return [check_no_messages_and_pattern ctz "!\\(call" rtl-expand {
9385 return __builtin_ctz (b);
9390 # Return 1 if the target supports ctz on long.
9392 proc check_effective_target_ctzl { } {
9393 return [check_no_messages_and_pattern ctzl "!\\(call" rtl-expand {
9396 return __builtin_ctzl (b);
9401 # Return 1 if the target supports ctz on long long.
9403 proc check_effective_target_ctzll { } {
9404 return [check_no_messages_and_pattern ctzll "!\\(call" rtl-expand {
9405 int foo (long long b)
9407 return __builtin_ctzll (b);
9412 # Return 1 if the target supports atomic operations on "long long"
9413 # and can execute them.
9415 # Note: 32bit x86 targets require -march=pentium in dg-options.
9417 proc check_effective_target_sync_long_long_runtime { } {
9418 if { (([istarget x86_64-*-*] || [istarget i?86-*-*])
9419 && [check_cached_effective_target sync_long_long_available {
9420 check_runtime_nocache sync_long_long_available {
9424 unsigned int eax, ebx, ecx, edx;
9425 if (__get_cpuid (1, &eax, &ebx, &ecx, &edx))
9426 return !(edx & bit_CMPXCHG8B);
9431 || [istarget aarch64*-*-*]
9432 || [istarget arm*-*-uclinuxfdpiceabi]
9433 || ([istarget arm*-*-linux-*]
9434 && [check_runtime sync_longlong_runtime {
9440 if (sizeof (long long) != 8)
9443 /* Just check for native;
9444 checking for kernel fallback is tricky. */
9445 asm volatile ("ldrexd r0,r1, [%0]"
9446 : : "r" (&l1) : "r0", "r1");
9450 || [istarget alpha*-*-*]
9451 || ([istarget sparc*-*-*]
9452 && [check_effective_target_lp64]
9453 && [check_effective_target_ultrasparc_hw])
9454 || ([istarget powerpc*-*-*] && [check_effective_target_lp64]) } {
9461 # Return 1 if the target supports byte swap instructions.
9463 proc check_effective_target_bswap { } {
9464 return [check_cached_effective_target bswap {
9465 expr { [istarget aarch64*-*-*]
9466 || [istarget alpha*-*-*]
9467 || [istarget i?86-*-*] || [istarget x86_64-*-*]
9468 || [istarget m68k-*-*]
9469 || [istarget powerpc*-*-*]
9470 || [istarget rs6000-*-*]
9471 || [istarget s390*-*-*]
9472 || ([istarget riscv*-*-*]
9473 && [check_no_compiler_messages_nocache riscv_zbb object {
9474 #if __riscv_zbb <= 0
9475 #error ZBB is not enabled
9479 || ([istarget arm*-*-*]
9480 && [check_no_compiler_messages_nocache arm_v6_or_later object {
9482 #error not armv6 or later
9488 # Return 1 if the target supports atomic operations on "int" and "long".
9490 proc check_effective_target_sync_int_long { } {
9491 # This is intentionally powerpc but not rs6000, rs6000 doesn't have the
9492 #
load-reserved/store
-conditional instructions.
9493 return [check_cached_effective_target sync_int_long
{
9494 expr
{ [istarget ia64
-*-*]
9495 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
9496 ||
[istarget aarch64
*-*-*]
9497 ||
[istarget alpha
*-*-*]
9498 ||
[istarget arm
*-*-linux
-*]
9499 ||
[istarget arm
*-*-uclinuxfdpiceabi
]
9500 ||
([istarget arm
*-*-*]
9501 && [check_effective_target_arm_acq_rel
])
9502 ||
[istarget bfin
*-*linux
*]
9503 ||
[istarget hppa
*-*linux
*]
9504 ||
[istarget s390
*-*-*]
9505 ||
[istarget powerpc
*-*-*]
9506 ||
[istarget cris
-*-*]
9507 ||
([istarget sparc
*-*-*] && [check_effective_target_sparc_v9
])
9508 ||
([istarget arc
*-*-*] && [check_effective_target_arc_atomic
])
9509 ||
[check_effective_target_mips_llsc
]
9510 ||
[istarget nvptx
*-*-*]
9514 #
Return 1 if the target supports atomic operations
on "int" and "long" on
9517 proc check_effective_target_sync_int_long_stack
{ } {
9518 return [check_cached_effective_target sync_int_long_stack
{
9519 expr
{ ![istarget nvptx
*-*-*]
9520 && [check_effective_target_sync_int_long
]
9524 #
Return 1 if the target supports atomic operations
on "char" and "short".
9526 proc check_effective_target_sync_char_short
{ } {
9527 # This is intentionally powerpc but not rs6000
, rs6000 doesn
't have the
9528 # load-reserved/store-conditional instructions.
9529 return [check_cached_effective_target sync_char_short {
9530 expr { [istarget aarch64*-*-*]
9531 || [istarget ia64-*-*]
9532 || [istarget i?86-*-*] || [istarget x86_64-*-*]
9533 || [istarget alpha*-*-*]
9534 || [istarget arm*-*-linux-*]
9535 || [istarget arm*-*-uclinuxfdpiceabi]
9536 || ([istarget arm*-*-*]
9537 && [check_effective_target_arm_acq_rel])
9538 || [istarget hppa*-*linux*]
9539 || [istarget s390*-*-*]
9540 || [istarget powerpc*-*-*]
9541 || [istarget cris-*-*]
9542 || ([istarget sparc*-*-*] && [check_effective_target_sparc_v9])
9543 || ([istarget arc*-*-*] && [check_effective_target_arc_atomic])
9544 || [istarget loongarch*-*-*]
9545 || [check_effective_target_mips_llsc] }}]
9548 # Return 1 if thread_fence does not rely on __sync_synchronize
9551 proc check_effective_target_thread_fence {} {
9552 return [check_no_compiler_messages thread_fence executable {
9554 __atomic_thread_fence (__ATOMIC_SEQ_CST);
9560 # Return 1 if the target uses a ColdFire FPU.
9562 proc check_effective_target_coldfire_fpu { } {
9563 return [check_no_compiler_messages coldfire_fpu assembly {
9570 # Return true if this is a uClibc target.
9572 proc check_effective_target_uclibc {} {
9573 return [check_no_compiler_messages uclibc object {
9574 #include <features.h>
9575 #if !defined (__UCLIBC__)
9581 # Return true if this is a uclibc target and if the uclibc feature
9582 # described by __$feature__ is not present.
9584 proc check_missing_uclibc_feature {feature} {
9585 return [check_no_compiler_messages $feature object "
9586 #include <features.h>
9587 #if !defined (__UCLIBC) || defined (__${feature}__)
9593 # Return true if this is a Newlib target.
9595 proc check_effective_target_newlib {} {
9596 return [check_no_compiler_messages newlib object {
9601 # Return true if GCC was configured with --enable-newlib-nano-formatted-io
9602 proc check_effective_target_newlib_nano_io { } {
9603 return [check_configured_with "--enable-newlib-nano-formatted-io"]
9606 # Some newlib versions don't provide a frexpl and instead depend
9607 #
on frexp to implement long double conversions in their printf
-like
9608 # functions. This leads to broken results. Detect such versions here.
9610 proc check_effective_target_newlib_broken_long_double_io
{} {
9611 if { [is
-effective
-target newlib
] && ![is
-effective
-target frexpl
] } {
9617 #
Return true
if this is NOT a Bionic target.
9619 proc check_effective_target_non_bionic
{} {
9620 return [check_no_compiler_messages non_bionic object
{
9622 #
if defined
(__BIONIC__
)
9628 #
Return true
if this target has error.h header.
9630 proc check_effective_target_error_h
{} {
9631 return [check_no_compiler_messages error_h object
{
9636 #
Return true
if this target has tgmath.h header.
9638 proc check_effective_target_tgmath_h
{} {
9639 return [check_no_compiler_messages tgmath_h object
{
9644 #
Return true
if target
's libc supports complex functions.
9646 proc check_effective_target_libc_has_complex_functions {} {
9647 return [check_no_compiler_messages libc_has_complex_functions object {
9648 #include <complex.h>
9653 # (a) an error of a few ULP is expected in string to floating-point
9654 # conversion functions; and
9655 # (b) overflow is not always detected correctly by those functions.
9657 proc check_effective_target_lax_strtofp {} {
9658 # By default, assume that all uClibc targets suffer from this.
9659 return [check_effective_target_uclibc]
9662 # Return 1 if this is a target for which wcsftime is a dummy
9663 # function that always returns 0.
9665 proc check_effective_target_dummy_wcsftime {} {
9666 # By default, assume that all uClibc targets suffer from this.
9667 return [check_effective_target_uclibc]
9670 # Return 1 if constructors with initialization priority arguments are
9671 # supposed on this target.
9673 proc check_effective_target_init_priority {} {
9674 return [check_no_compiler_messages init_priority assembly "
9675 void f() __attribute__((constructor (1000)));
9680 # Return 1 if the target matches the effective target 'arg', 0 otherwise.
9681 # This can be used with any check_* proc that takes no argument and
9682 # returns only 1 or 0. It could be used with check_* procs that take
9683 # arguments with keywords that pass particular arguments.
9685 proc is-effective-target { arg } {
9688 if { ![info exists et_index] } {
9689 # Initialize the effective target index that is used in some
9690 # check_effective_target_* procs.
9693 if { [info procs check_effective_target_${arg}] != [list] } {
9694 set selected [check_effective_target_${arg}]
9697 "vmx_hw" { set selected [check_vmx_hw_available] }
9698 "vsx_hw" { set selected [check_vsx_hw_available] }
9699 "p8vector_hw" { set selected [check_p8vector_hw_available] }
9700 "p9vector_hw" { set selected [check_p9vector_hw_available] }
9701 "p9modulo_hw" { set selected [check_p9modulo_hw_available] }
9702 "power10_hw" { set selected [check_power10_hw_available] }
9703 "ppc_float128_sw" { set selected [check_ppc_float128_sw_available] }
9704 "ppc_float128_hw" { set selected [check_ppc_float128_hw_available] }
9705 "ppc_recip_hw" { set selected [check_ppc_recip_hw_available] }
9706 "ppc_cpu_supports_hw" { set selected [check_ppc_cpu_supports_hw_available] }
9707 "ppc_mma_hw" { set selected [check_ppc_mma_hw_available] }
9708 "dfp_hw" { set selected [check_dfp_hw_available] }
9709 "htm_hw" { set selected [check_htm_hw_available] }
9710 "named_sections" { set selected [check_named_sections_available] }
9711 "gc_sections" { set selected [check_gc_sections_available] }
9712 "cxa_atexit" { set selected [check_cxa_atexit_available] }
9713 default { error "unknown effective target keyword `$arg'" }
9717 verbose
"is-effective-target: $arg $selected" 2
9721 #
Return 1 if the
argument is an effective
-target keyword
, 0 otherwise.
9723 proc is
-effective
-target
-keyword
{ arg } {
9724 if { [info procs check_effective_target_$
{arg}] != [list
] } {
9727 # These have different names
for their check_
* procs.
9729 "vmx_hw" { return 1 }
9730 "vsx_hw" { return 1 }
9731 "p8vector_hw" { return 1 }
9732 "p9vector_hw" { return 1 }
9733 "p9modulo_hw" { return 1 }
9734 "power10_hw" { return 1 }
9735 "ppc_float128_sw" { return 1 }
9736 "ppc_float128_hw" { return 1 }
9737 "ppc_recip_hw" { return 1 }
9738 "ppc_mma_hw" { return 1 }
9739 "dfp_hw" { return 1 }
9740 "htm_hw" { return 1 }
9741 "named_sections" { return 1 }
9742 "gc_sections" { return 1 }
9743 "cxa_atexit" { return 1 }
9744 "ppc_cpu_supports_hw" { return 1 }
9745 default
{ return 0 }
9750 #
Execute tests
for all targets in EFFECTIVE_TARGETS list.
Set et_index to
9751 # indicate what target is currently being processed. This is
for
9752 # the vectorizer tests
, e.g. vect_int
, to keep track what target supports
9755 proc et
-dg
-runtest
{ runtest testcases flags default
-extra
-flags
} {
9756 global dg
-do-what
-default
9757 global EFFECTIVE_TARGETS
9760 if { [llength $EFFECTIVE_TARGETS
] > 0 } {
9761 foreach target $EFFECTIVE_TARGETS
{
9762 set target_flags $flags
9763 set dg
-do-what
-default
compile
9764 set et_index
[lsearch
-exact $EFFECTIVE_TARGETS $target
]
9765 if { [info procs add_options_for_$
{target
}] != [list
] } {
9766 set target_flags
[add_options_for_$
{target
} "$flags"]
9768 if { [info procs check_effective_target_$
{target
}_runtime
]
9769 != [list
] && [check_effective_target_$
{target
}_runtime
] } {
9770 set dg
-do-what
-default run
9772 $runtest $testcases $target_flags $
{default
-extra
-flags
}
9776 $runtest $testcases $flags $
{default
-extra
-flags
}
9780 #
Return 1 if a target matches the target in EFFECTIVE_TARGETS at index
9781 # et_index
, 0 otherwise.
9783 proc et
-is
-effective
-target
{ target
} {
9784 global EFFECTIVE_TARGETS
9787 if { [info exists EFFECTIVE_TARGETS
] } {
9788 if { [llength $EFFECTIVE_TARGETS
] > $et_index
9789 && [lindex $EFFECTIVE_TARGETS $et_index
] == $target
} {
9795 return [check_effective_target_$
{target
}]
9799 #
Return 1 if target default to short enums
9801 proc check_effective_target_short_enums
{ } {
9802 return [check_no_compiler_messages short_enums assembly
{
9804 int s
[sizeof
(enum foo
) == 1 ?
1 : -1];
9808 #
Return 1 if target supports merging string constants at link time.
9810 proc check_effective_target_string_merging
{ } {
9811 return [check_no_messages_and_pattern string_merging \
9812 "rodata\\.str" assembly {
9813 const char
*var
= "String";
9817 #
Return 1 if target has the basic signed and unsigned types in
9818 #
<stdint.h
>, 0 otherwise. This will be obsolete when GCC ensures a
9819 # working
<stdint.h
> for all targets.
9821 proc check_effective_target_stdint_types
{ } {
9822 return [check_no_compiler_messages stdint_types assembly
{
9824 int8_t a
; int16_t b
; int32_t c
; int64_t d
;
9825 uint8_t e
; uint16_t f
; uint32_t g
; uint64_t h
;
9829 # Like check_effective_target_stdint_types
, but test what happens when
9830 #
-mbig
-endian is passed. This test only makes sense
on targets that
9831 # support
-mbig
-endian
; it will fail elsewhere.
9833 proc check_effective_target_stdint_types_mbig_endian
{ } {
9834 return [check_no_compiler_messages stdint_types_mbig_endian assembly
{
9836 int8_t a
; int16_t b
; int32_t c
; int64_t d
;
9837 uint8_t e
; uint16_t f
; uint32_t g
; uint64_t h
;
9841 #
Return 1 if target has the basic signed and unsigned types in
9842 #
<inttypes.h
>, 0 otherwise. This is
for tests that GCC
's notions of
9843 # these types agree with those in the header, as some systems have
9844 # only <inttypes.h>.
9846 proc check_effective_target_inttypes_types { } {
9847 return [check_no_compiler_messages inttypes_types assembly {
9848 #include <inttypes.h>
9849 int8_t a; int16_t b; int32_t c; int64_t d;
9850 uint8_t e; uint16_t f; uint32_t g; uint64_t h;
9854 # Return 1 if programs are intended to be run on a simulator
9855 # (i.e. slowly) rather than hardware (i.e. fast).
9857 proc check_effective_target_simulator { } {
9859 # All "src/sim" simulators set this one.
9860 if [board_info target exists is_simulator] {
9861 return [board_info target is_simulator]
9864 # The "sid" simulators don't
set that one
, but at least they
set
9866 if [board_info target
exists slow_simulator
] {
9867 return [board_info target slow_simulator
]
9873 #
Return 1 if programs are intended to be run
on hardware rather than
9876 proc check_effective_target_hw
{ } {
9878 # All
"src/sim" simulators set this one.
9879 if [board_info target
exists is_simulator
] {
9880 if [board_info target is_simulator
] {
9887 # The
"sid" simulators don't set that one, but at least they set
9889 if [board_info target
exists slow_simulator
] {
9890 if [board_info target slow_simulator
] {
9900 #
Return 1 if the target is a VxWorks kernel.
9902 proc check_effective_target_vxworks_kernel
{ } {
9903 return [check_no_compiler_messages vxworks_kernel assembly
{
9904 #
if !defined __vxworks || defined __RTP__
9910 #
Return 1 if the target is a VxWorks RTP.
9912 proc check_effective_target_vxworks_rtp
{ } {
9913 return [check_no_compiler_messages vxworks_rtp assembly
{
9914 #
if !defined __vxworks ||
!defined __RTP__
9920 #
Return 1 if the target is expected to provide wide character support.
9922 proc check_effective_target_wchar
{ } {
9923 if {[check_missing_uclibc_feature UCLIBC_HAS_WCHAR
]} {
9926 return [check_no_compiler_messages wchar assembly
{
9931 #
Return 1 if the target has
<pthread.h
>.
9933 proc check_effective_target_pthread_h
{ } {
9934 return [check_no_compiler_messages pthread_h assembly
{
9935 #
include <pthread.h
>
9939 #
Return 1 if the target can truncate a file from a file
-descriptor
,
9940 # as used by libgfortran
/io
/unix.c
:fd_truncate
; i.e. ftruncate or
9941 # chsize. We test
for a trivially functional truncation
; no stubs.
9942 # As libgfortran uses _FILE_OFFSET_BITS
64, we
do too
; it
'll cause a
9943 # different function to be used.
9945 proc check_effective_target_fd_truncate { } {
9947 #define _FILE_OFFSET_BITS 64
9954 FILE *f = fopen ("tst.tmp", "wb");
9956 const char t[] = "test writing more than ten characters";
9960 write (fd, t, sizeof (t) - 1);
9962 if (ftruncate (fd, 10) != 0)
9971 f = fopen ("tst.tmp", "rb");
9972 if (fread (s, 1, sizeof (s), f) != 10 || strncmp (s, t, 10) != 0)
9980 if { [check_runtime ftruncate $prog] } {
9984 regsub "ftruncate" $prog "chsize" prog
9985 return [check_runtime chsize $prog]
9988 # Add to FLAGS all the target-specific flags needed to enable
9989 # full IEEE compliance mode.
9991 proc add_options_for_ieee { flags } {
9992 if { [istarget alpha*-*-*]
9993 || [istarget sh*-*-*] } {
9994 return "$flags -mieee"
9996 if { [istarget rx-*-*] } {
9997 return "$flags -mnofpu"
10002 if {![info exists flags_to_postpone]} {
10003 set flags_to_postpone ""
10006 # Add to FLAGS the flags needed to enable functions to bind locally
10007 # when using pic/PIC passes in the testsuite.
10008 proc add_options_for_bind_pic_locally { flags } {
10009 global flags_to_postpone
10011 # Instead of returning 'flags
' with the -fPIE or -fpie appended, we save it
10012 # in 'flags_to_postpone
' and append it later in gcc_target_compile procedure in
10013 # order to make sure that the multilib_flags doesn't override this.
10015 if {[check_no_compiler_messages using_pic2 assembly
{
10017 #error __PIC__
!= 2
10020 set flags_to_postpone
"-fPIE"
10023 if {[check_no_compiler_messages using_pic1 assembly
{
10025 #error __PIC__
!= 1
10028 set flags_to_postpone
"-fpie"
10034 # Add to FLAGS the flags needed to enable
64-bit vectors.
10036 proc add_options_for_double_vectors
{ flags
} {
10037 if [is
-effective
-target arm_neon_ok
] {
10038 return "$flags -mvectorize-with-neon-double"
10044 # Add to FLAGS the flags needed to
define the STACK_SIZE macro.
10046 proc add_options_for_stack_size
{ flags
} {
10047 if [is
-effective
-target stack_size
] {
10048 set stack_size
[dg
-effective
-target
-value stack_size
]
10049 return "$flags -DSTACK_SIZE=$stack_size"
10055 #
Return 1 if the target provides a full C99 runtime.
10057 proc check_effective_target_c99_runtime
{ } {
10058 return [check_cached_effective_target c99_runtime
{
10061 set file
[open
"$srcdir/gcc.dg/builtins-config.h"]
10062 set contents
[read $file
]
10065 #ifndef HAVE_C99_RUNTIME
10066 #error
!HAVE_C99_RUNTIME
10069 check_no_compiler_messages_nocache c99_runtime assembly $contents
10073 #
Return 1 if the target provides the D runtime.
10075 proc check_effective_target_d_runtime
{ } {
10076 return [check_no_compiler_messages d_runtime executable
{
10080 extern
(C
) int main
() {
10086 #
Return 1 if the target provides the D standard library.
10088 proc check_effective_target_d_runtime_has_std_library
{ } {
10089 return [check_no_compiler_messages d_runtime_has_std_library executable
{
10093 extern
(C
) int main
() {
10095 real function
(real
) pcos
= &cos;
10101 #
Return 1 if target wchar_t is at least
4 bytes.
10103 proc check_effective_target_4byte_wchar_t
{ } {
10104 return [check_no_compiler_messages
4byte_wchar_t object
{
10105 int dummy
[sizeof
(__WCHAR_TYPE__
) >= 4 ?
1 : -1];
10109 #
Return 1 if the target supports automatic stack alignment.
10111 proc check_effective_target_automatic_stack_alignment
{ } {
10112 # Ordinarily x86 supports automatic stack alignment ...
10113 if { [istarget i?
86*-*-*] ||
[istarget x86_64
-*-*] } then {
10114 if { [istarget
*-*-mingw
*] ||
[istarget
*-*-cygwin
*] } {
10115 # ... except Win64 SEH doesn
't. Succeed for Win32 though.
10116 return [check_effective_target_ilp32];
10123 # Return true if we are compiling for AVX target.
10125 proc check_avx_available { } {
10126 if { [check_no_compiler_messages avx_available assembly {
10136 # Return true if we are compiling for AVX2 target.
10138 proc check_avx2_available { } {
10139 if { [check_no_compiler_messages avx2_available assembly {
10149 # Return true if we are compiling for SSSE3 target.
10151 proc check_ssse3_available { } {
10152 if { [check_no_compiler_messages sse3a_available assembly {
10162 # Return true if 32- and 16-bytes vectors are available.
10164 proc check_effective_target_vect_sizes_32B_16B { } {
10165 return [expr { [available_vector_sizes] == [list 256 128] }]
10168 # Return true if 16- and 8-bytes vectors are available.
10170 proc check_effective_target_vect_sizes_16B_8B { } {
10171 if { [check_avx_available]
10172 || [is-effective-target arm_neon]
10173 || [istarget aarch64*-*-*]
10174 || [check_effective_target_riscv_v] } {
10182 # Return true if 128-bits vectors are preferred even if 256-bits vectors
10185 proc check_prefer_avx128 { } {
10186 if ![check_avx_available] {
10189 return [check_no_messages_and_pattern avx_explicit "xmm" assembly {
10190 float a[1024],b[1024],c[1024];
10191 void foo (void) { int i; for (i = 0; i < 1024; i++) a[i]=b[i]+c[i];}
10192 } "-O2 -ftree-vectorize"]
10196 # Return 1 if avx512fp16 instructions can be compiled.
10198 proc check_effective_target_avx512fp16 { } {
10199 return [check_no_compiler_messages avx512fp16 object {
10202 asm volatile ("vmovw %edi, %xmm0");
10204 } "-O2 -mavx512fp16" ]
10207 # Return 1 if avx512f instructions can be compiled.
10209 proc check_effective_target_avx512f { } {
10210 return [check_no_compiler_messages avx512f object {
10211 typedef double __m512d __attribute__ ((__vector_size__ (64)));
10212 typedef double __m128d __attribute__ ((__vector_size__ (16)));
10214 __m512d _mm512_add (__m512d a)
10216 return __builtin_ia32_addpd512_mask (a, a, a, 1, 4);
10219 __m128d _mm128_add (__m128d a)
10221 return __builtin_ia32_addsd_round (a, a, 8);
10224 __m128d _mm128_getmant (__m128d a)
10226 return __builtin_ia32_getmantsd_round (a, a, 0, 8);
10228 } "-O2 -mavx512f" ]
10231 # Return 1 if avx instructions can be compiled.
10233 proc check_effective_target_avx { } {
10234 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
10237 return [check_no_compiler_messages avx object {
10238 void _mm256_zeroall (void)
10240 __builtin_ia32_vzeroall ();
10245 # Return 1 if avx2 instructions can be compiled.
10246 proc check_effective_target_avx2 { } {
10247 return [check_no_compiler_messages avx2 object {
10248 typedef long long __v4di __attribute__ ((__vector_size__ (32)));
10250 mm256_is32_andnotsi256 (__v4di __X, __v4di __Y)
10252 return __builtin_ia32_andnotsi256 (__X, __Y);
10257 # Return 1 if avxvnni instructions can be compiled.
10258 proc check_effective_target_avxvnni { } {
10259 return [check_no_compiler_messages avxvnni object {
10260 typedef int __v8si __attribute__ ((__vector_size__ (32)));
10262 _mm256_dpbusd_epi32 (__v8si __A, __v8si __B, __v8si __C)
10264 return __builtin_ia32_vpdpbusd_v8si (__A, __B, __C);
10269 # Return 1 if avxifma instructions can be compiled.
10270 proc check_effective_target_avxifma { } {
10271 return [check_no_compiler_messages avxifma object {
10272 typedef long long __v4di __attribute__ ((__vector_size__ (32)));
10274 _mm256_maddlo_epu64 (__v4di __A, __v4di __B, __v4di __C)
10276 return __builtin_ia32_vpmadd52luq256 (__A, __B, __C);
10278 } "-O0 -mavxifma" ]
10281 # Return 1 if avxvnniint8 instructions can be compiled.
10282 proc check_effective_target_avxvnniint8 { } {
10283 return [check_no_compiler_messages avxvnniint8 object {
10284 typedef int __v8si __attribute__ ((__vector_size__ (32)));
10286 _mm256_dpbssd_epi32 (__v8si __A, __v8si __B, __v8si __C)
10288 return __builtin_ia32_vpdpbssd256 (__A, __B, __C);
10290 } "-O0 -mavxvnniint8" ]
10293 # Return 1 if avxneconvert instructions can be compiled.
10294 proc check_effective_target_avxneconvert { } {
10295 return [check_no_compiler_messages avxneconvert object {
10296 typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__));
10298 _mm_bcstnebf16_ps (const void *__P)
10300 return (__m128) __builtin_ia32_vbcstnebf162ps128 ((const __bf16 *) __P);
10302 } "-O0 -mavxneconvert" ]
10305 # Return 1 if cmpccxadd instructions can be compiled.
10306 proc check_effective_target_cmpccxadd { } {
10307 return [check_no_compiler_messages cmpccxadd object {
10308 int _cmpccxadd_epi32 (int *__A, int __B, int __C, const int __D)
10310 return (int)__builtin_ia32_cmpccxadd (__A, __B, __C, 1);
10315 # Return 1 if raoint instructions can be compiled.
10316 proc check_effective_target_raoint { } {
10317 return [check_no_compiler_messages raoint object {
10319 _aadd_si32 (int *__A, int __B)
10321 return __builtin_ia32_aadd32((int *)__A, __B);
10326 # Return 1 if amx-complex instructions can be compiled.
10327 proc check_effective_target_amx_complex { } {
10328 return [check_no_compiler_messages amx_complex object {
10332 __asm__ volatile ("tcmmimfp16ps\t%%tmm1, %%tmm2, %%tmm3" ::);
10334 } "-mamx-complex" ]
10337 # Return 1 if avxvnniint16 instructions can be compiled.
10338 proc check_effective_target_avxvnniint16 { } {
10339 return [check_no_compiler_messages avxvnniint16 object {
10340 typedef int __v8si __attribute__ ((__vector_size__ (32)));
10342 _mm256_dpwsud_avx_epi32 (__v8si __A, __v8si __B, __v8si __C)
10344 return __builtin_ia32_vpdpwsud256 (__A, __B, __C);
10346 } "-O0 -mavxvnniint16" ]
10349 # Return 1 if sm3 instructions can be compiled.
10350 proc check_effective_target_sm3 { } {
10351 return [check_no_compiler_messages sm3 object {
10352 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10353 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10355 _mm_sm3msg1_epi32 (__m128i __A, __m128i __B, __m128i __C)
10357 return (__m128i) __builtin_ia32_vsm3msg1 ((__v4si) __A,
10364 # Return 1 if sha512 instructions can be compiled.
10365 proc check_effective_target_sha512 { } {
10366 return [check_no_compiler_messages sha512 object {
10367 typedef long long __m256i __attribute__ ((__vector_size__ (32)));
10368 typedef long long __v4di __attribute__ ((__vector_size__ (32)));
10370 _mm256_sha512msg2_epi64 (__m256i __A, __m256i __B)
10372 return (__m256i) __builtin_ia32_vsha512msg2 ((__v4di) __A,
10378 # Return 1 if sm4 instructions can be compiled.
10379 proc check_effective_target_sm4 { } {
10380 return [check_no_compiler_messages sm4 object {
10381 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10382 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10384 _mm_sm4key4_epi32 (__m128i __A, __m128i __B)
10386 return (__m128i) __builtin_ia32_vsm4key4128 ((__v4si) __A,
10392 proc check_effective_target_apxf { } {
10393 return [check_no_compiler_messages apxf object {
10397 __asm__ volatile ("add\t%%r16, %%r31" ::);
10402 # Return 1 if sse instructions can be compiled.
10403 proc check_effective_target_sse { } {
10404 return [check_no_compiler_messages sse object {
10407 __builtin_ia32_stmxcsr ();
10413 # Return 1 if sse2 instructions can be compiled.
10414 proc check_effective_target_sse2 { } {
10415 return [check_no_compiler_messages sse2 object {
10416 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10418 __m128i _mm_srli_si128 (__m128i __A, int __N)
10420 return (__m128i)__builtin_ia32_psrldqi128 (__A, 8);
10425 # Return 1 if sse4.1 instructions can be compiled.
10426 proc check_effective_target_sse4 { } {
10427 return [check_no_compiler_messages sse4.1 object {
10428 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10429 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10431 __m128i _mm_mullo_epi32 (__m128i __X, __m128i __Y)
10433 return (__m128i) __builtin_ia32_pmulld128 ((__v4si)__X,
10439 # Return 1 if F16C instructions can be compiled.
10441 proc check_effective_target_f16c { } {
10442 return [check_no_compiler_messages f16c object {
10443 #include "immintrin.h"
10445 foo (unsigned short val)
10447 return _cvtsh_ss (val);
10452 proc check_effective_target_ms_hook_prologue { } {
10453 if { [check_no_compiler_messages ms_hook_prologue object {
10454 void __attribute__ ((__ms_hook_prologue__)) foo ();
10462 # Return 1 if 3dnow instructions can be compiled.
10463 proc check_effective_target_3dnow { } {
10464 return [check_no_compiler_messages 3dnow object {
10465 typedef int __m64 __attribute__ ((__vector_size__ (8)));
10466 typedef float __v2sf __attribute__ ((__vector_size__ (8)));
10468 __m64 _m_pfadd (__m64 __A, __m64 __B)
10470 return (__m64) __builtin_ia32_pfadd ((__v2sf)__A, (__v2sf)__B);
10475 # Return 1 if sse3 instructions can be compiled.
10476 proc check_effective_target_sse3 { } {
10477 return [check_no_compiler_messages sse3 object {
10478 typedef double __m128d __attribute__ ((__vector_size__ (16)));
10479 typedef double __v2df __attribute__ ((__vector_size__ (16)));
10481 __m128d _mm_addsub_pd (__m128d __X, __m128d __Y)
10483 return (__m128d) __builtin_ia32_addsubpd ((__v2df)__X, (__v2df)__Y);
10488 # Return 1 if ssse3 instructions can be compiled.
10489 proc check_effective_target_ssse3 { } {
10490 return [check_no_compiler_messages ssse3 object {
10491 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10492 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10494 __m128i _mm_abs_epi32 (__m128i __X)
10496 return (__m128i) __builtin_ia32_pabsd128 ((__v4si)__X);
10501 # Return 1 if aes instructions can be compiled.
10502 proc check_effective_target_aes { } {
10503 return [check_no_compiler_messages aes object {
10504 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10505 typedef long long __v2di __attribute__ ((__vector_size__ (16)));
10507 __m128i _mm_aesimc_si128 (__m128i __X)
10509 return (__m128i) __builtin_ia32_aesimc128 ((__v2di)__X);
10514 # Return 1 if vaes instructions can be compiled.
10515 proc check_effective_target_vaes { } {
10516 return [check_no_compiler_messages vaes object {
10517 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10518 typedef long long __v2di __attribute__ ((__vector_size__ (16)));
10520 __m128i _mm_aesimc_si128 (__m128i __X)
10522 return (__m128i) __builtin_ia32_aesimc128 ((__v2di)__X);
10524 } "-O2 -maes -mavx" ]
10527 # Return 1 if pclmul instructions can be compiled.
10528 proc check_effective_target_pclmul { } {
10529 return [check_no_compiler_messages pclmul object {
10530 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10531 typedef long long __v2di __attribute__ ((__vector_size__ (16)));
10533 __m128i pclmulqdq_test (__m128i __X, __m128i __Y)
10535 return (__m128i) __builtin_ia32_pclmulqdq128 ((__v2di)__X,
10542 # Return 1 if vpclmul instructions can be compiled.
10543 proc check_effective_target_vpclmul { } {
10544 return [check_no_compiler_messages vpclmul object {
10545 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10546 typedef long long __v2di __attribute__ ((__vector_size__ (16)));
10548 __m128i pclmulqdq_test (__m128i __X, __m128i __Y)
10550 return (__m128i) __builtin_ia32_pclmulqdq128 ((__v2di)__X,
10554 } "-O2 -mpclmul -mavx" ]
10557 # Return 1 if sse4a instructions can be compiled.
10558 proc check_effective_target_sse4a { } {
10559 return [check_no_compiler_messages sse4a object {
10560 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10561 typedef long long __v2di __attribute__ ((__vector_size__ (16)));
10563 __m128i _mm_insert_si64 (__m128i __X,__m128i __Y)
10565 return (__m128i) __builtin_ia32_insertq ((__v2di)__X, (__v2di)__Y);
10570 # Return 1 if fma4 instructions can be compiled.
10571 proc check_effective_target_fma4 { } {
10572 return [check_no_compiler_messages fma4 object {
10573 typedef float __m128 __attribute__ ((__vector_size__ (16)));
10574 typedef float __v4sf __attribute__ ((__vector_size__ (16)));
10575 __m128 _mm_macc_ps(__m128 __A, __m128 __B, __m128 __C)
10577 return (__m128) __builtin_ia32_vfmaddps ((__v4sf)__A,
10584 # Return 1 if fma instructions can be compiled.
10585 proc check_effective_target_fma { } {
10586 return [check_no_compiler_messages fma object {
10587 typedef float __m128 __attribute__ ((__vector_size__ (16)));
10588 typedef float __v4sf __attribute__ ((__vector_size__ (16)));
10589 __m128 _mm_macc_ps(__m128 __A, __m128 __B, __m128 __C)
10591 return (__m128) __builtin_ia32_vfmaddps ((__v4sf)__A,
10598 # Return 1 if xop instructions can be compiled.
10599 proc check_effective_target_xop { } {
10600 return [check_no_compiler_messages xop object {
10601 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10602 typedef short __v8hi __attribute__ ((__vector_size__ (16)));
10603 __m128i _mm_maccs_epi16(__m128i __A, __m128i __B, __m128i __C)
10605 return (__m128i) __builtin_ia32_vpmacssww ((__v8hi)__A,
10612 # Return 1 if lzcnt instruction can be compiled.
10613 proc check_effective_target_lzcnt { } {
10614 return [check_no_compiler_messages lzcnt object {
10615 unsigned short _lzcnt (unsigned short __X)
10617 return __builtin_clzs (__X);
10622 # Return 1 if bmi instructions can be compiled.
10623 proc check_effective_target_bmi { } {
10624 return [check_no_compiler_messages bmi object {
10625 unsigned int __bextr_u32 (unsigned int __X, unsigned int __Y)
10627 return __builtin_ia32_bextr_u32 (__X, __Y);
10632 # Return 1 if ADX instructions can be compiled.
10633 proc check_effective_target_adx { } {
10634 return [check_no_compiler_messages adx object {
10636 _adxcarry_u32 (unsigned char __CF, unsigned int __X,
10637 unsigned int __Y, unsigned int *__P)
10639 return __builtin_ia32_addcarryx_u32 (__CF, __X, __Y, __P);
10644 # Return 1 if rtm instructions can be compiled.
10645 proc check_effective_target_rtm { } {
10646 return [check_no_compiler_messages rtm object {
10650 return __builtin_ia32_xend ();
10655 # Return 1 if avx512vl instructions can be compiled.
10656 proc check_effective_target_avx512vl { } {
10657 return [check_no_compiler_messages avx512vl object {
10658 typedef long long __v4di __attribute__ ((__vector_size__ (32)));
10660 mm256_and_epi64 (__v4di __X, __v4di __Y)
10663 return __builtin_ia32_pandq256_mask (__X, __Y, __W, -1);
10668 # Return 1 if avx512cd instructions can be compiled.
10669 proc check_effective_target_avx512cd { } {
10670 return [check_no_compiler_messages avx512cd_trans object {
10671 typedef long long __v8di __attribute__ ((__vector_size__ (64)));
10673 _mm512_conflict_epi64 (__v8di __W, __v8di __A)
10675 return (__v8di) __builtin_ia32_vpconflictdi_512_mask ((__v8di) __A,
10679 } "-Wno-psabi -mavx512cd" ]
10682 # Return 1 if avx512er instructions can be compiled.
10683 proc check_effective_target_avx512er { } {
10684 return [check_no_compiler_messages avx512er_trans object {
10685 typedef float __v16sf __attribute__ ((__vector_size__ (64)));
10687 mm512_exp2a23_ps (__v16sf __X)
10689 return __builtin_ia32_exp2ps_mask (__X, __X, -1, 4);
10691 } "-Wno-psabi -mavx512er" ]
10694 # Return 1 if sha instructions can be compiled.
10695 proc check_effective_target_sha { } {
10696 return [check_no_compiler_messages sha object {
10697 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10698 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10700 __m128i _mm_sha1msg1_epu32 (__m128i __X, __m128i __Y)
10702 return (__m128i) __builtin_ia32_sha1msg1 ((__v4si)__X,
10708 # Return 1 if avx512dq instructions can be compiled.
10709 proc check_effective_target_avx512dq { } {
10710 return [check_no_compiler_messages avx512dq object {
10711 typedef long long __v8di __attribute__ ((__vector_size__ (64)));
10713 _mm512_mask_mullo_epi64 (__v8di __W, __v8di __A, __v8di __B)
10715 return (__v8di) __builtin_ia32_pmullq512_mask ((__v8di) __A,
10723 # Return 1 if avx512bw instructions can be compiled.
10724 proc check_effective_target_avx512bw { } {
10725 return [check_no_compiler_messages avx512bw object {
10726 typedef short __v32hi __attribute__ ((__vector_size__ (64)));
10728 _mm512_mask_mulhrs_epi16 (__v32hi __W, __v32hi __A, __v32hi __B)
10730 return (__v32hi) __builtin_ia32_pmulhrsw512_mask ((__v32hi) __A,
10738 # Return 1 if -Wa,-march=+noavx512bw is supported.
10739 proc check_effective_target_assembler_march_noavx512bw {} {
10740 if { [istarget i?86*-*-*] || [istarget x86_64*-*-*] } {
10741 return [check_no_compiler_messages assembler_march_noavx512bw object {
10743 } "-mno-avx512bw -Wa,-march=+noavx512bw"]
10748 # Return 1 if avx512vp2intersect instructions can be compiled.
10749 proc check_effective_target_avx512vp2intersect { } {
10750 return [check_no_compiler_messages avx512vp2intersect object {
10751 typedef int __v16si __attribute__ ((__vector_size__ (64)));
10752 typedef short __mmask16;
10754 _mm512_2intersect_epi32 (__v16si __A, __v16si __B, __mmask16 *__U,
10757 __builtin_ia32_2intersectd512 (__U, __M, (__v16si) __A, (__v16si) __B);
10759 } "-mavx512vp2intersect" ]
10762 # Return 1 if avx512ifma instructions can be compiled.
10763 proc check_effective_target_avx512ifma { } {
10764 return [check_no_compiler_messages avx512ifma object {
10765 typedef long long __v8di __attribute__ ((__vector_size__ (64)));
10767 _mm512_madd52lo_epu64 (__v8di __X, __v8di __Y, __v8di __Z)
10769 return (__v8di) __builtin_ia32_vpmadd52luq512_mask ((__v8di) __X,
10777 # Return 1 if avx512vbmi instructions can be compiled.
10778 proc check_effective_target_avx512vbmi { } {
10779 return [check_no_compiler_messages avx512vbmi object {
10780 typedef char __v64qi __attribute__ ((__vector_size__ (64)));
10782 _mm512_multishift_epi64_epi8 (__v64qi __X, __v64qi __Y)
10784 return (__v64qi) __builtin_ia32_vpmultishiftqb512_mask ((__v64qi) __X,
10792 # Return 1 if avx512_4fmaps instructions can be compiled.
10793 proc check_effective_target_avx5124fmaps { } {
10794 return [check_no_compiler_messages avx5124fmaps object {
10795 typedef float __v16sf __attribute__ ((__vector_size__ (64)));
10796 typedef float __v4sf __attribute__ ((__vector_size__ (16)));
10799 _mm512_mask_4fmadd_ps (__v16sf __DEST, __v16sf __A, __v16sf __B, __v16sf __C,
10800 __v16sf __D, __v16sf __E, __v4sf *__F)
10802 return (__v16sf) __builtin_ia32_4fmaddps_mask ((__v16sf) __A,
10807 (const __v4sf *) __F,
10811 } "-mavx5124fmaps" ]
10814 # Return 1 if avx512_4vnniw instructions can be compiled.
10815 proc check_effective_target_avx5124vnniw { } {
10816 return [check_no_compiler_messages avx5124vnniw object {
10817 typedef int __v16si __attribute__ ((__vector_size__ (64)));
10818 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10821 _mm512_4dpwssd_epi32 (__v16si __A, __v16si __B, __v16si __C,
10822 __v16si __D, __v16si __E, __v4si *__F)
10824 return (__v16si) __builtin_ia32_vp4dpwssd ((__v16si) __B,
10829 (const __v4si *) __F);
10831 } "-mavx5124vnniw" ]
10834 # Return 1 if avx512_vpopcntdq instructions can be compiled.
10835 proc check_effective_target_avx512vpopcntdq { } {
10836 return [check_no_compiler_messages avx512vpopcntdq object {
10837 typedef int __v16si __attribute__ ((__vector_size__ (64)));
10840 _mm512_popcnt_epi32 (__v16si __A)
10842 return (__v16si) __builtin_ia32_vpopcountd_v16si ((__v16si) __A);
10844 } "-mavx512vpopcntdq" ]
10847 # Return 1 if 128 or 256-bit avx512_vpopcntdq instructions can be compiled.
10848 proc check_effective_target_avx512vpopcntdqvl { } {
10849 return [check_no_compiler_messages avx512vpopcntdqvl object {
10850 typedef int __v8si __attribute__ ((__vector_size__ (32)));
10853 _mm256_popcnt_epi32 (__v8si __A)
10855 return (__v8si) __builtin_ia32_vpopcountd_v8si ((__v8si) __A);
10857 } "-mavx512vpopcntdq -mavx512vl" ]
10860 # Return 1 if gfni instructions can be compiled.
10861 proc check_effective_target_gfni { } {
10862 return [check_no_compiler_messages gfni object {
10863 typedef char __v16qi __attribute__ ((__vector_size__ (16)));
10866 _mm_gf2p8affineinv_epi64_epi8 (__v16qi __A, __v16qi __B, const int __C)
10868 return (__v16qi) __builtin_ia32_vgf2p8affineinvqb_v16qi ((__v16qi) __A,
10875 # Return 1 if avx512vbmi2 instructions can be compiled.
10876 proc check_effective_target_avx512vbmi2 { } {
10877 return [check_no_compiler_messages avx512vbmi2 object {
10878 typedef char __v16qi __attribute__ ((__vector_size__ (16)));
10879 typedef unsigned long long __mmask16;
10882 _mm_mask_compress_epi8 (__v16qi __A, __mmask16 __B, __v16qi __C)
10884 return (__v16qi) __builtin_ia32_compressqi128_mask((__v16qi)__C,
10888 } "-mavx512vbmi2 -mavx512vl" ]
10891 # Return 1 if avx512vbmi2 instructions can be compiled.
10892 proc check_effective_target_avx512vnni { } {
10893 return [check_no_compiler_messages avx512vnni object {
10894 typedef int __v16si __attribute__ ((__vector_size__ (64)));
10897 _mm_mask_compress_epi8 (__v16si __A, __v16si __B, __v16si __C)
10899 return (__v16si) __builtin_ia32_vpdpbusd_v16si ((__v16si)__A,
10903 } "-mavx512vnni -mavx512f" ]
10906 # Return 1 if vaes instructions can be compiled.
10907 proc check_effective_target_avx512vaes { } {
10908 return [check_no_compiler_messages avx512vaes object {
10910 typedef int __v16si __attribute__ ((__vector_size__ (64)));
10913 _mm256_aesdec_epi128 (__v32qi __A, __v32qi __B)
10915 return (__v32qi)__builtin_ia32_vaesdec_v32qi ((__v32qi) __A, (__v32qi) __B);
10920 # Return 1 if amx-tile instructions can be compiled.
10921 proc check_effective_target_amx_tile { } {
10922 return [check_no_compiler_messages amx_tile object {
10926 __asm__ volatile ("tilerelease" ::);
10931 # Return 1 if amx-int8 instructions can be compiled.
10932 proc check_effective_target_amx_int8 { } {
10933 return [check_no_compiler_messages amx_int8 object {
10937 __asm__ volatile ("tdpbssd\t%%tmm1, %%tmm2, %%tmm3" ::);
10942 # Return 1 if amx-bf16 instructions can be compiled.
10943 proc check_effective_target_amx_bf16 { } {
10944 return [check_no_compiler_messages amx_bf16 object {
10948 __asm__ volatile ("tdpbf16ps\t%%tmm1, %%tmm2, %%tmm3" ::);
10953 # Return 1 if amx-fp16 instructions can be compiled.
10954 proc check_effective_target_amx_fp16 { } {
10955 return [check_no_compiler_messages amx_fp16 object {
10959 __asm__ volatile ("tdpfp16ps\t%%tmm1, %%tmm2, %%tmm3" ::);
10964 # Return 1 if vpclmulqdq instructions can be compiled.
10965 proc check_effective_target_vpclmulqdq { } {
10966 return [check_no_compiler_messages vpclmulqdq object {
10967 typedef long long __v4di __attribute__ ((__vector_size__ (32)));
10970 _mm256_clmulepi64_epi128 (__v4di __A, __v4di __B)
10972 return (__v4di) __builtin_ia32_vpclmulqdq_v4di (__A, __B, 0);
10974 } "-mvpclmulqdq -mavx512vl" ]
10977 # Return 1 if avx512_bitalg instructions can be compiled.
10978 proc check_effective_target_avx512bitalg { } {
10979 return [check_no_compiler_messages avx512bitalg object {
10980 typedef short int __v32hi __attribute__ ((__vector_size__ (64)));
10983 _mm512_popcnt_epi16 (__v32hi __A)
10985 return (__v32hi) __builtin_ia32_vpopcountw_v32hi ((__v32hi) __A);
10987 } "-mavx512bitalg" ]
10990 # Return 1 if C wchar_t type is compatible with char16_t.
10992 proc check_effective_target_wchar_t_char16_t_compatible { } {
10993 return [check_no_compiler_messages wchar_t_char16_t object {
10995 __CHAR16_TYPE__ *p16 = &wc;
10996 char t[(((__CHAR16_TYPE__) -1) < 0 == ((__WCHAR_TYPE__) -1) < 0) ? 1 : -1];
11000 # Return 1 if C wchar_t type is compatible with char32_t.
11002 proc check_effective_target_wchar_t_char32_t_compatible { } {
11003 return [check_no_compiler_messages wchar_t_char32_t object {
11005 __CHAR32_TYPE__ *p32 = &wc;
11006 char t[(((__CHAR32_TYPE__) -1) < 0 == ((__WCHAR_TYPE__) -1) < 0) ? 1 : -1];
11010 # Return 1 if pow10 function exists.
11012 proc check_effective_target_pow10 { } {
11013 return [check_runtime pow10 {
11023 # Return 1 if frexpl function exists.
11025 proc check_effective_target_frexpl { } {
11026 return [check_runtime frexpl {
11031 x = frexpl (5.0, &y);
11038 # Return 1 if issignaling function exists.
11039 proc check_effective_target_issignaling {} {
11040 return [check_runtime issignaling {
11041 #define _GNU_SOURCE
11045 return issignaling (0.0);
11050 # Return 1 if current options generate DFP instructions, 0 otherwise.
11051 proc check_effective_target_hard_dfp {} {
11052 return [check_no_messages_and_pattern hard_dfp "!adddd3" assembly {
11053 typedef float d64 __attribute__((mode(DD)));
11055 void foo (void) { z = x + y; }
11059 # Return 1 if string.h and wchar.h headers provide C++ requires overloads
11060 # for strchr etc. functions.
11062 proc check_effective_target_correct_iso_cpp_string_wchar_protos { } {
11063 return [check_no_compiler_messages correct_iso_cpp_string_wchar_protos assembly {
11064 #include <string.h>
11066 #if !defined(__cplusplus) \
11067 || !defined(__CORRECT_ISO_CPP_STRING_H_PROTO) \
11068 || !defined(__CORRECT_ISO_CPP_WCHAR_H_PROTO)
11069 ISO C++ correct string.h and wchar.h protos not supported.
11076 # Return 1 if GNU as is used.
11078 proc check_effective_target_gas { } {
11079 global use_gas_saved
11082 if {![info exists use_gas_saved]} {
11083 # Check if the as used by gcc is GNU as.
11084 set options [list "additional_flags=-print-prog-name=as"]
11085 set gcc_as [lindex [${tool}_target_compile "" "" "none" $options] 0]
11086 # Provide /dev/null as input, otherwise gas times out reading from
11088 set status [remote_exec host "$gcc_as" "-v /dev/null"]
11089 set as_output [lindex $status 1]
11090 if { [ string first "GNU" $as_output ] >= 0 } {
11091 # Some Darwin versions have an assembler which is based on an old
11092 # version of GAS (and reports GNU assembler in its -v output) but
11093 # but doesn't support many of the modern GAS features.
11094 if { [ string first
"cctools" $as_output ] >= 0 } {
11095 set use_gas_saved
0
11097 set use_gas_saved
1
11100 set use_gas_saved
0
11103 return $use_gas_saved
11106 #
Return 1 if GNU
ld is used.
11108 proc check_effective_target_gld
{ } {
11109 global use_gld_saved
11112 if {![info exists use_gld_saved
]} {
11113 # Check
if the
ld used by gcc is GNU
ld.
11114 set options
[list
"additional_flags=-print-prog-name=ld"]
11115 set gcc_ld
[lindex
[$
{tool
}_target_compile
"" "" "none" $options] 0]
11116 set status [remote_exec host
"$gcc_ld" "--version"]
11117 set ld_output
[lindex $
status 1]
11118 if { [ string first
"GNU" $ld_output ] >= 0 } {
11119 set use_gld_saved
1
11121 set use_gld_saved
0
11124 return $use_gld_saved
11127 #
Return 1 if the compiler has been configure with link
-time optimization
11130 proc check_effective_target_lto
{ } {
11131 if { [istarget
*-*-vxworks
*] } {
11132 # No LTO
on VxWorks
, with kernel modules
11133 # built with partial links
11136 if { [istarget nvptx
-*-*]
11137 ||
[istarget amdgcn
-*-*] } {
11140 return [check_no_compiler_messages lto object
{
11141 void foo
(void
) { }
11145 #
Return 1 if the compiler and linker support incremental link
-time
11148 proc check_effective_target_lto_incremental
{ } {
11149 if ![check_effective_target_lto
] {
11152 return [check_no_compiler_messages lto_incremental executable
{
11153 int main
() { return 0; }
11154 } "-flto -r -nostdlib"]
11157 #
Return 1 if the compiler has been configured with analyzer support.
11159 proc check_effective_target_analyzer
{ } {
11160 return [check_no_compiler_messages analyzer object
{
11161 void foo
(void
) { }
11165 #
Return 1 if -mx32
-maddress
-mode=short can
compile, 0 otherwise.
11167 proc check_effective_target_maybe_x32
{ } {
11168 return [check_no_compiler_messages maybe_x32 object
{
11170 } "-mx32 -maddress-mode=short"]
11173 #
Return 1 if this target supports the
-fsplit
-stack option
, 0
11176 proc check_effective_target_split_stack
{} {
11177 return [check_no_compiler_messages split_stack object
{
11178 void foo
(void
) { }
11182 #
Return 1 if this target supports the
-masm
=intel option
, 0
11185 proc check_effective_target_masm_intel
{} {
11186 return [check_no_compiler_messages masm_intel object
{
11187 extern void abort
(void
);
11191 #
Return 1 if the language
for the compiler under test is C.
11193 proc check_effective_target_c
{ } {
11195 if [string match $tool
"gcc"] {
11201 #
Return 1 if the language
for the compiler under test is C
++.
11203 proc check_effective_target_c
++ { } {
11205 if { [string match $tool
"g++"] || [string match $tool "libstdc++"] } {
11211 set cxx_default
"c++17"
11212 # Check whether the current active language standard supports the features
11213 # of C
++11/C
++14 by checking
for the presence of one of the
-std flags.
11214 # This assumes that the default
for the compiler is $cxx_default
, and that
11215 # there will never be multiple
-std
= arguments
on the command line.
11216 proc check_effective_target_c
++11_only
{ } {
11218 if ![check_effective_target_c
++] {
11221 if [check
-flags
{ { } { } { -std
=c
++0x
-std
=gnu
++0x
-std
=c
++11 -std
=gnu
++11 } }] {
11224 if { $cxx_default
== "c++11" && [check-flags { { } { } { } { -std=* } }] } {
11229 proc check_effective_target_c
++11 { } {
11230 if [check_effective_target_c
++11_only
] {
11233 return [check_effective_target_c
++14]
11235 proc check_effective_target_c
++11_down
{ } {
11236 if ![check_effective_target_c
++] {
11239 return [expr
![check_effective_target_c
++14] ]
11242 proc check_effective_target_c
++14_only
{ } {
11244 if ![check_effective_target_c
++] {
11247 if [check
-flags
{ { } { } { -std
=c
++14 -std
=gnu
++14 -std
=c
++14 -std
=gnu
++14 } }] {
11250 if { $cxx_default
== "c++14" && [check-flags { { } { } { } { -std=* } }] } {
11256 proc check_effective_target_c
++14 { } {
11257 if [check_effective_target_c
++14_only
] {
11260 return [check_effective_target_c
++17]
11262 proc check_effective_target_c
++14_down
{ } {
11263 if ![check_effective_target_c
++] {
11266 return [expr
![check_effective_target_c
++17] ]
11269 proc check_effective_target_c
++98_only
{ } {
11271 if ![check_effective_target_c
++] {
11274 if [check
-flags
{ { } { } { -std
=c
++98 -std
=gnu
++98 -std
=c
++03 -std
=gnu
++03 } }] {
11277 if { $cxx_default
== "c++98" && [check-flags { { } { } { } { -std=* } }] } {
11283 proc check_effective_target_c
++17_only
{ } {
11285 if ![check_effective_target_c
++] {
11288 if [check
-flags
{ { } { } { -std
=c
++17 -std
=gnu
++17 -std
=c
++1z
-std
=gnu
++1z
} }] {
11291 if { $cxx_default
== "c++17" && [check-flags { { } { } { } { -std=* } }] } {
11297 proc check_effective_target_c
++17 { } {
11298 if [check_effective_target_c
++17_only
] {
11301 return [check_effective_target_c
++2a
]
11303 proc check_effective_target_c
++17_down
{ } {
11304 if ![check_effective_target_c
++] {
11307 return [expr
![check_effective_target_c
++2a
] ]
11310 proc check_effective_target_c
++2a_only
{ } {
11312 if ![check_effective_target_c
++] {
11315 if [check
-flags
{ { } { } { -std
=c
++2a
-std
=gnu
++2a
-std
=c
++20 -std
=gnu
++20 } }] {
11318 if { $cxx_default
== "c++20" && [check-flags { { } { } { } { -std=* } }] } {
11323 proc check_effective_target_c
++2a
{ } {
11324 if [check_effective_target_c
++2a_only
] {
11327 return [check_effective_target_c
++23]
11330 proc check_effective_target_c
++20_only
{ } {
11331 return [check_effective_target_c
++2a_only
]
11334 proc check_effective_target_c
++20 { } {
11335 return [check_effective_target_c
++2a
]
11337 proc check_effective_target_c
++20_down
{ } {
11338 if ![check_effective_target_c
++] {
11341 return [expr
![check_effective_target_c
++23] ]
11344 proc check_effective_target_c
++23_only
{ } {
11346 if ![check_effective_target_c
++] {
11349 if [check
-flags
{ { } { } { -std
=c
++23 -std
=gnu
++23 -std
=c
++2b
-std
=gnu
++2b
} }] {
11352 if { $cxx_default
== "c++23" && [check-flags { { } { } { } { -std=* } }] } {
11357 proc check_effective_target_c
++23 { } {
11358 if [check_effective_target_c
++23_only
] {
11361 return [check_effective_target_c
++26]
11364 proc check_effective_target_c
++23_down
{ } {
11365 if ![check_effective_target_c
++] {
11368 return [expr
![check_effective_target_c
++26] ]
11371 proc check_effective_target_c
++26_only
{ } {
11373 if ![check_effective_target_c
++] {
11376 if [check
-flags
{ { } { } { -std
=c
++26 -std
=gnu
++26 -std
=c
++2c
-std
=gnu
++2c
} }] {
11379 if { $cxx_default
== "c++26" && [check-flags { { } { } { } { -std=* } }] } {
11385 proc check_effective_target_c
++26 { } {
11386 return [check_effective_target_c
++26_only
]
11389 # Check
for C
++ Concepts support
, i.e.
-fconcepts flag.
11390 proc check_effective_target_concepts
{ } {
11391 if [check_effective_target_c
++2a
] {
11394 return [check
-flags
{ "" { } { -fconcepts } }]
11397 proc check_effective_target_implicit_constexpr
{ } {
11398 return [check
-flags
{ "" { } { -fimplicit-constexpr } }]
11401 #
Return 1 if expensive testcases should be run.
11403 proc check_effective_target_run_expensive_tests
{ } {
11404 if { [getenv GCC_TEST_RUN_EXPENSIVE
] != "" } {
11410 # Returns
1 if "mempcpy" is available on the target system.
11412 proc check_effective_target_mempcpy
{} {
11413 if { [istarget
*-*-vxworks
*] } {
11414 # VxWorks doesn
't have mempcpy but our way to test fails
11415 # to detect as we're doing partial links
for kernel modules.
11418 return [check_function_available
"mempcpy"]
11421 # Returns
1 if "stpcpy" is available on the target system.
11423 proc check_effective_target_stpcpy
{} {
11424 return [check_function_available
"stpcpy"]
11427 # Returns
1 if "sigsetjmp" is available on the target system.
11428 # Also check
if "__sigsetjmp" is defined since that's what glibc
11431 proc check_effective_target_sigsetjmp
{} {
11432 if { [check_function_available
"sigsetjmp"]
11433 ||
[check_function_available
"__sigsetjmp"] } {
11439 # Check whether the vectorizer tests are supported by the target and
11440 # append additional target
-dependent
compile flags to DEFAULT_VECTCFLAGS.
11441 #
If a port wants to
execute the tests more than once it should append
11442 # the supported target to EFFECTIVE_TARGETS instead
, and the
compile flags
11443 # will be added by a
call to add_options_for_
<target
>.
11444 #
Set dg
-do-what
-default to either
compile or run
, depending
on target
11445 # capabilities.
Do not
set this
if the supported target is appended to
11446 # EFFECTIVE_TARGETS. Flags and this
variable will be
set by et
-dg
-runtest
11447 # automatically.
Return the number of effective targets
if vectorizer tests
11448 # are supported
, 0 otherwise.
11450 proc check_vect_support_and_set_flags
{ } {
11451 global DEFAULT_VECTCFLAGS
11452 global dg
-do-what
-default
11453 global EFFECTIVE_TARGETS
11455 if [istarget powerpc
-*paired
*] {
11456 lappend DEFAULT_VECTCFLAGS
"-mpaired"
11457 if [check_750cl_hw_available
] {
11458 set dg
-do-what
-default run
11460 set dg
-do-what
-default
compile
11462 } elseif
[istarget powerpc
*-*-*] {
11463 # Skip targets not supporting
-maltivec.
11464 if ![is
-effective
-target powerpc_altivec_ok
] {
11468 lappend DEFAULT_VECTCFLAGS
"-maltivec"
11469 if [check_p9vector_hw_available
] {
11470 lappend DEFAULT_VECTCFLAGS
"-mpower9-vector"
11471 } elseif
[check_p8vector_hw_available
] {
11472 lappend DEFAULT_VECTCFLAGS
"-mpower8-vector"
11473 } elseif
[check_vsx_hw_available
] {
11474 lappend DEFAULT_VECTCFLAGS
"-mvsx" "-mno-allow-movmisalign"
11477 if [check_vmx_hw_available
] {
11478 set dg
-do-what
-default run
11480 if [is
-effective
-target ilp32
] {
11481 # Specify a cpu that supports VMX
for compile-only tests.
11482 lappend DEFAULT_VECTCFLAGS
"-mcpu=970"
11484 set dg
-do-what
-default
compile
11486 } elseif
{ [istarget i?
86-*-*] ||
[istarget x86_64
-*-*] } {
11487 lappend DEFAULT_VECTCFLAGS
"-msse2"
11488 if { [check_effective_target_sse2_runtime
] } {
11489 set dg
-do-what
-default run
11491 set dg
-do-what
-default
compile
11493 } elseif
{ [istarget mips
*-*-*]
11494 && [check_effective_target_nomips16
] } {
11495 if { [check_effective_target_mpaired_single
"-mpaired-single"] } {
11496 lappend EFFECTIVE_TARGETS mpaired_single
11498 if { [check_effective_target_mips_loongson_mmi
"-mloongson-mmi"] } {
11499 lappend EFFECTIVE_TARGETS mips_loongson_mmi
11501 if { [check_effective_target_mips_msa
"-mmsa"] } {
11502 lappend EFFECTIVE_TARGETS mips_msa
11504 return [llength $EFFECTIVE_TARGETS
]
11505 } elseif
[istarget sparc
*-*-*] {
11506 lappend DEFAULT_VECTCFLAGS
"-mcpu=ultrasparc" "-mvis"
11507 if [check_effective_target_ultrasparc_hw
] {
11508 set dg
-do-what
-default run
11510 set dg
-do-what
-default
compile
11512 } elseif
[istarget alpha
*-*-*] {
11513 # Alpha
's vectorization capabilities are extremely limited.
11514 # It's more effort than its worth disabling all of the tests
11515 # that it cannot pass. But
if you actually want to see what
11516 # does work
, command out the
return.
11519 lappend DEFAULT_VECTCFLAGS
"-mmax"
11520 if [check_alpha_max_hw_available
] {
11521 set dg
-do-what
-default run
11523 set dg
-do-what
-default
compile
11525 } elseif
[istarget ia64
-*-*] {
11526 set dg
-do-what
-default run
11527 } elseif
[is
-effective
-target arm_neon_ok
] {
11528 eval lappend DEFAULT_VECTCFLAGS
[add_options_for_arm_neon
""]
11529 # NEON does not support denormals
, so is not used
for vectorization by
11530 # default to avoid loss of precision. We must pass
-ffast
-math to test
11531 # vectorization of float operations.
11532 lappend DEFAULT_VECTCFLAGS
"-ffast-math"
11533 if [is
-effective
-target arm_neon_hw
] {
11534 set dg
-do-what
-default run
11536 set dg
-do-what
-default
compile
11538 } elseif
[istarget aarch64
*-*-*] {
11539 set dg
-do-what
-default run
11540 } elseif
[istarget s390
*-*-*] {
11541 # The S
/390 backend
set a default of
2 for that value.
11542 # Override it to have the same situation as with other
11544 lappend DEFAULT_VECTCFLAGS
"--param" "min-vect-loop-bound=1"
11545 lappend DEFAULT_VECTCFLAGS
"--param" "max-unrolled-insns=200"
11546 lappend DEFAULT_VECTCFLAGS
"--param" "max-unroll-times=8"
11547 lappend DEFAULT_VECTCFLAGS
"--param" "max-completely-peeled-insns=200"
11548 lappend DEFAULT_VECTCFLAGS
"--param" "max-completely-peel-times=16"
11549 if [check_effective_target_s390_vxe2
] {
11550 lappend DEFAULT_VECTCFLAGS
"-march=z15" "-mzarch"
11551 set dg
-do-what
-default run
11552 } elseif
[check_effective_target_s390_vxe
] {
11553 lappend DEFAULT_VECTCFLAGS
"-march=z14" "-mzarch"
11554 set dg
-do-what
-default run
11555 } elseif
[check_effective_target_s390_vx
] {
11556 lappend DEFAULT_VECTCFLAGS
"-march=z13" "-mzarch"
11557 set dg
-do-what
-default run
11559 lappend DEFAULT_VECTCFLAGS
"-march=z14" "-mzarch"
11560 set dg
-do-what
-default
compile
11562 } elseif
[istarget amdgcn
-*-*] {
11563 set dg
-do-what
-default run
11564 } elseif
[istarget riscv64
-*-*] {
11565 if [check_effective_target_riscv_vector_hw
] {
11566 lappend DEFAULT_VECTCFLAGS
"--param" "riscv-autovec-preference=scalable"
11567 lappend DEFAULT_VECTCFLAGS
"--param" "riscv-vector-abi"
11568 set dg
-do-what
-default run
11570 lappend DEFAULT_VECTCFLAGS
"-march=rv64gcv_zvfh" "-mabi=lp64d"
11571 lappend DEFAULT_VECTCFLAGS
"--param" "riscv-autovec-preference=scalable"
11572 lappend DEFAULT_VECTCFLAGS
"--param" "riscv-vector-abi"
11573 set dg
-do-what
-default
compile
11575 } elseif
[istarget loongarch
*-*-*] {
11576 lappend DEFAULT_VECTCFLAGS
"-mdouble-float" "-mlasx"
11577 if [check_effective_target_loongarch_asx_hw
] {
11578 set dg
-do-what
-default run
11580 set dg
-do-what
-default
compile
11589 #
Return 1 if the target does
*not
* require strict alignment.
11591 proc check_effective_target_non_strict_align
{} {
11593 #
On ARM
, the default is to use STRICT_ALIGNMENT
, but there
11594 # are interfaces defined
for misaligned access and thus
11595 # depending
on the architecture levels unaligned access is
11597 if [istarget
"arm*-*-*"] {
11598 return [check_effective_target_arm_unaligned
]
11601 return [check_no_compiler_messages non_strict_align assembly
{
11603 typedef char __attribute__
((__aligned__
(__BIGGEST_ALIGNMENT__
))) c
;
11605 void foo
(void
) { z
= (c
*) y
; }
11609 #
Return 1 if the target supports
-mstrict
-align
(and
-mno
-strict
-align
).
11611 proc check_effective_target_opt_mstrict_align
{} {
11612 return [check_no_compiler_messages opt_mstrict_align assembly
{
11614 } "-mstrict-align -mno-strict-align"]
11617 #
Return 1 if the target has
<ucontext.h
>.
11619 proc check_effective_target_ucontext_h
{ } {
11620 return [check_no_compiler_messages ucontext_h assembly
{
11621 #
include <ucontext.h
>
11625 proc check_effective_target_aarch64_tiny
{ } {
11626 if { [istarget aarch64
*-*-*] } {
11627 return [check_no_compiler_messages aarch64_tiny object
{
11628 #ifdef __AARCH64_CMODEL_TINY__
11631 #error target not AArch64 tiny code
model
11639 # Create functions to check that the AArch64 assembler supports the
11640 # various architecture extensions via the .arch_extension pseudo
-op.
11642 foreach
{ aarch64_ext
} { "fp" "simd" "crypto" "crc" "lse" "dotprod" "sve"
11643 "i8mm" "f32mm" "f64mm" "bf16" "sb" "sve2" "ls64" } {
11644 eval
[string map
[list FUNC $aarch64_ext
] {
11645 proc check_effective_target_aarch64_asm_FUNC_ok
{ } {
11646 if { [istarget aarch64
*-*-*] } {
11647 return [check_no_compiler_messages aarch64_FUNC_assembler object
{
11648 __asm__
(".arch_extension FUNC");
11649 } "-march=armv8-a+FUNC"]
11657 proc check_effective_target_aarch64_small
{ } {
11658 if { [istarget aarch64
*-*-*] } {
11659 return [check_no_compiler_messages aarch64_small object
{
11660 #ifdef __AARCH64_CMODEL_SMALL__
11663 #error target not AArch64 small code
model
11671 proc check_effective_target_aarch64_large
{ } {
11672 if { [istarget aarch64
*-*-*] } {
11673 return [check_no_compiler_messages aarch64_large object
{
11674 #ifdef __AARCH64_CMODEL_LARGE__
11677 #error target not AArch64 large code
model
11685 #
Return 1 if the assembler accepts the aarch64 .variant_pcs directive.
11687 proc check_effective_target_aarch64_variant_pcs
{ } {
11688 if { [istarget aarch64
*-*-*] } {
11689 return [check_no_compiler_messages aarch64_variant_pcs object
{
11690 __asm__
(".variant_pcs foo");
11697 #
Return 1 if this is a reduced AVR Tiny core. Such cores have different
11698 # register
set, instruction
set, addressing capabilities and ABI.
11700 proc check_effective_target_avr_tiny
{ } {
11701 if { [istarget avr
*-*-*] } {
11702 return [check_no_compiler_messages avr_tiny object
{
11703 #ifdef __AVR_TINY__
11706 #error target not a reduced AVR Tiny core
11714 #
Return 1 if <fenv.h
> is available.
11716 proc check_effective_target_fenv
{} {
11717 return [check_no_compiler_messages fenv object
{
11719 } [add_options_for_ieee
"-std=gnu99"]]
11722 #
Return 1 if <fenv.h
> is available with all the standard IEEE
11723 # exceptions and floating
-point exceptions are raised by arithmetic
11724 # operations.
(If the target requires special options
for "inexact"
11725 # exceptions
, those need to be specified in the testcases.
)
11727 proc check_effective_target_fenv_exceptions
{} {
11728 return [check_runtime fenv_exceptions
{
11730 #
include <stdlib.h
>
11731 #ifndef FE_DIVBYZERO
11732 # error Missing FE_DIVBYZERO
11735 # error Missing FE_INEXACT
11738 # error Missing FE_INVALID
11740 #ifndef FE_OVERFLOW
11741 # error Missing FE_OVERFLOW
11743 #ifndef FE_UNDERFLOW
11744 # error Missing FE_UNDERFLOW
11746 volatile float a
= 0.0f
, r
;
11751 if (fetestexcept
(FE_INVALID
))
11756 } [add_options_for_ieee
"-std=gnu99"]]
11759 #
Return 1 if <fenv.h
> is available with all the standard IEEE
11760 # exceptions and floating
-point exceptions are raised by arithmetic
11761 # operations
for decimal floating point.
(If the target requires
11762 # special options
for "inexact" exceptions, those need to be specified
11763 # in the testcases.
)
11765 proc check_effective_target_fenv_exceptions_dfp
{} {
11766 return [check_runtime fenv_exceptions_dfp
{
11768 #
include <stdlib.h
>
11769 #ifndef FE_DIVBYZERO
11770 # error Missing FE_DIVBYZERO
11773 # error Missing FE_INEXACT
11776 # error Missing FE_INVALID
11778 #ifndef FE_OVERFLOW
11779 # error Missing FE_OVERFLOW
11781 #ifndef FE_UNDERFLOW
11782 # error Missing FE_UNDERFLOW
11784 volatile _Decimal64 a
= 0.0DD
, r
;
11789 if (fetestexcept
(FE_INVALID
))
11794 } [add_options_for_ieee
"-std=gnu99"]]
11797 #
Return 1 if <fenv.h
> is available with all the standard IEEE
11798 # exceptions and floating
-point exceptions are raised by arithmetic
11799 # operations.
(If the target requires special options
for "inexact"
11800 # exceptions
, those need to be specified in the testcases.
)
11802 proc check_effective_target_fenv_exceptions_double
{} {
11803 return [check_runtime fenv_exceptions_double
{
11805 #
include <stdlib.h
>
11806 #ifndef FE_DIVBYZERO
11807 # error Missing FE_DIVBYZERO
11810 # error Missing FE_INEXACT
11813 # error Missing FE_INVALID
11815 #ifndef FE_OVERFLOW
11816 # error Missing FE_OVERFLOW
11818 #ifndef FE_UNDERFLOW
11819 # error Missing FE_UNDERFLOW
11821 volatile double a
= 0.0f
, r
;
11826 if (fetestexcept
(FE_INVALID
))
11831 } [add_options_for_ieee
"-std=gnu99"]]
11834 #
Return 1 if <fenv.h
> is available with all the standard IEEE
11835 # exceptions and floating
-point exceptions are raised by arithmetic
11836 # operations.
(If the target requires special options
for "inexact"
11837 # exceptions
, those need to be specified in the testcases.
)
11839 proc check_effective_target_fenv_exceptions_long_double
{} {
11840 return [check_runtime fenv_exceptions_long_double
{
11842 #
include <stdlib.h
>
11843 #ifndef FE_DIVBYZERO
11844 # error Missing FE_DIVBYZERO
11847 # error Missing FE_INEXACT
11850 # error Missing FE_INVALID
11852 #ifndef FE_OVERFLOW
11853 # error Missing FE_OVERFLOW
11855 #ifndef FE_UNDERFLOW
11856 # error Missing FE_UNDERFLOW
11858 volatile long double a
= 0.0f
, r
;
11863 if (fetestexcept
(FE_INVALID
))
11868 } [add_options_for_ieee
"-std=gnu99"]]
11871 #
Return 1 if -fexceptions is supported.
11873 proc check_effective_target_exceptions
{} {
11874 if { [istarget amdgcn
*-*-*] } {
11880 # Used to check
if the testing configuration supports exceptions.
11881 # Returns
0 if exceptions are unsupported or disabled
(e.g. by passing
11882 #
-fno
-exceptions
). Returns
1 if exceptions are enabled.
11883 proc check_effective_target_exceptions_enabled
{} {
11884 return [check_cached_effective_target exceptions_enabled
{
11885 if { [check_effective_target_exceptions
] } {
11886 return [check_no_compiler_messages exceptions_enabled assembly
{
11894 #
If exceptions aren
't supported, then they're not enabled.
11900 proc check_effective_target_tiny
{} {
11901 return [check_cached_effective_target tiny
{
11902 if { [istarget aarch64
*-*-*]
11903 && [check_effective_target_aarch64_tiny
] } {
11906 if { [istarget avr
-*-*]
11907 && [check_effective_target_avr_tiny
] } {
11910 # PRU
Program Counter is
16-bits
, and trampolines are not supported.
11911 # Hence directly declare as a tiny target.
11912 if [istarget pru
-*-*] {
11919 #
Return 1 if the target supports
-mbranch
-cost
=N option.
11921 proc check_effective_target_branch_cost
{} {
11922 if { [ istarget arm
*-*-*]
11923 ||
[istarget avr
*-*-*]
11924 ||
[istarget csky
*-*-*]
11925 ||
[istarget epiphany
*-*-*]
11926 ||
[istarget frv
*-*-*]
11927 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
11928 ||
[istarget loongarch
*-*-*]
11929 ||
[istarget mips
*-*-*]
11930 ||
[istarget s390
*-*-*]
11931 ||
[istarget riscv
*-*-*]
11932 ||
[istarget sh
*-*-*] } {
11938 # Record that dg
-final test TEST requires convential compilation.
11940 proc set_required_options_for
{ test
} {
11941 if { [info proc $test
] == "" } {
11942 perror
"$test does not exist"
11945 proc $
{test
}_required_options
{} {
11946 global gcc_set_required_options
11947 upvar
1 extra_tool_flags extra_tool_flags
11948 if {[regexp
-- "^scan-assembler" [info level 0]]
11949 && ![string match
"*-fident*" $extra_tool_flags]} {
11950 #
Do not let .ident confuse assembler scan tests
11951 return [list $gcc_set_required_options
"-fno-ident"]
11953 return $gcc_set_required_options
11957 # Record that dg
-final test scan
-ltrans
-tree
-dump
* requires
-flto
-partition
=one
11958 # in order to force a single partition
, allowing scan
-ltrans
-tree
-dump
* to scan
11959 # a dump file
*.exe.ltrans0.
*.
11961 proc scan
-ltrans
-tree
-dump_required_options
{} {
11962 return "-flto-partition=one"
11964 proc scan
-ltrans
-tree
-dump
-times_required_options
{} {
11965 return "-flto-partition=one"
11967 proc scan
-ltrans
-tree
-dump
-not_required_options
{} {
11968 return "-flto-partition=one"
11970 proc scan
-ltrans
-tree
-dump
-dem_required_options
{} {
11971 return "-flto-partition=one"
11973 proc scan
-ltrans
-tree
-dump
-dem
-not_required_options
{} {
11974 return "-flto-partition=one"
11977 #
Return 1 if the x86
-64 target supports PIE with copy reloc
, 0
11978 # otherwise.
Cache the result.
11980 proc check_effective_target_pie_copyreloc
{ } {
11982 global GCC_UNDER_TEST
11984 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
11988 # Need auto
-host.h to check linker support.
11989 if { ![file
exists ..
/..
/auto
-host.h
] } {
11993 return [check_cached_effective_target pie_copyreloc
{
11994 #
Set up and
compile to see
if linker supports PIE with copy
11995 # reloc.
Include the current process ID in the file names to
11996 # prevent conflicts with invocations
for multiple testsuites.
12001 set f
[open $src
"w"]
12002 puts $f
"#include \"../../auto-host.h\""
12003 puts $f
"#if HAVE_LD_PIE_COPYRELOC == 0"
12004 puts $f
"# error Linker does not support PIE with copy reloc."
12008 verbose
"check_effective_target_pie_copyreloc compiling testfile $src" 2
12009 set lines
[$
{tool
}_target_compile $src $
obj object
""]
12014 if [string match
"" $lines] then {
12015 verbose
"check_effective_target_pie_copyreloc testfile compilation passed" 2
12018 verbose
"check_effective_target_pie_copyreloc testfile compilation failed" 2
12024 #
Return 1 if the x86 target supports R_386_GOT32X relocation
, 0
12025 # otherwise.
Cache the result.
12027 proc check_effective_target_got32x_reloc
{ } {
12029 global GCC_UNDER_TEST
12031 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
12035 # Need auto
-host.h to check linker support.
12036 if { ![file
exists ..
/..
/auto
-host.h
] } {
12040 return [check_cached_effective_target got32x_reloc
{
12041 #
Include the current process ID in the file names to prevent
12042 # conflicts with invocations
for multiple testsuites.
12044 set src got32x
[pid
].c
12045 set obj got32x
[pid
].o
12047 set f
[open $src
"w"]
12048 puts $f
"#include \"../../auto-host.h\""
12049 puts $f
"#if HAVE_AS_IX86_GOT32X == 0"
12050 puts $f
"# error Assembler does not support R_386_GOT32X."
12054 verbose
"check_effective_target_got32x_reloc compiling testfile $src" 2
12055 set lines
[$
{tool
}_target_compile $src $
obj object
""]
12060 if [string match
"" $lines] then {
12061 verbose
"check_effective_target_got32x_reloc testfile compilation passed" 2
12064 verbose
"check_effective_target_got32x_reloc testfile compilation failed" 2
12069 return $got32x_reloc_available_saved
12072 #
Return 1 if the x86 target supports calling ___tls_get_addr via GOT
,
12073 #
0 otherwise.
Cache the result.
12075 proc check_effective_target_tls_get_addr_via_got
{ } {
12077 global GCC_UNDER_TEST
12079 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
12083 # Need auto
-host.h to check linker support.
12084 if { ![file
exists ..
/..
/auto
-host.h
] } {
12088 return [check_cached_effective_target tls_get_addr_via_got
{
12089 #
Include the current process ID in the file names to prevent
12090 # conflicts with invocations
for multiple testsuites.
12092 set src tls_get_addr_via_got
[pid
].c
12093 set obj tls_get_addr_via_got
[pid
].o
12095 set f
[open $src
"w"]
12096 puts $f
"#include \"../../auto-host.h\""
12097 puts $f
"#if HAVE_AS_IX86_TLS_GET_ADDR_GOT == 0"
12098 puts $f
"# error Assembler/linker do not support calling ___tls_get_addr via GOT."
12102 verbose
"check_effective_target_tls_get_addr_via_got compiling testfile $src" 2
12103 set lines
[$
{tool
}_target_compile $src $
obj object
""]
12108 if [string match
"" $lines] then {
12109 verbose
"check_effective_target_tls_get_addr_via_got testfile compilation passed" 2
12112 verbose
"check_effective_target_tls_get_addr_via_got testfile compilation failed" 2
12118 #
Return 1 if the target uses comdat groups.
12120 proc check_effective_target_comdat_group
{} {
12121 return [check_no_messages_and_pattern comdat_group
"\.section\[^\n\r]*,comdat|\.group\[^\n\r]*,#comdat" assembly {
12123 inline
int foo
() { return 1; }
12124 int (*fn
) () = foo
;
12128 #
Return 1 if target supports __builtin_eh_return
12129 proc check_effective_target_builtin_eh_return
{ } {
12130 return [check_no_compiler_messages builtin_eh_return object
{
12131 void test
(long l
, void
*p
)
12133 __builtin_eh_return
(l
, p
);
12138 #
Return 1 if the target supports
max reduction
for vectors.
12140 proc check_effective_target_vect_max_reduc
{ } {
12141 if { [istarget aarch64
*-*-*] ||
[is
-effective
-target arm_neon
]
12142 ||
[check_effective_target_riscv_v
] } {
12148 #
Return 1 if the compiler has been configured with nvptx offloading.
12150 proc check_effective_target_offload_nvptx
{ } {
12151 return [check_no_compiler_messages offload_nvptx assembly
{
12152 int main
() {return 0;}
12153 } "-foffload=nvptx-none" ]
12156 #
Return 1 if the compiler has been configured with gcn offloading.
12158 proc check_effective_target_offload_gcn
{ } {
12159 return [check_no_compiler_messages offload_gcn assembly
{
12160 int main
() {return 0;}
12161 } "-foffload=amdgcn-amdhsa" ]
12164 #
Return 1 if the target support
-fprofile
-update=atomic
12165 proc check_effective_target_profile_update_atomic
{} {
12166 return [check_no_compiler_messages profile_update_atomic assembly
{
12167 int main
(void
) { return 0; }
12168 } "-fprofile-update=atomic -fprofile-generate"]
12171 #
Return 1 if vector
(va
- vector add
) instructions are understood by
12172 # the assembler and can be executed. This also covers checking
for
12173 # the VX kernel feature. A kernel without that feature does not
12174 # enable the vector facility and the following check will die with a
12176 proc check_effective_target_s390_vx
{ } {
12177 if ![istarget s390
*-*-*] then {
12181 return [check_runtime s390_check_vx
{
12184 asm
("va %%v24, %%v26, %%v28, 3" : : : "v24", "v26", "v28");
12187 } "-march=z13 -mzarch" ]
12190 # Same as above but
for the z14 vector enhancement facility. Test
12191 # is performed with the vector nand instruction.
12192 proc check_effective_target_s390_vxe
{ } {
12193 if ![istarget s390
*-*-*] then {
12197 return [check_runtime s390_check_vxe
{
12200 asm
("vnn %%v24, %%v26, %%v28" : : : "v24", "v26", "v28");
12203 } "-march=z14 -mzarch" ]
12206 # Same as above but
for the arch13 vector enhancement facility. Test
12207 # is performed with the vector shift left double by bit instruction.
12208 proc check_effective_target_s390_vxe2
{ } {
12209 if ![istarget s390
*-*-*] then {
12213 return [check_runtime s390_check_vxe2
{
12216 asm
("vsld %%v24, %%v26, %%v28, 3" : : : "v24", "v26", "v28");
12219 } "-march=arch13 -mzarch" ]
12222 # Same as above but
for the arch14 NNPA facility.
12223 proc check_effective_target_s390_nnpa
{ } {
12224 if ![istarget s390
*-*-*] then {
12228 return [check_runtime s390_check_nnpa
{
12231 asm
("vzero %%v24\n\t"
12232 "vcrnf %%v24,%%v24,%%v24,0,2" : : : "v24");
12235 } "-march=arch14 -mzarch" ]
12238 #
For versions of ARM architectures that have hardware div insn
,
12239 #disable the divmod transform
12241 proc check_effective_target_arm_divmod_simode
{ } {
12242 return [check_no_compiler_messages arm_divmod assembly
{
12243 #ifdef __ARM_ARCH_EXT_IDIV__
12244 #error has div insn
12250 #
Return 1 if target supports divmod hardware insn or divmod libcall.
12252 proc check_effective_target_divmod
{ } {
12253 #TODO
: Add checks
for all targets that have either hardware divmod insn
12254 # or
define libfunc
for divmod.
12255 if { [istarget arm
*-*-*]
12256 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
12257 ||
[istarget amdgcn
-*-*] } {
12263 #
Return 1 if target supports divmod
for SImode. The reason
for
12264 # separating this from check_effective_target_divmod is that
12265 # some versions of ARM architecture
define div instruction
12266 # only
for simode
, and
for these archs
, we
do not want to enable
12267 # divmod transform
for simode.
12269 proc check_effective_target_divmod_simode
{ } {
12270 if { [istarget arm
*-*-*] } {
12271 return [check_effective_target_arm_divmod_simode
]
12274 return [check_effective_target_divmod
]
12277 #
Return 1 if store merging optimization is applicable
for target.
12278 # Store merging is not profitable
for targets like the avr which
12279 # can
load/store only one byte at a time. Use
int size as a proxy
12280 #
for the number of bytes the target can write
, and skip
for targets
12281 # with a smallish
(< 32) size.
12283 proc check_effective_target_store_merge
{ } {
12284 if { [is
-effective
-target non_strict_align
] && [is
-effective
-target int32plus
] } {
12291 #
Return 1 if we
're able to assemble rdrand
12293 proc check_effective_target_rdrand { } {
12294 return [check_no_compiler_messages_nocache rdrand object {
12299 __builtin_ia32_rdrand32_step(&val);
12305 # Return 1 if the target supports coprocessor instructions: cdp, ldc, ldcl,
12306 # stc, stcl, mcr and mrc.
12307 proc check_effective_target_arm_coproc1_ok_nocache { } {
12308 if { ![istarget arm*-*-*] } {
12311 return [check_no_compiler_messages_nocache arm_coproc1_ok assembly {
12312 #if (__thumb__ && !__thumb2__) || __ARM_ARCH < 4
12315 #include <arm_acle.h>
12319 proc check_effective_target_arm_coproc1_ok { } {
12320 return [check_cached_effective_target arm_coproc1_ok \
12321 check_effective_target_arm_coproc1_ok_nocache]
12324 # Return 1 if the target supports all coprocessor instructions checked by
12325 # check_effective_target_arm_coproc1_ok in addition to the following: cdp2,
12326 # ldc2, ldc2l, stc2, stc2l, mcr2 and mrc2.
12327 proc check_effective_target_arm_coproc2_ok_nocache { } {
12328 if { ![check_effective_target_arm_coproc1_ok] } {
12331 return [check_no_compiler_messages_nocache arm_coproc2_ok assembly {
12332 #if (__thumb__ && !__thumb2__) || __ARM_ARCH < 5
12335 #include <arm_acle.h>
12339 proc check_effective_target_arm_coproc2_ok { } {
12340 return [check_cached_effective_target arm_coproc2_ok \
12341 check_effective_target_arm_coproc2_ok_nocache]
12344 # Return 1 if the target supports all coprocessor instructions checked by
12345 # check_effective_target_arm_coproc2_ok in addition the following: mcrr and
12347 proc check_effective_target_arm_coproc3_ok_nocache { } {
12348 if { ![check_effective_target_arm_coproc2_ok] } {
12351 return [check_no_compiler_messages_nocache arm_coproc3_ok assembly {
12352 #if (__thumb__ && !__thumb2__) \
12353 || (__ARM_ARCH < 6 && !defined (__ARM_ARCH_5TE__))
12356 #include <arm_acle.h>
12360 proc check_effective_target_arm_coproc3_ok { } {
12361 return [check_cached_effective_target arm_coproc3_ok \
12362 check_effective_target_arm_coproc3_ok_nocache]
12365 # Return 1 if the target supports all coprocessor instructions checked by
12366 # check_effective_target_arm_coproc3_ok in addition the following: mcrr2 and
12368 proc check_effective_target_arm_coproc4_ok_nocache { } {
12369 if { ![check_effective_target_arm_coproc3_ok] } {
12372 return [check_no_compiler_messages_nocache arm_coproc4_ok assembly {
12373 #if (__thumb__ && !__thumb2__) || __ARM_ARCH < 6
12376 #include <arm_acle.h>
12380 proc check_effective_target_arm_coproc4_ok { } {
12381 return [check_cached_effective_target arm_coproc4_ok \
12382 check_effective_target_arm_coproc4_ok_nocache]
12385 # Return 1 if the target supports the auto_inc_dec optimization pass.
12386 proc check_effective_target_autoincdec { } {
12387 if { ![check_no_compiler_messages auto_incdec assembly { void f () { }
12388 } "-O2 -fdump-rtl-auto_inc_dec" ] } {
12392 set dumpfile [glob -nocomplain "auto_incdec[pid].c.\[0-9\]\[0-9\]\[0-9\]r.auto_inc_dec"]
12393 if { [file exists $dumpfile ] } {
12394 file delete $dumpfile
12400 # Return 1 if the target has support for stack probing designed
12401 # to avoid stack-clash style attacks.
12403 # This is used to restrict the stack-clash mitigation tests to
12404 # just those targets that have been explicitly supported.
12406 # In addition to the prologue work on those targets, each target's
12407 # properties should be described in the functions below so that
12408 # tests
do not become a mess of unreadable target conditions.
12410 proc check_effective_target_supports_stack_clash_protection
{ } {
12412 if { [istarget x86_64
-*-*] ||
[istarget i?
86-*-*]
12413 ||
[istarget powerpc
*-*-*] ||
[istarget rs6000
*-*-*]
12414 ||
[istarget aarch64
*-**] ||
[istarget s390
*-*-*]
12415 ||
[istarget loongarch64
*-**] } {
12421 #
Return 1 if the target creates a frame pointer
for non
-leaf functions
12422 # Note we ignore cases where we apply tail
call optimization here.
12423 proc check_effective_target_frame_pointer_for_non_leaf
{ } {
12424 # Solaris
/x86 defaults to
-fno
-omit
-frame
-pointer.
12425 if { [istarget i?
86-*-solaris
*] ||
[istarget x86_64
-*-solaris
*] } {
12432 #
Return 1 if the target can perform tail
-call optimizations of the
12433 # most trivial type.
12434 proc check_effective_target_tail_call
{ } {
12435 return [check_no_messages_and_pattern tail_call
",SIBCALL" rtl-expand {
12436 __attribute__
((__noipa__
)) void foo
(void
) { }
12437 __attribute__
((__noipa__
)) void bar
(void
) { foo
(); }
12438 } {-O2
-fdump
-rtl
-expand
-all
}] ;# The
"SIBCALL" note requires a detailed dump.
12441 #
Return 1 if the target
's calling sequence or its ABI
12442 # create implicit stack probes at or prior to function entry.
12443 proc check_effective_target_caller_implicit_probes { } {
12445 # On x86/x86_64 the call instruction itself pushes the return
12446 # address onto the stack. That is an implicit probe of *sp.
12447 if { [istarget x86_64-*-*] || [istarget i?86-*-*] } {
12451 # On PPC, the ABI mandates that the address of the outer
12452 # frame be stored at *sp. Thus each allocation of stack
12453 # space is itself an implicit probe of *sp.
12454 if { [istarget powerpc*-*-*] || [istarget rs6000*-*-*] } {
12458 # s390's ABI has a register save area allocated by the
12459 # caller
for use by the callee. The mere existence does
12460 # not constitute a probe by the caller
, but when the slots
12461 # used by the callee those stores are implicit probes.
12462 if { [istarget s390
*-*-*] } {
12466 # Not strictly true
on aarch64
, but we have agreed that we will
12467 #
consider any function that pushes SP more than
3kbytes into
12468 # the guard
page as broken. This essentially means that we can
12469 #
consider the aarch64 as having a caller implicit probe at
12471 if { [istarget aarch64
*-*-*] } {
12475 if { [istarget loongarch64
*-*-*] } {
12482 # Targets that potentially realign the stack pointer often cause residual
12483 # stack allocations and make it difficult to elimination loops or residual
12484 # allocations
for dynamic stack allocations
12485 proc check_effective_target_callee_realigns_stack
{ } {
12486 if { [istarget x86_64
-*-*] ||
[istarget i?
86-*-*] } {
12492 #
Return 1 if CET instructions can be compiled.
12493 proc check_effective_target_cet
{ } {
12494 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
12497 return [check_no_compiler_messages cet object
{
12502 } "-O2 -fcf-protection" ]
12505 #
Return 1 if target supports floating point
"infinite"
12506 proc check_effective_target_inf
{ } {
12507 return [check_no_compiler_messages supports_inf assembly
{
12508 const double pinf
= __builtin_inf
();
12512 #
Return 1 if target supports floating point
"infinite" for float.
12513 proc check_effective_target_inff
{ } {
12514 return [check_no_compiler_messages supports_inff assembly
{
12515 const float pinf
= __builtin_inff
();
12519 #
Return 1 if the target supports ARMv8.3 Adv.SIMD Complex instructions
12520 # instructions
, 0 otherwise. The test is valid
for ARM and
for AArch64.
12521 # Record the command line options needed.
12523 proc check_effective_target_arm_v8_3a_complex_neon_ok_nocache
{ } {
12524 global et_arm_v8_3a_complex_neon_flags
12525 set et_arm_v8_3a_complex_neon_flags
""
12527 if { ![istarget arm
*-*-*] && ![istarget aarch64
*-*-*] } {
12531 # Iterate through sets of options to find the compiler flags that
12532 # need to be added to the
-march option.
12533 foreach flags
{"" "-mfloat-abi=softfp -mfpu=auto" "-mfloat-abi=hard -mfpu=auto"} {
12534 if { [check_no_compiler_messages_nocache \
12535 arm_v8_3a_complex_neon_ok assembly
{
12536 #
if !defined
(__ARM_FEATURE_COMPLEX
)
12537 #error
"__ARM_FEATURE_COMPLEX not defined"
12539 } "$flags -march=armv8.3-a"] } {
12540 set et_arm_v8_3a_complex_neon_flags
"$flags -march=armv8.3-a"
12548 proc check_effective_target_arm_v8_3a_complex_neon_ok
{ } {
12549 return [check_cached_effective_target arm_v8_3a_complex_neon_ok \
12550 check_effective_target_arm_v8_3a_complex_neon_ok_nocache
]
12553 proc add_options_for_arm_v8_3a_complex_neon
{ flags
} {
12554 if { ! [check_effective_target_arm_v8_3a_complex_neon_ok
] } {
12557 global et_arm_v8_3a_complex_neon_flags
12558 return "$flags $et_arm_v8_3a_complex_neon_flags"
12561 #
Return 1 if the target supports ARMv8.3 Adv.SIMD
+ FP16 Complex instructions
12562 # instructions
, 0 otherwise. The test is valid
for ARM and
for AArch64.
12563 # Record the command line options needed.
12565 proc check_effective_target_arm_v8_3a_fp16_complex_neon_ok_nocache
{ } {
12566 global et_arm_v8_3a_fp16_complex_neon_flags
12567 set et_arm_v8_3a_fp16_complex_neon_flags
""
12569 if { ![istarget arm
*-*-*] && ![istarget aarch64
*-*-*] } {
12573 # Iterate through sets of options to find the compiler flags that
12574 # need to be added to the
-march option.
12575 foreach flags
{"" "-mfloat-abi=softfp -mfpu=auto" "-mfloat-abi=hard -mfpu=auto"} {
12576 if { [check_no_compiler_messages_nocache \
12577 arm_v8_3a_fp16_complex_neon_ok assembly
{
12578 #
if !defined
(__ARM_FEATURE_COMPLEX
)
12579 #error
"__ARM_FEATURE_COMPLEX not defined"
12581 } "$flags -march=armv8.3-a+fp16"] } {
12582 set et_arm_v8_3a_fp16_complex_neon_flags \
12583 "$flags -march=armv8.3-a+fp16"
12591 proc check_effective_target_arm_v8_3a_fp16_complex_neon_ok
{ } {
12592 return [check_cached_effective_target arm_v8_3a_fp16_complex_neon_ok \
12593 check_effective_target_arm_v8_3a_fp16_complex_neon_ok_nocache
]
12596 proc add_options_for_arm_v8_3a_fp16_complex_neon
{ flags
} {
12597 if { ! [check_effective_target_arm_v8_3a_fp16_complex_neon_ok
] } {
12600 global et_arm_v8_3a_fp16_complex_neon_flags
12601 return "$flags $et_arm_v8_3a_fp16_complex_neon_flags"
12605 #
Return 1 if the target supports executing AdvSIMD instructions from ARMv8.3
12606 # with the complex instruction extension
, 0 otherwise. The test is valid
for
12607 # ARM and
for AArch64.
12609 proc check_effective_target_arm_v8_3a_complex_neon_hw
{ } {
12610 if { ![check_effective_target_arm_v8_3a_complex_neon_ok
] } {
12613 return [check_runtime arm_v8_3a_complex_neon_hw_available
{
12614 #
include "arm_neon.h"
12619 float32x2_t results
= {-4.0,5.0};
12620 float32x2_t a
= {1.0,3.0};
12621 float32x2_t b
= {2.0,5.0};
12623 #ifdef __ARM_ARCH_ISA_A64
12624 asm
("fcadd %0.2s, %1.2s, %2.2s, #90"
12627 : /* No clobbers.
*/);
12630 asm
("vcadd.f32 %P0, %P1, %P2, #90"
12633 : /* No clobbers.
*/);
12636 return (results
[0] == 8 && results
[1] == 24) ?
0 : 1;
12638 } [add_options_for_arm_v8_3a_complex_neon
""]]
12641 #
Return 1 if the assembler supports assembling the Armv8.3 pointer authentication B
key directive
12642 proc check_effective_target_arm_v8_3a_bkey_directive
{ } {
12643 return [check_no_compiler_messages cet object
{
12645 asm
(".cfi_b_key_frame");
12651 #
Return 1 if the target supports executing the Armv8.1
-M Mainline Low
12652 # Overhead Loop
, 0 otherwise. The test is valid
for ARM.
12654 proc check_effective_target_arm_v8_1_lob_ok
{ } {
12655 if { ![check_effective_target_arm_cortex_m
] } {
12658 return [check_runtime arm_v8_1_lob_hw_available
{
12662 asm
("movw r3, #10\n\t" /* movs? */
12663 "dls lr, r3" : : : "r3", "lr");
12666 asm
goto ("le lr, %l0" : : : "lr" : loop);
12669 } "-march=armv8.1-m.main -mthumb" ]
12673 #
Return 1 if this is an ARM target where Thumb
-2 is used without
12674 # options added by the test and the target does not support executing
12675 # the Armv8.1
-M Mainline Low Overhead Loop
, 0 otherwise. The test is
12678 proc check_effective_target_arm_thumb2_no_arm_v8_1_lob
{ } {
12679 if { [check_effective_target_arm_thumb2
]
12680 && ![check_effective_target_arm_v8_1_lob_ok
] } {
12686 #
Return 1 if this is an ARM target where
-mthumb causes Thumb
-2 to be
12687 # used and the target does not support executing the Armv8.1
-M
12688 # Mainline Low Overhead Loop
, 0 otherwise. The test is valid
for ARM.
12690 proc check_effective_target_arm_thumb2_ok_no_arm_v8_1_lob
{ } {
12691 if { [check_effective_target_arm_thumb2_ok
]
12692 && ![check_effective_target_arm_v8_1_lob_ok
] } {
12698 # Returns
1 if the target is using glibc
, 0 otherwise.
12700 proc check_effective_target_glibc
{ } {
12701 return [check_no_compiler_messages glibc_object assembly
{
12702 #
include <stdlib.h
>
12703 #
if !defined
(__GLIBC__
)
12709 #
Return 1 if the target plus current options supports a vector
12710 # complex addition with rotate of half and single float modes
, 0 otherwise.
12712 # This won
't change for different subtargets so cache the result.
12714 foreach N {hf sf} {
12715 eval [string map [list N $N] {
12716 proc check_effective_target_vect_complex_rot_N { } {
12717 return [check_cached_effective_target_indexed vect_complex_rot_N {
12718 expr { [istarget aarch64*-*-*]
12719 || [istarget arm*-*-*] }}]
12724 # Return 1 if the target plus current options supports a vector
12725 # complex addition with rotate of double float modes, 0 otherwise.
12727 # This won't change
for different subtargets so
cache the result.
12730 eval
[string map
[list N $N
] {
12731 proc check_effective_target_vect_complex_rot_N
{ } {
12732 return [check_cached_effective_target_indexed vect_complex_rot_N
{
12733 expr
{ [istarget aarch64
*-*-*] }}]
12738 #
Return 1 if this target uses an LLVM assembler and
/or linker
12739 proc check_effective_target_llvm_binutils
{ } {
12740 return [check_cached_effective_target llvm_binutils
{
12741 expr
{ [istarget amdgcn
*-*-*]
12742 ||
[check_effective_target_offload_gcn
] }}]
12745 #
Return 1 if the compiler supports
'-mfentry'.
12747 proc check_effective_target_mfentry
{ } {
12748 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
12751 return [check_no_compiler_messages mfentry object
{
12752 void foo
(void
) { }
12756 #
Return 1 if this target supports indirect calls
12757 proc check_effective_target_indirect_calls
{ } {
12758 if { [istarget bpf
-*-*] } {
12764 #
Return 1 if we can use the
-lgccjit option
, 0 otherwise.
12766 proc check_effective_target_lgccjit
{ } {
12767 if { [info procs jit_target_compile
] == "" } then {
12768 global GCC_UNDER_TEST
12769 if ![info exists GCC_UNDER_TEST
] {
12770 set GCC_UNDER_TEST
"[find_gcc]"
12772 proc jit_target_compile
{ source dest type options
} [info body gcc_target_compile
]
12774 return [check_no_compiler_messages lgccjit executable
{
12775 int main
() { return 0; }
12779 #
Return 1 if the MSP430 small memory
model is in use.
12780 proc check_effective_target_msp430_small
{} {
12781 return [check_no_compiler_messages msp430_small assembly
{
12782 #
if (!defined __MSP430__ || defined __MSP430X_LARGE__
)
12783 #error
!msp430 || __MSP430X_LARGE__
12788 #
Return 1 if the MSP430 large memory
model is in use.
12789 proc check_effective_target_msp430_large
{} {
12790 return [check_no_compiler_messages msp430_large assembly
{
12791 #ifndef __MSP430X_LARGE__
12792 #error __MSP430X_LARGE__
12797 #
Return 1 if GCC was configured with
--with
-tune
=cortex
-a76
12798 proc check_effective_target_tune_cortex_a76
{ } {
12799 return [check_configured_with
"with-tune=cortex-a76"]
12802 #
Return 1 if the target has an efficient means to encode large initializers
12805 proc check_effective_target_large_initializer
{ } {
12806 if { [istarget nvptx
*-*-*] } {
12813 #
Return 1 if the target allows function prototype mismatches
12816 proc check_effective_target_non_strict_prototype
{ } {
12817 if { [istarget nvptx
*-*-*] } {
12824 # Returns
1 if the target toolchain supports extended
12825 # syntax of .symver directive
, 0 otherwise.
12827 proc check_symver_available
{ } {
12828 return [check_no_compiler_messages symver_available object
{
12829 int foo
(void
) { return 0; }
12831 asm volatile
(".symver foo,foo@VER_1, local");
12837 #
Return 1 if emitted assembly contains .ident directive.
12839 proc check_effective_target_ident_directive
{} {
12840 return [check_no_messages_and_pattern ident_directive \
12841 "(?n)^\[\t\]+\\.ident" assembly {
12846 #
Return 1 if we
're able to assemble movdiri and movdir64b
12848 proc check_effective_target_movdir { } {
12849 return [check_no_compiler_messages movdir object {
12851 foo (unsigned int *d, unsigned int s)
12853 __builtin_ia32_directstoreu_u32 (d, s);
12856 bar (void *d, const void *s)
12858 __builtin_ia32_movdir64b (d, s);
12860 } "-mmovdiri -mmovdir64b" ]
12863 # Return 1 if the target does not support address sanitizer, 0 otherwise
12865 proc check_effective_target_no_fsanitize_address {} {
12866 if ![check_no_compiler_messages fsanitize_address executable {
12867 int main (void) { return 0; }
12868 } "-fsanitize=address" ] {
12875 # Return 1 if this target supports 'R
' flag in .section directive, 0
12876 # otherwise. Cache the result.
12878 proc check_effective_target_R_flag_in_section { } {
12880 global GCC_UNDER_TEST
12882 # Need auto-host.h to check linker support.
12883 if { ![file exists ../../auto-host.h ] } {
12887 return [check_cached_effective_target R_flag_in_section {
12892 set f [open $src "w"]
12893 puts $f "#include \"../../auto-host.h\""
12894 puts $f "#if HAVE_GAS_SHF_GNU_RETAIN == 0 || HAVE_INITFINI_ARRAY_SUPPORT == 0"
12895 puts $f "# error Assembler does not support 'R
' flag in .section directive."
12899 verbose "check_effective_target_R_flag_in_section compiling testfile $src" 2
12900 set lines [${tool}_target_compile $src $obj assembly ""]
12905 if [string match "" $lines] then {
12906 verbose "check_effective_target_R_flag_in_section testfile compilation passed" 2
12909 verbose "check_effective_target_R_flag_in_section testfile compilation failed" 2
12915 # Return 1 if this target supports 'o
' flag in .section directive, 0
12916 # otherwise. Cache the result.
12918 proc check_effective_target_o_flag_in_section { } {
12920 global GCC_UNDER_TEST
12922 # Need auto-host.h to check linker support.
12923 if { ![file exists ../../auto-host.h ] } {
12927 return [check_cached_effective_target o_flag_in_section {
12932 set f [open $src "w"]
12933 puts $f "#include \"../../auto-host.h\""
12934 puts $f "#if HAVE_GAS_SECTION_LINK_ORDER == 0"
12935 puts $f "# error Assembler does not support 'o
' flag in .section directive."
12939 verbose "check_effective_target_o_flag_in_section compiling testfile $src" 2
12940 set lines [${tool}_target_compile $src $obj object ""]
12945 if [string match "" $lines] then {
12946 verbose "check_effective_target_o_flag_in_section testfile compilation passed" 2
12949 verbose "check_effective_target_o_flag_in_section testfile compilation failed" 2
12955 # Return 1 if the given assembler supports hardware transactional memory
12956 # instructions with machine type Power10, 0 otherwise. Cache the result.
12958 proc check_effective_target_powerpc_as_p10_htm { } {
12960 global GCC_UNDER_TEST
12962 # Need auto-host.h to check linker support.
12963 if { ![file exists ../../auto-host.h ] } {
12967 return [check_cached_effective_target powerpc_as_p10_htm {
12972 set f [open $src "w"]
12973 puts $f "#include \"../../auto-host.h\""
12974 puts $f "#if HAVE_AS_POWER10_HTM == 0"
12975 puts $f "# error Assembler does not support htm insns with power10."
12979 verbose "check_effective_target_powerpc_as_p10_htm compiling testfile $src" 2
12980 set lines [${tool}_target_compile $src $obj object ""]
12985 if [string match "" $lines] then {
12986 verbose "check_effective_target_powerpc_as_p10_htm testfile compilation passed" 2
12989 verbose "check_effective_target_powerpc_as_p10_htm testfile compilation failed" 2
12995 # return 1 if LRA is supported.
12997 proc check_effective_target_lra { } {
12998 if { [istarget hppa*-*-*] || [istarget avr-*-*] } {
13004 # Test whether optimizations are enabled ('__OPTIMIZE__
') per the
13005 # 'current_compiler_flags
' (thus don't
cache).
13007 proc check_effective_target___OPTIMIZE__
{} {
13008 return [check_no_compiler_messages_nocache __OPTIMIZE__ assembly
{
13009 #ifndef __OPTIMIZE__
13012 /* Avoid pedwarn about empty TU.
*/
13014 } [current_compiler_flags
]]
13017 #
Return 1 if python3
(>= 3.6) is available.
13019 proc check_effective_target_recent_python3
{ } {
13020 set result
[remote_exec host
"python3 -c \"import sys; assert sys.version_info >= (3, 6)\""]
13021 set status [lindex $result
0]
13022 if { $
status == 0 } then {
13029 #
Return 1 if python3 contains a module
13031 proc check_effective_target_python3_module
{ module
} {
13032 set result
[remote_exec host
"python3 -c \"import $module\""]
13033 set status [lindex $result
0]
13034 if { $
status == 0 } then {
13041 #
Return 1 if pytest module is available
for python3.
13043 proc check_effective_target_pytest3
{ } {
13044 set result
[remote_exec host
"python3 -m pytest --color=no -rap -s --tb=no --version"]
13045 set status [lindex $result
0]
13046 if { $
status == 0 } then {
13053 proc check_effective_target_property_1_needed
{ } {
13054 return [check_no_compiler_messages property_1_needed executable
{
13055 /* Assembly code
*/
13057 #
define __PROPERTY_ALIGN
3
13059 #
define __PROPERTY_ALIGN
2
13062 .section
".note.gnu.property", "a"
13063 .p2align __PROPERTY_ALIGN
13064 .long
1f
- 0f
/* name length.
*/
13065 .long
4f
- 1f
/* data length.
*/
13066 /* NT_GNU_PROPERTY_TYPE_0.
*/
13067 .long
5 /* note type.
*/
13069 .asciz
"GNU" /* vendor name. */
13071 .p2align __PROPERTY_ALIGN
13072 /* GNU_PROPERTY_1_NEEDED.
*/
13073 .long
0xb0008000 /* pr_type.
*/
13074 .long
3f
- 2f
/* pr_datasz.
*/
13076 /* GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS.
*/
13079 .p2align __PROPERTY_ALIGN
13088 #
Return 1 if this target has prog named
"$prog", 0 otherwise.
13090 proc check_is_prog_name_available
{ prog
} {
13093 set options
[list
"additional_flags=-print-prog-name=$prog"]
13094 set output
[lindex
[$
{tool
}_target_compile
"" "" "none" $options] 0]
13096 if { $output
== $prog
} {
13103 # returns
1 if target does selects a readonly section
for const volatile variables.
13104 proc check_effective_target_const_volatile_readonly_section
{ } {
13106 if { [istarget powerpc
-*-*]
13107 ||
[check
-flags
{ "" { powerpc64-*-* } { -m32 } }] } {
13113 #
Return 1 if the CORE
-V MAC extension is available.
13114 proc check_effective_target_cv_mac
{ } {
13115 if { !([istarget riscv
*-*-*]) } {
13118 return [check_no_compiler_messages cv_mac object
{
13121 asm
("cv.mac t0, t1, t2");
13123 } "-march=rv32i_xcvmac" ]
13126 #
Return 1 if the CORE
-V ALU extension is available.
13127 proc check_effective_target_cv_alu
{ } {
13128 if { !([istarget riscv
*-*-*]) } {
13131 return [check_no_compiler_messages cv_alu object
{
13134 asm
("cv.addn t0, t1, t2, 0");
13136 } "-march=rv32i_xcvalu" ]
13139 proc check_effective_target_loongarch_sx
{ } {
13140 return [check_no_compiler_messages loongarch_lsx assembly
{
13141 #
if !defined
(__loongarch_sx
)
13142 #error
"LSX not defined"
13147 proc check_effective_target_loongarch_sx_hw
{ } {
13148 return [check_runtime loongarch_sx_hw
{
13149 #
include <lsxintrin.h
>
13153 c
= __lsx_vand_v
(a
, b
);
13159 proc check_effective_target_loongarch_asx
{ } {
13160 return [check_no_compiler_messages loongarch_asx assembly
{
13161 #
if !defined
(__loongarch_asx
)
13162 #error
"LASX not defined"
13167 proc check_effective_target_loongarch_asx_hw
{ } {
13168 return [check_runtime loongarch_asx_hw
{
13169 #
include <lasxintrin.h
>
13173 c
= __lasx_xvand_v
(a
, b
);
13179 # Check whether LoongArch binutils supports call36 relocation.
13180 proc check_effective_target_loongarch_call36_support
{ } {
13181 return [check_no_compiler_messages loongarch_call36_support object
{
13182 /* Assembly code
*/
13183 pcaddu18i $r1
,%call36
(a
)
13188 # Appends necessary Python flags to extra
-tool
-flags
if Python.h is supported.
13189 # Otherwise
, modifies dg
-do-what.
13190 proc dg
-require
-python
-h
{ args } {
13191 upvar dg
-extra
-tool
-flags extra
-tool
-flags
13193 verbose
"ENTER dg-require-python-h" 2
13196 set result
[remote_exec host
"python3-config --includes"]
13197 set status [lindex $result
0]
13198 if { $
status == 0 } {
13199 # Remove trailing newline from python3
-config output.
13200 set python_flags
[string trim
[lindex $result
1]]
13201 if [check_no_compiler_messages python_h assembly
{
13202 #
include <Python.h
>
13203 int main
(void
) { return 0; }
13209 if { $supported
== 0 } {
13210 verbose
"Python.h not supported" 2
13211 upvar dg
-do-what dg
-do-what
13212 set dg
-do-what
[list
[lindex $
{dg
-do-what
} 0] "N" "P"]
13216 verbose
"Python flags are: $python_flags" 2
13218 verbose
"Before appending, extra-tool-flags: ${extra-tool-flags}" 3
13219 eval lappend extra
-tool
-flags $python_flags
13220 verbose
"After appending, extra-tool-flags: ${extra-tool-flags}" 3