gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
   3    1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
   4    Free Software Foundation, Inc.
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify it under
   9 the terms of the GNU General Public License as published by the Free
  10 Software Foundation; either version 3, or (at your option) any later
  11 version.
  12
  13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16 for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 /* This module is essentially the "combiner" phase of the U. of Arizona
  23    Portable Optimizer, but redone to work on our list-structured
  24    representation for RTL instead of their string representation.
  25
  26    The LOG_LINKS of each insn identify the most recent assignment
  27    to each REG used in the insn.  It is a list of previous insns,
  28    each of which contains a SET for a REG that is used in this insn
  29    and not used or set in between.  LOG_LINKs never cross basic blocks.
  30    They were set up by the preceding pass (lifetime analysis).
  31
  32    We try to combine each pair of insns joined by a logical link.
  33    We also try to combine triples of insns A, B and C when
  34    C has a link back to B and B has a link back to A.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information isn't
  53    completely updated (however this is only a local issue since it is
  54    regenerated before the next pass that uses it):
  55
  56    - reg_live_length is not updated
  57    - reg_n_refs is not adjusted in the rare case when a register is
  58      no longer required in a computation
  59    - there are extremely rare cases (see distribute_notes) when a
  60      REG_DEAD note is lost
  61    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  62      removed because there is no way to know which register it was
  63      linking
  64
  65    To simplify substitution, we combine only when the earlier insn(s)
  66    consist of only a single assignment.  To simplify updating afterward,
  67    we never combine when a subroutine call appears in the middle.
  68
  69    Since we do not represent assignments to CC0 explicitly except when that
  70    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  71    the condition code for the insn that set the condition code.
  72    Fortunately, these two insns must be consecutive.
  73    Therefore, every JUMP_INSN is taken to have an implicit logical link
  74    to the preceding insn.  This is not quite right, since non-jumps can
  75    also use the condition code; but in practice such insns would not
  76    combine anyway.  */
  77
  78 #include "config.h"
  79 #include "system.h"
  80 #include "coretypes.h"
  81 #include "tm.h"
  82 #include "rtl.h"
  83 #include "tree.h"
  84 #include "tm_p.h"
  85 #include "flags.h"
  86 #include "regs.h"
  87 #include "hard-reg-set.h"
  88 #include "basic-block.h"
  89 #include "insn-config.h"
  90 #include "function.h"
  91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
  92 #include "expr.h"
  93 #include "insn-attr.h"
  94 #include "recog.h"
  95 #include "real.h"
  96 #include "toplev.h"
  97 #include "target.h"
  98 #include "optabs.h"
  99 #include "insn-codes.h"
 100 #include "rtlhooks-def.h"
 101 /* Include output.h for dump_file.  */
 102 #include "output.h"
 103 #include "params.h"
 104 #include "timevar.h"
 105 #include "tree-pass.h"
 106 #include "df.h"
 107 #include "cgraph.h"
 108
 109 /* Number of attempts to combine instructions in this function.  */
 110
 111 static int combine_attempts;
 112
 113 /* Number of attempts that got as far as substitution in this function.  */
 114
 115 static int combine_merges;
 116
 117 /* Number of instructions combined with added SETs in this function.  */
 118
 119 static int combine_extras;
 120
 121 /* Number of instructions combined in this function.  */
 122
 123 static int combine_successes;
 124
 125 /* Totals over entire compilation.  */
 126
 127 static int total_attempts, total_merges, total_extras, total_successes;
 128
 129 /* combine_instructions may try to replace the right hand side of the
 130    second instruction with the value of an associated REG_EQUAL note
 131    before throwing it at try_combine.  That is problematic when there
 132    is a REG_DEAD note for a register used in the old right hand side
 133    and can cause distribute_notes to do wrong things.  This is the
 134    second instruction if it has been so modified, null otherwise.  */
 135
 136 static rtx i2mod;
 137
 138 /* When I2MOD is nonnull, this is a copy of the old right hand side.  */
 139
 140 static rtx i2mod_old_rhs;
 141
 142 /* When I2MOD is nonnull, this is a copy of the new right hand side.  */
 143
 144 static rtx i2mod_new_rhs;
 145 \f
 146 typedef struct reg_stat_struct {
 147   /* Record last point of death of (hard or pseudo) register n.  */
 148   rtx                           last_death;
 149
 150   /* Record last point of modification of (hard or pseudo) register n.  */
 151   rtx                           last_set;
 152
 153   /* The next group of fields allows the recording of the last value assigned
 154      to (hard or pseudo) register n.  We use this information to see if an
 155      operation being processed is redundant given a prior operation performed
 156      on the register.  For example, an `and' with a constant is redundant if
 157      all the zero bits are already known to be turned off.
 158
 159      We use an approach similar to that used by cse, but change it in the
 160      following ways:
 161
 162      (1) We do not want to reinitialize at each label.
 163      (2) It is useful, but not critical, to know the actual value assigned
 164          to a register.  Often just its form is helpful.
 165
 166      Therefore, we maintain the following fields:
 167
 168      last_set_value             the last value assigned
 169      last_set_label             records the value of label_tick when the
 170                                 register was assigned
 171      last_set_table_tick        records the value of label_tick when a
 172                                 value using the register is assigned
 173      last_set_invalid           set to nonzero when it is not valid
 174                                 to use the value of this register in some
 175                                 register's value
 176
 177      To understand the usage of these tables, it is important to understand
 178      the distinction between the value in last_set_value being valid and
 179      the register being validly contained in some other expression in the
 180      table.
 181
 182      (The next two parameters are out of date).
 183
 184      reg_stat[i].last_set_value is valid if it is nonzero, and either
 185      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 186
 187      Register I may validly appear in any expression returned for the value
 188      of another register if reg_n_sets[i] is 1.  It may also appear in the
 189      value for register J if reg_stat[j].last_set_invalid is zero, or
 190      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 191
 192      If an expression is found in the table containing a register which may
 193      not validly appear in an expression, the register is replaced by
 194      something that won't match, (clobber (const_int 0)).  */
 195
 196   /* Record last value assigned to (hard or pseudo) register n.  */
 197
 198   rtx                           last_set_value;
 199
 200   /* Record the value of label_tick when an expression involving register n
 201      is placed in last_set_value.  */
 202
 203   int                           last_set_table_tick;
 204
 205   /* Record the value of label_tick when the value for register n is placed in
 206      last_set_value.  */
 207
 208   int                           last_set_label;
 209
 210   /* These fields are maintained in parallel with last_set_value and are
 211      used to store the mode in which the register was last set, the bits
 212      that were known to be zero when it was last set, and the number of
 213      sign bits copies it was known to have when it was last set.  */
 214
 215   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 216   char                          last_set_sign_bit_copies;
 217   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 218
 219   /* Set nonzero if references to register n in expressions should not be
 220      used.  last_set_invalid is set nonzero when this register is being
 221      assigned to and last_set_table_tick == label_tick.  */
 222
 223   char                          last_set_invalid;
 224
 225   /* Some registers that are set more than once and used in more than one
 226      basic block are nevertheless always set in similar ways.  For example,
 227      a QImode register may be loaded from memory in two places on a machine
 228      where byte loads zero extend.
 229
 230      We record in the following fields if a register has some leading bits
 231      that are always equal to the sign bit, and what we know about the
 232      nonzero bits of a register, specifically which bits are known to be
 233      zero.
 234
 235      If an entry is zero, it means that we don't know anything special.  */
 236
 237   unsigned char                 sign_bit_copies;
 238
 239   unsigned HOST_WIDE_INT        nonzero_bits;
 240
 241   /* Record the value of the label_tick when the last truncation
 242      happened.  The field truncated_to_mode is only valid if
 243      truncation_label == label_tick.  */
 244
 245   int                           truncation_label;
 246
 247   /* Record the last truncation seen for this register.  If truncation
 248      is not a nop to this mode we might be able to save an explicit
 249      truncation if we know that value already contains a truncated
 250      value.  */
 251
 252   ENUM_BITFIELD(machine_mode)   truncated_to_mode : 8;
 253 } reg_stat_type;
 254
 255 DEF_VEC_O(reg_stat_type);
 256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
 257
 258 static VEC(reg_stat_type,heap) *reg_stat;
 259
 260 /* Record the luid of the last insn that invalidated memory
 261    (anything that writes memory, and subroutine calls, but not pushes).  */
 262
 263 static int mem_last_set;
 264
 265 /* Record the luid of the last CALL_INSN
 266    so we can tell whether a potential combination crosses any calls.  */
 267
 268 static int last_call_luid;
 269
 270 /* When `subst' is called, this is the insn that is being modified
 271    (by combining in a previous insn).  The PATTERN of this insn
 272    is still the old pattern partially modified and it should not be
 273    looked at, but this may be used to examine the successors of the insn
 274    to judge whether a simplification is valid.  */
 275
 276 static rtx subst_insn;
 277
 278 /* This is the lowest LUID that `subst' is currently dealing with.
 279    get_last_value will not return a value if the register was set at or
 280    after this LUID.  If not for this mechanism, we could get confused if
 281    I2 or I1 in try_combine were an insn that used the old value of a register
 282    to obtain a new value.  In that case, we might erroneously get the
 283    new value of the register when we wanted the old one.  */
 284
 285 static int subst_low_luid;
 286
 287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 288    must consider all these registers to be always live.  */
 289
 290 static HARD_REG_SET newpat_used_regs;
 291
 292 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 293    insn is the earlier than I2 or I3, combine should rescan starting at
 294    that location.  */
 295
 296 static rtx added_links_insn;
 297
 298 /* Basic block in which we are performing combines.  */
 299 static basic_block this_basic_block;
 300
 301 \f
 302 /* Length of the currently allocated uid_insn_cost array.  */
 303
 304 static int max_uid_known;
 305
 306 /* The following array records the insn_rtx_cost for every insn
 307    in the instruction stream.  */
 308
 309 static int *uid_insn_cost;
 310
 311 /* The following array records the LOG_LINKS for every insn in the
 312    instruction stream as an INSN_LIST rtx.  */
 313
 314 static rtx *uid_log_links;
 315
 316 #define INSN_COST(INSN)         (uid_insn_cost[INSN_UID (INSN)])
 317 #define LOG_LINKS(INSN)         (uid_log_links[INSN_UID (INSN)])
 318
 319 /* Incremented for each basic block.  */
 320
 321 static int label_tick;
 322
 323 /* Reset to label_tick for each label.  */
 324
 325 static int label_tick_ebb_start;
 326
 327 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 328    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 329
 330 static enum machine_mode nonzero_bits_mode;
 331
 332 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 333    be safely used.  It is zero while computing them and after combine has
 334    completed.  This former test prevents propagating values based on
 335    previously set values, which can be incorrect if a variable is modified
 336    in a loop.  */
 337
 338 static int nonzero_sign_valid;
 339
 340 \f
 341 /* Record one modification to rtl structure
 342    to be undone by storing old_contents into *where.  */
 343
 344 struct undo
 345 {
 346   struct undo *next;
 347   enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind;
 348   union { rtx r; int i; enum machine_mode m; } old_contents;
 349   union { rtx *r; int *i; } where;
 350 };
 351
 352 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 353    num_undo says how many are currently recorded.
 354
 355    other_insn is nonzero if we have modified some other insn in the process
 356    of working on subst_insn.  It must be verified too.  */
 357
 358 struct undobuf
 359 {
 360   struct undo *undos;
 361   struct undo *frees;
 362   rtx other_insn;
 363 };
 364
 365 static struct undobuf undobuf;
 366
 367 /* Number of times the pseudo being substituted for
 368    was found and replaced.  */
 369
 370 static int n_occurrences;
 371
 372 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
 373                                          enum machine_mode,
 374                                          unsigned HOST_WIDE_INT,
 375                                          unsigned HOST_WIDE_INT *);
 376 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
 377                                                 enum machine_mode,
 378                                                 unsigned int, unsigned int *);
 379 static void do_SUBST (rtx *, rtx);
 380 static void do_SUBST_INT (int *, int);
 381 static void init_reg_last (void);
 382 static void setup_incoming_promotions (rtx);
 383 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
 384 static int cant_combine_insn_p (rtx);
 385 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
 386 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
 387 static int contains_muldiv (rtx);
 388 static rtx try_combine (rtx, rtx, rtx, int *);
 389 static void undo_all (void);
 390 static void undo_commit (void);
 391 static rtx *find_split_point (rtx *, rtx);
 392 static rtx subst (rtx, rtx, rtx, int, int);
 393 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
 394 static rtx simplify_if_then_else (rtx);
 395 static rtx simplify_set (rtx);
 396 static rtx simplify_logical (rtx);
 397 static rtx expand_compound_operation (rtx);
 398 static const_rtx expand_field_assignment (const_rtx);
 399 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
 400                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 401 static rtx extract_left_shift (rtx, int);
 402 static rtx make_compound_operation (rtx, enum rtx_code);
 403 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 404                               unsigned HOST_WIDE_INT *);
 405 static rtx canon_reg_for_combine (rtx, rtx);
 406 static rtx force_to_mode (rtx, enum machine_mode,
 407                           unsigned HOST_WIDE_INT, int);
 408 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 409 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 410 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 411 static rtx make_field_assignment (rtx);
 412 static rtx apply_distributive_law (rtx);
 413 static rtx distribute_and_simplify_rtx (rtx, int);
 414 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
 415                                      unsigned HOST_WIDE_INT);
 416 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
 417                                    unsigned HOST_WIDE_INT);
 418 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 419                             HOST_WIDE_INT, enum machine_mode, int *);
 420 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
 421 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
 422                                  int);
 423 static int recog_for_combine (rtx *, rtx, rtx *);
 424 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
 425 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 426 static void update_table_tick (rtx);
 427 static void record_value_for_reg (rtx, rtx, rtx);
 428 static void check_conversions (rtx, rtx);
 429 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
 430 static void record_dead_and_set_regs (rtx);
 431 static int get_last_value_validate (rtx *, rtx, int, int);
 432 static rtx get_last_value (const_rtx);
 433 static int use_crosses_set_p (const_rtx, int);
 434 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
 435 static int reg_dead_at_p (rtx, rtx);
 436 static void move_deaths (rtx, rtx, int, rtx, rtx *);
 437 static int reg_bitfield_target_p (rtx, rtx);
 438 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
 439 static void distribute_links (rtx);
 440 static void mark_used_regs_combine (rtx);
 441 static void record_promoted_value (rtx, rtx);
 442 static int unmentioned_reg_p_1 (rtx *, void *);
 443 static bool unmentioned_reg_p (rtx, rtx);
 444 static void record_truncated_value (rtx);
 445 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
 446 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
 447 \f
 448
 449 /* It is not safe to use ordinary gen_lowpart in combine.
 450    See comments in gen_lowpart_for_combine.  */
 451 #undef RTL_HOOKS_GEN_LOWPART
 452 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 453
 454 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 455 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 456 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 457
 458 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 459 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 460
 461 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 462 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 463
 464 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
 465 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE    reg_truncated_to_mode
 466
 467 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 468
 469 \f
 470 /* Try to split PATTERN found in INSN.  This returns NULL_RTX if
 471    PATTERN can not be split.  Otherwise, it returns an insn sequence.
 472    This is a wrapper around split_insns which ensures that the
 473    reg_stat vector is made larger if the splitter creates a new
 474    register.  */
 475
 476 static rtx
 477 combine_split_insns (rtx pattern, rtx insn)
 478 {
 479   rtx ret;
 480   unsigned int nregs;
 481
 482   ret = split_insns (pattern, insn);
 483   nregs = max_reg_num ();
 484   if (nregs > VEC_length (reg_stat_type, reg_stat))
 485     VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
 486   return ret;
 487 }
 488
 489 /* This is used by find_single_use to locate an rtx in LOC that
 490    contains exactly one use of DEST, which is typically either a REG
 491    or CC0.  It returns a pointer to the innermost rtx expression
 492    containing DEST.  Appearances of DEST that are being used to
 493    totally replace it are not counted.  */
 494
 495 static rtx *
 496 find_single_use_1 (rtx dest, rtx *loc)
 497 {
 498   rtx x = *loc;
 499   enum rtx_code code = GET_CODE (x);
 500   rtx *result = NULL;
 501   rtx *this_result;
 502   int i;
 503   const char *fmt;
 504
 505   switch (code)
 506     {
 507     case CONST_INT:
 508     case CONST:
 509     case LABEL_REF:
 510     case SYMBOL_REF:
 511     case CONST_DOUBLE:
 512     case CONST_VECTOR:
 513     case CLOBBER:
 514       return 0;
 515
 516     case SET:
 517       /* If the destination is anything other than CC0, PC, a REG or a SUBREG
 518          of a REG that occupies all of the REG, the insn uses DEST if
 519          it is mentioned in the destination or the source.  Otherwise, we
 520          need just check the source.  */
 521       if (GET_CODE (SET_DEST (x)) != CC0
 522           && GET_CODE (SET_DEST (x)) != PC
 523           && !REG_P (SET_DEST (x))
 524           && ! (GET_CODE (SET_DEST (x)) == SUBREG
 525                 && REG_P (SUBREG_REG (SET_DEST (x)))
 526                 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
 527                       + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
 528                     == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
 529                          + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
 530         break;
 531
 532       return find_single_use_1 (dest, &SET_SRC (x));
 533
 534     case MEM:
 535     case SUBREG:
 536       return find_single_use_1 (dest, &XEXP (x, 0));
 537
 538     default:
 539       break;
 540     }
 541
 542   /* If it wasn't one of the common cases above, check each expression and
 543      vector of this code.  Look for a unique usage of DEST.  */
 544
 545   fmt = GET_RTX_FORMAT (code);
 546   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
 547     {
 548       if (fmt[i] == 'e')
 549         {
 550           if (dest == XEXP (x, i)
 551               || (REG_P (dest) && REG_P (XEXP (x, i))
 552                   && REGNO (dest) == REGNO (XEXP (x, i))))
 553             this_result = loc;
 554           else
 555             this_result = find_single_use_1 (dest, &XEXP (x, i));
 556
 557           if (result == NULL)
 558             result = this_result;
 559           else if (this_result)
 560             /* Duplicate usage.  */
 561             return NULL;
 562         }
 563       else if (fmt[i] == 'E')
 564         {
 565           int j;
 566
 567           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
 568             {
 569               if (XVECEXP (x, i, j) == dest
 570                   || (REG_P (dest)
 571                       && REG_P (XVECEXP (x, i, j))
 572                       && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
 573                 this_result = loc;
 574               else
 575                 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
 576
 577               if (result == NULL)
 578                 result = this_result;
 579               else if (this_result)
 580                 return NULL;
 581             }
 582         }
 583     }
 584
 585   return result;
 586 }
 587
 588
 589 /* See if DEST, produced in INSN, is used only a single time in the
 590    sequel.  If so, return a pointer to the innermost rtx expression in which
 591    it is used.
 592
 593    If PLOC is nonzero, *PLOC is set to the insn containing the single use.
 594
 595    If DEST is cc0_rtx, we look only at the next insn.  In that case, we don't
 596    care about REG_DEAD notes or LOG_LINKS.
 597
 598    Otherwise, we find the single use by finding an insn that has a
 599    LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST.  If DEST is
 600    only referenced once in that insn, we know that it must be the first
 601    and last insn referencing DEST.  */
 602
 603 static rtx *
 604 find_single_use (rtx dest, rtx insn, rtx *ploc)
 605 {
 606   rtx next;
 607   rtx *result;
 608   rtx link;
 609
 610 #ifdef HAVE_cc0
 611   if (dest == cc0_rtx)
 612     {
 613       next = NEXT_INSN (insn);
 614       if (next == 0
 615           || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
 616         return 0;
 617
 618       result = find_single_use_1 (dest, &PATTERN (next));
 619       if (result && ploc)
 620         *ploc = next;
 621       return result;
 622     }
 623 #endif
 624
 625   if (!REG_P (dest))
 626     return 0;
 627
 628   for (next = next_nonnote_insn (insn);
 629        next != 0 && !LABEL_P (next);
 630        next = next_nonnote_insn (next))
 631     if (INSN_P (next) && dead_or_set_p (next, dest))
 632       {
 633         for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
 634           if (XEXP (link, 0) == insn)
 635             break;
 636
 637         if (link)
 638           {
 639             result = find_single_use_1 (dest, &PATTERN (next));
 640             if (ploc)
 641               *ploc = next;
 642             return result;
 643           }
 644       }
 645
 646   return 0;
 647 }
 648 \f
 649 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 650    insn.  The substitution can be undone by undo_all.  If INTO is already
 651    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 652    also call SUBST, we have to compute it before we put anything into
 653    the undo table.  */
 654
 655 static void
 656 do_SUBST (rtx *into, rtx newval)
 657 {
 658   struct undo *buf;
 659   rtx oldval = *into;
 660
 661   if (oldval == newval)
 662     return;
 663
 664   /* We'd like to catch as many invalid transformations here as
 665      possible.  Unfortunately, there are way too many mode changes
 666      that are perfectly valid, so we'd waste too much effort for
 667      little gain doing the checks here.  Focus on catching invalid
 668      transformations involving integer constants.  */
 669   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 670       && GET_CODE (newval) == CONST_INT)
 671     {
 672       /* Sanity check that we're replacing oldval with a CONST_INT
 673          that is a valid sign-extension for the original mode.  */
 674       gcc_assert (INTVAL (newval)
 675                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 676
 677       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 678          CONST_INT is not valid, because after the replacement, the
 679          original mode would be gone.  Unfortunately, we can't tell
 680          when do_SUBST is called to replace the operand thereof, so we
 681          perform this test on oldval instead, checking whether an
 682          invalid replacement took place before we got here.  */
 683       gcc_assert (!(GET_CODE (oldval) == SUBREG
 684                     && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
 685       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 686                     && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
 687     }
 688
 689   if (undobuf.frees)
 690     buf = undobuf.frees, undobuf.frees = buf->next;
 691   else
 692     buf = XNEW (struct undo);
 693
 694   buf->kind = UNDO_RTX;
 695   buf->where.r = into;
 696   buf->old_contents.r = oldval;
 697   *into = newval;
 698
 699   buf->next = undobuf.undos, undobuf.undos = buf;
 700 }
 701
 702 #define SUBST(INTO, NEWVAL)     do_SUBST(&(INTO), (NEWVAL))
 703
 704 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 705    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 706    not safe.  */
 707
 708 static void
 709 do_SUBST_INT (int *into, int newval)
 710 {
 711   struct undo *buf;
 712   int oldval = *into;
 713
 714   if (oldval == newval)
 715     return;
 716
 717   if (undobuf.frees)
 718     buf = undobuf.frees, undobuf.frees = buf->next;
 719   else
 720     buf = XNEW (struct undo);
 721
 722   buf->kind = UNDO_INT;
 723   buf->where.i = into;
 724   buf->old_contents.i = oldval;
 725   *into = newval;
 726
 727   buf->next = undobuf.undos, undobuf.undos = buf;
 728 }
 729
 730 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT(&(INTO), (NEWVAL))
 731
 732 /* Similar to SUBST, but just substitute the mode.  This is used when
 733    changing the mode of a pseudo-register, so that any other
 734    references to the entry in the regno_reg_rtx array will change as
 735    well.  */
 736
 737 static void
 738 do_SUBST_MODE (rtx *into, enum machine_mode newval)
 739 {
 740   struct undo *buf;
 741   enum machine_mode oldval = GET_MODE (*into);
 742
 743   if (oldval == newval)
 744     return;
 745
 746   if (undobuf.frees)
 747     buf = undobuf.frees, undobuf.frees = buf->next;
 748   else
 749     buf = XNEW (struct undo);
 750
 751   buf->kind = UNDO_MODE;
 752   buf->where.r = into;
 753   buf->old_contents.m = oldval;
 754   PUT_MODE (*into, newval);
 755
 756   buf->next = undobuf.undos, undobuf.undos = buf;
 757 }
 758
 759 #define SUBST_MODE(INTO, NEWVAL)  do_SUBST_MODE(&(INTO), (NEWVAL))
 760 \f
 761 /* Subroutine of try_combine.  Determine whether the combine replacement
 762    patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
 763    insn_rtx_cost that the original instruction sequence I1, I2, I3 and
 764    undobuf.other_insn.  Note that I1 and/or NEWI2PAT may be NULL_RTX.
 765    NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX.  This
 766    function returns false, if the costs of all instructions can be
 767    estimated, and the replacements are more expensive than the original
 768    sequence.  */
 769
 770 static bool
 771 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat,
 772                        rtx newotherpat)
 773 {
 774   int i1_cost, i2_cost, i3_cost;
 775   int new_i2_cost, new_i3_cost;
 776   int old_cost, new_cost;
 777
 778   /* Lookup the original insn_rtx_costs.  */
 779   i2_cost = INSN_COST (i2);
 780   i3_cost = INSN_COST (i3);
 781
 782   if (i1)
 783     {
 784       i1_cost = INSN_COST (i1);
 785       old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
 786                  ? i1_cost + i2_cost + i3_cost : 0;
 787     }
 788   else
 789     {
 790       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 791       i1_cost = 0;
 792     }
 793
 794   /* Calculate the replacement insn_rtx_costs.  */
 795   new_i3_cost = insn_rtx_cost (newpat);
 796   if (newi2pat)
 797     {
 798       new_i2_cost = insn_rtx_cost (newi2pat);
 799       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 800                  ? new_i2_cost + new_i3_cost : 0;
 801     }
 802   else
 803     {
 804       new_cost = new_i3_cost;
 805       new_i2_cost = 0;
 806     }
 807
 808   if (undobuf.other_insn)
 809     {
 810       int old_other_cost, new_other_cost;
 811
 812       old_other_cost = INSN_COST (undobuf.other_insn);
 813       new_other_cost = insn_rtx_cost (newotherpat);
 814       if (old_other_cost > 0 && new_other_cost > 0)
 815         {
 816           old_cost += old_other_cost;
 817           new_cost += new_other_cost;
 818         }
 819       else
 820         old_cost = 0;
 821     }
 822
 823   /* Disallow this recombination if both new_cost and old_cost are
 824      greater than zero, and new_cost is greater than old cost.  */
 825   if (old_cost > 0
 826       && new_cost > old_cost)
 827     {
 828       if (dump_file)
 829         {
 830           if (i1)
 831             {
 832               fprintf (dump_file,
 833                        "rejecting combination of insns %d, %d and %d\n",
 834                        INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
 835               fprintf (dump_file, "original costs %d + %d + %d = %d\n",
 836                        i1_cost, i2_cost, i3_cost, old_cost);
 837             }
 838           else
 839             {
 840               fprintf (dump_file,
 841                        "rejecting combination of insns %d and %d\n",
 842                        INSN_UID (i2), INSN_UID (i3));
 843               fprintf (dump_file, "original costs %d + %d = %d\n",
 844                        i2_cost, i3_cost, old_cost);
 845             }
 846
 847           if (newi2pat)
 848             {
 849               fprintf (dump_file, "replacement costs %d + %d = %d\n",
 850                        new_i2_cost, new_i3_cost, new_cost);
 851             }
 852           else
 853             fprintf (dump_file, "replacement cost %d\n", new_cost);
 854         }
 855
 856       return false;
 857     }
 858
 859   /* Update the uid_insn_cost array with the replacement costs.  */
 860   INSN_COST (i2) = new_i2_cost;
 861   INSN_COST (i3) = new_i3_cost;
 862   if (i1)
 863     INSN_COST (i1) = 0;
 864
 865   return true;
 866 }
 867
 868
 869 /* Delete any insns that copy a register to itself.  */
 870
 871 static void
 872 delete_noop_moves (void)
 873 {
 874   rtx insn, next;
 875   basic_block bb;
 876
 877   FOR_EACH_BB (bb)
 878     {
 879       for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
 880         {
 881           next = NEXT_INSN (insn);
 882           if (INSN_P (insn) && noop_move_p (insn))
 883             {
 884               rtx note;
 885
 886               /* If we're about to remove the first insn of a libcall
 887                  then move the libcall note to the next real insn and
 888                  update the retval note.  */
 889               if ((note = find_reg_note (insn, REG_LIBCALL, NULL_RTX))
 890                        && XEXP (note, 0) != insn)
 891                 {
 892                   rtx new_libcall_insn = next_real_insn (insn);
 893                   rtx retval_note = find_reg_note (XEXP (note, 0),
 894                                                    REG_RETVAL, NULL_RTX);
 895                   REG_NOTES (new_libcall_insn)
 896                     = gen_rtx_INSN_LIST (REG_LIBCALL, XEXP (note, 0),
 897                                          REG_NOTES (new_libcall_insn));
 898                   XEXP (retval_note, 0) = new_libcall_insn;
 899                 }
 900
 901               if (dump_file)
 902                 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
 903
 904               delete_insn_and_edges (insn);
 905             }
 906         }
 907     }
 908 }
 909
 910 \f
 911 /* Fill in log links field for all insns.  */
 912
 913 static void
 914 create_log_links (void)
 915 {
 916   basic_block bb;
 917   rtx *next_use, insn;
 918   struct df_ref **def_vec, **use_vec;
 919
 920   next_use = XCNEWVEC (rtx, max_reg_num ());
 921
 922   /* Pass through each block from the end, recording the uses of each
 923      register and establishing log links when def is encountered.
 924      Note that we do not clear next_use array in order to save time,
 925      so we have to test whether the use is in the same basic block as def.
 926
 927      There are a few cases below when we do not consider the definition or
 928      usage -- these are taken from original flow.c did. Don't ask me why it is
 929      done this way; I don't know and if it works, I don't want to know.  */
 930
 931   FOR_EACH_BB (bb)
 932     {
 933       FOR_BB_INSNS_REVERSE (bb, insn)
 934         {
 935           if (!INSN_P (insn))
 936             continue;
 937
 938           /* Log links are created only once.  */
 939           gcc_assert (!LOG_LINKS (insn));
 940
 941           for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
 942             {
 943               struct df_ref *def = *def_vec;
 944               int regno = DF_REF_REGNO (def);
 945               rtx use_insn;
 946
 947               if (!next_use[regno])
 948                 continue;
 949
 950               /* Do not consider if it is pre/post modification in MEM.  */
 951               if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
 952                 continue;
 953
 954               /* Do not make the log link for frame pointer.  */
 955               if ((regno == FRAME_POINTER_REGNUM
 956                    && (! reload_completed || frame_pointer_needed))
 957 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
 958                   || (regno == HARD_FRAME_POINTER_REGNUM
 959                       && (! reload_completed || frame_pointer_needed))
 960 #endif
 961 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
 962                   || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
 963 #endif
 964                   )
 965                 continue;
 966
 967               use_insn = next_use[regno];
 968               if (BLOCK_FOR_INSN (use_insn) == bb)
 969                 {
 970                   /* flow.c claimed:
 971
 972                      We don't build a LOG_LINK for hard registers contained
 973                      in ASM_OPERANDs.  If these registers get replaced,
 974                      we might wind up changing the semantics of the insn,
 975                      even if reload can make what appear to be valid
 976                      assignments later.  */
 977                   if (regno >= FIRST_PSEUDO_REGISTER
 978                       || asm_noperands (PATTERN (use_insn)) < 0)
 979                     LOG_LINKS (use_insn) =
 980                       alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
 981                 }
 982               next_use[regno] = NULL_RTX;
 983             }
 984
 985           for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
 986             {
 987               struct df_ref *use = *use_vec;
 988               int regno = DF_REF_REGNO (use);
 989
 990               /* Do not consider the usage of the stack pointer
 991                  by function call.  */
 992               if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
 993                 continue;
 994
 995               next_use[regno] = insn;
 996             }
 997         }
 998     }
 999
1000   free (next_use);
1001 }
1002
1003 /* Clear LOG_LINKS fields of insns.  */
1004
1005 static void
1006 clear_log_links (void)
1007 {
1008   rtx insn;
1009
1010   for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1011     if (INSN_P (insn))
1012       free_INSN_LIST_list (&LOG_LINKS (insn));
1013 }
1014
1015
1016
1017 \f
1018 /* Main entry point for combiner.  F is the first insn of the function.
1019    NREGS is the first unused pseudo-reg number.
1020
1021    Return nonzero if the combiner has turned an indirect jump
1022    instruction into a direct jump.  */
1023 static int
1024 combine_instructions (rtx f, unsigned int nregs)
1025 {
1026   rtx insn, next;
1027 #ifdef HAVE_cc0
1028   rtx prev;
1029 #endif
1030   rtx links, nextlinks;
1031   rtx first;
1032
1033   int new_direct_jump_p = 0;
1034
1035   for (first = f; first && !INSN_P (first); )
1036     first = NEXT_INSN (first);
1037   if (!first)
1038     return 0;
1039
1040   combine_attempts = 0;
1041   combine_merges = 0;
1042   combine_extras = 0;
1043   combine_successes = 0;
1044
1045   rtl_hooks = combine_rtl_hooks;
1046
1047   VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1048
1049   init_recog_no_volatile ();
1050
1051   /* Allocate array for insn info.  */
1052   max_uid_known = get_max_uid ();
1053   uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1054   uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1055
1056   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1057
1058   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
1059      problems when, for example, we have j <<= 1 in a loop.  */
1060
1061   nonzero_sign_valid = 0;
1062
1063   /* Scan all SETs and see if we can deduce anything about what
1064      bits are known to be zero for some registers and how many copies
1065      of the sign bit are known to exist for those registers.
1066
1067      Also set any known values so that we can use it while searching
1068      for what bits are known to be set.  */
1069
1070   label_tick = label_tick_ebb_start = 1;
1071
1072   setup_incoming_promotions (first);
1073
1074   create_log_links ();
1075   FOR_EACH_BB (this_basic_block)
1076     {
1077       last_call_luid = 0;
1078       mem_last_set = -1;
1079       label_tick++;
1080       FOR_BB_INSNS (this_basic_block, insn)
1081         if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1082           {
1083             subst_low_luid = DF_INSN_LUID (insn);
1084             subst_insn = insn;
1085
1086             note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1087                          insn);
1088             record_dead_and_set_regs (insn);
1089
1090 #ifdef AUTO_INC_DEC
1091             for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1092               if (REG_NOTE_KIND (links) == REG_INC)
1093                 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1094                                                   insn);
1095 #endif
1096
1097             /* Record the current insn_rtx_cost of this instruction.  */
1098             if (NONJUMP_INSN_P (insn))
1099               INSN_COST (insn) = insn_rtx_cost (PATTERN (insn));
1100             if (dump_file)
1101               fprintf(dump_file, "insn_cost %d: %d\n",
1102                     INSN_UID (insn), INSN_COST (insn));
1103           }
1104         else if (LABEL_P (insn))
1105           label_tick_ebb_start = label_tick;
1106     }
1107
1108   nonzero_sign_valid = 1;
1109
1110   /* Now scan all the insns in forward order.  */
1111
1112   label_tick = label_tick_ebb_start = 1;
1113   init_reg_last ();
1114   setup_incoming_promotions (first);
1115
1116   FOR_EACH_BB (this_basic_block)
1117     {
1118       last_call_luid = 0;
1119       mem_last_set = -1;
1120       label_tick++;
1121       for (insn = BB_HEAD (this_basic_block);
1122            insn != NEXT_INSN (BB_END (this_basic_block));
1123            insn = next ? next : NEXT_INSN (insn))
1124         {
1125           next = 0;
1126           if (INSN_P (insn))
1127             {
1128               /* See if we know about function return values before this
1129                  insn based upon SUBREG flags.  */
1130               check_conversions (insn, PATTERN (insn));
1131
1132               /* Try this insn with each insn it links back to.  */
1133
1134               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1135                 if ((next = try_combine (insn, XEXP (links, 0),
1136                                          NULL_RTX, &new_direct_jump_p)) != 0)
1137                   goto retry;
1138
1139               /* Try each sequence of three linked insns ending with this one.  */
1140
1141               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1142                 {
1143                   rtx link = XEXP (links, 0);
1144
1145                   /* If the linked insn has been replaced by a note, then there
1146                      is no point in pursuing this chain any further.  */
1147                   if (NOTE_P (link))
1148                     continue;
1149
1150                   for (nextlinks = LOG_LINKS (link);
1151                        nextlinks;
1152                        nextlinks = XEXP (nextlinks, 1))
1153                     if ((next = try_combine (insn, link,
1154                                              XEXP (nextlinks, 0),
1155                                              &new_direct_jump_p)) != 0)
1156                       goto retry;
1157                 }
1158
1159 #ifdef HAVE_cc0
1160               /* Try to combine a jump insn that uses CC0
1161                  with a preceding insn that sets CC0, and maybe with its
1162                  logical predecessor as well.
1163                  This is how we make decrement-and-branch insns.
1164                  We need this special code because data flow connections
1165                  via CC0 do not get entered in LOG_LINKS.  */
1166
1167               if (JUMP_P (insn)
1168                   && (prev = prev_nonnote_insn (insn)) != 0
1169                   && NONJUMP_INSN_P (prev)
1170                   && sets_cc0_p (PATTERN (prev)))
1171                 {
1172                   if ((next = try_combine (insn, prev,
1173                                            NULL_RTX, &new_direct_jump_p)) != 0)
1174                     goto retry;
1175
1176                   for (nextlinks = LOG_LINKS (prev); nextlinks;
1177                        nextlinks = XEXP (nextlinks, 1))
1178                     if ((next = try_combine (insn, prev,
1179                                              XEXP (nextlinks, 0),
1180                                              &new_direct_jump_p)) != 0)
1181                       goto retry;
1182                 }
1183
1184               /* Do the same for an insn that explicitly references CC0.  */
1185               if (NONJUMP_INSN_P (insn)
1186                   && (prev = prev_nonnote_insn (insn)) != 0
1187                   && NONJUMP_INSN_P (prev)
1188                   && sets_cc0_p (PATTERN (prev))
1189                   && GET_CODE (PATTERN (insn)) == SET
1190                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1191                 {
1192                   if ((next = try_combine (insn, prev,
1193                                            NULL_RTX, &new_direct_jump_p)) != 0)
1194                     goto retry;
1195
1196                   for (nextlinks = LOG_LINKS (prev); nextlinks;
1197                        nextlinks = XEXP (nextlinks, 1))
1198                     if ((next = try_combine (insn, prev,
1199                                              XEXP (nextlinks, 0),
1200                                              &new_direct_jump_p)) != 0)
1201                       goto retry;
1202                 }
1203
1204               /* Finally, see if any of the insns that this insn links to
1205                  explicitly references CC0.  If so, try this insn, that insn,
1206                  and its predecessor if it sets CC0.  */
1207               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1208                 if (NONJUMP_INSN_P (XEXP (links, 0))
1209                     && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1210                     && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1211                     && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1212                     && NONJUMP_INSN_P (prev)
1213                     && sets_cc0_p (PATTERN (prev))
1214                     && (next = try_combine (insn, XEXP (links, 0),
1215                                             prev, &new_direct_jump_p)) != 0)
1216                   goto retry;
1217 #endif
1218
1219               /* Try combining an insn with two different insns whose results it
1220                  uses.  */
1221               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1222                 for (nextlinks = XEXP (links, 1); nextlinks;
1223                      nextlinks = XEXP (nextlinks, 1))
1224                   if ((next = try_combine (insn, XEXP (links, 0),
1225                                            XEXP (nextlinks, 0),
1226                                            &new_direct_jump_p)) != 0)
1227                     goto retry;
1228
1229               /* Try this insn with each REG_EQUAL note it links back to.  */
1230               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1231                 {
1232                   rtx set, note;
1233                   rtx temp = XEXP (links, 0);
1234                   if ((set = single_set (temp)) != 0
1235                       && (note = find_reg_equal_equiv_note (temp)) != 0
1236                       && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1237                       /* Avoid using a register that may already been marked
1238                          dead by an earlier instruction.  */
1239                       && ! unmentioned_reg_p (note, SET_SRC (set))
1240                       && (GET_MODE (note) == VOIDmode
1241                           ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1242                           : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1243                     {
1244                       /* Temporarily replace the set's source with the
1245                          contents of the REG_EQUAL note.  The insn will
1246                          be deleted or recognized by try_combine.  */
1247                       rtx orig = SET_SRC (set);
1248                       SET_SRC (set) = note;
1249                       i2mod = temp;
1250                       i2mod_old_rhs = copy_rtx (orig);
1251                       i2mod_new_rhs = copy_rtx (note);
1252                       next = try_combine (insn, i2mod, NULL_RTX,
1253                                           &new_direct_jump_p);
1254                       i2mod = NULL_RTX;
1255                       if (next)
1256                         goto retry;
1257                       SET_SRC (set) = orig;
1258                     }
1259                 }
1260
1261               if (!NOTE_P (insn))
1262                 record_dead_and_set_regs (insn);
1263
1264             retry:
1265               ;
1266             }
1267           else if (LABEL_P (insn))
1268             label_tick_ebb_start = label_tick;
1269         }
1270     }
1271
1272   clear_log_links ();
1273   clear_bb_flags ();
1274   new_direct_jump_p |= purge_all_dead_edges ();
1275   delete_noop_moves ();
1276
1277   /* Clean up.  */
1278   free (uid_log_links);
1279   free (uid_insn_cost);
1280   VEC_free (reg_stat_type, heap, reg_stat);
1281
1282   {
1283     struct undo *undo, *next;
1284     for (undo = undobuf.frees; undo; undo = next)
1285       {
1286         next = undo->next;
1287         free (undo);
1288       }
1289     undobuf.frees = 0;
1290   }
1291
1292   total_attempts += combine_attempts;
1293   total_merges += combine_merges;
1294   total_extras += combine_extras;
1295   total_successes += combine_successes;
1296
1297   nonzero_sign_valid = 0;
1298   rtl_hooks = general_rtl_hooks;
1299
1300   /* Make recognizer allow volatile MEMs again.  */
1301   init_recog ();
1302
1303   return new_direct_jump_p;
1304 }
1305
1306 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
1307
1308 static void
1309 init_reg_last (void)
1310 {
1311   unsigned int i;
1312   reg_stat_type *p;
1313
1314   for (i = 0; VEC_iterate (reg_stat_type, reg_stat, i, p); ++i)
1315     memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1316 }
1317 \f
1318 /* Set up any promoted values for incoming argument registers.  */
1319
1320 static void
1321 setup_incoming_promotions (rtx first)
1322 {
1323   tree arg;
1324   bool strictly_local = false;
1325
1326   if (!targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
1327     return;
1328
1329   for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1330        arg = TREE_CHAIN (arg))
1331     {
1332       rtx reg = DECL_INCOMING_RTL (arg);
1333       int uns1, uns3;
1334       enum machine_mode mode1, mode2, mode3, mode4;
1335
1336       /* Only continue if the incoming argument is in a register.  */
1337       if (!REG_P (reg))
1338         continue;
1339
1340       /* Determine, if possible, whether all call sites of the current
1341          function lie within the current compilation unit.  (This does
1342          take into account the exporting of a function via taking its
1343          address, and so forth.)  */
1344       if (flag_unit_at_a_time)
1345         strictly_local = cgraph_local_info (current_function_decl)->local;
1346
1347       /* The mode and signedness of the argument before any promotions happen
1348          (equal to the mode of the pseudo holding it at that stage).  */
1349       mode1 = TYPE_MODE (TREE_TYPE (arg));
1350       uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1351
1352       /* The mode and signedness of the argument after any source language and
1353          TARGET_PROMOTE_PROTOTYPES-driven promotions.  */
1354       mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1355       uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1356
1357       /* The mode and signedness of the argument as it is actually passed,
1358          after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions.  */
1359       mode3 = promote_mode (DECL_ARG_TYPE (arg), mode2, &uns3, 1);
1360
1361       /* The mode of the register in which the argument is being passed.  */
1362       mode4 = GET_MODE (reg);
1363
1364       /* Eliminate sign extensions in the callee when possible.  Only
1365          do this when:
1366          (a) the mode of the register is the same as the mode of
1367              the argument as it is passed; and
1368          (b) the signedness does not change across any of the promotions; and
1369          (c) when no language-level promotions (which we cannot guarantee
1370              will have been done by an external caller) are necessary,
1371              unless we know that this function is only ever called from
1372              the current compilation unit -- all of whose call sites will
1373              do the mode1 --> mode2 promotion.  */
1374       if (mode3 == mode4
1375           && uns1 == uns3
1376           && (mode1 == mode2 || strictly_local))
1377         {
1378           /* Record that the value was promoted from mode1 to mode3,
1379              so that any sign extension at the head of the current
1380              function may be eliminated.  */
1381           rtx x;
1382           x = gen_rtx_CLOBBER (mode1, const0_rtx);
1383           x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1384           record_value_for_reg (reg, first, x);
1385         }
1386     }
1387 }
1388
1389 /* Called via note_stores.  If X is a pseudo that is narrower than
1390    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1391
1392    If we are setting only a portion of X and we can't figure out what
1393    portion, assume all bits will be used since we don't know what will
1394    be happening.
1395
1396    Similarly, set how many bits of X are known to be copies of the sign bit
1397    at all locations in the function.  This is the smallest number implied
1398    by any set of X.  */
1399
1400 static void
1401 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1402 {
1403   rtx insn = (rtx) data;
1404   unsigned int num;
1405
1406   if (REG_P (x)
1407       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1408       /* If this register is undefined at the start of the file, we can't
1409          say what its contents were.  */
1410       && ! REGNO_REG_SET_P
1411            (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1412       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1413     {
1414       reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1415
1416       if (set == 0 || GET_CODE (set) == CLOBBER)
1417         {
1418           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1419           rsp->sign_bit_copies = 1;
1420           return;
1421         }
1422
1423       /* If this register is being initialized using itself, and the
1424          register is uninitialized in this basic block, and there are
1425          no LOG_LINKS which set the register, then part of the
1426          register is uninitialized.  In that case we can't assume
1427          anything about the number of nonzero bits.
1428
1429          ??? We could do better if we checked this in
1430          reg_{nonzero_bits,num_sign_bit_copies}_for_combine.  Then we
1431          could avoid making assumptions about the insn which initially
1432          sets the register, while still using the information in other
1433          insns.  We would have to be careful to check every insn
1434          involved in the combination.  */
1435
1436       if (insn
1437           && reg_referenced_p (x, PATTERN (insn))
1438           && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1439                                REGNO (x)))
1440         {
1441           rtx link;
1442
1443           for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1444             {
1445               if (dead_or_set_p (XEXP (link, 0), x))
1446                 break;
1447             }
1448           if (!link)
1449             {
1450               rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1451               rsp->sign_bit_copies = 1;
1452               return;
1453             }
1454         }
1455
1456       /* If this is a complex assignment, see if we can convert it into a
1457          simple assignment.  */
1458       set = expand_field_assignment (set);
1459
1460       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1461          set what we know about X.  */
1462
1463       if (SET_DEST (set) == x
1464           || (GET_CODE (SET_DEST (set)) == SUBREG
1465               && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1466                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1467               && SUBREG_REG (SET_DEST (set)) == x))
1468         {
1469           rtx src = SET_SRC (set);
1470
1471 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1472           /* If X is narrower than a word and SRC is a non-negative
1473              constant that would appear negative in the mode of X,
1474              sign-extend it for use in reg_stat[].nonzero_bits because some
1475              machines (maybe most) will actually do the sign-extension
1476              and this is the conservative approach.
1477
1478              ??? For 2.5, try to tighten up the MD files in this regard
1479              instead of this kludge.  */
1480
1481           if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1482               && GET_CODE (src) == CONST_INT
1483               && INTVAL (src) > 0
1484               && 0 != (INTVAL (src)
1485                        & ((HOST_WIDE_INT) 1
1486                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1487             src = GEN_INT (INTVAL (src)
1488                            | ((HOST_WIDE_INT) (-1)
1489                               << GET_MODE_BITSIZE (GET_MODE (x))));
1490 #endif
1491
1492           /* Don't call nonzero_bits if it cannot change anything.  */
1493           if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1494             rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1495           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1496           if (rsp->sign_bit_copies == 0
1497               || rsp->sign_bit_copies > num)
1498             rsp->sign_bit_copies = num;
1499         }
1500       else
1501         {
1502           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1503           rsp->sign_bit_copies = 1;
1504         }
1505     }
1506 }
1507 \f
1508 /* See if INSN can be combined into I3.  PRED and SUCC are optionally
1509    insns that were previously combined into I3 or that will be combined
1510    into the merger of INSN and I3.
1511
1512    Return 0 if the combination is not allowed for any reason.
1513
1514    If the combination is allowed, *PDEST will be set to the single
1515    destination of INSN and *PSRC to the single source, and this function
1516    will return 1.  */
1517
1518 static int
1519 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1520                rtx *pdest, rtx *psrc)
1521 {
1522   int i;
1523   const_rtx set = 0;
1524   rtx src, dest;
1525   rtx p;
1526 #ifdef AUTO_INC_DEC
1527   rtx link;
1528 #endif
1529   int all_adjacent = (succ ? (next_active_insn (insn) == succ
1530                               && next_active_insn (succ) == i3)
1531                       : next_active_insn (insn) == i3);
1532
1533   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1534      or a PARALLEL consisting of such a SET and CLOBBERs.
1535
1536      If INSN has CLOBBER parallel parts, ignore them for our processing.
1537      By definition, these happen during the execution of the insn.  When it
1538      is merged with another insn, all bets are off.  If they are, in fact,
1539      needed and aren't also supplied in I3, they may be added by
1540      recog_for_combine.  Otherwise, it won't match.
1541
1542      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1543      note.
1544
1545      Get the source and destination of INSN.  If more than one, can't
1546      combine.  */
1547
1548   if (GET_CODE (PATTERN (insn)) == SET)
1549     set = PATTERN (insn);
1550   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1551            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1552     {
1553       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1554         {
1555           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1556           rtx note;
1557
1558           switch (GET_CODE (elt))
1559             {
1560             /* This is important to combine floating point insns
1561                for the SH4 port.  */
1562             case USE:
1563               /* Combining an isolated USE doesn't make sense.
1564                  We depend here on combinable_i3pat to reject them.  */
1565               /* The code below this loop only verifies that the inputs of
1566                  the SET in INSN do not change.  We call reg_set_between_p
1567                  to verify that the REG in the USE does not change between
1568                  I3 and INSN.
1569                  If the USE in INSN was for a pseudo register, the matching
1570                  insn pattern will likely match any register; combining this
1571                  with any other USE would only be safe if we knew that the
1572                  used registers have identical values, or if there was
1573                  something to tell them apart, e.g. different modes.  For
1574                  now, we forgo such complicated tests and simply disallow
1575                  combining of USES of pseudo registers with any other USE.  */
1576               if (REG_P (XEXP (elt, 0))
1577                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1578                 {
1579                   rtx i3pat = PATTERN (i3);
1580                   int i = XVECLEN (i3pat, 0) - 1;
1581                   unsigned int regno = REGNO (XEXP (elt, 0));
1582
1583                   do
1584                     {
1585                       rtx i3elt = XVECEXP (i3pat, 0, i);
1586
1587                       if (GET_CODE (i3elt) == USE
1588                           && REG_P (XEXP (i3elt, 0))
1589                           && (REGNO (XEXP (i3elt, 0)) == regno
1590                               ? reg_set_between_p (XEXP (elt, 0),
1591                                                    PREV_INSN (insn), i3)
1592                               : regno >= FIRST_PSEUDO_REGISTER))
1593                         return 0;
1594                     }
1595                   while (--i >= 0);
1596                 }
1597               break;
1598
1599               /* We can ignore CLOBBERs.  */
1600             case CLOBBER:
1601               break;
1602
1603             case SET:
1604               /* Ignore SETs whose result isn't used but not those that
1605                  have side-effects.  */
1606               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1607                   && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1608                       || INTVAL (XEXP (note, 0)) <= 0)
1609                   && ! side_effects_p (elt))
1610                 break;
1611
1612               /* If we have already found a SET, this is a second one and
1613                  so we cannot combine with this insn.  */
1614               if (set)
1615                 return 0;
1616
1617               set = elt;
1618               break;
1619
1620             default:
1621               /* Anything else means we can't combine.  */
1622               return 0;
1623             }
1624         }
1625
1626       if (set == 0
1627           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1628              so don't do anything with it.  */
1629           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1630         return 0;
1631     }
1632   else
1633     return 0;
1634
1635   if (set == 0)
1636     return 0;
1637
1638   set = expand_field_assignment (set);
1639   src = SET_SRC (set), dest = SET_DEST (set);
1640
1641   /* Don't eliminate a store in the stack pointer.  */
1642   if (dest == stack_pointer_rtx
1643       /* Don't combine with an insn that sets a register to itself if it has
1644          a REG_EQUAL note.  This may be part of a REG_NO_CONFLICT sequence.  */
1645       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1646       /* Can't merge an ASM_OPERANDS.  */
1647       || GET_CODE (src) == ASM_OPERANDS
1648       /* Can't merge a function call.  */
1649       || GET_CODE (src) == CALL
1650       /* Don't eliminate a function call argument.  */
1651       || (CALL_P (i3)
1652           && (find_reg_fusage (i3, USE, dest)
1653               || (REG_P (dest)
1654                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1655                   && global_regs[REGNO (dest)])))
1656       /* Don't substitute into an incremented register.  */
1657       || FIND_REG_INC_NOTE (i3, dest)
1658       || (succ && FIND_REG_INC_NOTE (succ, dest))
1659       /* Don't substitute into a non-local goto, this confuses CFG.  */
1660       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1661 #if 0
1662       /* Don't combine the end of a libcall into anything.  */
1663       /* ??? This gives worse code, and appears to be unnecessary, since no
1664          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  Local-alloc does
1665          use REG_RETVAL notes for noconflict blocks, but other code here
1666          makes sure that those insns don't disappear.  */
1667       || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1668 #endif
1669       /* Make sure that DEST is not used after SUCC but before I3.  */
1670       || (succ && ! all_adjacent
1671           && reg_used_between_p (dest, succ, i3))
1672       /* Make sure that the value that is to be substituted for the register
1673          does not use any registers whose values alter in between.  However,
1674          If the insns are adjacent, a use can't cross a set even though we
1675          think it might (this can happen for a sequence of insns each setting
1676          the same destination; last_set of that register might point to
1677          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1678          equivalent to the memory so the substitution is valid even if there
1679          are intervening stores.  Also, don't move a volatile asm or
1680          UNSPEC_VOLATILE across any other insns.  */
1681       || (! all_adjacent
1682           && (((!MEM_P (src)
1683                 || ! find_reg_note (insn, REG_EQUIV, src))
1684                && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1685               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1686               || GET_CODE (src) == UNSPEC_VOLATILE))
1687       /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1688          better register allocation by not doing the combine.  */
1689       || find_reg_note (i3, REG_NO_CONFLICT, dest)
1690       || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1691       /* Don't combine across a CALL_INSN, because that would possibly
1692          change whether the life span of some REGs crosses calls or not,
1693          and it is a pain to update that information.
1694          Exception: if source is a constant, moving it later can't hurt.
1695          Accept that special case, because it helps -fforce-addr a lot.  */
1696       || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1697     return 0;
1698
1699   /* DEST must either be a REG or CC0.  */
1700   if (REG_P (dest))
1701     {
1702       /* If register alignment is being enforced for multi-word items in all
1703          cases except for parameters, it is possible to have a register copy
1704          insn referencing a hard register that is not allowed to contain the
1705          mode being copied and which would not be valid as an operand of most
1706          insns.  Eliminate this problem by not combining with such an insn.
1707
1708          Also, on some machines we don't want to extend the life of a hard
1709          register.  */
1710
1711       if (REG_P (src)
1712           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1713                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1714               /* Don't extend the life of a hard register unless it is
1715                  user variable (if we have few registers) or it can't
1716                  fit into the desired register (meaning something special
1717                  is going on).
1718                  Also avoid substituting a return register into I3, because
1719                  reload can't handle a conflict with constraints of other
1720                  inputs.  */
1721               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1722                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1723         return 0;
1724     }
1725   else if (GET_CODE (dest) != CC0)
1726     return 0;
1727
1728
1729   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1730     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1731       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1732         {
1733           /* Don't substitute for a register intended as a clobberable
1734              operand.  */
1735           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1736           if (rtx_equal_p (reg, dest))
1737             return 0;
1738
1739           /* If the clobber represents an earlyclobber operand, we must not
1740              substitute an expression containing the clobbered register.
1741              As we do not analyze the constraint strings here, we have to
1742              make the conservative assumption.  However, if the register is
1743              a fixed hard reg, the clobber cannot represent any operand;
1744              we leave it up to the machine description to either accept or
1745              reject use-and-clobber patterns.  */
1746           if (!REG_P (reg)
1747               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1748               || !fixed_regs[REGNO (reg)])
1749             if (reg_overlap_mentioned_p (reg, src))
1750               return 0;
1751         }
1752
1753   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1754      or not), reject, unless nothing volatile comes between it and I3 */
1755
1756   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1757     {
1758       /* Make sure succ doesn't contain a volatile reference.  */
1759       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1760         return 0;
1761
1762       for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1763         if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1764           return 0;
1765     }
1766
1767   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1768      to be an explicit register variable, and was chosen for a reason.  */
1769
1770   if (GET_CODE (src) == ASM_OPERANDS
1771       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1772     return 0;
1773
1774   /* If there are any volatile insns between INSN and I3, reject, because
1775      they might affect machine state.  */
1776
1777   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1778     if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1779       return 0;
1780
1781   /* If INSN contains an autoincrement or autodecrement, make sure that
1782      register is not used between there and I3, and not already used in
1783      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
1784      Also insist that I3 not be a jump; if it were one
1785      and the incremented register were spilled, we would lose.  */
1786
1787 #ifdef AUTO_INC_DEC
1788   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1789     if (REG_NOTE_KIND (link) == REG_INC
1790         && (JUMP_P (i3)
1791             || reg_used_between_p (XEXP (link, 0), insn, i3)
1792             || (pred != NULL_RTX
1793                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1794             || (succ != NULL_RTX
1795                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1796             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1797       return 0;
1798 #endif
1799
1800 #ifdef HAVE_cc0
1801   /* Don't combine an insn that follows a CC0-setting insn.
1802      An insn that uses CC0 must not be separated from the one that sets it.
1803      We do, however, allow I2 to follow a CC0-setting insn if that insn
1804      is passed as I1; in that case it will be deleted also.
1805      We also allow combining in this case if all the insns are adjacent
1806      because that would leave the two CC0 insns adjacent as well.
1807      It would be more logical to test whether CC0 occurs inside I1 or I2,
1808      but that would be much slower, and this ought to be equivalent.  */
1809
1810   p = prev_nonnote_insn (insn);
1811   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1812       && ! all_adjacent)
1813     return 0;
1814 #endif
1815
1816   /* If we get here, we have passed all the tests and the combination is
1817      to be allowed.  */
1818
1819   *pdest = dest;
1820   *psrc = src;
1821
1822   return 1;
1823 }
1824 \f
1825 /* LOC is the location within I3 that contains its pattern or the component
1826    of a PARALLEL of the pattern.  We validate that it is valid for combining.
1827
1828    One problem is if I3 modifies its output, as opposed to replacing it
1829    entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1830    so would produce an insn that is not equivalent to the original insns.
1831
1832    Consider:
1833
1834          (set (reg:DI 101) (reg:DI 100))
1835          (set (subreg:SI (reg:DI 101) 0) <foo>)
1836
1837    This is NOT equivalent to:
1838
1839          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1840                     (set (reg:DI 101) (reg:DI 100))])
1841
1842    Not only does this modify 100 (in which case it might still be valid
1843    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1844
1845    We can also run into a problem if I2 sets a register that I1
1846    uses and I1 gets directly substituted into I3 (not via I2).  In that
1847    case, we would be getting the wrong value of I2DEST into I3, so we
1848    must reject the combination.  This case occurs when I2 and I1 both
1849    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1850    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1851    of a SET must prevent combination from occurring.
1852
1853    Before doing the above check, we first try to expand a field assignment
1854    into a set of logical operations.
1855
1856    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1857    we place a register that is both set and used within I3.  If more than one
1858    such register is detected, we fail.
1859
1860    Return 1 if the combination is valid, zero otherwise.  */
1861
1862 static int
1863 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1864                   int i1_not_in_src, rtx *pi3dest_killed)
1865 {
1866   rtx x = *loc;
1867
1868   if (GET_CODE (x) == SET)
1869     {
1870       rtx set = x ;
1871       rtx dest = SET_DEST (set);
1872       rtx src = SET_SRC (set);
1873       rtx inner_dest = dest;
1874       rtx subdest;
1875
1876       while (GET_CODE (inner_dest) == STRICT_LOW_PART
1877              || GET_CODE (inner_dest) == SUBREG
1878              || GET_CODE (inner_dest) == ZERO_EXTRACT)
1879         inner_dest = XEXP (inner_dest, 0);
1880
1881       /* Check for the case where I3 modifies its output, as discussed
1882          above.  We don't want to prevent pseudos from being combined
1883          into the address of a MEM, so only prevent the combination if
1884          i1 or i2 set the same MEM.  */
1885       if ((inner_dest != dest &&
1886            (!MEM_P (inner_dest)
1887             || rtx_equal_p (i2dest, inner_dest)
1888             || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1889            && (reg_overlap_mentioned_p (i2dest, inner_dest)
1890                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1891
1892           /* This is the same test done in can_combine_p except we can't test
1893              all_adjacent; we don't have to, since this instruction will stay
1894              in place, thus we are not considering increasing the lifetime of
1895              INNER_DEST.
1896
1897              Also, if this insn sets a function argument, combining it with
1898              something that might need a spill could clobber a previous
1899              function argument; the all_adjacent test in can_combine_p also
1900              checks this; here, we do a more specific test for this case.  */
1901
1902           || (REG_P (inner_dest)
1903               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1904               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1905                                         GET_MODE (inner_dest))))
1906           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1907         return 0;
1908
1909       /* If DEST is used in I3, it is being killed in this insn, so
1910          record that for later.  We have to consider paradoxical
1911          subregs here, since they kill the whole register, but we
1912          ignore partial subregs, STRICT_LOW_PART, etc.
1913          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1914          STACK_POINTER_REGNUM, since these are always considered to be
1915          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
1916       subdest = dest;
1917       if (GET_CODE (subdest) == SUBREG
1918           && (GET_MODE_SIZE (GET_MODE (subdest))
1919               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1920         subdest = SUBREG_REG (subdest);
1921       if (pi3dest_killed
1922           && REG_P (subdest)
1923           && reg_referenced_p (subdest, PATTERN (i3))
1924           && REGNO (subdest) != FRAME_POINTER_REGNUM
1925 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1926           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1927 #endif
1928 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1929           && (REGNO (subdest) != ARG_POINTER_REGNUM
1930               || ! fixed_regs [REGNO (subdest)])
1931 #endif
1932           && REGNO (subdest) != STACK_POINTER_REGNUM)
1933         {
1934           if (*pi3dest_killed)
1935             return 0;
1936
1937           *pi3dest_killed = subdest;
1938         }
1939     }
1940
1941   else if (GET_CODE (x) == PARALLEL)
1942     {
1943       int i;
1944
1945       for (i = 0; i < XVECLEN (x, 0); i++)
1946         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1947                                 i1_not_in_src, pi3dest_killed))
1948           return 0;
1949     }
1950
1951   return 1;
1952 }
1953 \f
1954 /* Return 1 if X is an arithmetic expression that contains a multiplication
1955    and division.  We don't count multiplications by powers of two here.  */
1956
1957 static int
1958 contains_muldiv (rtx x)
1959 {
1960   switch (GET_CODE (x))
1961     {
1962     case MOD:  case DIV:  case UMOD:  case UDIV:
1963       return 1;
1964
1965     case MULT:
1966       return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1967                 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1968     default:
1969       if (BINARY_P (x))
1970         return contains_muldiv (XEXP (x, 0))
1971             || contains_muldiv (XEXP (x, 1));
1972
1973       if (UNARY_P (x))
1974         return contains_muldiv (XEXP (x, 0));
1975
1976       return 0;
1977     }
1978 }
1979 \f
1980 /* Determine whether INSN can be used in a combination.  Return nonzero if
1981    not.  This is used in try_combine to detect early some cases where we
1982    can't perform combinations.  */
1983
1984 static int
1985 cant_combine_insn_p (rtx insn)
1986 {
1987   rtx set;
1988   rtx src, dest;
1989
1990   /* If this isn't really an insn, we can't do anything.
1991      This can occur when flow deletes an insn that it has merged into an
1992      auto-increment address.  */
1993   if (! INSN_P (insn))
1994     return 1;
1995
1996   /* Never combine loads and stores involving hard regs that are likely
1997      to be spilled.  The register allocator can usually handle such
1998      reg-reg moves by tying.  If we allow the combiner to make
1999      substitutions of likely-spilled regs, reload might die.
2000      As an exception, we allow combinations involving fixed regs; these are
2001      not available to the register allocator so there's no risk involved.  */
2002
2003   set = single_set (insn);
2004   if (! set)
2005     return 0;
2006   src = SET_SRC (set);
2007   dest = SET_DEST (set);
2008   if (GET_CODE (src) == SUBREG)
2009     src = SUBREG_REG (src);
2010   if (GET_CODE (dest) == SUBREG)
2011     dest = SUBREG_REG (dest);
2012   if (REG_P (src) && REG_P (dest)
2013       && ((REGNO (src) < FIRST_PSEUDO_REGISTER
2014            && ! fixed_regs[REGNO (src)]
2015            && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
2016           || (REGNO (dest) < FIRST_PSEUDO_REGISTER
2017               && ! fixed_regs[REGNO (dest)]
2018               && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
2019     return 1;
2020
2021   return 0;
2022 }
2023
2024 struct likely_spilled_retval_info
2025 {
2026   unsigned regno, nregs;
2027   unsigned mask;
2028 };
2029
2030 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
2031    hard registers that are known to be written to / clobbered in full.  */
2032 static void
2033 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2034 {
2035   struct likely_spilled_retval_info *info = data;
2036   unsigned regno, nregs;
2037   unsigned new_mask;
2038
2039   if (!REG_P (XEXP (set, 0)))
2040     return;
2041   regno = REGNO (x);
2042   if (regno >= info->regno + info->nregs)
2043     return;
2044   nregs = hard_regno_nregs[regno][GET_MODE (x)];
2045   if (regno + nregs <= info->regno)
2046     return;
2047   new_mask = (2U << (nregs - 1)) - 1;
2048   if (regno < info->regno)
2049     new_mask >>= info->regno - regno;
2050   else
2051     new_mask <<= regno - info->regno;
2052   info->mask &= ~new_mask;
2053 }
2054
2055 /* Return nonzero iff part of the return value is live during INSN, and
2056    it is likely spilled.  This can happen when more than one insn is needed
2057    to copy the return value, e.g. when we consider to combine into the
2058    second copy insn for a complex value.  */
2059
2060 static int
2061 likely_spilled_retval_p (rtx insn)
2062 {
2063   rtx use = BB_END (this_basic_block);
2064   rtx reg, p;
2065   unsigned regno, nregs;
2066   /* We assume here that no machine mode needs more than
2067      32 hard registers when the value overlaps with a register
2068      for which FUNCTION_VALUE_REGNO_P is true.  */
2069   unsigned mask;
2070   struct likely_spilled_retval_info info;
2071
2072   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2073     return 0;
2074   reg = XEXP (PATTERN (use), 0);
2075   if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
2076     return 0;
2077   regno = REGNO (reg);
2078   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2079   if (nregs == 1)
2080     return 0;
2081   mask = (2U << (nregs - 1)) - 1;
2082
2083   /* Disregard parts of the return value that are set later.  */
2084   info.regno = regno;
2085   info.nregs = nregs;
2086   info.mask = mask;
2087   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2088     if (INSN_P (p))
2089       note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2090   mask = info.mask;
2091
2092   /* Check if any of the (probably) live return value registers is
2093      likely spilled.  */
2094   nregs --;
2095   do
2096     {
2097       if ((mask & 1 << nregs)
2098           && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
2099         return 1;
2100     } while (nregs--);
2101   return 0;
2102 }
2103
2104 /* Adjust INSN after we made a change to its destination.
2105
2106    Changing the destination can invalidate notes that say something about
2107    the results of the insn and a LOG_LINK pointing to the insn.  */
2108
2109 static void
2110 adjust_for_new_dest (rtx insn)
2111 {
2112   /* For notes, be conservative and simply remove them.  */
2113   remove_reg_equal_equiv_notes (insn);
2114
2115   /* The new insn will have a destination that was previously the destination
2116      of an insn just above it.  Call distribute_links to make a LOG_LINK from
2117      the next use of that destination.  */
2118   distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2119
2120   df_insn_rescan (insn);
2121 }
2122
2123 /* Return TRUE if combine can reuse reg X in mode MODE.
2124    ADDED_SETS is nonzero if the original set is still required.  */
2125 static bool
2126 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2127 {
2128   unsigned int regno;
2129
2130   if (!REG_P(x))
2131     return false;
2132
2133   regno = REGNO (x);
2134   /* Allow hard registers if the new mode is legal, and occupies no more
2135      registers than the old mode.  */
2136   if (regno < FIRST_PSEUDO_REGISTER)
2137     return (HARD_REGNO_MODE_OK (regno, mode)
2138             && (hard_regno_nregs[regno][GET_MODE (x)]
2139                 >= hard_regno_nregs[regno][mode]));
2140
2141   /* Or a pseudo that is only used once.  */
2142   return (REG_N_SETS (regno) == 1 && !added_sets
2143           && !REG_USERVAR_P (x));
2144 }
2145
2146
2147 /* Check whether X, the destination of a set, refers to part of
2148    the register specified by REG.  */
2149
2150 static bool
2151 reg_subword_p (rtx x, rtx reg)
2152 {
2153   /* Check that reg is an integer mode register.  */
2154   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2155     return false;
2156
2157   if (GET_CODE (x) == STRICT_LOW_PART
2158       || GET_CODE (x) == ZERO_EXTRACT)
2159     x = XEXP (x, 0);
2160
2161   return GET_CODE (x) == SUBREG
2162          && SUBREG_REG (x) == reg
2163          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2164 }
2165
2166
2167 /* Try to combine the insns I1 and I2 into I3.
2168    Here I1 and I2 appear earlier than I3.
2169    I1 can be zero; then we combine just I2 into I3.
2170
2171    If we are combining three insns and the resulting insn is not recognized,
2172    try splitting it into two insns.  If that happens, I2 and I3 are retained
2173    and I1 is pseudo-deleted by turning it into a NOTE.  Otherwise, I1 and I2
2174    are pseudo-deleted.
2175
2176    Return 0 if the combination does not work.  Then nothing is changed.
2177    If we did the combination, return the insn at which combine should
2178    resume scanning.
2179
2180    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2181    new direct jump instruction.  */
2182
2183 static rtx
2184 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
2185 {
2186   /* New patterns for I3 and I2, respectively.  */
2187   rtx newpat, newi2pat = 0;
2188   rtvec newpat_vec_with_clobbers = 0;
2189   int substed_i2 = 0, substed_i1 = 0;
2190   /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead.  */
2191   int added_sets_1, added_sets_2;
2192   /* Total number of SETs to put into I3.  */
2193   int total_sets;
2194   /* Nonzero if I2's body now appears in I3.  */
2195   int i2_is_used;
2196   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
2197   int insn_code_number, i2_code_number = 0, other_code_number = 0;
2198   /* Contains I3 if the destination of I3 is used in its source, which means
2199      that the old life of I3 is being killed.  If that usage is placed into
2200      I2 and not in I3, a REG_DEAD note must be made.  */
2201   rtx i3dest_killed = 0;
2202   /* SET_DEST and SET_SRC of I2 and I1.  */
2203   rtx i2dest, i2src, i1dest = 0, i1src = 0;
2204   /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases.  */
2205   rtx i1pat = 0, i2pat = 0;
2206   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
2207   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2208   int i2dest_killed = 0, i1dest_killed = 0;
2209   int i1_feeds_i3 = 0;
2210   /* Notes that must be added to REG_NOTES in I3 and I2.  */
2211   rtx new_i3_notes, new_i2_notes;
2212   /* Notes that we substituted I3 into I2 instead of the normal case.  */
2213   int i3_subst_into_i2 = 0;
2214   /* Notes that I1, I2 or I3 is a MULT operation.  */
2215   int have_mult = 0;
2216   int swap_i2i3 = 0;
2217
2218   int maxreg;
2219   rtx temp;
2220   rtx link;
2221   rtx other_pat = 0;
2222   rtx new_other_notes;
2223   int i;
2224
2225   /* Exit early if one of the insns involved can't be used for
2226      combinations.  */
2227   if (cant_combine_insn_p (i3)
2228       || cant_combine_insn_p (i2)
2229       || (i1 && cant_combine_insn_p (i1))
2230       || likely_spilled_retval_p (i3)
2231       /* We also can't do anything if I3 has a
2232          REG_LIBCALL note since we don't want to disrupt the contiguity of a
2233          libcall.  */
2234 #if 0
2235       /* ??? This gives worse code, and appears to be unnecessary, since no
2236          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  */
2237       || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
2238 #endif
2239       )
2240     return 0;
2241
2242   combine_attempts++;
2243   undobuf.other_insn = 0;
2244
2245   /* Reset the hard register usage information.  */
2246   CLEAR_HARD_REG_SET (newpat_used_regs);
2247
2248   /* If I1 and I2 both feed I3, they can be in any order.  To simplify the
2249      code below, set I1 to be the earlier of the two insns.  */
2250   if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2251     temp = i1, i1 = i2, i2 = temp;
2252
2253   added_links_insn = 0;
2254
2255   /* First check for one important special-case that the code below will
2256      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
2257      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
2258      we may be able to replace that destination with the destination of I3.
2259      This occurs in the common code where we compute both a quotient and
2260      remainder into a structure, in which case we want to do the computation
2261      directly into the structure to avoid register-register copies.
2262
2263      Note that this case handles both multiple sets in I2 and also
2264      cases where I2 has a number of CLOBBER or PARALLELs.
2265
2266      We make very conservative checks below and only try to handle the
2267      most common cases of this.  For example, we only handle the case
2268      where I2 and I3 are adjacent to avoid making difficult register
2269      usage tests.  */
2270
2271   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2272       && REG_P (SET_SRC (PATTERN (i3)))
2273       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2274       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2275       && GET_CODE (PATTERN (i2)) == PARALLEL
2276       && ! side_effects_p (SET_DEST (PATTERN (i3)))
2277       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2278          below would need to check what is inside (and reg_overlap_mentioned_p
2279          doesn't support those codes anyway).  Don't allow those destinations;
2280          the resulting insn isn't likely to be recognized anyway.  */
2281       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2282       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2283       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2284                                     SET_DEST (PATTERN (i3)))
2285       && next_real_insn (i2) == i3)
2286     {
2287       rtx p2 = PATTERN (i2);
2288
2289       /* Make sure that the destination of I3,
2290          which we are going to substitute into one output of I2,
2291          is not used within another output of I2.  We must avoid making this:
2292          (parallel [(set (mem (reg 69)) ...)
2293                     (set (reg 69) ...)])
2294          which is not well-defined as to order of actions.
2295          (Besides, reload can't handle output reloads for this.)
2296
2297          The problem can also happen if the dest of I3 is a memory ref,
2298          if another dest in I2 is an indirect memory ref.  */
2299       for (i = 0; i < XVECLEN (p2, 0); i++)
2300         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2301              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2302             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2303                                         SET_DEST (XVECEXP (p2, 0, i))))
2304           break;
2305
2306       if (i == XVECLEN (p2, 0))
2307         for (i = 0; i < XVECLEN (p2, 0); i++)
2308           if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2309                || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2310               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2311             {
2312               combine_merges++;
2313
2314               subst_insn = i3;
2315               subst_low_luid = DF_INSN_LUID (i2);
2316
2317               added_sets_2 = added_sets_1 = 0;
2318               i2dest = SET_SRC (PATTERN (i3));
2319               i2dest_killed = dead_or_set_p (i2, i2dest);
2320
2321               /* Replace the dest in I2 with our dest and make the resulting
2322                  insn the new pattern for I3.  Then skip to where we
2323                  validate the pattern.  Everything was set up above.  */
2324               SUBST (SET_DEST (XVECEXP (p2, 0, i)),
2325                      SET_DEST (PATTERN (i3)));
2326
2327               newpat = p2;
2328               i3_subst_into_i2 = 1;
2329               goto validate_replacement;
2330             }
2331     }
2332
2333   /* If I2 is setting a pseudo to a constant and I3 is setting some
2334      sub-part of it to another constant, merge them by making a new
2335      constant.  */
2336   if (i1 == 0
2337       && (temp = single_set (i2)) != 0
2338       && (GET_CODE (SET_SRC (temp)) == CONST_INT
2339           || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2340       && GET_CODE (PATTERN (i3)) == SET
2341       && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
2342           || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2343       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2344     {
2345       rtx dest = SET_DEST (PATTERN (i3));
2346       int offset = -1;
2347       int width = 0;
2348
2349       if (GET_CODE (dest) == ZERO_EXTRACT)
2350         {
2351           if (GET_CODE (XEXP (dest, 1)) == CONST_INT
2352               && GET_CODE (XEXP (dest, 2)) == CONST_INT)
2353             {
2354               width = INTVAL (XEXP (dest, 1));
2355               offset = INTVAL (XEXP (dest, 2));
2356               dest = XEXP (dest, 0);
2357               if (BITS_BIG_ENDIAN)
2358                 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2359             }
2360         }
2361       else
2362         {
2363           if (GET_CODE (dest) == STRICT_LOW_PART)
2364             dest = XEXP (dest, 0);
2365           width = GET_MODE_BITSIZE (GET_MODE (dest));
2366           offset = 0;
2367         }
2368
2369       if (offset >= 0)
2370         {
2371           /* If this is the low part, we're done.  */
2372           if (subreg_lowpart_p (dest))
2373             ;
2374           /* Handle the case where inner is twice the size of outer.  */
2375           else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2376                    == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2377             offset += GET_MODE_BITSIZE (GET_MODE (dest));
2378           /* Otherwise give up for now.  */
2379           else
2380             offset = -1;
2381         }
2382
2383       if (offset >= 0
2384           && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2385               <= HOST_BITS_PER_WIDE_INT * 2))
2386         {
2387           HOST_WIDE_INT mhi, ohi, ihi;
2388           HOST_WIDE_INT mlo, olo, ilo;
2389           rtx inner = SET_SRC (PATTERN (i3));
2390           rtx outer = SET_SRC (temp);
2391
2392           if (GET_CODE (outer) == CONST_INT)
2393             {
2394               olo = INTVAL (outer);
2395               ohi = olo < 0 ? -1 : 0;
2396             }
2397           else
2398             {
2399               olo = CONST_DOUBLE_LOW (outer);
2400               ohi = CONST_DOUBLE_HIGH (outer);
2401             }
2402
2403           if (GET_CODE (inner) == CONST_INT)
2404             {
2405               ilo = INTVAL (inner);
2406               ihi = ilo < 0 ? -1 : 0;
2407             }
2408           else
2409             {
2410               ilo = CONST_DOUBLE_LOW (inner);
2411               ihi = CONST_DOUBLE_HIGH (inner);
2412             }
2413
2414           if (width < HOST_BITS_PER_WIDE_INT)
2415             {
2416               mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2417               mhi = 0;
2418             }
2419           else if (width < HOST_BITS_PER_WIDE_INT * 2)
2420             {
2421               mhi = ((unsigned HOST_WIDE_INT) 1
2422                      << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2423               mlo = -1;
2424             }
2425           else
2426             {
2427               mlo = -1;
2428               mhi = -1;
2429             }
2430
2431           ilo &= mlo;
2432           ihi &= mhi;
2433
2434           if (offset >= HOST_BITS_PER_WIDE_INT)
2435             {
2436               mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2437               mlo = 0;
2438               ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2439               ilo = 0;
2440             }
2441           else if (offset > 0)
2442             {
2443               mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2444                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2445               mlo = mlo << offset;
2446               ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2447                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2448               ilo = ilo << offset;
2449             }
2450
2451           olo = (olo & ~mlo) | ilo;
2452           ohi = (ohi & ~mhi) | ihi;
2453
2454           combine_merges++;
2455           subst_insn = i3;
2456           subst_low_luid = DF_INSN_LUID (i2);
2457           added_sets_2 = added_sets_1 = 0;
2458           i2dest = SET_DEST (temp);
2459           i2dest_killed = dead_or_set_p (i2, i2dest);
2460
2461           SUBST (SET_SRC (temp),
2462                  immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2463
2464           newpat = PATTERN (i2);
2465           goto validate_replacement;
2466         }
2467     }
2468
2469 #ifndef HAVE_cc0
2470   /* If we have no I1 and I2 looks like:
2471         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2472                    (set Y OP)])
2473      make up a dummy I1 that is
2474         (set Y OP)
2475      and change I2 to be
2476         (set (reg:CC X) (compare:CC Y (const_int 0)))
2477
2478      (We can ignore any trailing CLOBBERs.)
2479
2480      This undoes a previous combination and allows us to match a branch-and-
2481      decrement insn.  */
2482
2483   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2484       && XVECLEN (PATTERN (i2), 0) >= 2
2485       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2486       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2487           == MODE_CC)
2488       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2489       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2490       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2491       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2492       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2493                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2494     {
2495       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2496         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2497           break;
2498
2499       if (i == 1)
2500         {
2501           /* We make I1 with the same INSN_UID as I2.  This gives it
2502              the same DF_INSN_LUID for value tracking.  Our fake I1 will
2503              never appear in the insn stream so giving it the same INSN_UID
2504              as I2 will not cause a problem.  */
2505
2506           i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2507                              BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2508                              XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX);
2509
2510           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2511           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2512                  SET_DEST (PATTERN (i1)));
2513         }
2514     }
2515 #endif
2516
2517   /* Verify that I2 and I1 are valid for combining.  */
2518   if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2519       || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2520     {
2521       undo_all ();
2522       return 0;
2523     }
2524
2525   /* Record whether I2DEST is used in I2SRC and similarly for the other
2526      cases.  Knowing this will help in register status updating below.  */
2527   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2528   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2529   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2530   i2dest_killed = dead_or_set_p (i2, i2dest);
2531   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2532
2533   /* See if I1 directly feeds into I3.  It does if I1DEST is not used
2534      in I2SRC.  */
2535   i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2536
2537   /* Ensure that I3's pattern can be the destination of combines.  */
2538   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2539                           i1 && i2dest_in_i1src && i1_feeds_i3,
2540                           &i3dest_killed))
2541     {
2542       undo_all ();
2543       return 0;
2544     }
2545
2546   /* See if any of the insns is a MULT operation.  Unless one is, we will
2547      reject a combination that is, since it must be slower.  Be conservative
2548      here.  */
2549   if (GET_CODE (i2src) == MULT
2550       || (i1 != 0 && GET_CODE (i1src) == MULT)
2551       || (GET_CODE (PATTERN (i3)) == SET
2552           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2553     have_mult = 1;
2554
2555   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2556      We used to do this EXCEPT in one case: I3 has a post-inc in an
2557      output operand.  However, that exception can give rise to insns like
2558         mov r3,(r3)+
2559      which is a famous insn on the PDP-11 where the value of r3 used as the
2560      source was model-dependent.  Avoid this sort of thing.  */
2561
2562 #if 0
2563   if (!(GET_CODE (PATTERN (i3)) == SET
2564         && REG_P (SET_SRC (PATTERN (i3)))
2565         && MEM_P (SET_DEST (PATTERN (i3)))
2566         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2567             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2568     /* It's not the exception.  */
2569 #endif
2570 #ifdef AUTO_INC_DEC
2571     for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2572       if (REG_NOTE_KIND (link) == REG_INC
2573           && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2574               || (i1 != 0
2575                   && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2576         {
2577           undo_all ();
2578           return 0;
2579         }
2580 #endif
2581
2582   /* See if the SETs in I1 or I2 need to be kept around in the merged
2583      instruction: whenever the value set there is still needed past I3.
2584      For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2585
2586      For the SET in I1, we have two cases:  If I1 and I2 independently
2587      feed into I3, the set in I1 needs to be kept around if I1DEST dies
2588      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2589      in I1 needs to be kept around unless I1DEST dies or is set in either
2590      I2 or I3.  We can distinguish these cases by seeing if I2SRC mentions
2591      I1DEST.  If so, we know I1 feeds into I2.  */
2592
2593   added_sets_2 = ! dead_or_set_p (i3, i2dest);
2594
2595   added_sets_1
2596     = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2597                : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2598
2599   /* If the set in I2 needs to be kept around, we must make a copy of
2600      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2601      PATTERN (I2), we are only substituting for the original I1DEST, not into
2602      an already-substituted copy.  This also prevents making self-referential
2603      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2604      I2DEST.  */
2605
2606   if (added_sets_2)
2607     {
2608       if (GET_CODE (PATTERN (i2)) == PARALLEL)
2609         i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2610       else
2611         i2pat = copy_rtx (PATTERN (i2));
2612     }
2613
2614   if (added_sets_1)
2615     {
2616       if (GET_CODE (PATTERN (i1)) == PARALLEL)
2617         i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2618       else
2619         i1pat = copy_rtx (PATTERN (i1));
2620     }
2621
2622   combine_merges++;
2623
2624   /* Substitute in the latest insn for the regs set by the earlier ones.  */
2625
2626   maxreg = max_reg_num ();
2627
2628   subst_insn = i3;
2629
2630 #ifndef HAVE_cc0
2631   /* Many machines that don't use CC0 have insns that can both perform an
2632      arithmetic operation and set the condition code.  These operations will
2633      be represented as a PARALLEL with the first element of the vector
2634      being a COMPARE of an arithmetic operation with the constant zero.
2635      The second element of the vector will set some pseudo to the result
2636      of the same arithmetic operation.  If we simplify the COMPARE, we won't
2637      match such a pattern and so will generate an extra insn.   Here we test
2638      for this case, where both the comparison and the operation result are
2639      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2640      I2SRC.  Later we will make the PARALLEL that contains I2.  */
2641
2642   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2643       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2644       && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2645       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2646     {
2647 #ifdef SELECT_CC_MODE
2648       rtx *cc_use;
2649       enum machine_mode compare_mode;
2650 #endif
2651
2652       newpat = PATTERN (i3);
2653       SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2654
2655       i2_is_used = 1;
2656
2657 #ifdef SELECT_CC_MODE
2658       /* See if a COMPARE with the operand we substituted in should be done
2659          with the mode that is currently being used.  If not, do the same
2660          processing we do in `subst' for a SET; namely, if the destination
2661          is used only once, try to replace it with a register of the proper
2662          mode and also replace the COMPARE.  */
2663       if (undobuf.other_insn == 0
2664           && (cc_use = find_single_use (SET_DEST (newpat), i3,
2665                                         &undobuf.other_insn))
2666           && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2667                                               i2src, const0_rtx))
2668               != GET_MODE (SET_DEST (newpat))))
2669         {
2670           if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2671                                    compare_mode))
2672             {
2673               unsigned int regno = REGNO (SET_DEST (newpat));
2674               rtx new_dest;
2675
2676               if (regno < FIRST_PSEUDO_REGISTER)
2677                 new_dest = gen_rtx_REG (compare_mode, regno);
2678               else
2679                 {
2680                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2681                   new_dest = regno_reg_rtx[regno];
2682                 }
2683
2684               SUBST (SET_DEST (newpat), new_dest);
2685               SUBST (XEXP (*cc_use, 0), new_dest);
2686               SUBST (SET_SRC (newpat),
2687                      gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2688             }
2689           else
2690             undobuf.other_insn = 0;
2691         }
2692 #endif
2693     }
2694   else
2695 #endif
2696     {
2697       /* It is possible that the source of I2 or I1 may be performing
2698          an unneeded operation, such as a ZERO_EXTEND of something
2699          that is known to have the high part zero.  Handle that case
2700          by letting subst look at the innermost one of them.
2701
2702          Another way to do this would be to have a function that tries
2703          to simplify a single insn instead of merging two or more
2704          insns.  We don't do this because of the potential of infinite
2705          loops and because of the potential extra memory required.
2706          However, doing it the way we are is a bit of a kludge and
2707          doesn't catch all cases.
2708
2709          But only do this if -fexpensive-optimizations since it slows
2710          things down and doesn't usually win.
2711
2712          This is not done in the COMPARE case above because the
2713          unmodified I2PAT is used in the PARALLEL and so a pattern
2714          with a modified I2SRC would not match.  */
2715
2716       if (flag_expensive_optimizations)
2717         {
2718           /* Pass pc_rtx so no substitutions are done, just
2719              simplifications.  */
2720           if (i1)
2721             {
2722               subst_low_luid = DF_INSN_LUID (i1);
2723               i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2724             }
2725           else
2726             {
2727               subst_low_luid = DF_INSN_LUID (i2);
2728               i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2729             }
2730         }
2731
2732       n_occurrences = 0;                /* `subst' counts here */
2733
2734       /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2735          need to make a unique copy of I2SRC each time we substitute it
2736          to avoid self-referential rtl.  */
2737
2738       subst_low_luid = DF_INSN_LUID (i2);
2739       newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2740                       ! i1_feeds_i3 && i1dest_in_i1src);
2741       substed_i2 = 1;
2742
2743       /* Record whether i2's body now appears within i3's body.  */
2744       i2_is_used = n_occurrences;
2745     }
2746
2747   /* If we already got a failure, don't try to do more.  Otherwise,
2748      try to substitute in I1 if we have it.  */
2749
2750   if (i1 && GET_CODE (newpat) != CLOBBER)
2751     {
2752       /* Before we can do this substitution, we must redo the test done
2753          above (see detailed comments there) that ensures  that I1DEST
2754          isn't mentioned in any SETs in NEWPAT that are field assignments.  */
2755
2756       if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2757                               0, (rtx*) 0))
2758         {
2759           undo_all ();
2760           return 0;
2761         }
2762
2763       n_occurrences = 0;
2764       subst_low_luid = DF_INSN_LUID (i1);
2765       newpat = subst (newpat, i1dest, i1src, 0, 0);
2766       substed_i1 = 1;
2767     }
2768
2769   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
2770      to count all the ways that I2SRC and I1SRC can be used.  */
2771   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2772        && i2_is_used + added_sets_2 > 1)
2773       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2774           && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2775               > 1))
2776       /* Fail if we tried to make a new register.  */
2777       || max_reg_num () != maxreg
2778       /* Fail if we couldn't do something and have a CLOBBER.  */
2779       || GET_CODE (newpat) == CLOBBER
2780       /* Fail if this new pattern is a MULT and we didn't have one before
2781          at the outer level.  */
2782       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2783           && ! have_mult))
2784     {
2785       undo_all ();
2786       return 0;
2787     }
2788
2789   /* If the actions of the earlier insns must be kept
2790      in addition to substituting them into the latest one,
2791      we must make a new PARALLEL for the latest insn
2792      to hold additional the SETs.  */
2793
2794   if (added_sets_1 || added_sets_2)
2795     {
2796       combine_extras++;
2797
2798       if (GET_CODE (newpat) == PARALLEL)
2799         {
2800           rtvec old = XVEC (newpat, 0);
2801           total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2802           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2803           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2804                   sizeof (old->elem[0]) * old->num_elem);
2805         }
2806       else
2807         {
2808           rtx old = newpat;
2809           total_sets = 1 + added_sets_1 + added_sets_2;
2810           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2811           XVECEXP (newpat, 0, 0) = old;
2812         }
2813
2814       if (added_sets_1)
2815         XVECEXP (newpat, 0, --total_sets) = i1pat;
2816
2817       if (added_sets_2)
2818         {
2819           /* If there is no I1, use I2's body as is.  We used to also not do
2820              the subst call below if I2 was substituted into I3,
2821              but that could lose a simplification.  */
2822           if (i1 == 0)
2823             XVECEXP (newpat, 0, --total_sets) = i2pat;
2824           else
2825             /* See comment where i2pat is assigned.  */
2826             XVECEXP (newpat, 0, --total_sets)
2827               = subst (i2pat, i1dest, i1src, 0, 0);
2828         }
2829     }
2830
2831   /* We come here when we are replacing a destination in I2 with the
2832      destination of I3.  */
2833  validate_replacement:
2834
2835   /* Note which hard regs this insn has as inputs.  */
2836   mark_used_regs_combine (newpat);
2837
2838   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
2839      consider splitting this pattern, we might need these clobbers.  */
2840   if (i1 && GET_CODE (newpat) == PARALLEL
2841       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2842     {
2843       int len = XVECLEN (newpat, 0);
2844
2845       newpat_vec_with_clobbers = rtvec_alloc (len);
2846       for (i = 0; i < len; i++)
2847         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2848     }
2849
2850   /* Is the result of combination a valid instruction?  */
2851   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2852
2853   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2854      the second SET's destination is a register that is unused and isn't
2855      marked as an instruction that might trap in an EH region.  In that case,
2856      we just need the first SET.   This can occur when simplifying a divmod
2857      insn.  We *must* test for this case here because the code below that
2858      splits two independent SETs doesn't handle this case correctly when it
2859      updates the register status.
2860
2861      It's pointless doing this if we originally had two sets, one from
2862      i3, and one from i2.  Combining then splitting the parallel results
2863      in the original i2 again plus an invalid insn (which we delete).
2864      The net effect is only to move instructions around, which makes
2865      debug info less accurate.
2866
2867      Also check the case where the first SET's destination is unused.
2868      That would not cause incorrect code, but does cause an unneeded
2869      insn to remain.  */
2870
2871   if (insn_code_number < 0
2872       && !(added_sets_2 && i1 == 0)
2873       && GET_CODE (newpat) == PARALLEL
2874       && XVECLEN (newpat, 0) == 2
2875       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2876       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2877       && asm_noperands (newpat) < 0)
2878     {
2879       rtx set0 = XVECEXP (newpat, 0, 0);
2880       rtx set1 = XVECEXP (newpat, 0, 1);
2881       rtx note;
2882
2883       if (((REG_P (SET_DEST (set1))
2884             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2885            || (GET_CODE (SET_DEST (set1)) == SUBREG
2886                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2887           && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2888               || INTVAL (XEXP (note, 0)) <= 0)
2889           && ! side_effects_p (SET_SRC (set1)))
2890         {
2891           newpat = set0;
2892           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2893         }
2894
2895       else if (((REG_P (SET_DEST (set0))
2896                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2897                 || (GET_CODE (SET_DEST (set0)) == SUBREG
2898                     && find_reg_note (i3, REG_UNUSED,
2899                                       SUBREG_REG (SET_DEST (set0)))))
2900                && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2901                    || INTVAL (XEXP (note, 0)) <= 0)
2902                && ! side_effects_p (SET_SRC (set0)))
2903         {
2904           newpat = set1;
2905           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2906
2907           if (insn_code_number >= 0)
2908             {
2909               /* If we will be able to accept this, we have made a
2910                  change to the destination of I3.  This requires us to
2911                  do a few adjustments.  */
2912
2913               PATTERN (i3) = newpat;
2914               adjust_for_new_dest (i3);
2915             }
2916         }
2917     }
2918
2919   /* If we were combining three insns and the result is a simple SET
2920      with no ASM_OPERANDS that wasn't recognized, try to split it into two
2921      insns.  There are two ways to do this.  It can be split using a
2922      machine-specific method (like when you have an addition of a large
2923      constant) or by combine in the function find_split_point.  */
2924
2925   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2926       && asm_noperands (newpat) < 0)
2927     {
2928       rtx parallel, m_split, *split;
2929
2930       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
2931          use I2DEST as a scratch register will help.  In the latter case,
2932          convert I2DEST to the mode of the source of NEWPAT if we can.  */
2933
2934       m_split = combine_split_insns (newpat, i3);
2935
2936       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2937          inputs of NEWPAT.  */
2938
2939       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2940          possible to try that as a scratch reg.  This would require adding
2941          more code to make it work though.  */
2942
2943       if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
2944         {
2945           enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2946
2947           /* First try to split using the original register as a
2948              scratch register.  */
2949           parallel = gen_rtx_PARALLEL (VOIDmode,
2950                                        gen_rtvec (2, newpat,
2951                                                   gen_rtx_CLOBBER (VOIDmode,
2952                                                                    i2dest)));
2953           m_split = combine_split_insns (parallel, i3);
2954
2955           /* If that didn't work, try changing the mode of I2DEST if
2956              we can.  */
2957           if (m_split == 0
2958               && new_mode != GET_MODE (i2dest)
2959               && new_mode != VOIDmode
2960               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2961             {
2962               enum machine_mode old_mode = GET_MODE (i2dest);
2963               rtx ni2dest;
2964
2965               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2966                 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
2967               else
2968                 {
2969                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
2970                   ni2dest = regno_reg_rtx[REGNO (i2dest)];
2971                 }
2972
2973               parallel = (gen_rtx_PARALLEL
2974                           (VOIDmode,
2975                            gen_rtvec (2, newpat,
2976                                       gen_rtx_CLOBBER (VOIDmode,
2977                                                        ni2dest))));
2978               m_split = combine_split_insns (parallel, i3);
2979
2980               if (m_split == 0
2981                   && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2982                 {
2983                   struct undo *buf;
2984
2985                   PUT_MODE (regno_reg_rtx[REGNO (i2dest)], old_mode);
2986                   buf = undobuf.undos;
2987                   undobuf.undos = buf->next;
2988                   buf->next = undobuf.frees;
2989                   undobuf.frees = buf;
2990                 }
2991             }
2992         }
2993
2994       /* If recog_for_combine has discarded clobbers, try to use them
2995          again for the split.  */
2996       if (m_split == 0 && newpat_vec_with_clobbers)
2997         {
2998           parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
2999           m_split = combine_split_insns (parallel, i3);
3000         }
3001
3002       if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3003         {
3004           m_split = PATTERN (m_split);
3005           insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3006           if (insn_code_number >= 0)
3007             newpat = m_split;
3008         }
3009       else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3010                && (next_real_insn (i2) == i3
3011                    || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3012         {
3013           rtx i2set, i3set;
3014           rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3015           newi2pat = PATTERN (m_split);
3016
3017           i3set = single_set (NEXT_INSN (m_split));
3018           i2set = single_set (m_split);
3019
3020           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3021
3022           /* If I2 or I3 has multiple SETs, we won't know how to track
3023              register status, so don't use these insns.  If I2's destination
3024              is used between I2 and I3, we also can't use these insns.  */
3025
3026           if (i2_code_number >= 0 && i2set && i3set
3027               && (next_real_insn (i2) == i3
3028                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3029             insn_code_number = recog_for_combine (&newi3pat, i3,
3030                                                   &new_i3_notes);
3031           if (insn_code_number >= 0)
3032             newpat = newi3pat;
3033
3034           /* It is possible that both insns now set the destination of I3.
3035              If so, we must show an extra use of it.  */
3036
3037           if (insn_code_number >= 0)
3038             {
3039               rtx new_i3_dest = SET_DEST (i3set);
3040               rtx new_i2_dest = SET_DEST (i2set);
3041
3042               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3043                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3044                      || GET_CODE (new_i3_dest) == SUBREG)
3045                 new_i3_dest = XEXP (new_i3_dest, 0);
3046
3047               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3048                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3049                      || GET_CODE (new_i2_dest) == SUBREG)
3050                 new_i2_dest = XEXP (new_i2_dest, 0);
3051
3052               if (REG_P (new_i3_dest)
3053                   && REG_P (new_i2_dest)
3054                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3055                 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3056             }
3057         }
3058
3059       /* If we can split it and use I2DEST, go ahead and see if that
3060          helps things be recognized.  Verify that none of the registers
3061          are set between I2 and I3.  */
3062       if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
3063 #ifdef HAVE_cc0
3064           && REG_P (i2dest)
3065 #endif
3066           /* We need I2DEST in the proper mode.  If it is a hard register
3067              or the only use of a pseudo, we can change its mode.
3068              Make sure we don't change a hard register to have a mode that
3069              isn't valid for it, or change the number of registers.  */
3070           && (GET_MODE (*split) == GET_MODE (i2dest)
3071               || GET_MODE (*split) == VOIDmode
3072               || can_change_dest_mode (i2dest, added_sets_2,
3073                                        GET_MODE (*split)))
3074           && (next_real_insn (i2) == i3
3075               || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3076           /* We can't overwrite I2DEST if its value is still used by
3077              NEWPAT.  */
3078           && ! reg_referenced_p (i2dest, newpat))
3079         {
3080           rtx newdest = i2dest;
3081           enum rtx_code split_code = GET_CODE (*split);
3082           enum machine_mode split_mode = GET_MODE (*split);
3083           bool subst_done = false;
3084           newi2pat = NULL_RTX;
3085
3086           /* Get NEWDEST as a register in the proper mode.  We have already
3087              validated that we can do this.  */
3088           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3089             {
3090               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3091                 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3092               else
3093                 {
3094                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3095                   newdest = regno_reg_rtx[REGNO (i2dest)];
3096                 }
3097             }
3098
3099           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3100              an ASHIFT.  This can occur if it was inside a PLUS and hence
3101              appeared to be a memory address.  This is a kludge.  */
3102           if (split_code == MULT
3103               && GET_CODE (XEXP (*split, 1)) == CONST_INT
3104               && INTVAL (XEXP (*split, 1)) > 0
3105               && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
3106             {
3107               SUBST (*split, gen_rtx_ASHIFT (split_mode,
3108                                              XEXP (*split, 0), GEN_INT (i)));
3109               /* Update split_code because we may not have a multiply
3110                  anymore.  */
3111               split_code = GET_CODE (*split);
3112             }
3113
3114 #ifdef INSN_SCHEDULING
3115           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3116              be written as a ZERO_EXTEND.  */
3117           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3118             {
3119 #ifdef LOAD_EXTEND_OP
3120               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3121                  what it really is.  */
3122               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3123                   == SIGN_EXTEND)
3124                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3125                                                     SUBREG_REG (*split)));
3126               else
3127 #endif
3128                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3129                                                     SUBREG_REG (*split)));
3130             }
3131 #endif
3132
3133           /* Attempt to split binary operators using arithmetic identities.  */
3134           if (BINARY_P (SET_SRC (newpat))
3135               && split_mode == GET_MODE (SET_SRC (newpat))
3136               && ! side_effects_p (SET_SRC (newpat)))
3137             {
3138               rtx setsrc = SET_SRC (newpat);
3139               enum machine_mode mode = GET_MODE (setsrc);
3140               enum rtx_code code = GET_CODE (setsrc);
3141               rtx src_op0 = XEXP (setsrc, 0);
3142               rtx src_op1 = XEXP (setsrc, 1);
3143
3144               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
3145               if (rtx_equal_p (src_op0, src_op1))
3146                 {
3147                   newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3148                   SUBST (XEXP (setsrc, 0), newdest);
3149                   SUBST (XEXP (setsrc, 1), newdest);
3150                   subst_done = true;
3151                 }
3152               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
3153               else if ((code == PLUS || code == MULT)
3154                        && GET_CODE (src_op0) == code
3155                        && GET_CODE (XEXP (src_op0, 0)) == code
3156                        && (INTEGRAL_MODE_P (mode)
3157                            || (FLOAT_MODE_P (mode)
3158                                && flag_unsafe_math_optimizations)))
3159                 {
3160                   rtx p = XEXP (XEXP (src_op0, 0), 0);
3161                   rtx q = XEXP (XEXP (src_op0, 0), 1);
3162                   rtx r = XEXP (src_op0, 1);
3163                   rtx s = src_op1;
3164
3165                   /* Split both "((X op Y) op X) op Y" and
3166                      "((X op Y) op Y) op X" as "T op T" where T is
3167                      "X op Y".  */
3168                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3169                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3170                     {
3171                       newi2pat = gen_rtx_SET (VOIDmode, newdest,
3172                                               XEXP (src_op0, 0));
3173                       SUBST (XEXP (setsrc, 0), newdest);
3174                       SUBST (XEXP (setsrc, 1), newdest);
3175                       subst_done = true;
3176                     }
3177                   /* Split "((X op X) op Y) op Y)" as "T op T" where
3178                      T is "X op Y".  */
3179                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3180                     {
3181                       rtx tmp = simplify_gen_binary (code, mode, p, r);
3182                       newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3183                       SUBST (XEXP (setsrc, 0), newdest);
3184                       SUBST (XEXP (setsrc, 1), newdest);
3185                       subst_done = true;
3186                     }
3187                 }
3188             }
3189
3190           if (!subst_done)
3191             {
3192               newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3193               SUBST (*split, newdest);
3194             }
3195
3196           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3197
3198           /* recog_for_combine might have added CLOBBERs to newi2pat.
3199              Make sure NEWPAT does not depend on the clobbered regs.  */
3200           if (GET_CODE (newi2pat) == PARALLEL)
3201             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3202               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3203                 {
3204                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3205                   if (reg_overlap_mentioned_p (reg, newpat))
3206                     {
3207                       undo_all ();
3208                       return 0;
3209                     }
3210                 }
3211
3212           /* If the split point was a MULT and we didn't have one before,
3213              don't use one now.  */
3214           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3215             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3216         }
3217     }
3218
3219   /* Check for a case where we loaded from memory in a narrow mode and
3220      then sign extended it, but we need both registers.  In that case,
3221      we have a PARALLEL with both loads from the same memory location.
3222      We can split this into a load from memory followed by a register-register
3223      copy.  This saves at least one insn, more if register allocation can
3224      eliminate the copy.
3225
3226      We cannot do this if the destination of the first assignment is a
3227      condition code register or cc0.  We eliminate this case by making sure
3228      the SET_DEST and SET_SRC have the same mode.
3229
3230      We cannot do this if the destination of the second assignment is
3231      a register that we have already assumed is zero-extended.  Similarly
3232      for a SUBREG of such a register.  */
3233
3234   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3235            && GET_CODE (newpat) == PARALLEL
3236            && XVECLEN (newpat, 0) == 2
3237            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3238            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3239            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3240                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3241            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3242            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3243                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3244            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3245                                    DF_INSN_LUID (i2))
3246            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3247            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3248            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3249                  (REG_P (temp)
3250                   && VEC_index (reg_stat_type, reg_stat,
3251                                 REGNO (temp))->nonzero_bits != 0
3252                   && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3253                   && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3254                   && (VEC_index (reg_stat_type, reg_stat,
3255                                  REGNO (temp))->nonzero_bits
3256                       != GET_MODE_MASK (word_mode))))
3257            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3258                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3259                      (REG_P (temp)
3260                       && VEC_index (reg_stat_type, reg_stat,
3261                                     REGNO (temp))->nonzero_bits != 0
3262                       && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3263                       && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3264                       && (VEC_index (reg_stat_type, reg_stat,
3265                                      REGNO (temp))->nonzero_bits
3266                           != GET_MODE_MASK (word_mode)))))
3267            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3268                                          SET_SRC (XVECEXP (newpat, 0, 1)))
3269            && ! find_reg_note (i3, REG_UNUSED,
3270                                SET_DEST (XVECEXP (newpat, 0, 0))))
3271     {
3272       rtx ni2dest;
3273
3274       newi2pat = XVECEXP (newpat, 0, 0);
3275       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3276       newpat = XVECEXP (newpat, 0, 1);
3277       SUBST (SET_SRC (newpat),
3278              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3279       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3280
3281       if (i2_code_number >= 0)
3282         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3283
3284       if (insn_code_number >= 0)
3285         swap_i2i3 = 1;
3286     }
3287
3288   /* Similarly, check for a case where we have a PARALLEL of two independent
3289      SETs but we started with three insns.  In this case, we can do the sets
3290      as two separate insns.  This case occurs when some SET allows two
3291      other insns to combine, but the destination of that SET is still live.  */
3292
3293   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3294            && GET_CODE (newpat) == PARALLEL
3295            && XVECLEN (newpat, 0) == 2
3296            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3297            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3298            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3299            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3300            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3301            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3302            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3303                                    DF_INSN_LUID (i2))
3304            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3305                                   XVECEXP (newpat, 0, 0))
3306            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3307                                   XVECEXP (newpat, 0, 1))
3308            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3309                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
3310 #ifdef HAVE_cc0
3311            /* We cannot split the parallel into two sets if both sets
3312               reference cc0.  */
3313            && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3314                  && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
3315 #endif
3316            )
3317     {
3318       /* Normally, it doesn't matter which of the two is done first,
3319          but it does if one references cc0.  In that case, it has to
3320          be first.  */
3321 #ifdef HAVE_cc0
3322       if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
3323         {
3324           newi2pat = XVECEXP (newpat, 0, 0);
3325           newpat = XVECEXP (newpat, 0, 1);
3326         }
3327       else
3328 #endif
3329         {
3330           newi2pat = XVECEXP (newpat, 0, 1);
3331           newpat = XVECEXP (newpat, 0, 0);
3332         }
3333
3334       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3335
3336       if (i2_code_number >= 0)
3337         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3338     }
3339
3340   /* If it still isn't recognized, fail and change things back the way they
3341      were.  */
3342   if ((insn_code_number < 0
3343        /* Is the result a reasonable ASM_OPERANDS?  */
3344        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3345     {
3346       undo_all ();
3347       return 0;
3348     }
3349
3350   /* If we had to change another insn, make sure it is valid also.  */
3351   if (undobuf.other_insn)
3352     {
3353       CLEAR_HARD_REG_SET (newpat_used_regs);
3354
3355       other_pat = PATTERN (undobuf.other_insn);
3356       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3357                                              &new_other_notes);
3358
3359       if (other_code_number < 0 && ! check_asm_operands (other_pat))
3360         {
3361           undo_all ();
3362           return 0;
3363         }
3364     }
3365
3366 #ifdef HAVE_cc0
3367   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3368      they are adjacent to each other or not.  */
3369   {
3370     rtx p = prev_nonnote_insn (i3);
3371     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3372         && sets_cc0_p (newi2pat))
3373       {
3374         undo_all ();
3375         return 0;
3376       }
3377   }
3378 #endif
3379
3380   /* Only allow this combination if insn_rtx_costs reports that the
3381      replacement instructions are cheaper than the originals.  */
3382   if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat, other_pat))
3383     {
3384       undo_all ();
3385       return 0;
3386     }
3387
3388   /* We now know that we can do this combination.  Merge the insns and
3389      update the status of registers and LOG_LINKS.  */
3390
3391   if (undobuf.other_insn)
3392     {
3393       rtx note, next;
3394
3395       PATTERN (undobuf.other_insn) = other_pat;
3396
3397       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3398          are still valid.  Then add any non-duplicate notes added by
3399          recog_for_combine.  */
3400       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3401         {
3402           next = XEXP (note, 1);
3403
3404           if (REG_NOTE_KIND (note) == REG_UNUSED
3405               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3406             remove_note (undobuf.other_insn, note);
3407         }
3408
3409       distribute_notes (new_other_notes, undobuf.other_insn,
3410                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
3411     }
3412
3413   if (swap_i2i3)
3414     {
3415       rtx insn;
3416       rtx link;
3417       rtx ni2dest;
3418
3419       /* I3 now uses what used to be its destination and which is now
3420          I2's destination.  This requires us to do a few adjustments.  */
3421       PATTERN (i3) = newpat;
3422       adjust_for_new_dest (i3);
3423
3424       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
3425          so we still will.
3426
3427          However, some later insn might be using I2's dest and have
3428          a LOG_LINK pointing at I3.  We must remove this link.
3429          The simplest way to remove the link is to point it at I1,
3430          which we know will be a NOTE.  */
3431
3432       /* newi2pat is usually a SET here; however, recog_for_combine might
3433          have added some clobbers.  */
3434       if (GET_CODE (newi2pat) == PARALLEL)
3435         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3436       else
3437         ni2dest = SET_DEST (newi2pat);
3438
3439       for (insn = NEXT_INSN (i3);
3440            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3441                     || insn != BB_HEAD (this_basic_block->next_bb));
3442            insn = NEXT_INSN (insn))
3443         {
3444           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3445             {
3446               for (link = LOG_LINKS (insn); link;
3447                    link = XEXP (link, 1))
3448                 if (XEXP (link, 0) == i3)
3449                   XEXP (link, 0) = i1;
3450
3451               break;
3452             }
3453         }
3454     }
3455
3456   {
3457     rtx i3notes, i2notes, i1notes = 0;
3458     rtx i3links, i2links, i1links = 0;
3459     rtx midnotes = 0;
3460     unsigned int regno;
3461     /* Compute which registers we expect to eliminate.  newi2pat may be setting
3462        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
3463        same as i3dest, in which case newi2pat may be setting i1dest.  */
3464     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3465                    || i2dest_in_i2src || i2dest_in_i1src
3466                    || !i2dest_killed
3467                    ? 0 : i2dest);
3468     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3469                    || (newi2pat && reg_set_p (i1dest, newi2pat))
3470                    || !i1dest_killed
3471                    ? 0 : i1dest);
3472
3473     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3474        clear them.  */
3475     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3476     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3477     if (i1)
3478       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3479
3480     /* Ensure that we do not have something that should not be shared but
3481        occurs multiple times in the new insns.  Check this by first
3482        resetting all the `used' flags and then copying anything is shared.  */
3483
3484     reset_used_flags (i3notes);
3485     reset_used_flags (i2notes);
3486     reset_used_flags (i1notes);
3487     reset_used_flags (newpat);
3488     reset_used_flags (newi2pat);
3489     if (undobuf.other_insn)
3490       reset_used_flags (PATTERN (undobuf.other_insn));
3491
3492     i3notes = copy_rtx_if_shared (i3notes);
3493     i2notes = copy_rtx_if_shared (i2notes);
3494     i1notes = copy_rtx_if_shared (i1notes);
3495     newpat = copy_rtx_if_shared (newpat);
3496     newi2pat = copy_rtx_if_shared (newi2pat);
3497     if (undobuf.other_insn)
3498       reset_used_flags (PATTERN (undobuf.other_insn));
3499
3500     INSN_CODE (i3) = insn_code_number;
3501     PATTERN (i3) = newpat;
3502
3503     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3504       {
3505         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3506
3507         reset_used_flags (call_usage);
3508         call_usage = copy_rtx (call_usage);
3509
3510         if (substed_i2)
3511           replace_rtx (call_usage, i2dest, i2src);
3512
3513         if (substed_i1)
3514           replace_rtx (call_usage, i1dest, i1src);
3515
3516         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3517       }
3518
3519     if (undobuf.other_insn)
3520       INSN_CODE (undobuf.other_insn) = other_code_number;
3521
3522     /* We had one special case above where I2 had more than one set and
3523        we replaced a destination of one of those sets with the destination
3524        of I3.  In that case, we have to update LOG_LINKS of insns later
3525        in this basic block.  Note that this (expensive) case is rare.
3526
3527        Also, in this case, we must pretend that all REG_NOTEs for I2
3528        actually came from I3, so that REG_UNUSED notes from I2 will be
3529        properly handled.  */
3530
3531     if (i3_subst_into_i2)
3532       {
3533         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3534           if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3535                || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3536               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3537               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3538               && ! find_reg_note (i2, REG_UNUSED,
3539                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3540             for (temp = NEXT_INSN (i2);
3541                  temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3542                           || BB_HEAD (this_basic_block) != temp);
3543                  temp = NEXT_INSN (temp))
3544               if (temp != i3 && INSN_P (temp))
3545                 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3546                   if (XEXP (link, 0) == i2)
3547                     XEXP (link, 0) = i3;
3548
3549         if (i3notes)
3550           {
3551             rtx link = i3notes;
3552             while (XEXP (link, 1))
3553               link = XEXP (link, 1);
3554             XEXP (link, 1) = i2notes;
3555           }
3556         else
3557           i3notes = i2notes;
3558         i2notes = 0;
3559       }
3560
3561     LOG_LINKS (i3) = 0;
3562     REG_NOTES (i3) = 0;
3563     LOG_LINKS (i2) = 0;
3564     REG_NOTES (i2) = 0;
3565
3566     if (newi2pat)
3567       {
3568         INSN_CODE (i2) = i2_code_number;
3569         PATTERN (i2) = newi2pat;
3570       }
3571     else
3572       SET_INSN_DELETED (i2);
3573
3574     if (i1)
3575       {
3576         LOG_LINKS (i1) = 0;
3577         REG_NOTES (i1) = 0;
3578         SET_INSN_DELETED (i1);
3579       }
3580
3581     /* Get death notes for everything that is now used in either I3 or
3582        I2 and used to die in a previous insn.  If we built two new
3583        patterns, move from I1 to I2 then I2 to I3 so that we get the
3584        proper movement on registers that I2 modifies.  */
3585
3586     if (newi2pat)
3587       {
3588         move_deaths (newi2pat, NULL_RTX, DF_INSN_LUID (i1), i2, &midnotes);
3589         move_deaths (newpat, newi2pat, DF_INSN_LUID (i1), i3, &midnotes);
3590       }
3591     else
3592       move_deaths (newpat, NULL_RTX, i1 ? DF_INSN_LUID (i1) : DF_INSN_LUID (i2),
3593                    i3, &midnotes);
3594
3595     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
3596     if (i3notes)
3597       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3598                         elim_i2, elim_i1);
3599     if (i2notes)
3600       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3601                         elim_i2, elim_i1);
3602     if (i1notes)
3603       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3604                         elim_i2, elim_i1);
3605     if (midnotes)
3606       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3607                         elim_i2, elim_i1);
3608
3609     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
3610        know these are REG_UNUSED and want them to go to the desired insn,
3611        so we always pass it as i3.  */
3612
3613     if (newi2pat && new_i2_notes)
3614       distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3615
3616     if (new_i3_notes)
3617       distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3618
3619     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
3620        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
3621        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
3622        in that case, it might delete I2.  Similarly for I2 and I1.
3623        Show an additional death due to the REG_DEAD note we make here.  If
3624        we discard it in distribute_notes, we will decrement it again.  */
3625
3626     if (i3dest_killed)
3627       {
3628         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3629           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3630                                                NULL_RTX),
3631                             NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3632         else
3633           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3634                                                NULL_RTX),
3635                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3636                             elim_i2, elim_i1);
3637       }
3638
3639     if (i2dest_in_i2src)
3640       {
3641         if (newi2pat && reg_set_p (i2dest, newi2pat))
3642           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3643                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3644         else
3645           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3646                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3647                             NULL_RTX, NULL_RTX);
3648       }
3649
3650     if (i1dest_in_i1src)
3651       {
3652         if (newi2pat && reg_set_p (i1dest, newi2pat))
3653           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3654                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3655         else
3656           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3657                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3658                             NULL_RTX, NULL_RTX);
3659       }
3660
3661     distribute_links (i3links);
3662     distribute_links (i2links);
3663     distribute_links (i1links);
3664
3665     if (REG_P (i2dest))
3666       {
3667         rtx link;
3668         rtx i2_insn = 0, i2_val = 0, set;
3669
3670         /* The insn that used to set this register doesn't exist, and
3671            this life of the register may not exist either.  See if one of
3672            I3's links points to an insn that sets I2DEST.  If it does,
3673            that is now the last known value for I2DEST. If we don't update
3674            this and I2 set the register to a value that depended on its old
3675            contents, we will get confused.  If this insn is used, thing
3676            will be set correctly in combine_instructions.  */
3677
3678         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3679           if ((set = single_set (XEXP (link, 0))) != 0
3680               && rtx_equal_p (i2dest, SET_DEST (set)))
3681             i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3682
3683         record_value_for_reg (i2dest, i2_insn, i2_val);
3684
3685         /* If the reg formerly set in I2 died only once and that was in I3,
3686            zero its use count so it won't make `reload' do any work.  */
3687         if (! added_sets_2
3688             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3689             && ! i2dest_in_i2src)
3690           {
3691             regno = REGNO (i2dest);
3692             INC_REG_N_SETS (regno, -1);
3693           }
3694       }
3695
3696     if (i1 && REG_P (i1dest))
3697       {
3698         rtx link;
3699         rtx i1_insn = 0, i1_val = 0, set;
3700
3701         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3702           if ((set = single_set (XEXP (link, 0))) != 0
3703               && rtx_equal_p (i1dest, SET_DEST (set)))
3704             i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3705
3706         record_value_for_reg (i1dest, i1_insn, i1_val);
3707
3708         regno = REGNO (i1dest);
3709         if (! added_sets_1 && ! i1dest_in_i1src)
3710           INC_REG_N_SETS (regno, -1);
3711       }
3712
3713     /* Update reg_stat[].nonzero_bits et al for any changes that may have
3714        been made to this insn.  The order of
3715        set_nonzero_bits_and_sign_copies() is important.  Because newi2pat
3716        can affect nonzero_bits of newpat */
3717     if (newi2pat)
3718       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3719     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3720
3721     /* Set new_direct_jump_p if a new return or simple jump instruction
3722        has been created.
3723
3724        If I3 is now an unconditional jump, ensure that it has a
3725        BARRIER following it since it may have initially been a
3726        conditional jump.  It may also be the last nonnote insn.  */
3727
3728     if (returnjump_p (i3) || any_uncondjump_p (i3))
3729       {
3730         *new_direct_jump_p = 1;
3731         mark_jump_label (PATTERN (i3), i3, 0);
3732
3733         if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3734             || !BARRIER_P (temp))
3735           emit_barrier_after (i3);
3736       }
3737
3738     if (undobuf.other_insn != NULL_RTX
3739         && (returnjump_p (undobuf.other_insn)
3740             || any_uncondjump_p (undobuf.other_insn)))
3741       {
3742         *new_direct_jump_p = 1;
3743
3744         if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3745             || !BARRIER_P (temp))
3746           emit_barrier_after (undobuf.other_insn);
3747       }
3748
3749     /* An NOOP jump does not need barrier, but it does need cleaning up
3750        of CFG.  */
3751     if (GET_CODE (newpat) == SET
3752         && SET_SRC (newpat) == pc_rtx
3753         && SET_DEST (newpat) == pc_rtx)
3754       *new_direct_jump_p = 1;
3755   }
3756
3757   if (undobuf.other_insn != NULL_RTX)
3758     {
3759       if (dump_file)
3760         {
3761           fprintf (dump_file, "modifying other_insn ");
3762           dump_insn_slim (dump_file, undobuf.other_insn);
3763         }
3764       df_insn_rescan (undobuf.other_insn);
3765     }
3766
3767   if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
3768     {
3769       if (dump_file)
3770         {
3771           fprintf (dump_file, "modifying insn i1 ");
3772           dump_insn_slim (dump_file, i1);
3773         }
3774       df_insn_rescan (i1);
3775     }
3776
3777   if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
3778     {
3779       if (dump_file)
3780         {
3781           fprintf (dump_file, "modifying insn i2 ");
3782           dump_insn_slim (dump_file, i2);
3783         }
3784       df_insn_rescan (i2);
3785     }
3786
3787   if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
3788     {
3789       if (dump_file)
3790         {
3791           fprintf (dump_file, "modifying insn i3 ");
3792           dump_insn_slim (dump_file, i3);
3793         }
3794       df_insn_rescan (i3);
3795     }
3796
3797   combine_successes++;
3798   undo_commit ();
3799
3800   if (added_links_insn
3801       && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
3802       && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
3803     return added_links_insn;
3804   else
3805     return newi2pat ? i2 : i3;
3806 }
3807 \f
3808 /* Undo all the modifications recorded in undobuf.  */
3809
3810 static void
3811 undo_all (void)
3812 {
3813   struct undo *undo, *next;
3814
3815   for (undo = undobuf.undos; undo; undo = next)
3816     {
3817       next = undo->next;
3818       switch (undo->kind)
3819         {
3820         case UNDO_RTX:
3821           *undo->where.r = undo->old_contents.r;
3822           break;
3823         case UNDO_INT:
3824           *undo->where.i = undo->old_contents.i;
3825           break;
3826         case UNDO_MODE:
3827           PUT_MODE (*undo->where.r, undo->old_contents.m);
3828           break;
3829         default:
3830           gcc_unreachable ();
3831         }
3832
3833       undo->next = undobuf.frees;
3834       undobuf.frees = undo;
3835     }
3836
3837   undobuf.undos = 0;
3838 }
3839
3840 /* We've committed to accepting the changes we made.  Move all
3841    of the undos to the free list.  */
3842
3843 static void
3844 undo_commit (void)
3845 {
3846   struct undo *undo, *next;
3847
3848   for (undo = undobuf.undos; undo; undo = next)
3849     {
3850       next = undo->next;
3851       undo->next = undobuf.frees;
3852       undobuf.frees = undo;
3853     }
3854   undobuf.undos = 0;
3855 }
3856 \f
3857 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3858    where we have an arithmetic expression and return that point.  LOC will
3859    be inside INSN.
3860
3861    try_combine will call this function to see if an insn can be split into
3862    two insns.  */
3863
3864 static rtx *
3865 find_split_point (rtx *loc, rtx insn)
3866 {
3867   rtx x = *loc;
3868   enum rtx_code code = GET_CODE (x);
3869   rtx *split;
3870   unsigned HOST_WIDE_INT len = 0;
3871   HOST_WIDE_INT pos = 0;
3872   int unsignedp = 0;
3873   rtx inner = NULL_RTX;
3874
3875   /* First special-case some codes.  */
3876   switch (code)
3877     {
3878     case SUBREG:
3879 #ifdef INSN_SCHEDULING
3880       /* If we are making a paradoxical SUBREG invalid, it becomes a split
3881          point.  */
3882       if (MEM_P (SUBREG_REG (x)))
3883         return loc;
3884 #endif
3885       return find_split_point (&SUBREG_REG (x), insn);
3886
3887     case MEM:
3888 #ifdef HAVE_lo_sum
3889       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3890          using LO_SUM and HIGH.  */
3891       if (GET_CODE (XEXP (x, 0)) == CONST
3892           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3893         {
3894           SUBST (XEXP (x, 0),
3895                  gen_rtx_LO_SUM (Pmode,
3896                                  gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3897                                  XEXP (x, 0)));
3898           return &XEXP (XEXP (x, 0), 0);
3899         }
3900 #endif
3901
3902       /* If we have a PLUS whose second operand is a constant and the
3903          address is not valid, perhaps will can split it up using
3904          the machine-specific way to split large constants.  We use
3905          the first pseudo-reg (one of the virtual regs) as a placeholder;
3906          it will not remain in the result.  */
3907       if (GET_CODE (XEXP (x, 0)) == PLUS
3908           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3909           && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3910         {
3911           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3912           rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
3913                                                       XEXP (x, 0)),
3914                                          subst_insn);
3915
3916           /* This should have produced two insns, each of which sets our
3917              placeholder.  If the source of the second is a valid address,
3918              we can make put both sources together and make a split point
3919              in the middle.  */
3920
3921           if (seq
3922               && NEXT_INSN (seq) != NULL_RTX
3923               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3924               && NONJUMP_INSN_P (seq)
3925               && GET_CODE (PATTERN (seq)) == SET
3926               && SET_DEST (PATTERN (seq)) == reg
3927               && ! reg_mentioned_p (reg,
3928                                     SET_SRC (PATTERN (seq)))
3929               && NONJUMP_INSN_P (NEXT_INSN (seq))
3930               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3931               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3932               && memory_address_p (GET_MODE (x),
3933                                    SET_SRC (PATTERN (NEXT_INSN (seq)))))
3934             {
3935               rtx src1 = SET_SRC (PATTERN (seq));
3936               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3937
3938               /* Replace the placeholder in SRC2 with SRC1.  If we can
3939                  find where in SRC2 it was placed, that can become our
3940                  split point and we can replace this address with SRC2.
3941                  Just try two obvious places.  */
3942
3943               src2 = replace_rtx (src2, reg, src1);
3944               split = 0;
3945               if (XEXP (src2, 0) == src1)
3946                 split = &XEXP (src2, 0);
3947               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3948                        && XEXP (XEXP (src2, 0), 0) == src1)
3949                 split = &XEXP (XEXP (src2, 0), 0);
3950
3951               if (split)
3952                 {
3953                   SUBST (XEXP (x, 0), src2);
3954                   return split;
3955                 }
3956             }
3957
3958           /* If that didn't work, perhaps the first operand is complex and
3959              needs to be computed separately, so make a split point there.
3960              This will occur on machines that just support REG + CONST
3961              and have a constant moved through some previous computation.  */
3962
3963           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3964                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3965                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3966             return &XEXP (XEXP (x, 0), 0);
3967         }
3968       break;
3969
3970     case SET:
3971 #ifdef HAVE_cc0
3972       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3973          ZERO_EXTRACT, the most likely reason why this doesn't match is that
3974          we need to put the operand into a register.  So split at that
3975          point.  */
3976
3977       if (SET_DEST (x) == cc0_rtx
3978           && GET_CODE (SET_SRC (x)) != COMPARE
3979           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3980           && !OBJECT_P (SET_SRC (x))
3981           && ! (GET_CODE (SET_SRC (x)) == SUBREG
3982                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3983         return &SET_SRC (x);
3984 #endif
3985
3986       /* See if we can split SET_SRC as it stands.  */
3987       split = find_split_point (&SET_SRC (x), insn);
3988       if (split && split != &SET_SRC (x))
3989         return split;
3990
3991       /* See if we can split SET_DEST as it stands.  */
3992       split = find_split_point (&SET_DEST (x), insn);
3993       if (split && split != &SET_DEST (x))
3994         return split;
3995
3996       /* See if this is a bitfield assignment with everything constant.  If
3997          so, this is an IOR of an AND, so split it into that.  */
3998       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3999           && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4000               <= HOST_BITS_PER_WIDE_INT)
4001           && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
4002           && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
4003           && GET_CODE (SET_SRC (x)) == CONST_INT
4004           && ((INTVAL (XEXP (SET_DEST (x), 1))
4005                + INTVAL (XEXP (SET_DEST (x), 2)))
4006               <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4007           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4008         {
4009           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4010           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4011           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4012           rtx dest = XEXP (SET_DEST (x), 0);
4013           enum machine_mode mode = GET_MODE (dest);
4014           unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
4015           rtx or_mask;
4016
4017           if (BITS_BIG_ENDIAN)
4018             pos = GET_MODE_BITSIZE (mode) - len - pos;
4019
4020           or_mask = gen_int_mode (src << pos, mode);
4021           if (src == mask)
4022             SUBST (SET_SRC (x),
4023                    simplify_gen_binary (IOR, mode, dest, or_mask));
4024           else
4025             {
4026               rtx negmask = gen_int_mode (~(mask << pos), mode);
4027               SUBST (SET_SRC (x),
4028                      simplify_gen_binary (IOR, mode,
4029                                           simplify_gen_binary (AND, mode,
4030                                                                dest, negmask),
4031                                           or_mask));
4032             }
4033
4034           SUBST (SET_DEST (x), dest);
4035
4036           split = find_split_point (&SET_SRC (x), insn);
4037           if (split && split != &SET_SRC (x))
4038             return split;
4039         }
4040
4041       /* Otherwise, see if this is an operation that we can split into two.
4042          If so, try to split that.  */
4043       code = GET_CODE (SET_SRC (x));
4044
4045       switch (code)
4046         {
4047         case AND:
4048           /* If we are AND'ing with a large constant that is only a single
4049              bit and the result is only being used in a context where we
4050              need to know if it is zero or nonzero, replace it with a bit
4051              extraction.  This will avoid the large constant, which might
4052              have taken more than one insn to make.  If the constant were
4053              not a valid argument to the AND but took only one insn to make,
4054              this is no worse, but if it took more than one insn, it will
4055              be better.  */
4056
4057           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
4058               && REG_P (XEXP (SET_SRC (x), 0))
4059               && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4060               && REG_P (SET_DEST (x))
4061               && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4062               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4063               && XEXP (*split, 0) == SET_DEST (x)
4064               && XEXP (*split, 1) == const0_rtx)
4065             {
4066               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4067                                                 XEXP (SET_SRC (x), 0),
4068                                                 pos, NULL_RTX, 1, 1, 0, 0);
4069               if (extraction != 0)
4070                 {
4071                   SUBST (SET_SRC (x), extraction);
4072                   return find_split_point (loc, insn);
4073                 }
4074             }
4075           break;
4076
4077         case NE:
4078           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4079              is known to be on, this can be converted into a NEG of a shift.  */
4080           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4081               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4082               && 1 <= (pos = exact_log2
4083                        (nonzero_bits (XEXP (SET_SRC (x), 0),
4084                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
4085             {
4086               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4087
4088               SUBST (SET_SRC (x),
4089                      gen_rtx_NEG (mode,
4090                                   gen_rtx_LSHIFTRT (mode,
4091                                                     XEXP (SET_SRC (x), 0),
4092                                                     GEN_INT (pos))));
4093
4094               split = find_split_point (&SET_SRC (x), insn);
4095               if (split && split != &SET_SRC (x))
4096                 return split;
4097             }
4098           break;
4099
4100         case SIGN_EXTEND:
4101           inner = XEXP (SET_SRC (x), 0);
4102
4103           /* We can't optimize if either mode is a partial integer
4104              mode as we don't know how many bits are significant
4105              in those modes.  */
4106           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4107               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4108             break;
4109
4110           pos = 0;
4111           len = GET_MODE_BITSIZE (GET_MODE (inner));
4112           unsignedp = 0;
4113           break;
4114
4115         case SIGN_EXTRACT:
4116         case ZERO_EXTRACT:
4117           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
4118               && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
4119             {
4120               inner = XEXP (SET_SRC (x), 0);
4121               len = INTVAL (XEXP (SET_SRC (x), 1));
4122               pos = INTVAL (XEXP (SET_SRC (x), 2));
4123
4124               if (BITS_BIG_ENDIAN)
4125                 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4126               unsignedp = (code == ZERO_EXTRACT);
4127             }
4128           break;
4129
4130         default:
4131           break;
4132         }
4133
4134       if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4135         {
4136           enum machine_mode mode = GET_MODE (SET_SRC (x));
4137
4138           /* For unsigned, we have a choice of a shift followed by an
4139              AND or two shifts.  Use two shifts for field sizes where the
4140              constant might be too large.  We assume here that we can
4141              always at least get 8-bit constants in an AND insn, which is
4142              true for every current RISC.  */
4143
4144           if (unsignedp && len <= 8)
4145             {
4146               SUBST (SET_SRC (x),
4147                      gen_rtx_AND (mode,
4148                                   gen_rtx_LSHIFTRT
4149                                   (mode, gen_lowpart (mode, inner),
4150                                    GEN_INT (pos)),
4151                                   GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
4152
4153               split = find_split_point (&SET_SRC (x), insn);
4154               if (split && split != &SET_SRC (x))
4155                 return split;
4156             }
4157           else
4158             {
4159               SUBST (SET_SRC (x),
4160                      gen_rtx_fmt_ee
4161                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4162                       gen_rtx_ASHIFT (mode,
4163                                       gen_lowpart (mode, inner),
4164                                       GEN_INT (GET_MODE_BITSIZE (mode)
4165                                                - len - pos)),
4166                       GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4167
4168               split = find_split_point (&SET_SRC (x), insn);
4169               if (split && split != &SET_SRC (x))
4170                 return split;
4171             }
4172         }
4173
4174       /* See if this is a simple operation with a constant as the second
4175          operand.  It might be that this constant is out of range and hence
4176          could be used as a split point.  */
4177       if (BINARY_P (SET_SRC (x))
4178           && CONSTANT_P (XEXP (SET_SRC (x), 1))
4179           && (OBJECT_P (XEXP (SET_SRC (x), 0))
4180               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4181                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4182         return &XEXP (SET_SRC (x), 1);
4183
4184       /* Finally, see if this is a simple operation with its first operand
4185          not in a register.  The operation might require this operand in a
4186          register, so return it as a split point.  We can always do this
4187          because if the first operand were another operation, we would have
4188          already found it as a split point.  */
4189       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4190           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4191         return &XEXP (SET_SRC (x), 0);
4192
4193       return 0;
4194
4195     case AND:
4196     case IOR:
4197       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4198          it is better to write this as (not (ior A B)) so we can split it.
4199          Similarly for IOR.  */
4200       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4201         {
4202           SUBST (*loc,
4203                  gen_rtx_NOT (GET_MODE (x),
4204                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4205                                               GET_MODE (x),
4206                                               XEXP (XEXP (x, 0), 0),
4207                                               XEXP (XEXP (x, 1), 0))));
4208           return find_split_point (loc, insn);
4209         }
4210
4211       /* Many RISC machines have a large set of logical insns.  If the
4212          second operand is a NOT, put it first so we will try to split the
4213          other operand first.  */
4214       if (GET_CODE (XEXP (x, 1)) == NOT)
4215         {
4216           rtx tem = XEXP (x, 0);
4217           SUBST (XEXP (x, 0), XEXP (x, 1));
4218           SUBST (XEXP (x, 1), tem);
4219         }
4220       break;
4221
4222     default:
4223       break;
4224     }
4225
4226   /* Otherwise, select our actions depending on our rtx class.  */
4227   switch (GET_RTX_CLASS (code))
4228     {
4229     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
4230     case RTX_TERNARY:
4231       split = find_split_point (&XEXP (x, 2), insn);
4232       if (split)
4233         return split;
4234       /* ... fall through ...  */
4235     case RTX_BIN_ARITH:
4236     case RTX_COMM_ARITH:
4237     case RTX_COMPARE:
4238     case RTX_COMM_COMPARE:
4239       split = find_split_point (&XEXP (x, 1), insn);
4240       if (split)
4241         return split;
4242       /* ... fall through ...  */
4243     case RTX_UNARY:
4244       /* Some machines have (and (shift ...) ...) insns.  If X is not
4245          an AND, but XEXP (X, 0) is, use it as our split point.  */
4246       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4247         return &XEXP (x, 0);
4248
4249       split = find_split_point (&XEXP (x, 0), insn);
4250       if (split)
4251         return split;
4252       return loc;
4253
4254     default:
4255       /* Otherwise, we don't have a split point.  */
4256       return 0;
4257     }
4258 }
4259 \f
4260 /* Throughout X, replace FROM with TO, and return the result.
4261    The result is TO if X is FROM;
4262    otherwise the result is X, but its contents may have been modified.
4263    If they were modified, a record was made in undobuf so that
4264    undo_all will (among other things) return X to its original state.
4265
4266    If the number of changes necessary is too much to record to undo,
4267    the excess changes are not made, so the result is invalid.
4268    The changes already made can still be undone.
4269    undobuf.num_undo is incremented for such changes, so by testing that
4270    the caller can tell whether the result is valid.
4271
4272    `n_occurrences' is incremented each time FROM is replaced.
4273
4274    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4275
4276    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
4277    by copying if `n_occurrences' is nonzero.  */
4278
4279 static rtx
4280 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4281 {
4282   enum rtx_code code = GET_CODE (x);
4283   enum machine_mode op0_mode = VOIDmode;
4284   const char *fmt;
4285   int len, i;
4286   rtx new;
4287
4288 /* Two expressions are equal if they are identical copies of a shared
4289    RTX or if they are both registers with the same register number
4290    and mode.  */
4291
4292 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
4293   ((X) == (Y)                                           \
4294    || (REG_P (X) && REG_P (Y)   \
4295        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4296
4297   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4298     {
4299       n_occurrences++;
4300       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4301     }
4302
4303   /* If X and FROM are the same register but different modes, they
4304      will not have been seen as equal above.  However, the log links code
4305      will make a LOG_LINKS entry for that case.  If we do nothing, we
4306      will try to rerecognize our original insn and, when it succeeds,
4307      we will delete the feeding insn, which is incorrect.
4308
4309      So force this insn not to match in this (rare) case.  */
4310   if (! in_dest && code == REG && REG_P (from)
4311       && reg_overlap_mentioned_p (x, from))
4312     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4313
4314   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4315      of which may contain things that can be combined.  */
4316   if (code != MEM && code != LO_SUM && OBJECT_P (x))
4317     return x;
4318
4319   /* It is possible to have a subexpression appear twice in the insn.
4320      Suppose that FROM is a register that appears within TO.
4321      Then, after that subexpression has been scanned once by `subst',
4322      the second time it is scanned, TO may be found.  If we were
4323      to scan TO here, we would find FROM within it and create a
4324      self-referent rtl structure which is completely wrong.  */
4325   if (COMBINE_RTX_EQUAL_P (x, to))
4326     return to;
4327
4328   /* Parallel asm_operands need special attention because all of the
4329      inputs are shared across the arms.  Furthermore, unsharing the
4330      rtl results in recognition failures.  Failure to handle this case
4331      specially can result in circular rtl.
4332
4333      Solve this by doing a normal pass across the first entry of the
4334      parallel, and only processing the SET_DESTs of the subsequent
4335      entries.  Ug.  */
4336
4337   if (code == PARALLEL
4338       && GET_CODE (XVECEXP (x, 0, 0)) == SET
4339       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4340     {
4341       new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4342
4343       /* If this substitution failed, this whole thing fails.  */
4344       if (GET_CODE (new) == CLOBBER
4345           && XEXP (new, 0) == const0_rtx)
4346         return new;
4347
4348       SUBST (XVECEXP (x, 0, 0), new);
4349
4350       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4351         {
4352           rtx dest = SET_DEST (XVECEXP (x, 0, i));
4353
4354           if (!REG_P (dest)
4355               && GET_CODE (dest) != CC0
4356               && GET_CODE (dest) != PC)
4357             {
4358               new = subst (dest, from, to, 0, unique_copy);
4359
4360               /* If this substitution failed, this whole thing fails.  */
4361               if (GET_CODE (new) == CLOBBER
4362                   && XEXP (new, 0) == const0_rtx)
4363                 return new;
4364
4365               SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
4366             }
4367         }
4368     }
4369   else
4370     {
4371       len = GET_RTX_LENGTH (code);
4372       fmt = GET_RTX_FORMAT (code);
4373
4374       /* We don't need to process a SET_DEST that is a register, CC0,
4375          or PC, so set up to skip this common case.  All other cases
4376          where we want to suppress replacing something inside a
4377          SET_SRC are handled via the IN_DEST operand.  */
4378       if (code == SET
4379           && (REG_P (SET_DEST (x))
4380               || GET_CODE (SET_DEST (x)) == CC0
4381               || GET_CODE (SET_DEST (x)) == PC))
4382         fmt = "ie";
4383
4384       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4385          constant.  */
4386       if (fmt[0] == 'e')
4387         op0_mode = GET_MODE (XEXP (x, 0));
4388
4389       for (i = 0; i < len; i++)
4390         {
4391           if (fmt[i] == 'E')
4392             {
4393               int j;
4394               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4395                 {
4396                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4397                     {
4398                       new = (unique_copy && n_occurrences
4399                              ? copy_rtx (to) : to);
4400                       n_occurrences++;
4401                     }
4402                   else
4403                     {
4404                       new = subst (XVECEXP (x, i, j), from, to, 0,
4405                                    unique_copy);
4406
4407                       /* If this substitution failed, this whole thing
4408                          fails.  */
4409                       if (GET_CODE (new) == CLOBBER
4410                           && XEXP (new, 0) == const0_rtx)
4411                         return new;
4412                     }
4413
4414                   SUBST (XVECEXP (x, i, j), new);
4415                 }
4416             }
4417           else if (fmt[i] == 'e')
4418             {
4419               /* If this is a register being set, ignore it.  */
4420               new = XEXP (x, i);
4421               if (in_dest
4422                   && i == 0
4423                   && (((code == SUBREG || code == ZERO_EXTRACT)
4424                        && REG_P (new))
4425                       || code == STRICT_LOW_PART))
4426                 ;
4427
4428               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4429                 {
4430                   /* In general, don't install a subreg involving two
4431                      modes not tieable.  It can worsen register
4432                      allocation, and can even make invalid reload
4433                      insns, since the reg inside may need to be copied
4434                      from in the outside mode, and that may be invalid
4435                      if it is an fp reg copied in integer mode.
4436
4437                      We allow two exceptions to this: It is valid if
4438                      it is inside another SUBREG and the mode of that
4439                      SUBREG and the mode of the inside of TO is
4440                      tieable and it is valid if X is a SET that copies
4441                      FROM to CC0.  */
4442
4443                   if (GET_CODE (to) == SUBREG
4444                       && ! MODES_TIEABLE_P (GET_MODE (to),
4445                                             GET_MODE (SUBREG_REG (to)))
4446                       && ! (code == SUBREG
4447                             && MODES_TIEABLE_P (GET_MODE (x),
4448                                                 GET_MODE (SUBREG_REG (to))))
4449 #ifdef HAVE_cc0
4450                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4451 #endif
4452                       )
4453                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4454
4455 #ifdef CANNOT_CHANGE_MODE_CLASS
4456                   if (code == SUBREG
4457                       && REG_P (to)
4458                       && REGNO (to) < FIRST_PSEUDO_REGISTER
4459                       && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4460                                                    GET_MODE (to),
4461                                                    GET_MODE (x)))
4462                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4463 #endif
4464
4465                   new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4466                   n_occurrences++;
4467                 }
4468               else
4469                 /* If we are in a SET_DEST, suppress most cases unless we
4470                    have gone inside a MEM, in which case we want to
4471                    simplify the address.  We assume here that things that
4472                    are actually part of the destination have their inner
4473                    parts in the first expression.  This is true for SUBREG,
4474                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4475                    things aside from REG and MEM that should appear in a
4476                    SET_DEST.  */
4477                 new = subst (XEXP (x, i), from, to,
4478                              (((in_dest
4479                                 && (code == SUBREG || code == STRICT_LOW_PART
4480                                     || code == ZERO_EXTRACT))
4481                                || code == SET)
4482                               && i == 0), unique_copy);
4483
4484               /* If we found that we will have to reject this combination,
4485                  indicate that by returning the CLOBBER ourselves, rather than
4486                  an expression containing it.  This will speed things up as
4487                  well as prevent accidents where two CLOBBERs are considered
4488                  to be equal, thus producing an incorrect simplification.  */
4489
4490               if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
4491                 return new;
4492
4493               if (GET_CODE (x) == SUBREG
4494                   && (GET_CODE (new) == CONST_INT
4495                       || GET_CODE (new) == CONST_DOUBLE))
4496                 {
4497                   enum machine_mode mode = GET_MODE (x);
4498
4499                   x = simplify_subreg (GET_MODE (x), new,
4500                                        GET_MODE (SUBREG_REG (x)),
4501                                        SUBREG_BYTE (x));
4502                   if (! x)
4503                     x = gen_rtx_CLOBBER (mode, const0_rtx);
4504                 }
4505               else if (GET_CODE (new) == CONST_INT
4506                        && GET_CODE (x) == ZERO_EXTEND)
4507                 {
4508                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4509                                                 new, GET_MODE (XEXP (x, 0)));
4510                   gcc_assert (x);
4511                 }
4512               else
4513                 SUBST (XEXP (x, i), new);
4514             }
4515         }
4516     }
4517
4518   /* Check if we are loading something from the constant pool via float
4519      extension; in this case we would undo compress_float_constant
4520      optimization and degenerate constant load to an immediate value.  */
4521   if (GET_CODE (x) == FLOAT_EXTEND
4522       && MEM_P (XEXP (x, 0))
4523       && MEM_READONLY_P (XEXP (x, 0)))
4524     {
4525       rtx tmp = avoid_constant_pool_reference (x);
4526       if (x != tmp)
4527         return x;
4528     }
4529
4530   /* Try to simplify X.  If the simplification changed the code, it is likely
4531      that further simplification will help, so loop, but limit the number
4532      of repetitions that will be performed.  */
4533
4534   for (i = 0; i < 4; i++)
4535     {
4536       /* If X is sufficiently simple, don't bother trying to do anything
4537          with it.  */
4538       if (code != CONST_INT && code != REG && code != CLOBBER)
4539         x = combine_simplify_rtx (x, op0_mode, in_dest);
4540
4541       if (GET_CODE (x) == code)
4542         break;
4543
4544       code = GET_CODE (x);
4545
4546       /* We no longer know the original mode of operand 0 since we
4547          have changed the form of X)  */
4548       op0_mode = VOIDmode;
4549     }
4550
4551   return x;
4552 }
4553 \f
4554 /* Simplify X, a piece of RTL.  We just operate on the expression at the
4555    outer level; call `subst' to simplify recursively.  Return the new
4556    expression.
4557
4558    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
4559    if we are inside a SET_DEST.  */
4560
4561 static rtx
4562 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4563 {
4564   enum rtx_code code = GET_CODE (x);
4565   enum machine_mode mode = GET_MODE (x);
4566   rtx temp;
4567   int i;
4568
4569   /* If this is a commutative operation, put a constant last and a complex
4570      expression first.  We don't need to do this for comparisons here.  */
4571   if (COMMUTATIVE_ARITH_P (x)
4572       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4573     {
4574       temp = XEXP (x, 0);
4575       SUBST (XEXP (x, 0), XEXP (x, 1));
4576       SUBST (XEXP (x, 1), temp);
4577     }
4578
4579   /* If this is a simple operation applied to an IF_THEN_ELSE, try
4580      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
4581      things.  Check for cases where both arms are testing the same
4582      condition.
4583
4584      Don't do anything if all operands are very simple.  */
4585
4586   if ((BINARY_P (x)
4587        && ((!OBJECT_P (XEXP (x, 0))
4588             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4589                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4590            || (!OBJECT_P (XEXP (x, 1))
4591                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4592                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4593       || (UNARY_P (x)
4594           && (!OBJECT_P (XEXP (x, 0))
4595                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4596                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4597     {
4598       rtx cond, true_rtx, false_rtx;
4599
4600       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4601       if (cond != 0
4602           /* If everything is a comparison, what we have is highly unlikely
4603              to be simpler, so don't use it.  */
4604           && ! (COMPARISON_P (x)
4605                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4606         {
4607           rtx cop1 = const0_rtx;
4608           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4609
4610           if (cond_code == NE && COMPARISON_P (cond))
4611             return x;
4612
4613           /* Simplify the alternative arms; this may collapse the true and
4614              false arms to store-flag values.  Be careful to use copy_rtx
4615              here since true_rtx or false_rtx might share RTL with x as a
4616              result of the if_then_else_cond call above.  */
4617           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4618           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4619
4620           /* If true_rtx and false_rtx are not general_operands, an if_then_else
4621              is unlikely to be simpler.  */
4622           if (general_operand (true_rtx, VOIDmode)
4623               && general_operand (false_rtx, VOIDmode))
4624             {
4625               enum rtx_code reversed;
4626
4627               /* Restarting if we generate a store-flag expression will cause
4628                  us to loop.  Just drop through in this case.  */
4629
4630               /* If the result values are STORE_FLAG_VALUE and zero, we can
4631                  just make the comparison operation.  */
4632               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4633                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4634                                              cond, cop1);
4635               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4636                        && ((reversed = reversed_comparison_code_parts
4637                                         (cond_code, cond, cop1, NULL))
4638                            != UNKNOWN))
4639                 x = simplify_gen_relational (reversed, mode, VOIDmode,
4640                                              cond, cop1);
4641
4642               /* Likewise, we can make the negate of a comparison operation
4643                  if the result values are - STORE_FLAG_VALUE and zero.  */
4644               else if (GET_CODE (true_rtx) == CONST_INT
4645                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4646                        && false_rtx == const0_rtx)
4647                 x = simplify_gen_unary (NEG, mode,
4648                                         simplify_gen_relational (cond_code,
4649                                                                  mode, VOIDmode,
4650                                                                  cond, cop1),
4651                                         mode);
4652               else if (GET_CODE (false_rtx) == CONST_INT
4653                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4654                        && true_rtx == const0_rtx
4655                        && ((reversed = reversed_comparison_code_parts
4656                                         (cond_code, cond, cop1, NULL))
4657                            != UNKNOWN))
4658                 x = simplify_gen_unary (NEG, mode,
4659                                         simplify_gen_relational (reversed,
4660                                                                  mode, VOIDmode,
4661                                                                  cond, cop1),
4662                                         mode);
4663               else
4664                 return gen_rtx_IF_THEN_ELSE (mode,
4665                                              simplify_gen_relational (cond_code,
4666                                                                       mode,
4667                                                                       VOIDmode,
4668                                                                       cond,
4669                                                                       cop1),
4670                                              true_rtx, false_rtx);
4671
4672               code = GET_CODE (x);
4673               op0_mode = VOIDmode;
4674             }
4675         }
4676     }
4677
4678   /* Try to fold this expression in case we have constants that weren't
4679      present before.  */
4680   temp = 0;
4681   switch (GET_RTX_CLASS (code))
4682     {
4683     case RTX_UNARY:
4684       if (op0_mode == VOIDmode)
4685         op0_mode = GET_MODE (XEXP (x, 0));
4686       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4687       break;
4688     case RTX_COMPARE:
4689     case RTX_COMM_COMPARE:
4690       {
4691         enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4692         if (cmp_mode == VOIDmode)
4693           {
4694             cmp_mode = GET_MODE (XEXP (x, 1));
4695             if (cmp_mode == VOIDmode)
4696               cmp_mode = op0_mode;
4697           }
4698         temp = simplify_relational_operation (code, mode, cmp_mode,
4699                                               XEXP (x, 0), XEXP (x, 1));
4700       }
4701       break;
4702     case RTX_COMM_ARITH:
4703     case RTX_BIN_ARITH:
4704       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4705       break;
4706     case RTX_BITFIELD_OPS:
4707     case RTX_TERNARY:
4708       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4709                                          XEXP (x, 1), XEXP (x, 2));
4710       break;
4711     default:
4712       break;
4713     }
4714
4715   if (temp)
4716     {
4717       x = temp;
4718       code = GET_CODE (temp);
4719       op0_mode = VOIDmode;
4720       mode = GET_MODE (temp);
4721     }
4722
4723   /* First see if we can apply the inverse distributive law.  */
4724   if (code == PLUS || code == MINUS
4725       || code == AND || code == IOR || code == XOR)
4726     {
4727       x = apply_distributive_law (x);
4728       code = GET_CODE (x);
4729       op0_mode = VOIDmode;
4730     }
4731
4732   /* If CODE is an associative operation not otherwise handled, see if we
4733      can associate some operands.  This can win if they are constants or
4734      if they are logically related (i.e. (a & b) & a).  */
4735   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4736        || code == AND || code == IOR || code == XOR
4737        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4738       && ((INTEGRAL_MODE_P (mode) && code != DIV)
4739           || (flag_associative_math && FLOAT_MODE_P (mode))))
4740     {
4741       if (GET_CODE (XEXP (x, 0)) == code)
4742         {
4743           rtx other = XEXP (XEXP (x, 0), 0);
4744           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4745           rtx inner_op1 = XEXP (x, 1);
4746           rtx inner;
4747
4748           /* Make sure we pass the constant operand if any as the second
4749              one if this is a commutative operation.  */
4750           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4751             {
4752               rtx tem = inner_op0;
4753               inner_op0 = inner_op1;
4754               inner_op1 = tem;
4755             }
4756           inner = simplify_binary_operation (code == MINUS ? PLUS
4757                                              : code == DIV ? MULT
4758                                              : code,
4759                                              mode, inner_op0, inner_op1);
4760
4761           /* For commutative operations, try the other pair if that one
4762              didn't simplify.  */
4763           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4764             {
4765               other = XEXP (XEXP (x, 0), 1);
4766               inner = simplify_binary_operation (code, mode,
4767                                                  XEXP (XEXP (x, 0), 0),
4768                                                  XEXP (x, 1));
4769             }
4770
4771           if (inner)
4772             return simplify_gen_binary (code, mode, other, inner);
4773         }
4774     }
4775
4776   /* A little bit of algebraic simplification here.  */
4777   switch (code)
4778     {
4779     case MEM:
4780       /* Ensure that our address has any ASHIFTs converted to MULT in case
4781          address-recognizing predicates are called later.  */
4782       temp = make_compound_operation (XEXP (x, 0), MEM);
4783       SUBST (XEXP (x, 0), temp);
4784       break;
4785
4786     case SUBREG:
4787       if (op0_mode == VOIDmode)
4788         op0_mode = GET_MODE (SUBREG_REG (x));
4789
4790       /* See if this can be moved to simplify_subreg.  */
4791       if (CONSTANT_P (SUBREG_REG (x))
4792           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4793              /* Don't call gen_lowpart if the inner mode
4794                 is VOIDmode and we cannot simplify it, as SUBREG without
4795                 inner mode is invalid.  */
4796           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4797               || gen_lowpart_common (mode, SUBREG_REG (x))))
4798         return gen_lowpart (mode, SUBREG_REG (x));
4799
4800       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4801         break;
4802       {
4803         rtx temp;
4804         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4805                                 SUBREG_BYTE (x));
4806         if (temp)
4807           return temp;
4808       }
4809
4810       /* Don't change the mode of the MEM if that would change the meaning
4811          of the address.  */
4812       if (MEM_P (SUBREG_REG (x))
4813           && (MEM_VOLATILE_P (SUBREG_REG (x))
4814               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4815         return gen_rtx_CLOBBER (mode, const0_rtx);
4816
4817       /* Note that we cannot do any narrowing for non-constants since
4818          we might have been counting on using the fact that some bits were
4819          zero.  We now do this in the SET.  */
4820
4821       break;
4822
4823     case NEG:
4824       temp = expand_compound_operation (XEXP (x, 0));
4825
4826       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4827          replaced by (lshiftrt X C).  This will convert
4828          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
4829
4830       if (GET_CODE (temp) == ASHIFTRT
4831           && GET_CODE (XEXP (temp, 1)) == CONST_INT
4832           && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4833         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4834                                      INTVAL (XEXP (temp, 1)));
4835
4836       /* If X has only a single bit that might be nonzero, say, bit I, convert
4837          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4838          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
4839          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
4840          or a SUBREG of one since we'd be making the expression more
4841          complex if it was just a register.  */
4842
4843       if (!REG_P (temp)
4844           && ! (GET_CODE (temp) == SUBREG
4845                 && REG_P (SUBREG_REG (temp)))
4846           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4847         {
4848           rtx temp1 = simplify_shift_const
4849             (NULL_RTX, ASHIFTRT, mode,
4850              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4851                                    GET_MODE_BITSIZE (mode) - 1 - i),
4852              GET_MODE_BITSIZE (mode) - 1 - i);
4853
4854           /* If all we did was surround TEMP with the two shifts, we
4855              haven't improved anything, so don't use it.  Otherwise,
4856              we are better off with TEMP1.  */
4857           if (GET_CODE (temp1) != ASHIFTRT
4858               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4859               || XEXP (XEXP (temp1, 0), 0) != temp)
4860             return temp1;
4861         }
4862       break;
4863
4864     case TRUNCATE:
4865       /* We can't handle truncation to a partial integer mode here
4866          because we don't know the real bitsize of the partial
4867          integer mode.  */
4868       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4869         break;
4870
4871       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4872           && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4873                                     GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4874         SUBST (XEXP (x, 0),
4875                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4876                               GET_MODE_MASK (mode), 0));
4877
4878       /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4879          whose value is a comparison can be replaced with a subreg if
4880          STORE_FLAG_VALUE permits.  */
4881       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4882           && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4883           && (temp = get_last_value (XEXP (x, 0)))
4884           && COMPARISON_P (temp))
4885         return gen_lowpart (mode, XEXP (x, 0));
4886       break;
4887
4888 #ifdef HAVE_cc0
4889     case COMPARE:
4890       /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4891          using cc0, in which case we want to leave it as a COMPARE
4892          so we can distinguish it from a register-register-copy.  */
4893       if (XEXP (x, 1) == const0_rtx)
4894         return XEXP (x, 0);
4895
4896       /* x - 0 is the same as x unless x's mode has signed zeros and
4897          allows rounding towards -infinity.  Under those conditions,
4898          0 - 0 is -0.  */
4899       if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4900             && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4901           && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4902         return XEXP (x, 0);
4903       break;
4904 #endif
4905
4906     case CONST:
4907       /* (const (const X)) can become (const X).  Do it this way rather than
4908          returning the inner CONST since CONST can be shared with a
4909          REG_EQUAL note.  */
4910       if (GET_CODE (XEXP (x, 0)) == CONST)
4911         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4912       break;
4913
4914 #ifdef HAVE_lo_sum
4915     case LO_SUM:
4916       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
4917          can add in an offset.  find_split_point will split this address up
4918          again if it doesn't match.  */
4919       if (GET_CODE (XEXP (x, 0)) == HIGH
4920           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4921         return XEXP (x, 1);
4922       break;
4923 #endif
4924
4925     case PLUS:
4926       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4927          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4928          bit-field and can be replaced by either a sign_extend or a
4929          sign_extract.  The `and' may be a zero_extend and the two
4930          <c>, -<c> constants may be reversed.  */
4931       if (GET_CODE (XEXP (x, 0)) == XOR
4932           && GET_CODE (XEXP (x, 1)) == CONST_INT
4933           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4934           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4935           && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4936               || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4937           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4938           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4939                && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4940                && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4941                    == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4942               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4943                   && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4944                       == (unsigned int) i + 1))))
4945         return simplify_shift_const
4946           (NULL_RTX, ASHIFTRT, mode,
4947            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4948                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
4949                                  GET_MODE_BITSIZE (mode) - (i + 1)),
4950            GET_MODE_BITSIZE (mode) - (i + 1));
4951
4952       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4953          can become (ashiftrt (ashift (xor x 1) C) C) where C is
4954          the bitsize of the mode - 1.  This allows simplification of
4955          "a = (b & 8) == 0;"  */
4956       if (XEXP (x, 1) == constm1_rtx
4957           && !REG_P (XEXP (x, 0))
4958           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4959                 && REG_P (SUBREG_REG (XEXP (x, 0))))
4960           && nonzero_bits (XEXP (x, 0), mode) == 1)
4961         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4962            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4963                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4964                                  GET_MODE_BITSIZE (mode) - 1),
4965            GET_MODE_BITSIZE (mode) - 1);
4966
4967       /* If we are adding two things that have no bits in common, convert
4968          the addition into an IOR.  This will often be further simplified,
4969          for example in cases like ((a & 1) + (a & 2)), which can
4970          become a & 3.  */
4971
4972       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4973           && (nonzero_bits (XEXP (x, 0), mode)
4974               & nonzero_bits (XEXP (x, 1), mode)) == 0)
4975         {
4976           /* Try to simplify the expression further.  */
4977           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4978           temp = combine_simplify_rtx (tor, mode, in_dest);
4979
4980           /* If we could, great.  If not, do not go ahead with the IOR
4981              replacement, since PLUS appears in many special purpose
4982              address arithmetic instructions.  */
4983           if (GET_CODE (temp) != CLOBBER && temp != tor)
4984             return temp;
4985         }
4986       break;
4987
4988     case MINUS:
4989       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4990          (and <foo> (const_int pow2-1))  */
4991       if (GET_CODE (XEXP (x, 1)) == AND
4992           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4993           && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4994           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4995         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4996                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4997       break;
4998
4999     case MULT:
5000       /* If we have (mult (plus A B) C), apply the distributive law and then
5001          the inverse distributive law to see if things simplify.  This
5002          occurs mostly in addresses, often when unrolling loops.  */
5003
5004       if (GET_CODE (XEXP (x, 0)) == PLUS)
5005         {
5006           rtx result = distribute_and_simplify_rtx (x, 0);
5007           if (result)
5008             return result;
5009         }
5010
5011       /* Try simplify a*(b/c) as (a*b)/c.  */
5012       if (FLOAT_MODE_P (mode) && flag_associative_math
5013           && GET_CODE (XEXP (x, 0)) == DIV)
5014         {
5015           rtx tem = simplify_binary_operation (MULT, mode,
5016                                                XEXP (XEXP (x, 0), 0),
5017                                                XEXP (x, 1));
5018           if (tem)
5019             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5020         }
5021       break;
5022
5023     case UDIV:
5024       /* If this is a divide by a power of two, treat it as a shift if
5025          its first operand is a shift.  */
5026       if (GET_CODE (XEXP (x, 1)) == CONST_INT
5027           && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
5028           && (GET_CODE (XEXP (x, 0)) == ASHIFT
5029               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5030               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5031               || GET_CODE (XEXP (x, 0)) == ROTATE
5032               || GET_CODE (XEXP (x, 0)) == ROTATERT))
5033         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5034       break;
5035
5036     case EQ:  case NE:
5037     case GT:  case GTU:  case GE:  case GEU:
5038     case LT:  case LTU:  case LE:  case LEU:
5039     case UNEQ:  case LTGT:
5040     case UNGT:  case UNGE:
5041     case UNLT:  case UNLE:
5042     case UNORDERED: case ORDERED:
5043       /* If the first operand is a condition code, we can't do anything
5044          with it.  */
5045       if (GET_CODE (XEXP (x, 0)) == COMPARE
5046           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5047               && ! CC0_P (XEXP (x, 0))))
5048         {
5049           rtx op0 = XEXP (x, 0);
5050           rtx op1 = XEXP (x, 1);
5051           enum rtx_code new_code;
5052
5053           if (GET_CODE (op0) == COMPARE)
5054             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5055
5056           /* Simplify our comparison, if possible.  */
5057           new_code = simplify_comparison (code, &op0, &op1);
5058
5059           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5060              if only the low-order bit is possibly nonzero in X (such as when
5061              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
5062              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
5063              known to be either 0 or -1, NE becomes a NEG and EQ becomes
5064              (plus X 1).
5065
5066              Remove any ZERO_EXTRACT we made when thinking this was a
5067              comparison.  It may now be simpler to use, e.g., an AND.  If a
5068              ZERO_EXTRACT is indeed appropriate, it will be placed back by
5069              the call to make_compound_operation in the SET case.  */
5070
5071           if (STORE_FLAG_VALUE == 1
5072               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5073               && op1 == const0_rtx
5074               && mode == GET_MODE (op0)
5075               && nonzero_bits (op0, mode) == 1)
5076             return gen_lowpart (mode,
5077                                 expand_compound_operation (op0));
5078
5079           else if (STORE_FLAG_VALUE == 1
5080                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5081                    && op1 == const0_rtx
5082                    && mode == GET_MODE (op0)
5083                    && (num_sign_bit_copies (op0, mode)
5084                        == GET_MODE_BITSIZE (mode)))
5085             {
5086               op0 = expand_compound_operation (op0);
5087               return simplify_gen_unary (NEG, mode,
5088                                          gen_lowpart (mode, op0),
5089                                          mode);
5090             }
5091
5092           else if (STORE_FLAG_VALUE == 1
5093                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5094                    && op1 == const0_rtx
5095                    && mode == GET_MODE (op0)
5096                    && nonzero_bits (op0, mode) == 1)
5097             {
5098               op0 = expand_compound_operation (op0);
5099               return simplify_gen_binary (XOR, mode,
5100                                           gen_lowpart (mode, op0),
5101                                           const1_rtx);
5102             }
5103
5104           else if (STORE_FLAG_VALUE == 1
5105                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5106                    && op1 == const0_rtx
5107                    && mode == GET_MODE (op0)
5108                    && (num_sign_bit_copies (op0, mode)
5109                        == GET_MODE_BITSIZE (mode)))
5110             {
5111               op0 = expand_compound_operation (op0);
5112               return plus_constant (gen_lowpart (mode, op0), 1);
5113             }
5114
5115           /* If STORE_FLAG_VALUE is -1, we have cases similar to
5116              those above.  */
5117           if (STORE_FLAG_VALUE == -1
5118               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5119               && op1 == const0_rtx
5120               && (num_sign_bit_copies (op0, mode)
5121                   == GET_MODE_BITSIZE (mode)))
5122             return gen_lowpart (mode,
5123                                 expand_compound_operation (op0));
5124
5125           else if (STORE_FLAG_VALUE == -1
5126                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5127                    && op1 == const0_rtx
5128                    && mode == GET_MODE (op0)
5129                    && nonzero_bits (op0, mode) == 1)
5130             {
5131               op0 = expand_compound_operation (op0);
5132               return simplify_gen_unary (NEG, mode,
5133                                          gen_lowpart (mode, op0),
5134                                          mode);
5135             }
5136
5137           else if (STORE_FLAG_VALUE == -1
5138                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5139                    && op1 == const0_rtx
5140                    && mode == GET_MODE (op0)
5141                    && (num_sign_bit_copies (op0, mode)
5142                        == GET_MODE_BITSIZE (mode)))
5143             {
5144               op0 = expand_compound_operation (op0);
5145               return simplify_gen_unary (NOT, mode,
5146                                          gen_lowpart (mode, op0),
5147                                          mode);
5148             }
5149
5150           /* If X is 0/1, (eq X 0) is X-1.  */
5151           else if (STORE_FLAG_VALUE == -1
5152                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5153                    && op1 == const0_rtx
5154                    && mode == GET_MODE (op0)
5155                    && nonzero_bits (op0, mode) == 1)
5156             {
5157               op0 = expand_compound_operation (op0);
5158               return plus_constant (gen_lowpart (mode, op0), -1);
5159             }
5160
5161           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5162              one bit that might be nonzero, we can convert (ne x 0) to
5163              (ashift x c) where C puts the bit in the sign bit.  Remove any
5164              AND with STORE_FLAG_VALUE when we are done, since we are only
5165              going to test the sign bit.  */
5166           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5167               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5168               && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5169                   == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5170               && op1 == const0_rtx
5171               && mode == GET_MODE (op0)
5172               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5173             {
5174               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5175                                         expand_compound_operation (op0),
5176                                         GET_MODE_BITSIZE (mode) - 1 - i);
5177               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5178                 return XEXP (x, 0);
5179               else
5180                 return x;
5181             }
5182
5183           /* If the code changed, return a whole new comparison.  */
5184           if (new_code != code)
5185             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5186
5187           /* Otherwise, keep this operation, but maybe change its operands.
5188              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
5189           SUBST (XEXP (x, 0), op0);
5190           SUBST (XEXP (x, 1), op1);
5191         }
5192       break;
5193
5194     case IF_THEN_ELSE:
5195       return simplify_if_then_else (x);
5196
5197     case ZERO_EXTRACT:
5198     case SIGN_EXTRACT:
5199     case ZERO_EXTEND:
5200     case SIGN_EXTEND:
5201       /* If we are processing SET_DEST, we are done.  */
5202       if (in_dest)
5203         return x;
5204
5205       return expand_compound_operation (x);
5206
5207     case SET:
5208       return simplify_set (x);
5209
5210     case AND:
5211     case IOR:
5212       return simplify_logical (x);
5213
5214     case ASHIFT:
5215     case LSHIFTRT:
5216     case ASHIFTRT:
5217     case ROTATE:
5218     case ROTATERT:
5219       /* If this is a shift by a constant amount, simplify it.  */
5220       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5221         return simplify_shift_const (x, code, mode, XEXP (x, 0),
5222                                      INTVAL (XEXP (x, 1)));
5223
5224       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5225         SUBST (XEXP (x, 1),
5226                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5227                               ((HOST_WIDE_INT) 1
5228                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5229                               - 1,
5230                               0));
5231       break;
5232
5233     default:
5234       break;
5235     }
5236
5237   return x;
5238 }
5239 \f
5240 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
5241
5242 static rtx
5243 simplify_if_then_else (rtx x)
5244 {
5245   enum machine_mode mode = GET_MODE (x);
5246   rtx cond = XEXP (x, 0);
5247   rtx true_rtx = XEXP (x, 1);
5248   rtx false_rtx = XEXP (x, 2);
5249   enum rtx_code true_code = GET_CODE (cond);
5250   int comparison_p = COMPARISON_P (cond);
5251   rtx temp;
5252   int i;
5253   enum rtx_code false_code;
5254   rtx reversed;
5255
5256   /* Simplify storing of the truth value.  */
5257   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5258     return simplify_gen_relational (true_code, mode, VOIDmode,
5259                                     XEXP (cond, 0), XEXP (cond, 1));
5260
5261   /* Also when the truth value has to be reversed.  */
5262   if (comparison_p
5263       && true_rtx == const0_rtx && false_rtx == const_true_rtx
5264       && (reversed = reversed_comparison (cond, mode)))
5265     return reversed;
5266
5267   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5268      in it is being compared against certain values.  Get the true and false
5269      comparisons and see if that says anything about the value of each arm.  */
5270
5271   if (comparison_p
5272       && ((false_code = reversed_comparison_code (cond, NULL))
5273           != UNKNOWN)
5274       && REG_P (XEXP (cond, 0)))
5275     {
5276       HOST_WIDE_INT nzb;
5277       rtx from = XEXP (cond, 0);
5278       rtx true_val = XEXP (cond, 1);
5279       rtx false_val = true_val;
5280       int swapped = 0;
5281
5282       /* If FALSE_CODE is EQ, swap the codes and arms.  */
5283
5284       if (false_code == EQ)
5285         {
5286           swapped = 1, true_code = EQ, false_code = NE;
5287           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5288         }
5289
5290       /* If we are comparing against zero and the expression being tested has
5291          only a single bit that might be nonzero, that is its value when it is
5292          not equal to zero.  Similarly if it is known to be -1 or 0.  */
5293
5294       if (true_code == EQ && true_val == const0_rtx
5295           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5296         {
5297           false_code = EQ;
5298           false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5299         }
5300       else if (true_code == EQ && true_val == const0_rtx
5301                && (num_sign_bit_copies (from, GET_MODE (from))
5302                    == GET_MODE_BITSIZE (GET_MODE (from))))
5303         {
5304           false_code = EQ;
5305           false_val = constm1_rtx;
5306         }
5307
5308       /* Now simplify an arm if we know the value of the register in the
5309          branch and it is used in the arm.  Be careful due to the potential
5310          of locally-shared RTL.  */
5311
5312       if (reg_mentioned_p (from, true_rtx))
5313         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5314                                       from, true_val),
5315                       pc_rtx, pc_rtx, 0, 0);
5316       if (reg_mentioned_p (from, false_rtx))
5317         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5318                                    from, false_val),
5319                        pc_rtx, pc_rtx, 0, 0);
5320
5321       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5322       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5323
5324       true_rtx = XEXP (x, 1);
5325       false_rtx = XEXP (x, 2);
5326       true_code = GET_CODE (cond);
5327     }
5328
5329   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5330      reversed, do so to avoid needing two sets of patterns for
5331      subtract-and-branch insns.  Similarly if we have a constant in the true
5332      arm, the false arm is the same as the first operand of the comparison, or
5333      the false arm is more complicated than the true arm.  */
5334
5335   if (comparison_p
5336       && reversed_comparison_code (cond, NULL) != UNKNOWN
5337       && (true_rtx == pc_rtx
5338           || (CONSTANT_P (true_rtx)
5339               && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
5340           || true_rtx == const0_rtx
5341           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5342           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5343               && !OBJECT_P (false_rtx))
5344           || reg_mentioned_p (true_rtx, false_rtx)
5345           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5346     {
5347       true_code = reversed_comparison_code (cond, NULL);
5348       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5349       SUBST (XEXP (x, 1), false_rtx);
5350       SUBST (XEXP (x, 2), true_rtx);
5351
5352       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5353       cond = XEXP (x, 0);
5354
5355       /* It is possible that the conditional has been simplified out.  */
5356       true_code = GET_CODE (cond);
5357       comparison_p = COMPARISON_P (cond);
5358     }
5359
5360   /* If the two arms are identical, we don't need the comparison.  */
5361
5362   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5363     return true_rtx;
5364
5365   /* Convert a == b ? b : a to "a".  */
5366   if (true_code == EQ && ! side_effects_p (cond)
5367       && !HONOR_NANS (mode)
5368       && rtx_equal_p (XEXP (cond, 0), false_rtx)
5369       && rtx_equal_p (XEXP (cond, 1), true_rtx))
5370     return false_rtx;
5371   else if (true_code == NE && ! side_effects_p (cond)
5372            && !HONOR_NANS (mode)
5373            && rtx_equal_p (XEXP (cond, 0), true_rtx)
5374            && rtx_equal_p (XEXP (cond, 1), false_rtx))
5375     return true_rtx;
5376
5377   /* Look for cases where we have (abs x) or (neg (abs X)).  */
5378
5379   if (GET_MODE_CLASS (mode) == MODE_INT
5380       && GET_CODE (false_rtx) == NEG
5381       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5382       && comparison_p
5383       && rtx_equal_p (true_rtx, XEXP (cond, 0))
5384       && ! side_effects_p (true_rtx))
5385     switch (true_code)
5386       {
5387       case GT:
5388       case GE:
5389         return simplify_gen_unary (ABS, mode, true_rtx, mode);
5390       case LT:
5391       case LE:
5392         return
5393           simplify_gen_unary (NEG, mode,
5394                               simplify_gen_unary (ABS, mode, true_rtx, mode),
5395                               mode);
5396       default:
5397         break;
5398       }
5399
5400   /* Look for MIN or MAX.  */
5401
5402   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5403       && comparison_p
5404       && rtx_equal_p (XEXP (cond, 0), true_rtx)
5405       && rtx_equal_p (XEXP (cond, 1), false_rtx)
5406       && ! side_effects_p (cond))
5407     switch (true_code)
5408       {
5409       case GE:
5410       case GT:
5411         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5412       case LE:
5413       case LT:
5414         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5415       case GEU:
5416       case GTU:
5417         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5418       case LEU:
5419       case LTU:
5420         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5421       default:
5422         break;
5423       }
5424
5425   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5426      second operand is zero, this can be done as (OP Z (mult COND C2)) where
5427      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5428      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5429      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5430      neither 1 or -1, but it isn't worth checking for.  */
5431
5432   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5433       && comparison_p
5434       && GET_MODE_CLASS (mode) == MODE_INT
5435       && ! side_effects_p (x))
5436     {
5437       rtx t = make_compound_operation (true_rtx, SET);
5438       rtx f = make_compound_operation (false_rtx, SET);
5439       rtx cond_op0 = XEXP (cond, 0);
5440       rtx cond_op1 = XEXP (cond, 1);
5441       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5442       enum machine_mode m = mode;
5443       rtx z = 0, c1 = NULL_RTX;
5444
5445       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5446            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5447            || GET_CODE (t) == ASHIFT
5448            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5449           && rtx_equal_p (XEXP (t, 0), f))
5450         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5451
5452       /* If an identity-zero op is commutative, check whether there
5453          would be a match if we swapped the operands.  */
5454       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5455                 || GET_CODE (t) == XOR)
5456                && rtx_equal_p (XEXP (t, 1), f))
5457         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5458       else if (GET_CODE (t) == SIGN_EXTEND
5459                && (GET_CODE (XEXP (t, 0)) == PLUS
5460                    || GET_CODE (XEXP (t, 0)) == MINUS
5461                    || GET_CODE (XEXP (t, 0)) == IOR
5462                    || GET_CODE (XEXP (t, 0)) == XOR
5463                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5464                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5465                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5466                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5467                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5468                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5469                && (num_sign_bit_copies (f, GET_MODE (f))
5470                    > (unsigned int)
5471                      (GET_MODE_BITSIZE (mode)
5472                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5473         {
5474           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5475           extend_op = SIGN_EXTEND;
5476           m = GET_MODE (XEXP (t, 0));
5477         }
5478       else if (GET_CODE (t) == SIGN_EXTEND
5479                && (GET_CODE (XEXP (t, 0)) == PLUS
5480                    || GET_CODE (XEXP (t, 0)) == IOR
5481                    || GET_CODE (XEXP (t, 0)) == XOR)
5482                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5483                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5484                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5485                && (num_sign_bit_copies (f, GET_MODE (f))
5486                    > (unsigned int)
5487                      (GET_MODE_BITSIZE (mode)
5488                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5489         {
5490           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5491           extend_op = SIGN_EXTEND;
5492           m = GET_MODE (XEXP (t, 0));
5493         }
5494       else if (GET_CODE (t) == ZERO_EXTEND
5495                && (GET_CODE (XEXP (t, 0)) == PLUS
5496                    || GET_CODE (XEXP (t, 0)) == MINUS
5497                    || GET_CODE (XEXP (t, 0)) == IOR
5498                    || GET_CODE (XEXP (t, 0)) == XOR
5499                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5500                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5501                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5502                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5503                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5504                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5505                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5506                && ((nonzero_bits (f, GET_MODE (f))
5507                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5508                    == 0))
5509         {
5510           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5511           extend_op = ZERO_EXTEND;
5512           m = GET_MODE (XEXP (t, 0));
5513         }
5514       else if (GET_CODE (t) == ZERO_EXTEND
5515                && (GET_CODE (XEXP (t, 0)) == PLUS
5516                    || GET_CODE (XEXP (t, 0)) == IOR
5517                    || GET_CODE (XEXP (t, 0)) == XOR)
5518                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5519                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5520                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5521                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5522                && ((nonzero_bits (f, GET_MODE (f))
5523                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5524                    == 0))
5525         {
5526           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5527           extend_op = ZERO_EXTEND;
5528           m = GET_MODE (XEXP (t, 0));
5529         }
5530
5531       if (z)
5532         {
5533           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5534                                                  cond_op0, cond_op1),
5535                         pc_rtx, pc_rtx, 0, 0);
5536           temp = simplify_gen_binary (MULT, m, temp,
5537                                       simplify_gen_binary (MULT, m, c1,
5538                                                            const_true_rtx));
5539           temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5540           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5541
5542           if (extend_op != UNKNOWN)
5543             temp = simplify_gen_unary (extend_op, mode, temp, m);
5544
5545           return temp;
5546         }
5547     }
5548
5549   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5550      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5551      negation of a single bit, we can convert this operation to a shift.  We
5552      can actually do this more generally, but it doesn't seem worth it.  */
5553
5554   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5555       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5556       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5557            && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5558           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5559                == GET_MODE_BITSIZE (mode))
5560               && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5561     return
5562       simplify_shift_const (NULL_RTX, ASHIFT, mode,
5563                             gen_lowpart (mode, XEXP (cond, 0)), i);
5564
5565   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
5566   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5567       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5568       && GET_MODE (XEXP (cond, 0)) == mode
5569       && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5570           == nonzero_bits (XEXP (cond, 0), mode)
5571       && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5572     return XEXP (cond, 0);
5573
5574   return x;
5575 }
5576 \f
5577 /* Simplify X, a SET expression.  Return the new expression.  */
5578
5579 static rtx
5580 simplify_set (rtx x)
5581 {
5582   rtx src = SET_SRC (x);
5583   rtx dest = SET_DEST (x);
5584   enum machine_mode mode
5585     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5586   rtx other_insn;
5587   rtx *cc_use;
5588
5589   /* (set (pc) (return)) gets written as (return).  */
5590   if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5591     return src;
5592
5593   /* Now that we know for sure which bits of SRC we are using, see if we can
5594      simplify the expression for the object knowing that we only need the
5595      low-order bits.  */
5596
5597   if (GET_MODE_CLASS (mode) == MODE_INT
5598       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5599     {
5600       src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5601       SUBST (SET_SRC (x), src);
5602     }
5603
5604   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5605      the comparison result and try to simplify it unless we already have used
5606      undobuf.other_insn.  */
5607   if ((GET_MODE_CLASS (mode) == MODE_CC
5608        || GET_CODE (src) == COMPARE
5609        || CC0_P (dest))
5610       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5611       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5612       && COMPARISON_P (*cc_use)
5613       && rtx_equal_p (XEXP (*cc_use, 0), dest))
5614     {
5615       enum rtx_code old_code = GET_CODE (*cc_use);
5616       enum rtx_code new_code;
5617       rtx op0, op1, tmp;
5618       int other_changed = 0;
5619       enum machine_mode compare_mode = GET_MODE (dest);
5620
5621       if (GET_CODE (src) == COMPARE)
5622         op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5623       else
5624         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5625
5626       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5627                                            op0, op1);
5628       if (!tmp)
5629         new_code = old_code;
5630       else if (!CONSTANT_P (tmp))
5631         {
5632           new_code = GET_CODE (tmp);
5633           op0 = XEXP (tmp, 0);
5634           op1 = XEXP (tmp, 1);
5635         }
5636       else
5637         {
5638           rtx pat = PATTERN (other_insn);
5639           undobuf.other_insn = other_insn;
5640           SUBST (*cc_use, tmp);
5641
5642           /* Attempt to simplify CC user.  */
5643           if (GET_CODE (pat) == SET)
5644             {
5645               rtx new = simplify_rtx (SET_SRC (pat));
5646               if (new != NULL_RTX)
5647                 SUBST (SET_SRC (pat), new);
5648             }
5649
5650           /* Convert X into a no-op move.  */
5651           SUBST (SET_DEST (x), pc_rtx);
5652           SUBST (SET_SRC (x), pc_rtx);
5653           return x;
5654         }
5655
5656       /* Simplify our comparison, if possible.  */
5657       new_code = simplify_comparison (new_code, &op0, &op1);
5658
5659 #ifdef SELECT_CC_MODE
5660       /* If this machine has CC modes other than CCmode, check to see if we
5661          need to use a different CC mode here.  */
5662       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5663         compare_mode = GET_MODE (op0);
5664       else
5665         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5666
5667 #ifndef HAVE_cc0
5668       /* If the mode changed, we have to change SET_DEST, the mode in the
5669          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
5670          a hard register, just build new versions with the proper mode.  If it
5671          is a pseudo, we lose unless it is only time we set the pseudo, in
5672          which case we can safely change its mode.  */
5673       if (compare_mode != GET_MODE (dest))
5674         {
5675           if (can_change_dest_mode (dest, 0, compare_mode))
5676             {
5677               unsigned int regno = REGNO (dest);
5678               rtx new_dest;
5679
5680               if (regno < FIRST_PSEUDO_REGISTER)
5681                 new_dest = gen_rtx_REG (compare_mode, regno);
5682               else
5683                 {
5684                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5685                   new_dest = regno_reg_rtx[regno];
5686                 }
5687
5688               SUBST (SET_DEST (x), new_dest);
5689               SUBST (XEXP (*cc_use, 0), new_dest);
5690               other_changed = 1;
5691
5692               dest = new_dest;
5693             }
5694         }
5695 #endif  /* cc0 */
5696 #endif  /* SELECT_CC_MODE */
5697
5698       /* If the code changed, we have to build a new comparison in
5699          undobuf.other_insn.  */
5700       if (new_code != old_code)
5701         {
5702           int other_changed_previously = other_changed;
5703           unsigned HOST_WIDE_INT mask;
5704
5705           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5706                                           dest, const0_rtx));
5707           other_changed = 1;
5708
5709           /* If the only change we made was to change an EQ into an NE or
5710              vice versa, OP0 has only one bit that might be nonzero, and OP1
5711              is zero, check if changing the user of the condition code will
5712              produce a valid insn.  If it won't, we can keep the original code
5713              in that insn by surrounding our operation with an XOR.  */
5714
5715           if (((old_code == NE && new_code == EQ)
5716                || (old_code == EQ && new_code == NE))
5717               && ! other_changed_previously && op1 == const0_rtx
5718               && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5719               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5720             {
5721               rtx pat = PATTERN (other_insn), note = 0;
5722
5723               if ((recog_for_combine (&pat, other_insn, &note) < 0
5724                    && ! check_asm_operands (pat)))
5725                 {
5726                   PUT_CODE (*cc_use, old_code);
5727                   other_changed = 0;
5728
5729                   op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5730                                              op0, GEN_INT (mask));
5731                 }
5732             }
5733         }
5734
5735       if (other_changed)
5736         undobuf.other_insn = other_insn;
5737
5738 #ifdef HAVE_cc0
5739       /* If we are now comparing against zero, change our source if
5740          needed.  If we do not use cc0, we always have a COMPARE.  */
5741       if (op1 == const0_rtx && dest == cc0_rtx)
5742         {
5743           SUBST (SET_SRC (x), op0);
5744           src = op0;
5745         }
5746       else
5747 #endif
5748
5749       /* Otherwise, if we didn't previously have a COMPARE in the
5750          correct mode, we need one.  */
5751       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5752         {
5753           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5754           src = SET_SRC (x);
5755         }
5756       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5757         {
5758           SUBST (SET_SRC (x), op0);
5759           src = SET_SRC (x);
5760         }
5761       /* Otherwise, update the COMPARE if needed.  */
5762       else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
5763         {
5764           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5765           src = SET_SRC (x);
5766         }
5767     }
5768   else
5769     {
5770       /* Get SET_SRC in a form where we have placed back any
5771          compound expressions.  Then do the checks below.  */
5772       src = make_compound_operation (src, SET);
5773       SUBST (SET_SRC (x), src);
5774     }
5775
5776   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5777      and X being a REG or (subreg (reg)), we may be able to convert this to
5778      (set (subreg:m2 x) (op)).
5779
5780      We can always do this if M1 is narrower than M2 because that means that
5781      we only care about the low bits of the result.
5782
5783      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5784      perform a narrower operation than requested since the high-order bits will
5785      be undefined.  On machine where it is defined, this transformation is safe
5786      as long as M1 and M2 have the same number of words.  */
5787
5788   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5789       && !OBJECT_P (SUBREG_REG (src))
5790       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5791            / UNITS_PER_WORD)
5792           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5793                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5794 #ifndef WORD_REGISTER_OPERATIONS
5795       && (GET_MODE_SIZE (GET_MODE (src))
5796         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5797 #endif
5798 #ifdef CANNOT_CHANGE_MODE_CLASS
5799       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5800             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5801                                          GET_MODE (SUBREG_REG (src)),
5802                                          GET_MODE (src)))
5803 #endif
5804       && (REG_P (dest)
5805           || (GET_CODE (dest) == SUBREG
5806               && REG_P (SUBREG_REG (dest)))))
5807     {
5808       SUBST (SET_DEST (x),
5809              gen_lowpart (GET_MODE (SUBREG_REG (src)),
5810                                       dest));
5811       SUBST (SET_SRC (x), SUBREG_REG (src));
5812
5813       src = SET_SRC (x), dest = SET_DEST (x);
5814     }
5815
5816 #ifdef HAVE_cc0
5817   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5818      in SRC.  */
5819   if (dest == cc0_rtx
5820       && GET_CODE (src) == SUBREG
5821       && subreg_lowpart_p (src)
5822       && (GET_MODE_BITSIZE (GET_MODE (src))
5823           < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5824     {
5825       rtx inner = SUBREG_REG (src);
5826       enum machine_mode inner_mode = GET_MODE (inner);
5827
5828       /* Here we make sure that we don't have a sign bit on.  */
5829       if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5830           && (nonzero_bits (inner, inner_mode)
5831               < ((unsigned HOST_WIDE_INT) 1
5832                  << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5833         {
5834           SUBST (SET_SRC (x), inner);
5835           src = SET_SRC (x);
5836         }
5837     }
5838 #endif
5839
5840 #ifdef LOAD_EXTEND_OP
5841   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5842      would require a paradoxical subreg.  Replace the subreg with a
5843      zero_extend to avoid the reload that would otherwise be required.  */
5844
5845   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5846       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5847       && SUBREG_BYTE (src) == 0
5848       && (GET_MODE_SIZE (GET_MODE (src))
5849           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5850       && MEM_P (SUBREG_REG (src)))
5851     {
5852       SUBST (SET_SRC (x),
5853              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5854                             GET_MODE (src), SUBREG_REG (src)));
5855
5856       src = SET_SRC (x);
5857     }
5858 #endif
5859
5860   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5861      are comparing an item known to be 0 or -1 against 0, use a logical
5862      operation instead. Check for one of the arms being an IOR of the other
5863      arm with some value.  We compute three terms to be IOR'ed together.  In
5864      practice, at most two will be nonzero.  Then we do the IOR's.  */
5865
5866   if (GET_CODE (dest) != PC
5867       && GET_CODE (src) == IF_THEN_ELSE
5868       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5869       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5870       && XEXP (XEXP (src, 0), 1) == const0_rtx
5871       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5872 #ifdef HAVE_conditional_move
5873       && ! can_conditionally_move_p (GET_MODE (src))
5874 #endif
5875       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5876                                GET_MODE (XEXP (XEXP (src, 0), 0)))
5877           == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5878       && ! side_effects_p (src))
5879     {
5880       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5881                       ? XEXP (src, 1) : XEXP (src, 2));
5882       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5883                    ? XEXP (src, 2) : XEXP (src, 1));
5884       rtx term1 = const0_rtx, term2, term3;
5885
5886       if (GET_CODE (true_rtx) == IOR
5887           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5888         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5889       else if (GET_CODE (true_rtx) == IOR
5890                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5891         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5892       else if (GET_CODE (false_rtx) == IOR
5893                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5894         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5895       else if (GET_CODE (false_rtx) == IOR
5896                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5897         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5898
5899       term2 = simplify_gen_binary (AND, GET_MODE (src),
5900                                    XEXP (XEXP (src, 0), 0), true_rtx);
5901       term3 = simplify_gen_binary (AND, GET_MODE (src),
5902                                    simplify_gen_unary (NOT, GET_MODE (src),
5903                                                        XEXP (XEXP (src, 0), 0),
5904                                                        GET_MODE (src)),
5905                                    false_rtx);
5906
5907       SUBST (SET_SRC (x),
5908              simplify_gen_binary (IOR, GET_MODE (src),
5909                                   simplify_gen_binary (IOR, GET_MODE (src),
5910                                                        term1, term2),
5911                                   term3));
5912
5913       src = SET_SRC (x);
5914     }
5915
5916   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5917      whole thing fail.  */
5918   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5919     return src;
5920   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5921     return dest;
5922   else
5923     /* Convert this into a field assignment operation, if possible.  */
5924     return make_field_assignment (x);
5925 }
5926 \f
5927 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5928    result.  */
5929
5930 static rtx
5931 simplify_logical (rtx x)
5932 {
5933   enum machine_mode mode = GET_MODE (x);
5934   rtx op0 = XEXP (x, 0);
5935   rtx op1 = XEXP (x, 1);
5936
5937   switch (GET_CODE (x))
5938     {
5939     case AND:
5940       /* We can call simplify_and_const_int only if we don't lose
5941          any (sign) bits when converting INTVAL (op1) to
5942          "unsigned HOST_WIDE_INT".  */
5943       if (GET_CODE (op1) == CONST_INT
5944           && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5945               || INTVAL (op1) > 0))
5946         {
5947           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5948           if (GET_CODE (x) != AND)
5949             return x;
5950
5951           op0 = XEXP (x, 0);
5952           op1 = XEXP (x, 1);
5953         }
5954
5955       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5956          apply the distributive law and then the inverse distributive
5957          law to see if things simplify.  */
5958       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5959         {
5960           rtx result = distribute_and_simplify_rtx (x, 0);
5961           if (result)
5962             return result;
5963         }
5964       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5965         {
5966           rtx result = distribute_and_simplify_rtx (x, 1);
5967           if (result)
5968             return result;
5969         }
5970       break;
5971
5972     case IOR:
5973       /* If we have (ior (and A B) C), apply the distributive law and then
5974          the inverse distributive law to see if things simplify.  */
5975
5976       if (GET_CODE (op0) == AND)
5977         {
5978           rtx result = distribute_and_simplify_rtx (x, 0);
5979           if (result)
5980             return result;
5981         }
5982
5983       if (GET_CODE (op1) == AND)
5984         {
5985           rtx result = distribute_and_simplify_rtx (x, 1);
5986           if (result)
5987             return result;
5988         }
5989       break;
5990
5991     default:
5992       gcc_unreachable ();
5993     }
5994
5995   return x;
5996 }
5997 \f
5998 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5999    operations" because they can be replaced with two more basic operations.
6000    ZERO_EXTEND is also considered "compound" because it can be replaced with
6001    an AND operation, which is simpler, though only one operation.
6002
6003    The function expand_compound_operation is called with an rtx expression
6004    and will convert it to the appropriate shifts and AND operations,
6005    simplifying at each stage.
6006
6007    The function make_compound_operation is called to convert an expression
6008    consisting of shifts and ANDs into the equivalent compound expression.
6009    It is the inverse of this function, loosely speaking.  */
6010
6011 static rtx
6012 expand_compound_operation (rtx x)
6013 {
6014   unsigned HOST_WIDE_INT pos = 0, len;
6015   int unsignedp = 0;
6016   unsigned int modewidth;
6017   rtx tem;
6018
6019   switch (GET_CODE (x))
6020     {
6021     case ZERO_EXTEND:
6022       unsignedp = 1;
6023     case SIGN_EXTEND:
6024       /* We can't necessarily use a const_int for a multiword mode;
6025          it depends on implicitly extending the value.
6026          Since we don't know the right way to extend it,
6027          we can't tell whether the implicit way is right.
6028
6029          Even for a mode that is no wider than a const_int,
6030          we can't win, because we need to sign extend one of its bits through
6031          the rest of it, and we don't know which bit.  */
6032       if (GET_CODE (XEXP (x, 0)) == CONST_INT)
6033         return x;
6034
6035       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6036          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
6037          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6038          reloaded. If not for that, MEM's would very rarely be safe.
6039
6040          Reject MODEs bigger than a word, because we might not be able
6041          to reference a two-register group starting with an arbitrary register
6042          (and currently gen_lowpart might crash for a SUBREG).  */
6043
6044       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6045         return x;
6046
6047       /* Reject MODEs that aren't scalar integers because turning vector
6048          or complex modes into shifts causes problems.  */
6049
6050       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6051         return x;
6052
6053       len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6054       /* If the inner object has VOIDmode (the only way this can happen
6055          is if it is an ASM_OPERANDS), we can't do anything since we don't
6056          know how much masking to do.  */
6057       if (len == 0)
6058         return x;
6059
6060       break;
6061
6062     case ZERO_EXTRACT:
6063       unsignedp = 1;
6064
6065       /* ... fall through ...  */
6066
6067     case SIGN_EXTRACT:
6068       /* If the operand is a CLOBBER, just return it.  */
6069       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6070         return XEXP (x, 0);
6071
6072       if (GET_CODE (XEXP (x, 1)) != CONST_INT
6073           || GET_CODE (XEXP (x, 2)) != CONST_INT
6074           || GET_MODE (XEXP (x, 0)) == VOIDmode)
6075         return x;
6076
6077       /* Reject MODEs that aren't scalar integers because turning vector
6078          or complex modes into shifts causes problems.  */
6079
6080       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6081         return x;
6082
6083       len = INTVAL (XEXP (x, 1));
6084       pos = INTVAL (XEXP (x, 2));
6085
6086       /* This should stay within the object being extracted, fail otherwise.  */
6087       if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6088         return x;
6089
6090       if (BITS_BIG_ENDIAN)
6091         pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6092
6093       break;
6094
6095     default:
6096       return x;
6097     }
6098   /* Convert sign extension to zero extension, if we know that the high
6099      bit is not set, as this is easier to optimize.  It will be converted
6100      back to cheaper alternative in make_extraction.  */
6101   if (GET_CODE (x) == SIGN_EXTEND
6102       && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6103           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6104                 & ~(((unsigned HOST_WIDE_INT)
6105                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6106                      >> 1))
6107                == 0)))
6108     {
6109       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6110       rtx temp2 = expand_compound_operation (temp);
6111
6112       /* Make sure this is a profitable operation.  */
6113       if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
6114        return temp2;
6115       else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
6116        return temp;
6117       else
6118        return x;
6119     }
6120
6121   /* We can optimize some special cases of ZERO_EXTEND.  */
6122   if (GET_CODE (x) == ZERO_EXTEND)
6123     {
6124       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6125          know that the last value didn't have any inappropriate bits
6126          set.  */
6127       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6128           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6129           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6130           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6131               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6132         return XEXP (XEXP (x, 0), 0);
6133
6134       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6135       if (GET_CODE (XEXP (x, 0)) == SUBREG
6136           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6137           && subreg_lowpart_p (XEXP (x, 0))
6138           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6139           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6140               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6141         return SUBREG_REG (XEXP (x, 0));
6142
6143       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6144          is a comparison and STORE_FLAG_VALUE permits.  This is like
6145          the first case, but it works even when GET_MODE (x) is larger
6146          than HOST_WIDE_INT.  */
6147       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6148           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6149           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6150           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6151               <= HOST_BITS_PER_WIDE_INT)
6152           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6153               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6154         return XEXP (XEXP (x, 0), 0);
6155
6156       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6157       if (GET_CODE (XEXP (x, 0)) == SUBREG
6158           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6159           && subreg_lowpart_p (XEXP (x, 0))
6160           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6161           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6162               <= HOST_BITS_PER_WIDE_INT)
6163           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6164               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6165         return SUBREG_REG (XEXP (x, 0));
6166
6167     }
6168
6169   /* If we reach here, we want to return a pair of shifts.  The inner
6170      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
6171      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
6172      logical depending on the value of UNSIGNEDP.
6173
6174      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6175      converted into an AND of a shift.
6176
6177      We must check for the case where the left shift would have a negative
6178      count.  This can happen in a case like (x >> 31) & 255 on machines
6179      that can't shift by a constant.  On those machines, we would first
6180      combine the shift with the AND to produce a variable-position
6181      extraction.  Then the constant of 31 would be substituted in to produce
6182      a such a position.  */
6183
6184   modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6185   if (modewidth + len >= pos)
6186     {
6187       enum machine_mode mode = GET_MODE (x);
6188       tem = gen_lowpart (mode, XEXP (x, 0));
6189       if (!tem || GET_CODE (tem) == CLOBBER)
6190         return x;
6191       tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6192                                   tem, modewidth - pos - len);
6193       tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6194                                   mode, tem, modewidth - len);
6195     }
6196   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6197     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6198                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
6199                                                         GET_MODE (x),
6200                                                         XEXP (x, 0), pos),
6201                                   ((HOST_WIDE_INT) 1 << len) - 1);
6202   else
6203     /* Any other cases we can't handle.  */
6204     return x;
6205
6206   /* If we couldn't do this for some reason, return the original
6207      expression.  */
6208   if (GET_CODE (tem) == CLOBBER)
6209     return x;
6210
6211   return tem;
6212 }
6213 \f
6214 /* X is a SET which contains an assignment of one object into
6215    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6216    or certain SUBREGS). If possible, convert it into a series of
6217    logical operations.
6218
6219    We half-heartedly support variable positions, but do not at all
6220    support variable lengths.  */
6221
6222 static const_rtx
6223 expand_field_assignment (const_rtx x)
6224 {
6225   rtx inner;
6226   rtx pos;                      /* Always counts from low bit.  */
6227   int len;
6228   rtx mask, cleared, masked;
6229   enum machine_mode compute_mode;
6230
6231   /* Loop until we find something we can't simplify.  */
6232   while (1)
6233     {
6234       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6235           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6236         {
6237           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6238           len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6239           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6240         }
6241       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6242                && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
6243         {
6244           inner = XEXP (SET_DEST (x), 0);
6245           len = INTVAL (XEXP (SET_DEST (x), 1));
6246           pos = XEXP (SET_DEST (x), 2);
6247
6248           /* A constant position should stay within the width of INNER.  */
6249           if (GET_CODE (pos) == CONST_INT
6250               && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6251             break;
6252
6253           if (BITS_BIG_ENDIAN)
6254             {
6255               if (GET_CODE (pos) == CONST_INT)
6256                 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6257                                - INTVAL (pos));
6258               else if (GET_CODE (pos) == MINUS
6259                        && GET_CODE (XEXP (pos, 1)) == CONST_INT
6260                        && (INTVAL (XEXP (pos, 1))
6261                            == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6262                 /* If position is ADJUST - X, new position is X.  */
6263                 pos = XEXP (pos, 0);
6264               else
6265                 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6266                                            GEN_INT (GET_MODE_BITSIZE (
6267                                                     GET_MODE (inner))
6268                                                     - len),
6269                                            pos);
6270             }
6271         }
6272
6273       /* A SUBREG between two modes that occupy the same numbers of words
6274          can be done by moving the SUBREG to the source.  */
6275       else if (GET_CODE (SET_DEST (x)) == SUBREG
6276                /* We need SUBREGs to compute nonzero_bits properly.  */
6277                && nonzero_sign_valid
6278                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6279                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6280                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6281                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6282         {
6283           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6284                            gen_lowpart
6285                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
6286                             SET_SRC (x)));
6287           continue;
6288         }
6289       else
6290         break;
6291
6292       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6293         inner = SUBREG_REG (inner);
6294
6295       compute_mode = GET_MODE (inner);
6296
6297       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
6298       if (! SCALAR_INT_MODE_P (compute_mode))
6299         {
6300           enum machine_mode imode;
6301
6302           /* Don't do anything for vector or complex integral types.  */
6303           if (! FLOAT_MODE_P (compute_mode))
6304             break;
6305
6306           /* Try to find an integral mode to pun with.  */
6307           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6308           if (imode == BLKmode)
6309             break;
6310
6311           compute_mode = imode;
6312           inner = gen_lowpart (imode, inner);
6313         }
6314
6315       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
6316       if (len >= HOST_BITS_PER_WIDE_INT)
6317         break;
6318
6319       /* Now compute the equivalent expression.  Make a copy of INNER
6320          for the SET_DEST in case it is a MEM into which we will substitute;
6321          we don't want shared RTL in that case.  */
6322       mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6323       cleared = simplify_gen_binary (AND, compute_mode,
6324                                      simplify_gen_unary (NOT, compute_mode,
6325                                        simplify_gen_binary (ASHIFT,
6326                                                             compute_mode,
6327                                                             mask, pos),
6328                                        compute_mode),
6329                                      inner);
6330       masked = simplify_gen_binary (ASHIFT, compute_mode,
6331                                     simplify_gen_binary (
6332                                       AND, compute_mode,
6333                                       gen_lowpart (compute_mode, SET_SRC (x)),
6334                                       mask),
6335                                     pos);
6336
6337       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6338                        simplify_gen_binary (IOR, compute_mode,
6339                                             cleared, masked));
6340     }
6341
6342   return x;
6343 }
6344 \f
6345 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
6346    it is an RTX that represents a variable starting position; otherwise,
6347    POS is the (constant) starting bit position (counted from the LSB).
6348
6349    UNSIGNEDP is nonzero for an unsigned reference and zero for a
6350    signed reference.
6351
6352    IN_DEST is nonzero if this is a reference in the destination of a
6353    SET.  This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
6354    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6355    be used.
6356
6357    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
6358    ZERO_EXTRACT should be built even for bits starting at bit 0.
6359
6360    MODE is the desired mode of the result (if IN_DEST == 0).
6361
6362    The result is an RTX for the extraction or NULL_RTX if the target
6363    can't handle it.  */
6364
6365 static rtx
6366 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6367                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6368                  int in_dest, int in_compare)
6369 {
6370   /* This mode describes the size of the storage area
6371      to fetch the overall value from.  Within that, we
6372      ignore the POS lowest bits, etc.  */
6373   enum machine_mode is_mode = GET_MODE (inner);
6374   enum machine_mode inner_mode;
6375   enum machine_mode wanted_inner_mode;
6376   enum machine_mode wanted_inner_reg_mode = word_mode;
6377   enum machine_mode pos_mode = word_mode;
6378   enum machine_mode extraction_mode = word_mode;
6379   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6380   rtx new = 0;
6381   rtx orig_pos_rtx = pos_rtx;
6382   HOST_WIDE_INT orig_pos;
6383
6384   if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6385     {
6386       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6387          consider just the QI as the memory to extract from.
6388          The subreg adds or removes high bits; its mode is
6389          irrelevant to the meaning of this extraction,
6390          since POS and LEN count from the lsb.  */
6391       if (MEM_P (SUBREG_REG (inner)))
6392         is_mode = GET_MODE (SUBREG_REG (inner));
6393       inner = SUBREG_REG (inner);
6394     }
6395   else if (GET_CODE (inner) == ASHIFT
6396            && GET_CODE (XEXP (inner, 1)) == CONST_INT
6397            && pos_rtx == 0 && pos == 0
6398            && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6399     {
6400       /* We're extracting the least significant bits of an rtx
6401          (ashift X (const_int C)), where LEN > C.  Extract the
6402          least significant (LEN - C) bits of X, giving an rtx
6403          whose mode is MODE, then shift it left C times.  */
6404       new = make_extraction (mode, XEXP (inner, 0),
6405                              0, 0, len - INTVAL (XEXP (inner, 1)),
6406                              unsignedp, in_dest, in_compare);
6407       if (new != 0)
6408         return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6409     }
6410
6411   inner_mode = GET_MODE (inner);
6412
6413   if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6414     pos = INTVAL (pos_rtx), pos_rtx = 0;
6415
6416   /* See if this can be done without an extraction.  We never can if the
6417      width of the field is not the same as that of some integer mode. For
6418      registers, we can only avoid the extraction if the position is at the
6419      low-order bit and this is either not in the destination or we have the
6420      appropriate STRICT_LOW_PART operation available.
6421
6422      For MEM, we can avoid an extract if the field starts on an appropriate
6423      boundary and we can change the mode of the memory reference.  */
6424
6425   if (tmode != BLKmode
6426       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6427            && !MEM_P (inner)
6428            && (inner_mode == tmode
6429                || !REG_P (inner)
6430                || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6431                                          GET_MODE_BITSIZE (inner_mode))
6432                || reg_truncated_to_mode (tmode, inner))
6433            && (! in_dest
6434                || (REG_P (inner)
6435                    && have_insn_for (STRICT_LOW_PART, tmode))))
6436           || (MEM_P (inner) && pos_rtx == 0
6437               && (pos
6438                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6439                      : BITS_PER_UNIT)) == 0
6440               /* We can't do this if we are widening INNER_MODE (it
6441                  may not be aligned, for one thing).  */
6442               && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6443               && (inner_mode == tmode
6444                   || (! mode_dependent_address_p (XEXP (inner, 0))
6445                       && ! MEM_VOLATILE_P (inner))))))
6446     {
6447       /* If INNER is a MEM, make a new MEM that encompasses just the desired
6448          field.  If the original and current mode are the same, we need not
6449          adjust the offset.  Otherwise, we do if bytes big endian.
6450
6451          If INNER is not a MEM, get a piece consisting of just the field
6452          of interest (in this case POS % BITS_PER_WORD must be 0).  */
6453
6454       if (MEM_P (inner))
6455         {
6456           HOST_WIDE_INT offset;
6457
6458           /* POS counts from lsb, but make OFFSET count in memory order.  */
6459           if (BYTES_BIG_ENDIAN)
6460             offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6461           else
6462             offset = pos / BITS_PER_UNIT;
6463
6464           new = adjust_address_nv (inner, tmode, offset);
6465         }
6466       else if (REG_P (inner))
6467         {
6468           if (tmode != inner_mode)
6469             {
6470               /* We can't call gen_lowpart in a DEST since we
6471                  always want a SUBREG (see below) and it would sometimes
6472                  return a new hard register.  */
6473               if (pos || in_dest)
6474                 {
6475                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6476
6477                   if (WORDS_BIG_ENDIAN
6478                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6479                     final_word = ((GET_MODE_SIZE (inner_mode)
6480                                    - GET_MODE_SIZE (tmode))
6481                                   / UNITS_PER_WORD) - final_word;
6482
6483                   final_word *= UNITS_PER_WORD;
6484                   if (BYTES_BIG_ENDIAN &&
6485                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6486                     final_word += (GET_MODE_SIZE (inner_mode)
6487                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6488
6489                   /* Avoid creating invalid subregs, for example when
6490                      simplifying (x>>32)&255.  */
6491                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
6492                     return NULL_RTX;
6493
6494                   new = gen_rtx_SUBREG (tmode, inner, final_word);
6495                 }
6496               else
6497                 new = gen_lowpart (tmode, inner);
6498             }
6499           else
6500             new = inner;
6501         }
6502       else
6503         new = force_to_mode (inner, tmode,
6504                              len >= HOST_BITS_PER_WIDE_INT
6505                              ? ~(unsigned HOST_WIDE_INT) 0
6506                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6507                              0);
6508
6509       /* If this extraction is going into the destination of a SET,
6510          make a STRICT_LOW_PART unless we made a MEM.  */
6511
6512       if (in_dest)
6513         return (MEM_P (new) ? new
6514                 : (GET_CODE (new) != SUBREG
6515                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
6516                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6517
6518       if (mode == tmode)
6519         return new;
6520
6521       if (GET_CODE (new) == CONST_INT)
6522         return gen_int_mode (INTVAL (new), mode);
6523
6524       /* If we know that no extraneous bits are set, and that the high
6525          bit is not set, convert the extraction to the cheaper of
6526          sign and zero extension, that are equivalent in these cases.  */
6527       if (flag_expensive_optimizations
6528           && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6529               && ((nonzero_bits (new, tmode)
6530                    & ~(((unsigned HOST_WIDE_INT)
6531                         GET_MODE_MASK (tmode))
6532                        >> 1))
6533                   == 0)))
6534         {
6535           rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6536           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6537
6538           /* Prefer ZERO_EXTENSION, since it gives more information to
6539              backends.  */
6540           if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6541             return temp;
6542           return temp1;
6543         }
6544
6545       /* Otherwise, sign- or zero-extend unless we already are in the
6546          proper mode.  */
6547
6548       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6549                              mode, new));
6550     }
6551
6552   /* Unless this is a COMPARE or we have a funny memory reference,
6553      don't do anything with zero-extending field extracts starting at
6554      the low-order bit since they are simple AND operations.  */
6555   if (pos_rtx == 0 && pos == 0 && ! in_dest
6556       && ! in_compare && unsignedp)
6557     return 0;
6558
6559   /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6560      if the position is not a constant and the length is not 1.  In all
6561      other cases, we would only be going outside our object in cases when
6562      an original shift would have been undefined.  */
6563   if (MEM_P (inner)
6564       && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6565           || (pos_rtx != 0 && len != 1)))
6566     return 0;
6567
6568   /* Get the mode to use should INNER not be a MEM, the mode for the position,
6569      and the mode for the result.  */
6570   if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6571     {
6572       wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6573       pos_mode = mode_for_extraction (EP_insv, 2);
6574       extraction_mode = mode_for_extraction (EP_insv, 3);
6575     }
6576
6577   if (! in_dest && unsignedp
6578       && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6579     {
6580       wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6581       pos_mode = mode_for_extraction (EP_extzv, 3);
6582       extraction_mode = mode_for_extraction (EP_extzv, 0);
6583     }
6584
6585   if (! in_dest && ! unsignedp
6586       && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6587     {
6588       wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6589       pos_mode = mode_for_extraction (EP_extv, 3);
6590       extraction_mode = mode_for_extraction (EP_extv, 0);
6591     }
6592
6593   /* Never narrow an object, since that might not be safe.  */
6594
6595   if (mode != VOIDmode
6596       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6597     extraction_mode = mode;
6598
6599   if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6600       && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6601     pos_mode = GET_MODE (pos_rtx);
6602
6603   /* If this is not from memory, the desired mode is the preferred mode
6604      for an extraction pattern's first input operand, or word_mode if there
6605      is none.  */
6606   if (!MEM_P (inner))
6607     wanted_inner_mode = wanted_inner_reg_mode;
6608   else
6609     {
6610       /* Be careful not to go beyond the extracted object and maintain the
6611          natural alignment of the memory.  */
6612       wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6613       while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6614              > GET_MODE_BITSIZE (wanted_inner_mode))
6615         {
6616           wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6617           gcc_assert (wanted_inner_mode != VOIDmode);
6618         }
6619
6620       /* If we have to change the mode of memory and cannot, the desired mode
6621          is EXTRACTION_MODE.  */
6622       if (inner_mode != wanted_inner_mode
6623           && (mode_dependent_address_p (XEXP (inner, 0))
6624               || MEM_VOLATILE_P (inner)
6625               || pos_rtx))
6626         wanted_inner_mode = extraction_mode;
6627     }
6628
6629   orig_pos = pos;
6630
6631   if (BITS_BIG_ENDIAN)
6632     {
6633       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6634          BITS_BIG_ENDIAN style.  If position is constant, compute new
6635          position.  Otherwise, build subtraction.
6636          Note that POS is relative to the mode of the original argument.
6637          If it's a MEM we need to recompute POS relative to that.
6638          However, if we're extracting from (or inserting into) a register,
6639          we want to recompute POS relative to wanted_inner_mode.  */
6640       int width = (MEM_P (inner)
6641                    ? GET_MODE_BITSIZE (is_mode)
6642                    : GET_MODE_BITSIZE (wanted_inner_mode));
6643
6644       if (pos_rtx == 0)
6645         pos = width - len - pos;
6646       else
6647         pos_rtx
6648           = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6649       /* POS may be less than 0 now, but we check for that below.
6650          Note that it can only be less than 0 if !MEM_P (inner).  */
6651     }
6652
6653   /* If INNER has a wider mode, and this is a constant extraction, try to
6654      make it smaller and adjust the byte to point to the byte containing
6655      the value.  */
6656   if (wanted_inner_mode != VOIDmode
6657       && inner_mode != wanted_inner_mode
6658       && ! pos_rtx
6659       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6660       && MEM_P (inner)
6661       && ! mode_dependent_address_p (XEXP (inner, 0))
6662       && ! MEM_VOLATILE_P (inner))
6663     {
6664       int offset = 0;
6665
6666       /* The computations below will be correct if the machine is big
6667          endian in both bits and bytes or little endian in bits and bytes.
6668          If it is mixed, we must adjust.  */
6669
6670       /* If bytes are big endian and we had a paradoxical SUBREG, we must
6671          adjust OFFSET to compensate.  */
6672       if (BYTES_BIG_ENDIAN
6673           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6674         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6675
6676       /* We can now move to the desired byte.  */
6677       offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6678                 * GET_MODE_SIZE (wanted_inner_mode);
6679       pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6680
6681       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6682           && is_mode != wanted_inner_mode)
6683         offset = (GET_MODE_SIZE (is_mode)
6684                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
6685
6686       inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6687     }
6688
6689   /* If INNER is not memory, we can always get it into the proper mode.  If we
6690      are changing its mode, POS must be a constant and smaller than the size
6691      of the new mode.  */
6692   else if (!MEM_P (inner))
6693     {
6694       if (GET_MODE (inner) != wanted_inner_mode
6695           && (pos_rtx != 0
6696               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6697         return 0;
6698
6699       if (orig_pos < 0)
6700         return 0;
6701
6702       inner = force_to_mode (inner, wanted_inner_mode,
6703                              pos_rtx
6704                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6705                              ? ~(unsigned HOST_WIDE_INT) 0
6706                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6707                                 << orig_pos),
6708                              0);
6709     }
6710
6711   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
6712      have to zero extend.  Otherwise, we can just use a SUBREG.  */
6713   if (pos_rtx != 0
6714       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6715     {
6716       rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6717
6718       /* If we know that no extraneous bits are set, and that the high
6719          bit is not set, convert extraction to cheaper one - either
6720          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6721          cases.  */
6722       if (flag_expensive_optimizations
6723           && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6724               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6725                    & ~(((unsigned HOST_WIDE_INT)
6726                         GET_MODE_MASK (GET_MODE (pos_rtx)))
6727                        >> 1))
6728                   == 0)))
6729         {
6730           rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6731
6732           /* Prefer ZERO_EXTENSION, since it gives more information to
6733              backends.  */
6734           if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6735             temp = temp1;
6736         }
6737       pos_rtx = temp;
6738     }
6739   else if (pos_rtx != 0
6740            && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6741     pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6742
6743   /* Make POS_RTX unless we already have it and it is correct.  If we don't
6744      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6745      be a CONST_INT.  */
6746   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6747     pos_rtx = orig_pos_rtx;
6748
6749   else if (pos_rtx == 0)
6750     pos_rtx = GEN_INT (pos);
6751
6752   /* Make the required operation.  See if we can use existing rtx.  */
6753   new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6754                          extraction_mode, inner, GEN_INT (len), pos_rtx);
6755   if (! in_dest)
6756     new = gen_lowpart (mode, new);
6757
6758   return new;
6759 }
6760 \f
6761 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6762    with any other operations in X.  Return X without that shift if so.  */
6763
6764 static rtx
6765 extract_left_shift (rtx x, int count)
6766 {
6767   enum rtx_code code = GET_CODE (x);
6768   enum machine_mode mode = GET_MODE (x);
6769   rtx tem;
6770
6771   switch (code)
6772     {
6773     case ASHIFT:
6774       /* This is the shift itself.  If it is wide enough, we will return
6775          either the value being shifted if the shift count is equal to
6776          COUNT or a shift for the difference.  */
6777       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6778           && INTVAL (XEXP (x, 1)) >= count)
6779         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6780                                      INTVAL (XEXP (x, 1)) - count);
6781       break;
6782
6783     case NEG:  case NOT:
6784       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6785         return simplify_gen_unary (code, mode, tem, mode);
6786
6787       break;
6788
6789     case PLUS:  case IOR:  case XOR:  case AND:
6790       /* If we can safely shift this constant and we find the inner shift,
6791          make a new operation.  */
6792       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6793           && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6794           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6795         return simplify_gen_binary (code, mode, tem,
6796                                     GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6797
6798       break;
6799
6800     default:
6801       break;
6802     }
6803
6804   return 0;
6805 }
6806 \f
6807 /* Look at the expression rooted at X.  Look for expressions
6808    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6809    Form these expressions.
6810
6811    Return the new rtx, usually just X.
6812
6813    Also, for machines like the VAX that don't have logical shift insns,
6814    try to convert logical to arithmetic shift operations in cases where
6815    they are equivalent.  This undoes the canonicalizations to logical
6816    shifts done elsewhere.
6817
6818    We try, as much as possible, to re-use rtl expressions to save memory.
6819
6820    IN_CODE says what kind of expression we are processing.  Normally, it is
6821    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
6822    being kludges), it is MEM.  When processing the arguments of a comparison
6823    or a COMPARE against zero, it is COMPARE.  */
6824
6825 static rtx
6826 make_compound_operation (rtx x, enum rtx_code in_code)
6827 {
6828   enum rtx_code code = GET_CODE (x);
6829   enum machine_mode mode = GET_MODE (x);
6830   int mode_width = GET_MODE_BITSIZE (mode);
6831   rtx rhs, lhs;
6832   enum rtx_code next_code;
6833   int i;
6834   rtx new = 0;
6835   rtx tem;
6836   const char *fmt;
6837
6838   /* Select the code to be used in recursive calls.  Once we are inside an
6839      address, we stay there.  If we have a comparison, set to COMPARE,
6840      but once inside, go back to our default of SET.  */
6841
6842   next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6843                : ((code == COMPARE || COMPARISON_P (x))
6844                   && XEXP (x, 1) == const0_rtx) ? COMPARE
6845                : in_code == COMPARE ? SET : in_code);
6846
6847   /* Process depending on the code of this operation.  If NEW is set
6848      nonzero, it will be returned.  */
6849
6850   switch (code)
6851     {
6852     case ASHIFT:
6853       /* Convert shifts by constants into multiplications if inside
6854          an address.  */
6855       if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6856           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6857           && INTVAL (XEXP (x, 1)) >= 0)
6858         {
6859           new = make_compound_operation (XEXP (x, 0), next_code);
6860           new = gen_rtx_MULT (mode, new,
6861                               GEN_INT ((HOST_WIDE_INT) 1
6862                                        << INTVAL (XEXP (x, 1))));
6863         }
6864       break;
6865
6866     case AND:
6867       /* If the second operand is not a constant, we can't do anything
6868          with it.  */
6869       if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6870         break;
6871
6872       /* If the constant is a power of two minus one and the first operand
6873          is a logical right shift, make an extraction.  */
6874       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6875           && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6876         {
6877           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6878           new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6879                                  0, in_code == COMPARE);
6880         }
6881
6882       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
6883       else if (GET_CODE (XEXP (x, 0)) == SUBREG
6884                && subreg_lowpart_p (XEXP (x, 0))
6885                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6886                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6887         {
6888           new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6889                                          next_code);
6890           new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6891                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6892                                  0, in_code == COMPARE);
6893         }
6894       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
6895       else if ((GET_CODE (XEXP (x, 0)) == XOR
6896                 || GET_CODE (XEXP (x, 0)) == IOR)
6897                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6898                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6899                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6900         {
6901           /* Apply the distributive law, and then try to make extractions.  */
6902           new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6903                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6904                                              XEXP (x, 1)),
6905                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6906                                              XEXP (x, 1)));
6907           new = make_compound_operation (new, in_code);
6908         }
6909
6910       /* If we are have (and (rotate X C) M) and C is larger than the number
6911          of bits in M, this is an extraction.  */
6912
6913       else if (GET_CODE (XEXP (x, 0)) == ROTATE
6914                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6915                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6916                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6917         {
6918           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6919           new = make_extraction (mode, new,
6920                                  (GET_MODE_BITSIZE (mode)
6921                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
6922                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
6923         }
6924
6925       /* On machines without logical shifts, if the operand of the AND is
6926          a logical shift and our mask turns off all the propagated sign
6927          bits, we can replace the logical shift with an arithmetic shift.  */
6928       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6929                && !have_insn_for (LSHIFTRT, mode)
6930                && have_insn_for (ASHIFTRT, mode)
6931                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6932                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6933                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6934                && mode_width <= HOST_BITS_PER_WIDE_INT)
6935         {
6936           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6937
6938           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6939           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6940             SUBST (XEXP (x, 0),
6941                    gen_rtx_ASHIFTRT (mode,
6942                                      make_compound_operation
6943                                      (XEXP (XEXP (x, 0), 0), next_code),
6944                                      XEXP (XEXP (x, 0), 1)));
6945         }
6946
6947       /* If the constant is one less than a power of two, this might be
6948          representable by an extraction even if no shift is present.
6949          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6950          we are in a COMPARE.  */
6951       else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6952         new = make_extraction (mode,
6953                                make_compound_operation (XEXP (x, 0),
6954                                                         next_code),
6955                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6956
6957       /* If we are in a comparison and this is an AND with a power of two,
6958          convert this into the appropriate bit extract.  */
6959       else if (in_code == COMPARE
6960                && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6961         new = make_extraction (mode,
6962                                make_compound_operation (XEXP (x, 0),
6963                                                         next_code),
6964                                i, NULL_RTX, 1, 1, 0, 1);
6965
6966       break;
6967
6968     case LSHIFTRT:
6969       /* If the sign bit is known to be zero, replace this with an
6970          arithmetic shift.  */
6971       if (have_insn_for (ASHIFTRT, mode)
6972           && ! have_insn_for (LSHIFTRT, mode)
6973           && mode_width <= HOST_BITS_PER_WIDE_INT
6974           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6975         {
6976           new = gen_rtx_ASHIFTRT (mode,
6977                                   make_compound_operation (XEXP (x, 0),
6978                                                            next_code),
6979                                   XEXP (x, 1));
6980           break;
6981         }
6982
6983       /* ... fall through ...  */
6984
6985     case ASHIFTRT:
6986       lhs = XEXP (x, 0);
6987       rhs = XEXP (x, 1);
6988
6989       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6990          this is a SIGN_EXTRACT.  */
6991       if (GET_CODE (rhs) == CONST_INT
6992           && GET_CODE (lhs) == ASHIFT
6993           && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6994           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6995         {
6996           new = make_compound_operation (XEXP (lhs, 0), next_code);
6997           new = make_extraction (mode, new,
6998                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6999                                  NULL_RTX, mode_width - INTVAL (rhs),
7000                                  code == LSHIFTRT, 0, in_code == COMPARE);
7001           break;
7002         }
7003
7004       /* See if we have operations between an ASHIFTRT and an ASHIFT.
7005          If so, try to merge the shifts into a SIGN_EXTEND.  We could
7006          also do this for some cases of SIGN_EXTRACT, but it doesn't
7007          seem worth the effort; the case checked for occurs on Alpha.  */
7008
7009       if (!OBJECT_P (lhs)
7010           && ! (GET_CODE (lhs) == SUBREG
7011                 && (OBJECT_P (SUBREG_REG (lhs))))
7012           && GET_CODE (rhs) == CONST_INT
7013           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7014           && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7015         new = make_extraction (mode, make_compound_operation (new, next_code),
7016                                0, NULL_RTX, mode_width - INTVAL (rhs),
7017                                code == LSHIFTRT, 0, in_code == COMPARE);
7018
7019       break;
7020
7021     case SUBREG:
7022       /* Call ourselves recursively on the inner expression.  If we are
7023          narrowing the object and it has a different RTL code from
7024          what it originally did, do this SUBREG as a force_to_mode.  */
7025
7026       tem = make_compound_operation (SUBREG_REG (x), in_code);
7027
7028       {
7029         rtx simplified;
7030         simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
7031                                       SUBREG_BYTE (x));
7032
7033         if (simplified)
7034           tem = simplified;
7035
7036         if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
7037             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
7038             && subreg_lowpart_p (x))
7039           {
7040             rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
7041                                        0);
7042
7043             /* If we have something other than a SUBREG, we might have
7044                done an expansion, so rerun ourselves.  */
7045             if (GET_CODE (newer) != SUBREG)
7046               newer = make_compound_operation (newer, in_code);
7047
7048             return newer;
7049           }
7050
7051         if (simplified)
7052           return tem;
7053       }
7054       break;
7055
7056     default:
7057       break;
7058     }
7059
7060   if (new)
7061     {
7062       x = gen_lowpart (mode, new);
7063       code = GET_CODE (x);
7064     }
7065
7066   /* Now recursively process each operand of this operation.  */
7067   fmt = GET_RTX_FORMAT (code);
7068   for (i = 0; i < GET_RTX_LENGTH (code); i++)
7069     if (fmt[i] == 'e')
7070       {
7071         new = make_compound_operation (XEXP (x, i), next_code);
7072         SUBST (XEXP (x, i), new);
7073       }
7074
7075   /* If this is a commutative operation, the changes to the operands
7076      may have made it noncanonical.  */
7077   if (COMMUTATIVE_ARITH_P (x)
7078       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7079     {
7080       tem = XEXP (x, 0);
7081       SUBST (XEXP (x, 0), XEXP (x, 1));
7082       SUBST (XEXP (x, 1), tem);
7083     }
7084
7085   return x;
7086 }
7087 \f
7088 /* Given M see if it is a value that would select a field of bits
7089    within an item, but not the entire word.  Return -1 if not.
7090    Otherwise, return the starting position of the field, where 0 is the
7091    low-order bit.
7092
7093    *PLEN is set to the length of the field.  */
7094
7095 static int
7096 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7097 {
7098   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
7099   int pos = exact_log2 (m & -m);
7100   int len = 0;
7101
7102   if (pos >= 0)
7103     /* Now shift off the low-order zero bits and see if we have a
7104        power of two minus 1.  */
7105     len = exact_log2 ((m >> pos) + 1);
7106
7107   if (len <= 0)
7108     pos = -1;
7109
7110   *plen = len;
7111   return pos;
7112 }
7113 \f
7114 /* If X refers to a register that equals REG in value, replace these
7115    references with REG.  */
7116 static rtx
7117 canon_reg_for_combine (rtx x, rtx reg)
7118 {
7119   rtx op0, op1, op2;
7120   const char *fmt;
7121   int i;
7122   bool copied;
7123
7124   enum rtx_code code = GET_CODE (x);
7125   switch (GET_RTX_CLASS (code))
7126     {
7127     case RTX_UNARY:
7128       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7129       if (op0 != XEXP (x, 0))
7130         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7131                                    GET_MODE (reg));
7132       break;
7133
7134     case RTX_BIN_ARITH:
7135     case RTX_COMM_ARITH:
7136       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7137       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7138       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7139         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7140       break;
7141
7142     case RTX_COMPARE:
7143     case RTX_COMM_COMPARE:
7144       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7145       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7146       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7147         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7148                                         GET_MODE (op0), op0, op1);
7149       break;
7150
7151     case RTX_TERNARY:
7152     case RTX_BITFIELD_OPS:
7153       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7154       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7155       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7156       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7157         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7158                                      GET_MODE (op0), op0, op1, op2);
7159
7160     case RTX_OBJ:
7161       if (REG_P (x))
7162         {
7163           if (rtx_equal_p (get_last_value (reg), x)
7164               || rtx_equal_p (reg, get_last_value (x)))
7165             return reg;
7166           else
7167             break;
7168         }
7169
7170       /* fall through */
7171
7172     default:
7173       fmt = GET_RTX_FORMAT (code);
7174       copied = false;
7175       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7176         if (fmt[i] == 'e')
7177           {
7178             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7179             if (op != XEXP (x, i))
7180               {
7181                 if (!copied)
7182                   {
7183                     copied = true;
7184                     x = copy_rtx (x);
7185                   }
7186                 XEXP (x, i) = op;
7187               }
7188           }
7189         else if (fmt[i] == 'E')
7190           {
7191             int j;
7192             for (j = 0; j < XVECLEN (x, i); j++)
7193               {
7194                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7195                 if (op != XVECEXP (x, i, j))
7196                   {
7197                     if (!copied)
7198                       {
7199                         copied = true;
7200                         x = copy_rtx (x);
7201                       }
7202                     XVECEXP (x, i, j) = op;
7203                   }
7204               }
7205           }
7206
7207       break;
7208     }
7209
7210   return x;
7211 }
7212
7213 /* Return X converted to MODE.  If the value is already truncated to
7214    MODE we can just return a subreg even though in the general case we
7215    would need an explicit truncation.  */
7216
7217 static rtx
7218 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7219 {
7220   if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
7221       || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7222                                 GET_MODE_BITSIZE (GET_MODE (x)))
7223       || (REG_P (x) && reg_truncated_to_mode (mode, x)))
7224     return gen_lowpart (mode, x);
7225   else
7226     return simplify_gen_unary (TRUNCATE, mode, x, GET_MODE (x));
7227 }
7228
7229 /* See if X can be simplified knowing that we will only refer to it in
7230    MODE and will only refer to those bits that are nonzero in MASK.
7231    If other bits are being computed or if masking operations are done
7232    that select a superset of the bits in MASK, they can sometimes be
7233    ignored.
7234
7235    Return a possibly simplified expression, but always convert X to
7236    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
7237
7238    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7239    are all off in X.  This is used when X will be complemented, by either
7240    NOT, NEG, or XOR.  */
7241
7242 static rtx
7243 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7244                int just_select)
7245 {
7246   enum rtx_code code = GET_CODE (x);
7247   int next_select = just_select || code == XOR || code == NOT || code == NEG;
7248   enum machine_mode op_mode;
7249   unsigned HOST_WIDE_INT fuller_mask, nonzero;
7250   rtx op0, op1, temp;
7251
7252   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
7253      code below will do the wrong thing since the mode of such an
7254      expression is VOIDmode.
7255
7256      Also do nothing if X is a CLOBBER; this can happen if X was
7257      the return value from a call to gen_lowpart.  */
7258   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7259     return x;
7260
7261   /* We want to perform the operation is its present mode unless we know
7262      that the operation is valid in MODE, in which case we do the operation
7263      in MODE.  */
7264   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7265               && have_insn_for (code, mode))
7266              ? mode : GET_MODE (x));
7267
7268   /* It is not valid to do a right-shift in a narrower mode
7269      than the one it came in with.  */
7270   if ((code == LSHIFTRT || code == ASHIFTRT)
7271       && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7272     op_mode = GET_MODE (x);
7273
7274   /* Truncate MASK to fit OP_MODE.  */
7275   if (op_mode)
7276     mask &= GET_MODE_MASK (op_mode);
7277
7278   /* When we have an arithmetic operation, or a shift whose count we
7279      do not know, we need to assume that all bits up to the highest-order
7280      bit in MASK will be needed.  This is how we form such a mask.  */
7281   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7282     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7283   else
7284     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7285                    - 1);
7286
7287   /* Determine what bits of X are guaranteed to be (non)zero.  */
7288   nonzero = nonzero_bits (x, mode);
7289
7290   /* If none of the bits in X are needed, return a zero.  */
7291   if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7292     x = const0_rtx;
7293
7294   /* If X is a CONST_INT, return a new one.  Do this here since the
7295      test below will fail.  */
7296   if (GET_CODE (x) == CONST_INT)
7297     {
7298       if (SCALAR_INT_MODE_P (mode))
7299         return gen_int_mode (INTVAL (x) & mask, mode);
7300       else
7301         {
7302           x = GEN_INT (INTVAL (x) & mask);
7303           return gen_lowpart_common (mode, x);
7304         }
7305     }
7306
7307   /* If X is narrower than MODE and we want all the bits in X's mode, just
7308      get X in the proper mode.  */
7309   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7310       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7311     return gen_lowpart (mode, x);
7312
7313   switch (code)
7314     {
7315     case CLOBBER:
7316       /* If X is a (clobber (const_int)), return it since we know we are
7317          generating something that won't match.  */
7318       return x;
7319
7320     case SIGN_EXTEND:
7321     case ZERO_EXTEND:
7322     case ZERO_EXTRACT:
7323     case SIGN_EXTRACT:
7324       x = expand_compound_operation (x);
7325       if (GET_CODE (x) != code)
7326         return force_to_mode (x, mode, mask, next_select);
7327       break;
7328
7329     case SUBREG:
7330       if (subreg_lowpart_p (x)
7331           /* We can ignore the effect of this SUBREG if it narrows the mode or
7332              if the constant masks to zero all the bits the mode doesn't
7333              have.  */
7334           && ((GET_MODE_SIZE (GET_MODE (x))
7335                < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7336               || (0 == (mask
7337                         & GET_MODE_MASK (GET_MODE (x))
7338                         & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7339         return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
7340       break;
7341
7342     case AND:
7343       /* If this is an AND with a constant, convert it into an AND
7344          whose constant is the AND of that constant with MASK.  If it
7345          remains an AND of MASK, delete it since it is redundant.  */
7346
7347       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7348         {
7349           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7350                                       mask & INTVAL (XEXP (x, 1)));
7351
7352           /* If X is still an AND, see if it is an AND with a mask that
7353              is just some low-order bits.  If so, and it is MASK, we don't
7354              need it.  */
7355
7356           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7357               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7358                   == mask))
7359             x = XEXP (x, 0);
7360
7361           /* If it remains an AND, try making another AND with the bits
7362              in the mode mask that aren't in MASK turned on.  If the
7363              constant in the AND is wide enough, this might make a
7364              cheaper constant.  */
7365
7366           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7367               && GET_MODE_MASK (GET_MODE (x)) != mask
7368               && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7369             {
7370               HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7371                                     | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7372               int width = GET_MODE_BITSIZE (GET_MODE (x));
7373               rtx y;
7374
7375               /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7376                  number, sign extend it.  */
7377               if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7378                   && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7379                 cval |= (HOST_WIDE_INT) -1 << width;
7380
7381               y = simplify_gen_binary (AND, GET_MODE (x),
7382                                        XEXP (x, 0), GEN_INT (cval));
7383               if (rtx_cost (y, SET) < rtx_cost (x, SET))
7384                 x = y;
7385             }
7386
7387           break;
7388         }
7389
7390       goto binop;
7391
7392     case PLUS:
7393       /* In (and (plus FOO C1) M), if M is a mask that just turns off
7394          low-order bits (as in an alignment operation) and FOO is already
7395          aligned to that boundary, mask C1 to that boundary as well.
7396          This may eliminate that PLUS and, later, the AND.  */
7397
7398       {
7399         unsigned int width = GET_MODE_BITSIZE (mode);
7400         unsigned HOST_WIDE_INT smask = mask;
7401
7402         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7403            number, sign extend it.  */
7404
7405         if (width < HOST_BITS_PER_WIDE_INT
7406             && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7407           smask |= (HOST_WIDE_INT) -1 << width;
7408
7409         if (GET_CODE (XEXP (x, 1)) == CONST_INT
7410             && exact_log2 (- smask) >= 0
7411             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7412             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7413           return force_to_mode (plus_constant (XEXP (x, 0),
7414                                                (INTVAL (XEXP (x, 1)) & smask)),
7415                                 mode, smask, next_select);
7416       }
7417
7418       /* ... fall through ...  */
7419
7420     case MULT:
7421       /* For PLUS, MINUS and MULT, we need any bits less significant than the
7422          most significant bit in MASK since carries from those bits will
7423          affect the bits we are interested in.  */
7424       mask = fuller_mask;
7425       goto binop;
7426
7427     case MINUS:
7428       /* If X is (minus C Y) where C's least set bit is larger than any bit
7429          in the mask, then we may replace with (neg Y).  */
7430       if (GET_CODE (XEXP (x, 0)) == CONST_INT
7431           && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7432                                         & -INTVAL (XEXP (x, 0))))
7433               > mask))
7434         {
7435           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7436                                   GET_MODE (x));
7437           return force_to_mode (x, mode, mask, next_select);
7438         }
7439
7440       /* Similarly, if C contains every bit in the fuller_mask, then we may
7441          replace with (not Y).  */
7442       if (GET_CODE (XEXP (x, 0)) == CONST_INT
7443           && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7444               == INTVAL (XEXP (x, 0))))
7445         {
7446           x = simplify_gen_unary (NOT, GET_MODE (x),
7447                                   XEXP (x, 1), GET_MODE (x));
7448           return force_to_mode (x, mode, mask, next_select);
7449         }
7450
7451       mask = fuller_mask;
7452       goto binop;
7453
7454     case IOR:
7455     case XOR:
7456       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7457          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7458          operation which may be a bitfield extraction.  Ensure that the
7459          constant we form is not wider than the mode of X.  */
7460
7461       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7462           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7463           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7464           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7465           && GET_CODE (XEXP (x, 1)) == CONST_INT
7466           && ((INTVAL (XEXP (XEXP (x, 0), 1))
7467                + floor_log2 (INTVAL (XEXP (x, 1))))
7468               < GET_MODE_BITSIZE (GET_MODE (x)))
7469           && (INTVAL (XEXP (x, 1))
7470               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7471         {
7472           temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7473                           << INTVAL (XEXP (XEXP (x, 0), 1)));
7474           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7475                                       XEXP (XEXP (x, 0), 0), temp);
7476           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7477                                    XEXP (XEXP (x, 0), 1));
7478           return force_to_mode (x, mode, mask, next_select);
7479         }
7480
7481     binop:
7482       /* For most binary operations, just propagate into the operation and
7483          change the mode if we have an operation of that mode.  */
7484
7485       op0 = gen_lowpart_or_truncate (op_mode,
7486                                      force_to_mode (XEXP (x, 0), mode, mask,
7487                                                     next_select));
7488       op1 = gen_lowpart_or_truncate (op_mode,
7489                                      force_to_mode (XEXP (x, 1), mode, mask,
7490                                         next_select));
7491
7492       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7493         x = simplify_gen_binary (code, op_mode, op0, op1);
7494       break;
7495
7496     case ASHIFT:
7497       /* For left shifts, do the same, but just for the first operand.
7498          However, we cannot do anything with shifts where we cannot
7499          guarantee that the counts are smaller than the size of the mode
7500          because such a count will have a different meaning in a
7501          wider mode.  */
7502
7503       if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7504              && INTVAL (XEXP (x, 1)) >= 0
7505              && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7506           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7507                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7508                     < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7509         break;
7510
7511       /* If the shift count is a constant and we can do arithmetic in
7512          the mode of the shift, refine which bits we need.  Otherwise, use the
7513          conservative form of the mask.  */
7514       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7515           && INTVAL (XEXP (x, 1)) >= 0
7516           && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7517           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7518         mask >>= INTVAL (XEXP (x, 1));
7519       else
7520         mask = fuller_mask;
7521
7522       op0 = gen_lowpart_or_truncate (op_mode,
7523                                      force_to_mode (XEXP (x, 0), op_mode,
7524                                                     mask, next_select));
7525
7526       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7527         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7528       break;
7529
7530     case LSHIFTRT:
7531       /* Here we can only do something if the shift count is a constant,
7532          this shift constant is valid for the host, and we can do arithmetic
7533          in OP_MODE.  */
7534
7535       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7536           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7537           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7538         {
7539           rtx inner = XEXP (x, 0);
7540           unsigned HOST_WIDE_INT inner_mask;
7541
7542           /* Select the mask of the bits we need for the shift operand.  */
7543           inner_mask = mask << INTVAL (XEXP (x, 1));
7544
7545           /* We can only change the mode of the shift if we can do arithmetic
7546              in the mode of the shift and INNER_MASK is no wider than the
7547              width of X's mode.  */
7548           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7549             op_mode = GET_MODE (x);
7550
7551           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7552
7553           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7554             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7555         }
7556
7557       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7558          shift and AND produces only copies of the sign bit (C2 is one less
7559          than a power of two), we can do this with just a shift.  */
7560
7561       if (GET_CODE (x) == LSHIFTRT
7562           && GET_CODE (XEXP (x, 1)) == CONST_INT
7563           /* The shift puts one of the sign bit copies in the least significant
7564              bit.  */
7565           && ((INTVAL (XEXP (x, 1))
7566                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7567               >= GET_MODE_BITSIZE (GET_MODE (x)))
7568           && exact_log2 (mask + 1) >= 0
7569           /* Number of bits left after the shift must be more than the mask
7570              needs.  */
7571           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7572               <= GET_MODE_BITSIZE (GET_MODE (x)))
7573           /* Must be more sign bit copies than the mask needs.  */
7574           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7575               >= exact_log2 (mask + 1)))
7576         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7577                                  GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7578                                           - exact_log2 (mask + 1)));
7579
7580       goto shiftrt;
7581
7582     case ASHIFTRT:
7583       /* If we are just looking for the sign bit, we don't need this shift at
7584          all, even if it has a variable count.  */
7585       if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7586           && (mask == ((unsigned HOST_WIDE_INT) 1
7587                        << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7588         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7589
7590       /* If this is a shift by a constant, get a mask that contains those bits
7591          that are not copies of the sign bit.  We then have two cases:  If
7592          MASK only includes those bits, this can be a logical shift, which may
7593          allow simplifications.  If MASK is a single-bit field not within
7594          those bits, we are requesting a copy of the sign bit and hence can
7595          shift the sign bit to the appropriate location.  */
7596
7597       if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7598           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7599         {
7600           int i;
7601
7602           /* If the considered data is wider than HOST_WIDE_INT, we can't
7603              represent a mask for all its bits in a single scalar.
7604              But we only care about the lower bits, so calculate these.  */
7605
7606           if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7607             {
7608               nonzero = ~(HOST_WIDE_INT) 0;
7609
7610               /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7611                  is the number of bits a full-width mask would have set.
7612                  We need only shift if these are fewer than nonzero can
7613                  hold.  If not, we must keep all bits set in nonzero.  */
7614
7615               if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7616                   < HOST_BITS_PER_WIDE_INT)
7617                 nonzero >>= INTVAL (XEXP (x, 1))
7618                             + HOST_BITS_PER_WIDE_INT
7619                             - GET_MODE_BITSIZE (GET_MODE (x)) ;
7620             }
7621           else
7622             {
7623               nonzero = GET_MODE_MASK (GET_MODE (x));
7624               nonzero >>= INTVAL (XEXP (x, 1));
7625             }
7626
7627           if ((mask & ~nonzero) == 0)
7628             {
7629               x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7630                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
7631               if (GET_CODE (x) != ASHIFTRT)
7632                 return force_to_mode (x, mode, mask, next_select);
7633             }
7634
7635           else if ((i = exact_log2 (mask)) >= 0)
7636             {
7637               x = simplify_shift_const
7638                   (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7639                    GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7640
7641               if (GET_CODE (x) != ASHIFTRT)
7642                 return force_to_mode (x, mode, mask, next_select);
7643             }
7644         }
7645
7646       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
7647          even if the shift count isn't a constant.  */
7648       if (mask == 1)
7649         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7650                                  XEXP (x, 0), XEXP (x, 1));
7651
7652     shiftrt:
7653
7654       /* If this is a zero- or sign-extension operation that just affects bits
7655          we don't care about, remove it.  Be sure the call above returned
7656          something that is still a shift.  */
7657
7658       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7659           && GET_CODE (XEXP (x, 1)) == CONST_INT
7660           && INTVAL (XEXP (x, 1)) >= 0
7661           && (INTVAL (XEXP (x, 1))
7662               <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7663           && GET_CODE (XEXP (x, 0)) == ASHIFT
7664           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7665         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7666                               next_select);
7667
7668       break;
7669
7670     case ROTATE:
7671     case ROTATERT:
7672       /* If the shift count is constant and we can do computations
7673          in the mode of X, compute where the bits we care about are.
7674          Otherwise, we can't do anything.  Don't change the mode of
7675          the shift or propagate MODE into the shift, though.  */
7676       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7677           && INTVAL (XEXP (x, 1)) >= 0)
7678         {
7679           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7680                                             GET_MODE (x), GEN_INT (mask),
7681                                             XEXP (x, 1));
7682           if (temp && GET_CODE (temp) == CONST_INT)
7683             SUBST (XEXP (x, 0),
7684                    force_to_mode (XEXP (x, 0), GET_MODE (x),
7685                                   INTVAL (temp), next_select));
7686         }
7687       break;
7688
7689     case NEG:
7690       /* If we just want the low-order bit, the NEG isn't needed since it
7691          won't change the low-order bit.  */
7692       if (mask == 1)
7693         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7694
7695       /* We need any bits less significant than the most significant bit in
7696          MASK since carries from those bits will affect the bits we are
7697          interested in.  */
7698       mask = fuller_mask;
7699       goto unop;
7700
7701     case NOT:
7702       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7703          same as the XOR case above.  Ensure that the constant we form is not
7704          wider than the mode of X.  */
7705
7706       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7707           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7708           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7709           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7710               < GET_MODE_BITSIZE (GET_MODE (x)))
7711           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7712         {
7713           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7714                                GET_MODE (x));
7715           temp = simplify_gen_binary (XOR, GET_MODE (x),
7716                                       XEXP (XEXP (x, 0), 0), temp);
7717           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7718                                    temp, XEXP (XEXP (x, 0), 1));
7719
7720           return force_to_mode (x, mode, mask, next_select);
7721         }
7722
7723       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7724          use the full mask inside the NOT.  */
7725       mask = fuller_mask;
7726
7727     unop:
7728       op0 = gen_lowpart_or_truncate (op_mode,
7729                                      force_to_mode (XEXP (x, 0), mode, mask,
7730                                                     next_select));
7731       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7732         x = simplify_gen_unary (code, op_mode, op0, op_mode);
7733       break;
7734
7735     case NE:
7736       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7737          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7738          which is equal to STORE_FLAG_VALUE.  */
7739       if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7740           && GET_MODE (XEXP (x, 0)) == mode
7741           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7742           && (nonzero_bits (XEXP (x, 0), mode)
7743               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7744         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7745
7746       break;
7747
7748     case IF_THEN_ELSE:
7749       /* We have no way of knowing if the IF_THEN_ELSE can itself be
7750          written in a narrower mode.  We play it safe and do not do so.  */
7751
7752       SUBST (XEXP (x, 1),
7753              gen_lowpart_or_truncate (GET_MODE (x),
7754                                       force_to_mode (XEXP (x, 1), mode,
7755                                                      mask, next_select)));
7756       SUBST (XEXP (x, 2),
7757              gen_lowpart_or_truncate (GET_MODE (x),
7758                                       force_to_mode (XEXP (x, 2), mode,
7759                                                      mask, next_select)));
7760       break;
7761
7762     default:
7763       break;
7764     }
7765
7766   /* Ensure we return a value of the proper mode.  */
7767   return gen_lowpart_or_truncate (mode, x);
7768 }
7769 \f
7770 /* Return nonzero if X is an expression that has one of two values depending on
7771    whether some other value is zero or nonzero.  In that case, we return the
7772    value that is being tested, *PTRUE is set to the value if the rtx being
7773    returned has a nonzero value, and *PFALSE is set to the other alternative.
7774
7775    If we return zero, we set *PTRUE and *PFALSE to X.  */
7776
7777 static rtx
7778 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7779 {
7780   enum machine_mode mode = GET_MODE (x);
7781   enum rtx_code code = GET_CODE (x);
7782   rtx cond0, cond1, true0, true1, false0, false1;
7783   unsigned HOST_WIDE_INT nz;
7784
7785   /* If we are comparing a value against zero, we are done.  */
7786   if ((code == NE || code == EQ)
7787       && XEXP (x, 1) == const0_rtx)
7788     {
7789       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7790       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7791       return XEXP (x, 0);
7792     }
7793
7794   /* If this is a unary operation whose operand has one of two values, apply
7795      our opcode to compute those values.  */
7796   else if (UNARY_P (x)
7797            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7798     {
7799       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7800       *pfalse = simplify_gen_unary (code, mode, false0,
7801                                     GET_MODE (XEXP (x, 0)));
7802       return cond0;
7803     }
7804
7805   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7806      make can't possibly match and would suppress other optimizations.  */
7807   else if (code == COMPARE)
7808     ;
7809
7810   /* If this is a binary operation, see if either side has only one of two
7811      values.  If either one does or if both do and they are conditional on
7812      the same value, compute the new true and false values.  */
7813   else if (BINARY_P (x))
7814     {
7815       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7816       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7817
7818       if ((cond0 != 0 || cond1 != 0)
7819           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7820         {
7821           /* If if_then_else_cond returned zero, then true/false are the
7822              same rtl.  We must copy one of them to prevent invalid rtl
7823              sharing.  */
7824           if (cond0 == 0)
7825             true0 = copy_rtx (true0);
7826           else if (cond1 == 0)
7827             true1 = copy_rtx (true1);
7828
7829           if (COMPARISON_P (x))
7830             {
7831               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7832                                                 true0, true1);
7833               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7834                                                  false0, false1);
7835              }
7836           else
7837             {
7838               *ptrue = simplify_gen_binary (code, mode, true0, true1);
7839               *pfalse = simplify_gen_binary (code, mode, false0, false1);
7840             }
7841
7842           return cond0 ? cond0 : cond1;
7843         }
7844
7845       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7846          operands is zero when the other is nonzero, and vice-versa,
7847          and STORE_FLAG_VALUE is 1 or -1.  */
7848
7849       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7850           && (code == PLUS || code == IOR || code == XOR || code == MINUS
7851               || code == UMAX)
7852           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7853         {
7854           rtx op0 = XEXP (XEXP (x, 0), 1);
7855           rtx op1 = XEXP (XEXP (x, 1), 1);
7856
7857           cond0 = XEXP (XEXP (x, 0), 0);
7858           cond1 = XEXP (XEXP (x, 1), 0);
7859
7860           if (COMPARISON_P (cond0)
7861               && COMPARISON_P (cond1)
7862               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7863                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7864                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7865                   || ((swap_condition (GET_CODE (cond0))
7866                        == reversed_comparison_code (cond1, NULL))
7867                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7868                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7869               && ! side_effects_p (x))
7870             {
7871               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7872               *pfalse = simplify_gen_binary (MULT, mode,
7873                                              (code == MINUS
7874                                               ? simplify_gen_unary (NEG, mode,
7875                                                                     op1, mode)
7876                                               : op1),
7877                                               const_true_rtx);
7878               return cond0;
7879             }
7880         }
7881
7882       /* Similarly for MULT, AND and UMIN, except that for these the result
7883          is always zero.  */
7884       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7885           && (code == MULT || code == AND || code == UMIN)
7886           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7887         {
7888           cond0 = XEXP (XEXP (x, 0), 0);
7889           cond1 = XEXP (XEXP (x, 1), 0);
7890
7891           if (COMPARISON_P (cond0)
7892               && COMPARISON_P (cond1)
7893               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7894                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7895                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7896                   || ((swap_condition (GET_CODE (cond0))
7897                        == reversed_comparison_code (cond1, NULL))
7898                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7899                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7900               && ! side_effects_p (x))
7901             {
7902               *ptrue = *pfalse = const0_rtx;
7903               return cond0;
7904             }
7905         }
7906     }
7907
7908   else if (code == IF_THEN_ELSE)
7909     {
7910       /* If we have IF_THEN_ELSE already, extract the condition and
7911          canonicalize it if it is NE or EQ.  */
7912       cond0 = XEXP (x, 0);
7913       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7914       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7915         return XEXP (cond0, 0);
7916       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7917         {
7918           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7919           return XEXP (cond0, 0);
7920         }
7921       else
7922         return cond0;
7923     }
7924
7925   /* If X is a SUBREG, we can narrow both the true and false values
7926      if the inner expression, if there is a condition.  */
7927   else if (code == SUBREG
7928            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7929                                                &true0, &false0)))
7930     {
7931       true0 = simplify_gen_subreg (mode, true0,
7932                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7933       false0 = simplify_gen_subreg (mode, false0,
7934                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7935       if (true0 && false0)
7936         {
7937           *ptrue = true0;
7938           *pfalse = false0;
7939           return cond0;
7940         }
7941     }
7942
7943   /* If X is a constant, this isn't special and will cause confusions
7944      if we treat it as such.  Likewise if it is equivalent to a constant.  */
7945   else if (CONSTANT_P (x)
7946            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7947     ;
7948
7949   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7950      will be least confusing to the rest of the compiler.  */
7951   else if (mode == BImode)
7952     {
7953       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7954       return x;
7955     }
7956
7957   /* If X is known to be either 0 or -1, those are the true and
7958      false values when testing X.  */
7959   else if (x == constm1_rtx || x == const0_rtx
7960            || (mode != VOIDmode
7961                && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7962     {
7963       *ptrue = constm1_rtx, *pfalse = const0_rtx;
7964       return x;
7965     }
7966
7967   /* Likewise for 0 or a single bit.  */
7968   else if (SCALAR_INT_MODE_P (mode)
7969            && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7970            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7971     {
7972       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7973       return x;
7974     }
7975
7976   /* Otherwise fail; show no condition with true and false values the same.  */
7977   *ptrue = *pfalse = x;
7978   return 0;
7979 }
7980 \f
7981 /* Return the value of expression X given the fact that condition COND
7982    is known to be true when applied to REG as its first operand and VAL
7983    as its second.  X is known to not be shared and so can be modified in
7984    place.
7985
7986    We only handle the simplest cases, and specifically those cases that
7987    arise with IF_THEN_ELSE expressions.  */
7988
7989 static rtx
7990 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7991 {
7992   enum rtx_code code = GET_CODE (x);
7993   rtx temp;
7994   const char *fmt;
7995   int i, j;
7996
7997   if (side_effects_p (x))
7998     return x;
7999
8000   /* If either operand of the condition is a floating point value,
8001      then we have to avoid collapsing an EQ comparison.  */
8002   if (cond == EQ
8003       && rtx_equal_p (x, reg)
8004       && ! FLOAT_MODE_P (GET_MODE (x))
8005       && ! FLOAT_MODE_P (GET_MODE (val)))
8006     return val;
8007
8008   if (cond == UNEQ && rtx_equal_p (x, reg))
8009     return val;
8010
8011   /* If X is (abs REG) and we know something about REG's relationship
8012      with zero, we may be able to simplify this.  */
8013
8014   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8015     switch (cond)
8016       {
8017       case GE:  case GT:  case EQ:
8018         return XEXP (x, 0);
8019       case LT:  case LE:
8020         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8021                                    XEXP (x, 0),
8022                                    GET_MODE (XEXP (x, 0)));
8023       default:
8024         break;
8025       }
8026
8027   /* The only other cases we handle are MIN, MAX, and comparisons if the
8028      operands are the same as REG and VAL.  */
8029
8030   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8031     {
8032       if (rtx_equal_p (XEXP (x, 0), val))
8033         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8034
8035       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8036         {
8037           if (COMPARISON_P (x))
8038             {
8039               if (comparison_dominates_p (cond, code))
8040                 return const_true_rtx;
8041
8042               code = reversed_comparison_code (x, NULL);
8043               if (code != UNKNOWN
8044                   && comparison_dominates_p (cond, code))
8045                 return const0_rtx;
8046               else
8047                 return x;
8048             }
8049           else if (code == SMAX || code == SMIN
8050                    || code == UMIN || code == UMAX)
8051             {
8052               int unsignedp = (code == UMIN || code == UMAX);
8053
8054               /* Do not reverse the condition when it is NE or EQ.
8055                  This is because we cannot conclude anything about
8056                  the value of 'SMAX (x, y)' when x is not equal to y,
8057                  but we can when x equals y.  */
8058               if ((code == SMAX || code == UMAX)
8059                   && ! (cond == EQ || cond == NE))
8060                 cond = reverse_condition (cond);
8061
8062               switch (cond)
8063                 {
8064                 case GE:   case GT:
8065                   return unsignedp ? x : XEXP (x, 1);
8066                 case LE:   case LT:
8067                   return unsignedp ? x : XEXP (x, 0);
8068                 case GEU:  case GTU:
8069                   return unsignedp ? XEXP (x, 1) : x;
8070                 case LEU:  case LTU:
8071                   return unsignedp ? XEXP (x, 0) : x;
8072                 default:
8073                   break;
8074                 }
8075             }
8076         }
8077     }
8078   else if (code == SUBREG)
8079     {
8080       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8081       rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
8082
8083       if (SUBREG_REG (x) != r)
8084         {
8085           /* We must simplify subreg here, before we lose track of the
8086              original inner_mode.  */
8087           new = simplify_subreg (GET_MODE (x), r,
8088                                  inner_mode, SUBREG_BYTE (x));
8089           if (new)
8090             return new;
8091           else
8092             SUBST (SUBREG_REG (x), r);
8093         }
8094
8095       return x;
8096     }
8097   /* We don't have to handle SIGN_EXTEND here, because even in the
8098      case of replacing something with a modeless CONST_INT, a
8099      CONST_INT is already (supposed to be) a valid sign extension for
8100      its narrower mode, which implies it's already properly
8101      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
8102      story is different.  */
8103   else if (code == ZERO_EXTEND)
8104     {
8105       enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8106       rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
8107
8108       if (XEXP (x, 0) != r)
8109         {
8110           /* We must simplify the zero_extend here, before we lose
8111              track of the original inner_mode.  */
8112           new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8113                                           r, inner_mode);
8114           if (new)
8115             return new;
8116           else
8117             SUBST (XEXP (x, 0), r);
8118         }
8119
8120       return x;
8121     }
8122
8123   fmt = GET_RTX_FORMAT (code);
8124   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8125     {
8126       if (fmt[i] == 'e')
8127         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8128       else if (fmt[i] == 'E')
8129         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8130           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8131                                                 cond, reg, val));
8132     }
8133
8134   return x;
8135 }
8136 \f
8137 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8138    assignment as a field assignment.  */
8139
8140 static int
8141 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8142 {
8143   if (x == y || rtx_equal_p (x, y))
8144     return 1;
8145
8146   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8147     return 0;
8148
8149   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8150      Note that all SUBREGs of MEM are paradoxical; otherwise they
8151      would have been rewritten.  */
8152   if (MEM_P (x) && GET_CODE (y) == SUBREG
8153       && MEM_P (SUBREG_REG (y))
8154       && rtx_equal_p (SUBREG_REG (y),
8155                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8156     return 1;
8157
8158   if (MEM_P (y) && GET_CODE (x) == SUBREG
8159       && MEM_P (SUBREG_REG (x))
8160       && rtx_equal_p (SUBREG_REG (x),
8161                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8162     return 1;
8163
8164   /* We used to see if get_last_value of X and Y were the same but that's
8165      not correct.  In one direction, we'll cause the assignment to have
8166      the wrong destination and in the case, we'll import a register into this
8167      insn that might have already have been dead.   So fail if none of the
8168      above cases are true.  */
8169   return 0;
8170 }
8171 \f
8172 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8173    Return that assignment if so.
8174
8175    We only handle the most common cases.  */
8176
8177 static rtx
8178 make_field_assignment (rtx x)
8179 {
8180   rtx dest = SET_DEST (x);
8181   rtx src = SET_SRC (x);
8182   rtx assign;
8183   rtx rhs, lhs;
8184   HOST_WIDE_INT c1;
8185   HOST_WIDE_INT pos;
8186   unsigned HOST_WIDE_INT len;
8187   rtx other;
8188   enum machine_mode mode;
8189
8190   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8191      a clear of a one-bit field.  We will have changed it to
8192      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
8193      for a SUBREG.  */
8194
8195   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8196       && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
8197       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8198       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8199     {
8200       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8201                                 1, 1, 1, 0);
8202       if (assign != 0)
8203         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8204       return x;
8205     }
8206
8207   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8208       && subreg_lowpart_p (XEXP (src, 0))
8209       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8210           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8211       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8212       && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
8213       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8214       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8215     {
8216       assign = make_extraction (VOIDmode, dest, 0,
8217                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8218                                 1, 1, 1, 0);
8219       if (assign != 0)
8220         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8221       return x;
8222     }
8223
8224   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8225      one-bit field.  */
8226   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8227       && XEXP (XEXP (src, 0), 0) == const1_rtx
8228       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8229     {
8230       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8231                                 1, 1, 1, 0);
8232       if (assign != 0)
8233         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8234       return x;
8235     }
8236
8237   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8238      SRC is an AND with all bits of that field set, then we can discard
8239      the AND.  */
8240   if (GET_CODE (dest) == ZERO_EXTRACT
8241       && GET_CODE (XEXP (dest, 1)) == CONST_INT
8242       && GET_CODE (src) == AND
8243       && GET_CODE (XEXP (src, 1)) == CONST_INT)
8244     {
8245       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8246       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8247       unsigned HOST_WIDE_INT ze_mask;
8248
8249       if (width >= HOST_BITS_PER_WIDE_INT)
8250         ze_mask = -1;
8251       else
8252         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8253
8254       /* Complete overlap.  We can remove the source AND.  */
8255       if ((and_mask & ze_mask) == ze_mask)
8256         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8257
8258       /* Partial overlap.  We can reduce the source AND.  */
8259       if ((and_mask & ze_mask) != and_mask)
8260         {
8261           mode = GET_MODE (src);
8262           src = gen_rtx_AND (mode, XEXP (src, 0),
8263                              gen_int_mode (and_mask & ze_mask, mode));
8264           return gen_rtx_SET (VOIDmode, dest, src);
8265         }
8266     }
8267
8268   /* The other case we handle is assignments into a constant-position
8269      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
8270      a mask that has all one bits except for a group of zero bits and
8271      OTHER is known to have zeros where C1 has ones, this is such an
8272      assignment.  Compute the position and length from C1.  Shift OTHER
8273      to the appropriate position, force it to the required mode, and
8274      make the extraction.  Check for the AND in both operands.  */
8275
8276   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8277     return x;
8278
8279   rhs = expand_compound_operation (XEXP (src, 0));
8280   lhs = expand_compound_operation (XEXP (src, 1));
8281
8282   if (GET_CODE (rhs) == AND
8283       && GET_CODE (XEXP (rhs, 1)) == CONST_INT
8284       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8285     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8286   else if (GET_CODE (lhs) == AND
8287            && GET_CODE (XEXP (lhs, 1)) == CONST_INT
8288            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8289     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8290   else
8291     return x;
8292
8293   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8294   if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8295       || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8296       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8297     return x;
8298
8299   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8300   if (assign == 0)
8301     return x;
8302
8303   /* The mode to use for the source is the mode of the assignment, or of
8304      what is inside a possible STRICT_LOW_PART.  */
8305   mode = (GET_CODE (assign) == STRICT_LOW_PART
8306           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8307
8308   /* Shift OTHER right POS places and make it the source, restricting it
8309      to the proper length and mode.  */
8310
8311   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
8312                                                      GET_MODE (src),
8313                                                      other, pos),
8314                                dest);
8315   src = force_to_mode (src, mode,
8316                        GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
8317                        ? ~(unsigned HOST_WIDE_INT) 0
8318                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8319                        0);
8320
8321   /* If SRC is masked by an AND that does not make a difference in
8322      the value being stored, strip it.  */
8323   if (GET_CODE (assign) == ZERO_EXTRACT
8324       && GET_CODE (XEXP (assign, 1)) == CONST_INT
8325       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8326       && GET_CODE (src) == AND
8327       && GET_CODE (XEXP (src, 1)) == CONST_INT
8328       && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8329           == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8330     src = XEXP (src, 0);
8331
8332   return gen_rtx_SET (VOIDmode, assign, src);
8333 }
8334 \f
8335 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8336    if so.  */
8337
8338 static rtx
8339 apply_distributive_law (rtx x)
8340 {
8341   enum rtx_code code = GET_CODE (x);
8342   enum rtx_code inner_code;
8343   rtx lhs, rhs, other;
8344   rtx tem;
8345
8346   /* Distributivity is not true for floating point as it can change the
8347      value.  So we don't do it unless -funsafe-math-optimizations.  */
8348   if (FLOAT_MODE_P (GET_MODE (x))
8349       && ! flag_unsafe_math_optimizations)
8350     return x;
8351
8352   /* The outer operation can only be one of the following:  */
8353   if (code != IOR && code != AND && code != XOR
8354       && code != PLUS && code != MINUS)
8355     return x;
8356
8357   lhs = XEXP (x, 0);
8358   rhs = XEXP (x, 1);
8359
8360   /* If either operand is a primitive we can't do anything, so get out
8361      fast.  */
8362   if (OBJECT_P (lhs) || OBJECT_P (rhs))
8363     return x;
8364
8365   lhs = expand_compound_operation (lhs);
8366   rhs = expand_compound_operation (rhs);
8367   inner_code = GET_CODE (lhs);
8368   if (inner_code != GET_CODE (rhs))
8369     return x;
8370
8371   /* See if the inner and outer operations distribute.  */
8372   switch (inner_code)
8373     {
8374     case LSHIFTRT:
8375     case ASHIFTRT:
8376     case AND:
8377     case IOR:
8378       /* These all distribute except over PLUS.  */
8379       if (code == PLUS || code == MINUS)
8380         return x;
8381       break;
8382
8383     case MULT:
8384       if (code != PLUS && code != MINUS)
8385         return x;
8386       break;
8387
8388     case ASHIFT:
8389       /* This is also a multiply, so it distributes over everything.  */
8390       break;
8391
8392     case SUBREG:
8393       /* Non-paradoxical SUBREGs distributes over all operations,
8394          provided the inner modes and byte offsets are the same, this
8395          is an extraction of a low-order part, we don't convert an fp
8396          operation to int or vice versa, this is not a vector mode,
8397          and we would not be converting a single-word operation into a
8398          multi-word operation.  The latter test is not required, but
8399          it prevents generating unneeded multi-word operations.  Some
8400          of the previous tests are redundant given the latter test,
8401          but are retained because they are required for correctness.
8402
8403          We produce the result slightly differently in this case.  */
8404
8405       if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8406           || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8407           || ! subreg_lowpart_p (lhs)
8408           || (GET_MODE_CLASS (GET_MODE (lhs))
8409               != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8410           || (GET_MODE_SIZE (GET_MODE (lhs))
8411               > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8412           || VECTOR_MODE_P (GET_MODE (lhs))
8413           || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
8414           /* Result might need to be truncated.  Don't change mode if
8415              explicit truncation is needed.  */
8416           || !TRULY_NOOP_TRUNCATION
8417                (GET_MODE_BITSIZE (GET_MODE (x)),
8418                 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
8419         return x;
8420
8421       tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8422                                  SUBREG_REG (lhs), SUBREG_REG (rhs));
8423       return gen_lowpart (GET_MODE (x), tem);
8424
8425     default:
8426       return x;
8427     }
8428
8429   /* Set LHS and RHS to the inner operands (A and B in the example
8430      above) and set OTHER to the common operand (C in the example).
8431      There is only one way to do this unless the inner operation is
8432      commutative.  */
8433   if (COMMUTATIVE_ARITH_P (lhs)
8434       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8435     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8436   else if (COMMUTATIVE_ARITH_P (lhs)
8437            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8438     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8439   else if (COMMUTATIVE_ARITH_P (lhs)
8440            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8441     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8442   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8443     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8444   else
8445     return x;
8446
8447   /* Form the new inner operation, seeing if it simplifies first.  */
8448   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8449
8450   /* There is one exception to the general way of distributing:
8451      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
8452   if (code == XOR && inner_code == IOR)
8453     {
8454       inner_code = AND;
8455       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8456     }
8457
8458   /* We may be able to continuing distributing the result, so call
8459      ourselves recursively on the inner operation before forming the
8460      outer operation, which we return.  */
8461   return simplify_gen_binary (inner_code, GET_MODE (x),
8462                               apply_distributive_law (tem), other);
8463 }
8464
8465 /* See if X is of the form (* (+ A B) C), and if so convert to
8466    (+ (* A C) (* B C)) and try to simplify.
8467
8468    Most of the time, this results in no change.  However, if some of
8469    the operands are the same or inverses of each other, simplifications
8470    will result.
8471
8472    For example, (and (ior A B) (not B)) can occur as the result of
8473    expanding a bit field assignment.  When we apply the distributive
8474    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8475    which then simplifies to (and (A (not B))).
8476
8477    Note that no checks happen on the validity of applying the inverse
8478    distributive law.  This is pointless since we can do it in the
8479    few places where this routine is called.
8480
8481    N is the index of the term that is decomposed (the arithmetic operation,
8482    i.e. (+ A B) in the first example above).  !N is the index of the term that
8483    is distributed, i.e. of C in the first example above.  */
8484 static rtx
8485 distribute_and_simplify_rtx (rtx x, int n)
8486 {
8487   enum machine_mode mode;
8488   enum rtx_code outer_code, inner_code;
8489   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8490
8491   decomposed = XEXP (x, n);
8492   if (!ARITHMETIC_P (decomposed))
8493     return NULL_RTX;
8494
8495   mode = GET_MODE (x);
8496   outer_code = GET_CODE (x);
8497   distributed = XEXP (x, !n);
8498
8499   inner_code = GET_CODE (decomposed);
8500   inner_op0 = XEXP (decomposed, 0);
8501   inner_op1 = XEXP (decomposed, 1);
8502
8503   /* Special case (and (xor B C) (not A)), which is equivalent to
8504      (xor (ior A B) (ior A C))  */
8505   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8506     {
8507       distributed = XEXP (distributed, 0);
8508       outer_code = IOR;
8509     }
8510
8511   if (n == 0)
8512     {
8513       /* Distribute the second term.  */
8514       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8515       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8516     }
8517   else
8518     {
8519       /* Distribute the first term.  */
8520       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8521       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8522     }
8523
8524   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8525                                                      new_op0, new_op1));
8526   if (GET_CODE (tmp) != outer_code
8527       && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8528     return tmp;
8529
8530   return NULL_RTX;
8531 }
8532 \f
8533 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8534    in MODE.  Return an equivalent form, if different from (and VAROP
8535    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
8536
8537 static rtx
8538 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8539                           unsigned HOST_WIDE_INT constop)
8540 {
8541   unsigned HOST_WIDE_INT nonzero;
8542   unsigned HOST_WIDE_INT orig_constop;
8543   rtx orig_varop;
8544   int i;
8545
8546   orig_varop = varop;
8547   orig_constop = constop;
8548   if (GET_CODE (varop) == CLOBBER)
8549     return NULL_RTX;
8550
8551   /* Simplify VAROP knowing that we will be only looking at some of the
8552      bits in it.
8553
8554      Note by passing in CONSTOP, we guarantee that the bits not set in
8555      CONSTOP are not significant and will never be examined.  We must
8556      ensure that is the case by explicitly masking out those bits
8557      before returning.  */
8558   varop = force_to_mode (varop, mode, constop, 0);
8559
8560   /* If VAROP is a CLOBBER, we will fail so return it.  */
8561   if (GET_CODE (varop) == CLOBBER)
8562     return varop;
8563
8564   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8565      to VAROP and return the new constant.  */
8566   if (GET_CODE (varop) == CONST_INT)
8567     return gen_int_mode (INTVAL (varop) & constop, mode);
8568
8569   /* See what bits may be nonzero in VAROP.  Unlike the general case of
8570      a call to nonzero_bits, here we don't care about bits outside
8571      MODE.  */
8572
8573   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8574
8575   /* Turn off all bits in the constant that are known to already be zero.
8576      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8577      which is tested below.  */
8578
8579   constop &= nonzero;
8580
8581   /* If we don't have any bits left, return zero.  */
8582   if (constop == 0)
8583     return const0_rtx;
8584
8585   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8586      a power of two, we can replace this with an ASHIFT.  */
8587   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8588       && (i = exact_log2 (constop)) >= 0)
8589     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8590
8591   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8592      or XOR, then try to apply the distributive law.  This may eliminate
8593      operations if either branch can be simplified because of the AND.
8594      It may also make some cases more complex, but those cases probably
8595      won't match a pattern either with or without this.  */
8596
8597   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8598     return
8599       gen_lowpart
8600         (mode,
8601          apply_distributive_law
8602          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8603                                simplify_and_const_int (NULL_RTX,
8604                                                        GET_MODE (varop),
8605                                                        XEXP (varop, 0),
8606                                                        constop),
8607                                simplify_and_const_int (NULL_RTX,
8608                                                        GET_MODE (varop),
8609                                                        XEXP (varop, 1),
8610                                                        constop))));
8611
8612   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8613      the AND and see if one of the operands simplifies to zero.  If so, we
8614      may eliminate it.  */
8615
8616   if (GET_CODE (varop) == PLUS
8617       && exact_log2 (constop + 1) >= 0)
8618     {
8619       rtx o0, o1;
8620
8621       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8622       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8623       if (o0 == const0_rtx)
8624         return o1;
8625       if (o1 == const0_rtx)
8626         return o0;
8627     }
8628
8629   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
8630   varop = gen_lowpart (mode, varop);
8631   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8632     return NULL_RTX;
8633
8634   /* If we are only masking insignificant bits, return VAROP.  */
8635   if (constop == nonzero)
8636     return varop;
8637
8638   if (varop == orig_varop && constop == orig_constop)
8639     return NULL_RTX;
8640
8641   /* Otherwise, return an AND.  */
8642   return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8643 }
8644
8645
8646 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8647    in MODE.
8648
8649    Return an equivalent form, if different from X.  Otherwise, return X.  If
8650    X is zero, we are to always construct the equivalent form.  */
8651
8652 static rtx
8653 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8654                         unsigned HOST_WIDE_INT constop)
8655 {
8656   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8657   if (tem)
8658     return tem;
8659
8660   if (!x)
8661     x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8662                              gen_int_mode (constop, mode));
8663   if (GET_MODE (x) != mode)
8664     x = gen_lowpart (mode, x);
8665   return x;
8666 }
8667 \f
8668 /* Given a REG, X, compute which bits in X can be nonzero.
8669    We don't care about bits outside of those defined in MODE.
8670
8671    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8672    a shift, AND, or zero_extract, we can do better.  */
8673
8674 static rtx
8675 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
8676                               const_rtx known_x ATTRIBUTE_UNUSED,
8677                               enum machine_mode known_mode ATTRIBUTE_UNUSED,
8678                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8679                               unsigned HOST_WIDE_INT *nonzero)
8680 {
8681   rtx tem;
8682   reg_stat_type *rsp;
8683
8684   /* If X is a register whose nonzero bits value is current, use it.
8685      Otherwise, if X is a register whose value we can find, use that
8686      value.  Otherwise, use the previously-computed global nonzero bits
8687      for this register.  */
8688
8689   rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8690   if (rsp->last_set_value != 0
8691       && (rsp->last_set_mode == mode
8692           || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
8693               && GET_MODE_CLASS (mode) == MODE_INT))
8694       && ((rsp->last_set_label >= label_tick_ebb_start
8695            && rsp->last_set_label < label_tick)
8696           || (rsp->last_set_label == label_tick
8697               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
8698           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8699               && REG_N_SETS (REGNO (x)) == 1
8700               && !REGNO_REG_SET_P
8701                   (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
8702     {
8703       *nonzero &= rsp->last_set_nonzero_bits;
8704       return NULL;
8705     }
8706
8707   tem = get_last_value (x);
8708
8709   if (tem)
8710     {
8711 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8712       /* If X is narrower than MODE and TEM is a non-negative
8713          constant that would appear negative in the mode of X,
8714          sign-extend it for use in reg_nonzero_bits because some
8715          machines (maybe most) will actually do the sign-extension
8716          and this is the conservative approach.
8717
8718          ??? For 2.5, try to tighten up the MD files in this regard
8719          instead of this kludge.  */
8720
8721       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8722           && GET_CODE (tem) == CONST_INT
8723           && INTVAL (tem) > 0
8724           && 0 != (INTVAL (tem)
8725                    & ((HOST_WIDE_INT) 1
8726                       << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8727         tem = GEN_INT (INTVAL (tem)
8728                        | ((HOST_WIDE_INT) (-1)
8729                           << GET_MODE_BITSIZE (GET_MODE (x))));
8730 #endif
8731       return tem;
8732     }
8733   else if (nonzero_sign_valid && rsp->nonzero_bits)
8734     {
8735       unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
8736
8737       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8738         /* We don't know anything about the upper bits.  */
8739         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8740       *nonzero &= mask;
8741     }
8742
8743   return NULL;
8744 }
8745
8746 /* Return the number of bits at the high-order end of X that are known to
8747    be equal to the sign bit.  X will be used in mode MODE; if MODE is
8748    VOIDmode, X will be used in its own mode.  The returned value  will always
8749    be between 1 and the number of bits in MODE.  */
8750
8751 static rtx
8752 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
8753                                      const_rtx known_x ATTRIBUTE_UNUSED,
8754                                      enum machine_mode known_mode
8755                                      ATTRIBUTE_UNUSED,
8756                                      unsigned int known_ret ATTRIBUTE_UNUSED,
8757                                      unsigned int *result)
8758 {
8759   rtx tem;
8760   reg_stat_type *rsp;
8761
8762   rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8763   if (rsp->last_set_value != 0
8764       && rsp->last_set_mode == mode
8765       && ((rsp->last_set_label >= label_tick_ebb_start
8766            && rsp->last_set_label < label_tick)
8767           || (rsp->last_set_label == label_tick
8768               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
8769           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8770               && REG_N_SETS (REGNO (x)) == 1
8771               && !REGNO_REG_SET_P
8772                   (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
8773     {
8774       *result = rsp->last_set_sign_bit_copies;
8775       return NULL;
8776     }
8777
8778   tem = get_last_value (x);
8779   if (tem != 0)
8780     return tem;
8781
8782   if (nonzero_sign_valid && rsp->sign_bit_copies != 0
8783       && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8784     *result = rsp->sign_bit_copies;
8785
8786   return NULL;
8787 }
8788 \f
8789 /* Return the number of "extended" bits there are in X, when interpreted
8790    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
8791    unsigned quantities, this is the number of high-order zero bits.
8792    For signed quantities, this is the number of copies of the sign bit
8793    minus 1.  In both case, this function returns the number of "spare"
8794    bits.  For example, if two quantities for which this function returns
8795    at least 1 are added, the addition is known not to overflow.
8796
8797    This function will always return 0 unless called during combine, which
8798    implies that it must be called from a define_split.  */
8799
8800 unsigned int
8801 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
8802 {
8803   if (nonzero_sign_valid == 0)
8804     return 0;
8805
8806   return (unsignedp
8807           ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8808              ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8809                                - floor_log2 (nonzero_bits (x, mode)))
8810              : 0)
8811           : num_sign_bit_copies (x, mode) - 1);
8812 }
8813 \f
8814 /* This function is called from `simplify_shift_const' to merge two
8815    outer operations.  Specifically, we have already found that we need
8816    to perform operation *POP0 with constant *PCONST0 at the outermost
8817    position.  We would now like to also perform OP1 with constant CONST1
8818    (with *POP0 being done last).
8819
8820    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8821    the resulting operation.  *PCOMP_P is set to 1 if we would need to
8822    complement the innermost operand, otherwise it is unchanged.
8823
8824    MODE is the mode in which the operation will be done.  No bits outside
8825    the width of this mode matter.  It is assumed that the width of this mode
8826    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8827
8828    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
8829    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
8830    result is simply *PCONST0.
8831
8832    If the resulting operation cannot be expressed as one operation, we
8833    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
8834
8835 static int
8836 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8837 {
8838   enum rtx_code op0 = *pop0;
8839   HOST_WIDE_INT const0 = *pconst0;
8840
8841   const0 &= GET_MODE_MASK (mode);
8842   const1 &= GET_MODE_MASK (mode);
8843
8844   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
8845   if (op0 == AND)
8846     const1 &= const0;
8847
8848   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
8849      if OP0 is SET.  */
8850
8851   if (op1 == UNKNOWN || op0 == SET)
8852     return 1;
8853
8854   else if (op0 == UNKNOWN)
8855     op0 = op1, const0 = const1;
8856
8857   else if (op0 == op1)
8858     {
8859       switch (op0)
8860         {
8861         case AND:
8862           const0 &= const1;
8863           break;
8864         case IOR:
8865           const0 |= const1;
8866           break;
8867         case XOR:
8868           const0 ^= const1;
8869           break;
8870         case PLUS:
8871           const0 += const1;
8872           break;
8873         case NEG:
8874           op0 = UNKNOWN;
8875           break;
8876         default:
8877           break;
8878         }
8879     }
8880
8881   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
8882   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8883     return 0;
8884
8885   /* If the two constants aren't the same, we can't do anything.  The
8886      remaining six cases can all be done.  */
8887   else if (const0 != const1)
8888     return 0;
8889
8890   else
8891     switch (op0)
8892       {
8893       case IOR:
8894         if (op1 == AND)
8895           /* (a & b) | b == b */
8896           op0 = SET;
8897         else /* op1 == XOR */
8898           /* (a ^ b) | b == a | b */
8899           {;}
8900         break;
8901
8902       case XOR:
8903         if (op1 == AND)
8904           /* (a & b) ^ b == (~a) & b */
8905           op0 = AND, *pcomp_p = 1;
8906         else /* op1 == IOR */
8907           /* (a | b) ^ b == a & ~b */
8908           op0 = AND, const0 = ~const0;
8909         break;
8910
8911       case AND:
8912         if (op1 == IOR)
8913           /* (a | b) & b == b */
8914         op0 = SET;
8915         else /* op1 == XOR */
8916           /* (a ^ b) & b) == (~a) & b */
8917           *pcomp_p = 1;
8918         break;
8919       default:
8920         break;
8921       }
8922
8923   /* Check for NO-OP cases.  */
8924   const0 &= GET_MODE_MASK (mode);
8925   if (const0 == 0
8926       && (op0 == IOR || op0 == XOR || op0 == PLUS))
8927     op0 = UNKNOWN;
8928   else if (const0 == 0 && op0 == AND)
8929     op0 = SET;
8930   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8931            && op0 == AND)
8932     op0 = UNKNOWN;
8933
8934   /* ??? Slightly redundant with the above mask, but not entirely.
8935      Moving this above means we'd have to sign-extend the mode mask
8936      for the final test.  */
8937   const0 = trunc_int_for_mode (const0, mode);
8938
8939   *pop0 = op0;
8940   *pconst0 = const0;
8941
8942   return 1;
8943 }
8944 \f
8945 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
8946    The result of the shift is RESULT_MODE.  Return NULL_RTX if we cannot
8947    simplify it.  Otherwise, return a simplified value.
8948
8949    The shift is normally computed in the widest mode we find in VAROP, as
8950    long as it isn't a different number of words than RESULT_MODE.  Exceptions
8951    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
8952
8953 static rtx
8954 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8955                         rtx varop, int orig_count)
8956 {
8957   enum rtx_code orig_code = code;
8958   rtx orig_varop = varop;
8959   int count;
8960   enum machine_mode mode = result_mode;
8961   enum machine_mode shift_mode, tmode;
8962   unsigned int mode_words
8963     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8964   /* We form (outer_op (code varop count) (outer_const)).  */
8965   enum rtx_code outer_op = UNKNOWN;
8966   HOST_WIDE_INT outer_const = 0;
8967   int complement_p = 0;
8968   rtx new, x;
8969
8970   /* Make sure and truncate the "natural" shift on the way in.  We don't
8971      want to do this inside the loop as it makes it more difficult to
8972      combine shifts.  */
8973   if (SHIFT_COUNT_TRUNCATED)
8974     orig_count &= GET_MODE_BITSIZE (mode) - 1;
8975
8976   /* If we were given an invalid count, don't do anything except exactly
8977      what was requested.  */
8978
8979   if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8980     return NULL_RTX;
8981
8982   count = orig_count;
8983
8984   /* Unless one of the branches of the `if' in this loop does a `continue',
8985      we will `break' the loop after the `if'.  */
8986
8987   while (count != 0)
8988     {
8989       /* If we have an operand of (clobber (const_int 0)), fail.  */
8990       if (GET_CODE (varop) == CLOBBER)
8991         return NULL_RTX;
8992
8993       /* If we discovered we had to complement VAROP, leave.  Making a NOT
8994          here would cause an infinite loop.  */
8995       if (complement_p)
8996         break;
8997
8998       /* Convert ROTATERT to ROTATE.  */
8999       if (code == ROTATERT)
9000         {
9001           unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9002           code = ROTATE;
9003           if (VECTOR_MODE_P (result_mode))
9004             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9005           else
9006             count = bitsize - count;
9007         }
9008
9009       /* We need to determine what mode we will do the shift in.  If the
9010          shift is a right shift or a ROTATE, we must always do it in the mode
9011          it was originally done in.  Otherwise, we can do it in MODE, the
9012          widest mode encountered.  */
9013       shift_mode
9014         = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9015            ? result_mode : mode);
9016
9017       /* Handle cases where the count is greater than the size of the mode
9018          minus 1.  For ASHIFT, use the size minus one as the count (this can
9019          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
9020          take the count modulo the size.  For other shifts, the result is
9021          zero.
9022
9023          Since these shifts are being produced by the compiler by combining
9024          multiple operations, each of which are defined, we know what the
9025          result is supposed to be.  */
9026
9027       if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9028         {
9029           if (code == ASHIFTRT)
9030             count = GET_MODE_BITSIZE (shift_mode) - 1;
9031           else if (code == ROTATE || code == ROTATERT)
9032             count %= GET_MODE_BITSIZE (shift_mode);
9033           else
9034             {
9035               /* We can't simply return zero because there may be an
9036                  outer op.  */
9037               varop = const0_rtx;
9038               count = 0;
9039               break;
9040             }
9041         }
9042
9043       /* An arithmetic right shift of a quantity known to be -1 or 0
9044          is a no-op.  */
9045       if (code == ASHIFTRT
9046           && (num_sign_bit_copies (varop, shift_mode)
9047               == GET_MODE_BITSIZE (shift_mode)))
9048         {
9049           count = 0;
9050           break;
9051         }
9052
9053       /* If we are doing an arithmetic right shift and discarding all but
9054          the sign bit copies, this is equivalent to doing a shift by the
9055          bitsize minus one.  Convert it into that shift because it will often
9056          allow other simplifications.  */
9057
9058       if (code == ASHIFTRT
9059           && (count + num_sign_bit_copies (varop, shift_mode)
9060               >= GET_MODE_BITSIZE (shift_mode)))
9061         count = GET_MODE_BITSIZE (shift_mode) - 1;
9062
9063       /* We simplify the tests below and elsewhere by converting
9064          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9065          `make_compound_operation' will convert it to an ASHIFTRT for
9066          those machines (such as VAX) that don't have an LSHIFTRT.  */
9067       if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9068           && code == ASHIFTRT
9069           && ((nonzero_bits (varop, shift_mode)
9070                & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9071               == 0))
9072         code = LSHIFTRT;
9073
9074       if (((code == LSHIFTRT
9075             && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9076             && !(nonzero_bits (varop, shift_mode) >> count))
9077            || (code == ASHIFT
9078                && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9079                && !((nonzero_bits (varop, shift_mode) << count)
9080                     & GET_MODE_MASK (shift_mode))))
9081           && !side_effects_p (varop))
9082         varop = const0_rtx;
9083
9084       switch (GET_CODE (varop))
9085         {
9086         case SIGN_EXTEND:
9087         case ZERO_EXTEND:
9088         case SIGN_EXTRACT:
9089         case ZERO_EXTRACT:
9090           new = expand_compound_operation (varop);
9091           if (new != varop)
9092             {
9093               varop = new;
9094               continue;
9095             }
9096           break;
9097
9098         case MEM:
9099           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9100              minus the width of a smaller mode, we can do this with a
9101              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
9102           if ((code == ASHIFTRT || code == LSHIFTRT)
9103               && ! mode_dependent_address_p (XEXP (varop, 0))
9104               && ! MEM_VOLATILE_P (varop)
9105               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9106                                          MODE_INT, 1)) != BLKmode)
9107             {
9108               new = adjust_address_nv (varop, tmode,
9109                                        BYTES_BIG_ENDIAN ? 0
9110                                        : count / BITS_PER_UNIT);
9111
9112               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9113                                      : ZERO_EXTEND, mode, new);
9114               count = 0;
9115               continue;
9116             }
9117           break;
9118
9119         case SUBREG:
9120           /* If VAROP is a SUBREG, strip it as long as the inner operand has
9121              the same number of words as what we've seen so far.  Then store
9122              the widest mode in MODE.  */
9123           if (subreg_lowpart_p (varop)
9124               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9125                   > GET_MODE_SIZE (GET_MODE (varop)))
9126               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9127                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9128                  == mode_words)
9129             {
9130               varop = SUBREG_REG (varop);
9131               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9132                 mode = GET_MODE (varop);
9133               continue;
9134             }
9135           break;
9136
9137         case MULT:
9138           /* Some machines use MULT instead of ASHIFT because MULT
9139              is cheaper.  But it is still better on those machines to
9140              merge two shifts into one.  */
9141           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9142               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9143             {
9144               varop
9145                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9146                                        XEXP (varop, 0),
9147                                        GEN_INT (exact_log2 (
9148                                                 INTVAL (XEXP (varop, 1)))));
9149               continue;
9150             }
9151           break;
9152
9153         case UDIV:
9154           /* Similar, for when divides are cheaper.  */
9155           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9156               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9157             {
9158               varop
9159                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9160                                        XEXP (varop, 0),
9161                                        GEN_INT (exact_log2 (
9162                                                 INTVAL (XEXP (varop, 1)))));
9163               continue;
9164             }
9165           break;
9166
9167         case ASHIFTRT:
9168           /* If we are extracting just the sign bit of an arithmetic
9169              right shift, that shift is not needed.  However, the sign
9170              bit of a wider mode may be different from what would be
9171              interpreted as the sign bit in a narrower mode, so, if
9172              the result is narrower, don't discard the shift.  */
9173           if (code == LSHIFTRT
9174               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9175               && (GET_MODE_BITSIZE (result_mode)
9176                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
9177             {
9178               varop = XEXP (varop, 0);
9179               continue;
9180             }
9181
9182           /* ... fall through ...  */
9183
9184         case LSHIFTRT:
9185         case ASHIFT:
9186         case ROTATE:
9187           /* Here we have two nested shifts.  The result is usually the
9188              AND of a new shift with a mask.  We compute the result below.  */
9189           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9190               && INTVAL (XEXP (varop, 1)) >= 0
9191               && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9192               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9193               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9194               && !VECTOR_MODE_P (result_mode))
9195             {
9196               enum rtx_code first_code = GET_CODE (varop);
9197               unsigned int first_count = INTVAL (XEXP (varop, 1));
9198               unsigned HOST_WIDE_INT mask;
9199               rtx mask_rtx;
9200
9201               /* We have one common special case.  We can't do any merging if
9202                  the inner code is an ASHIFTRT of a smaller mode.  However, if
9203                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9204                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9205                  we can convert it to
9206                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9207                  This simplifies certain SIGN_EXTEND operations.  */
9208               if (code == ASHIFT && first_code == ASHIFTRT
9209                   && count == (GET_MODE_BITSIZE (result_mode)
9210                                - GET_MODE_BITSIZE (GET_MODE (varop))))
9211                 {
9212                   /* C3 has the low-order C1 bits zero.  */
9213
9214                   mask = (GET_MODE_MASK (mode)
9215                           & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9216
9217                   varop = simplify_and_const_int (NULL_RTX, result_mode,
9218                                                   XEXP (varop, 0), mask);
9219                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9220                                                 varop, count);
9221                   count = first_count;
9222                   code = ASHIFTRT;
9223                   continue;
9224                 }
9225
9226               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9227                  than C1 high-order bits equal to the sign bit, we can convert
9228                  this to either an ASHIFT or an ASHIFTRT depending on the
9229                  two counts.
9230
9231                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
9232
9233               if (code == ASHIFTRT && first_code == ASHIFT
9234                   && GET_MODE (varop) == shift_mode
9235                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9236                       > first_count))
9237                 {
9238                   varop = XEXP (varop, 0);
9239                   count -= first_count;
9240                   if (count < 0)
9241                     {
9242                       count = -count;
9243                       code = ASHIFT;
9244                     }
9245
9246                   continue;
9247                 }
9248
9249               /* There are some cases we can't do.  If CODE is ASHIFTRT,
9250                  we can only do this if FIRST_CODE is also ASHIFTRT.
9251
9252                  We can't do the case when CODE is ROTATE and FIRST_CODE is
9253                  ASHIFTRT.
9254
9255                  If the mode of this shift is not the mode of the outer shift,
9256                  we can't do this if either shift is a right shift or ROTATE.
9257
9258                  Finally, we can't do any of these if the mode is too wide
9259                  unless the codes are the same.
9260
9261                  Handle the case where the shift codes are the same
9262                  first.  */
9263
9264               if (code == first_code)
9265                 {
9266                   if (GET_MODE (varop) != result_mode
9267                       && (code == ASHIFTRT || code == LSHIFTRT
9268                           || code == ROTATE))
9269                     break;
9270
9271                   count += first_count;
9272                   varop = XEXP (varop, 0);
9273                   continue;
9274                 }
9275
9276               if (code == ASHIFTRT
9277                   || (code == ROTATE && first_code == ASHIFTRT)
9278                   || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9279                   || (GET_MODE (varop) != result_mode
9280                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
9281                           || first_code == ROTATE
9282                           || code == ROTATE)))
9283                 break;
9284
9285               /* To compute the mask to apply after the shift, shift the
9286                  nonzero bits of the inner shift the same way the
9287                  outer shift will.  */
9288
9289               mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9290
9291               mask_rtx
9292                 = simplify_const_binary_operation (code, result_mode, mask_rtx,
9293                                                    GEN_INT (count));
9294
9295               /* Give up if we can't compute an outer operation to use.  */
9296               if (mask_rtx == 0
9297                   || GET_CODE (mask_rtx) != CONST_INT
9298                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
9299                                         INTVAL (mask_rtx),
9300                                         result_mode, &complement_p))
9301                 break;
9302
9303               /* If the shifts are in the same direction, we add the
9304                  counts.  Otherwise, we subtract them.  */
9305               if ((code == ASHIFTRT || code == LSHIFTRT)
9306                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9307                 count += first_count;
9308               else
9309                 count -= first_count;
9310
9311               /* If COUNT is positive, the new shift is usually CODE,
9312                  except for the two exceptions below, in which case it is
9313                  FIRST_CODE.  If the count is negative, FIRST_CODE should
9314                  always be used  */
9315               if (count > 0
9316                   && ((first_code == ROTATE && code == ASHIFT)
9317                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
9318                 code = first_code;
9319               else if (count < 0)
9320                 code = first_code, count = -count;
9321
9322               varop = XEXP (varop, 0);
9323               continue;
9324             }
9325
9326           /* If we have (A << B << C) for any shift, we can convert this to
9327              (A << C << B).  This wins if A is a constant.  Only try this if
9328              B is not a constant.  */
9329
9330           else if (GET_CODE (varop) == code
9331                    && GET_CODE (XEXP (varop, 0)) == CONST_INT
9332                    && GET_CODE (XEXP (varop, 1)) != CONST_INT)
9333             {
9334               rtx new = simplify_const_binary_operation (code, mode,
9335                                                          XEXP (varop, 0),
9336                                                          GEN_INT (count));
9337               varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9338               count = 0;
9339               continue;
9340             }
9341           break;
9342
9343         case NOT:
9344           /* Make this fit the case below.  */
9345           varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9346                                GEN_INT (GET_MODE_MASK (mode)));
9347           continue;
9348
9349         case IOR:
9350         case AND:
9351         case XOR:
9352           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9353              with C the size of VAROP - 1 and the shift is logical if
9354              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9355              we have an (le X 0) operation.   If we have an arithmetic shift
9356              and STORE_FLAG_VALUE is 1 or we have a logical shift with
9357              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
9358
9359           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9360               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9361               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9362               && (code == LSHIFTRT || code == ASHIFTRT)
9363               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9364               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9365             {
9366               count = 0;
9367               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9368                                   const0_rtx);
9369
9370               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9371                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9372
9373               continue;
9374             }
9375
9376           /* If we have (shift (logical)), move the logical to the outside
9377              to allow it to possibly combine with another logical and the
9378              shift to combine with another shift.  This also canonicalizes to
9379              what a ZERO_EXTRACT looks like.  Also, some machines have
9380              (and (shift)) insns.  */
9381
9382           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9383               /* We can't do this if we have (ashiftrt (xor))  and the
9384                  constant has its sign bit set in shift_mode.  */
9385               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9386                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9387                                               shift_mode))
9388               && (new = simplify_const_binary_operation (code, result_mode,
9389                                                          XEXP (varop, 1),
9390                                                          GEN_INT (count))) != 0
9391               && GET_CODE (new) == CONST_INT
9392               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9393                                   INTVAL (new), result_mode, &complement_p))
9394             {
9395               varop = XEXP (varop, 0);
9396               continue;
9397             }
9398
9399           /* If we can't do that, try to simplify the shift in each arm of the
9400              logical expression, make a new logical expression, and apply
9401              the inverse distributive law.  This also can't be done
9402              for some (ashiftrt (xor)).  */
9403           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9404              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9405                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9406                                              shift_mode)))
9407             {
9408               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9409                                               XEXP (varop, 0), count);
9410               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9411                                               XEXP (varop, 1), count);
9412
9413               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9414                                            lhs, rhs);
9415               varop = apply_distributive_law (varop);
9416
9417               count = 0;
9418               continue;
9419             }
9420           break;
9421
9422         case EQ:
9423           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9424              says that the sign bit can be tested, FOO has mode MODE, C is
9425              GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9426              that may be nonzero.  */
9427           if (code == LSHIFTRT
9428               && XEXP (varop, 1) == const0_rtx
9429               && GET_MODE (XEXP (varop, 0)) == result_mode
9430               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9431               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9432               && STORE_FLAG_VALUE == -1
9433               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9434               && merge_outer_ops (&outer_op, &outer_const, XOR,
9435                                   (HOST_WIDE_INT) 1, result_mode,
9436                                   &complement_p))
9437             {
9438               varop = XEXP (varop, 0);
9439               count = 0;
9440               continue;
9441             }
9442           break;
9443
9444         case NEG:
9445           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9446              than the number of bits in the mode is equivalent to A.  */
9447           if (code == LSHIFTRT
9448               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9449               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9450             {
9451               varop = XEXP (varop, 0);
9452               count = 0;
9453               continue;
9454             }
9455
9456           /* NEG commutes with ASHIFT since it is multiplication.  Move the
9457              NEG outside to allow shifts to combine.  */
9458           if (code == ASHIFT
9459               && merge_outer_ops (&outer_op, &outer_const, NEG,
9460                                   (HOST_WIDE_INT) 0, result_mode,
9461                                   &complement_p))
9462             {
9463               varop = XEXP (varop, 0);
9464               continue;
9465             }
9466           break;
9467
9468         case PLUS:
9469           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9470              is one less than the number of bits in the mode is
9471              equivalent to (xor A 1).  */
9472           if (code == LSHIFTRT
9473               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9474               && XEXP (varop, 1) == constm1_rtx
9475               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9476               && merge_outer_ops (&outer_op, &outer_const, XOR,
9477                                   (HOST_WIDE_INT) 1, result_mode,
9478                                   &complement_p))
9479             {
9480               count = 0;
9481               varop = XEXP (varop, 0);
9482               continue;
9483             }
9484
9485           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9486              that might be nonzero in BAR are those being shifted out and those
9487              bits are known zero in FOO, we can replace the PLUS with FOO.
9488              Similarly in the other operand order.  This code occurs when
9489              we are computing the size of a variable-size array.  */
9490
9491           if ((code == ASHIFTRT || code == LSHIFTRT)
9492               && count < HOST_BITS_PER_WIDE_INT
9493               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9494               && (nonzero_bits (XEXP (varop, 1), result_mode)
9495                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9496             {
9497               varop = XEXP (varop, 0);
9498               continue;
9499             }
9500           else if ((code == ASHIFTRT || code == LSHIFTRT)
9501                    && count < HOST_BITS_PER_WIDE_INT
9502                    && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9503                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9504                             >> count)
9505                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9506                             & nonzero_bits (XEXP (varop, 1),
9507                                                  result_mode)))
9508             {
9509               varop = XEXP (varop, 1);
9510               continue;
9511             }
9512
9513           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
9514           if (code == ASHIFT
9515               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9516               && (new = simplify_const_binary_operation (ASHIFT, result_mode,
9517                                                          XEXP (varop, 1),
9518                                                          GEN_INT (count))) != 0
9519               && GET_CODE (new) == CONST_INT
9520               && merge_outer_ops (&outer_op, &outer_const, PLUS,
9521                                   INTVAL (new), result_mode, &complement_p))
9522             {
9523               varop = XEXP (varop, 0);
9524               continue;
9525             }
9526
9527           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9528              signbit', and attempt to change the PLUS to an XOR and move it to
9529              the outer operation as is done above in the AND/IOR/XOR case
9530              leg for shift(logical). See details in logical handling above
9531              for reasoning in doing so.  */
9532           if (code == LSHIFTRT
9533               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9534               && mode_signbit_p (result_mode, XEXP (varop, 1))
9535               && (new = simplify_const_binary_operation (code, result_mode,
9536                                                          XEXP (varop, 1),
9537                                                          GEN_INT (count))) != 0
9538               && GET_CODE (new) == CONST_INT
9539               && merge_outer_ops (&outer_op, &outer_const, XOR,
9540                                   INTVAL (new), result_mode, &complement_p))
9541             {
9542               varop = XEXP (varop, 0);
9543               continue;
9544             }
9545
9546           break;
9547
9548         case MINUS:
9549           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9550              with C the size of VAROP - 1 and the shift is logical if
9551              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9552              we have a (gt X 0) operation.  If the shift is arithmetic with
9553              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9554              we have a (neg (gt X 0)) operation.  */
9555
9556           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9557               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9558               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9559               && (code == LSHIFTRT || code == ASHIFTRT)
9560               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9561               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9562               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9563             {
9564               count = 0;
9565               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9566                                   const0_rtx);
9567
9568               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9569                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9570
9571               continue;
9572             }
9573           break;
9574
9575         case TRUNCATE:
9576           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9577              if the truncate does not affect the value.  */
9578           if (code == LSHIFTRT
9579               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9580               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9581               && (INTVAL (XEXP (XEXP (varop, 0), 1))
9582                   >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9583                       - GET_MODE_BITSIZE (GET_MODE (varop)))))
9584             {
9585               rtx varop_inner = XEXP (varop, 0);
9586
9587               varop_inner
9588                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9589                                     XEXP (varop_inner, 0),
9590                                     GEN_INT
9591                                     (count + INTVAL (XEXP (varop_inner, 1))));
9592               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9593               count = 0;
9594               continue;
9595             }
9596           break;
9597
9598         default:
9599           break;
9600         }
9601
9602       break;
9603     }
9604
9605   /* We need to determine what mode to do the shift in.  If the shift is
9606      a right shift or ROTATE, we must always do it in the mode it was
9607      originally done in.  Otherwise, we can do it in MODE, the widest mode
9608      encountered.  The code we care about is that of the shift that will
9609      actually be done, not the shift that was originally requested.  */
9610   shift_mode
9611     = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9612        ? result_mode : mode);
9613
9614   /* We have now finished analyzing the shift.  The result should be
9615      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
9616      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9617      to the result of the shift.  OUTER_CONST is the relevant constant,
9618      but we must turn off all bits turned off in the shift.  */
9619
9620   if (outer_op == UNKNOWN
9621       && orig_code == code && orig_count == count
9622       && varop == orig_varop
9623       && shift_mode == GET_MODE (varop))
9624     return NULL_RTX;
9625
9626   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
9627   varop = gen_lowpart (shift_mode, varop);
9628   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9629     return NULL_RTX;
9630
9631   /* If we have an outer operation and we just made a shift, it is
9632      possible that we could have simplified the shift were it not
9633      for the outer operation.  So try to do the simplification
9634      recursively.  */
9635
9636   if (outer_op != UNKNOWN)
9637     x = simplify_shift_const_1 (code, shift_mode, varop, count);
9638   else
9639     x = NULL_RTX;
9640
9641   if (x == NULL_RTX)
9642     x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9643
9644   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9645      turn off all the bits that the shift would have turned off.  */
9646   if (orig_code == LSHIFTRT && result_mode != shift_mode)
9647     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9648                                 GET_MODE_MASK (result_mode) >> orig_count);
9649
9650   /* Do the remainder of the processing in RESULT_MODE.  */
9651   x = gen_lowpart_or_truncate (result_mode, x);
9652
9653   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9654      operation.  */
9655   if (complement_p)
9656     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9657
9658   if (outer_op != UNKNOWN)
9659     {
9660       if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9661         outer_const = trunc_int_for_mode (outer_const, result_mode);
9662
9663       if (outer_op == AND)
9664         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9665       else if (outer_op == SET)
9666         {
9667           /* This means that we have determined that the result is
9668              equivalent to a constant.  This should be rare.  */
9669           if (!side_effects_p (x))
9670             x = GEN_INT (outer_const);
9671         }
9672       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9673         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9674       else
9675         x = simplify_gen_binary (outer_op, result_mode, x,
9676                                  GEN_INT (outer_const));
9677     }
9678
9679   return x;
9680 }
9681
9682 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
9683    The result of the shift is RESULT_MODE.  If we cannot simplify it,
9684    return X or, if it is NULL, synthesize the expression with
9685    simplify_gen_binary.  Otherwise, return a simplified value.
9686
9687    The shift is normally computed in the widest mode we find in VAROP, as
9688    long as it isn't a different number of words than RESULT_MODE.  Exceptions
9689    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
9690
9691 static rtx
9692 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9693                       rtx varop, int count)
9694 {
9695   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9696   if (tem)
9697     return tem;
9698
9699   if (!x)
9700     x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9701   if (GET_MODE (x) != result_mode)
9702     x = gen_lowpart (result_mode, x);
9703   return x;
9704 }
9705
9706 \f
9707 /* Like recog, but we receive the address of a pointer to a new pattern.
9708    We try to match the rtx that the pointer points to.
9709    If that fails, we may try to modify or replace the pattern,
9710    storing the replacement into the same pointer object.
9711
9712    Modifications include deletion or addition of CLOBBERs.
9713
9714    PNOTES is a pointer to a location where any REG_UNUSED notes added for
9715    the CLOBBERs are placed.
9716
9717    The value is the final insn code from the pattern ultimately matched,
9718    or -1.  */
9719
9720 static int
9721 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9722 {
9723   rtx pat = *pnewpat;
9724   int insn_code_number;
9725   int num_clobbers_to_add = 0;
9726   int i;
9727   rtx notes = 0;
9728   rtx old_notes, old_pat;
9729
9730   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9731      we use to indicate that something didn't match.  If we find such a
9732      thing, force rejection.  */
9733   if (GET_CODE (pat) == PARALLEL)
9734     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9735       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9736           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9737         return -1;
9738
9739   old_pat = PATTERN (insn);
9740   old_notes = REG_NOTES (insn);
9741   PATTERN (insn) = pat;
9742   REG_NOTES (insn) = 0;
9743
9744   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9745   if (dump_file && (dump_flags & TDF_DETAILS))
9746     {
9747       if (insn_code_number < 0)
9748         fputs ("Failed to match this instruction:\n", dump_file);
9749       else
9750         fputs ("Successfully matched this instruction:\n", dump_file);
9751       print_rtl_single (dump_file, pat);
9752     }
9753
9754   /* If it isn't, there is the possibility that we previously had an insn
9755      that clobbered some register as a side effect, but the combined
9756      insn doesn't need to do that.  So try once more without the clobbers
9757      unless this represents an ASM insn.  */
9758
9759   if (insn_code_number < 0 && ! check_asm_operands (pat)
9760       && GET_CODE (pat) == PARALLEL)
9761     {
9762       int pos;
9763
9764       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9765         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9766           {
9767             if (i != pos)
9768               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9769             pos++;
9770           }
9771
9772       SUBST_INT (XVECLEN (pat, 0), pos);
9773
9774       if (pos == 1)
9775         pat = XVECEXP (pat, 0, 0);
9776
9777       PATTERN (insn) = pat;
9778       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9779       if (dump_file && (dump_flags & TDF_DETAILS))
9780         {
9781           if (insn_code_number < 0)
9782             fputs ("Failed to match this instruction:\n", dump_file);
9783           else
9784             fputs ("Successfully matched this instruction:\n", dump_file);
9785           print_rtl_single (dump_file, pat);
9786         }
9787     }
9788   PATTERN (insn) = old_pat;
9789   REG_NOTES (insn) = old_notes;
9790
9791   /* Recognize all noop sets, these will be killed by followup pass.  */
9792   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9793     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9794
9795   /* If we had any clobbers to add, make a new pattern than contains
9796      them.  Then check to make sure that all of them are dead.  */
9797   if (num_clobbers_to_add)
9798     {
9799       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9800                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
9801                                                   ? (XVECLEN (pat, 0)
9802                                                      + num_clobbers_to_add)
9803                                                   : num_clobbers_to_add + 1));
9804
9805       if (GET_CODE (pat) == PARALLEL)
9806         for (i = 0; i < XVECLEN (pat, 0); i++)
9807           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9808       else
9809         XVECEXP (newpat, 0, 0) = pat;
9810
9811       add_clobbers (newpat, insn_code_number);
9812
9813       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9814            i < XVECLEN (newpat, 0); i++)
9815         {
9816           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9817               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9818             return -1;
9819           if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
9820             {
9821               gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
9822               notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9823                                          XEXP (XVECEXP (newpat, 0, i), 0), notes);
9824             }
9825         }
9826       pat = newpat;
9827     }
9828
9829   *pnewpat = pat;
9830   *pnotes = notes;
9831
9832   return insn_code_number;
9833 }
9834 \f
9835 /* Like gen_lowpart_general but for use by combine.  In combine it
9836    is not possible to create any new pseudoregs.  However, it is
9837    safe to create invalid memory addresses, because combine will
9838    try to recognize them and all they will do is make the combine
9839    attempt fail.
9840
9841    If for some reason this cannot do its job, an rtx
9842    (clobber (const_int 0)) is returned.
9843    An insn containing that will not be recognized.  */
9844
9845 static rtx
9846 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9847 {
9848   enum machine_mode imode = GET_MODE (x);
9849   unsigned int osize = GET_MODE_SIZE (omode);
9850   unsigned int isize = GET_MODE_SIZE (imode);
9851   rtx result;
9852
9853   if (omode == imode)
9854     return x;
9855
9856   /* Return identity if this is a CONST or symbolic reference.  */
9857   if (omode == Pmode
9858       && (GET_CODE (x) == CONST
9859           || GET_CODE (x) == SYMBOL_REF
9860           || GET_CODE (x) == LABEL_REF))
9861     return x;
9862
9863   /* We can only support MODE being wider than a word if X is a
9864      constant integer or has a mode the same size.  */
9865   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9866       && ! ((imode == VOIDmode
9867              && (GET_CODE (x) == CONST_INT
9868                  || GET_CODE (x) == CONST_DOUBLE))
9869             || isize == osize))
9870     goto fail;
9871
9872   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
9873      won't know what to do.  So we will strip off the SUBREG here and
9874      process normally.  */
9875   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9876     {
9877       x = SUBREG_REG (x);
9878
9879       /* For use in case we fall down into the address adjustments
9880          further below, we need to adjust the known mode and size of
9881          x; imode and isize, since we just adjusted x.  */
9882       imode = GET_MODE (x);
9883
9884       if (imode == omode)
9885         return x;
9886
9887       isize = GET_MODE_SIZE (imode);
9888     }
9889
9890   result = gen_lowpart_common (omode, x);
9891
9892   if (result)
9893     return result;
9894
9895   if (MEM_P (x))
9896     {
9897       int offset = 0;
9898
9899       /* Refuse to work on a volatile memory ref or one with a mode-dependent
9900          address.  */
9901       if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9902         goto fail;
9903
9904       /* If we want to refer to something bigger than the original memref,
9905          generate a paradoxical subreg instead.  That will force a reload
9906          of the original memref X.  */
9907       if (isize < osize)
9908         return gen_rtx_SUBREG (omode, x, 0);
9909
9910       if (WORDS_BIG_ENDIAN)
9911         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9912
9913       /* Adjust the address so that the address-after-the-data is
9914          unchanged.  */
9915       if (BYTES_BIG_ENDIAN)
9916         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9917
9918       return adjust_address_nv (x, omode, offset);
9919     }
9920
9921   /* If X is a comparison operator, rewrite it in a new mode.  This
9922      probably won't match, but may allow further simplifications.  */
9923   else if (COMPARISON_P (x))
9924     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9925
9926   /* If we couldn't simplify X any other way, just enclose it in a
9927      SUBREG.  Normally, this SUBREG won't match, but some patterns may
9928      include an explicit SUBREG or we may simplify it further in combine.  */
9929   else
9930     {
9931       int offset = 0;
9932       rtx res;
9933
9934       offset = subreg_lowpart_offset (omode, imode);
9935       if (imode == VOIDmode)
9936         {
9937           imode = int_mode_for_mode (omode);
9938           x = gen_lowpart_common (imode, x);
9939           if (x == NULL)
9940             goto fail;
9941         }
9942       res = simplify_gen_subreg (omode, x, imode, offset);
9943       if (res)
9944         return res;
9945     }
9946
9947  fail:
9948   return gen_rtx_CLOBBER (imode, const0_rtx);
9949 }
9950 \f
9951 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9952    comparison code that will be tested.
9953
9954    The result is a possibly different comparison code to use.  *POP0 and
9955    *POP1 may be updated.
9956
9957    It is possible that we might detect that a comparison is either always
9958    true or always false.  However, we do not perform general constant
9959    folding in combine, so this knowledge isn't useful.  Such tautologies
9960    should have been detected earlier.  Hence we ignore all such cases.  */
9961
9962 static enum rtx_code
9963 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9964 {
9965   rtx op0 = *pop0;
9966   rtx op1 = *pop1;
9967   rtx tem, tem1;
9968   int i;
9969   enum machine_mode mode, tmode;
9970
9971   /* Try a few ways of applying the same transformation to both operands.  */
9972   while (1)
9973     {
9974 #ifndef WORD_REGISTER_OPERATIONS
9975       /* The test below this one won't handle SIGN_EXTENDs on these machines,
9976          so check specially.  */
9977       if (code != GTU && code != GEU && code != LTU && code != LEU
9978           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9979           && GET_CODE (XEXP (op0, 0)) == ASHIFT
9980           && GET_CODE (XEXP (op1, 0)) == ASHIFT
9981           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9982           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9983           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9984               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9985           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9986           && XEXP (op0, 1) == XEXP (op1, 1)
9987           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9988           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9989           && (INTVAL (XEXP (op0, 1))
9990               == (GET_MODE_BITSIZE (GET_MODE (op0))
9991                   - (GET_MODE_BITSIZE
9992                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9993         {
9994           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9995           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9996         }
9997 #endif
9998
9999       /* If both operands are the same constant shift, see if we can ignore the
10000          shift.  We can if the shift is a rotate or if the bits shifted out of
10001          this shift are known to be zero for both inputs and if the type of
10002          comparison is compatible with the shift.  */
10003       if (GET_CODE (op0) == GET_CODE (op1)
10004           && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10005           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10006               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10007                   && (code != GT && code != LT && code != GE && code != LE))
10008               || (GET_CODE (op0) == ASHIFTRT
10009                   && (code != GTU && code != LTU
10010                       && code != GEU && code != LEU)))
10011           && GET_CODE (XEXP (op0, 1)) == CONST_INT
10012           && INTVAL (XEXP (op0, 1)) >= 0
10013           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10014           && XEXP (op0, 1) == XEXP (op1, 1))
10015         {
10016           enum machine_mode mode = GET_MODE (op0);
10017           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10018           int shift_count = INTVAL (XEXP (op0, 1));
10019
10020           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10021             mask &= (mask >> shift_count) << shift_count;
10022           else if (GET_CODE (op0) == ASHIFT)
10023             mask = (mask & (mask << shift_count)) >> shift_count;
10024
10025           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10026               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10027             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10028           else
10029             break;
10030         }
10031
10032       /* If both operands are AND's of a paradoxical SUBREG by constant, the
10033          SUBREGs are of the same mode, and, in both cases, the AND would
10034          be redundant if the comparison was done in the narrower mode,
10035          do the comparison in the narrower mode (e.g., we are AND'ing with 1
10036          and the operand's possibly nonzero bits are 0xffffff01; in that case
10037          if we only care about QImode, we don't need the AND).  This case
10038          occurs if the output mode of an scc insn is not SImode and
10039          STORE_FLAG_VALUE == 1 (e.g., the 386).
10040
10041          Similarly, check for a case where the AND's are ZERO_EXTEND
10042          operations from some narrower mode even though a SUBREG is not
10043          present.  */
10044
10045       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10046                && GET_CODE (XEXP (op0, 1)) == CONST_INT
10047                && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10048         {
10049           rtx inner_op0 = XEXP (op0, 0);
10050           rtx inner_op1 = XEXP (op1, 0);
10051           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10052           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10053           int changed = 0;
10054
10055           if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10056               && (GET_MODE_SIZE (GET_MODE (inner_op0))
10057                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10058               && (GET_MODE (SUBREG_REG (inner_op0))
10059                   == GET_MODE (SUBREG_REG (inner_op1)))
10060               && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10061                   <= HOST_BITS_PER_WIDE_INT)
10062               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10063                                              GET_MODE (SUBREG_REG (inner_op0)))))
10064               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10065                                              GET_MODE (SUBREG_REG (inner_op1))))))
10066             {
10067               op0 = SUBREG_REG (inner_op0);
10068               op1 = SUBREG_REG (inner_op1);
10069
10070               /* The resulting comparison is always unsigned since we masked
10071                  off the original sign bit.  */
10072               code = unsigned_condition (code);
10073
10074               changed = 1;
10075             }
10076
10077           else if (c0 == c1)
10078             for (tmode = GET_CLASS_NARROWEST_MODE
10079                  (GET_MODE_CLASS (GET_MODE (op0)));
10080                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10081               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10082                 {
10083                   op0 = gen_lowpart (tmode, inner_op0);
10084                   op1 = gen_lowpart (tmode, inner_op1);
10085                   code = unsigned_condition (code);
10086                   changed = 1;
10087                   break;
10088                 }
10089
10090           if (! changed)
10091             break;
10092         }
10093
10094       /* If both operands are NOT, we can strip off the outer operation
10095          and adjust the comparison code for swapped operands; similarly for
10096          NEG, except that this must be an equality comparison.  */
10097       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10098                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10099                    && (code == EQ || code == NE)))
10100         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10101
10102       else
10103         break;
10104     }
10105
10106   /* If the first operand is a constant, swap the operands and adjust the
10107      comparison code appropriately, but don't do this if the second operand
10108      is already a constant integer.  */
10109   if (swap_commutative_operands_p (op0, op1))
10110     {
10111       tem = op0, op0 = op1, op1 = tem;
10112       code = swap_condition (code);
10113     }
10114
10115   /* We now enter a loop during which we will try to simplify the comparison.
10116      For the most part, we only are concerned with comparisons with zero,
10117      but some things may really be comparisons with zero but not start
10118      out looking that way.  */
10119
10120   while (GET_CODE (op1) == CONST_INT)
10121     {
10122       enum machine_mode mode = GET_MODE (op0);
10123       unsigned int mode_width = GET_MODE_BITSIZE (mode);
10124       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10125       int equality_comparison_p;
10126       int sign_bit_comparison_p;
10127       int unsigned_comparison_p;
10128       HOST_WIDE_INT const_op;
10129
10130       /* We only want to handle integral modes.  This catches VOIDmode,
10131          CCmode, and the floating-point modes.  An exception is that we
10132          can handle VOIDmode if OP0 is a COMPARE or a comparison
10133          operation.  */
10134
10135       if (GET_MODE_CLASS (mode) != MODE_INT
10136           && ! (mode == VOIDmode
10137                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10138         break;
10139
10140       /* Get the constant we are comparing against and turn off all bits
10141          not on in our mode.  */
10142       const_op = INTVAL (op1);
10143       if (mode != VOIDmode)
10144         const_op = trunc_int_for_mode (const_op, mode);
10145       op1 = GEN_INT (const_op);
10146
10147       /* If we are comparing against a constant power of two and the value
10148          being compared can only have that single bit nonzero (e.g., it was
10149          `and'ed with that bit), we can replace this with a comparison
10150          with zero.  */
10151       if (const_op
10152           && (code == EQ || code == NE || code == GE || code == GEU
10153               || code == LT || code == LTU)
10154           && mode_width <= HOST_BITS_PER_WIDE_INT
10155           && exact_log2 (const_op) >= 0
10156           && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10157         {
10158           code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10159           op1 = const0_rtx, const_op = 0;
10160         }
10161
10162       /* Similarly, if we are comparing a value known to be either -1 or
10163          0 with -1, change it to the opposite comparison against zero.  */
10164
10165       if (const_op == -1
10166           && (code == EQ || code == NE || code == GT || code == LE
10167               || code == GEU || code == LTU)
10168           && num_sign_bit_copies (op0, mode) == mode_width)
10169         {
10170           code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10171           op1 = const0_rtx, const_op = 0;
10172         }
10173
10174       /* Do some canonicalizations based on the comparison code.  We prefer
10175          comparisons against zero and then prefer equality comparisons.
10176          If we can reduce the size of a constant, we will do that too.  */
10177
10178       switch (code)
10179         {
10180         case LT:
10181           /* < C is equivalent to <= (C - 1) */
10182           if (const_op > 0)
10183             {
10184               const_op -= 1;
10185               op1 = GEN_INT (const_op);
10186               code = LE;
10187               /* ... fall through to LE case below.  */
10188             }
10189           else
10190             break;
10191
10192         case LE:
10193           /* <= C is equivalent to < (C + 1); we do this for C < 0  */
10194           if (const_op < 0)
10195             {
10196               const_op += 1;
10197               op1 = GEN_INT (const_op);
10198               code = LT;
10199             }
10200
10201           /* If we are doing a <= 0 comparison on a value known to have
10202              a zero sign bit, we can replace this with == 0.  */
10203           else if (const_op == 0
10204                    && mode_width <= HOST_BITS_PER_WIDE_INT
10205                    && (nonzero_bits (op0, mode)
10206                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10207             code = EQ;
10208           break;
10209
10210         case GE:
10211           /* >= C is equivalent to > (C - 1).  */
10212           if (const_op > 0)
10213             {
10214               const_op -= 1;
10215               op1 = GEN_INT (const_op);
10216               code = GT;
10217               /* ... fall through to GT below.  */
10218             }
10219           else
10220             break;
10221
10222         case GT:
10223           /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
10224           if (const_op < 0)
10225             {
10226               const_op += 1;
10227               op1 = GEN_INT (const_op);
10228               code = GE;
10229             }
10230
10231           /* If we are doing a > 0 comparison on a value known to have
10232              a zero sign bit, we can replace this with != 0.  */
10233           else if (const_op == 0
10234                    && mode_width <= HOST_BITS_PER_WIDE_INT
10235                    && (nonzero_bits (op0, mode)
10236                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10237             code = NE;
10238           break;
10239
10240         case LTU:
10241           /* < C is equivalent to <= (C - 1).  */
10242           if (const_op > 0)
10243             {
10244               const_op -= 1;
10245               op1 = GEN_INT (const_op);
10246               code = LEU;
10247               /* ... fall through ...  */
10248             }
10249
10250           /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
10251           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10252                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10253             {
10254               const_op = 0, op1 = const0_rtx;
10255               code = GE;
10256               break;
10257             }
10258           else
10259             break;
10260
10261         case LEU:
10262           /* unsigned <= 0 is equivalent to == 0 */
10263           if (const_op == 0)
10264             code = EQ;
10265
10266           /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
10267           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10268                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10269             {
10270               const_op = 0, op1 = const0_rtx;
10271               code = GE;
10272             }
10273           break;
10274
10275         case GEU:
10276           /* >= C is equivalent to > (C - 1).  */
10277           if (const_op > 1)
10278             {
10279               const_op -= 1;
10280               op1 = GEN_INT (const_op);
10281               code = GTU;
10282               /* ... fall through ...  */
10283             }
10284
10285           /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
10286           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10287                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10288             {
10289               const_op = 0, op1 = const0_rtx;
10290               code = LT;
10291               break;
10292             }
10293           else
10294             break;
10295
10296         case GTU:
10297           /* unsigned > 0 is equivalent to != 0 */
10298           if (const_op == 0)
10299             code = NE;
10300
10301           /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
10302           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10303                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10304             {
10305               const_op = 0, op1 = const0_rtx;
10306               code = LT;
10307             }
10308           break;
10309
10310         default:
10311           break;
10312         }
10313
10314       /* Compute some predicates to simplify code below.  */
10315
10316       equality_comparison_p = (code == EQ || code == NE);
10317       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10318       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10319                                || code == GEU);
10320
10321       /* If this is a sign bit comparison and we can do arithmetic in
10322          MODE, say that we will only be needing the sign bit of OP0.  */
10323       if (sign_bit_comparison_p
10324           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10325         op0 = force_to_mode (op0, mode,
10326                              ((HOST_WIDE_INT) 1
10327                               << (GET_MODE_BITSIZE (mode) - 1)),
10328                              0);
10329
10330       /* Now try cases based on the opcode of OP0.  If none of the cases
10331          does a "continue", we exit this loop immediately after the
10332          switch.  */
10333
10334       switch (GET_CODE (op0))
10335         {
10336         case ZERO_EXTRACT:
10337           /* If we are extracting a single bit from a variable position in
10338              a constant that has only a single bit set and are comparing it
10339              with zero, we can convert this into an equality comparison
10340              between the position and the location of the single bit.  */
10341           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10342              have already reduced the shift count modulo the word size.  */
10343           if (!SHIFT_COUNT_TRUNCATED
10344               && GET_CODE (XEXP (op0, 0)) == CONST_INT
10345               && XEXP (op0, 1) == const1_rtx
10346               && equality_comparison_p && const_op == 0
10347               && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10348             {
10349               if (BITS_BIG_ENDIAN)
10350                 {
10351                   enum machine_mode new_mode
10352                     = mode_for_extraction (EP_extzv, 1);
10353                   if (new_mode == MAX_MACHINE_MODE)
10354                     i = BITS_PER_WORD - 1 - i;
10355                   else
10356                     {
10357                       mode = new_mode;
10358                       i = (GET_MODE_BITSIZE (mode) - 1 - i);
10359                     }
10360                 }
10361
10362               op0 = XEXP (op0, 2);
10363               op1 = GEN_INT (i);
10364               const_op = i;
10365
10366               /* Result is nonzero iff shift count is equal to I.  */
10367               code = reverse_condition (code);
10368               continue;
10369             }
10370
10371           /* ... fall through ...  */
10372
10373         case SIGN_EXTRACT:
10374           tem = expand_compound_operation (op0);
10375           if (tem != op0)
10376             {
10377               op0 = tem;
10378               continue;
10379             }
10380           break;
10381
10382         case NOT:
10383           /* If testing for equality, we can take the NOT of the constant.  */
10384           if (equality_comparison_p
10385               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10386             {
10387               op0 = XEXP (op0, 0);
10388               op1 = tem;
10389               continue;
10390             }
10391
10392           /* If just looking at the sign bit, reverse the sense of the
10393              comparison.  */
10394           if (sign_bit_comparison_p)
10395             {
10396               op0 = XEXP (op0, 0);
10397               code = (code == GE ? LT : GE);
10398               continue;
10399             }
10400           break;
10401
10402         case NEG:
10403           /* If testing for equality, we can take the NEG of the constant.  */
10404           if (equality_comparison_p
10405               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10406             {
10407               op0 = XEXP (op0, 0);
10408               op1 = tem;
10409               continue;
10410             }
10411
10412           /* The remaining cases only apply to comparisons with zero.  */
10413           if (const_op != 0)
10414             break;
10415
10416           /* When X is ABS or is known positive,
10417              (neg X) is < 0 if and only if X != 0.  */
10418
10419           if (sign_bit_comparison_p
10420               && (GET_CODE (XEXP (op0, 0)) == ABS
10421                   || (mode_width <= HOST_BITS_PER_WIDE_INT
10422                       && (nonzero_bits (XEXP (op0, 0), mode)
10423                           & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10424             {
10425               op0 = XEXP (op0, 0);
10426               code = (code == LT ? NE : EQ);
10427               continue;
10428             }
10429
10430           /* If we have NEG of something whose two high-order bits are the
10431              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
10432           if (num_sign_bit_copies (op0, mode) >= 2)
10433             {
10434               op0 = XEXP (op0, 0);
10435               code = swap_condition (code);
10436               continue;
10437             }
10438           break;
10439
10440         case ROTATE:
10441           /* If we are testing equality and our count is a constant, we
10442              can perform the inverse operation on our RHS.  */
10443           if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10444               && (tem = simplify_binary_operation (ROTATERT, mode,
10445                                                    op1, XEXP (op0, 1))) != 0)
10446             {
10447               op0 = XEXP (op0, 0);
10448               op1 = tem;
10449               continue;
10450             }
10451
10452           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10453              a particular bit.  Convert it to an AND of a constant of that
10454              bit.  This will be converted into a ZERO_EXTRACT.  */
10455           if (const_op == 0 && sign_bit_comparison_p
10456               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10457               && mode_width <= HOST_BITS_PER_WIDE_INT)
10458             {
10459               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10460                                             ((HOST_WIDE_INT) 1
10461                                              << (mode_width - 1
10462                                                  - INTVAL (XEXP (op0, 1)))));
10463               code = (code == LT ? NE : EQ);
10464               continue;
10465             }
10466
10467           /* Fall through.  */
10468
10469         case ABS:
10470           /* ABS is ignorable inside an equality comparison with zero.  */
10471           if (const_op == 0 && equality_comparison_p)
10472             {
10473               op0 = XEXP (op0, 0);
10474               continue;
10475             }
10476           break;
10477
10478         case SIGN_EXTEND:
10479           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10480              (compare FOO CONST) if CONST fits in FOO's mode and we
10481              are either testing inequality or have an unsigned
10482              comparison with ZERO_EXTEND or a signed comparison with
10483              SIGN_EXTEND.  But don't do it if we don't have a compare
10484              insn of the given mode, since we'd have to revert it
10485              later on, and then we wouldn't know whether to sign- or
10486              zero-extend.  */
10487           mode = GET_MODE (XEXP (op0, 0));
10488           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10489               && ! unsigned_comparison_p
10490               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10491               && ((unsigned HOST_WIDE_INT) const_op
10492                   < (((unsigned HOST_WIDE_INT) 1
10493                       << (GET_MODE_BITSIZE (mode) - 1))))
10494               && optab_handler (cmp_optab, mode)->insn_code != CODE_FOR_nothing)
10495             {
10496               op0 = XEXP (op0, 0);
10497               continue;
10498             }
10499           break;
10500
10501         case SUBREG:
10502           /* Check for the case where we are comparing A - C1 with C2, that is
10503
10504                (subreg:MODE (plus (A) (-C1))) op (C2)
10505
10506              with C1 a constant, and try to lift the SUBREG, i.e. to do the
10507              comparison in the wider mode.  One of the following two conditions
10508              must be true in order for this to be valid:
10509
10510                1. The mode extension results in the same bit pattern being added
10511                   on both sides and the comparison is equality or unsigned.  As
10512                   C2 has been truncated to fit in MODE, the pattern can only be
10513                   all 0s or all 1s.
10514
10515                2. The mode extension results in the sign bit being copied on
10516                   each side.
10517
10518              The difficulty here is that we have predicates for A but not for
10519              (A - C1) so we need to check that C1 is within proper bounds so
10520              as to perturbate A as little as possible.  */
10521
10522           if (mode_width <= HOST_BITS_PER_WIDE_INT
10523               && subreg_lowpart_p (op0)
10524               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10525               && GET_CODE (SUBREG_REG (op0)) == PLUS
10526               && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10527             {
10528               enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10529               rtx a = XEXP (SUBREG_REG (op0), 0);
10530               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10531
10532               if ((c1 > 0
10533                    && (unsigned HOST_WIDE_INT) c1
10534                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10535                    && (equality_comparison_p || unsigned_comparison_p)
10536                    /* (A - C1) zero-extends if it is positive and sign-extends
10537                       if it is negative, C2 both zero- and sign-extends.  */
10538                    && ((0 == (nonzero_bits (a, inner_mode)
10539                               & ~GET_MODE_MASK (mode))
10540                         && const_op >= 0)
10541                        /* (A - C1) sign-extends if it is positive and 1-extends
10542                           if it is negative, C2 both sign- and 1-extends.  */
10543                        || (num_sign_bit_copies (a, inner_mode)
10544                            > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10545                                              - mode_width)
10546                            && const_op < 0)))
10547                   || ((unsigned HOST_WIDE_INT) c1
10548                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10549                       /* (A - C1) always sign-extends, like C2.  */
10550                       && num_sign_bit_copies (a, inner_mode)
10551                          > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10552                                            - (mode_width - 1))))
10553                 {
10554                   op0 = SUBREG_REG (op0);
10555                   continue;
10556                 }
10557             }
10558
10559           /* If the inner mode is narrower and we are extracting the low part,
10560              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
10561           if (subreg_lowpart_p (op0)
10562               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10563             /* Fall through */ ;
10564           else
10565             break;
10566
10567           /* ... fall through ...  */
10568
10569         case ZERO_EXTEND:
10570           mode = GET_MODE (XEXP (op0, 0));
10571           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10572               && (unsigned_comparison_p || equality_comparison_p)
10573               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10574               && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10575               && optab_handler (cmp_optab, mode)->insn_code != CODE_FOR_nothing)
10576             {
10577               op0 = XEXP (op0, 0);
10578               continue;
10579             }
10580           break;
10581
10582         case PLUS:
10583           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
10584              this for equality comparisons due to pathological cases involving
10585              overflows.  */
10586           if (equality_comparison_p
10587               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10588                                                         op1, XEXP (op0, 1))))
10589             {
10590               op0 = XEXP (op0, 0);
10591               op1 = tem;
10592               continue;
10593             }
10594
10595           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
10596           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10597               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10598             {
10599               op0 = XEXP (XEXP (op0, 0), 0);
10600               code = (code == LT ? EQ : NE);
10601               continue;
10602             }
10603           break;
10604
10605         case MINUS:
10606           /* We used to optimize signed comparisons against zero, but that
10607              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
10608              arrive here as equality comparisons, or (GEU, LTU) are
10609              optimized away.  No need to special-case them.  */
10610
10611           /* (eq (minus A B) C) -> (eq A (plus B C)) or
10612              (eq B (minus A C)), whichever simplifies.  We can only do
10613              this for equality comparisons due to pathological cases involving
10614              overflows.  */
10615           if (equality_comparison_p
10616               && 0 != (tem = simplify_binary_operation (PLUS, mode,
10617                                                         XEXP (op0, 1), op1)))
10618             {
10619               op0 = XEXP (op0, 0);
10620               op1 = tem;
10621               continue;
10622             }
10623
10624           if (equality_comparison_p
10625               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10626                                                         XEXP (op0, 0), op1)))
10627             {
10628               op0 = XEXP (op0, 1);
10629               op1 = tem;
10630               continue;
10631             }
10632
10633           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10634              of bits in X minus 1, is one iff X > 0.  */
10635           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10636               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10637               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10638                  == mode_width - 1
10639               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10640             {
10641               op0 = XEXP (op0, 1);
10642               code = (code == GE ? LE : GT);
10643               continue;
10644             }
10645           break;
10646
10647         case XOR:
10648           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
10649              if C is zero or B is a constant.  */
10650           if (equality_comparison_p
10651               && 0 != (tem = simplify_binary_operation (XOR, mode,
10652                                                         XEXP (op0, 1), op1)))
10653             {
10654               op0 = XEXP (op0, 0);
10655               op1 = tem;
10656               continue;
10657             }
10658           break;
10659
10660         case EQ:  case NE:
10661         case UNEQ:  case LTGT:
10662         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
10663         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
10664         case UNORDERED: case ORDERED:
10665           /* We can't do anything if OP0 is a condition code value, rather
10666              than an actual data value.  */
10667           if (const_op != 0
10668               || CC0_P (XEXP (op0, 0))
10669               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10670             break;
10671
10672           /* Get the two operands being compared.  */
10673           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10674             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10675           else
10676             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10677
10678           /* Check for the cases where we simply want the result of the
10679              earlier test or the opposite of that result.  */
10680           if (code == NE || code == EQ
10681               || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10682                   && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10683                   && (STORE_FLAG_VALUE
10684                       & (((HOST_WIDE_INT) 1
10685                           << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10686                   && (code == LT || code == GE)))
10687             {
10688               enum rtx_code new_code;
10689               if (code == LT || code == NE)
10690                 new_code = GET_CODE (op0);
10691               else
10692                 new_code = reversed_comparison_code (op0, NULL);
10693
10694               if (new_code != UNKNOWN)
10695                 {
10696                   code = new_code;
10697                   op0 = tem;
10698                   op1 = tem1;
10699                   continue;
10700                 }
10701             }
10702           break;
10703
10704         case IOR:
10705           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10706              iff X <= 0.  */
10707           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10708               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10709               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10710             {
10711               op0 = XEXP (op0, 1);
10712               code = (code == GE ? GT : LE);
10713               continue;
10714             }
10715           break;
10716
10717         case AND:
10718           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
10719              will be converted to a ZERO_EXTRACT later.  */
10720           if (const_op == 0 && equality_comparison_p
10721               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10722               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10723             {
10724               op0 = simplify_and_const_int
10725                 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10726                                                    XEXP (op0, 1),
10727                                                    XEXP (XEXP (op0, 0), 1)),
10728                  (HOST_WIDE_INT) 1);
10729               continue;
10730             }
10731
10732           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10733              zero and X is a comparison and C1 and C2 describe only bits set
10734              in STORE_FLAG_VALUE, we can compare with X.  */
10735           if (const_op == 0 && equality_comparison_p
10736               && mode_width <= HOST_BITS_PER_WIDE_INT
10737               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10738               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10739               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10740               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10741               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10742             {
10743               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10744                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
10745               if ((~STORE_FLAG_VALUE & mask) == 0
10746                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10747                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10748                           && COMPARISON_P (tem))))
10749                 {
10750                   op0 = XEXP (XEXP (op0, 0), 0);
10751                   continue;
10752                 }
10753             }
10754
10755           /* If we are doing an equality comparison of an AND of a bit equal
10756              to the sign bit, replace this with a LT or GE comparison of
10757              the underlying value.  */
10758           if (equality_comparison_p
10759               && const_op == 0
10760               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10761               && mode_width <= HOST_BITS_PER_WIDE_INT
10762               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10763                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10764             {
10765               op0 = XEXP (op0, 0);
10766               code = (code == EQ ? GE : LT);
10767               continue;
10768             }
10769
10770           /* If this AND operation is really a ZERO_EXTEND from a narrower
10771              mode, the constant fits within that mode, and this is either an
10772              equality or unsigned comparison, try to do this comparison in
10773              the narrower mode.
10774
10775              Note that in:
10776
10777              (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10778              -> (ne:DI (reg:SI 4) (const_int 0))
10779
10780              unless TRULY_NOOP_TRUNCATION allows it or the register is
10781              known to hold a value of the required mode the
10782              transformation is invalid.  */
10783           if ((equality_comparison_p || unsigned_comparison_p)
10784               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10785               && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10786                                    & GET_MODE_MASK (mode))
10787                                   + 1)) >= 0
10788               && const_op >> i == 0
10789               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
10790               && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
10791                                          GET_MODE_BITSIZE (GET_MODE (op0)))
10792                   || (REG_P (XEXP (op0, 0))
10793                       && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
10794             {
10795               op0 = gen_lowpart (tmode, XEXP (op0, 0));
10796               continue;
10797             }
10798
10799           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10800              fits in both M1 and M2 and the SUBREG is either paradoxical
10801              or represents the low part, permute the SUBREG and the AND
10802              and try again.  */
10803           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10804             {
10805               unsigned HOST_WIDE_INT c1;
10806               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10807               /* Require an integral mode, to avoid creating something like
10808                  (AND:SF ...).  */
10809               if (SCALAR_INT_MODE_P (tmode)
10810                   /* It is unsafe to commute the AND into the SUBREG if the
10811                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10812                      not defined.  As originally written the upper bits
10813                      have a defined value due to the AND operation.
10814                      However, if we commute the AND inside the SUBREG then
10815                      they no longer have defined values and the meaning of
10816                      the code has been changed.  */
10817                   && (0
10818 #ifdef WORD_REGISTER_OPERATIONS
10819                       || (mode_width > GET_MODE_BITSIZE (tmode)
10820                           && mode_width <= BITS_PER_WORD)
10821 #endif
10822                       || (mode_width <= GET_MODE_BITSIZE (tmode)
10823                           && subreg_lowpart_p (XEXP (op0, 0))))
10824                   && GET_CODE (XEXP (op0, 1)) == CONST_INT
10825                   && mode_width <= HOST_BITS_PER_WIDE_INT
10826                   && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10827                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10828                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
10829                   && c1 != mask
10830                   && c1 != GET_MODE_MASK (tmode))
10831                 {
10832                   op0 = simplify_gen_binary (AND, tmode,
10833                                              SUBREG_REG (XEXP (op0, 0)),
10834                                              gen_int_mode (c1, tmode));
10835                   op0 = gen_lowpart (mode, op0);
10836                   continue;
10837                 }
10838             }
10839
10840           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
10841           if (const_op == 0 && equality_comparison_p
10842               && XEXP (op0, 1) == const1_rtx
10843               && GET_CODE (XEXP (op0, 0)) == NOT)
10844             {
10845               op0 = simplify_and_const_int
10846                 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10847               code = (code == NE ? EQ : NE);
10848               continue;
10849             }
10850
10851           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10852              (eq (and (lshiftrt X) 1) 0).
10853              Also handle the case where (not X) is expressed using xor.  */
10854           if (const_op == 0 && equality_comparison_p
10855               && XEXP (op0, 1) == const1_rtx
10856               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10857             {
10858               rtx shift_op = XEXP (XEXP (op0, 0), 0);
10859               rtx shift_count = XEXP (XEXP (op0, 0), 1);
10860
10861               if (GET_CODE (shift_op) == NOT
10862                   || (GET_CODE (shift_op) == XOR
10863                       && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10864                       && GET_CODE (shift_count) == CONST_INT
10865                       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10866                       && (INTVAL (XEXP (shift_op, 1))
10867                           == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10868                 {
10869                   op0 = simplify_and_const_int
10870                     (NULL_RTX, mode,
10871                      gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10872                      (HOST_WIDE_INT) 1);
10873                   code = (code == NE ? EQ : NE);
10874                   continue;
10875                 }
10876             }
10877           break;
10878
10879         case ASHIFT:
10880           /* If we have (compare (ashift FOO N) (const_int C)) and
10881              the high order N bits of FOO (N+1 if an inequality comparison)
10882              are known to be zero, we can do this by comparing FOO with C
10883              shifted right N bits so long as the low-order N bits of C are
10884              zero.  */
10885           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10886               && INTVAL (XEXP (op0, 1)) >= 0
10887               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10888                   < HOST_BITS_PER_WIDE_INT)
10889               && ((const_op
10890                    & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10891               && mode_width <= HOST_BITS_PER_WIDE_INT
10892               && (nonzero_bits (XEXP (op0, 0), mode)
10893                   & ~(mask >> (INTVAL (XEXP (op0, 1))
10894                                + ! equality_comparison_p))) == 0)
10895             {
10896               /* We must perform a logical shift, not an arithmetic one,
10897                  as we want the top N bits of C to be zero.  */
10898               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10899
10900               temp >>= INTVAL (XEXP (op0, 1));
10901               op1 = gen_int_mode (temp, mode);
10902               op0 = XEXP (op0, 0);
10903               continue;
10904             }
10905
10906           /* If we are doing a sign bit comparison, it means we are testing
10907              a particular bit.  Convert it to the appropriate AND.  */
10908           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10909               && mode_width <= HOST_BITS_PER_WIDE_INT)
10910             {
10911               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10912                                             ((HOST_WIDE_INT) 1
10913                                              << (mode_width - 1
10914                                                  - INTVAL (XEXP (op0, 1)))));
10915               code = (code == LT ? NE : EQ);
10916               continue;
10917             }
10918
10919           /* If this an equality comparison with zero and we are shifting
10920              the low bit to the sign bit, we can convert this to an AND of the
10921              low-order bit.  */
10922           if (const_op == 0 && equality_comparison_p
10923               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10924               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10925                  == mode_width - 1)
10926             {
10927               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10928                                             (HOST_WIDE_INT) 1);
10929               continue;
10930             }
10931           break;
10932
10933         case ASHIFTRT:
10934           /* If this is an equality comparison with zero, we can do this
10935              as a logical shift, which might be much simpler.  */
10936           if (equality_comparison_p && const_op == 0
10937               && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10938             {
10939               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10940                                           XEXP (op0, 0),
10941                                           INTVAL (XEXP (op0, 1)));
10942               continue;
10943             }
10944
10945           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10946              do the comparison in a narrower mode.  */
10947           if (! unsigned_comparison_p
10948               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10949               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10950               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10951               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10952                                          MODE_INT, 1)) != BLKmode
10953               && (((unsigned HOST_WIDE_INT) const_op
10954                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10955                   <= GET_MODE_MASK (tmode)))
10956             {
10957               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10958               continue;
10959             }
10960
10961           /* Likewise if OP0 is a PLUS of a sign extension with a
10962              constant, which is usually represented with the PLUS
10963              between the shifts.  */
10964           if (! unsigned_comparison_p
10965               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10966               && GET_CODE (XEXP (op0, 0)) == PLUS
10967               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10968               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10969               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10970               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10971                                          MODE_INT, 1)) != BLKmode
10972               && (((unsigned HOST_WIDE_INT) const_op
10973                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10974                   <= GET_MODE_MASK (tmode)))
10975             {
10976               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10977               rtx add_const = XEXP (XEXP (op0, 0), 1);
10978               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10979                                                    add_const, XEXP (op0, 1));
10980
10981               op0 = simplify_gen_binary (PLUS, tmode,
10982                                          gen_lowpart (tmode, inner),
10983                                          new_const);
10984               continue;
10985             }
10986
10987           /* ... fall through ...  */
10988         case LSHIFTRT:
10989           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10990              the low order N bits of FOO are known to be zero, we can do this
10991              by comparing FOO with C shifted left N bits so long as no
10992              overflow occurs.  */
10993           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10994               && INTVAL (XEXP (op0, 1)) >= 0
10995               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10996               && mode_width <= HOST_BITS_PER_WIDE_INT
10997               && (nonzero_bits (XEXP (op0, 0), mode)
10998                   & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10999               && (((unsigned HOST_WIDE_INT) const_op
11000                    + (GET_CODE (op0) != LSHIFTRT
11001                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11002                          + 1)
11003                       : 0))
11004                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11005             {
11006               /* If the shift was logical, then we must make the condition
11007                  unsigned.  */
11008               if (GET_CODE (op0) == LSHIFTRT)
11009                 code = unsigned_condition (code);
11010
11011               const_op <<= INTVAL (XEXP (op0, 1));
11012               op1 = GEN_INT (const_op);
11013               op0 = XEXP (op0, 0);
11014               continue;
11015             }
11016
11017           /* If we are using this shift to extract just the sign bit, we
11018              can replace this with an LT or GE comparison.  */
11019           if (const_op == 0
11020               && (equality_comparison_p || sign_bit_comparison_p)
11021               && GET_CODE (XEXP (op0, 1)) == CONST_INT
11022               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11023                  == mode_width - 1)
11024             {
11025               op0 = XEXP (op0, 0);
11026               code = (code == NE || code == GT ? LT : GE);
11027               continue;
11028             }
11029           break;
11030
11031         default:
11032           break;
11033         }
11034
11035       break;
11036     }
11037
11038   /* Now make any compound operations involved in this comparison.  Then,
11039      check for an outmost SUBREG on OP0 that is not doing anything or is
11040      paradoxical.  The latter transformation must only be performed when
11041      it is known that the "extra" bits will be the same in op0 and op1 or
11042      that they don't matter.  There are three cases to consider:
11043
11044      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
11045      care bits and we can assume they have any convenient value.  So
11046      making the transformation is safe.
11047
11048      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11049      In this case the upper bits of op0 are undefined.  We should not make
11050      the simplification in that case as we do not know the contents of
11051      those bits.
11052
11053      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11054      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
11055      also be sure that they are the same as the upper bits of op1.
11056
11057      We can never remove a SUBREG for a non-equality comparison because
11058      the sign bit is in a different place in the underlying object.  */
11059
11060   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11061   op1 = make_compound_operation (op1, SET);
11062
11063   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11064       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11065       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11066       && (code == NE || code == EQ))
11067     {
11068       if (GET_MODE_SIZE (GET_MODE (op0))
11069           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11070         {
11071           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
11072              implemented.  */
11073           if (REG_P (SUBREG_REG (op0)))
11074             {
11075               op0 = SUBREG_REG (op0);
11076               op1 = gen_lowpart (GET_MODE (op0), op1);
11077             }
11078         }
11079       else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11080                 <= HOST_BITS_PER_WIDE_INT)
11081                && (nonzero_bits (SUBREG_REG (op0),
11082                                  GET_MODE (SUBREG_REG (op0)))
11083                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11084         {
11085           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11086
11087           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11088                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11089             op0 = SUBREG_REG (op0), op1 = tem;
11090         }
11091     }
11092
11093   /* We now do the opposite procedure: Some machines don't have compare
11094      insns in all modes.  If OP0's mode is an integer mode smaller than a
11095      word and we can't do a compare in that mode, see if there is a larger
11096      mode for which we can do the compare.  There are a number of cases in
11097      which we can use the wider mode.  */
11098
11099   mode = GET_MODE (op0);
11100   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11101       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11102       && ! have_insn_for (COMPARE, mode))
11103     for (tmode = GET_MODE_WIDER_MODE (mode);
11104          (tmode != VOIDmode
11105           && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11106          tmode = GET_MODE_WIDER_MODE (tmode))
11107       if (have_insn_for (COMPARE, tmode))
11108         {
11109           int zero_extended;
11110
11111           /* If the only nonzero bits in OP0 and OP1 are those in the
11112              narrower mode and this is an equality or unsigned comparison,
11113              we can use the wider mode.  Similarly for sign-extended
11114              values, in which case it is true for all comparisons.  */
11115           zero_extended = ((code == EQ || code == NE
11116                             || code == GEU || code == GTU
11117                             || code == LEU || code == LTU)
11118                            && (nonzero_bits (op0, tmode)
11119                                & ~GET_MODE_MASK (mode)) == 0
11120                            && ((GET_CODE (op1) == CONST_INT
11121                                 || (nonzero_bits (op1, tmode)
11122                                     & ~GET_MODE_MASK (mode)) == 0)));
11123
11124           if (zero_extended
11125               || ((num_sign_bit_copies (op0, tmode)
11126                    > (unsigned int) (GET_MODE_BITSIZE (tmode)
11127                                      - GET_MODE_BITSIZE (mode)))
11128                   && (num_sign_bit_copies (op1, tmode)
11129                       > (unsigned int) (GET_MODE_BITSIZE (tmode)
11130                                         - GET_MODE_BITSIZE (mode)))))
11131             {
11132               /* If OP0 is an AND and we don't have an AND in MODE either,
11133                  make a new AND in the proper mode.  */
11134               if (GET_CODE (op0) == AND
11135                   && !have_insn_for (AND, mode))
11136                 op0 = simplify_gen_binary (AND, tmode,
11137                                            gen_lowpart (tmode,
11138                                                         XEXP (op0, 0)),
11139                                            gen_lowpart (tmode,
11140                                                         XEXP (op0, 1)));
11141
11142               op0 = gen_lowpart (tmode, op0);
11143               if (zero_extended && GET_CODE (op1) == CONST_INT)
11144                 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11145               op1 = gen_lowpart (tmode, op1);
11146               break;
11147             }
11148
11149           /* If this is a test for negative, we can make an explicit
11150              test of the sign bit.  */
11151
11152           if (op1 == const0_rtx && (code == LT || code == GE)
11153               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11154             {
11155               op0 = simplify_gen_binary (AND, tmode,
11156                                          gen_lowpart (tmode, op0),
11157                                          GEN_INT ((HOST_WIDE_INT) 1
11158                                                   << (GET_MODE_BITSIZE (mode)
11159                                                       - 1)));
11160               code = (code == LT) ? NE : EQ;
11161               break;
11162             }
11163         }
11164
11165 #ifdef CANONICALIZE_COMPARISON
11166   /* If this machine only supports a subset of valid comparisons, see if we
11167      can convert an unsupported one into a supported one.  */
11168   CANONICALIZE_COMPARISON (code, op0, op1);
11169 #endif
11170
11171   *pop0 = op0;
11172   *pop1 = op1;
11173
11174   return code;
11175 }
11176 \f
11177 /* Utility function for record_value_for_reg.  Count number of
11178    rtxs in X.  */
11179 static int
11180 count_rtxs (rtx x)
11181 {
11182   enum rtx_code code = GET_CODE (x);
11183   const char *fmt;
11184   int i, ret = 1;
11185
11186   if (GET_RTX_CLASS (code) == '2'
11187       || GET_RTX_CLASS (code) == 'c')
11188     {
11189       rtx x0 = XEXP (x, 0);
11190       rtx x1 = XEXP (x, 1);
11191
11192       if (x0 == x1)
11193         return 1 + 2 * count_rtxs (x0);
11194
11195       if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11196            || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11197           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11198         return 2 + 2 * count_rtxs (x0)
11199                + count_rtxs (x == XEXP (x1, 0)
11200                              ? XEXP (x1, 1) : XEXP (x1, 0));
11201
11202       if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11203            || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11204           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11205         return 2 + 2 * count_rtxs (x1)
11206                + count_rtxs (x == XEXP (x0, 0)
11207                              ? XEXP (x0, 1) : XEXP (x0, 0));
11208     }
11209
11210   fmt = GET_RTX_FORMAT (code);
11211   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11212     if (fmt[i] == 'e')
11213       ret += count_rtxs (XEXP (x, i));
11214
11215   return ret;
11216 }
11217 \f
11218 /* Utility function for following routine.  Called when X is part of a value
11219    being stored into last_set_value.  Sets last_set_table_tick
11220    for each register mentioned.  Similar to mention_regs in cse.c  */
11221
11222 static void
11223 update_table_tick (rtx x)
11224 {
11225   enum rtx_code code = GET_CODE (x);
11226   const char *fmt = GET_RTX_FORMAT (code);
11227   int i;
11228
11229   if (code == REG)
11230     {
11231       unsigned int regno = REGNO (x);
11232       unsigned int endregno = END_REGNO (x);
11233       unsigned int r;
11234
11235       for (r = regno; r < endregno; r++)
11236         {
11237           reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
11238           rsp->last_set_table_tick = label_tick;
11239         }
11240
11241       return;
11242     }
11243
11244   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11245     /* Note that we can't have an "E" in values stored; see
11246        get_last_value_validate.  */
11247     if (fmt[i] == 'e')
11248       {
11249         /* Check for identical subexpressions.  If x contains
11250            identical subexpression we only have to traverse one of
11251            them.  */
11252         if (i == 0 && ARITHMETIC_P (x))
11253           {
11254             /* Note that at this point x1 has already been
11255                processed.  */
11256             rtx x0 = XEXP (x, 0);
11257             rtx x1 = XEXP (x, 1);
11258
11259             /* If x0 and x1 are identical then there is no need to
11260                process x0.  */
11261             if (x0 == x1)
11262               break;
11263
11264             /* If x0 is identical to a subexpression of x1 then while
11265                processing x1, x0 has already been processed.  Thus we
11266                are done with x.  */
11267             if (ARITHMETIC_P (x1)
11268                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11269               break;
11270
11271             /* If x1 is identical to a subexpression of x0 then we
11272                still have to process the rest of x0.  */
11273             if (ARITHMETIC_P (x0)
11274                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11275               {
11276                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11277                 break;
11278               }
11279           }
11280
11281         update_table_tick (XEXP (x, i));
11282       }
11283 }
11284
11285 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
11286    are saying that the register is clobbered and we no longer know its
11287    value.  If INSN is zero, don't update reg_stat[].last_set; this is
11288    only permitted with VALUE also zero and is used to invalidate the
11289    register.  */
11290
11291 static void
11292 record_value_for_reg (rtx reg, rtx insn, rtx value)
11293 {
11294   unsigned int regno = REGNO (reg);
11295   unsigned int endregno = END_REGNO (reg);
11296   unsigned int i;
11297   reg_stat_type *rsp;
11298
11299   /* If VALUE contains REG and we have a previous value for REG, substitute
11300      the previous value.  */
11301   if (value && insn && reg_overlap_mentioned_p (reg, value))
11302     {
11303       rtx tem;
11304
11305       /* Set things up so get_last_value is allowed to see anything set up to
11306          our insn.  */
11307       subst_low_luid = DF_INSN_LUID (insn);
11308       tem = get_last_value (reg);
11309
11310       /* If TEM is simply a binary operation with two CLOBBERs as operands,
11311          it isn't going to be useful and will take a lot of time to process,
11312          so just use the CLOBBER.  */
11313
11314       if (tem)
11315         {
11316           if (ARITHMETIC_P (tem)
11317               && GET_CODE (XEXP (tem, 0)) == CLOBBER
11318               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11319             tem = XEXP (tem, 0);
11320           else if (count_occurrences (value, reg, 1) >= 2)
11321             {
11322               /* If there are two or more occurrences of REG in VALUE,
11323                  prevent the value from growing too much.  */
11324               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
11325                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
11326             }
11327
11328           value = replace_rtx (copy_rtx (value), reg, tem);
11329         }
11330     }
11331
11332   /* For each register modified, show we don't know its value, that
11333      we don't know about its bitwise content, that its value has been
11334      updated, and that we don't know the location of the death of the
11335      register.  */
11336   for (i = regno; i < endregno; i++)
11337     {
11338       rsp = VEC_index (reg_stat_type, reg_stat, i);
11339
11340       if (insn)
11341         rsp->last_set = insn;
11342
11343       rsp->last_set_value = 0;
11344       rsp->last_set_mode = 0;
11345       rsp->last_set_nonzero_bits = 0;
11346       rsp->last_set_sign_bit_copies = 0;
11347       rsp->last_death = 0;
11348       rsp->truncated_to_mode = 0;
11349     }
11350
11351   /* Mark registers that are being referenced in this value.  */
11352   if (value)
11353     update_table_tick (value);
11354
11355   /* Now update the status of each register being set.
11356      If someone is using this register in this block, set this register
11357      to invalid since we will get confused between the two lives in this
11358      basic block.  This makes using this register always invalid.  In cse, we
11359      scan the table to invalidate all entries using this register, but this
11360      is too much work for us.  */
11361
11362   for (i = regno; i < endregno; i++)
11363     {
11364       rsp = VEC_index (reg_stat_type, reg_stat, i);
11365       rsp->last_set_label = label_tick;
11366       if (!insn
11367           || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
11368         rsp->last_set_invalid = 1;
11369       else
11370         rsp->last_set_invalid = 0;
11371     }
11372
11373   /* The value being assigned might refer to X (like in "x++;").  In that
11374      case, we must replace it with (clobber (const_int 0)) to prevent
11375      infinite loops.  */
11376   rsp = VEC_index (reg_stat_type, reg_stat, regno);
11377   if (value && ! get_last_value_validate (&value, insn,
11378                                           rsp->last_set_label, 0))
11379     {
11380       value = copy_rtx (value);
11381       if (! get_last_value_validate (&value, insn,
11382                                      rsp->last_set_label, 1))
11383         value = 0;
11384     }
11385
11386   /* For the main register being modified, update the value, the mode, the
11387      nonzero bits, and the number of sign bit copies.  */
11388
11389   rsp->last_set_value = value;
11390
11391   if (value)
11392     {
11393       enum machine_mode mode = GET_MODE (reg);
11394       subst_low_luid = DF_INSN_LUID (insn);
11395       rsp->last_set_mode = mode;
11396       if (GET_MODE_CLASS (mode) == MODE_INT
11397           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11398         mode = nonzero_bits_mode;
11399       rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
11400       rsp->last_set_sign_bit_copies
11401         = num_sign_bit_copies (value, GET_MODE (reg));
11402     }
11403 }
11404
11405 /* Called via note_stores from record_dead_and_set_regs to handle one
11406    SET or CLOBBER in an insn.  DATA is the instruction in which the
11407    set is occurring.  */
11408
11409 static void
11410 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
11411 {
11412   rtx record_dead_insn = (rtx) data;
11413
11414   if (GET_CODE (dest) == SUBREG)
11415     dest = SUBREG_REG (dest);
11416
11417   if (!record_dead_insn)
11418     {
11419       if (REG_P (dest))
11420         record_value_for_reg (dest, NULL_RTX, NULL_RTX);
11421       return;
11422     }
11423
11424   if (REG_P (dest))
11425     {
11426       /* If we are setting the whole register, we know its value.  Otherwise
11427          show that we don't know the value.  We can handle SUBREG in
11428          some cases.  */
11429       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11430         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11431       else if (GET_CODE (setter) == SET
11432                && GET_CODE (SET_DEST (setter)) == SUBREG
11433                && SUBREG_REG (SET_DEST (setter)) == dest
11434                && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11435                && subreg_lowpart_p (SET_DEST (setter)))
11436         record_value_for_reg (dest, record_dead_insn,
11437                               gen_lowpart (GET_MODE (dest),
11438                                                        SET_SRC (setter)));
11439       else
11440         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11441     }
11442   else if (MEM_P (dest)
11443            /* Ignore pushes, they clobber nothing.  */
11444            && ! push_operand (dest, GET_MODE (dest)))
11445     mem_last_set = DF_INSN_LUID (record_dead_insn);
11446 }
11447
11448 /* Update the records of when each REG was most recently set or killed
11449    for the things done by INSN.  This is the last thing done in processing
11450    INSN in the combiner loop.
11451
11452    We update reg_stat[], in particular fields last_set, last_set_value,
11453    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11454    last_death, and also the similar information mem_last_set (which insn
11455    most recently modified memory) and last_call_luid (which insn was the
11456    most recent subroutine call).  */
11457
11458 static void
11459 record_dead_and_set_regs (rtx insn)
11460 {
11461   rtx link;
11462   unsigned int i;
11463
11464   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11465     {
11466       if (REG_NOTE_KIND (link) == REG_DEAD
11467           && REG_P (XEXP (link, 0)))
11468         {
11469           unsigned int regno = REGNO (XEXP (link, 0));
11470           unsigned int endregno = END_REGNO (XEXP (link, 0));
11471
11472           for (i = regno; i < endregno; i++)
11473             {
11474               reg_stat_type *rsp;
11475
11476               rsp = VEC_index (reg_stat_type, reg_stat, i);
11477               rsp->last_death = insn;
11478             }
11479         }
11480       else if (REG_NOTE_KIND (link) == REG_INC)
11481         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11482     }
11483
11484   if (CALL_P (insn))
11485     {
11486       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11487         if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11488           {
11489             reg_stat_type *rsp;
11490
11491             rsp = VEC_index (reg_stat_type, reg_stat, i);
11492             rsp->last_set_invalid = 1;
11493             rsp->last_set = insn;
11494             rsp->last_set_value = 0;
11495             rsp->last_set_mode = 0;
11496             rsp->last_set_nonzero_bits = 0;
11497             rsp->last_set_sign_bit_copies = 0;
11498             rsp->last_death = 0;
11499             rsp->truncated_to_mode = 0;
11500           }
11501
11502       last_call_luid = mem_last_set = DF_INSN_LUID (insn);
11503
11504       /* We can't combine into a call pattern.  Remember, though, that
11505          the return value register is set at this LUID.  We could
11506          still replace a register with the return value from the
11507          wrong subroutine call!  */
11508       note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11509     }
11510   else
11511     note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11512 }
11513
11514 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11515    register present in the SUBREG, so for each such SUBREG go back and
11516    adjust nonzero and sign bit information of the registers that are
11517    known to have some zero/sign bits set.
11518
11519    This is needed because when combine blows the SUBREGs away, the
11520    information on zero/sign bits is lost and further combines can be
11521    missed because of that.  */
11522
11523 static void
11524 record_promoted_value (rtx insn, rtx subreg)
11525 {
11526   rtx links, set;
11527   unsigned int regno = REGNO (SUBREG_REG (subreg));
11528   enum machine_mode mode = GET_MODE (subreg);
11529
11530   if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11531     return;
11532
11533   for (links = LOG_LINKS (insn); links;)
11534     {
11535       reg_stat_type *rsp;
11536
11537       insn = XEXP (links, 0);
11538       set = single_set (insn);
11539
11540       if (! set || !REG_P (SET_DEST (set))
11541           || REGNO (SET_DEST (set)) != regno
11542           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11543         {
11544           links = XEXP (links, 1);
11545           continue;
11546         }
11547
11548       rsp = VEC_index (reg_stat_type, reg_stat, regno);
11549       if (rsp->last_set == insn)
11550         {
11551           if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11552             rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
11553         }
11554
11555       if (REG_P (SET_SRC (set)))
11556         {
11557           regno = REGNO (SET_SRC (set));
11558           links = LOG_LINKS (insn);
11559         }
11560       else
11561         break;
11562     }
11563 }
11564
11565 /* Check if X, a register, is known to contain a value already
11566    truncated to MODE.  In this case we can use a subreg to refer to
11567    the truncated value even though in the generic case we would need
11568    an explicit truncation.  */
11569
11570 static bool
11571 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
11572 {
11573   reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11574   enum machine_mode truncated = rsp->truncated_to_mode;
11575
11576   if (truncated == 0
11577       || rsp->truncation_label < label_tick_ebb_start)
11578     return false;
11579   if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11580     return true;
11581   if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11582                              GET_MODE_BITSIZE (truncated)))
11583     return true;
11584   return false;
11585 }
11586
11587 /* X is a REG or a SUBREG.  If X is some sort of a truncation record
11588    it.  For non-TRULY_NOOP_TRUNCATION targets we might be able to turn
11589    a truncate into a subreg using this information.  */
11590
11591 static void
11592 record_truncated_value (rtx x)
11593 {
11594   enum machine_mode truncated_mode;
11595   reg_stat_type *rsp;
11596
11597   if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11598     {
11599       enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11600       truncated_mode = GET_MODE (x);
11601
11602       if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11603         return;
11604
11605       if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11606                                  GET_MODE_BITSIZE (original_mode)))
11607         return;
11608
11609       x = SUBREG_REG (x);
11610     }
11611   /* ??? For hard-regs we now record everything.  We might be able to
11612      optimize this using last_set_mode.  */
11613   else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11614     truncated_mode = GET_MODE (x);
11615   else
11616     return;
11617
11618   rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11619   if (rsp->truncated_to_mode == 0
11620       || rsp->truncation_label < label_tick_ebb_start
11621       || (GET_MODE_SIZE (truncated_mode)
11622           < GET_MODE_SIZE (rsp->truncated_to_mode)))
11623     {
11624       rsp->truncated_to_mode = truncated_mode;
11625       rsp->truncation_label = label_tick;
11626     }
11627 }
11628
11629 /* Scan X for promoted SUBREGs and truncated REGs.  For each one
11630    found, note what it implies to the registers used in it.  */
11631
11632 static void
11633 check_conversions (rtx insn, rtx x)
11634 {
11635   if (GET_CODE (x) == SUBREG || REG_P (x))
11636     {
11637       if (GET_CODE (x) == SUBREG
11638           && SUBREG_PROMOTED_VAR_P (x)
11639           && REG_P (SUBREG_REG (x)))
11640         record_promoted_value (insn, x);
11641
11642       record_truncated_value (x);
11643     }
11644   else
11645     {
11646       const char *format = GET_RTX_FORMAT (GET_CODE (x));
11647       int i, j;
11648
11649       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11650         switch (format[i])
11651           {
11652           case 'e':
11653             check_conversions (insn, XEXP (x, i));
11654             break;
11655           case 'V':
11656           case 'E':
11657             if (XVEC (x, i) != 0)
11658               for (j = 0; j < XVECLEN (x, i); j++)
11659                 check_conversions (insn, XVECEXP (x, i, j));
11660             break;
11661           }
11662     }
11663 }
11664 \f
11665 /* Utility routine for the following function.  Verify that all the registers
11666    mentioned in *LOC are valid when *LOC was part of a value set when
11667    label_tick == TICK.  Return 0 if some are not.
11668
11669    If REPLACE is nonzero, replace the invalid reference with
11670    (clobber (const_int 0)) and return 1.  This replacement is useful because
11671    we often can get useful information about the form of a value (e.g., if
11672    it was produced by a shift that always produces -1 or 0) even though
11673    we don't know exactly what registers it was produced from.  */
11674
11675 static int
11676 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11677 {
11678   rtx x = *loc;
11679   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11680   int len = GET_RTX_LENGTH (GET_CODE (x));
11681   int i;
11682
11683   if (REG_P (x))
11684     {
11685       unsigned int regno = REGNO (x);
11686       unsigned int endregno = END_REGNO (x);
11687       unsigned int j;
11688
11689       for (j = regno; j < endregno; j++)
11690         {
11691           reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
11692           if (rsp->last_set_invalid
11693               /* If this is a pseudo-register that was only set once and not
11694                  live at the beginning of the function, it is always valid.  */
11695               || (! (regno >= FIRST_PSEUDO_REGISTER
11696                      && REG_N_SETS (regno) == 1
11697                      && (!REGNO_REG_SET_P
11698                          (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
11699                   && rsp->last_set_label > tick))
11700           {
11701             if (replace)
11702               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11703             return replace;
11704           }
11705         }
11706
11707       return 1;
11708     }
11709   /* If this is a memory reference, make sure that there were
11710      no stores after it that might have clobbered the value.  We don't
11711      have alias info, so we assume any store invalidates it.  */
11712   else if (MEM_P (x) && !MEM_READONLY_P (x)
11713            && DF_INSN_LUID (insn) <= mem_last_set)
11714     {
11715       if (replace)
11716         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11717       return replace;
11718     }
11719
11720   for (i = 0; i < len; i++)
11721     {
11722       if (fmt[i] == 'e')
11723         {
11724           /* Check for identical subexpressions.  If x contains
11725              identical subexpression we only have to traverse one of
11726              them.  */
11727           if (i == 1 && ARITHMETIC_P (x))
11728             {
11729               /* Note that at this point x0 has already been checked
11730                  and found valid.  */
11731               rtx x0 = XEXP (x, 0);
11732               rtx x1 = XEXP (x, 1);
11733
11734               /* If x0 and x1 are identical then x is also valid.  */
11735               if (x0 == x1)
11736                 return 1;
11737
11738               /* If x1 is identical to a subexpression of x0 then
11739                  while checking x0, x1 has already been checked.  Thus
11740                  it is valid and so as x.  */
11741               if (ARITHMETIC_P (x0)
11742                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11743                 return 1;
11744
11745               /* If x0 is identical to a subexpression of x1 then x is
11746                  valid iff the rest of x1 is valid.  */
11747               if (ARITHMETIC_P (x1)
11748                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11749                 return
11750                   get_last_value_validate (&XEXP (x1,
11751                                                   x0 == XEXP (x1, 0) ? 1 : 0),
11752                                            insn, tick, replace);
11753             }
11754
11755           if (get_last_value_validate (&XEXP (x, i), insn, tick,
11756                                        replace) == 0)
11757             return 0;
11758         }
11759       /* Don't bother with these.  They shouldn't occur anyway.  */
11760       else if (fmt[i] == 'E')
11761         return 0;
11762     }
11763
11764   /* If we haven't found a reason for it to be invalid, it is valid.  */
11765   return 1;
11766 }
11767
11768 /* Get the last value assigned to X, if known.  Some registers
11769    in the value may be replaced with (clobber (const_int 0)) if their value
11770    is known longer known reliably.  */
11771
11772 static rtx
11773 get_last_value (const_rtx x)
11774 {
11775   unsigned int regno;
11776   rtx value;
11777   reg_stat_type *rsp;
11778
11779   /* If this is a non-paradoxical SUBREG, get the value of its operand and
11780      then convert it to the desired mode.  If this is a paradoxical SUBREG,
11781      we cannot predict what values the "extra" bits might have.  */
11782   if (GET_CODE (x) == SUBREG
11783       && subreg_lowpart_p (x)
11784       && (GET_MODE_SIZE (GET_MODE (x))
11785           <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11786       && (value = get_last_value (SUBREG_REG (x))) != 0)
11787     return gen_lowpart (GET_MODE (x), value);
11788
11789   if (!REG_P (x))
11790     return 0;
11791
11792   regno = REGNO (x);
11793   rsp = VEC_index (reg_stat_type, reg_stat, regno);
11794   value = rsp->last_set_value;
11795
11796   /* If we don't have a value, or if it isn't for this basic block and
11797      it's either a hard register, set more than once, or it's a live
11798      at the beginning of the function, return 0.
11799
11800      Because if it's not live at the beginning of the function then the reg
11801      is always set before being used (is never used without being set).
11802      And, if it's set only once, and it's always set before use, then all
11803      uses must have the same last value, even if it's not from this basic
11804      block.  */
11805
11806   if (value == 0
11807       || (rsp->last_set_label < label_tick_ebb_start
11808           && (regno < FIRST_PSEUDO_REGISTER
11809               || REG_N_SETS (regno) != 1
11810               || REGNO_REG_SET_P
11811                  (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
11812     return 0;
11813
11814   /* If the value was set in a later insn than the ones we are processing,
11815      we can't use it even if the register was only set once.  */
11816   if (rsp->last_set_label == label_tick
11817       && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
11818     return 0;
11819
11820   /* If the value has all its registers valid, return it.  */
11821   if (get_last_value_validate (&value, rsp->last_set,
11822                                rsp->last_set_label, 0))
11823     return value;
11824
11825   /* Otherwise, make a copy and replace any invalid register with
11826      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
11827
11828   value = copy_rtx (value);
11829   if (get_last_value_validate (&value, rsp->last_set,
11830                                rsp->last_set_label, 1))
11831     return value;
11832
11833   return 0;
11834 }
11835 \f
11836 /* Return nonzero if expression X refers to a REG or to memory
11837    that is set in an instruction more recent than FROM_LUID.  */
11838
11839 static int
11840 use_crosses_set_p (const_rtx x, int from_luid)
11841 {
11842   const char *fmt;
11843   int i;
11844   enum rtx_code code = GET_CODE (x);
11845
11846   if (code == REG)
11847     {
11848       unsigned int regno = REGNO (x);
11849       unsigned endreg = END_REGNO (x);
11850
11851 #ifdef PUSH_ROUNDING
11852       /* Don't allow uses of the stack pointer to be moved,
11853          because we don't know whether the move crosses a push insn.  */
11854       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11855         return 1;
11856 #endif
11857       for (; regno < endreg; regno++)
11858         {
11859           reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
11860           if (rsp->last_set
11861               && rsp->last_set_label == label_tick
11862               && DF_INSN_LUID (rsp->last_set) > from_luid)
11863             return 1;
11864         }
11865       return 0;
11866     }
11867
11868   if (code == MEM && mem_last_set > from_luid)
11869     return 1;
11870
11871   fmt = GET_RTX_FORMAT (code);
11872
11873   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11874     {
11875       if (fmt[i] == 'E')
11876         {
11877           int j;
11878           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11879             if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
11880               return 1;
11881         }
11882       else if (fmt[i] == 'e'
11883                && use_crosses_set_p (XEXP (x, i), from_luid))
11884         return 1;
11885     }
11886   return 0;
11887 }
11888 \f
11889 /* Define three variables used for communication between the following
11890    routines.  */
11891
11892 static unsigned int reg_dead_regno, reg_dead_endregno;
11893 static int reg_dead_flag;
11894
11895 /* Function called via note_stores from reg_dead_at_p.
11896
11897    If DEST is within [reg_dead_regno, reg_dead_endregno), set
11898    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
11899
11900 static void
11901 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
11902 {
11903   unsigned int regno, endregno;
11904
11905   if (!REG_P (dest))
11906     return;
11907
11908   regno = REGNO (dest);
11909   endregno = END_REGNO (dest);
11910   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11911     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11912 }
11913
11914 /* Return nonzero if REG is known to be dead at INSN.
11915
11916    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
11917    referencing REG, it is dead.  If we hit a SET referencing REG, it is
11918    live.  Otherwise, see if it is live or dead at the start of the basic
11919    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
11920    must be assumed to be always live.  */
11921
11922 static int
11923 reg_dead_at_p (rtx reg, rtx insn)
11924 {
11925   basic_block block;
11926   unsigned int i;
11927
11928   /* Set variables for reg_dead_at_p_1.  */
11929   reg_dead_regno = REGNO (reg);
11930   reg_dead_endregno = END_REGNO (reg);
11931
11932   reg_dead_flag = 0;
11933
11934   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
11935      we allow the machine description to decide whether use-and-clobber
11936      patterns are OK.  */
11937   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11938     {
11939       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11940         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11941           return 0;
11942     }
11943
11944   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11945      beginning of function.  */
11946   for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11947        insn = prev_nonnote_insn (insn))
11948     {
11949       note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11950       if (reg_dead_flag)
11951         return reg_dead_flag == 1 ? 1 : 0;
11952
11953       if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11954         return 1;
11955     }
11956
11957   /* Get the basic block that we were in.  */
11958   if (insn == 0)
11959     block = ENTRY_BLOCK_PTR->next_bb;
11960   else
11961     {
11962       FOR_EACH_BB (block)
11963         if (insn == BB_HEAD (block))
11964           break;
11965
11966       if (block == EXIT_BLOCK_PTR)
11967         return 0;
11968     }
11969
11970   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11971     if (REGNO_REG_SET_P (df_get_live_in (block), i))
11972       return 0;
11973
11974   return 1;
11975 }
11976 \f
11977 /* Note hard registers in X that are used.  */
11978
11979 static void
11980 mark_used_regs_combine (rtx x)
11981 {
11982   RTX_CODE code = GET_CODE (x);
11983   unsigned int regno;
11984   int i;
11985
11986   switch (code)
11987     {
11988     case LABEL_REF:
11989     case SYMBOL_REF:
11990     case CONST_INT:
11991     case CONST:
11992     case CONST_DOUBLE:
11993     case CONST_VECTOR:
11994     case PC:
11995     case ADDR_VEC:
11996     case ADDR_DIFF_VEC:
11997     case ASM_INPUT:
11998 #ifdef HAVE_cc0
11999     /* CC0 must die in the insn after it is set, so we don't need to take
12000        special note of it here.  */
12001     case CC0:
12002 #endif
12003       return;
12004
12005     case CLOBBER:
12006       /* If we are clobbering a MEM, mark any hard registers inside the
12007          address as used.  */
12008       if (MEM_P (XEXP (x, 0)))
12009         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12010       return;
12011
12012     case REG:
12013       regno = REGNO (x);
12014       /* A hard reg in a wide mode may really be multiple registers.
12015          If so, mark all of them just like the first.  */
12016       if (regno < FIRST_PSEUDO_REGISTER)
12017         {
12018           /* None of this applies to the stack, frame or arg pointers.  */
12019           if (regno == STACK_POINTER_REGNUM
12020 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12021               || regno == HARD_FRAME_POINTER_REGNUM
12022 #endif
12023 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12024               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12025 #endif
12026               || regno == FRAME_POINTER_REGNUM)
12027             return;
12028
12029           add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12030         }
12031       return;
12032
12033     case SET:
12034       {
12035         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12036            the address.  */
12037         rtx testreg = SET_DEST (x);
12038
12039         while (GET_CODE (testreg) == SUBREG
12040                || GET_CODE (testreg) == ZERO_EXTRACT
12041                || GET_CODE (testreg) == STRICT_LOW_PART)
12042           testreg = XEXP (testreg, 0);
12043
12044         if (MEM_P (testreg))
12045           mark_used_regs_combine (XEXP (testreg, 0));
12046
12047         mark_used_regs_combine (SET_SRC (x));
12048       }
12049       return;
12050
12051     default:
12052       break;
12053     }
12054
12055   /* Recursively scan the operands of this expression.  */
12056
12057   {
12058     const char *fmt = GET_RTX_FORMAT (code);
12059
12060     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12061       {
12062         if (fmt[i] == 'e')
12063           mark_used_regs_combine (XEXP (x, i));
12064         else if (fmt[i] == 'E')
12065           {
12066             int j;
12067
12068             for (j = 0; j < XVECLEN (x, i); j++)
12069               mark_used_regs_combine (XVECEXP (x, i, j));
12070           }
12071       }
12072   }
12073 }
12074 \f
12075 /* Remove register number REGNO from the dead registers list of INSN.
12076
12077    Return the note used to record the death, if there was one.  */
12078
12079 rtx
12080 remove_death (unsigned int regno, rtx insn)
12081 {
12082   rtx note = find_regno_note (insn, REG_DEAD, regno);
12083
12084   if (note)
12085     remove_note (insn, note);
12086
12087   return note;
12088 }
12089
12090 /* For each register (hardware or pseudo) used within expression X, if its
12091    death is in an instruction with luid between FROM_LUID (inclusive) and
12092    TO_INSN (exclusive), put a REG_DEAD note for that register in the
12093    list headed by PNOTES.
12094
12095    That said, don't move registers killed by maybe_kill_insn.
12096
12097    This is done when X is being merged by combination into TO_INSN.  These
12098    notes will then be distributed as needed.  */
12099
12100 static void
12101 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12102              rtx *pnotes)
12103 {
12104   const char *fmt;
12105   int len, i;
12106   enum rtx_code code = GET_CODE (x);
12107
12108   if (code == REG)
12109     {
12110       unsigned int regno = REGNO (x);
12111       rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12112
12113       /* Don't move the register if it gets killed in between from and to.  */
12114       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12115           && ! reg_referenced_p (x, maybe_kill_insn))
12116         return;
12117
12118       if (where_dead
12119           && DF_INSN_LUID (where_dead) >= from_luid
12120           && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12121         {
12122           rtx note = remove_death (regno, where_dead);
12123
12124           /* It is possible for the call above to return 0.  This can occur
12125              when last_death points to I2 or I1 that we combined with.
12126              In that case make a new note.
12127
12128              We must also check for the case where X is a hard register
12129              and NOTE is a death note for a range of hard registers
12130              including X.  In that case, we must put REG_DEAD notes for
12131              the remaining registers in place of NOTE.  */
12132
12133           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12134               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12135                   > GET_MODE_SIZE (GET_MODE (x))))
12136             {
12137               unsigned int deadregno = REGNO (XEXP (note, 0));
12138               unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12139               unsigned int ourend = END_HARD_REGNO (x);
12140               unsigned int i;
12141
12142               for (i = deadregno; i < deadend; i++)
12143                 if (i < regno || i >= ourend)
12144                   REG_NOTES (where_dead)
12145                     = gen_rtx_EXPR_LIST (REG_DEAD,
12146                                          regno_reg_rtx[i],
12147                                          REG_NOTES (where_dead));
12148             }
12149
12150           /* If we didn't find any note, or if we found a REG_DEAD note that
12151              covers only part of the given reg, and we have a multi-reg hard
12152              register, then to be safe we must check for REG_DEAD notes
12153              for each register other than the first.  They could have
12154              their own REG_DEAD notes lying around.  */
12155           else if ((note == 0
12156                     || (note != 0
12157                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12158                             < GET_MODE_SIZE (GET_MODE (x)))))
12159                    && regno < FIRST_PSEUDO_REGISTER
12160                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12161             {
12162               unsigned int ourend = END_HARD_REGNO (x);
12163               unsigned int i, offset;
12164               rtx oldnotes = 0;
12165
12166               if (note)
12167                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12168               else
12169                 offset = 1;
12170
12171               for (i = regno + offset; i < ourend; i++)
12172                 move_deaths (regno_reg_rtx[i],
12173                              maybe_kill_insn, from_luid, to_insn, &oldnotes);
12174             }
12175
12176           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12177             {
12178               XEXP (note, 1) = *pnotes;
12179               *pnotes = note;
12180             }
12181           else
12182             *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
12183         }
12184
12185       return;
12186     }
12187
12188   else if (GET_CODE (x) == SET)
12189     {
12190       rtx dest = SET_DEST (x);
12191
12192       move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12193
12194       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12195          that accesses one word of a multi-word item, some
12196          piece of everything register in the expression is used by
12197          this insn, so remove any old death.  */
12198       /* ??? So why do we test for equality of the sizes?  */
12199
12200       if (GET_CODE (dest) == ZERO_EXTRACT
12201           || GET_CODE (dest) == STRICT_LOW_PART
12202           || (GET_CODE (dest) == SUBREG
12203               && (((GET_MODE_SIZE (GET_MODE (dest))
12204                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12205                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12206                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12207         {
12208           move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
12209           return;
12210         }
12211
12212       /* If this is some other SUBREG, we know it replaces the entire
12213          value, so use that as the destination.  */
12214       if (GET_CODE (dest) == SUBREG)
12215         dest = SUBREG_REG (dest);
12216
12217       /* If this is a MEM, adjust deaths of anything used in the address.
12218          For a REG (the only other possibility), the entire value is
12219          being replaced so the old value is not used in this insn.  */
12220
12221       if (MEM_P (dest))
12222         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
12223                      to_insn, pnotes);
12224       return;
12225     }
12226
12227   else if (GET_CODE (x) == CLOBBER)
12228     return;
12229
12230   len = GET_RTX_LENGTH (code);
12231   fmt = GET_RTX_FORMAT (code);
12232
12233   for (i = 0; i < len; i++)
12234     {
12235       if (fmt[i] == 'E')
12236         {
12237           int j;
12238           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12239             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
12240                          to_insn, pnotes);
12241         }
12242       else if (fmt[i] == 'e')
12243         move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
12244     }
12245 }
12246 \f
12247 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12248    pattern of an insn.  X must be a REG.  */
12249
12250 static int
12251 reg_bitfield_target_p (rtx x, rtx body)
12252 {
12253   int i;
12254
12255   if (GET_CODE (body) == SET)
12256     {
12257       rtx dest = SET_DEST (body);
12258       rtx target;
12259       unsigned int regno, tregno, endregno, endtregno;
12260
12261       if (GET_CODE (dest) == ZERO_EXTRACT)
12262         target = XEXP (dest, 0);
12263       else if (GET_CODE (dest) == STRICT_LOW_PART)
12264         target = SUBREG_REG (XEXP (dest, 0));
12265       else
12266         return 0;
12267
12268       if (GET_CODE (target) == SUBREG)
12269         target = SUBREG_REG (target);
12270
12271       if (!REG_P (target))
12272         return 0;
12273
12274       tregno = REGNO (target), regno = REGNO (x);
12275       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12276         return target == x;
12277
12278       endtregno = end_hard_regno (GET_MODE (target), tregno);
12279       endregno = end_hard_regno (GET_MODE (x), regno);
12280
12281       return endregno > tregno && regno < endtregno;
12282     }
12283
12284   else if (GET_CODE (body) == PARALLEL)
12285     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12286       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12287         return 1;
12288
12289   return 0;
12290 }
12291 \f
12292 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12293    as appropriate.  I3 and I2 are the insns resulting from the combination
12294    insns including FROM (I2 may be zero).
12295
12296    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12297    not need REG_DEAD notes because they are being substituted for.  This
12298    saves searching in the most common cases.
12299
12300    Each note in the list is either ignored or placed on some insns, depending
12301    on the type of note.  */
12302
12303 static void
12304 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
12305                   rtx elim_i1)
12306 {
12307   rtx note, next_note;
12308   rtx tem;
12309
12310   for (note = notes; note; note = next_note)
12311     {
12312       rtx place = 0, place2 = 0;
12313
12314       next_note = XEXP (note, 1);
12315       switch (REG_NOTE_KIND (note))
12316         {
12317         case REG_BR_PROB:
12318         case REG_BR_PRED:
12319           /* Doesn't matter much where we put this, as long as it's somewhere.
12320              It is preferable to keep these notes on branches, which is most
12321              likely to be i3.  */
12322           place = i3;
12323           break;
12324
12325         case REG_VALUE_PROFILE:
12326           /* Just get rid of this note, as it is unused later anyway.  */
12327           break;
12328
12329         case REG_NON_LOCAL_GOTO:
12330           if (JUMP_P (i3))
12331             place = i3;
12332           else
12333             {
12334               gcc_assert (i2 && JUMP_P (i2));
12335               place = i2;
12336             }
12337           break;
12338
12339         case REG_EH_REGION:
12340           /* These notes must remain with the call or trapping instruction.  */
12341           if (CALL_P (i3))
12342             place = i3;
12343           else if (i2 && CALL_P (i2))
12344             place = i2;
12345           else
12346             {
12347               gcc_assert (flag_non_call_exceptions);
12348               if (may_trap_p (i3))
12349                 place = i3;
12350               else if (i2 && may_trap_p (i2))
12351                 place = i2;
12352               /* ??? Otherwise assume we've combined things such that we
12353                  can now prove that the instructions can't trap.  Drop the
12354                  note in this case.  */
12355             }
12356           break;
12357
12358         case REG_NORETURN:
12359         case REG_SETJMP:
12360           /* These notes must remain with the call.  It should not be
12361              possible for both I2 and I3 to be a call.  */
12362           if (CALL_P (i3))
12363             place = i3;
12364           else
12365             {
12366               gcc_assert (i2 && CALL_P (i2));
12367               place = i2;
12368             }
12369           break;
12370
12371         case REG_UNUSED:
12372           /* Any clobbers for i3 may still exist, and so we must process
12373              REG_UNUSED notes from that insn.
12374
12375              Any clobbers from i2 or i1 can only exist if they were added by
12376              recog_for_combine.  In that case, recog_for_combine created the
12377              necessary REG_UNUSED notes.  Trying to keep any original
12378              REG_UNUSED notes from these insns can cause incorrect output
12379              if it is for the same register as the original i3 dest.
12380              In that case, we will notice that the register is set in i3,
12381              and then add a REG_UNUSED note for the destination of i3, which
12382              is wrong.  However, it is possible to have REG_UNUSED notes from
12383              i2 or i1 for register which were both used and clobbered, so
12384              we keep notes from i2 or i1 if they will turn into REG_DEAD
12385              notes.  */
12386
12387           /* If this register is set or clobbered in I3, put the note there
12388              unless there is one already.  */
12389           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12390             {
12391               if (from_insn != i3)
12392                 break;
12393
12394               if (! (REG_P (XEXP (note, 0))
12395                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12396                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12397                 place = i3;
12398             }
12399           /* Otherwise, if this register is used by I3, then this register
12400              now dies here, so we must put a REG_DEAD note here unless there
12401              is one already.  */
12402           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12403                    && ! (REG_P (XEXP (note, 0))
12404                          ? find_regno_note (i3, REG_DEAD,
12405                                             REGNO (XEXP (note, 0)))
12406                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12407             {
12408               PUT_REG_NOTE_KIND (note, REG_DEAD);
12409               place = i3;
12410             }
12411           break;
12412
12413         case REG_EQUAL:
12414         case REG_EQUIV:
12415         case REG_NOALIAS:
12416           /* These notes say something about results of an insn.  We can
12417              only support them if they used to be on I3 in which case they
12418              remain on I3.  Otherwise they are ignored.
12419
12420              If the note refers to an expression that is not a constant, we
12421              must also ignore the note since we cannot tell whether the
12422              equivalence is still true.  It might be possible to do
12423              slightly better than this (we only have a problem if I2DEST
12424              or I1DEST is present in the expression), but it doesn't
12425              seem worth the trouble.  */
12426
12427           if (from_insn == i3
12428               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12429             place = i3;
12430           break;
12431
12432         case REG_INC:
12433         case REG_NO_CONFLICT:
12434           /* These notes say something about how a register is used.  They must
12435              be present on any use of the register in I2 or I3.  */
12436           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12437             place = i3;
12438
12439           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12440             {
12441               if (place)
12442                 place2 = i2;
12443               else
12444                 place = i2;
12445             }
12446           break;
12447
12448         case REG_LABEL_TARGET:
12449         case REG_LABEL_OPERAND:
12450           /* This can show up in several ways -- either directly in the
12451              pattern, or hidden off in the constant pool with (or without?)
12452              a REG_EQUAL note.  */
12453           /* ??? Ignore the without-reg_equal-note problem for now.  */
12454           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12455               || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12456                   && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12457                   && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12458             place = i3;
12459
12460           if (i2
12461               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12462                   || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12463                       && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12464                       && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12465             {
12466               if (place)
12467                 place2 = i2;
12468               else
12469                 place = i2;
12470             }
12471
12472           /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
12473              as a JUMP_LABEL or decrement LABEL_NUSES if it's already
12474              there.  */
12475           if (place && JUMP_P (place)
12476               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12477               && (JUMP_LABEL (place) == NULL
12478                   || JUMP_LABEL (place) == XEXP (note, 0)))
12479             {
12480               rtx label = JUMP_LABEL (place);
12481
12482               if (!label)
12483                 JUMP_LABEL (place) = XEXP (note, 0);
12484               else if (LABEL_P (label))
12485                 LABEL_NUSES (label)--;
12486             }
12487
12488           if (place2 && JUMP_P (place2)
12489               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12490               && (JUMP_LABEL (place2) == NULL
12491                   || JUMP_LABEL (place2) == XEXP (note, 0)))
12492             {
12493               rtx label = JUMP_LABEL (place2);
12494
12495               if (!label)
12496                 JUMP_LABEL (place2) = XEXP (note, 0);
12497               else if (LABEL_P (label))
12498                 LABEL_NUSES (label)--;
12499               place2 = 0;
12500             }
12501           break;
12502
12503         case REG_NONNEG:
12504           /* This note says something about the value of a register prior
12505              to the execution of an insn.  It is too much trouble to see
12506              if the note is still correct in all situations.  It is better
12507              to simply delete it.  */
12508           break;
12509
12510         case REG_LIBCALL_ID:
12511           /* If the insn previously containing this note still exists,
12512              put it back where it was.  Otherwise move it to the previous
12513              insn.  */
12514           if (!NOTE_P (from_insn))
12515             place = from_insn;
12516           else
12517             place = prev_real_insn (from_insn);
12518           break;
12519         case REG_RETVAL:
12520           /* If the insn previously containing this note still exists,
12521              put it back where it was.  Otherwise move it to the previous
12522              insn.  Adjust the corresponding REG_LIBCALL note.  */
12523           if (!NOTE_P (from_insn))
12524             place = from_insn;
12525           else
12526             {
12527               tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12528               place = prev_real_insn (from_insn);
12529               if (tem && place)
12530                 XEXP (tem, 0) = place;
12531               /* If we're deleting the last remaining instruction of a
12532                  libcall sequence, don't add the notes.  */
12533               else if (XEXP (note, 0) == from_insn)
12534                 tem = place = 0;
12535               /* Don't add the dangling REG_RETVAL note.  */
12536               else if (! tem)
12537                 place = 0;
12538             }
12539           break;
12540
12541         case REG_LIBCALL:
12542           /* This is handled similarly to REG_RETVAL.  */
12543           if (!NOTE_P (from_insn))
12544             place = from_insn;
12545           else
12546             {
12547               tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12548               place = next_real_insn (from_insn);
12549               if (tem && place)
12550                 XEXP (tem, 0) = place;
12551               /* If we're deleting the last remaining instruction of a
12552                  libcall sequence, don't add the notes.  */
12553               else if (XEXP (note, 0) == from_insn)
12554                 tem = place = 0;
12555               /* Don't add the dangling REG_LIBCALL note.  */
12556               else if (! tem)
12557                 place = 0;
12558             }
12559           break;
12560
12561         case REG_DEAD:
12562           /* If we replaced the right hand side of FROM_INSN with a
12563              REG_EQUAL note, the original use of the dying register
12564              will not have been combined into I3 and I2.  In such cases,
12565              FROM_INSN is guaranteed to be the first of the combined
12566              instructions, so we simply need to search back before
12567              FROM_INSN for the previous use or set of this register,
12568              then alter the notes there appropriately.
12569
12570              If the register is used as an input in I3, it dies there.
12571              Similarly for I2, if it is nonzero and adjacent to I3.
12572
12573              If the register is not used as an input in either I3 or I2
12574              and it is not one of the registers we were supposed to eliminate,
12575              there are two possibilities.  We might have a non-adjacent I2
12576              or we might have somehow eliminated an additional register
12577              from a computation.  For example, we might have had A & B where
12578              we discover that B will always be zero.  In this case we will
12579              eliminate the reference to A.
12580
12581              In both cases, we must search to see if we can find a previous
12582              use of A and put the death note there.  */
12583
12584           if (from_insn
12585               && from_insn == i2mod
12586               && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12587             tem = from_insn;
12588           else
12589             {
12590               if (from_insn
12591                   && CALL_P (from_insn)
12592                   && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12593                 place = from_insn;
12594               else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12595                 place = i3;
12596               else if (i2 != 0 && next_nonnote_insn (i2) == i3
12597                        && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12598                 place = i2;
12599               else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12600                         && !(i2mod
12601                              && reg_overlap_mentioned_p (XEXP (note, 0),
12602                                                          i2mod_old_rhs)))
12603                        || rtx_equal_p (XEXP (note, 0), elim_i1))
12604                 break;
12605               tem = i3;
12606             }
12607
12608           if (place == 0)
12609             {
12610               basic_block bb = this_basic_block;
12611
12612               for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12613                 {
12614                   if (! INSN_P (tem))
12615                     {
12616                       if (tem == BB_HEAD (bb))
12617                         break;
12618                       continue;
12619                     }
12620
12621                   /* If the register is being set at TEM, see if that is all
12622                      TEM is doing.  If so, delete TEM.  Otherwise, make this
12623                      into a REG_UNUSED note instead. Don't delete sets to
12624                      global register vars.  */
12625                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12626                        || !global_regs[REGNO (XEXP (note, 0))])
12627                       && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12628                     {
12629                       rtx set = single_set (tem);
12630                       rtx inner_dest = 0;
12631 #ifdef HAVE_cc0
12632                       rtx cc0_setter = NULL_RTX;
12633 #endif
12634
12635                       if (set != 0)
12636                         for (inner_dest = SET_DEST (set);
12637                              (GET_CODE (inner_dest) == STRICT_LOW_PART
12638                               || GET_CODE (inner_dest) == SUBREG
12639                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
12640                              inner_dest = XEXP (inner_dest, 0))
12641                           ;
12642
12643                       /* Verify that it was the set, and not a clobber that
12644                          modified the register.
12645
12646                          CC0 targets must be careful to maintain setter/user
12647                          pairs.  If we cannot delete the setter due to side
12648                          effects, mark the user with an UNUSED note instead
12649                          of deleting it.  */
12650
12651                       if (set != 0 && ! side_effects_p (SET_SRC (set))
12652                           && rtx_equal_p (XEXP (note, 0), inner_dest)
12653 #ifdef HAVE_cc0
12654                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12655                               || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12656                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12657 #endif
12658                           )
12659                         {
12660                           /* Move the notes and links of TEM elsewhere.
12661                              This might delete other dead insns recursively.
12662                              First set the pattern to something that won't use
12663                              any register.  */
12664                           rtx old_notes = REG_NOTES (tem);
12665
12666                           PATTERN (tem) = pc_rtx;
12667                           REG_NOTES (tem) = NULL;
12668
12669                           distribute_notes (old_notes, tem, tem, NULL_RTX,
12670                                             NULL_RTX, NULL_RTX);
12671                           distribute_links (LOG_LINKS (tem));
12672
12673                           SET_INSN_DELETED (tem);
12674
12675 #ifdef HAVE_cc0
12676                           /* Delete the setter too.  */
12677                           if (cc0_setter)
12678                             {
12679                               PATTERN (cc0_setter) = pc_rtx;
12680                               old_notes = REG_NOTES (cc0_setter);
12681                               REG_NOTES (cc0_setter) = NULL;
12682
12683                               distribute_notes (old_notes, cc0_setter,
12684                                                 cc0_setter, NULL_RTX,
12685                                                 NULL_RTX, NULL_RTX);
12686                               distribute_links (LOG_LINKS (cc0_setter));
12687
12688                               SET_INSN_DELETED (cc0_setter);
12689                             }
12690 #endif
12691                         }
12692                       else
12693                         {
12694                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
12695
12696                           /*  If there isn't already a REG_UNUSED note, put one
12697                               here.  Do not place a REG_DEAD note, even if
12698                               the register is also used here; that would not
12699                               match the algorithm used in lifetime analysis
12700                               and can cause the consistency check in the
12701                               scheduler to fail.  */
12702                           if (! find_regno_note (tem, REG_UNUSED,
12703                                                  REGNO (XEXP (note, 0))))
12704                             place = tem;
12705                           break;
12706                         }
12707                     }
12708                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12709                            || (CALL_P (tem)
12710                                && find_reg_fusage (tem, USE, XEXP (note, 0))))
12711                     {
12712                       place = tem;
12713
12714                       /* If we are doing a 3->2 combination, and we have a
12715                          register which formerly died in i3 and was not used
12716                          by i2, which now no longer dies in i3 and is used in
12717                          i2 but does not die in i2, and place is between i2
12718                          and i3, then we may need to move a link from place to
12719                          i2.  */
12720                       if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
12721                           && from_insn
12722                           && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
12723                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12724                         {
12725                           rtx links = LOG_LINKS (place);
12726                           LOG_LINKS (place) = 0;
12727                           distribute_links (links);
12728                         }
12729                       break;
12730                     }
12731
12732                   if (tem == BB_HEAD (bb))
12733                     break;
12734                 }
12735
12736             }
12737
12738           /* If the register is set or already dead at PLACE, we needn't do
12739              anything with this note if it is still a REG_DEAD note.
12740              We check here if it is set at all, not if is it totally replaced,
12741              which is what `dead_or_set_p' checks, so also check for it being
12742              set partially.  */
12743
12744           if (place && REG_NOTE_KIND (note) == REG_DEAD)
12745             {
12746               unsigned int regno = REGNO (XEXP (note, 0));
12747               reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12748
12749               if (dead_or_set_p (place, XEXP (note, 0))
12750                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12751                 {
12752                   /* Unless the register previously died in PLACE, clear
12753                      last_death.  [I no longer understand why this is
12754                      being done.] */
12755                   if (rsp->last_death != place)
12756                     rsp->last_death = 0;
12757                   place = 0;
12758                 }
12759               else
12760                 rsp->last_death = place;
12761
12762               /* If this is a death note for a hard reg that is occupying
12763                  multiple registers, ensure that we are still using all
12764                  parts of the object.  If we find a piece of the object
12765                  that is unused, we must arrange for an appropriate REG_DEAD
12766                  note to be added for it.  However, we can't just emit a USE
12767                  and tag the note to it, since the register might actually
12768                  be dead; so we recourse, and the recursive call then finds
12769                  the previous insn that used this register.  */
12770
12771               if (place && regno < FIRST_PSEUDO_REGISTER
12772                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12773                 {
12774                   unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
12775                   int all_used = 1;
12776                   unsigned int i;
12777
12778                   for (i = regno; i < endregno; i++)
12779                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12780                          && ! find_regno_fusage (place, USE, i))
12781                         || dead_or_set_regno_p (place, i))
12782                       all_used = 0;
12783
12784                   if (! all_used)
12785                     {
12786                       /* Put only REG_DEAD notes for pieces that are
12787                          not already dead or set.  */
12788
12789                       for (i = regno; i < endregno;
12790                            i += hard_regno_nregs[i][reg_raw_mode[i]])
12791                         {
12792                           rtx piece = regno_reg_rtx[i];
12793                           basic_block bb = this_basic_block;
12794
12795                           if (! dead_or_set_p (place, piece)
12796                               && ! reg_bitfield_target_p (piece,
12797                                                           PATTERN (place)))
12798                             {
12799                               rtx new_note
12800                                 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12801
12802                               distribute_notes (new_note, place, place,
12803                                                 NULL_RTX, NULL_RTX, NULL_RTX);
12804                             }
12805                           else if (! refers_to_regno_p (i, i + 1,
12806                                                         PATTERN (place), 0)
12807                                    && ! find_regno_fusage (place, USE, i))
12808                             for (tem = PREV_INSN (place); ;
12809                                  tem = PREV_INSN (tem))
12810                               {
12811                                 if (! INSN_P (tem))
12812                                   {
12813                                     if (tem == BB_HEAD (bb))
12814                                       break;
12815                                     continue;
12816                                   }
12817                                 if (dead_or_set_p (tem, piece)
12818                                     || reg_bitfield_target_p (piece,
12819                                                               PATTERN (tem)))
12820                                   {
12821                                     REG_NOTES (tem)
12822                                       = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12823                                                            REG_NOTES (tem));
12824                                     break;
12825                                   }
12826                               }
12827
12828                         }
12829
12830                       place = 0;
12831                     }
12832                 }
12833             }
12834           break;
12835
12836         default:
12837           /* Any other notes should not be present at this point in the
12838              compilation.  */
12839           gcc_unreachable ();
12840         }
12841
12842       if (place)
12843         {
12844           XEXP (note, 1) = REG_NOTES (place);
12845           REG_NOTES (place) = note;
12846         }
12847
12848       if (place2)
12849         REG_NOTES (place2)
12850           = gen_rtx_fmt_ee (GET_CODE (note), REG_NOTE_KIND (note),
12851                             XEXP (note, 0), REG_NOTES (place2));
12852     }
12853 }
12854 \f
12855 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12856    I3, I2, and I1 to new locations.  This is also called to add a link
12857    pointing at I3 when I3's destination is changed.  */
12858
12859 static void
12860 distribute_links (rtx links)
12861 {
12862   rtx link, next_link;
12863
12864   for (link = links; link; link = next_link)
12865     {
12866       rtx place = 0;
12867       rtx insn;
12868       rtx set, reg;
12869
12870       next_link = XEXP (link, 1);
12871
12872       /* If the insn that this link points to is a NOTE or isn't a single
12873          set, ignore it.  In the latter case, it isn't clear what we
12874          can do other than ignore the link, since we can't tell which
12875          register it was for.  Such links wouldn't be used by combine
12876          anyway.
12877
12878          It is not possible for the destination of the target of the link to
12879          have been changed by combine.  The only potential of this is if we
12880          replace I3, I2, and I1 by I3 and I2.  But in that case the
12881          destination of I2 also remains unchanged.  */
12882
12883       if (NOTE_P (XEXP (link, 0))
12884           || (set = single_set (XEXP (link, 0))) == 0)
12885         continue;
12886
12887       reg = SET_DEST (set);
12888       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12889              || GET_CODE (reg) == STRICT_LOW_PART)
12890         reg = XEXP (reg, 0);
12891
12892       /* A LOG_LINK is defined as being placed on the first insn that uses
12893          a register and points to the insn that sets the register.  Start
12894          searching at the next insn after the target of the link and stop
12895          when we reach a set of the register or the end of the basic block.
12896
12897          Note that this correctly handles the link that used to point from
12898          I3 to I2.  Also note that not much searching is typically done here
12899          since most links don't point very far away.  */
12900
12901       for (insn = NEXT_INSN (XEXP (link, 0));
12902            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12903                      || BB_HEAD (this_basic_block->next_bb) != insn));
12904            insn = NEXT_INSN (insn))
12905         if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12906           {
12907             if (reg_referenced_p (reg, PATTERN (insn)))
12908               place = insn;
12909             break;
12910           }
12911         else if (CALL_P (insn)
12912                  && find_reg_fusage (insn, USE, reg))
12913           {
12914             place = insn;
12915             break;
12916           }
12917         else if (INSN_P (insn) && reg_set_p (reg, insn))
12918           break;
12919
12920       /* If we found a place to put the link, place it there unless there
12921          is already a link to the same insn as LINK at that point.  */
12922
12923       if (place)
12924         {
12925           rtx link2;
12926
12927           for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12928             if (XEXP (link2, 0) == XEXP (link, 0))
12929               break;
12930
12931           if (link2 == 0)
12932             {
12933               XEXP (link, 1) = LOG_LINKS (place);
12934               LOG_LINKS (place) = link;
12935
12936               /* Set added_links_insn to the earliest insn we added a
12937                  link to.  */
12938               if (added_links_insn == 0
12939                   || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
12940                 added_links_insn = place;
12941             }
12942         }
12943     }
12944 }
12945 \f
12946 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12947    Check whether the expression pointer to by LOC is a register or
12948    memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12949    Otherwise return zero.  */
12950
12951 static int
12952 unmentioned_reg_p_1 (rtx *loc, void *expr)
12953 {
12954   rtx x = *loc;
12955
12956   if (x != NULL_RTX
12957       && (REG_P (x) || MEM_P (x))
12958       && ! reg_mentioned_p (x, (rtx) expr))
12959     return 1;
12960   return 0;
12961 }
12962
12963 /* Check for any register or memory mentioned in EQUIV that is not
12964    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
12965    of EXPR where some registers may have been replaced by constants.  */
12966
12967 static bool
12968 unmentioned_reg_p (rtx equiv, rtx expr)
12969 {
12970   return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12971 }
12972 \f
12973 void
12974 dump_combine_stats (FILE *file)
12975 {
12976   fprintf
12977     (file,
12978      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12979      combine_attempts, combine_merges, combine_extras, combine_successes);
12980 }
12981
12982 void
12983 dump_combine_total_stats (FILE *file)
12984 {
12985   fprintf
12986     (file,
12987      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12988      total_attempts, total_merges, total_extras, total_successes);
12989 }
12990 \f
12991 static bool
12992 gate_handle_combine (void)
12993 {
12994   return (optimize > 0);
12995 }
12996
12997 /* Try combining insns through substitution.  */
12998 static unsigned int
12999 rest_of_handle_combine (void)
13000 {
13001   int rebuild_jump_labels_after_combine;
13002
13003   df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13004   df_note_add_problem ();
13005   df_analyze ();
13006
13007   regstat_init_n_sets_and_refs ();
13008
13009   rebuild_jump_labels_after_combine
13010     = combine_instructions (get_insns (), max_reg_num ());
13011
13012   /* Combining insns may have turned an indirect jump into a
13013      direct jump.  Rebuild the JUMP_LABEL fields of jumping
13014      instructions.  */
13015   if (rebuild_jump_labels_after_combine)
13016     {
13017       timevar_push (TV_JUMP);
13018       rebuild_jump_labels (get_insns ());
13019       cleanup_cfg (0);
13020       timevar_pop (TV_JUMP);
13021     }
13022
13023   regstat_free_n_sets_and_refs ();
13024   return 0;
13025 }
13026
13027 struct tree_opt_pass pass_combine =
13028 {
13029   "combine",                            /* name */
13030   gate_handle_combine,                  /* gate */
13031   rest_of_handle_combine,               /* execute */
13032   NULL,                                 /* sub */
13033   NULL,                                 /* next */
13034   0,                                    /* static_pass_number */
13035   TV_COMBINE,                           /* tv_id */
13036   0,                                    /* properties_required */
13037   0,                                    /* properties_provided */
13038   0,                                    /* properties_destroyed */
13039   0,                                    /* todo_flags_start */
13040   TODO_dump_func |
13041   TODO_df_finish | TODO_verify_rtl_sharing |
13042   TODO_ggc_collect,                     /* todo_flags_finish */
13043   'c'                                   /* letter */
13044 };
13045