| blob | 7e611399f2cd7a7ab60b780a2f6a24cb317004cb |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2018 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with modified_between_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
109 /* Number of attempts to combine instructions in this function. */
113 /* Number of attempts that got as far as substitution in this function. */
117 /* Number of instructions combined with added SETs in this function. */
121 /* Number of instructions combined in this function. */
125 /* Totals over entire compilation. */
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
145 \f
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
160 following ways:
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
175 register's value
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
180 table.
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
198 rtx last_set_value;
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
205 /* Record the value of label_tick when the value for register n is placed in
206 last_set_value. */
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
233 zero.
235 If an entry is zero, it means that we don't know anything special. */
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
250 value. */
253 };
258 /* One plus the highest pseudo for which we track REG_N_SETS.
259 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
260 but during combine_split_insns new pseudos can be created. As we don't have
261 updated DF information in that case, it is hard to initialize the array
262 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
263 so instead of growing the arrays, just assume all newly created pseudos
264 during combine might be set multiple times. */
268 /* Record the luid of the last insn that invalidated memory
269 (anything that writes memory, and subroutine calls, but not pushes). */
273 /* Record the luid of the last CALL_INSN
274 so we can tell whether a potential combination crosses any calls. */
278 /* When `subst' is called, this is the insn that is being modified
279 (by combining in a previous insn). The PATTERN of this insn
280 is still the old pattern partially modified and it should not be
281 looked at, but this may be used to examine the successors of the insn
282 to judge whether a simplification is valid. */
286 /* This is the lowest LUID that `subst' is currently dealing with.
287 get_last_value will not return a value if the register was set at or
288 after this LUID. If not for this mechanism, we could get confused if
289 I2 or I1 in try_combine were an insn that used the old value of a register
290 to obtain a new value. In that case, we might erroneously get the
291 new value of the register when we wanted the old one. */
295 /* This contains any hard registers that are used in newpat; reg_dead_at_p
296 must consider all these registers to be always live. */
300 /* This is an insn to which a LOG_LINKS entry has been added. If this
301 insn is the earlier than I2 or I3, combine should rescan starting at
302 that location. */
306 /* And similarly, for notes. */
310 /* Basic block in which we are performing combines. */
314 \f
315 /* Length of the currently allocated uid_insn_cost array. */
319 /* The following array records the insn_cost for every insn
320 in the instruction stream. */
324 /* The following array records the LOG_LINKS for every insn in the
325 instruction stream as struct insn_link pointers. */
331 };
337 {
341 }
343 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
344 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
346 #define FOR_EACH_LOG_LINK(L, INSN) \
347 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
349 /* Links for LOG_LINKS are allocated from this obstack. */
353 /* Allocate a link. */
357 {
365 }
367 /* Incremented for each basic block. */
371 /* Reset to label_tick for each extended basic block in scanning order. */
375 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
376 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
380 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
381 be safely used. It is zero while computing them and after combine has
382 completed. This former test prevents propagating values based on
383 previously set values, which can be incorrect if a variable is modified
384 in a loop. */
388 \f
389 /* Record one modification to rtl structure
390 to be undone by storing old_contents into *where. */
394 struct undo
395 {
400 };
402 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
403 num_undo says how many are currently recorded.
405 other_insn is nonzero if we have modified some other insn in the process
406 of working on subst_insn. It must be verified too. */
408 struct undobuf
409 {
413 };
417 /* Number of times the pseudo being substituted for
418 was found and replaced. */
423 scalar_int_mode,
426 scalar_int_mode,
498 \f
500 /* It is not safe to use ordinary gen_lowpart in combine.
501 See comments in gen_lowpart_for_combine. */
502 #undef RTL_HOOKS_GEN_LOWPART
503 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
505 /* Our implementation of gen_lowpart never emits a new pseudo. */
506 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
507 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
509 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
510 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
512 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
513 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
515 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
516 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
520 \f
521 /* Convenience wrapper for the canonicalize_comparison target hook.
522 Target hooks cannot use enum rtx_code. */
526 {
530 }
532 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
533 PATTERN can not be split. Otherwise, it returns an insn sequence.
534 This is a wrapper around split_insns which ensures that the
535 reg_stat vector is made larger if the splitter creates a new
536 register. */
540 {
549 }
551 /* This is used by find_single_use to locate an rtx in LOC that
552 contains exactly one use of DEST, which is typically either a REG
553 or CC0. It returns a pointer to the innermost rtx expression
554 containing DEST. Appearances of DEST that are being used to
555 totally replace it are not counted. */
559 {
568 {
572 CASE_CONST_ANY:
578 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
579 of a REG that occupies all of the REG, the insn uses DEST if
580 it is mentioned in the destination or the source. Otherwise, we
581 need just check the source. */
598 }
600 /* If it wasn't one of the common cases above, check each expression and
601 vector of this code. Look for a unique usage of DEST. */
605 {
607 {
612 else
618 /* Duplicate usage. */
620 }
622 {
626 {
632 else
639 }
640 }
641 }
644 }
647 /* See if DEST, produced in INSN, is used only a single time in the
648 sequel. If so, return a pointer to the innermost rtx expression in which
649 it is used.
651 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
653 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
654 care about REG_DEAD notes or LOG_LINKS.
656 Otherwise, we find the single use by finding an insn that has a
657 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
658 only referenced once in that insn, we know that it must be the first
659 and last insn referencing DEST. */
663 {
664 basic_block bb;
670 {
680 }
690 {
696 {
701 }
702 }
705 }
706 \f
707 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
708 insn. The substitution can be undone by undo_all. If INTO is already
709 set to NEWVAL, do not record this change. Because computing NEWVAL might
710 also call SUBST, we have to compute it before we put anything into
711 the undo table. */
713 static void
715 {
722 /* We'd like to catch as many invalid transformations here as
723 possible. Unfortunately, there are way too many mode changes
724 that are perfectly valid, so we'd waste too much effort for
725 little gain doing the checks here. Focus on catching invalid
726 transformations involving integer constants. */
729 {
730 /* Sanity check that we're replacing oldval with a CONST_INT
731 that is a valid sign-extension for the original mode. */
735 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
736 CONST_INT is not valid, because after the replacement, the
737 original mode would be gone. Unfortunately, we can't tell
738 when do_SUBST is called to replace the operand thereof, so we
739 perform this test on oldval instead, checking whether an
740 invalid replacement took place before we got here. */
745 }
749 else
758 }
760 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
762 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
763 for the value of a HOST_WIDE_INT value (including CONST_INT) is
764 not safe. */
766 static void
768 {
777 else
786 }
788 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
790 /* Similar to SUBST, but just substitute the mode. This is used when
791 changing the mode of a pseudo-register, so that any other
792 references to the entry in the regno_reg_rtx array will change as
793 well. */
795 static void
797 {
806 else
815 }
817 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
819 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
821 static void
823 {
832 else
841 }
843 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
844 \f
845 /* Subroutine of try_combine. Determine whether the replacement patterns
846 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_cost
847 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
848 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
849 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
850 of all the instructions can be estimated and the replacements are more
851 expensive than the original sequence. */
853 static bool
856 {
861 /* Lookup the original insn_costs. */
866 {
869 {
873 }
874 else
875 {
879 }
880 }
881 else
882 {
885 }
887 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
888 correct that. */
893 /* Calculate the replacement insn_costs. */
902 {
912 }
913 else
914 {
917 }
920 {
929 optimize_this_for_speed_p);
933 {
936 }
937 else
939 }
941 /* Disallow this combination if both new_cost and old_cost are greater than
942 zero, and new_cost is greater than old cost. */
946 {
965 else
967 }
972 /* Update the uid_insn_cost array with the replacement costs. */
976 {
980 }
983 }
986 /* Delete any insns that copy a register to itself. */
988 static void
990 {
992 basic_block bb;
995 {
997 {
1000 {
1005 }
1006 }
1007 }
1008 }
1010 \f
1011 /* Return false if we do not want to (or cannot) combine DEF. */
1012 static bool
1014 {
1015 /* Do not consider if it is pre/post modification in MEM. */
1021 /* Do not combine frame pointer adjustments. */
1024 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1032 }
1034 /* Return false if we do not want to (or cannot) combine USE. */
1035 static bool
1037 {
1038 /* Do not consider the usage of the stack pointer by function call. */
1043 }
1045 /* Fill in log links field for all insns. */
1047 static void
1049 {
1050 basic_block bb;
1057 /* Pass through each block from the end, recording the uses of each
1058 register and establishing log links when def is encountered.
1059 Note that we do not clear next_use array in order to save time,
1060 so we have to test whether the use is in the same basic block as def.
1062 There are a few cases below when we do not consider the definition or
1063 usage -- these are taken from original flow.c did. Don't ask me why it is
1064 done this way; I don't know and if it works, I don't want to know. */
1067 {
1069 {
1073 /* Log links are created only once. */
1077 {
1093 /* flow.c claimed:
1095 We don't build a LOG_LINK for hard registers contained
1096 in ASM_OPERANDs. If these registers get replaced,
1097 we might wind up changing the semantics of the insn,
1098 even if reload can make what appear to be valid
1099 assignments later. */
1104 /* Don't add duplicate links between instructions. */
1113 }
1118 }
1119 }
1122 }
1124 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1125 true if we found a LOG_LINK that proves that A feeds B. This only works
1126 if there are no instructions between A and B which could have a link
1127 depending on A, since in that case we would not record a link for B.
1128 We also check the implicit dependency created by a cc0 setter/user
1129 pair. */
1131 static bool
1133 {
1141 }
1142 \f
1143 /* Main entry point for combiner. F is the first insn of the function.
1144 NREGS is the first unused pseudo-reg number.
1146 Return nonzero if the combiner has turned an indirect jump
1147 instruction into a direct jump. */
1148 static int
1150 {
1155 basic_block last_bb;
1175 /* Allocate array for insn info. */
1183 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1184 problems when, for example, we have j <<= 1 in a loop. */
1189 /* Scan all SETs and see if we can deduce anything about what
1190 bits are known to be zero for some registers and how many copies
1191 of the sign bit are known to exist for those registers.
1193 Also set any known values so that we can use it while searching
1194 for what bits are known to be set. */
1197 /* Allow the entry block and the first block to fall into the same EBB.
1198 Conceptually the incoming promotions are assigned to the entry block. */
1203 {
1208 label_tick++;
1216 {
1217 rtx links;
1223 insn);
1230 insn);
1232 /* Record the current insn_cost of this instruction. */
1236 {
1239 }
1240 }
1241 }
1245 /* Now scan all the insns in forward order. */
1253 {
1256 /* Ignore instruction combination in basic blocks that are going to
1257 be removed as unreachable anyway. See PR82386. */
1265 label_tick++;
1275 {
1289 /* See if we know about function return values before this
1290 insn based upon SUBREG flags. */
1293 /* See if we can find hardregs and subreg of pseudos in
1294 narrower modes. This could help turning TRUNCATEs
1295 into SUBREGs. */
1298 /* Try this insn with each insn it links back to. */
1304 {
1307 }
1309 /* Try each sequence of three linked insns ending with this one. */
1313 {
1316 /* If the linked insn has been replaced by a note, then there
1317 is no point in pursuing this chain any further. */
1325 {
1328 }
1329 }
1331 /* Try to combine a jump insn that uses CC0
1332 with a preceding insn that sets CC0, and maybe with its
1333 logical predecessor as well.
1334 This is how we make decrement-and-branch insns.
1335 We need this special code because data flow connections
1336 via CC0 do not get entered in LOG_LINKS. */
1343 {
1354 }
1356 /* Do the same for an insn that explicitly references CC0. */
1363 {
1374 }
1376 /* Finally, see if any of the insns that this insn links to
1377 explicitly references CC0. If so, try this insn, that insn,
1378 and its predecessor if it sets CC0. */
1380 {
1392 }
1394 /* Try combining an insn with two different insns whose results it
1395 uses. */
1405 {
1408 }
1410 /* Try four-instruction combinations. */
1413 {
1417 /* If the linked insn has been replaced by a note, then there
1418 is no point in pursuing this chain any further. */
1423 {
1427 /* I0 -> I1 -> I2 -> I3. */
1433 {
1436 }
1437 /* I0, I1 -> I2, I2 -> I3. */
1444 {
1447 }
1448 }
1451 {
1455 /* I0 -> I2; I1, I2 -> I3. */
1461 {
1464 }
1465 /* I0 -> I1; I1, I2 -> I3. */
1471 {
1474 }
1475 }
1476 }
1478 /* Try this insn with each REG_EQUAL note it links back to. */
1480 {
1486 /* Avoid using a register that may already been marked
1487 dead by an earlier instruction. */
1495 {
1496 /* Temporarily replace the set's source with the
1497 contents of the REG_EQUAL note. The insn will
1498 be deleted or recognized by try_combine. */
1509 last_combined_insn);
1512 {
1515 }
1518 }
1519 }
1524 retry:
1525 ;
1526 }
1527 }
1534 /* Clean up. */
1540 {
1543 {
1546 }
1548 }
1558 /* Make recognizer allow volatile MEMs again. */
1562 }
1564 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1566 static void
1568 {
1574 }
1575 \f
1576 /* Set up any promoted values for incoming argument registers. */
1578 static void
1580 {
1581 tree arg;
1586 {
1591 /* Only continue if the incoming argument is in a register. */
1595 /* Determine, if possible, whether all call sites of the current
1596 function lie within the current compilation unit. (This does
1597 take into account the exporting of a function via taking its
1598 address, and so forth.) */
1601 /* The mode and signedness of the argument before any promotions happen
1602 (equal to the mode of the pseudo holding it at that stage). */
1606 /* The mode and signedness of the argument after any source language and
1607 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1611 /* The mode and signedness of the argument as it is actually passed,
1612 see assign_parm_setup_reg in function.c. */
1616 /* The mode of the register in which the argument is being passed. */
1619 /* Eliminate sign extensions in the callee when:
1620 (a) A mode promotion has occurred; */
1623 /* (b) The mode of the register is the same as the mode of
1624 the argument as it is passed; */
1627 /* (c) There's no language level extension; */
1629 ;
1630 /* (c.1) All callers are from the current compilation unit. If that's
1631 the case we don't have to rely on an ABI, we only have to know
1632 what we're generating right now, and we know that we will do the
1633 mode1 to mode2 promotion with the given sign. */
1636 /* (c.2) The combination of the two promotions is useful. This is
1637 true when the signs match, or if the first promotion is unsigned.
1638 In the later case, (sign_extend (zero_extend x)) is the same as
1639 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1645 /* Record that the value was promoted from mode1 to mode3,
1646 so that any sign extension at the head of the current
1647 function may be eliminated. */
1651 }
1652 }
1654 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1655 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1656 because some machines (maybe most) will actually do the sign-extension and
1657 this is the conservative approach.
1659 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1660 kludge. */
1662 static rtx
1664 {
1665 scalar_int_mode int_mode;
1674 }
1676 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1677 and SET. */
1679 static void
1681 rtx x)
1682 {
1692 {
1696 }
1698 /* Don't call nonzero_bits if it cannot change anything. */
1700 {
1705 }
1707 /* Don't call num_sign_bit_copies if it cannot change anything. */
1709 {
1712 {
1716 }
1719 }
1720 }
1722 /* Called via note_stores. If X is a pseudo that is narrower than
1723 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1725 If we are setting only a portion of X and we can't figure out what
1726 portion, assume all bits will be used since we don't know what will
1727 be happening.
1729 Similarly, set how many bits of X are known to be copies of the sign bit
1730 at all locations in the function. This is the smallest number implied
1731 by any set of X. */
1733 static void
1735 {
1737 scalar_int_mode mode;
1741 /* If this register is undefined at the start of the file, we can't
1742 say what its contents were. */
1743 && ! REGNO_REG_SET_P
1747 {
1751 {
1755 }
1757 /* Should not happen as we only using pseduo registers. */
1760 /* If this register is being initialized using itself, and the
1761 register is uninitialized in this basic block, and there are
1762 no LOG_LINKS which set the register, then part of the
1763 register is uninitialized. In that case we can't assume
1764 anything about the number of nonzero bits.
1766 ??? We could do better if we checked this in
1767 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1768 could avoid making assumptions about the insn which initially
1769 sets the register, while still using the information in other
1770 insns. We would have to be careful to check every insn
1771 involved in the combination. */
1777 {
1784 {
1788 }
1789 }
1791 /* If this is a complex assignment, see if we can convert it into a
1792 simple assignment. */
1795 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1796 set what we know about X. */
1802 else
1803 {
1806 }
1807 }
1808 }
1809 \f
1810 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1811 optionally insns that were previously combined into I3 or that will be
1812 combined into the merger of INSN and I3. The order is PRED, PRED2,
1813 INSN, SUCC, SUCC2, I3.
1815 Return 0 if the combination is not allowed for any reason.
1817 If the combination is allowed, *PDEST will be set to the single
1818 destination of INSN and *PSRC to the single source, and this function
1819 will return 1. */
1821 static int
1825 {
1830 rtx link;
1835 {
1837 {
1842 }
1847 }
1851 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1852 or a PARALLEL consisting of such a SET and CLOBBERs.
1854 If INSN has CLOBBER parallel parts, ignore them for our processing.
1855 By definition, these happen during the execution of the insn. When it
1856 is merged with another insn, all bets are off. If they are, in fact,
1857 needed and aren't also supplied in I3, they may be added by
1858 recog_for_combine. Otherwise, it won't match.
1860 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1861 note.
1863 Get the source and destination of INSN. If more than one, can't
1864 combine. */
1870 {
1872 {
1876 {
1877 /* This is important to combine floating point insns
1878 for the SH4 port. */
1880 /* Combining an isolated USE doesn't make sense.
1881 We depend here on combinable_i3pat to reject them. */
1882 /* The code below this loop only verifies that the inputs of
1883 the SET in INSN do not change. We call reg_set_between_p
1884 to verify that the REG in the USE does not change between
1885 I3 and INSN.
1886 If the USE in INSN was for a pseudo register, the matching
1887 insn pattern will likely match any register; combining this
1888 with any other USE would only be safe if we knew that the
1889 used registers have identical values, or if there was
1890 something to tell them apart, e.g. different modes. For
1891 now, we forgo such complicated tests and simply disallow
1892 combining of USES of pseudo registers with any other USE. */
1895 {
1900 do
1901 {
1911 }
1913 }
1916 /* We can ignore CLOBBERs. */
1922 /* Ignore SETs whose result isn't used but not those that
1923 have side-effects. */
1929 /* If we have already found a SET, this is a second one and
1930 so we cannot combine with this insn. */
1938 /* Anything else means we can't combine. */
1940 }
1941 }
1944 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1945 so don't do anything with it. */
1948 }
1949 else
1955 /* The simplification in expand_field_assignment may call back to
1956 get_last_value, so set safe guard here. */
1962 /* Do not eliminate user-specified register if it is in an
1963 asm input because we may break the register asm usage defined
1964 in GCC manual if allow to do so.
1965 Be aware that this may cover more cases than we expect but this
1966 should be harmless. */
1971 /* Don't eliminate a store in the stack pointer. */
1973 /* Don't combine with an insn that sets a register to itself if it has
1974 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1976 /* Can't merge an ASM_OPERANDS. */
1978 /* Can't merge a function call. */
1980 /* Don't eliminate a function call argument. */
1986 /* Don't substitute into an incremented register. */
1990 /* Don't substitute into a non-local goto, this confuses CFG. */
1992 /* Make sure that DEST is not used after INSN but before SUCC, or
1993 after SUCC and before SUCC2, or after SUCC2 but before I3. */
1994 || (!all_adjacent
1995 && ((succ2
2000 || (succ
2001 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
2002 that case SUCC is not in the insn stream, so use SUCC2
2003 instead for this test. */
2005 succ2
2008 /* Make sure that the value that is to be substituted for the register
2009 does not use any registers whose values alter in between. However,
2010 If the insns are adjacent, a use can't cross a set even though we
2011 think it might (this can happen for a sequence of insns each setting
2012 the same destination; last_set of that register might point to
2013 a NOTE). If INSN has a REG_EQUIV note, the register is always
2014 equivalent to the memory so the substitution is valid even if there
2015 are intervening stores. Also, don't move a volatile asm or
2016 UNSPEC_VOLATILE across any other insns. */
2017 || (! all_adjacent
2023 /* Don't combine across a CALL_INSN, because that would possibly
2024 change whether the life span of some REGs crosses calls or not,
2025 and it is a pain to update that information.
2026 Exception: if source is a constant, moving it later can't hurt.
2027 Accept that as a special case. */
2031 /* DEST must either be a REG or CC0. */
2033 {
2034 /* If register alignment is being enforced for multi-word items in all
2035 cases except for parameters, it is possible to have a register copy
2036 insn referencing a hard register that is not allowed to contain the
2037 mode being copied and which would not be valid as an operand of most
2038 insns. Eliminate this problem by not combining with such an insn.
2040 Also, on some machines we don't want to extend the life of a hard
2041 register. */
2046 /* Don't extend the life of a hard register unless it is
2047 user variable (if we have few registers) or it can't
2048 fit into the desired register (meaning something special
2049 is going on).
2050 Also avoid substituting a return register into I3, because
2051 reload can't handle a conflict with constraints of other
2052 inputs. */
2057 }
2065 {
2068 /* If the clobber represents an earlyclobber operand, we must not
2069 substitute an expression containing the clobbered register.
2070 As we do not analyze the constraint strings here, we have to
2071 make the conservative assumption. However, if the register is
2072 a fixed hard reg, the clobber cannot represent any operand;
2073 we leave it up to the machine description to either accept or
2074 reject use-and-clobber patterns. */
2080 }
2082 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2083 or not), reject, unless nothing volatile comes between it and I3 */
2086 {
2087 /* Make sure neither succ nor succ2 contains a volatile reference. */
2092 /* We'll check insns between INSN and I3 below. */
2093 }
2095 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2096 to be an explicit register variable, and was chosen for a reason. */
2102 /* If INSN contains volatile references (specifically volatile MEMs),
2103 we cannot combine across any other volatile references.
2104 Even if INSN doesn't contain volatile references, any intervening
2105 volatile insn might affect machine state. */
2108 ? volatile_refs_p
2115 /* If INSN contains an autoincrement or autodecrement, make sure that
2116 register is not used between there and I3, and not already used in
2117 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2118 Also insist that I3 not be a jump; if it were one
2119 and the incremented register were spilled, we would lose. */
2137 /* Don't combine an insn that follows a CC0-setting insn.
2138 An insn that uses CC0 must not be separated from the one that sets it.
2139 We do, however, allow I2 to follow a CC0-setting insn if that insn
2140 is passed as I1; in that case it will be deleted also.
2141 We also allow combining in this case if all the insns are adjacent
2142 because that would leave the two CC0 insns adjacent as well.
2143 It would be more logical to test whether CC0 occurs inside I1 or I2,
2144 but that would be much slower, and this ought to be equivalent. */
2147 {
2152 }
2154 /* If we get here, we have passed all the tests and the combination is
2155 to be allowed. */
2161 }
2162 \f
2163 /* LOC is the location within I3 that contains its pattern or the component
2164 of a PARALLEL of the pattern. We validate that it is valid for combining.
2166 One problem is if I3 modifies its output, as opposed to replacing it
2167 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2168 doing so would produce an insn that is not equivalent to the original insns.
2170 Consider:
2172 (set (reg:DI 101) (reg:DI 100))
2173 (set (subreg:SI (reg:DI 101) 0) <foo>)
2175 This is NOT equivalent to:
2177 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2178 (set (reg:DI 101) (reg:DI 100))])
2180 Not only does this modify 100 (in which case it might still be valid
2181 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2183 We can also run into a problem if I2 sets a register that I1
2184 uses and I1 gets directly substituted into I3 (not via I2). In that
2185 case, we would be getting the wrong value of I2DEST into I3, so we
2186 must reject the combination. This case occurs when I2 and I1 both
2187 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2188 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2189 of a SET must prevent combination from occurring. The same situation
2190 can occur for I0, in which case I0_NOT_IN_SRC is set.
2192 Before doing the above check, we first try to expand a field assignment
2193 into a set of logical operations.
2195 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2196 we place a register that is both set and used within I3. If more than one
2197 such register is detected, we fail.
2199 Return 1 if the combination is valid, zero otherwise. */
2201 static int
2204 {
2208 {
2213 rtx subdest;
2220 /* Check for the case where I3 modifies its output, as discussed
2221 above. We don't want to prevent pseudos from being combined
2222 into the address of a MEM, so only prevent the combination if
2223 i1 or i2 set the same MEM. */
2233 /* This is the same test done in can_combine_p except we can't test
2234 all_adjacent; we don't have to, since this instruction will stay
2235 in place, thus we are not considering increasing the lifetime of
2236 INNER_DEST.
2238 Also, if this insn sets a function argument, combining it with
2239 something that might need a spill could clobber a previous
2240 function argument; the all_adjacent test in can_combine_p also
2241 checks this; here, we do a more specific test for this case. */
2251 /* If DEST is used in I3, it is being killed in this insn, so
2252 record that for later. We have to consider paradoxical
2253 subregs here, since they kill the whole register, but we
2254 ignore partial subregs, STRICT_LOW_PART, etc.
2255 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2256 STACK_POINTER_REGNUM, since these are always considered to be
2257 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2265 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2271 {
2276 }
2277 }
2280 {
2287 }
2290 }
2291 \f
2292 /* Return 1 if X is an arithmetic expression that contains a multiplication
2293 and division. We don't count multiplications by powers of two here. */
2295 static int
2297 {
2299 {
2315 }
2316 }
2317 \f
2318 /* Determine whether INSN can be used in a combination. Return nonzero if
2319 not. This is used in try_combine to detect early some cases where we
2320 can't perform combinations. */
2322 static int
2324 {
2325 rtx set;
2328 /* If this isn't really an insn, we can't do anything.
2329 This can occur when flow deletes an insn that it has merged into an
2330 auto-increment address. */
2334 /* Never combine loads and stores involving hard regs that are likely
2335 to be spilled. The register allocator can usually handle such
2336 reg-reg moves by tying. If we allow the combiner to make
2337 substitutions of likely-spilled regs, reload might die.
2338 As an exception, we allow combinations involving fixed regs; these are
2339 not available to the register allocator so there's no risk involved. */
2359 }
2361 struct likely_spilled_retval_info
2362 {
2365 };
2367 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2368 hard registers that are known to be written to / clobbered in full. */
2369 static void
2371 {
2388 else
2391 }
2393 /* Return nonzero iff part of the return value is live during INSN, and
2394 it is likely spilled. This can happen when more than one insn is needed
2395 to copy the return value, e.g. when we consider to combine into the
2396 second copy insn for a complex value. */
2398 static int
2400 {
2402 rtx reg;
2405 /* We assume here that no machine mode needs more than
2406 32 hard registers when the value overlaps with a register
2407 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2422 /* Disregard parts of the return value that are set later. */
2431 /* Check if any of the (probably) live return value registers is
2432 likely spilled. */
2433 nregs --;
2434 do
2435 {
2441 }
2443 /* Adjust INSN after we made a change to its destination.
2445 Changing the destination can invalidate notes that say something about
2446 the results of the insn and a LOG_LINK pointing to the insn. */
2448 static void
2450 {
2451 /* For notes, be conservative and simply remove them. */
2454 /* The new insn will have a destination that was previously the destination
2455 of an insn just above it. Call distribute_links to make a LOG_LINK from
2456 the next use of that destination. */
2472 }
2474 /* Return TRUE if combine can reuse reg X in mode MODE.
2475 ADDED_SETS is nonzero if the original set is still required. */
2476 static bool
2478 {
2484 /* Don't change between modes with different underlying register sizes,
2485 since this could lead to invalid subregs. */
2491 /* Allow hard registers if the new mode is legal, and occupies no more
2492 registers than the old mode. */
2497 /* Or a pseudo that is only used once. */
2500 && !added_sets
2502 }
2505 /* Check whether X, the destination of a set, refers to part of
2506 the register specified by REG. */
2508 static bool
2510 {
2511 /* Check that reg is an integer mode register. */
2522 }
2524 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2525 Note that the INSN should be deleted *after* removing dead edges, so
2526 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2527 but not for a (set (pc) (label_ref FOO)). */
2529 static void
2531 {
2539 {
2544 /* Remove barriers from the footer if there are any. */
2547 {
2550 else
2554 }
2557 }
2558 }
2560 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2561 by an arbitrary number of CLOBBERs. */
2562 static bool
2564 {
2579 {
2588 }
2590 }
2592 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2593 CLOBBERs), can be split into individual SETs in that order, without
2594 changing semantics. */
2595 static bool
2597 {
2605 {
2614 }
2617 }
2619 /* Return whether X is just a single set, with the source
2620 a general_operand. */
2621 static bool
2623 {
2628 }
2630 /* Try to combine the insns I0, I1 and I2 into I3.
2631 Here I0, I1 and I2 appear earlier than I3.
2632 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2633 I3.
2635 If we are combining more than two insns and the resulting insn is not
2636 recognized, try splitting it into two insns. If that happens, I2 and I3
2637 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2638 Otherwise, I0, I1 and I2 are pseudo-deleted.
2640 Return 0 if the combination does not work. Then nothing is changed.
2641 If we did the combination, return the insn at which combine should
2642 resume scanning.
2644 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2645 new direct jump instruction.
2647 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2648 been I3 passed to an earlier try_combine within the same basic
2649 block. */
2654 {
2655 /* New patterns for I3 and I2, respectively. */
2659 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2660 dead. */
2662 /* Total number of SETs to put into I3. */
2664 /* Nonzero if I2's or I1's body now appears in I3. */
2666 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2668 /* Contains I3 if the destination of I3 is used in its source, which means
2669 that the old life of I3 is being killed. If that usage is placed into
2670 I2 and not in I3, a REG_DEAD note must be made. */
2672 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2674 /* Copy of SET_SRC of I1 and I0, if needed. */
2676 /* Set if I2DEST was reused as a scratch register. */
2678 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2680 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2685 /* Notes that must be added to REG_NOTES in I3 and I2. */
2687 /* Notes that we substituted I3 into I2 instead of the normal case. */
2689 /* Notes that I1, I2 or I3 is a MULT operation. */
2698 rtx temp_expr;
2701 rtx new_other_notes;
2705 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2706 never be). */
2710 /* Only try four-insn combinations when there's high likelihood of
2711 success. Look for simple insns, such as loads of constants or
2712 binary operations involving a constant. */
2714 {
2724 {
2727 rtx src;
2732 {
2735 }
2737 ngood++;
2740 nshift++;
2741 }
2743 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2744 are likely manipulating its value. Ideally we'll be able to combine
2745 all four insns into a bitfield insertion of some kind.
2747 Note the source in I0 might be inside a sign/zero extension and the
2748 memory modes in I0 and I3 might be different. So extract the address
2749 from the destination of I3 and search for it in the source of I0.
2751 In the event that there's a match but the source/dest do not actually
2752 refer to the same memory, the worst that happens is we try some
2753 combinations that we wouldn't have otherwise. */
2755 /* Ensure the source of SET0 is a MEM, possibly buried inside
2756 an extension. */
2762 /* Ensure the destination of SET3 is a MEM. */
2764 /* Would it be better to extract the base address for the MEM
2765 in SET3 and look for that? I don't have cases where it matters
2766 but I could envision such cases. */
2772 }
2774 /* Exit early if one of the insns involved can't be used for
2775 combinations. */
2786 combine_attempts++;
2789 /* Reset the hard register usage information. */
2793 {
2800 else
2810 }
2812 /* If multiple insns feed into one of I2 or I3, they can be in any
2813 order. To simplify the code below, reorder them in sequence. */
2824 /* First check for one important special case that the code below will
2825 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2826 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2827 we may be able to replace that destination with the destination of I3.
2828 This occurs in the common code where we compute both a quotient and
2829 remainder into a structure, in which case we want to do the computation
2830 directly into the structure to avoid register-register copies.
2832 Note that this case handles both multiple sets in I2 and also cases
2833 where I2 has a number of CLOBBERs inside the PARALLEL.
2835 We make very conservative checks below and only try to handle the
2836 most common cases of this. For example, we only handle the case
2837 where I2 and I3 are adjacent to avoid making difficult register
2838 usage tests. */
2846 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2847 below would need to check what is inside (and reg_overlap_mentioned_p
2848 doesn't support those codes anyway). Don't allow those destinations;
2849 the resulting insn isn't likely to be recognized anyway. */
2855 {
2858 /* Make sure that the destination of I3,
2859 which we are going to substitute into one output of I2,
2860 is not used within another output of I2. We must avoid making this:
2861 (parallel [(set (mem (reg 69)) ...)
2862 (set (reg 69) ...)])
2863 which is not well-defined as to order of actions.
2864 (Besides, reload can't handle output reloads for this.)
2866 The problem can also happen if the dest of I3 is a memory ref,
2867 if another dest in I2 is an indirect memory ref.
2869 Neither can this PARALLEL be an asm. We do not allow combining
2870 that usually (see can_combine_p), so do not here either. */
2873 {
2883 }
2889 {
2890 combine_merges++;
2900 /* Replace the dest in I2 with our dest and make the resulting
2901 insn the new pattern for I3. Then skip to where we validate
2902 the pattern. Everything was set up above. */
2907 }
2908 }
2910 /* If I2 is setting a pseudo to a constant and I3 is setting some
2911 sub-part of it to another constant, merge them by making a new
2912 constant. */
2920 {
2927 {
2932 {
2938 }
2939 }
2940 else
2941 {
2945 {
2948 }
2949 }
2952 {
2953 /* If this is the low part, we're done. */
2955 ;
2956 /* Handle the case where inner is twice the size of outer. */
2960 /* Otherwise give up for now. */
2961 else
2963 }
2966 {
2974 combine_merges++;
2981 /* Replace the source in I2 with the new constant and make the
2982 resulting insn the new pattern for I3. Then skip to where we
2983 validate the pattern. Everything was set up above. */
2989 /* The dest of I3 has been replaced with the dest of I2. */
2992 }
2993 }
2995 /* If we have no I1 and I2 looks like:
2996 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2997 (set Y OP)])
2998 make up a dummy I1 that is
2999 (set Y OP)
3000 and change I2 to be
3001 (set (reg:CC X) (compare:CC Y (const_int 0)))
3003 (We can ignore any trailing CLOBBERs.)
3005 This undoes a previous combination and allows us to match a branch-and-
3006 decrement insn. */
3018 {
3019 /* We make I1 with the same INSN_UID as I2. This gives it
3020 the same DF_INSN_LUID for value tracking. Our fake I1 will
3021 never appear in the insn stream so giving it the same INSN_UID
3022 as I2 will not cause a problem. */
3035 }
3037 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
3038 make those two SETs separate I1 and I2 insns, and make an I0 that is
3039 the original I1. */
3047 {
3048 /* If there is no I1, there is no I0 either. */
3051 /* We make I1 with the same INSN_UID as I2. This gives it
3052 the same DF_INSN_LUID for value tracking. Our fake I1 will
3053 never appear in the insn stream so giving it the same INSN_UID
3054 as I2 will not cause a problem. */
3062 }
3064 /* Verify that I2 and maybe I1 and I0 can be combined into I3. */
3066 {
3071 }
3073 {
3078 }
3080 {
3085 }
3087 /* Record whether i2 and i3 are trivial moves. */
3091 /* Record whether I2DEST is used in I2SRC and similarly for the other
3092 cases. Knowing this will help in register status updating below. */
3103 /* For the earlier insns, determine which of the subsequent ones they
3104 feed. */
3111 /* Ensure that I3's pattern can be the destination of combines. */
3117 {
3120 }
3122 /* See if any of the insns is a MULT operation. Unless one is, we will
3123 reject a combination that is, since it must be slower. Be conservative
3124 here. */
3132 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3133 We used to do this EXCEPT in one case: I3 has a post-inc in an
3134 output operand. However, that exception can give rise to insns like
3135 mov r3,(r3)+
3136 which is a famous insn on the PDP-11 where the value of r3 used as the
3137 source was model-dependent. Avoid this sort of thing. */
3139 #if 0
3145 /* It's not the exception. */
3146 #endif
3148 {
3149 rtx link;
3155 {
3158 }
3159 }
3161 /* See if the SETs in I1 or I2 need to be kept around in the merged
3162 instruction: whenever the value set there is still needed past I3.
3163 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3165 For the SET in I1, we have two cases: if I1 and I2 independently feed
3166 into I3, the set in I1 needs to be kept around unless I1DEST dies
3167 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3168 in I1 needs to be kept around unless I1DEST dies or is set in either
3169 I2 or I3. The same considerations apply to I0. */
3176 else
3184 else
3187 /* We are about to copy insns for the case where they need to be kept
3188 around. Check that they can be copied in the merged instruction. */
3194 {
3197 }
3199 /* If the set in I2 needs to be kept around, we must make a copy of
3200 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3201 PATTERN (I2), we are only substituting for the original I1DEST, not into
3202 an already-substituted copy. This also prevents making self-referential
3203 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3204 I2DEST. */
3207 {
3210 else
3212 }
3215 {
3218 else
3220 }
3223 {
3226 else
3228 }
3230 combine_merges++;
3232 /* Substitute in the latest insn for the regs set by the earlier ones. */
3238 /* Many machines that don't use CC0 have insns that can both perform an
3239 arithmetic operation and set the condition code. These operations will
3240 be represented as a PARALLEL with the first element of the vector
3241 being a COMPARE of an arithmetic operation with the constant zero.
3242 The second element of the vector will set some pseudo to the result
3243 of the same arithmetic operation. If we simplify the COMPARE, we won't
3244 match such a pattern and so will generate an extra insn. Here we test
3245 for this case, where both the comparison and the operation result are
3246 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3247 I2SRC. Later we will make the PARALLEL that contains I2. */
3253 {
3254 rtx newpat_dest;
3260 scalar_int_mode mode;
3269 {
3275 }
3277 /* Do the rest only if op1 is const0_rtx, which may be the
3278 result of simplification. */
3280 {
3281 /* If a single use of the CC is found, prepare to modify it
3282 when SELECT_CC_MODE returns a new CC-class mode, or when
3283 the above simplify_compare_const() returned a new comparison
3284 operator. undobuf.other_insn is assigned the CC use insn
3285 when modifying it. */
3287 {
3288 #ifdef SELECT_CC_MODE
3289 machine_mode new_mode
3294 {
3299 else
3300 {
3303 }
3304 }
3305 #endif
3306 /* Cases for modifying the CC-using comparison. */
3308 /* ??? Do we need to verify the zero rtx? */
3310 {
3311 /* Replace cc_use_loc with entire new RTX. */
3316 }
3318 {
3319 /* Just replace the CC reg with a new mode. */
3322 }
3323 }
3325 /* Now we modify the current newpat:
3326 First, SET_DEST(newpat) is updated if the CC mode has been
3327 altered. For targets without SELECT_CC_MODE, this should be
3328 optimized away. */
3331 /* This is always done to propagate i2src into newpat. */
3334 /* Create new version of i2pat if needed; the below PARALLEL
3335 creation needs this to work correctly. */
3339 }
3340 }
3343 {
3344 /* It is possible that the source of I2 or I1 may be performing
3345 an unneeded operation, such as a ZERO_EXTEND of something
3346 that is known to have the high part zero. Handle that case
3347 by letting subst look at the inner insns.
3349 Another way to do this would be to have a function that tries
3350 to simplify a single insn instead of merging two or more
3351 insns. We don't do this because of the potential of infinite
3352 loops and because of the potential extra memory required.
3353 However, doing it the way we are is a bit of a kludge and
3354 doesn't catch all cases.
3356 But only do this if -fexpensive-optimizations since it slows
3357 things down and doesn't usually win.
3359 This is not done in the COMPARE case above because the
3360 unmodified I2PAT is used in the PARALLEL and so a pattern
3361 with a modified I2SRC would not match. */
3364 {
3365 /* Pass pc_rtx so no substitutions are done, just
3366 simplifications. */
3368 {
3371 }
3375 }
3380 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3381 copy of I2SRC each time we substitute it, in order to avoid creating
3382 self-referential RTL when we will be substituting I1SRC for I1DEST
3383 later. Likewise if I0 feeds into I2, either directly or indirectly
3384 through I1, and I0DEST is in I0SRC. */
3391 /* Record whether I2's body now appears within I3's body. */
3393 }
3395 /* If we already got a failure, don't try to do more. Otherwise, try to
3396 substitute I1 if we have it. */
3399 {
3400 /* Check that an autoincrement side-effect on I1 has not been lost.
3401 This happens if I1DEST is mentioned in I2 and dies there, and
3402 has disappeared from the new pattern. */
3404 && i1_feeds_i2_n
3407 /* Before we can do this substitution, we must redo the test done
3408 above (see detailed comments there) that ensures I1DEST isn't
3409 mentioned in any SETs in NEWPAT that are field assignments. */
3412 {
3415 }
3420 /* If the following substitution will modify I1SRC, make a copy of it
3421 for the case where it is substituted for I1DEST in I2PAT later. */
3425 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3426 copy of I1SRC each time we substitute it, in order to avoid creating
3427 self-referential RTL when we will be substituting I0SRC for I0DEST
3428 later. */
3433 /* Record whether I1's body now appears within I3's body. */
3435 }
3437 /* Likewise for I0 if we have it. */
3440 {
3447 {
3450 }
3452 /* If the following substitution will modify I0SRC, make a copy of it
3453 for the case where it is substituted for I0DEST in I1PAT later. */
3456 /* And a copy for I0DEST in I2PAT substitution. */
3465 }
3467 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3468 to count all the ways that I2SRC and I1SRC can be used. */
3479 /* Fail if we tried to make a new register. */
3481 /* Fail if we couldn't do something and have a CLOBBER. */
3483 /* Fail if this new pattern is a MULT and we didn't have one before
3484 at the outer level. */
3487 {
3490 }
3492 /* If the actions of the earlier insns must be kept
3493 in addition to substituting them into the latest one,
3494 we must make a new PARALLEL for the latest insn
3495 to hold additional the SETs. */
3498 {
3500 combine_extras++;
3503 {
3509 }
3510 else
3511 {
3516 }
3522 {
3528 }
3530 {
3539 }
3540 }
3542 validate_replacement:
3544 /* Note which hard regs this insn has as inputs. */
3547 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3548 consider splitting this pattern, we might need these clobbers. */
3551 {
3557 }
3559 /* We have recognized nothing yet. */
3562 /* See if this is a PARALLEL of two SETs where one SET's destination is
3563 a register that is unused and this isn't marked as an instruction that
3564 might trap in an EH region. In that case, we just need the other SET.
3565 We prefer this over the PARALLEL.
3567 This can occur when simplifying a divmod insn. We *must* test for this
3568 case here because the code below that splits two independent SETs doesn't
3569 handle this case correctly when it updates the register status.
3571 It's pointless doing this if we originally had two sets, one from
3572 i3, and one from i2. Combining then splitting the parallel results
3573 in the original i2 again plus an invalid insn (which we delete).
3574 The net effect is only to move instructions around, which makes
3575 debug info less accurate.
3577 If the remaining SET came from I2 its destination should not be used
3578 between I2 and I3. See PR82024. */
3583 {
3594 {
3597 }
3606 {
3611 {
3617 }
3618 }
3622 }
3624 /* Is the result of combination a valid instruction? */
3628 /* If we were combining three insns and the result is a simple SET
3629 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3630 insns. There are two ways to do this. It can be split using a
3631 machine-specific method (like when you have an addition of a large
3632 constant) or by combine in the function find_split_point. */
3636 {
3640 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3641 use I2DEST as a scratch register will help. In the latter case,
3642 convert I2DEST to the mode of the source of NEWPAT if we can. */
3646 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3647 inputs of NEWPAT. */
3649 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3650 possible to try that as a scratch reg. This would require adding
3651 more code to make it work though. */
3654 {
3657 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3658 (temporarily, until we are committed to this instruction
3659 combination) does not work: for example, any call to nonzero_bits
3660 on the register (from a splitter in the MD file, for example)
3661 will get the old information, which is invalid.
3663 Since nowadays we can create registers during combine just fine,
3664 we should just create a new one here, not reuse i2dest. */
3666 /* First try to split using the original register as a
3667 scratch register. */
3671 i2dest)));
3674 /* If that didn't work, try changing the mode of I2DEST if
3675 we can. */
3680 {
3682 rtx ni2dest;
3686 else
3687 {
3690 }
3692 parallel = (gen_rtx_PARALLEL
3696 ni2dest))));
3701 {
3709 }
3710 }
3713 }
3715 /* If recog_for_combine has discarded clobbers, try to use them
3716 again for the split. */
3718 {
3721 }
3724 {
3729 }
3733 {
3743 /* If I2 or I3 has multiple SETs, we won't know how to track
3744 register status, so don't use these insns. If I2's destination
3745 is used between I2 and I3, we also can't use these insns. */
3755 /* It is possible that both insns now set the destination of I3.
3756 If so, we must show an extra use of it. */
3759 {
3778 }
3779 }
3781 /* If we can split it and use I2DEST, go ahead and see if that
3782 helps things be recognized. Verify that none of the registers
3783 are set between I2 and I3. */
3787 /* We need I2DEST in the proper mode. If it is a hard register
3788 or the only use of a pseudo, we can change its mode.
3789 Make sure we don't change a hard register to have a mode that
3790 isn't valid for it, or change the number of registers. */
3797 /* We can't overwrite I2DEST if its value is still used by
3798 NEWPAT. */
3800 {
3809 /* *SPLIT may be part of I2SRC, so make sure we have the
3810 original expression around for later debug processing.
3811 We should not need I2SRC any more in other cases. */
3814 else
3817 /* Get NEWDEST as a register in the proper mode. We have already
3818 validated that we can do this. */
3820 {
3823 else
3824 {
3827 }
3828 }
3830 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3831 an ASHIFT. This can occur if it was inside a PLUS and hence
3832 appeared to be a memory address. This is a kludge. */
3837 {
3841 /* Update split_code because we may not have a multiply
3842 anymore. */
3844 }
3846 /* Similarly for (plus (mult FOO (const_int pow2))). */
3852 {
3857 i_rtx));
3858 /* Update split_code because we may not have a multiply
3859 anymore. */
3861 }
3863 #ifdef INSN_SCHEDULING
3864 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3865 be written as a ZERO_EXTEND. */
3867 {
3868 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3869 what it really is. */
3874 else
3877 }
3878 #endif
3880 /* Attempt to split binary operators using arithmetic identities. */
3884 {
3891 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3893 {
3898 }
3899 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3906 {
3912 /* Split both "((X op Y) op X) op Y" and
3913 "((X op Y) op Y) op X" as "T op T" where T is
3914 "X op Y". */
3917 {
3922 }
3923 /* Split "((X op X) op Y) op Y)" as "T op T" where
3924 T is "X op Y". */
3926 {
3932 }
3933 }
3934 }
3937 {
3940 }
3944 /* recog_for_combine might have added CLOBBERs to newi2pat.
3945 Make sure NEWPAT does not depend on the clobbered regs. */
3949 {
3952 {
3955 }
3956 }
3958 /* If the split point was a MULT and we didn't have one before,
3959 don't use one now. */
3962 }
3963 }
3965 /* Check for a case where we loaded from memory in a narrow mode and
3966 then sign extended it, but we need both registers. In that case,
3967 we have a PARALLEL with both loads from the same memory location.
3968 We can split this into a load from memory followed by a register-register
3969 copy. This saves at least one insn, more if register allocation can
3970 eliminate the copy.
3972 We cannot do this if the destination of the first assignment is a
3973 condition code register or cc0. We eliminate this case by making sure
3974 the SET_DEST and SET_SRC have the same mode.
3976 We cannot do this if the destination of the second assignment is
3977 a register that we have already assumed is zero-extended. Similarly
3978 for a SUBREG of such a register. */
3997 BITS_PER_WORD)
3999 HOST_BITS_PER_INT)
4007 BITS_PER_WORD)
4009 HOST_BITS_PER_INT)
4016 {
4017 rtx ni2dest;
4031 }
4033 /* Similarly, check for a case where we have a PARALLEL of two independent
4034 SETs but we started with three insns. In this case, we can do the sets
4035 as two separate insns. This case occurs when some SET allows two
4036 other insns to combine, but the destination of that SET is still live.
4038 Also do this if we started with two insns and (at least) one of the
4039 resulting sets is a noop; this noop will be deleted later.
4041 Also do this if we started with two insns neither of which was a simple
4042 move. */
4049 && (i1
4063 {
4067 /* Normally, it doesn't matter which of the two is done first,
4068 but the one that references cc0 can't be the second, and
4069 one which uses any regs/memory set in between i2 and i3 can't
4070 be first. The PARALLEL might also have been pre-existing in i3,
4071 so we need to make sure that we won't wrongly hoist a SET to i2
4072 that would conflict with a death note present in there, or would
4073 have its dest modified between i2 and i3. */
4082 /* If I3 is a jump, ensure that set0 is a jump so that
4083 we do not create invalid RTL. */
4085 )
4086 {
4089 }
4098 /* If I3 is a jump, ensure that set1 is a jump so that
4099 we do not create invalid RTL. */
4101 )
4102 {
4105 }
4106 else
4107 {
4110 }
4115 {
4116 /* recog_for_combine might have added CLOBBERs to newi2pat.
4117 Make sure NEWPAT does not depend on the clobbered regs. */
4119 {
4122 {
4125 {
4128 }
4129 }
4130 }
4136 }
4137 }
4139 /* If it still isn't recognized, fail and change things back the way they
4140 were. */
4142 /* Is the result a reasonable ASM_OPERANDS? */
4144 {
4147 }
4149 /* If we had to change another insn, make sure it is valid also. */
4151 {
4159 {
4162 }
4163 }
4165 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4166 they are adjacent to each other or not. */
4168 {
4172 {
4175 }
4176 }
4178 /* Only allow this combination if insn_cost reports that the
4179 replacement instructions are cheaper than the originals. */
4181 {
4184 }
4187 {
4192 {
4197 /* Temporarily revert mode back. */
4201 {
4202 /* If we used i2dest as a scratch register with a
4203 different mode, substitute it for the original
4204 i2src while its original mode is temporarily
4205 restored, and then clear i2scratch so that we don't
4206 do it again later. */
4208 this_basic_block);
4210 /* Put back the new mode. */
4212 }
4213 else
4214 {
4219 {
4222 }
4223 else
4224 {
4231 }
4233 /* We're dealing with a reg that changed mode but not
4234 meaning, so we want to turn it into a subreg for
4235 the new mode. However, because of REG sharing and
4236 because its mode had already changed, we have to do
4237 it in two steps. First, replace any debug uses of
4238 reg, with its original mode temporarily restored,
4239 with this copy we have created; then, replace the
4240 copy with the SUBREG of the original shared reg,
4241 once again changed to the new mode. */
4243 this_basic_block);
4247 this_basic_block);
4248 }
4249 }
4250 }
4252 /* If we will be able to accept this, we have made a
4253 change to the destination of I3. This requires us to
4254 do a few adjustments. */
4257 {
4260 }
4262 /* We now know that we can do this combination. Merge the insns and
4263 update the status of registers and LOG_LINKS. */
4266 {
4271 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4272 ensure that they are still valid. Then add any non-duplicate
4273 notes added by recog_for_combine. */
4275 {
4284 /* Simply drop equal note since it may be no longer valid
4285 for other_insn. It may be possible to record that CC
4286 register is changed and only discard those notes, but
4287 in practice it's unnecessary complication and doesn't
4288 give any meaningful improvement.
4290 See PR78559. */
4294 }
4298 NULL_RTX);
4299 }
4302 {
4303 /* I3 now uses what used to be its destination and which is now
4304 I2's destination. This requires us to do a few adjustments. */
4307 }
4310 {
4311 /* We might need a LOG_LINK from I3 to I2. But then we used to
4312 have one, so we still will.
4314 However, some later insn might be using I2's dest and have
4315 a LOG_LINK pointing at I3. We should change it to point at
4316 I2 instead. */
4318 /* newi2pat is usually a SET here; however, recog_for_combine might
4319 have added some clobbers. */
4324 /* It can only be a SET of a REG or of a SUBREG of a REG. */
4329 !done
4330 && insn
4334 {
4338 {
4342 }
4343 }
4344 }
4346 {
4351 /* Compute which registers we expect to eliminate. newi2pat may be setting
4352 either i3dest or i2dest, so we must check it. */
4355 || !i2dest_killed
4357 /* For i1, we need to compute both local elimination and global
4358 elimination information with respect to newi2pat because i1dest
4359 may be the same as i3dest, in which case newi2pat may be setting
4360 i1dest. Global information is used when distributing REG_DEAD
4361 note for i2 and i3, in which case it does matter if newi2pat sets
4362 i1dest or not.
4364 Local information is used when distributing REG_DEAD note for i1,
4365 in which case it doesn't matter if newi2pat sets i1dest or not.
4366 See PR62151, if we have four insns combination:
4367 i0: r0 <- i0src
4368 i1: r1 <- i1src (using r0)
4369 REG_DEAD (r0)
4370 i2: r0 <- i2src (using r1)
4371 i3: r3 <- i3src (using r0)
4372 ix: using r0
4373 From i1's point of view, r0 is eliminated, no matter if it is set
4374 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4375 should be discarded.
4377 Note local information only affects cases in forms like "I1->I2->I3",
4378 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4379 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4380 i0dest anyway. */
4382 || !i1dest_killed
4387 /* Same case as i1. */
4394 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4395 clear them. */
4403 /* Ensure that we do not have something that should not be shared but
4404 occurs multiple times in the new insns. Check this by first
4405 resetting all the `used' flags and then copying anything is shared. */
4429 {
4432 {
4434 {
4435 /* I2SRC must still be meaningful at this point. Some
4436 splitting operations can invalidate I2SRC, but those
4437 operations do not apply to calls. */
4441 }
4448 }
4449 }
4454 /* We had one special case above where I2 had more than one set and
4455 we replaced a destination of one of those sets with the destination
4456 of I3. In that case, we have to update LOG_LINKS of insns later
4457 in this basic block. Note that this (expensive) case is rare.
4459 Also, in this case, we must pretend that all REG_NOTEs for I2
4460 actually came from I3, so that REG_UNUSED notes from I2 will be
4461 properly handled. */
4464 {
4473 temp_insn
4483 {
4488 }
4489 else
4492 }
4500 {
4503 this_basic_block);
4506 }
4507 else
4508 {
4511 this_basic_block);
4513 }
4516 {
4521 this_basic_block);
4523 }
4526 {
4531 this_basic_block);
4533 }
4535 /* Get death notes for everything that is now used in either I3 or
4536 I2 and used to die in a previous insn. If we built two new
4537 patterns, move from I1 to I2 then I2 to I3 so that we get the
4538 proper movement on registers that I2 modifies. */
4544 else
4550 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4567 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4568 know these are REG_UNUSED and want them to go to the desired insn,
4569 so we always pass it as i3. */
4573 NULL_RTX);
4577 NULL_RTX);
4579 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4580 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4581 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4582 in that case, it might delete I2. Similarly for I2 and I1.
4583 Show an additional death due to the REG_DEAD note we make here. If
4584 we discard it in distribute_notes, we will decrement it again. */
4587 {
4592 else
4595 }
4598 {
4603 else
4606 }
4609 {
4614 else
4617 }
4620 {
4625 else
4628 }
4636 {
4641 /* The insn that used to set this register doesn't exist, and
4642 this life of the register may not exist either. See if one of
4643 I3's links points to an insn that sets I2DEST. If it does,
4644 that is now the last known value for I2DEST. If we don't update
4645 this and I2 set the register to a value that depended on its old
4646 contents, we will get confused. If this insn is used, thing
4647 will be set correctly in combine_instructions. */
4655 /* If the reg formerly set in I2 died only once and that was in I3,
4656 zero its use count so it won't make `reload' do any work. */
4659 && ! i2dest_in_i2src
4662 }
4665 {
4678 && ! i1dest_in_i1src
4681 }
4684 {
4697 && ! i0dest_in_i0src
4700 }
4702 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4703 been made to this insn. The order is important, because newi2pat
4704 can affect nonzero_bits of newpat. */
4708 }
4711 {
4713 {
4716 }
4718 }
4721 {
4723 {
4726 }
4728 }
4731 {
4733 {
4736 }
4738 }
4741 {
4743 {
4746 }
4748 }
4751 {
4753 {
4756 }
4758 }
4760 /* Set new_direct_jump_p if a new return or simple jump instruction
4761 has been created. Adjust the CFG accordingly. */
4763 {
4767 }
4772 {
4775 }
4779 {
4785 }
4790 {
4796 }
4798 /* A noop might also need cleaning up of CFG, if it comes from the
4799 simplification of a jump. */
4804 {
4807 }
4814 {
4817 }
4819 combine_successes++;
4829 }
4830 \f
4831 /* Get a marker for undoing to the current state. */
4835 {
4837 }
4839 /* Undo the modifications up to the marker. */
4841 static void
4843 {
4847 {
4852 {
4867 }
4871 }
4874 }
4876 /* Undo all the modifications recorded in undobuf. */
4878 static void
4880 {
4882 }
4884 /* We've committed to accepting the changes we made. Move all
4885 of the undos to the free list. */
4887 static void
4889 {
4893 {
4897 }
4899 }
4900 \f
4901 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4902 where we have an arithmetic expression and return that point. LOC will
4903 be inside INSN.
4905 try_combine will call this function to see if an insn can be split into
4906 two insns. */
4910 {
4920 /* First special-case some codes. */
4922 {
4924 #ifdef INSN_SCHEDULING
4925 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4926 point. */
4929 #endif
4933 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4934 using LO_SUM and HIGH. */
4937 {
4945 }
4947 /* If we have a PLUS whose second operand is a constant and the
4948 address is not valid, perhaps we can split it up using
4949 the machine-specific way to split large constants. We use
4950 the first pseudo-reg (one of the virtual regs) as a placeholder;
4951 it will not remain in the result. */
4956 {
4959 subst_insn);
4961 /* This should have produced two insns, each of which sets our
4962 placeholder. If the source of the second is a valid address,
4963 we can put both sources together and make a split point
4964 in the middle. */
4977 && memory_address_addr_space_p
4980 {
4984 /* Replace the placeholder in SRC2 with SRC1. If we can
4985 find where in SRC2 it was placed, that can become our
4986 split point and we can replace this address with SRC2.
4987 Just try two obvious places. */
4998 {
5001 }
5002 }
5004 /* If that didn't work and we have a nested plus, like:
5005 ((REG1 * CONST1) + REG2) + CONST2 and (REG1 + REG2) + CONST2
5006 is valid address, try to split (REG1 * CONST1). */
5013 {
5018 {
5021 }
5023 }
5030 {
5035 {
5038 }
5040 }
5042 /* If that didn't work, perhaps the first operand is complex and
5043 needs to be computed separately, so make a split point there.
5044 This will occur on machines that just support REG + CONST
5045 and have a constant moved through some previous computation. */
5050 }
5052 /* If we have a PLUS whose first operand is complex, try computing it
5053 separately by making a split there. */
5064 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
5065 ZERO_EXTRACT, the most likely reason why this doesn't match is that
5066 we need to put the operand into a register. So split at that
5067 point. */
5077 /* See if we can split SET_SRC as it stands. */
5082 /* See if we can split SET_DEST as it stands. */
5087 /* See if this is a bitfield assignment with everything constant. If
5088 so, this is an IOR of an AND, so split it into that. */
5100 {
5105 unsigned HOST_WIDE_INT mask
5107 rtx or_mask;
5116 else
5117 {
5123 or_mask));
5124 }
5131 }
5133 /* Otherwise, see if this is an operation that we can split into two.
5134 If so, try to split that. */
5138 {
5140 /* If we are AND'ing with a large constant that is only a single
5141 bit and the result is only being used in a context where we
5142 need to know if it is zero or nonzero, replace it with a bit
5143 extraction. This will avoid the large constant, which might
5144 have taken more than one insn to make. If the constant were
5145 not a valid argument to the AND but took only one insn to make,
5146 this is no worse, but if it took more than one insn, it will
5147 be better. */
5157 {
5162 {
5165 }
5166 }
5170 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5171 is known to be on, this can be converted into a NEG of a shift. */
5177 {
5184 pos_rtx)));
5189 }
5195 /* We can't optimize if either mode is a partial integer
5196 mode as we don't know how many bits are significant
5197 in those modes. */
5213 {
5221 }
5226 }
5232 {
5233 /* For unsigned, we have a choice of a shift followed by an
5234 AND or two shifts. Use two shifts for field sizes where the
5235 constant might be too large. We assume here that we can
5236 always at least get 8-bit constants in an AND insn, which is
5237 true for every current RISC. */
5240 {
5241 unsigned HOST_WIDE_INT mask
5246 gen_rtx_LSHIFTRT
5253 }
5254 else
5255 {
5259 gen_rtx_fmt_ee
5269 }
5270 }
5272 /* See if this is a simple operation with a constant as the second
5273 operand. It might be that this constant is out of range and hence
5274 could be used as a split point. */
5282 /* Finally, see if this is a simple operation with its first operand
5283 not in a register. The operation might require this operand in a
5284 register, so return it as a split point. We can always do this
5285 because if the first operand were another operation, we would have
5286 already found it as a split point. */
5295 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5296 it is better to write this as (not (ior A B)) so we can split it.
5297 Similarly for IOR. */
5299 {
5307 }
5309 /* Many RISC machines have a large set of logical insns. If the
5310 second operand is a NOT, put it first so we will try to split the
5311 other operand first. */
5313 {
5317 }
5322 /* Canonicalization can produce (minus A (mult B C)), where C is a
5323 constant. It may be better to try splitting (plus (mult B -C) A)
5324 instead if this isn't a multiply by a power of two. */
5328 {
5336 mode)),
5339 }
5341 /* Split at a multiply-accumulate instruction. However if this is
5342 the SET_SRC, we likely do not have such an instruction and it's
5343 worthless to try this split. */
5352 }
5354 /* Otherwise, select our actions depending on our rtx class. */
5356 {
5362 /* fall through */
5370 /* fall through */
5372 /* Some machines have (and (shift ...) ...) insns. If X is not
5373 an AND, but XEXP (X, 0) is, use it as our split point. */
5383 /* Otherwise, we don't have a split point. */
5385 }
5386 }
5387 \f
5388 /* Throughout X, replace FROM with TO, and return the result.
5389 The result is TO if X is FROM;
5390 otherwise the result is X, but its contents may have been modified.
5391 If they were modified, a record was made in undobuf so that
5392 undo_all will (among other things) return X to its original state.
5394 If the number of changes necessary is too much to record to undo,
5395 the excess changes are not made, so the result is invalid.
5396 The changes already made can still be undone.
5397 undobuf.num_undo is incremented for such changes, so by testing that
5398 the caller can tell whether the result is valid.
5400 `n_occurrences' is incremented each time FROM is replaced.
5402 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5404 IN_COND is nonzero if we are at the top level of a condition.
5406 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5407 by copying if `n_occurrences' is nonzero. */
5409 static rtx
5411 {
5416 rtx new_rtx;
5418 /* Two expressions are equal if they are identical copies of a shared
5419 RTX or if they are both registers with the same register number
5420 and mode. */
5422 #define COMBINE_RTX_EQUAL_P(X,Y) \
5423 ((X) == (Y) \
5424 || (REG_P (X) && REG_P (Y) \
5425 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5427 /* Do not substitute into clobbers of regs -- this will never result in
5428 valid RTL. */
5433 {
5434 n_occurrences++;
5436 }
5438 /* If X and FROM are the same register but different modes, they
5439 will not have been seen as equal above. However, the log links code
5440 will make a LOG_LINKS entry for that case. If we do nothing, we
5441 will try to rerecognize our original insn and, when it succeeds,
5442 we will delete the feeding insn, which is incorrect.
5444 So force this insn not to match in this (rare) case. */
5449 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5450 of which may contain things that can be combined. */
5454 /* It is possible to have a subexpression appear twice in the insn.
5455 Suppose that FROM is a register that appears within TO.
5456 Then, after that subexpression has been scanned once by `subst',
5457 the second time it is scanned, TO may be found. If we were
5458 to scan TO here, we would find FROM within it and create a
5459 self-referent rtl structure which is completely wrong. */
5463 /* Parallel asm_operands need special attention because all of the
5464 inputs are shared across the arms. Furthermore, unsharing the
5465 rtl results in recognition failures. Failure to handle this case
5466 specially can result in circular rtl.
5468 Solve this by doing a normal pass across the first entry of the
5469 parallel, and only processing the SET_DESTs of the subsequent
5470 entries. Ug. */
5475 {
5478 /* If this substitution failed, this whole thing fails. */
5486 {
5492 {
5495 /* If this substitution failed, this whole thing fails. */
5501 }
5502 }
5503 }
5504 else
5505 {
5509 /* We don't need to process a SET_DEST that is a register, CC0,
5510 or PC, so set up to skip this common case. All other cases
5511 where we want to suppress replacing something inside a
5512 SET_SRC are handled via the IN_DEST operand. */
5519 /* Trying to simplify the operands of a widening MULT is not likely
5520 to create RTL matching a machine insn. */
5532 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5533 constant. */
5538 {
5540 {
5543 {
5545 {
5548 n_occurrences++;
5549 }
5550 else
5551 {
5553 unique_copy);
5555 /* If this substitution failed, this whole thing
5556 fails. */
5560 }
5563 }
5564 }
5566 {
5567 /* If this is a register being set, ignore it. */
5574 ;
5577 {
5578 /* In general, don't install a subreg involving two
5579 modes not tieable. It can worsen register
5580 allocation, and can even make invalid reload
5581 insns, since the reg inside may need to be copied
5582 from in the outside mode, and that may be invalid
5583 if it is an fp reg copied in integer mode.
5585 We allow two exceptions to this: It is valid if
5586 it is inside another SUBREG and the mode of that
5587 SUBREG and the mode of the inside of TO is
5588 tieable and it is valid if X is a SET that copies
5589 FROM to CC0. */
5597 && (!HAVE_cc0
5612 n_occurrences++;
5613 }
5614 else
5615 /* If we are in a SET_DEST, suppress most cases unless we
5616 have gone inside a MEM, in which case we want to
5617 simplify the address. We assume here that things that
5618 are actually part of the destination have their inner
5619 parts in the first expression. This is true for SUBREG,
5620 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5621 things aside from REG and MEM that should appear in a
5622 SET_DEST. */
5624 (((in_dest
5630 unique_copy);
5632 /* If we found that we will have to reject this combination,
5633 indicate that by returning the CLOBBER ourselves, rather than
5634 an expression containing it. This will speed things up as
5635 well as prevent accidents where two CLOBBERs are considered
5636 to be equal, thus producing an incorrect simplification. */
5642 {
5650 }
5655 {
5657 new_rtx,
5661 }
5662 else
5664 }
5665 }
5666 }
5668 /* Check if we are loading something from the constant pool via float
5669 extension; in this case we would undo compress_float_constant
5670 optimization and degenerate constant load to an immediate value. */
5674 {
5678 }
5680 /* Try to simplify X. If the simplification changed the code, it is likely
5681 that further simplification will help, so loop, but limit the number
5682 of repetitions that will be performed. */
5685 {
5686 /* If X is sufficiently simple, don't bother trying to do anything
5687 with it. */
5696 /* We no longer know the original mode of operand 0 since we
5697 have changed the form of X) */
5699 }
5702 }
5703 \f
5704 /* If X is a commutative operation whose operands are not in the canonical
5705 order, use substitutions to swap them. */
5707 static void
5709 {
5712 {
5716 }
5717 }
5719 /* Simplify X, a piece of RTL. We just operate on the expression at the
5720 outer level; call `subst' to simplify recursively. Return the new
5721 expression.
5723 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5724 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5725 of a condition. */
5727 static rtx
5730 {
5733 scalar_int_mode int_mode;
5734 rtx temp;
5737 /* If this is a commutative operation, put a constant last and a complex
5738 expression first. We don't need to do this for comparisons here. */
5741 /* Try to fold this expression in case we have constants that weren't
5742 present before. */
5745 {
5753 {
5756 {
5760 }
5763 }
5776 }
5779 {
5784 }
5786 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5787 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5788 things. Check for cases where both arms are testing the same
5789 condition.
5791 Don't do anything if all operands are very simple. */
5804 {
5809 /* If everything is a comparison, what we have is highly unlikely
5810 to be simpler, so don't use it. */
5813 /* Similarly, if we end up with one of the expressions the same
5814 as the original, it is certainly not simpler. */
5817 {
5824 /* Simplify the alternative arms; this may collapse the true and
5825 false arms to store-flag values. Be careful to use copy_rtx
5826 here since true_rtx or false_rtx might share RTL with x as a
5827 result of the if_then_else_cond call above. */
5831 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5832 is unlikely to be simpler. */
5835 {
5838 /* Restarting if we generate a store-flag expression will cause
5839 us to loop. Just drop through in this case. */
5841 /* If the result values are STORE_FLAG_VALUE and zero, we can
5842 just make the comparison operation. */
5853 /* Likewise, we can make the negate of a comparison operation
5854 if the result values are - STORE_FLAG_VALUE and zero. */
5862 mode);
5873 mode);
5874 else
5877 mode,
5878 VOIDmode,
5879 cond,
5880 cop1),
5885 }
5886 }
5887 }
5889 /* First see if we can apply the inverse distributive law. */
5892 {
5896 }
5898 /* If CODE is an associative operation not otherwise handled, see if we
5899 can associate some operands. This can win if they are constants or
5900 if they are logically related (i.e. (a & b) & a). */
5906 {
5908 {
5912 rtx inner;
5914 /* Make sure we pass the constant operand if any as the second
5915 one if this is a commutative operation. */
5923 /* For commutative operations, try the other pair if that one
5924 didn't simplify. */
5926 {
5931 }
5935 }
5936 }
5938 /* A little bit of algebraic simplification here. */
5940 {
5942 /* Ensure that our address has any ASHIFTs converted to MULT in case
5943 address-recognizing predicates are called later. */
5952 /* See if this can be moved to simplify_subreg. */
5955 /* Don't call gen_lowpart if the inner mode
5956 is VOIDmode and we cannot simplify it, as SUBREG without
5957 inner mode is invalid. */
5964 {
5965 rtx temp;
5971 /* If op is known to have all lower bits zero, the result is zero. */
5984 }
5986 /* Don't change the mode of the MEM if that would change the meaning
5987 of the address. */
5994 /* Note that we cannot do any narrowing for non-constants since
5995 we might have been counting on using the fact that some bits were
5996 zero. We now do this in the SET. */
6003 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
6004 replaced by (lshiftrt X C). This will convert
6005 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
6013 /* If X has only a single bit that might be nonzero, say, bit I, convert
6014 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
6015 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
6016 (sign_extract X 1 Y). But only do this if TEMP isn't a register
6017 or a SUBREG of one since we'd be making the expression more
6018 complex if it was just a register. */
6025 {
6026 rtx temp1 = simplify_shift_const
6032 /* If all we did was surround TEMP with the two shifts, we
6033 haven't improved anything, so don't use it. Otherwise,
6034 we are better off with TEMP1. */
6039 }
6043 /* We can't handle truncation to a partial integer mode here
6044 because we don't know the real bitsize of the partial
6045 integer mode. */
6054 /* We can truncate a constant value and return it. */
6055 {
6056 poly_int64 c;
6059 }
6061 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
6062 whose value is a comparison can be replaced with a subreg if
6063 STORE_FLAG_VALUE permits. */
6072 /* (const (const X)) can become (const X). Do it this way rather than
6073 returning the inner CONST since CONST can be shared with a
6074 REG_EQUAL note. */
6080 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
6081 can add in an offset. find_split_point will split this address up
6082 again if it doesn't match. */
6089 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
6090 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
6091 bit-field and can be replaced by either a sign_extend or a
6092 sign_extract. The `and' may be a zero_extend and the two
6093 <c>, -<c> constants may be reversed. */
6110 return simplify_shift_const
6117 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6118 can become (ashiftrt (ashift (xor x 1) C) C) where C is
6119 the bitsize of the mode - 1. This allows simplification of
6120 "a = (b & 8) == 0;" */
6127 return simplify_shift_const
6131 const1_rtx),
6135 /* If we are adding two things that have no bits in common, convert
6136 the addition into an IOR. This will often be further simplified,
6137 for example in cases like ((a & 1) + (a & 2)), which can
6138 become a & 3. */
6143 {
6144 /* Try to simplify the expression further. */
6148 /* If we could, great. If not, do not go ahead with the IOR
6149 replacement, since PLUS appears in many special purpose
6150 address arithmetic instructions. */
6158 }
6160 /* Canonicalize x + x into x << 1. */
6169 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6170 (and <foo> (const_int pow2-1)) */
6181 /* If we have (mult (plus A B) C), apply the distributive law and then
6182 the inverse distributive law to see if things simplify. This
6183 occurs mostly in addresses, often when unrolling loops. */
6186 {
6190 }
6192 /* Try simplify a*(b/c) as (a*b)/c. */
6195 {
6201 }
6205 /* If this is a divide by a power of two, treat it as a shift if
6206 its first operand is a shift. */
6226 /* If the first operand is a condition code, we can't do anything
6227 with it. */
6231 {
6239 /* Simplify our comparison, if possible. */
6242 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6243 if only the low-order bit is possibly nonzero in X (such as when
6244 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6245 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6246 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6247 (plus X 1).
6249 Remove any ZERO_EXTRACT we made when thinking this was a
6250 comparison. It may now be simpler to use, e.g., an AND. If a
6251 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6252 the call to make_compound_operation in the SET case.
6254 Don't apply these optimizations if the caller would
6255 prefer a comparison rather than a value.
6256 E.g., for the condition in an IF_THEN_ELSE most targets need
6257 an explicit comparison. */
6260 ;
6278 {
6282 int_mode);
6283 }
6291 {
6295 const1_rtx);
6296 }
6305 {
6308 }
6310 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6311 those above. */
6313 ;
6330 {
6334 int_mode);
6335 }
6344 {
6348 int_mode);
6349 }
6351 /* If X is 0/1, (eq X 0) is X-1. */
6358 {
6361 }
6363 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6364 one bit that might be nonzero, we can convert (ne x 0) to
6365 (ashift x c) where C puts the bit in the sign bit. Remove any
6366 AND with STORE_FLAG_VALUE when we are done, since we are only
6367 going to test the sign bit. */
6375 {
6381 else
6383 }
6385 /* If the code changed, return a whole new comparison.
6386 We also need to avoid using SUBST in cases where
6387 simplify_comparison has widened a comparison with a CONST_INT,
6388 since in that case the wider CONST_INT may fail the sanity
6389 checks in do_SUBST. */
6396 /* Otherwise, keep this operation, but maybe change its operands.
6397 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6400 }
6410 /* If we are processing SET_DEST, we are done. */
6428 /* If this is a shift by a constant amount, simplify it. */
6436 (HOST_WIDE_INT_1U
6445 }
6448 }
6449 \f
6450 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6452 static rtx
6454 {
6461 rtx temp;
6464 rtx reversed;
6467 /* Simplify storing of the truth value. */
6472 /* Also when the truth value has to be reversed. */
6478 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6479 in it is being compared against certain values. Get the true and false
6480 comparisons and see if that says anything about the value of each arm. */
6486 {
6487 HOST_WIDE_INT nzb;
6493 /* If FALSE_CODE is EQ, swap the codes and arms. */
6496 {
6499 }
6501 scalar_int_mode from_mode;
6503 {
6504 /* If we are comparing against zero and the expression being
6505 tested has only a single bit that might be nonzero, that is
6506 its value when it is not equal to zero. Similarly if it is
6507 known to be -1 or 0. */
6511 {
6514 }
6519 {
6522 }
6523 }
6525 /* Now simplify an arm if we know the value of the register in the
6526 branch and it is used in the arm. Be careful due to the potential
6527 of locally-shared RTL. */
6544 }
6546 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6547 reversed, do so to avoid needing two sets of patterns for
6548 subtract-and-branch insns. Similarly if we have a constant in the true
6549 arm, the false arm is the same as the first operand of the comparison, or
6550 the false arm is more complicated than the true arm. */
6563 {
6572 /* It is possible that the conditional has been simplified out. */
6575 }
6577 /* If the two arms are identical, we don't need the comparison. */
6582 /* Convert a == b ? b : a to "a". */
6594 /* Look for cases where we have (abs x) or (neg (abs X)). */
6597 && comparison_p
6604 {
6610 return
6613 mode);
6616 }
6618 /* Look for MIN or MAX. */
6621 && comparison_p
6626 {
6641 }
6643 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6644 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6645 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6646 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6647 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6648 neither 1 or -1, but it isn't worth checking for. */
6651 && comparison_p
6654 {
6670 /* If an identity-zero op is commutative, check whether there
6671 would be a match if we swapped the operands. */
6692 {
6696 }
6709 {
6713 }
6730 {
6734 }
6747 {
6751 }
6754 {
6764 const_true_rtx));
6772 }
6773 }
6775 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6776 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6777 negation of a single bit, we can convert this operation to a shift. We
6778 can actually do this more generally, but it doesn't seem worth it. */
6790 return
6794 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6795 non-zero bit in A is C1. */
6803 {
6809 }
6812 }
6813 \f
6814 /* Simplify X, a SET expression. Return the new expression. */
6816 static rtx
6818 {
6821 machine_mode mode
6825 scalar_int_mode int_mode;
6827 /* (set (pc) (return)) gets written as (return). */
6831 /* Now that we know for sure which bits of SRC we are using, see if we can
6832 simplify the expression for the object knowing that we only need the
6833 low-order bits. */
6836 {
6839 }
6841 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6842 the comparison result and try to simplify it unless we already have used
6843 undobuf.other_insn. */
6851 {
6860 {
6863 {
6866 }
6867 }
6868 else
6876 {
6880 }
6881 else
6882 {
6887 /* Attempt to simplify CC user. */
6889 {
6893 }
6895 /* Convert X into a no-op move. */
6899 }
6901 /* Simplify our comparison, if possible. */
6904 #ifdef SELECT_CC_MODE
6905 /* If this machine has CC modes other than CCmode, check to see if we
6906 need to use a different CC mode here. */
6915 else
6918 /* If the mode changed, we have to change SET_DEST, the mode in the
6919 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6920 a hard register, just build new versions with the proper mode. If it
6921 is a pseudo, we lose unless it is only time we set the pseudo, in
6922 which case we can safely change its mode. */
6924 {
6926 {
6928 rtx new_dest;
6932 else
6933 {
6936 }
6943 }
6944 }
6947 /* If the code changed, we have to build a new comparison in
6948 undobuf.other_insn. */
6950 {
6959 /* If the only change we made was to change an EQ into an NE or
6960 vice versa, OP0 has only one bit that might be nonzero, and OP1
6961 is zero, check if changing the user of the condition code will
6962 produce a valid insn. If it won't, we can keep the original code
6963 in that insn by surrounding our operation with an XOR. */
6970 {
6975 {
6982 }
6983 }
6984 }
6989 /* Don't generate a compare of a CC with 0, just use that CC. */
6991 {
6994 }
6995 /* Otherwise, if we didn't previously have the same COMPARE we
6996 want, create it from scratch. */
6999 {
7002 }
7003 }
7004 else
7005 {
7006 /* Get SET_SRC in a form where we have placed back any
7007 compound expressions. Then do the checks below. */
7010 }
7012 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
7013 and X being a REG or (subreg (reg)), we may be able to convert this to
7014 (set (subreg:m2 x) (op)).
7016 We can always do this if M1 is narrower than M2 because that means that
7017 we only care about the low bits of the result.
7019 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
7020 perform a narrower operation than requested since the high-order bits will
7021 be undefined. On machine where it is defined, this transformation is safe
7022 as long as M1 and M2 have the same number of words. */
7026 && (known_equal_after_align_up
7029 UNITS_PER_WORD))
7038 {
7041 dest));
7045 }
7047 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
7048 in SRC. */
7052 {
7056 /* Here we make sure that we don't have a sign bit on. */
7059 {
7062 }
7063 }
7065 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
7066 would require a paradoxical subreg. Replace the subreg with a
7067 zero_extend to avoid the reload that would otherwise be required.
7068 Don't do this unless we have a scalar integer mode, otherwise the
7069 transformation is incorrect. */
7076 {
7081 }
7083 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
7084 are comparing an item known to be 0 or -1 against 0, use a logical
7085 operation instead. Check for one of the arms being an IOR of the other
7086 arm with some value. We compute three terms to be IOR'ed together. In
7087 practice, at most two will be nonzero. Then we do the IOR's. */
7095 && (!HAVE_conditional_move
7100 {
7125 int_mode),
7126 false_rtx);
7132 term3));
7135 }
7137 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7138 whole thing fail. */
7143 else
7144 /* Convert this into a field assignment operation, if possible. */
7146 }
7147 \f
7148 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7149 result. */
7151 static rtx
7153 {
7156 scalar_int_mode mode;
7159 {
7161 /* We can call simplify_and_const_int only if we don't lose
7162 any (sign) bits when converting INTVAL (op1) to
7163 "unsigned HOST_WIDE_INT". */
7168 {
7175 }
7177 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7178 apply the distributive law and then the inverse distributive
7179 law to see if things simplify. */
7181 {
7185 }
7187 {
7191 }
7195 /* If we have (ior (and A B) C), apply the distributive law and then
7196 the inverse distributive law to see if things simplify. */
7199 {
7203 }
7206 {
7210 }
7215 }
7218 }
7219 \f
7220 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7221 operations" because they can be replaced with two more basic operations.
7222 ZERO_EXTEND is also considered "compound" because it can be replaced with
7223 an AND operation, which is simpler, though only one operation.
7225 The function expand_compound_operation is called with an rtx expression
7226 and will convert it to the appropriate shifts and AND operations,
7227 simplifying at each stage.
7229 The function make_compound_operation is called to convert an expression
7230 consisting of shifts and ANDs into the equivalent compound expression.
7231 It is the inverse of this function, loosely speaking. */
7233 static rtx
7235 {
7239 rtx tem;
7240 scalar_int_mode inner_mode;
7243 {
7246 /* FALLTHRU */
7248 /* We can't necessarily use a const_int for a multiword mode;
7249 it depends on implicitly extending the value.
7250 Since we don't know the right way to extend it,
7251 we can't tell whether the implicit way is right.
7253 Even for a mode that is no wider than a const_int,
7254 we can't win, because we need to sign extend one of its bits through
7255 the rest of it, and we don't know which bit. */
7259 /* Reject modes that aren't scalar integers because turning vector
7260 or complex modes into shifts causes problems. */
7264 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7265 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7266 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7267 reloaded. If not for that, MEM's would very rarely be safe.
7269 Reject modes bigger than a word, because we might not be able
7270 to reference a two-register group starting with an arbitrary register
7271 (and currently gen_lowpart might crash for a SUBREG). */
7277 /* If the inner object has VOIDmode (the only way this can happen
7278 is if it is an ASM_OPERANDS), we can't do anything since we don't
7279 know how much masking to do. */
7288 /* fall through */
7291 /* If the operand is a CLOBBER, just return it. */
7299 /* Reject modes that aren't scalar integers because turning vector
7300 or complex modes into shifts causes problems. */
7307 /* This should stay within the object being extracted, fail otherwise. */
7318 }
7320 /* We've rejected non-scalar operations by now. */
7323 /* Convert sign extension to zero extension, if we know that the high
7324 bit is not set, as this is easier to optimize. It will be converted
7325 back to cheaper alternative in make_extraction. */
7331 {
7335 /* Make sure this is a profitable operation. */
7342 else
7344 }
7346 /* We can optimize some special cases of ZERO_EXTEND. */
7348 {
7349 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7350 know that the last value didn't have any inappropriate bits
7351 set. */
7359 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7368 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7369 is a comparison and STORE_FLAG_VALUE permits. This is like
7370 the first case, but it works even when MODE is larger
7371 than HOST_WIDE_INT. */
7379 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7388 }
7390 /* If we reach here, we want to return a pair of shifts. The inner
7391 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7392 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7393 logical depending on the value of UNSIGNEDP.
7395 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7396 converted into an AND of a shift.
7398 We must check for the case where the left shift would have a negative
7399 count. This can happen in a case like (x >> 31) & 255 on machines
7400 that can't shift by a constant. On those machines, we would first
7401 combine the shift with the AND to produce a variable-position
7402 extraction. Then the constant of 31 would be substituted in
7403 to produce such a position. */
7407 {
7415 }
7420 pos),
7422 else
7423 /* Any other cases we can't handle. */
7426 /* If we couldn't do this for some reason, return the original
7427 expression. */
7432 }
7433 \f
7434 /* X is a SET which contains an assignment of one object into
7435 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7436 or certain SUBREGS). If possible, convert it into a series of
7437 logical operations.
7439 We half-heartedly support variable positions, but do not at all
7440 support variable lengths. */
7442 static const_rtx
7444 {
7445 rtx inner;
7449 scalar_int_mode compute_mode;
7451 /* Loop until we find something we can't simplify. */
7453 {
7456 {
7462 MAX_MODE_INT);
7463 }
7466 {
7474 /* A constant position should stay within the width of INNER. */
7479 {
7485 /* If position is ADJUST - X, new position is X. */
7487 else
7491 pos);
7492 }
7493 }
7495 /* If the destination is a subreg that overwrites the whole of the inner
7496 register, we can move the subreg to the source. */
7498 /* We need SUBREGs to compute nonzero_bits properly. */
7499 && nonzero_sign_valid
7501 {
7503 gen_lowpart
7507 }
7508 else
7514 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7516 {
7517 /* Don't do anything for vector or complex integral types. */
7521 /* Try to find an integral mode to pun with. */
7527 }
7529 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7533 /* Don't try to compute in too wide unsupported modes. */
7537 /* Now compute the equivalent expression. Make a copy of INNER
7538 for the SET_DEST in case it is a MEM into which we will substitute;
7539 we don't want shared RTL in that case. */
7541 compute_mode);
7545 compute_mode,
7547 compute_mode),
7548 inner);
7553 mask),
7554 pos);
7559 }
7562 }
7563 \f
7564 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7565 it is an RTX that represents the (variable) starting position; otherwise,
7566 POS is the (constant) starting bit position. Both are counted from the LSB.
7568 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7570 IN_DEST is nonzero if this is a reference in the destination of a SET.
7571 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7572 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7573 be used.
7575 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7576 ZERO_EXTRACT should be built even for bits starting at bit 0.
7578 MODE is the desired mode of the result (if IN_DEST == 0).
7580 The result is an RTX for the extraction or NULL_RTX if the target
7581 can't handle it. */
7583 static rtx
7587 {
7588 /* This mode describes the size of the storage area
7589 to fetch the overall value from. Within that, we
7590 ignore the POS lowest bits, etc. */
7592 machine_mode inner_mode;
7593 scalar_int_mode wanted_inner_mode;
7599 HOST_WIDE_INT orig_pos;
7607 /* If trying or potentionally trying to extract
7608 bits outside of is_mode, don't look through
7609 non-paradoxical SUBREGs. See PR82192. */
7612 {
7613 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7614 consider just the QI as the memory to extract from.
7615 The subreg adds or removes high bits; its mode is
7616 irrelevant to the meaning of this extraction,
7617 since POS and LEN count from the lsb. */
7621 }
7626 {
7627 /* We're extracting the least significant bits of an rtx
7628 (ashift X (const_int C)), where LEN > C. Extract the
7629 least significant (LEN - C) bits of X, giving an rtx
7630 whose mode is MODE, then shift it left C times. */
7636 }
7638 /* If trying or potentionally trying to extract
7639 bits outside of is_mode, don't look through
7640 TRUNCATE. See PR82192. */
7647 /* See if this can be done without an extraction. We never can if the
7648 width of the field is not the same as that of some integer mode. For
7649 registers, we can only avoid the extraction if the position is at the
7650 low-order bit and this is either not in the destination or we have the
7651 appropriate STRICT_LOW_PART operation available.
7653 For MEM, we can avoid an extract if the field starts on an appropriate
7654 boundary and we can change the mode of the memory reference. */
7656 scalar_int_mode tmode;
7665 && (! in_dest
7669 && (pos
7672 /* We can't do this if we are widening INNER_MODE (it
7673 may not be aligned, for one thing). */
7679 {
7680 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7681 field. If the original and current mode are the same, we need not
7682 adjust the offset. Otherwise, we do if bytes big endian.
7684 If INNER is not a MEM, get a piece consisting of just the field
7685 of interest (in this case POS % BITS_PER_WORD must be 0). */
7688 {
7689 poly_int64 offset;
7691 /* POS counts from lsb, but make OFFSET count in memory order. */
7695 else
7699 }
7701 {
7703 {
7704 /* We can't call gen_lowpart in a DEST since we
7705 always want a SUBREG (see below) and it would sometimes
7706 return a new hard register. */
7708 {
7709 poly_uint64 offset
7712 /* Avoid creating invalid subregs, for example when
7713 simplifying (x>>32)&255. */
7718 }
7719 else
7721 }
7722 else
7724 }
7725 else
7727 len >= HOST_BITS_PER_WIDE_INT
7728 ? HOST_WIDE_INT_M1U
7731 /* If this extraction is going into the destination of a SET,
7732 make a STRICT_LOW_PART unless we made a MEM. */
7747 /* If we know that no extraneous bits are set, and that the high
7748 bit is not set, convert the extraction to the cheaper of
7749 sign and zero extension, that are equivalent in these cases. */
7755 {
7759 /* Prefer ZERO_EXTENSION, since it gives more information to
7760 backends. */
7765 }
7767 /* Otherwise, sign- or zero-extend unless we already are in the
7768 proper mode. */
7772 }
7774 /* Unless this is a COMPARE or we have a funny memory reference,
7775 don't do anything with zero-extending field extracts starting at
7776 the low-order bit since they are simple AND operations. */
7781 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7782 if the position is not a constant and the length is not 1. In all
7783 other cases, we would only be going outside our object in cases when
7784 an original shift would have been undefined. */
7793 /* If INNER is not from memory, we want it to have the mode of a register
7794 extraction pattern's structure operand, or word_mode if there is no
7795 such pattern. The same applies to extraction_mode and pos_mode
7796 and their respective operands.
7798 For memory, assume that the desired extraction_mode and pos_mode
7799 are the same as for a register operation, since at present we don't
7800 have named patterns for aligned memory structures. */
7805 {
7809 }
7811 /* Never narrow an object, since that might not be safe. */
7819 else
7820 {
7821 /* Be careful not to go beyond the extracted object and maintain the
7822 natural alignment of the memory. */
7827 }
7832 {
7833 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7834 BITS_BIG_ENDIAN style. If position is constant, compute new
7835 position. Otherwise, build subtraction.
7836 Note that POS is relative to the mode of the original argument.
7837 If it's a MEM we need to recompute POS relative to that.
7838 However, if we're extracting from (or inserting into) a register,
7839 we want to recompute POS relative to wanted_inner_mode. */
7848 else
7849 pos_rtx
7852 pos_rtx);
7853 /* POS may be less than 0 now, but we check for that below.
7854 Note that it can only be less than 0 if !MEM_P (inner). */
7855 }
7857 /* If INNER has a wider mode, and this is a constant extraction, try to
7858 make it smaller and adjust the byte to point to the byte containing
7859 the value. */
7862 && ! pos_rtx
7867 {
7870 /* The computations below will be correct if the machine is big
7871 endian in both bits and bytes or little endian in bits and bytes.
7872 If it is mixed, we must adjust. */
7874 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7875 adjust OFFSET to compensate. */
7880 /* We can now move to the desired byte. */
7891 }
7893 /* If INNER is not memory, get it into the proper mode. If we are changing
7894 its mode, POS must be a constant and smaller than the size of the new
7895 mode. */
7897 {
7898 /* On the LHS, don't create paradoxical subregs implicitely truncating
7899 the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7902 wanted_inner_mode))
7914 pos_rtx
7916 ? HOST_WIDE_INT_M1U
7920 }
7922 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7923 have to zero extend. Otherwise, we can just use a SUBREG.
7925 We dealt with constant rtxes earlier, so pos_rtx cannot
7926 have VOIDmode at this point. */
7930 {
7934 /* If we know that no extraneous bits are set, and that the high
7935 bit is not set, convert extraction to cheaper one - either
7936 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7937 cases. */
7945 {
7949 /* Prefer ZERO_EXTENSION, since it gives more information to
7950 backends. */
7954 }
7956 }
7958 /* Make POS_RTX unless we already have it and it is correct. If we don't
7959 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7960 be a CONST_INT. */
7967 /* Make the required operation. See if we can use existing rtx. */
7974 }
7975 \f
7976 /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
7977 can be commuted with any other operations in X. Return X without
7978 that shift if so. */
7980 static rtx
7982 {
7984 rtx tem;
7987 {
7989 /* This is the shift itself. If it is wide enough, we will return
7990 either the value being shifted if the shift count is equal to
7991 COUNT or a shift for the difference. */
8005 /* If we can safely shift this constant and we find the inner shift,
8006 make a new operation. */
8011 {
8015 }
8020 }
8023 }
8024 \f
8025 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
8026 level of the expression and MODE is its mode. IN_CODE is as for
8027 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
8028 that should be used when recursing on operands of *X_PTR.
8030 There are two possible actions:
8032 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
8033 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
8035 - Return a new rtx, which the caller returns directly. */
8037 static rtx
8041 {
8049 rtx tem;
8050 scalar_int_mode inner_mode;
8054 {
8057 }
8059 /* Process depending on the code of this operation. If NEW is set
8060 nonzero, it will be returned. */
8063 {
8065 /* Convert shifts by constants into multiplications if inside
8066 an address. */
8070 {
8076 {
8079 }
8082 }
8091 {
8095 }
8098 {
8102 mode));
8104 }
8105 else
8106 {
8109 }
8119 {
8123 }
8126 {
8130 mode));
8132 }
8133 else
8134 {
8138 }
8141 /* If the second operand is not a constant, we can't do anything
8142 with it. */
8146 /* If the constant is a power of two minus one and the first operand
8147 is a logical right shift, make an extraction. */
8150 {
8154 }
8156 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8163 {
8170 /* If we narrowed the mode when dropping the subreg, then we lose. */
8174 /* If that didn't give anything, see if the AND simplifies on
8175 its own. */
8177 {
8181 }
8182 }
8183 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8189 {
8190 /* Apply the distributive law, and then try to make extractions. */
8197 }
8199 /* If we are have (and (rotate X C) M) and C is larger than the number
8200 of bits in M, this is an extraction. */
8206 {
8212 }
8214 /* On machines without logical shifts, if the operand of the AND is
8215 a logical shift and our mask turns off all the propagated sign
8216 bits, we can replace the logical shift with an arithmetic shift. */
8224 {
8234 next_code),
8236 }
8238 /* If the constant is one less than a power of two, this might be
8239 representable by an extraction even if no shift is present.
8240 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8241 we are in a COMPARE. */
8245 next_code),
8248 /* If we are in a comparison and this is an AND with a power of two,
8249 convert this into the appropriate bit extract. */
8255 next_code),
8258 /* If the one operand is a paradoxical subreg of a register or memory and
8259 the constant (limited to the smaller mode) has only zero bits where
8260 the sub expression has known zero bits, this can be expressed as
8261 a zero_extend. */
8263 {
8264 rtx sub;
8272 {
8276 /* original AND constant with all the known zero bits set */
8279 {
8283 }
8284 }
8285 }
8290 /* If the sign bit is known to be zero, replace this with an
8291 arithmetic shift. */
8296 {
8299 next_code),
8302 }
8304 /* fall through */
8310 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8311 this is a SIGN_EXTRACT. */
8318 {
8325 }
8327 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8328 If so, try to merge the shifts into a SIGN_EXTEND. We could
8329 also do this for some cases of SIGN_EXTRACT, but it doesn't
8330 seem worth the effort; the case checked for occurs on Alpha. */
8341 next_code),
8348 /* Call ourselves recursively on the inner expression. If we are
8349 narrowing the object and it has a different RTL code from
8350 what it originally did, do this SUBREG as a force_to_mode. */
8351 {
8355 /* If the SUBREG is masking of a logical right shift,
8356 make an extraction. */
8363 {
8372 }
8374 /* If in_code is COMPARE, it isn't always safe to pass it through
8375 to the recursive make_compound_operation call. */
8379 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8380 is (const_int 0), rather than
8381 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8382 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8383 for non-equality comparisons against 0 is not equivalent
8384 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8394 simplified
8402 {
8403 rtx newer
8406 /* If we have something other than a SUBREG, we might have
8407 done an expansion, so rerun ourselves. */
8411 /* force_to_mode can expand compounds. If it just re-expanded
8412 the compound, use gen_lowpart to convert to the desired
8413 mode. */
8415 /* Likewise if it re-expanded the compound only partially.
8416 This happens for SUBREG of ZERO_EXTRACT if they extract
8417 the same number of bits. */
8426 }
8430 }
8435 }
8441 }
8443 /* Look at the expression rooted at X. Look for expressions
8444 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8445 Form these expressions.
8447 Return the new rtx, usually just X.
8449 Also, for machines like the VAX that don't have logical shift insns,
8450 try to convert logical to arithmetic shift operations in cases where
8451 they are equivalent. This undoes the canonicalizations to logical
8452 shifts done elsewhere.
8454 We try, as much as possible, to re-use rtl expressions to save memory.
8456 IN_CODE says what kind of expression we are processing. Normally, it is
8457 SET. In a memory address it is MEM. When processing the arguments of
8458 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8459 precisely it is an equality comparison against zero. */
8461 rtx
8463 {
8470 /* Select the code to be used in recursive calls. Once we are inside an
8471 address, we stay there. If we have a comparison, set to COMPARE,
8472 but once inside, go back to our default of SET. */
8479 scalar_int_mode mode;
8481 {
8487 }
8489 /* Now recursively process each operand of this operation. We need to
8490 handle ZERO_EXTEND specially so that we don't lose track of the
8491 inner mode. */
8493 {
8501 }
8506 {
8509 }
8512 {
8515 }
8519 }
8520 \f
8521 /* Given M see if it is a value that would select a field of bits
8522 within an item, but not the entire word. Return -1 if not.
8523 Otherwise, return the starting position of the field, where 0 is the
8524 low-order bit.
8526 *PLEN is set to the length of the field. */
8528 static int
8530 {
8531 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8536 /* Now shift off the low-order zero bits and see if we have a
8537 power of two minus 1. */
8545 }
8546 \f
8547 /* If X refers to a register that equals REG in value, replace these
8548 references with REG. */
8549 static rtx
8551 {
8559 {
8592 /* FALLTHRU */
8596 {
8600 else
8602 }
8604 /* fall through */
8611 {
8614 {
8616 {
8619 }
8621 }
8622 }
8624 {
8627 {
8630 {
8632 {
8635 }
8637 }
8638 }
8639 }
8642 }
8645 }
8647 /* Return X converted to MODE. If the value is already truncated to
8648 MODE we can just return a subreg even though in the general case we
8649 would need an explicit truncation. */
8651 static rtx
8653 {
8658 {
8659 /* Bit-cast X into an integer mode. */
8664 }
8667 }
8669 /* See if X can be simplified knowing that we will only refer to it in
8670 MODE and will only refer to those bits that are nonzero in MASK.
8671 If other bits are being computed or if masking operations are done
8672 that select a superset of the bits in MASK, they can sometimes be
8673 ignored.
8675 Return a possibly simplified expression, but always convert X to
8676 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8678 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8679 are all off in X. This is used when X will be complemented, by either
8680 NOT, NEG, or XOR. */
8682 static rtx
8685 {
8688 machine_mode op_mode;
8691 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8692 code below will do the wrong thing since the mode of such an
8693 expression is VOIDmode.
8695 Also do nothing if X is a CLOBBER; this can happen if X was
8696 the return value from a call to gen_lowpart. */
8700 /* We want to perform the operation in its present mode unless we know
8701 that the operation is valid in MODE, in which case we do the operation
8702 in MODE. */
8707 /* It is not valid to do a right-shift in a narrower mode
8708 than the one it came in with. */
8713 /* Truncate MASK to fit OP_MODE. */
8717 /* Determine what bits of X are guaranteed to be (non)zero. */
8720 /* If none of the bits in X are needed, return a zero. */
8724 /* If X is a CONST_INT, return a new one. Do this here since the
8725 test below will fail. */
8727 {
8730 else
8731 {
8734 }
8735 }
8737 /* If X is narrower than MODE and we want all the bits in X's mode, just
8738 get X in the proper mode. */
8743 /* We can ignore the effect of a SUBREG if it narrows the mode or
8744 if the constant masks to zero all the bits the mode doesn't have. */
8748 || (mask
8756 /* OP_MODE is either MODE or XMODE, so it must be a scalar
8757 integer too. */
8763 }
8765 /* Subroutine of force_to_mode that handles cases in which both X and
8766 the result are scalar integers. MODE is the mode of the result,
8767 XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8768 is preferred for simplified versions of X. The other arguments
8769 are as for force_to_mode. */
8771 static rtx
8775 {
8780 poly_int64 const_op0;
8782 /* When we have an arithmetic operation, or a shift whose count we
8783 do not know, we need to assume that all bits up to the highest-order
8784 bit in MASK will be needed. This is how we form such a mask. */
8787 else
8792 {
8794 /* If X is a (clobber (const_int)), return it since we know we are
8795 generating something that won't match. */
8808 /* Similarly for a truncate. */
8812 /* If this is an AND with a constant, convert it into an AND
8813 whose constant is the AND of that constant with MASK. If it
8814 remains an AND of MASK, delete it since it is redundant. */
8817 {
8822 /* If X is still an AND, see if it is an AND with a mask that
8823 is just some low-order bits. If so, and it is MASK, we don't
8824 need it. */
8830 /* If it remains an AND, try making another AND with the bits
8831 in the mode mask that aren't in MASK turned on. If the
8832 constant in the AND is wide enough, this might make a
8833 cheaper constant. */
8838 {
8839 unsigned HOST_WIDE_INT cval
8841 rtx y;
8848 }
8851 }
8856 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8857 low-order bits (as in an alignment operation) and FOO is already
8858 aligned to that boundary, mask C1 to that boundary as well.
8859 This may eliminate that PLUS and, later, the AND. */
8861 {
8865 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8866 number, sign extend it. */
8879 }
8881 /* fall through */
8884 /* Substituting into the operands of a widening MULT is not likely to
8885 create RTL matching a machine insn. */
8895 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8896 most significant bit in MASK since carries from those bits will
8897 affect the bits we are interested in. */
8902 /* If X is (minus C Y) where C's least set bit is larger than any bit
8903 in the mask, then we may replace with (neg Y). */
8906 {
8909 }
8911 /* Similarly, if C contains every bit in the fuller_mask, then we may
8912 replace with (not Y). */
8915 {
8918 }
8925 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8926 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8927 operation which may be a bitfield extraction. Ensure that the
8928 constant we form is not wider than the mode of X. */
8940 {
8943 xmode);
8949 }
8951 binop:
8952 /* For most binary operations, just propagate into the operation and
8953 change the mode if we have an operation of that mode. */
8958 /* If we ended up truncating both operands, truncate the result of the
8959 operation instead. */
8962 {
8965 }
8971 {
8974 }
8978 /* For left shifts, do the same, but just for the first operand.
8979 However, we cannot do anything with shifts where we cannot
8980 guarantee that the counts are smaller than the size of the mode
8981 because such a count will have a different meaning in a
8982 wider mode. */
8992 /* If the shift count is a constant and we can do arithmetic in
8993 the mode of the shift, refine which bits we need. Otherwise, use the
8994 conservative form of the mask. */
9000 else
9008 {
9011 }
9015 /* Here we can only do something if the shift count is a constant,
9016 this shift constant is valid for the host, and we can do arithmetic
9017 in OP_MODE. */
9023 {
9027 /* Select the mask of the bits we need for the shift operand. */
9030 /* We can only change the mode of the shift if we can do arithmetic
9031 in the mode of the shift and INNER_MASK is no wider than the
9032 width of X's mode. */
9039 {
9042 }
9043 }
9045 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
9046 shift and AND produces only copies of the sign bit (C2 is one less
9047 than a power of two), we can do this with just a shift. */
9051 /* The shift puts one of the sign bit copies in the least significant
9052 bit. */
9057 /* Number of bits left after the shift must be more than the mask
9058 needs. */
9061 /* Must be more sign bit copies than the mask needs. */
9064 {
9068 }
9072 /* If we are just looking for the sign bit, we don't need this shift at
9073 all, even if it has a variable count. */
9077 /* If this is a shift by a constant, get a mask that contains those bits
9078 that are not copies of the sign bit. We then have two cases: If
9079 MASK only includes those bits, this can be a logical shift, which may
9080 allow simplifications. If MASK is a single-bit field not within
9081 those bits, we are requesting a copy of the sign bit and hence can
9082 shift the sign bit to the appropriate location. */
9086 {
9090 /* If the considered data is wider than HOST_WIDE_INT, we can't
9091 represent a mask for all its bits in a single scalar.
9092 But we only care about the lower bits, so calculate these. */
9095 {
9098 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
9099 is the number of bits a full-width mask would have set.
9100 We need only shift if these are fewer than nonzero can
9101 hold. If not, we must keep all bits set in nonzero. */
9106 + HOST_BITS_PER_WIDE_INT
9108 }
9109 else
9110 {
9113 }
9116 {
9121 }
9124 {
9125 x = simplify_shift_const
9131 }
9132 }
9134 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9135 even if the shift count isn't a constant. */
9139 shiftrt:
9141 /* If this is a zero- or sign-extension operation that just affects bits
9142 we don't care about, remove it. Be sure the call above returned
9143 something that is still a shift. */
9153 next_select);
9159 /* If the shift count is constant and we can do computations
9160 in the mode of X, compute where the bits we care about are.
9161 Otherwise, we can't do anything. Don't change the mode of
9162 the shift or propagate MODE into the shift, though. */
9165 {
9174 }
9178 /* If we just want the low-order bit, the NEG isn't needed since it
9179 won't change the low-order bit. */
9183 /* We need any bits less significant than the most significant bit in
9184 MASK since carries from those bits will affect the bits we are
9185 interested in. */
9190 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9191 same as the XOR case above. Ensure that the constant we form is not
9192 wider than the mode of X. */
9200 {
9207 }
9209 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9210 use the full mask inside the NOT. */
9213 unop:
9216 next_select));
9218 {
9221 }
9225 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9226 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9227 which is equal to STORE_FLAG_VALUE. */
9239 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9240 written in a narrower mode. We play it safe and do not do so. */
9256 }
9258 /* Ensure we return a value of the proper mode. */
9260 }
9261 \f
9262 /* Return nonzero if X is an expression that has one of two values depending on
9263 whether some other value is zero or nonzero. In that case, we return the
9264 value that is being tested, *PTRUE is set to the value if the rtx being
9265 returned has a nonzero value, and *PFALSE is set to the other alternative.
9267 If we return zero, we set *PTRUE and *PFALSE to X. */
9269 static rtx
9271 {
9276 scalar_int_mode int_mode;
9278 /* If we are comparing a value against zero, we are done. */
9281 {
9285 }
9287 /* If this is a unary operation whose operand has one of two values, apply
9288 our opcode to compute those values. */
9291 {
9296 }
9298 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9299 make can't possibly match and would suppress other optimizations. */
9301 ;
9303 /* If this is a binary operation, see if either side has only one of two
9304 values. If either one does or if both do and they are conditional on
9305 the same value, compute the new true and false values. */
9307 {
9315 {
9316 /* Try to enable a simplification by undoing work done by
9317 if_then_else_cond if it converted a REG into something more
9318 complex. */
9320 {
9323 }
9324 else
9325 {
9328 }
9329 }
9333 {
9334 /* If if_then_else_cond returned zero, then true/false are the
9335 same rtl. We must copy one of them to prevent invalid rtl
9336 sharing. */
9343 {
9348 }
9349 else
9350 {
9353 }
9356 }
9358 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9359 operands is zero when the other is nonzero, and vice-versa,
9360 and STORE_FLAG_VALUE is 1 or -1. */
9366 {
9384 {
9391 const_true_rtx);
9393 }
9394 }
9396 /* Similarly for MULT, AND and UMIN, except that for these the result
9397 is always zero. */
9401 {
9415 {
9418 }
9419 }
9420 }
9423 {
9424 /* If we have IF_THEN_ELSE already, extract the condition and
9425 canonicalize it if it is NE or EQ. */
9431 {
9434 }
9435 else
9437 }
9439 /* If X is a SUBREG, we can narrow both the true and false values
9440 if the inner expression, if there is a condition. */
9444 {
9450 {
9454 }
9455 }
9457 /* If X is a constant, this isn't special and will cause confusions
9458 if we treat it as such. Likewise if it is equivalent to a constant. */
9461 ;
9463 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9464 will be least confusing to the rest of the compiler. */
9466 {
9469 }
9471 /* If X is known to be either 0 or -1, those are the true and
9472 false values when testing X. */
9477 {
9480 }
9482 /* Likewise for 0 or a single bit. */
9485 {
9488 }
9490 /* Otherwise fail; show no condition with true and false values the same. */
9493 }
9494 \f
9495 /* Return the value of expression X given the fact that condition COND
9496 is known to be true when applied to REG as its first operand and VAL
9497 as its second. X is known to not be shared and so can be modified in
9498 place.
9500 We only handle the simplest cases, and specifically those cases that
9501 arise with IF_THEN_ELSE expressions. */
9503 static rtx
9505 {
9513 /* If either operand of the condition is a floating point value,
9514 then we have to avoid collapsing an EQ comparison. */
9524 /* If X is (abs REG) and we know something about REG's relationship
9525 with zero, we may be able to simplify this. */
9529 {
9538 }
9540 /* The only other cases we handle are MIN, MAX, and comparisons if the
9541 operands are the same as REG and VAL. */
9544 {
9546 {
9549 }
9552 {
9554 {
9562 else
9564 }
9567 {
9570 /* Do not reverse the condition when it is NE or EQ.
9571 This is because we cannot conclude anything about
9572 the value of 'SMAX (x, y)' when x is not equal to y,
9573 but we can when x equals y. */
9579 {
9590 }
9591 }
9592 }
9593 }
9595 {
9600 {
9601 /* We must simplify subreg here, before we lose track of the
9602 original inner_mode. */
9607 else
9609 }
9612 }
9613 /* We don't have to handle SIGN_EXTEND here, because even in the
9614 case of replacing something with a modeless CONST_INT, a
9615 CONST_INT is already (supposed to be) a valid sign extension for
9616 its narrower mode, which implies it's already properly
9617 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9618 story is different. */
9620 {
9625 {
9626 /* We must simplify the zero_extend here, before we lose
9627 track of the original inner_mode. */
9632 else
9634 }
9637 }
9641 {
9648 }
9651 }
9652 \f
9653 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9654 assignment as a field assignment. */
9656 static int
9658 {
9660 {
9668 }
9676 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9677 Note that all SUBREGs of MEM are paradoxical; otherwise they
9678 would have been rewritten. */
9691 /* We used to see if get_last_value of X and Y were the same but that's
9692 not correct. In one direction, we'll cause the assignment to have
9693 the wrong destination and in the case, we'll import a register into this
9694 insn that might have already have been dead. So fail if none of the
9695 above cases are true. */
9697 }
9698 \f
9699 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9700 Return that assignment if so.
9702 We only handle the most common cases. */
9704 static rtx
9706 {
9709 rtx assign;
9711 HOST_WIDE_INT c1;
9712 HOST_WIDE_INT pos;
9714 rtx other;
9716 /* All the rules in this function are specific to scalar integers. */
9717 scalar_int_mode mode;
9721 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9722 a clear of a one-bit field. We will have changed it to
9723 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9724 for a SUBREG. */
9730 {
9736 }
9745 {
9752 }
9754 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9755 one-bit field. */
9759 {
9765 }
9767 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9768 SRC is an AND with all bits of that field set, then we can discard
9769 the AND. */
9774 {
9781 else
9784 /* Complete overlap. We can remove the source AND. */
9788 /* Partial overlap. We can reduce the source AND. */
9790 {
9794 }
9795 }
9797 /* The other case we handle is assignments into a constant-position
9798 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9799 a mask that has all one bits except for a group of zero bits and
9800 OTHER is known to have zeros where C1 has ones, this is such an
9801 assignment. Compute the position and length from C1. Shift OTHER
9802 to the appropriate position, force it to the required mode, and
9803 make the extraction. Check for the AND in both operands. */
9805 /* One or more SUBREGs might obscure the constant-position field
9806 assignment. The first one we are likely to encounter is an outer
9807 narrowing SUBREG, which we can just strip for the purposes of
9808 identifying the constant-field assignment. */
9825 /* The second SUBREG that might get in the way is a paradoxical
9826 SUBREG around the first operand of the AND. We want to
9827 pretend the operand is as wide as the destination here. We
9828 do this by adjusting the MEM to wider mode for the sole
9829 purpose of the call to rtx_equal_for_field_assignment_p. Also
9830 note this trick only works for MEMs. */
9842 /* The second SUBREG that might get in the way is a paradoxical
9843 SUBREG around the first operand of the AND. We want to
9844 pretend the operand is as wide as the destination here. We
9845 do this by adjusting the MEM to wider mode for the sole
9846 purpose of the call to rtx_equal_for_field_assignment_p. Also
9847 note this trick only works for MEMs. */
9855 else
9869 /* The mode to use for the source is the mode of the assignment, or of
9870 what is inside a possible STRICT_LOW_PART. */
9874 /* Shift OTHER right POS places and make it the source, restricting it
9875 to the proper length and mode. */
9879 dest);
9881 len >= HOST_BITS_PER_WIDE_INT
9882 ? HOST_WIDE_INT_M1U
9886 /* If SRC is masked by an AND that does not make a difference in
9887 the value being stored, strip it. */
9898 }
9899 \f
9900 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9901 if so. */
9903 static rtx
9905 {
9909 rtx tem;
9911 /* Distributivity is not true for floating point as it can change the
9912 value. So we don't do it unless -funsafe-math-optimizations. */
9917 /* The outer operation can only be one of the following: */
9925 /* If either operand is a primitive we can't do anything, so get out
9926 fast. */
9936 /* See if the inner and outer operations distribute. */
9938 {
9943 /* These all distribute except over PLUS. */
9954 /* This is also a multiply, so it distributes over everything. */
9957 /* This used to handle SUBREG, but this turned out to be counter-
9958 productive, since (subreg (op ...)) usually is not handled by
9959 insn patterns, and this "optimization" therefore transformed
9960 recognizable patterns into unrecognizable ones. Therefore the
9961 SUBREG case was removed from here.
9963 It is possible that distributing SUBREG over arithmetic operations
9964 leads to an intermediate result than can then be optimized further,
9965 e.g. by moving the outer SUBREG to the other side of a SET as done
9966 in simplify_set. This seems to have been the original intent of
9967 handling SUBREGs here.
9969 However, with current GCC this does not appear to actually happen,
9970 at least on major platforms. If some case is found where removing
9971 the SUBREG case here prevents follow-on optimizations, distributing
9972 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9976 }
9978 /* Set LHS and RHS to the inner operands (A and B in the example
9979 above) and set OTHER to the common operand (C in the example).
9980 There is only one way to do this unless the inner operation is
9981 commutative. */
9993 else
9996 /* Form the new inner operation, seeing if it simplifies first. */
9999 /* There is one exception to the general way of distributing:
10000 (a | c) ^ (b | c) -> (a ^ b) & ~c */
10002 {
10005 }
10007 /* We may be able to continuing distributing the result, so call
10008 ourselves recursively on the inner operation before forming the
10009 outer operation, which we return. */
10012 }
10014 /* See if X is of the form (* (+ A B) C), and if so convert to
10015 (+ (* A C) (* B C)) and try to simplify.
10017 Most of the time, this results in no change. However, if some of
10018 the operands are the same or inverses of each other, simplifications
10019 will result.
10021 For example, (and (ior A B) (not B)) can occur as the result of
10022 expanding a bit field assignment. When we apply the distributive
10023 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
10024 which then simplifies to (and (A (not B))).
10026 Note that no checks happen on the validity of applying the inverse
10027 distributive law. This is pointless since we can do it in the
10028 few places where this routine is called.
10030 N is the index of the term that is decomposed (the arithmetic operation,
10031 i.e. (+ A B) in the first example above). !N is the index of the term that
10032 is distributed, i.e. of C in the first example above. */
10033 static rtx
10035 {
10036 machine_mode mode;
10040 /* Distributivity is not true for floating point as it can change the
10041 value. So we don't do it unless -funsafe-math-optimizations. */
10058 /* Special case (and (xor B C) (not A)), which is equivalent to
10059 (xor (ior A B) (ior A C)) */
10061 {
10064 }
10067 {
10068 /* Distribute the second term. */
10071 }
10072 else
10073 {
10074 /* Distribute the first term. */
10077 }
10087 }
10088 \f
10089 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
10090 in MODE. Return an equivalent form, if different from (and VAROP
10091 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
10093 static rtx
10096 {
10099 rtx orig_varop;
10107 /* Simplify VAROP knowing that we will be only looking at some of the
10108 bits in it.
10110 Note by passing in CONSTOP, we guarantee that the bits not set in
10111 CONSTOP are not significant and will never be examined. We must
10112 ensure that is the case by explicitly masking out those bits
10113 before returning. */
10116 /* If VAROP is a CLOBBER, we will fail so return it. */
10120 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10121 to VAROP and return the new constant. */
10125 /* See what bits may be nonzero in VAROP. Unlike the general case of
10126 a call to nonzero_bits, here we don't care about bits outside
10127 MODE. */
10131 /* Turn off all bits in the constant that are known to already be zero.
10132 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10133 which is tested below. */
10137 /* If we don't have any bits left, return zero. */
10141 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10142 a power of two, we can replace this with an ASHIFT. */
10147 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10148 or XOR, then try to apply the distributive law. This may eliminate
10149 operations if either branch can be simplified because of the AND.
10150 It may also make some cases more complex, but those cases probably
10151 won't match a pattern either with or without this. */
10154 {
10156 return
10157 gen_lowpart
10159 apply_distributive_law
10163 constop),
10166 constop))));
10167 }
10169 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10170 the AND and see if one of the operands simplifies to zero. If so, we
10171 may eliminate it. */
10175 {
10184 }
10186 /* Make a SUBREG if necessary. If we can't make it, fail. */
10191 /* If we are only masking insignificant bits, return VAROP. */
10198 /* Otherwise, return an AND. */
10200 }
10203 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10204 in MODE.
10206 Return an equivalent form, if different from X. Otherwise, return X. If
10207 X is zero, we are to always construct the equivalent form. */
10209 static rtx
10212 {
10223 }
10224 \f
10225 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10226 We don't care about bits outside of those defined in MODE.
10228 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10229 a shift, AND, or zero_extract, we can do better. */
10231 static rtx
10233 scalar_int_mode mode,
10235 {
10236 rtx tem;
10239 /* If X is a register whose nonzero bits value is current, use it.
10240 Otherwise, if X is a register whose value we can find, use that
10241 value. Otherwise, use the previously-computed global nonzero bits
10242 for this register. */
10257 && !REGNO_REG_SET_P
10260 {
10261 /* Note that, even if the precision of last_set_mode is lower than that
10262 of mode, record_value_for_reg invoked nonzero_bits on the register
10263 with nonzero_bits_mode (because last_set_mode is necessarily integral
10264 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10265 are all valid, hence in mode too since nonzero_bits_mode is defined
10266 to the largest HWI_COMPUTABLE_MODE_P mode. */
10269 }
10273 {
10278 }
10281 {
10285 /* We don't know anything about the upper bits. */
10289 }
10292 }
10294 /* Given a reg X of mode XMODE, return the number of bits at the high-order
10295 end of X that are known to be equal to the sign bit. X will be used
10296 in mode MODE; the returned value will always be between 1 and the
10297 number of bits in MODE. */
10299 static rtx
10301 scalar_int_mode mode,
10303 {
10304 rtx tem;
10317 && !REGNO_REG_SET_P
10320 {
10323 }
10334 }
10335 \f
10336 /* Return the number of "extended" bits there are in X, when interpreted
10337 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10338 unsigned quantities, this is the number of high-order zero bits.
10339 For signed quantities, this is the number of copies of the sign bit
10340 minus 1. In both case, this function returns the number of "spare"
10341 bits. For example, if two quantities for which this function returns
10342 at least 1 are added, the addition is known not to overflow.
10344 This function will always return 0 unless called during combine, which
10345 implies that it must be called from a define_split. */
10347 unsigned int
10349 {
10353 scalar_int_mode int_mode;
10361 }
10363 /* This function is called from `simplify_shift_const' to merge two
10364 outer operations. Specifically, we have already found that we need
10365 to perform operation *POP0 with constant *PCONST0 at the outermost
10366 position. We would now like to also perform OP1 with constant CONST1
10367 (with *POP0 being done last).
10369 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10370 the resulting operation. *PCOMP_P is set to 1 if we would need to
10371 complement the innermost operand, otherwise it is unchanged.
10373 MODE is the mode in which the operation will be done. No bits outside
10374 the width of this mode matter. It is assumed that the width of this mode
10375 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10377 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10378 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10379 result is simply *PCONST0.
10381 If the resulting operation cannot be expressed as one operation, we
10382 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10384 static int
10385 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
10386 {
10393 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10397 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10398 if OP0 is SET. */
10407 {
10409 {
10427 }
10428 }
10430 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10434 /* If the two constants aren't the same, we can't do anything. The
10435 remaining six cases can all be done. */
10439 else
10441 {
10444 /* (a & b) | b == b */
10447 /* (a ^ b) | b == a | b */
10448 {;}
10453 /* (a & b) ^ b == (~a) & b */
10456 /* (a | b) ^ b == a & ~b */
10462 /* (a | b) & b == b */
10465 /* (a ^ b) & b) == (~a) & b */
10470 }
10472 /* Check for NO-OP cases. */
10485 /* ??? Slightly redundant with the above mask, but not entirely.
10486 Moving this above means we'd have to sign-extend the mode mask
10487 for the final test. */
10492 }
10493 \f
10494 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10495 the shift in. The original shift operation CODE is performed on OP in
10496 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10497 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10498 result of the shift is subject to operation OUTER_CODE with operand
10499 OUTER_CONST. */
10501 static scalar_int_mode
10505 {
10508 /* In general we can't perform in wider mode for right shift and rotate. */
10510 {
10512 /* We can still widen if the bits brought in from the left are identical
10513 to the sign bit of ORIG_MODE. */
10521 /* Similarly here but with zero bits. */
10526 /* We can also widen if the bits brought in will be masked off. This
10527 operation is performed in ORIG_MODE. */
10529 {
10535 }
10536 /* fall through */
10546 }
10547 }
10549 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10550 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10551 if we cannot simplify it. Otherwise, return a simplified value.
10553 The shift is normally computed in the widest mode we find in VAROP, as
10554 long as it isn't a different number of words than RESULT_MODE. Exceptions
10555 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10557 static rtx
10560 {
10565 machine_mode shift_mode;
10567 /* We form (outer_op (code varop count) (outer_const)). */
10573 /* Make sure and truncate the "natural" shift on the way in. We don't
10574 want to do this inside the loop as it makes it more difficult to
10575 combine shifts. */
10579 /* If we were given an invalid count, don't do anything except exactly
10580 what was requested. */
10587 /* Unless one of the branches of the `if' in this loop does a `continue',
10588 we will `break' the loop after the `if'. */
10591 {
10592 /* If we have an operand of (clobber (const_int 0)), fail. */
10596 /* Convert ROTATERT to ROTATE. */
10598 {
10602 }
10606 {
10607 /* We only change the modes of scalar shifts. */
10613 }
10615 scalar_int_mode shift_unit_mode
10618 /* Handle cases where the count is greater than the size of the mode
10619 minus 1. For ASHIFT, use the size minus one as the count (this can
10620 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10621 take the count modulo the size. For other shifts, the result is
10622 zero.
10624 Since these shifts are being produced by the compiler by combining
10625 multiple operations, each of which are defined, we know what the
10626 result is supposed to be. */
10629 {
10634 else
10635 {
10636 /* We can't simply return zero because there may be an
10637 outer op. */
10641 }
10642 }
10644 /* If we discovered we had to complement VAROP, leave. Making a NOT
10645 here would cause an infinite loop. */
10650 {
10651 /* An arithmetic right shift of a quantity known to be -1 or 0
10652 is a no-op. */
10656 {
10659 }
10661 /* If we are doing an arithmetic right shift and discarding all but
10662 the sign bit copies, this is equivalent to doing a shift by the
10663 bitsize minus one. Convert it into that shift because it will
10664 often allow other simplifications. */
10671 /* We simplify the tests below and elsewhere by converting
10672 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10673 `make_compound_operation' will convert it to an ASHIFTRT for
10674 those machines (such as VAX) that don't have an LSHIFTRT. */
10679 shift_unit_mode)))
10691 }
10694 {
10701 {
10704 }
10708 /* The following rules apply only to scalars. */
10713 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10714 minus the width of a smaller mode, we can do this with a
10715 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10722 {
10731 }
10735 /* The following rules apply only to scalars. */
10741 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10742 the same number of words as what we've seen so far. Then store
10743 the widest mode in MODE. */
10750 {
10755 }
10759 /* Some machines use MULT instead of ASHIFT because MULT
10760 is cheaper. But it is still better on those machines to
10761 merge two shifts into one. */
10764 {
10769 }
10773 /* Similar, for when divides are cheaper. */
10776 {
10781 }
10785 /* If we are extracting just the sign bit of an arithmetic
10786 right shift, that shift is not needed. However, the sign
10787 bit of a wider mode may be different from what would be
10788 interpreted as the sign bit in a narrower mode, so, if
10789 the result is narrower, don't discard the shift. */
10794 {
10797 }
10799 /* fall through */
10804 /* The following rules apply only to scalars. */
10811 /* Here we have two nested shifts. The result is usually the
10812 AND of a new shift with a mask. We compute the result below. */
10818 {
10822 rtx mask_rtx;
10824 /* We have one common special case. We can't do any merging if
10825 the inner code is an ASHIFTRT of a smaller mode. However, if
10826 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10827 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10828 we can convert it to
10829 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10830 This simplifies certain SIGN_EXTEND operations. */
10834 {
10835 /* C3 has the low-order C1 bits zero. */
10847 }
10849 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10850 than C1 high-order bits equal to the sign bit, we can convert
10851 this to either an ASHIFT or an ASHIFTRT depending on the
10852 two counts.
10854 We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10860 {
10864 {
10867 }
10870 }
10872 /* There are some cases we can't do. If CODE is ASHIFTRT,
10873 we can only do this if FIRST_CODE is also ASHIFTRT.
10875 We can't do the case when CODE is ROTATE and FIRST_CODE is
10876 ASHIFTRT.
10878 If the mode of this shift is not the mode of the outer shift,
10879 we can't do this if either shift is a right shift or ROTATE.
10881 Finally, we can't do any of these if the mode is too wide
10882 unless the codes are the same.
10884 Handle the case where the shift codes are the same
10885 first. */
10888 {
10897 }
10908 /* To compute the mask to apply after the shift, shift the
10909 nonzero bits of the inner shift the same way the
10910 outer shift will. */
10913 int_result_mode);
10915 mask_rtx
10919 /* Give up if we can't compute an outer operation to use. */
10927 /* If the shifts are in the same direction, we add the
10928 counts. Otherwise, we subtract them. */
10932 else
10935 /* If COUNT is positive, the new shift is usually CODE,
10936 except for the two exceptions below, in which case it is
10937 FIRST_CODE. If the count is negative, FIRST_CODE should
10938 always be used */
10948 }
10950 /* If we have (A << B << C) for any shift, we can convert this to
10951 (A << C << B). This wins if A is a constant. Only try this if
10952 B is not a constant. */
10957 {
10958 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10959 sure the result will be masked. See PR70222. */
10967 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10968 up outer sign extension (often left and right shift) is
10969 hardly more efficient than the original. See PR70429. */
10976 count_rtx);
10980 }
10984 /* The following rules apply only to scalars. */
10988 /* Make this fit the case below. */
10995 /* The following rules apply only to scalars. */
11001 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
11002 with C the size of VAROP - 1 and the shift is logical if
11003 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11004 we have an (le X 0) operation. If we have an arithmetic shift
11005 and STORE_FLAG_VALUE is 1 or we have a logical shift with
11006 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
11014 {
11017 const0_rtx);
11023 }
11025 /* If we have (shift (logical)), move the logical to the outside
11026 to allow it to possibly combine with another logical and the
11027 shift to combine with another shift. This also canonicalizes to
11028 what a ZERO_EXTRACT looks like. Also, some machines have
11029 (and (shift)) insns. */
11032 /* We can't do this if we have (ashiftrt (xor)) and the
11033 constant has its sign bit set in shift_unit_mode with
11034 shift_unit_mode wider than result_mode. */
11047 {
11050 }
11052 /* If we can't do that, try to simplify the shift in each arm of the
11053 logical expression, make a new logical expression, and apply
11054 the inverse distributive law. This also can't be done for
11055 (ashiftrt (xor)) where we've widened the shift and the constant
11056 changes the sign bit. */
11062 {
11074 }
11078 /* The following rules apply only to scalars. */
11083 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
11084 says that the sign bit can be tested, FOO has mode MODE, C is
11085 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
11086 that may be nonzero. */
11096 {
11100 }
11104 /* The following rules apply only to scalars. */
11109 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
11110 than the number of bits in the mode is equivalent to A. */
11114 {
11118 }
11120 /* NEG commutes with ASHIFT since it is multiplication. Move the
11121 NEG outside to allow shifts to combine. */
11125 {
11128 }
11132 /* The following rules apply only to scalars. */
11137 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11138 is one less than the number of bits in the mode is
11139 equivalent to (xor A 1). */
11146 {
11150 }
11152 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11153 that might be nonzero in BAR are those being shifted out and those
11154 bits are known zero in FOO, we can replace the PLUS with FOO.
11155 Similarly in the other operand order. This code occurs when
11156 we are computing the size of a variable-size array. */
11163 {
11166 }
11174 {
11177 }
11179 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11190 {
11193 }
11195 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11196 signbit', and attempt to change the PLUS to an XOR and move it to
11197 the outer operation as is done above in the AND/IOR/XOR case
11198 leg for shift(logical). See details in logical handling above
11199 for reasoning in doing so. */
11211 {
11214 }
11219 /* The following rules apply only to scalars. */
11224 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11225 with C the size of VAROP - 1 and the shift is logical if
11226 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11227 we have a (gt X 0) operation. If the shift is arithmetic with
11228 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11229 we have a (neg (gt X 0)) operation. */
11238 {
11241 const0_rtx);
11247 }
11251 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11252 if the truncate does not affect the value. */
11259 {
11263 new_count);
11266 new_count_rtx);
11270 }
11275 }
11278 }
11282 {
11283 /* We only change the modes of scalar shifts. */
11288 }
11290 /* We have now finished analyzing the shift. The result should be
11291 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11292 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11293 to the result of the shift. OUTER_CONST is the relevant constant,
11294 but we must turn off all bits turned off in the shift. */
11302 /* Make a SUBREG if necessary. If we can't make it, fail. */
11307 /* If we have an outer operation and we just made a shift, it is
11308 possible that we could have simplified the shift were it not
11309 for the outer operation. So try to do the simplification
11310 recursively. */
11314 else
11321 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11322 turn off all the bits that the shift would have turned off. */
11324 /* We only change the modes of scalar shifts. */
11328 /* Do the remainder of the processing in RESULT_MODE. */
11331 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11332 operation. */
11337 {
11347 {
11348 /* This means that we have determined that the result is
11349 equivalent to a constant. This should be rare. */
11352 }
11355 else
11358 }
11361 }
11363 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11364 The result of the shift is RESULT_MODE. If we cannot simplify it,
11365 return X or, if it is NULL, synthesize the expression with
11366 simplify_gen_binary. Otherwise, return a simplified value.
11368 The shift is normally computed in the widest mode we find in VAROP, as
11369 long as it isn't a different number of words than RESULT_MODE. Exceptions
11370 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11372 static rtx
11375 {
11386 }
11388 \f
11389 /* A subroutine of recog_for_combine. See there for arguments and
11390 return value. */
11392 static int
11394 {
11396 rtx pat_without_clobbers;
11404 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11405 we use to indicate that something didn't match. If we find such a
11406 thing, force rejection. */
11420 {
11423 else
11426 }
11428 /* If it isn't, there is the possibility that we previously had an insn
11429 that clobbered some register as a side effect, but the combined
11430 insn doesn't need to do that. So try once more without the clobbers
11431 unless this represents an ASM insn. */
11435 {
11440 {
11443 pos++;
11444 }
11454 {
11457 else
11460 }
11461 }
11468 /* Recognize all noop sets, these will be killed by followup pass. */
11472 /* If we had any clobbers to add, make a new pattern than contains
11473 them. Then check to make sure that all of them are dead. */
11475 {
11485 else
11492 {
11497 {
11501 }
11502 }
11504 }
11508 {
11516 /* Allow targets to reject combined insn. */
11518 {
11521 dump_file);
11523 /* Callers expect recog_for_combine to strip
11524 clobbers from the pattern on failure. */
11529 }
11534 }
11540 }
11542 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11543 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11544 Return whether anything was so changed. */
11546 static bool
11548 {
11554 {
11566 {
11576 else
11580 {
11586 }
11587 }
11593 {
11598 {
11604 }
11605 }
11610 {
11614 }
11615 else
11621 {
11624 }
11628 }
11635 scalar_int_mode mode;
11641 {
11655 else
11663 }
11666 }
11668 /* Like recog, but we receive the address of a pointer to a new pattern.
11669 We try to match the rtx that the pointer points to.
11670 If that fails, we may try to modify or replace the pattern,
11671 storing the replacement into the same pointer object.
11673 Modifications include deletion or addition of CLOBBERs. If the
11674 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11675 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11676 (and undo if that fails).
11678 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11679 the CLOBBERs are placed.
11681 The value is the final insn code from the pattern ultimately matched,
11682 or -1. */
11684 static int
11686 {
11698 {
11701 {
11705 }
11706 }
11709 {
11714 }
11717 }
11718 \f
11719 /* Like gen_lowpart_general but for use by combine. In combine it
11720 is not possible to create any new pseudoregs. However, it is
11721 safe to create invalid memory addresses, because combine will
11722 try to recognize them and all they will do is make the combine
11723 attempt fail.
11725 If for some reason this cannot do its job, an rtx
11726 (clobber (const_int 0)) is returned.
11727 An insn containing that will not be recognized. */
11729 static rtx
11731 {
11733 rtx result;
11738 /* We can only support MODE being wider than a word if X is a
11739 constant integer or has a mode the same size. */
11745 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11746 won't know what to do. So we will strip off the SUBREG here and
11747 process normally. */
11749 {
11752 /* For use in case we fall down into the address adjustments
11753 further below, we need to adjust the known mode and size of
11754 x; imode and isize, since we just adjusted x. */
11759 }
11767 {
11768 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11769 address. */
11774 /* If we want to refer to something bigger than the original memref,
11775 generate a paradoxical subreg instead. That will force a reload
11776 of the original memref X. */
11782 }
11784 /* If X is a comparison operator, rewrite it in a new mode. This
11785 probably won't match, but may allow further simplifications. */
11789 /* If we couldn't simplify X any other way, just enclose it in a
11790 SUBREG. Normally, this SUBREG won't match, but some patterns may
11791 include an explicit SUBREG or we may simplify it further in combine. */
11792 else
11793 {
11794 rtx res;
11797 {
11802 }
11806 }
11808 fail:
11810 }
11811 \f
11812 /* Try to simplify a comparison between OP0 and a constant OP1,
11813 where CODE is the comparison code that will be tested, into a
11814 (CODE OP0 const0_rtx) form.
11816 The result is a possibly different comparison code to use.
11817 *POP1 may be updated. */
11819 static enum rtx_code
11822 {
11823 scalar_int_mode int_mode;
11826 /* Get the constant we are comparing against and turn off all bits
11827 not on in our mode. */
11831 /* If we are comparing against a constant power of two and the value
11832 being compared can only have that single bit nonzero (e.g., it was
11833 `and'ed with that bit), we can replace this with a comparison
11834 with zero. */
11843 {
11846 }
11848 /* Similarly, if we are comparing a value known to be either -1 or
11849 0 with -1, change it to the opposite comparison against zero. */
11855 {
11858 }
11860 /* Do some canonicalizations based on the comparison code. We prefer
11861 comparisons against zero and then prefer equality comparisons.
11862 If we can reduce the size of a constant, we will do that too. */
11864 {
11866 /* < C is equivalent to <= (C - 1) */
11868 {
11871 /* ... fall through to LE case below. */
11873 }
11874 else
11878 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11880 {
11883 }
11885 /* If we are doing a <= 0 comparison on a value known to have
11886 a zero sign bit, we can replace this with == 0. */
11897 /* >= C is equivalent to > (C - 1). */
11899 {
11902 /* ... fall through to GT below. */
11904 }
11905 else
11909 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11911 {
11914 }
11916 /* If we are doing a > 0 comparison on a value known to have
11917 a zero sign bit, we can replace this with != 0. */
11928 /* < C is equivalent to <= (C - 1). */
11930 {
11933 /* ... fall through ... */
11935 }
11936 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11941 {
11945 }
11946 else
11950 /* unsigned <= 0 is equivalent to == 0 */
11953 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11957 == ((HOST_WIDE_INT_1U
11959 {
11962 }
11966 /* >= C is equivalent to > (C - 1). */
11968 {
11971 /* ... fall through ... */
11973 }
11975 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11980 {
11984 }
11985 else
11989 /* unsigned > 0 is equivalent to != 0 */
11992 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11996 == (HOST_WIDE_INT_1U
11998 {
12001 }
12006 }
12010 }
12011 \f
12012 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
12013 comparison code that will be tested.
12015 The result is a possibly different comparison code to use. *POP0 and
12016 *POP1 may be updated.
12018 It is possible that we might detect that a comparison is either always
12019 true or always false. However, we do not perform general constant
12020 folding in combine, so this knowledge isn't useful. Such tautologies
12021 should have been detected earlier. Hence we ignore all such cases. */
12023 static enum rtx_code
12025 {
12031 opt_scalar_int_mode tmode_iter;
12033 /* Try a few ways of applying the same transformation to both operands. */
12035 {
12036 /* The test below this one won't handle SIGN_EXTENDs on these machines,
12037 so check specially. */
12056 {
12059 }
12061 /* If both operands are the same constant shift, see if we can ignore the
12062 shift. We can if the shift is a rotate or if the bits shifted out of
12063 this shift are known to be zero for both inputs and if the type of
12064 comparison is compatible with the shift. */
12077 {
12090 else
12092 }
12094 /* If both operands are AND's of a paradoxical SUBREG by constant, the
12095 SUBREGs are of the same mode, and, in both cases, the AND would
12096 be redundant if the comparison was done in the narrower mode,
12097 do the comparison in the narrower mode (e.g., we are AND'ing with 1
12098 and the operand's possibly nonzero bits are 0xffffff01; in that case
12099 if we only care about QImode, we don't need the AND). This case
12100 occurs if the output mode of an scc insn is not SImode and
12101 STORE_FLAG_VALUE == 1 (e.g., the 386).
12103 Similarly, check for a case where the AND's are ZERO_EXTEND
12104 operations from some narrower mode even though a SUBREG is not
12105 present. */
12110 {
12126 {
12130 /* The resulting comparison is always unsigned since we masked
12131 off the original sign bit. */
12135 }
12141 {
12147 }
12151 }
12153 /* If both operands are NOT, we can strip off the outer operation
12154 and adjust the comparison code for swapped operands; similarly for
12155 NEG, except that this must be an equality comparison. */
12161 else
12163 }
12165 /* If the first operand is a constant, swap the operands and adjust the
12166 comparison code appropriately, but don't do this if the second operand
12167 is already a constant integer. */
12169 {
12172 }
12174 /* We now enter a loop during which we will try to simplify the comparison.
12175 For the most part, we only are concerned with comparisons with zero,
12176 but some things may really be comparisons with zero but not start
12177 out looking that way. */
12180 {
12182 scalar_int_mode int_mode;
12186 HOST_WIDE_INT const_op;
12188 /* We only want to handle integral modes. This catches VOIDmode,
12189 CCmode, and the floating-point modes. An exception is that we
12190 can handle VOIDmode if OP0 is a COMPARE or a comparison
12191 operation. */
12198 /* Try to simplify the compare to constant, possibly changing the
12199 comparison op, and/or changing op1 to zero. */
12203 /* Compute some predicates to simplify code below. */
12210 /* If this is a sign bit comparison and we can do arithmetic in
12211 MODE, say that we will only be needing the sign bit of OP0. */
12216 HOST_WIDE_INT_1U
12221 {
12222 /* We can't do anything if OP0 is a condition code value, rather
12223 than an actual data value. */
12229 /* Get the two operands being compared. */
12232 else
12235 /* Check for the cases where we simply want the result of the
12236 earlier test or the opposite of that result. */
12240 {
12244 else
12248 {
12253 }
12254 }
12256 }
12262 /* Now try cases based on the opcode of OP0. If none of the cases
12263 does a "continue", we exit this loop immediately after the
12264 switch. */
12269 {
12271 /* If we are extracting a single bit from a variable position in
12272 a constant that has only a single bit set and are comparing it
12273 with zero, we can convert this into an equality comparison
12274 between the position and the location of the single bit. */
12275 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12276 have already reduced the shift count modulo the word size. */
12282 {
12290 /* Result is nonzero iff shift count is equal to I. */
12293 }
12295 /* fall through */
12300 {
12303 }
12307 /* If testing for equality, we can take the NOT of the constant. */
12310 {
12314 }
12316 /* If just looking at the sign bit, reverse the sense of the
12317 comparison. */
12319 {
12323 }
12327 /* If testing for equality, we can take the NEG of the constant. */
12330 {
12334 }
12336 /* The remaining cases only apply to comparisons with zero. */
12340 /* When X is ABS or is known positive,
12341 (neg X) is < 0 if and only if X != 0. */
12349 {
12353 }
12355 /* If we have NEG of something whose two high-order bits are the
12356 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12358 {
12362 }
12366 /* If we are testing equality and our count is a constant, we
12367 can perform the inverse operation on our RHS. */
12371 {
12375 }
12377 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12378 a particular bit. Convert it to an AND of a constant of that
12379 bit. This will be converted into a ZERO_EXTRACT. */
12383 {
12385 (HOST_WIDE_INT_1U
12390 }
12392 /* Fall through. */
12395 /* ABS is ignorable inside an equality comparison with zero. */
12397 {
12400 }
12404 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12405 (compare FOO CONST) if CONST fits in FOO's mode and we
12406 are either testing inequality or have an unsigned
12407 comparison with ZERO_EXTEND or a signed comparison with
12408 SIGN_EXTEND. But don't do it if we don't have a compare
12409 insn of the given mode, since we'd have to revert it
12410 later on, and then we wouldn't know whether to sign- or
12411 zero-extend. */
12413 && ! unsigned_comparison_p
12417 {
12420 }
12424 /* Check for the case where we are comparing A - C1 with C2, that is
12426 (subreg:MODE (plus (A) (-C1))) op (C2)
12428 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12429 comparison in the wider mode. One of the following two conditions
12430 must be true in order for this to be valid:
12432 1. The mode extension results in the same bit pattern being added
12433 on both sides and the comparison is equality or unsigned. As
12434 C2 has been truncated to fit in MODE, the pattern can only be
12435 all 0s or all 1s.
12437 2. The mode extension results in the sign bit being copied on
12438 each side.
12440 The difficulty here is that we have predicates for A but not for
12441 (A - C1) so we need to check that C1 is within proper bounds so
12442 as to perturbate A as little as possible. */
12451 {
12459 /* (A - C1) zero-extends if it is positive and sign-extends
12460 if it is negative, C2 both zero- and sign-extends. */
12464 /* (A - C1) sign-extends if it is positive and 1-extends
12465 if it is negative, C2 both sign- and 1-extends. */
12472 /* (A - C1) always sign-extends, like C2. */
12476 {
12479 }
12480 }
12482 /* If the inner mode is narrower and we are extracting the low part,
12483 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12485 ;
12494 {
12495 /* Remove outer subregs that don't do anything. */
12500 {
12504 }
12506 }
12507 else
12510 /* FALLTHROUGH */
12519 {
12522 }
12526 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12527 this for equality comparisons due to pathological cases involving
12528 overflows. */
12532 {
12536 }
12538 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12541 {
12545 }
12549 /* We used to optimize signed comparisons against zero, but that
12550 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12551 arrive here as equality comparisons, or (GEU, LTU) are
12552 optimized away. No need to special-case them. */
12554 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12555 (eq B (minus A C)), whichever simplifies. We can only do
12556 this for equality comparisons due to pathological cases involving
12557 overflows. */
12561 {
12565 }
12570 {
12574 }
12576 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12577 of bits in X minus 1, is one iff X > 0. */
12582 {
12586 }
12590 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12591 if C is zero or B is a constant. */
12595 {
12599 }
12604 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12605 iff X <= 0. */
12609 {
12613 }
12617 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12618 will be converted to a ZERO_EXTRACT later. */
12622 {
12627 }
12629 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12630 zero and X is a comparison and C1 and C2 describe only bits set
12631 in STORE_FLAG_VALUE, we can compare with X. */
12639 {
12646 {
12649 }
12650 }
12652 /* If we are doing an equality comparison of an AND of a bit equal
12653 to the sign bit, replace this with a LT or GE comparison of
12654 the underlying value. */
12661 {
12665 }
12667 /* If this AND operation is really a ZERO_EXTEND from a narrower
12668 mode, the constant fits within that mode, and this is either an
12669 equality or unsigned comparison, try to do this comparison in
12670 the narrower mode.
12672 Note that in:
12674 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12675 -> (ne:DI (reg:SI 4) (const_int 0))
12677 unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12678 known to hold a value of the required mode the
12679 transformation is invalid. */
12687 {
12690 }
12692 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12693 fits in both M1 and M2 and the SUBREG is either paradoxical
12694 or represents the low part, permute the SUBREG and the AND
12695 and try again. */
12698 {
12700 /* Require an integral mode, to avoid creating something like
12701 (AND:SF ...). */
12704 /* It is unsafe to commute the AND into the SUBREG if the
12705 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12706 not defined. As originally written the upper bits
12707 have a defined value due to the AND operation.
12708 However, if we commute the AND inside the SUBREG then
12709 they no longer have defined values and the meaning of
12710 the code has been changed.
12711 Also C1 should not change value in the smaller mode,
12712 see PR67028 (a positive C1 can become negative in the
12713 smaller mode, so that the AND does no longer mask the
12714 upper bits). */
12715 && ((WORD_REGISTER_OPERATIONS
12727 {
12733 }
12734 }
12736 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12740 {
12745 }
12747 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12748 (eq (and (lshiftrt X) 1) 0).
12749 Also handle the case where (not X) is expressed using xor. */
12753 {
12763 == HOST_WIDE_INT_1U
12765 {
12766 op0
12771 }
12772 }
12776 /* If we have (compare (ashift FOO N) (const_int C)) and
12777 the high order N bits of FOO (N+1 if an inequality comparison)
12778 are known to be zero, we can do this by comparing FOO with C
12779 shifted right N bits so long as the low-order N bits of C are
12780 zero. */
12792 {
12793 /* We must perform a logical shift, not an arithmetic one,
12794 as we want the top N bits of C to be zero. */
12801 }
12803 /* If we are doing a sign bit comparison, it means we are testing
12804 a particular bit. Convert it to the appropriate AND. */
12807 {
12809 (HOST_WIDE_INT_1U
12814 }
12816 /* If this an equality comparison with zero and we are shifting
12817 the low bit to the sign bit, we can convert this to an AND of the
12818 low-order bit. */
12822 {
12825 }
12829 /* If this is an equality comparison with zero, we can do this
12830 as a logical shift, which might be much simpler. */
12833 {
12838 }
12840 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12841 do the comparison in a narrower mode. */
12851 {
12854 }
12856 /* Likewise if OP0 is a PLUS of a sign extension with a
12857 constant, which is usually represented with the PLUS
12858 between the shifts. */
12870 {
12878 new_const);
12880 }
12882 /* FALLTHROUGH */
12884 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12885 the low order N bits of FOO are known to be zero, we can do this
12886 by comparing FOO with C shifted left N bits so long as no
12887 overflow occurs. Even if the low order N bits of FOO aren't known
12888 to be zero, if the comparison is >= or < we can use the same
12889 optimization and for > or <= by setting all the low
12890 order N bits in the comparison constant. */
12901 {
12902 unsigned HOST_WIDE_INT low_bits
12904 & ((HOST_WIDE_INT_1U
12907 {
12908 /* If the shift was logical, then we must make the condition
12909 unsigned. */
12918 const_op
12923 }
12924 }
12926 /* If we are using this shift to extract just the sign bit, we
12927 can replace this with an LT or GE comparison. */
12932 {
12936 }
12941 }
12944 }
12946 /* Now make any compound operations involved in this comparison. Then,
12947 check for an outmost SUBREG on OP0 that is not doing anything or is
12948 paradoxical. The latter transformation must only be performed when
12949 it is known that the "extra" bits will be the same in op0 and op1 or
12950 that they don't matter. There are three cases to consider:
12952 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12953 care bits and we can assume they have any convenient value. So
12954 making the transformation is safe.
12956 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12957 In this case the upper bits of op0 are undefined. We should not make
12958 the simplification in that case as we do not know the contents of
12959 those bits.
12961 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12962 In that case we know those bits are zeros or ones. We must also be
12963 sure that they are the same as the upper bits of op1.
12965 We can never remove a SUBREG for a non-equality comparison because
12966 the sign bit is in a different place in the underlying object. */
12979 {
12981 {
12982 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12983 implemented. */
12985 {
12988 }
12989 }
12993 {
12998 }
12999 }
13001 /* We now do the opposite procedure: Some machines don't have compare
13002 insns in all modes. If OP0's mode is an integer mode smaller than a
13003 word and we can't do a compare in that mode, see if there is a larger
13004 mode for which we can do the compare. There are a number of cases in
13005 which we can use the wider mode. */
13011 {
13016 {
13019 /* If this is a test for negative, we can make an explicit
13020 test of the sign bit. Test this first so we can use
13021 a paradoxical subreg to extend OP0. */
13025 {
13026 unsigned HOST_WIDE_INT sign
13033 }
13035 /* If the only nonzero bits in OP0 and OP1 are those in the
13036 narrower mode and this is an equality or unsigned comparison,
13037 we can use the wider mode. Similarly for sign-extended
13038 values, in which case it is true for all comparisons. */
13055 {
13056 /* If OP0 is an AND and we don't have an AND in MODE either,
13057 make a new AND in the proper mode. */
13065 else
13066 {
13068 {
13073 }
13074 else
13075 {
13080 }
13082 }
13083 }
13084 }
13085 }
13087 /* We may have changed the comparison operands. Re-canonicalize. */
13089 {
13092 }
13094 /* If this machine only supports a subset of valid comparisons, see if we
13095 can convert an unsupported one into a supported one. */
13102 }
13103 \f
13104 /* Utility function for record_value_for_reg. Count number of
13105 rtxs in X. */
13106 static int
13108 {
13115 {
13135 }
13146 }
13147 \f
13148 /* Utility function for following routine. Called when X is part of a value
13149 being stored into last_set_value. Sets last_set_table_tick
13150 for each register mentioned. Similar to mention_regs in cse.c */
13152 static void
13154 {
13160 {
13166 {
13169 }
13172 }
13176 {
13177 /* Check for identical subexpressions. If x contains
13178 identical subexpression we only have to traverse one of
13179 them. */
13181 {
13182 /* Note that at this point x1 has already been
13183 processed. */
13187 /* If x0 and x1 are identical then there is no need to
13188 process x0. */
13192 /* If x0 is identical to a subexpression of x1 then while
13193 processing x1, x0 has already been processed. Thus we
13194 are done with x. */
13199 /* If x1 is identical to a subexpression of x0 then we
13200 still have to process the rest of x0. */
13203 {
13206 }
13207 }
13210 }
13214 }
13216 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13217 are saying that the register is clobbered and we no longer know its
13218 value. If INSN is zero, don't update reg_stat[].last_set; this is
13219 only permitted with VALUE also zero and is used to invalidate the
13220 register. */
13222 static void
13224 {
13230 /* If VALUE contains REG and we have a previous value for REG, substitute
13231 the previous value. */
13233 {
13234 rtx tem;
13236 /* Set things up so get_last_value is allowed to see anything set up to
13237 our insn. */
13241 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13242 it isn't going to be useful and will take a lot of time to process,
13243 so just use the CLOBBER. */
13246 {
13252 {
13253 /* If there are two or more occurrences of REG in VALUE,
13254 prevent the value from growing too much. */
13257 }
13260 }
13261 }
13263 /* For each register modified, show we don't know its value, that
13264 we don't know about its bitwise content, that its value has been
13265 updated, and that we don't know the location of the death of the
13266 register. */
13268 {
13280 }
13282 /* Mark registers that are being referenced in this value. */
13286 /* Now update the status of each register being set.
13287 If someone is using this register in this block, set this register
13288 to invalid since we will get confused between the two lives in this
13289 basic block. This makes using this register always invalid. In cse, we
13290 scan the table to invalidate all entries using this register, but this
13291 is too much work for us. */
13294 {
13300 else
13302 }
13304 /* The value being assigned might refer to X (like in "x++;"). In that
13305 case, we must replace it with (clobber (const_int 0)) to prevent
13306 infinite loops. */
13309 {
13313 }
13315 /* For the main register being modified, update the value, the mode, the
13316 nonzero bits, and the number of sign bit copies. */
13321 {
13329 rsp->last_set_sign_bit_copies
13331 }
13332 }
13334 /* Called via note_stores from record_dead_and_set_regs to handle one
13335 SET or CLOBBER in an insn. DATA is the instruction in which the
13336 set is occurring. */
13338 static void
13340 {
13347 {
13351 }
13354 {
13355 /* If we are setting the whole register, we know its value. Otherwise
13356 show that we don't know the value. We can handle a SUBREG if it's
13357 the low part, but we must be careful with paradoxical SUBREGs on
13358 RISC architectures because we cannot strip e.g. an extension around
13359 a load and record the naked load since the RTL middle-end considers
13360 that the upper bits are defined according to LOAD_EXTEND_OP. */
13367 BITS_PER_WORD)
13370 WORD_REGISTER_OPERATIONS
13377 {
13380 && reg_is_clobbered_by_clobber_high
13384 }
13385 else
13387 }
13389 /* Ignore pushes, they clobber nothing. */
13392 }
13394 /* Update the records of when each REG was most recently set or killed
13395 for the things done by INSN. This is the last thing done in processing
13396 INSN in the combiner loop.
13398 We update reg_stat[], in particular fields last_set, last_set_value,
13399 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13400 last_death, and also the similar information mem_last_set (which insn
13401 most recently modified memory) and last_call_luid (which insn was the
13402 most recent subroutine call). */
13404 static void
13406 {
13407 rtx link;
13411 {
13414 {
13419 {
13424 }
13425 }
13428 }
13431 {
13432 hard_reg_set_iterator hrsi;
13434 {
13446 }
13450 /* We can't combine into a call pattern. Remember, though, that
13451 the return value register is set at this LUID. We could
13452 still replace a register with the return value from the
13453 wrong subroutine call! */
13455 }
13456 else
13458 }
13460 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13461 register present in the SUBREG, so for each such SUBREG go back and
13462 adjust nonzero and sign bit information of the registers that are
13463 known to have some zero/sign bits set.
13465 This is needed because when combine blows the SUBREGs away, the
13466 information on zero/sign bits is lost and further combines can be
13467 missed because of that. */
13469 static void
13471 {
13473 rtx set;
13481 {
13490 {
13493 }
13497 {
13500 }
13503 {
13506 }
13507 else
13509 }
13510 }
13512 /* Check if X, a register, is known to contain a value already
13513 truncated to MODE. In this case we can use a subreg to refer to
13514 the truncated value even though in the generic case we would need
13515 an explicit truncation. */
13517 static bool
13519 {
13531 }
13533 /* If X is a hard reg or a subreg record the mode that the register is
13534 accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13535 able to turn a truncate into a subreg using this information. Return true
13536 if traversing X is complete. */
13538 static bool
13540 {
13541 machine_mode truncated_mode;
13545 {
13557 }
13558 /* ??? For hard-regs we now record everything. We might be able to
13559 optimize this using last_set_mode. */
13562 else
13569 {
13572 }
13575 }
13577 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13578 the modes they are used in. This can help truning TRUNCATEs into
13579 SUBREGs. */
13581 static void
13583 {
13588 }
13590 /* Scan X for promoted SUBREGs. For each one found,
13591 note what it implies to the registers used in it. */
13593 static void
13595 {
13600 else
13601 {
13607 {
13617 }
13618 }
13619 }
13620 \f
13621 /* Verify that all the registers and memory references mentioned in *LOC are
13622 still valid. *LOC was part of a value set in INSN when label_tick was
13623 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13624 the invalid references with (clobber (const_int 0)) and return 1. This
13625 replacement is useful because we often can get useful information about
13626 the form of a value (e.g., if it was produced by a shift that always
13627 produces -1 or 0) even though we don't know exactly what registers it
13628 was produced from. */
13630 static int
13632 {
13639 {
13645 {
13648 /* If this is a pseudo-register that was only set once and not
13649 live at the beginning of the function, it is always valid. */
13653 && (!REGNO_REG_SET_P
13655 regno)))
13657 {
13661 }
13662 }
13665 }
13666 /* If this is a memory reference, make sure that there were no stores after
13667 it that might have clobbered the value. We don't have alias info, so we
13668 assume any store invalidates it. Moreover, we only have local UIDs, so
13669 we also assume that there were stores in the intervening basic blocks. */
13672 {
13676 }
13679 {
13681 {
13682 /* Check for identical subexpressions. If x contains
13683 identical subexpression we only have to traverse one of
13684 them. */
13686 {
13687 /* Note that at this point x0 has already been checked
13688 and found valid. */
13692 /* If x0 and x1 are identical then x is also valid. */
13696 /* If x1 is identical to a subexpression of x0 then
13697 while checking x0, x1 has already been checked. Thus
13698 it is valid and so as x. */
13703 /* If x0 is identical to a subexpression of x1 then x is
13704 valid iff the rest of x1 is valid. */
13707 return
13711 }
13716 }
13722 }
13724 /* If we haven't found a reason for it to be invalid, it is valid. */
13726 }
13728 /* Get the last value assigned to X, if known. Some registers
13729 in the value may be replaced with (clobber (const_int 0)) if their value
13730 is known longer known reliably. */
13732 static rtx
13734 {
13736 rtx value;
13739 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13740 then convert it to the desired mode. If this is a paradoxical SUBREG,
13741 we cannot predict what values the "extra" bits might have. */
13755 /* If we don't have a value, or if it isn't for this basic block and
13756 it's either a hard register, set more than once, or it's a live
13757 at the beginning of the function, return 0.
13759 Because if it's not live at the beginning of the function then the reg
13760 is always set before being used (is never used without being set).
13761 And, if it's set only once, and it's always set before use, then all
13762 uses must have the same last value, even if it's not from this basic
13763 block. */
13770 || REGNO_REG_SET_P
13774 /* If the value was set in a later insn than the ones we are processing,
13775 we can't use it even if the register was only set once. */
13780 /* If fewer bits were set than what we are asked for now, we cannot use
13781 the value. */
13786 /* If the value has all its registers valid, return it. */
13790 /* Otherwise, make a copy and replace any invalid register with
13791 (clobber (const_int 0)). If that fails for some reason, return 0. */
13798 }
13799 \f
13800 /* Define three variables used for communication between the following
13801 routines. */
13805 rtx reg_dead_reg;
13807 /* Function called via note_stores from reg_dead_at_p.
13809 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13810 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13812 static void
13814 {
13828 }
13830 /* Return nonzero if REG is known to be dead at INSN.
13832 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13833 referencing REG, it is dead. If we hit a SET referencing REG, it is
13834 live. Otherwise, see if it is live or dead at the start of the basic
13835 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13836 must be assumed to be always live. */
13838 static int
13840 {
13841 basic_block block;
13844 /* Set variables for reg_dead_at_p_1. */
13851 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13852 we allow the machine description to decide whether use-and-clobber
13853 patterns are OK. */
13855 {
13859 }
13861 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13862 beginning of basic block. */
13865 {
13867 {
13877 }
13883 }
13885 /* Look at live-in sets for the basic block that we were in. */
13891 }
13892 \f
13893 /* Note hard registers in X that are used. */
13895 static void
13897 {
13903 {
13907 CASE_CONST_ANY:
13912 /* CC0 must die in the insn after it is set, so we don't need to take
13913 special note of it here. */
13918 /* If we are clobbering a MEM, mark any hard registers inside the
13919 address as used. */
13926 /* A hard reg in a wide mode may really be multiple registers.
13927 If so, mark all of them just like the first. */
13929 {
13930 /* None of this applies to the stack, frame or arg pointers. */
13932 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13940 }
13944 {
13945 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13946 the address. */
13958 }
13963 }
13965 /* Recursively scan the operands of this expression. */
13967 {
13971 {
13975 {
13980 }
13981 }
13982 }
13983 }
13984 \f
13985 /* Remove register number REGNO from the dead registers list of INSN.
13987 Return the note used to record the death, if there was one. */
13989 rtx
13991 {
13998 }
14000 /* For each register (hardware or pseudo) used within expression X, if its
14001 death is in an instruction with luid between FROM_LUID (inclusive) and
14002 TO_INSN (exclusive), put a REG_DEAD note for that register in the
14003 list headed by PNOTES.
14005 That said, don't move registers killed by maybe_kill_insn.
14007 This is done when X is being merged by combination into TO_INSN. These
14008 notes will then be distributed as needed. */
14010 static void
14013 {
14019 {
14023 /* If we do not know where the register died, it may still die between
14024 FROM_LUID and TO_INSN. If so, find it. This is PR83304. */
14026 {
14031 {
14033 {
14037 }
14040 }
14041 }
14043 /* Don't move the register if it gets killed in between from and to. */
14052 {
14055 /* It is possible for the call above to return 0. This can occur
14056 when last_death points to I2 or I1 that we combined with.
14057 In that case make a new note.
14059 We must also check for the case where X is a hard register
14060 and NOTE is a death note for a range of hard registers
14061 including X. In that case, we must put REG_DEAD notes for
14062 the remaining registers in place of NOTE. */
14066 {
14075 }
14077 /* If we didn't find any note, or if we found a REG_DEAD note that
14078 covers only part of the given reg, and we have a multi-reg hard
14079 register, then to be safe we must check for REG_DEAD notes
14080 for each register other than the first. They could have
14081 their own REG_DEAD notes lying around. */
14088 {
14095 else
14101 }
14104 {
14107 }
14108 else
14110 }
14113 }
14116 {
14121 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
14122 that accesses one word of a multi-word item, some
14123 piece of everything register in the expression is used by
14124 this insn, so remove any old death. */
14125 /* ??? So why do we test for equality of the sizes? */
14131 {
14134 }
14136 /* If this is some other SUBREG, we know it replaces the entire
14137 value, so use that as the destination. */
14141 /* If this is a MEM, adjust deaths of anything used in the address.
14142 For a REG (the only other possibility), the entire value is
14143 being replaced so the old value is not used in this insn. */
14149 }
14158 {
14160 {
14165 }
14168 }
14169 }
14170 \f
14171 /* Return 1 if X is the target of a bit-field assignment in BODY, the
14172 pattern of an insn. X must be a REG. */
14174 static int
14176 {
14180 {
14182 rtx target;
14189 else
14206 }
14214 }
14215 \f
14216 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14217 as appropriate. I3 and I2 are the insns resulting from the combination
14218 insns including FROM (I2 may be zero).
14220 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14221 not need REG_DEAD notes because they are being substituted for. This
14222 saves searching in the most common cases.
14224 Each note in the list is either ignored or placed on some insns, depending
14225 on the type of note. */
14227 static void
14230 {
14232 rtx tem_note;
14236 {
14241 {
14244 /* Doesn't matter much where we put this, as long as it's somewhere.
14245 It is preferable to keep these notes on branches, which is most
14246 likely to be i3. */
14253 else
14254 {
14257 }
14261 /* These notes must remain with the call or trapping instruction. */
14266 else
14267 {
14273 /* ??? Otherwise assume we've combined things such that we
14274 can now prove that the instructions can't trap. Drop the
14275 note in this case. */
14276 }
14280 /* ??? How to distribute between i3-i1. Assume i3 contains the
14281 entire adjustment. Assert i3 contains at least some adjust. */
14283 {
14285 /* fixup_args_size_notes looks at REG_NORETURN note,
14286 so ensure the note is placed there first. */
14288 {
14292 {
14298 }
14299 }
14301 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14302 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14305 && !ACCUMULATE_OUTGOING_ARGS
14307 }
14315 /* These notes must remain with the call. It should not be
14316 possible for both I2 and I3 to be a call. */
14319 else
14320 {
14323 }
14327 /* Any clobbers for i3 may still exist, and so we must process
14328 REG_UNUSED notes from that insn.
14330 Any clobbers from i2 or i1 can only exist if they were added by
14331 recog_for_combine. In that case, recog_for_combine created the
14332 necessary REG_UNUSED notes. Trying to keep any original
14333 REG_UNUSED notes from these insns can cause incorrect output
14334 if it is for the same register as the original i3 dest.
14335 In that case, we will notice that the register is set in i3,
14336 and then add a REG_UNUSED note for the destination of i3, which
14337 is wrong. However, it is possible to have REG_UNUSED notes from
14338 i2 or i1 for register which were both used and clobbered, so
14339 we keep notes from i2 or i1 if they will turn into REG_DEAD
14340 notes. */
14342 /* If this register is set or clobbered in I3, put the note there
14343 unless there is one already. */
14345 {
14353 }
14354 /* Otherwise, if this register is used by I3, then this register
14355 now dies here, so we must put a REG_DEAD note here unless there
14356 is one already. */
14362 {
14365 }
14367 /* A SET or CLOBBER of the REG_UNUSED reg has been removed,
14368 but we can't tell which at this point. We must reset any
14369 expectations we had about the value that was previously
14370 stored in the reg. ??? Ideally, we'd adjust REG_N_SETS
14371 and, if appropriate, restore its previous value, but we
14372 don't have enough information for that at this point. */
14373 else
14374 {
14377 /* Otherwise, if this register is now referenced in i2
14378 then the register used to be modified in one of the
14379 original insns. If it was i3 (say, in an unused
14380 parallel), it's now completely gone, so the note can
14381 be discarded. But if it was modified in i2, i1 or i0
14382 and we still reference it in i2, then we're
14383 referencing the previous value, and since the
14384 register was modified and REG_UNUSED, we know that
14385 the previous value is now dead. So, if we only
14386 reference the register in i2, we change the note to
14387 REG_DEAD, to reflect the previous value. However, if
14388 we're also setting or clobbering the register as
14389 scratch, we know (because the register was not
14390 referenced in i3) that it's unused, just as it was
14391 unused before, and we place the note in i2. */
14394 {
14403 }
14404 }
14411 /* These notes say something about results of an insn. We can
14412 only support them if they used to be on I3 in which case they
14413 remain on I3. Otherwise they are ignored.
14415 If the note refers to an expression that is not a constant, we
14416 must also ignore the note since we cannot tell whether the
14417 equivalence is still true. It might be possible to do
14418 slightly better than this (we only have a problem if I2DEST
14419 or I1DEST is present in the expression), but it doesn't
14420 seem worth the trouble. */
14428 /* These notes say something about how a register is used. They must
14429 be present on any use of the register in I2 or I3. */
14434 {
14437 else
14439 }
14444 /* This can show up in several ways -- either directly in the
14445 pattern, or hidden off in the constant pool with (or without?)
14446 a REG_EQUAL note. */
14447 /* ??? Ignore the without-reg_equal-note problem for now. */
14459 {
14462 else
14464 }
14466 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14467 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14468 there. */
14473 {
14480 }
14486 {
14494 }
14498 /* This note says something about the value of a register prior
14499 to the execution of an insn. It is too much trouble to see
14500 if the note is still correct in all situations. It is better
14501 to simply delete it. */
14505 /* If we replaced the right hand side of FROM_INSN with a
14506 REG_EQUAL note, the original use of the dying register
14507 will not have been combined into I3 and I2. In such cases,
14508 FROM_INSN is guaranteed to be the first of the combined
14509 instructions, so we simply need to search back before
14510 FROM_INSN for the previous use or set of this register,
14511 then alter the notes there appropriately.
14513 If the register is used as an input in I3, it dies there.
14514 Similarly for I2, if it is nonzero and adjacent to I3.
14516 If the register is not used as an input in either I3 or I2
14517 and it is not one of the registers we were supposed to eliminate,
14518 there are two possibilities. We might have a non-adjacent I2
14519 or we might have somehow eliminated an additional register
14520 from a computation. For example, we might have had A & B where
14521 we discover that B will always be zero. In this case we will
14522 eliminate the reference to A.
14524 In both cases, we must search to see if we can find a previous
14525 use of A and put the death note there. */
14531 else
14532 {
14538 {
14539 /* If the new I2 sets the same register that is marked
14540 dead in the note, we do not in general know where to
14541 put the note. One important case we _can_ handle is
14542 when the note comes from I3. */
14545 else
14547 }
14554 && !(i2mod
14556 i2mod_old_rhs)))
14561 }
14564 {
14568 {
14570 {
14574 }
14576 /* If the register is being set at TEM_INSN, see if that is all
14577 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14578 into a REG_UNUSED note instead. Don't delete sets to
14579 global register vars. */
14583 {
14594 ;
14596 /* Verify that it was the set, and not a clobber that
14597 modified the register.
14599 CC0 targets must be careful to maintain setter/user
14600 pairs. If we cannot delete the setter due to side
14601 effects, mark the user with an UNUSED note instead
14602 of deleting it. */
14606 && (!HAVE_cc0
14610 {
14611 /* Move the notes and links of TEM_INSN elsewhere.
14612 This might delete other dead insns recursively.
14613 First set the pattern to something that won't use
14614 any register. */
14633 /* Delete the setter too. */
14635 {
14648 }
14649 }
14650 else
14651 {
14654 /* If there isn't already a REG_UNUSED note, put one
14655 here. Do not place a REG_DEAD note, even if
14656 the register is also used here; that would not
14657 match the algorithm used in lifetime analysis
14658 and can cause the consistency check in the
14659 scheduler to fail. */
14664 }
14665 }
14669 {
14672 /* If we are doing a 3->2 combination, and we have a
14673 register which formerly died in i3 and was not used
14674 by i2, which now no longer dies in i3 and is used in
14675 i2 but does not die in i2, and place is between i2
14676 and i3, then we may need to move a link from place to
14677 i2. */
14679 && from_insn
14682 {
14686 }
14688 }
14692 }
14694 }
14696 /* If the register is set or already dead at PLACE, we needn't do
14697 anything with this note if it is still a REG_DEAD note.
14698 We check here if it is set at all, not if is it totally replaced,
14699 which is what `dead_or_set_p' checks, so also check for it being
14700 set partially. */
14703 {
14709 {
14710 /* Unless the register previously died in PLACE, clear
14711 last_death. [I no longer understand why this is
14712 being done.] */
14716 }
14717 else
14720 /* If this is a death note for a hard reg that is occupying
14721 multiple registers, ensure that we are still using all
14722 parts of the object. If we find a piece of the object
14723 that is unused, we must arrange for an appropriate REG_DEAD
14724 note to be added for it. However, we can't just emit a USE
14725 and tag the note to it, since the register might actually
14726 be dead; so we recourse, and the recursive call then finds
14727 the previous insn that used this register. */
14730 {
14739 {
14742 }
14745 {
14746 /* Put only REG_DEAD notes for pieces that are
14747 not already dead or set. */
14751 {
14758 {
14760 NULL_RTX);
14764 NULL_RTX);
14765 }
14770 {
14772 {
14776 }
14780 {
14783 }
14784 }
14785 }
14788 }
14789 }
14790 }
14794 /* Any other notes should not be present at this point in the
14795 compilation. */
14797 }
14800 {
14804 /* Set added_notes_insn to the earliest insn we added a note to. */
14808 }
14811 {
14814 /* Set added_notes_insn to the earliest insn we added a note to. */
14818 }
14819 }
14820 }
14821 \f
14822 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14823 I3, I2, and I1 to new locations. This is also called to add a link
14824 pointing at I3 when I3's destination is changed. */
14826 static void
14828 {
14832 {
14839 /* If the insn that this link points to is a NOTE, ignore it. */
14848 {
14851 {
14867 }
14870 }
14871 else
14884 /* A LOG_LINK is defined as being placed on the first insn that uses
14885 a register and points to the insn that sets the register. Start
14886 searching at the next insn after the target of the link and stop
14887 when we reach a set of the register or the end of the basic block.
14889 Note that this correctly handles the link that used to point from
14890 I3 to I2. Also note that not much searching is typically done here
14891 since most links don't point very far away. */
14900 {
14904 }
14907 {
14910 }
14914 /* If we found a place to put the link, place it there unless there
14915 is already a link to the same insn as LINK at that point. */
14918 {
14926 {
14930 /* Set added_links_insn to the earliest insn we added a
14931 link to. */
14935 }
14936 }
14937 }
14938 }
14939 \f
14940 /* Check for any register or memory mentioned in EQUIV that is not
14941 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14942 of EXPR where some registers may have been replaced by constants. */
14944 static bool
14946 {
14949 {
14954 }
14956 }
14957 \f
14958 DEBUG_FUNCTION void
14960 {
14961 fprintf
14963 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14965 }
14967 void
14969 {
14970 fprintf
14972 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14974 }
14975 \f
14976 /* Make pseudo-to-pseudo copies after every hard-reg-to-pseudo-copy, because
14977 the reg-to-reg copy can usefully combine with later instructions, but we
14978 do not want to combine the hard reg into later instructions, for that
14979 restricts register allocation. */
14980 static void
14982 {
14983 basic_block bb;
14986 {
14990 {
15013 }
15014 }
15015 }
15017 /* Try combining insns through substitution. */
15018 static unsigned int
15020 {
15030 int rebuild_jump_labels_after_combine
15033 /* Combining insns may have turned an indirect jump into a
15034 direct jump. Rebuild the JUMP_LABEL fields of jumping
15035 instructions. */
15037 {
15044 }
15048 }
15053 {
15063 };
15066 {
15070 {}
15072 /* opt_pass methods: */
15075 {
15077 }
15083 rtl_opt_pass *
15085 {
15087 }