1 @c Copyright (C) 1988-2014 Free Software Foundation, Inc.
2 @c This is part of the GCC manual.
3 @c For copying conditions, see the file gcc.texi.
7 @chapter Machine Descriptions
8 @cindex machine descriptions
10 A machine description has two parts: a file of instruction patterns
11 (@file{.md} file) and a C header file of macro definitions.
13 The @file{.md} file for a target machine contains a pattern for each
14 instruction that the target machine supports (or at least each instruction
15 that is worth telling the compiler about). It may also contain comments.
16 A semicolon causes the rest of the line to be a comment, unless the semicolon
17 is inside a quoted string.
19 See the next chapter for information on the C header file.
22 * Overview:: How the machine description is used.
23 * Patterns:: How to write instruction patterns.
24 * Example:: An explained example of a @code{define_insn} pattern.
25 * RTL Template:: The RTL template defines what insns match a pattern.
26 * Output Template:: The output template says how to make assembler code
28 * Output Statement:: For more generality, write C code to output
30 * Predicates:: Controlling what kinds of operands can be used
32 * Constraints:: Fine-tuning operand selection.
33 * Standard Names:: Names mark patterns to use for code generation.
34 * Pattern Ordering:: When the order of patterns makes a difference.
35 * Dependent Patterns:: Having one pattern may make you need another.
36 * Jump Patterns:: Special considerations for patterns for jump insns.
37 * Looping Patterns:: How to define patterns for special looping insns.
38 * Insn Canonicalizations::Canonicalization of Instructions
39 * Expander Definitions::Generating a sequence of several RTL insns
40 for a standard operation.
41 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
42 * Including Patterns:: Including Patterns in Machine Descriptions.
43 * Peephole Definitions::Defining machine-specific peephole optimizations.
44 * Insn Attributes:: Specifying the value of attributes for generated insns.
45 * Conditional Execution::Generating @code{define_insn} patterns for
47 * Define Subst:: Generating @code{define_insn} and @code{define_expand}
48 patterns from other patterns.
49 * Constant Definitions::Defining symbolic constants that can be used in the
51 * Iterators:: Using iterators to generate patterns from a template.
55 @section Overview of How the Machine Description is Used
57 There are three main conversions that happen in the compiler:
62 The front end reads the source code and builds a parse tree.
65 The parse tree is used to generate an RTL insn list based on named
69 The insn list is matched against the RTL templates to produce assembler
74 For the generate pass, only the names of the insns matter, from either a
75 named @code{define_insn} or a @code{define_expand}. The compiler will
76 choose the pattern with the right name and apply the operands according
77 to the documentation later in this chapter, without regard for the RTL
78 template or operand constraints. Note that the names the compiler looks
79 for are hard-coded in the compiler---it will ignore unnamed patterns and
80 patterns with names it doesn't know about, but if you don't provide a
81 named pattern it needs, it will abort.
83 If a @code{define_insn} is used, the template given is inserted into the
84 insn list. If a @code{define_expand} is used, one of three things
85 happens, based on the condition logic. The condition logic may manually
86 create new insns for the insn list, say via @code{emit_insn()}, and
87 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
88 compiler to use an alternate way of performing that task. If it invokes
89 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
90 is inserted, as if the @code{define_expand} were a @code{define_insn}.
92 Once the insn list is generated, various optimization passes convert,
93 replace, and rearrange the insns in the insn list. This is where the
94 @code{define_split} and @code{define_peephole} patterns get used, for
97 Finally, the insn list's RTL is matched up with the RTL templates in the
98 @code{define_insn} patterns, and those patterns are used to emit the
99 final assembly code. For this purpose, each named @code{define_insn}
100 acts like it's unnamed, since the names are ignored.
103 @section Everything about Instruction Patterns
105 @cindex instruction patterns
108 Each instruction pattern contains an incomplete RTL expression, with pieces
109 to be filled in later, operand constraints that restrict how the pieces can
110 be filled in, and an output pattern or C code to generate the assembler
111 output, all wrapped up in a @code{define_insn} expression.
113 A @code{define_insn} is an RTL expression containing four or five operands:
117 An optional name. The presence of a name indicate that this instruction
118 pattern can perform a certain standard job for the RTL-generation
119 pass of the compiler. This pass knows certain names and will use
120 the instruction patterns with those names, if the names are defined
121 in the machine description.
123 The absence of a name is indicated by writing an empty string
124 where the name should go. Nameless instruction patterns are never
125 used for generating RTL code, but they may permit several simpler insns
126 to be combined later on.
128 Names that are not thus known and used in RTL-generation have no
129 effect; they are equivalent to no name at all.
131 For the purpose of debugging the compiler, you may also specify a
132 name beginning with the @samp{*} character. Such a name is used only
133 for identifying the instruction in RTL dumps; it is entirely equivalent
134 to having a nameless pattern for all other purposes.
137 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
138 RTL expressions which show what the instruction should look like. It is
139 incomplete because it may contain @code{match_operand},
140 @code{match_operator}, and @code{match_dup} expressions that stand for
141 operands of the instruction.
143 If the vector has only one element, that element is the template for the
144 instruction pattern. If the vector has multiple elements, then the
145 instruction pattern is a @code{parallel} expression containing the
149 @cindex pattern conditions
150 @cindex conditions, in patterns
151 A condition. This is a string which contains a C expression that is
152 the final test to decide whether an insn body matches this pattern.
154 @cindex named patterns and conditions
155 For a named pattern, the condition (if present) may not depend on
156 the data in the insn being matched, but only the target-machine-type
157 flags. The compiler needs to test these conditions during
158 initialization in order to learn exactly which named instructions are
159 available in a particular run.
162 For nameless patterns, the condition is applied only when matching an
163 individual insn, and only after the insn has matched the pattern's
164 recognition template. The insn's operands may be found in the vector
165 @code{operands}. For an insn where the condition has once matched, it
166 can't be used to control register allocation, for example by excluding
167 certain hard registers or hard register combinations.
170 The @dfn{output template}: a string that says how to output matching
171 insns as assembler code. @samp{%} in this string specifies where
172 to substitute the value of an operand. @xref{Output Template}.
174 When simple substitution isn't general enough, you can specify a piece
175 of C code to compute the output. @xref{Output Statement}.
178 Optionally, a vector containing the values of attributes for insns matching
179 this pattern. @xref{Insn Attributes}.
183 @section Example of @code{define_insn}
184 @cindex @code{define_insn} example
186 Here is an actual example of an instruction pattern, for the 68000/68020.
191 (match_operand:SI 0 "general_operand" "rm"))]
195 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
197 return \"cmpl #0,%0\";
202 This can also be written using braced strings:
207 (match_operand:SI 0 "general_operand" "rm"))]
210 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
216 This is an instruction that sets the condition codes based on the value of
217 a general operand. It has no condition, so any insn whose RTL description
218 has the form shown may be handled according to this pattern. The name
219 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
220 pass that, when it is necessary to test such a value, an insn to do so
221 can be constructed using this pattern.
223 The output control string is a piece of C code which chooses which
224 output template to return based on the kind of operand and the specific
225 type of CPU for which code is being generated.
227 @samp{"rm"} is an operand constraint. Its meaning is explained below.
230 @section RTL Template
231 @cindex RTL insn template
232 @cindex generating insns
233 @cindex insns, generating
234 @cindex recognizing insns
235 @cindex insns, recognizing
237 The RTL template is used to define which insns match the particular pattern
238 and how to find their operands. For named patterns, the RTL template also
239 says how to construct an insn from specified operands.
241 Construction involves substituting specified operands into a copy of the
242 template. Matching involves determining the values that serve as the
243 operands in the insn being matched. Both of these activities are
244 controlled by special expression types that direct matching and
245 substitution of the operands.
248 @findex match_operand
249 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
250 This expression is a placeholder for operand number @var{n} of
251 the insn. When constructing an insn, operand number @var{n}
252 will be substituted at this point. When matching an insn, whatever
253 appears at this position in the insn will be taken as operand
254 number @var{n}; but it must satisfy @var{predicate} or this instruction
255 pattern will not match at all.
257 Operand numbers must be chosen consecutively counting from zero in
258 each instruction pattern. There may be only one @code{match_operand}
259 expression in the pattern for each operand number. Usually operands
260 are numbered in the order of appearance in @code{match_operand}
261 expressions. In the case of a @code{define_expand}, any operand numbers
262 used only in @code{match_dup} expressions have higher values than all
263 other operand numbers.
265 @var{predicate} is a string that is the name of a function that
266 accepts two arguments, an expression and a machine mode.
267 @xref{Predicates}. During matching, the function will be called with
268 the putative operand as the expression and @var{m} as the mode
269 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
270 which normally causes @var{predicate} to accept any mode). If it
271 returns zero, this instruction pattern fails to match.
272 @var{predicate} may be an empty string; then it means no test is to be
273 done on the operand, so anything which occurs in this position is
276 Most of the time, @var{predicate} will reject modes other than @var{m}---but
277 not always. For example, the predicate @code{address_operand} uses
278 @var{m} as the mode of memory ref that the address should be valid for.
279 Many predicates accept @code{const_int} nodes even though their mode is
282 @var{constraint} controls reloading and the choice of the best register
283 class to use for a value, as explained later (@pxref{Constraints}).
284 If the constraint would be an empty string, it can be omitted.
286 People are often unclear on the difference between the constraint and the
287 predicate. The predicate helps decide whether a given insn matches the
288 pattern. The constraint plays no role in this decision; instead, it
289 controls various decisions in the case of an insn which does match.
291 @findex match_scratch
292 @item (match_scratch:@var{m} @var{n} @var{constraint})
293 This expression is also a placeholder for operand number @var{n}
294 and indicates that operand must be a @code{scratch} or @code{reg}
297 When matching patterns, this is equivalent to
300 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
303 but, when generating RTL, it produces a (@code{scratch}:@var{m})
306 If the last few expressions in a @code{parallel} are @code{clobber}
307 expressions whose operands are either a hard register or
308 @code{match_scratch}, the combiner can add or delete them when
309 necessary. @xref{Side Effects}.
312 @item (match_dup @var{n})
313 This expression is also a placeholder for operand number @var{n}.
314 It is used when the operand needs to appear more than once in the
317 In construction, @code{match_dup} acts just like @code{match_operand}:
318 the operand is substituted into the insn being constructed. But in
319 matching, @code{match_dup} behaves differently. It assumes that operand
320 number @var{n} has already been determined by a @code{match_operand}
321 appearing earlier in the recognition template, and it matches only an
322 identical-looking expression.
324 Note that @code{match_dup} should not be used to tell the compiler that
325 a particular register is being used for two operands (example:
326 @code{add} that adds one register to another; the second register is
327 both an input operand and the output operand). Use a matching
328 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
329 operand is used in two places in the template, such as an instruction
330 that computes both a quotient and a remainder, where the opcode takes
331 two input operands but the RTL template has to refer to each of those
332 twice; once for the quotient pattern and once for the remainder pattern.
334 @findex match_operator
335 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
336 This pattern is a kind of placeholder for a variable RTL expression
339 When constructing an insn, it stands for an RTL expression whose
340 expression code is taken from that of operand @var{n}, and whose
341 operands are constructed from the patterns @var{operands}.
343 When matching an expression, it matches an expression if the function
344 @var{predicate} returns nonzero on that expression @emph{and} the
345 patterns @var{operands} match the operands of the expression.
347 Suppose that the function @code{commutative_operator} is defined as
348 follows, to match any expression whose operator is one of the
349 commutative arithmetic operators of RTL and whose mode is @var{mode}:
353 commutative_integer_operator (x, mode)
355 enum machine_mode mode;
357 enum rtx_code code = GET_CODE (x);
358 if (GET_MODE (x) != mode)
360 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
361 || code == EQ || code == NE);
365 Then the following pattern will match any RTL expression consisting
366 of a commutative operator applied to two general operands:
369 (match_operator:SI 3 "commutative_operator"
370 [(match_operand:SI 1 "general_operand" "g")
371 (match_operand:SI 2 "general_operand" "g")])
374 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
375 because the expressions to be matched all contain two operands.
377 When this pattern does match, the two operands of the commutative
378 operator are recorded as operands 1 and 2 of the insn. (This is done
379 by the two instances of @code{match_operand}.) Operand 3 of the insn
380 will be the entire commutative expression: use @code{GET_CODE
381 (operands[3])} to see which commutative operator was used.
383 The machine mode @var{m} of @code{match_operator} works like that of
384 @code{match_operand}: it is passed as the second argument to the
385 predicate function, and that function is solely responsible for
386 deciding whether the expression to be matched ``has'' that mode.
388 When constructing an insn, argument 3 of the gen-function will specify
389 the operation (i.e.@: the expression code) for the expression to be
390 made. It should be an RTL expression, whose expression code is copied
391 into a new expression whose operands are arguments 1 and 2 of the
392 gen-function. The subexpressions of argument 3 are not used;
393 only its expression code matters.
395 When @code{match_operator} is used in a pattern for matching an insn,
396 it usually best if the operand number of the @code{match_operator}
397 is higher than that of the actual operands of the insn. This improves
398 register allocation because the register allocator often looks at
399 operands 1 and 2 of insns to see if it can do register tying.
401 There is no way to specify constraints in @code{match_operator}. The
402 operand of the insn which corresponds to the @code{match_operator}
403 never has any constraints because it is never reloaded as a whole.
404 However, if parts of its @var{operands} are matched by
405 @code{match_operand} patterns, those parts may have constraints of
409 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
410 Like @code{match_dup}, except that it applies to operators instead of
411 operands. When constructing an insn, operand number @var{n} will be
412 substituted at this point. But in matching, @code{match_op_dup} behaves
413 differently. It assumes that operand number @var{n} has already been
414 determined by a @code{match_operator} appearing earlier in the
415 recognition template, and it matches only an identical-looking
418 @findex match_parallel
419 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
420 This pattern is a placeholder for an insn that consists of a
421 @code{parallel} expression with a variable number of elements. This
422 expression should only appear at the top level of an insn pattern.
424 When constructing an insn, operand number @var{n} will be substituted at
425 this point. When matching an insn, it matches if the body of the insn
426 is a @code{parallel} expression with at least as many elements as the
427 vector of @var{subpat} expressions in the @code{match_parallel}, if each
428 @var{subpat} matches the corresponding element of the @code{parallel},
429 @emph{and} the function @var{predicate} returns nonzero on the
430 @code{parallel} that is the body of the insn. It is the responsibility
431 of the predicate to validate elements of the @code{parallel} beyond
432 those listed in the @code{match_parallel}.
434 A typical use of @code{match_parallel} is to match load and store
435 multiple expressions, which can contain a variable number of elements
436 in a @code{parallel}. For example,
440 [(match_parallel 0 "load_multiple_operation"
441 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
442 (match_operand:SI 2 "memory_operand" "m"))
444 (clobber (reg:SI 179))])]
449 This example comes from @file{a29k.md}. The function
450 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
451 that subsequent elements in the @code{parallel} are the same as the
452 @code{set} in the pattern, except that they are referencing subsequent
453 registers and memory locations.
455 An insn that matches this pattern might look like:
459 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
461 (clobber (reg:SI 179))
463 (mem:SI (plus:SI (reg:SI 100)
466 (mem:SI (plus:SI (reg:SI 100)
470 @findex match_par_dup
471 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
472 Like @code{match_op_dup}, but for @code{match_parallel} instead of
473 @code{match_operator}.
477 @node Output Template
478 @section Output Templates and Operand Substitution
479 @cindex output templates
480 @cindex operand substitution
482 @cindex @samp{%} in template
484 The @dfn{output template} is a string which specifies how to output the
485 assembler code for an instruction pattern. Most of the template is a
486 fixed string which is output literally. The character @samp{%} is used
487 to specify where to substitute an operand; it can also be used to
488 identify places where different variants of the assembler require
491 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
492 operand @var{n} at that point in the string.
494 @samp{%} followed by a letter and a digit says to output an operand in an
495 alternate fashion. Four letters have standard, built-in meanings described
496 below. The machine description macro @code{PRINT_OPERAND} can define
497 additional letters with nonstandard meanings.
499 @samp{%c@var{digit}} can be used to substitute an operand that is a
500 constant value without the syntax that normally indicates an immediate
503 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
504 the constant is negated before printing.
506 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
507 memory reference, with the actual operand treated as the address. This may
508 be useful when outputting a ``load address'' instruction, because often the
509 assembler syntax for such an instruction requires you to write the operand
510 as if it were a memory reference.
512 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
515 @samp{%=} outputs a number which is unique to each instruction in the
516 entire compilation. This is useful for making local labels to be
517 referred to more than once in a single template that generates multiple
518 assembler instructions.
520 @samp{%} followed by a punctuation character specifies a substitution that
521 does not use an operand. Only one case is standard: @samp{%%} outputs a
522 @samp{%} into the assembler code. Other nonstandard cases can be
523 defined in the @code{PRINT_OPERAND} macro. You must also define
524 which punctuation characters are valid with the
525 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
529 The template may generate multiple assembler instructions. Write the text
530 for the instructions, with @samp{\;} between them.
532 @cindex matching operands
533 When the RTL contains two operands which are required by constraint to match
534 each other, the output template must refer only to the lower-numbered operand.
535 Matching operands are not always identical, and the rest of the compiler
536 arranges to put the proper RTL expression for printing into the lower-numbered
539 One use of nonstandard letters or punctuation following @samp{%} is to
540 distinguish between different assembler languages for the same machine; for
541 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
542 requires periods in most opcode names, while MIT syntax does not. For
543 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
544 syntax. The same file of patterns is used for both kinds of output syntax,
545 but the character sequence @samp{%.} is used in each place where Motorola
546 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
547 defines the sequence to output a period; the macro for MIT syntax defines
550 @cindex @code{#} in template
551 As a special case, a template consisting of the single character @code{#}
552 instructs the compiler to first split the insn, and then output the
553 resulting instructions separately. This helps eliminate redundancy in the
554 output templates. If you have a @code{define_insn} that needs to emit
555 multiple assembler instructions, and there is a matching @code{define_split}
556 already defined, then you can simply use @code{#} as the output template
557 instead of writing an output template that emits the multiple assembler
560 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
561 of the form @samp{@{option0|option1|option2@}} in the templates. These
562 describe multiple variants of assembler language syntax.
563 @xref{Instruction Output}.
565 @node Output Statement
566 @section C Statements for Assembler Output
567 @cindex output statements
568 @cindex C statements for assembler output
569 @cindex generating assembler output
571 Often a single fixed template string cannot produce correct and efficient
572 assembler code for all the cases that are recognized by a single
573 instruction pattern. For example, the opcodes may depend on the kinds of
574 operands; or some unfortunate combinations of operands may require extra
575 machine instructions.
577 If the output control string starts with a @samp{@@}, then it is actually
578 a series of templates, each on a separate line. (Blank lines and
579 leading spaces and tabs are ignored.) The templates correspond to the
580 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
581 if a target machine has a two-address add instruction @samp{addr} to add
582 into a register and another @samp{addm} to add a register to memory, you
583 might write this pattern:
586 (define_insn "addsi3"
587 [(set (match_operand:SI 0 "general_operand" "=r,m")
588 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
589 (match_operand:SI 2 "general_operand" "g,r")))]
596 @cindex @code{*} in template
597 @cindex asterisk in template
598 If the output control string starts with a @samp{*}, then it is not an
599 output template but rather a piece of C program that should compute a
600 template. It should execute a @code{return} statement to return the
601 template-string you want. Most such templates use C string literals, which
602 require doublequote characters to delimit them. To include these
603 doublequote characters in the string, prefix each one with @samp{\}.
605 If the output control string is written as a brace block instead of a
606 double-quoted string, it is automatically assumed to be C code. In that
607 case, it is not necessary to put in a leading asterisk, or to escape the
608 doublequotes surrounding C string literals.
610 The operands may be found in the array @code{operands}, whose C data type
613 It is very common to select different ways of generating assembler code
614 based on whether an immediate operand is within a certain range. Be
615 careful when doing this, because the result of @code{INTVAL} is an
616 integer on the host machine. If the host machine has more bits in an
617 @code{int} than the target machine has in the mode in which the constant
618 will be used, then some of the bits you get from @code{INTVAL} will be
619 superfluous. For proper results, you must carefully disregard the
620 values of those bits.
622 @findex output_asm_insn
623 It is possible to output an assembler instruction and then go on to output
624 or compute more of them, using the subroutine @code{output_asm_insn}. This
625 receives two arguments: a template-string and a vector of operands. The
626 vector may be @code{operands}, or it may be another array of @code{rtx}
627 that you declare locally and initialize yourself.
629 @findex which_alternative
630 When an insn pattern has multiple alternatives in its constraints, often
631 the appearance of the assembler code is determined mostly by which alternative
632 was matched. When this is so, the C code can test the variable
633 @code{which_alternative}, which is the ordinal number of the alternative
634 that was actually satisfied (0 for the first, 1 for the second alternative,
637 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
638 for registers and @samp{clrmem} for memory locations. Here is how
639 a pattern could use @code{which_alternative} to choose between them:
643 [(set (match_operand:SI 0 "general_operand" "=r,m")
647 return (which_alternative == 0
648 ? "clrreg %0" : "clrmem %0");
652 The example above, where the assembler code to generate was
653 @emph{solely} determined by the alternative, could also have been specified
654 as follows, having the output control string start with a @samp{@@}:
659 [(set (match_operand:SI 0 "general_operand" "=r,m")
668 If you just need a little bit of C code in one (or a few) alternatives,
669 you can use @samp{*} inside of a @samp{@@} multi-alternative template:
674 [(set (match_operand:SI 0 "general_operand" "=r,<,m")
679 * return stack_mem_p (operands[0]) ? \"push 0\" : \"clrmem %0\";
687 @cindex operand predicates
688 @cindex operator predicates
690 A predicate determines whether a @code{match_operand} or
691 @code{match_operator} expression matches, and therefore whether the
692 surrounding instruction pattern will be used for that combination of
693 operands. GCC has a number of machine-independent predicates, and you
694 can define machine-specific predicates as needed. By convention,
695 predicates used with @code{match_operand} have names that end in
696 @samp{_operand}, and those used with @code{match_operator} have names
697 that end in @samp{_operator}.
699 All predicates are Boolean functions (in the mathematical sense) of
700 two arguments: the RTL expression that is being considered at that
701 position in the instruction pattern, and the machine mode that the
702 @code{match_operand} or @code{match_operator} specifies. In this
703 section, the first argument is called @var{op} and the second argument
704 @var{mode}. Predicates can be called from C as ordinary two-argument
705 functions; this can be useful in output templates or other
706 machine-specific code.
708 Operand predicates can allow operands that are not actually acceptable
709 to the hardware, as long as the constraints give reload the ability to
710 fix them up (@pxref{Constraints}). However, GCC will usually generate
711 better code if the predicates specify the requirements of the machine
712 instructions as closely as possible. Reload cannot fix up operands
713 that must be constants (``immediate operands''); you must use a
714 predicate that allows only constants, or else enforce the requirement
715 in the extra condition.
717 @cindex predicates and machine modes
718 @cindex normal predicates
719 @cindex special predicates
720 Most predicates handle their @var{mode} argument in a uniform manner.
721 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
722 any mode. If @var{mode} is anything else, then @var{op} must have the
723 same mode, unless @var{op} is a @code{CONST_INT} or integer
724 @code{CONST_DOUBLE}. These RTL expressions always have
725 @code{VOIDmode}, so it would be counterproductive to check that their
726 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
727 integer @code{CONST_DOUBLE} check that the value stored in the
728 constant will fit in the requested mode.
730 Predicates with this behavior are called @dfn{normal}.
731 @command{genrecog} can optimize the instruction recognizer based on
732 knowledge of how normal predicates treat modes. It can also diagnose
733 certain kinds of common errors in the use of normal predicates; for
734 instance, it is almost always an error to use a normal predicate
735 without specifying a mode.
737 Predicates that do something different with their @var{mode} argument
738 are called @dfn{special}. The generic predicates
739 @code{address_operand} and @code{pmode_register_operand} are special
740 predicates. @command{genrecog} does not do any optimizations or
741 diagnosis when special predicates are used.
744 * Machine-Independent Predicates:: Predicates available to all back ends.
745 * Defining Predicates:: How to write machine-specific predicate
749 @node Machine-Independent Predicates
750 @subsection Machine-Independent Predicates
751 @cindex machine-independent predicates
752 @cindex generic predicates
754 These are the generic predicates available to all back ends. They are
755 defined in @file{recog.c}. The first category of predicates allow
756 only constant, or @dfn{immediate}, operands.
758 @defun immediate_operand
759 This predicate allows any sort of constant that fits in @var{mode}.
760 It is an appropriate choice for instructions that take operands that
764 @defun const_int_operand
765 This predicate allows any @code{CONST_INT} expression that fits in
766 @var{mode}. It is an appropriate choice for an immediate operand that
767 does not allow a symbol or label.
770 @defun const_double_operand
771 This predicate accepts any @code{CONST_DOUBLE} expression that has
772 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
773 accept @code{CONST_INT}. It is intended for immediate floating point
778 The second category of predicates allow only some kind of machine
781 @defun register_operand
782 This predicate allows any @code{REG} or @code{SUBREG} expression that
783 is valid for @var{mode}. It is often suitable for arithmetic
784 instruction operands on a RISC machine.
787 @defun pmode_register_operand
788 This is a slight variant on @code{register_operand} which works around
789 a limitation in the machine-description reader.
792 (match_operand @var{n} "pmode_register_operand" @var{constraint})
799 (match_operand:P @var{n} "register_operand" @var{constraint})
803 would mean, if the machine-description reader accepted @samp{:P}
804 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
805 alias for some other mode, and might vary with machine-specific
806 options. @xref{Misc}.
809 @defun scratch_operand
810 This predicate allows hard registers and @code{SCRATCH} expressions,
811 but not pseudo-registers. It is used internally by @code{match_scratch};
812 it should not be used directly.
816 The third category of predicates allow only some kind of memory reference.
818 @defun memory_operand
819 This predicate allows any valid reference to a quantity of mode
820 @var{mode} in memory, as determined by the weak form of
821 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
824 @defun address_operand
825 This predicate is a little unusual; it allows any operand that is a
826 valid expression for the @emph{address} of a quantity of mode
827 @var{mode}, again determined by the weak form of
828 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
829 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
830 @code{memory_operand}, then @var{exp} is acceptable to
831 @code{address_operand}. Note that @var{exp} does not necessarily have
835 @defun indirect_operand
836 This is a stricter form of @code{memory_operand} which allows only
837 memory references with a @code{general_operand} as the address
838 expression. New uses of this predicate are discouraged, because
839 @code{general_operand} is very permissive, so it's hard to tell what
840 an @code{indirect_operand} does or does not allow. If a target has
841 different requirements for memory operands for different instructions,
842 it is better to define target-specific predicates which enforce the
843 hardware's requirements explicitly.
847 This predicate allows a memory reference suitable for pushing a value
848 onto the stack. This will be a @code{MEM} which refers to
849 @code{stack_pointer_rtx}, with a side-effect in its address expression
850 (@pxref{Incdec}); which one is determined by the
851 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
855 This predicate allows a memory reference suitable for popping a value
856 off the stack. Again, this will be a @code{MEM} referring to
857 @code{stack_pointer_rtx}, with a side-effect in its address
858 expression. However, this time @code{STACK_POP_CODE} is expected.
862 The fourth category of predicates allow some combination of the above
865 @defun nonmemory_operand
866 This predicate allows any immediate or register operand valid for @var{mode}.
869 @defun nonimmediate_operand
870 This predicate allows any register or memory operand valid for @var{mode}.
873 @defun general_operand
874 This predicate allows any immediate, register, or memory operand
875 valid for @var{mode}.
879 Finally, there are two generic operator predicates.
881 @defun comparison_operator
882 This predicate matches any expression which performs an arithmetic
883 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
887 @defun ordered_comparison_operator
888 This predicate matches any expression which performs an arithmetic
889 comparison in @var{mode} and whose expression code is valid for integer
890 modes; that is, the expression code will be one of @code{eq}, @code{ne},
891 @code{lt}, @code{ltu}, @code{le}, @code{leu}, @code{gt}, @code{gtu},
892 @code{ge}, @code{geu}.
895 @node Defining Predicates
896 @subsection Defining Machine-Specific Predicates
897 @cindex defining predicates
898 @findex define_predicate
899 @findex define_special_predicate
901 Many machines have requirements for their operands that cannot be
902 expressed precisely using the generic predicates. You can define
903 additional predicates using @code{define_predicate} and
904 @code{define_special_predicate} expressions. These expressions have
909 The name of the predicate, as it will be referred to in
910 @code{match_operand} or @code{match_operator} expressions.
913 An RTL expression which evaluates to true if the predicate allows the
914 operand @var{op}, false if it does not. This expression can only use
915 the following RTL codes:
919 When written inside a predicate expression, a @code{MATCH_OPERAND}
920 expression evaluates to true if the predicate it names would allow
921 @var{op}. The operand number and constraint are ignored. Due to
922 limitations in @command{genrecog}, you can only refer to generic
923 predicates and predicates that have already been defined.
926 This expression evaluates to true if @var{op} or a specified
927 subexpression of @var{op} has one of a given list of RTX codes.
929 The first operand of this expression is a string constant containing a
930 comma-separated list of RTX code names (in lower case). These are the
931 codes for which the @code{MATCH_CODE} will be true.
933 The second operand is a string constant which indicates what
934 subexpression of @var{op} to examine. If it is absent or the empty
935 string, @var{op} itself is examined. Otherwise, the string constant
936 must be a sequence of digits and/or lowercase letters. Each character
937 indicates a subexpression to extract from the current expression; for
938 the first character this is @var{op}, for the second and subsequent
939 characters it is the result of the previous character. A digit
940 @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l}
941 extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the
942 alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
943 @code{MATCH_CODE} then examines the RTX code of the subexpression
944 extracted by the complete string. It is not possible to extract
945 components of an @code{rtvec} that is not at position 0 within its RTX
949 This expression has one operand, a string constant containing a C
950 expression. The predicate's arguments, @var{op} and @var{mode}, are
951 available with those names in the C expression. The @code{MATCH_TEST}
952 evaluates to true if the C expression evaluates to a nonzero value.
953 @code{MATCH_TEST} expressions must not have side effects.
959 The basic @samp{MATCH_} expressions can be combined using these
960 logical operators, which have the semantics of the C operators
961 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
962 in Common Lisp, you may give an @code{AND} or @code{IOR} expression an
963 arbitrary number of arguments; this has exactly the same effect as
964 writing a chain of two-argument @code{AND} or @code{IOR} expressions.
968 An optional block of C code, which should execute
969 @samp{@w{return true}} if the predicate is found to match and
970 @samp{@w{return false}} if it does not. It must not have any side
971 effects. The predicate arguments, @var{op} and @var{mode}, are
972 available with those names.
974 If a code block is present in a predicate definition, then the RTL
975 expression must evaluate to true @emph{and} the code block must
976 execute @samp{@w{return true}} for the predicate to allow the operand.
977 The RTL expression is evaluated first; do not re-check anything in the
978 code block that was checked in the RTL expression.
981 The program @command{genrecog} scans @code{define_predicate} and
982 @code{define_special_predicate} expressions to determine which RTX
983 codes are possibly allowed. You should always make this explicit in
984 the RTL predicate expression, using @code{MATCH_OPERAND} and
987 Here is an example of a simple predicate definition, from the IA64
992 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
993 (define_predicate "small_addr_symbolic_operand"
994 (and (match_code "symbol_ref")
995 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
1000 And here is another, showing the use of the C block.
1004 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
1005 (define_predicate "gr_register_operand"
1006 (match_operand 0 "register_operand")
1009 if (GET_CODE (op) == SUBREG)
1010 op = SUBREG_REG (op);
1013 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
1018 Predicates written with @code{define_predicate} automatically include
1019 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
1020 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
1021 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
1022 integer @code{CONST_DOUBLE}, nor do they test that the value of either
1023 kind of constant fits in the requested mode. This is because
1024 target-specific predicates that take constants usually have to do more
1025 stringent value checks anyway. If you need the exact same treatment
1026 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
1027 provide, use a @code{MATCH_OPERAND} subexpression to call
1028 @code{const_int_operand}, @code{const_double_operand}, or
1029 @code{immediate_operand}.
1031 Predicates written with @code{define_special_predicate} do not get any
1032 automatic mode checks, and are treated as having special mode handling
1033 by @command{genrecog}.
1035 The program @command{genpreds} is responsible for generating code to
1036 test predicates. It also writes a header file containing function
1037 declarations for all machine-specific predicates. It is not necessary
1038 to declare these predicates in @file{@var{cpu}-protos.h}.
1041 @c Most of this node appears by itself (in a different place) even
1042 @c when the INTERNALS flag is clear. Passages that require the internals
1043 @c manual's context are conditionalized to appear only in the internals manual.
1046 @section Operand Constraints
1047 @cindex operand constraints
1050 Each @code{match_operand} in an instruction pattern can specify
1051 constraints for the operands allowed. The constraints allow you to
1052 fine-tune matching within the set of operands allowed by the
1058 @section Constraints for @code{asm} Operands
1059 @cindex operand constraints, @code{asm}
1060 @cindex constraints, @code{asm}
1061 @cindex @code{asm} constraints
1063 Here are specific details on what constraint letters you can use with
1064 @code{asm} operands.
1066 Constraints can say whether
1067 an operand may be in a register, and which kinds of register; whether the
1068 operand can be a memory reference, and which kinds of address; whether the
1069 operand may be an immediate constant, and which possible values it may
1070 have. Constraints can also require two operands to match.
1071 Side-effects aren't allowed in operands of inline @code{asm}, unless
1072 @samp{<} or @samp{>} constraints are used, because there is no guarantee
1073 that the side-effects will happen exactly once in an instruction that can update
1074 the addressing register.
1078 * Simple Constraints:: Basic use of constraints.
1079 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1080 * Class Preferences:: Constraints guide which hard register to put things in.
1081 * Modifiers:: More precise control over effects of constraints.
1082 * Machine Constraints:: Existing constraints for some particular machines.
1083 * Disable Insn Alternatives:: Disable insn alternatives using the @code{enabled} attribute.
1084 * Define Constraints:: How to define machine-specific constraints.
1085 * C Constraint Interface:: How to test constraints from C code.
1091 * Simple Constraints:: Basic use of constraints.
1092 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1093 * Modifiers:: More precise control over effects of constraints.
1094 * Machine Constraints:: Special constraints for some particular machines.
1098 @node Simple Constraints
1099 @subsection Simple Constraints
1100 @cindex simple constraints
1102 The simplest kind of constraint is a string full of letters, each of
1103 which describes one kind of operand that is permitted. Here are
1104 the letters that are allowed:
1108 Whitespace characters are ignored and can be inserted at any position
1109 except the first. This enables each alternative for different operands to
1110 be visually aligned in the machine description even if they have different
1111 number of constraints and modifiers.
1113 @cindex @samp{m} in constraint
1114 @cindex memory references in constraints
1116 A memory operand is allowed, with any kind of address that the machine
1117 supports in general.
1118 Note that the letter used for the general memory constraint can be
1119 re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro.
1121 @cindex offsettable address
1122 @cindex @samp{o} in constraint
1124 A memory operand is allowed, but only if the address is
1125 @dfn{offsettable}. This means that adding a small integer (actually,
1126 the width in bytes of the operand, as determined by its machine mode)
1127 may be added to the address and the result is also a valid memory
1130 @cindex autoincrement/decrement addressing
1131 For example, an address which is constant is offsettable; so is an
1132 address that is the sum of a register and a constant (as long as a
1133 slightly larger constant is also within the range of address-offsets
1134 supported by the machine); but an autoincrement or autodecrement
1135 address is not offsettable. More complicated indirect/indexed
1136 addresses may or may not be offsettable depending on the other
1137 addressing modes that the machine supports.
1139 Note that in an output operand which can be matched by another
1140 operand, the constraint letter @samp{o} is valid only when accompanied
1141 by both @samp{<} (if the target machine has predecrement addressing)
1142 and @samp{>} (if the target machine has preincrement addressing).
1144 @cindex @samp{V} in constraint
1146 A memory operand that is not offsettable. In other words, anything that
1147 would fit the @samp{m} constraint but not the @samp{o} constraint.
1149 @cindex @samp{<} in constraint
1151 A memory operand with autodecrement addressing (either predecrement or
1152 postdecrement) is allowed. In inline @code{asm} this constraint is only
1153 allowed if the operand is used exactly once in an instruction that can
1154 handle the side-effects. Not using an operand with @samp{<} in constraint
1155 string in the inline @code{asm} pattern at all or using it in multiple
1156 instructions isn't valid, because the side-effects wouldn't be performed
1157 or would be performed more than once. Furthermore, on some targets
1158 the operand with @samp{<} in constraint string must be accompanied by
1159 special instruction suffixes like @code{%U0} instruction suffix on PowerPC
1160 or @code{%P0} on IA-64.
1162 @cindex @samp{>} in constraint
1164 A memory operand with autoincrement addressing (either preincrement or
1165 postincrement) is allowed. In inline @code{asm} the same restrictions
1166 as for @samp{<} apply.
1168 @cindex @samp{r} in constraint
1169 @cindex registers in constraints
1171 A register operand is allowed provided that it is in a general
1174 @cindex constants in constraints
1175 @cindex @samp{i} in constraint
1177 An immediate integer operand (one with constant value) is allowed.
1178 This includes symbolic constants whose values will be known only at
1179 assembly time or later.
1181 @cindex @samp{n} in constraint
1183 An immediate integer operand with a known numeric value is allowed.
1184 Many systems cannot support assembly-time constants for operands less
1185 than a word wide. Constraints for these operands should use @samp{n}
1186 rather than @samp{i}.
1188 @cindex @samp{I} in constraint
1189 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1190 Other letters in the range @samp{I} through @samp{P} may be defined in
1191 a machine-dependent fashion to permit immediate integer operands with
1192 explicit integer values in specified ranges. For example, on the
1193 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1194 This is the range permitted as a shift count in the shift
1197 @cindex @samp{E} in constraint
1199 An immediate floating operand (expression code @code{const_double}) is
1200 allowed, but only if the target floating point format is the same as
1201 that of the host machine (on which the compiler is running).
1203 @cindex @samp{F} in constraint
1205 An immediate floating operand (expression code @code{const_double} or
1206 @code{const_vector}) is allowed.
1208 @cindex @samp{G} in constraint
1209 @cindex @samp{H} in constraint
1210 @item @samp{G}, @samp{H}
1211 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1212 permit immediate floating operands in particular ranges of values.
1214 @cindex @samp{s} in constraint
1216 An immediate integer operand whose value is not an explicit integer is
1219 This might appear strange; if an insn allows a constant operand with a
1220 value not known at compile time, it certainly must allow any known
1221 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1222 better code to be generated.
1224 For example, on the 68000 in a fullword instruction it is possible to
1225 use an immediate operand; but if the immediate value is between @minus{}128
1226 and 127, better code results from loading the value into a register and
1227 using the register. This is because the load into the register can be
1228 done with a @samp{moveq} instruction. We arrange for this to happen
1229 by defining the letter @samp{K} to mean ``any integer outside the
1230 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1233 @cindex @samp{g} in constraint
1235 Any register, memory or immediate integer operand is allowed, except for
1236 registers that are not general registers.
1238 @cindex @samp{X} in constraint
1241 Any operand whatsoever is allowed, even if it does not satisfy
1242 @code{general_operand}. This is normally used in the constraint of
1243 a @code{match_scratch} when certain alternatives will not actually
1244 require a scratch register.
1247 Any operand whatsoever is allowed.
1250 @cindex @samp{0} in constraint
1251 @cindex digits in constraint
1252 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1253 An operand that matches the specified operand number is allowed. If a
1254 digit is used together with letters within the same alternative, the
1255 digit should come last.
1257 This number is allowed to be more than a single digit. If multiple
1258 digits are encountered consecutively, they are interpreted as a single
1259 decimal integer. There is scant chance for ambiguity, since to-date
1260 it has never been desirable that @samp{10} be interpreted as matching
1261 either operand 1 @emph{or} operand 0. Should this be desired, one
1262 can use multiple alternatives instead.
1264 @cindex matching constraint
1265 @cindex constraint, matching
1266 This is called a @dfn{matching constraint} and what it really means is
1267 that the assembler has only a single operand that fills two roles
1269 considered separate in the RTL insn. For example, an add insn has two
1270 input operands and one output operand in the RTL, but on most CISC
1273 which @code{asm} distinguishes. For example, an add instruction uses
1274 two input operands and an output operand, but on most CISC
1276 machines an add instruction really has only two operands, one of them an
1277 input-output operand:
1283 Matching constraints are used in these circumstances.
1284 More precisely, the two operands that match must include one input-only
1285 operand and one output-only operand. Moreover, the digit must be a
1286 smaller number than the number of the operand that uses it in the
1290 For operands to match in a particular case usually means that they
1291 are identical-looking RTL expressions. But in a few special cases
1292 specific kinds of dissimilarity are allowed. For example, @code{*x}
1293 as an input operand will match @code{*x++} as an output operand.
1294 For proper results in such cases, the output template should always
1295 use the output-operand's number when printing the operand.
1298 @cindex load address instruction
1299 @cindex push address instruction
1300 @cindex address constraints
1301 @cindex @samp{p} in constraint
1303 An operand that is a valid memory address is allowed. This is
1304 for ``load address'' and ``push address'' instructions.
1306 @findex address_operand
1307 @samp{p} in the constraint must be accompanied by @code{address_operand}
1308 as the predicate in the @code{match_operand}. This predicate interprets
1309 the mode specified in the @code{match_operand} as the mode of the memory
1310 reference for which the address would be valid.
1312 @cindex other register constraints
1313 @cindex extensible constraints
1314 @item @var{other-letters}
1315 Other letters can be defined in machine-dependent fashion to stand for
1316 particular classes of registers or other arbitrary operand types.
1317 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1318 for data, address and floating point registers.
1322 In order to have valid assembler code, each operand must satisfy
1323 its constraint. But a failure to do so does not prevent the pattern
1324 from applying to an insn. Instead, it directs the compiler to modify
1325 the code so that the constraint will be satisfied. Usually this is
1326 done by copying an operand into a register.
1328 Contrast, therefore, the two instruction patterns that follow:
1332 [(set (match_operand:SI 0 "general_operand" "=r")
1333 (plus:SI (match_dup 0)
1334 (match_operand:SI 1 "general_operand" "r")))]
1340 which has two operands, one of which must appear in two places, and
1344 [(set (match_operand:SI 0 "general_operand" "=r")
1345 (plus:SI (match_operand:SI 1 "general_operand" "0")
1346 (match_operand:SI 2 "general_operand" "r")))]
1352 which has three operands, two of which are required by a constraint to be
1353 identical. If we are considering an insn of the form
1356 (insn @var{n} @var{prev} @var{next}
1358 (plus:SI (reg:SI 6) (reg:SI 109)))
1363 the first pattern would not apply at all, because this insn does not
1364 contain two identical subexpressions in the right place. The pattern would
1365 say, ``That does not look like an add instruction; try other patterns''.
1366 The second pattern would say, ``Yes, that's an add instruction, but there
1367 is something wrong with it''. It would direct the reload pass of the
1368 compiler to generate additional insns to make the constraint true. The
1369 results might look like this:
1372 (insn @var{n2} @var{prev} @var{n}
1373 (set (reg:SI 3) (reg:SI 6))
1376 (insn @var{n} @var{n2} @var{next}
1378 (plus:SI (reg:SI 3) (reg:SI 109)))
1382 It is up to you to make sure that each operand, in each pattern, has
1383 constraints that can handle any RTL expression that could be present for
1384 that operand. (When multiple alternatives are in use, each pattern must,
1385 for each possible combination of operand expressions, have at least one
1386 alternative which can handle that combination of operands.) The
1387 constraints don't need to @emph{allow} any possible operand---when this is
1388 the case, they do not constrain---but they must at least point the way to
1389 reloading any possible operand so that it will fit.
1393 If the constraint accepts whatever operands the predicate permits,
1394 there is no problem: reloading is never necessary for this operand.
1396 For example, an operand whose constraints permit everything except
1397 registers is safe provided its predicate rejects registers.
1399 An operand whose predicate accepts only constant values is safe
1400 provided its constraints include the letter @samp{i}. If any possible
1401 constant value is accepted, then nothing less than @samp{i} will do;
1402 if the predicate is more selective, then the constraints may also be
1406 Any operand expression can be reloaded by copying it into a register.
1407 So if an operand's constraints allow some kind of register, it is
1408 certain to be safe. It need not permit all classes of registers; the
1409 compiler knows how to copy a register into another register of the
1410 proper class in order to make an instruction valid.
1412 @cindex nonoffsettable memory reference
1413 @cindex memory reference, nonoffsettable
1415 A nonoffsettable memory reference can be reloaded by copying the
1416 address into a register. So if the constraint uses the letter
1417 @samp{o}, all memory references are taken care of.
1420 A constant operand can be reloaded by allocating space in memory to
1421 hold it as preinitialized data. Then the memory reference can be used
1422 in place of the constant. So if the constraint uses the letters
1423 @samp{o} or @samp{m}, constant operands are not a problem.
1426 If the constraint permits a constant and a pseudo register used in an insn
1427 was not allocated to a hard register and is equivalent to a constant,
1428 the register will be replaced with the constant. If the predicate does
1429 not permit a constant and the insn is re-recognized for some reason, the
1430 compiler will crash. Thus the predicate must always recognize any
1431 objects allowed by the constraint.
1434 If the operand's predicate can recognize registers, but the constraint does
1435 not permit them, it can make the compiler crash. When this operand happens
1436 to be a register, the reload pass will be stymied, because it does not know
1437 how to copy a register temporarily into memory.
1439 If the predicate accepts a unary operator, the constraint applies to the
1440 operand. For example, the MIPS processor at ISA level 3 supports an
1441 instruction which adds two registers in @code{SImode} to produce a
1442 @code{DImode} result, but only if the registers are correctly sign
1443 extended. This predicate for the input operands accepts a
1444 @code{sign_extend} of an @code{SImode} register. Write the constraint
1445 to indicate the type of register that is required for the operand of the
1449 @node Multi-Alternative
1450 @subsection Multiple Alternative Constraints
1451 @cindex multiple alternative constraints
1453 Sometimes a single instruction has multiple alternative sets of possible
1454 operands. For example, on the 68000, a logical-or instruction can combine
1455 register or an immediate value into memory, or it can combine any kind of
1456 operand into a register; but it cannot combine one memory location into
1459 These constraints are represented as multiple alternatives. An alternative
1460 can be described by a series of letters for each operand. The overall
1461 constraint for an operand is made from the letters for this operand
1462 from the first alternative, a comma, the letters for this operand from
1463 the second alternative, a comma, and so on until the last alternative.
1465 Here is how it is done for fullword logical-or on the 68000:
1468 (define_insn "iorsi3"
1469 [(set (match_operand:SI 0 "general_operand" "=m,d")
1470 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1471 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1475 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1476 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1477 2. The second alternative has @samp{d} (data register) for operand 0,
1478 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1479 @samp{%} in the constraints apply to all the alternatives; their
1480 meaning is explained in the next section (@pxref{Class Preferences}).
1483 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1484 If all the operands fit any one alternative, the instruction is valid.
1485 Otherwise, for each alternative, the compiler counts how many instructions
1486 must be added to copy the operands so that that alternative applies.
1487 The alternative requiring the least copying is chosen. If two alternatives
1488 need the same amount of copying, the one that comes first is chosen.
1489 These choices can be altered with the @samp{?} and @samp{!} characters:
1492 @cindex @samp{?} in constraint
1493 @cindex question mark
1495 Disparage slightly the alternative that the @samp{?} appears in,
1496 as a choice when no alternative applies exactly. The compiler regards
1497 this alternative as one unit more costly for each @samp{?} that appears
1500 @cindex @samp{!} in constraint
1501 @cindex exclamation point
1503 Disparage severely the alternative that the @samp{!} appears in.
1504 This alternative can still be used if it fits without reloading,
1505 but if reloading is needed, some other alternative will be used.
1509 When an insn pattern has multiple alternatives in its constraints, often
1510 the appearance of the assembler code is determined mostly by which
1511 alternative was matched. When this is so, the C code for writing the
1512 assembler code can use the variable @code{which_alternative}, which is
1513 the ordinal number of the alternative that was actually satisfied (0 for
1514 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1518 @node Class Preferences
1519 @subsection Register Class Preferences
1520 @cindex class preference constraints
1521 @cindex register class preference constraints
1523 @cindex voting between constraint alternatives
1524 The operand constraints have another function: they enable the compiler
1525 to decide which kind of hardware register a pseudo register is best
1526 allocated to. The compiler examines the constraints that apply to the
1527 insns that use the pseudo register, looking for the machine-dependent
1528 letters such as @samp{d} and @samp{a} that specify classes of registers.
1529 The pseudo register is put in whichever class gets the most ``votes''.
1530 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1531 favor of a general register. The machine description says which registers
1532 are considered general.
1534 Of course, on some machines all registers are equivalent, and no register
1535 classes are defined. Then none of this complexity is relevant.
1539 @subsection Constraint Modifier Characters
1540 @cindex modifiers in constraints
1541 @cindex constraint modifier characters
1543 @c prevent bad page break with this line
1544 Here are constraint modifier characters.
1547 @cindex @samp{=} in constraint
1549 Means that this operand is write-only for this instruction: the previous
1550 value is discarded and replaced by output data.
1552 @cindex @samp{+} in constraint
1554 Means that this operand is both read and written by the instruction.
1556 When the compiler fixes up the operands to satisfy the constraints,
1557 it needs to know which operands are inputs to the instruction and
1558 which are outputs from it. @samp{=} identifies an output; @samp{+}
1559 identifies an operand that is both input and output; all other operands
1560 are assumed to be input only.
1562 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1563 first character of the constraint string.
1565 @cindex @samp{&} in constraint
1566 @cindex earlyclobber operand
1568 Means (in a particular alternative) that this operand is an
1569 @dfn{earlyclobber} operand, which is modified before the instruction is
1570 finished using the input operands. Therefore, this operand may not lie
1571 in a register that is used as an input operand or as part of any memory
1574 @samp{&} applies only to the alternative in which it is written. In
1575 constraints with multiple alternatives, sometimes one alternative
1576 requires @samp{&} while others do not. See, for example, the
1577 @samp{movdf} insn of the 68000.
1579 An input operand can be tied to an earlyclobber operand if its only
1580 use as an input occurs before the early result is written. Adding
1581 alternatives of this form often allows GCC to produce better code
1582 when only some of the inputs can be affected by the earlyclobber.
1583 See, for example, the @samp{mulsi3} insn of the ARM@.
1585 Furthermore, if the @dfn{earlyclobber} operand is also read/write operand, then
1586 that operand is modified only after it's used.
1588 @samp{&} does not obviate the need to write @samp{=} or @samp{+}.
1590 @cindex @samp{%} in constraint
1592 Declares the instruction to be commutative for this operand and the
1593 following operand. This means that the compiler may interchange the
1594 two operands if that is the cheapest way to make all operands fit the
1595 constraints. @samp{%} applies to all alternatives and must appear as
1596 the first character in the constraint. Only input operands can use
1600 This is often used in patterns for addition instructions
1601 that really have only two operands: the result must go in one of the
1602 arguments. Here for example, is how the 68000 halfword-add
1603 instruction is defined:
1606 (define_insn "addhi3"
1607 [(set (match_operand:HI 0 "general_operand" "=m,r")
1608 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1609 (match_operand:HI 2 "general_operand" "di,g")))]
1613 GCC can only handle one commutative pair in an asm; if you use more,
1614 the compiler may fail. Note that you need not use the modifier if
1615 the two alternatives are strictly identical; this would only waste
1616 time in the reload pass. The modifier is not operational after
1617 register allocation, so the result of @code{define_peephole2}
1618 and @code{define_split}s performed after reload cannot rely on
1619 @samp{%} to make the intended insn match.
1621 @cindex @samp{#} in constraint
1623 Says that all following characters, up to the next comma, are to be
1624 ignored as a constraint. They are significant only for choosing
1625 register preferences.
1627 @cindex @samp{*} in constraint
1629 Says that the following character should be ignored when choosing
1630 register preferences. @samp{*} has no effect on the meaning of the
1631 constraint as a constraint, and no effect on reloading. For LRA
1632 @samp{*} additionally disparages slightly the alternative if the
1633 following character matches the operand.
1636 Here is an example: the 68000 has an instruction to sign-extend a
1637 halfword in a data register, and can also sign-extend a value by
1638 copying it into an address register. While either kind of register is
1639 acceptable, the constraints on an address-register destination are
1640 less strict, so it is best if register allocation makes an address
1641 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1642 constraint letter (for data register) is ignored when computing
1643 register preferences.
1646 (define_insn "extendhisi2"
1647 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1649 (match_operand:HI 1 "general_operand" "0,g")))]
1655 @node Machine Constraints
1656 @subsection Constraints for Particular Machines
1657 @cindex machine specific constraints
1658 @cindex constraints, machine specific
1660 Whenever possible, you should use the general-purpose constraint letters
1661 in @code{asm} arguments, since they will convey meaning more readily to
1662 people reading your code. Failing that, use the constraint letters
1663 that usually have very similar meanings across architectures. The most
1664 commonly used constraints are @samp{m} and @samp{r} (for memory and
1665 general-purpose registers respectively; @pxref{Simple Constraints}), and
1666 @samp{I}, usually the letter indicating the most common
1667 immediate-constant format.
1669 Each architecture defines additional constraints. These constraints
1670 are used by the compiler itself for instruction generation, as well as
1671 for @code{asm} statements; therefore, some of the constraints are not
1672 particularly useful for @code{asm}. Here is a summary of some of the
1673 machine-dependent constraints available on some particular machines;
1674 it includes both constraints that are useful for @code{asm} and
1675 constraints that aren't. The compiler source file mentioned in the
1676 table heading for each architecture is the definitive reference for
1677 the meanings of that architecture's constraints.
1680 @item AArch64 family---@file{config/aarch64/constraints.md}
1683 The stack pointer register (@code{SP})
1686 Floating point or SIMD vector register
1689 Integer constant that is valid as an immediate operand in an @code{ADD}
1693 Integer constant that is valid as an immediate operand in a @code{SUB}
1694 instruction (once negated)
1697 Integer constant that can be used with a 32-bit logical instruction
1700 Integer constant that can be used with a 64-bit logical instruction
1703 Integer constant that is valid as an immediate operand in a 32-bit @code{MOV}
1704 pseudo instruction. The @code{MOV} may be assembled to one of several different
1705 machine instructions depending on the value
1708 Integer constant that is valid as an immediate operand in a 64-bit @code{MOV}
1712 An absolute symbolic address or a label reference
1715 Floating point constant zero
1718 Integer constant zero
1721 The high part (bits 12 and upwards) of the pc-relative address of a symbol
1722 within 4GB of the instruction
1725 A memory address which uses a single base register with no offset
1728 A memory address suitable for a load/store pair instruction in SI, DI, SF and
1734 @item ARC ---@file{config/arc/constraints.md}
1737 Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
1738 @code{r12}-@code{r15}. This constraint can only match when the @option{-mq}
1739 option is in effect.
1742 Registers usable as base-regs of memory addresses in ARCompact 16-bit memory
1743 instructions: @code{r0}-@code{r3}, @code{r12}-@code{r15}, @code{sp}.
1744 This constraint can only match when the @option{-mq}
1745 option is in effect.
1747 ARC FPX (dpfp) 64-bit registers. @code{D0}, @code{D1}.
1750 A signed 12-bit integer constant.
1753 constant for arithmetic/logical operations. This might be any constant
1754 that can be put into a long immediate by the assmbler or linker without
1755 involving a PIC relocation.
1758 A 3-bit unsigned integer constant.
1761 A 6-bit unsigned integer constant.
1764 One's complement of a 6-bit unsigned integer constant.
1767 Two's complement of a 6-bit unsigned integer constant.
1770 A 5-bit unsigned integer constant.
1773 A 7-bit unsigned integer constant.
1776 A 8-bit unsigned integer constant.
1779 Any const_double value.
1782 @item ARM family---@file{config/arm/constraints.md}
1785 VFP floating-point register
1788 The floating-point constant 0.0
1791 Integer that is valid as an immediate operand in a data processing
1792 instruction. That is, an integer in the range 0 to 255 rotated by a
1796 Integer in the range @minus{}4095 to 4095
1799 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1802 Integer that satisfies constraint @samp{I} when negated (twos complement)
1805 Integer in the range 0 to 32
1808 A memory reference where the exact address is in a single register
1809 (`@samp{m}' is preferable for @code{asm} statements)
1812 An item in the constant pool
1815 A symbol in the text segment of the current file
1818 A memory reference suitable for VFP load/store insns (reg+constant offset)
1821 A memory reference suitable for iWMMXt load/store instructions.
1824 A memory reference suitable for the ARMv4 ldrsb instruction.
1827 @item AVR family---@file{config/avr/constraints.md}
1830 Registers from r0 to r15
1833 Registers from r16 to r23
1836 Registers from r16 to r31
1839 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1842 Pointer register (r26--r31)
1845 Base pointer register (r28--r31)
1848 Stack pointer register (SPH:SPL)
1851 Temporary register r0
1854 Register pair X (r27:r26)
1857 Register pair Y (r29:r28)
1860 Register pair Z (r31:r30)
1863 Constant greater than @minus{}1, less than 64
1866 Constant greater than @minus{}64, less than 1
1875 Constant that fits in 8 bits
1878 Constant integer @minus{}1
1881 Constant integer 8, 16, or 24
1887 A floating point constant 0.0
1890 A memory address based on Y or Z pointer with displacement.
1893 @item Epiphany---@file{config/epiphany/constraints.md}
1896 An unsigned 16-bit constant.
1899 An unsigned 5-bit constant.
1902 A signed 11-bit constant.
1905 A signed 11-bit constant added to @minus{}1.
1906 Can only match when the @option{-m1reg-@var{reg}} option is active.
1909 Left-shift of @minus{}1, i.e., a bit mask with a block of leading ones, the rest
1910 being a block of trailing zeroes.
1911 Can only match when the @option{-m1reg-@var{reg}} option is active.
1914 Right-shift of @minus{}1, i.e., a bit mask with a trailing block of ones, the
1915 rest being zeroes. Or to put it another way, one less than a power of two.
1916 Can only match when the @option{-m1reg-@var{reg}} option is active.
1919 Constant for arithmetic/logical operations.
1920 This is like @code{i}, except that for position independent code,
1921 no symbols / expressions needing relocations are allowed.
1924 Symbolic constant for call/jump instruction.
1927 The register class usable in short insns. This is a register class
1928 constraint, and can thus drive register allocation.
1929 This constraint won't match unless @option{-mprefer-short-insn-regs} is
1933 The the register class of registers that can be used to hold a
1934 sibcall call address. I.e., a caller-saved register.
1937 Core control register class.
1940 The register group usable in short insns.
1941 This constraint does not use a register class, so that it only
1942 passively matches suitable registers, and doesn't drive register allocation.
1946 Constant suitable for the addsi3_r pattern. This is a valid offset
1947 For byte, halfword, or word addressing.
1951 Matches the return address if it can be replaced with the link register.
1954 Matches the integer condition code register.
1957 Matches the return address if it is in a stack slot.
1960 Matches control register values to switch fp mode, which are encapsulated in
1961 @code{UNSPEC_FP_MODE}.
1964 @item CR16 Architecture---@file{config/cr16/cr16.h}
1968 Registers from r0 to r14 (registers without stack pointer)
1971 Register from r0 to r11 (all 16-bit registers)
1974 Register from r12 to r15 (all 32-bit registers)
1977 Signed constant that fits in 4 bits
1980 Signed constant that fits in 5 bits
1983 Signed constant that fits in 6 bits
1986 Unsigned constant that fits in 4 bits
1989 Signed constant that fits in 32 bits
1992 Check for 64 bits wide constants for add/sub instructions
1995 Floating point constant that is legal for store immediate
1998 @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
2004 Floating point register
2007 Shift amount register
2010 Floating point register (deprecated)
2013 Upper floating point register (32-bit), floating point register (64-bit)
2019 Signed 11-bit integer constant
2022 Signed 14-bit integer constant
2025 Integer constant that can be deposited with a @code{zdepi} instruction
2028 Signed 5-bit integer constant
2034 Integer constant that can be loaded with a @code{ldil} instruction
2037 Integer constant whose value plus one is a power of 2
2040 Integer constant that can be used for @code{and} operations in @code{depi}
2041 and @code{extru} instructions
2050 Floating-point constant 0.0
2053 A @code{lo_sum} data-linkage-table memory operand
2056 A memory operand that can be used as the destination operand of an
2057 integer store instruction
2060 A scaled or unscaled indexed memory operand
2063 A memory operand for floating-point loads and stores
2066 A register indirect memory operand
2069 @item picoChip family---@file{picochip.h}
2075 Pointer register. A register which can be used to access memory without
2076 supplying an offset. Any other register can be used to access memory,
2077 but will need a constant offset. In the case of the offset being zero,
2078 it is more efficient to use a pointer register, since this reduces code
2082 A twin register. A register which may be paired with an adjacent
2083 register to create a 32-bit register.
2086 Any absolute memory address (e.g., symbolic constant, symbolic
2090 4-bit signed integer.
2093 4-bit unsigned integer.
2096 8-bit signed integer.
2099 Any constant whose absolute value is no greater than 4-bits.
2102 10-bit signed integer
2105 16-bit signed integer.
2109 @item PowerPC and IBM RS6000---@file{config/rs6000/constraints.md}
2112 Address base register
2115 Floating point register (containing 64-bit value)
2118 Floating point register (containing 32-bit value)
2121 Altivec vector register
2124 Any VSX register if the -mvsx option was used or NO_REGS.
2127 VSX vector register to hold vector double data or NO_REGS.
2130 VSX vector register to hold vector float data or NO_REGS.
2133 If @option{-mmfpgpr} was used, a floating point register or NO_REGS.
2136 Floating point register if direct moves are available, or NO_REGS.
2139 FP or VSX register to hold 64-bit integers or NO_REGS.
2142 FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.
2145 FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.
2148 Floating point register if the LFIWAX instruction is enabled or NO_REGS.
2151 VSX register if direct move instructions are enabled, or NO_REGS.
2154 No register (NO_REGS).
2157 General purpose register if 64-bit instructions are enabled or NO_REGS.
2160 VSX vector register to hold scalar double values or NO_REGS.
2163 VSX vector register to hold 128 bit integer or NO_REGS.
2166 Altivec register to use for float/32-bit int loads/stores or NO_REGS.
2169 Altivec register to use for double loads/stores or NO_REGS.
2172 FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS.
2175 Floating point register if the STFIWX instruction is enabled or NO_REGS.
2178 FP or VSX register to perform ISA 2.07 float ops or NO_REGS.
2181 Floating point register if the LFIWZX instruction is enabled or NO_REGS.
2184 Int constant that is the element number of the 64-bit scalar in a vector.
2187 A memory address that will work with the @code{lq} and @code{stq}
2191 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
2200 @samp{LINK} register
2203 @samp{CR} register (condition register) number 0
2206 @samp{CR} register (condition register)
2209 @samp{XER[CA]} carry bit (part of the XER register)
2212 Signed 16-bit constant
2215 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
2216 @code{SImode} constants)
2219 Unsigned 16-bit constant
2222 Signed 16-bit constant shifted left 16 bits
2225 Constant larger than 31
2234 Constant whose negation is a signed 16-bit constant
2237 Floating point constant that can be loaded into a register with one
2238 instruction per word
2241 Integer/Floating point constant that can be loaded into a register using
2246 Normally, @code{m} does not allow addresses that update the base register.
2247 If @samp{<} or @samp{>} constraint is also used, they are allowed and
2248 therefore on PowerPC targets in that case it is only safe
2249 to use @samp{m<>} in an @code{asm} statement if that @code{asm} statement
2250 accesses the operand exactly once. The @code{asm} statement must also
2251 use @samp{%U@var{<opno>}} as a placeholder for the ``update'' flag in the
2252 corresponding load or store instruction. For example:
2255 asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val));
2261 asm ("st %1,%0" : "=m<>" (mem) : "r" (val));
2267 A ``stable'' memory operand; that is, one which does not include any
2268 automodification of the base register. This used to be useful when
2269 @samp{m} allowed automodification of the base register, but as those are now only
2270 allowed when @samp{<} or @samp{>} is used, @samp{es} is basically the same
2271 as @samp{m} without @samp{<} and @samp{>}.
2274 Memory operand that is an offset from a register (it is usually better
2275 to use @samp{m} or @samp{es} in @code{asm} statements)
2278 Memory operand that is an indexed or indirect from a register (it is
2279 usually better to use @samp{m} or @samp{es} in @code{asm} statements)
2285 Address operand that is an indexed or indirect from a register (@samp{p} is
2286 preferable for @code{asm} statements)
2289 Constant suitable as a 64-bit mask operand
2292 Constant suitable as a 32-bit mask operand
2295 System V Release 4 small data area reference
2298 AND masks that can be performed by two rldic@{l, r@} instructions
2301 Vector constant that does not require memory
2304 Vector constant that is all zeros.
2308 @item Intel 386---@file{config/i386/constraints.md}
2311 Legacy register---the eight integer registers available on all
2312 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
2313 @code{si}, @code{di}, @code{bp}, @code{sp}).
2316 Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
2317 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
2320 Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
2321 @code{c}, and @code{d}.
2325 Any register that can be used as the index in a base+index memory
2326 access: that is, any general register except the stack pointer.
2330 The @code{a} register.
2333 The @code{b} register.
2336 The @code{c} register.
2339 The @code{d} register.
2342 The @code{si} register.
2345 The @code{di} register.
2348 The @code{a} and @code{d} registers. This class is used for instructions
2349 that return double word results in the @code{ax:dx} register pair. Single
2350 word values will be allocated either in @code{ax} or @code{dx}.
2351 For example on i386 the following implements @code{rdtsc}:
2354 unsigned long long rdtsc (void)
2356 unsigned long long tick;
2357 __asm__ __volatile__("rdtsc":"=A"(tick));
2362 This is not correct on x86_64 as it would allocate tick in either @code{ax}
2363 or @code{dx}. You have to use the following variant instead:
2366 unsigned long long rdtsc (void)
2368 unsigned int tickl, tickh;
2369 __asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh));
2370 return ((unsigned long long)tickh << 32)|tickl;
2376 Any 80387 floating-point (stack) register.
2379 Top of 80387 floating-point stack (@code{%st(0)}).
2382 Second from top of 80387 floating-point stack (@code{%st(1)}).
2391 First SSE register (@code{%xmm0}).
2395 Any SSE register, when SSE2 is enabled.
2398 Any SSE register, when SSE2 and inter-unit moves are enabled.
2401 Any MMX register, when inter-unit moves are enabled.
2405 Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
2408 Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
2411 Signed 8-bit integer constant.
2414 @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
2417 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
2420 Unsigned 8-bit integer constant (for @code{in} and @code{out}
2425 Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
2429 Standard 80387 floating point constant.
2432 Standard SSE floating point constant.
2435 32-bit signed integer constant, or a symbolic reference known
2436 to fit that range (for immediate operands in sign-extending x86-64
2440 32-bit unsigned integer constant, or a symbolic reference known
2441 to fit that range (for immediate operands in zero-extending x86-64
2446 @item Intel IA-64---@file{config/ia64/ia64.h}
2449 General register @code{r0} to @code{r3} for @code{addl} instruction
2455 Predicate register (@samp{c} as in ``conditional'')
2458 Application register residing in M-unit
2461 Application register residing in I-unit
2464 Floating-point register
2467 Memory operand. If used together with @samp{<} or @samp{>},
2468 the operand can have postincrement and postdecrement which
2469 require printing with @samp{%Pn} on IA-64.
2472 Floating-point constant 0.0 or 1.0
2475 14-bit signed integer constant
2478 22-bit signed integer constant
2481 8-bit signed integer constant for logical instructions
2484 8-bit adjusted signed integer constant for compare pseudo-ops
2487 6-bit unsigned integer constant for shift counts
2490 9-bit signed integer constant for load and store postincrements
2496 0 or @minus{}1 for @code{dep} instruction
2499 Non-volatile memory for floating-point loads and stores
2502 Integer constant in the range 1 to 4 for @code{shladd} instruction
2505 Memory operand except postincrement and postdecrement. This is
2506 now roughly the same as @samp{m} when not used together with @samp{<}
2510 @item FRV---@file{config/frv/frv.h}
2513 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2516 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2519 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
2520 @code{icc0} to @code{icc3}).
2523 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2526 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2527 Odd registers are excluded not in the class but through the use of a machine
2528 mode larger than 4 bytes.
2531 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2534 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2535 Odd registers are excluded not in the class but through the use of a machine
2536 mode larger than 4 bytes.
2539 Register in the class @code{LR_REG} (the @code{lr} register).
2542 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2543 Register numbers not divisible by 4 are excluded not in the class but through
2544 the use of a machine mode larger than 8 bytes.
2547 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2550 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2553 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2556 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2559 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2560 Register numbers not divisible by 4 are excluded not in the class but through
2561 the use of a machine mode larger than 8 bytes.
2564 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2567 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2570 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2573 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2576 Floating point constant zero
2579 6-bit signed integer constant
2582 10-bit signed integer constant
2585 16-bit signed integer constant
2588 16-bit unsigned integer constant
2591 12-bit signed integer constant that is negative---i.e.@: in the
2592 range of @minus{}2048 to @minus{}1
2598 12-bit signed integer constant that is greater than zero---i.e.@: in the
2603 @item Blackfin family---@file{config/bfin/constraints.md}
2612 A call clobbered P register.
2615 A single register. If @var{n} is in the range 0 to 7, the corresponding D
2616 register. If it is @code{A}, then the register P0.
2619 Even-numbered D register
2622 Odd-numbered D register
2625 Accumulator register.
2628 Even-numbered accumulator register.
2631 Odd-numbered accumulator register.
2643 Registers used for circular buffering, i.e. I, B, or L registers.
2658 Any D, P, B, M, I or L register.
2661 Additional registers typically used only in prologues and epilogues: RETS,
2662 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
2665 Any register except accumulators or CC.
2668 Signed 16 bit integer (in the range @minus{}32768 to 32767)
2671 Unsigned 16 bit integer (in the range 0 to 65535)
2674 Signed 7 bit integer (in the range @minus{}64 to 63)
2677 Unsigned 7 bit integer (in the range 0 to 127)
2680 Unsigned 5 bit integer (in the range 0 to 31)
2683 Signed 4 bit integer (in the range @minus{}8 to 7)
2686 Signed 3 bit integer (in the range @minus{}3 to 4)
2689 Unsigned 3 bit integer (in the range 0 to 7)
2692 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2695 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2696 use with either accumulator.
2699 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2700 use only with accumulator A1.
2709 An integer constant with exactly a single bit set.
2712 An integer constant with all bits set except exactly one.
2720 @item M32C---@file{config/m32c/m32c.c}
2725 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2728 Any control register, when they're 16 bits wide (nothing if control
2729 registers are 24 bits wide)
2732 Any control register, when they're 24 bits wide.
2741 $r0 or $r2, or $r2r0 for 32 bit values.
2744 $r1 or $r3, or $r3r1 for 32 bit values.
2747 A register that can hold a 64 bit value.
2750 $r0 or $r1 (registers with addressable high/low bytes)
2759 Address registers when they're 16 bits wide.
2762 Address registers when they're 24 bits wide.
2765 Registers that can hold QI values.
2768 Registers that can be used with displacements ($a0, $a1, $sb).
2771 Registers that can hold 32 bit values.
2774 Registers that can hold 16 bit values.
2777 Registers chat can hold 16 bit values, including all control
2781 $r0 through R1, plus $a0 and $a1.
2787 The memory-based pseudo-registers $mem0 through $mem15.
2790 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2791 bit registers for m32cm, m32c).
2794 Matches multiple registers in a PARALLEL to form a larger register.
2795 Used to match function return values.
2801 @minus{}128 @dots{} 127
2804 @minus{}32768 @dots{} 32767
2810 @minus{}8 @dots{} @minus{}1 or 1 @dots{} 8
2813 @minus{}16 @dots{} @minus{}1 or 1 @dots{} 16
2816 @minus{}32 @dots{} @minus{}1 or 1 @dots{} 32
2819 @minus{}65536 @dots{} @minus{}1
2822 An 8 bit value with exactly one bit set.
2825 A 16 bit value with exactly one bit set.
2828 The common src/dest memory addressing modes.
2831 Memory addressed using $a0 or $a1.
2834 Memory addressed with immediate addresses.
2837 Memory addressed using the stack pointer ($sp).
2840 Memory addressed using the frame base register ($fb).
2843 Memory addressed using the small base register ($sb).
2849 @item MeP---@file{config/mep/constraints.md}
2859 Any control register.
2862 Either the $hi or the $lo register.
2865 Coprocessor registers that can be directly loaded ($c0-$c15).
2868 Coprocessor registers that can be moved to each other.
2871 Coprocessor registers that can be moved to core registers.
2883 Registers which can be used in $tp-relative addressing.
2889 The coprocessor registers.
2892 The coprocessor control registers.
2898 User-defined register set A.
2901 User-defined register set B.
2904 User-defined register set C.
2907 User-defined register set D.
2910 Offsets for $gp-rel addressing.
2913 Constants that can be used directly with boolean insns.
2916 Constants that can be moved directly to registers.
2919 Small constants that can be added to registers.
2925 Small constants that can be compared to registers.
2928 Constants that can be loaded into the top half of registers.
2931 Signed 8-bit immediates.
2934 Symbols encoded for $tp-rel or $gp-rel addressing.
2937 Non-constant addresses for loading/saving coprocessor registers.
2940 The top half of a symbol's value.
2943 A register indirect address without offset.
2946 Symbolic references to the control bus.
2950 @item MicroBlaze---@file{config/microblaze/constraints.md}
2953 A general register (@code{r0} to @code{r31}).
2956 A status register (@code{rmsr}, @code{$fcc1} to @code{$fcc7}).
2960 @item MIPS---@file{config/mips/constraints.md}
2963 An address register. This is equivalent to @code{r} unless
2964 generating MIPS16 code.
2967 A floating-point register (if available).
2970 Formerly the @code{hi} register. This constraint is no longer supported.
2973 The @code{lo} register. Use this register to store values that are
2974 no bigger than a word.
2977 The concatenated @code{hi} and @code{lo} registers. Use this register
2978 to store doubleword values.
2981 A register suitable for use in an indirect jump. This will always be
2982 @code{$25} for @option{-mabicalls}.
2985 Register @code{$3}. Do not use this constraint in new code;
2986 it is retained only for compatibility with glibc.
2989 Equivalent to @code{r}; retained for backwards compatibility.
2992 A floating-point condition code register.
2995 A signed 16-bit constant (for arithmetic instructions).
3001 An unsigned 16-bit constant (for logic instructions).
3004 A signed 32-bit constant in which the lower 16 bits are zero.
3005 Such constants can be loaded using @code{lui}.
3008 A constant that cannot be loaded using @code{lui}, @code{addiu}
3012 A constant in the range @minus{}65535 to @minus{}1 (inclusive).
3015 A signed 15-bit constant.
3018 A constant in the range 1 to 65535 (inclusive).
3021 Floating-point zero.
3024 An address that can be used in a non-macro load or store.
3027 When compiling microMIPS code, this constraint matches a memory operand
3028 whose address is formed from a base register and a 12-bit offset. These
3029 operands can be used for microMIPS instructions such as @code{ll} and
3030 @code{sc}. When not compiling for microMIPS code, @code{ZC} is
3031 equivalent to @code{R}.
3034 When compiling microMIPS code, this constraint matches an address operand
3035 that is formed from a base register and a 12-bit offset. These operands
3036 can be used for microMIPS instructions such as @code{prefetch}. When
3037 not compiling for microMIPS code, @code{ZD} is equivalent to @code{p}.
3040 @item Motorola 680x0---@file{config/m68k/constraints.md}
3049 68881 floating-point register, if available
3052 Integer in the range 1 to 8
3055 16-bit signed number
3058 Signed number whose magnitude is greater than 0x80
3061 Integer in the range @minus{}8 to @minus{}1
3064 Signed number whose magnitude is greater than 0x100
3067 Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
3070 16 (for rotate using swap)
3073 Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
3076 Numbers that mov3q can handle
3079 Floating point constant that is not a 68881 constant
3082 Operands that satisfy 'm' when -mpcrel is in effect
3085 Operands that satisfy 's' when -mpcrel is not in effect
3088 Address register indirect addressing mode
3091 Register offset addressing
3106 Range of signed numbers that don't fit in 16 bits
3109 Integers valid for mvq
3112 Integers valid for a moveq followed by a swap
3115 Integers valid for mvz
3118 Integers valid for mvs
3124 Non-register operands allowed in clr
3128 @item Moxie---@file{config/moxie/constraints.md}
3137 A register indirect memory operand
3140 A constant in the range of 0 to 255.
3143 A constant in the range of 0 to @minus{}255.
3147 @item MSP430--@file{config/msp430/constraints.md}
3160 Integer constant -1^20..1^19.
3163 Integer constant 1-4.
3166 Memory references which do not require an extended MOVX instruction.
3169 Memory reference, labels only.
3172 Memory reference, stack only.
3176 @item NDS32---@file{config/nds32/constraints.md}
3179 LOW register class $r0 to $r7 constraint for V3/V3M ISA.
3181 LOW register class $r0 to $r7.
3183 MIDDLE register class $r0 to $r11, $r16 to $r19.
3185 HIGH register class $r12 to $r14, $r20 to $r31.
3187 Temporary assist register $ta (i.e.@: $r15).
3191 Unsigned immediate 3-bit value.
3193 Negative immediate 3-bit value in the range of @minus{}7--0.
3195 Unsigned immediate 4-bit value.
3197 Signed immediate 5-bit value.
3199 Unsigned immediate 5-bit value.
3201 Negative immediate 5-bit value in the range of @minus{}31--0.
3203 Unsigned immediate 5-bit value for movpi45 instruction with range 16--47.
3205 Unsigned immediate 6-bit value constraint for addri36.sp instruction.
3207 Unsigned immediate 8-bit value.
3209 Unsigned immediate 9-bit value.
3211 Signed immediate 10-bit value.
3213 Signed immediate 11-bit value.
3215 Signed immediate 15-bit value.
3217 Unsigned immediate 15-bit value.
3219 A constant which is not in the range of imm15u but ok for bclr instruction.
3221 A constant which is not in the range of imm15u but ok for bset instruction.
3223 A constant which is not in the range of imm15u but ok for btgl instruction.
3225 A constant whose compliment value is in the range of imm15u
3226 and ok for bitci instruction.
3228 Signed immediate 16-bit value.
3230 Signed immediate 17-bit value.
3232 Signed immediate 19-bit value.
3234 Signed immediate 20-bit value.
3236 The immediate value that can be simply set high 20-bit.
3238 The immediate value 0xff.
3240 The immediate value 0xffff.
3242 The immediate value 0x01.
3244 The immediate value 0x7ff.
3246 The immediate value with power of 2.
3248 The immediate value with power of 2 minus 1.
3250 Memory constraint for 333 format.
3252 Memory constraint for 45 format.
3254 Memory constraint for 37 format.
3257 @item Nios II family---@file{config/nios2/constraints.md}
3261 Integer that is valid as an immediate operand in an
3262 instruction taking a signed 16-bit number. Range
3263 @minus{}32768 to 32767.
3266 Integer that is valid as an immediate operand in an
3267 instruction taking an unsigned 16-bit number. Range
3271 Integer that is valid as an immediate operand in an
3272 instruction taking only the upper 16-bits of a
3273 32-bit number. Range 32-bit numbers with the lower
3277 Integer that is valid as an immediate operand for a
3278 shift instruction. Range 0 to 31.
3281 Integer that is valid as an immediate operand for
3282 only the value 0. Can be used in conjunction with
3283 the format modifier @code{z} to use @code{r0}
3284 instead of @code{0} in the assembly output.
3287 Integer that is valid as an immediate operand for
3288 a custom instruction opcode. Range 0 to 255.
3291 Matches immediates which are addresses in the small
3292 data section and therefore can be added to @code{gp}
3293 as a 16-bit immediate to re-create their 32-bit value.
3297 A @code{const} wrapped @code{UNSPEC} expression,
3298 representing a supported PIC or TLS relocation.
3303 @item PDP-11---@file{config/pdp11/constraints.md}
3306 Floating point registers AC0 through AC3. These can be loaded from/to
3307 memory with a single instruction.
3310 Odd numbered general registers (R1, R3, R5). These are used for
3311 16-bit multiply operations.
3314 Any of the floating point registers (AC0 through AC5).
3317 Floating point constant 0.
3320 An integer constant that fits in 16 bits.
3323 An integer constant whose low order 16 bits are zero.
3326 An integer constant that does not meet the constraints for codes
3327 @samp{I} or @samp{J}.
3330 The integer constant 1.
3333 The integer constant @minus{}1.
3336 The integer constant 0.
3339 Integer constants @minus{}4 through @minus{}1 and 1 through 4; shifts by these
3340 amounts are handled as multiple single-bit shifts rather than a single
3341 variable-length shift.
3344 A memory reference which requires an additional word (address or
3345 offset) after the opcode.
3348 A memory reference that is encoded within the opcode.
3352 @item RL78---@file{config/rl78/constraints.md}
3356 An integer constant in the range 1 @dots{} 7.
3358 An integer constant in the range 0 @dots{} 255.
3360 An integer constant in the range @minus{}255 @dots{} 0
3362 The integer constant 1.
3364 The integer constant -1.
3366 The integer constant 0.
3368 The integer constant 2.
3370 The integer constant -2.
3372 An integer constant in the range 1 @dots{} 15.
3374 The built-in compare types--eq, ne, gtu, ltu, geu, and leu.
3376 The synthetic compare types--gt, lt, ge, and le.
3378 A memory reference with an absolute address.
3380 A memory reference using @code{BC} as a base register, with an optional offset.
3382 A memory reference using @code{AX}, @code{BC}, @code{DE}, or @code{HL} for the address, for calls.
3384 A memory reference using any 16-bit register pair for the address, for calls.
3386 A memory reference using @code{DE} as a base register, with an optional offset.
3388 A memory reference using @code{DE} as a base register, without any offset.
3390 Any memory reference to an address in the far address space.
3392 A memory reference using @code{HL} as a base register, with an optional one-byte offset.
3394 A memory reference using @code{HL} as a base register, with @code{B} or @code{C} as the index register.
3396 A memory reference using @code{HL} as a base register, without any offset.
3398 A memory reference using @code{SP} as a base register, with an optional one-byte offset.
3400 Any memory reference to an address in the near address space.
3402 The @code{AX} register.
3404 The @code{BC} register.
3406 The @code{DE} register.
3408 @code{A} through @code{L} registers.
3410 The @code{SP} register.
3412 The @code{HL} register.
3414 The 16-bit @code{R8} register.
3416 The 16-bit @code{R10} register.
3418 The registers reserved for interrupts (@code{R24} to @code{R31}).
3420 The @code{A} register.
3422 The @code{B} register.
3424 The @code{C} register.
3426 The @code{D} register.
3428 The @code{E} register.
3430 The @code{H} register.
3432 The @code{L} register.
3434 The virtual registers.
3436 The @code{PSW} register.
3438 The @code{X} register.
3442 @item RX---@file{config/rx/constraints.md}
3445 An address which does not involve register indirect addressing or
3446 pre/post increment/decrement addressing.
3452 A constant in the range @minus{}256 to 255, inclusive.
3455 A constant in the range @minus{}128 to 127, inclusive.
3458 A constant in the range @minus{}32768 to 32767, inclusive.
3461 A constant in the range @minus{}8388608 to 8388607, inclusive.
3464 A constant in the range 0 to 15, inclusive.
3469 @item SPARC---@file{config/sparc/sparc.h}
3472 Floating-point register on the SPARC-V8 architecture and
3473 lower floating-point register on the SPARC-V9 architecture.
3476 Floating-point register. It is equivalent to @samp{f} on the
3477 SPARC-V8 architecture and contains both lower and upper
3478 floating-point registers on the SPARC-V9 architecture.
3481 Floating-point condition code register.
3484 Lower floating-point register. It is only valid on the SPARC-V9
3485 architecture when the Visual Instruction Set is available.
3488 Floating-point register. It is only valid on the SPARC-V9 architecture
3489 when the Visual Instruction Set is available.
3492 64-bit global or out register for the SPARC-V8+ architecture.
3495 The constant all-ones, for floating-point.
3498 Signed 5-bit constant
3504 Signed 13-bit constant
3510 32-bit constant with the low 12 bits clear (a constant that can be
3511 loaded with the @code{sethi} instruction)
3514 A constant in the range supported by @code{movcc} instructions (11-bit
3518 A constant in the range supported by @code{movrcc} instructions (10-bit
3522 Same as @samp{K}, except that it verifies that bits that are not in the
3523 lower 32-bit range are all zero. Must be used instead of @samp{K} for
3524 modes wider than @code{SImode}
3533 Signed 13-bit constant, sign-extended to 32 or 64 bits
3539 Floating-point constant whose integral representation can
3540 be moved into an integer register using a single sethi
3544 Floating-point constant whose integral representation can
3545 be moved into an integer register using a single mov
3549 Floating-point constant whose integral representation can
3550 be moved into an integer register using a high/lo_sum
3551 instruction sequence
3554 Memory address aligned to an 8-byte boundary
3560 Memory address for @samp{e} constraint registers
3563 Memory address with only a base register
3570 @item SPU---@file{config/spu/spu.h}
3573 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
3576 An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
3579 An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
3582 An immediate which can be loaded with @code{fsmbi}.
3585 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
3588 An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
3591 An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
3594 An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
3597 A constant in the range [@minus{}64, 63] for shift/rotate instructions.
3600 An unsigned 7-bit constant for conversion/nop/channel instructions.
3603 A signed 10-bit constant for most arithmetic instructions.
3606 A signed 16 bit immediate for @code{stop}.
3609 An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
3612 An unsigned 7-bit constant whose 3 least significant bits are 0.
3615 An unsigned 3-bit constant for 16-byte rotates and shifts
3618 Call operand, reg, for indirect calls
3621 Call operand, symbol, for relative calls.
3624 Call operand, const_int, for absolute calls.
3627 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
3630 An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
3633 An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
3636 An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
3640 @item S/390 and zSeries---@file{config/s390/s390.h}
3643 Address register (general purpose register except r0)
3646 Condition code register
3649 Data register (arbitrary general purpose register)
3652 Floating-point register
3655 Unsigned 8-bit constant (0--255)
3658 Unsigned 12-bit constant (0--4095)
3661 Signed 16-bit constant (@minus{}32768--32767)
3664 Value appropriate as displacement.
3667 for short displacement
3668 @item (@minus{}524288..524287)
3669 for long displacement
3673 Constant integer with a value of 0x7fffffff.
3676 Multiple letter constraint followed by 4 parameter letters.
3679 number of the part counting from most to least significant
3683 mode of the containing operand
3685 value of the other parts (F---all bits set)
3687 The constraint matches if the specified part of a constant
3688 has a value different from its other parts.
3691 Memory reference without index register and with short displacement.
3694 Memory reference with index register and short displacement.
3697 Memory reference without index register but with long displacement.
3700 Memory reference with index register and long displacement.
3703 Pointer with short displacement.
3706 Pointer with long displacement.
3709 Shift count operand.
3713 @item Score family---@file{config/score/score.h}
3716 Registers from r0 to r32.
3719 Registers from r0 to r16.
3722 r8---r11 or r22---r27 registers.
3743 cnt + lcb + scb register.
3746 cr0---cr15 register.
3758 cp1 + cp2 + cp3 registers.
3761 High 16-bit constant (32-bit constant with 16 LSBs zero).
3764 Unsigned 5 bit integer (in the range 0 to 31).
3767 Unsigned 16 bit integer (in the range 0 to 65535).
3770 Signed 16 bit integer (in the range @minus{}32768 to 32767).
3773 Unsigned 14 bit integer (in the range 0 to 16383).
3776 Signed 14 bit integer (in the range @minus{}8192 to 8191).
3782 @item Xstormy16---@file{config/stormy16/stormy16.h}
3797 Registers r0 through r7.
3800 Registers r0 and r1.
3806 Registers r8 and r9.
3809 A constant between 0 and 3 inclusive.
3812 A constant that has exactly one bit set.
3815 A constant that has exactly one bit clear.
3818 A constant between 0 and 255 inclusive.
3821 A constant between @minus{}255 and 0 inclusive.
3824 A constant between @minus{}3 and 0 inclusive.
3827 A constant between 1 and 4 inclusive.
3830 A constant between @minus{}4 and @minus{}1 inclusive.
3833 A memory reference that is a stack push.
3836 A memory reference that is a stack pop.
3839 A memory reference that refers to a constant address of known value.
3842 The register indicated by Rx (not implemented yet).
3845 A constant that is not between 2 and 15 inclusive.
3852 @item TI C6X family---@file{config/c6x/constraints.md}
3855 Register file A (A0--A31).
3858 Register file B (B0--B31).
3861 Predicate registers in register file A (A0--A2 on C64X and
3862 higher, A1 and A2 otherwise).
3865 Predicate registers in register file B (B0--B2).
3868 A call-used register in register file B (B0--B9, B16--B31).
3871 Register file A, excluding predicate registers (A3--A31,
3872 plus A0 if not C64X or higher).
3875 Register file B, excluding predicate registers (B3--B31).
3878 Integer constant in the range 0 @dots{} 15.
3881 Integer constant in the range 0 @dots{} 31.
3884 Integer constant in the range @minus{}31 @dots{} 0.
3887 Integer constant in the range @minus{}16 @dots{} 15.
3890 Integer constant that can be the operand of an ADDA or a SUBA insn.
3893 Integer constant in the range 0 @dots{} 65535.
3896 Integer constant in the range @minus{}32768 @dots{} 32767.
3899 Integer constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}.
3902 Integer constant that is a valid mask for the clr instruction.
3905 Integer constant that is a valid mask for the set instruction.
3908 Memory location with A base register.
3911 Memory location with B base register.
3915 On C64x+ targets, a GP-relative small data reference.
3918 Any kind of @code{SYMBOL_REF}, for use in a call address.
3921 Any kind of immediate operand, unless it matches the S0 constraint.
3924 Memory location with B base register, but not using a long offset.
3927 A memory operand with an address that can't be used in an unaligned access.
3931 Register B14 (aka DP).
3935 @item TILE-Gx---@file{config/tilegx/constraints.md}
3948 Each of these represents a register constraint for an individual
3949 register, from r0 to r10.
3952 Signed 8-bit integer constant.
3955 Signed 16-bit integer constant.
3958 Unsigned 16-bit integer constant.
3961 Integer constant that fits in one signed byte when incremented by one
3962 (@minus{}129 @dots{} 126).
3965 Memory operand. If used together with @samp{<} or @samp{>}, the
3966 operand can have postincrement which requires printing with @samp{%In}
3967 and @samp{%in} on TILE-Gx. For example:
3970 asm ("st_add %I0,%1,%i0" : "=m<>" (*mem) : "r" (val));
3974 A bit mask suitable for the BFINS instruction.
3977 Integer constant that is a byte tiled out eight times.
3980 The integer zero constant.
3983 Integer constant that is a sign-extended byte tiled out as four shorts.
3986 Integer constant that fits in one signed byte when incremented
3987 (@minus{}129 @dots{} 126), but excluding -1.
3990 Integer constant that has all 1 bits consecutive and starting at bit 0.
3993 A 16-bit fragment of a got, tls, or pc-relative reference.
3996 Memory operand except postincrement. This is roughly the same as
3997 @samp{m} when not used together with @samp{<} or @samp{>}.
4000 An 8-element vector constant with identical elements.
4003 A 4-element vector constant with identical elements.
4006 The integer constant 0xffffffff.
4009 The integer constant 0xffffffff00000000.
4013 @item TILEPro---@file{config/tilepro/constraints.md}
4026 Each of these represents a register constraint for an individual
4027 register, from r0 to r10.
4030 Signed 8-bit integer constant.
4033 Signed 16-bit integer constant.
4036 Nonzero integer constant with low 16 bits zero.
4039 Integer constant that fits in one signed byte when incremented by one
4040 (@minus{}129 @dots{} 126).
4043 Memory operand. If used together with @samp{<} or @samp{>}, the
4044 operand can have postincrement which requires printing with @samp{%In}
4045 and @samp{%in} on TILEPro. For example:
4048 asm ("swadd %I0,%1,%i0" : "=m<>" (mem) : "r" (val));
4052 A bit mask suitable for the MM instruction.
4055 Integer constant that is a byte tiled out four times.
4058 The integer zero constant.
4061 Integer constant that is a sign-extended byte tiled out as two shorts.
4064 Integer constant that fits in one signed byte when incremented
4065 (@minus{}129 @dots{} 126), but excluding -1.
4068 A symbolic operand, or a 16-bit fragment of a got, tls, or pc-relative
4072 Memory operand except postincrement. This is roughly the same as
4073 @samp{m} when not used together with @samp{<} or @samp{>}.
4076 A 4-element vector constant with identical elements.
4079 A 2-element vector constant with identical elements.
4083 @item Xtensa---@file{config/xtensa/constraints.md}
4086 General-purpose 32-bit register
4089 One-bit boolean register
4092 MAC16 40-bit accumulator register
4095 Signed 12-bit integer constant, for use in MOVI instructions
4098 Signed 8-bit integer constant, for use in ADDI instructions
4101 Integer constant valid for BccI instructions
4104 Unsigned constant valid for BccUI instructions
4111 @node Disable Insn Alternatives
4112 @subsection Disable insn alternatives using the @code{enabled} attribute
4115 The @code{enabled} insn attribute may be used to disable insn
4116 alternatives that are not available for the current subtarget.
4117 This is useful when adding new instructions to an existing pattern
4118 which are only available for certain cpu architecture levels as
4119 specified with the @code{-march=} option.
4121 If an insn alternative is disabled, then it will never be used. The
4122 compiler treats the constraints for the disabled alternative as
4125 In order to make use of the @code{enabled} attribute a back end has to add
4126 in the machine description files:
4130 A definition of the @code{enabled} insn attribute. The attribute is
4131 defined as usual using the @code{define_attr} command. This
4132 definition should be based on other insn attributes and/or target flags.
4133 The attribute must be a static property of the subtarget; that is, it
4134 must not depend on the current operands or any other dynamic context
4135 (for example, the location of the insn within the body of a loop).
4137 The @code{enabled} attribute is a numeric attribute and should evaluate to
4138 @code{(const_int 1)} for an enabled alternative and to
4139 @code{(const_int 0)} otherwise.
4141 A definition of another insn attribute used to describe for what
4142 reason an insn alternative might be available or
4143 not. E.g. @code{cpu_facility} as in the example below.
4145 An assignment for the second attribute to each insn definition
4146 combining instructions which are not all available under the same
4147 circumstances. (Note: It obviously only makes sense for definitions
4148 with more than one alternative. Otherwise the insn pattern should be
4149 disabled or enabled using the insn condition.)
4152 E.g. the following two patterns could easily be merged using the @code{enabled}
4157 (define_insn "*movdi_old"
4158 [(set (match_operand:DI 0 "register_operand" "=d")
4159 (match_operand:DI 1 "register_operand" " d"))]
4163 (define_insn "*movdi_new"
4164 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4165 (match_operand:DI 1 "register_operand" " d,d,f"))]
4178 (define_insn "*movdi_combined"
4179 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4180 (match_operand:DI 1 "register_operand" " d,d,f"))]
4186 [(set_attr "cpu_facility" "*,new,new")])
4190 with the @code{enabled} attribute defined like this:
4194 (define_attr "cpu_facility" "standard,new" (const_string "standard"))
4196 (define_attr "enabled" ""
4197 (cond [(eq_attr "cpu_facility" "standard") (const_int 1)
4198 (and (eq_attr "cpu_facility" "new")
4199 (ne (symbol_ref "TARGET_NEW") (const_int 0)))
4208 @node Define Constraints
4209 @subsection Defining Machine-Specific Constraints
4210 @cindex defining constraints
4211 @cindex constraints, defining
4213 Machine-specific constraints fall into two categories: register and
4214 non-register constraints. Within the latter category, constraints
4215 which allow subsets of all possible memory or address operands should
4216 be specially marked, to give @code{reload} more information.
4218 Machine-specific constraints can be given names of arbitrary length,
4219 but they must be entirely composed of letters, digits, underscores
4220 (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
4221 must begin with a letter or underscore.
4223 In order to avoid ambiguity in operand constraint strings, no
4224 constraint can have a name that begins with any other constraint's
4225 name. For example, if @code{x} is defined as a constraint name,
4226 @code{xy} may not be, and vice versa. As a consequence of this rule,
4227 no constraint may begin with one of the generic constraint letters:
4228 @samp{E F V X g i m n o p r s}.
4230 Register constraints correspond directly to register classes.
4231 @xref{Register Classes}. There is thus not much flexibility in their
4234 @deffn {MD Expression} define_register_constraint name regclass docstring
4235 All three arguments are string constants.
4236 @var{name} is the name of the constraint, as it will appear in
4237 @code{match_operand} expressions. If @var{name} is a multi-letter
4238 constraint its length shall be the same for all constraints starting
4239 with the same letter. @var{regclass} can be either the
4240 name of the corresponding register class (@pxref{Register Classes}),
4241 or a C expression which evaluates to the appropriate register class.
4242 If it is an expression, it must have no side effects, and it cannot
4243 look at the operand. The usual use of expressions is to map some
4244 register constraints to @code{NO_REGS} when the register class
4245 is not available on a given subarchitecture.
4247 @var{docstring} is a sentence documenting the meaning of the
4248 constraint. Docstrings are explained further below.
4251 Non-register constraints are more like predicates: the constraint
4252 definition gives a Boolean expression which indicates whether the
4255 @deffn {MD Expression} define_constraint name docstring exp
4256 The @var{name} and @var{docstring} arguments are the same as for
4257 @code{define_register_constraint}, but note that the docstring comes
4258 immediately after the name for these expressions. @var{exp} is an RTL
4259 expression, obeying the same rules as the RTL expressions in predicate
4260 definitions. @xref{Defining Predicates}, for details. If it
4261 evaluates true, the constraint matches; if it evaluates false, it
4262 doesn't. Constraint expressions should indicate which RTL codes they
4263 might match, just like predicate expressions.
4265 @code{match_test} C expressions have access to the
4266 following variables:
4270 The RTL object defining the operand.
4272 The machine mode of @var{op}.
4274 @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
4276 @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer
4277 @code{const_double}.
4279 @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer
4280 @code{const_double}.
4282 @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point
4283 @code{const_double}.
4286 The @var{*val} variables should only be used once another piece of the
4287 expression has verified that @var{op} is the appropriate kind of RTL
4291 Most non-register constraints should be defined with
4292 @code{define_constraint}. The remaining two definition expressions
4293 are only appropriate for constraints that should be handled specially
4294 by @code{reload} if they fail to match.
4296 @deffn {MD Expression} define_memory_constraint name docstring exp
4297 Use this expression for constraints that match a subset of all memory
4298 operands: that is, @code{reload} can make them match by converting the
4299 operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a
4300 base register (from the register class specified by
4301 @code{BASE_REG_CLASS}, @pxref{Register Classes}).
4303 For example, on the S/390, some instructions do not accept arbitrary
4304 memory references, but only those that do not make use of an index
4305 register. The constraint letter @samp{Q} is defined to represent a
4306 memory address of this type. If @samp{Q} is defined with
4307 @code{define_memory_constraint}, a @samp{Q} constraint can handle any
4308 memory operand, because @code{reload} knows it can simply copy the
4309 memory address into a base register if required. This is analogous to
4310 the way an @samp{o} constraint can handle any memory operand.
4312 The syntax and semantics are otherwise identical to
4313 @code{define_constraint}.
4316 @deffn {MD Expression} define_address_constraint name docstring exp
4317 Use this expression for constraints that match a subset of all address
4318 operands: that is, @code{reload} can make the constraint match by
4319 converting the operand to the form @samp{@w{(reg @var{X})}}, again
4320 with @var{X} a base register.
4322 Constraints defined with @code{define_address_constraint} can only be
4323 used with the @code{address_operand} predicate, or machine-specific
4324 predicates that work the same way. They are treated analogously to
4325 the generic @samp{p} constraint.
4327 The syntax and semantics are otherwise identical to
4328 @code{define_constraint}.
4331 For historical reasons, names beginning with the letters @samp{G H}
4332 are reserved for constraints that match only @code{const_double}s, and
4333 names beginning with the letters @samp{I J K L M N O P} are reserved
4334 for constraints that match only @code{const_int}s. This may change in
4335 the future. For the time being, constraints with these names must be
4336 written in a stylized form, so that @code{genpreds} can tell you did
4341 (define_constraint "[@var{GHIJKLMNOP}]@dots{}"
4343 (and (match_code "const_int") ; @r{@code{const_double} for G/H}
4344 @var{condition}@dots{})) ; @r{usually a @code{match_test}}
4347 @c the semicolons line up in the formatted manual
4349 It is fine to use names beginning with other letters for constraints
4350 that match @code{const_double}s or @code{const_int}s.
4352 Each docstring in a constraint definition should be one or more complete
4353 sentences, marked up in Texinfo format. @emph{They are currently unused.}
4354 In the future they will be copied into the GCC manual, in @ref{Machine
4355 Constraints}, replacing the hand-maintained tables currently found in
4356 that section. Also, in the future the compiler may use this to give
4357 more helpful diagnostics when poor choice of @code{asm} constraints
4358 causes a reload failure.
4360 If you put the pseudo-Texinfo directive @samp{@@internal} at the
4361 beginning of a docstring, then (in the future) it will appear only in
4362 the internals manual's version of the machine-specific constraint tables.
4363 Use this for constraints that should not appear in @code{asm} statements.
4365 @node C Constraint Interface
4366 @subsection Testing constraints from C
4367 @cindex testing constraints
4368 @cindex constraints, testing
4370 It is occasionally useful to test a constraint from C code rather than
4371 implicitly via the constraint string in a @code{match_operand}. The
4372 generated file @file{tm_p.h} declares a few interfaces for working
4373 with constraints. At present these are defined for all constraints
4374 except @code{g} (which is equivalent to @code{general_operand}).
4376 Some valid constraint names are not valid C identifiers, so there is a
4377 mangling scheme for referring to them from C@. Constraint names that
4378 do not contain angle brackets or underscores are left unchanged.
4379 Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and
4380 each @samp{>} with @samp{_g}. Here are some examples:
4382 @c the @c's prevent double blank lines in the printed manual.
4384 @multitable {Original} {Mangled}
4385 @item @strong{Original} @tab @strong{Mangled} @c
4386 @item @code{x} @tab @code{x} @c
4387 @item @code{P42x} @tab @code{P42x} @c
4388 @item @code{P4_x} @tab @code{P4__x} @c
4389 @item @code{P4>x} @tab @code{P4_gx} @c
4390 @item @code{P4>>} @tab @code{P4_g_g} @c
4391 @item @code{P4_g>} @tab @code{P4__g_g} @c
4395 Throughout this section, the variable @var{c} is either a constraint
4396 in the abstract sense, or a constant from @code{enum constraint_num};
4397 the variable @var{m} is a mangled constraint name (usually as part of
4398 a larger identifier).
4400 @deftp Enum constraint_num
4401 For each constraint except @code{g}, there is a corresponding
4402 enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the
4403 constraint. Functions that take an @code{enum constraint_num} as an
4404 argument expect one of these constants.
4407 @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp})
4408 For each non-register constraint @var{m} except @code{g}, there is
4409 one of these functions; it returns @code{true} if @var{exp} satisfies the
4410 constraint. These functions are only visible if @file{rtl.h} was included
4411 before @file{tm_p.h}.
4414 @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c})
4415 Like the @code{satisfies_constraint_@var{m}} functions, but the
4416 constraint to test is given as an argument, @var{c}. If @var{c}
4417 specifies a register constraint, this function will always return
4421 @deftypefun {enum reg_class} reg_class_for_constraint (enum constraint_num @var{c})
4422 Returns the register class associated with @var{c}. If @var{c} is not
4423 a register constraint, or those registers are not available for the
4424 currently selected subtarget, returns @code{NO_REGS}.
4427 Here is an example use of @code{satisfies_constraint_@var{m}}. In
4428 peephole optimizations (@pxref{Peephole Definitions}), operand
4429 constraint strings are ignored, so if there are relevant constraints,
4430 they must be tested in the C condition. In the example, the
4431 optimization is applied if operand 2 does @emph{not} satisfy the
4432 @samp{K} constraint. (This is a simplified version of a peephole
4433 definition from the i386 machine description.)
4437 [(match_scratch:SI 3 "r")
4438 (set (match_operand:SI 0 "register_operand" "")
4439 (mult:SI (match_operand:SI 1 "memory_operand" "")
4440 (match_operand:SI 2 "immediate_operand" "")))]
4442 "!satisfies_constraint_K (operands[2])"
4444 [(set (match_dup 3) (match_dup 1))
4445 (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))]
4450 @node Standard Names
4451 @section Standard Pattern Names For Generation
4452 @cindex standard pattern names
4453 @cindex pattern names
4454 @cindex names, pattern
4456 Here is a table of the instruction names that are meaningful in the RTL
4457 generation pass of the compiler. Giving one of these names to an
4458 instruction pattern tells the RTL generation pass that it can use the
4459 pattern to accomplish a certain task.
4462 @cindex @code{mov@var{m}} instruction pattern
4463 @item @samp{mov@var{m}}
4464 Here @var{m} stands for a two-letter machine mode name, in lowercase.
4465 This instruction pattern moves data with that machine mode from operand
4466 1 to operand 0. For example, @samp{movsi} moves full-word data.
4468 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
4469 own mode is wider than @var{m}, the effect of this instruction is
4470 to store the specified value in the part of the register that corresponds
4471 to mode @var{m}. Bits outside of @var{m}, but which are within the
4472 same target word as the @code{subreg} are undefined. Bits which are
4473 outside the target word are left unchanged.
4475 This class of patterns is special in several ways. First of all, each
4476 of these names up to and including full word size @emph{must} be defined,
4477 because there is no other way to copy a datum from one place to another.
4478 If there are patterns accepting operands in larger modes,
4479 @samp{mov@var{m}} must be defined for integer modes of those sizes.
4481 Second, these patterns are not used solely in the RTL generation pass.
4482 Even the reload pass can generate move insns to copy values from stack
4483 slots into temporary registers. When it does so, one of the operands is
4484 a hard register and the other is an operand that can need to be reloaded
4488 Therefore, when given such a pair of operands, the pattern must generate
4489 RTL which needs no reloading and needs no temporary registers---no
4490 registers other than the operands. For example, if you support the
4491 pattern with a @code{define_expand}, then in such a case the
4492 @code{define_expand} mustn't call @code{force_reg} or any other such
4493 function which might generate new pseudo registers.
4495 This requirement exists even for subword modes on a RISC machine where
4496 fetching those modes from memory normally requires several insns and
4497 some temporary registers.
4499 @findex change_address
4500 During reload a memory reference with an invalid address may be passed
4501 as an operand. Such an address will be replaced with a valid address
4502 later in the reload pass. In this case, nothing may be done with the
4503 address except to use it as it stands. If it is copied, it will not be
4504 replaced with a valid address. No attempt should be made to make such
4505 an address into a valid address and no routine (such as
4506 @code{change_address}) that will do so may be called. Note that
4507 @code{general_operand} will fail when applied to such an address.
4509 @findex reload_in_progress
4510 The global variable @code{reload_in_progress} (which must be explicitly
4511 declared if required) can be used to determine whether such special
4512 handling is required.
4514 The variety of operands that have reloads depends on the rest of the
4515 machine description, but typically on a RISC machine these can only be
4516 pseudo registers that did not get hard registers, while on other
4517 machines explicit memory references will get optional reloads.
4519 If a scratch register is required to move an object to or from memory,
4520 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
4522 If there are cases which need scratch registers during or after reload,
4523 you must provide an appropriate secondary_reload target hook.
4525 @findex can_create_pseudo_p
4526 The macro @code{can_create_pseudo_p} can be used to determine if it
4527 is unsafe to create new pseudo registers. If this variable is nonzero, then
4528 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
4530 The constraints on a @samp{mov@var{m}} must permit moving any hard
4531 register to any other hard register provided that
4532 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
4533 @code{TARGET_REGISTER_MOVE_COST} applied to their classes returns a value
4536 It is obligatory to support floating point @samp{mov@var{m}}
4537 instructions into and out of any registers that can hold fixed point
4538 values, because unions and structures (which have modes @code{SImode} or
4539 @code{DImode}) can be in those registers and they may have floating
4542 There may also be a need to support fixed point @samp{mov@var{m}}
4543 instructions in and out of floating point registers. Unfortunately, I
4544 have forgotten why this was so, and I don't know whether it is still
4545 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
4546 floating point registers, then the constraints of the fixed point
4547 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
4548 reload into a floating point register.
4550 @cindex @code{reload_in} instruction pattern
4551 @cindex @code{reload_out} instruction pattern
4552 @item @samp{reload_in@var{m}}
4553 @itemx @samp{reload_out@var{m}}
4554 These named patterns have been obsoleted by the target hook
4555 @code{secondary_reload}.
4557 Like @samp{mov@var{m}}, but used when a scratch register is required to
4558 move between operand 0 and operand 1. Operand 2 describes the scratch
4559 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
4560 macro in @pxref{Register Classes}.
4562 There are special restrictions on the form of the @code{match_operand}s
4563 used in these patterns. First, only the predicate for the reload
4564 operand is examined, i.e., @code{reload_in} examines operand 1, but not
4565 the predicates for operand 0 or 2. Second, there may be only one
4566 alternative in the constraints. Third, only a single register class
4567 letter may be used for the constraint; subsequent constraint letters
4568 are ignored. As a special exception, an empty constraint string
4569 matches the @code{ALL_REGS} register class. This may relieve ports
4570 of the burden of defining an @code{ALL_REGS} constraint letter just
4573 @cindex @code{movstrict@var{m}} instruction pattern
4574 @item @samp{movstrict@var{m}}
4575 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
4576 with mode @var{m} of a register whose natural mode is wider,
4577 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
4578 any of the register except the part which belongs to mode @var{m}.
4580 @cindex @code{movmisalign@var{m}} instruction pattern
4581 @item @samp{movmisalign@var{m}}
4582 This variant of a move pattern is designed to load or store a value
4583 from a memory address that is not naturally aligned for its mode.
4584 For a store, the memory will be in operand 0; for a load, the memory
4585 will be in operand 1. The other operand is guaranteed not to be a
4586 memory, so that it's easy to tell whether this is a load or store.
4588 This pattern is used by the autovectorizer, and when expanding a
4589 @code{MISALIGNED_INDIRECT_REF} expression.
4591 @cindex @code{load_multiple} instruction pattern
4592 @item @samp{load_multiple}
4593 Load several consecutive memory locations into consecutive registers.
4594 Operand 0 is the first of the consecutive registers, operand 1
4595 is the first memory location, and operand 2 is a constant: the
4596 number of consecutive registers.
4598 Define this only if the target machine really has such an instruction;
4599 do not define this if the most efficient way of loading consecutive
4600 registers from memory is to do them one at a time.
4602 On some machines, there are restrictions as to which consecutive
4603 registers can be stored into memory, such as particular starting or
4604 ending register numbers or only a range of valid counts. For those
4605 machines, use a @code{define_expand} (@pxref{Expander Definitions})
4606 and make the pattern fail if the restrictions are not met.
4608 Write the generated insn as a @code{parallel} with elements being a
4609 @code{set} of one register from the appropriate memory location (you may
4610 also need @code{use} or @code{clobber} elements). Use a
4611 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
4612 @file{rs6000.md} for examples of the use of this insn pattern.
4614 @cindex @samp{store_multiple} instruction pattern
4615 @item @samp{store_multiple}
4616 Similar to @samp{load_multiple}, but store several consecutive registers
4617 into consecutive memory locations. Operand 0 is the first of the
4618 consecutive memory locations, operand 1 is the first register, and
4619 operand 2 is a constant: the number of consecutive registers.
4621 @cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern
4622 @item @samp{vec_load_lanes@var{m}@var{n}}
4623 Perform an interleaved load of several vectors from memory operand 1
4624 into register operand 0. Both operands have mode @var{m}. The register
4625 operand is viewed as holding consecutive vectors of mode @var{n},
4626 while the memory operand is a flat array that contains the same number
4627 of elements. The operation is equivalent to:
4630 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4631 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4632 for (i = 0; i < c; i++)
4633 operand0[i][j] = operand1[j * c + i];
4636 For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values
4637 from memory into a register of mode @samp{TI}@. The register
4638 contains two consecutive vectors of mode @samp{V4HI}@.
4640 This pattern can only be used if:
4642 TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c})
4644 is true. GCC assumes that, if a target supports this kind of
4645 instruction for some mode @var{n}, it also supports unaligned
4646 loads for vectors of mode @var{n}.
4648 @cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern
4649 @item @samp{vec_store_lanes@var{m}@var{n}}
4650 Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory
4651 and register operands reversed. That is, the instruction is
4655 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4656 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4657 for (i = 0; i < c; i++)
4658 operand0[j * c + i] = operand1[i][j];
4661 for a memory operand 0 and register operand 1.
4663 @cindex @code{vec_set@var{m}} instruction pattern
4664 @item @samp{vec_set@var{m}}
4665 Set given field in the vector value. Operand 0 is the vector to modify,
4666 operand 1 is new value of field and operand 2 specify the field index.
4668 @cindex @code{vec_extract@var{m}} instruction pattern
4669 @item @samp{vec_extract@var{m}}
4670 Extract given field from the vector value. Operand 1 is the vector, operand 2
4671 specify field index and operand 0 place to store value into.
4673 @cindex @code{vec_init@var{m}} instruction pattern
4674 @item @samp{vec_init@var{m}}
4675 Initialize the vector to given values. Operand 0 is the vector to initialize
4676 and operand 1 is parallel containing values for individual fields.
4678 @cindex @code{vcond@var{m}@var{n}} instruction pattern
4679 @item @samp{vcond@var{m}@var{n}}
4680 Output a conditional vector move. Operand 0 is the destination to
4681 receive a combination of operand 1 and operand 2, which are of mode @var{m},
4682 dependent on the outcome of the predicate in operand 3 which is a
4683 vector comparison with operands of mode @var{n} in operands 4 and 5. The
4684 modes @var{m} and @var{n} should have the same size. Operand 0
4685 will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk}
4686 where @var{msk} is computed by element-wise evaluation of the vector
4687 comparison with a truth value of all-ones and a false value of all-zeros.
4689 @cindex @code{vec_perm@var{m}} instruction pattern
4690 @item @samp{vec_perm@var{m}}
4691 Output a (variable) vector permutation. Operand 0 is the destination
4692 to receive elements from operand 1 and operand 2, which are of mode
4693 @var{m}. Operand 3 is the @dfn{selector}. It is an integral mode
4694 vector of the same width and number of elements as mode @var{m}.
4696 The input elements are numbered from 0 in operand 1 through
4697 @math{2*@var{N}-1} in operand 2. The elements of the selector must
4698 be computed modulo @math{2*@var{N}}. Note that if
4699 @code{rtx_equal_p(operand1, operand2)}, this can be implemented
4700 with just operand 1 and selector elements modulo @var{N}.
4702 In order to make things easy for a number of targets, if there is no
4703 @samp{vec_perm} pattern for mode @var{m}, but there is for mode @var{q}
4704 where @var{q} is a vector of @code{QImode} of the same width as @var{m},
4705 the middle-end will lower the mode @var{m} @code{VEC_PERM_EXPR} to
4708 @cindex @code{vec_perm_const@var{m}} instruction pattern
4709 @item @samp{vec_perm_const@var{m}}
4710 Like @samp{vec_perm} except that the permutation is a compile-time
4711 constant. That is, operand 3, the @dfn{selector}, is a @code{CONST_VECTOR}.
4713 Some targets cannot perform a permutation with a variable selector,
4714 but can efficiently perform a constant permutation. Further, the
4715 target hook @code{vec_perm_ok} is queried to determine if the
4716 specific constant permutation is available efficiently; the named
4717 pattern is never expanded without @code{vec_perm_ok} returning true.
4719 There is no need for a target to supply both @samp{vec_perm@var{m}}
4720 and @samp{vec_perm_const@var{m}} if the former can trivially implement
4721 the operation with, say, the vector constant loaded into a register.
4723 @cindex @code{push@var{m}1} instruction pattern
4724 @item @samp{push@var{m}1}
4725 Output a push instruction. Operand 0 is value to push. Used only when
4726 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
4727 missing and in such case an @code{mov} expander is used instead, with a
4728 @code{MEM} expression forming the push operation. The @code{mov} expander
4729 method is deprecated.
4731 @cindex @code{add@var{m}3} instruction pattern
4732 @item @samp{add@var{m}3}
4733 Add operand 2 and operand 1, storing the result in operand 0. All operands
4734 must have mode @var{m}. This can be used even on two-address machines, by
4735 means of constraints requiring operands 1 and 0 to be the same location.
4737 @cindex @code{addptr@var{m}3} instruction pattern
4738 @item @samp{addptr@var{m}3}
4739 Like @code{add@var{m}3} but is guaranteed to only be used for address
4740 calculations. The expanded code is not allowed to clobber the
4741 condition code. It only needs to be defined if @code{add@var{m}3}
4742 sets the condition code. If adds used for address calculations and
4743 normal adds are not compatible it is required to expand a distinct
4744 pattern (e.g. using an unspec). The pattern is used by LRA to emit
4745 address calculations. @code{add@var{m}3} is used if
4746 @code{addptr@var{m}3} is not defined.
4748 @cindex @code{ssadd@var{m}3} instruction pattern
4749 @cindex @code{usadd@var{m}3} instruction pattern
4750 @cindex @code{sub@var{m}3} instruction pattern
4751 @cindex @code{sssub@var{m}3} instruction pattern
4752 @cindex @code{ussub@var{m}3} instruction pattern
4753 @cindex @code{mul@var{m}3} instruction pattern
4754 @cindex @code{ssmul@var{m}3} instruction pattern
4755 @cindex @code{usmul@var{m}3} instruction pattern
4756 @cindex @code{div@var{m}3} instruction pattern
4757 @cindex @code{ssdiv@var{m}3} instruction pattern
4758 @cindex @code{udiv@var{m}3} instruction pattern
4759 @cindex @code{usdiv@var{m}3} instruction pattern
4760 @cindex @code{mod@var{m}3} instruction pattern
4761 @cindex @code{umod@var{m}3} instruction pattern
4762 @cindex @code{umin@var{m}3} instruction pattern
4763 @cindex @code{umax@var{m}3} instruction pattern
4764 @cindex @code{and@var{m}3} instruction pattern
4765 @cindex @code{ior@var{m}3} instruction pattern
4766 @cindex @code{xor@var{m}3} instruction pattern
4767 @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
4768 @itemx @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
4769 @itemx @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
4770 @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
4771 @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
4772 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
4773 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
4774 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
4775 Similar, for other arithmetic operations.
4777 @cindex @code{fma@var{m}4} instruction pattern
4778 @item @samp{fma@var{m}4}
4779 Multiply operand 2 and operand 1, then add operand 3, storing the
4780 result in operand 0 without doing an intermediate rounding step. All
4781 operands must have mode @var{m}. This pattern is used to implement
4782 the @code{fma}, @code{fmaf}, and @code{fmal} builtin functions from
4783 the ISO C99 standard.
4785 @cindex @code{fms@var{m}4} instruction pattern
4786 @item @samp{fms@var{m}4}
4787 Like @code{fma@var{m}4}, except operand 3 subtracted from the
4788 product instead of added to the product. This is represented
4792 (fma:@var{m} @var{op1} @var{op2} (neg:@var{m} @var{op3}))
4795 @cindex @code{fnma@var{m}4} instruction pattern
4796 @item @samp{fnma@var{m}4}
4797 Like @code{fma@var{m}4} except that the intermediate product
4798 is negated before being added to operand 3. This is represented
4802 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} @var{op3})
4805 @cindex @code{fnms@var{m}4} instruction pattern
4806 @item @samp{fnms@var{m}4}
4807 Like @code{fms@var{m}4} except that the intermediate product
4808 is negated before subtracting operand 3. This is represented
4812 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} (neg:@var{m} @var{op3}))
4815 @cindex @code{min@var{m}3} instruction pattern
4816 @cindex @code{max@var{m}3} instruction pattern
4817 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
4818 Signed minimum and maximum operations. When used with floating point,
4819 if both operands are zeros, or if either operand is @code{NaN}, then
4820 it is unspecified which of the two operands is returned as the result.
4822 @cindex @code{reduc_smin_@var{m}} instruction pattern
4823 @cindex @code{reduc_smax_@var{m}} instruction pattern
4824 @item @samp{reduc_smin_@var{m}}, @samp{reduc_smax_@var{m}}
4825 Find the signed minimum/maximum of the elements of a vector. The vector is
4826 operand 1, and the scalar result is stored in the least significant bits of
4827 operand 0 (also a vector). The output and input vector should have the same
4830 @cindex @code{reduc_umin_@var{m}} instruction pattern
4831 @cindex @code{reduc_umax_@var{m}} instruction pattern
4832 @item @samp{reduc_umin_@var{m}}, @samp{reduc_umax_@var{m}}
4833 Find the unsigned minimum/maximum of the elements of a vector. The vector is
4834 operand 1, and the scalar result is stored in the least significant bits of
4835 operand 0 (also a vector). The output and input vector should have the same
4838 @cindex @code{reduc_splus_@var{m}} instruction pattern
4839 @item @samp{reduc_splus_@var{m}}
4840 Compute the sum of the signed elements of a vector. The vector is operand 1,
4841 and the scalar result is stored in the least significant bits of operand 0
4842 (also a vector). The output and input vector should have the same modes.
4844 @cindex @code{reduc_uplus_@var{m}} instruction pattern
4845 @item @samp{reduc_uplus_@var{m}}
4846 Compute the sum of the unsigned elements of a vector. The vector is operand 1,
4847 and the scalar result is stored in the least significant bits of operand 0
4848 (also a vector). The output and input vector should have the same modes.
4850 @cindex @code{sdot_prod@var{m}} instruction pattern
4851 @item @samp{sdot_prod@var{m}}
4852 @cindex @code{udot_prod@var{m}} instruction pattern
4853 @itemx @samp{udot_prod@var{m}}
4854 Compute the sum of the products of two signed/unsigned elements.
4855 Operand 1 and operand 2 are of the same mode. Their product, which is of a
4856 wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
4857 wider than the mode of the product. The result is placed in operand 0, which
4858 is of the same mode as operand 3.
4860 @cindex @code{ssad@var{m}} instruction pattern
4861 @item @samp{ssad@var{m}}
4862 @cindex @code{usad@var{m}} instruction pattern
4863 @item @samp{usad@var{m}}
4864 Compute the sum of absolute differences of two signed/unsigned elements.
4865 Operand 1 and operand 2 are of the same mode. Their absolute difference, which
4866 is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode
4867 equal or wider than the mode of the absolute difference. The result is placed
4868 in operand 0, which is of the same mode as operand 3.
4870 @cindex @code{ssum_widen@var{m3}} instruction pattern
4871 @item @samp{ssum_widen@var{m3}}
4872 @cindex @code{usum_widen@var{m3}} instruction pattern
4873 @itemx @samp{usum_widen@var{m3}}
4874 Operands 0 and 2 are of the same mode, which is wider than the mode of
4875 operand 1. Add operand 1 to operand 2 and place the widened result in
4876 operand 0. (This is used express accumulation of elements into an accumulator
4879 @cindex @code{vec_shl_@var{m}} instruction pattern
4880 @cindex @code{vec_shr_@var{m}} instruction pattern
4881 @item @samp{vec_shl_@var{m}}, @samp{vec_shr_@var{m}}
4882 Whole vector left/right shift in bits.
4883 Operand 1 is a vector to be shifted.
4884 Operand 2 is an integer shift amount in bits.
4885 Operand 0 is where the resulting shifted vector is stored.
4886 The output and input vectors should have the same modes.
4888 @cindex @code{vec_pack_trunc_@var{m}} instruction pattern
4889 @item @samp{vec_pack_trunc_@var{m}}
4890 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
4891 are vectors of the same mode having N integral or floating point elements
4892 of size S@. Operand 0 is the resulting vector in which 2*N elements of
4893 size N/2 are concatenated after narrowing them down using truncation.
4895 @cindex @code{vec_pack_ssat_@var{m}} instruction pattern
4896 @cindex @code{vec_pack_usat_@var{m}} instruction pattern
4897 @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}}
4898 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
4899 are vectors of the same mode having N integral elements of size S.
4900 Operand 0 is the resulting vector in which the elements of the two input
4901 vectors are concatenated after narrowing them down using signed/unsigned
4902 saturating arithmetic.
4904 @cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern
4905 @cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern
4906 @item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}}
4907 Narrow, convert to signed/unsigned integral type and merge the elements
4908 of two vectors. Operands 1 and 2 are vectors of the same mode having N
4909 floating point elements of size S@. Operand 0 is the resulting vector
4910 in which 2*N elements of size N/2 are concatenated.
4912 @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern
4913 @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern
4914 @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}}
4915 Extract and widen (promote) the high/low part of a vector of signed
4916 integral or floating point elements. The input vector (operand 1) has N
4917 elements of size S@. Widen (promote) the high/low elements of the vector
4918 using signed or floating point extension and place the resulting N/2
4919 values of size 2*S in the output vector (operand 0).
4921 @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern
4922 @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern
4923 @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}}
4924 Extract and widen (promote) the high/low part of a vector of unsigned
4925 integral elements. The input vector (operand 1) has N elements of size S.
4926 Widen (promote) the high/low elements of the vector using zero extension and
4927 place the resulting N/2 values of size 2*S in the output vector (operand 0).
4929 @cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern
4930 @cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern
4931 @cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern
4932 @cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern
4933 @item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}}
4934 @itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}}
4935 Extract, convert to floating point type and widen the high/low part of a
4936 vector of signed/unsigned integral elements. The input vector (operand 1)
4937 has N elements of size S@. Convert the high/low elements of the vector using
4938 floating point conversion and place the resulting N/2 values of size 2*S in
4939 the output vector (operand 0).
4941 @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern
4942 @cindex @code{vec_widen_umult_lo_@var{m}} instruction pattern
4943 @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern
4944 @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern
4945 @cindex @code{vec_widen_umult_even_@var{m}} instruction pattern
4946 @cindex @code{vec_widen_umult_odd_@var{m}} instruction pattern
4947 @cindex @code{vec_widen_smult_even_@var{m}} instruction pattern
4948 @cindex @code{vec_widen_smult_odd_@var{m}} instruction pattern
4949 @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}}
4950 @itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}}
4951 @itemx @samp{vec_widen_umult_even_@var{m}}, @samp{vec_widen_umult_odd_@var{m}}
4952 @itemx @samp{vec_widen_smult_even_@var{m}}, @samp{vec_widen_smult_odd_@var{m}}
4953 Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
4954 are vectors with N signed/unsigned elements of size S@. Multiply the high/low
4955 or even/odd elements of the two vectors, and put the N/2 products of size 2*S
4956 in the output vector (operand 0). A target shouldn't implement even/odd pattern
4957 pair if it is less efficient than lo/hi one.
4959 @cindex @code{vec_widen_ushiftl_hi_@var{m}} instruction pattern
4960 @cindex @code{vec_widen_ushiftl_lo_@var{m}} instruction pattern
4961 @cindex @code{vec_widen_sshiftl_hi_@var{m}} instruction pattern
4962 @cindex @code{vec_widen_sshiftl_lo_@var{m}} instruction pattern
4963 @item @samp{vec_widen_ushiftl_hi_@var{m}}, @samp{vec_widen_ushiftl_lo_@var{m}}
4964 @itemx @samp{vec_widen_sshiftl_hi_@var{m}}, @samp{vec_widen_sshiftl_lo_@var{m}}
4965 Signed/Unsigned widening shift left. The first input (operand 1) is a vector
4966 with N signed/unsigned elements of size S@. Operand 2 is a constant. Shift
4967 the high/low elements of operand 1, and put the N/2 results of size 2*S in the
4968 output vector (operand 0).
4970 @cindex @code{mulhisi3} instruction pattern
4971 @item @samp{mulhisi3}
4972 Multiply operands 1 and 2, which have mode @code{HImode}, and store
4973 a @code{SImode} product in operand 0.
4975 @cindex @code{mulqihi3} instruction pattern
4976 @cindex @code{mulsidi3} instruction pattern
4977 @item @samp{mulqihi3}, @samp{mulsidi3}
4978 Similar widening-multiplication instructions of other widths.
4980 @cindex @code{umulqihi3} instruction pattern
4981 @cindex @code{umulhisi3} instruction pattern
4982 @cindex @code{umulsidi3} instruction pattern
4983 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
4984 Similar widening-multiplication instructions that do unsigned
4987 @cindex @code{usmulqihi3} instruction pattern
4988 @cindex @code{usmulhisi3} instruction pattern
4989 @cindex @code{usmulsidi3} instruction pattern
4990 @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3}
4991 Similar widening-multiplication instructions that interpret the first
4992 operand as unsigned and the second operand as signed, then do a signed
4995 @cindex @code{smul@var{m}3_highpart} instruction pattern
4996 @item @samp{smul@var{m}3_highpart}
4997 Perform a signed multiplication of operands 1 and 2, which have mode
4998 @var{m}, and store the most significant half of the product in operand 0.
4999 The least significant half of the product is discarded.
5001 @cindex @code{umul@var{m}3_highpart} instruction pattern
5002 @item @samp{umul@var{m}3_highpart}
5003 Similar, but the multiplication is unsigned.
5005 @cindex @code{madd@var{m}@var{n}4} instruction pattern
5006 @item @samp{madd@var{m}@var{n}4}
5007 Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
5008 operand 3, and store the result in operand 0. Operands 1 and 2
5009 have mode @var{m} and operands 0 and 3 have mode @var{n}.
5010 Both modes must be integer or fixed-point modes and @var{n} must be twice
5011 the size of @var{m}.
5013 In other words, @code{madd@var{m}@var{n}4} is like
5014 @code{mul@var{m}@var{n}3} except that it also adds operand 3.
5016 These instructions are not allowed to @code{FAIL}.
5018 @cindex @code{umadd@var{m}@var{n}4} instruction pattern
5019 @item @samp{umadd@var{m}@var{n}4}
5020 Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
5021 operands instead of sign-extending them.
5023 @cindex @code{ssmadd@var{m}@var{n}4} instruction pattern
5024 @item @samp{ssmadd@var{m}@var{n}4}
5025 Like @code{madd@var{m}@var{n}4}, but all involved operations must be
5028 @cindex @code{usmadd@var{m}@var{n}4} instruction pattern
5029 @item @samp{usmadd@var{m}@var{n}4}
5030 Like @code{umadd@var{m}@var{n}4}, but all involved operations must be
5031 unsigned-saturating.
5033 @cindex @code{msub@var{m}@var{n}4} instruction pattern
5034 @item @samp{msub@var{m}@var{n}4}
5035 Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the
5036 result from operand 3, and store the result in operand 0. Operands 1 and 2
5037 have mode @var{m} and operands 0 and 3 have mode @var{n}.
5038 Both modes must be integer or fixed-point modes and @var{n} must be twice
5039 the size of @var{m}.
5041 In other words, @code{msub@var{m}@var{n}4} is like
5042 @code{mul@var{m}@var{n}3} except that it also subtracts the result
5045 These instructions are not allowed to @code{FAIL}.
5047 @cindex @code{umsub@var{m}@var{n}4} instruction pattern
5048 @item @samp{umsub@var{m}@var{n}4}
5049 Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication
5050 operands instead of sign-extending them.
5052 @cindex @code{ssmsub@var{m}@var{n}4} instruction pattern
5053 @item @samp{ssmsub@var{m}@var{n}4}
5054 Like @code{msub@var{m}@var{n}4}, but all involved operations must be
5057 @cindex @code{usmsub@var{m}@var{n}4} instruction pattern
5058 @item @samp{usmsub@var{m}@var{n}4}
5059 Like @code{umsub@var{m}@var{n}4}, but all involved operations must be
5060 unsigned-saturating.
5062 @cindex @code{divmod@var{m}4} instruction pattern
5063 @item @samp{divmod@var{m}4}
5064 Signed division that produces both a quotient and a remainder.
5065 Operand 1 is divided by operand 2 to produce a quotient stored
5066 in operand 0 and a remainder stored in operand 3.
5068 For machines with an instruction that produces both a quotient and a
5069 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
5070 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
5071 allows optimization in the relatively common case when both the quotient
5072 and remainder are computed.
5074 If an instruction that just produces a quotient or just a remainder
5075 exists and is more efficient than the instruction that produces both,
5076 write the output routine of @samp{divmod@var{m}4} to call
5077 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
5078 quotient or remainder and generate the appropriate instruction.
5080 @cindex @code{udivmod@var{m}4} instruction pattern
5081 @item @samp{udivmod@var{m}4}
5082 Similar, but does unsigned division.
5084 @anchor{shift patterns}
5085 @cindex @code{ashl@var{m}3} instruction pattern
5086 @cindex @code{ssashl@var{m}3} instruction pattern
5087 @cindex @code{usashl@var{m}3} instruction pattern
5088 @item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3}
5089 Arithmetic-shift operand 1 left by a number of bits specified by operand
5090 2, and store the result in operand 0. Here @var{m} is the mode of
5091 operand 0 and operand 1; operand 2's mode is specified by the
5092 instruction pattern, and the compiler will convert the operand to that
5093 mode before generating the instruction. The meaning of out-of-range shift
5094 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
5095 @xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type.
5097 @cindex @code{ashr@var{m}3} instruction pattern
5098 @cindex @code{lshr@var{m}3} instruction pattern
5099 @cindex @code{rotl@var{m}3} instruction pattern
5100 @cindex @code{rotr@var{m}3} instruction pattern
5101 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
5102 Other shift and rotate instructions, analogous to the
5103 @code{ashl@var{m}3} instructions. Operand 2 is always a scalar type.
5105 @cindex @code{vashl@var{m}3} instruction pattern
5106 @cindex @code{vashr@var{m}3} instruction pattern
5107 @cindex @code{vlshr@var{m}3} instruction pattern
5108 @cindex @code{vrotl@var{m}3} instruction pattern
5109 @cindex @code{vrotr@var{m}3} instruction pattern
5110 @item @samp{vashl@var{m}3}, @samp{vashr@var{m}3}, @samp{vlshr@var{m}3}, @samp{vrotl@var{m}3}, @samp{vrotr@var{m}3}
5111 Vector shift and rotate instructions that take vectors as operand 2
5112 instead of a scalar type.
5114 @cindex @code{bswap@var{m}2} instruction pattern
5115 @item @samp{bswap@var{m}2}
5116 Reverse the order of bytes of operand 1 and store the result in operand 0.
5118 @cindex @code{neg@var{m}2} instruction pattern
5119 @cindex @code{ssneg@var{m}2} instruction pattern
5120 @cindex @code{usneg@var{m}2} instruction pattern
5121 @item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2}
5122 Negate operand 1 and store the result in operand 0.
5124 @cindex @code{abs@var{m}2} instruction pattern
5125 @item @samp{abs@var{m}2}
5126 Store the absolute value of operand 1 into operand 0.
5128 @cindex @code{sqrt@var{m}2} instruction pattern
5129 @item @samp{sqrt@var{m}2}
5130 Store the square root of operand 1 into operand 0.
5132 The @code{sqrt} built-in function of C always uses the mode which
5133 corresponds to the C data type @code{double} and the @code{sqrtf}
5134 built-in function uses the mode which corresponds to the C data
5137 @cindex @code{fmod@var{m}3} instruction pattern
5138 @item @samp{fmod@var{m}3}
5139 Store the remainder of dividing operand 1 by operand 2 into
5140 operand 0, rounded towards zero to an integer.
5142 The @code{fmod} built-in function of C always uses the mode which
5143 corresponds to the C data type @code{double} and the @code{fmodf}
5144 built-in function uses the mode which corresponds to the C data
5147 @cindex @code{remainder@var{m}3} instruction pattern
5148 @item @samp{remainder@var{m}3}
5149 Store the remainder of dividing operand 1 by operand 2 into
5150 operand 0, rounded to the nearest integer.
5152 The @code{remainder} built-in function of C always uses the mode
5153 which corresponds to the C data type @code{double} and the
5154 @code{remainderf} built-in function uses the mode which corresponds
5155 to the C data type @code{float}.
5157 @cindex @code{cos@var{m}2} instruction pattern
5158 @item @samp{cos@var{m}2}
5159 Store the cosine of operand 1 into operand 0.
5161 The @code{cos} built-in function of C always uses the mode which
5162 corresponds to the C data type @code{double} and the @code{cosf}
5163 built-in function uses the mode which corresponds to the C data
5166 @cindex @code{sin@var{m}2} instruction pattern
5167 @item @samp{sin@var{m}2}
5168 Store the sine of operand 1 into operand 0.
5170 The @code{sin} built-in function of C always uses the mode which
5171 corresponds to the C data type @code{double} and the @code{sinf}
5172 built-in function uses the mode which corresponds to the C data
5175 @cindex @code{sincos@var{m}3} instruction pattern
5176 @item @samp{sincos@var{m}3}
5177 Store the cosine of operand 2 into operand 0 and the sine of
5178 operand 2 into operand 1.
5180 The @code{sin} and @code{cos} built-in functions of C always use the
5181 mode which corresponds to the C data type @code{double} and the
5182 @code{sinf} and @code{cosf} built-in function use the mode which
5183 corresponds to the C data type @code{float}.
5184 Targets that can calculate the sine and cosine simultaneously can
5185 implement this pattern as opposed to implementing individual
5186 @code{sin@var{m}2} and @code{cos@var{m}2} patterns. The @code{sin}
5187 and @code{cos} built-in functions will then be expanded to the
5188 @code{sincos@var{m}3} pattern, with one of the output values
5191 @cindex @code{exp@var{m}2} instruction pattern
5192 @item @samp{exp@var{m}2}
5193 Store the exponential of operand 1 into operand 0.
5195 The @code{exp} built-in function of C always uses the mode which
5196 corresponds to the C data type @code{double} and the @code{expf}
5197 built-in function uses the mode which corresponds to the C data
5200 @cindex @code{log@var{m}2} instruction pattern
5201 @item @samp{log@var{m}2}
5202 Store the natural logarithm of operand 1 into operand 0.
5204 The @code{log} built-in function of C always uses the mode which
5205 corresponds to the C data type @code{double} and the @code{logf}
5206 built-in function uses the mode which corresponds to the C data
5209 @cindex @code{pow@var{m}3} instruction pattern
5210 @item @samp{pow@var{m}3}
5211 Store the value of operand 1 raised to the exponent operand 2
5214 The @code{pow} built-in function of C always uses the mode which
5215 corresponds to the C data type @code{double} and the @code{powf}
5216 built-in function uses the mode which corresponds to the C data
5219 @cindex @code{atan2@var{m}3} instruction pattern
5220 @item @samp{atan2@var{m}3}
5221 Store the arc tangent (inverse tangent) of operand 1 divided by
5222 operand 2 into operand 0, using the signs of both arguments to
5223 determine the quadrant of the result.
5225 The @code{atan2} built-in function of C always uses the mode which
5226 corresponds to the C data type @code{double} and the @code{atan2f}
5227 built-in function uses the mode which corresponds to the C data
5230 @cindex @code{floor@var{m}2} instruction pattern
5231 @item @samp{floor@var{m}2}
5232 Store the largest integral value not greater than argument.
5234 The @code{floor} built-in function of C always uses the mode which
5235 corresponds to the C data type @code{double} and the @code{floorf}
5236 built-in function uses the mode which corresponds to the C data
5239 @cindex @code{btrunc@var{m}2} instruction pattern
5240 @item @samp{btrunc@var{m}2}
5241 Store the argument rounded to integer towards zero.
5243 The @code{trunc} built-in function of C always uses the mode which
5244 corresponds to the C data type @code{double} and the @code{truncf}
5245 built-in function uses the mode which corresponds to the C data
5248 @cindex @code{round@var{m}2} instruction pattern
5249 @item @samp{round@var{m}2}
5250 Store the argument rounded to integer away from zero.
5252 The @code{round} built-in function of C always uses the mode which
5253 corresponds to the C data type @code{double} and the @code{roundf}
5254 built-in function uses the mode which corresponds to the C data
5257 @cindex @code{ceil@var{m}2} instruction pattern
5258 @item @samp{ceil@var{m}2}
5259 Store the argument rounded to integer away from zero.
5261 The @code{ceil} built-in function of C always uses the mode which
5262 corresponds to the C data type @code{double} and the @code{ceilf}
5263 built-in function uses the mode which corresponds to the C data
5266 @cindex @code{nearbyint@var{m}2} instruction pattern
5267 @item @samp{nearbyint@var{m}2}
5268 Store the argument rounded according to the default rounding mode
5270 The @code{nearbyint} built-in function of C always uses the mode which
5271 corresponds to the C data type @code{double} and the @code{nearbyintf}
5272 built-in function uses the mode which corresponds to the C data
5275 @cindex @code{rint@var{m}2} instruction pattern
5276 @item @samp{rint@var{m}2}
5277 Store the argument rounded according to the default rounding mode and
5278 raise the inexact exception when the result differs in value from
5281 The @code{rint} built-in function of C always uses the mode which
5282 corresponds to the C data type @code{double} and the @code{rintf}
5283 built-in function uses the mode which corresponds to the C data
5286 @cindex @code{lrint@var{m}@var{n}2}
5287 @item @samp{lrint@var{m}@var{n}2}
5288 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5289 point mode @var{n} as a signed number according to the current
5290 rounding mode and store in operand 0 (which has mode @var{n}).
5292 @cindex @code{lround@var{m}@var{n}2}
5293 @item @samp{lround@var{m}@var{n}2}
5294 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5295 point mode @var{n} as a signed number rounding to nearest and away
5296 from zero and store in operand 0 (which has mode @var{n}).
5298 @cindex @code{lfloor@var{m}@var{n}2}
5299 @item @samp{lfloor@var{m}@var{n}2}
5300 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5301 point mode @var{n} as a signed number rounding down and store in
5302 operand 0 (which has mode @var{n}).
5304 @cindex @code{lceil@var{m}@var{n}2}
5305 @item @samp{lceil@var{m}@var{n}2}
5306 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5307 point mode @var{n} as a signed number rounding up and store in
5308 operand 0 (which has mode @var{n}).
5310 @cindex @code{copysign@var{m}3} instruction pattern
5311 @item @samp{copysign@var{m}3}
5312 Store a value with the magnitude of operand 1 and the sign of operand
5315 The @code{copysign} built-in function of C always uses the mode which
5316 corresponds to the C data type @code{double} and the @code{copysignf}
5317 built-in function uses the mode which corresponds to the C data
5320 @cindex @code{ffs@var{m}2} instruction pattern
5321 @item @samp{ffs@var{m}2}
5322 Store into operand 0 one plus the index of the least significant 1-bit
5323 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
5324 of operand 0; operand 1's mode is specified by the instruction
5325 pattern, and the compiler will convert the operand to that mode before
5326 generating the instruction.
5328 The @code{ffs} built-in function of C always uses the mode which
5329 corresponds to the C data type @code{int}.
5331 @cindex @code{clrsb@var{m}2} instruction pattern
5332 @item @samp{clrsb@var{m}2}
5333 Count leading redundant sign bits.
5334 Store into operand 0 the number of redundant sign bits in operand 1, starting
5335 at the most significant bit position.
5336 A redundant sign bit is defined as any sign bit after the first. As such,
5337 this count will be one less than the count of leading sign bits.
5339 @cindex @code{clz@var{m}2} instruction pattern
5340 @item @samp{clz@var{m}2}
5341 Store into operand 0 the number of leading 0-bits in operand 1, starting
5342 at the most significant bit position. If operand 1 is 0, the
5343 @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
5344 the result is undefined or has a useful value.
5345 @var{m} is the mode of operand 0; operand 1's mode is
5346 specified by the instruction pattern, and the compiler will convert the
5347 operand to that mode before generating the instruction.
5349 @cindex @code{ctz@var{m}2} instruction pattern
5350 @item @samp{ctz@var{m}2}
5351 Store into operand 0 the number of trailing 0-bits in operand 1, starting
5352 at the least significant bit position. If operand 1 is 0, the
5353 @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
5354 the result is undefined or has a useful value.
5355 @var{m} is the mode of operand 0; operand 1's mode is
5356 specified by the instruction pattern, and the compiler will convert the
5357 operand to that mode before generating the instruction.
5359 @cindex @code{popcount@var{m}2} instruction pattern
5360 @item @samp{popcount@var{m}2}
5361 Store into operand 0 the number of 1-bits in operand 1. @var{m} is the
5362 mode of operand 0; operand 1's mode is specified by the instruction
5363 pattern, and the compiler will convert the operand to that mode before
5364 generating the instruction.
5366 @cindex @code{parity@var{m}2} instruction pattern
5367 @item @samp{parity@var{m}2}
5368 Store into operand 0 the parity of operand 1, i.e.@: the number of 1-bits
5369 in operand 1 modulo 2. @var{m} is the mode of operand 0; operand 1's mode
5370 is specified by the instruction pattern, and the compiler will convert
5371 the operand to that mode before generating the instruction.
5373 @cindex @code{one_cmpl@var{m}2} instruction pattern
5374 @item @samp{one_cmpl@var{m}2}
5375 Store the bitwise-complement of operand 1 into operand 0.
5377 @cindex @code{movmem@var{m}} instruction pattern
5378 @item @samp{movmem@var{m}}
5379 Block move instruction. The destination and source blocks of memory
5380 are the first two operands, and both are @code{mem:BLK}s with an
5381 address in mode @code{Pmode}.
5383 The number of bytes to move is the third operand, in mode @var{m}.
5384 Usually, you specify @code{Pmode} for @var{m}. However, if you can
5385 generate better code knowing the range of valid lengths is smaller than
5386 those representable in a full Pmode pointer, you should provide
5388 mode corresponding to the range of values you can handle efficiently
5389 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
5390 that appear negative) and also a pattern with @code{Pmode}.
5392 The fourth operand is the known shared alignment of the source and
5393 destination, in the form of a @code{const_int} rtx. Thus, if the
5394 compiler knows that both source and destination are word-aligned,
5395 it may provide the value 4 for this operand.
5397 Optional operands 5 and 6 specify expected alignment and size of block
5398 respectively. The expected alignment differs from alignment in operand 4
5399 in a way that the blocks are not required to be aligned according to it in
5400 all cases. This expected alignment is also in bytes, just like operand 4.
5401 Expected size, when unknown, is set to @code{(const_int -1)}.
5403 Descriptions of multiple @code{movmem@var{m}} patterns can only be
5404 beneficial if the patterns for smaller modes have fewer restrictions
5405 on their first, second and fourth operands. Note that the mode @var{m}
5406 in @code{movmem@var{m}} does not impose any restriction on the mode of
5407 individually moved data units in the block.
5409 These patterns need not give special consideration to the possibility
5410 that the source and destination strings might overlap.
5412 @cindex @code{movstr} instruction pattern
5414 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
5415 an output operand in mode @code{Pmode}. The addresses of the
5416 destination and source strings are operands 1 and 2, and both are
5417 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
5418 the expansion of this pattern should store in operand 0 the address in
5419 which the @code{NUL} terminator was stored in the destination string.
5421 This patern has also several optional operands that are same as in
5424 @cindex @code{setmem@var{m}} instruction pattern
5425 @item @samp{setmem@var{m}}
5426 Block set instruction. The destination string is the first operand,
5427 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
5428 number of bytes to set is the second operand, in mode @var{m}. The value to
5429 initialize the memory with is the third operand. Targets that only support the
5430 clearing of memory should reject any value that is not the constant 0. See
5431 @samp{movmem@var{m}} for a discussion of the choice of mode.
5433 The fourth operand is the known alignment of the destination, in the form
5434 of a @code{const_int} rtx. Thus, if the compiler knows that the
5435 destination is word-aligned, it may provide the value 4 for this
5438 Optional operands 5 and 6 specify expected alignment and size of block
5439 respectively. The expected alignment differs from alignment in operand 4
5440 in a way that the blocks are not required to be aligned according to it in
5441 all cases. This expected alignment is also in bytes, just like operand 4.
5442 Expected size, when unknown, is set to @code{(const_int -1)}.
5443 Operand 7 is the minimal size of the block and operand 8 is the
5444 maximal size of the block (NULL if it can not be represented as CONST_INT).
5445 Operand 9 is the probable maximal size (i.e. we can not rely on it for correctness,
5446 but it can be used for choosing proper code sequence for a given size).
5448 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
5450 @cindex @code{cmpstrn@var{m}} instruction pattern
5451 @item @samp{cmpstrn@var{m}}
5452 String compare instruction, with five operands. Operand 0 is the output;
5453 it has mode @var{m}. The remaining four operands are like the operands
5454 of @samp{movmem@var{m}}. The two memory blocks specified are compared
5455 byte by byte in lexicographic order starting at the beginning of each
5456 string. The instruction is not allowed to prefetch more than one byte
5457 at a time since either string may end in the first byte and reading past
5458 that may access an invalid page or segment and cause a fault. The
5459 comparison terminates early if the fetched bytes are different or if
5460 they are equal to zero. The effect of the instruction is to store a
5461 value in operand 0 whose sign indicates the result of the comparison.
5463 @cindex @code{cmpstr@var{m}} instruction pattern
5464 @item @samp{cmpstr@var{m}}
5465 String compare instruction, without known maximum length. Operand 0 is the
5466 output; it has mode @var{m}. The second and third operand are the blocks of
5467 memory to be compared; both are @code{mem:BLK} with an address in mode
5470 The fourth operand is the known shared alignment of the source and
5471 destination, in the form of a @code{const_int} rtx. Thus, if the
5472 compiler knows that both source and destination are word-aligned,
5473 it may provide the value 4 for this operand.
5475 The two memory blocks specified are compared byte by byte in lexicographic
5476 order starting at the beginning of each string. The instruction is not allowed
5477 to prefetch more than one byte at a time since either string may end in the
5478 first byte and reading past that may access an invalid page or segment and
5479 cause a fault. The comparison will terminate when the fetched bytes
5480 are different or if they are equal to zero. The effect of the
5481 instruction is to store a value in operand 0 whose sign indicates the
5482 result of the comparison.
5484 @cindex @code{cmpmem@var{m}} instruction pattern
5485 @item @samp{cmpmem@var{m}}
5486 Block compare instruction, with five operands like the operands
5487 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
5488 byte by byte in lexicographic order starting at the beginning of each
5489 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
5490 any bytes in the two memory blocks. Also unlike @samp{cmpstr@var{m}}
5491 the comparison will not stop if both bytes are zero. The effect of
5492 the instruction is to store a value in operand 0 whose sign indicates
5493 the result of the comparison.
5495 @cindex @code{strlen@var{m}} instruction pattern
5496 @item @samp{strlen@var{m}}
5497 Compute the length of a string, with three operands.
5498 Operand 0 is the result (of mode @var{m}), operand 1 is
5499 a @code{mem} referring to the first character of the string,
5500 operand 2 is the character to search for (normally zero),
5501 and operand 3 is a constant describing the known alignment
5502 of the beginning of the string.
5504 @cindex @code{float@var{m}@var{n}2} instruction pattern
5505 @item @samp{float@var{m}@var{n}2}
5506 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
5507 floating point mode @var{n} and store in operand 0 (which has mode
5510 @cindex @code{floatuns@var{m}@var{n}2} instruction pattern
5511 @item @samp{floatuns@var{m}@var{n}2}
5512 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
5513 to floating point mode @var{n} and store in operand 0 (which has mode
5516 @cindex @code{fix@var{m}@var{n}2} instruction pattern
5517 @item @samp{fix@var{m}@var{n}2}
5518 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5519 point mode @var{n} as a signed number and store in operand 0 (which
5520 has mode @var{n}). This instruction's result is defined only when
5521 the value of operand 1 is an integer.
5523 If the machine description defines this pattern, it also needs to
5524 define the @code{ftrunc} pattern.
5526 @cindex @code{fixuns@var{m}@var{n}2} instruction pattern
5527 @item @samp{fixuns@var{m}@var{n}2}
5528 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5529 point mode @var{n} as an unsigned number and store in operand 0 (which
5530 has mode @var{n}). This instruction's result is defined only when the
5531 value of operand 1 is an integer.
5533 @cindex @code{ftrunc@var{m}2} instruction pattern
5534 @item @samp{ftrunc@var{m}2}
5535 Convert operand 1 (valid for floating point mode @var{m}) to an
5536 integer value, still represented in floating point mode @var{m}, and
5537 store it in operand 0 (valid for floating point mode @var{m}).
5539 @cindex @code{fix_trunc@var{m}@var{n}2} instruction pattern
5540 @item @samp{fix_trunc@var{m}@var{n}2}
5541 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
5542 of mode @var{m} by converting the value to an integer.
5544 @cindex @code{fixuns_trunc@var{m}@var{n}2} instruction pattern
5545 @item @samp{fixuns_trunc@var{m}@var{n}2}
5546 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
5547 value of mode @var{m} by converting the value to an integer.
5549 @cindex @code{trunc@var{m}@var{n}2} instruction pattern
5550 @item @samp{trunc@var{m}@var{n}2}
5551 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
5552 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5553 point or both floating point.
5555 @cindex @code{extend@var{m}@var{n}2} instruction pattern
5556 @item @samp{extend@var{m}@var{n}2}
5557 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
5558 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5559 point or both floating point.
5561 @cindex @code{zero_extend@var{m}@var{n}2} instruction pattern
5562 @item @samp{zero_extend@var{m}@var{n}2}
5563 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
5564 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5567 @cindex @code{fract@var{m}@var{n}2} instruction pattern
5568 @item @samp{fract@var{m}@var{n}2}
5569 Convert operand 1 of mode @var{m} to mode @var{n} and store in
5570 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5571 could be fixed-point to fixed-point, signed integer to fixed-point,
5572 fixed-point to signed integer, floating-point to fixed-point,
5573 or fixed-point to floating-point.
5574 When overflows or underflows happen, the results are undefined.
5576 @cindex @code{satfract@var{m}@var{n}2} instruction pattern
5577 @item @samp{satfract@var{m}@var{n}2}
5578 Convert operand 1 of mode @var{m} to mode @var{n} and store in
5579 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5580 could be fixed-point to fixed-point, signed integer to fixed-point,
5581 or floating-point to fixed-point.
5582 When overflows or underflows happen, the instruction saturates the
5583 results to the maximum or the minimum.
5585 @cindex @code{fractuns@var{m}@var{n}2} instruction pattern
5586 @item @samp{fractuns@var{m}@var{n}2}
5587 Convert operand 1 of mode @var{m} to mode @var{n} and store in
5588 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5589 could be unsigned integer to fixed-point, or
5590 fixed-point to unsigned integer.
5591 When overflows or underflows happen, the results are undefined.
5593 @cindex @code{satfractuns@var{m}@var{n}2} instruction pattern
5594 @item @samp{satfractuns@var{m}@var{n}2}
5595 Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode
5596 @var{n} and store in operand 0 (which has mode @var{n}).
5597 When overflows or underflows happen, the instruction saturates the
5598 results to the maximum or the minimum.
5600 @cindex @code{extv@var{m}} instruction pattern
5601 @item @samp{extv@var{m}}
5602 Extract a bit-field from register operand 1, sign-extend it, and store
5603 it in operand 0. Operand 2 specifies the width of the field in bits
5604 and operand 3 the starting bit, which counts from the most significant
5605 bit if @samp{BITS_BIG_ENDIAN} is true and from the least significant bit
5608 Operands 0 and 1 both have mode @var{m}. Operands 2 and 3 have a
5609 target-specific mode.
5611 @cindex @code{extvmisalign@var{m}} instruction pattern
5612 @item @samp{extvmisalign@var{m}}
5613 Extract a bit-field from memory operand 1, sign extend it, and store
5614 it in operand 0. Operand 2 specifies the width in bits and operand 3
5615 the starting bit. The starting bit is always somewhere in the first byte of
5616 operand 1; it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
5617 is true and from the least significant bit otherwise.
5619 Operand 0 has mode @var{m} while operand 1 has @code{BLK} mode.
5620 Operands 2 and 3 have a target-specific mode.
5622 The instruction must not read beyond the last byte of the bit-field.
5624 @cindex @code{extzv@var{m}} instruction pattern
5625 @item @samp{extzv@var{m}}
5626 Like @samp{extv@var{m}} except that the bit-field value is zero-extended.
5628 @cindex @code{extzvmisalign@var{m}} instruction pattern
5629 @item @samp{extzvmisalign@var{m}}
5630 Like @samp{extvmisalign@var{m}} except that the bit-field value is
5633 @cindex @code{insv@var{m}} instruction pattern
5634 @item @samp{insv@var{m}}
5635 Insert operand 3 into a bit-field of register operand 0. Operand 1
5636 specifies the width of the field in bits and operand 2 the starting bit,
5637 which counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
5638 is true and from the least significant bit otherwise.
5640 Operands 0 and 3 both have mode @var{m}. Operands 1 and 2 have a
5641 target-specific mode.
5643 @cindex @code{insvmisalign@var{m}} instruction pattern
5644 @item @samp{insvmisalign@var{m}}
5645 Insert operand 3 into a bit-field of memory operand 0. Operand 1
5646 specifies the width of the field in bits and operand 2 the starting bit.
5647 The starting bit is always somewhere in the first byte of operand 0;
5648 it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
5649 is true and from the least significant bit otherwise.
5651 Operand 3 has mode @var{m} while operand 0 has @code{BLK} mode.
5652 Operands 1 and 2 have a target-specific mode.
5654 The instruction must not read or write beyond the last byte of the bit-field.
5656 @cindex @code{extv} instruction pattern
5658 Extract a bit-field from operand 1 (a register or memory operand), where
5659 operand 2 specifies the width in bits and operand 3 the starting bit,
5660 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
5661 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
5662 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
5663 be valid for @code{word_mode}.
5665 The RTL generation pass generates this instruction only with constants
5666 for operands 2 and 3 and the constant is never zero for operand 2.
5668 The bit-field value is sign-extended to a full word integer
5669 before it is stored in operand 0.
5671 This pattern is deprecated; please use @samp{extv@var{m}} and
5672 @code{extvmisalign@var{m}} instead.
5674 @cindex @code{extzv} instruction pattern
5676 Like @samp{extv} except that the bit-field value is zero-extended.
5678 This pattern is deprecated; please use @samp{extzv@var{m}} and
5679 @code{extzvmisalign@var{m}} instead.
5681 @cindex @code{insv} instruction pattern
5683 Store operand 3 (which must be valid for @code{word_mode}) into a
5684 bit-field in operand 0, where operand 1 specifies the width in bits and
5685 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
5686 @code{word_mode}; often @code{word_mode} is allowed only for registers.
5687 Operands 1 and 2 must be valid for @code{word_mode}.
5689 The RTL generation pass generates this instruction only with constants
5690 for operands 1 and 2 and the constant is never zero for operand 1.
5692 This pattern is deprecated; please use @samp{insv@var{m}} and
5693 @code{insvmisalign@var{m}} instead.
5695 @cindex @code{mov@var{mode}cc} instruction pattern
5696 @item @samp{mov@var{mode}cc}
5697 Conditionally move operand 2 or operand 3 into operand 0 according to the
5698 comparison in operand 1. If the comparison is true, operand 2 is moved
5699 into operand 0, otherwise operand 3 is moved.
5701 The mode of the operands being compared need not be the same as the operands
5702 being moved. Some machines, sparc64 for example, have instructions that
5703 conditionally move an integer value based on the floating point condition
5704 codes and vice versa.
5706 If the machine does not have conditional move instructions, do not
5707 define these patterns.
5709 @cindex @code{add@var{mode}cc} instruction pattern
5710 @item @samp{add@var{mode}cc}
5711 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
5712 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
5713 comparison in operand 1. If the comparison is false, operand 2 is moved into
5714 operand 0, otherwise (operand 2 + operand 3) is moved.
5716 @cindex @code{cstore@var{mode}4} instruction pattern
5717 @item @samp{cstore@var{mode}4}
5718 Store zero or nonzero in operand 0 according to whether a comparison
5719 is true. Operand 1 is a comparison operator. Operand 2 and operand 3
5720 are the first and second operand of the comparison, respectively.
5721 You specify the mode that operand 0 must have when you write the
5722 @code{match_operand} expression. The compiler automatically sees which
5723 mode you have used and supplies an operand of that mode.
5725 The value stored for a true condition must have 1 as its low bit, or
5726 else must be negative. Otherwise the instruction is not suitable and
5727 you should omit it from the machine description. You describe to the
5728 compiler exactly which value is stored by defining the macro
5729 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
5730 found that can be used for all the possible comparison operators, you
5731 should pick one and use a @code{define_expand} to map all results
5732 onto the one you chose.
5734 These operations may @code{FAIL}, but should do so only in relatively
5735 uncommon cases; if they would @code{FAIL} for common cases involving
5736 integer comparisons, it is best to restrict the predicates to not
5737 allow these operands. Likewise if a given comparison operator will
5738 always fail, independent of the operands (for floating-point modes, the
5739 @code{ordered_comparison_operator} predicate is often useful in this case).
5741 If this pattern is omitted, the compiler will generate a conditional
5742 branch---for example, it may copy a constant one to the target and branching
5743 around an assignment of zero to the target---or a libcall. If the predicate
5744 for operand 1 only rejects some operators, it will also try reordering the
5745 operands and/or inverting the result value (e.g.@: by an exclusive OR).
5746 These possibilities could be cheaper or equivalent to the instructions
5747 used for the @samp{cstore@var{mode}4} pattern followed by those required
5748 to convert a positive result from @code{STORE_FLAG_VALUE} to 1; in this
5749 case, you can and should make operand 1's predicate reject some operators
5750 in the @samp{cstore@var{mode}4} pattern, or remove the pattern altogether
5751 from the machine description.
5753 @cindex @code{cbranch@var{mode}4} instruction pattern
5754 @item @samp{cbranch@var{mode}4}
5755 Conditional branch instruction combined with a compare instruction.
5756 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
5757 first and second operands of the comparison, respectively. Operand 3
5758 is a @code{label_ref} that refers to the label to jump to.
5760 @cindex @code{jump} instruction pattern
5762 A jump inside a function; an unconditional branch. Operand 0 is the
5763 @code{label_ref} of the label to jump to. This pattern name is mandatory
5766 @cindex @code{call} instruction pattern
5768 Subroutine call instruction returning no value. Operand 0 is the
5769 function to call; operand 1 is the number of bytes of arguments pushed
5770 as a @code{const_int}; operand 2 is the number of registers used as
5773 On most machines, operand 2 is not actually stored into the RTL
5774 pattern. It is supplied for the sake of some RISC machines which need
5775 to put this information into the assembler code; they can put it in
5776 the RTL instead of operand 1.
5778 Operand 0 should be a @code{mem} RTX whose address is the address of the
5779 function. Note, however, that this address can be a @code{symbol_ref}
5780 expression even if it would not be a legitimate memory address on the
5781 target machine. If it is also not a valid argument for a call
5782 instruction, the pattern for this operation should be a
5783 @code{define_expand} (@pxref{Expander Definitions}) that places the
5784 address into a register and uses that register in the call instruction.
5786 @cindex @code{call_value} instruction pattern
5787 @item @samp{call_value}
5788 Subroutine call instruction returning a value. Operand 0 is the hard
5789 register in which the value is returned. There are three more
5790 operands, the same as the three operands of the @samp{call}
5791 instruction (but with numbers increased by one).
5793 Subroutines that return @code{BLKmode} objects use the @samp{call}
5796 @cindex @code{call_pop} instruction pattern
5797 @cindex @code{call_value_pop} instruction pattern
5798 @item @samp{call_pop}, @samp{call_value_pop}
5799 Similar to @samp{call} and @samp{call_value}, except used if defined and
5800 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
5801 that contains both the function call and a @code{set} to indicate the
5802 adjustment made to the frame pointer.
5804 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
5805 patterns increases the number of functions for which the frame pointer
5806 can be eliminated, if desired.
5808 @cindex @code{untyped_call} instruction pattern
5809 @item @samp{untyped_call}
5810 Subroutine call instruction returning a value of any type. Operand 0 is
5811 the function to call; operand 1 is a memory location where the result of
5812 calling the function is to be stored; operand 2 is a @code{parallel}
5813 expression where each element is a @code{set} expression that indicates
5814 the saving of a function return value into the result block.
5816 This instruction pattern should be defined to support
5817 @code{__builtin_apply} on machines where special instructions are needed
5818 to call a subroutine with arbitrary arguments or to save the value
5819 returned. This instruction pattern is required on machines that have
5820 multiple registers that can hold a return value
5821 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
5823 @cindex @code{return} instruction pattern
5825 Subroutine return instruction. This instruction pattern name should be
5826 defined only if a single instruction can do all the work of returning
5829 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
5830 RTL generation phase. In this case it is to support machines where
5831 multiple instructions are usually needed to return from a function, but
5832 some class of functions only requires one instruction to implement a
5833 return. Normally, the applicable functions are those which do not need
5834 to save any registers or allocate stack space.
5836 It is valid for this pattern to expand to an instruction using
5837 @code{simple_return} if no epilogue is required.
5839 @cindex @code{simple_return} instruction pattern
5840 @item @samp{simple_return}
5841 Subroutine return instruction. This instruction pattern name should be
5842 defined only if a single instruction can do all the work of returning
5843 from a function on a path where no epilogue is required. This pattern
5844 is very similar to the @code{return} instruction pattern, but it is emitted
5845 only by the shrink-wrapping optimization on paths where the function
5846 prologue has not been executed, and a function return should occur without
5847 any of the effects of the epilogue. Additional uses may be introduced on
5848 paths where both the prologue and the epilogue have executed.
5850 @findex reload_completed
5851 @findex leaf_function_p
5852 For such machines, the condition specified in this pattern should only
5853 be true when @code{reload_completed} is nonzero and the function's
5854 epilogue would only be a single instruction. For machines with register
5855 windows, the routine @code{leaf_function_p} may be used to determine if
5856 a register window push is required.
5858 Machines that have conditional return instructions should define patterns
5864 (if_then_else (match_operator
5865 0 "comparison_operator"
5866 [(cc0) (const_int 0)])
5873 where @var{condition} would normally be the same condition specified on the
5874 named @samp{return} pattern.
5876 @cindex @code{untyped_return} instruction pattern
5877 @item @samp{untyped_return}
5878 Untyped subroutine return instruction. This instruction pattern should
5879 be defined to support @code{__builtin_return} on machines where special
5880 instructions are needed to return a value of any type.
5882 Operand 0 is a memory location where the result of calling a function
5883 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
5884 expression where each element is a @code{set} expression that indicates
5885 the restoring of a function return value from the result block.
5887 @cindex @code{nop} instruction pattern
5889 No-op instruction. This instruction pattern name should always be defined
5890 to output a no-op in assembler code. @code{(const_int 0)} will do as an
5893 @cindex @code{indirect_jump} instruction pattern
5894 @item @samp{indirect_jump}
5895 An instruction to jump to an address which is operand zero.
5896 This pattern name is mandatory on all machines.
5898 @cindex @code{casesi} instruction pattern
5900 Instruction to jump through a dispatch table, including bounds checking.
5901 This instruction takes five operands:
5905 The index to dispatch on, which has mode @code{SImode}.
5908 The lower bound for indices in the table, an integer constant.
5911 The total range of indices in the table---the largest index
5912 minus the smallest one (both inclusive).
5915 A label that precedes the table itself.
5918 A label to jump to if the index has a value outside the bounds.
5921 The table is an @code{addr_vec} or @code{addr_diff_vec} inside of a
5922 @code{jump_table_data}. The number of elements in the table is one plus the
5923 difference between the upper bound and the lower bound.
5925 @cindex @code{tablejump} instruction pattern
5926 @item @samp{tablejump}
5927 Instruction to jump to a variable address. This is a low-level
5928 capability which can be used to implement a dispatch table when there
5929 is no @samp{casesi} pattern.
5931 This pattern requires two operands: the address or offset, and a label
5932 which should immediately precede the jump table. If the macro
5933 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
5934 operand is an offset which counts from the address of the table; otherwise,
5935 it is an absolute address to jump to. In either case, the first operand has
5938 The @samp{tablejump} insn is always the last insn before the jump
5939 table it uses. Its assembler code normally has no need to use the
5940 second operand, but you should incorporate it in the RTL pattern so
5941 that the jump optimizer will not delete the table as unreachable code.
5944 @cindex @code{decrement_and_branch_until_zero} instruction pattern
5945 @item @samp{decrement_and_branch_until_zero}
5946 Conditional branch instruction that decrements a register and
5947 jumps if the register is nonzero. Operand 0 is the register to
5948 decrement and test; operand 1 is the label to jump to if the
5949 register is nonzero. @xref{Looping Patterns}.
5951 This optional instruction pattern is only used by the combiner,
5952 typically for loops reversed by the loop optimizer when strength
5953 reduction is enabled.
5955 @cindex @code{doloop_end} instruction pattern
5956 @item @samp{doloop_end}
5957 Conditional branch instruction that decrements a register and
5958 jumps if the register is nonzero. Operand 0 is the register to
5959 decrement and test; operand 1 is the label to jump to if the
5960 register is nonzero.
5961 @xref{Looping Patterns}.
5963 This optional instruction pattern should be defined for machines with
5964 low-overhead looping instructions as the loop optimizer will try to
5965 modify suitable loops to utilize it. The target hook
5966 @code{TARGET_CAN_USE_DOLOOP_P} controls the conditions under which
5967 low-overhead loops can be used.
5969 @cindex @code{doloop_begin} instruction pattern
5970 @item @samp{doloop_begin}
5971 Companion instruction to @code{doloop_end} required for machines that
5972 need to perform some initialization, such as loading a special counter
5973 register. Operand 1 is the associated @code{doloop_end} pattern and
5974 operand 0 is the register that it decrements.
5976 If initialization insns do not always need to be emitted, use a
5977 @code{define_expand} (@pxref{Expander Definitions}) and make it fail.
5979 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
5980 @item @samp{canonicalize_funcptr_for_compare}
5981 Canonicalize the function pointer in operand 1 and store the result
5984 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
5985 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
5986 and also has mode @code{Pmode}.
5988 Canonicalization of a function pointer usually involves computing
5989 the address of the function which would be called if the function
5990 pointer were used in an indirect call.
5992 Only define this pattern if function pointers on the target machine
5993 can have different values but still call the same function when
5994 used in an indirect call.
5996 @cindex @code{save_stack_block} instruction pattern
5997 @cindex @code{save_stack_function} instruction pattern
5998 @cindex @code{save_stack_nonlocal} instruction pattern
5999 @cindex @code{restore_stack_block} instruction pattern
6000 @cindex @code{restore_stack_function} instruction pattern
6001 @cindex @code{restore_stack_nonlocal} instruction pattern
6002 @item @samp{save_stack_block}
6003 @itemx @samp{save_stack_function}
6004 @itemx @samp{save_stack_nonlocal}
6005 @itemx @samp{restore_stack_block}
6006 @itemx @samp{restore_stack_function}
6007 @itemx @samp{restore_stack_nonlocal}
6008 Most machines save and restore the stack pointer by copying it to or
6009 from an object of mode @code{Pmode}. Do not define these patterns on
6012 Some machines require special handling for stack pointer saves and
6013 restores. On those machines, define the patterns corresponding to the
6014 non-standard cases by using a @code{define_expand} (@pxref{Expander
6015 Definitions}) that produces the required insns. The three types of
6016 saves and restores are:
6020 @samp{save_stack_block} saves the stack pointer at the start of a block
6021 that allocates a variable-sized object, and @samp{restore_stack_block}
6022 restores the stack pointer when the block is exited.
6025 @samp{save_stack_function} and @samp{restore_stack_function} do a
6026 similar job for the outermost block of a function and are used when the
6027 function allocates variable-sized objects or calls @code{alloca}. Only
6028 the epilogue uses the restored stack pointer, allowing a simpler save or
6029 restore sequence on some machines.
6032 @samp{save_stack_nonlocal} is used in functions that contain labels
6033 branched to by nested functions. It saves the stack pointer in such a
6034 way that the inner function can use @samp{restore_stack_nonlocal} to
6035 restore the stack pointer. The compiler generates code to restore the
6036 frame and argument pointer registers, but some machines require saving
6037 and restoring additional data such as register window information or
6038 stack backchains. Place insns in these patterns to save and restore any
6042 When saving the stack pointer, operand 0 is the save area and operand 1
6043 is the stack pointer. The mode used to allocate the save area defaults
6044 to @code{Pmode} but you can override that choice by defining the
6045 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
6046 specify an integral mode, or @code{VOIDmode} if no save area is needed
6047 for a particular type of save (either because no save is needed or
6048 because a machine-specific save area can be used). Operand 0 is the
6049 stack pointer and operand 1 is the save area for restore operations. If
6050 @samp{save_stack_block} is defined, operand 0 must not be
6051 @code{VOIDmode} since these saves can be arbitrarily nested.
6053 A save area is a @code{mem} that is at a constant offset from
6054 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
6055 nonlocal gotos and a @code{reg} in the other two cases.
6057 @cindex @code{allocate_stack} instruction pattern
6058 @item @samp{allocate_stack}
6059 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
6060 the stack pointer to create space for dynamically allocated data.
6062 Store the resultant pointer to this space into operand 0. If you
6063 are allocating space from the main stack, do this by emitting a
6064 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
6065 If you are allocating the space elsewhere, generate code to copy the
6066 location of the space to operand 0. In the latter case, you must
6067 ensure this space gets freed when the corresponding space on the main
6070 Do not define this pattern if all that must be done is the subtraction.
6071 Some machines require other operations such as stack probes or
6072 maintaining the back chain. Define this pattern to emit those
6073 operations in addition to updating the stack pointer.
6075 @cindex @code{check_stack} instruction pattern
6076 @item @samp{check_stack}
6077 If stack checking (@pxref{Stack Checking}) cannot be done on your system by
6078 probing the stack, define this pattern to perform the needed check and signal
6079 an error if the stack has overflowed. The single operand is the address in
6080 the stack farthest from the current stack pointer that you need to validate.
6081 Normally, on platforms where this pattern is needed, you would obtain the
6082 stack limit from a global or thread-specific variable or register.
6084 @cindex @code{probe_stack_address} instruction pattern
6085 @item @samp{probe_stack_address}
6086 If stack checking (@pxref{Stack Checking}) can be done on your system by
6087 probing the stack but without the need to actually access it, define this
6088 pattern and signal an error if the stack has overflowed. The single operand
6089 is the memory address in the stack that needs to be probed.
6091 @cindex @code{probe_stack} instruction pattern
6092 @item @samp{probe_stack}
6093 If stack checking (@pxref{Stack Checking}) can be done on your system by
6094 probing the stack but doing it with a ``store zero'' instruction is not valid
6095 or optimal, define this pattern to do the probing differently and signal an
6096 error if the stack has overflowed. The single operand is the memory reference
6097 in the stack that needs to be probed.
6099 @cindex @code{nonlocal_goto} instruction pattern
6100 @item @samp{nonlocal_goto}
6101 Emit code to generate a non-local goto, e.g., a jump from one function
6102 to a label in an outer function. This pattern has four arguments,
6103 each representing a value to be used in the jump. The first
6104 argument is to be loaded into the frame pointer, the second is
6105 the address to branch to (code to dispatch to the actual label),
6106 the third is the address of a location where the stack is saved,
6107 and the last is the address of the label, to be placed in the
6108 location for the incoming static chain.
6110 On most machines you need not define this pattern, since GCC will
6111 already generate the correct code, which is to load the frame pointer
6112 and static chain, restore the stack (using the
6113 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
6114 to the dispatcher. You need only define this pattern if this code will
6115 not work on your machine.
6117 @cindex @code{nonlocal_goto_receiver} instruction pattern
6118 @item @samp{nonlocal_goto_receiver}
6119 This pattern, if defined, contains code needed at the target of a
6120 nonlocal goto after the code already generated by GCC@. You will not
6121 normally need to define this pattern. A typical reason why you might
6122 need this pattern is if some value, such as a pointer to a global table,
6123 must be restored when the frame pointer is restored. Note that a nonlocal
6124 goto only occurs within a unit-of-translation, so a global table pointer
6125 that is shared by all functions of a given module need not be restored.
6126 There are no arguments.
6128 @cindex @code{exception_receiver} instruction pattern
6129 @item @samp{exception_receiver}
6130 This pattern, if defined, contains code needed at the site of an
6131 exception handler that isn't needed at the site of a nonlocal goto. You
6132 will not normally need to define this pattern. A typical reason why you
6133 might need this pattern is if some value, such as a pointer to a global
6134 table, must be restored after control flow is branched to the handler of
6135 an exception. There are no arguments.
6137 @cindex @code{builtin_setjmp_setup} instruction pattern
6138 @item @samp{builtin_setjmp_setup}
6139 This pattern, if defined, contains additional code needed to initialize
6140 the @code{jmp_buf}. You will not normally need to define this pattern.
6141 A typical reason why you might need this pattern is if some value, such
6142 as a pointer to a global table, must be restored. Though it is
6143 preferred that the pointer value be recalculated if possible (given the
6144 address of a label for instance). The single argument is a pointer to
6145 the @code{jmp_buf}. Note that the buffer is five words long and that
6146 the first three are normally used by the generic mechanism.
6148 @cindex @code{builtin_setjmp_receiver} instruction pattern
6149 @item @samp{builtin_setjmp_receiver}
6150 This pattern, if defined, contains code needed at the site of a
6151 built-in setjmp that isn't needed at the site of a nonlocal goto. You
6152 will not normally need to define this pattern. A typical reason why you
6153 might need this pattern is if some value, such as a pointer to a global
6154 table, must be restored. It takes one argument, which is the label
6155 to which builtin_longjmp transferred control; this pattern may be emitted
6156 at a small offset from that label.
6158 @cindex @code{builtin_longjmp} instruction pattern
6159 @item @samp{builtin_longjmp}
6160 This pattern, if defined, performs the entire action of the longjmp.
6161 You will not normally need to define this pattern unless you also define
6162 @code{builtin_setjmp_setup}. The single argument is a pointer to the
6165 @cindex @code{eh_return} instruction pattern
6166 @item @samp{eh_return}
6167 This pattern, if defined, affects the way @code{__builtin_eh_return},
6168 and thence the call frame exception handling library routines, are
6169 built. It is intended to handle non-trivial actions needed along
6170 the abnormal return path.
6172 The address of the exception handler to which the function should return
6173 is passed as operand to this pattern. It will normally need to copied by
6174 the pattern to some special register or memory location.
6175 If the pattern needs to determine the location of the target call
6176 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
6177 if defined; it will have already been assigned.
6179 If this pattern is not defined, the default action will be to simply
6180 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
6181 that macro or this pattern needs to be defined if call frame exception
6182 handling is to be used.
6184 @cindex @code{prologue} instruction pattern
6185 @anchor{prologue instruction pattern}
6186 @item @samp{prologue}
6187 This pattern, if defined, emits RTL for entry to a function. The function
6188 entry is responsible for setting up the stack frame, initializing the frame
6189 pointer register, saving callee saved registers, etc.
6191 Using a prologue pattern is generally preferred over defining
6192 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
6194 The @code{prologue} pattern is particularly useful for targets which perform
6195 instruction scheduling.
6197 @cindex @code{window_save} instruction pattern
6198 @anchor{window_save instruction pattern}
6199 @item @samp{window_save}
6200 This pattern, if defined, emits RTL for a register window save. It should
6201 be defined if the target machine has register windows but the window events
6202 are decoupled from calls to subroutines. The canonical example is the SPARC
6205 @cindex @code{epilogue} instruction pattern
6206 @anchor{epilogue instruction pattern}
6207 @item @samp{epilogue}
6208 This pattern emits RTL for exit from a function. The function
6209 exit is responsible for deallocating the stack frame, restoring callee saved
6210 registers and emitting the return instruction.
6212 Using an epilogue pattern is generally preferred over defining
6213 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
6215 The @code{epilogue} pattern is particularly useful for targets which perform
6216 instruction scheduling or which have delay slots for their return instruction.
6218 @cindex @code{sibcall_epilogue} instruction pattern
6219 @item @samp{sibcall_epilogue}
6220 This pattern, if defined, emits RTL for exit from a function without the final
6221 branch back to the calling function. This pattern will be emitted before any
6222 sibling call (aka tail call) sites.
6224 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
6225 parameter passing or any stack slots for arguments passed to the current
6228 @cindex @code{trap} instruction pattern
6230 This pattern, if defined, signals an error, typically by causing some
6231 kind of signal to be raised. Among other places, it is used by the Java
6232 front end to signal `invalid array index' exceptions.
6234 @cindex @code{ctrap@var{MM}4} instruction pattern
6235 @item @samp{ctrap@var{MM}4}
6236 Conditional trap instruction. Operand 0 is a piece of RTL which
6237 performs a comparison, and operands 1 and 2 are the arms of the
6238 comparison. Operand 3 is the trap code, an integer.
6240 A typical @code{ctrap} pattern looks like
6243 (define_insn "ctrapsi4"
6244 [(trap_if (match_operator 0 "trap_operator"
6245 [(match_operand 1 "register_operand")
6246 (match_operand 2 "immediate_operand")])
6247 (match_operand 3 "const_int_operand" "i"))]
6252 @cindex @code{prefetch} instruction pattern
6253 @item @samp{prefetch}
6254 This pattern, if defined, emits code for a non-faulting data prefetch
6255 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
6256 is a constant 1 if the prefetch is preparing for a write to the memory
6257 address, or a constant 0 otherwise. Operand 2 is the expected degree of
6258 temporal locality of the data and is a value between 0 and 3, inclusive; 0
6259 means that the data has no temporal locality, so it need not be left in the
6260 cache after the access; 3 means that the data has a high degree of temporal
6261 locality and should be left in all levels of cache possible; 1 and 2 mean,
6262 respectively, a low or moderate degree of temporal locality.
6264 Targets that do not support write prefetches or locality hints can ignore
6265 the values of operands 1 and 2.
6267 @cindex @code{blockage} instruction pattern
6268 @item @samp{blockage}
6269 This pattern defines a pseudo insn that prevents the instruction
6270 scheduler and other passes from moving instructions and using register
6271 equivalences across the boundary defined by the blockage insn.
6272 This needs to be an UNSPEC_VOLATILE pattern or a volatile ASM.
6274 @cindex @code{memory_barrier} instruction pattern
6275 @item @samp{memory_barrier}
6276 If the target memory model is not fully synchronous, then this pattern
6277 should be defined to an instruction that orders both loads and stores
6278 before the instruction with respect to loads and stores after the instruction.
6279 This pattern has no operands.
6281 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
6282 @item @samp{sync_compare_and_swap@var{mode}}
6283 This pattern, if defined, emits code for an atomic compare-and-swap
6284 operation. Operand 1 is the memory on which the atomic operation is
6285 performed. Operand 2 is the ``old'' value to be compared against the
6286 current contents of the memory location. Operand 3 is the ``new'' value
6287 to store in the memory if the compare succeeds. Operand 0 is the result
6288 of the operation; it should contain the contents of the memory
6289 before the operation. If the compare succeeds, this should obviously be
6290 a copy of operand 2.
6292 This pattern must show that both operand 0 and operand 1 are modified.
6294 This pattern must issue any memory barrier instructions such that all
6295 memory operations before the atomic operation occur before the atomic
6296 operation and all memory operations after the atomic operation occur
6297 after the atomic operation.
6299 For targets where the success or failure of the compare-and-swap
6300 operation is available via the status flags, it is possible to
6301 avoid a separate compare operation and issue the subsequent
6302 branch or store-flag operation immediately after the compare-and-swap.
6303 To this end, GCC will look for a @code{MODE_CC} set in the
6304 output of @code{sync_compare_and_swap@var{mode}}; if the machine
6305 description includes such a set, the target should also define special
6306 @code{cbranchcc4} and/or @code{cstorecc4} instructions. GCC will then
6307 be able to take the destination of the @code{MODE_CC} set and pass it
6308 to the @code{cbranchcc4} or @code{cstorecc4} pattern as the first
6309 operand of the comparison (the second will be @code{(const_int 0)}).
6311 For targets where the operating system may provide support for this
6312 operation via library calls, the @code{sync_compare_and_swap_optab}
6313 may be initialized to a function with the same interface as the
6314 @code{__sync_val_compare_and_swap_@var{n}} built-in. If the entire
6315 set of @var{__sync} builtins are supported via library calls, the
6316 target can initialize all of the optabs at once with
6317 @code{init_sync_libfuncs}.
6318 For the purposes of C++11 @code{std::atomic::is_lock_free}, it is
6319 assumed that these library calls do @emph{not} use any kind of
6320 interruptable locking.
6322 @cindex @code{sync_add@var{mode}} instruction pattern
6323 @cindex @code{sync_sub@var{mode}} instruction pattern
6324 @cindex @code{sync_ior@var{mode}} instruction pattern
6325 @cindex @code{sync_and@var{mode}} instruction pattern
6326 @cindex @code{sync_xor@var{mode}} instruction pattern
6327 @cindex @code{sync_nand@var{mode}} instruction pattern
6328 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
6329 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
6330 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
6331 These patterns emit code for an atomic operation on memory.
6332 Operand 0 is the memory on which the atomic operation is performed.
6333 Operand 1 is the second operand to the binary operator.
6335 This pattern must issue any memory barrier instructions such that all
6336 memory operations before the atomic operation occur before the atomic
6337 operation and all memory operations after the atomic operation occur
6338 after the atomic operation.
6340 If these patterns are not defined, the operation will be constructed
6341 from a compare-and-swap operation, if defined.
6343 @cindex @code{sync_old_add@var{mode}} instruction pattern
6344 @cindex @code{sync_old_sub@var{mode}} instruction pattern
6345 @cindex @code{sync_old_ior@var{mode}} instruction pattern
6346 @cindex @code{sync_old_and@var{mode}} instruction pattern
6347 @cindex @code{sync_old_xor@var{mode}} instruction pattern
6348 @cindex @code{sync_old_nand@var{mode}} instruction pattern
6349 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
6350 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
6351 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
6352 These patterns emit code for an atomic operation on memory,
6353 and return the value that the memory contained before the operation.
6354 Operand 0 is the result value, operand 1 is the memory on which the
6355 atomic operation is performed, and operand 2 is the second operand
6356 to the binary operator.
6358 This pattern must issue any memory barrier instructions such that all
6359 memory operations before the atomic operation occur before the atomic
6360 operation and all memory operations after the atomic operation occur
6361 after the atomic operation.
6363 If these patterns are not defined, the operation will be constructed
6364 from a compare-and-swap operation, if defined.
6366 @cindex @code{sync_new_add@var{mode}} instruction pattern
6367 @cindex @code{sync_new_sub@var{mode}} instruction pattern
6368 @cindex @code{sync_new_ior@var{mode}} instruction pattern
6369 @cindex @code{sync_new_and@var{mode}} instruction pattern
6370 @cindex @code{sync_new_xor@var{mode}} instruction pattern
6371 @cindex @code{sync_new_nand@var{mode}} instruction pattern
6372 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
6373 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
6374 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
6375 These patterns are like their @code{sync_old_@var{op}} counterparts,
6376 except that they return the value that exists in the memory location
6377 after the operation, rather than before the operation.
6379 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
6380 @item @samp{sync_lock_test_and_set@var{mode}}
6381 This pattern takes two forms, based on the capabilities of the target.
6382 In either case, operand 0 is the result of the operand, operand 1 is
6383 the memory on which the atomic operation is performed, and operand 2
6384 is the value to set in the lock.
6386 In the ideal case, this operation is an atomic exchange operation, in
6387 which the previous value in memory operand is copied into the result
6388 operand, and the value operand is stored in the memory operand.
6390 For less capable targets, any value operand that is not the constant 1
6391 should be rejected with @code{FAIL}. In this case the target may use
6392 an atomic test-and-set bit operation. The result operand should contain
6393 1 if the bit was previously set and 0 if the bit was previously clear.
6394 The true contents of the memory operand are implementation defined.
6396 This pattern must issue any memory barrier instructions such that the
6397 pattern as a whole acts as an acquire barrier, that is all memory
6398 operations after the pattern do not occur until the lock is acquired.
6400 If this pattern is not defined, the operation will be constructed from
6401 a compare-and-swap operation, if defined.
6403 @cindex @code{sync_lock_release@var{mode}} instruction pattern
6404 @item @samp{sync_lock_release@var{mode}}
6405 This pattern, if defined, releases a lock set by
6406 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
6407 that contains the lock; operand 1 is the value to store in the lock.
6409 If the target doesn't implement full semantics for
6410 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
6411 the constant 0 should be rejected with @code{FAIL}, and the true contents
6412 of the memory operand are implementation defined.
6414 This pattern must issue any memory barrier instructions such that the
6415 pattern as a whole acts as a release barrier, that is the lock is
6416 released only after all previous memory operations have completed.
6418 If this pattern is not defined, then a @code{memory_barrier} pattern
6419 will be emitted, followed by a store of the value to the memory operand.
6421 @cindex @code{atomic_compare_and_swap@var{mode}} instruction pattern
6422 @item @samp{atomic_compare_and_swap@var{mode}}
6423 This pattern, if defined, emits code for an atomic compare-and-swap
6424 operation with memory model semantics. Operand 2 is the memory on which
6425 the atomic operation is performed. Operand 0 is an output operand which
6426 is set to true or false based on whether the operation succeeded. Operand
6427 1 is an output operand which is set to the contents of the memory before
6428 the operation was attempted. Operand 3 is the value that is expected to
6429 be in memory. Operand 4 is the value to put in memory if the expected
6430 value is found there. Operand 5 is set to 1 if this compare and swap is to
6431 be treated as a weak operation. Operand 6 is the memory model to be used
6432 if the operation is a success. Operand 7 is the memory model to be used
6433 if the operation fails.
6435 If memory referred to in operand 2 contains the value in operand 3, then
6436 operand 4 is stored in memory pointed to by operand 2 and fencing based on
6437 the memory model in operand 6 is issued.
6439 If memory referred to in operand 2 does not contain the value in operand 3,
6440 then fencing based on the memory model in operand 7 is issued.
6442 If a target does not support weak compare-and-swap operations, or the port
6443 elects not to implement weak operations, the argument in operand 5 can be
6444 ignored. Note a strong implementation must be provided.
6446 If this pattern is not provided, the @code{__atomic_compare_exchange}
6447 built-in functions will utilize the legacy @code{sync_compare_and_swap}
6448 pattern with an @code{__ATOMIC_SEQ_CST} memory model.
6450 @cindex @code{atomic_load@var{mode}} instruction pattern
6451 @item @samp{atomic_load@var{mode}}
6452 This pattern implements an atomic load operation with memory model
6453 semantics. Operand 1 is the memory address being loaded from. Operand 0
6454 is the result of the load. Operand 2 is the memory model to be used for
6457 If not present, the @code{__atomic_load} built-in function will either
6458 resort to a normal load with memory barriers, or a compare-and-swap
6459 operation if a normal load would not be atomic.
6461 @cindex @code{atomic_store@var{mode}} instruction pattern
6462 @item @samp{atomic_store@var{mode}}
6463 This pattern implements an atomic store operation with memory model
6464 semantics. Operand 0 is the memory address being stored to. Operand 1
6465 is the value to be written. Operand 2 is the memory model to be used for
6468 If not present, the @code{__atomic_store} built-in function will attempt to
6469 perform a normal store and surround it with any required memory fences. If
6470 the store would not be atomic, then an @code{__atomic_exchange} is
6471 attempted with the result being ignored.
6473 @cindex @code{atomic_exchange@var{mode}} instruction pattern
6474 @item @samp{atomic_exchange@var{mode}}
6475 This pattern implements an atomic exchange operation with memory model
6476 semantics. Operand 1 is the memory location the operation is performed on.
6477 Operand 0 is an output operand which is set to the original value contained
6478 in the memory pointed to by operand 1. Operand 2 is the value to be
6479 stored. Operand 3 is the memory model to be used.
6481 If this pattern is not present, the built-in function
6482 @code{__atomic_exchange} will attempt to preform the operation with a
6483 compare and swap loop.
6485 @cindex @code{atomic_add@var{mode}} instruction pattern
6486 @cindex @code{atomic_sub@var{mode}} instruction pattern
6487 @cindex @code{atomic_or@var{mode}} instruction pattern
6488 @cindex @code{atomic_and@var{mode}} instruction pattern
6489 @cindex @code{atomic_xor@var{mode}} instruction pattern
6490 @cindex @code{atomic_nand@var{mode}} instruction pattern
6491 @item @samp{atomic_add@var{mode}}, @samp{atomic_sub@var{mode}}
6492 @itemx @samp{atomic_or@var{mode}}, @samp{atomic_and@var{mode}}
6493 @itemx @samp{atomic_xor@var{mode}}, @samp{atomic_nand@var{mode}}
6494 These patterns emit code for an atomic operation on memory with memory
6495 model semantics. Operand 0 is the memory on which the atomic operation is
6496 performed. Operand 1 is the second operand to the binary operator.
6497 Operand 2 is the memory model to be used by the operation.
6499 If these patterns are not defined, attempts will be made to use legacy
6500 @code{sync} patterns, or equivalent patterns which return a result. If
6501 none of these are available a compare-and-swap loop will be used.
6503 @cindex @code{atomic_fetch_add@var{mode}} instruction pattern
6504 @cindex @code{atomic_fetch_sub@var{mode}} instruction pattern
6505 @cindex @code{atomic_fetch_or@var{mode}} instruction pattern
6506 @cindex @code{atomic_fetch_and@var{mode}} instruction pattern
6507 @cindex @code{atomic_fetch_xor@var{mode}} instruction pattern
6508 @cindex @code{atomic_fetch_nand@var{mode}} instruction pattern
6509 @item @samp{atomic_fetch_add@var{mode}}, @samp{atomic_fetch_sub@var{mode}}
6510 @itemx @samp{atomic_fetch_or@var{mode}}, @samp{atomic_fetch_and@var{mode}}
6511 @itemx @samp{atomic_fetch_xor@var{mode}}, @samp{atomic_fetch_nand@var{mode}}
6512 These patterns emit code for an atomic operation on memory with memory
6513 model semantics, and return the original value. Operand 0 is an output
6514 operand which contains the value of the memory location before the
6515 operation was performed. Operand 1 is the memory on which the atomic
6516 operation is performed. Operand 2 is the second operand to the binary
6517 operator. Operand 3 is the memory model to be used by the operation.
6519 If these patterns are not defined, attempts will be made to use legacy
6520 @code{sync} patterns. If none of these are available a compare-and-swap
6523 @cindex @code{atomic_add_fetch@var{mode}} instruction pattern
6524 @cindex @code{atomic_sub_fetch@var{mode}} instruction pattern
6525 @cindex @code{atomic_or_fetch@var{mode}} instruction pattern
6526 @cindex @code{atomic_and_fetch@var{mode}} instruction pattern
6527 @cindex @code{atomic_xor_fetch@var{mode}} instruction pattern
6528 @cindex @code{atomic_nand_fetch@var{mode}} instruction pattern
6529 @item @samp{atomic_add_fetch@var{mode}}, @samp{atomic_sub_fetch@var{mode}}
6530 @itemx @samp{atomic_or_fetch@var{mode}}, @samp{atomic_and_fetch@var{mode}}
6531 @itemx @samp{atomic_xor_fetch@var{mode}}, @samp{atomic_nand_fetch@var{mode}}
6532 These patterns emit code for an atomic operation on memory with memory
6533 model semantics and return the result after the operation is performed.
6534 Operand 0 is an output operand which contains the value after the
6535 operation. Operand 1 is the memory on which the atomic operation is
6536 performed. Operand 2 is the second operand to the binary operator.
6537 Operand 3 is the memory model to be used by the operation.
6539 If these patterns are not defined, attempts will be made to use legacy
6540 @code{sync} patterns, or equivalent patterns which return the result before
6541 the operation followed by the arithmetic operation required to produce the
6542 result. If none of these are available a compare-and-swap loop will be
6545 @cindex @code{atomic_test_and_set} instruction pattern
6546 @item @samp{atomic_test_and_set}
6547 This pattern emits code for @code{__builtin_atomic_test_and_set}.
6548 Operand 0 is an output operand which is set to true if the previous
6549 previous contents of the byte was "set", and false otherwise. Operand 1
6550 is the @code{QImode} memory to be modified. Operand 2 is the memory
6553 The specific value that defines "set" is implementation defined, and
6554 is normally based on what is performed by the native atomic test and set
6557 @cindex @code{mem_thread_fence@var{mode}} instruction pattern
6558 @item @samp{mem_thread_fence@var{mode}}
6559 This pattern emits code required to implement a thread fence with
6560 memory model semantics. Operand 0 is the memory model to be used.
6562 If this pattern is not specified, all memory models except
6563 @code{__ATOMIC_RELAXED} will result in issuing a @code{sync_synchronize}
6566 @cindex @code{mem_signal_fence@var{mode}} instruction pattern
6567 @item @samp{mem_signal_fence@var{mode}}
6568 This pattern emits code required to implement a signal fence with
6569 memory model semantics. Operand 0 is the memory model to be used.
6571 This pattern should impact the compiler optimizers the same way that
6572 mem_signal_fence does, but it does not need to issue any barrier
6575 If this pattern is not specified, all memory models except
6576 @code{__ATOMIC_RELAXED} will result in issuing a @code{sync_synchronize}
6579 @cindex @code{get_thread_pointer@var{mode}} instruction pattern
6580 @cindex @code{set_thread_pointer@var{mode}} instruction pattern
6581 @item @samp{get_thread_pointer@var{mode}}
6582 @itemx @samp{set_thread_pointer@var{mode}}
6583 These patterns emit code that reads/sets the TLS thread pointer. Currently,
6584 these are only needed if the target needs to support the
6585 @code{__builtin_thread_pointer} and @code{__builtin_set_thread_pointer}
6588 The get/set patterns have a single output/input operand respectively,
6589 with @var{mode} intended to be @code{Pmode}.
6591 @cindex @code{stack_protect_set} instruction pattern
6592 @item @samp{stack_protect_set}
6593 This pattern, if defined, moves a @code{ptr_mode} value from the memory
6594 in operand 1 to the memory in operand 0 without leaving the value in
6595 a register afterward. This is to avoid leaking the value some place
6596 that an attacker might use to rewrite the stack guard slot after
6597 having clobbered it.
6599 If this pattern is not defined, then a plain move pattern is generated.
6601 @cindex @code{stack_protect_test} instruction pattern
6602 @item @samp{stack_protect_test}
6603 This pattern, if defined, compares a @code{ptr_mode} value from the
6604 memory in operand 1 with the memory in operand 0 without leaving the
6605 value in a register afterward and branches to operand 2 if the values
6608 If this pattern is not defined, then a plain compare pattern and
6609 conditional branch pattern is used.
6611 @cindex @code{clear_cache} instruction pattern
6612 @item @samp{clear_cache}
6613 This pattern, if defined, flushes the instruction cache for a region of
6614 memory. The region is bounded to by the Pmode pointers in operand 0
6615 inclusive and operand 1 exclusive.
6617 If this pattern is not defined, a call to the library function
6618 @code{__clear_cache} is used.
6623 @c Each of the following nodes are wrapped in separate
6624 @c "@ifset INTERNALS" to work around memory limits for the default
6625 @c configuration in older tetex distributions. Known to not work:
6626 @c tetex-1.0.7, known to work: tetex-2.0.2.
6628 @node Pattern Ordering
6629 @section When the Order of Patterns Matters
6630 @cindex Pattern Ordering
6631 @cindex Ordering of Patterns
6633 Sometimes an insn can match more than one instruction pattern. Then the
6634 pattern that appears first in the machine description is the one used.
6635 Therefore, more specific patterns (patterns that will match fewer things)
6636 and faster instructions (those that will produce better code when they
6637 do match) should usually go first in the description.
6639 In some cases the effect of ordering the patterns can be used to hide
6640 a pattern when it is not valid. For example, the 68000 has an
6641 instruction for converting a fullword to floating point and another
6642 for converting a byte to floating point. An instruction converting
6643 an integer to floating point could match either one. We put the
6644 pattern to convert the fullword first to make sure that one will
6645 be used rather than the other. (Otherwise a large integer might
6646 be generated as a single-byte immediate quantity, which would not work.)
6647 Instead of using this pattern ordering it would be possible to make the
6648 pattern for convert-a-byte smart enough to deal properly with any
6653 @node Dependent Patterns
6654 @section Interdependence of Patterns
6655 @cindex Dependent Patterns
6656 @cindex Interdependence of Patterns
6658 In some cases machines support instructions identical except for the
6659 machine mode of one or more operands. For example, there may be
6660 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
6664 (set (match_operand:SI 0 @dots{})
6665 (extend:SI (match_operand:HI 1 @dots{})))
6667 (set (match_operand:SI 0 @dots{})
6668 (extend:SI (match_operand:QI 1 @dots{})))
6672 Constant integers do not specify a machine mode, so an instruction to
6673 extend a constant value could match either pattern. The pattern it
6674 actually will match is the one that appears first in the file. For correct
6675 results, this must be the one for the widest possible mode (@code{HImode},
6676 here). If the pattern matches the @code{QImode} instruction, the results
6677 will be incorrect if the constant value does not actually fit that mode.
6679 Such instructions to extend constants are rarely generated because they are
6680 optimized away, but they do occasionally happen in nonoptimized
6683 If a constraint in a pattern allows a constant, the reload pass may
6684 replace a register with a constant permitted by the constraint in some
6685 cases. Similarly for memory references. Because of this substitution,
6686 you should not provide separate patterns for increment and decrement
6687 instructions. Instead, they should be generated from the same pattern
6688 that supports register-register add insns by examining the operands and
6689 generating the appropriate machine instruction.
6694 @section Defining Jump Instruction Patterns
6695 @cindex jump instruction patterns
6696 @cindex defining jump instruction patterns
6698 GCC does not assume anything about how the machine realizes jumps.
6699 The machine description should define a single pattern, usually
6700 a @code{define_expand}, which expands to all the required insns.
6702 Usually, this would be a comparison insn to set the condition code
6703 and a separate branch insn testing the condition code and branching
6704 or not according to its value. For many machines, however,
6705 separating compares and branches is limiting, which is why the
6706 more flexible approach with one @code{define_expand} is used in GCC.
6707 The machine description becomes clearer for architectures that
6708 have compare-and-branch instructions but no condition code. It also
6709 works better when different sets of comparison operators are supported
6710 by different kinds of conditional branches (e.g. integer vs. floating-point),
6711 or by conditional branches with respect to conditional stores.
6713 Two separate insns are always used if the machine description represents
6714 a condition code register using the legacy RTL expression @code{(cc0)},
6715 and on most machines that use a separate condition code register
6716 (@pxref{Condition Code}). For machines that use @code{(cc0)}, in
6717 fact, the set and use of the condition code must be separate and
6718 adjacent@footnote{@code{note} insns can separate them, though.}, thus
6719 allowing flags in @code{cc_status} to be used (@pxref{Condition Code}) and
6720 so that the comparison and branch insns could be located from each other
6721 by using the functions @code{prev_cc0_setter} and @code{next_cc0_user}.
6723 Even in this case having a single entry point for conditional branches
6724 is advantageous, because it handles equally well the case where a single
6725 comparison instruction records the results of both signed and unsigned
6726 comparison of the given operands (with the branch insns coming in distinct
6727 signed and unsigned flavors) as in the x86 or SPARC, and the case where
6728 there are distinct signed and unsigned compare instructions and only
6729 one set of conditional branch instructions as in the PowerPC.
6733 @node Looping Patterns
6734 @section Defining Looping Instruction Patterns
6735 @cindex looping instruction patterns
6736 @cindex defining looping instruction patterns
6738 Some machines have special jump instructions that can be utilized to
6739 make loops more efficient. A common example is the 68000 @samp{dbra}
6740 instruction which performs a decrement of a register and a branch if the
6741 result was greater than zero. Other machines, in particular digital
6742 signal processors (DSPs), have special block repeat instructions to
6743 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
6744 DSPs have a block repeat instruction that loads special registers to
6745 mark the top and end of a loop and to count the number of loop
6746 iterations. This avoids the need for fetching and executing a
6747 @samp{dbra}-like instruction and avoids pipeline stalls associated with
6750 GCC has three special named patterns to support low overhead looping.
6751 They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
6752 and @samp{doloop_end}. The first pattern,
6753 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
6754 generation but may be emitted during the instruction combination phase.
6755 This requires the assistance of the loop optimizer, using information
6756 collected during strength reduction, to reverse a loop to count down to
6757 zero. Some targets also require the loop optimizer to add a
6758 @code{REG_NONNEG} note to indicate that the iteration count is always
6759 positive. This is needed if the target performs a signed loop
6760 termination test. For example, the 68000 uses a pattern similar to the
6761 following for its @code{dbra} instruction:
6765 (define_insn "decrement_and_branch_until_zero"
6768 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6771 (label_ref (match_operand 1 "" ""))
6774 (plus:SI (match_dup 0)
6776 "find_reg_note (insn, REG_NONNEG, 0)"
6781 Note that since the insn is both a jump insn and has an output, it must
6782 deal with its own reloads, hence the `m' constraints. Also note that
6783 since this insn is generated by the instruction combination phase
6784 combining two sequential insns together into an implicit parallel insn,
6785 the iteration counter needs to be biased by the same amount as the
6786 decrement operation, in this case @minus{}1. Note that the following similar
6787 pattern will not be matched by the combiner.
6791 (define_insn "decrement_and_branch_until_zero"
6794 (ge (match_operand:SI 0 "general_operand" "+d*am")
6796 (label_ref (match_operand 1 "" ""))
6799 (plus:SI (match_dup 0)
6801 "find_reg_note (insn, REG_NONNEG, 0)"
6806 The other two special looping patterns, @samp{doloop_begin} and
6807 @samp{doloop_end}, are emitted by the loop optimizer for certain
6808 well-behaved loops with a finite number of loop iterations using
6809 information collected during strength reduction.
6811 The @samp{doloop_end} pattern describes the actual looping instruction
6812 (or the implicit looping operation) and the @samp{doloop_begin} pattern
6813 is an optional companion pattern that can be used for initialization
6814 needed for some low-overhead looping instructions.
6816 Note that some machines require the actual looping instruction to be
6817 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
6818 the true RTL for a looping instruction at the top of the loop can cause
6819 problems with flow analysis. So instead, a dummy @code{doloop} insn is
6820 emitted at the end of the loop. The machine dependent reorg pass checks
6821 for the presence of this @code{doloop} insn and then searches back to
6822 the top of the loop, where it inserts the true looping insn (provided
6823 there are no instructions in the loop which would cause problems). Any
6824 additional labels can be emitted at this point. In addition, if the
6825 desired special iteration counter register was not allocated, this
6826 machine dependent reorg pass could emit a traditional compare and jump
6829 The essential difference between the
6830 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
6831 patterns is that the loop optimizer allocates an additional pseudo
6832 register for the latter as an iteration counter. This pseudo register
6833 cannot be used within the loop (i.e., general induction variables cannot
6834 be derived from it), however, in many cases the loop induction variable
6835 may become redundant and removed by the flow pass.
6840 @node Insn Canonicalizations
6841 @section Canonicalization of Instructions
6842 @cindex canonicalization of instructions
6843 @cindex insn canonicalization
6845 There are often cases where multiple RTL expressions could represent an
6846 operation performed by a single machine instruction. This situation is
6847 most commonly encountered with logical, branch, and multiply-accumulate
6848 instructions. In such cases, the compiler attempts to convert these
6849 multiple RTL expressions into a single canonical form to reduce the
6850 number of insn patterns required.
6852 In addition to algebraic simplifications, following canonicalizations
6857 For commutative and comparison operators, a constant is always made the
6858 second operand. If a machine only supports a constant as the second
6859 operand, only patterns that match a constant in the second operand need
6863 For associative operators, a sequence of operators will always chain
6864 to the left; for instance, only the left operand of an integer @code{plus}
6865 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
6866 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
6867 @code{umax} are associative when applied to integers, and sometimes to
6871 @cindex @code{neg}, canonicalization of
6872 @cindex @code{not}, canonicalization of
6873 @cindex @code{mult}, canonicalization of
6874 @cindex @code{plus}, canonicalization of
6875 @cindex @code{minus}, canonicalization of
6876 For these operators, if only one operand is a @code{neg}, @code{not},
6877 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
6881 In combinations of @code{neg}, @code{mult}, @code{plus}, and
6882 @code{minus}, the @code{neg} operations (if any) will be moved inside
6883 the operations as far as possible. For instance,
6884 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
6885 @code{(plus (mult (neg B) C) A)} is canonicalized as
6886 @code{(minus A (mult B C))}.
6888 @cindex @code{compare}, canonicalization of
6890 For the @code{compare} operator, a constant is always the second operand
6891 if the first argument is a condition code register or @code{(cc0)}.
6894 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
6895 @code{minus} is made the first operand under the same conditions as
6899 @code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to
6900 @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead
6904 @code{(minus @var{x} (const_int @var{n}))} is converted to
6905 @code{(plus @var{x} (const_int @var{-n}))}.
6908 Within address computations (i.e., inside @code{mem}), a left shift is
6909 converted into the appropriate multiplication by a power of two.
6911 @cindex @code{ior}, canonicalization of
6912 @cindex @code{and}, canonicalization of
6913 @cindex De Morgan's law
6915 De Morgan's Law is used to move bitwise negation inside a bitwise
6916 logical-and or logical-or operation. If this results in only one
6917 operand being a @code{not} expression, it will be the first one.
6919 A machine that has an instruction that performs a bitwise logical-and of one
6920 operand with the bitwise negation of the other should specify the pattern
6921 for that instruction as
6925 [(set (match_operand:@var{m} 0 @dots{})
6926 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
6927 (match_operand:@var{m} 2 @dots{})))]
6933 Similarly, a pattern for a ``NAND'' instruction should be written
6937 [(set (match_operand:@var{m} 0 @dots{})
6938 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
6939 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
6944 In both cases, it is not necessary to include patterns for the many
6945 logically equivalent RTL expressions.
6947 @cindex @code{xor}, canonicalization of
6949 The only possible RTL expressions involving both bitwise exclusive-or
6950 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
6951 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
6954 The sum of three items, one of which is a constant, will only appear in
6958 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
6961 @cindex @code{zero_extract}, canonicalization of
6962 @cindex @code{sign_extract}, canonicalization of
6964 Equality comparisons of a group of bits (usually a single bit) with zero
6965 will be written using @code{zero_extract} rather than the equivalent
6966 @code{and} or @code{sign_extract} operations.
6968 @cindex @code{mult}, canonicalization of
6970 @code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x})
6971 (sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1}
6972 (sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and likewise
6973 for @code{zero_extend}.
6976 @code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2}
6977 @var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted
6978 to @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2}
6979 @var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for
6980 patterns using @code{zero_extend} and @code{lshiftrt}. If the second
6981 operand of @code{mult} is also a shift, then that is extended also.
6982 This transformation is only applied when it can be proven that the
6983 original operation had sufficient precision to prevent overflow.
6987 Further canonicalization rules are defined in the function
6988 @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
6992 @node Expander Definitions
6993 @section Defining RTL Sequences for Code Generation
6994 @cindex expander definitions
6995 @cindex code generation RTL sequences
6996 @cindex defining RTL sequences for code generation
6998 On some target machines, some standard pattern names for RTL generation
6999 cannot be handled with single insn, but a sequence of RTL insns can
7000 represent them. For these target machines, you can write a
7001 @code{define_expand} to specify how to generate the sequence of RTL@.
7003 @findex define_expand
7004 A @code{define_expand} is an RTL expression that looks almost like a
7005 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
7006 only for RTL generation and it can produce more than one RTL insn.
7008 A @code{define_expand} RTX has four operands:
7012 The name. Each @code{define_expand} must have a name, since the only
7013 use for it is to refer to it by name.
7016 The RTL template. This is a vector of RTL expressions representing
7017 a sequence of separate instructions. Unlike @code{define_insn}, there
7018 is no implicit surrounding @code{PARALLEL}.
7021 The condition, a string containing a C expression. This expression is
7022 used to express how the availability of this pattern depends on
7023 subclasses of target machine, selected by command-line options when GCC
7024 is run. This is just like the condition of a @code{define_insn} that
7025 has a standard name. Therefore, the condition (if present) may not
7026 depend on the data in the insn being matched, but only the
7027 target-machine-type flags. The compiler needs to test these conditions
7028 during initialization in order to learn exactly which named instructions
7029 are available in a particular run.
7032 The preparation statements, a string containing zero or more C
7033 statements which are to be executed before RTL code is generated from
7036 Usually these statements prepare temporary registers for use as
7037 internal operands in the RTL template, but they can also generate RTL
7038 insns directly by calling routines such as @code{emit_insn}, etc.
7039 Any such insns precede the ones that come from the RTL template.
7042 Optionally, a vector containing the values of attributes. @xref{Insn
7046 Every RTL insn emitted by a @code{define_expand} must match some
7047 @code{define_insn} in the machine description. Otherwise, the compiler
7048 will crash when trying to generate code for the insn or trying to optimize
7051 The RTL template, in addition to controlling generation of RTL insns,
7052 also describes the operands that need to be specified when this pattern
7053 is used. In particular, it gives a predicate for each operand.
7055 A true operand, which needs to be specified in order to generate RTL from
7056 the pattern, should be described with a @code{match_operand} in its first
7057 occurrence in the RTL template. This enters information on the operand's
7058 predicate into the tables that record such things. GCC uses the
7059 information to preload the operand into a register if that is required for
7060 valid RTL code. If the operand is referred to more than once, subsequent
7061 references should use @code{match_dup}.
7063 The RTL template may also refer to internal ``operands'' which are
7064 temporary registers or labels used only within the sequence made by the
7065 @code{define_expand}. Internal operands are substituted into the RTL
7066 template with @code{match_dup}, never with @code{match_operand}. The
7067 values of the internal operands are not passed in as arguments by the
7068 compiler when it requests use of this pattern. Instead, they are computed
7069 within the pattern, in the preparation statements. These statements
7070 compute the values and store them into the appropriate elements of
7071 @code{operands} so that @code{match_dup} can find them.
7073 There are two special macros defined for use in the preparation statements:
7074 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
7081 Use the @code{DONE} macro to end RTL generation for the pattern. The
7082 only RTL insns resulting from the pattern on this occasion will be
7083 those already emitted by explicit calls to @code{emit_insn} within the
7084 preparation statements; the RTL template will not be generated.
7088 Make the pattern fail on this occasion. When a pattern fails, it means
7089 that the pattern was not truly available. The calling routines in the
7090 compiler will try other strategies for code generation using other patterns.
7092 Failure is currently supported only for binary (addition, multiplication,
7093 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
7097 If the preparation falls through (invokes neither @code{DONE} nor
7098 @code{FAIL}), then the @code{define_expand} acts like a
7099 @code{define_insn} in that the RTL template is used to generate the
7102 The RTL template is not used for matching, only for generating the
7103 initial insn list. If the preparation statement always invokes
7104 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
7105 list of operands, such as this example:
7109 (define_expand "addsi3"
7110 [(match_operand:SI 0 "register_operand" "")
7111 (match_operand:SI 1 "register_operand" "")
7112 (match_operand:SI 2 "register_operand" "")]
7118 handle_add (operands[0], operands[1], operands[2]);
7124 Here is an example, the definition of left-shift for the SPUR chip:
7128 (define_expand "ashlsi3"
7129 [(set (match_operand:SI 0 "register_operand" "")
7133 (match_operand:SI 1 "register_operand" "")
7134 (match_operand:SI 2 "nonmemory_operand" "")))]
7143 if (GET_CODE (operands[2]) != CONST_INT
7144 || (unsigned) INTVAL (operands[2]) > 3)
7151 This example uses @code{define_expand} so that it can generate an RTL insn
7152 for shifting when the shift-count is in the supported range of 0 to 3 but
7153 fail in other cases where machine insns aren't available. When it fails,
7154 the compiler tries another strategy using different patterns (such as, a
7157 If the compiler were able to handle nontrivial condition-strings in
7158 patterns with names, then it would be possible to use a
7159 @code{define_insn} in that case. Here is another case (zero-extension
7160 on the 68000) which makes more use of the power of @code{define_expand}:
7163 (define_expand "zero_extendhisi2"
7164 [(set (match_operand:SI 0 "general_operand" "")
7166 (set (strict_low_part
7170 (match_operand:HI 1 "general_operand" ""))]
7172 "operands[1] = make_safe_from (operands[1], operands[0]);")
7176 @findex make_safe_from
7177 Here two RTL insns are generated, one to clear the entire output operand
7178 and the other to copy the input operand into its low half. This sequence
7179 is incorrect if the input operand refers to [the old value of] the output
7180 operand, so the preparation statement makes sure this isn't so. The
7181 function @code{make_safe_from} copies the @code{operands[1]} into a
7182 temporary register if it refers to @code{operands[0]}. It does this
7183 by emitting another RTL insn.
7185 Finally, a third example shows the use of an internal operand.
7186 Zero-extension on the SPUR chip is done by @code{and}-ing the result
7187 against a halfword mask. But this mask cannot be represented by a
7188 @code{const_int} because the constant value is too large to be legitimate
7189 on this machine. So it must be copied into a register with
7190 @code{force_reg} and then the register used in the @code{and}.
7193 (define_expand "zero_extendhisi2"
7194 [(set (match_operand:SI 0 "register_operand" "")
7196 (match_operand:HI 1 "register_operand" "")
7201 = force_reg (SImode, GEN_INT (65535)); ")
7204 @emph{Note:} If the @code{define_expand} is used to serve a
7205 standard binary or unary arithmetic operation or a bit-field operation,
7206 then the last insn it generates must not be a @code{code_label},
7207 @code{barrier} or @code{note}. It must be an @code{insn},
7208 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
7209 at the end, emit an insn to copy the result of the operation into
7210 itself. Such an insn will generate no code, but it can avoid problems
7215 @node Insn Splitting
7216 @section Defining How to Split Instructions
7217 @cindex insn splitting
7218 @cindex instruction splitting
7219 @cindex splitting instructions
7221 There are two cases where you should specify how to split a pattern
7222 into multiple insns. On machines that have instructions requiring
7223 delay slots (@pxref{Delay Slots}) or that have instructions whose
7224 output is not available for multiple cycles (@pxref{Processor pipeline
7225 description}), the compiler phases that optimize these cases need to
7226 be able to move insns into one-instruction delay slots. However, some
7227 insns may generate more than one machine instruction. These insns
7228 cannot be placed into a delay slot.
7230 Often you can rewrite the single insn as a list of individual insns,
7231 each corresponding to one machine instruction. The disadvantage of
7232 doing so is that it will cause the compilation to be slower and require
7233 more space. If the resulting insns are too complex, it may also
7234 suppress some optimizations. The compiler splits the insn if there is a
7235 reason to believe that it might improve instruction or delay slot
7238 The insn combiner phase also splits putative insns. If three insns are
7239 merged into one insn with a complex expression that cannot be matched by
7240 some @code{define_insn} pattern, the combiner phase attempts to split
7241 the complex pattern into two insns that are recognized. Usually it can
7242 break the complex pattern into two patterns by splitting out some
7243 subexpression. However, in some other cases, such as performing an
7244 addition of a large constant in two insns on a RISC machine, the way to
7245 split the addition into two insns is machine-dependent.
7247 @findex define_split
7248 The @code{define_split} definition tells the compiler how to split a
7249 complex insn into several simpler insns. It looks like this:
7253 [@var{insn-pattern}]
7255 [@var{new-insn-pattern-1}
7256 @var{new-insn-pattern-2}
7258 "@var{preparation-statements}")
7261 @var{insn-pattern} is a pattern that needs to be split and
7262 @var{condition} is the final condition to be tested, as in a
7263 @code{define_insn}. When an insn matching @var{insn-pattern} and
7264 satisfying @var{condition} is found, it is replaced in the insn list
7265 with the insns given by @var{new-insn-pattern-1},
7266 @var{new-insn-pattern-2}, etc.
7268 The @var{preparation-statements} are similar to those statements that
7269 are specified for @code{define_expand} (@pxref{Expander Definitions})
7270 and are executed before the new RTL is generated to prepare for the
7271 generated code or emit some insns whose pattern is not fixed. Unlike
7272 those in @code{define_expand}, however, these statements must not
7273 generate any new pseudo-registers. Once reload has completed, they also
7274 must not allocate any space in the stack frame.
7276 Patterns are matched against @var{insn-pattern} in two different
7277 circumstances. If an insn needs to be split for delay slot scheduling
7278 or insn scheduling, the insn is already known to be valid, which means
7279 that it must have been matched by some @code{define_insn} and, if
7280 @code{reload_completed} is nonzero, is known to satisfy the constraints
7281 of that @code{define_insn}. In that case, the new insn patterns must
7282 also be insns that are matched by some @code{define_insn} and, if
7283 @code{reload_completed} is nonzero, must also satisfy the constraints
7284 of those definitions.
7286 As an example of this usage of @code{define_split}, consider the following
7287 example from @file{a29k.md}, which splits a @code{sign_extend} from
7288 @code{HImode} to @code{SImode} into a pair of shift insns:
7292 [(set (match_operand:SI 0 "gen_reg_operand" "")
7293 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
7296 (ashift:SI (match_dup 1)
7299 (ashiftrt:SI (match_dup 0)
7302 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
7305 When the combiner phase tries to split an insn pattern, it is always the
7306 case that the pattern is @emph{not} matched by any @code{define_insn}.
7307 The combiner pass first tries to split a single @code{set} expression
7308 and then the same @code{set} expression inside a @code{parallel}, but
7309 followed by a @code{clobber} of a pseudo-reg to use as a scratch
7310 register. In these cases, the combiner expects exactly two new insn
7311 patterns to be generated. It will verify that these patterns match some
7312 @code{define_insn} definitions, so you need not do this test in the
7313 @code{define_split} (of course, there is no point in writing a
7314 @code{define_split} that will never produce insns that match).
7316 Here is an example of this use of @code{define_split}, taken from
7321 [(set (match_operand:SI 0 "gen_reg_operand" "")
7322 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
7323 (match_operand:SI 2 "non_add_cint_operand" "")))]
7325 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
7326 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
7329 int low = INTVAL (operands[2]) & 0xffff;
7330 int high = (unsigned) INTVAL (operands[2]) >> 16;
7333 high++, low |= 0xffff0000;
7335 operands[3] = GEN_INT (high << 16);
7336 operands[4] = GEN_INT (low);
7340 Here the predicate @code{non_add_cint_operand} matches any
7341 @code{const_int} that is @emph{not} a valid operand of a single add
7342 insn. The add with the smaller displacement is written so that it
7343 can be substituted into the address of a subsequent operation.
7345 An example that uses a scratch register, from the same file, generates
7346 an equality comparison of a register and a large constant:
7350 [(set (match_operand:CC 0 "cc_reg_operand" "")
7351 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
7352 (match_operand:SI 2 "non_short_cint_operand" "")))
7353 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
7354 "find_single_use (operands[0], insn, 0)
7355 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
7356 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
7357 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
7358 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
7361 /* @r{Get the constant we are comparing against, C, and see what it
7362 looks like sign-extended to 16 bits. Then see what constant
7363 could be XOR'ed with C to get the sign-extended value.} */
7365 int c = INTVAL (operands[2]);
7366 int sextc = (c << 16) >> 16;
7367 int xorv = c ^ sextc;
7369 operands[4] = GEN_INT (xorv);
7370 operands[5] = GEN_INT (sextc);
7374 To avoid confusion, don't write a single @code{define_split} that
7375 accepts some insns that match some @code{define_insn} as well as some
7376 insns that don't. Instead, write two separate @code{define_split}
7377 definitions, one for the insns that are valid and one for the insns that
7380 The splitter is allowed to split jump instructions into sequence of
7381 jumps or create new jumps in while splitting non-jump instructions. As
7382 the central flowgraph and branch prediction information needs to be updated,
7383 several restriction apply.
7385 Splitting of jump instruction into sequence that over by another jump
7386 instruction is always valid, as compiler expect identical behavior of new
7387 jump. When new sequence contains multiple jump instructions or new labels,
7388 more assistance is needed. Splitter is required to create only unconditional
7389 jumps, or simple conditional jump instructions. Additionally it must attach a
7390 @code{REG_BR_PROB} note to each conditional jump. A global variable
7391 @code{split_branch_probability} holds the probability of the original branch in case
7392 it was a simple conditional jump, @minus{}1 otherwise. To simplify
7393 recomputing of edge frequencies, the new sequence is required to have only
7394 forward jumps to the newly created labels.
7396 @findex define_insn_and_split
7397 For the common case where the pattern of a define_split exactly matches the
7398 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
7402 (define_insn_and_split
7403 [@var{insn-pattern}]
7405 "@var{output-template}"
7406 "@var{split-condition}"
7407 [@var{new-insn-pattern-1}
7408 @var{new-insn-pattern-2}
7410 "@var{preparation-statements}"
7411 [@var{insn-attributes}])
7415 @var{insn-pattern}, @var{condition}, @var{output-template}, and
7416 @var{insn-attributes} are used as in @code{define_insn}. The
7417 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
7418 in a @code{define_split}. The @var{split-condition} is also used as in
7419 @code{define_split}, with the additional behavior that if the condition starts
7420 with @samp{&&}, the condition used for the split will be the constructed as a
7421 logical ``and'' of the split condition with the insn condition. For example,
7425 (define_insn_and_split "zero_extendhisi2_and"
7426 [(set (match_operand:SI 0 "register_operand" "=r")
7427 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
7428 (clobber (reg:CC 17))]
7429 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
7431 "&& reload_completed"
7432 [(parallel [(set (match_dup 0)
7433 (and:SI (match_dup 0) (const_int 65535)))
7434 (clobber (reg:CC 17))])]
7436 [(set_attr "type" "alu1")])
7440 In this case, the actual split condition will be
7441 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
7443 The @code{define_insn_and_split} construction provides exactly the same
7444 functionality as two separate @code{define_insn} and @code{define_split}
7445 patterns. It exists for compactness, and as a maintenance tool to prevent
7446 having to ensure the two patterns' templates match.
7450 @node Including Patterns
7451 @section Including Patterns in Machine Descriptions.
7452 @cindex insn includes
7455 The @code{include} pattern tells the compiler tools where to
7456 look for patterns that are in files other than in the file
7457 @file{.md}. This is used only at build time and there is no preprocessing allowed.
7471 (include "filestuff")
7475 Where @var{pathname} is a string that specifies the location of the file,
7476 specifies the include file to be in @file{gcc/config/target/filestuff}. The
7477 directory @file{gcc/config/target} is regarded as the default directory.
7480 Machine descriptions may be split up into smaller more manageable subsections
7481 and placed into subdirectories.
7487 (include "BOGUS/filestuff")
7491 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
7493 Specifying an absolute path for the include file such as;
7496 (include "/u2/BOGUS/filestuff")
7499 is permitted but is not encouraged.
7501 @subsection RTL Generation Tool Options for Directory Search
7502 @cindex directory options .md
7503 @cindex options, directory search
7504 @cindex search options
7506 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
7511 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
7516 Add the directory @var{dir} to the head of the list of directories to be
7517 searched for header files. This can be used to override a system machine definition
7518 file, substituting your own version, since these directories are
7519 searched before the default machine description file directories. If you use more than
7520 one @option{-I} option, the directories are scanned in left-to-right
7521 order; the standard default directory come after.
7526 @node Peephole Definitions
7527 @section Machine-Specific Peephole Optimizers
7528 @cindex peephole optimizer definitions
7529 @cindex defining peephole optimizers
7531 In addition to instruction patterns the @file{md} file may contain
7532 definitions of machine-specific peephole optimizations.
7534 The combiner does not notice certain peephole optimizations when the data
7535 flow in the program does not suggest that it should try them. For example,
7536 sometimes two consecutive insns related in purpose can be combined even
7537 though the second one does not appear to use a register computed in the
7538 first one. A machine-specific peephole optimizer can detect such
7541 There are two forms of peephole definitions that may be used. The
7542 original @code{define_peephole} is run at assembly output time to
7543 match insns and substitute assembly text. Use of @code{define_peephole}
7546 A newer @code{define_peephole2} matches insns and substitutes new
7547 insns. The @code{peephole2} pass is run after register allocation
7548 but before scheduling, which may result in much better code for
7549 targets that do scheduling.
7552 * define_peephole:: RTL to Text Peephole Optimizers
7553 * define_peephole2:: RTL to RTL Peephole Optimizers
7558 @node define_peephole
7559 @subsection RTL to Text Peephole Optimizers
7560 @findex define_peephole
7563 A definition looks like this:
7567 [@var{insn-pattern-1}
7568 @var{insn-pattern-2}
7572 "@var{optional-insn-attributes}")
7576 The last string operand may be omitted if you are not using any
7577 machine-specific information in this machine description. If present,
7578 it must obey the same rules as in a @code{define_insn}.
7580 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
7581 consecutive insns. The optimization applies to a sequence of insns when
7582 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
7583 the next, and so on.
7585 Each of the insns matched by a peephole must also match a
7586 @code{define_insn}. Peepholes are checked only at the last stage just
7587 before code generation, and only optionally. Therefore, any insn which
7588 would match a peephole but no @code{define_insn} will cause a crash in code
7589 generation in an unoptimized compilation, or at various optimization
7592 The operands of the insns are matched with @code{match_operands},
7593 @code{match_operator}, and @code{match_dup}, as usual. What is not
7594 usual is that the operand numbers apply to all the insn patterns in the
7595 definition. So, you can check for identical operands in two insns by
7596 using @code{match_operand} in one insn and @code{match_dup} in the
7599 The operand constraints used in @code{match_operand} patterns do not have
7600 any direct effect on the applicability of the peephole, but they will
7601 be validated afterward, so make sure your constraints are general enough
7602 to apply whenever the peephole matches. If the peephole matches
7603 but the constraints are not satisfied, the compiler will crash.
7605 It is safe to omit constraints in all the operands of the peephole; or
7606 you can write constraints which serve as a double-check on the criteria
7609 Once a sequence of insns matches the patterns, the @var{condition} is
7610 checked. This is a C expression which makes the final decision whether to
7611 perform the optimization (we do so if the expression is nonzero). If
7612 @var{condition} is omitted (in other words, the string is empty) then the
7613 optimization is applied to every sequence of insns that matches the
7616 The defined peephole optimizations are applied after register allocation
7617 is complete. Therefore, the peephole definition can check which
7618 operands have ended up in which kinds of registers, just by looking at
7621 @findex prev_active_insn
7622 The way to refer to the operands in @var{condition} is to write
7623 @code{operands[@var{i}]} for operand number @var{i} (as matched by
7624 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
7625 to refer to the last of the insns being matched; use
7626 @code{prev_active_insn} to find the preceding insns.
7628 @findex dead_or_set_p
7629 When optimizing computations with intermediate results, you can use
7630 @var{condition} to match only when the intermediate results are not used
7631 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
7632 @var{op})}, where @var{insn} is the insn in which you expect the value
7633 to be used for the last time (from the value of @code{insn}, together
7634 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
7635 value (from @code{operands[@var{i}]}).
7637 Applying the optimization means replacing the sequence of insns with one
7638 new insn. The @var{template} controls ultimate output of assembler code
7639 for this combined insn. It works exactly like the template of a
7640 @code{define_insn}. Operand numbers in this template are the same ones
7641 used in matching the original sequence of insns.
7643 The result of a defined peephole optimizer does not need to match any of
7644 the insn patterns in the machine description; it does not even have an
7645 opportunity to match them. The peephole optimizer definition itself serves
7646 as the insn pattern to control how the insn is output.
7648 Defined peephole optimizers are run as assembler code is being output,
7649 so the insns they produce are never combined or rearranged in any way.
7651 Here is an example, taken from the 68000 machine description:
7655 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
7656 (set (match_operand:DF 0 "register_operand" "=f")
7657 (match_operand:DF 1 "register_operand" "ad"))]
7658 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
7661 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7663 output_asm_insn ("move.l %1,(sp)", xoperands);
7664 output_asm_insn ("move.l %1,-(sp)", operands);
7665 return "fmove.d (sp)+,%0";
7667 output_asm_insn ("movel %1,sp@@", xoperands);
7668 output_asm_insn ("movel %1,sp@@-", operands);
7669 return "fmoved sp@@+,%0";
7675 The effect of this optimization is to change
7701 If a peephole matches a sequence including one or more jump insns, you must
7702 take account of the flags such as @code{CC_REVERSED} which specify that the
7703 condition codes are represented in an unusual manner. The compiler
7704 automatically alters any ordinary conditional jumps which occur in such
7705 situations, but the compiler cannot alter jumps which have been replaced by
7706 peephole optimizations. So it is up to you to alter the assembler code
7707 that the peephole produces. Supply C code to write the assembler output,
7708 and in this C code check the condition code status flags and change the
7709 assembler code as appropriate.
7712 @var{insn-pattern-1} and so on look @emph{almost} like the second
7713 operand of @code{define_insn}. There is one important difference: the
7714 second operand of @code{define_insn} consists of one or more RTX's
7715 enclosed in square brackets. Usually, there is only one: then the same
7716 action can be written as an element of a @code{define_peephole}. But
7717 when there are multiple actions in a @code{define_insn}, they are
7718 implicitly enclosed in a @code{parallel}. Then you must explicitly
7719 write the @code{parallel}, and the square brackets within it, in the
7720 @code{define_peephole}. Thus, if an insn pattern looks like this,
7723 (define_insn "divmodsi4"
7724 [(set (match_operand:SI 0 "general_operand" "=d")
7725 (div:SI (match_operand:SI 1 "general_operand" "0")
7726 (match_operand:SI 2 "general_operand" "dmsK")))
7727 (set (match_operand:SI 3 "general_operand" "=d")
7728 (mod:SI (match_dup 1) (match_dup 2)))]
7730 "divsl%.l %2,%3:%0")
7734 then the way to mention this insn in a peephole is as follows:
7740 [(set (match_operand:SI 0 "general_operand" "=d")
7741 (div:SI (match_operand:SI 1 "general_operand" "0")
7742 (match_operand:SI 2 "general_operand" "dmsK")))
7743 (set (match_operand:SI 3 "general_operand" "=d")
7744 (mod:SI (match_dup 1) (match_dup 2)))])
7751 @node define_peephole2
7752 @subsection RTL to RTL Peephole Optimizers
7753 @findex define_peephole2
7755 The @code{define_peephole2} definition tells the compiler how to
7756 substitute one sequence of instructions for another sequence,
7757 what additional scratch registers may be needed and what their
7762 [@var{insn-pattern-1}
7763 @var{insn-pattern-2}
7766 [@var{new-insn-pattern-1}
7767 @var{new-insn-pattern-2}
7769 "@var{preparation-statements}")
7772 The definition is almost identical to @code{define_split}
7773 (@pxref{Insn Splitting}) except that the pattern to match is not a
7774 single instruction, but a sequence of instructions.
7776 It is possible to request additional scratch registers for use in the
7777 output template. If appropriate registers are not free, the pattern
7778 will simply not match.
7780 @findex match_scratch
7782 Scratch registers are requested with a @code{match_scratch} pattern at
7783 the top level of the input pattern. The allocated register (initially) will
7784 be dead at the point requested within the original sequence. If the scratch
7785 is used at more than a single point, a @code{match_dup} pattern at the
7786 top level of the input pattern marks the last position in the input sequence
7787 at which the register must be available.
7789 Here is an example from the IA-32 machine description:
7793 [(match_scratch:SI 2 "r")
7794 (parallel [(set (match_operand:SI 0 "register_operand" "")
7795 (match_operator:SI 3 "arith_or_logical_operator"
7797 (match_operand:SI 1 "memory_operand" "")]))
7798 (clobber (reg:CC 17))])]
7799 "! optimize_size && ! TARGET_READ_MODIFY"
7800 [(set (match_dup 2) (match_dup 1))
7801 (parallel [(set (match_dup 0)
7802 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
7803 (clobber (reg:CC 17))])]
7808 This pattern tries to split a load from its use in the hopes that we'll be
7809 able to schedule around the memory load latency. It allocates a single
7810 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
7811 to be live only at the point just before the arithmetic.
7813 A real example requiring extended scratch lifetimes is harder to come by,
7814 so here's a silly made-up example:
7818 [(match_scratch:SI 4 "r")
7819 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
7820 (set (match_operand:SI 2 "" "") (match_dup 1))
7822 (set (match_operand:SI 3 "" "") (match_dup 1))]
7823 "/* @r{determine 1 does not overlap 0 and 2} */"
7824 [(set (match_dup 4) (match_dup 1))
7825 (set (match_dup 0) (match_dup 4))
7826 (set (match_dup 2) (match_dup 4))
7827 (set (match_dup 3) (match_dup 4))]
7832 If we had not added the @code{(match_dup 4)} in the middle of the input
7833 sequence, it might have been the case that the register we chose at the
7834 beginning of the sequence is killed by the first or second @code{set}.
7838 @node Insn Attributes
7839 @section Instruction Attributes
7840 @cindex insn attributes
7841 @cindex instruction attributes
7843 In addition to describing the instruction supported by the target machine,
7844 the @file{md} file also defines a group of @dfn{attributes} and a set of
7845 values for each. Every generated insn is assigned a value for each attribute.
7846 One possible attribute would be the effect that the insn has on the machine's
7847 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
7848 to track the condition codes.
7851 * Defining Attributes:: Specifying attributes and their values.
7852 * Expressions:: Valid expressions for attribute values.
7853 * Tagging Insns:: Assigning attribute values to insns.
7854 * Attr Example:: An example of assigning attributes.
7855 * Insn Lengths:: Computing the length of insns.
7856 * Constant Attributes:: Defining attributes that are constant.
7857 * Mnemonic Attribute:: Obtain the instruction mnemonic as attribute value.
7858 * Delay Slots:: Defining delay slots required for a machine.
7859 * Processor pipeline description:: Specifying information for insn scheduling.
7864 @node Defining Attributes
7865 @subsection Defining Attributes and their Values
7866 @cindex defining attributes and their values
7867 @cindex attributes, defining
7870 The @code{define_attr} expression is used to define each attribute required
7871 by the target machine. It looks like:
7874 (define_attr @var{name} @var{list-of-values} @var{default})
7877 @var{name} is a string specifying the name of the attribute being
7878 defined. Some attributes are used in a special way by the rest of the
7879 compiler. The @code{enabled} attribute can be used to conditionally
7880 enable or disable insn alternatives (@pxref{Disable Insn
7881 Alternatives}). The @code{predicable} attribute, together with a
7882 suitable @code{define_cond_exec} (@pxref{Conditional Execution}), can
7883 be used to automatically generate conditional variants of instruction
7884 patterns. The @code{mnemonic} attribute can be used to check for the
7885 instruction mnemonic (@pxref{Mnemonic Attribute}). The compiler
7886 internally uses the names @code{ce_enabled} and @code{nonce_enabled},
7887 so they should not be used elsewhere as alternative names.
7889 @var{list-of-values} is either a string that specifies a comma-separated
7890 list of values that can be assigned to the attribute, or a null string to
7891 indicate that the attribute takes numeric values.
7893 @var{default} is an attribute expression that gives the value of this
7894 attribute for insns that match patterns whose definition does not include
7895 an explicit value for this attribute. @xref{Attr Example}, for more
7896 information on the handling of defaults. @xref{Constant Attributes},
7897 for information on attributes that do not depend on any particular insn.
7900 For each defined attribute, a number of definitions are written to the
7901 @file{insn-attr.h} file. For cases where an explicit set of values is
7902 specified for an attribute, the following are defined:
7906 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
7909 An enumerated class is defined for @samp{attr_@var{name}} with
7910 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
7911 the attribute name and value are first converted to uppercase.
7914 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
7915 returns the attribute value for that insn.
7918 For example, if the following is present in the @file{md} file:
7921 (define_attr "type" "branch,fp,load,store,arith" @dots{})
7925 the following lines will be written to the file @file{insn-attr.h}.
7928 #define HAVE_ATTR_type 1
7929 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
7930 TYPE_STORE, TYPE_ARITH@};
7931 extern enum attr_type get_attr_type ();
7934 If the attribute takes numeric values, no @code{enum} type will be
7935 defined and the function to obtain the attribute's value will return
7938 There are attributes which are tied to a specific meaning. These
7939 attributes are not free to use for other purposes:
7943 The @code{length} attribute is used to calculate the length of emitted
7944 code chunks. This is especially important when verifying branch
7945 distances. @xref{Insn Lengths}.
7948 The @code{enabled} attribute can be defined to prevent certain
7949 alternatives of an insn definition from being used during code
7950 generation. @xref{Disable Insn Alternatives}.
7953 The @code{mnemonic} attribute can be defined to implement instruction
7954 specific checks in e.g. the pipeline description.
7955 @xref{Mnemonic Attribute}.
7958 For each of these special attributes, the corresponding
7959 @samp{HAVE_ATTR_@var{name}} @samp{#define} is also written when the
7960 attribute is not defined; in that case, it is defined as @samp{0}.
7962 @findex define_enum_attr
7963 @anchor{define_enum_attr}
7964 Another way of defining an attribute is to use:
7967 (define_enum_attr "@var{attr}" "@var{enum}" @var{default})
7970 This works in just the same way as @code{define_attr}, except that
7971 the list of values is taken from a separate enumeration called
7972 @var{enum} (@pxref{define_enum}). This form allows you to use
7973 the same list of values for several attributes without having to
7974 repeat the list each time. For example:
7977 (define_enum "processor" [
7982 (define_enum_attr "arch" "processor"
7983 (const (symbol_ref "target_arch")))
7984 (define_enum_attr "tune" "processor"
7985 (const (symbol_ref "target_tune")))
7988 defines the same attributes as:
7991 (define_attr "arch" "model_a,model_b,@dots{}"
7992 (const (symbol_ref "target_arch")))
7993 (define_attr "tune" "model_a,model_b,@dots{}"
7994 (const (symbol_ref "target_tune")))
7997 but without duplicating the processor list. The second example defines two
7998 separate C enums (@code{attr_arch} and @code{attr_tune}) whereas the first
7999 defines a single C enum (@code{processor}).
8003 @subsection Attribute Expressions
8004 @cindex attribute expressions
8006 RTL expressions used to define attributes use the codes described above
8007 plus a few specific to attribute definitions, to be discussed below.
8008 Attribute value expressions must have one of the following forms:
8011 @cindex @code{const_int} and attributes
8012 @item (const_int @var{i})
8013 The integer @var{i} specifies the value of a numeric attribute. @var{i}
8014 must be non-negative.
8016 The value of a numeric attribute can be specified either with a
8017 @code{const_int}, or as an integer represented as a string in
8018 @code{const_string}, @code{eq_attr} (see below), @code{attr},
8019 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
8020 overrides on specific instructions (@pxref{Tagging Insns}).
8022 @cindex @code{const_string} and attributes
8023 @item (const_string @var{value})
8024 The string @var{value} specifies a constant attribute value.
8025 If @var{value} is specified as @samp{"*"}, it means that the default value of
8026 the attribute is to be used for the insn containing this expression.
8027 @samp{"*"} obviously cannot be used in the @var{default} expression
8028 of a @code{define_attr}.
8030 If the attribute whose value is being specified is numeric, @var{value}
8031 must be a string containing a non-negative integer (normally
8032 @code{const_int} would be used in this case). Otherwise, it must
8033 contain one of the valid values for the attribute.
8035 @cindex @code{if_then_else} and attributes
8036 @item (if_then_else @var{test} @var{true-value} @var{false-value})
8037 @var{test} specifies an attribute test, whose format is defined below.
8038 The value of this expression is @var{true-value} if @var{test} is true,
8039 otherwise it is @var{false-value}.
8041 @cindex @code{cond} and attributes
8042 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
8043 The first operand of this expression is a vector containing an even
8044 number of expressions and consisting of pairs of @var{test} and @var{value}
8045 expressions. The value of the @code{cond} expression is that of the
8046 @var{value} corresponding to the first true @var{test} expression. If
8047 none of the @var{test} expressions are true, the value of the @code{cond}
8048 expression is that of the @var{default} expression.
8051 @var{test} expressions can have one of the following forms:
8054 @cindex @code{const_int} and attribute tests
8055 @item (const_int @var{i})
8056 This test is true if @var{i} is nonzero and false otherwise.
8058 @cindex @code{not} and attributes
8059 @cindex @code{ior} and attributes
8060 @cindex @code{and} and attributes
8061 @item (not @var{test})
8062 @itemx (ior @var{test1} @var{test2})
8063 @itemx (and @var{test1} @var{test2})
8064 These tests are true if the indicated logical function is true.
8066 @cindex @code{match_operand} and attributes
8067 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
8068 This test is true if operand @var{n} of the insn whose attribute value
8069 is being determined has mode @var{m} (this part of the test is ignored
8070 if @var{m} is @code{VOIDmode}) and the function specified by the string
8071 @var{pred} returns a nonzero value when passed operand @var{n} and mode
8072 @var{m} (this part of the test is ignored if @var{pred} is the null
8075 The @var{constraints} operand is ignored and should be the null string.
8077 @cindex @code{match_test} and attributes
8078 @item (match_test @var{c-expr})
8079 The test is true if C expression @var{c-expr} is true. In non-constant
8080 attributes, @var{c-expr} has access to the following variables:
8084 The rtl instruction under test.
8085 @item which_alternative
8086 The @code{define_insn} alternative that @var{insn} matches.
8087 @xref{Output Statement}.
8089 An array of @var{insn}'s rtl operands.
8092 @var{c-expr} behaves like the condition in a C @code{if} statement,
8093 so there is no need to explicitly convert the expression into a boolean
8094 0 or 1 value. For example, the following two tests are equivalent:
8097 (match_test "x & 2")
8098 (match_test "(x & 2) != 0")
8101 @cindex @code{le} and attributes
8102 @cindex @code{leu} and attributes
8103 @cindex @code{lt} and attributes
8104 @cindex @code{gt} and attributes
8105 @cindex @code{gtu} and attributes
8106 @cindex @code{ge} and attributes
8107 @cindex @code{geu} and attributes
8108 @cindex @code{ne} and attributes
8109 @cindex @code{eq} and attributes
8110 @cindex @code{plus} and attributes
8111 @cindex @code{minus} and attributes
8112 @cindex @code{mult} and attributes
8113 @cindex @code{div} and attributes
8114 @cindex @code{mod} and attributes
8115 @cindex @code{abs} and attributes
8116 @cindex @code{neg} and attributes
8117 @cindex @code{ashift} and attributes
8118 @cindex @code{lshiftrt} and attributes
8119 @cindex @code{ashiftrt} and attributes
8120 @item (le @var{arith1} @var{arith2})
8121 @itemx (leu @var{arith1} @var{arith2})
8122 @itemx (lt @var{arith1} @var{arith2})
8123 @itemx (ltu @var{arith1} @var{arith2})
8124 @itemx (gt @var{arith1} @var{arith2})
8125 @itemx (gtu @var{arith1} @var{arith2})
8126 @itemx (ge @var{arith1} @var{arith2})
8127 @itemx (geu @var{arith1} @var{arith2})
8128 @itemx (ne @var{arith1} @var{arith2})
8129 @itemx (eq @var{arith1} @var{arith2})
8130 These tests are true if the indicated comparison of the two arithmetic
8131 expressions is true. Arithmetic expressions are formed with
8132 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
8133 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
8134 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
8137 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
8138 Lengths},for additional forms). @code{symbol_ref} is a string
8139 denoting a C expression that yields an @code{int} when evaluated by the
8140 @samp{get_attr_@dots{}} routine. It should normally be a global
8144 @item (eq_attr @var{name} @var{value})
8145 @var{name} is a string specifying the name of an attribute.
8147 @var{value} is a string that is either a valid value for attribute
8148 @var{name}, a comma-separated list of values, or @samp{!} followed by a
8149 value or list. If @var{value} does not begin with a @samp{!}, this
8150 test is true if the value of the @var{name} attribute of the current
8151 insn is in the list specified by @var{value}. If @var{value} begins
8152 with a @samp{!}, this test is true if the attribute's value is
8153 @emph{not} in the specified list.
8158 (eq_attr "type" "load,store")
8165 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
8168 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
8169 value of the compiler variable @code{which_alternative}
8170 (@pxref{Output Statement}) and the values must be small integers. For
8174 (eq_attr "alternative" "2,3")
8181 (ior (eq (symbol_ref "which_alternative") (const_int 2))
8182 (eq (symbol_ref "which_alternative") (const_int 3)))
8185 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
8186 where the value of the attribute being tested is known for all insns matching
8187 a particular pattern. This is by far the most common case.
8190 @item (attr_flag @var{name})
8191 The value of an @code{attr_flag} expression is true if the flag
8192 specified by @var{name} is true for the @code{insn} currently being
8195 @var{name} is a string specifying one of a fixed set of flags to test.
8196 Test the flags @code{forward} and @code{backward} to determine the
8197 direction of a conditional branch.
8199 This example describes a conditional branch delay slot which
8200 can be nullified for forward branches that are taken (annul-true) or
8201 for backward branches which are not taken (annul-false).
8204 (define_delay (eq_attr "type" "cbranch")
8205 [(eq_attr "in_branch_delay" "true")
8206 (and (eq_attr "in_branch_delay" "true")
8207 (attr_flag "forward"))
8208 (and (eq_attr "in_branch_delay" "true")
8209 (attr_flag "backward"))])
8212 The @code{forward} and @code{backward} flags are false if the current
8213 @code{insn} being scheduled is not a conditional branch.
8215 @code{attr_flag} is only used during delay slot scheduling and has no
8216 meaning to other passes of the compiler.
8219 @item (attr @var{name})
8220 The value of another attribute is returned. This is most useful
8221 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
8222 produce more efficient code for non-numeric attributes.
8228 @subsection Assigning Attribute Values to Insns
8229 @cindex tagging insns
8230 @cindex assigning attribute values to insns
8232 The value assigned to an attribute of an insn is primarily determined by
8233 which pattern is matched by that insn (or which @code{define_peephole}
8234 generated it). Every @code{define_insn} and @code{define_peephole} can
8235 have an optional last argument to specify the values of attributes for
8236 matching insns. The value of any attribute not specified in a particular
8237 insn is set to the default value for that attribute, as specified in its
8238 @code{define_attr}. Extensive use of default values for attributes
8239 permits the specification of the values for only one or two attributes
8240 in the definition of most insn patterns, as seen in the example in the
8243 The optional last argument of @code{define_insn} and
8244 @code{define_peephole} is a vector of expressions, each of which defines
8245 the value for a single attribute. The most general way of assigning an
8246 attribute's value is to use a @code{set} expression whose first operand is an
8247 @code{attr} expression giving the name of the attribute being set. The
8248 second operand of the @code{set} is an attribute expression
8249 (@pxref{Expressions}) giving the value of the attribute.
8251 When the attribute value depends on the @samp{alternative} attribute
8252 (i.e., which is the applicable alternative in the constraint of the
8253 insn), the @code{set_attr_alternative} expression can be used. It
8254 allows the specification of a vector of attribute expressions, one for
8258 When the generality of arbitrary attribute expressions is not required,
8259 the simpler @code{set_attr} expression can be used, which allows
8260 specifying a string giving either a single attribute value or a list
8261 of attribute values, one for each alternative.
8263 The form of each of the above specifications is shown below. In each case,
8264 @var{name} is a string specifying the attribute to be set.
8267 @item (set_attr @var{name} @var{value-string})
8268 @var{value-string} is either a string giving the desired attribute value,
8269 or a string containing a comma-separated list giving the values for
8270 succeeding alternatives. The number of elements must match the number
8271 of alternatives in the constraint of the insn pattern.
8273 Note that it may be useful to specify @samp{*} for some alternative, in
8274 which case the attribute will assume its default value for insns matching
8277 @findex set_attr_alternative
8278 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
8279 Depending on the alternative of the insn, the value will be one of the
8280 specified values. This is a shorthand for using a @code{cond} with
8281 tests on the @samp{alternative} attribute.
8284 @item (set (attr @var{name}) @var{value})
8285 The first operand of this @code{set} must be the special RTL expression
8286 @code{attr}, whose sole operand is a string giving the name of the
8287 attribute being set. @var{value} is the value of the attribute.
8290 The following shows three different ways of representing the same
8291 attribute value specification:
8294 (set_attr "type" "load,store,arith")
8296 (set_attr_alternative "type"
8297 [(const_string "load") (const_string "store")
8298 (const_string "arith")])
8301 (cond [(eq_attr "alternative" "1") (const_string "load")
8302 (eq_attr "alternative" "2") (const_string "store")]
8303 (const_string "arith")))
8307 @findex define_asm_attributes
8308 The @code{define_asm_attributes} expression provides a mechanism to
8309 specify the attributes assigned to insns produced from an @code{asm}
8310 statement. It has the form:
8313 (define_asm_attributes [@var{attr-sets}])
8317 where @var{attr-sets} is specified the same as for both the
8318 @code{define_insn} and the @code{define_peephole} expressions.
8320 These values will typically be the ``worst case'' attribute values. For
8321 example, they might indicate that the condition code will be clobbered.
8323 A specification for a @code{length} attribute is handled specially. The
8324 way to compute the length of an @code{asm} insn is to multiply the
8325 length specified in the expression @code{define_asm_attributes} by the
8326 number of machine instructions specified in the @code{asm} statement,
8327 determined by counting the number of semicolons and newlines in the
8328 string. Therefore, the value of the @code{length} attribute specified
8329 in a @code{define_asm_attributes} should be the maximum possible length
8330 of a single machine instruction.
8335 @subsection Example of Attribute Specifications
8336 @cindex attribute specifications example
8337 @cindex attribute specifications
8339 The judicious use of defaulting is important in the efficient use of
8340 insn attributes. Typically, insns are divided into @dfn{types} and an
8341 attribute, customarily called @code{type}, is used to represent this
8342 value. This attribute is normally used only to define the default value
8343 for other attributes. An example will clarify this usage.
8345 Assume we have a RISC machine with a condition code and in which only
8346 full-word operations are performed in registers. Let us assume that we
8347 can divide all insns into loads, stores, (integer) arithmetic
8348 operations, floating point operations, and branches.
8350 Here we will concern ourselves with determining the effect of an insn on
8351 the condition code and will limit ourselves to the following possible
8352 effects: The condition code can be set unpredictably (clobbered), not
8353 be changed, be set to agree with the results of the operation, or only
8354 changed if the item previously set into the condition code has been
8357 Here is part of a sample @file{md} file for such a machine:
8360 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
8362 (define_attr "cc" "clobber,unchanged,set,change0"
8363 (cond [(eq_attr "type" "load")
8364 (const_string "change0")
8365 (eq_attr "type" "store,branch")
8366 (const_string "unchanged")
8367 (eq_attr "type" "arith")
8368 (if_then_else (match_operand:SI 0 "" "")
8369 (const_string "set")
8370 (const_string "clobber"))]
8371 (const_string "clobber")))
8374 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
8375 (match_operand:SI 1 "general_operand" "r,m,r"))]
8381 [(set_attr "type" "arith,load,store")])
8384 Note that we assume in the above example that arithmetic operations
8385 performed on quantities smaller than a machine word clobber the condition
8386 code since they will set the condition code to a value corresponding to the
8392 @subsection Computing the Length of an Insn
8393 @cindex insn lengths, computing
8394 @cindex computing the length of an insn
8396 For many machines, multiple types of branch instructions are provided, each
8397 for different length branch displacements. In most cases, the assembler
8398 will choose the correct instruction to use. However, when the assembler
8399 cannot do so, GCC can when a special attribute, the @code{length}
8400 attribute, is defined. This attribute must be defined to have numeric
8401 values by specifying a null string in its @code{define_attr}.
8403 In the case of the @code{length} attribute, two additional forms of
8404 arithmetic terms are allowed in test expressions:
8407 @cindex @code{match_dup} and attributes
8408 @item (match_dup @var{n})
8409 This refers to the address of operand @var{n} of the current insn, which
8410 must be a @code{label_ref}.
8412 @cindex @code{pc} and attributes
8414 This refers to the address of the @emph{current} insn. It might have
8415 been more consistent with other usage to make this the address of the
8416 @emph{next} insn but this would be confusing because the length of the
8417 current insn is to be computed.
8420 @cindex @code{addr_vec}, length of
8421 @cindex @code{addr_diff_vec}, length of
8422 For normal insns, the length will be determined by value of the
8423 @code{length} attribute. In the case of @code{addr_vec} and
8424 @code{addr_diff_vec} insn patterns, the length is computed as
8425 the number of vectors multiplied by the size of each vector.
8427 Lengths are measured in addressable storage units (bytes).
8429 The following macros can be used to refine the length computation:
8432 @findex ADJUST_INSN_LENGTH
8433 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
8434 If defined, modifies the length assigned to instruction @var{insn} as a
8435 function of the context in which it is used. @var{length} is an lvalue
8436 that contains the initially computed length of the insn and should be
8437 updated with the correct length of the insn.
8439 This macro will normally not be required. A case in which it is
8440 required is the ROMP@. On this machine, the size of an @code{addr_vec}
8441 insn must be increased by two to compensate for the fact that alignment
8445 @findex get_attr_length
8446 The routine that returns @code{get_attr_length} (the value of the
8447 @code{length} attribute) can be used by the output routine to
8448 determine the form of the branch instruction to be written, as the
8449 example below illustrates.
8451 As an example of the specification of variable-length branches, consider
8452 the IBM 360. If we adopt the convention that a register will be set to
8453 the starting address of a function, we can jump to labels within 4k of
8454 the start using a four-byte instruction. Otherwise, we need a six-byte
8455 sequence to load the address from memory and then branch to it.
8457 On such a machine, a pattern for a branch instruction might be specified
8463 (label_ref (match_operand 0 "" "")))]
8466 return (get_attr_length (insn) == 4
8467 ? "b %l0" : "l r15,=a(%l0); br r15");
8469 [(set (attr "length")
8470 (if_then_else (lt (match_dup 0) (const_int 4096))
8477 @node Constant Attributes
8478 @subsection Constant Attributes
8479 @cindex constant attributes
8481 A special form of @code{define_attr}, where the expression for the
8482 default value is a @code{const} expression, indicates an attribute that
8483 is constant for a given run of the compiler. Constant attributes may be
8484 used to specify which variety of processor is used. For example,
8487 (define_attr "cpu" "m88100,m88110,m88000"
8489 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
8490 (symbol_ref "TARGET_88110") (const_string "m88110")]
8491 (const_string "m88000"))))
8493 (define_attr "memory" "fast,slow"
8495 (if_then_else (symbol_ref "TARGET_FAST_MEM")
8496 (const_string "fast")
8497 (const_string "slow"))))
8500 The routine generated for constant attributes has no parameters as it
8501 does not depend on any particular insn. RTL expressions used to define
8502 the value of a constant attribute may use the @code{symbol_ref} form,
8503 but may not use either the @code{match_operand} form or @code{eq_attr}
8504 forms involving insn attributes.
8508 @node Mnemonic Attribute
8509 @subsection Mnemonic Attribute
8510 @cindex mnemonic attribute
8512 The @code{mnemonic} attribute is a string type attribute holding the
8513 instruction mnemonic for an insn alternative. The attribute values
8514 will automatically be generated by the machine description parser if
8515 there is an attribute definition in the md file:
8518 (define_attr "mnemonic" "unknown" (const_string "unknown"))
8521 The default value can be freely chosen as long as it does not collide
8522 with any of the instruction mnemonics. This value will be used
8523 whenever the machine description parser is not able to determine the
8524 mnemonic string. This might be the case for output templates
8525 containing more than a single instruction as in
8526 @code{"mvcle\t%0,%1,0\;jo\t.-4"}.
8528 The @code{mnemonic} attribute set is not generated automatically if the
8529 instruction string is generated via C code.
8531 An existing @code{mnemonic} attribute set in an insn definition will not
8532 be overriden by the md file parser. That way it is possible to
8533 manually set the instruction mnemonics for the cases where the md file
8534 parser fails to determine it automatically.
8536 The @code{mnemonic} attribute is useful for dealing with instruction
8537 specific properties in the pipeline description without defining
8538 additional insn attributes.
8541 (define_attr "ooo_expanded" ""
8542 (cond [(eq_attr "mnemonic" "dlr,dsgr,d,dsgf,stam,dsgfr,dlgr")
8550 @subsection Delay Slot Scheduling
8551 @cindex delay slots, defining
8553 The insn attribute mechanism can be used to specify the requirements for
8554 delay slots, if any, on a target machine. An instruction is said to
8555 require a @dfn{delay slot} if some instructions that are physically
8556 after the instruction are executed as if they were located before it.
8557 Classic examples are branch and call instructions, which often execute
8558 the following instruction before the branch or call is performed.
8560 On some machines, conditional branch instructions can optionally
8561 @dfn{annul} instructions in the delay slot. This means that the
8562 instruction will not be executed for certain branch outcomes. Both
8563 instructions that annul if the branch is true and instructions that
8564 annul if the branch is false are supported.
8566 Delay slot scheduling differs from instruction scheduling in that
8567 determining whether an instruction needs a delay slot is dependent only
8568 on the type of instruction being generated, not on data flow between the
8569 instructions. See the next section for a discussion of data-dependent
8570 instruction scheduling.
8572 @findex define_delay
8573 The requirement of an insn needing one or more delay slots is indicated
8574 via the @code{define_delay} expression. It has the following form:
8577 (define_delay @var{test}
8578 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
8579 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
8583 @var{test} is an attribute test that indicates whether this
8584 @code{define_delay} applies to a particular insn. If so, the number of
8585 required delay slots is determined by the length of the vector specified
8586 as the second argument. An insn placed in delay slot @var{n} must
8587 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
8588 attribute test that specifies which insns may be annulled if the branch
8589 is true. Similarly, @var{annul-false-n} specifies which insns in the
8590 delay slot may be annulled if the branch is false. If annulling is not
8591 supported for that delay slot, @code{(nil)} should be coded.
8593 For example, in the common case where branch and call insns require
8594 a single delay slot, which may contain any insn other than a branch or
8595 call, the following would be placed in the @file{md} file:
8598 (define_delay (eq_attr "type" "branch,call")
8599 [(eq_attr "type" "!branch,call") (nil) (nil)])
8602 Multiple @code{define_delay} expressions may be specified. In this
8603 case, each such expression specifies different delay slot requirements
8604 and there must be no insn for which tests in two @code{define_delay}
8605 expressions are both true.
8607 For example, if we have a machine that requires one delay slot for branches
8608 but two for calls, no delay slot can contain a branch or call insn,
8609 and any valid insn in the delay slot for the branch can be annulled if the
8610 branch is true, we might represent this as follows:
8613 (define_delay (eq_attr "type" "branch")
8614 [(eq_attr "type" "!branch,call")
8615 (eq_attr "type" "!branch,call")
8618 (define_delay (eq_attr "type" "call")
8619 [(eq_attr "type" "!branch,call") (nil) (nil)
8620 (eq_attr "type" "!branch,call") (nil) (nil)])
8622 @c the above is *still* too long. --mew 4feb93
8626 @node Processor pipeline description
8627 @subsection Specifying processor pipeline description
8628 @cindex processor pipeline description
8629 @cindex processor functional units
8630 @cindex instruction latency time
8631 @cindex interlock delays
8632 @cindex data dependence delays
8633 @cindex reservation delays
8634 @cindex pipeline hazard recognizer
8635 @cindex automaton based pipeline description
8636 @cindex regular expressions
8637 @cindex deterministic finite state automaton
8638 @cindex automaton based scheduler
8642 To achieve better performance, most modern processors
8643 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
8644 processors) have many @dfn{functional units} on which several
8645 instructions can be executed simultaneously. An instruction starts
8646 execution if its issue conditions are satisfied. If not, the
8647 instruction is stalled until its conditions are satisfied. Such
8648 @dfn{interlock (pipeline) delay} causes interruption of the fetching
8649 of successor instructions (or demands nop instructions, e.g.@: for some
8652 There are two major kinds of interlock delays in modern processors.
8653 The first one is a data dependence delay determining @dfn{instruction
8654 latency time}. The instruction execution is not started until all
8655 source data have been evaluated by prior instructions (there are more
8656 complex cases when the instruction execution starts even when the data
8657 are not available but will be ready in given time after the
8658 instruction execution start). Taking the data dependence delays into
8659 account is simple. The data dependence (true, output, and
8660 anti-dependence) delay between two instructions is given by a
8661 constant. In most cases this approach is adequate. The second kind
8662 of interlock delays is a reservation delay. The reservation delay
8663 means that two instructions under execution will be in need of shared
8664 processors resources, i.e.@: buses, internal registers, and/or
8665 functional units, which are reserved for some time. Taking this kind
8666 of delay into account is complex especially for modern @acronym{RISC}
8669 The task of exploiting more processor parallelism is solved by an
8670 instruction scheduler. For a better solution to this problem, the
8671 instruction scheduler has to have an adequate description of the
8672 processor parallelism (or @dfn{pipeline description}). GCC
8673 machine descriptions describe processor parallelism and functional
8674 unit reservations for groups of instructions with the aid of
8675 @dfn{regular expressions}.
8677 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
8678 figure out the possibility of the instruction issue by the processor
8679 on a given simulated processor cycle. The pipeline hazard recognizer is
8680 automatically generated from the processor pipeline description. The
8681 pipeline hazard recognizer generated from the machine description
8682 is based on a deterministic finite state automaton (@acronym{DFA}):
8683 the instruction issue is possible if there is a transition from one
8684 automaton state to another one. This algorithm is very fast, and
8685 furthermore, its speed is not dependent on processor
8686 complexity@footnote{However, the size of the automaton depends on
8687 processor complexity. To limit this effect, machine descriptions
8688 can split orthogonal parts of the machine description among several
8689 automata: but then, since each of these must be stepped independently,
8690 this does cause a small decrease in the algorithm's performance.}.
8692 @cindex automaton based pipeline description
8693 The rest of this section describes the directives that constitute
8694 an automaton-based processor pipeline description. The order of
8695 these constructions within the machine description file is not
8698 @findex define_automaton
8699 @cindex pipeline hazard recognizer
8700 The following optional construction describes names of automata
8701 generated and used for the pipeline hazards recognition. Sometimes
8702 the generated finite state automaton used by the pipeline hazard
8703 recognizer is large. If we use more than one automaton and bind functional
8704 units to the automata, the total size of the automata is usually
8705 less than the size of the single automaton. If there is no one such
8706 construction, only one finite state automaton is generated.
8709 (define_automaton @var{automata-names})
8712 @var{automata-names} is a string giving names of the automata. The
8713 names are separated by commas. All the automata should have unique names.
8714 The automaton name is used in the constructions @code{define_cpu_unit} and
8715 @code{define_query_cpu_unit}.
8717 @findex define_cpu_unit
8718 @cindex processor functional units
8719 Each processor functional unit used in the description of instruction
8720 reservations should be described by the following construction.
8723 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
8726 @var{unit-names} is a string giving the names of the functional units
8727 separated by commas. Don't use name @samp{nothing}, it is reserved
8730 @var{automaton-name} is a string giving the name of the automaton with
8731 which the unit is bound. The automaton should be described in
8732 construction @code{define_automaton}. You should give
8733 @dfn{automaton-name}, if there is a defined automaton.
8735 The assignment of units to automata are constrained by the uses of the
8736 units in insn reservations. The most important constraint is: if a
8737 unit reservation is present on a particular cycle of an alternative
8738 for an insn reservation, then some unit from the same automaton must
8739 be present on the same cycle for the other alternatives of the insn
8740 reservation. The rest of the constraints are mentioned in the
8741 description of the subsequent constructions.
8743 @findex define_query_cpu_unit
8744 @cindex querying function unit reservations
8745 The following construction describes CPU functional units analogously
8746 to @code{define_cpu_unit}. The reservation of such units can be
8747 queried for an automaton state. The instruction scheduler never
8748 queries reservation of functional units for given automaton state. So
8749 as a rule, you don't need this construction. This construction could
8750 be used for future code generation goals (e.g.@: to generate
8751 @acronym{VLIW} insn templates).
8754 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
8757 @var{unit-names} is a string giving names of the functional units
8758 separated by commas.
8760 @var{automaton-name} is a string giving the name of the automaton with
8761 which the unit is bound.
8763 @findex define_insn_reservation
8764 @cindex instruction latency time
8765 @cindex regular expressions
8767 The following construction is the major one to describe pipeline
8768 characteristics of an instruction.
8771 (define_insn_reservation @var{insn-name} @var{default_latency}
8772 @var{condition} @var{regexp})
8775 @var{default_latency} is a number giving latency time of the
8776 instruction. There is an important difference between the old
8777 description and the automaton based pipeline description. The latency
8778 time is used for all dependencies when we use the old description. In
8779 the automaton based pipeline description, the given latency time is only
8780 used for true dependencies. The cost of anti-dependencies is always
8781 zero and the cost of output dependencies is the difference between
8782 latency times of the producing and consuming insns (if the difference
8783 is negative, the cost is considered to be zero). You can always
8784 change the default costs for any description by using the target hook
8785 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
8787 @var{insn-name} is a string giving the internal name of the insn. The
8788 internal names are used in constructions @code{define_bypass} and in
8789 the automaton description file generated for debugging. The internal
8790 name has nothing in common with the names in @code{define_insn}. It is a
8791 good practice to use insn classes described in the processor manual.
8793 @var{condition} defines what RTL insns are described by this
8794 construction. You should remember that you will be in trouble if
8795 @var{condition} for two or more different
8796 @code{define_insn_reservation} constructions is TRUE for an insn. In
8797 this case what reservation will be used for the insn is not defined.
8798 Such cases are not checked during generation of the pipeline hazards
8799 recognizer because in general recognizing that two conditions may have
8800 the same value is quite difficult (especially if the conditions
8801 contain @code{symbol_ref}). It is also not checked during the
8802 pipeline hazard recognizer work because it would slow down the
8803 recognizer considerably.
8805 @var{regexp} is a string describing the reservation of the cpu's functional
8806 units by the instruction. The reservations are described by a regular
8807 expression according to the following syntax:
8810 regexp = regexp "," oneof
8813 oneof = oneof "|" allof
8816 allof = allof "+" repeat
8819 repeat = element "*" number
8822 element = cpu_function_unit_name
8831 @samp{,} is used for describing the start of the next cycle in
8835 @samp{|} is used for describing a reservation described by the first
8836 regular expression @strong{or} a reservation described by the second
8837 regular expression @strong{or} etc.
8840 @samp{+} is used for describing a reservation described by the first
8841 regular expression @strong{and} a reservation described by the
8842 second regular expression @strong{and} etc.
8845 @samp{*} is used for convenience and simply means a sequence in which
8846 the regular expression are repeated @var{number} times with cycle
8847 advancing (see @samp{,}).
8850 @samp{cpu_function_unit_name} denotes reservation of the named
8854 @samp{reservation_name} --- see description of construction
8855 @samp{define_reservation}.
8858 @samp{nothing} denotes no unit reservations.
8861 @findex define_reservation
8862 Sometimes unit reservations for different insns contain common parts.
8863 In such case, you can simplify the pipeline description by describing
8864 the common part by the following construction
8867 (define_reservation @var{reservation-name} @var{regexp})
8870 @var{reservation-name} is a string giving name of @var{regexp}.
8871 Functional unit names and reservation names are in the same name
8872 space. So the reservation names should be different from the
8873 functional unit names and can not be the reserved name @samp{nothing}.
8875 @findex define_bypass
8876 @cindex instruction latency time
8878 The following construction is used to describe exceptions in the
8879 latency time for given instruction pair. This is so called bypasses.
8882 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
8886 @var{number} defines when the result generated by the instructions
8887 given in string @var{out_insn_names} will be ready for the
8888 instructions given in string @var{in_insn_names}. Each of these
8889 strings is a comma-separated list of filename-style globs and
8890 they refer to the names of @code{define_insn_reservation}s.
8893 (define_bypass 1 "cpu1_load_*, cpu1_store_*" "cpu1_load_*")
8895 defines a bypass between instructions that start with
8896 @samp{cpu1_load_} or @samp{cpu1_store_} and those that start with
8899 @var{guard} is an optional string giving the name of a C function which
8900 defines an additional guard for the bypass. The function will get the
8901 two insns as parameters. If the function returns zero the bypass will
8902 be ignored for this case. The additional guard is necessary to
8903 recognize complicated bypasses, e.g.@: when the consumer is only an address
8904 of insn @samp{store} (not a stored value).
8906 If there are more one bypass with the same output and input insns, the
8907 chosen bypass is the first bypass with a guard in description whose
8908 guard function returns nonzero. If there is no such bypass, then
8909 bypass without the guard function is chosen.
8911 @findex exclusion_set
8912 @findex presence_set
8913 @findex final_presence_set
8915 @findex final_absence_set
8918 The following five constructions are usually used to describe
8919 @acronym{VLIW} processors, or more precisely, to describe a placement
8920 of small instructions into @acronym{VLIW} instruction slots. They
8921 can be used for @acronym{RISC} processors, too.
8924 (exclusion_set @var{unit-names} @var{unit-names})
8925 (presence_set @var{unit-names} @var{patterns})
8926 (final_presence_set @var{unit-names} @var{patterns})
8927 (absence_set @var{unit-names} @var{patterns})
8928 (final_absence_set @var{unit-names} @var{patterns})
8931 @var{unit-names} is a string giving names of functional units
8932 separated by commas.
8934 @var{patterns} is a string giving patterns of functional units
8935 separated by comma. Currently pattern is one unit or units
8936 separated by white-spaces.
8938 The first construction (@samp{exclusion_set}) means that each
8939 functional unit in the first string can not be reserved simultaneously
8940 with a unit whose name is in the second string and vice versa. For
8941 example, the construction is useful for describing processors
8942 (e.g.@: some SPARC processors) with a fully pipelined floating point
8943 functional unit which can execute simultaneously only single floating
8944 point insns or only double floating point insns.
8946 The second construction (@samp{presence_set}) means that each
8947 functional unit in the first string can not be reserved unless at
8948 least one of pattern of units whose names are in the second string is
8949 reserved. This is an asymmetric relation. For example, it is useful
8950 for description that @acronym{VLIW} @samp{slot1} is reserved after
8951 @samp{slot0} reservation. We could describe it by the following
8955 (presence_set "slot1" "slot0")
8958 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
8959 reservation. In this case we could write
8962 (presence_set "slot1" "slot0 b0")
8965 The third construction (@samp{final_presence_set}) is analogous to
8966 @samp{presence_set}. The difference between them is when checking is
8967 done. When an instruction is issued in given automaton state
8968 reflecting all current and planned unit reservations, the automaton
8969 state is changed. The first state is a source state, the second one
8970 is a result state. Checking for @samp{presence_set} is done on the
8971 source state reservation, checking for @samp{final_presence_set} is
8972 done on the result reservation. This construction is useful to
8973 describe a reservation which is actually two subsequent reservations.
8974 For example, if we use
8977 (presence_set "slot1" "slot0")
8980 the following insn will be never issued (because @samp{slot1} requires
8981 @samp{slot0} which is absent in the source state).
8984 (define_reservation "insn_and_nop" "slot0 + slot1")
8987 but it can be issued if we use analogous @samp{final_presence_set}.
8989 The forth construction (@samp{absence_set}) means that each functional
8990 unit in the first string can be reserved only if each pattern of units
8991 whose names are in the second string is not reserved. This is an
8992 asymmetric relation (actually @samp{exclusion_set} is analogous to
8993 this one but it is symmetric). For example it might be useful in a
8994 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
8995 after either @samp{slot1} or @samp{slot2} have been reserved. This
8996 can be described as:
8999 (absence_set "slot0" "slot1, slot2")
9002 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
9003 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
9004 this case we could write
9007 (absence_set "slot2" "slot0 b0, slot1 b1")
9010 All functional units mentioned in a set should belong to the same
9013 The last construction (@samp{final_absence_set}) is analogous to
9014 @samp{absence_set} but checking is done on the result (state)
9015 reservation. See comments for @samp{final_presence_set}.
9017 @findex automata_option
9018 @cindex deterministic finite state automaton
9019 @cindex nondeterministic finite state automaton
9020 @cindex finite state automaton minimization
9021 You can control the generator of the pipeline hazard recognizer with
9022 the following construction.
9025 (automata_option @var{options})
9028 @var{options} is a string giving options which affect the generated
9029 code. Currently there are the following options:
9033 @dfn{no-minimization} makes no minimization of the automaton. This is
9034 only worth to do when we are debugging the description and need to
9035 look more accurately at reservations of states.
9038 @dfn{time} means printing time statistics about the generation of
9042 @dfn{stats} means printing statistics about the generated automata
9043 such as the number of DFA states, NDFA states and arcs.
9046 @dfn{v} means a generation of the file describing the result automata.
9047 The file has suffix @samp{.dfa} and can be used for the description
9048 verification and debugging.
9051 @dfn{w} means a generation of warning instead of error for
9052 non-critical errors.
9055 @dfn{no-comb-vect} prevents the automaton generator from generating
9056 two data structures and comparing them for space efficiency. Using
9057 a comb vector to represent transitions may be better, but it can be
9058 very expensive to construct. This option is useful if the build
9059 process spends an unacceptably long time in genautomata.
9062 @dfn{ndfa} makes nondeterministic finite state automata. This affects
9063 the treatment of operator @samp{|} in the regular expressions. The
9064 usual treatment of the operator is to try the first alternative and,
9065 if the reservation is not possible, the second alternative. The
9066 nondeterministic treatment means trying all alternatives, some of them
9067 may be rejected by reservations in the subsequent insns.
9070 @dfn{collapse-ndfa} modifies the behaviour of the generator when
9071 producing an automaton. An additional state transition to collapse a
9072 nondeterministic @acronym{NDFA} state to a deterministic @acronym{DFA}
9073 state is generated. It can be triggered by passing @code{const0_rtx} to
9074 state_transition. In such an automaton, cycle advance transitions are
9075 available only for these collapsed states. This option is useful for
9076 ports that want to use the @code{ndfa} option, but also want to use
9077 @code{define_query_cpu_unit} to assign units to insns issued in a cycle.
9080 @dfn{progress} means output of a progress bar showing how many states
9081 were generated so far for automaton being processed. This is useful
9082 during debugging a @acronym{DFA} description. If you see too many
9083 generated states, you could interrupt the generator of the pipeline
9084 hazard recognizer and try to figure out a reason for generation of the
9088 As an example, consider a superscalar @acronym{RISC} machine which can
9089 issue three insns (two integer insns and one floating point insn) on
9090 the cycle but can finish only two insns. To describe this, we define
9091 the following functional units.
9094 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
9095 (define_cpu_unit "port0, port1")
9098 All simple integer insns can be executed in any integer pipeline and
9099 their result is ready in two cycles. The simple integer insns are
9100 issued into the first pipeline unless it is reserved, otherwise they
9101 are issued into the second pipeline. Integer division and
9102 multiplication insns can be executed only in the second integer
9103 pipeline and their results are ready correspondingly in 8 and 4
9104 cycles. The integer division is not pipelined, i.e.@: the subsequent
9105 integer division insn can not be issued until the current division
9106 insn finished. Floating point insns are fully pipelined and their
9107 results are ready in 3 cycles. Where the result of a floating point
9108 insn is used by an integer insn, an additional delay of one cycle is
9109 incurred. To describe all of this we could specify
9112 (define_cpu_unit "div")
9114 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
9115 "(i0_pipeline | i1_pipeline), (port0 | port1)")
9117 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
9118 "i1_pipeline, nothing*2, (port0 | port1)")
9120 (define_insn_reservation "div" 8 (eq_attr "type" "div")
9121 "i1_pipeline, div*7, div + (port0 | port1)")
9123 (define_insn_reservation "float" 3 (eq_attr "type" "float")
9124 "f_pipeline, nothing, (port0 | port1))
9126 (define_bypass 4 "float" "simple,mult,div")
9129 To simplify the description we could describe the following reservation
9132 (define_reservation "finish" "port0|port1")
9135 and use it in all @code{define_insn_reservation} as in the following
9139 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
9140 "(i0_pipeline | i1_pipeline), finish")
9146 @node Conditional Execution
9147 @section Conditional Execution
9148 @cindex conditional execution
9151 A number of architectures provide for some form of conditional
9152 execution, or predication. The hallmark of this feature is the
9153 ability to nullify most of the instructions in the instruction set.
9154 When the instruction set is large and not entirely symmetric, it
9155 can be quite tedious to describe these forms directly in the
9156 @file{.md} file. An alternative is the @code{define_cond_exec} template.
9158 @findex define_cond_exec
9161 [@var{predicate-pattern}]
9163 "@var{output-template}"
9164 "@var{optional-insn-attribues}")
9167 @var{predicate-pattern} is the condition that must be true for the
9168 insn to be executed at runtime and should match a relational operator.
9169 One can use @code{match_operator} to match several relational operators
9170 at once. Any @code{match_operand} operands must have no more than one
9173 @var{condition} is a C expression that must be true for the generated
9176 @findex current_insn_predicate
9177 @var{output-template} is a string similar to the @code{define_insn}
9178 output template (@pxref{Output Template}), except that the @samp{*}
9179 and @samp{@@} special cases do not apply. This is only useful if the
9180 assembly text for the predicate is a simple prefix to the main insn.
9181 In order to handle the general case, there is a global variable
9182 @code{current_insn_predicate} that will contain the entire predicate
9183 if the current insn is predicated, and will otherwise be @code{NULL}.
9185 @var{optional-insn-attributes} is an optional vector of attributes that gets
9186 appended to the insn attributes of the produced cond_exec rtx. It can
9187 be used to add some distinguishing attribute to cond_exec rtxs produced
9188 that way. An example usage would be to use this attribute in conjunction
9189 with attributes on the main pattern to disable particular alternatives under
9192 When @code{define_cond_exec} is used, an implicit reference to
9193 the @code{predicable} instruction attribute is made.
9194 @xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have
9195 exactly two elements in its @var{list-of-values}), with the possible
9196 values being @code{no} and @code{yes}. The default and all uses in
9197 the insns must be a simple constant, not a complex expressions. It
9198 may, however, depend on the alternative, by using a comma-separated
9199 list of values. If that is the case, the port should also define an
9200 @code{enabled} attribute (@pxref{Disable Insn Alternatives}), which
9201 should also allow only @code{no} and @code{yes} as its values.
9203 For each @code{define_insn} for which the @code{predicable}
9204 attribute is true, a new @code{define_insn} pattern will be
9205 generated that matches a predicated version of the instruction.
9209 (define_insn "addsi"
9210 [(set (match_operand:SI 0 "register_operand" "r")
9211 (plus:SI (match_operand:SI 1 "register_operand" "r")
9212 (match_operand:SI 2 "register_operand" "r")))]
9217 [(ne (match_operand:CC 0 "register_operand" "c")
9224 generates a new pattern
9229 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
9230 (set (match_operand:SI 0 "register_operand" "r")
9231 (plus:SI (match_operand:SI 1 "register_operand" "r")
9232 (match_operand:SI 2 "register_operand" "r"))))]
9233 "(@var{test2}) && (@var{test1})"
9234 "(%3) add %2,%1,%0")
9240 @section RTL Templates Transformations
9241 @cindex define_subst
9243 For some hardware architectures there are common cases when the RTL
9244 templates for the instructions can be derived from the other RTL
9245 templates using simple transformations. E.g., @file{i386.md} contains
9246 an RTL template for the ordinary @code{sub} instruction---
9247 @code{*subsi_1}, and for the @code{sub} instruction with subsequent
9248 zero-extension---@code{*subsi_1_zext}. Such cases can be easily
9249 implemented by a single meta-template capable of generating a modified
9250 case based on the initial one:
9252 @findex define_subst
9254 (define_subst "@var{name}"
9255 [@var{input-template}]
9257 [@var{output-template}])
9259 @var{input-template} is a pattern describing the source RTL template,
9260 which will be transformed.
9262 @var{condition} is a C expression that is conjunct with the condition
9263 from the input-template to generate a condition to be used in the
9266 @var{output-template} is a pattern that will be used in the resulting
9269 @code{define_subst} mechanism is tightly coupled with the notion of the
9270 subst attribute (@pxref{Subst Iterators}). The use of
9271 @code{define_subst} is triggered by a reference to a subst attribute in
9272 the transforming RTL template. This reference initiates duplication of
9273 the source RTL template and substitution of the attributes with their
9274 values. The source RTL template is left unchanged, while the copy is
9275 transformed by @code{define_subst}. This transformation can fail in the
9276 case when the source RTL template is not matched against the
9277 input-template of the @code{define_subst}. In such case the copy is
9280 @code{define_subst} can be used only in @code{define_insn} and
9281 @code{define_expand}, it cannot be used in other expressions (e.g. in
9282 @code{define_insn_and_split}).
9285 * Define Subst Example:: Example of @code{define_subst} work.
9286 * Define Subst Pattern Matching:: Process of template comparison.
9287 * Define Subst Output Template:: Generation of output template.
9290 @node Define Subst Example
9291 @subsection @code{define_subst} Example
9292 @cindex define_subst
9294 To illustrate how @code{define_subst} works, let us examine a simple
9295 template transformation.
9297 Suppose there are two kinds of instructions: one that touches flags and
9298 the other that does not. The instructions of the second type could be
9299 generated with the following @code{define_subst}:
9302 (define_subst "add_clobber_subst"
9303 [(set (match_operand:SI 0 "" "")
9304 (match_operand:SI 1 "" ""))]
9308 (clobber (reg:CC FLAGS_REG))]
9311 This @code{define_subst} can be applied to any RTL pattern containing
9312 @code{set} of mode SI and generates a copy with clobber when it is
9315 Assume there is an RTL template for a @code{max} instruction to be used
9316 in @code{define_subst} mentioned above:
9319 (define_insn "maxsi"
9320 [(set (match_operand:SI 0 "register_operand" "=r")
9322 (match_operand:SI 1 "register_operand" "r")
9323 (match_operand:SI 2 "register_operand" "r")))]
9325 "max\t@{%2, %1, %0|%0, %1, %2@}"
9329 To mark the RTL template for @code{define_subst} application,
9330 subst-attributes are used. They should be declared in advance:
9333 (define_subst_attr "add_clobber_name" "add_clobber_subst" "_noclobber" "_clobber")
9336 Here @samp{add_clobber_name} is the attribute name,
9337 @samp{add_clobber_subst} is the name of the corresponding
9338 @code{define_subst}, the third argument (@samp{_noclobber}) is the
9339 attribute value that would be substituted into the unchanged version of
9340 the source RTL template, and the last argument (@samp{_clobber}) is the
9341 value that would be substituted into the second, transformed,
9342 version of the RTL template.
9344 Once the subst-attribute has been defined, it should be used in RTL
9345 templates which need to be processed by the @code{define_subst}. So,
9346 the original RTL template should be changed:
9349 (define_insn "maxsi<add_clobber_name>"
9350 [(set (match_operand:SI 0 "register_operand" "=r")
9352 (match_operand:SI 1 "register_operand" "r")
9353 (match_operand:SI 2 "register_operand" "r")))]
9355 "max\t@{%2, %1, %0|%0, %1, %2@}"
9359 The result of the @code{define_subst} usage would look like the following:
9362 (define_insn "maxsi_noclobber"
9363 [(set (match_operand:SI 0 "register_operand" "=r")
9365 (match_operand:SI 1 "register_operand" "r")
9366 (match_operand:SI 2 "register_operand" "r")))]
9368 "max\t@{%2, %1, %0|%0, %1, %2@}"
9370 (define_insn "maxsi_clobber"
9371 [(set (match_operand:SI 0 "register_operand" "=r")
9373 (match_operand:SI 1 "register_operand" "r")
9374 (match_operand:SI 2 "register_operand" "r")))
9375 (clobber (reg:CC FLAGS_REG))]
9377 "max\t@{%2, %1, %0|%0, %1, %2@}"
9381 @node Define Subst Pattern Matching
9382 @subsection Pattern Matching in @code{define_subst}
9383 @cindex define_subst
9385 All expressions, allowed in @code{define_insn} or @code{define_expand},
9386 are allowed in the input-template of @code{define_subst}, except
9387 @code{match_par_dup}, @code{match_scratch}, @code{match_parallel}. The
9388 meanings of expressions in the input-template were changed:
9390 @code{match_operand} matches any expression (possibly, a subtree in
9391 RTL-template), if modes of the @code{match_operand} and this expression
9392 are the same, or mode of the @code{match_operand} is @code{VOIDmode}, or
9393 this expression is @code{match_dup}, @code{match_op_dup}. If the
9394 expression is @code{match_operand} too, and predicate of
9395 @code{match_operand} from the input pattern is not empty, then the
9396 predicates are compared. That can be used for more accurate filtering
9397 of accepted RTL-templates.
9399 @code{match_operator} matches common operators (like @code{plus},
9400 @code{minus}), @code{unspec}, @code{unspec_volatile} operators and
9401 @code{match_operator}s from the original pattern if the modes match and
9402 @code{match_operator} from the input pattern has the same number of
9403 operands as the operator from the original pattern.
9405 @node Define Subst Output Template
9406 @subsection Generation of output template in @code{define_subst}
9407 @cindex define_subst
9409 If all necessary checks for @code{define_subst} application pass, a new
9410 RTL-pattern, based on the output-template, is created to replace the old
9411 template. Like in input-patterns, meanings of some RTL expressions are
9412 changed when they are used in output-patterns of a @code{define_subst}.
9413 Thus, @code{match_dup} is used for copying the whole expression from the
9414 original pattern, which matched corresponding @code{match_operand} from
9417 @code{match_dup N} is used in the output template to be replaced with
9418 the expression from the original pattern, which matched
9419 @code{match_operand N} from the input pattern. As a consequence,
9420 @code{match_dup} cannot be used to point to @code{match_operand}s from
9421 the output pattern, it should always refer to a @code{match_operand}
9422 from the input pattern.
9424 In the output template one can refer to the expressions from the
9425 original pattern and create new ones. For instance, some operands could
9426 be added by means of standard @code{match_operand}.
9428 After replacing @code{match_dup} with some RTL-subtree from the original
9429 pattern, it could happen that several @code{match_operand}s in the
9430 output pattern have the same indexes. It is unknown, how many and what
9431 indexes would be used in the expression which would replace
9432 @code{match_dup}, so such conflicts in indexes are inevitable. To
9433 overcome this issue, @code{match_operands} and @code{match_operators},
9434 which were introduced into the output pattern, are renumerated when all
9435 @code{match_dup}s are replaced.
9437 Number of alternatives in @code{match_operand}s introduced into the
9438 output template @code{M} could differ from the number of alternatives in
9439 the original pattern @code{N}, so in the resultant pattern there would
9440 be @code{N*M} alternatives. Thus, constraints from the original pattern
9441 would be duplicated @code{N} times, constraints from the output pattern
9442 would be duplicated @code{M} times, producing all possible combinations.
9446 @node Constant Definitions
9447 @section Constant Definitions
9448 @cindex constant definitions
9449 @findex define_constants
9451 Using literal constants inside instruction patterns reduces legibility and
9452 can be a maintenance problem.
9454 To overcome this problem, you may use the @code{define_constants}
9455 expression. It contains a vector of name-value pairs. From that
9456 point on, wherever any of the names appears in the MD file, it is as
9457 if the corresponding value had been written instead. You may use
9458 @code{define_constants} multiple times; each appearance adds more
9459 constants to the table. It is an error to redefine a constant with
9462 To come back to the a29k load multiple example, instead of
9466 [(match_parallel 0 "load_multiple_operation"
9467 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
9468 (match_operand:SI 2 "memory_operand" "m"))
9470 (clobber (reg:SI 179))])]
9486 [(match_parallel 0 "load_multiple_operation"
9487 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
9488 (match_operand:SI 2 "memory_operand" "m"))
9490 (clobber (reg:SI R_CR))])]
9495 The constants that are defined with a define_constant are also output
9496 in the insn-codes.h header file as #defines.
9498 @cindex enumerations
9499 @findex define_c_enum
9500 You can also use the machine description file to define enumerations.
9501 Like the constants defined by @code{define_constant}, these enumerations
9502 are visible to both the machine description file and the main C code.
9504 The syntax is as follows:
9507 (define_c_enum "@var{name}" [
9515 This definition causes the equivalent of the following C code to appear
9516 in @file{insn-constants.h}:
9523 @var{valuen} = @var{n}
9525 #define NUM_@var{cname}_VALUES (@var{n} + 1)
9528 where @var{cname} is the capitalized form of @var{name}.
9529 It also makes each @var{valuei} available in the machine description
9530 file, just as if it had been declared with:
9533 (define_constants [(@var{valuei} @var{i})])
9536 Each @var{valuei} is usually an upper-case identifier and usually
9537 begins with @var{cname}.
9539 You can split the enumeration definition into as many statements as
9540 you like. The above example is directly equivalent to:
9543 (define_c_enum "@var{name}" [@var{value0}])
9544 (define_c_enum "@var{name}" [@var{value1}])
9546 (define_c_enum "@var{name}" [@var{valuen}])
9549 Splitting the enumeration helps to improve the modularity of each
9550 individual @code{.md} file. For example, if a port defines its
9551 synchronization instructions in a separate @file{sync.md} file,
9552 it is convenient to define all synchronization-specific enumeration
9553 values in @file{sync.md} rather than in the main @file{.md} file.
9555 Some enumeration names have special significance to GCC:
9559 @findex unspec_volatile
9560 If an enumeration called @code{unspecv} is defined, GCC will use it
9561 when printing out @code{unspec_volatile} expressions. For example:
9564 (define_c_enum "unspecv" [
9569 causes GCC to print @samp{(unspec_volatile @dots{} 0)} as:
9572 (unspec_volatile ... UNSPECV_BLOCKAGE)
9577 If an enumeration called @code{unspec} is defined, GCC will use
9578 it when printing out @code{unspec} expressions. GCC will also use
9579 it when printing out @code{unspec_volatile} expressions unless an
9580 @code{unspecv} enumeration is also defined. You can therefore
9581 decide whether to keep separate enumerations for volatile and
9582 non-volatile expressions or whether to use the same enumeration
9587 @anchor{define_enum}
9588 Another way of defining an enumeration is to use @code{define_enum}:
9591 (define_enum "@var{name}" [
9599 This directive implies:
9602 (define_c_enum "@var{name}" [
9603 @var{cname}_@var{cvalue0}
9604 @var{cname}_@var{cvalue1}
9606 @var{cname}_@var{cvaluen}
9610 @findex define_enum_attr
9611 where @var{cvaluei} is the capitalized form of @var{valuei}.
9612 However, unlike @code{define_c_enum}, the enumerations defined
9613 by @code{define_enum} can be used in attribute specifications
9614 (@pxref{define_enum_attr}).
9619 @cindex iterators in @file{.md} files
9621 Ports often need to define similar patterns for more than one machine
9622 mode or for more than one rtx code. GCC provides some simple iterator
9623 facilities to make this process easier.
9626 * Mode Iterators:: Generating variations of patterns for different modes.
9627 * Code Iterators:: Doing the same for codes.
9628 * Int Iterators:: Doing the same for integers.
9629 * Subst Iterators:: Generating variations of patterns for define_subst.
9632 @node Mode Iterators
9633 @subsection Mode Iterators
9634 @cindex mode iterators in @file{.md} files
9636 Ports often need to define similar patterns for two or more different modes.
9641 If a processor has hardware support for both single and double
9642 floating-point arithmetic, the @code{SFmode} patterns tend to be
9643 very similar to the @code{DFmode} ones.
9646 If a port uses @code{SImode} pointers in one configuration and
9647 @code{DImode} pointers in another, it will usually have very similar
9648 @code{SImode} and @code{DImode} patterns for manipulating pointers.
9651 Mode iterators allow several patterns to be instantiated from one
9652 @file{.md} file template. They can be used with any type of
9653 rtx-based construct, such as a @code{define_insn},
9654 @code{define_split}, or @code{define_peephole2}.
9657 * Defining Mode Iterators:: Defining a new mode iterator.
9658 * Substitutions:: Combining mode iterators with substitutions
9659 * Examples:: Examples
9662 @node Defining Mode Iterators
9663 @subsubsection Defining Mode Iterators
9664 @findex define_mode_iterator
9666 The syntax for defining a mode iterator is:
9669 (define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") @dots{} (@var{moden} "@var{condn}")])
9672 This allows subsequent @file{.md} file constructs to use the mode suffix
9673 @code{:@var{name}}. Every construct that does so will be expanded
9674 @var{n} times, once with every use of @code{:@var{name}} replaced by
9675 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
9676 and so on. In the expansion for a particular @var{modei}, every
9677 C condition will also require that @var{condi} be true.
9682 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
9685 defines a new mode suffix @code{:P}. Every construct that uses
9686 @code{:P} will be expanded twice, once with every @code{:P} replaced
9687 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
9688 The @code{:SI} version will only apply if @code{Pmode == SImode} and
9689 the @code{:DI} version will only apply if @code{Pmode == DImode}.
9691 As with other @file{.md} conditions, an empty string is treated
9692 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
9693 to @code{@var{mode}}. For example:
9696 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
9699 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
9700 but that the @code{:SI} expansion has no such constraint.
9702 Iterators are applied in the order they are defined. This can be
9703 significant if two iterators are used in a construct that requires
9704 substitutions. @xref{Substitutions}.
9707 @subsubsection Substitution in Mode Iterators
9708 @findex define_mode_attr
9710 If an @file{.md} file construct uses mode iterators, each version of the
9711 construct will often need slightly different strings or modes. For
9716 When a @code{define_expand} defines several @code{add@var{m}3} patterns
9717 (@pxref{Standard Names}), each expander will need to use the
9718 appropriate mode name for @var{m}.
9721 When a @code{define_insn} defines several instruction patterns,
9722 each instruction will often use a different assembler mnemonic.
9725 When a @code{define_insn} requires operands with different modes,
9726 using an iterator for one of the operand modes usually requires a specific
9727 mode for the other operand(s).
9730 GCC supports such variations through a system of ``mode attributes''.
9731 There are two standard attributes: @code{mode}, which is the name of
9732 the mode in lower case, and @code{MODE}, which is the same thing in
9733 upper case. You can define other attributes using:
9736 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") @dots{} (@var{moden} "@var{valuen}")])
9739 where @var{name} is the name of the attribute and @var{valuei}
9740 is the value associated with @var{modei}.
9742 When GCC replaces some @var{:iterator} with @var{:mode}, it will scan
9743 each string and mode in the pattern for sequences of the form
9744 @code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a
9745 mode attribute. If the attribute is defined for @var{mode}, the whole
9746 @code{<@dots{}>} sequence will be replaced by the appropriate attribute
9749 For example, suppose an @file{.md} file has:
9752 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
9753 (define_mode_attr load [(SI "lw") (DI "ld")])
9756 If one of the patterns that uses @code{:P} contains the string
9757 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
9758 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
9761 Here is an example of using an attribute for a mode:
9764 (define_mode_iterator LONG [SI DI])
9765 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
9766 (define_insn @dots{}
9767 (sign_extend:LONG (match_operand:<LONG:SHORT> @dots{})) @dots{})
9770 The @code{@var{iterator}:} prefix may be omitted, in which case the
9771 substitution will be attempted for every iterator expansion.
9774 @subsubsection Mode Iterator Examples
9776 Here is an example from the MIPS port. It defines the following
9777 modes and attributes (among others):
9780 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
9781 (define_mode_attr d [(SI "") (DI "d")])
9784 and uses the following template to define both @code{subsi3}
9788 (define_insn "sub<mode>3"
9789 [(set (match_operand:GPR 0 "register_operand" "=d")
9790 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
9791 (match_operand:GPR 2 "register_operand" "d")))]
9794 [(set_attr "type" "arith")
9795 (set_attr "mode" "<MODE>")])
9798 This is exactly equivalent to:
9801 (define_insn "subsi3"
9802 [(set (match_operand:SI 0 "register_operand" "=d")
9803 (minus:SI (match_operand:SI 1 "register_operand" "d")
9804 (match_operand:SI 2 "register_operand" "d")))]
9807 [(set_attr "type" "arith")
9808 (set_attr "mode" "SI")])
9810 (define_insn "subdi3"
9811 [(set (match_operand:DI 0 "register_operand" "=d")
9812 (minus:DI (match_operand:DI 1 "register_operand" "d")
9813 (match_operand:DI 2 "register_operand" "d")))]
9816 [(set_attr "type" "arith")
9817 (set_attr "mode" "DI")])
9820 @node Code Iterators
9821 @subsection Code Iterators
9822 @cindex code iterators in @file{.md} files
9823 @findex define_code_iterator
9824 @findex define_code_attr
9826 Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}.
9831 (define_code_iterator @var{name} [(@var{code1} "@var{cond1}") @dots{} (@var{coden} "@var{condn}")])
9834 defines a pseudo rtx code @var{name} that can be instantiated as
9835 @var{codei} if condition @var{condi} is true. Each @var{codei}
9836 must have the same rtx format. @xref{RTL Classes}.
9838 As with mode iterators, each pattern that uses @var{name} will be
9839 expanded @var{n} times, once with all uses of @var{name} replaced by
9840 @var{code1}, once with all uses replaced by @var{code2}, and so on.
9841 @xref{Defining Mode Iterators}.
9843 It is possible to define attributes for codes as well as for modes.
9844 There are two standard code attributes: @code{code}, the name of the
9845 code in lower case, and @code{CODE}, the name of the code in upper case.
9846 Other attributes are defined using:
9849 (define_code_attr @var{name} [(@var{code1} "@var{value1}") @dots{} (@var{coden} "@var{valuen}")])
9852 Here's an example of code iterators in action, taken from the MIPS port:
9855 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
9856 eq ne gt ge lt le gtu geu ltu leu])
9858 (define_expand "b<code>"
9860 (if_then_else (any_cond:CC (cc0)
9862 (label_ref (match_operand 0 ""))
9866 gen_conditional_branch (operands, <CODE>);
9871 This is equivalent to:
9874 (define_expand "bunordered"
9876 (if_then_else (unordered:CC (cc0)
9878 (label_ref (match_operand 0 ""))
9882 gen_conditional_branch (operands, UNORDERED);
9886 (define_expand "bordered"
9888 (if_then_else (ordered:CC (cc0)
9890 (label_ref (match_operand 0 ""))
9894 gen_conditional_branch (operands, ORDERED);
9902 @subsection Int Iterators
9903 @cindex int iterators in @file{.md} files
9904 @findex define_int_iterator
9905 @findex define_int_attr
9907 Int iterators operate in a similar way to code iterators. @xref{Code Iterators}.
9912 (define_int_iterator @var{name} [(@var{int1} "@var{cond1}") @dots{} (@var{intn} "@var{condn}")])
9915 defines a pseudo integer constant @var{name} that can be instantiated as
9916 @var{inti} if condition @var{condi} is true. Each @var{int}
9917 must have the same rtx format. @xref{RTL Classes}. Int iterators can appear
9918 in only those rtx fields that have 'i' as the specifier. This means that
9919 each @var{int} has to be a constant defined using define_constant or
9922 As with mode and code iterators, each pattern that uses @var{name} will be
9923 expanded @var{n} times, once with all uses of @var{name} replaced by
9924 @var{int1}, once with all uses replaced by @var{int2}, and so on.
9925 @xref{Defining Mode Iterators}.
9927 It is possible to define attributes for ints as well as for codes and modes.
9928 Attributes are defined using:
9931 (define_int_attr @var{name} [(@var{int1} "@var{value1}") @dots{} (@var{intn} "@var{valuen}")])
9934 Here's an example of int iterators in action, taken from the ARM port:
9937 (define_int_iterator QABSNEG [UNSPEC_VQABS UNSPEC_VQNEG])
9939 (define_int_attr absneg [(UNSPEC_VQABS "abs") (UNSPEC_VQNEG "neg")])
9941 (define_insn "neon_vq<absneg><mode>"
9942 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
9943 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
9944 (match_operand:SI 2 "immediate_operand" "i")]
9947 "vq<absneg>.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
9948 [(set_attr "type" "neon_vqneg_vqabs")]
9953 This is equivalent to:
9956 (define_insn "neon_vqabs<mode>"
9957 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
9958 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
9959 (match_operand:SI 2 "immediate_operand" "i")]
9962 "vqabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
9963 [(set_attr "type" "neon_vqneg_vqabs")]
9966 (define_insn "neon_vqneg<mode>"
9967 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
9968 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
9969 (match_operand:SI 2 "immediate_operand" "i")]
9972 "vqneg.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
9973 [(set_attr "type" "neon_vqneg_vqabs")]
9978 @node Subst Iterators
9979 @subsection Subst Iterators
9980 @cindex subst iterators in @file{.md} files
9981 @findex define_subst
9982 @findex define_subst_attr
9984 Subst iterators are special type of iterators with the following
9985 restrictions: they could not be declared explicitly, they always have
9986 only two values, and they do not have explicit dedicated name.
9987 Subst-iterators are triggered only when corresponding subst-attribute is
9988 used in RTL-pattern.
9990 Subst iterators transform templates in the following way: the templates
9991 are duplicated, the subst-attributes in these templates are replaced
9992 with the corresponding values, and a new attribute is implicitly added
9993 to the given @code{define_insn}/@code{define_expand}. The name of the
9994 added attribute matches the name of @code{define_subst}. Such
9995 attributes are declared implicitly, and it is not allowed to have a
9996 @code{define_attr} named as a @code{define_subst}.
9998 Each subst iterator is linked to a @code{define_subst}. It is declared
9999 implicitly by the first appearance of the corresponding
10000 @code{define_subst_attr}, and it is not allowed to define it explicitly.
10002 Declarations of subst-attributes have the following syntax:
10004 @findex define_subst_attr
10006 (define_subst_attr "@var{name}"
10008 "@var{no-subst-value}"
10009 "@var{subst-applied-value}")
10012 @var{name} is a string with which the given subst-attribute could be
10015 @var{subst-name} shows which @code{define_subst} should be applied to an
10016 RTL-template if the given subst-attribute is present in the
10019 @var{no-subst-value} is a value with which subst-attribute would be
10020 replaced in the first copy of the original RTL-template.
10022 @var{subst-applied-value} is a value with which subst-attribute would be
10023 replaced in the second copy of the original RTL-template.