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Merged with mainline at revision 128810.
[official-gcc.git] / gcc / config / xtensa / xtensa.c
blob79c4d895505392de1bf7145d0733ac72a7f2916f
1 /* Subroutines for insn-output.c for Tensilica's Xtensa architecture.
2 Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007
3 Free Software Foundation, Inc.
4 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
11 version.
12
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #include "config.h"
23 #include "system.h"
24 #include "coretypes.h"
25 #include "tm.h"
26 #include "rtl.h"
27 #include "regs.h"
28 #include "hard-reg-set.h"
29 #include "basic-block.h"
30 #include "real.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
34 #include "insn-attr.h"
35 #include "insn-codes.h"
36 #include "recog.h"
37 #include "output.h"
38 #include "tree.h"
39 #include "expr.h"
40 #include "flags.h"
41 #include "reload.h"
42 #include "tm_p.h"
43 #include "function.h"
44 #include "toplev.h"
45 #include "optabs.h"
46 #include "libfuncs.h"
47 #include "ggc.h"
48 #include "target.h"
49 #include "target-def.h"
50 #include "langhooks.h"
51 #include "tree-gimple.h"
52 #include "df.h"
53
54
55 /* Enumeration for all of the relational tests, so that we can build
56 arrays indexed by the test type, and not worry about the order
57 of EQ, NE, etc. */
58
59 enum internal_test
60 {
61 ITEST_EQ,
62 ITEST_NE,
63 ITEST_GT,
64 ITEST_GE,
65 ITEST_LT,
66 ITEST_LE,
67 ITEST_GTU,
68 ITEST_GEU,
69 ITEST_LTU,
70 ITEST_LEU,
71 ITEST_MAX
72 };
73
74 /* Cached operands, and operator to compare for use in set/branch on
75 condition codes. */
76 rtx branch_cmp[2];
77
78 /* what type of branch to use */
79 enum cmp_type branch_type;
80
81 /* Array giving truth value on whether or not a given hard register
82 can support a given mode. */
83 char xtensa_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
84
85 /* Current frame size calculated by compute_frame_size. */
86 unsigned xtensa_current_frame_size;
87
88 /* Largest block move to handle in-line. */
89 #define LARGEST_MOVE_RATIO 15
90
91 /* Define the structure for the machine field in struct function. */
92 struct machine_function GTY(())
93 {
94 int accesses_prev_frame;
95 bool need_a7_copy;
96 bool vararg_a7;
97 rtx vararg_a7_copy;
98 rtx set_frame_ptr_insn;
99 };
100
101 /* Vector, indexed by hard register number, which contains 1 for a
102 register that is allowable in a candidate for leaf function
103 treatment. */
104
105 const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER] =
106 {
107 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
108 1, 1, 1,
109 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
110 1
111 };
112
113 /* Map hard register number to register class */
114 const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER] =
115 {
116 RL_REGS, SP_REG, RL_REGS, RL_REGS,
117 RL_REGS, RL_REGS, RL_REGS, GR_REGS,
118 RL_REGS, RL_REGS, RL_REGS, RL_REGS,
119 RL_REGS, RL_REGS, RL_REGS, RL_REGS,
120 AR_REGS, AR_REGS, BR_REGS,
121 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
122 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
123 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
124 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
125 ACC_REG,
126 };
127
128 static enum internal_test map_test_to_internal_test (enum rtx_code);
129 static rtx gen_int_relational (enum rtx_code, rtx, rtx, int *);
130 static rtx gen_float_relational (enum rtx_code, rtx, rtx);
131 static rtx gen_conditional_move (rtx);
132 static rtx fixup_subreg_mem (rtx);
133 static struct machine_function * xtensa_init_machine_status (void);
134 static bool xtensa_return_in_msb (const_tree);
135 static void printx (FILE *, signed int);
136 static void xtensa_function_epilogue (FILE *, HOST_WIDE_INT);
137 static rtx xtensa_builtin_saveregs (void);
138 static unsigned int xtensa_multibss_section_type_flags (tree, const char *,
139 int) ATTRIBUTE_UNUSED;
140 static section *xtensa_select_rtx_section (enum machine_mode, rtx,
141 unsigned HOST_WIDE_INT);
142 static bool xtensa_rtx_costs (rtx, int, int, int *);
143 static tree xtensa_build_builtin_va_list (void);
144 static bool xtensa_return_in_memory (const_tree, const_tree);
145 static tree xtensa_gimplify_va_arg_expr (tree, tree, tree *, tree *);
146 static void xtensa_init_builtins (void);
147 static tree xtensa_fold_builtin (tree, tree, bool);
148 static rtx xtensa_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
149
150 static const int reg_nonleaf_alloc_order[FIRST_PSEUDO_REGISTER] =
151 REG_ALLOC_ORDER;
152 \f
153
154 /* This macro generates the assembly code for function exit,
155 on machines that need it. If FUNCTION_EPILOGUE is not defined
156 then individual return instructions are generated for each
157 return statement. Args are same as for FUNCTION_PROLOGUE. */
158
159 #undef TARGET_ASM_FUNCTION_EPILOGUE
160 #define TARGET_ASM_FUNCTION_EPILOGUE xtensa_function_epilogue
161
162 /* These hooks specify assembly directives for creating certain kinds
163 of integer object. */
164
165 #undef TARGET_ASM_ALIGNED_SI_OP
166 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
167
168 #undef TARGET_ASM_SELECT_RTX_SECTION
169 #define TARGET_ASM_SELECT_RTX_SECTION xtensa_select_rtx_section
170
171 #undef TARGET_DEFAULT_TARGET_FLAGS
172 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
173
174 #undef TARGET_RTX_COSTS
175 #define TARGET_RTX_COSTS xtensa_rtx_costs
176 #undef TARGET_ADDRESS_COST
177 #define TARGET_ADDRESS_COST hook_int_rtx_0
178
179 #undef TARGET_BUILD_BUILTIN_VA_LIST
180 #define TARGET_BUILD_BUILTIN_VA_LIST xtensa_build_builtin_va_list
181
182 #undef TARGET_PROMOTE_FUNCTION_ARGS
183 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
184 #undef TARGET_PROMOTE_FUNCTION_RETURN
185 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
186 #undef TARGET_PROMOTE_PROTOTYPES
187 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
188
189 #undef TARGET_RETURN_IN_MEMORY
190 #define TARGET_RETURN_IN_MEMORY xtensa_return_in_memory
191 #undef TARGET_SPLIT_COMPLEX_ARG
192 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
193 #undef TARGET_MUST_PASS_IN_STACK
194 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
195
196 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
197 #define TARGET_EXPAND_BUILTIN_SAVEREGS xtensa_builtin_saveregs
198 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
199 #define TARGET_GIMPLIFY_VA_ARG_EXPR xtensa_gimplify_va_arg_expr
200
201 #undef TARGET_RETURN_IN_MSB
202 #define TARGET_RETURN_IN_MSB xtensa_return_in_msb
203
204 #undef TARGET_INIT_BUILTINS
205 #define TARGET_INIT_BUILTINS xtensa_init_builtins
206 #undef TARGET_FOLD_BUILTIN
207 #define TARGET_FOLD_BUILTIN xtensa_fold_builtin
208 #undef TARGET_EXPAND_BUILTIN
209 #define TARGET_EXPAND_BUILTIN xtensa_expand_builtin
210
211 struct gcc_target targetm = TARGET_INITIALIZER;
212
213 \f
214 /* Functions to test Xtensa immediate operand validity. */
215
216 bool
217 xtensa_simm8 (HOST_WIDE_INT v)
218 {
219 return v >= -128 && v <= 127;
220 }
221
222
223 bool
224 xtensa_simm8x256 (HOST_WIDE_INT v)
225 {
226 return (v & 255) == 0 && (v >= -32768 && v <= 32512);
227 }
228
229
230 bool
231 xtensa_simm12b (HOST_WIDE_INT v)
232 {
233 return v >= -2048 && v <= 2047;
234 }
235
236
237 static bool
238 xtensa_uimm8 (HOST_WIDE_INT v)
239 {
240 return v >= 0 && v <= 255;
241 }
242
243
244 static bool
245 xtensa_uimm8x2 (HOST_WIDE_INT v)
246 {
247 return (v & 1) == 0 && (v >= 0 && v <= 510);
248 }
249
250
251 static bool
252 xtensa_uimm8x4 (HOST_WIDE_INT v)
253 {
254 return (v & 3) == 0 && (v >= 0 && v <= 1020);
255 }
256
257
258 static bool
259 xtensa_b4const (HOST_WIDE_INT v)
260 {
261 switch (v)
262 {
263 case -1:
264 case 1:
265 case 2:
266 case 3:
267 case 4:
268 case 5:
269 case 6:
270 case 7:
271 case 8:
272 case 10:
273 case 12:
274 case 16:
275 case 32:
276 case 64:
277 case 128:
278 case 256:
279 return true;
280 }
281 return false;
282 }
283
284
285 bool
286 xtensa_b4const_or_zero (HOST_WIDE_INT v)
287 {
288 if (v == 0)
289 return true;
290 return xtensa_b4const (v);
291 }
292
293
294 bool
295 xtensa_b4constu (HOST_WIDE_INT v)
296 {
297 switch (v)
298 {
299 case 32768:
300 case 65536:
301 case 2:
302 case 3:
303 case 4:
304 case 5:
305 case 6:
306 case 7:
307 case 8:
308 case 10:
309 case 12:
310 case 16:
311 case 32:
312 case 64:
313 case 128:
314 case 256:
315 return true;
316 }
317 return false;
318 }
319
320
321 bool
322 xtensa_mask_immediate (HOST_WIDE_INT v)
323 {
324 #define MAX_MASK_SIZE 16
325 int mask_size;
326
327 for (mask_size = 1; mask_size <= MAX_MASK_SIZE; mask_size++)
328 {
329 if ((v & 1) == 0)
330 return false;
331 v = v >> 1;
332 if (v == 0)
333 return true;
334 }
335
336 return false;
337 }
338
339
340 /* This is just like the standard true_regnum() function except that it
341 works even when reg_renumber is not initialized. */
342
343 int
344 xt_true_regnum (rtx x)
345 {
346 if (GET_CODE (x) == REG)
347 {
348 if (reg_renumber
349 && REGNO (x) >= FIRST_PSEUDO_REGISTER
350 && reg_renumber[REGNO (x)] >= 0)
351 return reg_renumber[REGNO (x)];
352 return REGNO (x);
353 }
354 if (GET_CODE (x) == SUBREG)
355 {
356 int base = xt_true_regnum (SUBREG_REG (x));
357 if (base >= 0 && base < FIRST_PSEUDO_REGISTER)
358 return base + subreg_regno_offset (REGNO (SUBREG_REG (x)),
359 GET_MODE (SUBREG_REG (x)),
360 SUBREG_BYTE (x), GET_MODE (x));
361 }
362 return -1;
363 }
364
365
366 int
367 xtensa_valid_move (enum machine_mode mode, rtx *operands)
368 {
369 /* Either the destination or source must be a register, and the
370 MAC16 accumulator doesn't count. */
371
372 if (register_operand (operands[0], mode))
373 {
374 int dst_regnum = xt_true_regnum (operands[0]);
375
376 /* The stack pointer can only be assigned with a MOVSP opcode. */
377 if (dst_regnum == STACK_POINTER_REGNUM)
378 return (mode == SImode
379 && register_operand (operands[1], mode)
380 && !ACC_REG_P (xt_true_regnum (operands[1])));
381
382 if (!ACC_REG_P (dst_regnum))
383 return true;
384 }
385 if (register_operand (operands[1], mode))
386 {
387 int src_regnum = xt_true_regnum (operands[1]);
388 if (!ACC_REG_P (src_regnum))
389 return true;
390 }
391 return FALSE;
392 }
393
394
395 int
396 smalloffset_mem_p (rtx op)
397 {
398 if (GET_CODE (op) == MEM)
399 {
400 rtx addr = XEXP (op, 0);
401 if (GET_CODE (addr) == REG)
402 return BASE_REG_P (addr, 0);
403 if (GET_CODE (addr) == PLUS)
404 {
405 rtx offset = XEXP (addr, 0);
406 HOST_WIDE_INT val;
407 if (GET_CODE (offset) != CONST_INT)
408 offset = XEXP (addr, 1);
409 if (GET_CODE (offset) != CONST_INT)
410 return FALSE;
411
412 val = INTVAL (offset);
413 return (val & 3) == 0 && (val >= 0 && val <= 60);
414 }
415 }
416 return FALSE;
417 }
418
419
420 int
421 constantpool_address_p (rtx addr)
422 {
423 rtx sym = addr;
424
425 if (GET_CODE (addr) == CONST)
426 {
427 rtx offset;
428
429 /* Only handle (PLUS (SYM, OFFSET)) form. */
430 addr = XEXP (addr, 0);
431 if (GET_CODE (addr) != PLUS)
432 return FALSE;
433
434 /* Make sure the address is word aligned. */
435 offset = XEXP (addr, 1);
436 if ((GET_CODE (offset) != CONST_INT)
437 || ((INTVAL (offset) & 3) != 0))
438 return FALSE;
439
440 sym = XEXP (addr, 0);
441 }
442
443 if ((GET_CODE (sym) == SYMBOL_REF)
444 && CONSTANT_POOL_ADDRESS_P (sym))
445 return TRUE;
446 return FALSE;
447 }
448
449
450 int
451 constantpool_mem_p (rtx op)
452 {
453 if (GET_CODE (op) == SUBREG)
454 op = SUBREG_REG (op);
455 if (GET_CODE (op) == MEM)
456 return constantpool_address_p (XEXP (op, 0));
457 return FALSE;
458 }
459
460
461 void
462 xtensa_extend_reg (rtx dst, rtx src)
463 {
464 rtx temp = gen_reg_rtx (SImode);
465 rtx shift = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (GET_MODE (src)));
466
467 /* Generate paradoxical subregs as needed so that the modes match. */
468 src = simplify_gen_subreg (SImode, src, GET_MODE (src), 0);
469 dst = simplify_gen_subreg (SImode, dst, GET_MODE (dst), 0);
470
471 emit_insn (gen_ashlsi3 (temp, src, shift));
472 emit_insn (gen_ashrsi3 (dst, temp, shift));
473 }
474
475
476 bool
477 xtensa_mem_offset (unsigned v, enum machine_mode mode)
478 {
479 switch (mode)
480 {
481 case BLKmode:
482 /* Handle the worst case for block moves. See xtensa_expand_block_move
483 where we emit an optimized block move operation if the block can be
484 moved in < "move_ratio" pieces. The worst case is when the block is
485 aligned but has a size of (3 mod 4) (does this happen?) so that the
486 last piece requires a byte load/store. */
487 return (xtensa_uimm8 (v)
488 && xtensa_uimm8 (v + MOVE_MAX * LARGEST_MOVE_RATIO));
489
490 case QImode:
491 return xtensa_uimm8 (v);
492
493 case HImode:
494 return xtensa_uimm8x2 (v);
495
496 case DFmode:
497 return (xtensa_uimm8x4 (v) && xtensa_uimm8x4 (v + 4));
498
499 default:
500 break;
501 }
502
503 return xtensa_uimm8x4 (v);
504 }
505
506
507 /* Make normal rtx_code into something we can index from an array. */
508
509 static enum internal_test
510 map_test_to_internal_test (enum rtx_code test_code)
511 {
512 enum internal_test test = ITEST_MAX;
513
514 switch (test_code)
515 {
516 default: break;
517 case EQ: test = ITEST_EQ; break;
518 case NE: test = ITEST_NE; break;
519 case GT: test = ITEST_GT; break;
520 case GE: test = ITEST_GE; break;
521 case LT: test = ITEST_LT; break;
522 case LE: test = ITEST_LE; break;
523 case GTU: test = ITEST_GTU; break;
524 case GEU: test = ITEST_GEU; break;
525 case LTU: test = ITEST_LTU; break;
526 case LEU: test = ITEST_LEU; break;
527 }
528
529 return test;
530 }
531
532
533 /* Generate the code to compare two integer values. The return value is
534 the comparison expression. */
535
536 static rtx
537 gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
538 rtx cmp0, /* first operand to compare */
539 rtx cmp1, /* second operand to compare */
540 int *p_invert /* whether branch needs to reverse test */)
541 {
542 struct cmp_info
543 {
544 enum rtx_code test_code; /* test code to use in insn */
545 bool (*const_range_p) (HOST_WIDE_INT); /* range check function */
546 int const_add; /* constant to add (convert LE -> LT) */
547 int reverse_regs; /* reverse registers in test */
548 int invert_const; /* != 0 if invert value if cmp1 is constant */
549 int invert_reg; /* != 0 if invert value if cmp1 is register */
550 int unsignedp; /* != 0 for unsigned comparisons. */
551 };
552
553 static struct cmp_info info[ (int)ITEST_MAX ] = {
554
555 { EQ, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* EQ */
556 { NE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* NE */
557
558 { LT, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* GT */
559 { GE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* GE */
560 { LT, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* LT */
561 { GE, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* LE */
562
563 { LTU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* GTU */
564 { GEU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* GEU */
565 { LTU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* LTU */
566 { GEU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* LEU */
567 };
568
569 enum internal_test test;
570 enum machine_mode mode;
571 struct cmp_info *p_info;
572
573 test = map_test_to_internal_test (test_code);
574 gcc_assert (test != ITEST_MAX);
575
576 p_info = &info[ (int)test ];
577
578 mode = GET_MODE (cmp0);
579 if (mode == VOIDmode)
580 mode = GET_MODE (cmp1);
581
582 /* Make sure we can handle any constants given to us. */
583 if (GET_CODE (cmp1) == CONST_INT)
584 {
585 HOST_WIDE_INT value = INTVAL (cmp1);
586 unsigned HOST_WIDE_INT uvalue = (unsigned HOST_WIDE_INT)value;
587
588 /* if the immediate overflows or does not fit in the immediate field,
589 spill it to a register */
590
591 if ((p_info->unsignedp ?
592 (uvalue + p_info->const_add > uvalue) :
593 (value + p_info->const_add > value)) != (p_info->const_add > 0))
594 {
595 cmp1 = force_reg (mode, cmp1);
596 }
597 else if (!(p_info->const_range_p) (value + p_info->const_add))
598 {
599 cmp1 = force_reg (mode, cmp1);
600 }
601 }
602 else if ((GET_CODE (cmp1) != REG) && (GET_CODE (cmp1) != SUBREG))
603 {
604 cmp1 = force_reg (mode, cmp1);
605 }
606
607 /* See if we need to invert the result. */
608 *p_invert = ((GET_CODE (cmp1) == CONST_INT)
609 ? p_info->invert_const
610 : p_info->invert_reg);
611
612 /* Comparison to constants, may involve adding 1 to change a LT into LE.
613 Comparison between two registers, may involve switching operands. */
614 if (GET_CODE (cmp1) == CONST_INT)
615 {
616 if (p_info->const_add != 0)
617 cmp1 = GEN_INT (INTVAL (cmp1) + p_info->const_add);
618
619 }
620 else if (p_info->reverse_regs)
621 {
622 rtx temp = cmp0;
623 cmp0 = cmp1;
624 cmp1 = temp;
625 }
626
627 return gen_rtx_fmt_ee (p_info->test_code, VOIDmode, cmp0, cmp1);
628 }
629
630
631 /* Generate the code to compare two float values. The return value is
632 the comparison expression. */
633
634 static rtx
635 gen_float_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
636 rtx cmp0, /* first operand to compare */
637 rtx cmp1 /* second operand to compare */)
638 {
639 rtx (*gen_fn) (rtx, rtx, rtx);
640 rtx brtmp;
641 int reverse_regs, invert;
642
643 switch (test_code)
644 {
645 case EQ: reverse_regs = 0; invert = 0; gen_fn = gen_seq_sf; break;
646 case NE: reverse_regs = 0; invert = 1; gen_fn = gen_seq_sf; break;
647 case LE: reverse_regs = 0; invert = 0; gen_fn = gen_sle_sf; break;
648 case GT: reverse_regs = 1; invert = 0; gen_fn = gen_slt_sf; break;
649 case LT: reverse_regs = 0; invert = 0; gen_fn = gen_slt_sf; break;
650 case GE: reverse_regs = 1; invert = 0; gen_fn = gen_sle_sf; break;
651 default:
652 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
653 reverse_regs = 0; invert = 0; gen_fn = 0; /* avoid compiler warnings */
654 }
655
656 if (reverse_regs)
657 {
658 rtx temp = cmp0;
659 cmp0 = cmp1;
660 cmp1 = temp;
661 }
662
663 brtmp = gen_rtx_REG (CCmode, FPCC_REGNUM);
664 emit_insn (gen_fn (brtmp, cmp0, cmp1));
665
666 return gen_rtx_fmt_ee (invert ? EQ : NE, VOIDmode, brtmp, const0_rtx);
667 }
668
669
670 void
671 xtensa_expand_conditional_branch (rtx *operands, enum rtx_code test_code)
672 {
673 enum cmp_type type = branch_type;
674 rtx cmp0 = branch_cmp[0];
675 rtx cmp1 = branch_cmp[1];
676 rtx cmp;
677 int invert;
678 rtx label1, label2;
679
680 switch (type)
681 {
682 case CMP_DF:
683 default:
684 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
685
686 case CMP_SI:
687 invert = FALSE;
688 cmp = gen_int_relational (test_code, cmp0, cmp1, &invert);
689 break;
690
691 case CMP_SF:
692 if (!TARGET_HARD_FLOAT)
693 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode,
694 cmp0, cmp1));
695 invert = FALSE;
696 cmp = gen_float_relational (test_code, cmp0, cmp1);
697 break;
698 }
699
700 /* Generate the branch. */
701
702 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
703 label2 = pc_rtx;
704
705 if (invert)
706 {
707 label2 = label1;
708 label1 = pc_rtx;
709 }
710
711 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
712 gen_rtx_IF_THEN_ELSE (VOIDmode, cmp,
713 label1,
714 label2)));
715 }
716
717
718 static rtx
719 gen_conditional_move (rtx cmp)
720 {
721 enum rtx_code code = GET_CODE (cmp);
722 rtx op0 = branch_cmp[0];
723 rtx op1 = branch_cmp[1];
724
725 if (branch_type == CMP_SI)
726 {
727 /* Jump optimization calls get_condition() which canonicalizes
728 comparisons like (GE x <const>) to (GT x <const-1>).
729 Transform those comparisons back to GE, since that is the
730 comparison supported in Xtensa. We shouldn't have to
731 transform <LE x const> comparisons, because neither
732 xtensa_expand_conditional_branch() nor get_condition() will
733 produce them. */
734
735 if ((code == GT) && (op1 == constm1_rtx))
736 {
737 code = GE;
738 op1 = const0_rtx;
739 }
740 cmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
741
742 if (boolean_operator (cmp, VOIDmode))
743 {
744 /* Swap the operands to make const0 second. */
745 if (op0 == const0_rtx)
746 {
747 op0 = op1;
748 op1 = const0_rtx;
749 }
750
751 /* If not comparing against zero, emit a comparison (subtract). */
752 if (op1 != const0_rtx)
753 {
754 op0 = expand_binop (SImode, sub_optab, op0, op1,
755 0, 0, OPTAB_LIB_WIDEN);
756 op1 = const0_rtx;
757 }
758 }
759 else if (branch_operator (cmp, VOIDmode))
760 {
761 /* Swap the operands to make const0 second. */
762 if (op0 == const0_rtx)
763 {
764 op0 = op1;
765 op1 = const0_rtx;
766
767 switch (code)
768 {
769 case LT: code = GE; break;
770 case GE: code = LT; break;
771 default: gcc_unreachable ();
772 }
773 }
774
775 if (op1 != const0_rtx)
776 return 0;
777 }
778 else
779 return 0;
780
781 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
782 }
783
784 if (TARGET_HARD_FLOAT && (branch_type == CMP_SF))
785 return gen_float_relational (code, op0, op1);
786
787 return 0;
788 }
789
790
791 int
792 xtensa_expand_conditional_move (rtx *operands, int isflt)
793 {
794 rtx cmp;
795 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx);
796
797 if (!(cmp = gen_conditional_move (operands[1])))
798 return 0;
799
800 if (isflt)
801 gen_fn = (branch_type == CMP_SI
802 ? gen_movsfcc_internal0
803 : gen_movsfcc_internal1);
804 else
805 gen_fn = (branch_type == CMP_SI
806 ? gen_movsicc_internal0
807 : gen_movsicc_internal1);
808
809 emit_insn (gen_fn (operands[0], XEXP (cmp, 0),
810 operands[2], operands[3], cmp));
811 return 1;
812 }
813
814
815 int
816 xtensa_expand_scc (rtx *operands)
817 {
818 rtx dest = operands[0];
819 rtx cmp = operands[1];
820 rtx one_tmp, zero_tmp;
821 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx);
822
823 if (!(cmp = gen_conditional_move (cmp)))
824 return 0;
825
826 one_tmp = gen_reg_rtx (SImode);
827 zero_tmp = gen_reg_rtx (SImode);
828 emit_insn (gen_movsi (one_tmp, const_true_rtx));
829 emit_insn (gen_movsi (zero_tmp, const0_rtx));
830
831 gen_fn = (branch_type == CMP_SI
832 ? gen_movsicc_internal0
833 : gen_movsicc_internal1);
834 emit_insn (gen_fn (dest, XEXP (cmp, 0), one_tmp, zero_tmp, cmp));
835 return 1;
836 }
837
838
839 /* Split OP[1] into OP[2,3] and likewise for OP[0] into OP[0,1]. MODE is
840 for the output, i.e., the input operands are twice as big as MODE. */
841
842 void
843 xtensa_split_operand_pair (rtx operands[4], enum machine_mode mode)
844 {
845 switch (GET_CODE (operands[1]))
846 {
847 case REG:
848 operands[3] = gen_rtx_REG (mode, REGNO (operands[1]) + 1);
849 operands[2] = gen_rtx_REG (mode, REGNO (operands[1]));
850 break;
851
852 case MEM:
853 operands[3] = adjust_address (operands[1], mode, GET_MODE_SIZE (mode));
854 operands[2] = adjust_address (operands[1], mode, 0);
855 break;
856
857 case CONST_INT:
858 case CONST_DOUBLE:
859 split_double (operands[1], &operands[2], &operands[3]);
860 break;
861
862 default:
863 gcc_unreachable ();
864 }
865
866 switch (GET_CODE (operands[0]))
867 {
868 case REG:
869 operands[1] = gen_rtx_REG (mode, REGNO (operands[0]) + 1);
870 operands[0] = gen_rtx_REG (mode, REGNO (operands[0]));
871 break;
872
873 case MEM:
874 operands[1] = adjust_address (operands[0], mode, GET_MODE_SIZE (mode));
875 operands[0] = adjust_address (operands[0], mode, 0);
876 break;
877
878 default:
879 gcc_unreachable ();
880 }
881 }
882
883
884 /* Emit insns to move operands[1] into operands[0].
885 Return 1 if we have written out everything that needs to be done to
886 do the move. Otherwise, return 0 and the caller will emit the move
887 normally. */
888
889 int
890 xtensa_emit_move_sequence (rtx *operands, enum machine_mode mode)
891 {
892 if (CONSTANT_P (operands[1])
893 && (GET_CODE (operands[1]) != CONST_INT
894 || !xtensa_simm12b (INTVAL (operands[1]))))
895 {
896 if (!TARGET_CONST16)
897 operands[1] = force_const_mem (SImode, operands[1]);
898
899 /* PC-relative loads are always SImode, and CONST16 is only
900 supported in the movsi pattern, so add a SUBREG for any other
901 (smaller) mode. */
902
903 if (mode != SImode)
904 {
905 if (register_operand (operands[0], mode))
906 {
907 operands[0] = simplify_gen_subreg (SImode, operands[0], mode, 0);
908 emit_move_insn (operands[0], operands[1]);
909 return 1;
910 }
911 else
912 {
913 operands[1] = force_reg (SImode, operands[1]);
914 operands[1] = gen_lowpart_SUBREG (mode, operands[1]);
915 }
916 }
917 }
918
919 if (!(reload_in_progress | reload_completed)
920 && !xtensa_valid_move (mode, operands))
921 operands[1] = force_reg (mode, operands[1]);
922
923 operands[1] = xtensa_copy_incoming_a7 (operands[1]);
924
925 /* During reload we don't want to emit (subreg:X (mem:Y)) since that
926 instruction won't be recognized after reload, so we remove the
927 subreg and adjust mem accordingly. */
928 if (reload_in_progress)
929 {
930 operands[0] = fixup_subreg_mem (operands[0]);
931 operands[1] = fixup_subreg_mem (operands[1]);
932 }
933 return 0;
934 }
935
936
937 static rtx
938 fixup_subreg_mem (rtx x)
939 {
940 if (GET_CODE (x) == SUBREG
941 && GET_CODE (SUBREG_REG (x)) == REG
942 && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER)
943 {
944 rtx temp =
945 gen_rtx_SUBREG (GET_MODE (x),
946 reg_equiv_mem [REGNO (SUBREG_REG (x))],
947 SUBREG_BYTE (x));
948 x = alter_subreg (&temp);
949 }
950 return x;
951 }
952
953
954 /* Check if an incoming argument in a7 is expected to be used soon and
955 if OPND is a register or register pair that includes a7. If so,
956 create a new pseudo and copy a7 into that pseudo at the very
957 beginning of the function, followed by the special "set_frame_ptr"
958 unspec_volatile insn. The return value is either the original
959 operand, if it is not a7, or the new pseudo containing a copy of
960 the incoming argument. This is necessary because the register
961 allocator will ignore conflicts with a7 and may either assign some
962 other pseudo to a7 or use a7 as the hard_frame_pointer, clobbering
963 the incoming argument in a7. By copying the argument out of a7 as
964 the very first thing, and then immediately following that with an
965 unspec_volatile to keep the scheduler away, we should avoid any
966 problems. Putting the set_frame_ptr insn at the beginning, with
967 only the a7 copy before it, also makes it easier for the prologue
968 expander to initialize the frame pointer after the a7 copy and to
969 fix up the a7 copy to use the stack pointer instead of the frame
970 pointer. */
971
972 rtx
973 xtensa_copy_incoming_a7 (rtx opnd)
974 {
975 rtx entry_insns = 0;
976 rtx reg, tmp;
977 enum machine_mode mode;
978
979 if (!cfun->machine->need_a7_copy)
980 return opnd;
981
982 /* This function should never be called again once a7 has been copied. */
983 gcc_assert (!cfun->machine->set_frame_ptr_insn);
984
985 mode = GET_MODE (opnd);
986
987 /* The operand using a7 may come in a later instruction, so just return
988 the original operand if it doesn't use a7. */
989 reg = opnd;
990 if (GET_CODE (reg) == SUBREG)
991 {
992 gcc_assert (SUBREG_BYTE (reg) == 0);
993 reg = SUBREG_REG (reg);
994 }
995 if (GET_CODE (reg) != REG
996 || REGNO (reg) > A7_REG
997 || REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) <= A7_REG)
998 return opnd;
999
1000 /* 1-word args will always be in a7; 2-word args in a6/a7. */
1001 gcc_assert (REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) - 1 == A7_REG);
1002
1003 cfun->machine->need_a7_copy = false;
1004
1005 /* Copy a7 to a new pseudo at the function entry. Use gen_raw_REG to
1006 create the REG for a7 so that hard_frame_pointer_rtx is not used. */
1007
1008 start_sequence ();
1009 tmp = gen_reg_rtx (mode);
1010
1011 switch (mode)
1012 {
1013 case DFmode:
1014 case DImode:
1015 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 0),
1016 gen_rtx_REG (SImode, A7_REG - 1)));
1017 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 4),
1018 gen_raw_REG (SImode, A7_REG)));
1019 break;
1020 case SFmode:
1021 emit_insn (gen_movsf_internal (tmp, gen_raw_REG (mode, A7_REG)));
1022 break;
1023 case SImode:
1024 emit_insn (gen_movsi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1025 break;
1026 case HImode:
1027 emit_insn (gen_movhi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1028 break;
1029 case QImode:
1030 emit_insn (gen_movqi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1031 break;
1032 default:
1033 gcc_unreachable ();
1034 }
1035
1036 cfun->machine->set_frame_ptr_insn = emit_insn (gen_set_frame_ptr ());
1037 entry_insns = get_insns ();
1038 end_sequence ();
1039
1040 if (cfun->machine->vararg_a7)
1041 {
1042 /* This is called from within builtin_saveregs, which will insert the
1043 saveregs code at the function entry, ahead of anything placed at
1044 the function entry now. Instead, save the sequence to be inserted
1045 at the beginning of the saveregs code. */
1046 cfun->machine->vararg_a7_copy = entry_insns;
1047 }
1048 else
1049 {
1050 /* Put entry_insns after the NOTE that starts the function. If
1051 this is inside a start_sequence, make the outer-level insn
1052 chain current, so the code is placed at the start of the
1053 function. */
1054 push_topmost_sequence ();
1055 /* Do not use entry_of_function() here. This is called from within
1056 expand_function_start, when the CFG still holds GIMPLE. */
1057 emit_insn_after (entry_insns, get_insns ());
1058 pop_topmost_sequence ();
1059 }
1060
1061 return tmp;
1062 }
1063
1064
1065 /* Try to expand a block move operation to a sequence of RTL move
1066 instructions. If not optimizing, or if the block size is not a
1067 constant, or if the block is too large, the expansion fails and GCC
1068 falls back to calling memcpy().
1069
1070 operands[0] is the destination
1071 operands[1] is the source
1072 operands[2] is the length
1073 operands[3] is the alignment */
1074
1075 int
1076 xtensa_expand_block_move (rtx *operands)
1077 {
1078 static const enum machine_mode mode_from_align[] =
1079 {
1080 VOIDmode, QImode, HImode, VOIDmode, SImode,
1081 };
1082
1083 rtx dst_mem = operands[0];
1084 rtx src_mem = operands[1];
1085 HOST_WIDE_INT bytes, align;
1086 int num_pieces, move_ratio;
1087 rtx temp[2];
1088 enum machine_mode mode[2];
1089 int amount[2];
1090 bool active[2];
1091 int phase = 0;
1092 int next;
1093 int offset_ld = 0;
1094 int offset_st = 0;
1095 rtx x;
1096
1097 /* If this is not a fixed size move, just call memcpy. */
1098 if (!optimize || (GET_CODE (operands[2]) != CONST_INT))
1099 return 0;
1100
1101 bytes = INTVAL (operands[2]);
1102 align = INTVAL (operands[3]);
1103
1104 /* Anything to move? */
1105 if (bytes <= 0)
1106 return 0;
1107
1108 if (align > MOVE_MAX)
1109 align = MOVE_MAX;
1110
1111 /* Decide whether to expand inline based on the optimization level. */
1112 move_ratio = 4;
1113 if (optimize > 2)
1114 move_ratio = LARGEST_MOVE_RATIO;
1115 num_pieces = (bytes / align) + (bytes % align); /* Close enough anyway. */
1116 if (num_pieces > move_ratio)
1117 return 0;
1118
1119 x = XEXP (dst_mem, 0);
1120 if (!REG_P (x))
1121 {
1122 x = force_reg (Pmode, x);
1123 dst_mem = replace_equiv_address (dst_mem, x);
1124 }
1125
1126 x = XEXP (src_mem, 0);
1127 if (!REG_P (x))
1128 {
1129 x = force_reg (Pmode, x);
1130 src_mem = replace_equiv_address (src_mem, x);
1131 }
1132
1133 active[0] = active[1] = false;
1134
1135 do
1136 {
1137 next = phase;
1138 phase ^= 1;
1139
1140 if (bytes > 0)
1141 {
1142 int next_amount;
1143
1144 next_amount = (bytes >= 4 ? 4 : (bytes >= 2 ? 2 : 1));
1145 next_amount = MIN (next_amount, align);
1146
1147 amount[next] = next_amount;
1148 mode[next] = mode_from_align[next_amount];
1149 temp[next] = gen_reg_rtx (mode[next]);
1150
1151 x = adjust_address (src_mem, mode[next], offset_ld);
1152 emit_insn (gen_rtx_SET (VOIDmode, temp[next], x));
1153
1154 offset_ld += next_amount;
1155 bytes -= next_amount;
1156 active[next] = true;
1157 }
1158
1159 if (active[phase])
1160 {
1161 active[phase] = false;
1162
1163 x = adjust_address (dst_mem, mode[phase], offset_st);
1164 emit_insn (gen_rtx_SET (VOIDmode, x, temp[phase]));
1165
1166 offset_st += amount[phase];
1167 }
1168 }
1169 while (active[next]);
1170
1171 return 1;
1172 }
1173
1174
1175 void
1176 xtensa_expand_nonlocal_goto (rtx *operands)
1177 {
1178 rtx goto_handler = operands[1];
1179 rtx containing_fp = operands[3];
1180
1181 /* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code
1182 is too big to generate in-line. */
1183
1184 if (GET_CODE (containing_fp) != REG)
1185 containing_fp = force_reg (Pmode, containing_fp);
1186
1187 goto_handler = copy_rtx (goto_handler);
1188 validate_replace_rtx (virtual_stack_vars_rtx, containing_fp, goto_handler);
1189
1190 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_nonlocal_goto"),
1191 0, VOIDmode, 2,
1192 containing_fp, Pmode,
1193 goto_handler, Pmode);
1194 }
1195
1196
1197 static struct machine_function *
1198 xtensa_init_machine_status (void)
1199 {
1200 return ggc_alloc_cleared (sizeof (struct machine_function));
1201 }
1202
1203
1204 /* Shift VAL of mode MODE left by COUNT bits. */
1205
1206 static inline rtx
1207 xtensa_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
1208 {
1209 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
1210 NULL_RTX, 1, OPTAB_DIRECT);
1211 return expand_simple_binop (SImode, ASHIFT, val, count,
1212 NULL_RTX, 1, OPTAB_DIRECT);
1213 }
1214
1215
1216 /* Structure to hold the initial parameters for a compare_and_swap operation
1217 in HImode and QImode. */
1218
1219 struct alignment_context
1220 {
1221 rtx memsi; /* SI aligned memory location. */
1222 rtx shift; /* Bit offset with regard to lsb. */
1223 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
1224 rtx modemaski; /* ~modemask */
1225 };
1226
1227
1228 /* Initialize structure AC for word access to HI and QI mode memory. */
1229
1230 static void
1231 init_alignment_context (struct alignment_context *ac, rtx mem)
1232 {
1233 enum machine_mode mode = GET_MODE (mem);
1234 rtx byteoffset = NULL_RTX;
1235 bool aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
1236
1237 if (aligned)
1238 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
1239 else
1240 {
1241 /* Alignment is unknown. */
1242 rtx addr, align;
1243
1244 /* Force the address into a register. */
1245 addr = force_reg (Pmode, XEXP (mem, 0));
1246
1247 /* Align it to SImode. */
1248 align = expand_simple_binop (Pmode, AND, addr,
1249 GEN_INT (-GET_MODE_SIZE (SImode)),
1250 NULL_RTX, 1, OPTAB_DIRECT);
1251 /* Generate MEM. */
1252 ac->memsi = gen_rtx_MEM (SImode, align);
1253 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
1254 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
1255 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
1256
1257 byteoffset = expand_simple_binop (Pmode, AND, addr,
1258 GEN_INT (GET_MODE_SIZE (SImode) - 1),
1259 NULL_RTX, 1, OPTAB_DIRECT);
1260 }
1261
1262 /* Calculate shiftcount. */
1263 if (TARGET_BIG_ENDIAN)
1264 {
1265 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
1266 if (!aligned)
1267 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
1268 NULL_RTX, 1, OPTAB_DIRECT);
1269 }
1270 else
1271 {
1272 if (aligned)
1273 ac->shift = NULL_RTX;
1274 else
1275 ac->shift = byteoffset;
1276 }
1277
1278 if (ac->shift != NULL_RTX)
1279 {
1280 /* Shift is the byte count, but we need the bitcount. */
1281 ac->shift = expand_simple_binop (SImode, MULT, ac->shift,
1282 GEN_INT (BITS_PER_UNIT),
1283 NULL_RTX, 1, OPTAB_DIRECT);
1284 ac->modemask = expand_simple_binop (SImode, ASHIFT,
1285 GEN_INT (GET_MODE_MASK (mode)),
1286 ac->shift,
1287 NULL_RTX, 1, OPTAB_DIRECT);
1288 }
1289 else
1290 ac->modemask = GEN_INT (GET_MODE_MASK (mode));
1291
1292 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
1293 }
1294
1295
1296 /* Expand an atomic compare and swap operation for HImode and QImode.
1297 MEM is the memory location, CMP the old value to compare MEM with
1298 and NEW the value to set if CMP == MEM. */
1299
1300 void
1301 xtensa_expand_compare_and_swap (rtx target, rtx mem, rtx cmp, rtx new)
1302 {
1303 enum machine_mode mode = GET_MODE (mem);
1304 struct alignment_context ac;
1305 rtx tmp, cmpv, newv, val;
1306 rtx oldval = gen_reg_rtx (SImode);
1307 rtx res = gen_reg_rtx (SImode);
1308 rtx csloop = gen_label_rtx ();
1309 rtx csend = gen_label_rtx ();
1310
1311 init_alignment_context (&ac, mem);
1312
1313 if (ac.shift != NULL_RTX)
1314 {
1315 cmp = xtensa_expand_mask_and_shift (cmp, mode, ac.shift);
1316 new = xtensa_expand_mask_and_shift (new, mode, ac.shift);
1317 }
1318
1319 /* Load the surrounding word into VAL with the MEM value masked out. */
1320 val = force_reg (SImode, expand_simple_binop (SImode, AND, ac.memsi,
1321 ac.modemaski, NULL_RTX, 1,
1322 OPTAB_DIRECT));
1323 emit_label (csloop);
1324
1325 /* Patch CMP and NEW into VAL at correct position. */
1326 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
1327 NULL_RTX, 1, OPTAB_DIRECT));
1328 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new, val,
1329 NULL_RTX, 1, OPTAB_DIRECT));
1330
1331 /* Jump to end if we're done. */
1332 emit_insn (gen_sync_compare_and_swapsi (res, ac.memsi, cmpv, newv));
1333 emit_cmp_and_jump_insns (res, cmpv, EQ, const0_rtx, SImode, true, csend);
1334
1335 /* Check for changes outside mode. */
1336 emit_move_insn (oldval, val);
1337 tmp = expand_simple_binop (SImode, AND, res, ac.modemaski,
1338 val, 1, OPTAB_DIRECT);
1339 if (tmp != val)
1340 emit_move_insn (val, tmp);
1341
1342 /* Loop internal if so. */
1343 emit_cmp_and_jump_insns (oldval, val, NE, const0_rtx, SImode, true, csloop);
1344
1345 emit_label (csend);
1346
1347 /* Return the correct part of the bitfield. */
1348 convert_move (target,
1349 (ac.shift == NULL_RTX ? res
1350 : expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
1351 NULL_RTX, 1, OPTAB_DIRECT)),
1352 1);
1353 }
1354
1355
1356 /* Expand an atomic operation CODE of mode MODE (either HImode or QImode --
1357 the default expansion works fine for SImode). MEM is the memory location
1358 and VAL the value to play with. If AFTER is true then store the value
1359 MEM holds after the operation, if AFTER is false then store the value MEM
1360 holds before the operation. If TARGET is zero then discard that value, else
1361 store it to TARGET. */
1362
1363 void
1364 xtensa_expand_atomic (enum rtx_code code, rtx target, rtx mem, rtx val,
1365 bool after)
1366 {
1367 enum machine_mode mode = GET_MODE (mem);
1368 struct alignment_context ac;
1369 rtx csloop = gen_label_rtx ();
1370 rtx cmp, tmp;
1371 rtx old = gen_reg_rtx (SImode);
1372 rtx new = gen_reg_rtx (SImode);
1373 rtx orig = NULL_RTX;
1374
1375 init_alignment_context (&ac, mem);
1376
1377 /* Prepare values before the compare-and-swap loop. */
1378 if (ac.shift != NULL_RTX)
1379 val = xtensa_expand_mask_and_shift (val, mode, ac.shift);
1380 switch (code)
1381 {
1382 case PLUS:
1383 case MINUS:
1384 orig = gen_reg_rtx (SImode);
1385 convert_move (orig, val, 1);
1386 break;
1387
1388 case SET:
1389 case IOR:
1390 case XOR:
1391 break;
1392
1393 case MULT: /* NAND */
1394 case AND:
1395 /* val = "11..1<val>11..1" */
1396 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
1397 NULL_RTX, 1, OPTAB_DIRECT);
1398 break;
1399
1400 default:
1401 gcc_unreachable ();
1402 }
1403
1404 /* Load full word. Subsequent loads are performed by S32C1I. */
1405 cmp = force_reg (SImode, ac.memsi);
1406
1407 emit_label (csloop);
1408 emit_move_insn (old, cmp);
1409
1410 switch (code)
1411 {
1412 case PLUS:
1413 case MINUS:
1414 val = expand_simple_binop (SImode, code, old, orig,
1415 NULL_RTX, 1, OPTAB_DIRECT);
1416 val = expand_simple_binop (SImode, AND, val, ac.modemask,
1417 NULL_RTX, 1, OPTAB_DIRECT);
1418 /* FALLTHRU */
1419 case SET:
1420 tmp = expand_simple_binop (SImode, AND, old, ac.modemaski,
1421 NULL_RTX, 1, OPTAB_DIRECT);
1422 tmp = expand_simple_binop (SImode, IOR, tmp, val,
1423 new, 1, OPTAB_DIRECT);
1424 break;
1425
1426 case AND:
1427 case IOR:
1428 case XOR:
1429 tmp = expand_simple_binop (SImode, code, old, val,
1430 new, 1, OPTAB_DIRECT);
1431 break;
1432
1433 case MULT: /* NAND */
1434 tmp = expand_simple_binop (SImode, XOR, old, ac.modemask,
1435 NULL_RTX, 1, OPTAB_DIRECT);
1436 tmp = expand_simple_binop (SImode, AND, tmp, val,
1437 new, 1, OPTAB_DIRECT);
1438 break;
1439
1440 default:
1441 gcc_unreachable ();
1442 }
1443
1444 if (tmp != new)
1445 emit_move_insn (new, tmp);
1446 emit_insn (gen_sync_compare_and_swapsi (cmp, ac.memsi, old, new));
1447 emit_cmp_and_jump_insns (cmp, old, NE, const0_rtx, SImode, true, csloop);
1448
1449 if (target)
1450 {
1451 tmp = (after ? new : cmp);
1452 convert_move (target,
1453 (ac.shift == NULL_RTX ? tmp
1454 : expand_simple_binop (SImode, LSHIFTRT, tmp, ac.shift,
1455 NULL_RTX, 1, OPTAB_DIRECT)),
1456 1);
1457 }
1458 }
1459
1460
1461 void
1462 xtensa_setup_frame_addresses (void)
1463 {
1464 /* Set flag to cause FRAME_POINTER_REQUIRED to be set. */
1465 cfun->machine->accesses_prev_frame = 1;
1466
1467 emit_library_call
1468 (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_libgcc_window_spill"),
1469 0, VOIDmode, 0);
1470 }
1471
1472
1473 /* Emit the assembly for the end of a zero-cost loop. Normally we just emit
1474 a comment showing where the end of the loop is. However, if there is a
1475 label or a branch at the end of the loop then we need to place a nop
1476 there. If the loop ends with a label we need the nop so that branches
1477 targeting that label will target the nop (and thus remain in the loop),
1478 instead of targeting the instruction after the loop (and thus exiting
1479 the loop). If the loop ends with a branch, we need the nop in case the
1480 branch is targeting a location inside the loop. When the branch
1481 executes it will cause the loop count to be decremented even if it is
1482 taken (because it is the last instruction in the loop), so we need to
1483 nop after the branch to prevent the loop count from being decremented
1484 when the branch is taken. */
1485
1486 void
1487 xtensa_emit_loop_end (rtx insn, rtx *operands)
1488 {
1489 char done = 0;
1490
1491 for (insn = PREV_INSN (insn); insn && !done; insn = PREV_INSN (insn))
1492 {
1493 switch (GET_CODE (insn))
1494 {
1495 case NOTE:
1496 case BARRIER:
1497 break;
1498
1499 case CODE_LABEL:
1500 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands);
1501 done = 1;
1502 break;
1503
1504 default:
1505 {
1506 rtx body = PATTERN (insn);
1507
1508 if (GET_CODE (body) == JUMP_INSN)
1509 {
1510 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands);
1511 done = 1;
1512 }
1513 else if ((GET_CODE (body) != USE)
1514 && (GET_CODE (body) != CLOBBER))
1515 done = 1;
1516 }
1517 break;
1518 }
1519 }
1520
1521 output_asm_insn ("# loop end for %0", operands);
1522 }
1523
1524
1525 char *
1526 xtensa_emit_branch (bool inverted, bool immed, rtx *operands)
1527 {
1528 static char result[64];
1529 enum rtx_code code;
1530 const char *op;
1531
1532 code = GET_CODE (operands[3]);
1533 switch (code)
1534 {
1535 case EQ: op = inverted ? "ne" : "eq"; break;
1536 case NE: op = inverted ? "eq" : "ne"; break;
1537 case LT: op = inverted ? "ge" : "lt"; break;
1538 case GE: op = inverted ? "lt" : "ge"; break;
1539 case LTU: op = inverted ? "geu" : "ltu"; break;
1540 case GEU: op = inverted ? "ltu" : "geu"; break;
1541 default: gcc_unreachable ();
1542 }
1543
1544 if (immed)
1545 {
1546 if (INTVAL (operands[1]) == 0)
1547 sprintf (result, "b%sz%s\t%%0, %%2", op,
1548 (TARGET_DENSITY && (code == EQ || code == NE)) ? ".n" : "");
1549 else
1550 sprintf (result, "b%si\t%%0, %%d1, %%2", op);
1551 }
1552 else
1553 sprintf (result, "b%s\t%%0, %%1, %%2", op);
1554
1555 return result;
1556 }
1557
1558
1559 char *
1560 xtensa_emit_bit_branch (bool inverted, bool immed, rtx *operands)
1561 {
1562 static char result[64];
1563 const char *op;
1564
1565 switch (GET_CODE (operands[3]))
1566 {
1567 case EQ: op = inverted ? "bs" : "bc"; break;
1568 case NE: op = inverted ? "bc" : "bs"; break;
1569 default: gcc_unreachable ();
1570 }
1571
1572 if (immed)
1573 {
1574 unsigned bitnum = INTVAL (operands[1]) & 0x1f;
1575 operands[1] = GEN_INT (bitnum);
1576 sprintf (result, "b%si\t%%0, %%d1, %%2", op);
1577 }
1578 else
1579 sprintf (result, "b%s\t%%0, %%1, %%2", op);
1580
1581 return result;
1582 }
1583
1584
1585 char *
1586 xtensa_emit_movcc (bool inverted, bool isfp, bool isbool, rtx *operands)
1587 {
1588 static char result[64];
1589 enum rtx_code code;
1590 const char *op;
1591
1592 code = GET_CODE (operands[4]);
1593 if (isbool)
1594 {
1595 switch (code)
1596 {
1597 case EQ: op = inverted ? "t" : "f"; break;
1598 case NE: op = inverted ? "f" : "t"; break;
1599 default: gcc_unreachable ();
1600 }
1601 }
1602 else
1603 {
1604 switch (code)
1605 {
1606 case EQ: op = inverted ? "nez" : "eqz"; break;
1607 case NE: op = inverted ? "eqz" : "nez"; break;
1608 case LT: op = inverted ? "gez" : "ltz"; break;
1609 case GE: op = inverted ? "ltz" : "gez"; break;
1610 default: gcc_unreachable ();
1611 }
1612 }
1613
1614 sprintf (result, "mov%s%s\t%%0, %%%d, %%1",
1615 op, isfp ? ".s" : "", inverted ? 3 : 2);
1616 return result;
1617 }
1618
1619
1620 char *
1621 xtensa_emit_call (int callop, rtx *operands)
1622 {
1623 static char result[64];
1624 rtx tgt = operands[callop];
1625
1626 if (GET_CODE (tgt) == CONST_INT)
1627 sprintf (result, "call8\t0x%lx", INTVAL (tgt));
1628 else if (register_operand (tgt, VOIDmode))
1629 sprintf (result, "callx8\t%%%d", callop);
1630 else
1631 sprintf (result, "call8\t%%%d", callop);
1632
1633 return result;
1634 }
1635
1636
1637 bool
1638 xtensa_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
1639 {
1640 /* Allow constant pool addresses. */
1641 if (mode != BLKmode && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
1642 && ! TARGET_CONST16 && constantpool_address_p (addr))
1643 return true;
1644
1645 while (GET_CODE (addr) == SUBREG)
1646 addr = SUBREG_REG (addr);
1647
1648 /* Allow base registers. */
1649 if (GET_CODE (addr) == REG && BASE_REG_P (addr, strict))
1650 return true;
1651
1652 /* Check for "register + offset" addressing. */
1653 if (GET_CODE (addr) == PLUS)
1654 {
1655 rtx xplus0 = XEXP (addr, 0);
1656 rtx xplus1 = XEXP (addr, 1);
1657 enum rtx_code code0;
1658 enum rtx_code code1;
1659
1660 while (GET_CODE (xplus0) == SUBREG)
1661 xplus0 = SUBREG_REG (xplus0);
1662 code0 = GET_CODE (xplus0);
1663
1664 while (GET_CODE (xplus1) == SUBREG)
1665 xplus1 = SUBREG_REG (xplus1);
1666 code1 = GET_CODE (xplus1);
1667
1668 /* Swap operands if necessary so the register is first. */
1669 if (code0 != REG && code1 == REG)
1670 {
1671 xplus0 = XEXP (addr, 1);
1672 xplus1 = XEXP (addr, 0);
1673 code0 = GET_CODE (xplus0);
1674 code1 = GET_CODE (xplus1);
1675 }
1676
1677 if (code0 == REG && BASE_REG_P (xplus0, strict)
1678 && code1 == CONST_INT
1679 && xtensa_mem_offset (INTVAL (xplus1), mode))
1680 return true;
1681 }
1682
1683 return false;
1684 }
1685
1686
1687 rtx
1688 xtensa_legitimize_address (rtx x,
1689 rtx oldx ATTRIBUTE_UNUSED,
1690 enum machine_mode mode)
1691 {
1692 if (GET_CODE (x) == PLUS)
1693 {
1694 rtx plus0 = XEXP (x, 0);
1695 rtx plus1 = XEXP (x, 1);
1696
1697 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
1698 {
1699 plus0 = XEXP (x, 1);
1700 plus1 = XEXP (x, 0);
1701 }
1702
1703 /* Try to split up the offset to use an ADDMI instruction. */
1704 if (GET_CODE (plus0) == REG
1705 && GET_CODE (plus1) == CONST_INT
1706 && !xtensa_mem_offset (INTVAL (plus1), mode)
1707 && !xtensa_simm8 (INTVAL (plus1))
1708 && xtensa_mem_offset (INTVAL (plus1) & 0xff, mode)
1709 && xtensa_simm8x256 (INTVAL (plus1) & ~0xff))
1710 {
1711 rtx temp = gen_reg_rtx (Pmode);
1712 rtx addmi_offset = GEN_INT (INTVAL (plus1) & ~0xff);
1713 emit_insn (gen_rtx_SET (Pmode, temp,
1714 gen_rtx_PLUS (Pmode, plus0, addmi_offset)));
1715 return gen_rtx_PLUS (Pmode, temp, GEN_INT (INTVAL (plus1) & 0xff));
1716 }
1717 }
1718
1719 return NULL_RTX;
1720 }
1721
1722
1723 /* Return the debugger register number to use for 'regno'. */
1724
1725 int
1726 xtensa_dbx_register_number (int regno)
1727 {
1728 int first = -1;
1729
1730 if (GP_REG_P (regno))
1731 {
1732 regno -= GP_REG_FIRST;
1733 first = 0;
1734 }
1735 else if (BR_REG_P (regno))
1736 {
1737 regno -= BR_REG_FIRST;
1738 first = 16;
1739 }
1740 else if (FP_REG_P (regno))
1741 {
1742 regno -= FP_REG_FIRST;
1743 first = 48;
1744 }
1745 else if (ACC_REG_P (regno))
1746 {
1747 first = 0x200; /* Start of Xtensa special registers. */
1748 regno = 16; /* ACCLO is special register 16. */
1749 }
1750
1751 /* When optimizing, we sometimes get asked about pseudo-registers
1752 that don't represent hard registers. Return 0 for these. */
1753 if (first == -1)
1754 return 0;
1755
1756 return first + regno;
1757 }
1758
1759
1760 /* Argument support functions. */
1761
1762 /* Initialize CUMULATIVE_ARGS for a function. */
1763
1764 void
1765 init_cumulative_args (CUMULATIVE_ARGS *cum, int incoming)
1766 {
1767 cum->arg_words = 0;
1768 cum->incoming = incoming;
1769 }
1770
1771
1772 /* Advance the argument to the next argument position. */
1773
1774 void
1775 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type)
1776 {
1777 int words, max;
1778 int *arg_words;
1779
1780 arg_words = &cum->arg_words;
1781 max = MAX_ARGS_IN_REGISTERS;
1782
1783 words = (((mode != BLKmode)
1784 ? (int) GET_MODE_SIZE (mode)
1785 : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1786
1787 if (*arg_words < max
1788 && (targetm.calls.must_pass_in_stack (mode, type)
1789 || *arg_words + words > max))
1790 *arg_words = max;
1791
1792 *arg_words += words;
1793 }
1794
1795
1796 /* Return an RTL expression containing the register for the given mode,
1797 or 0 if the argument is to be passed on the stack. INCOMING_P is nonzero
1798 if this is an incoming argument to the current function. */
1799
1800 rtx
1801 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
1802 int incoming_p)
1803 {
1804 int regbase, words, max;
1805 int *arg_words;
1806 int regno;
1807
1808 arg_words = &cum->arg_words;
1809 regbase = (incoming_p ? GP_ARG_FIRST : GP_OUTGOING_ARG_FIRST);
1810 max = MAX_ARGS_IN_REGISTERS;
1811
1812 words = (((mode != BLKmode)
1813 ? (int) GET_MODE_SIZE (mode)
1814 : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1815
1816 if (type && (TYPE_ALIGN (type) > BITS_PER_WORD))
1817 {
1818 int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_WORD;
1819 *arg_words = (*arg_words + align - 1) & -align;
1820 }
1821
1822 if (*arg_words + words > max)
1823 return (rtx)0;
1824
1825 regno = regbase + *arg_words;
1826
1827 if (cum->incoming && regno <= A7_REG && regno + words > A7_REG)
1828 cfun->machine->need_a7_copy = true;
1829
1830 return gen_rtx_REG (mode, regno);
1831 }
1832
1833
1834 int
1835 function_arg_boundary (enum machine_mode mode, tree type)
1836 {
1837 unsigned int alignment;
1838
1839 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
1840 if (alignment < PARM_BOUNDARY)
1841 alignment = PARM_BOUNDARY;
1842 if (alignment > STACK_BOUNDARY)
1843 alignment = STACK_BOUNDARY;
1844 return alignment;
1845 }
1846
1847
1848 static bool
1849 xtensa_return_in_msb (const_tree valtype)
1850 {
1851 return (TARGET_BIG_ENDIAN
1852 && AGGREGATE_TYPE_P (valtype)
1853 && int_size_in_bytes (valtype) >= UNITS_PER_WORD);
1854 }
1855
1856
1857 void
1858 override_options (void)
1859 {
1860 int regno;
1861 enum machine_mode mode;
1862
1863 if (!TARGET_BOOLEANS && TARGET_HARD_FLOAT)
1864 error ("boolean registers required for the floating-point option");
1865
1866 /* Set up array giving whether a given register can hold a given mode. */
1867 for (mode = VOIDmode;
1868 mode != MAX_MACHINE_MODE;
1869 mode = (enum machine_mode) ((int) mode + 1))
1870 {
1871 int size = GET_MODE_SIZE (mode);
1872 enum mode_class class = GET_MODE_CLASS (mode);
1873
1874 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1875 {
1876 int temp;
1877
1878 if (ACC_REG_P (regno))
1879 temp = (TARGET_MAC16
1880 && (class == MODE_INT) && (size <= UNITS_PER_WORD));
1881 else if (GP_REG_P (regno))
1882 temp = ((regno & 1) == 0 || (size <= UNITS_PER_WORD));
1883 else if (FP_REG_P (regno))
1884 temp = (TARGET_HARD_FLOAT && (mode == SFmode));
1885 else if (BR_REG_P (regno))
1886 temp = (TARGET_BOOLEANS && (mode == CCmode));
1887 else
1888 temp = FALSE;
1889
1890 xtensa_hard_regno_mode_ok[(int) mode][regno] = temp;
1891 }
1892 }
1893
1894 init_machine_status = xtensa_init_machine_status;
1895
1896 /* Check PIC settings. PIC is only supported when using L32R
1897 instructions, and some targets need to always use PIC. */
1898 if (flag_pic && TARGET_CONST16)
1899 error ("-f%s is not supported with CONST16 instructions",
1900 (flag_pic > 1 ? "PIC" : "pic"));
1901 else if (XTENSA_ALWAYS_PIC)
1902 {
1903 if (TARGET_CONST16)
1904 error ("PIC is required but not supported with CONST16 instructions");
1905 flag_pic = 1;
1906 }
1907 /* There's no need for -fPIC (as opposed to -fpic) on Xtensa. */
1908 if (flag_pic > 1)
1909 flag_pic = 1;
1910
1911 /* Hot/cold partitioning does not work on this architecture, because of
1912 constant pools (the load instruction cannot necessarily reach that far).
1913 Therefore disable it on this architecture. */
1914 if (flag_reorder_blocks_and_partition)
1915 {
1916 flag_reorder_blocks_and_partition = 0;
1917 flag_reorder_blocks = 1;
1918 }
1919 }
1920
1921
1922 /* A C compound statement to output to stdio stream STREAM the
1923 assembler syntax for an instruction operand X. X is an RTL
1924 expression.
1925
1926 CODE is a value that can be used to specify one of several ways
1927 of printing the operand. It is used when identical operands
1928 must be printed differently depending on the context. CODE
1929 comes from the '%' specification that was used to request
1930 printing of the operand. If the specification was just '%DIGIT'
1931 then CODE is 0; if the specification was '%LTR DIGIT' then CODE
1932 is the ASCII code for LTR.
1933
1934 If X is a register, this macro should print the register's name.
1935 The names can be found in an array 'reg_names' whose type is
1936 'char *[]'. 'reg_names' is initialized from 'REGISTER_NAMES'.
1937
1938 When the machine description has a specification '%PUNCT' (a '%'
1939 followed by a punctuation character), this macro is called with
1940 a null pointer for X and the punctuation character for CODE.
1941
1942 'a', 'c', 'l', and 'n' are reserved.
1943
1944 The Xtensa specific codes are:
1945
1946 'd' CONST_INT, print as signed decimal
1947 'x' CONST_INT, print as signed hexadecimal
1948 'K' CONST_INT, print number of bits in mask for EXTUI
1949 'R' CONST_INT, print (X & 0x1f)
1950 'L' CONST_INT, print ((32 - X) & 0x1f)
1951 'D' REG, print second register of double-word register operand
1952 'N' MEM, print address of next word following a memory operand
1953 'v' MEM, if memory reference is volatile, output a MEMW before it
1954 't' any constant, add "@h" suffix for top 16 bits
1955 'b' any constant, add "@l" suffix for bottom 16 bits
1956 */
1957
1958 static void
1959 printx (FILE *file, signed int val)
1960 {
1961 /* Print a hexadecimal value in a nice way. */
1962 if ((val > -0xa) && (val < 0xa))
1963 fprintf (file, "%d", val);
1964 else if (val < 0)
1965 fprintf (file, "-0x%x", -val);
1966 else
1967 fprintf (file, "0x%x", val);
1968 }
1969
1970
1971 void
1972 print_operand (FILE *file, rtx x, int letter)
1973 {
1974 if (!x)
1975 error ("PRINT_OPERAND null pointer");
1976
1977 switch (letter)
1978 {
1979 case 'D':
1980 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
1981 fprintf (file, "%s", reg_names[xt_true_regnum (x) + 1]);
1982 else
1983 output_operand_lossage ("invalid %%D value");
1984 break;
1985
1986 case 'v':
1987 if (GET_CODE (x) == MEM)
1988 {
1989 /* For a volatile memory reference, emit a MEMW before the
1990 load or store. */
1991 if (MEM_VOLATILE_P (x))
1992 fprintf (file, "memw\n\t");
1993 }
1994 else
1995 output_operand_lossage ("invalid %%v value");
1996 break;
1997
1998 case 'N':
1999 if (GET_CODE (x) == MEM
2000 && (GET_MODE (x) == DFmode || GET_MODE (x) == DImode))
2001 {
2002 x = adjust_address (x, GET_MODE (x) == DFmode ? SFmode : SImode, 4);
2003 output_address (XEXP (x, 0));
2004 }
2005 else
2006 output_operand_lossage ("invalid %%N value");
2007 break;
2008
2009 case 'K':
2010 if (GET_CODE (x) == CONST_INT)
2011 {
2012 int num_bits = 0;
2013 unsigned val = INTVAL (x);
2014 while (val & 1)
2015 {
2016 num_bits += 1;
2017 val = val >> 1;
2018 }
2019 if ((val != 0) || (num_bits == 0) || (num_bits > 16))
2020 fatal_insn ("invalid mask", x);
2021
2022 fprintf (file, "%d", num_bits);
2023 }
2024 else
2025 output_operand_lossage ("invalid %%K value");
2026 break;
2027
2028 case 'L':
2029 if (GET_CODE (x) == CONST_INT)
2030 fprintf (file, "%ld", (32 - INTVAL (x)) & 0x1f);
2031 else
2032 output_operand_lossage ("invalid %%L value");
2033 break;
2034
2035 case 'R':
2036 if (GET_CODE (x) == CONST_INT)
2037 fprintf (file, "%ld", INTVAL (x) & 0x1f);
2038 else
2039 output_operand_lossage ("invalid %%R value");
2040 break;
2041
2042 case 'x':
2043 if (GET_CODE (x) == CONST_INT)
2044 printx (file, INTVAL (x));
2045 else
2046 output_operand_lossage ("invalid %%x value");
2047 break;
2048
2049 case 'd':
2050 if (GET_CODE (x) == CONST_INT)
2051 fprintf (file, "%ld", INTVAL (x));
2052 else
2053 output_operand_lossage ("invalid %%d value");
2054 break;
2055
2056 case 't':
2057 case 'b':
2058 if (GET_CODE (x) == CONST_INT)
2059 {
2060 printx (file, INTVAL (x));
2061 fputs (letter == 't' ? "@h" : "@l", file);
2062 }
2063 else if (GET_CODE (x) == CONST_DOUBLE)
2064 {
2065 REAL_VALUE_TYPE r;
2066 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2067 if (GET_MODE (x) == SFmode)
2068 {
2069 long l;
2070 REAL_VALUE_TO_TARGET_SINGLE (r, l);
2071 fprintf (file, "0x%08lx@%c", l, letter == 't' ? 'h' : 'l');
2072 }
2073 else
2074 output_operand_lossage ("invalid %%t/%%b value");
2075 }
2076 else if (GET_CODE (x) == CONST)
2077 {
2078 /* X must be a symbolic constant on ELF. Write an expression
2079 suitable for 'const16' that sets the high or low 16 bits. */
2080 if (GET_CODE (XEXP (x, 0)) != PLUS
2081 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
2082 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
2083 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
2084 output_operand_lossage ("invalid %%t/%%b value");
2085 print_operand (file, XEXP (XEXP (x, 0), 0), 0);
2086 fputs (letter == 't' ? "@h" : "@l", file);
2087 /* There must be a non-alphanumeric character between 'h' or 'l'
2088 and the number. The '-' is added by print_operand() already. */
2089 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
2090 fputs ("+", file);
2091 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
2092 }
2093 else
2094 {
2095 output_addr_const (file, x);
2096 fputs (letter == 't' ? "@h" : "@l", file);
2097 }
2098 break;
2099
2100 default:
2101 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2102 fprintf (file, "%s", reg_names[xt_true_regnum (x)]);
2103 else if (GET_CODE (x) == MEM)
2104 output_address (XEXP (x, 0));
2105 else if (GET_CODE (x) == CONST_INT)
2106 fprintf (file, "%ld", INTVAL (x));
2107 else
2108 output_addr_const (file, x);
2109 }
2110 }
2111
2112
2113 /* A C compound statement to output to stdio stream STREAM the
2114 assembler syntax for an instruction operand that is a memory
2115 reference whose address is ADDR. ADDR is an RTL expression. */
2116
2117 void
2118 print_operand_address (FILE *file, rtx addr)
2119 {
2120 if (!addr)
2121 error ("PRINT_OPERAND_ADDRESS, null pointer");
2122
2123 switch (GET_CODE (addr))
2124 {
2125 default:
2126 fatal_insn ("invalid address", addr);
2127 break;
2128
2129 case REG:
2130 fprintf (file, "%s, 0", reg_names [REGNO (addr)]);
2131 break;
2132
2133 case PLUS:
2134 {
2135 rtx reg = (rtx)0;
2136 rtx offset = (rtx)0;
2137 rtx arg0 = XEXP (addr, 0);
2138 rtx arg1 = XEXP (addr, 1);
2139
2140 if (GET_CODE (arg0) == REG)
2141 {
2142 reg = arg0;
2143 offset = arg1;
2144 }
2145 else if (GET_CODE (arg1) == REG)
2146 {
2147 reg = arg1;
2148 offset = arg0;
2149 }
2150 else
2151 fatal_insn ("no register in address", addr);
2152
2153 if (CONSTANT_P (offset))
2154 {
2155 fprintf (file, "%s, ", reg_names [REGNO (reg)]);
2156 output_addr_const (file, offset);
2157 }
2158 else
2159 fatal_insn ("address offset not a constant", addr);
2160 }
2161 break;
2162
2163 case LABEL_REF:
2164 case SYMBOL_REF:
2165 case CONST_INT:
2166 case CONST:
2167 output_addr_const (file, addr);
2168 break;
2169 }
2170 }
2171
2172
2173 bool
2174 xtensa_output_addr_const_extra (FILE *fp, rtx x)
2175 {
2176 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
2177 {
2178 switch (XINT (x, 1))
2179 {
2180 case UNSPEC_PLT:
2181 if (flag_pic)
2182 {
2183 output_addr_const (fp, XVECEXP (x, 0, 0));
2184 fputs ("@PLT", fp);
2185 return true;
2186 }
2187 break;
2188 default:
2189 break;
2190 }
2191 }
2192 return false;
2193 }
2194
2195
2196 void
2197 xtensa_output_literal (FILE *file, rtx x, enum machine_mode mode, int labelno)
2198 {
2199 long value_long[2];
2200 REAL_VALUE_TYPE r;
2201 int size;
2202 rtx first, second;
2203
2204 fprintf (file, "\t.literal .LC%u, ", (unsigned) labelno);
2205
2206 switch (GET_MODE_CLASS (mode))
2207 {
2208 case MODE_FLOAT:
2209 gcc_assert (GET_CODE (x) == CONST_DOUBLE);
2210
2211 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2212 switch (mode)
2213 {
2214 case SFmode:
2215 REAL_VALUE_TO_TARGET_SINGLE (r, value_long[0]);
2216 if (HOST_BITS_PER_LONG > 32)
2217 value_long[0] &= 0xffffffff;
2218 fprintf (file, "0x%08lx\n", value_long[0]);
2219 break;
2220
2221 case DFmode:
2222 REAL_VALUE_TO_TARGET_DOUBLE (r, value_long);
2223 if (HOST_BITS_PER_LONG > 32)
2224 {
2225 value_long[0] &= 0xffffffff;
2226 value_long[1] &= 0xffffffff;
2227 }
2228 fprintf (file, "0x%08lx, 0x%08lx\n",
2229 value_long[0], value_long[1]);
2230 break;
2231
2232 default:
2233 gcc_unreachable ();
2234 }
2235
2236 break;
2237
2238 case MODE_INT:
2239 case MODE_PARTIAL_INT:
2240 size = GET_MODE_SIZE (mode);
2241 switch (size)
2242 {
2243 case 4:
2244 output_addr_const (file, x);
2245 fputs ("\n", file);
2246 break;
2247
2248 case 8:
2249 split_double (x, &first, &second);
2250 output_addr_const (file, first);
2251 fputs (", ", file);
2252 output_addr_const (file, second);
2253 fputs ("\n", file);
2254 break;
2255
2256 default:
2257 gcc_unreachable ();
2258 }
2259 break;
2260
2261 default:
2262 gcc_unreachable ();
2263 }
2264 }
2265
2266
2267 /* Return the bytes needed to compute the frame pointer from the current
2268 stack pointer. */
2269
2270 #define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT)
2271 #define XTENSA_STACK_ALIGN(LOC) (((LOC) + STACK_BYTES-1) & ~(STACK_BYTES-1))
2272
2273 long
2274 compute_frame_size (int size)
2275 {
2276 /* Add space for the incoming static chain value. */
2277 if (cfun->static_chain_decl != NULL)
2278 size += (1 * UNITS_PER_WORD);
2279
2280 xtensa_current_frame_size =
2281 XTENSA_STACK_ALIGN (size
2282 + current_function_outgoing_args_size
2283 + (WINDOW_SIZE * UNITS_PER_WORD));
2284 return xtensa_current_frame_size;
2285 }
2286
2287
2288 int
2289 xtensa_frame_pointer_required (void)
2290 {
2291 /* The code to expand builtin_frame_addr and builtin_return_addr
2292 currently uses the hard_frame_pointer instead of frame_pointer.
2293 This seems wrong but maybe it's necessary for other architectures.
2294 This function is derived from the i386 code. */
2295
2296 if (cfun->machine->accesses_prev_frame)
2297 return 1;
2298
2299 return 0;
2300 }
2301
2302
2303 void
2304 xtensa_expand_prologue (void)
2305 {
2306 HOST_WIDE_INT total_size;
2307 rtx size_rtx;
2308
2309 total_size = compute_frame_size (get_frame_size ());
2310 size_rtx = GEN_INT (total_size);
2311
2312 if (total_size < (1 << (12+3)))
2313 emit_insn (gen_entry (size_rtx, size_rtx));
2314 else
2315 {
2316 /* Use a8 as a temporary since a0-a7 may be live. */
2317 rtx tmp_reg = gen_rtx_REG (Pmode, A8_REG);
2318 emit_insn (gen_entry (size_rtx, GEN_INT (MIN_FRAME_SIZE)));
2319 emit_move_insn (tmp_reg, GEN_INT (total_size - MIN_FRAME_SIZE));
2320 emit_insn (gen_subsi3 (tmp_reg, stack_pointer_rtx, tmp_reg));
2321 emit_move_insn (stack_pointer_rtx, tmp_reg);
2322 }
2323
2324 if (frame_pointer_needed)
2325 {
2326 if (cfun->machine->set_frame_ptr_insn)
2327 {
2328 rtx first, insn;
2329
2330 push_topmost_sequence ();
2331 first = get_insns ();
2332 pop_topmost_sequence ();
2333
2334 /* For all instructions prior to set_frame_ptr_insn, replace
2335 hard_frame_pointer references with stack_pointer. */
2336 for (insn = first;
2337 insn != cfun->machine->set_frame_ptr_insn;
2338 insn = NEXT_INSN (insn))
2339 {
2340 if (INSN_P (insn))
2341 {
2342 PATTERN (insn) = replace_rtx (copy_rtx (PATTERN (insn)),
2343 hard_frame_pointer_rtx,
2344 stack_pointer_rtx);
2345 df_insn_rescan (insn);
2346 }
2347 }
2348 }
2349 else
2350 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
2351 }
2352 }
2353
2354
2355 /* Clear variables at function end. */
2356
2357 void
2358 xtensa_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
2359 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
2360 {
2361 xtensa_current_frame_size = 0;
2362 }
2363
2364
2365 rtx
2366 xtensa_return_addr (int count, rtx frame)
2367 {
2368 rtx result, retaddr;
2369
2370 if (count == -1)
2371 retaddr = gen_rtx_REG (Pmode, A0_REG);
2372 else
2373 {
2374 rtx addr = plus_constant (frame, -4 * UNITS_PER_WORD);
2375 addr = memory_address (Pmode, addr);
2376 retaddr = gen_reg_rtx (Pmode);
2377 emit_move_insn (retaddr, gen_rtx_MEM (Pmode, addr));
2378 }
2379
2380 /* The 2 most-significant bits of the return address on Xtensa hold
2381 the register window size. To get the real return address, these
2382 bits must be replaced with the high bits from the current PC. */
2383
2384 result = gen_reg_rtx (Pmode);
2385 emit_insn (gen_fix_return_addr (result, retaddr));
2386 return result;
2387 }
2388
2389
2390 /* Create the va_list data type.
2391
2392 This structure is set up by __builtin_saveregs. The __va_reg field
2393 points to a stack-allocated region holding the contents of the
2394 incoming argument registers. The __va_ndx field is an index
2395 initialized to the position of the first unnamed (variable)
2396 argument. This same index is also used to address the arguments
2397 passed in memory. Thus, the __va_stk field is initialized to point
2398 to the position of the first argument in memory offset to account
2399 for the arguments passed in registers and to account for the size
2400 of the argument registers not being 16-byte aligned. E.G., there
2401 are 6 argument registers of 4 bytes each, but we want the __va_ndx
2402 for the first stack argument to have the maximal alignment of 16
2403 bytes, so we offset the __va_stk address by 32 bytes so that
2404 __va_stk[32] references the first argument on the stack. */
2405
2406 static tree
2407 xtensa_build_builtin_va_list (void)
2408 {
2409 tree f_stk, f_reg, f_ndx, record, type_decl;
2410
2411 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
2412 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
2413
2414 f_stk = build_decl (FIELD_DECL, get_identifier ("__va_stk"),
2415 ptr_type_node);
2416 f_reg = build_decl (FIELD_DECL, get_identifier ("__va_reg"),
2417 ptr_type_node);
2418 f_ndx = build_decl (FIELD_DECL, get_identifier ("__va_ndx"),
2419 integer_type_node);
2420
2421 DECL_FIELD_CONTEXT (f_stk) = record;
2422 DECL_FIELD_CONTEXT (f_reg) = record;
2423 DECL_FIELD_CONTEXT (f_ndx) = record;
2424
2425 TREE_CHAIN (record) = type_decl;
2426 TYPE_NAME (record) = type_decl;
2427 TYPE_FIELDS (record) = f_stk;
2428 TREE_CHAIN (f_stk) = f_reg;
2429 TREE_CHAIN (f_reg) = f_ndx;
2430
2431 layout_type (record);
2432 return record;
2433 }
2434
2435
2436 /* Save the incoming argument registers on the stack. Returns the
2437 address of the saved registers. */
2438
2439 static rtx
2440 xtensa_builtin_saveregs (void)
2441 {
2442 rtx gp_regs;
2443 int arg_words = current_function_args_info.arg_words;
2444 int gp_left = MAX_ARGS_IN_REGISTERS - arg_words;
2445
2446 if (gp_left <= 0)
2447 return const0_rtx;
2448
2449 /* Allocate the general-purpose register space. */
2450 gp_regs = assign_stack_local
2451 (BLKmode, MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD, -1);
2452 set_mem_alias_set (gp_regs, get_varargs_alias_set ());
2453
2454 /* Now store the incoming registers. */
2455 cfun->machine->need_a7_copy = true;
2456 cfun->machine->vararg_a7 = true;
2457 move_block_from_reg (GP_ARG_FIRST + arg_words,
2458 adjust_address (gp_regs, BLKmode,
2459 arg_words * UNITS_PER_WORD),
2460 gp_left);
2461 gcc_assert (cfun->machine->vararg_a7_copy != 0);
2462 emit_insn_before (cfun->machine->vararg_a7_copy, get_insns ());
2463
2464 return XEXP (gp_regs, 0);
2465 }
2466
2467
2468 /* Implement `va_start' for varargs and stdarg. We look at the
2469 current function to fill in an initial va_list. */
2470
2471 void
2472 xtensa_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
2473 {
2474 tree f_stk, stk;
2475 tree f_reg, reg;
2476 tree f_ndx, ndx;
2477 tree t, u;
2478 int arg_words;
2479
2480 arg_words = current_function_args_info.arg_words;
2481
2482 f_stk = TYPE_FIELDS (va_list_type_node);
2483 f_reg = TREE_CHAIN (f_stk);
2484 f_ndx = TREE_CHAIN (f_reg);
2485
2486 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist, f_stk, NULL_TREE);
2487 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), valist, f_reg, NULL_TREE);
2488 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), valist, f_ndx, NULL_TREE);
2489
2490 /* Call __builtin_saveregs; save the result in __va_reg */
2491 u = make_tree (sizetype, expand_builtin_saveregs ());
2492 u = fold_convert (ptr_type_node, u);
2493 t = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, reg, u);
2494 TREE_SIDE_EFFECTS (t) = 1;
2495 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2496
2497 /* Set the __va_stk member to ($arg_ptr - 32). */
2498 u = make_tree (ptr_type_node, virtual_incoming_args_rtx);
2499 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u, size_int (-32));
2500 t = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, stk, u);
2501 TREE_SIDE_EFFECTS (t) = 1;
2502 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2503
2504 /* Set the __va_ndx member. If the first variable argument is on
2505 the stack, adjust __va_ndx by 2 words to account for the extra
2506 alignment offset for __va_stk. */
2507 if (arg_words >= MAX_ARGS_IN_REGISTERS)
2508 arg_words += 2;
2509 t = build2 (GIMPLE_MODIFY_STMT, integer_type_node, ndx,
2510 size_int (arg_words * UNITS_PER_WORD));
2511 TREE_SIDE_EFFECTS (t) = 1;
2512 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2513 }
2514
2515
2516 /* Implement `va_arg'. */
2517
2518 static tree
2519 xtensa_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p,
2520 tree *post_p ATTRIBUTE_UNUSED)
2521 {
2522 tree f_stk, stk;
2523 tree f_reg, reg;
2524 tree f_ndx, ndx;
2525 tree type_size, array, orig_ndx, addr, size, va_size, t;
2526 tree lab_false, lab_over, lab_false2;
2527 bool indirect;
2528
2529 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
2530 if (indirect)
2531 type = build_pointer_type (type);
2532
2533 /* Handle complex values as separate real and imaginary parts. */
2534 if (TREE_CODE (type) == COMPLEX_TYPE)
2535 {
2536 tree real_part, imag_part;
2537
2538 real_part = xtensa_gimplify_va_arg_expr (valist, TREE_TYPE (type),
2539 pre_p, NULL);
2540 real_part = get_initialized_tmp_var (real_part, pre_p, NULL);
2541
2542 imag_part = xtensa_gimplify_va_arg_expr (valist, TREE_TYPE (type),
2543 pre_p, NULL);
2544 imag_part = get_initialized_tmp_var (imag_part, pre_p, NULL);
2545
2546 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
2547 }
2548
2549 f_stk = TYPE_FIELDS (va_list_type_node);
2550 f_reg = TREE_CHAIN (f_stk);
2551 f_ndx = TREE_CHAIN (f_reg);
2552
2553 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist, f_stk, NULL_TREE);
2554 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), valist, f_reg, NULL_TREE);
2555 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), valist, f_ndx, NULL_TREE);
2556
2557 type_size = size_in_bytes (type);
2558 va_size = round_up (type_size, UNITS_PER_WORD);
2559 gimplify_expr (&va_size, pre_p, NULL, is_gimple_val, fb_rvalue);
2560
2561
2562 /* First align __va_ndx if necessary for this arg:
2563
2564 orig_ndx = (AP).__va_ndx;
2565 if (__alignof__ (TYPE) > 4 )
2566 orig_ndx = ((orig_ndx + __alignof__ (TYPE) - 1)
2567 & -__alignof__ (TYPE)); */
2568
2569 orig_ndx = get_initialized_tmp_var (ndx, pre_p, NULL);
2570
2571 if (TYPE_ALIGN (type) > BITS_PER_WORD)
2572 {
2573 int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_UNIT;
2574
2575 t = build2 (PLUS_EXPR, integer_type_node, orig_ndx, size_int (align - 1));
2576 t = build2 (BIT_AND_EXPR, integer_type_node, t, size_int (-align));
2577 t = build2 (GIMPLE_MODIFY_STMT, integer_type_node, orig_ndx, t);
2578 gimplify_and_add (t, pre_p);
2579 }
2580
2581
2582 /* Increment __va_ndx to point past the argument:
2583
2584 (AP).__va_ndx = orig_ndx + __va_size (TYPE); */
2585
2586 t = fold_convert (integer_type_node, va_size);
2587 t = build2 (PLUS_EXPR, integer_type_node, orig_ndx, t);
2588 t = build2 (GIMPLE_MODIFY_STMT, integer_type_node, ndx, t);
2589 gimplify_and_add (t, pre_p);
2590
2591
2592 /* Check if the argument is in registers:
2593
2594 if ((AP).__va_ndx <= __MAX_ARGS_IN_REGISTERS * 4
2595 && !must_pass_in_stack (type))
2596 __array = (AP).__va_reg; */
2597
2598 array = create_tmp_var (ptr_type_node, NULL);
2599
2600 lab_over = NULL;
2601 if (!targetm.calls.must_pass_in_stack (TYPE_MODE (type), type))
2602 {
2603 lab_false = create_artificial_label ();
2604 lab_over = create_artificial_label ();
2605
2606 t = build2 (GT_EXPR, boolean_type_node, ndx,
2607 size_int (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD));
2608 t = build3 (COND_EXPR, void_type_node, t,
2609 build1 (GOTO_EXPR, void_type_node, lab_false),
2610 NULL_TREE);
2611 gimplify_and_add (t, pre_p);
2612
2613 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, array, reg);
2614 gimplify_and_add (t, pre_p);
2615
2616 t = build1 (GOTO_EXPR, void_type_node, lab_over);
2617 gimplify_and_add (t, pre_p);
2618
2619 t = build1 (LABEL_EXPR, void_type_node, lab_false);
2620 gimplify_and_add (t, pre_p);
2621 }
2622
2623
2624 /* ...otherwise, the argument is on the stack (never split between
2625 registers and the stack -- change __va_ndx if necessary):
2626
2627 else
2628 {
2629 if (orig_ndx <= __MAX_ARGS_IN_REGISTERS * 4)
2630 (AP).__va_ndx = 32 + __va_size (TYPE);
2631 __array = (AP).__va_stk;
2632 } */
2633
2634 lab_false2 = create_artificial_label ();
2635
2636 t = build2 (GT_EXPR, boolean_type_node, orig_ndx,
2637 size_int (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD));
2638 t = build3 (COND_EXPR, void_type_node, t,
2639 build1 (GOTO_EXPR, void_type_node, lab_false2),
2640 NULL_TREE);
2641 gimplify_and_add (t, pre_p);
2642
2643 t = size_binop (PLUS_EXPR, va_size, size_int (32));
2644 t = fold_convert (integer_type_node, t);
2645 t = build2 (GIMPLE_MODIFY_STMT, integer_type_node, ndx, t);
2646 gimplify_and_add (t, pre_p);
2647
2648 t = build1 (LABEL_EXPR, void_type_node, lab_false2);
2649 gimplify_and_add (t, pre_p);
2650
2651 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, array, stk);
2652 gimplify_and_add (t, pre_p);
2653
2654 if (lab_over)
2655 {
2656 t = build1 (LABEL_EXPR, void_type_node, lab_over);
2657 gimplify_and_add (t, pre_p);
2658 }
2659
2660
2661 /* Given the base array pointer (__array) and index to the subsequent
2662 argument (__va_ndx), find the address:
2663
2664 __array + (AP).__va_ndx - (BYTES_BIG_ENDIAN && sizeof (TYPE) < 4
2665 ? sizeof (TYPE)
2666 : __va_size (TYPE))
2667
2668 The results are endian-dependent because values smaller than one word
2669 are aligned differently. */
2670
2671
2672 if (BYTES_BIG_ENDIAN && TREE_CODE (type_size) == INTEGER_CST)
2673 {
2674 t = fold_build2 (GE_EXPR, boolean_type_node, type_size,
2675 size_int (PARM_BOUNDARY / BITS_PER_UNIT));
2676 t = fold_build3 (COND_EXPR, sizetype, t, va_size, type_size);
2677 size = t;
2678 }
2679 else
2680 size = va_size;
2681
2682 t = build2 (MINUS_EXPR, sizetype, ndx, size);
2683 addr = build2 (POINTER_PLUS_EXPR, ptr_type_node, array, t);
2684
2685 addr = fold_convert (build_pointer_type (type), addr);
2686 if (indirect)
2687 addr = build_va_arg_indirect_ref (addr);
2688 return build_va_arg_indirect_ref (addr);
2689 }
2690
2691
2692 /* Builtins. */
2693
2694 enum xtensa_builtin
2695 {
2696 XTENSA_BUILTIN_UMULSIDI3,
2697 XTENSA_BUILTIN_max
2698 };
2699
2700
2701 static void
2702 xtensa_init_builtins (void)
2703 {
2704 tree ftype;
2705
2706 ftype = build_function_type_list (unsigned_intDI_type_node,
2707 unsigned_intSI_type_node,
2708 unsigned_intSI_type_node, NULL_TREE);
2709
2710 add_builtin_function ("__builtin_umulsidi3", ftype,
2711 XTENSA_BUILTIN_UMULSIDI3, BUILT_IN_MD,
2712 "__umulsidi3", NULL_TREE);
2713 }
2714
2715
2716 static tree
2717 xtensa_fold_builtin (tree fndecl, tree arglist, bool ignore ATTRIBUTE_UNUSED)
2718 {
2719 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
2720 tree arg0, arg1;
2721
2722 if (fcode == XTENSA_BUILTIN_UMULSIDI3)
2723 {
2724 arg0 = TREE_VALUE (arglist);
2725 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
2726 if ((TREE_CODE (arg0) == INTEGER_CST && TREE_CODE (arg1) == INTEGER_CST)
2727 || TARGET_MUL32_HIGH)
2728 return fold_build2 (MULT_EXPR, unsigned_intDI_type_node,
2729 fold_convert (unsigned_intDI_type_node, arg0),
2730 fold_convert (unsigned_intDI_type_node, arg1));
2731 else
2732 return NULL;
2733 }
2734
2735 internal_error ("bad builtin code");
2736 return NULL;
2737 }
2738
2739
2740 static rtx
2741 xtensa_expand_builtin (tree exp, rtx target,
2742 rtx subtarget ATTRIBUTE_UNUSED,
2743 enum machine_mode mode ATTRIBUTE_UNUSED,
2744 int ignore)
2745 {
2746 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
2747 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
2748
2749 /* The umulsidi3 builtin is just a mechanism to avoid calling the real
2750 __umulsidi3 function when the Xtensa configuration can directly
2751 implement it. If not, just call the function. */
2752 if (fcode == XTENSA_BUILTIN_UMULSIDI3)
2753 return expand_call (exp, target, ignore);
2754
2755 internal_error ("bad builtin code");
2756 return NULL_RTX;
2757 }
2758
2759
2760 enum reg_class
2761 xtensa_preferred_reload_class (rtx x, enum reg_class class, int isoutput)
2762 {
2763 if (!isoutput && CONSTANT_P (x) && GET_CODE (x) == CONST_DOUBLE)
2764 return NO_REGS;
2765
2766 /* Don't use the stack pointer or hard frame pointer for reloads!
2767 The hard frame pointer would normally be OK except that it may
2768 briefly hold an incoming argument in the prologue, and reload
2769 won't know that it is live because the hard frame pointer is
2770 treated specially. */
2771
2772 if (class == AR_REGS || class == GR_REGS)
2773 return RL_REGS;
2774
2775 return class;
2776 }
2777
2778
2779 enum reg_class
2780 xtensa_secondary_reload_class (enum reg_class class,
2781 enum machine_mode mode ATTRIBUTE_UNUSED,
2782 rtx x, int isoutput)
2783 {
2784 int regno;
2785
2786 if (GET_CODE (x) == SIGN_EXTEND)
2787 x = XEXP (x, 0);
2788 regno = xt_true_regnum (x);
2789
2790 if (!isoutput)
2791 {
2792 if (class == FP_REGS && constantpool_mem_p (x))
2793 return RL_REGS;
2794 }
2795
2796 if (ACC_REG_P (regno))
2797 return ((class == GR_REGS || class == RL_REGS) ? NO_REGS : RL_REGS);
2798 if (class == ACC_REG)
2799 return (GP_REG_P (regno) ? NO_REGS : RL_REGS);
2800
2801 return NO_REGS;
2802 }
2803
2804
2805 void
2806 order_regs_for_local_alloc (void)
2807 {
2808 if (!leaf_function_p ())
2809 {
2810 memcpy (reg_alloc_order, reg_nonleaf_alloc_order,
2811 FIRST_PSEUDO_REGISTER * sizeof (int));
2812 }
2813 else
2814 {
2815 int i, num_arg_regs;
2816 int nxt = 0;
2817
2818 /* Use the AR registers in increasing order (skipping a0 and a1)
2819 but save the incoming argument registers for a last resort. */
2820 num_arg_regs = current_function_args_info.arg_words;
2821 if (num_arg_regs > MAX_ARGS_IN_REGISTERS)
2822 num_arg_regs = MAX_ARGS_IN_REGISTERS;
2823 for (i = GP_ARG_FIRST; i < 16 - num_arg_regs; i++)
2824 reg_alloc_order[nxt++] = i + num_arg_regs;
2825 for (i = 0; i < num_arg_regs; i++)
2826 reg_alloc_order[nxt++] = GP_ARG_FIRST + i;
2827
2828 /* List the coprocessor registers in order. */
2829 for (i = 0; i < BR_REG_NUM; i++)
2830 reg_alloc_order[nxt++] = BR_REG_FIRST + i;
2831
2832 /* List the FP registers in order for now. */
2833 for (i = 0; i < 16; i++)
2834 reg_alloc_order[nxt++] = FP_REG_FIRST + i;
2835
2836 /* GCC requires that we list *all* the registers.... */
2837 reg_alloc_order[nxt++] = 0; /* a0 = return address */
2838 reg_alloc_order[nxt++] = 1; /* a1 = stack pointer */
2839 reg_alloc_order[nxt++] = 16; /* pseudo frame pointer */
2840 reg_alloc_order[nxt++] = 17; /* pseudo arg pointer */
2841
2842 reg_alloc_order[nxt++] = ACC_REG_FIRST; /* MAC16 accumulator */
2843 }
2844 }
2845
2846
2847 /* Some Xtensa targets support multiple bss sections. If the section
2848 name ends with ".bss", add SECTION_BSS to the flags. */
2849
2850 static unsigned int
2851 xtensa_multibss_section_type_flags (tree decl, const char *name, int reloc)
2852 {
2853 unsigned int flags = default_section_type_flags (decl, name, reloc);
2854 const char *suffix;
2855
2856 suffix = strrchr (name, '.');
2857 if (suffix && strcmp (suffix, ".bss") == 0)
2858 {
2859 if (!decl || (TREE_CODE (decl) == VAR_DECL
2860 && DECL_INITIAL (decl) == NULL_TREE))
2861 flags |= SECTION_BSS; /* @nobits */
2862 else
2863 warning (0, "only uninitialized variables can be placed in a "
2864 ".bss section");
2865 }
2866
2867 return flags;
2868 }
2869
2870
2871 /* The literal pool stays with the function. */
2872
2873 static section *
2874 xtensa_select_rtx_section (enum machine_mode mode ATTRIBUTE_UNUSED,
2875 rtx x ATTRIBUTE_UNUSED,
2876 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
2877 {
2878 return function_section (current_function_decl);
2879 }
2880
2881
2882 /* Compute a (partial) cost for rtx X. Return true if the complete
2883 cost has been computed, and false if subexpressions should be
2884 scanned. In either case, *TOTAL contains the cost result. */
2885
2886 static bool
2887 xtensa_rtx_costs (rtx x, int code, int outer_code, int *total)
2888 {
2889 switch (code)
2890 {
2891 case CONST_INT:
2892 switch (outer_code)
2893 {
2894 case SET:
2895 if (xtensa_simm12b (INTVAL (x)))
2896 {
2897 *total = 4;
2898 return true;
2899 }
2900 break;
2901 case PLUS:
2902 if (xtensa_simm8 (INTVAL (x))
2903 || xtensa_simm8x256 (INTVAL (x)))
2904 {
2905 *total = 0;
2906 return true;
2907 }
2908 break;
2909 case AND:
2910 if (xtensa_mask_immediate (INTVAL (x)))
2911 {
2912 *total = 0;
2913 return true;
2914 }
2915 break;
2916 case COMPARE:
2917 if ((INTVAL (x) == 0) || xtensa_b4const (INTVAL (x)))
2918 {
2919 *total = 0;
2920 return true;
2921 }
2922 break;
2923 case ASHIFT:
2924 case ASHIFTRT:
2925 case LSHIFTRT:
2926 case ROTATE:
2927 case ROTATERT:
2928 /* No way to tell if X is the 2nd operand so be conservative. */
2929 default: break;
2930 }
2931 if (xtensa_simm12b (INTVAL (x)))
2932 *total = 5;
2933 else if (TARGET_CONST16)
2934 *total = COSTS_N_INSNS (2);
2935 else
2936 *total = 6;
2937 return true;
2938
2939 case CONST:
2940 case LABEL_REF:
2941 case SYMBOL_REF:
2942 if (TARGET_CONST16)
2943 *total = COSTS_N_INSNS (2);
2944 else
2945 *total = 5;
2946 return true;
2947
2948 case CONST_DOUBLE:
2949 if (TARGET_CONST16)
2950 *total = COSTS_N_INSNS (4);
2951 else
2952 *total = 7;
2953 return true;
2954
2955 case MEM:
2956 {
2957 int num_words =
2958 (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) ? 2 : 1;
2959
2960 if (memory_address_p (GET_MODE (x), XEXP ((x), 0)))
2961 *total = COSTS_N_INSNS (num_words);
2962 else
2963 *total = COSTS_N_INSNS (2*num_words);
2964 return true;
2965 }
2966
2967 case FFS:
2968 case CTZ:
2969 *total = COSTS_N_INSNS (TARGET_NSA ? 5 : 50);
2970 return true;
2971
2972 case CLZ:
2973 *total = COSTS_N_INSNS (TARGET_NSA ? 1 : 50);
2974 return true;
2975
2976 case NOT:
2977 *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 3 : 2);
2978 return true;
2979
2980 case AND:
2981 case IOR:
2982 case XOR:
2983 if (GET_MODE (x) == DImode)
2984 *total = COSTS_N_INSNS (2);
2985 else
2986 *total = COSTS_N_INSNS (1);
2987 return true;
2988
2989 case ASHIFT:
2990 case ASHIFTRT:
2991 case LSHIFTRT:
2992 if (GET_MODE (x) == DImode)
2993 *total = COSTS_N_INSNS (50);
2994 else
2995 *total = COSTS_N_INSNS (1);
2996 return true;
2997
2998 case ABS:
2999 {
3000 enum machine_mode xmode = GET_MODE (x);
3001 if (xmode == SFmode)
3002 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50);
3003 else if (xmode == DFmode)
3004 *total = COSTS_N_INSNS (50);
3005 else
3006 *total = COSTS_N_INSNS (4);
3007 return true;
3008 }
3009
3010 case PLUS:
3011 case MINUS:
3012 {
3013 enum machine_mode xmode = GET_MODE (x);
3014 if (xmode == SFmode)
3015 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50);
3016 else if (xmode == DFmode || xmode == DImode)
3017 *total = COSTS_N_INSNS (50);
3018 else
3019 *total = COSTS_N_INSNS (1);
3020 return true;
3021 }
3022
3023 case NEG:
3024 *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 4 : 2);
3025 return true;
3026
3027 case MULT:
3028 {
3029 enum machine_mode xmode = GET_MODE (x);
3030 if (xmode == SFmode)
3031 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 4 : 50);
3032 else if (xmode == DFmode)
3033 *total = COSTS_N_INSNS (50);
3034 else if (xmode == DImode)
3035 *total = COSTS_N_INSNS (TARGET_MUL32_HIGH ? 10 : 50);
3036 else if (TARGET_MUL32)
3037 *total = COSTS_N_INSNS (4);
3038 else if (TARGET_MAC16)
3039 *total = COSTS_N_INSNS (16);
3040 else if (TARGET_MUL16)
3041 *total = COSTS_N_INSNS (12);
3042 else
3043 *total = COSTS_N_INSNS (50);
3044 return true;
3045 }
3046
3047 case DIV:
3048 case MOD:
3049 {
3050 enum machine_mode xmode = GET_MODE (x);
3051 if (xmode == SFmode)
3052 {
3053 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV ? 8 : 50);
3054 return true;
3055 }
3056 else if (xmode == DFmode)
3057 {
3058 *total = COSTS_N_INSNS (50);
3059 return true;
3060 }
3061 }
3062 /* Fall through. */
3063
3064 case UDIV:
3065 case UMOD:
3066 {
3067 enum machine_mode xmode = GET_MODE (x);
3068 if (xmode == DImode)
3069 *total = COSTS_N_INSNS (50);
3070 else if (TARGET_DIV32)
3071 *total = COSTS_N_INSNS (32);
3072 else
3073 *total = COSTS_N_INSNS (50);
3074 return true;
3075 }
3076
3077 case SQRT:
3078 if (GET_MODE (x) == SFmode)
3079 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT ? 8 : 50);
3080 else
3081 *total = COSTS_N_INSNS (50);
3082 return true;
3083
3084 case SMIN:
3085 case UMIN:
3086 case SMAX:
3087 case UMAX:
3088 *total = COSTS_N_INSNS (TARGET_MINMAX ? 1 : 50);
3089 return true;
3090
3091 case SIGN_EXTRACT:
3092 case SIGN_EXTEND:
3093 *total = COSTS_N_INSNS (TARGET_SEXT ? 1 : 2);
3094 return true;
3095
3096 case ZERO_EXTRACT:
3097 case ZERO_EXTEND:
3098 *total = COSTS_N_INSNS (1);
3099 return true;
3100
3101 default:
3102 return false;
3103 }
3104 }
3105
3106 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3107
3108 static bool
3109 xtensa_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
3110 {
3111 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)
3112 > 4 * UNITS_PER_WORD);
3113 }
3114
3115 #include "gt-xtensa.h"
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