1 ;; Machine description for Sunplus S+CORE
2 ;; Copyright (C) 2005, 2007
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Sunnorth.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 [(set (match_operand:SI 0 "push_operand" "=<")
26 (match_operand:SI 1 "register_operand" "d"))]
29 [(set_attr "type" "store")
30 (set_attr "mode" "SI")])
33 [(set (match_operand:SI 0 "register_operand" "=d")
34 (match_operand:SI 1 "pop_operand" ">"))]
37 [(set_attr "type" "store")
38 (set_attr "mode" "SI")])
41 [(set (match_operand:SI 0 "g32reg_operand" "")
42 (match_operand:SI 1 "loreg_operand" ""))
43 (set (match_operand:SI 2 "g32reg_operand" "")
44 (match_operand:SI 3 "hireg_operand" ""))]
47 [(set (match_dup 0) (match_dup 1))
48 (set (match_dup 2) (match_dup 3))])])
51 [(set (match_operand:SI 0 "g32reg_operand" "")
52 (match_operand:SI 1 "hireg_operand" ""))
53 (set (match_operand:SI 2 "g32reg_operand" "")
54 (match_operand:SI 3 "loreg_operand" ""))]
57 [(set (match_dup 2) (match_dup 3))
58 (set (match_dup 0) (match_dup 1))])])
60 (define_insn "movhilo"
62 [(set (match_operand:SI 0 "register_operand" "=d")
63 (match_operand:SI 1 "loreg_operand" ""))
64 (set (match_operand:SI 2 "register_operand" "=d")
65 (match_operand:SI 3 "hireg_operand" ""))])]
68 [(set_attr "type" "fce")
69 (set_attr "mode" "SI")])
71 (define_expand "movsicc"
72 [(set (match_operand:SI 0 "register_operand" "")
73 (if_then_else:SI (match_operator 1 "comparison_operator"
74 [(reg:CC CC_REGNUM) (const_int 0)])
75 (match_operand:SI 2 "register_operand" "")
76 (match_operand:SI 3 "register_operand" "")))]
79 mdx_movsicc (operands);
82 (define_insn "movsicc_internal"
83 [(set (match_operand:SI 0 "register_operand" "=d")
84 (if_then_else:SI (match_operator 1 "comparison_operator"
85 [(reg:CC CC_REGNUM) (const_int 0)])
86 (match_operand:SI 2 "arith_operand" "d")
87 (match_operand:SI 3 "arith_operand" "0")))]
90 [(set_attr "type" "cndmv")
91 (set_attr "mode" "SI")])
93 (define_insn "zero_extract_bittst"
94 [(set (reg:CC_NZ CC_REGNUM)
95 (compare:CC_NZ (unspec:SI
96 [(match_operand:SI 0 "register_operand" "*e,d")
97 (match_operand:SI 1 "const_uimm5" "")]
104 [(set_attr "type" "arith")
105 (set_attr "up_c" "yes")
106 (set_attr "mode" "SI")])
108 (define_expand "extzv"
109 [(set (match_operand:SI 0 "register_operand" "")
110 (zero_extract (match_operand:SI 1 "memory_operand" "")
111 (match_operand:SI 2 "immediate_operand" "")
112 (match_operand:SI 3 "immediate_operand" "")))]
113 "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
115 if (mdx_unaligned_load (operands))
121 (define_expand "insv"
122 [(set (zero_extract (match_operand:SI 0 "memory_operand" "")
123 (match_operand:SI 1 "immediate_operand" "")
124 (match_operand:SI 2 "immediate_operand" ""))
125 (match_operand:SI 3 "register_operand" ""))]
126 "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
128 if (mdx_unaligned_store (operands))
134 (define_expand "extv"
135 [(set (match_operand:SI 0 "register_operand" "")
136 (sign_extract (match_operand:SI 1 "memory_operand" "")
137 (match_operand:SI 2 "immediate_operand" "")
138 (match_operand:SI 3 "immediate_operand" "")))]
139 "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
141 if (mdx_unaligned_load (operands))
147 (define_expand "movmemsi"
148 [(parallel [(set (match_operand:BLK 0 "general_operand")
149 (match_operand:BLK 1 "general_operand"))
150 (use (match_operand:SI 2 ""))
151 (use (match_operand:SI 3 "const_int_operand"))])]
152 "!TARGET_SCORE5U && TARGET_ULS"
154 if (mdx_block_move (operands))
160 (define_insn "move_lbu_a"
161 [(set (match_operand:SI 0 "register_operand" "=d")
162 (plus:SI (match_operand:SI 1 "register_operand" "0")
163 (match_operand:SI 2 "const_simm12" "")))
164 (set (match_operand:QI 3 "register_operand" "=d")
165 (mem:QI (match_dup 1)))]
168 [(set_attr "type" "load")
169 (set_attr "mode" "QI")])
171 (define_insn "move_lhu_a"
172 [(set (match_operand:SI 0 "register_operand" "=d")
173 (plus:SI (match_operand:SI 1 "register_operand" "0")
174 (match_operand:SI 2 "const_simm12" "")))
175 (set (match_operand:HI 3 "register_operand" "=d")
176 (mem:HI (match_dup 1)))]
179 [(set_attr "type" "load")
180 (set_attr "mode" "HI")])
182 (define_insn "move_lw_a"
183 [(set (match_operand:SI 0 "register_operand" "=d")
184 (plus:SI (match_operand:SI 1 "register_operand" "0")
185 (match_operand:SI 2 "const_simm12" "")))
186 (set (match_operand:SI 3 "register_operand" "=d")
187 (mem:SI (match_dup 1)))]
190 [(set_attr "type" "load")
191 (set_attr "mode" "SI")])
193 (define_insn "move_sb_a"
194 [(set (match_operand:SI 0 "register_operand" "=d")
195 (plus:SI (match_operand:SI 1 "register_operand" "0")
196 (match_operand:SI 2 "const_simm12" "")))
197 (set (mem:QI (match_dup 1))
198 (match_operand:QI 3 "register_operand" "d"))]
201 [(set_attr "type" "store")
202 (set_attr "mode" "QI")])
204 (define_insn "move_sh_a"
205 [(set (match_operand:SI 0 "register_operand" "=d")
206 (plus:SI (match_operand:SI 1 "register_operand" "0")
207 (match_operand:SI 2 "const_simm12" "")))
208 (set (mem:HI (match_dup 1))
209 (match_operand:HI 3 "register_operand" "d"))]
212 [(set_attr "type" "store")
213 (set_attr "mode" "HI")])
215 (define_insn "move_sw_a"
216 [(set (match_operand:SI 0 "register_operand" "=d")
217 (plus:SI (match_operand:SI 1 "register_operand" "0")
218 (match_operand:SI 2 "const_simm12" "")))
219 (set (mem:SI (match_dup 1))
220 (match_operand:SI 3 "register_operand" "d"))]
223 [(set_attr "type" "store")
224 (set_attr "mode" "SI")])
226 (define_insn "move_lbu_b"
227 [(set (match_operand:SI 0 "register_operand" "=d")
228 (plus:SI (match_operand:SI 1 "register_operand" "0")
229 (match_operand:SI 2 "const_simm12" "")))
230 (set (match_operand:QI 3 "register_operand" "=d")
231 (mem:QI (plus:SI (match_dup 1)
235 [(set_attr "type" "load")
236 (set_attr "mode" "QI")])
238 (define_insn "move_lhu_b"
239 [(set (match_operand:SI 0 "register_operand" "=d")
240 (plus:SI (match_operand:SI 1 "register_operand" "0")
241 (match_operand:SI 2 "const_simm12" "")))
242 (set (match_operand:HI 3 "register_operand" "=d")
243 (mem:HI (plus:SI (match_dup 1)
247 [(set_attr "type" "load")
248 (set_attr "mode" "HI")])
250 (define_insn "move_lw_b"
251 [(set (match_operand:SI 0 "register_operand" "=d")
252 (plus:SI (match_operand:SI 1 "register_operand" "0")
253 (match_operand:SI 2 "const_simm12" "")))
254 (set (match_operand:SI 3 "register_operand" "=d")
255 (mem:SI (plus:SI (match_dup 1)
259 [(set_attr "type" "load")
260 (set_attr "mode" "SI")])
262 (define_insn "move_sb_b"
263 [(set (match_operand:SI 0 "register_operand" "=d")
264 (plus:SI (match_operand:SI 1 "register_operand" "0")
265 (match_operand:SI 2 "const_simm12" "")))
266 (set (mem:QI (plus:SI (match_dup 1)
268 (match_operand:QI 3 "register_operand" "d"))]
271 [(set_attr "type" "store")
272 (set_attr "mode" "QI")])
274 (define_insn "move_sh_b"
275 [(set (match_operand:SI 0 "register_operand" "=d")
276 (plus:SI (match_operand:SI 1 "register_operand" "0")
277 (match_operand:SI 2 "const_simm12" "")))
278 (set (mem:HI (plus:SI (match_dup 1)
280 (match_operand:HI 3 "register_operand" "d"))]
283 [(set_attr "type" "store")
284 (set_attr "mode" "HI")])
286 (define_insn "move_sw_b"
287 [(set (match_operand:SI 0 "register_operand" "=d")
288 (plus:SI (match_operand:SI 1 "register_operand" "0")
289 (match_operand:SI 2 "const_simm12" "")))
290 (set (mem:SI (plus:SI (match_dup 1)
292 (match_operand:SI 3 "register_operand" "d"))]
295 [(set_attr "type" "store")
296 (set_attr "mode" "SI")])
298 (define_insn "move_lcb"
299 [(set (match_operand:SI 0 "register_operand" "=d")
300 (plus:SI (match_operand:SI 1 "register_operand" "0")
302 (set (reg:SI LC_REGNUM)
303 (unspec:SI [(mem:BLK (match_dup 1))] LCB))]
304 "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
306 [(set_attr "type" "load")
307 (set_attr "mode" "SI")])
309 (define_insn "move_lcw"
310 [(set (match_operand:SI 0 "register_operand" "=d")
311 (plus:SI (match_operand:SI 1 "register_operand" "0")
313 (set (match_operand:SI 2 "register_operand" "=d")
314 (unspec:SI [(mem:BLK (match_dup 1))
315 (reg:SI LC_REGNUM)] LCW))
316 (set (reg:SI LC_REGNUM)
317 (unspec:SI [(mem:BLK (match_dup 1))] LCB))]
318 "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
320 [(set_attr "type" "load")
321 (set_attr "mode" "SI")])
323 (define_insn "move_lce"
324 [(set (match_operand:SI 0 "register_operand" "=d")
325 (plus:SI (match_operand:SI 1 "register_operand" "0")
327 (set (match_operand:SI 2 "register_operand" "=d")
328 (unspec:SI [(mem:BLK (match_dup 1))
329 (reg:SI LC_REGNUM)] LCE))]
330 "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
332 [(set_attr "type" "load")
333 (set_attr "mode" "SI")])
335 (define_insn "move_scb"
336 [(set (match_operand:SI 0 "register_operand" "=d")
337 (plus:SI (match_operand:SI 1 "register_operand" "0")
339 (set (mem:BLK (match_dup 1))
340 (unspec:BLK [(match_operand:SI 2 "register_operand" "d")] SCB))
341 (set (reg:SI SC_REGNUM)
342 (unspec:SI [(match_dup 2)] SCLC))]
343 "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
345 [(set_attr "type" "store")
346 (set_attr "mode" "SI")])
348 (define_insn "move_scw"
349 [(set (match_operand:SI 0 "register_operand" "=d")
350 (plus:SI (match_operand:SI 1 "register_operand" "0")
352 (set (mem:BLK (match_dup 1))
353 (unspec:BLK [(match_operand:SI 2 "register_operand" "d")
354 (reg:SI SC_REGNUM)] SCW))
355 (set (reg:SI SC_REGNUM)
356 (unspec:SI [(match_dup 2)] SCLC))]
357 "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
359 [(set_attr "type" "store")
360 (set_attr "mode" "SI")])
362 (define_insn "move_sce"
363 [(set (match_operand:SI 0 "register_operand" "=d")
364 (plus:SI (match_operand:SI 1 "register_operand" "0")
366 (set (mem:BLK (match_dup 1))
367 (unspec:BLK [(reg:SI SC_REGNUM)] SCE))]
368 "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
370 [(set_attr "type" "store")
371 (set_attr "mode" "SI")])
373 (define_insn "andsi3_extzh"
374 [(set (match_operand:SI 0 "register_operand" "=d")
375 (and:SI (match_operand:SI 1 "register_operand" "d")
379 [(set_attr "type" "arith")
380 (set_attr "mode" "SI")])