| blob | 954dfec6f0c4fb72ed960d0a243c828705942fc6 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 3, or (at your
12 ;; option) any later version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;;
26 ;; REGNOS
27 ;;
29 (define_constants
30 [(MQ_REGNO 64)
31 (LR_REGNO 65)
32 (CTR_REGNO 66)
33 (CR0_REGNO 68)
34 (CR1_REGNO 69)
35 (CR2_REGNO 70)
36 (CR3_REGNO 71)
37 (CR4_REGNO 72)
38 (CR5_REGNO 73)
39 (CR6_REGNO 74)
40 (CR7_REGNO 75)
41 (MAX_CR_REGNO 75)
42 (XER_REGNO 76)
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
45 (VRSAVE_REGNO 109)
46 (VSCR_REGNO 110)
47 (SPE_ACC_REGNO 111)
48 (SPEFSCR_REGNO 112)
49 (SFP_REGNO 113)
50 ])
52 ;;
53 ;; UNSPEC usage
54 ;;
56 (define_constants
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
59 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
60 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
61 (UNSPEC_MOVSI_GOT 8)
62 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
63 (UNSPEC_FCTIWZ 10)
64 (UNSPEC_FRIM 11)
65 (UNSPEC_FRIN 12)
66 (UNSPEC_FRIP 13)
67 (UNSPEC_FRIZ 14)
68 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
69 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
70 (UNSPEC_TLSGD 17)
71 (UNSPEC_TLSLD 18)
72 (UNSPEC_MOVESI_FROM_CR 19)
73 (UNSPEC_MOVESI_TO_CR 20)
74 (UNSPEC_TLSDTPREL 21)
75 (UNSPEC_TLSDTPRELHA 22)
76 (UNSPEC_TLSDTPRELLO 23)
77 (UNSPEC_TLSGOTDTPREL 24)
78 (UNSPEC_TLSTPREL 25)
79 (UNSPEC_TLSTPRELHA 26)
80 (UNSPEC_TLSTPRELLO 27)
81 (UNSPEC_TLSGOTTPREL 28)
82 (UNSPEC_TLSTLS 29)
83 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
84 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
85 (UNSPEC_STFIWX 32)
86 (UNSPEC_POPCNTB 33)
87 (UNSPEC_FRES 34)
88 (UNSPEC_SP_SET 35)
89 (UNSPEC_SP_TEST 36)
90 (UNSPEC_SYNC 37)
91 (UNSPEC_LWSYNC 38)
92 (UNSPEC_ISYNC 39)
93 (UNSPEC_SYNC_OP 40)
94 (UNSPEC_ATOMIC 41)
95 (UNSPEC_CMPXCHG 42)
96 (UNSPEC_XCHG 43)
97 (UNSPEC_AND 44)
98 (UNSPEC_DLMZB 45)
99 (UNSPEC_DLMZB_CR 46)
100 (UNSPEC_DLMZB_STRLEN 47)
101 (UNSPEC_RSQRT 48)
102 ])
104 ;;
105 ;; UNSPEC_VOLATILE usage
106 ;;
108 (define_constants
109 [(UNSPECV_BLOCK 0)
110 (UNSPECV_LL 1) ; load-locked
111 (UNSPECV_SC 2) ; store-conditional
112 (UNSPECV_EH_RR 9) ; eh_reg_restore
113 ])
114 \f
115 ;; Define an insn type attribute. This is used in function unit delay
116 ;; computations.
117 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr"
118 (const_string "integer"))
120 ;; Length (in bytes).
121 ; '(pc)' in the following doesn't include the instruction itself; it is
122 ; calculated as if the instruction had zero size.
123 (define_attr "length" ""
124 (if_then_else (eq_attr "type" "branch")
125 (if_then_else (and (ge (minus (match_dup 0) (pc))
126 (const_int -32768))
127 (lt (minus (match_dup 0) (pc))
128 (const_int 32764)))
129 (const_int 4)
130 (const_int 8))
131 (const_int 4)))
133 ;; Processor type -- this attribute must exactly match the processor_type
134 ;; enumeration in rs6000.h.
136 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5,power6,cell"
137 (const (symbol_ref "rs6000_cpu_attr")))
140 ;; If this instruction is microcoded on the CELL processor
141 ; The default for load and stores is conditional
142 ; The default for load extended and the recorded instructions is always microcoded
143 (define_attr "cell_micro" "not,conditional,always"
144 (if_then_else (ior (ior (eq_attr "type" "load")
145 (eq_attr "type" "store"))
146 (ior (eq_attr "type" "fpload")
147 (eq_attr "type" "fpstore")))
148 (const_string "conditional")
149 (if_then_else (ior (eq_attr "type" "load_ext")
150 (ior (eq_attr "type" "compare")
151 (eq_attr "type" "delayed_compare")))
152 (const_string "always")
153 (const_string "not"))))
156 (automata_option "ndfa")
158 (include "rios1.md")
159 (include "rios2.md")
160 (include "rs64.md")
161 (include "mpc.md")
162 (include "40x.md")
163 (include "440.md")
164 (include "603.md")
165 (include "6xx.md")
166 (include "7xx.md")
167 (include "7450.md")
168 (include "8540.md")
169 (include "power4.md")
170 (include "power5.md")
171 (include "power6.md")
172 (include "cell.md")
174 (include "predicates.md")
175 (include "constraints.md")
177 (include "darwin.md")
179 \f
180 ;; Mode iterators
182 ; This mode iterator allows :GPR to be used to indicate the allowable size
183 ; of whole values in GPRs.
184 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
186 ; Any supported integer mode.
187 (define_mode_iterator INT [QI HI SI DI TI])
189 ; Any supported integer mode that fits in one register.
190 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
192 ; extend modes for DImode
193 (define_mode_iterator QHSI [QI HI SI])
195 ; SImode or DImode, even if DImode doesn't fit in GPRs.
196 (define_mode_iterator SDI [SI DI])
198 ; The size of a pointer. Also, the size of the value that a record-condition
199 ; (one with a '.') will compare.
200 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
202 ; Any hardware-supported floating-point mode
203 (define_mode_iterator FP [(SF "TARGET_HARD_FLOAT")
204 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
205 (TF "!TARGET_IEEEQUAD
206 && TARGET_HARD_FLOAT
207 && (TARGET_FPRS || TARGET_E500_DOUBLE)
208 && TARGET_LONG_DOUBLE_128")
209 (DD "TARGET_DFP")
210 (TD "TARGET_DFP")])
212 ; Various instructions that come in SI and DI forms.
213 ; A generic w/d attribute, for things like cmpw/cmpd.
214 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
216 ; DImode bits
217 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
219 \f
220 ;; Start with fixed-point load and store insns. Here we put only the more
221 ;; complex forms. Basic data transfer is done later.
223 (define_expand "zero_extend<mode>di2"
224 [(set (match_operand:DI 0 "gpc_reg_operand" "")
225 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
226 "TARGET_POWERPC64"
227 "")
229 (define_insn "*zero_extend<mode>di2_internal1"
230 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
231 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
232 "TARGET_POWERPC64"
233 "@
234 l<wd>z%U1%X1 %0,%1
235 rldicl %0,%1,0,<dbits>"
236 [(set_attr "type" "load,*")])
238 (define_insn "*zero_extend<mode>di2_internal2"
239 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
240 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
241 (const_int 0)))
242 (clobber (match_scratch:DI 2 "=r,r"))]
243 "TARGET_64BIT"
244 "@
245 rldicl. %2,%1,0,<dbits>
246 #"
247 [(set_attr "type" "compare")
248 (set_attr "length" "4,8")])
250 (define_split
251 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
252 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
253 (const_int 0)))
254 (clobber (match_scratch:DI 2 ""))]
255 "TARGET_POWERPC64 && reload_completed"
256 [(set (match_dup 2)
257 (zero_extend:DI (match_dup 1)))
258 (set (match_dup 0)
259 (compare:CC (match_dup 2)
260 (const_int 0)))]
261 "")
263 (define_insn "*zero_extend<mode>di2_internal3"
264 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
265 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
266 (const_int 0)))
267 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
268 (zero_extend:DI (match_dup 1)))]
269 "TARGET_64BIT"
270 "@
271 rldicl. %0,%1,0,<dbits>
272 #"
273 [(set_attr "type" "compare")
274 (set_attr "length" "4,8")])
276 (define_split
277 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
278 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
279 (const_int 0)))
280 (set (match_operand:DI 0 "gpc_reg_operand" "")
281 (zero_extend:DI (match_dup 1)))]
282 "TARGET_POWERPC64 && reload_completed"
283 [(set (match_dup 0)
284 (zero_extend:DI (match_dup 1)))
285 (set (match_dup 2)
286 (compare:CC (match_dup 0)
287 (const_int 0)))]
288 "")
290 (define_insn "extendqidi2"
291 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
292 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
293 "TARGET_POWERPC64"
294 "extsb %0,%1"
295 [(set_attr "type" "exts")])
297 (define_insn ""
298 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
299 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
300 (const_int 0)))
301 (clobber (match_scratch:DI 2 "=r,r"))]
302 "TARGET_64BIT"
303 "@
304 extsb. %2,%1
305 #"
306 [(set_attr "type" "compare")
307 (set_attr "length" "4,8")])
309 (define_split
310 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
311 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
312 (const_int 0)))
313 (clobber (match_scratch:DI 2 ""))]
314 "TARGET_POWERPC64 && reload_completed"
315 [(set (match_dup 2)
316 (sign_extend:DI (match_dup 1)))
317 (set (match_dup 0)
318 (compare:CC (match_dup 2)
319 (const_int 0)))]
320 "")
322 (define_insn ""
323 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
324 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
325 (const_int 0)))
326 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
327 (sign_extend:DI (match_dup 1)))]
328 "TARGET_64BIT"
329 "@
330 extsb. %0,%1
331 #"
332 [(set_attr "type" "compare")
333 (set_attr "length" "4,8")])
335 (define_split
336 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
337 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
338 (const_int 0)))
339 (set (match_operand:DI 0 "gpc_reg_operand" "")
340 (sign_extend:DI (match_dup 1)))]
341 "TARGET_POWERPC64 && reload_completed"
342 [(set (match_dup 0)
343 (sign_extend:DI (match_dup 1)))
344 (set (match_dup 2)
345 (compare:CC (match_dup 0)
346 (const_int 0)))]
347 "")
349 (define_expand "extendhidi2"
350 [(set (match_operand:DI 0 "gpc_reg_operand" "")
351 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
352 "TARGET_POWERPC64"
353 "")
355 (define_insn ""
356 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
357 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
358 "TARGET_POWERPC64"
359 "@
360 lha%U1%X1 %0,%1
361 extsh %0,%1"
362 [(set_attr "type" "load_ext,exts")])
364 (define_insn ""
365 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
366 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
367 (const_int 0)))
368 (clobber (match_scratch:DI 2 "=r,r"))]
369 "TARGET_64BIT"
370 "@
371 extsh. %2,%1
372 #"
373 [(set_attr "type" "compare")
374 (set_attr "length" "4,8")])
376 (define_split
377 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
378 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
379 (const_int 0)))
380 (clobber (match_scratch:DI 2 ""))]
381 "TARGET_POWERPC64 && reload_completed"
382 [(set (match_dup 2)
383 (sign_extend:DI (match_dup 1)))
384 (set (match_dup 0)
385 (compare:CC (match_dup 2)
386 (const_int 0)))]
387 "")
389 (define_insn ""
390 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
391 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
392 (const_int 0)))
393 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
394 (sign_extend:DI (match_dup 1)))]
395 "TARGET_64BIT"
396 "@
397 extsh. %0,%1
398 #"
399 [(set_attr "type" "compare")
400 (set_attr "length" "4,8")])
402 (define_split
403 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
404 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
405 (const_int 0)))
406 (set (match_operand:DI 0 "gpc_reg_operand" "")
407 (sign_extend:DI (match_dup 1)))]
408 "TARGET_POWERPC64 && reload_completed"
409 [(set (match_dup 0)
410 (sign_extend:DI (match_dup 1)))
411 (set (match_dup 2)
412 (compare:CC (match_dup 0)
413 (const_int 0)))]
414 "")
416 (define_expand "extendsidi2"
417 [(set (match_operand:DI 0 "gpc_reg_operand" "")
418 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
419 "TARGET_POWERPC64"
420 "")
422 (define_insn ""
423 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
424 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
425 "TARGET_POWERPC64"
426 "@
427 lwa%U1%X1 %0,%1
428 extsw %0,%1"
429 [(set_attr "type" "load_ext,exts")])
431 (define_insn ""
432 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
433 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
434 (const_int 0)))
435 (clobber (match_scratch:DI 2 "=r,r"))]
436 "TARGET_64BIT"
437 "@
438 extsw. %2,%1
439 #"
440 [(set_attr "type" "compare")
441 (set_attr "length" "4,8")])
443 (define_split
444 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
445 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
446 (const_int 0)))
447 (clobber (match_scratch:DI 2 ""))]
448 "TARGET_POWERPC64 && reload_completed"
449 [(set (match_dup 2)
450 (sign_extend:DI (match_dup 1)))
451 (set (match_dup 0)
452 (compare:CC (match_dup 2)
453 (const_int 0)))]
454 "")
456 (define_insn ""
457 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
458 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
459 (const_int 0)))
460 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
461 (sign_extend:DI (match_dup 1)))]
462 "TARGET_64BIT"
463 "@
464 extsw. %0,%1
465 #"
466 [(set_attr "type" "compare")
467 (set_attr "length" "4,8")])
469 (define_split
470 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
471 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
472 (const_int 0)))
473 (set (match_operand:DI 0 "gpc_reg_operand" "")
474 (sign_extend:DI (match_dup 1)))]
475 "TARGET_POWERPC64 && reload_completed"
476 [(set (match_dup 0)
477 (sign_extend:DI (match_dup 1)))
478 (set (match_dup 2)
479 (compare:CC (match_dup 0)
480 (const_int 0)))]
481 "")
483 (define_expand "zero_extendqisi2"
484 [(set (match_operand:SI 0 "gpc_reg_operand" "")
485 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
486 ""
487 "")
489 (define_insn ""
490 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
491 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
492 ""
493 "@
494 lbz%U1%X1 %0,%1
495 {rlinm|rlwinm} %0,%1,0,0xff"
496 [(set_attr "type" "load,*")])
498 (define_insn ""
499 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
500 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
501 (const_int 0)))
502 (clobber (match_scratch:SI 2 "=r,r"))]
503 ""
504 "@
505 {andil.|andi.} %2,%1,0xff
506 #"
507 [(set_attr "type" "compare")
508 (set_attr "length" "4,8")])
510 (define_split
511 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
512 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
513 (const_int 0)))
514 (clobber (match_scratch:SI 2 ""))]
515 "reload_completed"
516 [(set (match_dup 2)
517 (zero_extend:SI (match_dup 1)))
518 (set (match_dup 0)
519 (compare:CC (match_dup 2)
520 (const_int 0)))]
521 "")
523 (define_insn ""
524 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
525 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
526 (const_int 0)))
527 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
528 (zero_extend:SI (match_dup 1)))]
529 ""
530 "@
531 {andil.|andi.} %0,%1,0xff
532 #"
533 [(set_attr "type" "compare")
534 (set_attr "length" "4,8")])
536 (define_split
537 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
538 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
539 (const_int 0)))
540 (set (match_operand:SI 0 "gpc_reg_operand" "")
541 (zero_extend:SI (match_dup 1)))]
542 "reload_completed"
543 [(set (match_dup 0)
544 (zero_extend:SI (match_dup 1)))
545 (set (match_dup 2)
546 (compare:CC (match_dup 0)
547 (const_int 0)))]
548 "")
550 (define_expand "extendqisi2"
551 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
552 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
553 ""
554 "
555 {
556 if (TARGET_POWERPC)
557 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
558 else if (TARGET_POWER)
559 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
560 else
561 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
562 DONE;
563 }")
565 (define_insn "extendqisi2_ppc"
566 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
567 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
568 "TARGET_POWERPC"
569 "extsb %0,%1"
570 [(set_attr "type" "exts")])
572 (define_insn ""
573 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
574 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
575 (const_int 0)))
576 (clobber (match_scratch:SI 2 "=r,r"))]
577 "TARGET_POWERPC"
578 "@
579 extsb. %2,%1
580 #"
581 [(set_attr "type" "compare")
582 (set_attr "length" "4,8")])
584 (define_split
585 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
586 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
587 (const_int 0)))
588 (clobber (match_scratch:SI 2 ""))]
589 "TARGET_POWERPC && reload_completed"
590 [(set (match_dup 2)
591 (sign_extend:SI (match_dup 1)))
592 (set (match_dup 0)
593 (compare:CC (match_dup 2)
594 (const_int 0)))]
595 "")
597 (define_insn ""
598 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
599 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
600 (const_int 0)))
601 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
602 (sign_extend:SI (match_dup 1)))]
603 "TARGET_POWERPC"
604 "@
605 extsb. %0,%1
606 #"
607 [(set_attr "type" "compare")
608 (set_attr "length" "4,8")])
610 (define_split
611 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
612 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
613 (const_int 0)))
614 (set (match_operand:SI 0 "gpc_reg_operand" "")
615 (sign_extend:SI (match_dup 1)))]
616 "TARGET_POWERPC && reload_completed"
617 [(set (match_dup 0)
618 (sign_extend:SI (match_dup 1)))
619 (set (match_dup 2)
620 (compare:CC (match_dup 0)
621 (const_int 0)))]
622 "")
624 (define_expand "extendqisi2_power"
625 [(parallel [(set (match_dup 2)
626 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
627 (const_int 24)))
628 (clobber (scratch:SI))])
629 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
630 (ashiftrt:SI (match_dup 2)
631 (const_int 24)))
632 (clobber (scratch:SI))])]
633 "TARGET_POWER"
634 "
635 { operands[1] = gen_lowpart (SImode, operands[1]);
636 operands[2] = gen_reg_rtx (SImode); }")
638 (define_expand "extendqisi2_no_power"
639 [(set (match_dup 2)
640 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
641 (const_int 24)))
642 (set (match_operand:SI 0 "gpc_reg_operand" "")
643 (ashiftrt:SI (match_dup 2)
644 (const_int 24)))]
645 "! TARGET_POWER && ! TARGET_POWERPC"
646 "
647 { operands[1] = gen_lowpart (SImode, operands[1]);
648 operands[2] = gen_reg_rtx (SImode); }")
650 (define_expand "zero_extendqihi2"
651 [(set (match_operand:HI 0 "gpc_reg_operand" "")
652 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
653 ""
654 "")
656 (define_insn ""
657 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
658 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
659 ""
660 "@
661 lbz%U1%X1 %0,%1
662 {rlinm|rlwinm} %0,%1,0,0xff"
663 [(set_attr "type" "load,*")])
665 (define_insn ""
666 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
667 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
668 (const_int 0)))
669 (clobber (match_scratch:HI 2 "=r,r"))]
670 ""
671 "@
672 {andil.|andi.} %2,%1,0xff
673 #"
674 [(set_attr "type" "compare")
675 (set_attr "length" "4,8")])
677 (define_split
678 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
679 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
680 (const_int 0)))
681 (clobber (match_scratch:HI 2 ""))]
682 "reload_completed"
683 [(set (match_dup 2)
684 (zero_extend:HI (match_dup 1)))
685 (set (match_dup 0)
686 (compare:CC (match_dup 2)
687 (const_int 0)))]
688 "")
690 (define_insn ""
691 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
692 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
693 (const_int 0)))
694 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
695 (zero_extend:HI (match_dup 1)))]
696 ""
697 "@
698 {andil.|andi.} %0,%1,0xff
699 #"
700 [(set_attr "type" "compare")
701 (set_attr "length" "4,8")])
703 (define_split
704 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
705 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
706 (const_int 0)))
707 (set (match_operand:HI 0 "gpc_reg_operand" "")
708 (zero_extend:HI (match_dup 1)))]
709 "reload_completed"
710 [(set (match_dup 0)
711 (zero_extend:HI (match_dup 1)))
712 (set (match_dup 2)
713 (compare:CC (match_dup 0)
714 (const_int 0)))]
715 "")
717 (define_expand "extendqihi2"
718 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
719 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
720 ""
721 "
722 {
723 if (TARGET_POWERPC)
724 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
725 else if (TARGET_POWER)
726 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
727 else
728 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
729 DONE;
730 }")
732 (define_insn "extendqihi2_ppc"
733 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
734 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
735 "TARGET_POWERPC"
736 "extsb %0,%1"
737 [(set_attr "type" "exts")])
739 (define_insn ""
740 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
741 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
742 (const_int 0)))
743 (clobber (match_scratch:HI 2 "=r,r"))]
744 "TARGET_POWERPC"
745 "@
746 extsb. %2,%1
747 #"
748 [(set_attr "type" "compare")
749 (set_attr "length" "4,8")])
751 (define_split
752 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
753 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
754 (const_int 0)))
755 (clobber (match_scratch:HI 2 ""))]
756 "TARGET_POWERPC && reload_completed"
757 [(set (match_dup 2)
758 (sign_extend:HI (match_dup 1)))
759 (set (match_dup 0)
760 (compare:CC (match_dup 2)
761 (const_int 0)))]
762 "")
764 (define_insn ""
765 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
766 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
767 (const_int 0)))
768 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
769 (sign_extend:HI (match_dup 1)))]
770 "TARGET_POWERPC"
771 "@
772 extsb. %0,%1
773 #"
774 [(set_attr "type" "compare")
775 (set_attr "length" "4,8")])
777 (define_split
778 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
779 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
780 (const_int 0)))
781 (set (match_operand:HI 0 "gpc_reg_operand" "")
782 (sign_extend:HI (match_dup 1)))]
783 "TARGET_POWERPC && reload_completed"
784 [(set (match_dup 0)
785 (sign_extend:HI (match_dup 1)))
786 (set (match_dup 2)
787 (compare:CC (match_dup 0)
788 (const_int 0)))]
789 "")
791 (define_expand "extendqihi2_power"
792 [(parallel [(set (match_dup 2)
793 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
794 (const_int 24)))
795 (clobber (scratch:SI))])
796 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
797 (ashiftrt:SI (match_dup 2)
798 (const_int 24)))
799 (clobber (scratch:SI))])]
800 "TARGET_POWER"
801 "
802 { operands[0] = gen_lowpart (SImode, operands[0]);
803 operands[1] = gen_lowpart (SImode, operands[1]);
804 operands[2] = gen_reg_rtx (SImode); }")
806 (define_expand "extendqihi2_no_power"
807 [(set (match_dup 2)
808 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
809 (const_int 24)))
810 (set (match_operand:HI 0 "gpc_reg_operand" "")
811 (ashiftrt:SI (match_dup 2)
812 (const_int 24)))]
813 "! TARGET_POWER && ! TARGET_POWERPC"
814 "
815 { operands[0] = gen_lowpart (SImode, operands[0]);
816 operands[1] = gen_lowpart (SImode, operands[1]);
817 operands[2] = gen_reg_rtx (SImode); }")
819 (define_expand "zero_extendhisi2"
820 [(set (match_operand:SI 0 "gpc_reg_operand" "")
821 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
822 ""
823 "")
825 (define_insn ""
826 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
827 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
828 ""
829 "@
830 lhz%U1%X1 %0,%1
831 {rlinm|rlwinm} %0,%1,0,0xffff"
832 [(set_attr "type" "load,*")])
834 (define_insn ""
835 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
836 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
837 (const_int 0)))
838 (clobber (match_scratch:SI 2 "=r,r"))]
839 ""
840 "@
841 {andil.|andi.} %2,%1,0xffff
842 #"
843 [(set_attr "type" "compare")
844 (set_attr "length" "4,8")])
846 (define_split
847 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
848 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
849 (const_int 0)))
850 (clobber (match_scratch:SI 2 ""))]
851 "reload_completed"
852 [(set (match_dup 2)
853 (zero_extend:SI (match_dup 1)))
854 (set (match_dup 0)
855 (compare:CC (match_dup 2)
856 (const_int 0)))]
857 "")
859 (define_insn ""
860 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
861 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
862 (const_int 0)))
863 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
864 (zero_extend:SI (match_dup 1)))]
865 ""
866 "@
867 {andil.|andi.} %0,%1,0xffff
868 #"
869 [(set_attr "type" "compare")
870 (set_attr "length" "4,8")])
872 (define_split
873 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
874 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
875 (const_int 0)))
876 (set (match_operand:SI 0 "gpc_reg_operand" "")
877 (zero_extend:SI (match_dup 1)))]
878 "reload_completed"
879 [(set (match_dup 0)
880 (zero_extend:SI (match_dup 1)))
881 (set (match_dup 2)
882 (compare:CC (match_dup 0)
883 (const_int 0)))]
884 "")
886 (define_expand "extendhisi2"
887 [(set (match_operand:SI 0 "gpc_reg_operand" "")
888 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
889 ""
890 "")
892 (define_insn ""
893 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
894 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
895 ""
896 "@
897 lha%U1%X1 %0,%1
898 {exts|extsh} %0,%1"
899 [(set_attr "type" "load_ext,exts")])
901 (define_insn ""
902 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
903 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
904 (const_int 0)))
905 (clobber (match_scratch:SI 2 "=r,r"))]
906 ""
907 "@
908 {exts.|extsh.} %2,%1
909 #"
910 [(set_attr "type" "compare")
911 (set_attr "length" "4,8")])
913 (define_split
914 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
915 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
916 (const_int 0)))
917 (clobber (match_scratch:SI 2 ""))]
918 "reload_completed"
919 [(set (match_dup 2)
920 (sign_extend:SI (match_dup 1)))
921 (set (match_dup 0)
922 (compare:CC (match_dup 2)
923 (const_int 0)))]
924 "")
926 (define_insn ""
927 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
928 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
929 (const_int 0)))
930 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
931 (sign_extend:SI (match_dup 1)))]
932 ""
933 "@
934 {exts.|extsh.} %0,%1
935 #"
936 [(set_attr "type" "compare")
937 (set_attr "length" "4,8")])
938 \f
939 ;; IBM 405 and 440 half-word multiplication operations.
941 (define_insn "*macchwc"
942 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
943 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
944 (match_operand:SI 2 "gpc_reg_operand" "r")
945 (const_int 16))
946 (sign_extend:SI
947 (match_operand:HI 1 "gpc_reg_operand" "r")))
948 (match_operand:SI 4 "gpc_reg_operand" "0"))
949 (const_int 0)))
950 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
951 (plus:SI (mult:SI (ashiftrt:SI
952 (match_dup 2)
953 (const_int 16))
954 (sign_extend:SI
955 (match_dup 1)))
956 (match_dup 4)))]
957 "TARGET_MULHW"
958 "macchw. %0, %1, %2"
959 [(set_attr "type" "imul3")])
961 (define_insn "*macchw"
962 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
963 (plus:SI (mult:SI (ashiftrt:SI
964 (match_operand:SI 2 "gpc_reg_operand" "r")
965 (const_int 16))
966 (sign_extend:SI
967 (match_operand:HI 1 "gpc_reg_operand" "r")))
968 (match_operand:SI 3 "gpc_reg_operand" "0")))]
969 "TARGET_MULHW"
970 "macchw %0, %1, %2"
971 [(set_attr "type" "imul3")])
973 (define_insn "*macchwuc"
974 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
975 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
976 (match_operand:SI 2 "gpc_reg_operand" "r")
977 (const_int 16))
978 (zero_extend:SI
979 (match_operand:HI 1 "gpc_reg_operand" "r")))
980 (match_operand:SI 4 "gpc_reg_operand" "0"))
981 (const_int 0)))
982 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
983 (plus:SI (mult:SI (lshiftrt:SI
984 (match_dup 2)
985 (const_int 16))
986 (zero_extend:SI
987 (match_dup 1)))
988 (match_dup 4)))]
989 "TARGET_MULHW"
990 "macchwu. %0, %1, %2"
991 [(set_attr "type" "imul3")])
993 (define_insn "*macchwu"
994 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
995 (plus:SI (mult:SI (lshiftrt:SI
996 (match_operand:SI 2 "gpc_reg_operand" "r")
997 (const_int 16))
998 (zero_extend:SI
999 (match_operand:HI 1 "gpc_reg_operand" "r")))
1000 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1001 "TARGET_MULHW"
1002 "macchwu %0, %1, %2"
1003 [(set_attr "type" "imul3")])
1005 (define_insn "*machhwc"
1006 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1007 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1008 (match_operand:SI 1 "gpc_reg_operand" "%r")
1009 (const_int 16))
1010 (ashiftrt:SI
1011 (match_operand:SI 2 "gpc_reg_operand" "r")
1012 (const_int 16)))
1013 (match_operand:SI 4 "gpc_reg_operand" "0"))
1014 (const_int 0)))
1015 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1016 (plus:SI (mult:SI (ashiftrt:SI
1017 (match_dup 1)
1018 (const_int 16))
1019 (ashiftrt:SI
1020 (match_dup 2)
1021 (const_int 16)))
1022 (match_dup 4)))]
1023 "TARGET_MULHW"
1024 "machhw. %0, %1, %2"
1025 [(set_attr "type" "imul3")])
1027 (define_insn "*machhw"
1028 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1029 (plus:SI (mult:SI (ashiftrt:SI
1030 (match_operand:SI 1 "gpc_reg_operand" "%r")
1031 (const_int 16))
1032 (ashiftrt:SI
1033 (match_operand:SI 2 "gpc_reg_operand" "r")
1034 (const_int 16)))
1035 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1036 "TARGET_MULHW"
1037 "machhw %0, %1, %2"
1038 [(set_attr "type" "imul3")])
1040 (define_insn "*machhwuc"
1041 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1042 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1043 (match_operand:SI 1 "gpc_reg_operand" "%r")
1044 (const_int 16))
1045 (lshiftrt:SI
1046 (match_operand:SI 2 "gpc_reg_operand" "r")
1047 (const_int 16)))
1048 (match_operand:SI 4 "gpc_reg_operand" "0"))
1049 (const_int 0)))
1050 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1051 (plus:SI (mult:SI (lshiftrt:SI
1052 (match_dup 1)
1053 (const_int 16))
1054 (lshiftrt:SI
1055 (match_dup 2)
1056 (const_int 16)))
1057 (match_dup 4)))]
1058 "TARGET_MULHW"
1059 "machhwu. %0, %1, %2"
1060 [(set_attr "type" "imul3")])
1062 (define_insn "*machhwu"
1063 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1064 (plus:SI (mult:SI (lshiftrt:SI
1065 (match_operand:SI 1 "gpc_reg_operand" "%r")
1066 (const_int 16))
1067 (lshiftrt:SI
1068 (match_operand:SI 2 "gpc_reg_operand" "r")
1069 (const_int 16)))
1070 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1071 "TARGET_MULHW"
1072 "machhwu %0, %1, %2"
1073 [(set_attr "type" "imul3")])
1075 (define_insn "*maclhwc"
1076 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1077 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1078 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1079 (sign_extend:SI
1080 (match_operand:HI 2 "gpc_reg_operand" "r")))
1081 (match_operand:SI 4 "gpc_reg_operand" "0"))
1082 (const_int 0)))
1083 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1084 (plus:SI (mult:SI (sign_extend:SI
1085 (match_dup 1))
1086 (sign_extend:SI
1087 (match_dup 2)))
1088 (match_dup 4)))]
1089 "TARGET_MULHW"
1090 "maclhw. %0, %1, %2"
1091 [(set_attr "type" "imul3")])
1093 (define_insn "*maclhw"
1094 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1095 (plus:SI (mult:SI (sign_extend:SI
1096 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1097 (sign_extend:SI
1098 (match_operand:HI 2 "gpc_reg_operand" "r")))
1099 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1100 "TARGET_MULHW"
1101 "maclhw %0, %1, %2"
1102 [(set_attr "type" "imul3")])
1104 (define_insn "*maclhwuc"
1105 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1106 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1107 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1108 (zero_extend:SI
1109 (match_operand:HI 2 "gpc_reg_operand" "r")))
1110 (match_operand:SI 4 "gpc_reg_operand" "0"))
1111 (const_int 0)))
1112 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1113 (plus:SI (mult:SI (zero_extend:SI
1114 (match_dup 1))
1115 (zero_extend:SI
1116 (match_dup 2)))
1117 (match_dup 4)))]
1118 "TARGET_MULHW"
1119 "maclhwu. %0, %1, %2"
1120 [(set_attr "type" "imul3")])
1122 (define_insn "*maclhwu"
1123 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1124 (plus:SI (mult:SI (zero_extend:SI
1125 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1126 (zero_extend:SI
1127 (match_operand:HI 2 "gpc_reg_operand" "r")))
1128 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1129 "TARGET_MULHW"
1130 "maclhwu %0, %1, %2"
1131 [(set_attr "type" "imul3")])
1133 (define_insn "*nmacchwc"
1134 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1135 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1136 (mult:SI (ashiftrt:SI
1137 (match_operand:SI 2 "gpc_reg_operand" "r")
1138 (const_int 16))
1139 (sign_extend:SI
1140 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1141 (const_int 0)))
1142 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1143 (minus:SI (match_dup 4)
1144 (mult:SI (ashiftrt:SI
1145 (match_dup 2)
1146 (const_int 16))
1147 (sign_extend:SI
1148 (match_dup 1)))))]
1149 "TARGET_MULHW"
1150 "nmacchw. %0, %1, %2"
1151 [(set_attr "type" "imul3")])
1153 (define_insn "*nmacchw"
1154 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1155 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1156 (mult:SI (ashiftrt:SI
1157 (match_operand:SI 2 "gpc_reg_operand" "r")
1158 (const_int 16))
1159 (sign_extend:SI
1160 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1161 "TARGET_MULHW"
1162 "nmacchw %0, %1, %2"
1163 [(set_attr "type" "imul3")])
1165 (define_insn "*nmachhwc"
1166 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1167 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1168 (mult:SI (ashiftrt:SI
1169 (match_operand:SI 1 "gpc_reg_operand" "%r")
1170 (const_int 16))
1171 (ashiftrt:SI
1172 (match_operand:SI 2 "gpc_reg_operand" "r")
1173 (const_int 16))))
1174 (const_int 0)))
1175 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1176 (minus:SI (match_dup 4)
1177 (mult:SI (ashiftrt:SI
1178 (match_dup 1)
1179 (const_int 16))
1180 (ashiftrt:SI
1181 (match_dup 2)
1182 (const_int 16)))))]
1183 "TARGET_MULHW"
1184 "nmachhw. %0, %1, %2"
1185 [(set_attr "type" "imul3")])
1187 (define_insn "*nmachhw"
1188 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1189 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1190 (mult:SI (ashiftrt:SI
1191 (match_operand:SI 1 "gpc_reg_operand" "%r")
1192 (const_int 16))
1193 (ashiftrt:SI
1194 (match_operand:SI 2 "gpc_reg_operand" "r")
1195 (const_int 16)))))]
1196 "TARGET_MULHW"
1197 "nmachhw %0, %1, %2"
1198 [(set_attr "type" "imul3")])
1200 (define_insn "*nmaclhwc"
1201 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1202 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1203 (mult:SI (sign_extend:SI
1204 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1205 (sign_extend:SI
1206 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1207 (const_int 0)))
1208 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1209 (minus:SI (match_dup 4)
1210 (mult:SI (sign_extend:SI
1211 (match_dup 1))
1212 (sign_extend:SI
1213 (match_dup 2)))))]
1214 "TARGET_MULHW"
1215 "nmaclhw. %0, %1, %2"
1216 [(set_attr "type" "imul3")])
1218 (define_insn "*nmaclhw"
1219 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1220 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1221 (mult:SI (sign_extend:SI
1222 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1223 (sign_extend:SI
1224 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1225 "TARGET_MULHW"
1226 "nmaclhw %0, %1, %2"
1227 [(set_attr "type" "imul3")])
1229 (define_insn "*mulchwc"
1230 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1231 (compare:CC (mult:SI (ashiftrt:SI
1232 (match_operand:SI 2 "gpc_reg_operand" "r")
1233 (const_int 16))
1234 (sign_extend:SI
1235 (match_operand:HI 1 "gpc_reg_operand" "r")))
1236 (const_int 0)))
1237 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1238 (mult:SI (ashiftrt:SI
1239 (match_dup 2)
1240 (const_int 16))
1241 (sign_extend:SI
1242 (match_dup 1))))]
1243 "TARGET_MULHW"
1244 "mulchw. %0, %1, %2"
1245 [(set_attr "type" "imul3")])
1247 (define_insn "*mulchw"
1248 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1249 (mult:SI (ashiftrt:SI
1250 (match_operand:SI 2 "gpc_reg_operand" "r")
1251 (const_int 16))
1252 (sign_extend:SI
1253 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1254 "TARGET_MULHW"
1255 "mulchw %0, %1, %2"
1256 [(set_attr "type" "imul3")])
1258 (define_insn "*mulchwuc"
1259 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1260 (compare:CC (mult:SI (lshiftrt:SI
1261 (match_operand:SI 2 "gpc_reg_operand" "r")
1262 (const_int 16))
1263 (zero_extend:SI
1264 (match_operand:HI 1 "gpc_reg_operand" "r")))
1265 (const_int 0)))
1266 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1267 (mult:SI (lshiftrt:SI
1268 (match_dup 2)
1269 (const_int 16))
1270 (zero_extend:SI
1271 (match_dup 1))))]
1272 "TARGET_MULHW"
1273 "mulchwu. %0, %1, %2"
1274 [(set_attr "type" "imul3")])
1276 (define_insn "*mulchwu"
1277 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1278 (mult:SI (lshiftrt:SI
1279 (match_operand:SI 2 "gpc_reg_operand" "r")
1280 (const_int 16))
1281 (zero_extend:SI
1282 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1283 "TARGET_MULHW"
1284 "mulchwu %0, %1, %2"
1285 [(set_attr "type" "imul3")])
1287 (define_insn "*mulhhwc"
1288 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1289 (compare:CC (mult:SI (ashiftrt:SI
1290 (match_operand:SI 1 "gpc_reg_operand" "%r")
1291 (const_int 16))
1292 (ashiftrt:SI
1293 (match_operand:SI 2 "gpc_reg_operand" "r")
1294 (const_int 16)))
1295 (const_int 0)))
1296 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1297 (mult:SI (ashiftrt:SI
1298 (match_dup 1)
1299 (const_int 16))
1300 (ashiftrt:SI
1301 (match_dup 2)
1302 (const_int 16))))]
1303 "TARGET_MULHW"
1304 "mulhhw. %0, %1, %2"
1305 [(set_attr "type" "imul3")])
1307 (define_insn "*mulhhw"
1308 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1309 (mult:SI (ashiftrt:SI
1310 (match_operand:SI 1 "gpc_reg_operand" "%r")
1311 (const_int 16))
1312 (ashiftrt:SI
1313 (match_operand:SI 2 "gpc_reg_operand" "r")
1314 (const_int 16))))]
1315 "TARGET_MULHW"
1316 "mulhhw %0, %1, %2"
1317 [(set_attr "type" "imul3")])
1319 (define_insn "*mulhhwuc"
1320 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1321 (compare:CC (mult:SI (lshiftrt:SI
1322 (match_operand:SI 1 "gpc_reg_operand" "%r")
1323 (const_int 16))
1324 (lshiftrt:SI
1325 (match_operand:SI 2 "gpc_reg_operand" "r")
1326 (const_int 16)))
1327 (const_int 0)))
1328 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1329 (mult:SI (lshiftrt:SI
1330 (match_dup 1)
1331 (const_int 16))
1332 (lshiftrt:SI
1333 (match_dup 2)
1334 (const_int 16))))]
1335 "TARGET_MULHW"
1336 "mulhhwu. %0, %1, %2"
1337 [(set_attr "type" "imul3")])
1339 (define_insn "*mulhhwu"
1340 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1341 (mult:SI (lshiftrt:SI
1342 (match_operand:SI 1 "gpc_reg_operand" "%r")
1343 (const_int 16))
1344 (lshiftrt:SI
1345 (match_operand:SI 2 "gpc_reg_operand" "r")
1346 (const_int 16))))]
1347 "TARGET_MULHW"
1348 "mulhhwu %0, %1, %2"
1349 [(set_attr "type" "imul3")])
1351 (define_insn "*mullhwc"
1352 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1353 (compare:CC (mult:SI (sign_extend:SI
1354 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1355 (sign_extend:SI
1356 (match_operand:HI 2 "gpc_reg_operand" "r")))
1357 (const_int 0)))
1358 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1359 (mult:SI (sign_extend:SI
1360 (match_dup 1))
1361 (sign_extend:SI
1362 (match_dup 2))))]
1363 "TARGET_MULHW"
1364 "mullhw. %0, %1, %2"
1365 [(set_attr "type" "imul3")])
1367 (define_insn "*mullhw"
1368 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1369 (mult:SI (sign_extend:SI
1370 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1371 (sign_extend:SI
1372 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1373 "TARGET_MULHW"
1374 "mullhw %0, %1, %2"
1375 [(set_attr "type" "imul3")])
1377 (define_insn "*mullhwuc"
1378 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1379 (compare:CC (mult:SI (zero_extend:SI
1380 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1381 (zero_extend:SI
1382 (match_operand:HI 2 "gpc_reg_operand" "r")))
1383 (const_int 0)))
1384 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1385 (mult:SI (zero_extend:SI
1386 (match_dup 1))
1387 (zero_extend:SI
1388 (match_dup 2))))]
1389 "TARGET_MULHW"
1390 "mullhwu. %0, %1, %2"
1391 [(set_attr "type" "imul3")])
1393 (define_insn "*mullhwu"
1394 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1395 (mult:SI (zero_extend:SI
1396 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1397 (zero_extend:SI
1398 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1399 "TARGET_MULHW"
1400 "mullhwu %0, %1, %2"
1401 [(set_attr "type" "imul3")])
1402 \f
1403 ;; IBM 405 and 440 string-search dlmzb instruction support.
1404 (define_insn "dlmzb"
1405 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1406 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1407 (match_operand:SI 2 "gpc_reg_operand" "r")]
1408 UNSPEC_DLMZB_CR))
1409 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1410 (unspec:SI [(match_dup 1)
1411 (match_dup 2)]
1412 UNSPEC_DLMZB))]
1413 "TARGET_DLMZB"
1414 "dlmzb. %0, %1, %2")
1416 (define_expand "strlensi"
1417 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1418 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1419 (match_operand:QI 2 "const_int_operand" "")
1420 (match_operand 3 "const_int_operand" "")]
1421 UNSPEC_DLMZB_STRLEN))
1422 (clobber (match_scratch:CC 4 "=x"))]
1423 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1424 {
1425 rtx result = operands[0];
1426 rtx src = operands[1];
1427 rtx search_char = operands[2];
1428 rtx align = operands[3];
1429 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1430 rtx loop_label, end_label, mem, cr0, cond;
1431 if (search_char != const0_rtx
1432 || GET_CODE (align) != CONST_INT
1433 || INTVAL (align) < 8)
1434 FAIL;
1435 word1 = gen_reg_rtx (SImode);
1436 word2 = gen_reg_rtx (SImode);
1437 scratch_dlmzb = gen_reg_rtx (SImode);
1438 scratch_string = gen_reg_rtx (Pmode);
1439 loop_label = gen_label_rtx ();
1440 end_label = gen_label_rtx ();
1441 addr = force_reg (Pmode, XEXP (src, 0));
1442 emit_move_insn (scratch_string, addr);
1443 emit_label (loop_label);
1444 mem = change_address (src, SImode, scratch_string);
1445 emit_move_insn (word1, mem);
1446 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1447 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1448 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1449 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1450 emit_jump_insn (gen_rtx_SET (VOIDmode,
1451 pc_rtx,
1452 gen_rtx_IF_THEN_ELSE (VOIDmode,
1453 cond,
1454 gen_rtx_LABEL_REF
1455 (VOIDmode,
1456 end_label),
1457 pc_rtx)));
1458 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1459 emit_jump_insn (gen_rtx_SET (VOIDmode,
1460 pc_rtx,
1461 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1462 emit_barrier ();
1463 emit_label (end_label);
1464 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1465 emit_insn (gen_subsi3 (result, scratch_string, addr));
1466 emit_insn (gen_subsi3 (result, result, const1_rtx));
1467 DONE;
1468 })
1469 \f
1470 (define_split
1471 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1472 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1473 (const_int 0)))
1474 (set (match_operand:SI 0 "gpc_reg_operand" "")
1475 (sign_extend:SI (match_dup 1)))]
1476 "reload_completed"
1477 [(set (match_dup 0)
1478 (sign_extend:SI (match_dup 1)))
1479 (set (match_dup 2)
1480 (compare:CC (match_dup 0)
1481 (const_int 0)))]
1482 "")
1484 ;; Fixed-point arithmetic insns.
1486 (define_expand "add<mode>3"
1487 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1488 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1489 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1490 ""
1491 {
1492 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1493 {
1494 if (non_short_cint_operand (operands[2], DImode))
1495 FAIL;
1496 }
1497 else if (GET_CODE (operands[2]) == CONST_INT
1498 && ! add_operand (operands[2], <MODE>mode))
1499 {
1500 rtx tmp = ((!can_create_pseudo_p ()
1501 || rtx_equal_p (operands[0], operands[1]))
1502 ? operands[0] : gen_reg_rtx (<MODE>mode));
1504 HOST_WIDE_INT val = INTVAL (operands[2]);
1505 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1506 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1508 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1509 FAIL;
1511 /* The ordering here is important for the prolog expander.
1512 When space is allocated from the stack, adding 'low' first may
1513 produce a temporary deallocation (which would be bad). */
1514 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1515 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1516 DONE;
1517 }
1518 })
1520 ;; Discourage ai/addic because of carry but provide it in an alternative
1521 ;; allowing register zero as source.
1522 (define_insn "*add<mode>3_internal1"
1523 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1524 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1525 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1526 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1527 "@
1528 {cax|add} %0,%1,%2
1529 {cal %0,%2(%1)|addi %0,%1,%2}
1530 {ai|addic} %0,%1,%2
1531 {cau|addis} %0,%1,%v2"
1532 [(set_attr "length" "4,4,4,4")])
1534 (define_insn "addsi3_high"
1535 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1536 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1537 (high:SI (match_operand 2 "" ""))))]
1538 "TARGET_MACHO && !TARGET_64BIT"
1539 "{cau|addis} %0,%1,ha16(%2)"
1540 [(set_attr "length" "4")])
1542 (define_insn "*add<mode>3_internal2"
1543 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1544 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1545 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1546 (const_int 0)))
1547 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1548 ""
1549 "@
1550 {cax.|add.} %3,%1,%2
1551 {ai.|addic.} %3,%1,%2
1552 #
1553 #"
1554 [(set_attr "type" "fast_compare,compare,compare,compare")
1555 (set_attr "length" "4,4,8,8")])
1557 (define_split
1558 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1559 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1560 (match_operand:GPR 2 "reg_or_short_operand" ""))
1561 (const_int 0)))
1562 (clobber (match_scratch:GPR 3 ""))]
1563 "reload_completed"
1564 [(set (match_dup 3)
1565 (plus:GPR (match_dup 1)
1566 (match_dup 2)))
1567 (set (match_dup 0)
1568 (compare:CC (match_dup 3)
1569 (const_int 0)))]
1570 "")
1572 (define_insn "*add<mode>3_internal3"
1573 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1574 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1575 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1576 (const_int 0)))
1577 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1578 (plus:P (match_dup 1)
1579 (match_dup 2)))]
1580 ""
1581 "@
1582 {cax.|add.} %0,%1,%2
1583 {ai.|addic.} %0,%1,%2
1584 #
1585 #"
1586 [(set_attr "type" "fast_compare,compare,compare,compare")
1587 (set_attr "length" "4,4,8,8")])
1589 (define_split
1590 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1591 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1592 (match_operand:P 2 "reg_or_short_operand" ""))
1593 (const_int 0)))
1594 (set (match_operand:P 0 "gpc_reg_operand" "")
1595 (plus:P (match_dup 1) (match_dup 2)))]
1596 "reload_completed"
1597 [(set (match_dup 0)
1598 (plus:P (match_dup 1)
1599 (match_dup 2)))
1600 (set (match_dup 3)
1601 (compare:CC (match_dup 0)
1602 (const_int 0)))]
1603 "")
1605 ;; Split an add that we can't do in one insn into two insns, each of which
1606 ;; does one 16-bit part. This is used by combine. Note that the low-order
1607 ;; add should be last in case the result gets used in an address.
1609 (define_split
1610 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1611 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1612 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1613 ""
1614 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1615 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1616 {
1617 HOST_WIDE_INT val = INTVAL (operands[2]);
1618 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1619 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1621 operands[4] = GEN_INT (low);
1622 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1623 operands[3] = GEN_INT (rest);
1624 else if (can_create_pseudo_p ())
1625 {
1626 operands[3] = gen_reg_rtx (DImode);
1627 emit_move_insn (operands[3], operands[2]);
1628 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1629 DONE;
1630 }
1631 else
1632 FAIL;
1633 })
1635 (define_insn "one_cmpl<mode>2"
1636 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1637 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1638 ""
1639 "nor %0,%1,%1")
1641 (define_insn ""
1642 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1643 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1644 (const_int 0)))
1645 (clobber (match_scratch:P 2 "=r,r"))]
1646 ""
1647 "@
1648 nor. %2,%1,%1
1649 #"
1650 [(set_attr "type" "compare")
1651 (set_attr "length" "4,8")])
1653 (define_split
1654 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1655 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1656 (const_int 0)))
1657 (clobber (match_scratch:P 2 ""))]
1658 "reload_completed"
1659 [(set (match_dup 2)
1660 (not:P (match_dup 1)))
1661 (set (match_dup 0)
1662 (compare:CC (match_dup 2)
1663 (const_int 0)))]
1664 "")
1666 (define_insn ""
1667 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1668 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1669 (const_int 0)))
1670 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1671 (not:P (match_dup 1)))]
1672 ""
1673 "@
1674 nor. %0,%1,%1
1675 #"
1676 [(set_attr "type" "compare")
1677 (set_attr "length" "4,8")])
1679 (define_split
1680 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1681 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1682 (const_int 0)))
1683 (set (match_operand:P 0 "gpc_reg_operand" "")
1684 (not:P (match_dup 1)))]
1685 "reload_completed"
1686 [(set (match_dup 0)
1687 (not:P (match_dup 1)))
1688 (set (match_dup 2)
1689 (compare:CC (match_dup 0)
1690 (const_int 0)))]
1691 "")
1693 (define_insn ""
1694 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1695 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1696 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1697 "! TARGET_POWERPC"
1698 "{sf%I1|subf%I1c} %0,%2,%1")
1700 (define_insn ""
1701 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1702 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1703 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1704 "TARGET_POWERPC"
1705 "@
1706 subf %0,%2,%1
1707 subfic %0,%2,%1")
1709 (define_insn ""
1710 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1711 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1712 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1713 (const_int 0)))
1714 (clobber (match_scratch:SI 3 "=r,r"))]
1715 "! TARGET_POWERPC"
1716 "@
1717 {sf.|subfc.} %3,%2,%1
1718 #"
1719 [(set_attr "type" "compare")
1720 (set_attr "length" "4,8")])
1722 (define_insn ""
1723 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1724 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1725 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1726 (const_int 0)))
1727 (clobber (match_scratch:P 3 "=r,r"))]
1728 "TARGET_POWERPC"
1729 "@
1730 subf. %3,%2,%1
1731 #"
1732 [(set_attr "type" "fast_compare")
1733 (set_attr "length" "4,8")])
1735 (define_split
1736 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1737 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1738 (match_operand:P 2 "gpc_reg_operand" ""))
1739 (const_int 0)))
1740 (clobber (match_scratch:P 3 ""))]
1741 "reload_completed"
1742 [(set (match_dup 3)
1743 (minus:P (match_dup 1)
1744 (match_dup 2)))
1745 (set (match_dup 0)
1746 (compare:CC (match_dup 3)
1747 (const_int 0)))]
1748 "")
1750 (define_insn ""
1751 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1752 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1753 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1754 (const_int 0)))
1755 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1756 (minus:SI (match_dup 1) (match_dup 2)))]
1757 "! TARGET_POWERPC"
1758 "@
1759 {sf.|subfc.} %0,%2,%1
1760 #"
1761 [(set_attr "type" "compare")
1762 (set_attr "length" "4,8")])
1764 (define_insn ""
1765 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1766 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1767 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1768 (const_int 0)))
1769 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1770 (minus:P (match_dup 1)
1771 (match_dup 2)))]
1772 "TARGET_POWERPC"
1773 "@
1774 subf. %0,%2,%1
1775 #"
1776 [(set_attr "type" "fast_compare")
1777 (set_attr "length" "4,8")])
1779 (define_split
1780 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1781 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1782 (match_operand:P 2 "gpc_reg_operand" ""))
1783 (const_int 0)))
1784 (set (match_operand:P 0 "gpc_reg_operand" "")
1785 (minus:P (match_dup 1)
1786 (match_dup 2)))]
1787 "reload_completed"
1788 [(set (match_dup 0)
1789 (minus:P (match_dup 1)
1790 (match_dup 2)))
1791 (set (match_dup 3)
1792 (compare:CC (match_dup 0)
1793 (const_int 0)))]
1794 "")
1796 (define_expand "sub<mode>3"
1797 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1798 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1799 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1800 ""
1801 "
1802 {
1803 if (GET_CODE (operands[2]) == CONST_INT)
1804 {
1805 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1806 negate_rtx (<MODE>mode, operands[2])));
1807 DONE;
1808 }
1809 }")
1811 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1812 ;; instruction and some auxiliary computations. Then we just have a single
1813 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1814 ;; combine.
1816 (define_expand "sminsi3"
1817 [(set (match_dup 3)
1818 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1819 (match_operand:SI 2 "reg_or_short_operand" ""))
1820 (const_int 0)
1821 (minus:SI (match_dup 2) (match_dup 1))))
1822 (set (match_operand:SI 0 "gpc_reg_operand" "")
1823 (minus:SI (match_dup 2) (match_dup 3)))]
1824 "TARGET_POWER || TARGET_ISEL"
1825 "
1826 {
1827 if (TARGET_ISEL)
1828 {
1829 operands[2] = force_reg (SImode, operands[2]);
1830 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1831 DONE;
1832 }
1834 operands[3] = gen_reg_rtx (SImode);
1835 }")
1837 (define_split
1838 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1839 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1840 (match_operand:SI 2 "reg_or_short_operand" "")))
1841 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1842 "TARGET_POWER"
1843 [(set (match_dup 3)
1844 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1845 (const_int 0)
1846 (minus:SI (match_dup 2) (match_dup 1))))
1847 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1848 "")
1850 (define_expand "smaxsi3"
1851 [(set (match_dup 3)
1852 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1853 (match_operand:SI 2 "reg_or_short_operand" ""))
1854 (const_int 0)
1855 (minus:SI (match_dup 2) (match_dup 1))))
1856 (set (match_operand:SI 0 "gpc_reg_operand" "")
1857 (plus:SI (match_dup 3) (match_dup 1)))]
1858 "TARGET_POWER || TARGET_ISEL"
1859 "
1860 {
1861 if (TARGET_ISEL)
1862 {
1863 operands[2] = force_reg (SImode, operands[2]);
1864 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1865 DONE;
1866 }
1867 operands[3] = gen_reg_rtx (SImode);
1868 }")
1870 (define_split
1871 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1872 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1873 (match_operand:SI 2 "reg_or_short_operand" "")))
1874 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1875 "TARGET_POWER"
1876 [(set (match_dup 3)
1877 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1878 (const_int 0)
1879 (minus:SI (match_dup 2) (match_dup 1))))
1880 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1881 "")
1883 (define_expand "uminsi3"
1884 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1885 (match_dup 5)))
1886 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1887 (match_dup 5)))
1888 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1889 (const_int 0)
1890 (minus:SI (match_dup 4) (match_dup 3))))
1891 (set (match_operand:SI 0 "gpc_reg_operand" "")
1892 (minus:SI (match_dup 2) (match_dup 3)))]
1893 "TARGET_POWER || TARGET_ISEL"
1894 "
1895 {
1896 if (TARGET_ISEL)
1897 {
1898 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1899 DONE;
1900 }
1901 operands[3] = gen_reg_rtx (SImode);
1902 operands[4] = gen_reg_rtx (SImode);
1903 operands[5] = GEN_INT (-2147483647 - 1);
1904 }")
1906 (define_expand "umaxsi3"
1907 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1908 (match_dup 5)))
1909 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1910 (match_dup 5)))
1911 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1912 (const_int 0)
1913 (minus:SI (match_dup 4) (match_dup 3))))
1914 (set (match_operand:SI 0 "gpc_reg_operand" "")
1915 (plus:SI (match_dup 3) (match_dup 1)))]
1916 "TARGET_POWER || TARGET_ISEL"
1917 "
1918 {
1919 if (TARGET_ISEL)
1920 {
1921 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1922 DONE;
1923 }
1924 operands[3] = gen_reg_rtx (SImode);
1925 operands[4] = gen_reg_rtx (SImode);
1926 operands[5] = GEN_INT (-2147483647 - 1);
1927 }")
1929 (define_insn ""
1930 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1931 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1932 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1933 (const_int 0)
1934 (minus:SI (match_dup 2) (match_dup 1))))]
1935 "TARGET_POWER"
1936 "doz%I2 %0,%1,%2")
1938 (define_insn ""
1939 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1940 (compare:CC
1941 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1942 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1943 (const_int 0)
1944 (minus:SI (match_dup 2) (match_dup 1)))
1945 (const_int 0)))
1946 (clobber (match_scratch:SI 3 "=r,r"))]
1947 "TARGET_POWER"
1948 "@
1949 doz%I2. %3,%1,%2
1950 #"
1951 [(set_attr "type" "delayed_compare")
1952 (set_attr "length" "4,8")])
1954 (define_split
1955 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1956 (compare:CC
1957 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1958 (match_operand:SI 2 "reg_or_short_operand" ""))
1959 (const_int 0)
1960 (minus:SI (match_dup 2) (match_dup 1)))
1961 (const_int 0)))
1962 (clobber (match_scratch:SI 3 ""))]
1963 "TARGET_POWER && reload_completed"
1964 [(set (match_dup 3)
1965 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1966 (const_int 0)
1967 (minus:SI (match_dup 2) (match_dup 1))))
1968 (set (match_dup 0)
1969 (compare:CC (match_dup 3)
1970 (const_int 0)))]
1971 "")
1973 (define_insn ""
1974 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1975 (compare:CC
1976 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1977 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1978 (const_int 0)
1979 (minus:SI (match_dup 2) (match_dup 1)))
1980 (const_int 0)))
1981 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1982 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1983 (const_int 0)
1984 (minus:SI (match_dup 2) (match_dup 1))))]
1985 "TARGET_POWER"
1986 "@
1987 doz%I2. %0,%1,%2
1988 #"
1989 [(set_attr "type" "delayed_compare")
1990 (set_attr "length" "4,8")])
1992 (define_split
1993 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1994 (compare:CC
1995 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1996 (match_operand:SI 2 "reg_or_short_operand" ""))
1997 (const_int 0)
1998 (minus:SI (match_dup 2) (match_dup 1)))
1999 (const_int 0)))
2000 (set (match_operand:SI 0 "gpc_reg_operand" "")
2001 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2002 (const_int 0)
2003 (minus:SI (match_dup 2) (match_dup 1))))]
2004 "TARGET_POWER && reload_completed"
2005 [(set (match_dup 0)
2006 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2007 (const_int 0)
2008 (minus:SI (match_dup 2) (match_dup 1))))
2009 (set (match_dup 3)
2010 (compare:CC (match_dup 0)
2011 (const_int 0)))]
2012 "")
2014 ;; We don't need abs with condition code because such comparisons should
2015 ;; never be done.
2016 (define_expand "abssi2"
2017 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2018 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2019 ""
2020 "
2021 {
2022 if (TARGET_ISEL)
2023 {
2024 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2025 DONE;
2026 }
2027 else if (! TARGET_POWER)
2028 {
2029 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2030 DONE;
2031 }
2032 }")
2034 (define_insn "*abssi2_power"
2035 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2036 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2037 "TARGET_POWER"
2038 "abs %0,%1")
2040 (define_insn_and_split "abssi2_isel"
2041 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2042 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
2043 (clobber (match_scratch:SI 2 "=&b"))
2044 (clobber (match_scratch:CC 3 "=y"))]
2045 "TARGET_ISEL"
2046 "#"
2047 "&& reload_completed"
2048 [(set (match_dup 2) (neg:SI (match_dup 1)))
2049 (set (match_dup 3)
2050 (compare:CC (match_dup 1)
2051 (const_int 0)))
2052 (set (match_dup 0)
2053 (if_then_else:SI (ge (match_dup 3)
2054 (const_int 0))
2055 (match_dup 1)
2056 (match_dup 2)))]
2057 "")
2059 (define_insn_and_split "abssi2_nopower"
2060 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2061 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2062 (clobber (match_scratch:SI 2 "=&r,&r"))]
2063 "! TARGET_POWER && ! TARGET_ISEL"
2064 "#"
2065 "&& reload_completed"
2066 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2067 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2068 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2069 "")
2071 (define_insn "*nabs_power"
2072 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2073 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2074 "TARGET_POWER"
2075 "nabs %0,%1")
2077 (define_insn_and_split "*nabs_nopower"
2078 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2079 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2080 (clobber (match_scratch:SI 2 "=&r,&r"))]
2081 "! TARGET_POWER"
2082 "#"
2083 "&& reload_completed"
2084 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2085 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2086 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2087 "")
2089 (define_expand "neg<mode>2"
2090 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2091 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2092 ""
2093 "")
2095 (define_insn "*neg<mode>2_internal"
2096 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2097 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2098 ""
2099 "neg %0,%1")
2101 (define_insn ""
2102 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2103 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2104 (const_int 0)))
2105 (clobber (match_scratch:P 2 "=r,r"))]
2106 ""
2107 "@
2108 neg. %2,%1
2109 #"
2110 [(set_attr "type" "fast_compare")
2111 (set_attr "length" "4,8")])
2113 (define_split
2114 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2115 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2116 (const_int 0)))
2117 (clobber (match_scratch:P 2 ""))]
2118 "reload_completed"
2119 [(set (match_dup 2)
2120 (neg:P (match_dup 1)))
2121 (set (match_dup 0)
2122 (compare:CC (match_dup 2)
2123 (const_int 0)))]
2124 "")
2126 (define_insn ""
2127 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2128 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2129 (const_int 0)))
2130 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2131 (neg:P (match_dup 1)))]
2132 ""
2133 "@
2134 neg. %0,%1
2135 #"
2136 [(set_attr "type" "fast_compare")
2137 (set_attr "length" "4,8")])
2139 (define_split
2140 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2141 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2142 (const_int 0)))
2143 (set (match_operand:P 0 "gpc_reg_operand" "")
2144 (neg:P (match_dup 1)))]
2145 "reload_completed"
2146 [(set (match_dup 0)
2147 (neg:P (match_dup 1)))
2148 (set (match_dup 2)
2149 (compare:CC (match_dup 0)
2150 (const_int 0)))]
2151 "")
2153 (define_insn "clz<mode>2"
2154 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2155 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2156 ""
2157 "{cntlz|cntlz<wd>} %0,%1"
2158 [(set_attr "type" "cntlz")])
2160 (define_expand "ctz<mode>2"
2161 [(set (match_dup 2)
2162 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2163 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2164 (match_dup 2)))
2165 (clobber (scratch:CC))])
2166 (set (match_dup 4) (clz:GPR (match_dup 3)))
2167 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2168 (minus:GPR (match_dup 5) (match_dup 4)))]
2169 ""
2170 {
2171 operands[2] = gen_reg_rtx (<MODE>mode);
2172 operands[3] = gen_reg_rtx (<MODE>mode);
2173 operands[4] = gen_reg_rtx (<MODE>mode);
2174 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2175 })
2177 (define_expand "ffs<mode>2"
2178 [(set (match_dup 2)
2179 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2180 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2181 (match_dup 2)))
2182 (clobber (scratch:CC))])
2183 (set (match_dup 4) (clz:GPR (match_dup 3)))
2184 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2185 (minus:GPR (match_dup 5) (match_dup 4)))]
2186 ""
2187 {
2188 operands[2] = gen_reg_rtx (<MODE>mode);
2189 operands[3] = gen_reg_rtx (<MODE>mode);
2190 operands[4] = gen_reg_rtx (<MODE>mode);
2191 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2192 })
2194 (define_insn "popcntb<mode>2"
2195 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2196 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2197 UNSPEC_POPCNTB))]
2198 "TARGET_POPCNTB"
2199 "popcntb %0,%1")
2201 (define_expand "popcount<mode>2"
2202 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2203 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2204 "TARGET_POPCNTB"
2205 {
2206 rs6000_emit_popcount (operands[0], operands[1]);
2207 DONE;
2208 })
2210 (define_expand "parity<mode>2"
2211 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2212 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2213 "TARGET_POPCNTB"
2214 {
2215 rs6000_emit_parity (operands[0], operands[1]);
2216 DONE;
2217 })
2219 (define_insn "bswapsi2"
2220 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2221 (bswap:SI (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2222 ""
2223 "@
2224 {lbrx|lwbrx} %0,%y1
2225 {stbrx|stwbrx} %1,%y0
2226 #"
2227 [(set_attr "length" "4,4,12")])
2229 (define_split
2230 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2231 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2232 "reload_completed"
2233 [(set (match_dup 0)
2234 (rotate:SI (match_dup 1) (const_int 8)))
2235 (set (zero_extract:SI (match_dup 0)
2236 (const_int 8)
2237 (const_int 0))
2238 (match_dup 1))
2239 (set (zero_extract:SI (match_dup 0)
2240 (const_int 8)
2241 (const_int 16))
2242 (rotate:SI (match_dup 1)
2243 (const_int 16)))]
2244 "")
2246 (define_expand "mulsi3"
2247 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2248 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2249 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2250 ""
2251 "
2252 {
2253 if (TARGET_POWER)
2254 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2255 else
2256 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2257 DONE;
2258 }")
2260 (define_insn "mulsi3_mq"
2261 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2262 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2263 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2264 (clobber (match_scratch:SI 3 "=q,q"))]
2265 "TARGET_POWER"
2266 "@
2267 {muls|mullw} %0,%1,%2
2268 {muli|mulli} %0,%1,%2"
2269 [(set (attr "type")
2270 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2271 (const_string "imul3")
2272 (match_operand:SI 2 "short_cint_operand" "")
2273 (const_string "imul2")]
2274 (const_string "imul")))])
2276 (define_insn "mulsi3_no_mq"
2277 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2278 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2279 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2280 "! TARGET_POWER"
2281 "@
2282 {muls|mullw} %0,%1,%2
2283 {muli|mulli} %0,%1,%2"
2284 [(set (attr "type")
2285 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2286 (const_string "imul3")
2287 (match_operand:SI 2 "short_cint_operand" "")
2288 (const_string "imul2")]
2289 (const_string "imul")))])
2291 (define_insn "*mulsi3_mq_internal1"
2292 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2293 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2294 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2295 (const_int 0)))
2296 (clobber (match_scratch:SI 3 "=r,r"))
2297 (clobber (match_scratch:SI 4 "=q,q"))]
2298 "TARGET_POWER"
2299 "@
2300 {muls.|mullw.} %3,%1,%2
2301 #"
2302 [(set_attr "type" "imul_compare")
2303 (set_attr "length" "4,8")])
2305 (define_split
2306 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2307 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2308 (match_operand:SI 2 "gpc_reg_operand" ""))
2309 (const_int 0)))
2310 (clobber (match_scratch:SI 3 ""))
2311 (clobber (match_scratch:SI 4 ""))]
2312 "TARGET_POWER && reload_completed"
2313 [(parallel [(set (match_dup 3)
2314 (mult:SI (match_dup 1) (match_dup 2)))
2315 (clobber (match_dup 4))])
2316 (set (match_dup 0)
2317 (compare:CC (match_dup 3)
2318 (const_int 0)))]
2319 "")
2321 (define_insn "*mulsi3_no_mq_internal1"
2322 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2323 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2324 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2325 (const_int 0)))
2326 (clobber (match_scratch:SI 3 "=r,r"))]
2327 "! TARGET_POWER"
2328 "@
2329 {muls.|mullw.} %3,%1,%2
2330 #"
2331 [(set_attr "type" "imul_compare")
2332 (set_attr "length" "4,8")])
2334 (define_split
2335 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2336 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2337 (match_operand:SI 2 "gpc_reg_operand" ""))
2338 (const_int 0)))
2339 (clobber (match_scratch:SI 3 ""))]
2340 "! TARGET_POWER && reload_completed"
2341 [(set (match_dup 3)
2342 (mult:SI (match_dup 1) (match_dup 2)))
2343 (set (match_dup 0)
2344 (compare:CC (match_dup 3)
2345 (const_int 0)))]
2346 "")
2348 (define_insn "*mulsi3_mq_internal2"
2349 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2350 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2351 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2352 (const_int 0)))
2353 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2354 (mult:SI (match_dup 1) (match_dup 2)))
2355 (clobber (match_scratch:SI 4 "=q,q"))]
2356 "TARGET_POWER"
2357 "@
2358 {muls.|mullw.} %0,%1,%2
2359 #"
2360 [(set_attr "type" "imul_compare")
2361 (set_attr "length" "4,8")])
2363 (define_split
2364 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2365 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2366 (match_operand:SI 2 "gpc_reg_operand" ""))
2367 (const_int 0)))
2368 (set (match_operand:SI 0 "gpc_reg_operand" "")
2369 (mult:SI (match_dup 1) (match_dup 2)))
2370 (clobber (match_scratch:SI 4 ""))]
2371 "TARGET_POWER && reload_completed"
2372 [(parallel [(set (match_dup 0)
2373 (mult:SI (match_dup 1) (match_dup 2)))
2374 (clobber (match_dup 4))])
2375 (set (match_dup 3)
2376 (compare:CC (match_dup 0)
2377 (const_int 0)))]
2378 "")
2380 (define_insn "*mulsi3_no_mq_internal2"
2381 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2382 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2383 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2384 (const_int 0)))
2385 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2386 (mult:SI (match_dup 1) (match_dup 2)))]
2387 "! TARGET_POWER"
2388 "@
2389 {muls.|mullw.} %0,%1,%2
2390 #"
2391 [(set_attr "type" "imul_compare")
2392 (set_attr "length" "4,8")])
2394 (define_split
2395 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2396 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2397 (match_operand:SI 2 "gpc_reg_operand" ""))
2398 (const_int 0)))
2399 (set (match_operand:SI 0 "gpc_reg_operand" "")
2400 (mult:SI (match_dup 1) (match_dup 2)))]
2401 "! TARGET_POWER && reload_completed"
2402 [(set (match_dup 0)
2403 (mult:SI (match_dup 1) (match_dup 2)))
2404 (set (match_dup 3)
2405 (compare:CC (match_dup 0)
2406 (const_int 0)))]
2407 "")
2409 ;; Operand 1 is divided by operand 2; quotient goes to operand
2410 ;; 0 and remainder to operand 3.
2411 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2413 (define_expand "divmodsi4"
2414 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2415 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2416 (match_operand:SI 2 "gpc_reg_operand" "")))
2417 (set (match_operand:SI 3 "register_operand" "")
2418 (mod:SI (match_dup 1) (match_dup 2)))])]
2419 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2420 "
2421 {
2422 if (! TARGET_POWER && ! TARGET_POWERPC)
2423 {
2424 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2425 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2426 emit_insn (gen_divss_call ());
2427 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2428 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2429 DONE;
2430 }
2431 }")
2433 (define_insn "*divmodsi4_internal"
2434 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2435 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2436 (match_operand:SI 2 "gpc_reg_operand" "r")))
2437 (set (match_operand:SI 3 "register_operand" "=q")
2438 (mod:SI (match_dup 1) (match_dup 2)))]
2439 "TARGET_POWER"
2440 "divs %0,%1,%2"
2441 [(set_attr "type" "idiv")])
2443 (define_expand "udiv<mode>3"
2444 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2445 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2446 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2447 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2448 "
2449 {
2450 if (! TARGET_POWER && ! TARGET_POWERPC)
2451 {
2452 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2453 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2454 emit_insn (gen_quous_call ());
2455 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2456 DONE;
2457 }
2458 else if (TARGET_POWER)
2459 {
2460 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2461 DONE;
2462 }
2463 }")
2465 (define_insn "udivsi3_mq"
2466 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2467 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2468 (match_operand:SI 2 "gpc_reg_operand" "r")))
2469 (clobber (match_scratch:SI 3 "=q"))]
2470 "TARGET_POWERPC && TARGET_POWER"
2471 "divwu %0,%1,%2"
2472 [(set_attr "type" "idiv")])
2474 (define_insn "*udivsi3_no_mq"
2475 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2476 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2477 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2478 "TARGET_POWERPC && ! TARGET_POWER"
2479 "div<wd>u %0,%1,%2"
2480 [(set (attr "type")
2481 (cond [(match_operand:SI 0 "" "")
2482 (const_string "idiv")]
2483 (const_string "ldiv")))])
2486 ;; For powers of two we can do srai/aze for divide and then adjust for
2487 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2488 ;; used; for PowerPC, force operands into register and do a normal divide;
2489 ;; for AIX common-mode, use quoss call on register operands.
2490 (define_expand "div<mode>3"
2491 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2492 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2493 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2494 ""
2495 "
2496 {
2497 if (GET_CODE (operands[2]) == CONST_INT
2498 && INTVAL (operands[2]) > 0
2499 && exact_log2 (INTVAL (operands[2])) >= 0)
2500 ;
2501 else if (TARGET_POWERPC)
2502 {
2503 operands[2] = force_reg (<MODE>mode, operands[2]);
2504 if (TARGET_POWER)
2505 {
2506 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2507 DONE;
2508 }
2509 }
2510 else if (TARGET_POWER)
2511 FAIL;
2512 else
2513 {
2514 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2515 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2516 emit_insn (gen_quoss_call ());
2517 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2518 DONE;
2519 }
2520 }")
2522 (define_insn "divsi3_mq"
2523 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2524 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2525 (match_operand:SI 2 "gpc_reg_operand" "r")))
2526 (clobber (match_scratch:SI 3 "=q"))]
2527 "TARGET_POWERPC && TARGET_POWER"
2528 "divw %0,%1,%2"
2529 [(set_attr "type" "idiv")])
2531 (define_insn "*div<mode>3_no_mq"
2532 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2533 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2534 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2535 "TARGET_POWERPC && ! TARGET_POWER"
2536 "div<wd> %0,%1,%2"
2537 [(set (attr "type")
2538 (cond [(match_operand:SI 0 "" "")
2539 (const_string "idiv")]
2540 (const_string "ldiv")))])
2542 (define_expand "mod<mode>3"
2543 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2544 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2545 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2546 ""
2547 "
2548 {
2549 int i;
2550 rtx temp1;
2551 rtx temp2;
2553 if (GET_CODE (operands[2]) != CONST_INT
2554 || INTVAL (operands[2]) <= 0
2555 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2556 FAIL;
2558 temp1 = gen_reg_rtx (<MODE>mode);
2559 temp2 = gen_reg_rtx (<MODE>mode);
2561 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2562 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2563 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2564 DONE;
2565 }")
2567 (define_insn ""
2568 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2569 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2570 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2571 ""
2572 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
2573 [(set_attr "type" "two")
2574 (set_attr "length" "8")])
2576 (define_insn ""
2577 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2578 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2579 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2580 (const_int 0)))
2581 (clobber (match_scratch:P 3 "=r,r"))]
2582 ""
2583 "@
2584 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
2585 #"
2586 [(set_attr "type" "compare")
2587 (set_attr "length" "8,12")])
2589 (define_split
2590 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2591 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2592 (match_operand:GPR 2 "exact_log2_cint_operand"
2593 ""))
2594 (const_int 0)))
2595 (clobber (match_scratch:GPR 3 ""))]
2596 "reload_completed"
2597 [(set (match_dup 3)
2598 (div:<MODE> (match_dup 1) (match_dup 2)))
2599 (set (match_dup 0)
2600 (compare:CC (match_dup 3)
2601 (const_int 0)))]
2602 "")
2604 (define_insn ""
2605 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2606 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2607 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2608 (const_int 0)))
2609 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2610 (div:P (match_dup 1) (match_dup 2)))]
2611 ""
2612 "@
2613 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
2614 #"
2615 [(set_attr "type" "compare")
2616 (set_attr "length" "8,12")])
2618 (define_split
2619 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2620 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2621 (match_operand:GPR 2 "exact_log2_cint_operand"
2622 ""))
2623 (const_int 0)))
2624 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2625 (div:GPR (match_dup 1) (match_dup 2)))]
2626 "reload_completed"
2627 [(set (match_dup 0)
2628 (div:<MODE> (match_dup 1) (match_dup 2)))
2629 (set (match_dup 3)
2630 (compare:CC (match_dup 0)
2631 (const_int 0)))]
2632 "")
2634 (define_insn ""
2635 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2636 (udiv:SI
2637 (plus:DI (ashift:DI
2638 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2639 (const_int 32))
2640 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2641 (match_operand:SI 3 "gpc_reg_operand" "r")))
2642 (set (match_operand:SI 2 "register_operand" "=*q")
2643 (umod:SI
2644 (plus:DI (ashift:DI
2645 (zero_extend:DI (match_dup 1)) (const_int 32))
2646 (zero_extend:DI (match_dup 4)))
2647 (match_dup 3)))]
2648 "TARGET_POWER"
2649 "div %0,%1,%3"
2650 [(set_attr "type" "idiv")])
2652 ;; To do unsigned divide we handle the cases of the divisor looking like a
2653 ;; negative number. If it is a constant that is less than 2**31, we don't
2654 ;; have to worry about the branches. So make a few subroutines here.
2655 ;;
2656 ;; First comes the normal case.
2657 (define_expand "udivmodsi4_normal"
2658 [(set (match_dup 4) (const_int 0))
2659 (parallel [(set (match_operand:SI 0 "" "")
2660 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2661 (const_int 32))
2662 (zero_extend:DI (match_operand:SI 1 "" "")))
2663 (match_operand:SI 2 "" "")))
2664 (set (match_operand:SI 3 "" "")
2665 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2666 (const_int 32))
2667 (zero_extend:DI (match_dup 1)))
2668 (match_dup 2)))])]
2669 "TARGET_POWER"
2670 "
2671 { operands[4] = gen_reg_rtx (SImode); }")
2673 ;; This handles the branches.
2674 (define_expand "udivmodsi4_tests"
2675 [(set (match_operand:SI 0 "" "") (const_int 0))
2676 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2677 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2678 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2679 (label_ref (match_operand:SI 4 "" "")) (pc)))
2680 (set (match_dup 0) (const_int 1))
2681 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2682 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2683 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2684 (label_ref (match_dup 4)) (pc)))]
2685 "TARGET_POWER"
2686 "
2687 { operands[5] = gen_reg_rtx (CCUNSmode);
2688 operands[6] = gen_reg_rtx (CCmode);
2689 }")
2691 (define_expand "udivmodsi4"
2692 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2693 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2694 (match_operand:SI 2 "reg_or_cint_operand" "")))
2695 (set (match_operand:SI 3 "gpc_reg_operand" "")
2696 (umod:SI (match_dup 1) (match_dup 2)))])]
2697 ""
2698 "
2699 {
2700 rtx label = 0;
2702 if (! TARGET_POWER)
2703 {
2704 if (! TARGET_POWERPC)
2705 {
2706 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2707 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2708 emit_insn (gen_divus_call ());
2709 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2710 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2711 DONE;
2712 }
2713 else
2714 FAIL;
2715 }
2717 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2718 {
2719 operands[2] = force_reg (SImode, operands[2]);
2720 label = gen_label_rtx ();
2721 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2722 operands[3], label));
2723 }
2724 else
2725 operands[2] = force_reg (SImode, operands[2]);
2727 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2728 operands[3]));
2729 if (label)
2730 emit_label (label);
2732 DONE;
2733 }")
2735 ;; AIX architecture-independent common-mode multiply (DImode),
2736 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2737 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2738 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2739 ;; assumed unused if generating common-mode, so ignore.
2740 (define_insn "mulh_call"
2741 [(set (reg:SI 3)
2742 (truncate:SI
2743 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2744 (sign_extend:DI (reg:SI 4)))
2745 (const_int 32))))
2746 (clobber (reg:SI LR_REGNO))]
2747 "! TARGET_POWER && ! TARGET_POWERPC"
2748 "bla __mulh"
2749 [(set_attr "type" "imul")])
2751 (define_insn "mull_call"
2752 [(set (reg:DI 3)
2753 (mult:DI (sign_extend:DI (reg:SI 3))
2754 (sign_extend:DI (reg:SI 4))))
2755 (clobber (reg:SI LR_REGNO))
2756 (clobber (reg:SI 0))]
2757 "! TARGET_POWER && ! TARGET_POWERPC"
2758 "bla __mull"
2759 [(set_attr "type" "imul")])
2761 (define_insn "divss_call"
2762 [(set (reg:SI 3)
2763 (div:SI (reg:SI 3) (reg:SI 4)))
2764 (set (reg:SI 4)
2765 (mod:SI (reg:SI 3) (reg:SI 4)))
2766 (clobber (reg:SI LR_REGNO))
2767 (clobber (reg:SI 0))]
2768 "! TARGET_POWER && ! TARGET_POWERPC"
2769 "bla __divss"
2770 [(set_attr "type" "idiv")])
2772 (define_insn "divus_call"
2773 [(set (reg:SI 3)
2774 (udiv:SI (reg:SI 3) (reg:SI 4)))
2775 (set (reg:SI 4)
2776 (umod:SI (reg:SI 3) (reg:SI 4)))
2777 (clobber (reg:SI LR_REGNO))
2778 (clobber (reg:SI 0))
2779 (clobber (match_scratch:CC 0 "=x"))
2780 (clobber (reg:CC CR1_REGNO))]
2781 "! TARGET_POWER && ! TARGET_POWERPC"
2782 "bla __divus"
2783 [(set_attr "type" "idiv")])
2785 (define_insn "quoss_call"
2786 [(set (reg:SI 3)
2787 (div:SI (reg:SI 3) (reg:SI 4)))
2788 (clobber (reg:SI LR_REGNO))]
2789 "! TARGET_POWER && ! TARGET_POWERPC"
2790 "bla __quoss"
2791 [(set_attr "type" "idiv")])
2793 (define_insn "quous_call"
2794 [(set (reg:SI 3)
2795 (udiv:SI (reg:SI 3) (reg:SI 4)))
2796 (clobber (reg:SI LR_REGNO))
2797 (clobber (reg:SI 0))
2798 (clobber (match_scratch:CC 0 "=x"))
2799 (clobber (reg:CC CR1_REGNO))]
2800 "! TARGET_POWER && ! TARGET_POWERPC"
2801 "bla __quous"
2802 [(set_attr "type" "idiv")])
2803 \f
2804 ;; Logical instructions
2805 ;; The logical instructions are mostly combined by using match_operator,
2806 ;; but the plain AND insns are somewhat different because there is no
2807 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2808 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2810 (define_insn "andsi3"
2811 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2812 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2813 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2814 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2815 ""
2816 "@
2817 and %0,%1,%2
2818 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2819 {andil.|andi.} %0,%1,%b2
2820 {andiu.|andis.} %0,%1,%u2"
2821 [(set_attr "type" "*,*,compare,compare")])
2823 ;; Note to set cr's other than cr0 we do the and immediate and then
2824 ;; the test again -- this avoids a mfcr which on the higher end
2825 ;; machines causes an execution serialization
2827 (define_insn "*andsi3_internal2"
2828 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2829 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2830 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2831 (const_int 0)))
2832 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2833 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2834 "TARGET_32BIT"
2835 "@
2836 and. %3,%1,%2
2837 {andil.|andi.} %3,%1,%b2
2838 {andiu.|andis.} %3,%1,%u2
2839 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2840 #
2841 #
2842 #
2843 #"
2844 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2845 (set_attr "length" "4,4,4,4,8,8,8,8")])
2847 (define_insn "*andsi3_internal3"
2848 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2849 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2850 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2851 (const_int 0)))
2852 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2853 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2854 "TARGET_64BIT"
2855 "@
2856 #
2857 {andil.|andi.} %3,%1,%b2
2858 {andiu.|andis.} %3,%1,%u2
2859 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2860 #
2861 #
2862 #
2863 #"
2864 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2865 (set_attr "length" "8,4,4,4,8,8,8,8")])
2867 (define_split
2868 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2869 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2870 (match_operand:GPR 2 "and_operand" ""))
2871 (const_int 0)))
2872 (clobber (match_scratch:GPR 3 ""))
2873 (clobber (match_scratch:CC 4 ""))]
2874 "reload_completed"
2875 [(parallel [(set (match_dup 3)
2876 (and:<MODE> (match_dup 1)
2877 (match_dup 2)))
2878 (clobber (match_dup 4))])
2879 (set (match_dup 0)
2880 (compare:CC (match_dup 3)
2881 (const_int 0)))]
2882 "")
2884 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2885 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2887 (define_split
2888 [(set (match_operand:CC 0 "cc_reg_operand" "")
2889 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2890 (match_operand:SI 2 "gpc_reg_operand" ""))
2891 (const_int 0)))
2892 (clobber (match_scratch:SI 3 ""))
2893 (clobber (match_scratch:CC 4 ""))]
2894 "TARGET_POWERPC64 && reload_completed"
2895 [(parallel [(set (match_dup 3)
2896 (and:SI (match_dup 1)
2897 (match_dup 2)))
2898 (clobber (match_dup 4))])
2899 (set (match_dup 0)
2900 (compare:CC (match_dup 3)
2901 (const_int 0)))]
2902 "")
2904 (define_insn "*andsi3_internal4"
2905 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2906 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2907 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2908 (const_int 0)))
2909 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2910 (and:SI (match_dup 1)
2911 (match_dup 2)))
2912 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2913 "TARGET_32BIT"
2914 "@
2915 and. %0,%1,%2
2916 {andil.|andi.} %0,%1,%b2
2917 {andiu.|andis.} %0,%1,%u2
2918 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2919 #
2920 #
2921 #
2922 #"
2923 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2924 (set_attr "length" "4,4,4,4,8,8,8,8")])
2926 (define_insn "*andsi3_internal5"
2927 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2928 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2929 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2930 (const_int 0)))
2931 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2932 (and:SI (match_dup 1)
2933 (match_dup 2)))
2934 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2935 "TARGET_64BIT"
2936 "@
2937 #
2938 {andil.|andi.} %0,%1,%b2
2939 {andiu.|andis.} %0,%1,%u2
2940 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2941 #
2942 #
2943 #
2944 #"
2945 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2946 (set_attr "length" "8,4,4,4,8,8,8,8")])
2948 (define_split
2949 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2950 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2951 (match_operand:SI 2 "and_operand" ""))
2952 (const_int 0)))
2953 (set (match_operand:SI 0 "gpc_reg_operand" "")
2954 (and:SI (match_dup 1)
2955 (match_dup 2)))
2956 (clobber (match_scratch:CC 4 ""))]
2957 "reload_completed"
2958 [(parallel [(set (match_dup 0)
2959 (and:SI (match_dup 1)
2960 (match_dup 2)))
2961 (clobber (match_dup 4))])
2962 (set (match_dup 3)
2963 (compare:CC (match_dup 0)
2964 (const_int 0)))]
2965 "")
2967 (define_split
2968 [(set (match_operand:CC 3 "cc_reg_operand" "")
2969 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2970 (match_operand:SI 2 "gpc_reg_operand" ""))
2971 (const_int 0)))
2972 (set (match_operand:SI 0 "gpc_reg_operand" "")
2973 (and:SI (match_dup 1)
2974 (match_dup 2)))
2975 (clobber (match_scratch:CC 4 ""))]
2976 "TARGET_POWERPC64 && reload_completed"
2977 [(parallel [(set (match_dup 0)
2978 (and:SI (match_dup 1)
2979 (match_dup 2)))
2980 (clobber (match_dup 4))])
2981 (set (match_dup 3)
2982 (compare:CC (match_dup 0)
2983 (const_int 0)))]
2984 "")
2986 ;; Handle the PowerPC64 rlwinm corner case
2988 (define_insn_and_split "*andsi3_internal6"
2989 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2990 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2991 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2992 "TARGET_POWERPC64"
2993 "#"
2994 "TARGET_POWERPC64"
2995 [(set (match_dup 0)
2996 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2997 (match_dup 4)))
2998 (set (match_dup 0)
2999 (rotate:SI (match_dup 0) (match_dup 5)))]
3000 "
3001 {
3002 int mb = extract_MB (operands[2]);
3003 int me = extract_ME (operands[2]);
3004 operands[3] = GEN_INT (me + 1);
3005 operands[5] = GEN_INT (32 - (me + 1));
3006 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3007 }"
3008 [(set_attr "length" "8")])
3010 (define_expand "iorsi3"
3011 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3012 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3013 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3014 ""
3015 "
3016 {
3017 if (GET_CODE (operands[2]) == CONST_INT
3018 && ! logical_operand (operands[2], SImode))
3019 {
3020 HOST_WIDE_INT value = INTVAL (operands[2]);
3021 rtx tmp = ((!can_create_pseudo_p ()
3022 || rtx_equal_p (operands[0], operands[1]))
3023 ? operands[0] : gen_reg_rtx (SImode));
3025 emit_insn (gen_iorsi3 (tmp, operands[1],
3026 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3027 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3028 DONE;
3029 }
3030 }")
3032 (define_expand "xorsi3"
3033 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3034 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3035 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3036 ""
3037 "
3038 {
3039 if (GET_CODE (operands[2]) == CONST_INT
3040 && ! logical_operand (operands[2], SImode))
3041 {
3042 HOST_WIDE_INT value = INTVAL (operands[2]);
3043 rtx tmp = ((!can_create_pseudo_p ()
3044 || rtx_equal_p (operands[0], operands[1]))
3045 ? operands[0] : gen_reg_rtx (SImode));
3047 emit_insn (gen_xorsi3 (tmp, operands[1],
3048 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3049 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3050 DONE;
3051 }
3052 }")
3054 (define_insn "*boolsi3_internal1"
3055 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3056 (match_operator:SI 3 "boolean_or_operator"
3057 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3058 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3059 ""
3060 "@
3061 %q3 %0,%1,%2
3062 {%q3il|%q3i} %0,%1,%b2
3063 {%q3iu|%q3is} %0,%1,%u2")
3065 (define_insn "*boolsi3_internal2"
3066 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3067 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3068 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3069 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3070 (const_int 0)))
3071 (clobber (match_scratch:SI 3 "=r,r"))]
3072 "TARGET_32BIT"
3073 "@
3074 %q4. %3,%1,%2
3075 #"
3076 [(set_attr "type" "compare")
3077 (set_attr "length" "4,8")])
3079 (define_split
3080 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3081 (compare:CC (match_operator:SI 4 "boolean_operator"
3082 [(match_operand:SI 1 "gpc_reg_operand" "")
3083 (match_operand:SI 2 "gpc_reg_operand" "")])
3084 (const_int 0)))
3085 (clobber (match_scratch:SI 3 ""))]
3086 "TARGET_32BIT && reload_completed"
3087 [(set (match_dup 3) (match_dup 4))
3088 (set (match_dup 0)
3089 (compare:CC (match_dup 3)
3090 (const_int 0)))]
3091 "")
3093 (define_insn "*boolsi3_internal3"
3094 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3095 (compare:CC (match_operator:SI 4 "boolean_operator"
3096 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3097 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3098 (const_int 0)))
3099 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3100 (match_dup 4))]
3101 "TARGET_32BIT"
3102 "@
3103 %q4. %0,%1,%2
3104 #"
3105 [(set_attr "type" "compare")
3106 (set_attr "length" "4,8")])
3108 (define_split
3109 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3110 (compare:CC (match_operator:SI 4 "boolean_operator"
3111 [(match_operand:SI 1 "gpc_reg_operand" "")
3112 (match_operand:SI 2 "gpc_reg_operand" "")])
3113 (const_int 0)))
3114 (set (match_operand:SI 0 "gpc_reg_operand" "")
3115 (match_dup 4))]
3116 "TARGET_32BIT && reload_completed"
3117 [(set (match_dup 0) (match_dup 4))
3118 (set (match_dup 3)
3119 (compare:CC (match_dup 0)
3120 (const_int 0)))]
3121 "")
3123 ;; Split a logical operation that we can't do in one insn into two insns,
3124 ;; each of which does one 16-bit part. This is used by combine.
3126 (define_split
3127 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3128 (match_operator:SI 3 "boolean_or_operator"
3129 [(match_operand:SI 1 "gpc_reg_operand" "")
3130 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3131 ""
3132 [(set (match_dup 0) (match_dup 4))
3133 (set (match_dup 0) (match_dup 5))]
3134 "
3135 {
3136 rtx i;
3137 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3138 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3139 operands[1], i);
3140 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3141 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3142 operands[0], i);
3143 }")
3145 (define_insn "*boolcsi3_internal1"
3146 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3147 (match_operator:SI 3 "boolean_operator"
3148 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3149 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3150 ""
3151 "%q3 %0,%2,%1")
3153 (define_insn "*boolcsi3_internal2"
3154 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3155 (compare:CC (match_operator:SI 4 "boolean_operator"
3156 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3157 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3158 (const_int 0)))
3159 (clobber (match_scratch:SI 3 "=r,r"))]
3160 "TARGET_32BIT"
3161 "@
3162 %q4. %3,%2,%1
3163 #"
3164 [(set_attr "type" "compare")
3165 (set_attr "length" "4,8")])
3167 (define_split
3168 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3169 (compare:CC (match_operator:SI 4 "boolean_operator"
3170 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3171 (match_operand:SI 2 "gpc_reg_operand" "")])
3172 (const_int 0)))
3173 (clobber (match_scratch:SI 3 ""))]
3174 "TARGET_32BIT && reload_completed"
3175 [(set (match_dup 3) (match_dup 4))
3176 (set (match_dup 0)
3177 (compare:CC (match_dup 3)
3178 (const_int 0)))]
3179 "")
3181 (define_insn "*boolcsi3_internal3"
3182 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3183 (compare:CC (match_operator:SI 4 "boolean_operator"
3184 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3185 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3186 (const_int 0)))
3187 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3188 (match_dup 4))]
3189 "TARGET_32BIT"
3190 "@
3191 %q4. %0,%2,%1
3192 #"
3193 [(set_attr "type" "compare")
3194 (set_attr "length" "4,8")])
3196 (define_split
3197 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3198 (compare:CC (match_operator:SI 4 "boolean_operator"
3199 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3200 (match_operand:SI 2 "gpc_reg_operand" "")])
3201 (const_int 0)))
3202 (set (match_operand:SI 0 "gpc_reg_operand" "")
3203 (match_dup 4))]
3204 "TARGET_32BIT && reload_completed"
3205 [(set (match_dup 0) (match_dup 4))
3206 (set (match_dup 3)
3207 (compare:CC (match_dup 0)
3208 (const_int 0)))]
3209 "")
3211 (define_insn "*boolccsi3_internal1"
3212 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3213 (match_operator:SI 3 "boolean_operator"
3214 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3215 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3216 ""
3217 "%q3 %0,%1,%2")
3219 (define_insn "*boolccsi3_internal2"
3220 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3221 (compare:CC (match_operator:SI 4 "boolean_operator"
3222 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3223 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3224 (const_int 0)))
3225 (clobber (match_scratch:SI 3 "=r,r"))]
3226 "TARGET_32BIT"
3227 "@
3228 %q4. %3,%1,%2
3229 #"
3230 [(set_attr "type" "compare")
3231 (set_attr "length" "4,8")])
3233 (define_split
3234 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3235 (compare:CC (match_operator:SI 4 "boolean_operator"
3236 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3237 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3238 (const_int 0)))
3239 (clobber (match_scratch:SI 3 ""))]
3240 "TARGET_32BIT && reload_completed"
3241 [(set (match_dup 3) (match_dup 4))
3242 (set (match_dup 0)
3243 (compare:CC (match_dup 3)
3244 (const_int 0)))]
3245 "")
3247 (define_insn "*boolccsi3_internal3"
3248 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3249 (compare:CC (match_operator:SI 4 "boolean_operator"
3250 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3251 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3252 (const_int 0)))
3253 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3254 (match_dup 4))]
3255 "TARGET_32BIT"
3256 "@
3257 %q4. %0,%1,%2
3258 #"
3259 [(set_attr "type" "compare")
3260 (set_attr "length" "4,8")])
3262 (define_split
3263 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3264 (compare:CC (match_operator:SI 4 "boolean_operator"
3265 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3266 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3267 (const_int 0)))
3268 (set (match_operand:SI 0 "gpc_reg_operand" "")
3269 (match_dup 4))]
3270 "TARGET_32BIT && reload_completed"
3271 [(set (match_dup 0) (match_dup 4))
3272 (set (match_dup 3)
3273 (compare:CC (match_dup 0)
3274 (const_int 0)))]
3275 "")
3277 ;; maskir insn. We need four forms because things might be in arbitrary
3278 ;; orders. Don't define forms that only set CR fields because these
3279 ;; would modify an input register.
3281 (define_insn "*maskir_internal1"
3282 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3283 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3284 (match_operand:SI 1 "gpc_reg_operand" "0"))
3285 (and:SI (match_dup 2)
3286 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3287 "TARGET_POWER"
3288 "maskir %0,%3,%2")
3290 (define_insn "*maskir_internal2"
3291 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3292 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3293 (match_operand:SI 1 "gpc_reg_operand" "0"))
3294 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3295 (match_dup 2))))]
3296 "TARGET_POWER"
3297 "maskir %0,%3,%2")
3299 (define_insn "*maskir_internal3"
3300 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3301 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3302 (match_operand:SI 3 "gpc_reg_operand" "r"))
3303 (and:SI (not:SI (match_dup 2))
3304 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3305 "TARGET_POWER"
3306 "maskir %0,%3,%2")
3308 (define_insn "*maskir_internal4"
3309 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3310 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3311 (match_operand:SI 2 "gpc_reg_operand" "r"))
3312 (and:SI (not:SI (match_dup 2))
3313 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3314 "TARGET_POWER"
3315 "maskir %0,%3,%2")
3317 (define_insn "*maskir_internal5"
3318 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3319 (compare:CC
3320 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3321 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3322 (and:SI (match_dup 2)
3323 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3324 (const_int 0)))
3325 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3326 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3327 (and:SI (match_dup 2) (match_dup 3))))]
3328 "TARGET_POWER"
3329 "@
3330 maskir. %0,%3,%2
3331 #"
3332 [(set_attr "type" "compare")
3333 (set_attr "length" "4,8")])
3335 (define_split
3336 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3337 (compare:CC
3338 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3339 (match_operand:SI 1 "gpc_reg_operand" ""))
3340 (and:SI (match_dup 2)
3341 (match_operand:SI 3 "gpc_reg_operand" "")))
3342 (const_int 0)))
3343 (set (match_operand:SI 0 "gpc_reg_operand" "")
3344 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3345 (and:SI (match_dup 2) (match_dup 3))))]
3346 "TARGET_POWER && reload_completed"
3347 [(set (match_dup 0)
3348 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3349 (and:SI (match_dup 2) (match_dup 3))))
3350 (set (match_dup 4)
3351 (compare:CC (match_dup 0)
3352 (const_int 0)))]
3353 "")
3355 (define_insn "*maskir_internal6"
3356 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3357 (compare:CC
3358 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3359 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3360 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3361 (match_dup 2)))
3362 (const_int 0)))
3363 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3364 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3365 (and:SI (match_dup 3) (match_dup 2))))]
3366 "TARGET_POWER"
3367 "@
3368 maskir. %0,%3,%2
3369 #"
3370 [(set_attr "type" "compare")
3371 (set_attr "length" "4,8")])
3373 (define_split
3374 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3375 (compare:CC
3376 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3377 (match_operand:SI 1 "gpc_reg_operand" ""))
3378 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3379 (match_dup 2)))
3380 (const_int 0)))
3381 (set (match_operand:SI 0 "gpc_reg_operand" "")
3382 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3383 (and:SI (match_dup 3) (match_dup 2))))]
3384 "TARGET_POWER && reload_completed"
3385 [(set (match_dup 0)
3386 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3387 (and:SI (match_dup 3) (match_dup 2))))
3388 (set (match_dup 4)
3389 (compare:CC (match_dup 0)
3390 (const_int 0)))]
3391 "")
3393 (define_insn "*maskir_internal7"
3394 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3395 (compare:CC
3396 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3397 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3398 (and:SI (not:SI (match_dup 2))
3399 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3400 (const_int 0)))
3401 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3402 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3403 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3404 "TARGET_POWER"
3405 "@
3406 maskir. %0,%3,%2
3407 #"
3408 [(set_attr "type" "compare")
3409 (set_attr "length" "4,8")])
3411 (define_split
3412 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3413 (compare:CC
3414 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3415 (match_operand:SI 3 "gpc_reg_operand" ""))
3416 (and:SI (not:SI (match_dup 2))
3417 (match_operand:SI 1 "gpc_reg_operand" "")))
3418 (const_int 0)))
3419 (set (match_operand:SI 0 "gpc_reg_operand" "")
3420 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3421 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3422 "TARGET_POWER && reload_completed"
3423 [(set (match_dup 0)
3424 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3425 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3426 (set (match_dup 4)
3427 (compare:CC (match_dup 0)
3428 (const_int 0)))]
3429 "")
3431 (define_insn "*maskir_internal8"
3432 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3433 (compare:CC
3434 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3435 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3436 (and:SI (not:SI (match_dup 2))
3437 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3438 (const_int 0)))
3439 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3440 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3441 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3442 "TARGET_POWER"
3443 "@
3444 maskir. %0,%3,%2
3445 #"
3446 [(set_attr "type" "compare")
3447 (set_attr "length" "4,8")])
3449 (define_split
3450 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3451 (compare:CC
3452 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3453 (match_operand:SI 2 "gpc_reg_operand" ""))
3454 (and:SI (not:SI (match_dup 2))
3455 (match_operand:SI 1 "gpc_reg_operand" "")))
3456 (const_int 0)))
3457 (set (match_operand:SI 0 "gpc_reg_operand" "")
3458 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3459 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3460 "TARGET_POWER && reload_completed"
3461 [(set (match_dup 0)
3462 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3463 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3464 (set (match_dup 4)
3465 (compare:CC (match_dup 0)
3466 (const_int 0)))]
3467 "")
3468 \f
3469 ;; Rotate and shift insns, in all their variants. These support shifts,
3470 ;; field inserts and extracts, and various combinations thereof.
3471 (define_expand "insv"
3472 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3473 (match_operand:SI 1 "const_int_operand" "")
3474 (match_operand:SI 2 "const_int_operand" ""))
3475 (match_operand 3 "gpc_reg_operand" ""))]
3476 ""
3477 "
3478 {
3479 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3480 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3481 compiler if the address of the structure is taken later. Likewise, do
3482 not handle invalid E500 subregs. */
3483 if (GET_CODE (operands[0]) == SUBREG
3484 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3485 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3486 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3487 FAIL;
3489 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3490 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3491 else
3492 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3493 DONE;
3494 }")
3496 (define_insn "insvsi"
3497 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3498 (match_operand:SI 1 "const_int_operand" "i")
3499 (match_operand:SI 2 "const_int_operand" "i"))
3500 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3501 ""
3502 "*
3503 {
3504 int start = INTVAL (operands[2]) & 31;
3505 int size = INTVAL (operands[1]) & 31;
3507 operands[4] = GEN_INT (32 - start - size);
3508 operands[1] = GEN_INT (start + size - 1);
3509 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3510 }"
3511 [(set_attr "type" "insert_word")])
3513 (define_insn "*insvsi_internal1"
3514 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3515 (match_operand:SI 1 "const_int_operand" "i")
3516 (match_operand:SI 2 "const_int_operand" "i"))
3517 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3518 (match_operand:SI 4 "const_int_operand" "i")))]
3519 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3520 "*
3521 {
3522 int shift = INTVAL (operands[4]) & 31;
3523 int start = INTVAL (operands[2]) & 31;
3524 int size = INTVAL (operands[1]) & 31;
3526 operands[4] = GEN_INT (shift - start - size);
3527 operands[1] = GEN_INT (start + size - 1);
3528 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3529 }"
3530 [(set_attr "type" "insert_word")])
3532 (define_insn "*insvsi_internal2"
3533 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3534 (match_operand:SI 1 "const_int_operand" "i")
3535 (match_operand:SI 2 "const_int_operand" "i"))
3536 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3537 (match_operand:SI 4 "const_int_operand" "i")))]
3538 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3539 "*
3540 {
3541 int shift = INTVAL (operands[4]) & 31;
3542 int start = INTVAL (operands[2]) & 31;
3543 int size = INTVAL (operands[1]) & 31;
3545 operands[4] = GEN_INT (32 - shift - start - size);
3546 operands[1] = GEN_INT (start + size - 1);
3547 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3548 }"
3549 [(set_attr "type" "insert_word")])
3551 (define_insn "*insvsi_internal3"
3552 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3553 (match_operand:SI 1 "const_int_operand" "i")
3554 (match_operand:SI 2 "const_int_operand" "i"))
3555 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3556 (match_operand:SI 4 "const_int_operand" "i")))]
3557 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3558 "*
3559 {
3560 int shift = INTVAL (operands[4]) & 31;
3561 int start = INTVAL (operands[2]) & 31;
3562 int size = INTVAL (operands[1]) & 31;
3564 operands[4] = GEN_INT (32 - shift - start - size);
3565 operands[1] = GEN_INT (start + size - 1);
3566 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3567 }"
3568 [(set_attr "type" "insert_word")])
3570 (define_insn "*insvsi_internal4"
3571 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3572 (match_operand:SI 1 "const_int_operand" "i")
3573 (match_operand:SI 2 "const_int_operand" "i"))
3574 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3575 (match_operand:SI 4 "const_int_operand" "i")
3576 (match_operand:SI 5 "const_int_operand" "i")))]
3577 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3578 "*
3579 {
3580 int extract_start = INTVAL (operands[5]) & 31;
3581 int extract_size = INTVAL (operands[4]) & 31;
3582 int insert_start = INTVAL (operands[2]) & 31;
3583 int insert_size = INTVAL (operands[1]) & 31;
3585 /* Align extract field with insert field */
3586 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3587 operands[1] = GEN_INT (insert_start + insert_size - 1);
3588 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3589 }"
3590 [(set_attr "type" "insert_word")])
3592 ;; combine patterns for rlwimi
3593 (define_insn "*insvsi_internal5"
3594 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3595 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3596 (match_operand:SI 1 "mask_operand" "i"))
3597 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3598 (match_operand:SI 2 "const_int_operand" "i"))
3599 (match_operand:SI 5 "mask_operand" "i"))))]
3600 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3601 "*
3602 {
3603 int me = extract_ME(operands[5]);
3604 int mb = extract_MB(operands[5]);
3605 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3606 operands[2] = GEN_INT(mb);
3607 operands[1] = GEN_INT(me);
3608 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3609 }"
3610 [(set_attr "type" "insert_word")])
3612 (define_insn "*insvsi_internal6"
3613 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3614 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3615 (match_operand:SI 2 "const_int_operand" "i"))
3616 (match_operand:SI 5 "mask_operand" "i"))
3617 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3618 (match_operand:SI 1 "mask_operand" "i"))))]
3619 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3620 "*
3621 {
3622 int me = extract_ME(operands[5]);
3623 int mb = extract_MB(operands[5]);
3624 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3625 operands[2] = GEN_INT(mb);
3626 operands[1] = GEN_INT(me);
3627 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3628 }"
3629 [(set_attr "type" "insert_word")])
3631 (define_insn "insvdi"
3632 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3633 (match_operand:SI 1 "const_int_operand" "i")
3634 (match_operand:SI 2 "const_int_operand" "i"))
3635 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3636 "TARGET_POWERPC64"
3637 "*
3638 {
3639 int start = INTVAL (operands[2]) & 63;
3640 int size = INTVAL (operands[1]) & 63;
3642 operands[1] = GEN_INT (64 - start - size);
3643 return \"rldimi %0,%3,%H1,%H2\";
3644 }"
3645 [(set_attr "type" "insert_dword")])
3647 (define_insn "*insvdi_internal2"
3648 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3649 (match_operand:SI 1 "const_int_operand" "i")
3650 (match_operand:SI 2 "const_int_operand" "i"))
3651 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3652 (match_operand:SI 4 "const_int_operand" "i")))]
3653 "TARGET_POWERPC64
3654 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3655 "*
3656 {
3657 int shift = INTVAL (operands[4]) & 63;
3658 int start = (INTVAL (operands[2]) & 63) - 32;
3659 int size = INTVAL (operands[1]) & 63;
3661 operands[4] = GEN_INT (64 - shift - start - size);
3662 operands[2] = GEN_INT (start);
3663 operands[1] = GEN_INT (start + size - 1);
3664 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3665 }")
3667 (define_insn "*insvdi_internal3"
3668 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3669 (match_operand:SI 1 "const_int_operand" "i")
3670 (match_operand:SI 2 "const_int_operand" "i"))
3671 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3672 (match_operand:SI 4 "const_int_operand" "i")))]
3673 "TARGET_POWERPC64
3674 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3675 "*
3676 {
3677 int shift = INTVAL (operands[4]) & 63;
3678 int start = (INTVAL (operands[2]) & 63) - 32;
3679 int size = INTVAL (operands[1]) & 63;
3681 operands[4] = GEN_INT (64 - shift - start - size);
3682 operands[2] = GEN_INT (start);
3683 operands[1] = GEN_INT (start + size - 1);
3684 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3685 }")
3687 (define_expand "extzv"
3688 [(set (match_operand 0 "gpc_reg_operand" "")
3689 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3690 (match_operand:SI 2 "const_int_operand" "")
3691 (match_operand:SI 3 "const_int_operand" "")))]
3692 ""
3693 "
3694 {
3695 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3696 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3697 compiler if the address of the structure is taken later. */
3698 if (GET_CODE (operands[0]) == SUBREG
3699 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3700 FAIL;
3702 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3703 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3704 else
3705 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3706 DONE;
3707 }")
3709 (define_insn "extzvsi"
3710 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3711 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3712 (match_operand:SI 2 "const_int_operand" "i")
3713 (match_operand:SI 3 "const_int_operand" "i")))]
3714 ""
3715 "*
3716 {
3717 int start = INTVAL (operands[3]) & 31;
3718 int size = INTVAL (operands[2]) & 31;
3720 if (start + size >= 32)
3721 operands[3] = const0_rtx;
3722 else
3723 operands[3] = GEN_INT (start + size);
3724 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3725 }")
3727 (define_insn "*extzvsi_internal1"
3728 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3729 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3730 (match_operand:SI 2 "const_int_operand" "i,i")
3731 (match_operand:SI 3 "const_int_operand" "i,i"))
3732 (const_int 0)))
3733 (clobber (match_scratch:SI 4 "=r,r"))]
3734 ""
3735 "*
3736 {
3737 int start = INTVAL (operands[3]) & 31;
3738 int size = INTVAL (operands[2]) & 31;
3740 /* Force split for non-cc0 compare. */
3741 if (which_alternative == 1)
3742 return \"#\";
3744 /* If the bit-field being tested fits in the upper or lower half of a
3745 word, it is possible to use andiu. or andil. to test it. This is
3746 useful because the condition register set-use delay is smaller for
3747 andi[ul]. than for rlinm. This doesn't work when the starting bit
3748 position is 0 because the LT and GT bits may be set wrong. */
3750 if ((start > 0 && start + size <= 16) || start >= 16)
3751 {
3752 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3753 - (1 << (16 - (start & 15) - size))));
3754 if (start < 16)
3755 return \"{andiu.|andis.} %4,%1,%3\";
3756 else
3757 return \"{andil.|andi.} %4,%1,%3\";
3758 }
3760 if (start + size >= 32)
3761 operands[3] = const0_rtx;
3762 else
3763 operands[3] = GEN_INT (start + size);
3764 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3765 }"
3766 [(set_attr "type" "delayed_compare")
3767 (set_attr "length" "4,8")])
3769 (define_split
3770 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3771 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3772 (match_operand:SI 2 "const_int_operand" "")
3773 (match_operand:SI 3 "const_int_operand" ""))
3774 (const_int 0)))
3775 (clobber (match_scratch:SI 4 ""))]
3776 "reload_completed"
3777 [(set (match_dup 4)
3778 (zero_extract:SI (match_dup 1) (match_dup 2)
3779 (match_dup 3)))
3780 (set (match_dup 0)
3781 (compare:CC (match_dup 4)
3782 (const_int 0)))]
3783 "")
3785 (define_insn "*extzvsi_internal2"
3786 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3787 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3788 (match_operand:SI 2 "const_int_operand" "i,i")
3789 (match_operand:SI 3 "const_int_operand" "i,i"))
3790 (const_int 0)))
3791 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3792 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3793 ""
3794 "*
3795 {
3796 int start = INTVAL (operands[3]) & 31;
3797 int size = INTVAL (operands[2]) & 31;
3799 /* Force split for non-cc0 compare. */
3800 if (which_alternative == 1)
3801 return \"#\";
3803 /* Since we are using the output value, we can't ignore any need for
3804 a shift. The bit-field must end at the LSB. */
3805 if (start >= 16 && start + size == 32)
3806 {
3807 operands[3] = GEN_INT ((1 << size) - 1);
3808 return \"{andil.|andi.} %0,%1,%3\";
3809 }
3811 if (start + size >= 32)
3812 operands[3] = const0_rtx;
3813 else
3814 operands[3] = GEN_INT (start + size);
3815 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3816 }"
3817 [(set_attr "type" "delayed_compare")
3818 (set_attr "length" "4,8")])
3820 (define_split
3821 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3822 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3823 (match_operand:SI 2 "const_int_operand" "")
3824 (match_operand:SI 3 "const_int_operand" ""))
3825 (const_int 0)))
3826 (set (match_operand:SI 0 "gpc_reg_operand" "")
3827 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3828 "reload_completed"
3829 [(set (match_dup 0)
3830 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3831 (set (match_dup 4)
3832 (compare:CC (match_dup 0)
3833 (const_int 0)))]
3834 "")
3836 (define_insn "extzvdi"
3837 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3838 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3839 (match_operand:SI 2 "const_int_operand" "i")
3840 (match_operand:SI 3 "const_int_operand" "i")))]
3841 "TARGET_POWERPC64"
3842 "*
3843 {
3844 int start = INTVAL (operands[3]) & 63;
3845 int size = INTVAL (operands[2]) & 63;
3847 if (start + size >= 64)
3848 operands[3] = const0_rtx;
3849 else
3850 operands[3] = GEN_INT (start + size);
3851 operands[2] = GEN_INT (64 - size);
3852 return \"rldicl %0,%1,%3,%2\";
3853 }")
3855 (define_insn "*extzvdi_internal1"
3856 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3857 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3858 (match_operand:SI 2 "const_int_operand" "i")
3859 (match_operand:SI 3 "const_int_operand" "i"))
3860 (const_int 0)))
3861 (clobber (match_scratch:DI 4 "=r"))]
3862 "TARGET_64BIT"
3863 "*
3864 {
3865 int start = INTVAL (operands[3]) & 63;
3866 int size = INTVAL (operands[2]) & 63;
3868 if (start + size >= 64)
3869 operands[3] = const0_rtx;
3870 else
3871 operands[3] = GEN_INT (start + size);
3872 operands[2] = GEN_INT (64 - size);
3873 return \"rldicl. %4,%1,%3,%2\";
3874 }"
3875 [(set_attr "type" "compare")])
3877 (define_insn "*extzvdi_internal2"
3878 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3879 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3880 (match_operand:SI 2 "const_int_operand" "i")
3881 (match_operand:SI 3 "const_int_operand" "i"))
3882 (const_int 0)))
3883 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3884 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3885 "TARGET_64BIT"
3886 "*
3887 {
3888 int start = INTVAL (operands[3]) & 63;
3889 int size = INTVAL (operands[2]) & 63;
3891 if (start + size >= 64)
3892 operands[3] = const0_rtx;
3893 else
3894 operands[3] = GEN_INT (start + size);
3895 operands[2] = GEN_INT (64 - size);
3896 return \"rldicl. %0,%1,%3,%2\";
3897 }"
3898 [(set_attr "type" "compare")])
3900 (define_insn "rotlsi3"
3901 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3902 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3903 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3904 ""
3905 "@
3906 {rlnm|rlwnm} %0,%1,%2,0xffffffff
3907 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
3908 [(set_attr "type" "var_shift_rotate,integer")])
3910 (define_insn "*rotlsi3_internal2"
3911 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3912 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3913 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3914 (const_int 0)))
3915 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3916 ""
3917 "@
3918 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
3919 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
3920 #
3921 #"
3922 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3923 (set_attr "length" "4,4,8,8")])
3925 (define_split
3926 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3927 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3928 (match_operand:SI 2 "reg_or_cint_operand" ""))
3929 (const_int 0)))
3930 (clobber (match_scratch:SI 3 ""))]
3931 "reload_completed"
3932 [(set (match_dup 3)
3933 (rotate:SI (match_dup 1) (match_dup 2)))
3934 (set (match_dup 0)
3935 (compare:CC (match_dup 3)
3936 (const_int 0)))]
3937 "")
3939 (define_insn "*rotlsi3_internal3"
3940 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3941 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3942 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3943 (const_int 0)))
3944 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3945 (rotate:SI (match_dup 1) (match_dup 2)))]
3946 ""
3947 "@
3948 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
3949 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
3950 #
3951 #"
3952 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3953 (set_attr "length" "4,4,8,8")])
3955 (define_split
3956 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3957 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3958 (match_operand:SI 2 "reg_or_cint_operand" ""))
3959 (const_int 0)))
3960 (set (match_operand:SI 0 "gpc_reg_operand" "")
3961 (rotate:SI (match_dup 1) (match_dup 2)))]
3962 "reload_completed"
3963 [(set (match_dup 0)
3964 (rotate:SI (match_dup 1) (match_dup 2)))
3965 (set (match_dup 3)
3966 (compare:CC (match_dup 0)
3967 (const_int 0)))]
3968 "")
3970 (define_insn "*rotlsi3_internal4"
3971 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3972 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3973 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3974 (match_operand:SI 3 "mask_operand" "n,n")))]
3975 ""
3976 "@
3977 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
3978 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
3979 [(set_attr "type" "var_shift_rotate,integer")])
3981 (define_insn "*rotlsi3_internal5"
3982 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3983 (compare:CC (and:SI
3984 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3985 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3986 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3987 (const_int 0)))
3988 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
3989 ""
3990 "@
3991 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
3992 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3993 #
3994 #"
3995 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3996 (set_attr "length" "4,4,8,8")])
3998 (define_split
3999 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4000 (compare:CC (and:SI
4001 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4002 (match_operand:SI 2 "reg_or_cint_operand" ""))
4003 (match_operand:SI 3 "mask_operand" ""))
4004 (const_int 0)))
4005 (clobber (match_scratch:SI 4 ""))]
4006 "reload_completed"
4007 [(set (match_dup 4)
4008 (and:SI (rotate:SI (match_dup 1)
4009 (match_dup 2))
4010 (match_dup 3)))
4011 (set (match_dup 0)
4012 (compare:CC (match_dup 4)
4013 (const_int 0)))]
4014 "")
4016 (define_insn "*rotlsi3_internal6"
4017 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
4018 (compare:CC (and:SI
4019 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4020 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4021 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4022 (const_int 0)))
4023 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4024 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4025 ""
4026 "@
4027 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4028 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4029 #
4030 #"
4031 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4032 (set_attr "length" "4,4,8,8")])
4034 (define_split
4035 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4036 (compare:CC (and:SI
4037 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4038 (match_operand:SI 2 "reg_or_cint_operand" ""))
4039 (match_operand:SI 3 "mask_operand" ""))
4040 (const_int 0)))
4041 (set (match_operand:SI 0 "gpc_reg_operand" "")
4042 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4043 "reload_completed"
4044 [(set (match_dup 0)
4045 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4046 (set (match_dup 4)
4047 (compare:CC (match_dup 0)
4048 (const_int 0)))]
4049 "")
4051 (define_insn "*rotlsi3_internal7"
4052 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4053 (zero_extend:SI
4054 (subreg:QI
4055 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4056 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4057 ""
4058 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
4060 (define_insn "*rotlsi3_internal8"
4061 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4062 (compare:CC (zero_extend:SI
4063 (subreg:QI
4064 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4065 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4066 (const_int 0)))
4067 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4068 ""
4069 "@
4070 {rlnm.|rlwnm.} %3,%1,%2,0xff
4071 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4072 #
4073 #"
4074 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4075 (set_attr "length" "4,4,8,8")])
4077 (define_split
4078 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4079 (compare:CC (zero_extend:SI
4080 (subreg:QI
4081 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4082 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4083 (const_int 0)))
4084 (clobber (match_scratch:SI 3 ""))]
4085 "reload_completed"
4086 [(set (match_dup 3)
4087 (zero_extend:SI (subreg:QI
4088 (rotate:SI (match_dup 1)
4089 (match_dup 2)) 0)))
4090 (set (match_dup 0)
4091 (compare:CC (match_dup 3)
4092 (const_int 0)))]
4093 "")
4095 (define_insn "*rotlsi3_internal9"
4096 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4097 (compare:CC (zero_extend:SI
4098 (subreg:QI
4099 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4100 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4101 (const_int 0)))
4102 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4103 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4104 ""
4105 "@
4106 {rlnm.|rlwnm.} %0,%1,%2,0xff
4107 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4108 #
4109 #"
4110 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4111 (set_attr "length" "4,4,8,8")])
4113 (define_split
4114 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4115 (compare:CC (zero_extend:SI
4116 (subreg:QI
4117 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4118 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4119 (const_int 0)))
4120 (set (match_operand:SI 0 "gpc_reg_operand" "")
4121 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4122 "reload_completed"
4123 [(set (match_dup 0)
4124 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4125 (set (match_dup 3)
4126 (compare:CC (match_dup 0)
4127 (const_int 0)))]
4128 "")
4130 (define_insn "*rotlsi3_internal10"
4131 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4132 (zero_extend:SI
4133 (subreg:HI
4134 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4135 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4136 ""
4137 "@
4138 {rlnm|rlwnm} %0,%1,%2,0xffff
4139 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4140 [(set_attr "type" "var_shift_rotate,integer")])
4143 (define_insn "*rotlsi3_internal11"
4144 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4145 (compare:CC (zero_extend:SI
4146 (subreg:HI
4147 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4148 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4149 (const_int 0)))
4150 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4151 ""
4152 "@
4153 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4154 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4155 #
4156 #"
4157 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4158 (set_attr "length" "4,4,8,8")])
4160 (define_split
4161 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4162 (compare:CC (zero_extend:SI
4163 (subreg:HI
4164 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4165 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4166 (const_int 0)))
4167 (clobber (match_scratch:SI 3 ""))]
4168 "reload_completed"
4169 [(set (match_dup 3)
4170 (zero_extend:SI (subreg:HI
4171 (rotate:SI (match_dup 1)
4172 (match_dup 2)) 0)))
4173 (set (match_dup 0)
4174 (compare:CC (match_dup 3)
4175 (const_int 0)))]
4176 "")
4178 (define_insn "*rotlsi3_internal12"
4179 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4180 (compare:CC (zero_extend:SI
4181 (subreg:HI
4182 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4183 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4184 (const_int 0)))
4185 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4186 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4187 ""
4188 "@
4189 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4190 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4191 #
4192 #"
4193 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4194 (set_attr "length" "4,4,8,8")])
4196 (define_split
4197 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4198 (compare:CC (zero_extend:SI
4199 (subreg:HI
4200 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4201 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4202 (const_int 0)))
4203 (set (match_operand:SI 0 "gpc_reg_operand" "")
4204 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4205 "reload_completed"
4206 [(set (match_dup 0)
4207 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4208 (set (match_dup 3)
4209 (compare:CC (match_dup 0)
4210 (const_int 0)))]
4211 "")
4213 ;; Note that we use "sle." instead of "sl." so that we can set
4214 ;; SHIFT_COUNT_TRUNCATED.
4216 (define_expand "ashlsi3"
4217 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4218 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4219 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4220 ""
4221 "
4222 {
4223 if (TARGET_POWER)
4224 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4225 else
4226 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4227 DONE;
4228 }")
4230 (define_insn "ashlsi3_power"
4231 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4232 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4233 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4234 (clobber (match_scratch:SI 3 "=q,X"))]
4235 "TARGET_POWER"
4236 "@
4237 sle %0,%1,%2
4238 {sli|slwi} %0,%1,%h2")
4240 (define_insn "ashlsi3_no_power"
4241 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4242 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4243 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4244 "! TARGET_POWER"
4245 "@
4246 {sl|slw} %0,%1,%2
4247 {sli|slwi} %0,%1,%h2"
4248 [(set_attr "type" "var_shift_rotate,shift")])
4250 (define_insn ""
4251 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4252 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4253 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4254 (const_int 0)))
4255 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4256 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4257 "TARGET_POWER"
4258 "@
4259 sle. %3,%1,%2
4260 {sli.|slwi.} %3,%1,%h2
4261 #
4262 #"
4263 [(set_attr "type" "delayed_compare")
4264 (set_attr "length" "4,4,8,8")])
4266 (define_split
4267 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4268 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4269 (match_operand:SI 2 "reg_or_cint_operand" ""))
4270 (const_int 0)))
4271 (clobber (match_scratch:SI 3 ""))
4272 (clobber (match_scratch:SI 4 ""))]
4273 "TARGET_POWER && reload_completed"
4274 [(parallel [(set (match_dup 3)
4275 (ashift:SI (match_dup 1) (match_dup 2)))
4276 (clobber (match_dup 4))])
4277 (set (match_dup 0)
4278 (compare:CC (match_dup 3)
4279 (const_int 0)))]
4280 "")
4282 (define_insn ""
4283 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4284 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4285 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4286 (const_int 0)))
4287 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4288 "! TARGET_POWER && TARGET_32BIT"
4289 "@
4290 {sl.|slw.} %3,%1,%2
4291 {sli.|slwi.} %3,%1,%h2
4292 #
4293 #"
4294 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4295 (set_attr "length" "4,4,8,8")])
4297 (define_split
4298 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4299 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4300 (match_operand:SI 2 "reg_or_cint_operand" ""))
4301 (const_int 0)))
4302 (clobber (match_scratch:SI 3 ""))]
4303 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4304 [(set (match_dup 3)
4305 (ashift:SI (match_dup 1) (match_dup 2)))
4306 (set (match_dup 0)
4307 (compare:CC (match_dup 3)
4308 (const_int 0)))]
4309 "")
4311 (define_insn ""
4312 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4313 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4314 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4315 (const_int 0)))
4316 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4317 (ashift:SI (match_dup 1) (match_dup 2)))
4318 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4319 "TARGET_POWER"
4320 "@
4321 sle. %0,%1,%2
4322 {sli.|slwi.} %0,%1,%h2
4323 #
4324 #"
4325 [(set_attr "type" "delayed_compare")
4326 (set_attr "length" "4,4,8,8")])
4328 (define_split
4329 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4330 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4331 (match_operand:SI 2 "reg_or_cint_operand" ""))
4332 (const_int 0)))
4333 (set (match_operand:SI 0 "gpc_reg_operand" "")
4334 (ashift:SI (match_dup 1) (match_dup 2)))
4335 (clobber (match_scratch:SI 4 ""))]
4336 "TARGET_POWER && reload_completed"
4337 [(parallel [(set (match_dup 0)
4338 (ashift:SI (match_dup 1) (match_dup 2)))
4339 (clobber (match_dup 4))])
4340 (set (match_dup 3)
4341 (compare:CC (match_dup 0)
4342 (const_int 0)))]
4343 "")
4345 (define_insn ""
4346 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4347 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4348 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4349 (const_int 0)))
4350 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4351 (ashift:SI (match_dup 1) (match_dup 2)))]
4352 "! TARGET_POWER && TARGET_32BIT"
4353 "@
4354 {sl.|slw.} %0,%1,%2
4355 {sli.|slwi.} %0,%1,%h2
4356 #
4357 #"
4358 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4359 (set_attr "length" "4,4,8,8")])
4361 (define_split
4362 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4363 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4364 (match_operand:SI 2 "reg_or_cint_operand" ""))
4365 (const_int 0)))
4366 (set (match_operand:SI 0 "gpc_reg_operand" "")
4367 (ashift:SI (match_dup 1) (match_dup 2)))]
4368 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4369 [(set (match_dup 0)
4370 (ashift:SI (match_dup 1) (match_dup 2)))
4371 (set (match_dup 3)
4372 (compare:CC (match_dup 0)
4373 (const_int 0)))]
4374 "")
4376 (define_insn "rlwinm"
4377 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4378 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4379 (match_operand:SI 2 "const_int_operand" "i"))
4380 (match_operand:SI 3 "mask_operand" "n")))]
4381 "includes_lshift_p (operands[2], operands[3])"
4382 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4384 (define_insn ""
4385 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4386 (compare:CC
4387 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4388 (match_operand:SI 2 "const_int_operand" "i,i"))
4389 (match_operand:SI 3 "mask_operand" "n,n"))
4390 (const_int 0)))
4391 (clobber (match_scratch:SI 4 "=r,r"))]
4392 "includes_lshift_p (operands[2], operands[3])"
4393 "@
4394 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4395 #"
4396 [(set_attr "type" "delayed_compare")
4397 (set_attr "length" "4,8")])
4399 (define_split
4400 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4401 (compare:CC
4402 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4403 (match_operand:SI 2 "const_int_operand" ""))
4404 (match_operand:SI 3 "mask_operand" ""))
4405 (const_int 0)))
4406 (clobber (match_scratch:SI 4 ""))]
4407 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4408 [(set (match_dup 4)
4409 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4410 (match_dup 3)))
4411 (set (match_dup 0)
4412 (compare:CC (match_dup 4)
4413 (const_int 0)))]
4414 "")
4416 (define_insn ""
4417 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4418 (compare:CC
4419 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4420 (match_operand:SI 2 "const_int_operand" "i,i"))
4421 (match_operand:SI 3 "mask_operand" "n,n"))
4422 (const_int 0)))
4423 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4424 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4425 "includes_lshift_p (operands[2], operands[3])"
4426 "@
4427 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4428 #"
4429 [(set_attr "type" "delayed_compare")
4430 (set_attr "length" "4,8")])
4432 (define_split
4433 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4434 (compare:CC
4435 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4436 (match_operand:SI 2 "const_int_operand" ""))
4437 (match_operand:SI 3 "mask_operand" ""))
4438 (const_int 0)))
4439 (set (match_operand:SI 0 "gpc_reg_operand" "")
4440 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4441 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4442 [(set (match_dup 0)
4443 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4444 (set (match_dup 4)
4445 (compare:CC (match_dup 0)
4446 (const_int 0)))]
4447 "")
4449 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4450 ;; "sli x,x,0".
4451 (define_expand "lshrsi3"
4452 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4453 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4454 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4455 ""
4456 "
4457 {
4458 if (TARGET_POWER)
4459 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4460 else
4461 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4462 DONE;
4463 }")
4465 (define_insn "lshrsi3_power"
4466 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4467 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4468 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4469 (clobber (match_scratch:SI 3 "=q,X,X"))]
4470 "TARGET_POWER"
4471 "@
4472 sre %0,%1,%2
4473 mr %0,%1
4474 {s%A2i|s%A2wi} %0,%1,%h2")
4476 (define_insn "lshrsi3_no_power"
4477 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4478 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4479 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4480 "! TARGET_POWER"
4481 "@
4482 mr %0,%1
4483 {sr|srw} %0,%1,%2
4484 {sri|srwi} %0,%1,%h2"
4485 [(set_attr "type" "integer,var_shift_rotate,shift")])
4487 (define_insn ""
4488 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4489 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4490 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4491 (const_int 0)))
4492 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4493 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4494 "TARGET_POWER"
4495 "@
4496 sre. %3,%1,%2
4497 mr. %1,%1
4498 {s%A2i.|s%A2wi.} %3,%1,%h2
4499 #
4500 #
4501 #"
4502 [(set_attr "type" "delayed_compare")
4503 (set_attr "length" "4,4,4,8,8,8")])
4505 (define_split
4506 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4507 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4508 (match_operand:SI 2 "reg_or_cint_operand" ""))
4509 (const_int 0)))
4510 (clobber (match_scratch:SI 3 ""))
4511 (clobber (match_scratch:SI 4 ""))]
4512 "TARGET_POWER && reload_completed"
4513 [(parallel [(set (match_dup 3)
4514 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4515 (clobber (match_dup 4))])
4516 (set (match_dup 0)
4517 (compare:CC (match_dup 3)
4518 (const_int 0)))]
4519 "")
4521 (define_insn ""
4522 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4523 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4524 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4525 (const_int 0)))
4526 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4527 "! TARGET_POWER && TARGET_32BIT"
4528 "@
4529 mr. %1,%1
4530 {sr.|srw.} %3,%1,%2
4531 {sri.|srwi.} %3,%1,%h2
4532 #
4533 #
4534 #"
4535 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4536 (set_attr "length" "4,4,4,8,8,8")])
4538 (define_split
4539 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4540 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4541 (match_operand:SI 2 "reg_or_cint_operand" ""))
4542 (const_int 0)))
4543 (clobber (match_scratch:SI 3 ""))]
4544 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4545 [(set (match_dup 3)
4546 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4547 (set (match_dup 0)
4548 (compare:CC (match_dup 3)
4549 (const_int 0)))]
4550 "")
4552 (define_insn ""
4553 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4554 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4555 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4556 (const_int 0)))
4557 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4558 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4559 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4560 "TARGET_POWER"
4561 "@
4562 sre. %0,%1,%2
4563 mr. %0,%1
4564 {s%A2i.|s%A2wi.} %0,%1,%h2
4565 #
4566 #
4567 #"
4568 [(set_attr "type" "delayed_compare")
4569 (set_attr "length" "4,4,4,8,8,8")])
4571 (define_split
4572 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4573 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4574 (match_operand:SI 2 "reg_or_cint_operand" ""))
4575 (const_int 0)))
4576 (set (match_operand:SI 0 "gpc_reg_operand" "")
4577 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4578 (clobber (match_scratch:SI 4 ""))]
4579 "TARGET_POWER && reload_completed"
4580 [(parallel [(set (match_dup 0)
4581 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4582 (clobber (match_dup 4))])
4583 (set (match_dup 3)
4584 (compare:CC (match_dup 0)
4585 (const_int 0)))]
4586 "")
4588 (define_insn ""
4589 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4590 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4591 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4592 (const_int 0)))
4593 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4594 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4595 "! TARGET_POWER && TARGET_32BIT"
4596 "@
4597 mr. %0,%1
4598 {sr.|srw.} %0,%1,%2
4599 {sri.|srwi.} %0,%1,%h2
4600 #
4601 #
4602 #"
4603 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4604 (set_attr "length" "4,4,4,8,8,8")])
4606 (define_split
4607 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4608 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4609 (match_operand:SI 2 "reg_or_cint_operand" ""))
4610 (const_int 0)))
4611 (set (match_operand:SI 0 "gpc_reg_operand" "")
4612 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4613 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4614 [(set (match_dup 0)
4615 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4616 (set (match_dup 3)
4617 (compare:CC (match_dup 0)
4618 (const_int 0)))]
4619 "")
4621 (define_insn ""
4622 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4623 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4624 (match_operand:SI 2 "const_int_operand" "i"))
4625 (match_operand:SI 3 "mask_operand" "n")))]
4626 "includes_rshift_p (operands[2], operands[3])"
4627 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4629 (define_insn ""
4630 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4631 (compare:CC
4632 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4633 (match_operand:SI 2 "const_int_operand" "i,i"))
4634 (match_operand:SI 3 "mask_operand" "n,n"))
4635 (const_int 0)))
4636 (clobber (match_scratch:SI 4 "=r,r"))]
4637 "includes_rshift_p (operands[2], operands[3])"
4638 "@
4639 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4640 #"
4641 [(set_attr "type" "delayed_compare")
4642 (set_attr "length" "4,8")])
4644 (define_split
4645 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4646 (compare:CC
4647 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4648 (match_operand:SI 2 "const_int_operand" ""))
4649 (match_operand:SI 3 "mask_operand" ""))
4650 (const_int 0)))
4651 (clobber (match_scratch:SI 4 ""))]
4652 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4653 [(set (match_dup 4)
4654 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4655 (match_dup 3)))
4656 (set (match_dup 0)
4657 (compare:CC (match_dup 4)
4658 (const_int 0)))]
4659 "")
4661 (define_insn ""
4662 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4663 (compare:CC
4664 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4665 (match_operand:SI 2 "const_int_operand" "i,i"))
4666 (match_operand:SI 3 "mask_operand" "n,n"))
4667 (const_int 0)))
4668 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4669 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4670 "includes_rshift_p (operands[2], operands[3])"
4671 "@
4672 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4673 #"
4674 [(set_attr "type" "delayed_compare")
4675 (set_attr "length" "4,8")])
4677 (define_split
4678 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4679 (compare:CC
4680 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4681 (match_operand:SI 2 "const_int_operand" ""))
4682 (match_operand:SI 3 "mask_operand" ""))
4683 (const_int 0)))
4684 (set (match_operand:SI 0 "gpc_reg_operand" "")
4685 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4686 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4687 [(set (match_dup 0)
4688 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4689 (set (match_dup 4)
4690 (compare:CC (match_dup 0)
4691 (const_int 0)))]
4692 "")
4694 (define_insn ""
4695 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4696 (zero_extend:SI
4697 (subreg:QI
4698 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4699 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4700 "includes_rshift_p (operands[2], GEN_INT (255))"
4701 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4703 (define_insn ""
4704 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4705 (compare:CC
4706 (zero_extend:SI
4707 (subreg:QI
4708 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4709 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4710 (const_int 0)))
4711 (clobber (match_scratch:SI 3 "=r,r"))]
4712 "includes_rshift_p (operands[2], GEN_INT (255))"
4713 "@
4714 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4715 #"
4716 [(set_attr "type" "delayed_compare")
4717 (set_attr "length" "4,8")])
4719 (define_split
4720 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4721 (compare:CC
4722 (zero_extend:SI
4723 (subreg:QI
4724 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4725 (match_operand:SI 2 "const_int_operand" "")) 0))
4726 (const_int 0)))
4727 (clobber (match_scratch:SI 3 ""))]
4728 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4729 [(set (match_dup 3)
4730 (zero_extend:SI (subreg:QI
4731 (lshiftrt:SI (match_dup 1)
4732 (match_dup 2)) 0)))
4733 (set (match_dup 0)
4734 (compare:CC (match_dup 3)
4735 (const_int 0)))]
4736 "")
4738 (define_insn ""
4739 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4740 (compare:CC
4741 (zero_extend:SI
4742 (subreg:QI
4743 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4744 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4745 (const_int 0)))
4746 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4747 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4748 "includes_rshift_p (operands[2], GEN_INT (255))"
4749 "@
4750 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4751 #"
4752 [(set_attr "type" "delayed_compare")
4753 (set_attr "length" "4,8")])
4755 (define_split
4756 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4757 (compare:CC
4758 (zero_extend:SI
4759 (subreg:QI
4760 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4761 (match_operand:SI 2 "const_int_operand" "")) 0))
4762 (const_int 0)))
4763 (set (match_operand:SI 0 "gpc_reg_operand" "")
4764 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4765 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4766 [(set (match_dup 0)
4767 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4768 (set (match_dup 3)
4769 (compare:CC (match_dup 0)
4770 (const_int 0)))]
4771 "")
4773 (define_insn ""
4774 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4775 (zero_extend:SI
4776 (subreg:HI
4777 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4778 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4779 "includes_rshift_p (operands[2], GEN_INT (65535))"
4780 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4782 (define_insn ""
4783 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4784 (compare:CC
4785 (zero_extend:SI
4786 (subreg:HI
4787 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4788 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4789 (const_int 0)))
4790 (clobber (match_scratch:SI 3 "=r,r"))]
4791 "includes_rshift_p (operands[2], GEN_INT (65535))"
4792 "@
4793 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4794 #"
4795 [(set_attr "type" "delayed_compare")
4796 (set_attr "length" "4,8")])
4798 (define_split
4799 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4800 (compare:CC
4801 (zero_extend:SI
4802 (subreg:HI
4803 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4804 (match_operand:SI 2 "const_int_operand" "")) 0))
4805 (const_int 0)))
4806 (clobber (match_scratch:SI 3 ""))]
4807 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4808 [(set (match_dup 3)
4809 (zero_extend:SI (subreg:HI
4810 (lshiftrt:SI (match_dup 1)
4811 (match_dup 2)) 0)))
4812 (set (match_dup 0)
4813 (compare:CC (match_dup 3)
4814 (const_int 0)))]
4815 "")
4817 (define_insn ""
4818 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4819 (compare:CC
4820 (zero_extend:SI
4821 (subreg:HI
4822 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4823 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4824 (const_int 0)))
4825 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4826 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4827 "includes_rshift_p (operands[2], GEN_INT (65535))"
4828 "@
4829 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4830 #"
4831 [(set_attr "type" "delayed_compare")
4832 (set_attr "length" "4,8")])
4834 (define_split
4835 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4836 (compare:CC
4837 (zero_extend:SI
4838 (subreg:HI
4839 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4840 (match_operand:SI 2 "const_int_operand" "")) 0))
4841 (const_int 0)))
4842 (set (match_operand:SI 0 "gpc_reg_operand" "")
4843 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4844 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4845 [(set (match_dup 0)
4846 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4847 (set (match_dup 3)
4848 (compare:CC (match_dup 0)
4849 (const_int 0)))]
4850 "")
4852 (define_insn ""
4853 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4854 (const_int 1)
4855 (match_operand:SI 1 "gpc_reg_operand" "r"))
4856 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4857 (const_int 31)))]
4858 "TARGET_POWER"
4859 "rrib %0,%1,%2")
4861 (define_insn ""
4862 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4863 (const_int 1)
4864 (match_operand:SI 1 "gpc_reg_operand" "r"))
4865 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4866 (const_int 31)))]
4867 "TARGET_POWER"
4868 "rrib %0,%1,%2")
4870 (define_insn ""
4871 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4872 (const_int 1)
4873 (match_operand:SI 1 "gpc_reg_operand" "r"))
4874 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4875 (const_int 1)
4876 (const_int 0)))]
4877 "TARGET_POWER"
4878 "rrib %0,%1,%2")
4880 (define_expand "ashrsi3"
4881 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4882 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4883 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4884 ""
4885 "
4886 {
4887 if (TARGET_POWER)
4888 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4889 else
4890 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4891 DONE;
4892 }")
4894 (define_insn "ashrsi3_power"
4895 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4896 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4897 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4898 (clobber (match_scratch:SI 3 "=q,X"))]
4899 "TARGET_POWER"
4900 "@
4901 srea %0,%1,%2
4902 {srai|srawi} %0,%1,%h2"
4903 [(set_attr "type" "shift")])
4905 (define_insn "ashrsi3_no_power"
4906 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4907 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4908 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4909 "! TARGET_POWER"
4910 "@
4911 {sra|sraw} %0,%1,%2
4912 {srai|srawi} %0,%1,%h2"
4913 [(set_attr "type" "var_shift_rotate,shift")])
4915 (define_insn ""
4916 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4917 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4918 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4919 (const_int 0)))
4920 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4921 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4922 "TARGET_POWER"
4923 "@
4924 srea. %3,%1,%2
4925 {srai.|srawi.} %3,%1,%h2
4926 #
4927 #"
4928 [(set_attr "type" "delayed_compare")
4929 (set_attr "length" "4,4,8,8")])
4931 (define_split
4932 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4933 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4934 (match_operand:SI 2 "reg_or_cint_operand" ""))
4935 (const_int 0)))
4936 (clobber (match_scratch:SI 3 ""))
4937 (clobber (match_scratch:SI 4 ""))]
4938 "TARGET_POWER && reload_completed"
4939 [(parallel [(set (match_dup 3)
4940 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4941 (clobber (match_dup 4))])
4942 (set (match_dup 0)
4943 (compare:CC (match_dup 3)
4944 (const_int 0)))]
4945 "")
4947 (define_insn ""
4948 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4949 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4950 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4951 (const_int 0)))
4952 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4953 "! TARGET_POWER"
4954 "@
4955 {sra.|sraw.} %3,%1,%2
4956 {srai.|srawi.} %3,%1,%h2
4957 #
4958 #"
4959 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4960 (set_attr "length" "4,4,8,8")])
4962 (define_split
4963 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4964 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4965 (match_operand:SI 2 "reg_or_cint_operand" ""))
4966 (const_int 0)))
4967 (clobber (match_scratch:SI 3 ""))]
4968 "! TARGET_POWER && reload_completed"
4969 [(set (match_dup 3)
4970 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4971 (set (match_dup 0)
4972 (compare:CC (match_dup 3)
4973 (const_int 0)))]
4974 "")
4976 (define_insn ""
4977 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4978 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4979 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4980 (const_int 0)))
4981 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4982 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4983 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4984 "TARGET_POWER"
4985 "@
4986 srea. %0,%1,%2
4987 {srai.|srawi.} %0,%1,%h2
4988 #
4989 #"
4990 [(set_attr "type" "delayed_compare")
4991 (set_attr "length" "4,4,8,8")])
4993 (define_split
4994 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4995 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4996 (match_operand:SI 2 "reg_or_cint_operand" ""))
4997 (const_int 0)))
4998 (set (match_operand:SI 0 "gpc_reg_operand" "")
4999 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5000 (clobber (match_scratch:SI 4 ""))]
5001 "TARGET_POWER && reload_completed"
5002 [(parallel [(set (match_dup 0)
5003 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5004 (clobber (match_dup 4))])
5005 (set (match_dup 3)
5006 (compare:CC (match_dup 0)
5007 (const_int 0)))]
5008 "")
5010 (define_insn ""
5011 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5012 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5013 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5014 (const_int 0)))
5015 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5016 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5017 "! TARGET_POWER"
5018 "@
5019 {sra.|sraw.} %0,%1,%2
5020 {srai.|srawi.} %0,%1,%h2
5021 #
5022 #"
5023 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5024 (set_attr "length" "4,4,8,8")])
5025 \f
5026 (define_split
5027 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5028 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5029 (match_operand:SI 2 "reg_or_cint_operand" ""))
5030 (const_int 0)))
5031 (set (match_operand:SI 0 "gpc_reg_operand" "")
5032 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5033 "! TARGET_POWER && reload_completed"
5034 [(set (match_dup 0)
5035 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5036 (set (match_dup 3)
5037 (compare:CC (match_dup 0)
5038 (const_int 0)))]
5039 "")
5041 ;; Floating-point insns, excluding normal data motion.
5042 ;;
5043 ;; PowerPC has a full set of single-precision floating point instructions.
5044 ;;
5045 ;; For the POWER architecture, we pretend that we have both SFmode and
5046 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5047 ;; The only conversions we will do will be when storing to memory. In that
5048 ;; case, we will use the "frsp" instruction before storing.
5049 ;;
5050 ;; Note that when we store into a single-precision memory location, we need to
5051 ;; use the frsp insn first. If the register being stored isn't dead, we
5052 ;; need a scratch register for the frsp. But this is difficult when the store
5053 ;; is done by reload. It is not incorrect to do the frsp on the register in
5054 ;; this case, we just lose precision that we would have otherwise gotten but
5055 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5057 (define_expand "extendsfdf2"
5058 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5059 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5060 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5061 "")
5063 (define_insn_and_split "*extendsfdf2_fpr"
5064 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
5065 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5066 "TARGET_HARD_FLOAT && TARGET_FPRS"
5067 "@
5068 #
5069 fmr %0,%1
5070 lfs%U1%X1 %0,%1"
5071 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5072 [(const_int 0)]
5073 {
5074 emit_note (NOTE_INSN_DELETED);
5075 DONE;
5076 }
5077 [(set_attr "type" "fp,fp,fpload")])
5079 (define_expand "truncdfsf2"
5080 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5081 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5082 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5083 "")
5085 (define_insn "*truncdfsf2_fpr"
5086 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5087 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5088 "TARGET_HARD_FLOAT && TARGET_FPRS"
5089 "frsp %0,%1"
5090 [(set_attr "type" "fp")])
5092 (define_insn "aux_truncdfsf2"
5093 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5094 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5095 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5096 "frsp %0,%1"
5097 [(set_attr "type" "fp")])
5099 (define_expand "negsf2"
5100 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5101 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5102 "TARGET_HARD_FLOAT"
5103 "")
5105 (define_insn "*negsf2"
5106 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5107 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5108 "TARGET_HARD_FLOAT && TARGET_FPRS"
5109 "fneg %0,%1"
5110 [(set_attr "type" "fp")])
5112 (define_expand "abssf2"
5113 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5114 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5115 "TARGET_HARD_FLOAT"
5116 "")
5118 (define_insn "*abssf2"
5119 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5120 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5121 "TARGET_HARD_FLOAT && TARGET_FPRS"
5122 "fabs %0,%1"
5123 [(set_attr "type" "fp")])
5125 (define_insn ""
5126 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5127 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5128 "TARGET_HARD_FLOAT && TARGET_FPRS"
5129 "fnabs %0,%1"
5130 [(set_attr "type" "fp")])
5132 (define_expand "addsf3"
5133 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5134 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5135 (match_operand:SF 2 "gpc_reg_operand" "")))]
5136 "TARGET_HARD_FLOAT"
5137 "")
5139 (define_insn ""
5140 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5141 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5142 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5143 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5144 "fadds %0,%1,%2"
5145 [(set_attr "type" "fp")])
5147 (define_insn ""
5148 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5149 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5150 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5151 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5152 "{fa|fadd} %0,%1,%2"
5153 [(set_attr "type" "fp")])
5155 (define_expand "subsf3"
5156 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5157 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5158 (match_operand:SF 2 "gpc_reg_operand" "")))]
5159 "TARGET_HARD_FLOAT"
5160 "")
5162 (define_insn ""
5163 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5164 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5165 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5166 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5167 "fsubs %0,%1,%2"
5168 [(set_attr "type" "fp")])
5170 (define_insn ""
5171 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5172 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5173 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5174 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5175 "{fs|fsub} %0,%1,%2"
5176 [(set_attr "type" "fp")])
5178 (define_expand "mulsf3"
5179 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5180 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5181 (match_operand:SF 2 "gpc_reg_operand" "")))]
5182 "TARGET_HARD_FLOAT"
5183 "")
5185 (define_insn ""
5186 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5187 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5188 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5189 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5190 "fmuls %0,%1,%2"
5191 [(set_attr "type" "fp")])
5193 (define_insn ""
5194 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5195 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5196 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5197 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5198 "{fm|fmul} %0,%1,%2"
5199 [(set_attr "type" "dmul")])
5201 (define_expand "divsf3"
5202 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5203 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5204 (match_operand:SF 2 "gpc_reg_operand" "")))]
5205 "TARGET_HARD_FLOAT"
5206 "")
5208 (define_insn ""
5209 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5210 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5211 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5212 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5213 "fdivs %0,%1,%2"
5214 [(set_attr "type" "sdiv")])
5216 (define_insn ""
5217 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5218 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5219 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5220 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5221 "{fd|fdiv} %0,%1,%2"
5222 [(set_attr "type" "ddiv")])
5224 (define_expand "recipsf3"
5225 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5226 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")
5227 (match_operand:SF 2 "gpc_reg_operand" "f")]
5228 UNSPEC_FRES))]
5229 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5230 && flag_finite_math_only && !flag_trapping_math"
5231 {
5232 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5233 DONE;
5234 })
5236 (define_insn "fres"
5237 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5238 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5239 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5240 "fres %0,%1"
5241 [(set_attr "type" "fp")])
5243 (define_insn ""
5244 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5245 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5246 (match_operand:SF 2 "gpc_reg_operand" "f"))
5247 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5248 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5249 "fmadds %0,%1,%2,%3"
5250 [(set_attr "type" "fp")])
5252 (define_insn ""
5253 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5254 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5255 (match_operand:SF 2 "gpc_reg_operand" "f"))
5256 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5257 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5258 "{fma|fmadd} %0,%1,%2,%3"
5259 [(set_attr "type" "dmul")])
5261 (define_insn ""
5262 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5263 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5264 (match_operand:SF 2 "gpc_reg_operand" "f"))
5265 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5266 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5267 "fmsubs %0,%1,%2,%3"
5268 [(set_attr "type" "fp")])
5270 (define_insn ""
5271 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5272 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5273 (match_operand:SF 2 "gpc_reg_operand" "f"))
5274 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5275 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5276 "{fms|fmsub} %0,%1,%2,%3"
5277 [(set_attr "type" "dmul")])
5279 (define_insn ""
5280 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5281 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5282 (match_operand:SF 2 "gpc_reg_operand" "f"))
5283 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5284 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5285 && HONOR_SIGNED_ZEROS (SFmode)"
5286 "fnmadds %0,%1,%2,%3"
5287 [(set_attr "type" "fp")])
5289 (define_insn ""
5290 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5291 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5292 (match_operand:SF 2 "gpc_reg_operand" "f"))
5293 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5294 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5295 && ! HONOR_SIGNED_ZEROS (SFmode)"
5296 "fnmadds %0,%1,%2,%3"
5297 [(set_attr "type" "fp")])
5299 (define_insn ""
5300 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5301 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5302 (match_operand:SF 2 "gpc_reg_operand" "f"))
5303 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5304 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5305 "{fnma|fnmadd} %0,%1,%2,%3"
5306 [(set_attr "type" "dmul")])
5308 (define_insn ""
5309 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5310 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5311 (match_operand:SF 2 "gpc_reg_operand" "f"))
5312 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5313 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5314 && ! HONOR_SIGNED_ZEROS (SFmode)"
5315 "{fnma|fnmadd} %0,%1,%2,%3"
5316 [(set_attr "type" "dmul")])
5318 (define_insn ""
5319 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5320 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5321 (match_operand:SF 2 "gpc_reg_operand" "f"))
5322 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5323 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5324 && HONOR_SIGNED_ZEROS (SFmode)"
5325 "fnmsubs %0,%1,%2,%3"
5326 [(set_attr "type" "fp")])
5328 (define_insn ""
5329 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5330 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5331 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5332 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5333 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5334 && ! HONOR_SIGNED_ZEROS (SFmode)"
5335 "fnmsubs %0,%1,%2,%3"
5336 [(set_attr "type" "fp")])
5338 (define_insn ""
5339 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5340 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5341 (match_operand:SF 2 "gpc_reg_operand" "f"))
5342 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5343 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5344 "{fnms|fnmsub} %0,%1,%2,%3"
5345 [(set_attr "type" "dmul")])
5347 (define_insn ""
5348 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5349 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5350 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5351 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5352 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5353 && ! HONOR_SIGNED_ZEROS (SFmode)"
5354 "{fnms|fnmsub} %0,%1,%2,%3"
5355 [(set_attr "type" "dmul")])
5357 (define_expand "sqrtsf2"
5358 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5359 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5360 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5361 "")
5363 (define_insn ""
5364 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5365 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5366 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5367 "fsqrts %0,%1"
5368 [(set_attr "type" "ssqrt")])
5370 (define_insn ""
5371 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5372 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5373 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
5374 "fsqrt %0,%1"
5375 [(set_attr "type" "dsqrt")])
5377 (define_expand "rsqrtsf2"
5378 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5379 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5380 UNSPEC_RSQRT))]
5381 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5382 && flag_finite_math_only && !flag_trapping_math"
5383 {
5384 rs6000_emit_swrsqrtsf (operands[0], operands[1]);
5385 DONE;
5386 })
5388 (define_insn "*rsqrt_internal1"
5389 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5390 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5391 UNSPEC_RSQRT))]
5392 "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
5393 "frsqrte %0,%1"
5394 [(set_attr "type" "fp")])
5396 (define_expand "copysignsf3"
5397 [(set (match_dup 3)
5398 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5399 (set (match_dup 4)
5400 (neg:SF (abs:SF (match_dup 1))))
5401 (set (match_operand:SF 0 "gpc_reg_operand" "")
5402 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5403 (match_dup 5))
5404 (match_dup 3)
5405 (match_dup 4)))]
5406 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5407 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5408 {
5409 operands[3] = gen_reg_rtx (SFmode);
5410 operands[4] = gen_reg_rtx (SFmode);
5411 operands[5] = CONST0_RTX (SFmode);
5412 })
5414 (define_expand "copysigndf3"
5415 [(set (match_dup 3)
5416 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5417 (set (match_dup 4)
5418 (neg:DF (abs:DF (match_dup 1))))
5419 (set (match_operand:DF 0 "gpc_reg_operand" "")
5420 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5421 (match_dup 5))
5422 (match_dup 3)
5423 (match_dup 4)))]
5424 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5425 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5426 {
5427 operands[3] = gen_reg_rtx (DFmode);
5428 operands[4] = gen_reg_rtx (DFmode);
5429 operands[5] = CONST0_RTX (DFmode);
5430 })
5432 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5433 ;; fsel instruction and some auxiliary computations. Then we just have a
5434 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5435 ;; combine.
5436 (define_expand "smaxsf3"
5437 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5438 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5439 (match_operand:SF 2 "gpc_reg_operand" ""))
5440 (match_dup 1)
5441 (match_dup 2)))]
5442 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5443 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5445 (define_expand "sminsf3"
5446 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5447 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5448 (match_operand:SF 2 "gpc_reg_operand" ""))
5449 (match_dup 2)
5450 (match_dup 1)))]
5451 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5452 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5454 (define_split
5455 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5456 (match_operator:SF 3 "min_max_operator"
5457 [(match_operand:SF 1 "gpc_reg_operand" "")
5458 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5459 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5460 [(const_int 0)]
5461 "
5462 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5463 operands[1], operands[2]);
5464 DONE;
5465 }")
5467 (define_expand "movsicc"
5468 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5469 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5470 (match_operand:SI 2 "gpc_reg_operand" "")
5471 (match_operand:SI 3 "gpc_reg_operand" "")))]
5472 "TARGET_ISEL"
5473 "
5474 {
5475 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5476 DONE;
5477 else
5478 FAIL;
5479 }")
5481 ;; We use the BASE_REGS for the isel input operands because, if rA is
5482 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5483 ;; because we may switch the operands and rB may end up being rA.
5484 ;;
5485 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5486 ;; leave out the mode in operand 4 and use one pattern, but reload can
5487 ;; change the mode underneath our feet and then gets confused trying
5488 ;; to reload the value.
5489 (define_insn "isel_signed"
5490 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5491 (if_then_else:SI
5492 (match_operator 1 "comparison_operator"
5493 [(match_operand:CC 4 "cc_reg_operand" "y")
5494 (const_int 0)])
5495 (match_operand:SI 2 "gpc_reg_operand" "b")
5496 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5497 "TARGET_ISEL"
5498 "*
5499 { return output_isel (operands); }"
5500 [(set_attr "length" "4")])
5502 (define_insn "isel_unsigned"
5503 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5504 (if_then_else:SI
5505 (match_operator 1 "comparison_operator"
5506 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5507 (const_int 0)])
5508 (match_operand:SI 2 "gpc_reg_operand" "b")
5509 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5510 "TARGET_ISEL"
5511 "*
5512 { return output_isel (operands); }"
5513 [(set_attr "length" "4")])
5515 (define_expand "movsfcc"
5516 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5517 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5518 (match_operand:SF 2 "gpc_reg_operand" "")
5519 (match_operand:SF 3 "gpc_reg_operand" "")))]
5520 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5521 "
5522 {
5523 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5524 DONE;
5525 else
5526 FAIL;
5527 }")
5529 (define_insn "*fselsfsf4"
5530 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5531 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5532 (match_operand:SF 4 "zero_fp_constant" "F"))
5533 (match_operand:SF 2 "gpc_reg_operand" "f")
5534 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5535 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5536 "fsel %0,%1,%2,%3"
5537 [(set_attr "type" "fp")])
5539 (define_insn "*fseldfsf4"
5540 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5541 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5542 (match_operand:DF 4 "zero_fp_constant" "F"))
5543 (match_operand:SF 2 "gpc_reg_operand" "f")
5544 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5545 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5546 "fsel %0,%1,%2,%3"
5547 [(set_attr "type" "fp")])
5549 (define_expand "negdf2"
5550 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5551 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5552 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5553 "")
5555 (define_insn "*negdf2_fpr"
5556 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5557 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5558 "TARGET_HARD_FLOAT && TARGET_FPRS"
5559 "fneg %0,%1"
5560 [(set_attr "type" "fp")])
5562 (define_expand "absdf2"
5563 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5564 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5565 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5566 "")
5568 (define_insn "*absdf2_fpr"
5569 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5570 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5571 "TARGET_HARD_FLOAT && TARGET_FPRS"
5572 "fabs %0,%1"
5573 [(set_attr "type" "fp")])
5575 (define_insn "*nabsdf2_fpr"
5576 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5577 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
5578 "TARGET_HARD_FLOAT && TARGET_FPRS"
5579 "fnabs %0,%1"
5580 [(set_attr "type" "fp")])
5582 (define_expand "adddf3"
5583 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5584 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5585 (match_operand:DF 2 "gpc_reg_operand" "")))]
5586 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5587 "")
5589 (define_insn "*adddf3_fpr"
5590 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5591 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5592 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5593 "TARGET_HARD_FLOAT && TARGET_FPRS"
5594 "{fa|fadd} %0,%1,%2"
5595 [(set_attr "type" "fp")])
5597 (define_expand "subdf3"
5598 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5599 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5600 (match_operand:DF 2 "gpc_reg_operand" "")))]
5601 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5602 "")
5604 (define_insn "*subdf3_fpr"
5605 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5606 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5607 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5608 "TARGET_HARD_FLOAT && TARGET_FPRS"
5609 "{fs|fsub} %0,%1,%2"
5610 [(set_attr "type" "fp")])
5612 (define_expand "muldf3"
5613 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5614 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5615 (match_operand:DF 2 "gpc_reg_operand" "")))]
5616 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5617 "")
5619 (define_insn "*muldf3_fpr"
5620 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5621 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5622 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5623 "TARGET_HARD_FLOAT && TARGET_FPRS"
5624 "{fm|fmul} %0,%1,%2"
5625 [(set_attr "type" "dmul")])
5627 (define_expand "divdf3"
5628 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5629 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5630 (match_operand:DF 2 "gpc_reg_operand" "")))]
5631 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5632 "")
5634 (define_insn "*divdf3_fpr"
5635 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5636 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5637 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5638 "TARGET_HARD_FLOAT && TARGET_FPRS"
5639 "{fd|fdiv} %0,%1,%2"
5640 [(set_attr "type" "ddiv")])
5642 (define_expand "recipdf3"
5643 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5644 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")
5645 (match_operand:DF 2 "gpc_reg_operand" "f")]
5646 UNSPEC_FRES))]
5647 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size
5648 && flag_finite_math_only && !flag_trapping_math"
5649 {
5650 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5651 DONE;
5652 })
5654 (define_insn "fred"
5655 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5656 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5657 "TARGET_POPCNTB && flag_finite_math_only"
5658 "fre %0,%1"
5659 [(set_attr "type" "fp")])
5661 (define_insn ""
5662 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5663 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5664 (match_operand:DF 2 "gpc_reg_operand" "f"))
5665 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5666 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5667 "{fma|fmadd} %0,%1,%2,%3"
5668 [(set_attr "type" "dmul")])
5670 (define_insn ""
5671 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5672 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5673 (match_operand:DF 2 "gpc_reg_operand" "f"))
5674 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5675 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5676 "{fms|fmsub} %0,%1,%2,%3"
5677 [(set_attr "type" "dmul")])
5679 (define_insn ""
5680 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5681 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5682 (match_operand:DF 2 "gpc_reg_operand" "f"))
5683 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5684 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5685 && HONOR_SIGNED_ZEROS (DFmode)"
5686 "{fnma|fnmadd} %0,%1,%2,%3"
5687 [(set_attr "type" "dmul")])
5689 (define_insn ""
5690 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5691 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5692 (match_operand:DF 2 "gpc_reg_operand" "f"))
5693 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5694 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5695 && ! HONOR_SIGNED_ZEROS (DFmode)"
5696 "{fnma|fnmadd} %0,%1,%2,%3"
5697 [(set_attr "type" "dmul")])
5699 (define_insn ""
5700 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5701 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5702 (match_operand:DF 2 "gpc_reg_operand" "f"))
5703 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5704 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5705 && HONOR_SIGNED_ZEROS (DFmode)"
5706 "{fnms|fnmsub} %0,%1,%2,%3"
5707 [(set_attr "type" "dmul")])
5709 (define_insn ""
5710 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5711 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5712 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5713 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5714 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5715 && ! HONOR_SIGNED_ZEROS (DFmode)"
5716 "{fnms|fnmsub} %0,%1,%2,%3"
5717 [(set_attr "type" "dmul")])
5719 (define_insn "sqrtdf2"
5720 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5721 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5722 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5723 "fsqrt %0,%1"
5724 [(set_attr "type" "dsqrt")])
5726 ;; The conditional move instructions allow us to perform max and min
5727 ;; operations even when
5729 (define_expand "smaxdf3"
5730 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5731 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5732 (match_operand:DF 2 "gpc_reg_operand" ""))
5733 (match_dup 1)
5734 (match_dup 2)))]
5735 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5736 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5738 (define_expand "smindf3"
5739 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5740 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5741 (match_operand:DF 2 "gpc_reg_operand" ""))
5742 (match_dup 2)
5743 (match_dup 1)))]
5744 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5745 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5747 (define_split
5748 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5749 (match_operator:DF 3 "min_max_operator"
5750 [(match_operand:DF 1 "gpc_reg_operand" "")
5751 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5752 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5753 [(const_int 0)]
5754 "
5755 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5756 operands[1], operands[2]);
5757 DONE;
5758 }")
5760 (define_expand "movdfcc"
5761 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5762 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5763 (match_operand:DF 2 "gpc_reg_operand" "")
5764 (match_operand:DF 3 "gpc_reg_operand" "")))]
5765 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5766 "
5767 {
5768 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5769 DONE;
5770 else
5771 FAIL;
5772 }")
5774 (define_insn "*fseldfdf4"
5775 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5776 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5777 (match_operand:DF 4 "zero_fp_constant" "F"))
5778 (match_operand:DF 2 "gpc_reg_operand" "f")
5779 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5780 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5781 "fsel %0,%1,%2,%3"
5782 [(set_attr "type" "fp")])
5784 (define_insn "*fselsfdf4"
5785 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5786 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5787 (match_operand:SF 4 "zero_fp_constant" "F"))
5788 (match_operand:DF 2 "gpc_reg_operand" "f")
5789 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5790 "TARGET_PPC_GFXOPT"
5791 "fsel %0,%1,%2,%3"
5792 [(set_attr "type" "fp")])
5793 \f
5794 ;; Conversions to and from floating-point.
5796 (define_expand "fixuns_truncsfsi2"
5797 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5798 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5799 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5800 "")
5802 (define_expand "fix_truncsfsi2"
5803 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5804 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5805 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5806 "")
5808 ; For each of these conversions, there is a define_expand, a define_insn
5809 ; with a '#' template, and a define_split (with C code). The idea is
5810 ; to allow constant folding with the template of the define_insn,
5811 ; then to have the insns split later (between sched1 and final).
5813 (define_expand "floatsidf2"
5814 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5815 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5816 (use (match_dup 2))
5817 (use (match_dup 3))
5818 (clobber (match_dup 4))
5819 (clobber (match_dup 5))
5820 (clobber (match_dup 6))])]
5821 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5822 "
5823 {
5824 if (TARGET_E500_DOUBLE)
5825 {
5826 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5827 DONE;
5828 }
5829 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS)
5830 {
5831 rtx t1 = gen_reg_rtx (DImode);
5832 emit_insn (gen_floatsidf_ppc64_mfpgpr (operands[0], operands[1], t1));
5833 DONE;
5834 }
5835 if (TARGET_POWERPC64)
5836 {
5837 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5838 rtx t1 = gen_reg_rtx (DImode);
5839 rtx t2 = gen_reg_rtx (DImode);
5840 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5841 DONE;
5842 }
5844 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5845 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5846 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5847 operands[5] = gen_reg_rtx (DFmode);
5848 operands[6] = gen_reg_rtx (SImode);
5849 }")
5851 (define_insn_and_split "*floatsidf2_internal"
5852 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5853 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5854 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5855 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5856 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5857 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5858 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5859 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5860 "#"
5861 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
5862 [(pc)]
5863 "
5864 {
5865 rtx lowword, highword;
5866 gcc_assert (MEM_P (operands[4]));
5867 highword = adjust_address (operands[4], SImode, 0);
5868 lowword = adjust_address (operands[4], SImode, 4);
5869 if (! WORDS_BIG_ENDIAN)
5870 {
5871 rtx tmp;
5872 tmp = highword; highword = lowword; lowword = tmp;
5873 }
5875 emit_insn (gen_xorsi3 (operands[6], operands[1],
5876 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5877 emit_move_insn (lowword, operands[6]);
5878 emit_move_insn (highword, operands[2]);
5879 emit_move_insn (operands[5], operands[4]);
5880 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5881 DONE;
5882 }"
5883 [(set_attr "length" "24")])
5885 (define_expand "floatunssisf2"
5886 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5887 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5888 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5889 "")
5891 (define_expand "floatunssidf2"
5892 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5893 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5894 (use (match_dup 2))
5895 (use (match_dup 3))
5896 (clobber (match_dup 4))
5897 (clobber (match_dup 5))])]
5898 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5899 "
5900 {
5901 if (TARGET_E500_DOUBLE)
5902 {
5903 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5904 DONE;
5905 }
5906 if (TARGET_POWERPC64)
5907 {
5908 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5909 rtx t1 = gen_reg_rtx (DImode);
5910 rtx t2 = gen_reg_rtx (DImode);
5911 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5912 t1, t2));
5913 DONE;
5914 }
5916 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5917 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5918 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5919 operands[5] = gen_reg_rtx (DFmode);
5920 }")
5922 (define_insn_and_split "*floatunssidf2_internal"
5923 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5924 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5925 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5926 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5927 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5928 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5929 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5930 "#"
5931 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
5932 [(pc)]
5933 "
5934 {
5935 rtx lowword, highword;
5936 gcc_assert (MEM_P (operands[4]));
5937 highword = adjust_address (operands[4], SImode, 0);
5938 lowword = adjust_address (operands[4], SImode, 4);
5939 if (! WORDS_BIG_ENDIAN)
5940 {
5941 rtx tmp;
5942 tmp = highword; highword = lowword; lowword = tmp;
5943 }
5945 emit_move_insn (lowword, operands[1]);
5946 emit_move_insn (highword, operands[2]);
5947 emit_move_insn (operands[5], operands[4]);
5948 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5949 DONE;
5950 }"
5951 [(set_attr "length" "20")])
5953 (define_expand "fix_truncdfsi2"
5954 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5955 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5956 (clobber (match_dup 2))
5957 (clobber (match_dup 3))])]
5958 "(TARGET_POWER2 || TARGET_POWERPC)
5959 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5960 "
5961 {
5962 if (TARGET_E500_DOUBLE)
5963 {
5964 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5965 DONE;
5966 }
5967 operands[2] = gen_reg_rtx (DImode);
5968 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
5969 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
5970 {
5971 operands[3] = gen_reg_rtx (DImode);
5972 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
5973 operands[2], operands[3]));
5974 DONE;
5975 }
5976 if (TARGET_PPC_GFXOPT)
5977 {
5978 rtx orig_dest = operands[0];
5979 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5980 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5981 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5982 operands[2]));
5983 if (operands[0] != orig_dest)
5984 emit_move_insn (orig_dest, operands[0]);
5985 DONE;
5986 }
5987 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5988 }")
5990 (define_insn_and_split "*fix_truncdfsi2_internal"
5991 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5992 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5993 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5994 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
5995 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5996 "#"
5997 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))"
5998 [(pc)]
5999 "
6000 {
6001 rtx lowword;
6002 gcc_assert (MEM_P (operands[3]));
6003 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6005 emit_insn (gen_fctiwz (operands[2], operands[1]));
6006 emit_move_insn (operands[3], operands[2]);
6007 emit_move_insn (operands[0], lowword);
6008 DONE;
6009 }"
6010 [(set_attr "length" "16")])
6012 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
6013 [(set (match_operand:SI 0 "memory_operand" "=Z")
6014 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6015 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
6016 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6017 && TARGET_PPC_GFXOPT"
6018 "#"
6019 "&& 1"
6020 [(pc)]
6021 "
6022 {
6023 emit_insn (gen_fctiwz (operands[2], operands[1]));
6024 emit_insn (gen_stfiwx (operands[0], operands[2]));
6025 DONE;
6026 }"
6027 [(set_attr "length" "16")])
6029 (define_insn_and_split "fix_truncdfsi2_mfpgpr"
6030 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6031 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6032 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
6033 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
6034 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6035 "#"
6036 "&& 1"
6037 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
6038 (set (match_dup 3) (match_dup 2))
6039 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
6040 ""
6041 [(set_attr "length" "12")])
6043 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6044 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6045 ; because the first makes it clear that operand 0 is not live
6046 ; before the instruction.
6047 (define_insn "fctiwz"
6048 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
6049 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
6050 UNSPEC_FCTIWZ))]
6051 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
6052 "{fcirz|fctiwz} %0,%1"
6053 [(set_attr "type" "fp")])
6055 (define_insn "btruncdf2"
6056 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6057 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6058 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6059 "friz %0,%1"
6060 [(set_attr "type" "fp")])
6062 (define_insn "btruncsf2"
6063 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6064 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6065 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6066 "friz %0,%1"
6067 [(set_attr "type" "fp")])
6069 (define_insn "ceildf2"
6070 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6071 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6072 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6073 "frip %0,%1"
6074 [(set_attr "type" "fp")])
6076 (define_insn "ceilsf2"
6077 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6078 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6079 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6080 "frip %0,%1"
6081 [(set_attr "type" "fp")])
6083 (define_insn "floordf2"
6084 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6085 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6086 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6087 "frim %0,%1"
6088 [(set_attr "type" "fp")])
6090 (define_insn "floorsf2"
6091 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6092 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6093 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6094 "frim %0,%1"
6095 [(set_attr "type" "fp")])
6097 (define_insn "rounddf2"
6098 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6099 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6100 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6101 "frin %0,%1"
6102 [(set_attr "type" "fp")])
6104 (define_insn "roundsf2"
6105 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6106 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6107 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6108 "frin %0,%1"
6109 [(set_attr "type" "fp")])
6111 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6112 (define_insn "stfiwx"
6113 [(set (match_operand:SI 0 "memory_operand" "=Z")
6114 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
6115 UNSPEC_STFIWX))]
6116 "TARGET_PPC_GFXOPT"
6117 "stfiwx %1,%y0"
6118 [(set_attr "type" "fpstore")])
6120 (define_expand "floatsisf2"
6121 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6122 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6123 "TARGET_HARD_FLOAT && !TARGET_FPRS"
6124 "")
6126 (define_insn "floatdidf2"
6127 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6128 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
6129 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6130 "fcfid %0,%1"
6131 [(set_attr "type" "fp")])
6133 (define_insn_and_split "floatsidf_ppc64_mfpgpr"
6134 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6135 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6136 (clobber (match_operand:DI 2 "gpc_reg_operand" "=r"))]
6137 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6138 "#"
6139 "&& 1"
6140 [(set (match_dup 2) (sign_extend:DI (match_dup 1)))
6141 (set (match_dup 0) (float:DF (match_dup 2)))]
6142 "")
6144 (define_insn_and_split "floatsidf_ppc64"
6145 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6146 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6147 (clobber (match_operand:DI 2 "offsettable_mem_operand" "=o"))
6148 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6149 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
6150 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6151 "#"
6152 "&& 1"
6153 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
6154 (set (match_dup 2) (match_dup 3))
6155 (set (match_dup 4) (match_dup 2))
6156 (set (match_dup 0) (float:DF (match_dup 4)))]
6157 "")
6159 (define_insn_and_split "floatunssidf_ppc64"
6160 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6161 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6162 (clobber (match_operand:DI 2 "offsettable_mem_operand" "=o"))
6163 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6164 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
6165 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6166 "#"
6167 "&& 1"
6168 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
6169 (set (match_dup 2) (match_dup 3))
6170 (set (match_dup 4) (match_dup 2))
6171 (set (match_dup 0) (float:DF (match_dup 4)))]
6172 "")
6174 (define_insn "fix_truncdfdi2"
6175 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
6176 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
6177 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6178 "fctidz %0,%1"
6179 [(set_attr "type" "fp")])
6181 (define_expand "floatdisf2"
6182 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6183 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6184 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6185 "
6186 {
6187 rtx val = operands[1];
6188 if (!flag_unsafe_math_optimizations)
6189 {
6190 rtx label = gen_label_rtx ();
6191 val = gen_reg_rtx (DImode);
6192 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6193 emit_label (label);
6194 }
6195 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6196 DONE;
6197 }")
6199 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6200 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6201 ;; from double rounding.
6202 (define_insn_and_split "floatdisf2_internal1"
6203 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6204 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
6205 (clobber (match_scratch:DF 2 "=f"))]
6206 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6207 "#"
6208 "&& reload_completed"
6209 [(set (match_dup 2)
6210 (float:DF (match_dup 1)))
6211 (set (match_dup 0)
6212 (float_truncate:SF (match_dup 2)))]
6213 "")
6215 ;; Twiddles bits to avoid double rounding.
6216 ;; Bits that might be truncated when converting to DFmode are replaced
6217 ;; by a bit that won't be lost at that stage, but is below the SFmode
6218 ;; rounding position.
6219 (define_expand "floatdisf2_internal2"
6220 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6221 (const_int 53)))
6222 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6223 (const_int 2047)))
6224 (clobber (scratch:CC))])
6225 (set (match_dup 3) (plus:DI (match_dup 3)
6226 (const_int 1)))
6227 (set (match_dup 0) (plus:DI (match_dup 0)
6228 (const_int 2047)))
6229 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6230 (const_int 2)))
6231 (set (match_dup 0) (ior:DI (match_dup 0)
6232 (match_dup 1)))
6233 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6234 (const_int -2048)))
6235 (clobber (scratch:CC))])
6236 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6237 (label_ref (match_operand:DI 2 "" ""))
6238 (pc)))
6239 (set (match_dup 0) (match_dup 1))]
6240 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6241 "
6242 {
6243 operands[3] = gen_reg_rtx (DImode);
6244 operands[4] = gen_reg_rtx (CCUNSmode);
6245 }")
6246 \f
6247 ;; Define the DImode operations that can be done in a small number
6248 ;; of instructions. The & constraints are to prevent the register
6249 ;; allocator from allocating registers that overlap with the inputs
6250 ;; (for example, having an input in 7,8 and an output in 6,7). We
6251 ;; also allow for the output being the same as one of the inputs.
6253 (define_insn "*adddi3_noppc64"
6254 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6255 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6256 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6257 "! TARGET_POWERPC64"
6258 "*
6259 {
6260 if (WORDS_BIG_ENDIAN)
6261 return (GET_CODE (operands[2])) != CONST_INT
6262 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6263 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6264 else
6265 return (GET_CODE (operands[2])) != CONST_INT
6266 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6267 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6268 }"
6269 [(set_attr "type" "two")
6270 (set_attr "length" "8")])
6272 (define_insn "*subdi3_noppc64"
6273 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6274 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6275 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6276 "! TARGET_POWERPC64"
6277 "*
6278 {
6279 if (WORDS_BIG_ENDIAN)
6280 return (GET_CODE (operands[1]) != CONST_INT)
6281 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6282 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6283 else
6284 return (GET_CODE (operands[1]) != CONST_INT)
6285 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6286 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6287 }"
6288 [(set_attr "type" "two")
6289 (set_attr "length" "8")])
6291 (define_insn "*negdi2_noppc64"
6292 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6293 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6294 "! TARGET_POWERPC64"
6295 "*
6296 {
6297 return (WORDS_BIG_ENDIAN)
6298 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6299 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6300 }"
6301 [(set_attr "type" "two")
6302 (set_attr "length" "8")])
6304 (define_expand "mulsidi3"
6305 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6306 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6307 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6308 "! TARGET_POWERPC64"
6309 "
6310 {
6311 if (! TARGET_POWER && ! TARGET_POWERPC)
6312 {
6313 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6314 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6315 emit_insn (gen_mull_call ());
6316 if (WORDS_BIG_ENDIAN)
6317 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6318 else
6319 {
6320 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6321 gen_rtx_REG (SImode, 3));
6322 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6323 gen_rtx_REG (SImode, 4));
6324 }
6325 DONE;
6326 }
6327 else if (TARGET_POWER)
6328 {
6329 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6330 DONE;
6331 }
6332 }")
6334 (define_insn "mulsidi3_mq"
6335 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6336 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6337 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6338 (clobber (match_scratch:SI 3 "=q"))]
6339 "TARGET_POWER"
6340 "mul %0,%1,%2\;mfmq %L0"
6341 [(set_attr "type" "imul")
6342 (set_attr "length" "8")])
6344 (define_insn "*mulsidi3_no_mq"
6345 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6346 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6347 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6348 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6349 "*
6350 {
6351 return (WORDS_BIG_ENDIAN)
6352 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6353 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6354 }"
6355 [(set_attr "type" "imul")
6356 (set_attr "length" "8")])
6358 (define_split
6359 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6360 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6361 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6362 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6363 [(set (match_dup 3)
6364 (truncate:SI
6365 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6366 (sign_extend:DI (match_dup 2)))
6367 (const_int 32))))
6368 (set (match_dup 4)
6369 (mult:SI (match_dup 1)
6370 (match_dup 2)))]
6371 "
6372 {
6373 int endian = (WORDS_BIG_ENDIAN == 0);
6374 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6375 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6376 }")
6378 (define_expand "umulsidi3"
6379 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6380 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6381 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6382 "TARGET_POWERPC && ! TARGET_POWERPC64"
6383 "
6384 {
6385 if (TARGET_POWER)
6386 {
6387 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6388 DONE;
6389 }
6390 }")
6392 (define_insn "umulsidi3_mq"
6393 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6394 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6395 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6396 (clobber (match_scratch:SI 3 "=q"))]
6397 "TARGET_POWERPC && TARGET_POWER"
6398 "*
6399 {
6400 return (WORDS_BIG_ENDIAN)
6401 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6402 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6403 }"
6404 [(set_attr "type" "imul")
6405 (set_attr "length" "8")])
6407 (define_insn "*umulsidi3_no_mq"
6408 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6409 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6410 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6411 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6412 "*
6413 {
6414 return (WORDS_BIG_ENDIAN)
6415 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6416 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6417 }"
6418 [(set_attr "type" "imul")
6419 (set_attr "length" "8")])
6421 (define_split
6422 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6423 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6424 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6425 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6426 [(set (match_dup 3)
6427 (truncate:SI
6428 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6429 (zero_extend:DI (match_dup 2)))
6430 (const_int 32))))
6431 (set (match_dup 4)
6432 (mult:SI (match_dup 1)
6433 (match_dup 2)))]
6434 "
6435 {
6436 int endian = (WORDS_BIG_ENDIAN == 0);
6437 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6438 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6439 }")
6441 (define_expand "smulsi3_highpart"
6442 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6443 (truncate:SI
6444 (lshiftrt:DI (mult:DI (sign_extend:DI
6445 (match_operand:SI 1 "gpc_reg_operand" ""))
6446 (sign_extend:DI
6447 (match_operand:SI 2 "gpc_reg_operand" "")))
6448 (const_int 32))))]
6449 ""
6450 "
6451 {
6452 if (! TARGET_POWER && ! TARGET_POWERPC)
6453 {
6454 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6455 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6456 emit_insn (gen_mulh_call ());
6457 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
6458 DONE;
6459 }
6460 else if (TARGET_POWER)
6461 {
6462 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6463 DONE;
6464 }
6465 }")
6467 (define_insn "smulsi3_highpart_mq"
6468 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6469 (truncate:SI
6470 (lshiftrt:DI (mult:DI (sign_extend:DI
6471 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6472 (sign_extend:DI
6473 (match_operand:SI 2 "gpc_reg_operand" "r")))
6474 (const_int 32))))
6475 (clobber (match_scratch:SI 3 "=q"))]
6476 "TARGET_POWER"
6477 "mul %0,%1,%2"
6478 [(set_attr "type" "imul")])
6480 (define_insn "*smulsi3_highpart_no_mq"
6481 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6482 (truncate:SI
6483 (lshiftrt:DI (mult:DI (sign_extend:DI
6484 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6485 (sign_extend:DI
6486 (match_operand:SI 2 "gpc_reg_operand" "r")))
6487 (const_int 32))))]
6488 "TARGET_POWERPC && ! TARGET_POWER"
6489 "mulhw %0,%1,%2"
6490 [(set_attr "type" "imul")])
6492 (define_expand "umulsi3_highpart"
6493 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6494 (truncate:SI
6495 (lshiftrt:DI (mult:DI (zero_extend:DI
6496 (match_operand:SI 1 "gpc_reg_operand" ""))
6497 (zero_extend:DI
6498 (match_operand:SI 2 "gpc_reg_operand" "")))
6499 (const_int 32))))]
6500 "TARGET_POWERPC"
6501 "
6502 {
6503 if (TARGET_POWER)
6504 {
6505 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6506 DONE;
6507 }
6508 }")
6510 (define_insn "umulsi3_highpart_mq"
6511 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6512 (truncate:SI
6513 (lshiftrt:DI (mult:DI (zero_extend:DI
6514 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6515 (zero_extend:DI
6516 (match_operand:SI 2 "gpc_reg_operand" "r")))
6517 (const_int 32))))
6518 (clobber (match_scratch:SI 3 "=q"))]
6519 "TARGET_POWERPC && TARGET_POWER"
6520 "mulhwu %0,%1,%2"
6521 [(set_attr "type" "imul")])
6523 (define_insn "*umulsi3_highpart_no_mq"
6524 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6525 (truncate:SI
6526 (lshiftrt:DI (mult:DI (zero_extend:DI
6527 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6528 (zero_extend:DI
6529 (match_operand:SI 2 "gpc_reg_operand" "r")))
6530 (const_int 32))))]
6531 "TARGET_POWERPC && ! TARGET_POWER"
6532 "mulhwu %0,%1,%2"
6533 [(set_attr "type" "imul")])
6535 ;; If operands 0 and 2 are in the same register, we have a problem. But
6536 ;; operands 0 and 1 (the usual case) can be in the same register. That's
6537 ;; why we have the strange constraints below.
6538 (define_insn "ashldi3_power"
6539 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6540 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6541 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6542 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6543 "TARGET_POWER"
6544 "@
6545 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6546 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6547 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6548 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6549 [(set_attr "length" "8")])
6551 (define_insn "lshrdi3_power"
6552 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6553 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6554 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6555 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6556 "TARGET_POWER"
6557 "@
6558 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
6559 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6560 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6561 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6562 [(set_attr "length" "8")])
6564 ;; Shift by a variable amount is too complex to be worth open-coding. We
6565 ;; just handle shifts by constants.
6566 (define_insn "ashrdi3_power"
6567 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6568 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6569 (match_operand:SI 2 "const_int_operand" "M,i")))
6570 (clobber (match_scratch:SI 3 "=X,q"))]
6571 "TARGET_POWER"
6572 "@
6573 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6574 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
6575 [(set_attr "type" "shift")
6576 (set_attr "length" "8")])
6578 (define_insn "ashrdi3_no_power"
6579 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6580 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6581 (match_operand:SI 2 "const_int_operand" "M,i")))]
6582 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
6583 "@
6584 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6585 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
6586 [(set_attr "type" "two,three")
6587 (set_attr "length" "8,12")])
6589 (define_insn "*ashrdisi3_noppc64"
6590 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6591 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6592 (const_int 32)) 4))]
6593 "TARGET_32BIT && !TARGET_POWERPC64"
6594 "*
6595 {
6596 if (REGNO (operands[0]) == REGNO (operands[1]))
6597 return \"\";
6598 else
6599 return \"mr %0,%1\";
6600 }"
6601 [(set_attr "length" "4")])
6603 \f
6604 ;; PowerPC64 DImode operations.
6606 (define_insn_and_split "absdi2"
6607 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6608 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6609 (clobber (match_scratch:DI 2 "=&r,&r"))]
6610 "TARGET_POWERPC64"
6611 "#"
6612 "&& reload_completed"
6613 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6614 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6615 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6616 "")
6618 (define_insn_and_split "*nabsdi2"
6619 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6620 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6621 (clobber (match_scratch:DI 2 "=&r,&r"))]
6622 "TARGET_POWERPC64"
6623 "#"
6624 "&& reload_completed"
6625 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6626 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6627 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6628 "")
6630 (define_insn "muldi3"
6631 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6632 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6633 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6634 "TARGET_POWERPC64"
6635 "@
6636 mulld %0,%1,%2
6637 mulli %0,%1,%2"
6638 [(set (attr "type")
6639 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6640 (const_string "imul3")
6641 (match_operand:SI 2 "short_cint_operand" "")
6642 (const_string "imul2")]
6643 (const_string "lmul")))])
6645 (define_insn "*muldi3_internal1"
6646 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6647 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6648 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6649 (const_int 0)))
6650 (clobber (match_scratch:DI 3 "=r,r"))]
6651 "TARGET_POWERPC64"
6652 "@
6653 mulld. %3,%1,%2
6654 #"
6655 [(set_attr "type" "lmul_compare")
6656 (set_attr "length" "4,8")])
6658 (define_split
6659 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6660 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6661 (match_operand:DI 2 "gpc_reg_operand" ""))
6662 (const_int 0)))
6663 (clobber (match_scratch:DI 3 ""))]
6664 "TARGET_POWERPC64 && reload_completed"
6665 [(set (match_dup 3)
6666 (mult:DI (match_dup 1) (match_dup 2)))
6667 (set (match_dup 0)
6668 (compare:CC (match_dup 3)
6669 (const_int 0)))]
6670 "")
6672 (define_insn "*muldi3_internal2"
6673 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6674 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6675 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6676 (const_int 0)))
6677 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6678 (mult:DI (match_dup 1) (match_dup 2)))]
6679 "TARGET_POWERPC64"
6680 "@
6681 mulld. %0,%1,%2
6682 #"
6683 [(set_attr "type" "lmul_compare")
6684 (set_attr "length" "4,8")])
6686 (define_split
6687 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6688 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6689 (match_operand:DI 2 "gpc_reg_operand" ""))
6690 (const_int 0)))
6691 (set (match_operand:DI 0 "gpc_reg_operand" "")
6692 (mult:DI (match_dup 1) (match_dup 2)))]
6693 "TARGET_POWERPC64 && reload_completed"
6694 [(set (match_dup 0)
6695 (mult:DI (match_dup 1) (match_dup 2)))
6696 (set (match_dup 3)
6697 (compare:CC (match_dup 0)
6698 (const_int 0)))]
6699 "")
6701 (define_insn "smuldi3_highpart"
6702 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6703 (truncate:DI
6704 (lshiftrt:TI (mult:TI (sign_extend:TI
6705 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6706 (sign_extend:TI
6707 (match_operand:DI 2 "gpc_reg_operand" "r")))
6708 (const_int 64))))]
6709 "TARGET_POWERPC64"
6710 "mulhd %0,%1,%2"
6711 [(set_attr "type" "lmul")])
6713 (define_insn "umuldi3_highpart"
6714 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6715 (truncate:DI
6716 (lshiftrt:TI (mult:TI (zero_extend:TI
6717 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6718 (zero_extend:TI
6719 (match_operand:DI 2 "gpc_reg_operand" "r")))
6720 (const_int 64))))]
6721 "TARGET_POWERPC64"
6722 "mulhdu %0,%1,%2"
6723 [(set_attr "type" "lmul")])
6725 (define_insn "rotldi3"
6726 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6727 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6728 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
6729 "TARGET_POWERPC64"
6730 "@
6731 rldcl %0,%1,%2,0
6732 rldicl %0,%1,%H2,0"
6733 [(set_attr "type" "var_shift_rotate,integer")])
6735 (define_insn "*rotldi3_internal2"
6736 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6737 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6738 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6739 (const_int 0)))
6740 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6741 "TARGET_64BIT"
6742 "@
6743 rldcl. %3,%1,%2,0
6744 rldicl. %3,%1,%H2,0
6745 #
6746 #"
6747 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6748 (set_attr "length" "4,4,8,8")])
6750 (define_split
6751 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6752 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6753 (match_operand:DI 2 "reg_or_cint_operand" ""))
6754 (const_int 0)))
6755 (clobber (match_scratch:DI 3 ""))]
6756 "TARGET_POWERPC64 && reload_completed"
6757 [(set (match_dup 3)
6758 (rotate:DI (match_dup 1) (match_dup 2)))
6759 (set (match_dup 0)
6760 (compare:CC (match_dup 3)
6761 (const_int 0)))]
6762 "")
6764 (define_insn "*rotldi3_internal3"
6765 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6766 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6767 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6768 (const_int 0)))
6769 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6770 (rotate:DI (match_dup 1) (match_dup 2)))]
6771 "TARGET_64BIT"
6772 "@
6773 rldcl. %0,%1,%2,0
6774 rldicl. %0,%1,%H2,0
6775 #
6776 #"
6777 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6778 (set_attr "length" "4,4,8,8")])
6780 (define_split
6781 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6782 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6783 (match_operand:DI 2 "reg_or_cint_operand" ""))
6784 (const_int 0)))
6785 (set (match_operand:DI 0 "gpc_reg_operand" "")
6786 (rotate:DI (match_dup 1) (match_dup 2)))]
6787 "TARGET_POWERPC64 && reload_completed"
6788 [(set (match_dup 0)
6789 (rotate:DI (match_dup 1) (match_dup 2)))
6790 (set (match_dup 3)
6791 (compare:CC (match_dup 0)
6792 (const_int 0)))]
6793 "")
6795 (define_insn "*rotldi3_internal4"
6796 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6797 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6798 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6799 (match_operand:DI 3 "mask64_operand" "n,n")))]
6800 "TARGET_POWERPC64"
6801 "@
6802 rldc%B3 %0,%1,%2,%S3
6803 rldic%B3 %0,%1,%H2,%S3"
6804 [(set_attr "type" "var_shift_rotate,integer")])
6806 (define_insn "*rotldi3_internal5"
6807 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6808 (compare:CC (and:DI
6809 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6810 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6811 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6812 (const_int 0)))
6813 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
6814 "TARGET_64BIT"
6815 "@
6816 rldc%B3. %4,%1,%2,%S3
6817 rldic%B3. %4,%1,%H2,%S3
6818 #
6819 #"
6820 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6821 (set_attr "length" "4,4,8,8")])
6823 (define_split
6824 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6825 (compare:CC (and:DI
6826 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6827 (match_operand:DI 2 "reg_or_cint_operand" ""))
6828 (match_operand:DI 3 "mask64_operand" ""))
6829 (const_int 0)))
6830 (clobber (match_scratch:DI 4 ""))]
6831 "TARGET_POWERPC64 && reload_completed"
6832 [(set (match_dup 4)
6833 (and:DI (rotate:DI (match_dup 1)
6834 (match_dup 2))
6835 (match_dup 3)))
6836 (set (match_dup 0)
6837 (compare:CC (match_dup 4)
6838 (const_int 0)))]
6839 "")
6841 (define_insn "*rotldi3_internal6"
6842 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
6843 (compare:CC (and:DI
6844 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6845 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6846 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6847 (const_int 0)))
6848 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6849 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6850 "TARGET_64BIT"
6851 "@
6852 rldc%B3. %0,%1,%2,%S3
6853 rldic%B3. %0,%1,%H2,%S3
6854 #
6855 #"
6856 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6857 (set_attr "length" "4,4,8,8")])
6859 (define_split
6860 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6861 (compare:CC (and:DI
6862 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6863 (match_operand:DI 2 "reg_or_cint_operand" ""))
6864 (match_operand:DI 3 "mask64_operand" ""))
6865 (const_int 0)))
6866 (set (match_operand:DI 0 "gpc_reg_operand" "")
6867 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6868 "TARGET_POWERPC64 && reload_completed"
6869 [(set (match_dup 0)
6870 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6871 (set (match_dup 4)
6872 (compare:CC (match_dup 0)
6873 (const_int 0)))]
6874 "")
6876 (define_insn "*rotldi3_internal7"
6877 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6878 (zero_extend:DI
6879 (subreg:QI
6880 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6881 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6882 "TARGET_POWERPC64"
6883 "@
6884 rldcl %0,%1,%2,56
6885 rldicl %0,%1,%H2,56"
6886 [(set_attr "type" "var_shift_rotate,integer")])
6888 (define_insn "*rotldi3_internal8"
6889 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6890 (compare:CC (zero_extend:DI
6891 (subreg:QI
6892 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6893 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6894 (const_int 0)))
6895 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6896 "TARGET_64BIT"
6897 "@
6898 rldcl. %3,%1,%2,56
6899 rldicl. %3,%1,%H2,56
6900 #
6901 #"
6902 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6903 (set_attr "length" "4,4,8,8")])
6905 (define_split
6906 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6907 (compare:CC (zero_extend:DI
6908 (subreg:QI
6909 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6910 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6911 (const_int 0)))
6912 (clobber (match_scratch:DI 3 ""))]
6913 "TARGET_POWERPC64 && reload_completed"
6914 [(set (match_dup 3)
6915 (zero_extend:DI (subreg:QI
6916 (rotate:DI (match_dup 1)
6917 (match_dup 2)) 0)))
6918 (set (match_dup 0)
6919 (compare:CC (match_dup 3)
6920 (const_int 0)))]
6921 "")
6923 (define_insn "*rotldi3_internal9"
6924 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6925 (compare:CC (zero_extend:DI
6926 (subreg:QI
6927 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6928 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6929 (const_int 0)))
6930 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6931 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6932 "TARGET_64BIT"
6933 "@
6934 rldcl. %0,%1,%2,56
6935 rldicl. %0,%1,%H2,56
6936 #
6937 #"
6938 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6939 (set_attr "length" "4,4,8,8")])
6941 (define_split
6942 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6943 (compare:CC (zero_extend:DI
6944 (subreg:QI
6945 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6946 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6947 (const_int 0)))
6948 (set (match_operand:DI 0 "gpc_reg_operand" "")
6949 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6950 "TARGET_POWERPC64 && reload_completed"
6951 [(set (match_dup 0)
6952 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6953 (set (match_dup 3)
6954 (compare:CC (match_dup 0)
6955 (const_int 0)))]
6956 "")
6958 (define_insn "*rotldi3_internal10"
6959 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6960 (zero_extend:DI
6961 (subreg:HI
6962 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6963 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6964 "TARGET_POWERPC64"
6965 "@
6966 rldcl %0,%1,%2,48
6967 rldicl %0,%1,%H2,48"
6968 [(set_attr "type" "var_shift_rotate,integer")])
6970 (define_insn "*rotldi3_internal11"
6971 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6972 (compare:CC (zero_extend:DI
6973 (subreg:HI
6974 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6975 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6976 (const_int 0)))
6977 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6978 "TARGET_64BIT"
6979 "@
6980 rldcl. %3,%1,%2,48
6981 rldicl. %3,%1,%H2,48
6982 #
6983 #"
6984 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6985 (set_attr "length" "4,4,8,8")])
6987 (define_split
6988 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6989 (compare:CC (zero_extend:DI
6990 (subreg:HI
6991 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6992 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6993 (const_int 0)))
6994 (clobber (match_scratch:DI 3 ""))]
6995 "TARGET_POWERPC64 && reload_completed"
6996 [(set (match_dup 3)
6997 (zero_extend:DI (subreg:HI
6998 (rotate:DI (match_dup 1)
6999 (match_dup 2)) 0)))
7000 (set (match_dup 0)
7001 (compare:CC (match_dup 3)
7002 (const_int 0)))]
7003 "")
7005 (define_insn "*rotldi3_internal12"
7006 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7007 (compare:CC (zero_extend:DI
7008 (subreg:HI
7009 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7010 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7011 (const_int 0)))
7012 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7013 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7014 "TARGET_64BIT"
7015 "@
7016 rldcl. %0,%1,%2,48
7017 rldicl. %0,%1,%H2,48
7018 #
7019 #"
7020 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7021 (set_attr "length" "4,4,8,8")])
7023 (define_split
7024 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7025 (compare:CC (zero_extend:DI
7026 (subreg:HI
7027 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7028 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7029 (const_int 0)))
7030 (set (match_operand:DI 0 "gpc_reg_operand" "")
7031 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7032 "TARGET_POWERPC64 && reload_completed"
7033 [(set (match_dup 0)
7034 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7035 (set (match_dup 3)
7036 (compare:CC (match_dup 0)
7037 (const_int 0)))]
7038 "")
7040 (define_insn "*rotldi3_internal13"
7041 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7042 (zero_extend:DI
7043 (subreg:SI
7044 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7045 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7046 "TARGET_POWERPC64"
7047 "@
7048 rldcl %0,%1,%2,32
7049 rldicl %0,%1,%H2,32"
7050 [(set_attr "type" "var_shift_rotate,integer")])
7052 (define_insn "*rotldi3_internal14"
7053 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7054 (compare:CC (zero_extend:DI
7055 (subreg:SI
7056 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7057 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7058 (const_int 0)))
7059 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7060 "TARGET_64BIT"
7061 "@
7062 rldcl. %3,%1,%2,32
7063 rldicl. %3,%1,%H2,32
7064 #
7065 #"
7066 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7067 (set_attr "length" "4,4,8,8")])
7069 (define_split
7070 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7071 (compare:CC (zero_extend:DI
7072 (subreg:SI
7073 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7074 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7075 (const_int 0)))
7076 (clobber (match_scratch:DI 3 ""))]
7077 "TARGET_POWERPC64 && reload_completed"
7078 [(set (match_dup 3)
7079 (zero_extend:DI (subreg:SI
7080 (rotate:DI (match_dup 1)
7081 (match_dup 2)) 0)))
7082 (set (match_dup 0)
7083 (compare:CC (match_dup 3)
7084 (const_int 0)))]
7085 "")
7087 (define_insn "*rotldi3_internal15"
7088 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7089 (compare:CC (zero_extend:DI
7090 (subreg:SI
7091 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7092 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7093 (const_int 0)))
7094 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7095 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7096 "TARGET_64BIT"
7097 "@
7098 rldcl. %0,%1,%2,32
7099 rldicl. %0,%1,%H2,32
7100 #
7101 #"
7102 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7103 (set_attr "length" "4,4,8,8")])
7105 (define_split
7106 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7107 (compare:CC (zero_extend:DI
7108 (subreg:SI
7109 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7110 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7111 (const_int 0)))
7112 (set (match_operand:DI 0 "gpc_reg_operand" "")
7113 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7114 "TARGET_POWERPC64 && reload_completed"
7115 [(set (match_dup 0)
7116 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7117 (set (match_dup 3)
7118 (compare:CC (match_dup 0)
7119 (const_int 0)))]
7120 "")
7122 (define_expand "ashldi3"
7123 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7124 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7125 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7126 "TARGET_POWERPC64 || TARGET_POWER"
7127 "
7128 {
7129 if (TARGET_POWERPC64)
7130 ;
7131 else if (TARGET_POWER)
7132 {
7133 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7134 DONE;
7135 }
7136 else
7137 FAIL;
7138 }")
7140 (define_insn "*ashldi3_internal1"
7141 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7142 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7143 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7144 "TARGET_POWERPC64"
7145 "@
7146 sld %0,%1,%2
7147 sldi %0,%1,%H2"
7148 [(set_attr "type" "var_shift_rotate,shift")])
7150 (define_insn "*ashldi3_internal2"
7151 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7152 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7153 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7154 (const_int 0)))
7155 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7156 "TARGET_64BIT"
7157 "@
7158 sld. %3,%1,%2
7159 sldi. %3,%1,%H2
7160 #
7161 #"
7162 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7163 (set_attr "length" "4,4,8,8")])
7165 (define_split
7166 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7167 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7168 (match_operand:SI 2 "reg_or_cint_operand" ""))
7169 (const_int 0)))
7170 (clobber (match_scratch:DI 3 ""))]
7171 "TARGET_POWERPC64 && reload_completed"
7172 [(set (match_dup 3)
7173 (ashift:DI (match_dup 1) (match_dup 2)))
7174 (set (match_dup 0)
7175 (compare:CC (match_dup 3)
7176 (const_int 0)))]
7177 "")
7179 (define_insn "*ashldi3_internal3"
7180 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7181 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7182 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7183 (const_int 0)))
7184 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7185 (ashift:DI (match_dup 1) (match_dup 2)))]
7186 "TARGET_64BIT"
7187 "@
7188 sld. %0,%1,%2
7189 sldi. %0,%1,%H2
7190 #
7191 #"
7192 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7193 (set_attr "length" "4,4,8,8")])
7195 (define_split
7196 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7197 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7198 (match_operand:SI 2 "reg_or_cint_operand" ""))
7199 (const_int 0)))
7200 (set (match_operand:DI 0 "gpc_reg_operand" "")
7201 (ashift:DI (match_dup 1) (match_dup 2)))]
7202 "TARGET_POWERPC64 && reload_completed"
7203 [(set (match_dup 0)
7204 (ashift:DI (match_dup 1) (match_dup 2)))
7205 (set (match_dup 3)
7206 (compare:CC (match_dup 0)
7207 (const_int 0)))]
7208 "")
7210 (define_insn "*ashldi3_internal4"
7211 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7212 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7213 (match_operand:SI 2 "const_int_operand" "i"))
7214 (match_operand:DI 3 "const_int_operand" "n")))]
7215 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7216 "rldic %0,%1,%H2,%W3")
7218 (define_insn "ashldi3_internal5"
7219 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7220 (compare:CC
7221 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7222 (match_operand:SI 2 "const_int_operand" "i,i"))
7223 (match_operand:DI 3 "const_int_operand" "n,n"))
7224 (const_int 0)))
7225 (clobber (match_scratch:DI 4 "=r,r"))]
7226 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7227 "@
7228 rldic. %4,%1,%H2,%W3
7229 #"
7230 [(set_attr "type" "compare")
7231 (set_attr "length" "4,8")])
7233 (define_split
7234 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7235 (compare:CC
7236 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7237 (match_operand:SI 2 "const_int_operand" ""))
7238 (match_operand:DI 3 "const_int_operand" ""))
7239 (const_int 0)))
7240 (clobber (match_scratch:DI 4 ""))]
7241 "TARGET_POWERPC64 && reload_completed
7242 && includes_rldic_lshift_p (operands[2], operands[3])"
7243 [(set (match_dup 4)
7244 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7245 (match_dup 3)))
7246 (set (match_dup 0)
7247 (compare:CC (match_dup 4)
7248 (const_int 0)))]
7249 "")
7251 (define_insn "*ashldi3_internal6"
7252 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7253 (compare:CC
7254 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7255 (match_operand:SI 2 "const_int_operand" "i,i"))
7256 (match_operand:DI 3 "const_int_operand" "n,n"))
7257 (const_int 0)))
7258 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7259 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7260 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7261 "@
7262 rldic. %0,%1,%H2,%W3
7263 #"
7264 [(set_attr "type" "compare")
7265 (set_attr "length" "4,8")])
7267 (define_split
7268 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7269 (compare:CC
7270 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7271 (match_operand:SI 2 "const_int_operand" ""))
7272 (match_operand:DI 3 "const_int_operand" ""))
7273 (const_int 0)))
7274 (set (match_operand:DI 0 "gpc_reg_operand" "")
7275 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7276 "TARGET_POWERPC64 && reload_completed
7277 && includes_rldic_lshift_p (operands[2], operands[3])"
7278 [(set (match_dup 0)
7279 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7280 (match_dup 3)))
7281 (set (match_dup 4)
7282 (compare:CC (match_dup 0)
7283 (const_int 0)))]
7284 "")
7286 (define_insn "*ashldi3_internal7"
7287 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7288 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7289 (match_operand:SI 2 "const_int_operand" "i"))
7290 (match_operand:DI 3 "mask64_operand" "n")))]
7291 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7292 "rldicr %0,%1,%H2,%S3")
7294 (define_insn "ashldi3_internal8"
7295 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7296 (compare:CC
7297 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7298 (match_operand:SI 2 "const_int_operand" "i,i"))
7299 (match_operand:DI 3 "mask64_operand" "n,n"))
7300 (const_int 0)))
7301 (clobber (match_scratch:DI 4 "=r,r"))]
7302 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7303 "@
7304 rldicr. %4,%1,%H2,%S3
7305 #"
7306 [(set_attr "type" "compare")
7307 (set_attr "length" "4,8")])
7309 (define_split
7310 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7311 (compare:CC
7312 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7313 (match_operand:SI 2 "const_int_operand" ""))
7314 (match_operand:DI 3 "mask64_operand" ""))
7315 (const_int 0)))
7316 (clobber (match_scratch:DI 4 ""))]
7317 "TARGET_POWERPC64 && reload_completed
7318 && includes_rldicr_lshift_p (operands[2], operands[3])"
7319 [(set (match_dup 4)
7320 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7321 (match_dup 3)))
7322 (set (match_dup 0)
7323 (compare:CC (match_dup 4)
7324 (const_int 0)))]
7325 "")
7327 (define_insn "*ashldi3_internal9"
7328 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7329 (compare:CC
7330 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7331 (match_operand:SI 2 "const_int_operand" "i,i"))
7332 (match_operand:DI 3 "mask64_operand" "n,n"))
7333 (const_int 0)))
7334 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7335 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7336 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7337 "@
7338 rldicr. %0,%1,%H2,%S3
7339 #"
7340 [(set_attr "type" "compare")
7341 (set_attr "length" "4,8")])
7343 (define_split
7344 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7345 (compare:CC
7346 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7347 (match_operand:SI 2 "const_int_operand" ""))
7348 (match_operand:DI 3 "mask64_operand" ""))
7349 (const_int 0)))
7350 (set (match_operand:DI 0 "gpc_reg_operand" "")
7351 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7352 "TARGET_POWERPC64 && reload_completed
7353 && includes_rldicr_lshift_p (operands[2], operands[3])"
7354 [(set (match_dup 0)
7355 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7356 (match_dup 3)))
7357 (set (match_dup 4)
7358 (compare:CC (match_dup 0)
7359 (const_int 0)))]
7360 "")
7362 (define_expand "lshrdi3"
7363 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7364 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7365 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7366 "TARGET_POWERPC64 || TARGET_POWER"
7367 "
7368 {
7369 if (TARGET_POWERPC64)
7370 ;
7371 else if (TARGET_POWER)
7372 {
7373 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7374 DONE;
7375 }
7376 else
7377 FAIL;
7378 }")
7380 (define_insn "*lshrdi3_internal1"
7381 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7382 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7383 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7384 "TARGET_POWERPC64"
7385 "@
7386 srd %0,%1,%2
7387 srdi %0,%1,%H2"
7388 [(set_attr "type" "var_shift_rotate,shift")])
7390 (define_insn "*lshrdi3_internal2"
7391 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7392 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7393 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7394 (const_int 0)))
7395 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7396 "TARGET_64BIT "
7397 "@
7398 srd. %3,%1,%2
7399 srdi. %3,%1,%H2
7400 #
7401 #"
7402 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7403 (set_attr "length" "4,4,8,8")])
7405 (define_split
7406 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7407 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7408 (match_operand:SI 2 "reg_or_cint_operand" ""))
7409 (const_int 0)))
7410 (clobber (match_scratch:DI 3 ""))]
7411 "TARGET_POWERPC64 && reload_completed"
7412 [(set (match_dup 3)
7413 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7414 (set (match_dup 0)
7415 (compare:CC (match_dup 3)
7416 (const_int 0)))]
7417 "")
7419 (define_insn "*lshrdi3_internal3"
7420 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7421 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7422 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7423 (const_int 0)))
7424 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7425 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7426 "TARGET_64BIT"
7427 "@
7428 srd. %0,%1,%2
7429 srdi. %0,%1,%H2
7430 #
7431 #"
7432 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7433 (set_attr "length" "4,4,8,8")])
7435 (define_split
7436 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7437 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7438 (match_operand:SI 2 "reg_or_cint_operand" ""))
7439 (const_int 0)))
7440 (set (match_operand:DI 0 "gpc_reg_operand" "")
7441 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7442 "TARGET_POWERPC64 && reload_completed"
7443 [(set (match_dup 0)
7444 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7445 (set (match_dup 3)
7446 (compare:CC (match_dup 0)
7447 (const_int 0)))]
7448 "")
7450 (define_expand "ashrdi3"
7451 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7452 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7453 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7454 "WORDS_BIG_ENDIAN"
7455 "
7456 {
7457 if (TARGET_POWERPC64)
7458 ;
7459 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7460 {
7461 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7462 DONE;
7463 }
7464 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7465 && WORDS_BIG_ENDIAN)
7466 {
7467 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7468 DONE;
7469 }
7470 else
7471 FAIL;
7472 }")
7474 (define_insn "*ashrdi3_internal1"
7475 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7476 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7477 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7478 "TARGET_POWERPC64"
7479 "@
7480 srad %0,%1,%2
7481 sradi %0,%1,%H2"
7482 [(set_attr "type" "var_shift_rotate,shift")])
7484 (define_insn "*ashrdi3_internal2"
7485 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7486 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7487 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7488 (const_int 0)))
7489 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7490 "TARGET_64BIT"
7491 "@
7492 srad. %3,%1,%2
7493 sradi. %3,%1,%H2
7494 #
7495 #"
7496 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7497 (set_attr "length" "4,4,8,8")])
7499 (define_split
7500 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7501 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7502 (match_operand:SI 2 "reg_or_cint_operand" ""))
7503 (const_int 0)))
7504 (clobber (match_scratch:DI 3 ""))]
7505 "TARGET_POWERPC64 && reload_completed"
7506 [(set (match_dup 3)
7507 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7508 (set (match_dup 0)
7509 (compare:CC (match_dup 3)
7510 (const_int 0)))]
7511 "")
7513 (define_insn "*ashrdi3_internal3"
7514 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7515 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7516 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7517 (const_int 0)))
7518 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7519 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7520 "TARGET_64BIT"
7521 "@
7522 srad. %0,%1,%2
7523 sradi. %0,%1,%H2
7524 #
7525 #"
7526 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7527 (set_attr "length" "4,4,8,8")])
7529 (define_split
7530 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7531 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7532 (match_operand:SI 2 "reg_or_cint_operand" ""))
7533 (const_int 0)))
7534 (set (match_operand:DI 0 "gpc_reg_operand" "")
7535 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7536 "TARGET_POWERPC64 && reload_completed"
7537 [(set (match_dup 0)
7538 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7539 (set (match_dup 3)
7540 (compare:CC (match_dup 0)
7541 (const_int 0)))]
7542 "")
7544 (define_insn "anddi3"
7545 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7546 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7547 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7548 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7549 "TARGET_POWERPC64"
7550 "@
7551 and %0,%1,%2
7552 rldic%B2 %0,%1,0,%S2
7553 rlwinm %0,%1,0,%m2,%M2
7554 andi. %0,%1,%b2
7555 andis. %0,%1,%u2
7556 #"
7557 [(set_attr "type" "*,*,*,compare,compare,*")
7558 (set_attr "length" "4,4,4,4,4,8")])
7560 (define_split
7561 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7562 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7563 (match_operand:DI 2 "mask64_2_operand" "")))
7564 (clobber (match_scratch:CC 3 ""))]
7565 "TARGET_POWERPC64
7566 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7567 && !mask_operand (operands[2], DImode)
7568 && !mask64_operand (operands[2], DImode)"
7569 [(set (match_dup 0)
7570 (and:DI (rotate:DI (match_dup 1)
7571 (match_dup 4))
7572 (match_dup 5)))
7573 (set (match_dup 0)
7574 (and:DI (rotate:DI (match_dup 0)
7575 (match_dup 6))
7576 (match_dup 7)))]
7577 {
7578 build_mask64_2_operands (operands[2], &operands[4]);
7579 })
7581 (define_insn "*anddi3_internal2"
7582 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7583 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7584 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7585 (const_int 0)))
7586 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7587 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7588 "TARGET_64BIT"
7589 "@
7590 and. %3,%1,%2
7591 rldic%B2. %3,%1,0,%S2
7592 rlwinm. %3,%1,0,%m2,%M2
7593 andi. %3,%1,%b2
7594 andis. %3,%1,%u2
7595 #
7596 #
7597 #
7598 #
7599 #
7600 #
7601 #"
7602 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7603 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7605 (define_split
7606 [(set (match_operand:CC 0 "cc_reg_operand" "")
7607 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7608 (match_operand:DI 2 "mask64_2_operand" ""))
7609 (const_int 0)))
7610 (clobber (match_scratch:DI 3 ""))
7611 (clobber (match_scratch:CC 4 ""))]
7612 "TARGET_64BIT && reload_completed
7613 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7614 && !mask_operand (operands[2], DImode)
7615 && !mask64_operand (operands[2], DImode)"
7616 [(set (match_dup 3)
7617 (and:DI (rotate:DI (match_dup 1)
7618 (match_dup 5))
7619 (match_dup 6)))
7620 (parallel [(set (match_dup 0)
7621 (compare:CC (and:DI (rotate:DI (match_dup 3)
7622 (match_dup 7))
7623 (match_dup 8))
7624 (const_int 0)))
7625 (clobber (match_dup 3))])]
7626 "
7627 {
7628 build_mask64_2_operands (operands[2], &operands[5]);
7629 }")
7631 (define_insn "*anddi3_internal3"
7632 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7633 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7634 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7635 (const_int 0)))
7636 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7637 (and:DI (match_dup 1) (match_dup 2)))
7638 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7639 "TARGET_64BIT"
7640 "@
7641 and. %0,%1,%2
7642 rldic%B2. %0,%1,0,%S2
7643 rlwinm. %0,%1,0,%m2,%M2
7644 andi. %0,%1,%b2
7645 andis. %0,%1,%u2
7646 #
7647 #
7648 #
7649 #
7650 #
7651 #
7652 #"
7653 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7654 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7656 (define_split
7657 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7658 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7659 (match_operand:DI 2 "and64_2_operand" ""))
7660 (const_int 0)))
7661 (set (match_operand:DI 0 "gpc_reg_operand" "")
7662 (and:DI (match_dup 1) (match_dup 2)))
7663 (clobber (match_scratch:CC 4 ""))]
7664 "TARGET_64BIT && reload_completed"
7665 [(parallel [(set (match_dup 0)
7666 (and:DI (match_dup 1) (match_dup 2)))
7667 (clobber (match_dup 4))])
7668 (set (match_dup 3)
7669 (compare:CC (match_dup 0)
7670 (const_int 0)))]
7671 "")
7673 (define_split
7674 [(set (match_operand:CC 3 "cc_reg_operand" "")
7675 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7676 (match_operand:DI 2 "mask64_2_operand" ""))
7677 (const_int 0)))
7678 (set (match_operand:DI 0 "gpc_reg_operand" "")
7679 (and:DI (match_dup 1) (match_dup 2)))
7680 (clobber (match_scratch:CC 4 ""))]
7681 "TARGET_64BIT && reload_completed
7682 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7683 && !mask_operand (operands[2], DImode)
7684 && !mask64_operand (operands[2], DImode)"
7685 [(set (match_dup 0)
7686 (and:DI (rotate:DI (match_dup 1)
7687 (match_dup 5))
7688 (match_dup 6)))
7689 (parallel [(set (match_dup 3)
7690 (compare:CC (and:DI (rotate:DI (match_dup 0)
7691 (match_dup 7))
7692 (match_dup 8))
7693 (const_int 0)))
7694 (set (match_dup 0)
7695 (and:DI (rotate:DI (match_dup 0)
7696 (match_dup 7))
7697 (match_dup 8)))])]
7698 "
7699 {
7700 build_mask64_2_operands (operands[2], &operands[5]);
7701 }")
7703 (define_expand "iordi3"
7704 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7705 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7706 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7707 "TARGET_POWERPC64"
7708 "
7709 {
7710 if (non_logical_cint_operand (operands[2], DImode))
7711 {
7712 HOST_WIDE_INT value;
7713 rtx tmp = ((!can_create_pseudo_p ()
7714 || rtx_equal_p (operands[0], operands[1]))
7715 ? operands[0] : gen_reg_rtx (DImode));
7717 if (GET_CODE (operands[2]) == CONST_INT)
7718 {
7719 value = INTVAL (operands[2]);
7720 emit_insn (gen_iordi3 (tmp, operands[1],
7721 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7722 }
7723 else
7724 {
7725 value = CONST_DOUBLE_LOW (operands[2]);
7726 emit_insn (gen_iordi3 (tmp, operands[1],
7727 immed_double_const (value
7728 & (~ (HOST_WIDE_INT) 0xffff),
7729 0, DImode)));
7730 }
7732 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7733 DONE;
7734 }
7735 }")
7737 (define_expand "xordi3"
7738 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7739 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7740 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7741 "TARGET_POWERPC64"
7742 "
7743 {
7744 if (non_logical_cint_operand (operands[2], DImode))
7745 {
7746 HOST_WIDE_INT value;
7747 rtx tmp = ((!can_create_pseudo_p ()
7748 || rtx_equal_p (operands[0], operands[1]))
7749 ? operands[0] : gen_reg_rtx (DImode));
7751 if (GET_CODE (operands[2]) == CONST_INT)
7752 {
7753 value = INTVAL (operands[2]);
7754 emit_insn (gen_xordi3 (tmp, operands[1],
7755 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7756 }
7757 else
7758 {
7759 value = CONST_DOUBLE_LOW (operands[2]);
7760 emit_insn (gen_xordi3 (tmp, operands[1],
7761 immed_double_const (value
7762 & (~ (HOST_WIDE_INT) 0xffff),
7763 0, DImode)));
7764 }
7766 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7767 DONE;
7768 }
7769 }")
7771 (define_insn "*booldi3_internal1"
7772 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7773 (match_operator:DI 3 "boolean_or_operator"
7774 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7775 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7776 "TARGET_POWERPC64"
7777 "@
7778 %q3 %0,%1,%2
7779 %q3i %0,%1,%b2
7780 %q3is %0,%1,%u2")
7782 (define_insn "*booldi3_internal2"
7783 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7784 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7785 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7786 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7787 (const_int 0)))
7788 (clobber (match_scratch:DI 3 "=r,r"))]
7789 "TARGET_64BIT"
7790 "@
7791 %q4. %3,%1,%2
7792 #"
7793 [(set_attr "type" "compare")
7794 (set_attr "length" "4,8")])
7796 (define_split
7797 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7798 (compare:CC (match_operator:DI 4 "boolean_operator"
7799 [(match_operand:DI 1 "gpc_reg_operand" "")
7800 (match_operand:DI 2 "gpc_reg_operand" "")])
7801 (const_int 0)))
7802 (clobber (match_scratch:DI 3 ""))]
7803 "TARGET_POWERPC64 && reload_completed"
7804 [(set (match_dup 3) (match_dup 4))
7805 (set (match_dup 0)
7806 (compare:CC (match_dup 3)
7807 (const_int 0)))]
7808 "")
7810 (define_insn "*booldi3_internal3"
7811 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7812 (compare:CC (match_operator:DI 4 "boolean_operator"
7813 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7814 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7815 (const_int 0)))
7816 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7817 (match_dup 4))]
7818 "TARGET_64BIT"
7819 "@
7820 %q4. %0,%1,%2
7821 #"
7822 [(set_attr "type" "compare")
7823 (set_attr "length" "4,8")])
7825 (define_split
7826 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7827 (compare:CC (match_operator:DI 4 "boolean_operator"
7828 [(match_operand:DI 1 "gpc_reg_operand" "")
7829 (match_operand:DI 2 "gpc_reg_operand" "")])
7830 (const_int 0)))
7831 (set (match_operand:DI 0 "gpc_reg_operand" "")
7832 (match_dup 4))]
7833 "TARGET_POWERPC64 && reload_completed"
7834 [(set (match_dup 0) (match_dup 4))
7835 (set (match_dup 3)
7836 (compare:CC (match_dup 0)
7837 (const_int 0)))]
7838 "")
7840 ;; Split a logical operation that we can't do in one insn into two insns,
7841 ;; each of which does one 16-bit part. This is used by combine.
7843 (define_split
7844 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7845 (match_operator:DI 3 "boolean_or_operator"
7846 [(match_operand:DI 1 "gpc_reg_operand" "")
7847 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7848 "TARGET_POWERPC64"
7849 [(set (match_dup 0) (match_dup 4))
7850 (set (match_dup 0) (match_dup 5))]
7851 "
7852 {
7853 rtx i3,i4;
7855 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7856 {
7857 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7858 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7859 0, DImode);
7860 i4 = GEN_INT (value & 0xffff);
7861 }
7862 else
7863 {
7864 i3 = GEN_INT (INTVAL (operands[2])
7865 & (~ (HOST_WIDE_INT) 0xffff));
7866 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7867 }
7868 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7869 operands[1], i3);
7870 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7871 operands[0], i4);
7872 }")
7874 (define_insn "*boolcdi3_internal1"
7875 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7876 (match_operator:DI 3 "boolean_operator"
7877 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7878 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7879 "TARGET_POWERPC64"
7880 "%q3 %0,%2,%1")
7882 (define_insn "*boolcdi3_internal2"
7883 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7884 (compare:CC (match_operator:DI 4 "boolean_operator"
7885 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7886 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7887 (const_int 0)))
7888 (clobber (match_scratch:DI 3 "=r,r"))]
7889 "TARGET_64BIT"
7890 "@
7891 %q4. %3,%2,%1
7892 #"
7893 [(set_attr "type" "compare")
7894 (set_attr "length" "4,8")])
7896 (define_split
7897 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7898 (compare:CC (match_operator:DI 4 "boolean_operator"
7899 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7900 (match_operand:DI 2 "gpc_reg_operand" "")])
7901 (const_int 0)))
7902 (clobber (match_scratch:DI 3 ""))]
7903 "TARGET_POWERPC64 && reload_completed"
7904 [(set (match_dup 3) (match_dup 4))
7905 (set (match_dup 0)
7906 (compare:CC (match_dup 3)
7907 (const_int 0)))]
7908 "")
7910 (define_insn "*boolcdi3_internal3"
7911 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7912 (compare:CC (match_operator:DI 4 "boolean_operator"
7913 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7914 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7915 (const_int 0)))
7916 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7917 (match_dup 4))]
7918 "TARGET_64BIT"
7919 "@
7920 %q4. %0,%2,%1
7921 #"
7922 [(set_attr "type" "compare")
7923 (set_attr "length" "4,8")])
7925 (define_split
7926 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7927 (compare:CC (match_operator:DI 4 "boolean_operator"
7928 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7929 (match_operand:DI 2 "gpc_reg_operand" "")])
7930 (const_int 0)))
7931 (set (match_operand:DI 0 "gpc_reg_operand" "")
7932 (match_dup 4))]
7933 "TARGET_POWERPC64 && reload_completed"
7934 [(set (match_dup 0) (match_dup 4))
7935 (set (match_dup 3)
7936 (compare:CC (match_dup 0)
7937 (const_int 0)))]
7938 "")
7940 (define_insn "*boolccdi3_internal1"
7941 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7942 (match_operator:DI 3 "boolean_operator"
7943 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7944 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7945 "TARGET_POWERPC64"
7946 "%q3 %0,%1,%2")
7948 (define_insn "*boolccdi3_internal2"
7949 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7950 (compare:CC (match_operator:DI 4 "boolean_operator"
7951 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7952 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7953 (const_int 0)))
7954 (clobber (match_scratch:DI 3 "=r,r"))]
7955 "TARGET_64BIT"
7956 "@
7957 %q4. %3,%1,%2
7958 #"
7959 [(set_attr "type" "compare")
7960 (set_attr "length" "4,8")])
7962 (define_split
7963 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7964 (compare:CC (match_operator:DI 4 "boolean_operator"
7965 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7966 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7967 (const_int 0)))
7968 (clobber (match_scratch:DI 3 ""))]
7969 "TARGET_POWERPC64 && reload_completed"
7970 [(set (match_dup 3) (match_dup 4))
7971 (set (match_dup 0)
7972 (compare:CC (match_dup 3)
7973 (const_int 0)))]
7974 "")
7976 (define_insn "*boolccdi3_internal3"
7977 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7978 (compare:CC (match_operator:DI 4 "boolean_operator"
7979 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7980 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7981 (const_int 0)))
7982 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7983 (match_dup 4))]
7984 "TARGET_64BIT"
7985 "@
7986 %q4. %0,%1,%2
7987 #"
7988 [(set_attr "type" "compare")
7989 (set_attr "length" "4,8")])
7991 (define_split
7992 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7993 (compare:CC (match_operator:DI 4 "boolean_operator"
7994 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7995 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7996 (const_int 0)))
7997 (set (match_operand:DI 0 "gpc_reg_operand" "")
7998 (match_dup 4))]
7999 "TARGET_POWERPC64 && reload_completed"
8000 [(set (match_dup 0) (match_dup 4))
8001 (set (match_dup 3)
8002 (compare:CC (match_dup 0)
8003 (const_int 0)))]
8004 "")
8005 \f
8006 ;; Now define ways of moving data around.
8008 ;; Set up a register with a value from the GOT table
8010 (define_expand "movsi_got"
8011 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8012 (unspec:SI [(match_operand:SI 1 "got_operand" "")
8013 (match_dup 2)] UNSPEC_MOVSI_GOT))]
8014 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8015 "
8016 {
8017 if (GET_CODE (operands[1]) == CONST)
8018 {
8019 rtx offset = const0_rtx;
8020 HOST_WIDE_INT value;
8022 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8023 value = INTVAL (offset);
8024 if (value != 0)
8025 {
8026 rtx tmp = (!can_create_pseudo_p ()
8027 ? operands[0]
8028 : gen_reg_rtx (Pmode));
8029 emit_insn (gen_movsi_got (tmp, operands[1]));
8030 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8031 DONE;
8032 }
8033 }
8035 operands[2] = rs6000_got_register (operands[1]);
8036 }")
8038 (define_insn "*movsi_got_internal"
8039 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8040 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8041 (match_operand:SI 2 "gpc_reg_operand" "b")]
8042 UNSPEC_MOVSI_GOT))]
8043 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8044 "{l|lwz} %0,%a1@got(%2)"
8045 [(set_attr "type" "load")])
8047 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8048 ;; didn't get allocated to a hard register.
8049 (define_split
8050 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8051 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8052 (match_operand:SI 2 "memory_operand" "")]
8053 UNSPEC_MOVSI_GOT))]
8054 "DEFAULT_ABI == ABI_V4
8055 && flag_pic == 1
8056 && (reload_in_progress || reload_completed)"
8057 [(set (match_dup 0) (match_dup 2))
8058 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8059 UNSPEC_MOVSI_GOT))]
8060 "")
8062 ;; For SI, we special-case integers that can't be loaded in one insn. We
8063 ;; do the load 16-bits at a time. We could do this by loading from memory,
8064 ;; and this is even supposed to be faster, but it is simpler not to get
8065 ;; integers in the TOC.
8066 (define_insn "movsi_low"
8067 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8068 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8069 (match_operand 2 "" ""))))]
8070 "TARGET_MACHO && ! TARGET_64BIT"
8071 "{l|lwz} %0,lo16(%2)(%1)"
8072 [(set_attr "type" "load")
8073 (set_attr "length" "4")])
8075 (define_insn "*movsi_internal1"
8076 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
8077 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
8078 "gpc_reg_operand (operands[0], SImode)
8079 || gpc_reg_operand (operands[1], SImode)"
8080 "@
8081 mr %0,%1
8082 {cal|la} %0,%a1
8083 {l%U1%X1|lwz%U1%X1} %0,%1
8084 {st%U0%X0|stw%U0%X0} %1,%0
8085 {lil|li} %0,%1
8086 {liu|lis} %0,%v1
8087 #
8088 {cal|la} %0,%a1
8089 mf%1 %0
8090 mt%0 %1
8091 mt%0 %1
8092 mt%0 %1
8093 {cror 0,0,0|nop}"
8094 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
8095 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8097 ;; Split a load of a large constant into the appropriate two-insn
8098 ;; sequence.
8100 (define_split
8101 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8102 (match_operand:SI 1 "const_int_operand" ""))]
8103 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8104 && (INTVAL (operands[1]) & 0xffff) != 0"
8105 [(set (match_dup 0)
8106 (match_dup 2))
8107 (set (match_dup 0)
8108 (ior:SI (match_dup 0)
8109 (match_dup 3)))]
8110 "
8111 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8113 if (tem == operands[0])
8114 DONE;
8115 else
8116 FAIL;
8117 }")
8119 (define_insn "*mov<mode>_internal2"
8120 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8121 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8122 (const_int 0)))
8123 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8124 ""
8125 "@
8126 {cmpi|cmp<wd>i} %2,%0,0
8127 mr. %0,%1
8128 #"
8129 [(set_attr "type" "cmp,compare,cmp")
8130 (set_attr "length" "4,4,8")])
8132 (define_split
8133 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8134 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8135 (const_int 0)))
8136 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8137 "reload_completed"
8138 [(set (match_dup 0) (match_dup 1))
8139 (set (match_dup 2)
8140 (compare:CC (match_dup 0)
8141 (const_int 0)))]
8142 "")
8143 \f
8144 (define_insn "*movhi_internal"
8145 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8146 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8147 "gpc_reg_operand (operands[0], HImode)
8148 || gpc_reg_operand (operands[1], HImode)"
8149 "@
8150 mr %0,%1
8151 lhz%U1%X1 %0,%1
8152 sth%U0%X0 %1,%0
8153 {lil|li} %0,%w1
8154 mf%1 %0
8155 mt%0 %1
8156 mt%0 %1
8157 {cror 0,0,0|nop}"
8158 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8160 (define_expand "mov<mode>"
8161 [(set (match_operand:INT 0 "general_operand" "")
8162 (match_operand:INT 1 "any_operand" ""))]
8163 ""
8164 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8166 (define_insn "*movqi_internal"
8167 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8168 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8169 "gpc_reg_operand (operands[0], QImode)
8170 || gpc_reg_operand (operands[1], QImode)"
8171 "@
8172 mr %0,%1
8173 lbz%U1%X1 %0,%1
8174 stb%U0%X0 %1,%0
8175 {lil|li} %0,%1
8176 mf%1 %0
8177 mt%0 %1
8178 mt%0 %1
8179 {cror 0,0,0|nop}"
8180 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8181 \f
8182 ;; Here is how to move condition codes around. When we store CC data in
8183 ;; an integer register or memory, we store just the high-order 4 bits.
8184 ;; This lets us not shift in the most common case of CR0.
8185 (define_expand "movcc"
8186 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8187 (match_operand:CC 1 "nonimmediate_operand" ""))]
8188 ""
8189 "")
8191 (define_insn "*movcc_internal1"
8192 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8193 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
8194 "register_operand (operands[0], CCmode)
8195 || register_operand (operands[1], CCmode)"
8196 "@
8197 mcrf %0,%1
8198 mtcrf 128,%1
8199 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
8200 crxor %0,%0,%0
8201 mfcr %0%Q1
8202 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
8203 mr %0,%1
8204 {lil|li} %0,%1
8205 mf%1 %0
8206 mt%0 %1
8207 mt%0 %1
8208 {l%U1%X1|lwz%U1%X1} %0,%1
8209 {st%U0%U1|stw%U0%U1} %1,%0"
8210 [(set (attr "type")
8211 (cond [(eq_attr "alternative" "0,3")
8212 (const_string "cr_logical")
8213 (eq_attr "alternative" "1,2")
8214 (const_string "mtcr")
8215 (eq_attr "alternative" "6,7,9")
8216 (const_string "integer")
8217 (eq_attr "alternative" "8")
8218 (const_string "mfjmpr")
8219 (eq_attr "alternative" "10")
8220 (const_string "mtjmpr")
8221 (eq_attr "alternative" "11")
8222 (const_string "load")
8223 (eq_attr "alternative" "12")
8224 (const_string "store")
8225 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8226 (const_string "mfcrf")
8227 ]
8228 (const_string "mfcr")))
8229 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
8230 \f
8231 ;; For floating-point, we normally deal with the floating-point registers
8232 ;; unless -msoft-float is used. The sole exception is that parameter passing
8233 ;; can produce floating-point values in fixed-point registers. Unless the
8234 ;; value is a simple constant or already in memory, we deal with this by
8235 ;; allocating memory and copying the value explicitly via that memory location.
8236 (define_expand "movsf"
8237 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8238 (match_operand:SF 1 "any_operand" ""))]
8239 ""
8240 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
8242 (define_split
8243 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8244 (match_operand:SF 1 "const_double_operand" ""))]
8245 "reload_completed
8246 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8247 || (GET_CODE (operands[0]) == SUBREG
8248 && GET_CODE (SUBREG_REG (operands[0])) == REG
8249 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8250 [(set (match_dup 2) (match_dup 3))]
8251 "
8252 {
8253 long l;
8254 REAL_VALUE_TYPE rv;
8256 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8257 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
8259 if (! TARGET_POWERPC64)
8260 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8261 else
8262 operands[2] = gen_lowpart (SImode, operands[0]);
8264 operands[3] = gen_int_mode (l, SImode);
8265 }")
8267 (define_insn "*movsf_hardfloat"
8268 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
8269 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
8270 "(gpc_reg_operand (operands[0], SFmode)
8271 || gpc_reg_operand (operands[1], SFmode))
8272 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
8273 "@
8274 mr %0,%1
8275 {l%U1%X1|lwz%U1%X1} %0,%1
8276 {st%U0%X0|stw%U0%X0} %1,%0
8277 fmr %0,%1
8278 lfs%U1%X1 %0,%1
8279 stfs%U0%X0 %1,%0
8280 mt%0 %1
8281 mt%0 %1
8282 mf%1 %0
8283 {cror 0,0,0|nop}
8284 #
8285 #"
8286 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
8287 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
8289 (define_insn "*movsf_softfloat"
8290 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8291 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
8292 "(gpc_reg_operand (operands[0], SFmode)
8293 || gpc_reg_operand (operands[1], SFmode))
8294 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8295 "@
8296 mr %0,%1
8297 mt%0 %1
8298 mt%0 %1
8299 mf%1 %0
8300 {l%U1%X1|lwz%U1%X1} %0,%1
8301 {st%U0%X0|stw%U0%X0} %1,%0
8302 {lil|li} %0,%1
8303 {liu|lis} %0,%v1
8304 {cal|la} %0,%a1
8305 #
8306 #
8307 {cror 0,0,0|nop}"
8308 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
8309 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
8311 \f
8312 (define_expand "movdf"
8313 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8314 (match_operand:DF 1 "any_operand" ""))]
8315 ""
8316 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
8318 (define_split
8319 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8320 (match_operand:DF 1 "const_int_operand" ""))]
8321 "! TARGET_POWERPC64 && reload_completed
8322 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8323 || (GET_CODE (operands[0]) == SUBREG
8324 && GET_CODE (SUBREG_REG (operands[0])) == REG
8325 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8326 [(set (match_dup 2) (match_dup 4))
8327 (set (match_dup 3) (match_dup 1))]
8328 "
8329 {
8330 int endian = (WORDS_BIG_ENDIAN == 0);
8331 HOST_WIDE_INT value = INTVAL (operands[1]);
8333 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8334 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8335 #if HOST_BITS_PER_WIDE_INT == 32
8336 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8337 #else
8338 operands[4] = GEN_INT (value >> 32);
8339 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8340 #endif
8341 }")
8343 (define_split
8344 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8345 (match_operand:DF 1 "const_double_operand" ""))]
8346 "! TARGET_POWERPC64 && reload_completed
8347 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8348 || (GET_CODE (operands[0]) == SUBREG
8349 && GET_CODE (SUBREG_REG (operands[0])) == REG
8350 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8351 [(set (match_dup 2) (match_dup 4))
8352 (set (match_dup 3) (match_dup 5))]
8353 "
8354 {
8355 int endian = (WORDS_BIG_ENDIAN == 0);
8356 long l[2];
8357 REAL_VALUE_TYPE rv;
8359 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8360 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8362 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8363 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8364 operands[4] = gen_int_mode (l[endian], SImode);
8365 operands[5] = gen_int_mode (l[1 - endian], SImode);
8366 }")
8368 (define_split
8369 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8370 (match_operand:DF 1 "const_double_operand" ""))]
8371 "TARGET_POWERPC64 && reload_completed
8372 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8373 || (GET_CODE (operands[0]) == SUBREG
8374 && GET_CODE (SUBREG_REG (operands[0])) == REG
8375 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8376 [(set (match_dup 2) (match_dup 3))]
8377 "
8378 {
8379 int endian = (WORDS_BIG_ENDIAN == 0);
8380 long l[2];
8381 REAL_VALUE_TYPE rv;
8382 #if HOST_BITS_PER_WIDE_INT >= 64
8383 HOST_WIDE_INT val;
8384 #endif
8386 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8387 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8389 operands[2] = gen_lowpart (DImode, operands[0]);
8390 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8391 #if HOST_BITS_PER_WIDE_INT >= 64
8392 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8393 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8395 operands[3] = gen_int_mode (val, DImode);
8396 #else
8397 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8398 #endif
8399 }")
8401 ;; Don't have reload use general registers to load a constant. First,
8402 ;; it might not work if the output operand is the equivalent of
8403 ;; a non-offsettable memref, but also it is less efficient than loading
8404 ;; the constant into an FP register, since it will probably be used there.
8405 ;; The "??" is a kludge until we can figure out a more reasonable way
8406 ;; of handling these non-offsettable values.
8407 (define_insn "*movdf_hardfloat32"
8408 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8409 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8410 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8411 && (gpc_reg_operand (operands[0], DFmode)
8412 || gpc_reg_operand (operands[1], DFmode))"
8413 "*
8414 {
8415 switch (which_alternative)
8416 {
8417 default:
8418 gcc_unreachable ();
8419 case 0:
8420 /* We normally copy the low-numbered register first. However, if
8421 the first register operand 0 is the same as the second register
8422 of operand 1, we must copy in the opposite order. */
8423 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8424 return \"mr %L0,%L1\;mr %0,%1\";
8425 else
8426 return \"mr %0,%1\;mr %L0,%L1\";
8427 case 1:
8428 if (rs6000_offsettable_memref_p (operands[1])
8429 || (GET_CODE (operands[1]) == MEM
8430 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8431 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8432 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC
8433 || GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)))
8434 {
8435 /* If the low-address word is used in the address, we must load
8436 it last. Otherwise, load it first. Note that we cannot have
8437 auto-increment in that case since the address register is
8438 known to be dead. */
8439 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8440 operands[1], 0))
8441 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8442 else
8443 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
8444 }
8445 else
8446 {
8447 rtx addreg;
8449 addreg = find_addr_reg (XEXP (operands[1], 0));
8450 if (refers_to_regno_p (REGNO (operands[0]),
8451 REGNO (operands[0]) + 1,
8452 operands[1], 0))
8453 {
8454 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8455 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8456 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8457 return \"{l%X1|lwz%X1} %0,%1\";
8458 }
8459 else
8460 {
8461 output_asm_insn (\"{l%X1|lwz%X1} %0,%1\", operands);
8462 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8463 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
8464 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8465 return \"\";
8466 }
8467 }
8468 case 2:
8469 if (rs6000_offsettable_memref_p (operands[0])
8470 || (GET_CODE (operands[0]) == MEM
8471 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8472 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8473 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
8474 || GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)))
8475 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
8476 else
8477 {
8478 rtx addreg;
8480 addreg = find_addr_reg (XEXP (operands[0], 0));
8481 output_asm_insn (\"{st%X0|stw%X0} %1,%0\", operands);
8482 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8483 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
8484 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8485 return \"\";
8486 }
8487 case 3:
8488 return \"fmr %0,%1\";
8489 case 4:
8490 return \"lfd%U1%X1 %0,%1\";
8491 case 5:
8492 return \"stfd%U0%X0 %1,%0\";
8493 case 6:
8494 case 7:
8495 case 8:
8496 return \"#\";
8497 }
8498 }"
8499 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
8500 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8502 (define_insn "*movdf_softfloat32"
8503 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8504 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8505 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8506 && (gpc_reg_operand (operands[0], DFmode)
8507 || gpc_reg_operand (operands[1], DFmode))"
8508 "*
8509 {
8510 switch (which_alternative)
8511 {
8512 default:
8513 gcc_unreachable ();
8514 case 0:
8515 /* We normally copy the low-numbered register first. However, if
8516 the first register operand 0 is the same as the second register of
8517 operand 1, we must copy in the opposite order. */
8518 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8519 return \"mr %L0,%L1\;mr %0,%1\";
8520 else
8521 return \"mr %0,%1\;mr %L0,%L1\";
8522 case 1:
8523 /* If the low-address word is used in the address, we must load
8524 it last. Otherwise, load it first. Note that we cannot have
8525 auto-increment in that case since the address register is
8526 known to be dead. */
8527 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8528 operands[1], 0))
8529 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8530 else
8531 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
8532 case 2:
8533 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
8534 case 3:
8535 case 4:
8536 case 5:
8537 return \"#\";
8538 }
8539 }"
8540 [(set_attr "type" "two,load,store,*,*,*")
8541 (set_attr "length" "8,8,8,8,12,16")])
8543 ; ld/std require word-aligned displacements -> 'Y' constraint.
8544 ; List Y->r and r->Y before r->r for reload.
8545 (define_insn "*movdf_hardfloat64_mfpgpr"
8546 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
8547 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
8548 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8549 && (gpc_reg_operand (operands[0], DFmode)
8550 || gpc_reg_operand (operands[1], DFmode))"
8551 "@
8552 std%U0%X0 %1,%0
8553 ld%U1%X1 %0,%1
8554 mr %0,%1
8555 fmr %0,%1
8556 lfd%U1%X1 %0,%1
8557 stfd%U0%X0 %1,%0
8558 mt%0 %1
8559 mf%1 %0
8560 {cror 0,0,0|nop}
8561 #
8562 #
8563 #
8564 mftgpr %0,%1
8565 mffgpr %0,%1"
8566 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8567 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8569 ; ld/std require word-aligned displacements -> 'Y' constraint.
8570 ; List Y->r and r->Y before r->r for reload.
8571 (define_insn "*movdf_hardfloat64"
8572 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
8573 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8574 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8575 && (gpc_reg_operand (operands[0], DFmode)
8576 || gpc_reg_operand (operands[1], DFmode))"
8577 "@
8578 std%U0%X0 %1,%0
8579 ld%U1%X1 %0,%1
8580 mr %0,%1
8581 fmr %0,%1
8582 lfd%U1%X1 %0,%1
8583 stfd%U0%X0 %1,%0
8584 mt%0 %1
8585 mf%1 %0
8586 {cror 0,0,0|nop}
8587 #
8588 #
8589 #"
8590 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
8591 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8593 (define_insn "*movdf_softfloat64"
8594 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8595 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8596 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8597 && (gpc_reg_operand (operands[0], DFmode)
8598 || gpc_reg_operand (operands[1], DFmode))"
8599 "@
8600 ld%U1%X1 %0,%1
8601 std%U0%X0 %1,%0
8602 mr %0,%1
8603 mt%0 %1
8604 mf%1 %0
8605 #
8606 #
8607 #
8608 {cror 0,0,0|nop}"
8609 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
8610 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8611 \f
8612 (define_expand "movtf"
8613 [(set (match_operand:TF 0 "general_operand" "")
8614 (match_operand:TF 1 "any_operand" ""))]
8615 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
8616 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8618 ; It's important to list the o->f and f->o moves before f->f because
8619 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8620 ; which doesn't make progress. Likewise r->Y must be before r->r.
8621 (define_insn_and_split "*movtf_internal"
8622 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8623 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
8624 "!TARGET_IEEEQUAD
8625 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8626 && (gpc_reg_operand (operands[0], TFmode)
8627 || gpc_reg_operand (operands[1], TFmode))"
8628 "#"
8629 "&& reload_completed"
8630 [(pc)]
8631 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8632 [(set_attr "length" "8,8,8,20,20,16")])
8634 (define_insn_and_split "*movtf_softfloat"
8635 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
8636 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
8637 "!TARGET_IEEEQUAD
8638 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8639 && (gpc_reg_operand (operands[0], TFmode)
8640 || gpc_reg_operand (operands[1], TFmode))"
8641 "#"
8642 "&& reload_completed"
8643 [(pc)]
8644 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8645 [(set_attr "length" "20,20,16")])
8647 (define_expand "extenddftf2"
8648 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8649 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8650 "!TARGET_IEEEQUAD
8651 && TARGET_HARD_FLOAT
8652 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8653 && TARGET_LONG_DOUBLE_128"
8654 {
8655 if (TARGET_E500_DOUBLE)
8656 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8657 else
8658 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8659 DONE;
8660 })
8662 (define_expand "extenddftf2_fprs"
8663 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8664 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8665 (use (match_dup 2))])]
8666 "!TARGET_IEEEQUAD
8667 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8668 {
8669 operands[2] = CONST0_RTX (DFmode);
8670 /* Generate GOT reference early for SVR4 PIC. */
8671 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8672 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8673 })
8675 (define_insn_and_split "*extenddftf2_internal"
8676 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8677 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8678 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
8679 "!TARGET_IEEEQUAD
8680 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8681 "#"
8682 "&& reload_completed"
8683 [(pc)]
8684 {
8685 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8686 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8687 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8688 operands[1]);
8689 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8690 operands[2]);
8691 DONE;
8692 })
8694 (define_expand "extendsftf2"
8695 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8696 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8697 "!TARGET_IEEEQUAD
8698 && TARGET_HARD_FLOAT
8699 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8700 && TARGET_LONG_DOUBLE_128"
8701 {
8702 rtx tmp = gen_reg_rtx (DFmode);
8703 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8704 emit_insn (gen_extenddftf2 (operands[0], tmp));
8705 DONE;
8706 })
8708 (define_expand "trunctfdf2"
8709 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8710 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8711 "!TARGET_IEEEQUAD
8712 && TARGET_HARD_FLOAT
8713 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8714 && TARGET_LONG_DOUBLE_128"
8715 "")
8717 (define_insn_and_split "trunctfdf2_internal1"
8718 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8719 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8720 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8721 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8722 "@
8723 #
8724 fmr %0,%1"
8725 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8726 [(const_int 0)]
8727 {
8728 emit_note (NOTE_INSN_DELETED);
8729 DONE;
8730 }
8731 [(set_attr "type" "fp")])
8733 (define_insn "trunctfdf2_internal2"
8734 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8735 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8736 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8737 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8738 "fadd %0,%1,%L1"
8739 [(set_attr "type" "fp")])
8741 (define_expand "trunctfsf2"
8742 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8743 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8744 "!TARGET_IEEEQUAD
8745 && TARGET_HARD_FLOAT
8746 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8747 && TARGET_LONG_DOUBLE_128"
8748 {
8749 if (TARGET_E500_DOUBLE)
8750 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8751 else
8752 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8753 DONE;
8754 })
8756 (define_insn_and_split "trunctfsf2_fprs"
8757 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8758 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8759 (clobber (match_scratch:DF 2 "=f"))]
8760 "!TARGET_IEEEQUAD
8761 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8762 "#"
8763 "&& reload_completed"
8764 [(set (match_dup 2)
8765 (float_truncate:DF (match_dup 1)))
8766 (set (match_dup 0)
8767 (float_truncate:SF (match_dup 2)))]
8768 "")
8770 (define_expand "floatsitf2"
8771 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8772 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8773 "!TARGET_IEEEQUAD
8774 && TARGET_HARD_FLOAT
8775 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8776 && TARGET_LONG_DOUBLE_128"
8777 {
8778 rtx tmp = gen_reg_rtx (DFmode);
8779 expand_float (tmp, operands[1], false);
8780 emit_insn (gen_extenddftf2 (operands[0], tmp));
8781 DONE;
8782 })
8784 ; fadd, but rounding towards zero.
8785 ; This is probably not the optimal code sequence.
8786 (define_insn "fix_trunc_helper"
8787 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8788 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8789 UNSPEC_FIX_TRUNC_TF))
8790 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8791 "TARGET_HARD_FLOAT && TARGET_FPRS"
8792 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8793 [(set_attr "type" "fp")
8794 (set_attr "length" "20")])
8796 (define_expand "fix_trunctfsi2"
8797 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8798 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8799 "!TARGET_IEEEQUAD
8800 && (TARGET_POWER2 || TARGET_POWERPC)
8801 && TARGET_HARD_FLOAT
8802 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8803 && TARGET_LONG_DOUBLE_128"
8804 {
8805 if (TARGET_E500_DOUBLE)
8806 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8807 else
8808 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8809 DONE;
8810 })
8812 (define_expand "fix_trunctfsi2_fprs"
8813 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8814 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8815 (clobber (match_dup 2))
8816 (clobber (match_dup 3))
8817 (clobber (match_dup 4))
8818 (clobber (match_dup 5))])]
8819 "!TARGET_IEEEQUAD
8820 && (TARGET_POWER2 || TARGET_POWERPC)
8821 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8822 {
8823 operands[2] = gen_reg_rtx (DFmode);
8824 operands[3] = gen_reg_rtx (DFmode);
8825 operands[4] = gen_reg_rtx (DImode);
8826 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8827 })
8829 (define_insn_and_split "*fix_trunctfsi2_internal"
8830 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8831 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8832 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8833 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8834 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8835 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
8836 "!TARGET_IEEEQUAD
8837 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8838 "#"
8839 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[5]))"
8840 [(pc)]
8841 {
8842 rtx lowword;
8843 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8845 gcc_assert (MEM_P (operands[5]));
8846 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8848 emit_insn (gen_fctiwz (operands[4], operands[2]));
8849 emit_move_insn (operands[5], operands[4]);
8850 emit_move_insn (operands[0], lowword);
8851 DONE;
8852 })
8854 (define_expand "negtf2"
8855 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8856 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8857 "!TARGET_IEEEQUAD
8858 && TARGET_HARD_FLOAT
8859 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8860 && TARGET_LONG_DOUBLE_128"
8861 "")
8863 (define_insn "negtf2_internal"
8864 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8865 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8866 "!TARGET_IEEEQUAD
8867 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8868 "*
8869 {
8870 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8871 return \"fneg %L0,%L1\;fneg %0,%1\";
8872 else
8873 return \"fneg %0,%1\;fneg %L0,%L1\";
8874 }"
8875 [(set_attr "type" "fp")
8876 (set_attr "length" "8")])
8878 (define_expand "abstf2"
8879 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8880 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8881 "!TARGET_IEEEQUAD
8882 && TARGET_HARD_FLOAT
8883 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8884 && TARGET_LONG_DOUBLE_128"
8885 "
8886 {
8887 rtx label = gen_label_rtx ();
8888 if (TARGET_E500_DOUBLE)
8889 {
8890 if (flag_unsafe_math_optimizations)
8891 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8892 else
8893 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8894 }
8895 else
8896 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8897 emit_label (label);
8898 DONE;
8899 }")
8901 (define_expand "abstf2_internal"
8902 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8903 (match_operand:TF 1 "gpc_reg_operand" ""))
8904 (set (match_dup 3) (match_dup 5))
8905 (set (match_dup 5) (abs:DF (match_dup 5)))
8906 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8907 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8908 (label_ref (match_operand 2 "" ""))
8909 (pc)))
8910 (set (match_dup 6) (neg:DF (match_dup 6)))]
8911 "!TARGET_IEEEQUAD
8912 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8913 "
8914 {
8915 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8916 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8917 operands[3] = gen_reg_rtx (DFmode);
8918 operands[4] = gen_reg_rtx (CCFPmode);
8919 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8920 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8921 }")
8922 \f
8923 ;; Next come the multi-word integer load and store and the load and store
8924 ;; multiple insns.
8926 ; List r->r after r->"o<>", otherwise reload will try to reload a
8927 ; non-offsettable address by using r->r which won't make progress.
8928 (define_insn "*movdi_internal32"
8929 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8930 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8931 "! TARGET_POWERPC64
8932 && (gpc_reg_operand (operands[0], DImode)
8933 || gpc_reg_operand (operands[1], DImode))"
8934 "@
8935 #
8936 #
8937 #
8938 fmr %0,%1
8939 lfd%U1%X1 %0,%1
8940 stfd%U0%X0 %1,%0
8941 #"
8942 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8944 (define_split
8945 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8946 (match_operand:DI 1 "const_int_operand" ""))]
8947 "! TARGET_POWERPC64 && reload_completed"
8948 [(set (match_dup 2) (match_dup 4))
8949 (set (match_dup 3) (match_dup 1))]
8950 "
8951 {
8952 HOST_WIDE_INT value = INTVAL (operands[1]);
8953 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8954 DImode);
8955 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8956 DImode);
8957 #if HOST_BITS_PER_WIDE_INT == 32
8958 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8959 #else
8960 operands[4] = GEN_INT (value >> 32);
8961 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8962 #endif
8963 }")
8965 (define_split
8966 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "")
8967 (match_operand:DI 1 "input_operand" ""))]
8968 "reload_completed && !TARGET_POWERPC64
8969 && gpr_or_gpr_p (operands[0], operands[1])"
8970 [(pc)]
8971 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8973 (define_insn "*movdi_mfpgpr"
8974 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h,r,*f")
8975 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0,*f,r"))]
8976 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8977 && (gpc_reg_operand (operands[0], DImode)
8978 || gpc_reg_operand (operands[1], DImode))"
8979 "@
8980 mr %0,%1
8981 ld%U1%X1 %0,%1
8982 std%U0%X0 %1,%0
8983 li %0,%1
8984 lis %0,%v1
8985 #
8986 {cal|la} %0,%a1
8987 fmr %0,%1
8988 lfd%U1%X1 %0,%1
8989 stfd%U0%X0 %1,%0
8990 mf%1 %0
8991 mt%0 %1
8992 {cror 0,0,0|nop}
8993 mftgpr %0,%1
8994 mffgpr %0,%1"
8995 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
8996 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
8998 (define_insn "*movdi_internal64"
8999 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
9000 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
9001 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
9002 && (gpc_reg_operand (operands[0], DImode)
9003 || gpc_reg_operand (operands[1], DImode))"
9004 "@
9005 mr %0,%1
9006 ld%U1%X1 %0,%1
9007 std%U0%X0 %1,%0
9008 li %0,%1
9009 lis %0,%v1
9010 #
9011 {cal|la} %0,%a1
9012 fmr %0,%1
9013 lfd%U1%X1 %0,%1
9014 stfd%U0%X0 %1,%0
9015 mf%1 %0
9016 mt%0 %1
9017 {cror 0,0,0|nop}"
9018 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
9019 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
9021 ;; immediate value valid for a single instruction hiding in a const_double
9022 (define_insn ""
9023 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9024 (match_operand:DI 1 "const_double_operand" "F"))]
9025 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9026 && GET_CODE (operands[1]) == CONST_DOUBLE
9027 && num_insns_constant (operands[1], DImode) == 1"
9028 "*
9029 {
9030 return ((unsigned HOST_WIDE_INT)
9031 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9032 ? \"li %0,%1\" : \"lis %0,%v1\";
9033 }")
9035 ;; Generate all one-bits and clear left or right.
9036 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9037 (define_split
9038 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9039 (match_operand:DI 1 "mask64_operand" ""))]
9040 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9041 [(set (match_dup 0) (const_int -1))
9042 (set (match_dup 0)
9043 (and:DI (rotate:DI (match_dup 0)
9044 (const_int 0))
9045 (match_dup 1)))]
9046 "")
9048 ;; Split a load of a large constant into the appropriate five-instruction
9049 ;; sequence. Handle anything in a constant number of insns.
9050 ;; When non-easy constants can go in the TOC, this should use
9051 ;; easy_fp_constant predicate.
9052 (define_split
9053 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9054 (match_operand:DI 1 "const_int_operand" ""))]
9055 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9056 [(set (match_dup 0) (match_dup 2))
9057 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9058 "
9059 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9061 if (tem == operands[0])
9062 DONE;
9063 else
9064 FAIL;
9065 }")
9067 (define_split
9068 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9069 (match_operand:DI 1 "const_double_operand" ""))]
9070 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9071 [(set (match_dup 0) (match_dup 2))
9072 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9073 "
9074 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9076 if (tem == operands[0])
9077 DONE;
9078 else
9079 FAIL;
9080 }")
9081 \f
9082 ;; TImode is similar, except that we usually want to compute the address into
9083 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
9084 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
9086 ;; We say that MQ is clobbered in the last alternative because the first
9087 ;; alternative would never get used otherwise since it would need a reload
9088 ;; while the 2nd alternative would not. We put memory cases first so they
9089 ;; are preferred. Otherwise, we'd try to reload the output instead of
9090 ;; giving the SCRATCH mq.
9092 (define_insn "*movti_power"
9093 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9094 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9095 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
9096 "TARGET_POWER && ! TARGET_POWERPC64
9097 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9098 "*
9099 {
9100 switch (which_alternative)
9101 {
9102 default:
9103 gcc_unreachable ();
9105 case 0:
9106 if (TARGET_STRING)
9107 return \"{stsi|stswi} %1,%P0,16\";
9108 case 1:
9109 case 2:
9110 return \"#\";
9111 case 3:
9112 /* If the address is not used in the output, we can use lsi. Otherwise,
9113 fall through to generating four loads. */
9114 if (TARGET_STRING
9115 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9116 return \"{lsi|lswi} %0,%P1,16\";
9117 /* ... fall through ... */
9118 case 4:
9119 case 5:
9120 return \"#\";
9121 }
9122 }"
9123 [(set_attr "type" "store,store,*,load,load,*")])
9125 (define_insn "*movti_string"
9126 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9127 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
9128 "! TARGET_POWER && ! TARGET_POWERPC64
9129 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9130 "*
9131 {
9132 switch (which_alternative)
9133 {
9134 default:
9135 gcc_unreachable ();
9136 case 0:
9137 if (TARGET_STRING)
9138 return \"{stsi|stswi} %1,%P0,16\";
9139 case 1:
9140 case 2:
9141 return \"#\";
9142 case 3:
9143 /* If the address is not used in the output, we can use lsi. Otherwise,
9144 fall through to generating four loads. */
9145 if (TARGET_STRING
9146 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9147 return \"{lsi|lswi} %0,%P1,16\";
9148 /* ... fall through ... */
9149 case 4:
9150 case 5:
9151 return \"#\";
9152 }
9153 }"
9154 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
9156 (define_insn "*movti_ppc64"
9157 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9158 (match_operand:TI 1 "input_operand" "r,r,m"))]
9159 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9160 || gpc_reg_operand (operands[1], TImode))"
9161 "#"
9162 [(set_attr "type" "*,load,store")])
9164 (define_split
9165 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9166 (match_operand:TI 1 "const_double_operand" ""))]
9167 "TARGET_POWERPC64"
9168 [(set (match_dup 2) (match_dup 4))
9169 (set (match_dup 3) (match_dup 5))]
9170 "
9171 {
9172 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9173 TImode);
9174 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9175 TImode);
9176 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9177 {
9178 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9179 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9180 }
9181 else if (GET_CODE (operands[1]) == CONST_INT)
9182 {
9183 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9184 operands[5] = operands[1];
9185 }
9186 else
9187 FAIL;
9188 }")
9190 (define_split
9191 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9192 (match_operand:TI 1 "input_operand" ""))]
9193 "reload_completed
9194 && gpr_or_gpr_p (operands[0], operands[1])"
9195 [(pc)]
9196 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9197 \f
9198 (define_expand "load_multiple"
9199 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9200 (match_operand:SI 1 "" ""))
9201 (use (match_operand:SI 2 "" ""))])]
9202 "TARGET_STRING && !TARGET_POWERPC64"
9203 "
9204 {
9205 int regno;
9206 int count;
9207 rtx op1;
9208 int i;
9210 /* Support only loading a constant number of fixed-point registers from
9211 memory and only bother with this if more than two; the machine
9212 doesn't support more than eight. */
9213 if (GET_CODE (operands[2]) != CONST_INT
9214 || INTVAL (operands[2]) <= 2
9215 || INTVAL (operands[2]) > 8
9216 || GET_CODE (operands[1]) != MEM
9217 || GET_CODE (operands[0]) != REG
9218 || REGNO (operands[0]) >= 32)
9219 FAIL;
9221 count = INTVAL (operands[2]);
9222 regno = REGNO (operands[0]);
9224 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9225 op1 = replace_equiv_address (operands[1],
9226 force_reg (SImode, XEXP (operands[1], 0)));
9228 for (i = 0; i < count; i++)
9229 XVECEXP (operands[3], 0, i)
9230 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9231 adjust_address_nv (op1, SImode, i * 4));
9232 }")
9234 (define_insn "*ldmsi8"
9235 [(match_parallel 0 "load_multiple_operation"
9236 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9237 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9238 (set (match_operand:SI 3 "gpc_reg_operand" "")
9239 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9240 (set (match_operand:SI 4 "gpc_reg_operand" "")
9241 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9242 (set (match_operand:SI 5 "gpc_reg_operand" "")
9243 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9244 (set (match_operand:SI 6 "gpc_reg_operand" "")
9245 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9246 (set (match_operand:SI 7 "gpc_reg_operand" "")
9247 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9248 (set (match_operand:SI 8 "gpc_reg_operand" "")
9249 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9250 (set (match_operand:SI 9 "gpc_reg_operand" "")
9251 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9252 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9253 "*
9254 { return rs6000_output_load_multiple (operands); }"
9255 [(set_attr "type" "load_ux")
9256 (set_attr "length" "32")])
9258 (define_insn "*ldmsi7"
9259 [(match_parallel 0 "load_multiple_operation"
9260 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9261 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9262 (set (match_operand:SI 3 "gpc_reg_operand" "")
9263 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9264 (set (match_operand:SI 4 "gpc_reg_operand" "")
9265 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9266 (set (match_operand:SI 5 "gpc_reg_operand" "")
9267 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9268 (set (match_operand:SI 6 "gpc_reg_operand" "")
9269 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9270 (set (match_operand:SI 7 "gpc_reg_operand" "")
9271 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9272 (set (match_operand:SI 8 "gpc_reg_operand" "")
9273 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9274 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9275 "*
9276 { return rs6000_output_load_multiple (operands); }"
9277 [(set_attr "type" "load_ux")
9278 (set_attr "length" "32")])
9280 (define_insn "*ldmsi6"
9281 [(match_parallel 0 "load_multiple_operation"
9282 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9283 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9284 (set (match_operand:SI 3 "gpc_reg_operand" "")
9285 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9286 (set (match_operand:SI 4 "gpc_reg_operand" "")
9287 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9288 (set (match_operand:SI 5 "gpc_reg_operand" "")
9289 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9290 (set (match_operand:SI 6 "gpc_reg_operand" "")
9291 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9292 (set (match_operand:SI 7 "gpc_reg_operand" "")
9293 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9294 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9295 "*
9296 { return rs6000_output_load_multiple (operands); }"
9297 [(set_attr "type" "load_ux")
9298 (set_attr "length" "32")])
9300 (define_insn "*ldmsi5"
9301 [(match_parallel 0 "load_multiple_operation"
9302 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9303 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9304 (set (match_operand:SI 3 "gpc_reg_operand" "")
9305 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9306 (set (match_operand:SI 4 "gpc_reg_operand" "")
9307 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9308 (set (match_operand:SI 5 "gpc_reg_operand" "")
9309 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9310 (set (match_operand:SI 6 "gpc_reg_operand" "")
9311 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9312 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9313 "*
9314 { return rs6000_output_load_multiple (operands); }"
9315 [(set_attr "type" "load_ux")
9316 (set_attr "length" "32")])
9318 (define_insn "*ldmsi4"
9319 [(match_parallel 0 "load_multiple_operation"
9320 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9321 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9322 (set (match_operand:SI 3 "gpc_reg_operand" "")
9323 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9324 (set (match_operand:SI 4 "gpc_reg_operand" "")
9325 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9326 (set (match_operand:SI 5 "gpc_reg_operand" "")
9327 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9328 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9329 "*
9330 { return rs6000_output_load_multiple (operands); }"
9331 [(set_attr "type" "load_ux")
9332 (set_attr "length" "32")])
9334 (define_insn "*ldmsi3"
9335 [(match_parallel 0 "load_multiple_operation"
9336 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9337 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9338 (set (match_operand:SI 3 "gpc_reg_operand" "")
9339 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9340 (set (match_operand:SI 4 "gpc_reg_operand" "")
9341 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9342 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9343 "*
9344 { return rs6000_output_load_multiple (operands); }"
9345 [(set_attr "type" "load_ux")
9346 (set_attr "length" "32")])
9348 (define_expand "store_multiple"
9349 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9350 (match_operand:SI 1 "" ""))
9351 (clobber (scratch:SI))
9352 (use (match_operand:SI 2 "" ""))])]
9353 "TARGET_STRING && !TARGET_POWERPC64"
9354 "
9355 {
9356 int regno;
9357 int count;
9358 rtx to;
9359 rtx op0;
9360 int i;
9362 /* Support only storing a constant number of fixed-point registers to
9363 memory and only bother with this if more than two; the machine
9364 doesn't support more than eight. */
9365 if (GET_CODE (operands[2]) != CONST_INT
9366 || INTVAL (operands[2]) <= 2
9367 || INTVAL (operands[2]) > 8
9368 || GET_CODE (operands[0]) != MEM
9369 || GET_CODE (operands[1]) != REG
9370 || REGNO (operands[1]) >= 32)
9371 FAIL;
9373 count = INTVAL (operands[2]);
9374 regno = REGNO (operands[1]);
9376 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9377 to = force_reg (SImode, XEXP (operands[0], 0));
9378 op0 = replace_equiv_address (operands[0], to);
9380 XVECEXP (operands[3], 0, 0)
9381 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9382 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9383 gen_rtx_SCRATCH (SImode));
9385 for (i = 1; i < count; i++)
9386 XVECEXP (operands[3], 0, i + 1)
9387 = gen_rtx_SET (VOIDmode,
9388 adjust_address_nv (op0, SImode, i * 4),
9389 gen_rtx_REG (SImode, regno + i));
9390 }")
9392 (define_insn "*stmsi8"
9393 [(match_parallel 0 "store_multiple_operation"
9394 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9395 (match_operand:SI 2 "gpc_reg_operand" "r"))
9396 (clobber (match_scratch:SI 3 "=X"))
9397 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9398 (match_operand:SI 4 "gpc_reg_operand" "r"))
9399 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9400 (match_operand:SI 5 "gpc_reg_operand" "r"))
9401 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9402 (match_operand:SI 6 "gpc_reg_operand" "r"))
9403 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9404 (match_operand:SI 7 "gpc_reg_operand" "r"))
9405 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9406 (match_operand:SI 8 "gpc_reg_operand" "r"))
9407 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9408 (match_operand:SI 9 "gpc_reg_operand" "r"))
9409 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9410 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9411 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9412 "{stsi|stswi} %2,%1,%O0"
9413 [(set_attr "type" "store_ux")])
9415 (define_insn "*stmsi7"
9416 [(match_parallel 0 "store_multiple_operation"
9417 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9418 (match_operand:SI 2 "gpc_reg_operand" "r"))
9419 (clobber (match_scratch:SI 3 "=X"))
9420 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9421 (match_operand:SI 4 "gpc_reg_operand" "r"))
9422 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9423 (match_operand:SI 5 "gpc_reg_operand" "r"))
9424 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9425 (match_operand:SI 6 "gpc_reg_operand" "r"))
9426 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9427 (match_operand:SI 7 "gpc_reg_operand" "r"))
9428 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9429 (match_operand:SI 8 "gpc_reg_operand" "r"))
9430 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9431 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9432 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9433 "{stsi|stswi} %2,%1,%O0"
9434 [(set_attr "type" "store_ux")])
9436 (define_insn "*stmsi6"
9437 [(match_parallel 0 "store_multiple_operation"
9438 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9439 (match_operand:SI 2 "gpc_reg_operand" "r"))
9440 (clobber (match_scratch:SI 3 "=X"))
9441 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9442 (match_operand:SI 4 "gpc_reg_operand" "r"))
9443 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9444 (match_operand:SI 5 "gpc_reg_operand" "r"))
9445 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9446 (match_operand:SI 6 "gpc_reg_operand" "r"))
9447 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9448 (match_operand:SI 7 "gpc_reg_operand" "r"))
9449 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9450 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9451 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9452 "{stsi|stswi} %2,%1,%O0"
9453 [(set_attr "type" "store_ux")])
9455 (define_insn "*stmsi5"
9456 [(match_parallel 0 "store_multiple_operation"
9457 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9458 (match_operand:SI 2 "gpc_reg_operand" "r"))
9459 (clobber (match_scratch:SI 3 "=X"))
9460 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9461 (match_operand:SI 4 "gpc_reg_operand" "r"))
9462 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9463 (match_operand:SI 5 "gpc_reg_operand" "r"))
9464 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9465 (match_operand:SI 6 "gpc_reg_operand" "r"))
9466 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9467 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9468 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9469 "{stsi|stswi} %2,%1,%O0"
9470 [(set_attr "type" "store_ux")])
9472 (define_insn "*stmsi4"
9473 [(match_parallel 0 "store_multiple_operation"
9474 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9475 (match_operand:SI 2 "gpc_reg_operand" "r"))
9476 (clobber (match_scratch:SI 3 "=X"))
9477 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9478 (match_operand:SI 4 "gpc_reg_operand" "r"))
9479 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9480 (match_operand:SI 5 "gpc_reg_operand" "r"))
9481 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9482 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9483 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9484 "{stsi|stswi} %2,%1,%O0"
9485 [(set_attr "type" "store_ux")])
9487 (define_insn "*stmsi3"
9488 [(match_parallel 0 "store_multiple_operation"
9489 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9490 (match_operand:SI 2 "gpc_reg_operand" "r"))
9491 (clobber (match_scratch:SI 3 "=X"))
9492 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9493 (match_operand:SI 4 "gpc_reg_operand" "r"))
9494 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9495 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9496 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9497 "{stsi|stswi} %2,%1,%O0"
9498 [(set_attr "type" "store_ux")])
9500 (define_insn "*stmsi8_power"
9501 [(match_parallel 0 "store_multiple_operation"
9502 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9503 (match_operand:SI 2 "gpc_reg_operand" "r"))
9504 (clobber (match_scratch:SI 3 "=q"))
9505 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9506 (match_operand:SI 4 "gpc_reg_operand" "r"))
9507 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9508 (match_operand:SI 5 "gpc_reg_operand" "r"))
9509 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9510 (match_operand:SI 6 "gpc_reg_operand" "r"))
9511 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9512 (match_operand:SI 7 "gpc_reg_operand" "r"))
9513 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9514 (match_operand:SI 8 "gpc_reg_operand" "r"))
9515 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9516 (match_operand:SI 9 "gpc_reg_operand" "r"))
9517 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9518 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9519 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9520 "{stsi|stswi} %2,%1,%O0"
9521 [(set_attr "type" "store_ux")])
9523 (define_insn "*stmsi7_power"
9524 [(match_parallel 0 "store_multiple_operation"
9525 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9526 (match_operand:SI 2 "gpc_reg_operand" "r"))
9527 (clobber (match_scratch:SI 3 "=q"))
9528 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9529 (match_operand:SI 4 "gpc_reg_operand" "r"))
9530 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9531 (match_operand:SI 5 "gpc_reg_operand" "r"))
9532 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9533 (match_operand:SI 6 "gpc_reg_operand" "r"))
9534 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9535 (match_operand:SI 7 "gpc_reg_operand" "r"))
9536 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9537 (match_operand:SI 8 "gpc_reg_operand" "r"))
9538 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9539 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9540 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9541 "{stsi|stswi} %2,%1,%O0"
9542 [(set_attr "type" "store_ux")])
9544 (define_insn "*stmsi6_power"
9545 [(match_parallel 0 "store_multiple_operation"
9546 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9547 (match_operand:SI 2 "gpc_reg_operand" "r"))
9548 (clobber (match_scratch:SI 3 "=q"))
9549 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9550 (match_operand:SI 4 "gpc_reg_operand" "r"))
9551 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9552 (match_operand:SI 5 "gpc_reg_operand" "r"))
9553 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9554 (match_operand:SI 6 "gpc_reg_operand" "r"))
9555 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9556 (match_operand:SI 7 "gpc_reg_operand" "r"))
9557 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9558 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9559 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9560 "{stsi|stswi} %2,%1,%O0"
9561 [(set_attr "type" "store_ux")])
9563 (define_insn "*stmsi5_power"
9564 [(match_parallel 0 "store_multiple_operation"
9565 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9566 (match_operand:SI 2 "gpc_reg_operand" "r"))
9567 (clobber (match_scratch:SI 3 "=q"))
9568 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9569 (match_operand:SI 4 "gpc_reg_operand" "r"))
9570 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9571 (match_operand:SI 5 "gpc_reg_operand" "r"))
9572 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9573 (match_operand:SI 6 "gpc_reg_operand" "r"))
9574 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9575 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9576 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9577 "{stsi|stswi} %2,%1,%O0"
9578 [(set_attr "type" "store_ux")])
9580 (define_insn "*stmsi4_power"
9581 [(match_parallel 0 "store_multiple_operation"
9582 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9583 (match_operand:SI 2 "gpc_reg_operand" "r"))
9584 (clobber (match_scratch:SI 3 "=q"))
9585 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9586 (match_operand:SI 4 "gpc_reg_operand" "r"))
9587 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9588 (match_operand:SI 5 "gpc_reg_operand" "r"))
9589 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9590 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9591 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9592 "{stsi|stswi} %2,%1,%O0"
9593 [(set_attr "type" "store_ux")])
9595 (define_insn "*stmsi3_power"
9596 [(match_parallel 0 "store_multiple_operation"
9597 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9598 (match_operand:SI 2 "gpc_reg_operand" "r"))
9599 (clobber (match_scratch:SI 3 "=q"))
9600 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9601 (match_operand:SI 4 "gpc_reg_operand" "r"))
9602 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9603 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9604 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9605 "{stsi|stswi} %2,%1,%O0"
9606 [(set_attr "type" "store_ux")])
9607 \f
9608 (define_expand "setmemsi"
9609 [(parallel [(set (match_operand:BLK 0 "" "")
9610 (match_operand 2 "const_int_operand" ""))
9611 (use (match_operand:SI 1 "" ""))
9612 (use (match_operand:SI 3 "" ""))])]
9613 ""
9614 "
9615 {
9616 /* If value to set is not zero, use the library routine. */
9617 if (operands[2] != const0_rtx)
9618 FAIL;
9620 if (expand_block_clear (operands))
9621 DONE;
9622 else
9623 FAIL;
9624 }")
9626 ;; String/block move insn.
9627 ;; Argument 0 is the destination
9628 ;; Argument 1 is the source
9629 ;; Argument 2 is the length
9630 ;; Argument 3 is the alignment
9632 (define_expand "movmemsi"
9633 [(parallel [(set (match_operand:BLK 0 "" "")
9634 (match_operand:BLK 1 "" ""))
9635 (use (match_operand:SI 2 "" ""))
9636 (use (match_operand:SI 3 "" ""))])]
9637 ""
9638 "
9639 {
9640 if (expand_block_move (operands))
9641 DONE;
9642 else
9643 FAIL;
9644 }")
9646 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9647 ;; register allocator doesn't have a clue about allocating 8 word registers.
9648 ;; rD/rS = r5 is preferred, efficient form.
9649 (define_expand "movmemsi_8reg"
9650 [(parallel [(set (match_operand 0 "" "")
9651 (match_operand 1 "" ""))
9652 (use (match_operand 2 "" ""))
9653 (use (match_operand 3 "" ""))
9654 (clobber (reg:SI 5))
9655 (clobber (reg:SI 6))
9656 (clobber (reg:SI 7))
9657 (clobber (reg:SI 8))
9658 (clobber (reg:SI 9))
9659 (clobber (reg:SI 10))
9660 (clobber (reg:SI 11))
9661 (clobber (reg:SI 12))
9662 (clobber (match_scratch:SI 4 ""))])]
9663 "TARGET_STRING"
9664 "")
9666 (define_insn ""
9667 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9668 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9669 (use (match_operand:SI 2 "immediate_operand" "i"))
9670 (use (match_operand:SI 3 "immediate_operand" "i"))
9671 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9672 (clobber (reg:SI 6))
9673 (clobber (reg:SI 7))
9674 (clobber (reg:SI 8))
9675 (clobber (reg:SI 9))
9676 (clobber (reg:SI 10))
9677 (clobber (reg:SI 11))
9678 (clobber (reg:SI 12))
9679 (clobber (match_scratch:SI 5 "=q"))]
9680 "TARGET_STRING && TARGET_POWER
9681 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9682 || INTVAL (operands[2]) == 0)
9683 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9684 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9685 && REGNO (operands[4]) == 5"
9686 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9687 [(set_attr "type" "store_ux")
9688 (set_attr "length" "8")])
9690 (define_insn ""
9691 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9692 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9693 (use (match_operand:SI 2 "immediate_operand" "i"))
9694 (use (match_operand:SI 3 "immediate_operand" "i"))
9695 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9696 (clobber (reg:SI 6))
9697 (clobber (reg:SI 7))
9698 (clobber (reg:SI 8))
9699 (clobber (reg:SI 9))
9700 (clobber (reg:SI 10))
9701 (clobber (reg:SI 11))
9702 (clobber (reg:SI 12))
9703 (clobber (match_scratch:SI 5 "=X"))]
9704 "TARGET_STRING && ! TARGET_POWER
9705 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9706 || INTVAL (operands[2]) == 0)
9707 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9708 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9709 && REGNO (operands[4]) == 5"
9710 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9711 [(set_attr "type" "store_ux")
9712 (set_attr "length" "8")])
9714 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9715 ;; register allocator doesn't have a clue about allocating 6 word registers.
9716 ;; rD/rS = r5 is preferred, efficient form.
9717 (define_expand "movmemsi_6reg"
9718 [(parallel [(set (match_operand 0 "" "")
9719 (match_operand 1 "" ""))
9720 (use (match_operand 2 "" ""))
9721 (use (match_operand 3 "" ""))
9722 (clobber (reg:SI 5))
9723 (clobber (reg:SI 6))
9724 (clobber (reg:SI 7))
9725 (clobber (reg:SI 8))
9726 (clobber (reg:SI 9))
9727 (clobber (reg:SI 10))
9728 (clobber (match_scratch:SI 4 ""))])]
9729 "TARGET_STRING"
9730 "")
9732 (define_insn ""
9733 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9734 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9735 (use (match_operand:SI 2 "immediate_operand" "i"))
9736 (use (match_operand:SI 3 "immediate_operand" "i"))
9737 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9738 (clobber (reg:SI 6))
9739 (clobber (reg:SI 7))
9740 (clobber (reg:SI 8))
9741 (clobber (reg:SI 9))
9742 (clobber (reg:SI 10))
9743 (clobber (match_scratch:SI 5 "=q"))]
9744 "TARGET_STRING && TARGET_POWER
9745 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9746 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9747 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9748 && REGNO (operands[4]) == 5"
9749 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9750 [(set_attr "type" "store_ux")
9751 (set_attr "length" "8")])
9753 (define_insn ""
9754 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9755 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9756 (use (match_operand:SI 2 "immediate_operand" "i"))
9757 (use (match_operand:SI 3 "immediate_operand" "i"))
9758 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9759 (clobber (reg:SI 6))
9760 (clobber (reg:SI 7))
9761 (clobber (reg:SI 8))
9762 (clobber (reg:SI 9))
9763 (clobber (reg:SI 10))
9764 (clobber (match_scratch:SI 5 "=X"))]
9765 "TARGET_STRING && ! TARGET_POWER
9766 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9767 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9768 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9769 && REGNO (operands[4]) == 5"
9770 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9771 [(set_attr "type" "store_ux")
9772 (set_attr "length" "8")])
9774 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9775 ;; problems with TImode.
9776 ;; rD/rS = r5 is preferred, efficient form.
9777 (define_expand "movmemsi_4reg"
9778 [(parallel [(set (match_operand 0 "" "")
9779 (match_operand 1 "" ""))
9780 (use (match_operand 2 "" ""))
9781 (use (match_operand 3 "" ""))
9782 (clobber (reg:SI 5))
9783 (clobber (reg:SI 6))
9784 (clobber (reg:SI 7))
9785 (clobber (reg:SI 8))
9786 (clobber (match_scratch:SI 4 ""))])]
9787 "TARGET_STRING"
9788 "")
9790 (define_insn ""
9791 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9792 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9793 (use (match_operand:SI 2 "immediate_operand" "i"))
9794 (use (match_operand:SI 3 "immediate_operand" "i"))
9795 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9796 (clobber (reg:SI 6))
9797 (clobber (reg:SI 7))
9798 (clobber (reg:SI 8))
9799 (clobber (match_scratch:SI 5 "=q"))]
9800 "TARGET_STRING && TARGET_POWER
9801 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9802 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9803 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9804 && REGNO (operands[4]) == 5"
9805 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9806 [(set_attr "type" "store_ux")
9807 (set_attr "length" "8")])
9809 (define_insn ""
9810 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9811 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9812 (use (match_operand:SI 2 "immediate_operand" "i"))
9813 (use (match_operand:SI 3 "immediate_operand" "i"))
9814 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9815 (clobber (reg:SI 6))
9816 (clobber (reg:SI 7))
9817 (clobber (reg:SI 8))
9818 (clobber (match_scratch:SI 5 "=X"))]
9819 "TARGET_STRING && ! TARGET_POWER
9820 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9821 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9822 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9823 && REGNO (operands[4]) == 5"
9824 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9825 [(set_attr "type" "store_ux")
9826 (set_attr "length" "8")])
9828 ;; Move up to 8 bytes at a time.
9829 (define_expand "movmemsi_2reg"
9830 [(parallel [(set (match_operand 0 "" "")
9831 (match_operand 1 "" ""))
9832 (use (match_operand 2 "" ""))
9833 (use (match_operand 3 "" ""))
9834 (clobber (match_scratch:DI 4 ""))
9835 (clobber (match_scratch:SI 5 ""))])]
9836 "TARGET_STRING && ! TARGET_POWERPC64"
9837 "")
9839 (define_insn ""
9840 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9841 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9842 (use (match_operand:SI 2 "immediate_operand" "i"))
9843 (use (match_operand:SI 3 "immediate_operand" "i"))
9844 (clobber (match_scratch:DI 4 "=&r"))
9845 (clobber (match_scratch:SI 5 "=q"))]
9846 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9847 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9848 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9849 [(set_attr "type" "store_ux")
9850 (set_attr "length" "8")])
9852 (define_insn ""
9853 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9854 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9855 (use (match_operand:SI 2 "immediate_operand" "i"))
9856 (use (match_operand:SI 3 "immediate_operand" "i"))
9857 (clobber (match_scratch:DI 4 "=&r"))
9858 (clobber (match_scratch:SI 5 "=X"))]
9859 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9860 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9861 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9862 [(set_attr "type" "store_ux")
9863 (set_attr "length" "8")])
9865 ;; Move up to 4 bytes at a time.
9866 (define_expand "movmemsi_1reg"
9867 [(parallel [(set (match_operand 0 "" "")
9868 (match_operand 1 "" ""))
9869 (use (match_operand 2 "" ""))
9870 (use (match_operand 3 "" ""))
9871 (clobber (match_scratch:SI 4 ""))
9872 (clobber (match_scratch:SI 5 ""))])]
9873 "TARGET_STRING"
9874 "")
9876 (define_insn ""
9877 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9878 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9879 (use (match_operand:SI 2 "immediate_operand" "i"))
9880 (use (match_operand:SI 3 "immediate_operand" "i"))
9881 (clobber (match_scratch:SI 4 "=&r"))
9882 (clobber (match_scratch:SI 5 "=q"))]
9883 "TARGET_STRING && TARGET_POWER
9884 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9885 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9886 [(set_attr "type" "store_ux")
9887 (set_attr "length" "8")])
9889 (define_insn ""
9890 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9891 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9892 (use (match_operand:SI 2 "immediate_operand" "i"))
9893 (use (match_operand:SI 3 "immediate_operand" "i"))
9894 (clobber (match_scratch:SI 4 "=&r"))
9895 (clobber (match_scratch:SI 5 "=X"))]
9896 "TARGET_STRING && ! TARGET_POWER
9897 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9898 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9899 [(set_attr "type" "store_ux")
9900 (set_attr "length" "8")])
9901 \f
9902 ;; Define insns that do load or store with update. Some of these we can
9903 ;; get by using pre-decrement or pre-increment, but the hardware can also
9904 ;; do cases where the increment is not the size of the object.
9905 ;;
9906 ;; In all these cases, we use operands 0 and 1 for the register being
9907 ;; incremented because those are the operands that local-alloc will
9908 ;; tie and these are the pair most likely to be tieable (and the ones
9909 ;; that will benefit the most).
9911 (define_insn "*movdi_update1"
9912 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9913 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9914 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9915 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9916 (plus:DI (match_dup 1) (match_dup 2)))]
9917 "TARGET_POWERPC64 && TARGET_UPDATE"
9918 "@
9919 ldux %3,%0,%2
9920 ldu %3,%2(%0)"
9921 [(set_attr "type" "load_ux,load_u")])
9923 (define_insn "movdi_<mode>_update"
9924 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9925 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9926 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9927 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9928 (plus:P (match_dup 1) (match_dup 2)))]
9929 "TARGET_POWERPC64 && TARGET_UPDATE"
9930 "@
9931 stdux %3,%0,%2
9932 stdu %3,%2(%0)"
9933 [(set_attr "type" "store_ux,store_u")])
9935 (define_insn "*movsi_update1"
9936 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9937 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9938 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9939 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9940 (plus:SI (match_dup 1) (match_dup 2)))]
9941 "TARGET_UPDATE"
9942 "@
9943 {lux|lwzux} %3,%0,%2
9944 {lu|lwzu} %3,%2(%0)"
9945 [(set_attr "type" "load_ux,load_u")])
9947 (define_insn "*movsi_update2"
9948 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9949 (sign_extend:DI
9950 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9951 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9952 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9953 (plus:DI (match_dup 1) (match_dup 2)))]
9954 "TARGET_POWERPC64"
9955 "lwaux %3,%0,%2"
9956 [(set_attr "type" "load_ext_ux")])
9958 (define_insn "movsi_update"
9959 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9960 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9961 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9962 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9963 (plus:SI (match_dup 1) (match_dup 2)))]
9964 "TARGET_UPDATE"
9965 "@
9966 {stux|stwux} %3,%0,%2
9967 {stu|stwu} %3,%2(%0)"
9968 [(set_attr "type" "store_ux,store_u")])
9970 (define_insn "*movhi_update1"
9971 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9972 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9973 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9974 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9975 (plus:SI (match_dup 1) (match_dup 2)))]
9976 "TARGET_UPDATE"
9977 "@
9978 lhzux %3,%0,%2
9979 lhzu %3,%2(%0)"
9980 [(set_attr "type" "load_ux,load_u")])
9982 (define_insn "*movhi_update2"
9983 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9984 (zero_extend:SI
9985 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9986 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9987 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9988 (plus:SI (match_dup 1) (match_dup 2)))]
9989 "TARGET_UPDATE"
9990 "@
9991 lhzux %3,%0,%2
9992 lhzu %3,%2(%0)"
9993 [(set_attr "type" "load_ux,load_u")])
9995 (define_insn "*movhi_update3"
9996 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9997 (sign_extend:SI
9998 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9999 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10000 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10001 (plus:SI (match_dup 1) (match_dup 2)))]
10002 "TARGET_UPDATE"
10003 "@
10004 lhaux %3,%0,%2
10005 lhau %3,%2(%0)"
10006 [(set_attr "type" "load_ext_ux,load_ext_u")])
10008 (define_insn "*movhi_update4"
10009 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10010 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10011 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
10012 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10013 (plus:SI (match_dup 1) (match_dup 2)))]
10014 "TARGET_UPDATE"
10015 "@
10016 sthux %3,%0,%2
10017 sthu %3,%2(%0)"
10018 [(set_attr "type" "store_ux,store_u")])
10020 (define_insn "*movqi_update1"
10021 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10022 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10023 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10024 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10025 (plus:SI (match_dup 1) (match_dup 2)))]
10026 "TARGET_UPDATE"
10027 "@
10028 lbzux %3,%0,%2
10029 lbzu %3,%2(%0)"
10030 [(set_attr "type" "load_ux,load_u")])
10032 (define_insn "*movqi_update2"
10033 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10034 (zero_extend:SI
10035 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10036 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10037 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10038 (plus:SI (match_dup 1) (match_dup 2)))]
10039 "TARGET_UPDATE"
10040 "@
10041 lbzux %3,%0,%2
10042 lbzu %3,%2(%0)"
10043 [(set_attr "type" "load_ux,load_u")])
10045 (define_insn "*movqi_update3"
10046 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10047 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10048 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10049 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10050 (plus:SI (match_dup 1) (match_dup 2)))]
10051 "TARGET_UPDATE"
10052 "@
10053 stbux %3,%0,%2
10054 stbu %3,%2(%0)"
10055 [(set_attr "type" "store_ux,store_u")])
10057 (define_insn "*movsf_update1"
10058 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10059 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10060 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10061 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10062 (plus:SI (match_dup 1) (match_dup 2)))]
10063 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
10064 "@
10065 lfsux %3,%0,%2
10066 lfsu %3,%2(%0)"
10067 [(set_attr "type" "fpload_ux,fpload_u")])
10069 (define_insn "*movsf_update2"
10070 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10071 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10072 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10073 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10074 (plus:SI (match_dup 1) (match_dup 2)))]
10075 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
10076 "@
10077 stfsux %3,%0,%2
10078 stfsu %3,%2(%0)"
10079 [(set_attr "type" "fpstore_ux,fpstore_u")])
10081 (define_insn "*movsf_update3"
10082 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10083 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10084 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10085 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10086 (plus:SI (match_dup 1) (match_dup 2)))]
10087 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
10088 "@
10089 {lux|lwzux} %3,%0,%2
10090 {lu|lwzu} %3,%2(%0)"
10091 [(set_attr "type" "load_ux,load_u")])
10093 (define_insn "*movsf_update4"
10094 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10095 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10096 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10097 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10098 (plus:SI (match_dup 1) (match_dup 2)))]
10099 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
10100 "@
10101 {stux|stwux} %3,%0,%2
10102 {stu|stwu} %3,%2(%0)"
10103 [(set_attr "type" "store_ux,store_u")])
10105 (define_insn "*movdf_update1"
10106 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
10107 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10108 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10109 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10110 (plus:SI (match_dup 1) (match_dup 2)))]
10111 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
10112 "@
10113 lfdux %3,%0,%2
10114 lfdu %3,%2(%0)"
10115 [(set_attr "type" "fpload_ux,fpload_u")])
10117 (define_insn "*movdf_update2"
10118 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10119 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10120 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
10121 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10122 (plus:SI (match_dup 1) (match_dup 2)))]
10123 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
10124 "@
10125 stfdux %3,%0,%2
10126 stfdu %3,%2(%0)"
10127 [(set_attr "type" "fpstore_ux,fpstore_u")])
10129 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10131 (define_insn "*lfq_power2"
10132 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10133 (match_operand:V2DF 1 "memory_operand" ""))]
10134 "TARGET_POWER2
10135 && TARGET_HARD_FLOAT && TARGET_FPRS"
10136 "lfq%U1%X1 %0,%1")
10138 (define_peephole2
10139 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10140 (match_operand:DF 1 "memory_operand" ""))
10141 (set (match_operand:DF 2 "gpc_reg_operand" "")
10142 (match_operand:DF 3 "memory_operand" ""))]
10143 "TARGET_POWER2
10144 && TARGET_HARD_FLOAT && TARGET_FPRS
10145 && registers_ok_for_quad_peep (operands[0], operands[2])
10146 && mems_ok_for_quad_peep (operands[1], operands[3])"
10147 [(set (match_dup 0)
10148 (match_dup 1))]
10149 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10150 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
10152 (define_insn "*stfq_power2"
10153 [(set (match_operand:V2DF 0 "memory_operand" "")
10154 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
10155 "TARGET_POWER2
10156 && TARGET_HARD_FLOAT && TARGET_FPRS"
10157 "stfq%U0%X0 %1,%0")
10160 (define_peephole2
10161 [(set (match_operand:DF 0 "memory_operand" "")
10162 (match_operand:DF 1 "gpc_reg_operand" ""))
10163 (set (match_operand:DF 2 "memory_operand" "")
10164 (match_operand:DF 3 "gpc_reg_operand" ""))]
10165 "TARGET_POWER2
10166 && TARGET_HARD_FLOAT && TARGET_FPRS
10167 && registers_ok_for_quad_peep (operands[1], operands[3])
10168 && mems_ok_for_quad_peep (operands[0], operands[2])"
10169 [(set (match_dup 0)
10170 (match_dup 1))]
10171 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10172 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
10174 ;; After inserting conditional returns we can sometimes have
10175 ;; unnecessary register moves. Unfortunately we cannot have a
10176 ;; modeless peephole here, because some single SImode sets have early
10177 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10178 ;; sequences, using get_attr_length here will smash the operands
10179 ;; array. Neither is there an early_cobbler_p predicate.
10180 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10181 (define_peephole2
10182 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10183 (match_operand:DF 1 "any_operand" ""))
10184 (set (match_operand:DF 2 "gpc_reg_operand" "")
10185 (match_dup 0))]
10186 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10187 && peep2_reg_dead_p (2, operands[0])"
10188 [(set (match_dup 2) (match_dup 1))])
10190 (define_peephole2
10191 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10192 (match_operand:SF 1 "any_operand" ""))
10193 (set (match_operand:SF 2 "gpc_reg_operand" "")
10194 (match_dup 0))]
10195 "peep2_reg_dead_p (2, operands[0])"
10196 [(set (match_dup 2) (match_dup 1))])
10198 \f
10199 ;; TLS support.
10201 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
10202 (define_insn "tls_gd_32"
10203 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10204 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10205 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10206 UNSPEC_TLSGD))]
10207 "HAVE_AS_TLS && !TARGET_64BIT"
10208 "addi %0,%1,%2@got@tlsgd")
10210 (define_insn "tls_gd_64"
10211 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10212 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10213 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10214 UNSPEC_TLSGD))]
10215 "HAVE_AS_TLS && TARGET_64BIT"
10216 "addi %0,%1,%2@got@tlsgd")
10218 (define_insn "tls_ld_32"
10219 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10220 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
10221 UNSPEC_TLSLD))]
10222 "HAVE_AS_TLS && !TARGET_64BIT"
10223 "addi %0,%1,%&@got@tlsld")
10225 (define_insn "tls_ld_64"
10226 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10227 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
10228 UNSPEC_TLSLD))]
10229 "HAVE_AS_TLS && TARGET_64BIT"
10230 "addi %0,%1,%&@got@tlsld")
10232 (define_insn "tls_dtprel_32"
10233 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10234 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10235 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10236 UNSPEC_TLSDTPREL))]
10237 "HAVE_AS_TLS && !TARGET_64BIT"
10238 "addi %0,%1,%2@dtprel")
10240 (define_insn "tls_dtprel_64"
10241 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10242 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10243 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10244 UNSPEC_TLSDTPREL))]
10245 "HAVE_AS_TLS && TARGET_64BIT"
10246 "addi %0,%1,%2@dtprel")
10248 (define_insn "tls_dtprel_ha_32"
10249 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10250 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10251 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10252 UNSPEC_TLSDTPRELHA))]
10253 "HAVE_AS_TLS && !TARGET_64BIT"
10254 "addis %0,%1,%2@dtprel@ha")
10256 (define_insn "tls_dtprel_ha_64"
10257 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10258 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10259 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10260 UNSPEC_TLSDTPRELHA))]
10261 "HAVE_AS_TLS && TARGET_64BIT"
10262 "addis %0,%1,%2@dtprel@ha")
10264 (define_insn "tls_dtprel_lo_32"
10265 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10266 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10267 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10268 UNSPEC_TLSDTPRELLO))]
10269 "HAVE_AS_TLS && !TARGET_64BIT"
10270 "addi %0,%1,%2@dtprel@l")
10272 (define_insn "tls_dtprel_lo_64"
10273 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10274 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10275 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10276 UNSPEC_TLSDTPRELLO))]
10277 "HAVE_AS_TLS && TARGET_64BIT"
10278 "addi %0,%1,%2@dtprel@l")
10280 (define_insn "tls_got_dtprel_32"
10281 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10282 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10283 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10284 UNSPEC_TLSGOTDTPREL))]
10285 "HAVE_AS_TLS && !TARGET_64BIT"
10286 "lwz %0,%2@got@dtprel(%1)")
10288 (define_insn "tls_got_dtprel_64"
10289 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10290 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10291 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10292 UNSPEC_TLSGOTDTPREL))]
10293 "HAVE_AS_TLS && TARGET_64BIT"
10294 "ld %0,%2@got@dtprel(%1)")
10296 (define_insn "tls_tprel_32"
10297 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10298 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10299 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10300 UNSPEC_TLSTPREL))]
10301 "HAVE_AS_TLS && !TARGET_64BIT"
10302 "addi %0,%1,%2@tprel")
10304 (define_insn "tls_tprel_64"
10305 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10306 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10307 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10308 UNSPEC_TLSTPREL))]
10309 "HAVE_AS_TLS && TARGET_64BIT"
10310 "addi %0,%1,%2@tprel")
10312 (define_insn "tls_tprel_ha_32"
10313 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10314 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10315 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10316 UNSPEC_TLSTPRELHA))]
10317 "HAVE_AS_TLS && !TARGET_64BIT"
10318 "addis %0,%1,%2@tprel@ha")
10320 (define_insn "tls_tprel_ha_64"
10321 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10322 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10323 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10324 UNSPEC_TLSTPRELHA))]
10325 "HAVE_AS_TLS && TARGET_64BIT"
10326 "addis %0,%1,%2@tprel@ha")
10328 (define_insn "tls_tprel_lo_32"
10329 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10330 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10331 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10332 UNSPEC_TLSTPRELLO))]
10333 "HAVE_AS_TLS && !TARGET_64BIT"
10334 "addi %0,%1,%2@tprel@l")
10336 (define_insn "tls_tprel_lo_64"
10337 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10338 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10339 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10340 UNSPEC_TLSTPRELLO))]
10341 "HAVE_AS_TLS && TARGET_64BIT"
10342 "addi %0,%1,%2@tprel@l")
10344 ;; "b" output constraint here and on tls_tls input to support linker tls
10345 ;; optimization. The linker may edit the instructions emitted by a
10346 ;; tls_got_tprel/tls_tls pair to addis,addi.
10347 (define_insn "tls_got_tprel_32"
10348 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10349 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10350 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10351 UNSPEC_TLSGOTTPREL))]
10352 "HAVE_AS_TLS && !TARGET_64BIT"
10353 "lwz %0,%2@got@tprel(%1)")
10355 (define_insn "tls_got_tprel_64"
10356 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10357 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10358 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10359 UNSPEC_TLSGOTTPREL))]
10360 "HAVE_AS_TLS && TARGET_64BIT"
10361 "ld %0,%2@got@tprel(%1)")
10363 (define_insn "tls_tls_32"
10364 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10365 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
10366 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10367 UNSPEC_TLSTLS))]
10368 "HAVE_AS_TLS && !TARGET_64BIT"
10369 "add %0,%1,%2@tls")
10371 (define_insn "tls_tls_64"
10372 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10373 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
10374 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10375 UNSPEC_TLSTLS))]
10376 "HAVE_AS_TLS && TARGET_64BIT"
10377 "add %0,%1,%2@tls")
10378 \f
10379 ;; Next come insns related to the calling sequence.
10380 ;;
10381 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10382 ;; We move the back-chain and decrement the stack pointer.
10384 (define_expand "allocate_stack"
10385 [(set (match_operand 0 "gpc_reg_operand" "")
10386 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10387 (set (reg 1)
10388 (minus (reg 1) (match_dup 1)))]
10389 ""
10390 "
10391 { rtx chain = gen_reg_rtx (Pmode);
10392 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10393 rtx neg_op0;
10395 emit_move_insn (chain, stack_bot);
10397 /* Check stack bounds if necessary. */
10398 if (current_function_limit_stack)
10399 {
10400 rtx available;
10401 available = expand_binop (Pmode, sub_optab,
10402 stack_pointer_rtx, stack_limit_rtx,
10403 NULL_RTX, 1, OPTAB_WIDEN);
10404 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10405 }
10407 if (GET_CODE (operands[1]) != CONST_INT
10408 || INTVAL (operands[1]) < -32767
10409 || INTVAL (operands[1]) > 32768)
10410 {
10411 neg_op0 = gen_reg_rtx (Pmode);
10412 if (TARGET_32BIT)
10413 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10414 else
10415 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10416 }
10417 else
10418 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10420 if (TARGET_UPDATE)
10421 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
10422 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
10424 else
10425 {
10426 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10427 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
10428 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
10429 }
10431 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10432 DONE;
10433 }")
10435 ;; These patterns say how to save and restore the stack pointer. We need not
10436 ;; save the stack pointer at function level since we are careful to
10437 ;; preserve the backchain. At block level, we have to restore the backchain
10438 ;; when we restore the stack pointer.
10439 ;;
10440 ;; For nonlocal gotos, we must save both the stack pointer and its
10441 ;; backchain and restore both. Note that in the nonlocal case, the
10442 ;; save area is a memory location.
10444 (define_expand "save_stack_function"
10445 [(match_operand 0 "any_operand" "")
10446 (match_operand 1 "any_operand" "")]
10447 ""
10448 "DONE;")
10450 (define_expand "restore_stack_function"
10451 [(match_operand 0 "any_operand" "")
10452 (match_operand 1 "any_operand" "")]
10453 ""
10454 "DONE;")
10456 ;; Adjust stack pointer (op0) to a new value (op1).
10457 ;; First copy old stack backchain to new location, and ensure that the
10458 ;; scheduler won't reorder the sp assignment before the backchain write.
10459 (define_expand "restore_stack_block"
10460 [(set (match_dup 2) (match_dup 3))
10461 (set (match_dup 4) (match_dup 2))
10462 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10463 (set (match_operand 0 "register_operand" "")
10464 (match_operand 1 "register_operand" ""))]
10465 ""
10466 "
10467 {
10468 operands[2] = gen_reg_rtx (Pmode);
10469 operands[3] = gen_frame_mem (Pmode, operands[0]);
10470 operands[4] = gen_frame_mem (Pmode, operands[1]);
10471 operands[5] = gen_frame_mem (BLKmode, operands[0]);
10472 }")
10474 (define_expand "save_stack_nonlocal"
10475 [(set (match_dup 3) (match_dup 4))
10476 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10477 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10478 ""
10479 "
10480 {
10481 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10483 /* Copy the backchain to the first word, sp to the second. */
10484 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10485 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10486 operands[3] = gen_reg_rtx (Pmode);
10487 operands[4] = gen_frame_mem (Pmode, operands[1]);
10488 }")
10490 (define_expand "restore_stack_nonlocal"
10491 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10492 (set (match_dup 3) (match_dup 4))
10493 (set (match_dup 5) (match_dup 2))
10494 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10495 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10496 ""
10497 "
10498 {
10499 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10501 /* Restore the backchain from the first word, sp from the second. */
10502 operands[2] = gen_reg_rtx (Pmode);
10503 operands[3] = gen_reg_rtx (Pmode);
10504 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10505 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10506 operands[5] = gen_frame_mem (Pmode, operands[3]);
10507 operands[6] = gen_frame_mem (BLKmode, operands[0]);
10508 }")
10509 \f
10510 ;; TOC register handling.
10512 ;; Code to initialize the TOC register...
10514 (define_insn "load_toc_aix_si"
10515 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10516 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10517 (use (reg:SI 2))])]
10518 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10519 "*
10520 {
10521 char buf[30];
10522 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10523 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10524 operands[2] = gen_rtx_REG (Pmode, 2);
10525 return \"{l|lwz} %0,%1(%2)\";
10526 }"
10527 [(set_attr "type" "load")])
10529 (define_insn "load_toc_aix_di"
10530 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10531 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10532 (use (reg:DI 2))])]
10533 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10534 "*
10535 {
10536 char buf[30];
10537 #ifdef TARGET_RELOCATABLE
10538 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10539 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10540 #else
10541 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10542 #endif
10543 if (TARGET_ELF)
10544 strcat (buf, \"@toc\");
10545 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10546 operands[2] = gen_rtx_REG (Pmode, 2);
10547 return \"ld %0,%1(%2)\";
10548 }"
10549 [(set_attr "type" "load")])
10551 (define_insn "load_toc_v4_pic_si"
10552 [(set (reg:SI LR_REGNO)
10553 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10554 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10555 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10556 [(set_attr "type" "branch")
10557 (set_attr "length" "4")])
10559 (define_insn "load_toc_v4_PIC_1"
10560 [(set (reg:SI LR_REGNO)
10561 (match_operand:SI 0 "immediate_operand" "s"))
10562 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10563 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10564 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10565 "bcl 20,31,%0\\n%0:"
10566 [(set_attr "type" "branch")
10567 (set_attr "length" "4")])
10569 (define_insn "load_toc_v4_PIC_1b"
10570 [(set (reg:SI LR_REGNO)
10571 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")]
10572 UNSPEC_TOCPTR))]
10573 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10574 "bcl 20,31,$+8\\n\\t.long %0-$"
10575 [(set_attr "type" "branch")
10576 (set_attr "length" "8")])
10578 (define_insn "load_toc_v4_PIC_2"
10579 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10580 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10581 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10582 (match_operand:SI 3 "immediate_operand" "s")))))]
10583 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10584 "{l|lwz} %0,%2-%3(%1)"
10585 [(set_attr "type" "load")])
10587 (define_insn "load_toc_v4_PIC_3b"
10588 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10589 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10590 (high:SI
10591 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10592 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10593 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10594 "{cau|addis} %0,%1,%2-%3@ha")
10596 (define_insn "load_toc_v4_PIC_3c"
10597 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10598 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10599 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10600 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10601 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10602 "{cal|addi} %0,%1,%2-%3@l")
10604 ;; If the TOC is shared over a translation unit, as happens with all
10605 ;; the kinds of PIC that we support, we need to restore the TOC
10606 ;; pointer only when jumping over units of translation.
10607 ;; On Darwin, we need to reload the picbase.
10609 (define_expand "builtin_setjmp_receiver"
10610 [(use (label_ref (match_operand 0 "" "")))]
10611 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10612 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10613 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10614 "
10615 {
10616 #if TARGET_MACHO
10617 if (DEFAULT_ABI == ABI_DARWIN)
10618 {
10619 const char *picbase = machopic_function_base_name ();
10620 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10621 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10622 rtx tmplabrtx;
10623 char tmplab[20];
10625 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10626 CODE_LABEL_NUMBER (operands[0]));
10627 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10629 emit_insn (gen_load_macho_picbase (tmplabrtx));
10630 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
10631 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10632 }
10633 else
10634 #endif
10635 rs6000_emit_load_toc_table (FALSE);
10636 DONE;
10637 }")
10639 ;; Elf specific ways of loading addresses for non-PIC code.
10640 ;; The output of this could be r0, but we make a very strong
10641 ;; preference for a base register because it will usually
10642 ;; be needed there.
10643 (define_insn "elf_high"
10644 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10645 (high:SI (match_operand 1 "" "")))]
10646 "TARGET_ELF && ! TARGET_64BIT"
10647 "{liu|lis} %0,%1@ha")
10649 (define_insn "elf_low"
10650 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10651 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10652 (match_operand 2 "" "")))]
10653 "TARGET_ELF && ! TARGET_64BIT"
10654 "@
10655 {cal|la} %0,%2@l(%1)
10656 {ai|addic} %0,%1,%K2")
10657 \f
10658 ;; A function pointer under AIX is a pointer to a data area whose first word
10659 ;; contains the actual address of the function, whose second word contains a
10660 ;; pointer to its TOC, and whose third word contains a value to place in the
10661 ;; static chain register (r11). Note that if we load the static chain, our
10662 ;; "trampoline" need not have any executable code.
10664 (define_expand "call_indirect_aix32"
10665 [(set (match_dup 2)
10666 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10667 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10668 (reg:SI 2))
10669 (set (reg:SI 2)
10670 (mem:SI (plus:SI (match_dup 0)
10671 (const_int 4))))
10672 (set (reg:SI 11)
10673 (mem:SI (plus:SI (match_dup 0)
10674 (const_int 8))))
10675 (parallel [(call (mem:SI (match_dup 2))
10676 (match_operand 1 "" ""))
10677 (use (reg:SI 2))
10678 (use (reg:SI 11))
10679 (set (reg:SI 2)
10680 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10681 (clobber (reg:SI LR_REGNO))])]
10682 "TARGET_32BIT"
10683 "
10684 { operands[2] = gen_reg_rtx (SImode); }")
10686 (define_expand "call_indirect_aix64"
10687 [(set (match_dup 2)
10688 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10689 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10690 (reg:DI 2))
10691 (set (reg:DI 2)
10692 (mem:DI (plus:DI (match_dup 0)
10693 (const_int 8))))
10694 (set (reg:DI 11)
10695 (mem:DI (plus:DI (match_dup 0)
10696 (const_int 16))))
10697 (parallel [(call (mem:SI (match_dup 2))
10698 (match_operand 1 "" ""))
10699 (use (reg:DI 2))
10700 (use (reg:DI 11))
10701 (set (reg:DI 2)
10702 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10703 (clobber (reg:SI LR_REGNO))])]
10704 "TARGET_64BIT"
10705 "
10706 { operands[2] = gen_reg_rtx (DImode); }")
10708 (define_expand "call_value_indirect_aix32"
10709 [(set (match_dup 3)
10710 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10711 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10712 (reg:SI 2))
10713 (set (reg:SI 2)
10714 (mem:SI (plus:SI (match_dup 1)
10715 (const_int 4))))
10716 (set (reg:SI 11)
10717 (mem:SI (plus:SI (match_dup 1)
10718 (const_int 8))))
10719 (parallel [(set (match_operand 0 "" "")
10720 (call (mem:SI (match_dup 3))
10721 (match_operand 2 "" "")))
10722 (use (reg:SI 2))
10723 (use (reg:SI 11))
10724 (set (reg:SI 2)
10725 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10726 (clobber (reg:SI LR_REGNO))])]
10727 "TARGET_32BIT"
10728 "
10729 { operands[3] = gen_reg_rtx (SImode); }")
10731 (define_expand "call_value_indirect_aix64"
10732 [(set (match_dup 3)
10733 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10734 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10735 (reg:DI 2))
10736 (set (reg:DI 2)
10737 (mem:DI (plus:DI (match_dup 1)
10738 (const_int 8))))
10739 (set (reg:DI 11)
10740 (mem:DI (plus:DI (match_dup 1)
10741 (const_int 16))))
10742 (parallel [(set (match_operand 0 "" "")
10743 (call (mem:SI (match_dup 3))
10744 (match_operand 2 "" "")))
10745 (use (reg:DI 2))
10746 (use (reg:DI 11))
10747 (set (reg:DI 2)
10748 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10749 (clobber (reg:SI LR_REGNO))])]
10750 "TARGET_64BIT"
10751 "
10752 { operands[3] = gen_reg_rtx (DImode); }")
10754 ;; Now the definitions for the call and call_value insns
10755 (define_expand "call"
10756 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10757 (match_operand 1 "" ""))
10758 (use (match_operand 2 "" ""))
10759 (clobber (reg:SI LR_REGNO))])]
10760 ""
10761 "
10762 {
10763 #if TARGET_MACHO
10764 if (MACHOPIC_INDIRECT)
10765 operands[0] = machopic_indirect_call_target (operands[0]);
10766 #endif
10768 gcc_assert (GET_CODE (operands[0]) == MEM);
10769 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10771 operands[0] = XEXP (operands[0], 0);
10773 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10774 && flag_pic
10775 && GET_CODE (operands[0]) == SYMBOL_REF
10776 && !SYMBOL_REF_LOCAL_P (operands[0]))
10777 {
10778 rtx call;
10779 rtvec tmp;
10781 tmp = gen_rtvec (3,
10782 gen_rtx_CALL (VOIDmode,
10783 gen_rtx_MEM (SImode, operands[0]),
10784 operands[1]),
10785 gen_rtx_USE (VOIDmode, operands[2]),
10786 gen_rtx_CLOBBER (VOIDmode,
10787 gen_rtx_REG (Pmode, LR_REGNO)));
10788 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10789 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10790 DONE;
10791 }
10793 if (GET_CODE (operands[0]) != SYMBOL_REF
10794 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10795 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10796 {
10797 if (INTVAL (operands[2]) & CALL_LONG)
10798 operands[0] = rs6000_longcall_ref (operands[0]);
10800 switch (DEFAULT_ABI)
10801 {
10802 case ABI_V4:
10803 case ABI_DARWIN:
10804 operands[0] = force_reg (Pmode, operands[0]);
10805 break;
10807 case ABI_AIX:
10808 /* AIX function pointers are really pointers to a three word
10809 area. */
10810 emit_call_insn (TARGET_32BIT
10811 ? gen_call_indirect_aix32 (force_reg (SImode,
10812 operands[0]),
10813 operands[1])
10814 : gen_call_indirect_aix64 (force_reg (DImode,
10815 operands[0]),
10816 operands[1]));
10817 DONE;
10819 default:
10820 gcc_unreachable ();
10821 }
10822 }
10823 }")
10825 (define_expand "call_value"
10826 [(parallel [(set (match_operand 0 "" "")
10827 (call (mem:SI (match_operand 1 "address_operand" ""))
10828 (match_operand 2 "" "")))
10829 (use (match_operand 3 "" ""))
10830 (clobber (reg:SI LR_REGNO))])]
10831 ""
10832 "
10833 {
10834 #if TARGET_MACHO
10835 if (MACHOPIC_INDIRECT)
10836 operands[1] = machopic_indirect_call_target (operands[1]);
10837 #endif
10839 gcc_assert (GET_CODE (operands[1]) == MEM);
10840 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10842 operands[1] = XEXP (operands[1], 0);
10844 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10845 && flag_pic
10846 && GET_CODE (operands[1]) == SYMBOL_REF
10847 && !SYMBOL_REF_LOCAL_P (operands[1]))
10848 {
10849 rtx call;
10850 rtvec tmp;
10852 tmp = gen_rtvec (3,
10853 gen_rtx_SET (VOIDmode,
10854 operands[0],
10855 gen_rtx_CALL (VOIDmode,
10856 gen_rtx_MEM (SImode,
10857 operands[1]),
10858 operands[2])),
10859 gen_rtx_USE (VOIDmode, operands[3]),
10860 gen_rtx_CLOBBER (VOIDmode,
10861 gen_rtx_REG (Pmode, LR_REGNO)));
10862 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10863 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10864 DONE;
10865 }
10867 if (GET_CODE (operands[1]) != SYMBOL_REF
10868 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10869 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10870 {
10871 if (INTVAL (operands[3]) & CALL_LONG)
10872 operands[1] = rs6000_longcall_ref (operands[1]);
10874 switch (DEFAULT_ABI)
10875 {
10876 case ABI_V4:
10877 case ABI_DARWIN:
10878 operands[1] = force_reg (Pmode, operands[1]);
10879 break;
10881 case ABI_AIX:
10882 /* AIX function pointers are really pointers to a three word
10883 area. */
10884 emit_call_insn (TARGET_32BIT
10885 ? gen_call_value_indirect_aix32 (operands[0],
10886 force_reg (SImode,
10887 operands[1]),
10888 operands[2])
10889 : gen_call_value_indirect_aix64 (operands[0],
10890 force_reg (DImode,
10891 operands[1]),
10892 operands[2]));
10893 DONE;
10895 default:
10896 gcc_unreachable ();
10897 }
10898 }
10899 }")
10901 ;; Call to function in current module. No TOC pointer reload needed.
10902 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10903 ;; either the function was not prototyped, or it was prototyped as a
10904 ;; variable argument function. It is > 0 if FP registers were passed
10905 ;; and < 0 if they were not.
10907 (define_insn "*call_local32"
10908 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10909 (match_operand 1 "" "g,g"))
10910 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10911 (clobber (reg:SI LR_REGNO))]
10912 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10913 "*
10914 {
10915 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10916 output_asm_insn (\"crxor 6,6,6\", operands);
10918 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10919 output_asm_insn (\"creqv 6,6,6\", operands);
10921 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10922 }"
10923 [(set_attr "type" "branch")
10924 (set_attr "length" "4,8")])
10926 (define_insn "*call_local64"
10927 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10928 (match_operand 1 "" "g,g"))
10929 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10930 (clobber (reg:SI LR_REGNO))]
10931 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10932 "*
10933 {
10934 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10935 output_asm_insn (\"crxor 6,6,6\", operands);
10937 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10938 output_asm_insn (\"creqv 6,6,6\", operands);
10940 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10941 }"
10942 [(set_attr "type" "branch")
10943 (set_attr "length" "4,8")])
10945 (define_insn "*call_value_local32"
10946 [(set (match_operand 0 "" "")
10947 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10948 (match_operand 2 "" "g,g")))
10949 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10950 (clobber (reg:SI LR_REGNO))]
10951 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10952 "*
10953 {
10954 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10955 output_asm_insn (\"crxor 6,6,6\", operands);
10957 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10958 output_asm_insn (\"creqv 6,6,6\", operands);
10960 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10961 }"
10962 [(set_attr "type" "branch")
10963 (set_attr "length" "4,8")])
10966 (define_insn "*call_value_local64"
10967 [(set (match_operand 0 "" "")
10968 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10969 (match_operand 2 "" "g,g")))
10970 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10971 (clobber (reg:SI LR_REGNO))]
10972 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10973 "*
10974 {
10975 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10976 output_asm_insn (\"crxor 6,6,6\", operands);
10978 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10979 output_asm_insn (\"creqv 6,6,6\", operands);
10981 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10982 }"
10983 [(set_attr "type" "branch")
10984 (set_attr "length" "4,8")])
10986 ;; Call to function which may be in another module. Restore the TOC
10987 ;; pointer (r2) after the call unless this is System V.
10988 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10989 ;; either the function was not prototyped, or it was prototyped as a
10990 ;; variable argument function. It is > 0 if FP registers were passed
10991 ;; and < 0 if they were not.
10993 (define_insn "*call_indirect_nonlocal_aix32"
10994 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10995 (match_operand 1 "" "g,g"))
10996 (use (reg:SI 2))
10997 (use (reg:SI 11))
10998 (set (reg:SI 2)
10999 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11000 (clobber (reg:SI LR_REGNO))]
11001 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11002 "b%T0l\;{l|lwz} 2,20(1)"
11003 [(set_attr "type" "jmpreg")
11004 (set_attr "length" "8")])
11006 (define_insn "*call_nonlocal_aix32"
11007 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11008 (match_operand 1 "" "g"))
11009 (use (match_operand:SI 2 "immediate_operand" "O"))
11010 (clobber (reg:SI LR_REGNO))]
11011 "TARGET_32BIT
11012 && DEFAULT_ABI == ABI_AIX
11013 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11014 "bl %z0\;%."
11015 [(set_attr "type" "branch")
11016 (set_attr "length" "8")])
11018 (define_insn "*call_indirect_nonlocal_aix64"
11019 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11020 (match_operand 1 "" "g,g"))
11021 (use (reg:DI 2))
11022 (use (reg:DI 11))
11023 (set (reg:DI 2)
11024 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11025 (clobber (reg:SI LR_REGNO))]
11026 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11027 "b%T0l\;ld 2,40(1)"
11028 [(set_attr "type" "jmpreg")
11029 (set_attr "length" "8")])
11031 (define_insn "*call_nonlocal_aix64"
11032 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11033 (match_operand 1 "" "g"))
11034 (use (match_operand:SI 2 "immediate_operand" "O"))
11035 (clobber (reg:SI LR_REGNO))]
11036 "TARGET_64BIT
11037 && DEFAULT_ABI == ABI_AIX
11038 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11039 "bl %z0\;%."
11040 [(set_attr "type" "branch")
11041 (set_attr "length" "8")])
11043 (define_insn "*call_value_indirect_nonlocal_aix32"
11044 [(set (match_operand 0 "" "")
11045 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11046 (match_operand 2 "" "g,g")))
11047 (use (reg:SI 2))
11048 (use (reg:SI 11))
11049 (set (reg:SI 2)
11050 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11051 (clobber (reg:SI LR_REGNO))]
11052 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11053 "b%T1l\;{l|lwz} 2,20(1)"
11054 [(set_attr "type" "jmpreg")
11055 (set_attr "length" "8")])
11057 (define_insn "*call_value_nonlocal_aix32"
11058 [(set (match_operand 0 "" "")
11059 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11060 (match_operand 2 "" "g")))
11061 (use (match_operand:SI 3 "immediate_operand" "O"))
11062 (clobber (reg:SI LR_REGNO))]
11063 "TARGET_32BIT
11064 && DEFAULT_ABI == ABI_AIX
11065 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11066 "bl %z1\;%."
11067 [(set_attr "type" "branch")
11068 (set_attr "length" "8")])
11070 (define_insn "*call_value_indirect_nonlocal_aix64"
11071 [(set (match_operand 0 "" "")
11072 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11073 (match_operand 2 "" "g,g")))
11074 (use (reg:DI 2))
11075 (use (reg:DI 11))
11076 (set (reg:DI 2)
11077 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11078 (clobber (reg:SI LR_REGNO))]
11079 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11080 "b%T1l\;ld 2,40(1)"
11081 [(set_attr "type" "jmpreg")
11082 (set_attr "length" "8")])
11084 (define_insn "*call_value_nonlocal_aix64"
11085 [(set (match_operand 0 "" "")
11086 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11087 (match_operand 2 "" "g")))
11088 (use (match_operand:SI 3 "immediate_operand" "O"))
11089 (clobber (reg:SI LR_REGNO))]
11090 "TARGET_64BIT
11091 && DEFAULT_ABI == ABI_AIX
11092 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11093 "bl %z1\;%."
11094 [(set_attr "type" "branch")
11095 (set_attr "length" "8")])
11097 ;; A function pointer under System V is just a normal pointer
11098 ;; operands[0] is the function pointer
11099 ;; operands[1] is the stack size to clean up
11100 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11101 ;; which indicates how to set cr1
11103 (define_insn "*call_indirect_nonlocal_sysv<mode>"
11104 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
11105 (match_operand 1 "" "g,g,g,g"))
11106 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
11107 (clobber (reg:SI LR_REGNO))]
11108 "DEFAULT_ABI == ABI_V4
11109 || DEFAULT_ABI == ABI_DARWIN"
11110 {
11111 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11112 output_asm_insn ("crxor 6,6,6", operands);
11114 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11115 output_asm_insn ("creqv 6,6,6", operands);
11117 return "b%T0l";
11118 }
11119 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11120 (set_attr "length" "4,4,8,8")])
11122 (define_insn "*call_nonlocal_sysv<mode>"
11123 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11124 (match_operand 1 "" "g,g"))
11125 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11126 (clobber (reg:SI LR_REGNO))]
11127 "(DEFAULT_ABI == ABI_DARWIN
11128 || (DEFAULT_ABI == ABI_V4
11129 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
11130 {
11131 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11132 output_asm_insn ("crxor 6,6,6", operands);
11134 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11135 output_asm_insn ("creqv 6,6,6", operands);
11137 #if TARGET_MACHO
11138 return output_call(insn, operands, 0, 2);
11139 #else
11140 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11141 {
11142 if (TARGET_SECURE_PLT && flag_pic == 2)
11143 /* The magic 32768 offset here and in the other sysv call insns
11144 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11145 See sysv4.h:toc_section. */
11146 return "bl %z0+32768@plt";
11147 else
11148 return "bl %z0@plt";
11149 }
11150 else
11151 return "bl %z0";
11152 #endif
11153 }
11154 [(set_attr "type" "branch,branch")
11155 (set_attr "length" "4,8")])
11157 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
11158 [(set (match_operand 0 "" "")
11159 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
11160 (match_operand 2 "" "g,g,g,g")))
11161 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
11162 (clobber (reg:SI LR_REGNO))]
11163 "DEFAULT_ABI == ABI_V4
11164 || DEFAULT_ABI == ABI_DARWIN"
11165 {
11166 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11167 output_asm_insn ("crxor 6,6,6", operands);
11169 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11170 output_asm_insn ("creqv 6,6,6", operands);
11172 return "b%T1l";
11173 }
11174 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11175 (set_attr "length" "4,4,8,8")])
11177 (define_insn "*call_value_nonlocal_sysv<mode>"
11178 [(set (match_operand 0 "" "")
11179 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11180 (match_operand 2 "" "g,g")))
11181 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11182 (clobber (reg:SI LR_REGNO))]
11183 "(DEFAULT_ABI == ABI_DARWIN
11184 || (DEFAULT_ABI == ABI_V4
11185 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
11186 {
11187 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11188 output_asm_insn ("crxor 6,6,6", operands);
11190 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11191 output_asm_insn ("creqv 6,6,6", operands);
11193 #if TARGET_MACHO
11194 return output_call(insn, operands, 1, 3);
11195 #else
11196 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11197 {
11198 if (TARGET_SECURE_PLT && flag_pic == 2)
11199 return "bl %z1+32768@plt";
11200 else
11201 return "bl %z1@plt";
11202 }
11203 else
11204 return "bl %z1";
11205 #endif
11206 }
11207 [(set_attr "type" "branch,branch")
11208 (set_attr "length" "4,8")])
11210 ;; Call subroutine returning any type.
11211 (define_expand "untyped_call"
11212 [(parallel [(call (match_operand 0 "" "")
11213 (const_int 0))
11214 (match_operand 1 "" "")
11215 (match_operand 2 "" "")])]
11216 ""
11217 "
11218 {
11219 int i;
11221 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11223 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11224 {
11225 rtx set = XVECEXP (operands[2], 0, i);
11226 emit_move_insn (SET_DEST (set), SET_SRC (set));
11227 }
11229 /* The optimizer does not know that the call sets the function value
11230 registers we stored in the result block. We avoid problems by
11231 claiming that all hard registers are used and clobbered at this
11232 point. */
11233 emit_insn (gen_blockage ());
11235 DONE;
11236 }")
11238 ;; sibling call patterns
11239 (define_expand "sibcall"
11240 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11241 (match_operand 1 "" ""))
11242 (use (match_operand 2 "" ""))
11243 (use (reg:SI LR_REGNO))
11244 (return)])]
11245 ""
11246 "
11247 {
11248 #if TARGET_MACHO
11249 if (MACHOPIC_INDIRECT)
11250 operands[0] = machopic_indirect_call_target (operands[0]);
11251 #endif
11253 gcc_assert (GET_CODE (operands[0]) == MEM);
11254 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11256 operands[0] = XEXP (operands[0], 0);
11257 }")
11259 ;; this and similar patterns must be marked as using LR, otherwise
11260 ;; dataflow will try to delete the store into it. This is true
11261 ;; even when the actual reg to jump to is in CTR, when LR was
11262 ;; saved and restored around the PIC-setting BCL.
11263 (define_insn "*sibcall_local32"
11264 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11265 (match_operand 1 "" "g,g"))
11266 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11267 (use (reg:SI LR_REGNO))
11268 (return)]
11269 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11270 "*
11271 {
11272 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11273 output_asm_insn (\"crxor 6,6,6\", operands);
11275 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11276 output_asm_insn (\"creqv 6,6,6\", operands);
11278 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11279 }"
11280 [(set_attr "type" "branch")
11281 (set_attr "length" "4,8")])
11283 (define_insn "*sibcall_local64"
11284 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11285 (match_operand 1 "" "g,g"))
11286 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11287 (use (reg:SI LR_REGNO))
11288 (return)]
11289 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11290 "*
11291 {
11292 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11293 output_asm_insn (\"crxor 6,6,6\", operands);
11295 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11296 output_asm_insn (\"creqv 6,6,6\", operands);
11298 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11299 }"
11300 [(set_attr "type" "branch")
11301 (set_attr "length" "4,8")])
11303 (define_insn "*sibcall_value_local32"
11304 [(set (match_operand 0 "" "")
11305 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11306 (match_operand 2 "" "g,g")))
11307 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11308 (use (reg:SI LR_REGNO))
11309 (return)]
11310 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11311 "*
11312 {
11313 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11314 output_asm_insn (\"crxor 6,6,6\", operands);
11316 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11317 output_asm_insn (\"creqv 6,6,6\", operands);
11319 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11320 }"
11321 [(set_attr "type" "branch")
11322 (set_attr "length" "4,8")])
11325 (define_insn "*sibcall_value_local64"
11326 [(set (match_operand 0 "" "")
11327 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11328 (match_operand 2 "" "g,g")))
11329 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11330 (use (reg:SI LR_REGNO))
11331 (return)]
11332 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11333 "*
11334 {
11335 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11336 output_asm_insn (\"crxor 6,6,6\", operands);
11338 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11339 output_asm_insn (\"creqv 6,6,6\", operands);
11341 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11342 }"
11343 [(set_attr "type" "branch")
11344 (set_attr "length" "4,8")])
11346 (define_insn "*sibcall_nonlocal_aix32"
11347 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11348 (match_operand 1 "" "g"))
11349 (use (match_operand:SI 2 "immediate_operand" "O"))
11350 (use (reg:SI LR_REGNO))
11351 (return)]
11352 "TARGET_32BIT
11353 && DEFAULT_ABI == ABI_AIX
11354 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11355 "b %z0"
11356 [(set_attr "type" "branch")
11357 (set_attr "length" "4")])
11359 (define_insn "*sibcall_nonlocal_aix64"
11360 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11361 (match_operand 1 "" "g"))
11362 (use (match_operand:SI 2 "immediate_operand" "O"))
11363 (use (reg:SI LR_REGNO))
11364 (return)]
11365 "TARGET_64BIT
11366 && DEFAULT_ABI == ABI_AIX
11367 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11368 "b %z0"
11369 [(set_attr "type" "branch")
11370 (set_attr "length" "4")])
11372 (define_insn "*sibcall_value_nonlocal_aix32"
11373 [(set (match_operand 0 "" "")
11374 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11375 (match_operand 2 "" "g")))
11376 (use (match_operand:SI 3 "immediate_operand" "O"))
11377 (use (reg:SI LR_REGNO))
11378 (return)]
11379 "TARGET_32BIT
11380 && DEFAULT_ABI == ABI_AIX
11381 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11382 "b %z1"
11383 [(set_attr "type" "branch")
11384 (set_attr "length" "4")])
11386 (define_insn "*sibcall_value_nonlocal_aix64"
11387 [(set (match_operand 0 "" "")
11388 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11389 (match_operand 2 "" "g")))
11390 (use (match_operand:SI 3 "immediate_operand" "O"))
11391 (use (reg:SI LR_REGNO))
11392 (return)]
11393 "TARGET_64BIT
11394 && DEFAULT_ABI == ABI_AIX
11395 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11396 "b %z1"
11397 [(set_attr "type" "branch")
11398 (set_attr "length" "4")])
11400 (define_insn "*sibcall_nonlocal_sysv<mode>"
11401 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11402 (match_operand 1 "" ""))
11403 (use (match_operand 2 "immediate_operand" "O,n"))
11404 (use (reg:SI LR_REGNO))
11405 (return)]
11406 "(DEFAULT_ABI == ABI_DARWIN
11407 || DEFAULT_ABI == ABI_V4)
11408 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11409 "*
11410 {
11411 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11412 output_asm_insn (\"crxor 6,6,6\", operands);
11414 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11415 output_asm_insn (\"creqv 6,6,6\", operands);
11417 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11418 {
11419 if (TARGET_SECURE_PLT && flag_pic == 2)
11420 return \"b %z0+32768@plt\";
11421 else
11422 return \"b %z0@plt\";
11423 }
11424 else
11425 return \"b %z0\";
11426 }"
11427 [(set_attr "type" "branch,branch")
11428 (set_attr "length" "4,8")])
11430 (define_expand "sibcall_value"
11431 [(parallel [(set (match_operand 0 "register_operand" "")
11432 (call (mem:SI (match_operand 1 "address_operand" ""))
11433 (match_operand 2 "" "")))
11434 (use (match_operand 3 "" ""))
11435 (use (reg:SI LR_REGNO))
11436 (return)])]
11437 ""
11438 "
11439 {
11440 #if TARGET_MACHO
11441 if (MACHOPIC_INDIRECT)
11442 operands[1] = machopic_indirect_call_target (operands[1]);
11443 #endif
11445 gcc_assert (GET_CODE (operands[1]) == MEM);
11446 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11448 operands[1] = XEXP (operands[1], 0);
11449 }")
11451 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11452 [(set (match_operand 0 "" "")
11453 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11454 (match_operand 2 "" "")))
11455 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11456 (use (reg:SI LR_REGNO))
11457 (return)]
11458 "(DEFAULT_ABI == ABI_DARWIN
11459 || DEFAULT_ABI == ABI_V4)
11460 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11461 "*
11462 {
11463 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11464 output_asm_insn (\"crxor 6,6,6\", operands);
11466 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11467 output_asm_insn (\"creqv 6,6,6\", operands);
11469 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11470 {
11471 if (TARGET_SECURE_PLT && flag_pic == 2)
11472 return \"b %z1+32768@plt\";
11473 else
11474 return \"b %z1@plt\";
11475 }
11476 else
11477 return \"b %z1\";
11478 }"
11479 [(set_attr "type" "branch,branch")
11480 (set_attr "length" "4,8")])
11482 (define_expand "sibcall_epilogue"
11483 [(use (const_int 0))]
11484 "TARGET_SCHED_PROLOG"
11485 "
11486 {
11487 rs6000_emit_epilogue (TRUE);
11488 DONE;
11489 }")
11491 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11492 ;; all of memory. This blocks insns from being moved across this point.
11494 (define_insn "blockage"
11495 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11496 ""
11497 "")
11498 \f
11499 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11500 ;; signed & unsigned, and one type of branch.
11501 ;;
11502 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11503 ;; insns, and branches. We store the operands of compares until we see
11504 ;; how it is used.
11505 (define_expand "cmp<mode>"
11506 [(set (cc0)
11507 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
11508 (match_operand:GPR 1 "reg_or_short_operand" "")))]
11509 ""
11510 "
11511 {
11512 /* Take care of the possibility that operands[1] might be negative but
11513 this might be a logical operation. That insn doesn't exist. */
11514 if (GET_CODE (operands[1]) == CONST_INT
11515 && INTVAL (operands[1]) < 0)
11516 operands[1] = force_reg (<MODE>mode, operands[1]);
11518 rs6000_compare_op0 = operands[0];
11519 rs6000_compare_op1 = operands[1];
11520 rs6000_compare_fp_p = 0;
11521 DONE;
11522 }")
11524 (define_expand "cmp<mode>"
11525 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
11526 (match_operand:FP 1 "gpc_reg_operand" "")))]
11527 ""
11528 "
11529 {
11530 rs6000_compare_op0 = operands[0];
11531 rs6000_compare_op1 = operands[1];
11532 rs6000_compare_fp_p = 1;
11533 DONE;
11534 }")
11536 (define_expand "beq"
11537 [(use (match_operand 0 "" ""))]
11538 ""
11539 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
11541 (define_expand "bne"
11542 [(use (match_operand 0 "" ""))]
11543 ""
11544 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11546 (define_expand "bge"
11547 [(use (match_operand 0 "" ""))]
11548 ""
11549 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11551 (define_expand "bgt"
11552 [(use (match_operand 0 "" ""))]
11553 ""
11554 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11556 (define_expand "ble"
11557 [(use (match_operand 0 "" ""))]
11558 ""
11559 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11561 (define_expand "blt"
11562 [(use (match_operand 0 "" ""))]
11563 ""
11564 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11566 (define_expand "bgeu"
11567 [(use (match_operand 0 "" ""))]
11568 ""
11569 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11571 (define_expand "bgtu"
11572 [(use (match_operand 0 "" ""))]
11573 ""
11574 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11576 (define_expand "bleu"
11577 [(use (match_operand 0 "" ""))]
11578 ""
11579 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11581 (define_expand "bltu"
11582 [(use (match_operand 0 "" ""))]
11583 ""
11584 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11586 (define_expand "bunordered"
11587 [(use (match_operand 0 "" ""))]
11588 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11589 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11591 (define_expand "bordered"
11592 [(use (match_operand 0 "" ""))]
11593 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11594 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11596 (define_expand "buneq"
11597 [(use (match_operand 0 "" ""))]
11598 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11599 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11601 (define_expand "bunge"
11602 [(use (match_operand 0 "" ""))]
11603 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11604 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11606 (define_expand "bungt"
11607 [(use (match_operand 0 "" ""))]
11608 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11609 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11611 (define_expand "bunle"
11612 [(use (match_operand 0 "" ""))]
11613 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11614 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11616 (define_expand "bunlt"
11617 [(use (match_operand 0 "" ""))]
11618 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11619 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11621 (define_expand "bltgt"
11622 [(use (match_operand 0 "" ""))]
11623 ""
11624 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11626 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11627 ;; For SEQ, likewise, except that comparisons with zero should be done
11628 ;; with an scc insns. However, due to the order that combine see the
11629 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11630 ;; the cases we don't want to handle.
11631 (define_expand "seq"
11632 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11633 ""
11634 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11636 (define_expand "sne"
11637 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11638 ""
11639 "
11640 {
11641 if (! rs6000_compare_fp_p)
11642 FAIL;
11644 rs6000_emit_sCOND (NE, operands[0]);
11645 DONE;
11646 }")
11648 ;; A >= 0 is best done the portable way for A an integer.
11649 (define_expand "sge"
11650 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11651 ""
11652 "
11653 {
11654 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11655 FAIL;
11657 rs6000_emit_sCOND (GE, operands[0]);
11658 DONE;
11659 }")
11661 ;; A > 0 is best done using the portable sequence, so fail in that case.
11662 (define_expand "sgt"
11663 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11664 ""
11665 "
11666 {
11667 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11668 FAIL;
11670 rs6000_emit_sCOND (GT, operands[0]);
11671 DONE;
11672 }")
11674 ;; A <= 0 is best done the portable way for A an integer.
11675 (define_expand "sle"
11676 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11677 ""
11678 "
11679 {
11680 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11681 FAIL;
11683 rs6000_emit_sCOND (LE, operands[0]);
11684 DONE;
11685 }")
11687 ;; A < 0 is best done in the portable way for A an integer.
11688 (define_expand "slt"
11689 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11690 ""
11691 "
11692 {
11693 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11694 FAIL;
11696 rs6000_emit_sCOND (LT, operands[0]);
11697 DONE;
11698 }")
11700 (define_expand "sgeu"
11701 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11702 ""
11703 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11705 (define_expand "sgtu"
11706 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11707 ""
11708 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11710 (define_expand "sleu"
11711 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11712 ""
11713 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11715 (define_expand "sltu"
11716 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11717 ""
11718 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11720 (define_expand "sunordered"
11721 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11722 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11723 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11725 (define_expand "sordered"
11726 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11727 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11728 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11730 (define_expand "suneq"
11731 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11732 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11733 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11735 (define_expand "sunge"
11736 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11737 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11738 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11740 (define_expand "sungt"
11741 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11742 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11743 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11745 (define_expand "sunle"
11746 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11747 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11748 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11750 (define_expand "sunlt"
11751 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11752 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11753 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11755 (define_expand "sltgt"
11756 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11757 ""
11758 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11760 (define_expand "stack_protect_set"
11761 [(match_operand 0 "memory_operand" "")
11762 (match_operand 1 "memory_operand" "")]
11763 ""
11764 {
11765 #ifdef TARGET_THREAD_SSP_OFFSET
11766 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11767 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11768 operands[1] = gen_rtx_MEM (Pmode, addr);
11769 #endif
11770 if (TARGET_64BIT)
11771 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11772 else
11773 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11774 DONE;
11775 })
11777 (define_insn "stack_protect_setsi"
11778 [(set (match_operand:SI 0 "memory_operand" "=m")
11779 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11780 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11781 "TARGET_32BIT"
11782 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
11783 [(set_attr "type" "three")
11784 (set_attr "length" "12")])
11786 (define_insn "stack_protect_setdi"
11787 [(set (match_operand:DI 0 "memory_operand" "=m")
11788 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11789 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11790 "TARGET_64BIT"
11791 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
11792 [(set_attr "type" "three")
11793 (set_attr "length" "12")])
11795 (define_expand "stack_protect_test"
11796 [(match_operand 0 "memory_operand" "")
11797 (match_operand 1 "memory_operand" "")
11798 (match_operand 2 "" "")]
11799 ""
11800 {
11801 #ifdef TARGET_THREAD_SSP_OFFSET
11802 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11803 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11804 operands[1] = gen_rtx_MEM (Pmode, addr);
11805 #endif
11806 rs6000_compare_op0 = operands[0];
11807 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
11808 UNSPEC_SP_TEST);
11809 rs6000_compare_fp_p = 0;
11810 emit_jump_insn (gen_beq (operands[2]));
11811 DONE;
11812 })
11814 (define_insn "stack_protect_testsi"
11815 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11816 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11817 (match_operand:SI 2 "memory_operand" "m,m")]
11818 UNSPEC_SP_TEST))
11819 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11820 (clobber (match_scratch:SI 3 "=&r,&r"))]
11821 "TARGET_32BIT"
11822 "@
11823 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11824 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11825 [(set_attr "length" "16,20")])
11827 (define_insn "stack_protect_testdi"
11828 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11829 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
11830 (match_operand:DI 2 "memory_operand" "m,m")]
11831 UNSPEC_SP_TEST))
11832 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11833 (clobber (match_scratch:DI 3 "=&r,&r"))]
11834 "TARGET_64BIT"
11835 "@
11836 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11837 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11838 [(set_attr "length" "16,20")])
11840 \f
11841 ;; Here are the actual compare insns.
11842 (define_insn "*cmp<mode>_internal1"
11843 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11844 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11845 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11846 ""
11847 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
11848 [(set_attr "type" "cmp")])
11850 ;; If we are comparing a register for equality with a large constant,
11851 ;; we can do this with an XOR followed by a compare. But this is profitable
11852 ;; only if the large constant is only used for the comparison (and in this
11853 ;; case we already have a register to reuse as scratch).
11854 ;;
11855 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11856 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11858 (define_peephole2
11859 [(set (match_operand:SI 0 "register_operand")
11860 (match_operand:SI 1 "logical_const_operand" ""))
11861 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11862 [(match_dup 0)
11863 (match_operand:SI 2 "logical_const_operand" "")]))
11864 (set (match_operand:CC 4 "cc_reg_operand" "")
11865 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11866 (match_dup 0)))
11867 (set (pc)
11868 (if_then_else (match_operator 6 "equality_operator"
11869 [(match_dup 4) (const_int 0)])
11870 (match_operand 7 "" "")
11871 (match_operand 8 "" "")))]
11872 "peep2_reg_dead_p (3, operands[0])
11873 && peep2_reg_dead_p (4, operands[4])"
11874 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11875 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11876 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11878 {
11879 /* Get the constant we are comparing against, and see what it looks like
11880 when sign-extended from 16 to 32 bits. Then see what constant we could
11881 XOR with SEXTC to get the sign-extended value. */
11882 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11883 SImode,
11884 operands[1], operands[2]);
11885 HOST_WIDE_INT c = INTVAL (cnst);
11886 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11887 HOST_WIDE_INT xorv = c ^ sextc;
11889 operands[9] = GEN_INT (xorv);
11890 operands[10] = GEN_INT (sextc);
11891 })
11893 (define_insn "*cmpsi_internal2"
11894 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11895 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11896 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11897 ""
11898 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11899 [(set_attr "type" "cmp")])
11901 (define_insn "*cmpdi_internal2"
11902 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11903 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11904 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11905 ""
11906 "cmpld%I2 %0,%1,%b2"
11907 [(set_attr "type" "cmp")])
11909 ;; The following two insns don't exist as single insns, but if we provide
11910 ;; them, we can swap an add and compare, which will enable us to overlap more
11911 ;; of the required delay between a compare and branch. We generate code for
11912 ;; them by splitting.
11914 (define_insn ""
11915 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11916 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11917 (match_operand:SI 2 "short_cint_operand" "i")))
11918 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11919 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11920 ""
11921 "#"
11922 [(set_attr "length" "8")])
11924 (define_insn ""
11925 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11926 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11927 (match_operand:SI 2 "u_short_cint_operand" "i")))
11928 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11929 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11930 ""
11931 "#"
11932 [(set_attr "length" "8")])
11934 (define_split
11935 [(set (match_operand:CC 3 "cc_reg_operand" "")
11936 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11937 (match_operand:SI 2 "short_cint_operand" "")))
11938 (set (match_operand:SI 0 "gpc_reg_operand" "")
11939 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11940 ""
11941 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11942 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11944 (define_split
11945 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11946 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11947 (match_operand:SI 2 "u_short_cint_operand" "")))
11948 (set (match_operand:SI 0 "gpc_reg_operand" "")
11949 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11950 ""
11951 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11952 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11954 (define_insn "*cmpsf_internal1"
11955 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11956 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11957 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11958 "TARGET_HARD_FLOAT && TARGET_FPRS"
11959 "fcmpu %0,%1,%2"
11960 [(set_attr "type" "fpcompare")])
11962 (define_insn "*cmpdf_internal1"
11963 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11964 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11965 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11966 "TARGET_HARD_FLOAT && TARGET_FPRS"
11967 "fcmpu %0,%1,%2"
11968 [(set_attr "type" "fpcompare")])
11970 ;; Only need to compare second words if first words equal
11971 (define_insn "*cmptf_internal1"
11972 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11973 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11974 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11975 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11976 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11977 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11978 [(set_attr "type" "fpcompare")
11979 (set_attr "length" "12")])
11981 (define_insn_and_split "*cmptf_internal2"
11982 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11983 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11984 (match_operand:TF 2 "gpc_reg_operand" "f")))
11985 (clobber (match_scratch:DF 3 "=f"))
11986 (clobber (match_scratch:DF 4 "=f"))
11987 (clobber (match_scratch:DF 5 "=f"))
11988 (clobber (match_scratch:DF 6 "=f"))
11989 (clobber (match_scratch:DF 7 "=f"))
11990 (clobber (match_scratch:DF 8 "=f"))
11991 (clobber (match_scratch:DF 9 "=f"))
11992 (clobber (match_scratch:DF 10 "=f"))]
11993 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11994 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11995 "#"
11996 "&& reload_completed"
11997 [(set (match_dup 3) (match_dup 13))
11998 (set (match_dup 4) (match_dup 14))
11999 (set (match_dup 9) (abs:DF (match_dup 5)))
12000 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
12001 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
12002 (label_ref (match_dup 11))
12003 (pc)))
12004 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
12005 (set (pc) (label_ref (match_dup 12)))
12006 (match_dup 11)
12007 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
12008 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
12009 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
12010 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
12011 (match_dup 12)]
12012 {
12013 REAL_VALUE_TYPE rv;
12014 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
12015 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
12017 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
12018 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
12019 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12020 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12021 operands[11] = gen_label_rtx ();
12022 operands[12] = gen_label_rtx ();
12023 real_inf (&rv);
12024 operands[13] = force_const_mem (DFmode,
12025 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12026 operands[14] = force_const_mem (DFmode,
12027 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12028 DFmode));
12029 if (TARGET_TOC)
12030 {
12031 operands[13] = gen_const_mem (DFmode,
12032 create_TOC_reference (XEXP (operands[13], 0)));
12033 operands[14] = gen_const_mem (DFmode,
12034 create_TOC_reference (XEXP (operands[14], 0)));
12035 set_mem_alias_set (operands[13], get_TOC_alias_set ());
12036 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12037 }
12038 })
12039 \f
12040 ;; Now we have the scc insns. We can do some combinations because of the
12041 ;; way the machine works.
12042 ;;
12043 ;; Note that this is probably faster if we can put an insn between the
12044 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12045 ;; cases the insns below which don't use an intermediate CR field will
12046 ;; be used instead.
12047 (define_insn ""
12048 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12049 (match_operator:SI 1 "scc_comparison_operator"
12050 [(match_operand 2 "cc_reg_operand" "y")
12051 (const_int 0)]))]
12052 ""
12053 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12054 [(set (attr "type")
12055 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12056 (const_string "mfcrf")
12057 ]
12058 (const_string "mfcr")))
12059 (set_attr "length" "8")])
12061 ;; Same as above, but get the GT bit.
12062 (define_insn "move_from_CR_gt_bit"
12063 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12064 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12065 "TARGET_E500"
12066 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
12067 [(set_attr "type" "mfcr")
12068 (set_attr "length" "8")])
12070 ;; Same as above, but get the OV/ORDERED bit.
12071 (define_insn "move_from_CR_ov_bit"
12072 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12073 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
12074 "TARGET_ISEL"
12075 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
12076 [(set_attr "type" "mfcr")
12077 (set_attr "length" "8")])
12079 (define_insn ""
12080 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12081 (match_operator:DI 1 "scc_comparison_operator"
12082 [(match_operand 2 "cc_reg_operand" "y")
12083 (const_int 0)]))]
12084 "TARGET_POWERPC64"
12085 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12086 [(set (attr "type")
12087 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12088 (const_string "mfcrf")
12089 ]
12090 (const_string "mfcr")))
12091 (set_attr "length" "8")])
12093 (define_insn ""
12094 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12095 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12096 [(match_operand 2 "cc_reg_operand" "y,y")
12097 (const_int 0)])
12098 (const_int 0)))
12099 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12100 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12101 "TARGET_32BIT"
12102 "@
12103 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
12104 #"
12105 [(set_attr "type" "delayed_compare")
12106 (set_attr "length" "8,16")])
12108 (define_split
12109 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12110 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12111 [(match_operand 2 "cc_reg_operand" "")
12112 (const_int 0)])
12113 (const_int 0)))
12114 (set (match_operand:SI 3 "gpc_reg_operand" "")
12115 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12116 "TARGET_32BIT && reload_completed"
12117 [(set (match_dup 3)
12118 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12119 (set (match_dup 0)
12120 (compare:CC (match_dup 3)
12121 (const_int 0)))]
12122 "")
12124 (define_insn ""
12125 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12126 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12127 [(match_operand 2 "cc_reg_operand" "y")
12128 (const_int 0)])
12129 (match_operand:SI 3 "const_int_operand" "n")))]
12130 ""
12131 "*
12132 {
12133 int is_bit = ccr_bit (operands[1], 1);
12134 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12135 int count;
12137 if (is_bit >= put_bit)
12138 count = is_bit - put_bit;
12139 else
12140 count = 32 - (put_bit - is_bit);
12142 operands[4] = GEN_INT (count);
12143 operands[5] = GEN_INT (put_bit);
12145 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
12146 }"
12147 [(set (attr "type")
12148 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12149 (const_string "mfcrf")
12150 ]
12151 (const_string "mfcr")))
12152 (set_attr "length" "8")])
12154 (define_insn ""
12155 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12156 (compare:CC
12157 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12158 [(match_operand 2 "cc_reg_operand" "y,y")
12159 (const_int 0)])
12160 (match_operand:SI 3 "const_int_operand" "n,n"))
12161 (const_int 0)))
12162 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
12163 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12164 (match_dup 3)))]
12165 ""
12166 "*
12167 {
12168 int is_bit = ccr_bit (operands[1], 1);
12169 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12170 int count;
12172 /* Force split for non-cc0 compare. */
12173 if (which_alternative == 1)
12174 return \"#\";
12176 if (is_bit >= put_bit)
12177 count = is_bit - put_bit;
12178 else
12179 count = 32 - (put_bit - is_bit);
12181 operands[5] = GEN_INT (count);
12182 operands[6] = GEN_INT (put_bit);
12184 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
12185 }"
12186 [(set_attr "type" "delayed_compare")
12187 (set_attr "length" "8,16")])
12189 (define_split
12190 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12191 (compare:CC
12192 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12193 [(match_operand 2 "cc_reg_operand" "")
12194 (const_int 0)])
12195 (match_operand:SI 3 "const_int_operand" ""))
12196 (const_int 0)))
12197 (set (match_operand:SI 4 "gpc_reg_operand" "")
12198 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12199 (match_dup 3)))]
12200 "reload_completed"
12201 [(set (match_dup 4)
12202 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12203 (match_dup 3)))
12204 (set (match_dup 0)
12205 (compare:CC (match_dup 4)
12206 (const_int 0)))]
12207 "")
12209 ;; There is a 3 cycle delay between consecutive mfcr instructions
12210 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12212 (define_peephole
12213 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12214 (match_operator:SI 1 "scc_comparison_operator"
12215 [(match_operand 2 "cc_reg_operand" "y")
12216 (const_int 0)]))
12217 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12218 (match_operator:SI 4 "scc_comparison_operator"
12219 [(match_operand 5 "cc_reg_operand" "y")
12220 (const_int 0)]))]
12221 "REGNO (operands[2]) != REGNO (operands[5])"
12222 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12223 [(set_attr "type" "mfcr")
12224 (set_attr "length" "12")])
12226 (define_peephole
12227 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12228 (match_operator:DI 1 "scc_comparison_operator"
12229 [(match_operand 2 "cc_reg_operand" "y")
12230 (const_int 0)]))
12231 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12232 (match_operator:DI 4 "scc_comparison_operator"
12233 [(match_operand 5 "cc_reg_operand" "y")
12234 (const_int 0)]))]
12235 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12236 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12237 [(set_attr "type" "mfcr")
12238 (set_attr "length" "12")])
12240 ;; There are some scc insns that can be done directly, without a compare.
12241 ;; These are faster because they don't involve the communications between
12242 ;; the FXU and branch units. In fact, we will be replacing all of the
12243 ;; integer scc insns here or in the portable methods in emit_store_flag.
12244 ;;
12245 ;; Also support (neg (scc ..)) since that construct is used to replace
12246 ;; branches, (plus (scc ..) ..) since that construct is common and
12247 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12248 ;; cases where it is no more expensive than (neg (scc ..)).
12250 ;; Have reload force a constant into a register for the simple insns that
12251 ;; otherwise won't accept constants. We do this because it is faster than
12252 ;; the cmp/mfcr sequence we would otherwise generate.
12254 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12255 (DI "rKJI")])
12257 (define_insn_and_split "*eq<mode>"
12258 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12259 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12260 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12261 "!TARGET_POWER"
12262 "#"
12263 "!TARGET_POWER"
12264 [(set (match_dup 0)
12265 (clz:GPR (match_dup 3)))
12266 (set (match_dup 0)
12267 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12268 {
12269 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12270 {
12271 /* Use output operand as intermediate. */
12272 operands[3] = operands[0];
12274 if (logical_operand (operands[2], <MODE>mode))
12275 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12276 gen_rtx_XOR (<MODE>mode,
12277 operands[1], operands[2])));
12278 else
12279 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12280 gen_rtx_PLUS (<MODE>mode, operands[1],
12281 negate_rtx (<MODE>mode,
12282 operands[2]))));
12283 }
12284 else
12285 operands[3] = operands[1];
12287 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12288 })
12290 (define_insn_and_split "*eq<mode>_compare"
12291 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12292 (compare:CC
12293 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12294 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12295 (const_int 0)))
12296 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12297 (eq:P (match_dup 1) (match_dup 2)))]
12298 "!TARGET_POWER && optimize_size"
12299 "#"
12300 "!TARGET_POWER && optimize_size"
12301 [(set (match_dup 0)
12302 (clz:P (match_dup 4)))
12303 (parallel [(set (match_dup 3)
12304 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12305 (const_int 0)))
12306 (set (match_dup 0)
12307 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12308 {
12309 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12310 {
12311 /* Use output operand as intermediate. */
12312 operands[4] = operands[0];
12314 if (logical_operand (operands[2], <MODE>mode))
12315 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12316 gen_rtx_XOR (<MODE>mode,
12317 operands[1], operands[2])));
12318 else
12319 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12320 gen_rtx_PLUS (<MODE>mode, operands[1],
12321 negate_rtx (<MODE>mode,
12322 operands[2]))));
12323 }
12324 else
12325 operands[4] = operands[1];
12327 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12328 })
12330 (define_insn "*eqsi_power"
12331 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
12332 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12333 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
12334 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
12335 "TARGET_POWER"
12336 "@
12337 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12338 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
12339 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12340 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12341 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
12342 [(set_attr "type" "three,two,three,three,three")
12343 (set_attr "length" "12,8,12,12,12")])
12345 ;; We have insns of the form shown by the first define_insn below. If
12346 ;; there is something inside the comparison operation, we must split it.
12347 (define_split
12348 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12349 (plus:SI (match_operator 1 "comparison_operator"
12350 [(match_operand:SI 2 "" "")
12351 (match_operand:SI 3
12352 "reg_or_cint_operand" "")])
12353 (match_operand:SI 4 "gpc_reg_operand" "")))
12354 (clobber (match_operand:SI 5 "register_operand" ""))]
12355 "! gpc_reg_operand (operands[2], SImode)"
12356 [(set (match_dup 5) (match_dup 2))
12357 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
12358 (match_dup 4)))])
12360 (define_insn "*plus_eqsi"
12361 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
12362 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12363 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
12364 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
12365 "TARGET_32BIT"
12366 "@
12367 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12368 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
12369 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12370 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12371 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12372 [(set_attr "type" "three,two,three,three,three")
12373 (set_attr "length" "12,8,12,12,12")])
12375 (define_insn "*compare_plus_eqsi"
12376 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12377 (compare:CC
12378 (plus:SI
12379 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12380 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12381 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12382 (const_int 0)))
12383 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12384 "TARGET_32BIT && optimize_size"
12385 "@
12386 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12387 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
12388 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12389 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12390 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12391 #
12392 #
12393 #
12394 #
12395 #"
12396 [(set_attr "type" "compare")
12397 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12399 (define_split
12400 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12401 (compare:CC
12402 (plus:SI
12403 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12404 (match_operand:SI 2 "scc_eq_operand" ""))
12405 (match_operand:SI 3 "gpc_reg_operand" ""))
12406 (const_int 0)))
12407 (clobber (match_scratch:SI 4 ""))]
12408 "TARGET_32BIT && optimize_size && reload_completed"
12409 [(set (match_dup 4)
12410 (plus:SI (eq:SI (match_dup 1)
12411 (match_dup 2))
12412 (match_dup 3)))
12413 (set (match_dup 0)
12414 (compare:CC (match_dup 4)
12415 (const_int 0)))]
12416 "")
12418 (define_insn "*plus_eqsi_compare"
12419 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12420 (compare:CC
12421 (plus:SI
12422 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12423 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12424 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12425 (const_int 0)))
12426 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12427 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12428 "TARGET_32BIT && optimize_size"
12429 "@
12430 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12431 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12432 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12433 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12434 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12435 #
12436 #
12437 #
12438 #
12439 #"
12440 [(set_attr "type" "compare")
12441 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12443 (define_split
12444 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12445 (compare:CC
12446 (plus:SI
12447 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12448 (match_operand:SI 2 "scc_eq_operand" ""))
12449 (match_operand:SI 3 "gpc_reg_operand" ""))
12450 (const_int 0)))
12451 (set (match_operand:SI 0 "gpc_reg_operand" "")
12452 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12453 "TARGET_32BIT && optimize_size && reload_completed"
12454 [(set (match_dup 0)
12455 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12456 (set (match_dup 4)
12457 (compare:CC (match_dup 0)
12458 (const_int 0)))]
12459 "")
12461 (define_insn "*neg_eq0<mode>"
12462 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12463 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12464 (const_int 0))))]
12465 ""
12466 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12467 [(set_attr "type" "two")
12468 (set_attr "length" "8")])
12470 (define_insn_and_split "*neg_eq<mode>"
12471 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12472 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12473 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12474 ""
12475 "#"
12476 ""
12477 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12478 {
12479 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12480 {
12481 /* Use output operand as intermediate. */
12482 operands[3] = operands[0];
12484 if (logical_operand (operands[2], <MODE>mode))
12485 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12486 gen_rtx_XOR (<MODE>mode,
12487 operands[1], operands[2])));
12488 else
12489 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12490 gen_rtx_PLUS (<MODE>mode, operands[1],
12491 negate_rtx (<MODE>mode,
12492 operands[2]))));
12493 }
12494 else
12495 operands[3] = operands[1];
12496 })
12498 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12499 ;; since it nabs/sr is just as fast.
12500 (define_insn "*ne0si"
12501 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12502 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12503 (const_int 31)))
12504 (clobber (match_scratch:SI 2 "=&r"))]
12505 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
12506 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
12507 [(set_attr "type" "two")
12508 (set_attr "length" "8")])
12510 (define_insn "*ne0di"
12511 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12512 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12513 (const_int 63)))
12514 (clobber (match_scratch:DI 2 "=&r"))]
12515 "TARGET_64BIT"
12516 "addic %2,%1,-1\;subfe %0,%2,%1"
12517 [(set_attr "type" "two")
12518 (set_attr "length" "8")])
12520 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
12521 (define_insn "*plus_ne0si"
12522 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12523 (plus:SI (lshiftrt:SI
12524 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12525 (const_int 31))
12526 (match_operand:SI 2 "gpc_reg_operand" "r")))
12527 (clobber (match_scratch:SI 3 "=&r"))]
12528 "TARGET_32BIT"
12529 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
12530 [(set_attr "type" "two")
12531 (set_attr "length" "8")])
12533 (define_insn "*plus_ne0di"
12534 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12535 (plus:DI (lshiftrt:DI
12536 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12537 (const_int 63))
12538 (match_operand:DI 2 "gpc_reg_operand" "r")))
12539 (clobber (match_scratch:DI 3 "=&r"))]
12540 "TARGET_64BIT"
12541 "addic %3,%1,-1\;addze %0,%2"
12542 [(set_attr "type" "two")
12543 (set_attr "length" "8")])
12545 (define_insn "*compare_plus_ne0si"
12546 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12547 (compare:CC
12548 (plus:SI (lshiftrt:SI
12549 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12550 (const_int 31))
12551 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12552 (const_int 0)))
12553 (clobber (match_scratch:SI 3 "=&r,&r"))
12554 (clobber (match_scratch:SI 4 "=X,&r"))]
12555 "TARGET_32BIT"
12556 "@
12557 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12558 #"
12559 [(set_attr "type" "compare")
12560 (set_attr "length" "8,12")])
12562 (define_split
12563 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12564 (compare:CC
12565 (plus:SI (lshiftrt:SI
12566 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12567 (const_int 31))
12568 (match_operand:SI 2 "gpc_reg_operand" ""))
12569 (const_int 0)))
12570 (clobber (match_scratch:SI 3 ""))
12571 (clobber (match_scratch:SI 4 ""))]
12572 "TARGET_32BIT && reload_completed"
12573 [(parallel [(set (match_dup 3)
12574 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12575 (const_int 31))
12576 (match_dup 2)))
12577 (clobber (match_dup 4))])
12578 (set (match_dup 0)
12579 (compare:CC (match_dup 3)
12580 (const_int 0)))]
12581 "")
12583 (define_insn "*compare_plus_ne0di"
12584 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12585 (compare:CC
12586 (plus:DI (lshiftrt:DI
12587 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12588 (const_int 63))
12589 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12590 (const_int 0)))
12591 (clobber (match_scratch:DI 3 "=&r,&r"))]
12592 "TARGET_64BIT"
12593 "@
12594 addic %3,%1,-1\;addze. %3,%2
12595 #"
12596 [(set_attr "type" "compare")
12597 (set_attr "length" "8,12")])
12599 (define_split
12600 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12601 (compare:CC
12602 (plus:DI (lshiftrt:DI
12603 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12604 (const_int 63))
12605 (match_operand:DI 2 "gpc_reg_operand" ""))
12606 (const_int 0)))
12607 (clobber (match_scratch:DI 3 ""))]
12608 "TARGET_64BIT && reload_completed"
12609 [(set (match_dup 3)
12610 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12611 (const_int 63))
12612 (match_dup 2)))
12613 (set (match_dup 0)
12614 (compare:CC (match_dup 3)
12615 (const_int 0)))]
12616 "")
12618 (define_insn "*plus_ne0si_compare"
12619 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12620 (compare:CC
12621 (plus:SI (lshiftrt:SI
12622 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12623 (const_int 31))
12624 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12625 (const_int 0)))
12626 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12627 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12628 (match_dup 2)))
12629 (clobber (match_scratch:SI 3 "=&r,&r"))]
12630 "TARGET_32BIT"
12631 "@
12632 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12633 #"
12634 [(set_attr "type" "compare")
12635 (set_attr "length" "8,12")])
12637 (define_split
12638 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12639 (compare:CC
12640 (plus:SI (lshiftrt:SI
12641 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12642 (const_int 31))
12643 (match_operand:SI 2 "gpc_reg_operand" ""))
12644 (const_int 0)))
12645 (set (match_operand:SI 0 "gpc_reg_operand" "")
12646 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12647 (match_dup 2)))
12648 (clobber (match_scratch:SI 3 ""))]
12649 "TARGET_32BIT && reload_completed"
12650 [(parallel [(set (match_dup 0)
12651 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12652 (match_dup 2)))
12653 (clobber (match_dup 3))])
12654 (set (match_dup 4)
12655 (compare:CC (match_dup 0)
12656 (const_int 0)))]
12657 "")
12659 (define_insn "*plus_ne0di_compare"
12660 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12661 (compare:CC
12662 (plus:DI (lshiftrt:DI
12663 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12664 (const_int 63))
12665 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12666 (const_int 0)))
12667 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12668 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12669 (match_dup 2)))
12670 (clobber (match_scratch:DI 3 "=&r,&r"))]
12671 "TARGET_64BIT"
12672 "@
12673 addic %3,%1,-1\;addze. %0,%2
12674 #"
12675 [(set_attr "type" "compare")
12676 (set_attr "length" "8,12")])
12678 (define_split
12679 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12680 (compare:CC
12681 (plus:DI (lshiftrt:DI
12682 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12683 (const_int 63))
12684 (match_operand:DI 2 "gpc_reg_operand" ""))
12685 (const_int 0)))
12686 (set (match_operand:DI 0 "gpc_reg_operand" "")
12687 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12688 (match_dup 2)))
12689 (clobber (match_scratch:DI 3 ""))]
12690 "TARGET_64BIT && reload_completed"
12691 [(parallel [(set (match_dup 0)
12692 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12693 (match_dup 2)))
12694 (clobber (match_dup 3))])
12695 (set (match_dup 4)
12696 (compare:CC (match_dup 0)
12697 (const_int 0)))]
12698 "")
12700 (define_insn ""
12701 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12702 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12703 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12704 (clobber (match_scratch:SI 3 "=r,X"))]
12705 "TARGET_POWER"
12706 "@
12707 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
12708 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
12709 [(set_attr "length" "12")])
12711 (define_insn ""
12712 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12713 (compare:CC
12714 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12715 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12716 (const_int 0)))
12717 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12718 (le:SI (match_dup 1) (match_dup 2)))
12719 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
12720 "TARGET_POWER"
12721 "@
12722 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12723 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12724 #
12725 #"
12726 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12727 (set_attr "length" "12,12,16,16")])
12729 (define_split
12730 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12731 (compare:CC
12732 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12733 (match_operand:SI 2 "reg_or_short_operand" ""))
12734 (const_int 0)))
12735 (set (match_operand:SI 0 "gpc_reg_operand" "")
12736 (le:SI (match_dup 1) (match_dup 2)))
12737 (clobber (match_scratch:SI 3 ""))]
12738 "TARGET_POWER && reload_completed"
12739 [(parallel [(set (match_dup 0)
12740 (le:SI (match_dup 1) (match_dup 2)))
12741 (clobber (match_dup 3))])
12742 (set (match_dup 4)
12743 (compare:CC (match_dup 0)
12744 (const_int 0)))]
12745 "")
12747 (define_insn ""
12748 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12749 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12750 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12751 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12752 "TARGET_POWER"
12753 "@
12754 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12755 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12756 [(set_attr "length" "12")])
12758 (define_insn ""
12759 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12760 (compare:CC
12761 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12762 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12763 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12764 (const_int 0)))
12765 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12766 "TARGET_POWER"
12767 "@
12768 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12769 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12770 #
12771 #"
12772 [(set_attr "type" "compare")
12773 (set_attr "length" "12,12,16,16")])
12775 (define_split
12776 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12777 (compare:CC
12778 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12779 (match_operand:SI 2 "reg_or_short_operand" ""))
12780 (match_operand:SI 3 "gpc_reg_operand" ""))
12781 (const_int 0)))
12782 (clobber (match_scratch:SI 4 ""))]
12783 "TARGET_POWER && reload_completed"
12784 [(set (match_dup 4)
12785 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12786 (match_dup 3)))
12787 (set (match_dup 0)
12788 (compare:CC (match_dup 4)
12789 (const_int 0)))]
12790 "")
12792 (define_insn ""
12793 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12794 (compare:CC
12795 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12796 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12797 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12798 (const_int 0)))
12799 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12800 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12801 "TARGET_POWER"
12802 "@
12803 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12804 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12805 #
12806 #"
12807 [(set_attr "type" "compare")
12808 (set_attr "length" "12,12,16,16")])
12810 (define_split
12811 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12812 (compare:CC
12813 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12814 (match_operand:SI 2 "reg_or_short_operand" ""))
12815 (match_operand:SI 3 "gpc_reg_operand" ""))
12816 (const_int 0)))
12817 (set (match_operand:SI 0 "gpc_reg_operand" "")
12818 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12819 "TARGET_POWER && reload_completed"
12820 [(set (match_dup 0)
12821 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12822 (set (match_dup 4)
12823 (compare:CC (match_dup 0)
12824 (const_int 0)))]
12825 "")
12827 (define_insn ""
12828 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12829 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12830 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12831 "TARGET_POWER"
12832 "@
12833 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12834 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12835 [(set_attr "length" "12")])
12837 (define_insn "*leu<mode>"
12838 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12839 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12840 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12841 ""
12842 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12843 [(set_attr "type" "three")
12844 (set_attr "length" "12")])
12846 (define_insn "*leu<mode>_compare"
12847 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12848 (compare:CC
12849 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12850 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12851 (const_int 0)))
12852 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12853 (leu:P (match_dup 1) (match_dup 2)))]
12854 ""
12855 "@
12856 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12857 #"
12858 [(set_attr "type" "compare")
12859 (set_attr "length" "12,16")])
12861 (define_split
12862 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12863 (compare:CC
12864 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12865 (match_operand:P 2 "reg_or_short_operand" ""))
12866 (const_int 0)))
12867 (set (match_operand:P 0 "gpc_reg_operand" "")
12868 (leu:P (match_dup 1) (match_dup 2)))]
12869 "reload_completed"
12870 [(set (match_dup 0)
12871 (leu:P (match_dup 1) (match_dup 2)))
12872 (set (match_dup 3)
12873 (compare:CC (match_dup 0)
12874 (const_int 0)))]
12875 "")
12877 (define_insn "*plus_leu<mode>"
12878 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12879 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12880 (match_operand:P 2 "reg_or_short_operand" "rI"))
12881 (match_operand:P 3 "gpc_reg_operand" "r")))]
12882 ""
12883 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12884 [(set_attr "type" "two")
12885 (set_attr "length" "8")])
12887 (define_insn ""
12888 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12889 (compare:CC
12890 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12891 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12892 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12893 (const_int 0)))
12894 (clobber (match_scratch:SI 4 "=&r,&r"))]
12895 "TARGET_32BIT"
12896 "@
12897 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12898 #"
12899 [(set_attr "type" "compare")
12900 (set_attr "length" "8,12")])
12902 (define_split
12903 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12904 (compare:CC
12905 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12906 (match_operand:SI 2 "reg_or_short_operand" ""))
12907 (match_operand:SI 3 "gpc_reg_operand" ""))
12908 (const_int 0)))
12909 (clobber (match_scratch:SI 4 ""))]
12910 "TARGET_32BIT && reload_completed"
12911 [(set (match_dup 4)
12912 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12913 (match_dup 3)))
12914 (set (match_dup 0)
12915 (compare:CC (match_dup 4)
12916 (const_int 0)))]
12917 "")
12919 (define_insn ""
12920 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12921 (compare:CC
12922 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12923 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12924 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12925 (const_int 0)))
12926 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12927 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12928 "TARGET_32BIT"
12929 "@
12930 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12931 #"
12932 [(set_attr "type" "compare")
12933 (set_attr "length" "8,12")])
12935 (define_split
12936 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12937 (compare:CC
12938 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12939 (match_operand:SI 2 "reg_or_short_operand" ""))
12940 (match_operand:SI 3 "gpc_reg_operand" ""))
12941 (const_int 0)))
12942 (set (match_operand:SI 0 "gpc_reg_operand" "")
12943 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12944 "TARGET_32BIT && reload_completed"
12945 [(set (match_dup 0)
12946 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12947 (set (match_dup 4)
12948 (compare:CC (match_dup 0)
12949 (const_int 0)))]
12950 "")
12952 (define_insn "*neg_leu<mode>"
12953 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12954 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12955 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12956 ""
12957 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12958 [(set_attr "type" "three")
12959 (set_attr "length" "12")])
12961 (define_insn "*and_neg_leu<mode>"
12962 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12963 (and:P (neg:P
12964 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12965 (match_operand:P 2 "reg_or_short_operand" "rI")))
12966 (match_operand:P 3 "gpc_reg_operand" "r")))]
12967 ""
12968 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12969 [(set_attr "type" "three")
12970 (set_attr "length" "12")])
12972 (define_insn ""
12973 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12974 (compare:CC
12975 (and:SI (neg:SI
12976 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12977 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12978 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12979 (const_int 0)))
12980 (clobber (match_scratch:SI 4 "=&r,&r"))]
12981 "TARGET_32BIT"
12982 "@
12983 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12984 #"
12985 [(set_attr "type" "compare")
12986 (set_attr "length" "12,16")])
12988 (define_split
12989 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12990 (compare:CC
12991 (and:SI (neg:SI
12992 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12993 (match_operand:SI 2 "reg_or_short_operand" "")))
12994 (match_operand:SI 3 "gpc_reg_operand" ""))
12995 (const_int 0)))
12996 (clobber (match_scratch:SI 4 ""))]
12997 "TARGET_32BIT && reload_completed"
12998 [(set (match_dup 4)
12999 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13000 (match_dup 3)))
13001 (set (match_dup 0)
13002 (compare:CC (match_dup 4)
13003 (const_int 0)))]
13004 "")
13006 (define_insn ""
13007 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13008 (compare:CC
13009 (and:SI (neg:SI
13010 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13011 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13012 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13013 (const_int 0)))
13014 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13015 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13016 "TARGET_32BIT"
13017 "@
13018 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13019 #"
13020 [(set_attr "type" "compare")
13021 (set_attr "length" "12,16")])
13023 (define_split
13024 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13025 (compare:CC
13026 (and:SI (neg:SI
13027 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13028 (match_operand:SI 2 "reg_or_short_operand" "")))
13029 (match_operand:SI 3 "gpc_reg_operand" ""))
13030 (const_int 0)))
13031 (set (match_operand:SI 0 "gpc_reg_operand" "")
13032 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13033 "TARGET_32BIT && reload_completed"
13034 [(set (match_dup 0)
13035 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13036 (match_dup 3)))
13037 (set (match_dup 4)
13038 (compare:CC (match_dup 0)
13039 (const_int 0)))]
13040 "")
13042 (define_insn ""
13043 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13044 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13045 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13046 "TARGET_POWER"
13047 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13048 [(set_attr "length" "12")])
13050 (define_insn ""
13051 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13052 (compare:CC
13053 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13054 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13055 (const_int 0)))
13056 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13057 (lt:SI (match_dup 1) (match_dup 2)))]
13058 "TARGET_POWER"
13059 "@
13060 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13061 #"
13062 [(set_attr "type" "delayed_compare")
13063 (set_attr "length" "12,16")])
13065 (define_split
13066 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13067 (compare:CC
13068 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13069 (match_operand:SI 2 "reg_or_short_operand" ""))
13070 (const_int 0)))
13071 (set (match_operand:SI 0 "gpc_reg_operand" "")
13072 (lt:SI (match_dup 1) (match_dup 2)))]
13073 "TARGET_POWER && reload_completed"
13074 [(set (match_dup 0)
13075 (lt:SI (match_dup 1) (match_dup 2)))
13076 (set (match_dup 3)
13077 (compare:CC (match_dup 0)
13078 (const_int 0)))]
13079 "")
13081 (define_insn ""
13082 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13083 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13084 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13085 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13086 "TARGET_POWER"
13087 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13088 [(set_attr "length" "12")])
13090 (define_insn ""
13091 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13092 (compare:CC
13093 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13094 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13095 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13096 (const_int 0)))
13097 (clobber (match_scratch:SI 4 "=&r,&r"))]
13098 "TARGET_POWER"
13099 "@
13100 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13101 #"
13102 [(set_attr "type" "compare")
13103 (set_attr "length" "12,16")])
13105 (define_split
13106 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13107 (compare:CC
13108 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13109 (match_operand:SI 2 "reg_or_short_operand" ""))
13110 (match_operand:SI 3 "gpc_reg_operand" ""))
13111 (const_int 0)))
13112 (clobber (match_scratch:SI 4 ""))]
13113 "TARGET_POWER && reload_completed"
13114 [(set (match_dup 4)
13115 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
13116 (match_dup 3)))
13117 (set (match_dup 0)
13118 (compare:CC (match_dup 4)
13119 (const_int 0)))]
13120 "")
13122 (define_insn ""
13123 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13124 (compare:CC
13125 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13126 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13127 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13128 (const_int 0)))
13129 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13130 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13131 "TARGET_POWER"
13132 "@
13133 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13134 #"
13135 [(set_attr "type" "compare")
13136 (set_attr "length" "12,16")])
13138 (define_split
13139 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13140 (compare:CC
13141 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13142 (match_operand:SI 2 "reg_or_short_operand" ""))
13143 (match_operand:SI 3 "gpc_reg_operand" ""))
13144 (const_int 0)))
13145 (set (match_operand:SI 0 "gpc_reg_operand" "")
13146 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13147 "TARGET_POWER && reload_completed"
13148 [(set (match_dup 0)
13149 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13150 (set (match_dup 4)
13151 (compare:CC (match_dup 0)
13152 (const_int 0)))]
13153 "")
13155 (define_insn ""
13156 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13157 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13158 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13159 "TARGET_POWER"
13160 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13161 [(set_attr "length" "12")])
13163 (define_insn_and_split "*ltu<mode>"
13164 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13165 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13166 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13167 ""
13168 "#"
13169 ""
13170 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13171 (set (match_dup 0) (neg:P (match_dup 0)))]
13172 "")
13174 (define_insn_and_split "*ltu<mode>_compare"
13175 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13176 (compare:CC
13177 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13178 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13179 (const_int 0)))
13180 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13181 (ltu:P (match_dup 1) (match_dup 2)))]
13182 ""
13183 "#"
13184 ""
13185 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13186 (parallel [(set (match_dup 3)
13187 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13188 (set (match_dup 0) (neg:P (match_dup 0)))])]
13189 "")
13191 (define_insn_and_split "*plus_ltu<mode>"
13192 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13193 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13194 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13195 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
13196 ""
13197 "#"
13198 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13199 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13200 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13201 "")
13203 (define_insn_and_split "*plus_ltu<mode>_compare"
13204 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13205 (compare:CC
13206 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13207 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13208 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13209 (const_int 0)))
13210 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13211 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13212 ""
13213 "#"
13214 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13215 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13216 (parallel [(set (match_dup 4)
13217 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13218 (const_int 0)))
13219 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13220 "")
13222 (define_insn "*neg_ltu<mode>"
13223 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13224 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13225 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13226 ""
13227 "@
13228 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
13229 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
13230 [(set_attr "type" "two")
13231 (set_attr "length" "8")])
13233 (define_insn ""
13234 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13235 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13236 (match_operand:SI 2 "reg_or_short_operand" "rI")))
13237 (clobber (match_scratch:SI 3 "=r"))]
13238 "TARGET_POWER"
13239 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
13240 [(set_attr "length" "12")])
13242 (define_insn ""
13243 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13244 (compare:CC
13245 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13246 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13247 (const_int 0)))
13248 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13249 (ge:SI (match_dup 1) (match_dup 2)))
13250 (clobber (match_scratch:SI 3 "=r,r"))]
13251 "TARGET_POWER"
13252 "@
13253 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13254 #"
13255 [(set_attr "type" "compare")
13256 (set_attr "length" "12,16")])
13258 (define_split
13259 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13260 (compare:CC
13261 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13262 (match_operand:SI 2 "reg_or_short_operand" ""))
13263 (const_int 0)))
13264 (set (match_operand:SI 0 "gpc_reg_operand" "")
13265 (ge:SI (match_dup 1) (match_dup 2)))
13266 (clobber (match_scratch:SI 3 ""))]
13267 "TARGET_POWER && reload_completed"
13268 [(parallel [(set (match_dup 0)
13269 (ge:SI (match_dup 1) (match_dup 2)))
13270 (clobber (match_dup 3))])
13271 (set (match_dup 4)
13272 (compare:CC (match_dup 0)
13273 (const_int 0)))]
13274 "")
13276 (define_insn ""
13277 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13278 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13279 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13280 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13281 "TARGET_POWER"
13282 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13283 [(set_attr "length" "12")])
13285 (define_insn ""
13286 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13287 (compare:CC
13288 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13289 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13290 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13291 (const_int 0)))
13292 (clobber (match_scratch:SI 4 "=&r,&r"))]
13293 "TARGET_POWER"
13294 "@
13295 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13296 #"
13297 [(set_attr "type" "compare")
13298 (set_attr "length" "12,16")])
13300 (define_split
13301 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13302 (compare:CC
13303 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13304 (match_operand:SI 2 "reg_or_short_operand" ""))
13305 (match_operand:SI 3 "gpc_reg_operand" ""))
13306 (const_int 0)))
13307 (clobber (match_scratch:SI 4 ""))]
13308 "TARGET_POWER && reload_completed"
13309 [(set (match_dup 4)
13310 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
13311 (match_dup 3)))
13312 (set (match_dup 0)
13313 (compare:CC (match_dup 4)
13314 (const_int 0)))]
13315 "")
13317 (define_insn ""
13318 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13319 (compare:CC
13320 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13321 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13322 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13323 (const_int 0)))
13324 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13325 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13326 "TARGET_POWER"
13327 "@
13328 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13329 #"
13330 [(set_attr "type" "compare")
13331 (set_attr "length" "12,16")])
13333 (define_split
13334 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13335 (compare:CC
13336 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13337 (match_operand:SI 2 "reg_or_short_operand" ""))
13338 (match_operand:SI 3 "gpc_reg_operand" ""))
13339 (const_int 0)))
13340 (set (match_operand:SI 0 "gpc_reg_operand" "")
13341 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13342 "TARGET_POWER && reload_completed"
13343 [(set (match_dup 0)
13344 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13345 (set (match_dup 4)
13346 (compare:CC (match_dup 0)
13347 (const_int 0)))]
13348 "")
13350 (define_insn ""
13351 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13352 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13353 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13354 "TARGET_POWER"
13355 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
13356 [(set_attr "length" "12")])
13358 (define_insn "*geu<mode>"
13359 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13360 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13361 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13362 ""
13363 "@
13364 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
13365 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13366 [(set_attr "type" "three")
13367 (set_attr "length" "12")])
13369 (define_insn "*geu<mode>_compare"
13370 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13371 (compare:CC
13372 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13373 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13374 (const_int 0)))
13375 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13376 (geu:P (match_dup 1) (match_dup 2)))]
13377 ""
13378 "@
13379 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13380 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13381 #
13382 #"
13383 [(set_attr "type" "compare")
13384 (set_attr "length" "12,12,16,16")])
13386 (define_split
13387 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13388 (compare:CC
13389 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13390 (match_operand:P 2 "reg_or_neg_short_operand" ""))
13391 (const_int 0)))
13392 (set (match_operand:P 0 "gpc_reg_operand" "")
13393 (geu:P (match_dup 1) (match_dup 2)))]
13394 "reload_completed"
13395 [(set (match_dup 0)
13396 (geu:P (match_dup 1) (match_dup 2)))
13397 (set (match_dup 3)
13398 (compare:CC (match_dup 0)
13399 (const_int 0)))]
13400 "")
13402 (define_insn "*plus_geu<mode>"
13403 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13404 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13405 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13406 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13407 ""
13408 "@
13409 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13410 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
13411 [(set_attr "type" "two")
13412 (set_attr "length" "8")])
13414 (define_insn ""
13415 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13416 (compare:CC
13417 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13418 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13419 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13420 (const_int 0)))
13421 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13422 "TARGET_32BIT"
13423 "@
13424 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
13425 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13426 #
13427 #"
13428 [(set_attr "type" "compare")
13429 (set_attr "length" "8,8,12,12")])
13431 (define_split
13432 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13433 (compare:CC
13434 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13435 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13436 (match_operand:SI 3 "gpc_reg_operand" ""))
13437 (const_int 0)))
13438 (clobber (match_scratch:SI 4 ""))]
13439 "TARGET_32BIT && reload_completed"
13440 [(set (match_dup 4)
13441 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13442 (match_dup 3)))
13443 (set (match_dup 0)
13444 (compare:CC (match_dup 4)
13445 (const_int 0)))]
13446 "")
13448 (define_insn ""
13449 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13450 (compare:CC
13451 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13452 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13453 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13454 (const_int 0)))
13455 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13456 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13457 "TARGET_32BIT"
13458 "@
13459 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13460 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
13461 #
13462 #"
13463 [(set_attr "type" "compare")
13464 (set_attr "length" "8,8,12,12")])
13466 (define_split
13467 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13468 (compare:CC
13469 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13470 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13471 (match_operand:SI 3 "gpc_reg_operand" ""))
13472 (const_int 0)))
13473 (set (match_operand:SI 0 "gpc_reg_operand" "")
13474 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13475 "TARGET_32BIT && reload_completed"
13476 [(set (match_dup 0)
13477 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13478 (set (match_dup 4)
13479 (compare:CC (match_dup 0)
13480 (const_int 0)))]
13481 "")
13483 (define_insn "*neg_geu<mode>"
13484 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13485 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13486 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13487 ""
13488 "@
13489 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
13490 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
13491 [(set_attr "type" "three")
13492 (set_attr "length" "12")])
13494 (define_insn "*and_neg_geu<mode>"
13495 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13496 (and:P (neg:P
13497 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13498 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13499 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13500 ""
13501 "@
13502 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13503 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13504 [(set_attr "type" "three")
13505 (set_attr "length" "12")])
13507 (define_insn ""
13508 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13509 (compare:CC
13510 (and:SI (neg:SI
13511 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13512 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13513 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13514 (const_int 0)))
13515 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13516 "TARGET_32BIT"
13517 "@
13518 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13519 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13520 #
13521 #"
13522 [(set_attr "type" "compare")
13523 (set_attr "length" "12,12,16,16")])
13525 (define_split
13526 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13527 (compare:CC
13528 (and:SI (neg:SI
13529 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13530 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13531 (match_operand:SI 3 "gpc_reg_operand" ""))
13532 (const_int 0)))
13533 (clobber (match_scratch:SI 4 ""))]
13534 "TARGET_32BIT && reload_completed"
13535 [(set (match_dup 4)
13536 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13537 (match_dup 3)))
13538 (set (match_dup 0)
13539 (compare:CC (match_dup 4)
13540 (const_int 0)))]
13541 "")
13543 (define_insn ""
13544 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13545 (compare:CC
13546 (and:SI (neg:SI
13547 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13548 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13549 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13550 (const_int 0)))
13551 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13552 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13553 "TARGET_32BIT"
13554 "@
13555 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13556 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13557 #
13558 #"
13559 [(set_attr "type" "compare")
13560 (set_attr "length" "12,12,16,16")])
13562 (define_split
13563 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13564 (compare:CC
13565 (and:SI (neg:SI
13566 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13567 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13568 (match_operand:SI 3 "gpc_reg_operand" ""))
13569 (const_int 0)))
13570 (set (match_operand:SI 0 "gpc_reg_operand" "")
13571 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13572 "TARGET_32BIT && reload_completed"
13573 [(set (match_dup 0)
13574 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13575 (set (match_dup 4)
13576 (compare:CC (match_dup 0)
13577 (const_int 0)))]
13578 "")
13580 (define_insn ""
13581 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13582 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13583 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13584 "TARGET_POWER"
13585 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13586 [(set_attr "length" "12")])
13588 (define_insn ""
13589 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13590 (compare:CC
13591 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13592 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13593 (const_int 0)))
13594 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13595 (gt:SI (match_dup 1) (match_dup 2)))]
13596 "TARGET_POWER"
13597 "@
13598 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13599 #"
13600 [(set_attr "type" "delayed_compare")
13601 (set_attr "length" "12,16")])
13603 (define_split
13604 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13605 (compare:CC
13606 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13607 (match_operand:SI 2 "reg_or_short_operand" ""))
13608 (const_int 0)))
13609 (set (match_operand:SI 0 "gpc_reg_operand" "")
13610 (gt:SI (match_dup 1) (match_dup 2)))]
13611 "TARGET_POWER && reload_completed"
13612 [(set (match_dup 0)
13613 (gt:SI (match_dup 1) (match_dup 2)))
13614 (set (match_dup 3)
13615 (compare:CC (match_dup 0)
13616 (const_int 0)))]
13617 "")
13619 (define_insn "*plus_gt0<mode>"
13620 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13621 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13622 (const_int 0))
13623 (match_operand:P 2 "gpc_reg_operand" "r")))]
13624 ""
13625 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13626 [(set_attr "type" "three")
13627 (set_attr "length" "12")])
13629 (define_insn ""
13630 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13631 (compare:CC
13632 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13633 (const_int 0))
13634 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13635 (const_int 0)))
13636 (clobber (match_scratch:SI 3 "=&r,&r"))]
13637 "TARGET_32BIT"
13638 "@
13639 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13640 #"
13641 [(set_attr "type" "compare")
13642 (set_attr "length" "12,16")])
13644 (define_split
13645 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13646 (compare:CC
13647 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13648 (const_int 0))
13649 (match_operand:SI 2 "gpc_reg_operand" ""))
13650 (const_int 0)))
13651 (clobber (match_scratch:SI 3 ""))]
13652 "TARGET_32BIT && reload_completed"
13653 [(set (match_dup 3)
13654 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13655 (match_dup 2)))
13656 (set (match_dup 0)
13657 (compare:CC (match_dup 3)
13658 (const_int 0)))]
13659 "")
13661 (define_insn ""
13662 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13663 (compare:CC
13664 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13665 (const_int 0))
13666 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13667 (const_int 0)))
13668 (clobber (match_scratch:DI 3 "=&r,&r"))]
13669 "TARGET_64BIT"
13670 "@
13671 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13672 #"
13673 [(set_attr "type" "compare")
13674 (set_attr "length" "12,16")])
13676 (define_split
13677 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13678 (compare:CC
13679 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13680 (const_int 0))
13681 (match_operand:DI 2 "gpc_reg_operand" ""))
13682 (const_int 0)))
13683 (clobber (match_scratch:DI 3 ""))]
13684 "TARGET_64BIT && reload_completed"
13685 [(set (match_dup 3)
13686 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13687 (match_dup 2)))
13688 (set (match_dup 0)
13689 (compare:CC (match_dup 3)
13690 (const_int 0)))]
13691 "")
13693 (define_insn ""
13694 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13695 (compare:CC
13696 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13697 (const_int 0))
13698 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13699 (const_int 0)))
13700 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13701 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13702 "TARGET_32BIT"
13703 "@
13704 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13705 #"
13706 [(set_attr "type" "compare")
13707 (set_attr "length" "12,16")])
13709 (define_split
13710 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13711 (compare:CC
13712 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13713 (const_int 0))
13714 (match_operand:SI 2 "gpc_reg_operand" ""))
13715 (const_int 0)))
13716 (set (match_operand:SI 0 "gpc_reg_operand" "")
13717 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13718 "TARGET_32BIT && reload_completed"
13719 [(set (match_dup 0)
13720 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13721 (set (match_dup 3)
13722 (compare:CC (match_dup 0)
13723 (const_int 0)))]
13724 "")
13726 (define_insn ""
13727 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13728 (compare:CC
13729 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13730 (const_int 0))
13731 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13732 (const_int 0)))
13733 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13734 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13735 "TARGET_64BIT"
13736 "@
13737 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13738 #"
13739 [(set_attr "type" "compare")
13740 (set_attr "length" "12,16")])
13742 (define_split
13743 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13744 (compare:CC
13745 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13746 (const_int 0))
13747 (match_operand:DI 2 "gpc_reg_operand" ""))
13748 (const_int 0)))
13749 (set (match_operand:DI 0 "gpc_reg_operand" "")
13750 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13751 "TARGET_64BIT && reload_completed"
13752 [(set (match_dup 0)
13753 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13754 (set (match_dup 3)
13755 (compare:CC (match_dup 0)
13756 (const_int 0)))]
13757 "")
13759 (define_insn ""
13760 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13761 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13762 (match_operand:SI 2 "reg_or_short_operand" "r"))
13763 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13764 "TARGET_POWER"
13765 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13766 [(set_attr "length" "12")])
13768 (define_insn ""
13769 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13770 (compare:CC
13771 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13772 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13773 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13774 (const_int 0)))
13775 (clobber (match_scratch:SI 4 "=&r,&r"))]
13776 "TARGET_POWER"
13777 "@
13778 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13779 #"
13780 [(set_attr "type" "compare")
13781 (set_attr "length" "12,16")])
13783 (define_split
13784 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13785 (compare:CC
13786 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13787 (match_operand:SI 2 "reg_or_short_operand" ""))
13788 (match_operand:SI 3 "gpc_reg_operand" ""))
13789 (const_int 0)))
13790 (clobber (match_scratch:SI 4 ""))]
13791 "TARGET_POWER && reload_completed"
13792 [(set (match_dup 4)
13793 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13794 (set (match_dup 0)
13795 (compare:CC (match_dup 4)
13796 (const_int 0)))]
13797 "")
13799 (define_insn ""
13800 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13801 (compare:CC
13802 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13803 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13804 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13805 (const_int 0)))
13806 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13807 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13808 "TARGET_POWER"
13809 "@
13810 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13811 #"
13812 [(set_attr "type" "compare")
13813 (set_attr "length" "12,16")])
13815 (define_split
13816 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13817 (compare:CC
13818 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13819 (match_operand:SI 2 "reg_or_short_operand" ""))
13820 (match_operand:SI 3 "gpc_reg_operand" ""))
13821 (const_int 0)))
13822 (set (match_operand:SI 0 "gpc_reg_operand" "")
13823 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13824 "TARGET_POWER && reload_completed"
13825 [(set (match_dup 0)
13826 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13827 (set (match_dup 4)
13828 (compare:CC (match_dup 0)
13829 (const_int 0)))]
13830 "")
13832 (define_insn ""
13833 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13834 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13835 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13836 "TARGET_POWER"
13837 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13838 [(set_attr "length" "12")])
13840 (define_insn_and_split "*gtu<mode>"
13841 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13842 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13843 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13844 ""
13845 "#"
13846 ""
13847 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13848 (set (match_dup 0) (neg:P (match_dup 0)))]
13849 "")
13851 (define_insn_and_split "*gtu<mode>_compare"
13852 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13853 (compare:CC
13854 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13855 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13856 (const_int 0)))
13857 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13858 (gtu:P (match_dup 1) (match_dup 2)))]
13859 ""
13860 "#"
13861 ""
13862 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13863 (parallel [(set (match_dup 3)
13864 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13865 (set (match_dup 0) (neg:P (match_dup 0)))])]
13866 "")
13868 (define_insn_and_split "*plus_gtu<mode>"
13869 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13870 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13871 (match_operand:P 2 "reg_or_short_operand" "rI"))
13872 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13873 ""
13874 "#"
13875 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13876 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13877 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13878 "")
13880 (define_insn_and_split "*plus_gtu<mode>_compare"
13881 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13882 (compare:CC
13883 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13884 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13885 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13886 (const_int 0)))
13887 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13888 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13889 ""
13890 "#"
13891 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13892 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13893 (parallel [(set (match_dup 4)
13894 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13895 (const_int 0)))
13896 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13897 "")
13899 (define_insn "*neg_gtu<mode>"
13900 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13901 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13902 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13903 ""
13904 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13905 [(set_attr "type" "two")
13906 (set_attr "length" "8")])
13908 \f
13909 ;; Define both directions of branch and return. If we need a reload
13910 ;; register, we'd rather use CR0 since it is much easier to copy a
13911 ;; register CC value to there.
13913 (define_insn ""
13914 [(set (pc)
13915 (if_then_else (match_operator 1 "branch_comparison_operator"
13916 [(match_operand 2
13917 "cc_reg_operand" "y")
13918 (const_int 0)])
13919 (label_ref (match_operand 0 "" ""))
13920 (pc)))]
13921 ""
13922 "*
13923 {
13924 return output_cbranch (operands[1], \"%l0\", 0, insn);
13925 }"
13926 [(set_attr "type" "branch")])
13928 (define_insn ""
13929 [(set (pc)
13930 (if_then_else (match_operator 0 "branch_comparison_operator"
13931 [(match_operand 1
13932 "cc_reg_operand" "y")
13933 (const_int 0)])
13934 (return)
13935 (pc)))]
13936 "direct_return ()"
13937 "*
13938 {
13939 return output_cbranch (operands[0], NULL, 0, insn);
13940 }"
13941 [(set_attr "type" "jmpreg")
13942 (set_attr "length" "4")])
13944 (define_insn ""
13945 [(set (pc)
13946 (if_then_else (match_operator 1 "branch_comparison_operator"
13947 [(match_operand 2
13948 "cc_reg_operand" "y")
13949 (const_int 0)])
13950 (pc)
13951 (label_ref (match_operand 0 "" ""))))]
13952 ""
13953 "*
13954 {
13955 return output_cbranch (operands[1], \"%l0\", 1, insn);
13956 }"
13957 [(set_attr "type" "branch")])
13959 (define_insn ""
13960 [(set (pc)
13961 (if_then_else (match_operator 0 "branch_comparison_operator"
13962 [(match_operand 1
13963 "cc_reg_operand" "y")
13964 (const_int 0)])
13965 (pc)
13966 (return)))]
13967 "direct_return ()"
13968 "*
13969 {
13970 return output_cbranch (operands[0], NULL, 1, insn);
13971 }"
13972 [(set_attr "type" "jmpreg")
13973 (set_attr "length" "4")])
13975 ;; Logic on condition register values.
13977 ; This pattern matches things like
13978 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13979 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13980 ; (const_int 1)))
13981 ; which are generated by the branch logic.
13982 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13984 (define_insn "*cceq_ior_compare"
13985 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13986 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13987 [(match_operator:SI 2
13988 "branch_positive_comparison_operator"
13989 [(match_operand 3
13990 "cc_reg_operand" "y,y")
13991 (const_int 0)])
13992 (match_operator:SI 4
13993 "branch_positive_comparison_operator"
13994 [(match_operand 5
13995 "cc_reg_operand" "0,y")
13996 (const_int 0)])])
13997 (const_int 1)))]
13998 ""
13999 "cr%q1 %E0,%j2,%j4"
14000 [(set_attr "type" "cr_logical,delayed_cr")])
14002 ; Why is the constant -1 here, but 1 in the previous pattern?
14003 ; Because ~1 has all but the low bit set.
14004 (define_insn ""
14005 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14006 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
14007 [(not:SI (match_operator:SI 2
14008 "branch_positive_comparison_operator"
14009 [(match_operand 3
14010 "cc_reg_operand" "y,y")
14011 (const_int 0)]))
14012 (match_operator:SI 4
14013 "branch_positive_comparison_operator"
14014 [(match_operand 5
14015 "cc_reg_operand" "0,y")
14016 (const_int 0)])])
14017 (const_int -1)))]
14018 ""
14019 "cr%q1 %E0,%j2,%j4"
14020 [(set_attr "type" "cr_logical,delayed_cr")])
14022 (define_insn "*cceq_rev_compare"
14023 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14024 (compare:CCEQ (match_operator:SI 1
14025 "branch_positive_comparison_operator"
14026 [(match_operand 2
14027 "cc_reg_operand" "0,y")
14028 (const_int 0)])
14029 (const_int 0)))]
14030 ""
14031 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
14032 [(set_attr "type" "cr_logical,delayed_cr")])
14034 ;; If we are comparing the result of two comparisons, this can be done
14035 ;; using creqv or crxor.
14037 (define_insn_and_split ""
14038 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14039 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14040 [(match_operand 2 "cc_reg_operand" "y")
14041 (const_int 0)])
14042 (match_operator 3 "branch_comparison_operator"
14043 [(match_operand 4 "cc_reg_operand" "y")
14044 (const_int 0)])))]
14045 ""
14046 "#"
14047 ""
14048 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14049 (match_dup 5)))]
14050 "
14051 {
14052 int positive_1, positive_2;
14054 positive_1 = branch_positive_comparison_operator (operands[1],
14055 GET_MODE (operands[1]));
14056 positive_2 = branch_positive_comparison_operator (operands[3],
14057 GET_MODE (operands[3]));
14059 if (! positive_1)
14060 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14061 GET_CODE (operands[1])),
14062 SImode,
14063 operands[2], const0_rtx);
14064 else if (GET_MODE (operands[1]) != SImode)
14065 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14066 operands[2], const0_rtx);
14068 if (! positive_2)
14069 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14070 GET_CODE (operands[3])),
14071 SImode,
14072 operands[4], const0_rtx);
14073 else if (GET_MODE (operands[3]) != SImode)
14074 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14075 operands[4], const0_rtx);
14077 if (positive_1 == positive_2)
14078 {
14079 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14080 operands[5] = constm1_rtx;
14081 }
14082 else
14083 {
14084 operands[5] = const1_rtx;
14085 }
14086 }")
14088 ;; Unconditional branch and return.
14090 (define_insn "jump"
14091 [(set (pc)
14092 (label_ref (match_operand 0 "" "")))]
14093 ""
14094 "b %l0"
14095 [(set_attr "type" "branch")])
14097 (define_insn "return"
14098 [(return)]
14099 "direct_return ()"
14100 "{br|blr}"
14101 [(set_attr "type" "jmpreg")])
14103 (define_expand "indirect_jump"
14104 [(set (pc) (match_operand 0 "register_operand" ""))])
14106 (define_insn "*indirect_jump<mode>"
14107 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14108 ""
14109 "@
14110 bctr
14111 {br|blr}"
14112 [(set_attr "type" "jmpreg")])
14114 ;; Table jump for switch statements:
14115 (define_expand "tablejump"
14116 [(use (match_operand 0 "" ""))
14117 (use (label_ref (match_operand 1 "" "")))]
14118 ""
14119 "
14120 {
14121 if (TARGET_32BIT)
14122 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14123 else
14124 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14125 DONE;
14126 }")
14128 (define_expand "tablejumpsi"
14129 [(set (match_dup 3)
14130 (plus:SI (match_operand:SI 0 "" "")
14131 (match_dup 2)))
14132 (parallel [(set (pc) (match_dup 3))
14133 (use (label_ref (match_operand 1 "" "")))])]
14134 "TARGET_32BIT"
14135 "
14136 { operands[0] = force_reg (SImode, operands[0]);
14137 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14138 operands[3] = gen_reg_rtx (SImode);
14139 }")
14141 (define_expand "tablejumpdi"
14142 [(set (match_dup 4)
14143 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14144 (set (match_dup 3)
14145 (plus:DI (match_dup 4)
14146 (match_dup 2)))
14147 (parallel [(set (pc) (match_dup 3))
14148 (use (label_ref (match_operand 1 "" "")))])]
14149 "TARGET_64BIT"
14150 "
14151 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14152 operands[3] = gen_reg_rtx (DImode);
14153 operands[4] = gen_reg_rtx (DImode);
14154 }")
14156 (define_insn "*tablejump<mode>_internal1"
14157 [(set (pc)
14158 (match_operand:P 0 "register_operand" "c,*l"))
14159 (use (label_ref (match_operand 1 "" "")))]
14160 ""
14161 "@
14162 bctr
14163 {br|blr}"
14164 [(set_attr "type" "jmpreg")])
14166 (define_insn "nop"
14167 [(const_int 0)]
14168 ""
14169 "{cror 0,0,0|nop}")
14170 \f
14171 ;; Define the subtract-one-and-jump insns, starting with the template
14172 ;; so loop.c knows what to generate.
14174 (define_expand "doloop_end"
14175 [(use (match_operand 0 "" "")) ; loop pseudo
14176 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14177 (use (match_operand 2 "" "")) ; max iterations
14178 (use (match_operand 3 "" "")) ; loop level
14179 (use (match_operand 4 "" ""))] ; label
14180 ""
14181 "
14182 {
14183 /* Only use this on innermost loops. */
14184 if (INTVAL (operands[3]) > 1)
14185 FAIL;
14186 if (TARGET_64BIT)
14187 {
14188 if (GET_MODE (operands[0]) != DImode)
14189 FAIL;
14190 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14191 }
14192 else
14193 {
14194 if (GET_MODE (operands[0]) != SImode)
14195 FAIL;
14196 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14197 }
14198 DONE;
14199 }")
14201 (define_expand "ctr<mode>"
14202 [(parallel [(set (pc)
14203 (if_then_else (ne (match_operand:P 0 "register_operand" "")
14204 (const_int 1))
14205 (label_ref (match_operand 1 "" ""))
14206 (pc)))
14207 (set (match_dup 0)
14208 (plus:P (match_dup 0)
14209 (const_int -1)))
14210 (clobber (match_scratch:CC 2 ""))
14211 (clobber (match_scratch:P 3 ""))])]
14212 ""
14213 "")
14215 ;; We need to be able to do this for any operand, including MEM, or we
14216 ;; will cause reload to blow up since we don't allow output reloads on
14217 ;; JUMP_INSNs.
14218 ;; For the length attribute to be calculated correctly, the
14219 ;; label MUST be operand 0.
14221 (define_insn "*ctr<mode>_internal1"
14222 [(set (pc)
14223 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14224 (const_int 1))
14225 (label_ref (match_operand 0 "" ""))
14226 (pc)))
14227 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14228 (plus:P (match_dup 1)
14229 (const_int -1)))
14230 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14231 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14232 ""
14233 "*
14234 {
14235 if (which_alternative != 0)
14236 return \"#\";
14237 else if (get_attr_length (insn) == 4)
14238 return \"{bdn|bdnz} %l0\";
14239 else
14240 return \"bdz $+8\;b %l0\";
14241 }"
14242 [(set_attr "type" "branch")
14243 (set_attr "length" "*,12,16,16")])
14245 (define_insn "*ctr<mode>_internal2"
14246 [(set (pc)
14247 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14248 (const_int 1))
14249 (pc)
14250 (label_ref (match_operand 0 "" ""))))
14251 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14252 (plus:P (match_dup 1)
14253 (const_int -1)))
14254 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14255 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14256 ""
14257 "*
14258 {
14259 if (which_alternative != 0)
14260 return \"#\";
14261 else if (get_attr_length (insn) == 4)
14262 return \"bdz %l0\";
14263 else
14264 return \"{bdn|bdnz} $+8\;b %l0\";
14265 }"
14266 [(set_attr "type" "branch")
14267 (set_attr "length" "*,12,16,16")])
14269 ;; Similar but use EQ
14271 (define_insn "*ctr<mode>_internal5"
14272 [(set (pc)
14273 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14274 (const_int 1))
14275 (label_ref (match_operand 0 "" ""))
14276 (pc)))
14277 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14278 (plus:P (match_dup 1)
14279 (const_int -1)))
14280 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14281 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14282 ""
14283 "*
14284 {
14285 if (which_alternative != 0)
14286 return \"#\";
14287 else if (get_attr_length (insn) == 4)
14288 return \"bdz %l0\";
14289 else
14290 return \"{bdn|bdnz} $+8\;b %l0\";
14291 }"
14292 [(set_attr "type" "branch")
14293 (set_attr "length" "*,12,16,16")])
14295 (define_insn "*ctr<mode>_internal6"
14296 [(set (pc)
14297 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14298 (const_int 1))
14299 (pc)
14300 (label_ref (match_operand 0 "" ""))))
14301 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14302 (plus:P (match_dup 1)
14303 (const_int -1)))
14304 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14305 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14306 ""
14307 "*
14308 {
14309 if (which_alternative != 0)
14310 return \"#\";
14311 else if (get_attr_length (insn) == 4)
14312 return \"{bdn|bdnz} %l0\";
14313 else
14314 return \"bdz $+8\;b %l0\";
14315 }"
14316 [(set_attr "type" "branch")
14317 (set_attr "length" "*,12,16,16")])
14319 ;; Now the splitters if we could not allocate the CTR register
14321 (define_split
14322 [(set (pc)
14323 (if_then_else (match_operator 2 "comparison_operator"
14324 [(match_operand:P 1 "gpc_reg_operand" "")
14325 (const_int 1)])
14326 (match_operand 5 "" "")
14327 (match_operand 6 "" "")))
14328 (set (match_operand:P 0 "gpc_reg_operand" "")
14329 (plus:P (match_dup 1) (const_int -1)))
14330 (clobber (match_scratch:CC 3 ""))
14331 (clobber (match_scratch:P 4 ""))]
14332 "reload_completed"
14333 [(parallel [(set (match_dup 3)
14334 (compare:CC (plus:P (match_dup 1)
14335 (const_int -1))
14336 (const_int 0)))
14337 (set (match_dup 0)
14338 (plus:P (match_dup 1)
14339 (const_int -1)))])
14340 (set (pc) (if_then_else (match_dup 7)
14341 (match_dup 5)
14342 (match_dup 6)))]
14343 "
14344 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14345 operands[3], const0_rtx); }")
14347 (define_split
14348 [(set (pc)
14349 (if_then_else (match_operator 2 "comparison_operator"
14350 [(match_operand:P 1 "gpc_reg_operand" "")
14351 (const_int 1)])
14352 (match_operand 5 "" "")
14353 (match_operand 6 "" "")))
14354 (set (match_operand:P 0 "nonimmediate_operand" "")
14355 (plus:P (match_dup 1) (const_int -1)))
14356 (clobber (match_scratch:CC 3 ""))
14357 (clobber (match_scratch:P 4 ""))]
14358 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
14359 [(parallel [(set (match_dup 3)
14360 (compare:CC (plus:P (match_dup 1)
14361 (const_int -1))
14362 (const_int 0)))
14363 (set (match_dup 4)
14364 (plus:P (match_dup 1)
14365 (const_int -1)))])
14366 (set (match_dup 0)
14367 (match_dup 4))
14368 (set (pc) (if_then_else (match_dup 7)
14369 (match_dup 5)
14370 (match_dup 6)))]
14371 "
14372 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14373 operands[3], const0_rtx); }")
14374 \f
14375 (define_insn "trap"
14376 [(trap_if (const_int 1) (const_int 0))]
14377 ""
14378 "{t 31,0,0|trap}"
14379 [(set_attr "type" "trap")])
14381 (define_expand "conditional_trap"
14382 [(trap_if (match_operator 0 "trap_comparison_operator"
14383 [(match_dup 2) (match_dup 3)])
14384 (match_operand 1 "const_int_operand" ""))]
14385 ""
14386 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14387 operands[2] = rs6000_compare_op0;
14388 operands[3] = rs6000_compare_op1;")
14390 (define_insn ""
14391 [(trap_if (match_operator 0 "trap_comparison_operator"
14392 [(match_operand:GPR 1 "register_operand" "r")
14393 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
14394 (const_int 0))]
14395 ""
14396 "{t|t<wd>}%V0%I2 %1,%2"
14397 [(set_attr "type" "trap")])
14398 \f
14399 ;; Insns related to generating the function prologue and epilogue.
14401 (define_expand "prologue"
14402 [(use (const_int 0))]
14403 "TARGET_SCHED_PROLOG"
14404 "
14405 {
14406 rs6000_emit_prologue ();
14407 DONE;
14408 }")
14410 (define_insn "*movesi_from_cr_one"
14411 [(match_parallel 0 "mfcr_operation"
14412 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14413 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14414 (match_operand 3 "immediate_operand" "n")]
14415 UNSPEC_MOVESI_FROM_CR))])]
14416 "TARGET_MFCRF"
14417 "*
14418 {
14419 int mask = 0;
14420 int i;
14421 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14422 {
14423 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14424 operands[4] = GEN_INT (mask);
14425 output_asm_insn (\"mfcr %1,%4\", operands);
14426 }
14427 return \"\";
14428 }"
14429 [(set_attr "type" "mfcrf")])
14431 (define_insn "movesi_from_cr"
14432 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14433 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
14434 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
14435 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
14436 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
14437 UNSPEC_MOVESI_FROM_CR))]
14438 ""
14439 "mfcr %0"
14440 [(set_attr "type" "mfcr")])
14442 (define_insn "*stmw"
14443 [(match_parallel 0 "stmw_operation"
14444 [(set (match_operand:SI 1 "memory_operand" "=m")
14445 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14446 "TARGET_MULTIPLE"
14447 "{stm|stmw} %2,%1"
14448 [(set_attr "type" "store_ux")])
14450 (define_insn "*save_fpregs_<mode>"
14451 [(match_parallel 0 "any_parallel_operand"
14452 [(clobber (reg:P 65))
14453 (use (match_operand:P 1 "call_operand" "s"))
14454 (set (match_operand:DF 2 "memory_operand" "=m")
14455 (match_operand:DF 3 "gpc_reg_operand" "f"))])]
14456 ""
14457 "bl %z1"
14458 [(set_attr "type" "branch")
14459 (set_attr "length" "4")])
14461 ; These are to explain that changes to the stack pointer should
14462 ; not be moved over stores to stack memory.
14463 (define_insn "stack_tie"
14464 [(set (match_operand:BLK 0 "memory_operand" "+m")
14465 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14466 ""
14467 ""
14468 [(set_attr "length" "0")])
14471 (define_expand "epilogue"
14472 [(use (const_int 0))]
14473 "TARGET_SCHED_PROLOG"
14474 "
14475 {
14476 rs6000_emit_epilogue (FALSE);
14477 DONE;
14478 }")
14480 ; On some processors, doing the mtcrf one CC register at a time is
14481 ; faster (like on the 604e). On others, doing them all at once is
14482 ; faster; for instance, on the 601 and 750.
14484 (define_expand "movsi_to_cr_one"
14485 [(set (match_operand:CC 0 "cc_reg_operand" "")
14486 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
14487 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14488 ""
14489 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14491 (define_insn "*movsi_to_cr"
14492 [(match_parallel 0 "mtcrf_operation"
14493 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14494 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14495 (match_operand 3 "immediate_operand" "n")]
14496 UNSPEC_MOVESI_TO_CR))])]
14497 ""
14498 "*
14499 {
14500 int mask = 0;
14501 int i;
14502 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14503 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14504 operands[4] = GEN_INT (mask);
14505 return \"mtcrf %4,%2\";
14506 }"
14507 [(set_attr "type" "mtcr")])
14509 (define_insn "*mtcrfsi"
14510 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14511 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14512 (match_operand 2 "immediate_operand" "n")]
14513 UNSPEC_MOVESI_TO_CR))]
14514 "GET_CODE (operands[0]) == REG
14515 && CR_REGNO_P (REGNO (operands[0]))
14516 && GET_CODE (operands[2]) == CONST_INT
14517 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14518 "mtcrf %R0,%1"
14519 [(set_attr "type" "mtcr")])
14521 ; The load-multiple instructions have similar properties.
14522 ; Note that "load_multiple" is a name known to the machine-independent
14523 ; code that actually corresponds to the PowerPC load-string.
14525 (define_insn "*lmw"
14526 [(match_parallel 0 "lmw_operation"
14527 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14528 (match_operand:SI 2 "memory_operand" "m"))])]
14529 "TARGET_MULTIPLE"
14530 "{lm|lmw} %1,%2"
14531 [(set_attr "type" "load_ux")])
14533 (define_insn "*return_internal_<mode>"
14534 [(return)
14535 (use (match_operand:P 0 "register_operand" "lc"))]
14536 ""
14537 "b%T0"
14538 [(set_attr "type" "jmpreg")])
14540 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14541 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14543 (define_insn "*return_and_restore_fpregs_<mode>"
14544 [(match_parallel 0 "any_parallel_operand"
14545 [(return)
14546 (use (reg:P 65))
14547 (use (match_operand:P 1 "call_operand" "s"))
14548 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
14549 (match_operand:DF 3 "memory_operand" "m"))])]
14550 ""
14551 "b %z1")
14553 ; This is used in compiling the unwind routines.
14554 (define_expand "eh_return"
14555 [(use (match_operand 0 "general_operand" ""))]
14556 ""
14557 "
14558 {
14559 if (TARGET_32BIT)
14560 emit_insn (gen_eh_set_lr_si (operands[0]));
14561 else
14562 emit_insn (gen_eh_set_lr_di (operands[0]));
14563 DONE;
14564 }")
14566 ; We can't expand this before we know where the link register is stored.
14567 (define_insn "eh_set_lr_<mode>"
14568 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14569 UNSPECV_EH_RR)
14570 (clobber (match_scratch:P 1 "=&b"))]
14571 ""
14572 "#")
14574 (define_split
14575 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14576 (clobber (match_scratch 1 ""))]
14577 "reload_completed"
14578 [(const_int 0)]
14579 "
14580 {
14581 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14582 DONE;
14583 }")
14585 (define_insn "prefetch"
14586 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14587 (match_operand:SI 1 "const_int_operand" "n")
14588 (match_operand:SI 2 "const_int_operand" "n"))]
14589 "TARGET_POWERPC"
14590 "*
14591 {
14592 if (GET_CODE (operands[0]) == REG)
14593 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14594 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14595 }"
14596 [(set_attr "type" "load")])
14597 \f
14599 (include "sync.md")
14600 (include "altivec.md")
14601 (include "spe.md")
14602 (include "dfp.md")
14603 (include "paired.md")