1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
58 #include "tm-constrs.h"
60 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
63 #include "gstab.h" /* for N_SLINE */
66 #ifndef TARGET_NO_PROTOTYPE
67 #define TARGET_NO_PROTOTYPE 0
70 #define min(A,B) ((A) < (B) ? (A) : (B))
71 #define max(A,B) ((A) > (B) ? (A) : (B))
73 /* Structure used to define the rs6000 stack */
74 typedef struct rs6000_stack
{
75 int first_gp_reg_save
; /* first callee saved GP register used */
76 int first_fp_reg_save
; /* first callee saved FP register used */
77 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
78 int lr_save_p
; /* true if the link reg needs to be saved */
79 int cr_save_p
; /* true if the CR reg needs to be saved */
80 unsigned int vrsave_mask
; /* mask of vec registers to save */
81 int push_p
; /* true if we need to allocate stack space */
82 int calls_p
; /* true if the function makes any calls */
83 int world_save_p
; /* true if we're saving *everything*:
84 r13-r31, cr, f14-f31, vrsave, v20-v31 */
85 enum rs6000_abi abi
; /* which ABI to use */
86 int gp_save_offset
; /* offset to save GP regs from initial SP */
87 int fp_save_offset
; /* offset to save FP regs from initial SP */
88 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
89 int lr_save_offset
; /* offset to save LR from initial SP */
90 int cr_save_offset
; /* offset to save CR from initial SP */
91 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
92 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
93 int varargs_save_offset
; /* offset to save the varargs registers */
94 int ehrd_offset
; /* offset to EH return data */
95 int reg_size
; /* register size (4 or 8) */
96 HOST_WIDE_INT vars_size
; /* variable save area size */
97 int parm_size
; /* outgoing parameter size */
98 int save_size
; /* save area size */
99 int fixed_size
; /* fixed size of stack frame */
100 int gp_size
; /* size of saved GP registers */
101 int fp_size
; /* size of saved FP registers */
102 int altivec_size
; /* size of saved AltiVec registers */
103 int cr_size
; /* size to hold CR if not in save_size */
104 int vrsave_size
; /* size to hold VRSAVE if not in save_size */
105 int altivec_padding_size
; /* size of altivec alignment padding if
107 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
108 int spe_padding_size
;
109 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
110 int spe_64bit_regs_used
;
113 /* A C structure for machine-specific, per-function data.
114 This is added to the cfun structure. */
115 typedef struct machine_function
GTY(())
117 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
118 int ra_needs_full_frame
;
119 /* Some local-dynamic symbol. */
120 const char *some_ld_name
;
121 /* Whether the instruction chain has been scanned already. */
122 int insn_chain_scanned_p
;
123 /* Flags if __builtin_return_address (0) was used. */
125 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
126 varargs save area. */
127 HOST_WIDE_INT varargs_save_offset
;
130 /* Target cpu type */
132 enum processor_type rs6000_cpu
;
133 struct rs6000_cpu_select rs6000_select
[3] =
135 /* switch name, tune arch */
136 { (const char *)0, "--with-cpu=", 1, 1 },
137 { (const char *)0, "-mcpu=", 1, 1 },
138 { (const char *)0, "-mtune=", 1, 0 },
141 static GTY(()) bool rs6000_cell_dont_microcode
;
143 /* Always emit branch hint bits. */
144 static GTY(()) bool rs6000_always_hint
;
146 /* Schedule instructions for group formation. */
147 static GTY(()) bool rs6000_sched_groups
;
149 /* Align branch targets. */
150 static GTY(()) bool rs6000_align_branch_targets
;
152 /* Support for -msched-costly-dep option. */
153 const char *rs6000_sched_costly_dep_str
;
154 enum rs6000_dependence_cost rs6000_sched_costly_dep
;
156 /* Support for -minsert-sched-nops option. */
157 const char *rs6000_sched_insert_nops_str
;
158 enum rs6000_nop_insertion rs6000_sched_insert_nops
;
160 /* Support targetm.vectorize.builtin_mask_for_load. */
161 static GTY(()) tree altivec_builtin_mask_for_load
;
163 /* Size of long double. */
164 int rs6000_long_double_type_size
;
166 /* IEEE quad extended precision long double. */
169 /* Whether -mabi=altivec has appeared. */
170 int rs6000_altivec_abi
;
172 /* Nonzero if we want SPE ABI extensions. */
175 /* Nonzero if floating point operations are done in the GPRs. */
176 int rs6000_float_gprs
= 0;
178 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
179 int rs6000_darwin64_abi
;
181 /* Set to nonzero once AIX common-mode calls have been defined. */
182 static GTY(()) int common_mode_defined
;
184 /* Save information from a "cmpxx" operation until the branch or scc is
186 rtx rs6000_compare_op0
, rs6000_compare_op1
;
187 int rs6000_compare_fp_p
;
189 /* Label number of label created for -mrelocatable, to call to so we can
190 get the address of the GOT section */
191 int rs6000_pic_labelno
;
194 /* Which abi to adhere to */
195 const char *rs6000_abi_name
;
197 /* Semantics of the small data area */
198 enum rs6000_sdata_type rs6000_sdata
= SDATA_DATA
;
200 /* Which small data model to use */
201 const char *rs6000_sdata_name
= (char *)0;
203 /* Counter for labels which are to be placed in .fixup. */
204 int fixuplabelno
= 0;
207 /* Bit size of immediate TLS offsets and string from which it is decoded. */
208 int rs6000_tls_size
= 32;
209 const char *rs6000_tls_size_string
;
211 /* ABI enumeration available for subtarget to use. */
212 enum rs6000_abi rs6000_current_abi
;
214 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
218 const char *rs6000_debug_name
;
219 int rs6000_debug_stack
; /* debug stack applications */
220 int rs6000_debug_arg
; /* debug argument handling */
222 /* Value is TRUE if register/mode pair is acceptable. */
223 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
225 /* Built in types. */
227 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
228 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
230 const char *rs6000_traceback_name
;
232 traceback_default
= 0,
238 /* Flag to say the TOC is initialized */
240 char toc_label_name
[10];
242 /* Cached value of rs6000_variable_issue. This is cached in
243 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
244 static short cached_can_issue_more
;
246 static GTY(()) section
*read_only_data_section
;
247 static GTY(()) section
*private_data_section
;
248 static GTY(()) section
*read_only_private_data_section
;
249 static GTY(()) section
*sdata2_section
;
250 static GTY(()) section
*toc_section
;
252 /* Control alignment for fields within structures. */
253 /* String from -malign-XXXXX. */
254 int rs6000_alignment_flags
;
256 /* True for any options that were explicitly set. */
258 bool aix_struct_ret
; /* True if -maix-struct-ret was used. */
259 bool alignment
; /* True if -malign- was used. */
260 bool abi
; /* True if -mabi=spe/nospe was used. */
261 bool spe
; /* True if -mspe= was used. */
262 bool float_gprs
; /* True if -mfloat-gprs= was used. */
263 bool isel
; /* True if -misel was used. */
264 bool long_double
; /* True if -mlong-double- was used. */
265 bool ieee
; /* True if -mabi=ieee/ibmlongdouble used. */
266 } rs6000_explicit_options
;
268 struct builtin_description
270 /* mask is not const because we're going to alter it below. This
271 nonsense will go away when we rewrite the -march infrastructure
272 to give us more target flag bits. */
274 const enum insn_code icode
;
275 const char *const name
;
276 const enum rs6000_builtins code
;
279 /* Target cpu costs. */
281 struct processor_costs
{
282 const int mulsi
; /* cost of SImode multiplication. */
283 const int mulsi_const
; /* cost of SImode multiplication by constant. */
284 const int mulsi_const9
; /* cost of SImode mult by short constant. */
285 const int muldi
; /* cost of DImode multiplication. */
286 const int divsi
; /* cost of SImode division. */
287 const int divdi
; /* cost of DImode division. */
288 const int fp
; /* cost of simple SFmode and DFmode insns. */
289 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
290 const int sdiv
; /* cost of SFmode division (fdivs). */
291 const int ddiv
; /* cost of DFmode division (fdiv). */
292 const int cache_line_size
; /* cache line size in bytes. */
293 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
294 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
295 const int simultaneous_prefetches
; /* number of parallel prefetch
299 const struct processor_costs
*rs6000_cost
;
301 /* Processor costs (relative to an add) */
303 /* Instruction size costs on 32bit processors. */
305 struct processor_costs size32_cost
= {
306 COSTS_N_INSNS (1), /* mulsi */
307 COSTS_N_INSNS (1), /* mulsi_const */
308 COSTS_N_INSNS (1), /* mulsi_const9 */
309 COSTS_N_INSNS (1), /* muldi */
310 COSTS_N_INSNS (1), /* divsi */
311 COSTS_N_INSNS (1), /* divdi */
312 COSTS_N_INSNS (1), /* fp */
313 COSTS_N_INSNS (1), /* dmul */
314 COSTS_N_INSNS (1), /* sdiv */
315 COSTS_N_INSNS (1), /* ddiv */
322 /* Instruction size costs on 64bit processors. */
324 struct processor_costs size64_cost
= {
325 COSTS_N_INSNS (1), /* mulsi */
326 COSTS_N_INSNS (1), /* mulsi_const */
327 COSTS_N_INSNS (1), /* mulsi_const9 */
328 COSTS_N_INSNS (1), /* muldi */
329 COSTS_N_INSNS (1), /* divsi */
330 COSTS_N_INSNS (1), /* divdi */
331 COSTS_N_INSNS (1), /* fp */
332 COSTS_N_INSNS (1), /* dmul */
333 COSTS_N_INSNS (1), /* sdiv */
334 COSTS_N_INSNS (1), /* ddiv */
341 /* Instruction costs on RIOS1 processors. */
343 struct processor_costs rios1_cost
= {
344 COSTS_N_INSNS (5), /* mulsi */
345 COSTS_N_INSNS (4), /* mulsi_const */
346 COSTS_N_INSNS (3), /* mulsi_const9 */
347 COSTS_N_INSNS (5), /* muldi */
348 COSTS_N_INSNS (19), /* divsi */
349 COSTS_N_INSNS (19), /* divdi */
350 COSTS_N_INSNS (2), /* fp */
351 COSTS_N_INSNS (2), /* dmul */
352 COSTS_N_INSNS (19), /* sdiv */
353 COSTS_N_INSNS (19), /* ddiv */
360 /* Instruction costs on RIOS2 processors. */
362 struct processor_costs rios2_cost
= {
363 COSTS_N_INSNS (2), /* mulsi */
364 COSTS_N_INSNS (2), /* mulsi_const */
365 COSTS_N_INSNS (2), /* mulsi_const9 */
366 COSTS_N_INSNS (2), /* muldi */
367 COSTS_N_INSNS (13), /* divsi */
368 COSTS_N_INSNS (13), /* divdi */
369 COSTS_N_INSNS (2), /* fp */
370 COSTS_N_INSNS (2), /* dmul */
371 COSTS_N_INSNS (17), /* sdiv */
372 COSTS_N_INSNS (17), /* ddiv */
379 /* Instruction costs on RS64A processors. */
381 struct processor_costs rs64a_cost
= {
382 COSTS_N_INSNS (20), /* mulsi */
383 COSTS_N_INSNS (12), /* mulsi_const */
384 COSTS_N_INSNS (8), /* mulsi_const9 */
385 COSTS_N_INSNS (34), /* muldi */
386 COSTS_N_INSNS (65), /* divsi */
387 COSTS_N_INSNS (67), /* divdi */
388 COSTS_N_INSNS (4), /* fp */
389 COSTS_N_INSNS (4), /* dmul */
390 COSTS_N_INSNS (31), /* sdiv */
391 COSTS_N_INSNS (31), /* ddiv */
398 /* Instruction costs on MPCCORE processors. */
400 struct processor_costs mpccore_cost
= {
401 COSTS_N_INSNS (2), /* mulsi */
402 COSTS_N_INSNS (2), /* mulsi_const */
403 COSTS_N_INSNS (2), /* mulsi_const9 */
404 COSTS_N_INSNS (2), /* muldi */
405 COSTS_N_INSNS (6), /* divsi */
406 COSTS_N_INSNS (6), /* divdi */
407 COSTS_N_INSNS (4), /* fp */
408 COSTS_N_INSNS (5), /* dmul */
409 COSTS_N_INSNS (10), /* sdiv */
410 COSTS_N_INSNS (17), /* ddiv */
417 /* Instruction costs on PPC403 processors. */
419 struct processor_costs ppc403_cost
= {
420 COSTS_N_INSNS (4), /* mulsi */
421 COSTS_N_INSNS (4), /* mulsi_const */
422 COSTS_N_INSNS (4), /* mulsi_const9 */
423 COSTS_N_INSNS (4), /* muldi */
424 COSTS_N_INSNS (33), /* divsi */
425 COSTS_N_INSNS (33), /* divdi */
426 COSTS_N_INSNS (11), /* fp */
427 COSTS_N_INSNS (11), /* dmul */
428 COSTS_N_INSNS (11), /* sdiv */
429 COSTS_N_INSNS (11), /* ddiv */
436 /* Instruction costs on PPC405 processors. */
438 struct processor_costs ppc405_cost
= {
439 COSTS_N_INSNS (5), /* mulsi */
440 COSTS_N_INSNS (4), /* mulsi_const */
441 COSTS_N_INSNS (3), /* mulsi_const9 */
442 COSTS_N_INSNS (5), /* muldi */
443 COSTS_N_INSNS (35), /* divsi */
444 COSTS_N_INSNS (35), /* divdi */
445 COSTS_N_INSNS (11), /* fp */
446 COSTS_N_INSNS (11), /* dmul */
447 COSTS_N_INSNS (11), /* sdiv */
448 COSTS_N_INSNS (11), /* ddiv */
455 /* Instruction costs on PPC440 processors. */
457 struct processor_costs ppc440_cost
= {
458 COSTS_N_INSNS (3), /* mulsi */
459 COSTS_N_INSNS (2), /* mulsi_const */
460 COSTS_N_INSNS (2), /* mulsi_const9 */
461 COSTS_N_INSNS (3), /* muldi */
462 COSTS_N_INSNS (34), /* divsi */
463 COSTS_N_INSNS (34), /* divdi */
464 COSTS_N_INSNS (5), /* fp */
465 COSTS_N_INSNS (5), /* dmul */
466 COSTS_N_INSNS (19), /* sdiv */
467 COSTS_N_INSNS (33), /* ddiv */
474 /* Instruction costs on PPC601 processors. */
476 struct processor_costs ppc601_cost
= {
477 COSTS_N_INSNS (5), /* mulsi */
478 COSTS_N_INSNS (5), /* mulsi_const */
479 COSTS_N_INSNS (5), /* mulsi_const9 */
480 COSTS_N_INSNS (5), /* muldi */
481 COSTS_N_INSNS (36), /* divsi */
482 COSTS_N_INSNS (36), /* divdi */
483 COSTS_N_INSNS (4), /* fp */
484 COSTS_N_INSNS (5), /* dmul */
485 COSTS_N_INSNS (17), /* sdiv */
486 COSTS_N_INSNS (31), /* ddiv */
493 /* Instruction costs on PPC603 processors. */
495 struct processor_costs ppc603_cost
= {
496 COSTS_N_INSNS (5), /* mulsi */
497 COSTS_N_INSNS (3), /* mulsi_const */
498 COSTS_N_INSNS (2), /* mulsi_const9 */
499 COSTS_N_INSNS (5), /* muldi */
500 COSTS_N_INSNS (37), /* divsi */
501 COSTS_N_INSNS (37), /* divdi */
502 COSTS_N_INSNS (3), /* fp */
503 COSTS_N_INSNS (4), /* dmul */
504 COSTS_N_INSNS (18), /* sdiv */
505 COSTS_N_INSNS (33), /* ddiv */
512 /* Instruction costs on PPC604 processors. */
514 struct processor_costs ppc604_cost
= {
515 COSTS_N_INSNS (4), /* mulsi */
516 COSTS_N_INSNS (4), /* mulsi_const */
517 COSTS_N_INSNS (4), /* mulsi_const9 */
518 COSTS_N_INSNS (4), /* muldi */
519 COSTS_N_INSNS (20), /* divsi */
520 COSTS_N_INSNS (20), /* divdi */
521 COSTS_N_INSNS (3), /* fp */
522 COSTS_N_INSNS (3), /* dmul */
523 COSTS_N_INSNS (18), /* sdiv */
524 COSTS_N_INSNS (32), /* ddiv */
531 /* Instruction costs on PPC604e processors. */
533 struct processor_costs ppc604e_cost
= {
534 COSTS_N_INSNS (2), /* mulsi */
535 COSTS_N_INSNS (2), /* mulsi_const */
536 COSTS_N_INSNS (2), /* mulsi_const9 */
537 COSTS_N_INSNS (2), /* muldi */
538 COSTS_N_INSNS (20), /* divsi */
539 COSTS_N_INSNS (20), /* divdi */
540 COSTS_N_INSNS (3), /* fp */
541 COSTS_N_INSNS (3), /* dmul */
542 COSTS_N_INSNS (18), /* sdiv */
543 COSTS_N_INSNS (32), /* ddiv */
550 /* Instruction costs on PPC620 processors. */
552 struct processor_costs ppc620_cost
= {
553 COSTS_N_INSNS (5), /* mulsi */
554 COSTS_N_INSNS (4), /* mulsi_const */
555 COSTS_N_INSNS (3), /* mulsi_const9 */
556 COSTS_N_INSNS (7), /* muldi */
557 COSTS_N_INSNS (21), /* divsi */
558 COSTS_N_INSNS (37), /* divdi */
559 COSTS_N_INSNS (3), /* fp */
560 COSTS_N_INSNS (3), /* dmul */
561 COSTS_N_INSNS (18), /* sdiv */
562 COSTS_N_INSNS (32), /* ddiv */
569 /* Instruction costs on PPC630 processors. */
571 struct processor_costs ppc630_cost
= {
572 COSTS_N_INSNS (5), /* mulsi */
573 COSTS_N_INSNS (4), /* mulsi_const */
574 COSTS_N_INSNS (3), /* mulsi_const9 */
575 COSTS_N_INSNS (7), /* muldi */
576 COSTS_N_INSNS (21), /* divsi */
577 COSTS_N_INSNS (37), /* divdi */
578 COSTS_N_INSNS (3), /* fp */
579 COSTS_N_INSNS (3), /* dmul */
580 COSTS_N_INSNS (17), /* sdiv */
581 COSTS_N_INSNS (21), /* ddiv */
588 /* Instruction costs on Cell processor. */
589 /* COSTS_N_INSNS (1) ~ one add. */
591 struct processor_costs ppccell_cost
= {
592 COSTS_N_INSNS (9/2)+2, /* mulsi */
593 COSTS_N_INSNS (6/2), /* mulsi_const */
594 COSTS_N_INSNS (6/2), /* mulsi_const9 */
595 COSTS_N_INSNS (15/2)+2, /* muldi */
596 COSTS_N_INSNS (38/2), /* divsi */
597 COSTS_N_INSNS (70/2), /* divdi */
598 COSTS_N_INSNS (10/2), /* fp */
599 COSTS_N_INSNS (10/2), /* dmul */
600 COSTS_N_INSNS (74/2), /* sdiv */
601 COSTS_N_INSNS (74/2), /* ddiv */
608 /* Instruction costs on PPC750 and PPC7400 processors. */
610 struct processor_costs ppc750_cost
= {
611 COSTS_N_INSNS (5), /* mulsi */
612 COSTS_N_INSNS (3), /* mulsi_const */
613 COSTS_N_INSNS (2), /* mulsi_const9 */
614 COSTS_N_INSNS (5), /* muldi */
615 COSTS_N_INSNS (17), /* divsi */
616 COSTS_N_INSNS (17), /* divdi */
617 COSTS_N_INSNS (3), /* fp */
618 COSTS_N_INSNS (3), /* dmul */
619 COSTS_N_INSNS (17), /* sdiv */
620 COSTS_N_INSNS (31), /* ddiv */
627 /* Instruction costs on PPC7450 processors. */
629 struct processor_costs ppc7450_cost
= {
630 COSTS_N_INSNS (4), /* mulsi */
631 COSTS_N_INSNS (3), /* mulsi_const */
632 COSTS_N_INSNS (3), /* mulsi_const9 */
633 COSTS_N_INSNS (4), /* muldi */
634 COSTS_N_INSNS (23), /* divsi */
635 COSTS_N_INSNS (23), /* divdi */
636 COSTS_N_INSNS (5), /* fp */
637 COSTS_N_INSNS (5), /* dmul */
638 COSTS_N_INSNS (21), /* sdiv */
639 COSTS_N_INSNS (35), /* ddiv */
646 /* Instruction costs on PPC8540 processors. */
648 struct processor_costs ppc8540_cost
= {
649 COSTS_N_INSNS (4), /* mulsi */
650 COSTS_N_INSNS (4), /* mulsi_const */
651 COSTS_N_INSNS (4), /* mulsi_const9 */
652 COSTS_N_INSNS (4), /* muldi */
653 COSTS_N_INSNS (19), /* divsi */
654 COSTS_N_INSNS (19), /* divdi */
655 COSTS_N_INSNS (4), /* fp */
656 COSTS_N_INSNS (4), /* dmul */
657 COSTS_N_INSNS (29), /* sdiv */
658 COSTS_N_INSNS (29), /* ddiv */
662 1, /* prefetch streams /*/
665 /* Instruction costs on POWER4 and POWER5 processors. */
667 struct processor_costs power4_cost
= {
668 COSTS_N_INSNS (3), /* mulsi */
669 COSTS_N_INSNS (2), /* mulsi_const */
670 COSTS_N_INSNS (2), /* mulsi_const9 */
671 COSTS_N_INSNS (4), /* muldi */
672 COSTS_N_INSNS (18), /* divsi */
673 COSTS_N_INSNS (34), /* divdi */
674 COSTS_N_INSNS (3), /* fp */
675 COSTS_N_INSNS (3), /* dmul */
676 COSTS_N_INSNS (17), /* sdiv */
677 COSTS_N_INSNS (17), /* ddiv */
681 8, /* prefetch streams /*/
684 /* Instruction costs on POWER6 processors. */
686 struct processor_costs power6_cost
= {
687 COSTS_N_INSNS (8), /* mulsi */
688 COSTS_N_INSNS (8), /* mulsi_const */
689 COSTS_N_INSNS (8), /* mulsi_const9 */
690 COSTS_N_INSNS (8), /* muldi */
691 COSTS_N_INSNS (22), /* divsi */
692 COSTS_N_INSNS (28), /* divdi */
693 COSTS_N_INSNS (3), /* fp */
694 COSTS_N_INSNS (3), /* dmul */
695 COSTS_N_INSNS (13), /* sdiv */
696 COSTS_N_INSNS (16), /* ddiv */
700 16, /* prefetch streams */
704 static bool rs6000_function_ok_for_sibcall (tree
, tree
);
705 static const char *rs6000_invalid_within_doloop (const_rtx
);
706 static rtx
rs6000_generate_compare (enum rtx_code
);
707 static void rs6000_emit_stack_tie (void);
708 static void rs6000_frame_related (rtx
, rtx
, HOST_WIDE_INT
, rtx
, rtx
);
709 static rtx
spe_synthesize_frame_save (rtx
);
710 static bool spe_func_has_64bit_regs_p (void);
711 static void emit_frame_save (rtx
, rtx
, enum machine_mode
, unsigned int,
713 static rtx
gen_frame_mem_offset (enum machine_mode
, rtx
, int);
714 static void rs6000_emit_allocate_stack (HOST_WIDE_INT
, int);
715 static unsigned rs6000_hash_constant (rtx
);
716 static unsigned toc_hash_function (const void *);
717 static int toc_hash_eq (const void *, const void *);
718 static int constant_pool_expr_1 (rtx
, int *, int *);
719 static bool constant_pool_expr_p (rtx
);
720 static bool legitimate_small_data_p (enum machine_mode
, rtx
);
721 static bool legitimate_lo_sum_address_p (enum machine_mode
, rtx
, int);
722 static struct machine_function
* rs6000_init_machine_status (void);
723 static bool rs6000_assemble_integer (rtx
, unsigned int, int);
724 static bool no_global_regs_above (int);
725 #ifdef HAVE_GAS_HIDDEN
726 static void rs6000_assemble_visibility (tree
, int);
728 static int rs6000_ra_ever_killed (void);
729 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
730 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
731 static bool rs6000_ms_bitfield_layout_p (const_tree
);
732 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
733 static void rs6000_eliminate_indexed_memrefs (rtx operands
[2]);
734 static const char *rs6000_mangle_type (const_tree
);
735 extern const struct attribute_spec rs6000_attribute_table
[];
736 static void rs6000_set_default_type_attributes (tree
);
737 static bool rs6000_reg_live_or_pic_offset_p (int);
738 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT
);
739 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT
);
740 static void rs6000_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
742 static rtx
rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
, HOST_WIDE_INT
);
743 static bool rs6000_return_in_memory (const_tree
, const_tree
);
744 static void rs6000_file_start (void);
746 static int rs6000_elf_reloc_rw_mask (void);
747 static void rs6000_elf_asm_out_constructor (rtx
, int);
748 static void rs6000_elf_asm_out_destructor (rtx
, int);
749 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED
;
750 static void rs6000_elf_asm_init_sections (void);
751 static section
*rs6000_elf_select_rtx_section (enum machine_mode
, rtx
,
752 unsigned HOST_WIDE_INT
);
753 static void rs6000_elf_encode_section_info (tree
, rtx
, int)
756 static bool rs6000_use_blocks_for_constant_p (enum machine_mode
, const_rtx
);
758 static void rs6000_xcoff_asm_output_anchor (rtx
);
759 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
760 static void rs6000_xcoff_asm_init_sections (void);
761 static int rs6000_xcoff_reloc_rw_mask (void);
762 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree
);
763 static section
*rs6000_xcoff_select_section (tree
, int,
764 unsigned HOST_WIDE_INT
);
765 static void rs6000_xcoff_unique_section (tree
, int);
766 static section
*rs6000_xcoff_select_rtx_section
767 (enum machine_mode
, rtx
, unsigned HOST_WIDE_INT
);
768 static const char * rs6000_xcoff_strip_name_encoding (const char *);
769 static unsigned int rs6000_xcoff_section_type_flags (tree
, const char *, int);
770 static void rs6000_xcoff_file_start (void);
771 static void rs6000_xcoff_file_end (void);
773 static int rs6000_variable_issue (FILE *, int, rtx
, int);
774 static bool rs6000_rtx_costs (rtx
, int, int, int *);
775 static int rs6000_adjust_cost (rtx
, rtx
, rtx
, int);
776 static void rs6000_sched_init (FILE *, int, int);
777 static bool is_microcoded_insn (rtx
);
778 static bool is_nonpipeline_insn (rtx
);
779 static bool is_cracked_insn (rtx
);
780 static bool is_branch_slot_insn (rtx
);
781 static bool is_load_insn (rtx
);
782 static rtx
get_store_dest (rtx pat
);
783 static bool is_store_insn (rtx
);
784 static bool set_to_load_agen (rtx
,rtx
);
785 static bool adjacent_mem_locations (rtx
,rtx
);
786 static int rs6000_adjust_priority (rtx
, int);
787 static int rs6000_issue_rate (void);
788 static bool rs6000_is_costly_dependence (dep_t
, int, int);
789 static rtx
get_next_active_insn (rtx
, rtx
);
790 static bool insn_terminates_group_p (rtx
, enum group_termination
);
791 static bool insn_must_be_first_in_group (rtx
);
792 static bool insn_must_be_last_in_group (rtx
);
793 static bool is_costly_group (rtx
*, rtx
);
794 static int force_new_group (int, FILE *, rtx
*, rtx
, bool *, int, int *);
795 static int redefine_groups (FILE *, int, rtx
, rtx
);
796 static int pad_groups (FILE *, int, rtx
, rtx
);
797 static void rs6000_sched_finish (FILE *, int);
798 static int rs6000_sched_reorder (FILE *, int, rtx
*, int *, int);
799 static int rs6000_sched_reorder2 (FILE *, int, rtx
*, int *, int);
800 static int rs6000_use_sched_lookahead (void);
801 static int rs6000_use_sched_lookahead_guard (rtx
);
802 static tree
rs6000_builtin_reciprocal (unsigned int, bool, bool);
803 static tree
rs6000_builtin_mask_for_load (void);
804 static tree
rs6000_builtin_mul_widen_even (tree
);
805 static tree
rs6000_builtin_mul_widen_odd (tree
);
806 static tree
rs6000_builtin_conversion (enum tree_code
, tree
);
808 static void def_builtin (int, const char *, tree
, int);
809 static bool rs6000_vector_alignment_reachable (const_tree
, bool);
810 static void rs6000_init_builtins (void);
811 static rtx
rs6000_expand_unop_builtin (enum insn_code
, tree
, rtx
);
812 static rtx
rs6000_expand_binop_builtin (enum insn_code
, tree
, rtx
);
813 static rtx
rs6000_expand_ternop_builtin (enum insn_code
, tree
, rtx
);
814 static rtx
rs6000_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
815 static void altivec_init_builtins (void);
816 static void rs6000_common_init_builtins (void);
817 static void rs6000_init_libfuncs (void);
819 static void paired_init_builtins (void);
820 static rtx
paired_expand_builtin (tree
, rtx
, bool *);
821 static rtx
paired_expand_lv_builtin (enum insn_code
, tree
, rtx
);
822 static rtx
paired_expand_stv_builtin (enum insn_code
, tree
);
823 static rtx
paired_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
825 static void enable_mask_for_builtins (struct builtin_description
*, int,
826 enum rs6000_builtins
,
827 enum rs6000_builtins
);
828 static tree
build_opaque_vector_type (tree
, int);
829 static void spe_init_builtins (void);
830 static rtx
spe_expand_builtin (tree
, rtx
, bool *);
831 static rtx
spe_expand_stv_builtin (enum insn_code
, tree
);
832 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
833 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
834 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
835 static rs6000_stack_t
*rs6000_stack_info (void);
836 static void debug_stack_info (rs6000_stack_t
*);
838 static rtx
altivec_expand_builtin (tree
, rtx
, bool *);
839 static rtx
altivec_expand_ld_builtin (tree
, rtx
, bool *);
840 static rtx
altivec_expand_st_builtin (tree
, rtx
, bool *);
841 static rtx
altivec_expand_dst_builtin (tree
, rtx
, bool *);
842 static rtx
altivec_expand_abs_builtin (enum insn_code
, tree
, rtx
);
843 static rtx
altivec_expand_predicate_builtin (enum insn_code
,
844 const char *, tree
, rtx
);
845 static rtx
altivec_expand_lv_builtin (enum insn_code
, tree
, rtx
);
846 static rtx
altivec_expand_stv_builtin (enum insn_code
, tree
);
847 static rtx
altivec_expand_vec_init_builtin (tree
, tree
, rtx
);
848 static rtx
altivec_expand_vec_set_builtin (tree
);
849 static rtx
altivec_expand_vec_ext_builtin (tree
, rtx
);
850 static int get_element_number (tree
, tree
);
851 static bool rs6000_handle_option (size_t, const char *, int);
852 static void rs6000_parse_tls_size_option (void);
853 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
854 static int first_altivec_reg_to_save (void);
855 static unsigned int compute_vrsave_mask (void);
856 static void compute_save_world_info (rs6000_stack_t
*info_ptr
);
857 static void is_altivec_return_reg (rtx
, void *);
858 static rtx
generate_set_vrsave (rtx
, rs6000_stack_t
*, int);
859 int easy_vector_constant (rtx
, enum machine_mode
);
860 static bool rs6000_is_opaque_type (const_tree
);
861 static rtx
rs6000_dwarf_register_span (rtx
);
862 static void rs6000_init_dwarf_reg_sizes_extra (tree
);
863 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
864 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
865 static rtx
rs6000_tls_get_addr (void);
866 static rtx
rs6000_got_sym (void);
867 static int rs6000_tls_symbol_ref_1 (rtx
*, void *);
868 static const char *rs6000_get_some_local_dynamic_name (void);
869 static int rs6000_get_some_local_dynamic_name_1 (rtx
*, void *);
870 static rtx
rs6000_complex_function_value (enum machine_mode
);
871 static rtx
rs6000_spe_function_arg (CUMULATIVE_ARGS
*,
872 enum machine_mode
, tree
);
873 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*,
875 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*,
876 tree
, HOST_WIDE_INT
);
877 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*,
880 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*,
881 const_tree
, HOST_WIDE_INT
,
883 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
, int, bool);
884 static rtx
rs6000_mixed_function_arg (enum machine_mode
, tree
, int);
885 static void rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
);
886 static void setup_incoming_varargs (CUMULATIVE_ARGS
*,
887 enum machine_mode
, tree
,
889 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS
*, enum machine_mode
,
891 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
893 static const char *invalid_arg_for_unprototyped_fn (const_tree
, const_tree
, const_tree
);
895 static void macho_branch_islands (void);
896 static int no_previous_def (tree function_name
);
897 static tree
get_prev_label (tree function_name
);
898 static void rs6000_darwin_file_start (void);
901 static tree
rs6000_build_builtin_va_list (void);
902 static tree
rs6000_gimplify_va_arg (tree
, tree
, tree
*, tree
*);
903 static bool rs6000_must_pass_in_stack (enum machine_mode
, const_tree
);
904 static bool rs6000_scalar_mode_supported_p (enum machine_mode
);
905 static bool rs6000_vector_mode_supported_p (enum machine_mode
);
906 static int get_vec_cmp_insn (enum rtx_code
, enum machine_mode
,
908 static rtx
rs6000_emit_vector_compare (enum rtx_code
, rtx
, rtx
,
910 static int get_vsel_insn (enum machine_mode
);
911 static void rs6000_emit_vector_select (rtx
, rtx
, rtx
, rtx
);
912 static tree
rs6000_stack_protect_fail (void);
914 const int INSN_NOT_AVAILABLE
= -1;
915 static enum machine_mode
rs6000_eh_return_filter_mode (void);
917 /* Hash table stuff for keeping track of TOC entries. */
919 struct toc_hash_struct
GTY(())
921 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
922 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
924 enum machine_mode key_mode
;
928 static GTY ((param_is (struct toc_hash_struct
))) htab_t toc_hash_table
;
930 /* Default register names. */
931 char rs6000_reg_names
[][8] =
933 "0", "1", "2", "3", "4", "5", "6", "7",
934 "8", "9", "10", "11", "12", "13", "14", "15",
935 "16", "17", "18", "19", "20", "21", "22", "23",
936 "24", "25", "26", "27", "28", "29", "30", "31",
937 "0", "1", "2", "3", "4", "5", "6", "7",
938 "8", "9", "10", "11", "12", "13", "14", "15",
939 "16", "17", "18", "19", "20", "21", "22", "23",
940 "24", "25", "26", "27", "28", "29", "30", "31",
941 "mq", "lr", "ctr","ap",
942 "0", "1", "2", "3", "4", "5", "6", "7",
944 /* AltiVec registers. */
945 "0", "1", "2", "3", "4", "5", "6", "7",
946 "8", "9", "10", "11", "12", "13", "14", "15",
947 "16", "17", "18", "19", "20", "21", "22", "23",
948 "24", "25", "26", "27", "28", "29", "30", "31",
951 "spe_acc", "spefscr",
952 /* Soft frame pointer. */
956 #ifdef TARGET_REGNAMES
957 static const char alt_reg_names
[][8] =
959 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
960 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
961 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
962 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
963 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
964 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
965 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
966 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
967 "mq", "lr", "ctr", "ap",
968 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
970 /* AltiVec registers. */
971 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
972 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
973 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
974 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
977 "spe_acc", "spefscr",
978 /* Soft frame pointer. */
983 #ifndef MASK_STRICT_ALIGN
984 #define MASK_STRICT_ALIGN 0
986 #ifndef TARGET_PROFILE_KERNEL
987 #define TARGET_PROFILE_KERNEL 0
990 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
991 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
993 /* Initialize the GCC target structure. */
994 #undef TARGET_ATTRIBUTE_TABLE
995 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
996 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
997 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
999 #undef TARGET_ASM_ALIGNED_DI_OP
1000 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1002 /* Default unaligned ops are only provided for ELF. Find the ops needed
1003 for non-ELF systems. */
1004 #ifndef OBJECT_FORMAT_ELF
1006 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1008 #undef TARGET_ASM_UNALIGNED_HI_OP
1009 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1010 #undef TARGET_ASM_UNALIGNED_SI_OP
1011 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1012 #undef TARGET_ASM_UNALIGNED_DI_OP
1013 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1016 #undef TARGET_ASM_UNALIGNED_HI_OP
1017 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1018 #undef TARGET_ASM_UNALIGNED_SI_OP
1019 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1020 #undef TARGET_ASM_UNALIGNED_DI_OP
1021 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1022 #undef TARGET_ASM_ALIGNED_DI_OP
1023 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1027 /* This hook deals with fixups for relocatable code and DI-mode objects
1029 #undef TARGET_ASM_INTEGER
1030 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1032 #ifdef HAVE_GAS_HIDDEN
1033 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1034 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1037 #undef TARGET_HAVE_TLS
1038 #define TARGET_HAVE_TLS HAVE_AS_TLS
1040 #undef TARGET_CANNOT_FORCE_CONST_MEM
1041 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
1043 #undef TARGET_ASM_FUNCTION_PROLOGUE
1044 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1045 #undef TARGET_ASM_FUNCTION_EPILOGUE
1046 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1048 #undef TARGET_SCHED_VARIABLE_ISSUE
1049 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1051 #undef TARGET_SCHED_ISSUE_RATE
1052 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1053 #undef TARGET_SCHED_ADJUST_COST
1054 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1055 #undef TARGET_SCHED_ADJUST_PRIORITY
1056 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1057 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1058 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1059 #undef TARGET_SCHED_INIT
1060 #define TARGET_SCHED_INIT rs6000_sched_init
1061 #undef TARGET_SCHED_FINISH
1062 #define TARGET_SCHED_FINISH rs6000_sched_finish
1063 #undef TARGET_SCHED_REORDER
1064 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1065 #undef TARGET_SCHED_REORDER2
1066 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1068 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1069 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1071 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1072 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1074 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1075 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1076 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
1077 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
1078 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
1079 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
1080 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
1081 #define TARGET_VECTORIZE_BUILTIN_CONVERSION rs6000_builtin_conversion
1083 #undef TARGET_VECTOR_ALIGNMENT_REACHABLE
1084 #define TARGET_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1086 #undef TARGET_INIT_BUILTINS
1087 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1089 #undef TARGET_EXPAND_BUILTIN
1090 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1092 #undef TARGET_MANGLE_TYPE
1093 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1095 #undef TARGET_INIT_LIBFUNCS
1096 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1099 #undef TARGET_BINDS_LOCAL_P
1100 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1103 #undef TARGET_MS_BITFIELD_LAYOUT_P
1104 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1106 #undef TARGET_ASM_OUTPUT_MI_THUNK
1107 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1109 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1110 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1112 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1113 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1115 #undef TARGET_INVALID_WITHIN_DOLOOP
1116 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1118 #undef TARGET_RTX_COSTS
1119 #define TARGET_RTX_COSTS rs6000_rtx_costs
1120 #undef TARGET_ADDRESS_COST
1121 #define TARGET_ADDRESS_COST hook_int_rtx_0
1123 #undef TARGET_VECTOR_OPAQUE_P
1124 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
1126 #undef TARGET_DWARF_REGISTER_SPAN
1127 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1129 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1130 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1132 /* On rs6000, function arguments are promoted, as are function return
1134 #undef TARGET_PROMOTE_FUNCTION_ARGS
1135 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
1136 #undef TARGET_PROMOTE_FUNCTION_RETURN
1137 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
1139 #undef TARGET_RETURN_IN_MEMORY
1140 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1142 #undef TARGET_SETUP_INCOMING_VARARGS
1143 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1145 /* Always strict argument naming on rs6000. */
1146 #undef TARGET_STRICT_ARGUMENT_NAMING
1147 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1148 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1149 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1150 #undef TARGET_SPLIT_COMPLEX_ARG
1151 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1152 #undef TARGET_MUST_PASS_IN_STACK
1153 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1154 #undef TARGET_PASS_BY_REFERENCE
1155 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1156 #undef TARGET_ARG_PARTIAL_BYTES
1157 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1159 #undef TARGET_BUILD_BUILTIN_VA_LIST
1160 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1162 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1163 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1165 #undef TARGET_EH_RETURN_FILTER_MODE
1166 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1168 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1169 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1171 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1172 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1174 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1175 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1177 #undef TARGET_HANDLE_OPTION
1178 #define TARGET_HANDLE_OPTION rs6000_handle_option
1180 #undef TARGET_DEFAULT_TARGET_FLAGS
1181 #define TARGET_DEFAULT_TARGET_FLAGS \
1184 #undef TARGET_STACK_PROTECT_FAIL
1185 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1187 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1188 The PowerPC architecture requires only weak consistency among
1189 processors--that is, memory accesses between processors need not be
1190 sequentially consistent and memory accesses among processors can occur
1191 in any order. The ability to order memory accesses weakly provides
1192 opportunities for more efficient use of the system bus. Unless a
1193 dependency exists, the 604e allows read operations to precede store
1195 #undef TARGET_RELAXED_ORDERING
1196 #define TARGET_RELAXED_ORDERING true
1199 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1200 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1203 /* Use a 32-bit anchor range. This leads to sequences like:
1205 addis tmp,anchor,high
1208 where tmp itself acts as an anchor, and can be shared between
1209 accesses to the same 64k page. */
1210 #undef TARGET_MIN_ANCHOR_OFFSET
1211 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1212 #undef TARGET_MAX_ANCHOR_OFFSET
1213 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1214 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1215 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1217 #undef TARGET_BUILTIN_RECIPROCAL
1218 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1220 struct gcc_target targetm
= TARGET_INITIALIZER
;
1223 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1226 rs6000_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
1228 /* The GPRs can hold any mode, but values bigger than one register
1229 cannot go past R31. */
1230 if (INT_REGNO_P (regno
))
1231 return INT_REGNO_P (regno
+ HARD_REGNO_NREGS (regno
, mode
) - 1);
1233 /* The float registers can only hold floating modes and DImode.
1234 This excludes the 32-bit decimal float mode for now. */
1235 if (FP_REGNO_P (regno
))
1237 ((SCALAR_FLOAT_MODE_P (mode
)
1238 && (mode
!= TDmode
|| (regno
% 2) == 0)
1240 && FP_REGNO_P (regno
+ HARD_REGNO_NREGS (regno
, mode
) - 1))
1241 || (GET_MODE_CLASS (mode
) == MODE_INT
1242 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
1243 || (PAIRED_SIMD_REGNO_P (regno
) && TARGET_PAIRED_FLOAT
1244 && PAIRED_VECTOR_MODE (mode
)));
1246 /* The CR register can only hold CC modes. */
1247 if (CR_REGNO_P (regno
))
1248 return GET_MODE_CLASS (mode
) == MODE_CC
;
1250 if (XER_REGNO_P (regno
))
1251 return mode
== PSImode
;
1253 /* AltiVec only in AldyVec registers. */
1254 if (ALTIVEC_REGNO_P (regno
))
1255 return ALTIVEC_VECTOR_MODE (mode
);
1257 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1258 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1261 /* We cannot put TImode anywhere except general register and it must be
1262 able to fit within the register set. */
1264 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1267 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1269 rs6000_init_hard_regno_mode_ok (void)
1273 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
1274 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1275 if (rs6000_hard_regno_mode_ok (r
, m
))
1276 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
1280 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
1283 darwin_rs6000_override_options (void)
1285 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
1287 rs6000_altivec_abi
= 1;
1288 TARGET_ALTIVEC_VRSAVE
= 1;
1289 if (DEFAULT_ABI
== ABI_DARWIN
)
1291 if (MACHO_DYNAMIC_NO_PIC_P
)
1294 warning (0, "-mdynamic-no-pic overrides -fpic or -fPIC");
1297 else if (flag_pic
== 1)
1302 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
1304 target_flags
|= MASK_POWERPC64
;
1305 warning (0, "-m64 requires PowerPC64 architecture, enabling");
1309 rs6000_default_long_calls
= 1;
1310 target_flags
|= MASK_SOFT_FLOAT
;
1313 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
1315 if (!flag_mkernel
&& !flag_apple_kext
1317 && ! (target_flags_explicit
& MASK_ALTIVEC
))
1318 target_flags
|= MASK_ALTIVEC
;
1320 /* Unless the user (not the configurer) has explicitly overridden
1321 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
1322 G4 unless targetting the kernel. */
1325 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
1326 && ! (target_flags_explicit
& MASK_ALTIVEC
)
1327 && ! rs6000_select
[1].string
)
1329 target_flags
|= MASK_ALTIVEC
;
1334 /* If not otherwise specified by a target, make 'long double' equivalent to
1337 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1338 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1341 /* Override command line options. Mostly we process the processor
1342 type and sometimes adjust other TARGET_ options. */
1345 rs6000_override_options (const char *default_cpu
)
1348 struct rs6000_cpu_select
*ptr
;
1351 /* Simplifications for entries below. */
1354 POWERPC_BASE_MASK
= MASK_POWERPC
| MASK_NEW_MNEMONICS
,
1355 POWERPC_7400_MASK
= POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_ALTIVEC
1358 /* This table occasionally claims that a processor does not support
1359 a particular feature even though it does, but the feature is slower
1360 than the alternative. Thus, it shouldn't be relied on as a
1361 complete description of the processor's support.
1363 Please keep this list in order, and don't forget to update the
1364 documentation in invoke.texi when adding a new processor or
1368 const char *const name
; /* Canonical processor name. */
1369 const enum processor_type processor
; /* Processor type enum value. */
1370 const int target_enable
; /* Target flags to enable. */
1371 } const processor_target_table
[]
1372 = {{"401", PROCESSOR_PPC403
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1373 {"403", PROCESSOR_PPC403
,
1374 POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
| MASK_STRICT_ALIGN
},
1375 {"405", PROCESSOR_PPC405
,
1376 POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
| MASK_MULHW
| MASK_DLMZB
},
1377 {"405fp", PROCESSOR_PPC405
,
1378 POWERPC_BASE_MASK
| MASK_MULHW
| MASK_DLMZB
},
1379 {"440", PROCESSOR_PPC440
,
1380 POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
| MASK_MULHW
| MASK_DLMZB
},
1381 {"440fp", PROCESSOR_PPC440
,
1382 POWERPC_BASE_MASK
| MASK_MULHW
| MASK_DLMZB
},
1383 {"505", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
},
1384 {"601", PROCESSOR_PPC601
,
1385 MASK_POWER
| POWERPC_BASE_MASK
| MASK_MULTIPLE
| MASK_STRING
},
1386 {"602", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1387 {"603", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1388 {"603e", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1389 {"604", PROCESSOR_PPC604
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1390 {"604e", PROCESSOR_PPC604e
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1391 {"620", PROCESSOR_PPC620
,
1392 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1393 {"630", PROCESSOR_PPC630
,
1394 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1395 {"740", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1396 {"7400", PROCESSOR_PPC7400
, POWERPC_7400_MASK
},
1397 {"7450", PROCESSOR_PPC7450
, POWERPC_7400_MASK
},
1398 {"750", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1399 {"801", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1400 {"821", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1401 {"823", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1402 {"8540", PROCESSOR_PPC8540
, POWERPC_BASE_MASK
| MASK_STRICT_ALIGN
},
1403 /* 8548 has a dummy entry for now. */
1404 {"8548", PROCESSOR_PPC8540
, POWERPC_BASE_MASK
| MASK_STRICT_ALIGN
},
1405 {"860", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1406 {"970", PROCESSOR_POWER4
,
1407 POWERPC_7400_MASK
| MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1408 {"cell", PROCESSOR_CELL
,
1409 POWERPC_7400_MASK
| MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1410 {"common", PROCESSOR_COMMON
, MASK_NEW_MNEMONICS
},
1411 {"ec603e", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1412 {"G3", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1413 {"G4", PROCESSOR_PPC7450
, POWERPC_7400_MASK
},
1414 {"G5", PROCESSOR_POWER4
,
1415 POWERPC_7400_MASK
| MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1416 {"power", PROCESSOR_POWER
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1417 {"power2", PROCESSOR_POWER
,
1418 MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
},
1419 {"power3", PROCESSOR_PPC630
,
1420 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1421 {"power4", PROCESSOR_POWER4
,
1422 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1423 {"power5", PROCESSOR_POWER5
,
1424 POWERPC_BASE_MASK
| MASK_POWERPC64
| MASK_PPC_GFXOPT
1425 | MASK_MFCRF
| MASK_POPCNTB
},
1426 {"power5+", PROCESSOR_POWER5
,
1427 POWERPC_BASE_MASK
| MASK_POWERPC64
| MASK_PPC_GFXOPT
1428 | MASK_MFCRF
| MASK_POPCNTB
| MASK_FPRND
},
1429 {"power6", PROCESSOR_POWER6
,
1430 POWERPC_7400_MASK
| MASK_POWERPC64
| MASK_MFCRF
| MASK_POPCNTB
1431 | MASK_FPRND
| MASK_CMPB
| MASK_DFP
},
1432 {"power6x", PROCESSOR_POWER6
,
1433 POWERPC_7400_MASK
| MASK_POWERPC64
| MASK_MFCRF
| MASK_POPCNTB
1434 | MASK_FPRND
| MASK_CMPB
| MASK_MFPGPR
| MASK_DFP
},
1435 {"powerpc", PROCESSOR_POWERPC
, POWERPC_BASE_MASK
},
1436 {"powerpc64", PROCESSOR_POWERPC64
,
1437 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1438 {"rios", PROCESSOR_RIOS1
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1439 {"rios1", PROCESSOR_RIOS1
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1440 {"rios2", PROCESSOR_RIOS2
,
1441 MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
},
1442 {"rsc", PROCESSOR_PPC601
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1443 {"rsc1", PROCESSOR_PPC601
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1444 {"rs64", PROCESSOR_RS64A
,
1445 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
}
1448 const size_t ptt_size
= ARRAY_SIZE (processor_target_table
);
1450 /* Some OSs don't support saving the high part of 64-bit registers on
1451 context switch. Other OSs don't support saving Altivec registers.
1452 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1453 settings; if the user wants either, the user must explicitly specify
1454 them and we won't interfere with the user's specification. */
1457 POWER_MASKS
= MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
,
1458 POWERPC_MASKS
= (POWERPC_BASE_MASK
| MASK_PPC_GPOPT
| MASK_STRICT_ALIGN
1459 | MASK_PPC_GFXOPT
| MASK_POWERPC64
| MASK_ALTIVEC
1460 | MASK_MFCRF
| MASK_POPCNTB
| MASK_FPRND
| MASK_MULHW
1461 | MASK_DLMZB
| MASK_CMPB
| MASK_MFPGPR
| MASK_DFP
)
1464 rs6000_init_hard_regno_mode_ok ();
1466 set_masks
= POWER_MASKS
| POWERPC_MASKS
| MASK_SOFT_FLOAT
;
1467 #ifdef OS_MISSING_POWERPC64
1468 if (OS_MISSING_POWERPC64
)
1469 set_masks
&= ~MASK_POWERPC64
;
1471 #ifdef OS_MISSING_ALTIVEC
1472 if (OS_MISSING_ALTIVEC
)
1473 set_masks
&= ~MASK_ALTIVEC
;
1476 /* Don't override by the processor default if given explicitly. */
1477 set_masks
&= ~target_flags_explicit
;
1479 /* Identify the processor type. */
1480 rs6000_select
[0].string
= default_cpu
;
1481 rs6000_cpu
= TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
;
1483 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
1485 ptr
= &rs6000_select
[i
];
1486 if (ptr
->string
!= (char *)0 && ptr
->string
[0] != '\0')
1488 for (j
= 0; j
< ptt_size
; j
++)
1489 if (! strcmp (ptr
->string
, processor_target_table
[j
].name
))
1491 if (ptr
->set_tune_p
)
1492 rs6000_cpu
= processor_target_table
[j
].processor
;
1494 if (ptr
->set_arch_p
)
1496 target_flags
&= ~set_masks
;
1497 target_flags
|= (processor_target_table
[j
].target_enable
1504 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
1511 /* If we are optimizing big endian systems for space, use the load/store
1512 multiple and string instructions. */
1513 if (BYTES_BIG_ENDIAN
&& optimize_size
)
1514 target_flags
|= ~target_flags_explicit
& (MASK_MULTIPLE
| MASK_STRING
);
1516 /* Don't allow -mmultiple or -mstring on little endian systems
1517 unless the cpu is a 750, because the hardware doesn't support the
1518 instructions used in little endian mode, and causes an alignment
1519 trap. The 750 does not cause an alignment trap (except when the
1520 target is unaligned). */
1522 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
1524 if (TARGET_MULTIPLE
)
1526 target_flags
&= ~MASK_MULTIPLE
;
1527 if ((target_flags_explicit
& MASK_MULTIPLE
) != 0)
1528 warning (0, "-mmultiple is not supported on little endian systems");
1533 target_flags
&= ~MASK_STRING
;
1534 if ((target_flags_explicit
& MASK_STRING
) != 0)
1535 warning (0, "-mstring is not supported on little endian systems");
1539 /* Set debug flags */
1540 if (rs6000_debug_name
)
1542 if (! strcmp (rs6000_debug_name
, "all"))
1543 rs6000_debug_stack
= rs6000_debug_arg
= 1;
1544 else if (! strcmp (rs6000_debug_name
, "stack"))
1545 rs6000_debug_stack
= 1;
1546 else if (! strcmp (rs6000_debug_name
, "arg"))
1547 rs6000_debug_arg
= 1;
1549 error ("unknown -mdebug-%s switch", rs6000_debug_name
);
1552 if (rs6000_traceback_name
)
1554 if (! strncmp (rs6000_traceback_name
, "full", 4))
1555 rs6000_traceback
= traceback_full
;
1556 else if (! strncmp (rs6000_traceback_name
, "part", 4))
1557 rs6000_traceback
= traceback_part
;
1558 else if (! strncmp (rs6000_traceback_name
, "no", 2))
1559 rs6000_traceback
= traceback_none
;
1561 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1562 rs6000_traceback_name
);
1565 if (!rs6000_explicit_options
.long_double
)
1566 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
1568 #ifndef POWERPC_LINUX
1569 if (!rs6000_explicit_options
.ieee
)
1570 rs6000_ieeequad
= 1;
1573 /* Set Altivec ABI as default for powerpc64 linux. */
1574 if (TARGET_ELF
&& TARGET_64BIT
)
1576 rs6000_altivec_abi
= 1;
1577 TARGET_ALTIVEC_VRSAVE
= 1;
1580 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1581 if (DEFAULT_ABI
== ABI_DARWIN
&& TARGET_64BIT
)
1583 rs6000_darwin64_abi
= 1;
1585 darwin_one_byte_bool
= 1;
1587 /* Default to natural alignment, for better performance. */
1588 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
1591 /* Place FP constants in the constant pool instead of TOC
1592 if section anchors enabled. */
1593 if (flag_section_anchors
)
1594 TARGET_NO_FP_IN_TOC
= 1;
1596 /* Handle -mtls-size option. */
1597 rs6000_parse_tls_size_option ();
1599 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1600 SUBTARGET_OVERRIDE_OPTIONS
;
1602 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1603 SUBSUBTARGET_OVERRIDE_OPTIONS
;
1605 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1606 SUB3TARGET_OVERRIDE_OPTIONS
;
1611 /* The e500 does not have string instructions, and we set
1612 MASK_STRING above when optimizing for size. */
1613 if ((target_flags
& MASK_STRING
) != 0)
1614 target_flags
= target_flags
& ~MASK_STRING
;
1616 else if (rs6000_select
[1].string
!= NULL
)
1618 /* For the powerpc-eabispe configuration, we set all these by
1619 default, so let's unset them if we manually set another
1620 CPU that is not the E500. */
1621 if (!rs6000_explicit_options
.abi
)
1623 if (!rs6000_explicit_options
.spe
)
1625 if (!rs6000_explicit_options
.float_gprs
)
1626 rs6000_float_gprs
= 0;
1627 if (!rs6000_explicit_options
.isel
)
1631 /* Detect invalid option combinations with E500. */
1634 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
1635 && rs6000_cpu
!= PROCESSOR_POWER5
1636 && rs6000_cpu
!= PROCESSOR_POWER6
1637 && rs6000_cpu
!= PROCESSOR_CELL
);
1638 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
1639 || rs6000_cpu
== PROCESSOR_POWER5
);
1640 rs6000_align_branch_targets
= (rs6000_cpu
== PROCESSOR_POWER4
1641 || rs6000_cpu
== PROCESSOR_POWER5
1642 || rs6000_cpu
== PROCESSOR_POWER6
);
1644 rs6000_sched_restricted_insns_priority
1645 = (rs6000_sched_groups
? 1 : 0);
1647 /* Handle -msched-costly-dep option. */
1648 rs6000_sched_costly_dep
1649 = (rs6000_sched_groups
? store_to_load_dep_costly
: no_dep_costly
);
1651 if (rs6000_sched_costly_dep_str
)
1653 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
1654 rs6000_sched_costly_dep
= no_dep_costly
;
1655 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
1656 rs6000_sched_costly_dep
= all_deps_costly
;
1657 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
1658 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
1659 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
1660 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
1662 rs6000_sched_costly_dep
= atoi (rs6000_sched_costly_dep_str
);
1665 /* Handle -minsert-sched-nops option. */
1666 rs6000_sched_insert_nops
1667 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
1669 if (rs6000_sched_insert_nops_str
)
1671 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
1672 rs6000_sched_insert_nops
= sched_finish_none
;
1673 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
1674 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
1675 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
1676 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
1678 rs6000_sched_insert_nops
= atoi (rs6000_sched_insert_nops_str
);
1681 #ifdef TARGET_REGNAMES
1682 /* If the user desires alternate register names, copy in the
1683 alternate names now. */
1684 if (TARGET_REGNAMES
)
1685 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
1688 /* Set aix_struct_return last, after the ABI is determined.
1689 If -maix-struct-return or -msvr4-struct-return was explicitly
1690 used, don't override with the ABI default. */
1691 if (!rs6000_explicit_options
.aix_struct_ret
)
1692 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
1694 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
1695 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
1698 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
1700 /* We can only guarantee the availability of DI pseudo-ops when
1701 assembling for 64-bit targets. */
1704 targetm
.asm_out
.aligned_op
.di
= NULL
;
1705 targetm
.asm_out
.unaligned_op
.di
= NULL
;
1708 /* Set branch target alignment, if not optimizing for size. */
1711 /* Cell wants to be aligned 8byte for dual issue. */
1712 if (rs6000_cpu
== PROCESSOR_CELL
)
1714 if (align_functions
<= 0)
1715 align_functions
= 8;
1716 if (align_jumps
<= 0)
1718 if (align_loops
<= 0)
1721 if (rs6000_align_branch_targets
)
1723 if (align_functions
<= 0)
1724 align_functions
= 16;
1725 if (align_jumps
<= 0)
1727 if (align_loops
<= 0)
1730 if (align_jumps_max_skip
<= 0)
1731 align_jumps_max_skip
= 15;
1732 if (align_loops_max_skip
<= 0)
1733 align_loops_max_skip
= 15;
1736 /* Arrange to save and restore machine status around nested functions. */
1737 init_machine_status
= rs6000_init_machine_status
;
1739 /* We should always be splitting complex arguments, but we can't break
1740 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1741 if (DEFAULT_ABI
!= ABI_AIX
)
1742 targetm
.calls
.split_complex_arg
= NULL
;
1744 /* Initialize rs6000_cost with the appropriate target costs. */
1746 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
1750 case PROCESSOR_RIOS1
:
1751 rs6000_cost
= &rios1_cost
;
1754 case PROCESSOR_RIOS2
:
1755 rs6000_cost
= &rios2_cost
;
1758 case PROCESSOR_RS64A
:
1759 rs6000_cost
= &rs64a_cost
;
1762 case PROCESSOR_MPCCORE
:
1763 rs6000_cost
= &mpccore_cost
;
1766 case PROCESSOR_PPC403
:
1767 rs6000_cost
= &ppc403_cost
;
1770 case PROCESSOR_PPC405
:
1771 rs6000_cost
= &ppc405_cost
;
1774 case PROCESSOR_PPC440
:
1775 rs6000_cost
= &ppc440_cost
;
1778 case PROCESSOR_PPC601
:
1779 rs6000_cost
= &ppc601_cost
;
1782 case PROCESSOR_PPC603
:
1783 rs6000_cost
= &ppc603_cost
;
1786 case PROCESSOR_PPC604
:
1787 rs6000_cost
= &ppc604_cost
;
1790 case PROCESSOR_PPC604e
:
1791 rs6000_cost
= &ppc604e_cost
;
1794 case PROCESSOR_PPC620
:
1795 rs6000_cost
= &ppc620_cost
;
1798 case PROCESSOR_PPC630
:
1799 rs6000_cost
= &ppc630_cost
;
1802 case PROCESSOR_CELL
:
1803 rs6000_cost
= &ppccell_cost
;
1806 case PROCESSOR_PPC750
:
1807 case PROCESSOR_PPC7400
:
1808 rs6000_cost
= &ppc750_cost
;
1811 case PROCESSOR_PPC7450
:
1812 rs6000_cost
= &ppc7450_cost
;
1815 case PROCESSOR_PPC8540
:
1816 rs6000_cost
= &ppc8540_cost
;
1819 case PROCESSOR_POWER4
:
1820 case PROCESSOR_POWER5
:
1821 rs6000_cost
= &power4_cost
;
1824 case PROCESSOR_POWER6
:
1825 rs6000_cost
= &power6_cost
;
1832 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES
))
1833 set_param_value ("simultaneous-prefetches",
1834 rs6000_cost
->simultaneous_prefetches
);
1835 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE
))
1836 set_param_value ("l1-cache-size", rs6000_cost
->l1_cache_size
);
1837 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE
))
1838 set_param_value ("l1-cache-line-size", rs6000_cost
->cache_line_size
);
1839 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE
))
1840 set_param_value ("l2-cache-size", rs6000_cost
->l2_cache_size
);
1843 /* Implement targetm.vectorize.builtin_mask_for_load. */
1845 rs6000_builtin_mask_for_load (void)
1848 return altivec_builtin_mask_for_load
;
1853 /* Implement targetm.vectorize.builtin_conversion. */
1855 rs6000_builtin_conversion (enum tree_code code
, tree type
)
1857 if (!TARGET_ALTIVEC
)
1863 switch (TYPE_MODE (type
))
1866 return TYPE_UNSIGNED (type
) ?
1867 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VCFUX
] :
1868 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VCFSX
];
1877 /* Implement targetm.vectorize.builtin_mul_widen_even. */
1879 rs6000_builtin_mul_widen_even (tree type
)
1881 if (!TARGET_ALTIVEC
)
1884 switch (TYPE_MODE (type
))
1887 return TYPE_UNSIGNED (type
) ?
1888 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULEUH
] :
1889 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULESH
];
1892 return TYPE_UNSIGNED (type
) ?
1893 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULEUB
] :
1894 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULESB
];
1900 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
1902 rs6000_builtin_mul_widen_odd (tree type
)
1904 if (!TARGET_ALTIVEC
)
1907 switch (TYPE_MODE (type
))
1910 return TYPE_UNSIGNED (type
) ?
1911 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOUH
] :
1912 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOSH
];
1915 return TYPE_UNSIGNED (type
) ?
1916 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOUB
] :
1917 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOSB
];
1924 /* Return true iff, data reference of TYPE can reach vector alignment (16)
1925 after applying N number of iterations. This routine does not determine
1926 how may iterations are required to reach desired alignment. */
1929 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
1936 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
1939 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
1949 /* Assuming that all other types are naturally aligned. CHECKME! */
1954 /* Handle generic options of the form -mfoo=yes/no.
1955 NAME is the option name.
1956 VALUE is the option value.
1957 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1958 whether the option value is 'yes' or 'no' respectively. */
1960 rs6000_parse_yes_no_option (const char *name
, const char *value
, int *flag
)
1964 else if (!strcmp (value
, "yes"))
1966 else if (!strcmp (value
, "no"))
1969 error ("unknown -m%s= option specified: '%s'", name
, value
);
1972 /* Validate and record the size specified with the -mtls-size option. */
1975 rs6000_parse_tls_size_option (void)
1977 if (rs6000_tls_size_string
== 0)
1979 else if (strcmp (rs6000_tls_size_string
, "16") == 0)
1980 rs6000_tls_size
= 16;
1981 else if (strcmp (rs6000_tls_size_string
, "32") == 0)
1982 rs6000_tls_size
= 32;
1983 else if (strcmp (rs6000_tls_size_string
, "64") == 0)
1984 rs6000_tls_size
= 64;
1986 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string
);
1990 optimization_options (int level ATTRIBUTE_UNUSED
, int size ATTRIBUTE_UNUSED
)
1992 if (DEFAULT_ABI
== ABI_DARWIN
)
1993 /* The Darwin libraries never set errno, so we might as well
1994 avoid calling them when that's the only reason we would. */
1995 flag_errno_math
= 0;
1997 /* Double growth factor to counter reduced min jump length. */
1998 set_param_value ("max-grow-copy-bb-insns", 16);
2000 /* Enable section anchors by default.
2001 Skip section anchors for Objective C and Objective C++
2002 until front-ends fixed. */
2003 if (!TARGET_MACHO
&& lang_hooks
.name
[4] != 'O')
2004 flag_section_anchors
= 1;
2007 /* Implement TARGET_HANDLE_OPTION. */
2010 rs6000_handle_option (size_t code
, const char *arg
, int value
)
2015 target_flags
&= ~(MASK_POWER
| MASK_POWER2
2016 | MASK_MULTIPLE
| MASK_STRING
);
2017 target_flags_explicit
|= (MASK_POWER
| MASK_POWER2
2018 | MASK_MULTIPLE
| MASK_STRING
);
2020 case OPT_mno_powerpc
:
2021 target_flags
&= ~(MASK_POWERPC
| MASK_PPC_GPOPT
2022 | MASK_PPC_GFXOPT
| MASK_POWERPC64
);
2023 target_flags_explicit
|= (MASK_POWERPC
| MASK_PPC_GPOPT
2024 | MASK_PPC_GFXOPT
| MASK_POWERPC64
);
2027 target_flags
&= ~MASK_MINIMAL_TOC
;
2028 TARGET_NO_FP_IN_TOC
= 0;
2029 TARGET_NO_SUM_IN_TOC
= 0;
2030 target_flags_explicit
|= MASK_MINIMAL_TOC
;
2031 #ifdef TARGET_USES_SYSV4_OPT
2032 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
2033 just the same as -mminimal-toc. */
2034 target_flags
|= MASK_MINIMAL_TOC
;
2035 target_flags_explicit
|= MASK_MINIMAL_TOC
;
2039 #ifdef TARGET_USES_SYSV4_OPT
2041 /* Make -mtoc behave like -mminimal-toc. */
2042 target_flags
|= MASK_MINIMAL_TOC
;
2043 target_flags_explicit
|= MASK_MINIMAL_TOC
;
2047 #ifdef TARGET_USES_AIX64_OPT
2052 target_flags
|= MASK_POWERPC64
| MASK_POWERPC
;
2053 target_flags
|= ~target_flags_explicit
& MASK_PPC_GFXOPT
;
2054 target_flags_explicit
|= MASK_POWERPC64
| MASK_POWERPC
;
2057 #ifdef TARGET_USES_AIX64_OPT
2062 target_flags
&= ~MASK_POWERPC64
;
2063 target_flags_explicit
|= MASK_POWERPC64
;
2066 case OPT_minsert_sched_nops_
:
2067 rs6000_sched_insert_nops_str
= arg
;
2070 case OPT_mminimal_toc
:
2073 TARGET_NO_FP_IN_TOC
= 0;
2074 TARGET_NO_SUM_IN_TOC
= 0;
2081 target_flags
|= (MASK_MULTIPLE
| MASK_STRING
);
2082 target_flags_explicit
|= (MASK_MULTIPLE
| MASK_STRING
);
2089 target_flags
|= (MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
);
2090 target_flags_explicit
|= (MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
);
2094 case OPT_mpowerpc_gpopt
:
2095 case OPT_mpowerpc_gfxopt
:
2098 target_flags
|= MASK_POWERPC
;
2099 target_flags_explicit
|= MASK_POWERPC
;
2103 case OPT_maix_struct_return
:
2104 case OPT_msvr4_struct_return
:
2105 rs6000_explicit_options
.aix_struct_ret
= true;
2109 rs6000_parse_yes_no_option ("vrsave", arg
, &(TARGET_ALTIVEC_VRSAVE
));
2113 rs6000_explicit_options
.isel
= true;
2114 rs6000_parse_yes_no_option ("isel", arg
, &(rs6000_isel
));
2118 rs6000_explicit_options
.spe
= true;
2119 rs6000_parse_yes_no_option ("spe", arg
, &(rs6000_spe
));
2123 rs6000_debug_name
= arg
;
2126 #ifdef TARGET_USES_SYSV4_OPT
2128 rs6000_abi_name
= arg
;
2132 rs6000_sdata_name
= arg
;
2135 case OPT_mtls_size_
:
2136 rs6000_tls_size_string
= arg
;
2139 case OPT_mrelocatable
:
2142 target_flags
|= MASK_MINIMAL_TOC
;
2143 target_flags_explicit
|= MASK_MINIMAL_TOC
;
2144 TARGET_NO_FP_IN_TOC
= 1;
2148 case OPT_mrelocatable_lib
:
2151 target_flags
|= MASK_RELOCATABLE
| MASK_MINIMAL_TOC
;
2152 target_flags_explicit
|= MASK_RELOCATABLE
| MASK_MINIMAL_TOC
;
2153 TARGET_NO_FP_IN_TOC
= 1;
2157 target_flags
&= ~MASK_RELOCATABLE
;
2158 target_flags_explicit
|= MASK_RELOCATABLE
;
2164 if (!strcmp (arg
, "altivec"))
2166 rs6000_explicit_options
.abi
= true;
2167 rs6000_altivec_abi
= 1;
2170 else if (! strcmp (arg
, "no-altivec"))
2172 /* ??? Don't set rs6000_explicit_options.abi here, to allow
2173 the default for rs6000_spe_abi to be chosen later. */
2174 rs6000_altivec_abi
= 0;
2176 else if (! strcmp (arg
, "spe"))
2178 rs6000_explicit_options
.abi
= true;
2180 rs6000_altivec_abi
= 0;
2181 if (!TARGET_SPE_ABI
)
2182 error ("not configured for ABI: '%s'", arg
);
2184 else if (! strcmp (arg
, "no-spe"))
2186 rs6000_explicit_options
.abi
= true;
2190 /* These are here for testing during development only, do not
2191 document in the manual please. */
2192 else if (! strcmp (arg
, "d64"))
2194 rs6000_darwin64_abi
= 1;
2195 warning (0, "Using darwin64 ABI");
2197 else if (! strcmp (arg
, "d32"))
2199 rs6000_darwin64_abi
= 0;
2200 warning (0, "Using old darwin ABI");
2203 else if (! strcmp (arg
, "ibmlongdouble"))
2205 rs6000_explicit_options
.ieee
= true;
2206 rs6000_ieeequad
= 0;
2207 warning (0, "Using IBM extended precision long double");
2209 else if (! strcmp (arg
, "ieeelongdouble"))
2211 rs6000_explicit_options
.ieee
= true;
2212 rs6000_ieeequad
= 1;
2213 warning (0, "Using IEEE extended precision long double");
2218 error ("unknown ABI specified: '%s'", arg
);
2224 rs6000_select
[1].string
= arg
;
2228 rs6000_select
[2].string
= arg
;
2231 case OPT_mtraceback_
:
2232 rs6000_traceback_name
= arg
;
2235 case OPT_mfloat_gprs_
:
2236 rs6000_explicit_options
.float_gprs
= true;
2237 if (! strcmp (arg
, "yes") || ! strcmp (arg
, "single"))
2238 rs6000_float_gprs
= 1;
2239 else if (! strcmp (arg
, "double"))
2240 rs6000_float_gprs
= 2;
2241 else if (! strcmp (arg
, "no"))
2242 rs6000_float_gprs
= 0;
2245 error ("invalid option for -mfloat-gprs: '%s'", arg
);
2250 case OPT_mlong_double_
:
2251 rs6000_explicit_options
.long_double
= true;
2252 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
2253 if (value
!= 64 && value
!= 128)
2255 error ("Unknown switch -mlong-double-%s", arg
);
2256 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
2260 rs6000_long_double_type_size
= value
;
2263 case OPT_msched_costly_dep_
:
2264 rs6000_sched_costly_dep_str
= arg
;
2268 rs6000_explicit_options
.alignment
= true;
2269 if (! strcmp (arg
, "power"))
2271 /* On 64-bit Darwin, power alignment is ABI-incompatible with
2272 some C library functions, so warn about it. The flag may be
2273 useful for performance studies from time to time though, so
2274 don't disable it entirely. */
2275 if (DEFAULT_ABI
== ABI_DARWIN
&& TARGET_64BIT
)
2276 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2277 " it is incompatible with the installed C and C++ libraries");
2278 rs6000_alignment_flags
= MASK_ALIGN_POWER
;
2280 else if (! strcmp (arg
, "natural"))
2281 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
2284 error ("unknown -malign-XXXXX option specified: '%s'", arg
);
2292 /* Do anything needed at the start of the asm file. */
2295 rs6000_file_start (void)
2299 const char *start
= buffer
;
2300 struct rs6000_cpu_select
*ptr
;
2301 const char *default_cpu
= TARGET_CPU_DEFAULT
;
2302 FILE *file
= asm_out_file
;
2304 default_file_start ();
2306 #ifdef TARGET_BI_ARCH
2307 if ((TARGET_DEFAULT
^ target_flags
) & MASK_64BIT
)
2311 if (flag_verbose_asm
)
2313 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
2314 rs6000_select
[0].string
= default_cpu
;
2316 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
2318 ptr
= &rs6000_select
[i
];
2319 if (ptr
->string
!= (char *)0 && ptr
->string
[0] != '\0')
2321 fprintf (file
, "%s %s%s", start
, ptr
->name
, ptr
->string
);
2326 if (PPC405_ERRATUM77
)
2328 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
2332 #ifdef USING_ELFOS_H
2333 switch (rs6000_sdata
)
2335 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
2336 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
2337 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
2338 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
2341 if (rs6000_sdata
&& g_switch_value
)
2343 fprintf (file
, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED
, start
,
2353 #ifdef HAVE_AS_GNU_ATTRIBUTE
2354 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
2356 fprintf (file
, "\t.gnu_attribute 4, %d\n",
2357 (TARGET_HARD_FLOAT
&& TARGET_FPRS
) ? 1 : 2);
2358 fprintf (file
, "\t.gnu_attribute 8, %d\n",
2359 (TARGET_ALTIVEC_ABI
? 2
2360 : TARGET_SPE_ABI
? 3
2365 if (DEFAULT_ABI
== ABI_AIX
|| (TARGET_ELF
&& flag_pic
== 2))
2367 switch_to_section (toc_section
);
2368 switch_to_section (text_section
);
2373 /* Return nonzero if this function is known to have a null epilogue. */
2376 direct_return (void)
2378 if (reload_completed
)
2380 rs6000_stack_t
*info
= rs6000_stack_info ();
2382 if (info
->first_gp_reg_save
== 32
2383 && info
->first_fp_reg_save
== 64
2384 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
2385 && ! info
->lr_save_p
2386 && ! info
->cr_save_p
2387 && info
->vrsave_mask
== 0
2395 /* Return the number of instructions it takes to form a constant in an
2396 integer register. */
2399 num_insns_constant_wide (HOST_WIDE_INT value
)
2401 /* signed constant loadable with {cal|addi} */
2402 if ((unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000)
2405 /* constant loadable with {cau|addis} */
2406 else if ((value
& 0xffff) == 0
2407 && (value
>> 31 == -1 || value
>> 31 == 0))
2410 #if HOST_BITS_PER_WIDE_INT == 64
2411 else if (TARGET_POWERPC64
)
2413 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2414 HOST_WIDE_INT high
= value
>> 31;
2416 if (high
== 0 || high
== -1)
2422 return num_insns_constant_wide (high
) + 1;
2424 return (num_insns_constant_wide (high
)
2425 + num_insns_constant_wide (low
) + 1);
2434 num_insns_constant (rtx op
, enum machine_mode mode
)
2436 HOST_WIDE_INT low
, high
;
2438 switch (GET_CODE (op
))
2441 #if HOST_BITS_PER_WIDE_INT == 64
2442 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
2443 && mask64_operand (op
, mode
))
2447 return num_insns_constant_wide (INTVAL (op
));
2455 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2456 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
2457 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
2460 if (mode
== VOIDmode
|| mode
== DImode
)
2462 high
= CONST_DOUBLE_HIGH (op
);
2463 low
= CONST_DOUBLE_LOW (op
);
2470 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2471 if (DECIMAL_FLOAT_MODE_P (mode
))
2472 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, l
);
2474 REAL_VALUE_TO_TARGET_DOUBLE (rv
, l
);
2475 high
= l
[WORDS_BIG_ENDIAN
== 0];
2476 low
= l
[WORDS_BIG_ENDIAN
!= 0];
2480 return (num_insns_constant_wide (low
)
2481 + num_insns_constant_wide (high
));
2484 if ((high
== 0 && low
>= 0)
2485 || (high
== -1 && low
< 0))
2486 return num_insns_constant_wide (low
);
2488 else if (mask64_operand (op
, mode
))
2492 return num_insns_constant_wide (high
) + 1;
2495 return (num_insns_constant_wide (high
)
2496 + num_insns_constant_wide (low
) + 1);
2504 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
2505 If the mode of OP is MODE_VECTOR_INT, this simply returns the
2506 corresponding element of the vector, but for V4SFmode and V2SFmode,
2507 the corresponding "float" is interpreted as an SImode integer. */
2509 static HOST_WIDE_INT
2510 const_vector_elt_as_int (rtx op
, unsigned int elt
)
2512 rtx tmp
= CONST_VECTOR_ELT (op
, elt
);
2513 if (GET_MODE (op
) == V4SFmode
2514 || GET_MODE (op
) == V2SFmode
)
2515 tmp
= gen_lowpart (SImode
, tmp
);
2516 return INTVAL (tmp
);
2519 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2520 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2521 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2522 all items are set to the same value and contain COPIES replicas of the
2523 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2524 operand and the others are set to the value of the operand's msb. */
2527 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
2529 enum machine_mode mode
= GET_MODE (op
);
2530 enum machine_mode inner
= GET_MODE_INNER (mode
);
2533 unsigned nunits
= GET_MODE_NUNITS (mode
);
2534 unsigned bitsize
= GET_MODE_BITSIZE (inner
);
2535 unsigned mask
= GET_MODE_MASK (inner
);
2537 HOST_WIDE_INT val
= const_vector_elt_as_int (op
, nunits
- 1);
2538 HOST_WIDE_INT splat_val
= val
;
2539 HOST_WIDE_INT msb_val
= val
> 0 ? 0 : -1;
2541 /* Construct the value to be splatted, if possible. If not, return 0. */
2542 for (i
= 2; i
<= copies
; i
*= 2)
2544 HOST_WIDE_INT small_val
;
2546 small_val
= splat_val
>> bitsize
;
2548 if (splat_val
!= ((small_val
<< bitsize
) | (small_val
& mask
)))
2550 splat_val
= small_val
;
2553 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2554 if (EASY_VECTOR_15 (splat_val
))
2557 /* Also check if we can splat, and then add the result to itself. Do so if
2558 the value is positive, of if the splat instruction is using OP's mode;
2559 for splat_val < 0, the splat and the add should use the same mode. */
2560 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
2561 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
2567 /* Check if VAL is present in every STEP-th element, and the
2568 other elements are filled with its most significant bit. */
2569 for (i
= 0; i
< nunits
- 1; ++i
)
2571 HOST_WIDE_INT desired_val
;
2572 if (((i
+ 1) & (step
- 1)) == 0)
2575 desired_val
= msb_val
;
2577 if (desired_val
!= const_vector_elt_as_int (op
, i
))
2585 /* Return true if OP is of the given MODE and can be synthesized
2586 with a vspltisb, vspltish or vspltisw. */
2589 easy_altivec_constant (rtx op
, enum machine_mode mode
)
2591 unsigned step
, copies
;
2593 if (mode
== VOIDmode
)
2594 mode
= GET_MODE (op
);
2595 else if (mode
!= GET_MODE (op
))
2598 /* Start with a vspltisw. */
2599 step
= GET_MODE_NUNITS (mode
) / 4;
2602 if (vspltis_constant (op
, step
, copies
))
2605 /* Then try with a vspltish. */
2611 if (vspltis_constant (op
, step
, copies
))
2614 /* And finally a vspltisb. */
2620 if (vspltis_constant (op
, step
, copies
))
2626 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2627 result is OP. Abort if it is not possible. */
2630 gen_easy_altivec_constant (rtx op
)
2632 enum machine_mode mode
= GET_MODE (op
);
2633 int nunits
= GET_MODE_NUNITS (mode
);
2634 rtx last
= CONST_VECTOR_ELT (op
, nunits
- 1);
2635 unsigned step
= nunits
/ 4;
2636 unsigned copies
= 1;
2638 /* Start with a vspltisw. */
2639 if (vspltis_constant (op
, step
, copies
))
2640 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, last
));
2642 /* Then try with a vspltish. */
2648 if (vspltis_constant (op
, step
, copies
))
2649 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, last
));
2651 /* And finally a vspltisb. */
2657 if (vspltis_constant (op
, step
, copies
))
2658 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, last
));
2664 output_vec_const_move (rtx
*operands
)
2667 enum machine_mode mode
;
2672 mode
= GET_MODE (dest
);
2677 if (zero_constant (vec
, mode
))
2678 return "vxor %0,%0,%0";
2680 splat_vec
= gen_easy_altivec_constant (vec
);
2681 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
2682 operands
[1] = XEXP (splat_vec
, 0);
2683 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
2686 switch (GET_MODE (splat_vec
))
2689 return "vspltisw %0,%1";
2692 return "vspltish %0,%1";
2695 return "vspltisb %0,%1";
2702 gcc_assert (TARGET_SPE
);
2704 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2705 pattern of V1DI, V4HI, and V2SF.
2707 FIXME: We should probably return # and add post reload
2708 splitters for these, but this way is so easy ;-). */
2709 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
2710 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
2711 operands
[1] = CONST_VECTOR_ELT (vec
, 0);
2712 operands
[2] = CONST_VECTOR_ELT (vec
, 1);
2714 return "li %0,%1\n\tevmergelo %0,%0,%0";
2716 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2719 /* Initialize vector TARGET to VALS. */
2722 rs6000_expand_vector_init (rtx target
, rtx vals
)
2724 enum machine_mode mode
= GET_MODE (target
);
2725 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
2726 int n_elts
= GET_MODE_NUNITS (mode
);
2727 int n_var
= 0, one_var
= -1;
2728 bool all_same
= true, all_const_zero
= true;
2732 for (i
= 0; i
< n_elts
; ++i
)
2734 x
= XVECEXP (vals
, 0, i
);
2735 if (!CONSTANT_P (x
))
2736 ++n_var
, one_var
= i
;
2737 else if (x
!= CONST0_RTX (inner_mode
))
2738 all_const_zero
= false;
2740 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
2746 if (mode
!= V4SFmode
&& all_const_zero
)
2748 /* Zero register. */
2749 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2750 gen_rtx_XOR (mode
, target
, target
)));
2753 else if (mode
!= V4SFmode
&& easy_vector_constant (vals
, mode
))
2755 /* Splat immediate. */
2756 emit_insn (gen_rtx_SET (VOIDmode
, target
, vals
));
2760 ; /* Splat vector element. */
2763 /* Load from constant pool. */
2764 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
2769 /* Store value to stack temp. Load vector element. Splat. */
2772 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
), 0);
2773 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
2774 XVECEXP (vals
, 0, 0));
2775 x
= gen_rtx_UNSPEC (VOIDmode
,
2776 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
2777 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
2779 gen_rtx_SET (VOIDmode
,
2782 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
2783 gen_rtx_PARALLEL (VOIDmode
,
2784 gen_rtvec (1, const0_rtx
)));
2785 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2786 gen_rtx_VEC_DUPLICATE (mode
, x
)));
2790 /* One field is non-constant. Load constant then overwrite
2794 rtx copy
= copy_rtx (vals
);
2796 /* Load constant part of vector, substitute neighboring value for
2798 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
2799 rs6000_expand_vector_init (target
, copy
);
2801 /* Insert variable. */
2802 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
2806 /* Construct the vector in memory one field at a time
2807 and load the whole vector. */
2808 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
), 0);
2809 for (i
= 0; i
< n_elts
; i
++)
2810 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
2811 i
* GET_MODE_SIZE (inner_mode
)),
2812 XVECEXP (vals
, 0, i
));
2813 emit_move_insn (target
, mem
);
2816 /* Set field ELT of TARGET to VAL. */
2819 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
2821 enum machine_mode mode
= GET_MODE (target
);
2822 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
2823 rtx reg
= gen_reg_rtx (mode
);
2825 int width
= GET_MODE_SIZE (inner_mode
);
2828 /* Load single variable value. */
2829 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
), 0);
2830 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
2831 x
= gen_rtx_UNSPEC (VOIDmode
,
2832 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
2833 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
2835 gen_rtx_SET (VOIDmode
,
2839 /* Linear sequence. */
2840 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
2841 for (i
= 0; i
< 16; ++i
)
2842 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
2844 /* Set permute mask to insert element into target. */
2845 for (i
= 0; i
< width
; ++i
)
2846 XVECEXP (mask
, 0, elt
*width
+ i
)
2847 = GEN_INT (i
+ 0x10);
2848 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
2849 x
= gen_rtx_UNSPEC (mode
,
2850 gen_rtvec (3, target
, reg
,
2851 force_reg (V16QImode
, x
)),
2853 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
2856 /* Extract field ELT from VEC into TARGET. */
2859 rs6000_expand_vector_extract (rtx target
, rtx vec
, int elt
)
2861 enum machine_mode mode
= GET_MODE (vec
);
2862 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
2865 /* Allocate mode-sized buffer. */
2866 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
), 0);
2868 /* Add offset to field within buffer matching vector element. */
2869 mem
= adjust_address_nv (mem
, mode
, elt
* GET_MODE_SIZE (inner_mode
));
2871 /* Store single field into mode-sized buffer. */
2872 x
= gen_rtx_UNSPEC (VOIDmode
,
2873 gen_rtvec (1, const0_rtx
), UNSPEC_STVE
);
2874 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
2876 gen_rtx_SET (VOIDmode
,
2879 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
2882 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2883 implement ANDing by the mask IN. */
2885 build_mask64_2_operands (rtx in
, rtx
*out
)
2887 #if HOST_BITS_PER_WIDE_INT >= 64
2888 unsigned HOST_WIDE_INT c
, lsb
, m1
, m2
;
2891 gcc_assert (GET_CODE (in
) == CONST_INT
);
2896 /* Assume c initially something like 0x00fff000000fffff. The idea
2897 is to rotate the word so that the middle ^^^^^^ group of zeros
2898 is at the MS end and can be cleared with an rldicl mask. We then
2899 rotate back and clear off the MS ^^ group of zeros with a
2901 c
= ~c
; /* c == 0xff000ffffff00000 */
2902 lsb
= c
& -c
; /* lsb == 0x0000000000100000 */
2903 m1
= -lsb
; /* m1 == 0xfffffffffff00000 */
2904 c
= ~c
; /* c == 0x00fff000000fffff */
2905 c
&= -lsb
; /* c == 0x00fff00000000000 */
2906 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
2907 c
= ~c
; /* c == 0xff000fffffffffff */
2908 c
&= -lsb
; /* c == 0xff00000000000000 */
2910 while ((lsb
>>= 1) != 0)
2911 shift
++; /* shift == 44 on exit from loop */
2912 m1
<<= 64 - shift
; /* m1 == 0xffffff0000000000 */
2913 m1
= ~m1
; /* m1 == 0x000000ffffffffff */
2914 m2
= ~c
; /* m2 == 0x00ffffffffffffff */
2918 /* Assume c initially something like 0xff000f0000000000. The idea
2919 is to rotate the word so that the ^^^ middle group of zeros
2920 is at the LS end and can be cleared with an rldicr mask. We then
2921 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2923 lsb
= c
& -c
; /* lsb == 0x0000010000000000 */
2924 m2
= -lsb
; /* m2 == 0xffffff0000000000 */
2925 c
= ~c
; /* c == 0x00fff0ffffffffff */
2926 c
&= -lsb
; /* c == 0x00fff00000000000 */
2927 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
2928 c
= ~c
; /* c == 0xff000fffffffffff */
2929 c
&= -lsb
; /* c == 0xff00000000000000 */
2931 while ((lsb
>>= 1) != 0)
2932 shift
++; /* shift == 44 on exit from loop */
2933 m1
= ~c
; /* m1 == 0x00ffffffffffffff */
2934 m1
>>= shift
; /* m1 == 0x0000000000000fff */
2935 m1
= ~m1
; /* m1 == 0xfffffffffffff000 */
2938 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2939 masks will be all 1's. We are guaranteed more than one transition. */
2940 out
[0] = GEN_INT (64 - shift
);
2941 out
[1] = GEN_INT (m1
);
2942 out
[2] = GEN_INT (shift
);
2943 out
[3] = GEN_INT (m2
);
2951 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2954 invalid_e500_subreg (rtx op
, enum machine_mode mode
)
2956 if (TARGET_E500_DOUBLE
)
2958 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
2959 subreg:TI and reg:TF. */
2960 if (GET_CODE (op
) == SUBREG
2961 && (mode
== SImode
|| mode
== DImode
|| mode
== TImode
)
2962 && REG_P (SUBREG_REG (op
))
2963 && (GET_MODE (SUBREG_REG (op
)) == DFmode
2964 || GET_MODE (SUBREG_REG (op
)) == TFmode
))
2967 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
2969 if (GET_CODE (op
) == SUBREG
2970 && (mode
== DFmode
|| mode
== TFmode
)
2971 && REG_P (SUBREG_REG (op
))
2972 && (GET_MODE (SUBREG_REG (op
)) == DImode
2973 || GET_MODE (SUBREG_REG (op
)) == TImode
))
2978 && GET_CODE (op
) == SUBREG
2980 && REG_P (SUBREG_REG (op
))
2981 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op
))))
2987 /* AIX increases natural record alignment to doubleword if the first
2988 field is an FP double while the FP fields remain word aligned. */
2991 rs6000_special_round_type_align (tree type
, unsigned int computed
,
2992 unsigned int specified
)
2994 unsigned int align
= MAX (computed
, specified
);
2995 tree field
= TYPE_FIELDS (type
);
2997 /* Skip all non field decls */
2998 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
2999 field
= TREE_CHAIN (field
);
3001 if (field
!= NULL
&& field
!= type
)
3003 type
= TREE_TYPE (field
);
3004 while (TREE_CODE (type
) == ARRAY_TYPE
)
3005 type
= TREE_TYPE (type
);
3007 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
3008 align
= MAX (align
, 64);
3014 /* Darwin increases record alignment to the natural alignment of
3018 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
3019 unsigned int specified
)
3021 unsigned int align
= MAX (computed
, specified
);
3023 if (TYPE_PACKED (type
))
3026 /* Find the first field, looking down into aggregates. */
3028 tree field
= TYPE_FIELDS (type
);
3029 /* Skip all non field decls */
3030 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
3031 field
= TREE_CHAIN (field
);
3034 type
= TREE_TYPE (field
);
3035 while (TREE_CODE (type
) == ARRAY_TYPE
)
3036 type
= TREE_TYPE (type
);
3037 } while (AGGREGATE_TYPE_P (type
));
3039 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
3040 align
= MAX (align
, TYPE_ALIGN (type
));
3045 /* Return 1 for an operand in small memory on V.4/eabi. */
3048 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
3049 enum machine_mode mode ATTRIBUTE_UNUSED
)
3054 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
3057 if (DEFAULT_ABI
!= ABI_V4
)
3060 if (GET_CODE (op
) == SYMBOL_REF
)
3063 else if (GET_CODE (op
) != CONST
3064 || GET_CODE (XEXP (op
, 0)) != PLUS
3065 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
3066 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
3071 rtx sum
= XEXP (op
, 0);
3072 HOST_WIDE_INT summand
;
3074 /* We have to be careful here, because it is the referenced address
3075 that must be 32k from _SDA_BASE_, not just the symbol. */
3076 summand
= INTVAL (XEXP (sum
, 1));
3077 if (summand
< 0 || (unsigned HOST_WIDE_INT
) summand
> g_switch_value
)
3080 sym_ref
= XEXP (sum
, 0);
3083 return SYMBOL_REF_SMALL_P (sym_ref
);
3089 /* Return true if either operand is a general purpose register. */
3092 gpr_or_gpr_p (rtx op0
, rtx op1
)
3094 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
3095 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
3099 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
3102 constant_pool_expr_1 (rtx op
, int *have_sym
, int *have_toc
)
3104 switch (GET_CODE (op
))
3107 if (RS6000_SYMBOL_REF_TLS_P (op
))
3109 else if (CONSTANT_POOL_ADDRESS_P (op
))
3111 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op
), Pmode
))
3119 else if (! strcmp (XSTR (op
, 0), toc_label_name
))
3128 return (constant_pool_expr_1 (XEXP (op
, 0), have_sym
, have_toc
)
3129 && constant_pool_expr_1 (XEXP (op
, 1), have_sym
, have_toc
));
3131 return constant_pool_expr_1 (XEXP (op
, 0), have_sym
, have_toc
);
3140 constant_pool_expr_p (rtx op
)
3144 return constant_pool_expr_1 (op
, &have_sym
, &have_toc
) && have_sym
;
3148 toc_relative_expr_p (rtx op
)
3152 return constant_pool_expr_1 (op
, &have_sym
, &have_toc
) && have_toc
;
3156 legitimate_constant_pool_address_p (rtx x
)
3159 && GET_CODE (x
) == PLUS
3160 && GET_CODE (XEXP (x
, 0)) == REG
3161 && (TARGET_MINIMAL_TOC
|| REGNO (XEXP (x
, 0)) == TOC_REGISTER
)
3162 && constant_pool_expr_p (XEXP (x
, 1)));
3166 legitimate_small_data_p (enum machine_mode mode
, rtx x
)
3168 return (DEFAULT_ABI
== ABI_V4
3169 && !flag_pic
&& !TARGET_TOC
3170 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
3171 && small_data_operand (x
, mode
));
3174 /* SPE offset addressing is limited to 5-bits worth of double words. */
3175 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3178 rs6000_legitimate_offset_address_p (enum machine_mode mode
, rtx x
, int strict
)
3180 unsigned HOST_WIDE_INT offset
, extra
;
3182 if (GET_CODE (x
) != PLUS
)
3184 if (GET_CODE (XEXP (x
, 0)) != REG
)
3186 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
3188 if (legitimate_constant_pool_address_p (x
))
3190 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3193 offset
= INTVAL (XEXP (x
, 1));
3201 /* AltiVec vector modes. Only reg+reg addressing is valid and
3202 constant offset zero should not occur due to canonicalization.
3203 Allow any offset when not strict before reload. */
3210 /* Paired vector modes. Only reg+reg addressing is valid and
3211 constant offset zero should not occur due to canonicalization.
3212 Allow any offset when not strict before reload. */
3213 if (TARGET_PAIRED_FLOAT
)
3215 /* SPE vector modes. */
3216 return SPE_CONST_OFFSET_OK (offset
);
3220 if (TARGET_E500_DOUBLE
)
3221 return SPE_CONST_OFFSET_OK (offset
);
3224 /* On e500v2, we may have:
3226 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
3228 Which gets addressed with evldd instructions. */
3229 if (TARGET_E500_DOUBLE
)
3230 return SPE_CONST_OFFSET_OK (offset
);
3232 if (mode
== DFmode
|| mode
== DDmode
|| !TARGET_POWERPC64
)
3234 else if (offset
& 3)
3239 if (TARGET_E500_DOUBLE
)
3240 return (SPE_CONST_OFFSET_OK (offset
)
3241 && SPE_CONST_OFFSET_OK (offset
+ 8));
3245 if (mode
== TFmode
|| mode
== TDmode
|| !TARGET_POWERPC64
)
3247 else if (offset
& 3)
3258 return (offset
< 0x10000) && (offset
+ extra
< 0x10000);
3262 legitimate_indexed_address_p (rtx x
, int strict
)
3266 if (GET_CODE (x
) != PLUS
)
3272 /* Recognize the rtl generated by reload which we know will later be
3273 replaced with proper base and index regs. */
3275 && reload_in_progress
3276 && (REG_P (op0
) || GET_CODE (op0
) == PLUS
)
3280 return (REG_P (op0
) && REG_P (op1
)
3281 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
3282 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
3283 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
3284 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
3288 legitimate_indirect_address_p (rtx x
, int strict
)
3290 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
3294 macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
)
3296 if (!TARGET_MACHO
|| !flag_pic
3297 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
3301 if (GET_CODE (x
) != LO_SUM
)
3303 if (GET_CODE (XEXP (x
, 0)) != REG
)
3305 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
3309 return CONSTANT_P (x
);
3313 legitimate_lo_sum_address_p (enum machine_mode mode
, rtx x
, int strict
)
3315 if (GET_CODE (x
) != LO_SUM
)
3317 if (GET_CODE (XEXP (x
, 0)) != REG
)
3319 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
3321 /* Restrict addressing for DI because of our SUBREG hackery. */
3322 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
3327 if (TARGET_ELF
|| TARGET_MACHO
)
3329 if (DEFAULT_ABI
!= ABI_AIX
&& DEFAULT_ABI
!= ABI_DARWIN
&& flag_pic
)
3333 if (GET_MODE_NUNITS (mode
) != 1)
3335 if (GET_MODE_BITSIZE (mode
) > 64
3336 || (GET_MODE_BITSIZE (mode
) > 32 && !TARGET_POWERPC64
3337 && !(TARGET_HARD_FLOAT
&& TARGET_FPRS
&& mode
== DFmode
)))
3340 return CONSTANT_P (x
);
3347 /* Try machine-dependent ways of modifying an illegitimate address
3348 to be legitimate. If we find one, return the new, valid address.
3349 This is used from only one place: `memory_address' in explow.c.
3351 OLDX is the address as it was before break_out_memory_refs was
3352 called. In some cases it is useful to look at this to decide what
3355 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3357 It is always safe for this function to do nothing. It exists to
3358 recognize opportunities to optimize the output.
3360 On RS/6000, first check for the sum of a register with a constant
3361 integer that is out of range. If so, generate code to add the
3362 constant with the low-order 16 bits masked to the register and force
3363 this result into another register (this can be done with `cau').
3364 Then generate an address of REG+(CONST&0xffff), allowing for the
3365 possibility of bit 16 being a one.
3367 Then check for the sum of a register and something not constant, try to
3368 load the other things into a register and return the sum. */
3371 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3372 enum machine_mode mode
)
3374 if (GET_CODE (x
) == SYMBOL_REF
)
3376 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
3378 return rs6000_legitimize_tls_address (x
, model
);
3381 if (GET_CODE (x
) == PLUS
3382 && GET_CODE (XEXP (x
, 0)) == REG
3383 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3384 && (unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000) >= 0x10000)
3386 HOST_WIDE_INT high_int
, low_int
;
3388 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3389 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
3390 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3391 GEN_INT (high_int
)), 0);
3392 return gen_rtx_PLUS (Pmode
, sum
, GEN_INT (low_int
));
3394 else if (GET_CODE (x
) == PLUS
3395 && GET_CODE (XEXP (x
, 0)) == REG
3396 && GET_CODE (XEXP (x
, 1)) != CONST_INT
3397 && GET_MODE_NUNITS (mode
) == 1
3398 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
3400 || (((mode
!= DImode
&& mode
!= DFmode
&& mode
!= DDmode
)
3401 || TARGET_E500_DOUBLE
)
3402 && mode
!= TFmode
&& mode
!= TDmode
))
3403 && (TARGET_POWERPC64
|| mode
!= DImode
)
3406 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3407 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
3409 else if (ALTIVEC_VECTOR_MODE (mode
))
3413 /* Make sure both operands are registers. */
3414 if (GET_CODE (x
) == PLUS
)
3415 return gen_rtx_PLUS (Pmode
, force_reg (Pmode
, XEXP (x
, 0)),
3416 force_reg (Pmode
, XEXP (x
, 1)));
3418 reg
= force_reg (Pmode
, x
);
3421 else if (SPE_VECTOR_MODE (mode
)
3422 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
3423 || mode
== DDmode
|| mode
== TDmode
3424 || mode
== DImode
)))
3428 /* We accept [reg + reg] and [reg + OFFSET]. */
3430 if (GET_CODE (x
) == PLUS
)
3432 rtx op1
= XEXP (x
, 0);
3433 rtx op2
= XEXP (x
, 1);
3435 op1
= force_reg (Pmode
, op1
);
3437 if (GET_CODE (op2
) != REG
3438 && (GET_CODE (op2
) != CONST_INT
3439 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))))
3440 op2
= force_reg (Pmode
, op2
);
3442 return gen_rtx_PLUS (Pmode
, op1
, op2
);
3445 return force_reg (Pmode
, x
);
3451 && GET_CODE (x
) != CONST_INT
3452 && GET_CODE (x
) != CONST_DOUBLE
3454 && GET_MODE_NUNITS (mode
) == 1
3455 && (GET_MODE_BITSIZE (mode
) <= 32
3456 || ((TARGET_HARD_FLOAT
&& TARGET_FPRS
) && mode
== DFmode
)))
3458 rtx reg
= gen_reg_rtx (Pmode
);
3459 emit_insn (gen_elf_high (reg
, x
));
3460 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
3462 else if (TARGET_MACHO
&& TARGET_32BIT
&& TARGET_NO_TOC
3465 && ! MACHO_DYNAMIC_NO_PIC_P
3467 && GET_CODE (x
) != CONST_INT
3468 && GET_CODE (x
) != CONST_DOUBLE
3470 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
) || mode
!= DFmode
)
3474 rtx reg
= gen_reg_rtx (Pmode
);
3475 emit_insn (gen_macho_high (reg
, x
));
3476 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
3479 && constant_pool_expr_p (x
)
3480 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
3482 return create_TOC_reference (x
);
3488 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3489 We need to emit DTP-relative relocations. */
3492 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
3497 fputs ("\t.long\t", file
);
3500 fputs (DOUBLE_INT_ASM_OP
, file
);
3505 output_addr_const (file
, x
);
3506 fputs ("@dtprel+0x8000", file
);
3509 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3511 static GTY(()) rtx rs6000_tls_symbol
;
3513 rs6000_tls_get_addr (void)
3515 if (!rs6000_tls_symbol
)
3516 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
3518 return rs6000_tls_symbol
;
3521 /* Construct the SYMBOL_REF for TLS GOT references. */
3523 static GTY(()) rtx rs6000_got_symbol
;
3525 rs6000_got_sym (void)
3527 if (!rs6000_got_symbol
)
3529 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3530 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
3531 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
3534 return rs6000_got_symbol
;
3537 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3538 this (thread-local) address. */
3541 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
3545 dest
= gen_reg_rtx (Pmode
);
3546 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
3552 tlsreg
= gen_rtx_REG (Pmode
, 13);
3553 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
3557 tlsreg
= gen_rtx_REG (Pmode
, 2);
3558 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
3562 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
3566 tmp
= gen_reg_rtx (Pmode
);
3569 tlsreg
= gen_rtx_REG (Pmode
, 13);
3570 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
3574 tlsreg
= gen_rtx_REG (Pmode
, 2);
3575 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
3579 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
3581 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
3586 rtx r3
, got
, tga
, tmp1
, tmp2
, eqv
;
3588 /* We currently use relocations like @got@tlsgd for tls, which
3589 means the linker will handle allocation of tls entries, placing
3590 them in the .got section. So use a pointer to the .got section,
3591 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3592 or to secondary GOT sections used by 32-bit -fPIC. */
3594 got
= gen_rtx_REG (Pmode
, 2);
3598 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
3601 rtx gsym
= rs6000_got_sym ();
3602 got
= gen_reg_rtx (Pmode
);
3604 rs6000_emit_move (got
, gsym
, Pmode
);
3610 tmp1
= gen_reg_rtx (Pmode
);
3611 tmp2
= gen_reg_rtx (Pmode
);
3612 tmp3
= gen_reg_rtx (Pmode
);
3613 mem
= gen_const_mem (Pmode
, tmp1
);
3615 first
= emit_insn (gen_load_toc_v4_PIC_1b (gsym
));
3616 emit_move_insn (tmp1
,
3617 gen_rtx_REG (Pmode
, LR_REGNO
));
3618 emit_move_insn (tmp2
, mem
);
3619 emit_insn (gen_addsi3 (tmp3
, tmp1
, tmp2
));
3620 last
= emit_move_insn (got
, tmp3
);
3621 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
3622 maybe_encapsulate_block (first
, last
, gsym
);
3627 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
3629 r3
= gen_rtx_REG (Pmode
, 3);
3631 insn
= gen_tls_gd_64 (r3
, got
, addr
);
3633 insn
= gen_tls_gd_32 (r3
, got
, addr
);
3636 tga
= gen_rtx_MEM (Pmode
, rs6000_tls_get_addr ());
3637 insn
= gen_call_value (r3
, tga
, const0_rtx
, const0_rtx
);
3638 insn
= emit_call_insn (insn
);
3639 CONST_OR_PURE_CALL_P (insn
) = 1;
3640 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r3
);
3641 insn
= get_insns ();
3643 emit_libcall_block (insn
, dest
, r3
, addr
);
3645 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
3647 r3
= gen_rtx_REG (Pmode
, 3);
3649 insn
= gen_tls_ld_64 (r3
, got
);
3651 insn
= gen_tls_ld_32 (r3
, got
);
3654 tga
= gen_rtx_MEM (Pmode
, rs6000_tls_get_addr ());
3655 insn
= gen_call_value (r3
, tga
, const0_rtx
, const0_rtx
);
3656 insn
= emit_call_insn (insn
);
3657 CONST_OR_PURE_CALL_P (insn
) = 1;
3658 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r3
);
3659 insn
= get_insns ();
3661 tmp1
= gen_reg_rtx (Pmode
);
3662 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3664 emit_libcall_block (insn
, tmp1
, r3
, eqv
);
3665 if (rs6000_tls_size
== 16)
3668 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
3670 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
3672 else if (rs6000_tls_size
== 32)
3674 tmp2
= gen_reg_rtx (Pmode
);
3676 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
3678 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
3681 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
3683 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
3687 tmp2
= gen_reg_rtx (Pmode
);
3689 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
3691 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
3693 insn
= gen_rtx_SET (Pmode
, dest
,
3694 gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
3700 /* IE, or 64-bit offset LE. */
3701 tmp2
= gen_reg_rtx (Pmode
);
3703 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
3705 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
3708 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
3710 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
3718 /* Return 1 if X contains a thread-local symbol. */
3721 rs6000_tls_referenced_p (rtx x
)
3723 if (! TARGET_HAVE_TLS
)
3726 return for_each_rtx (&x
, &rs6000_tls_symbol_ref_1
, 0);
3729 /* Return 1 if *X is a thread-local symbol. This is the same as
3730 rs6000_tls_symbol_ref except for the type of the unused argument. */
3733 rs6000_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
3735 return RS6000_SYMBOL_REF_TLS_P (*x
);
3738 /* The convention appears to be to define this wherever it is used.
3739 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3740 is now used here. */
3741 #ifndef REG_MODE_OK_FOR_BASE_P
3742 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3745 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3746 replace the input X, or the original X if no replacement is called for.
3747 The output parameter *WIN is 1 if the calling macro should goto WIN,
3750 For RS/6000, we wish to handle large displacements off a base
3751 register by splitting the addend across an addiu/addis and the mem insn.
3752 This cuts number of extra insns needed from 3 to 1.
3754 On Darwin, we use this to generate code for floating point constants.
3755 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3756 The Darwin code is inside #if TARGET_MACHO because only then is
3757 machopic_function_base_name() defined. */
3759 rs6000_legitimize_reload_address (rtx x
, enum machine_mode mode
,
3760 int opnum
, int type
,
3761 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
3763 /* We must recognize output that we have already generated ourselves. */
3764 if (GET_CODE (x
) == PLUS
3765 && GET_CODE (XEXP (x
, 0)) == PLUS
3766 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
3767 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3768 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3770 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3771 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3772 opnum
, (enum reload_type
)type
);
3778 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
3779 && GET_CODE (x
) == LO_SUM
3780 && GET_CODE (XEXP (x
, 0)) == PLUS
3781 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
3782 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
3783 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 0)) == CONST
3784 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
3785 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == MINUS
3786 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 0)) == SYMBOL_REF
3787 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == SYMBOL_REF
)
3789 /* Result of previous invocation of this function on Darwin
3790 floating point constant. */
3791 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3792 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
3793 opnum
, (enum reload_type
)type
);
3799 /* Force ld/std non-word aligned offset into base register by wrapping
3801 if (GET_CODE (x
) == PLUS
3802 && GET_CODE (XEXP (x
, 0)) == REG
3803 && REGNO (XEXP (x
, 0)) < 32
3804 && REG_MODE_OK_FOR_BASE_P (XEXP (x
, 0), mode
)
3805 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3806 && (INTVAL (XEXP (x
, 1)) & 3) != 0
3807 && !ALTIVEC_VECTOR_MODE (mode
)
3808 && GET_MODE_SIZE (mode
) >= UNITS_PER_WORD
3809 && TARGET_POWERPC64
)
3811 x
= gen_rtx_PLUS (GET_MODE (x
), x
, GEN_INT (0));
3812 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3813 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3814 opnum
, (enum reload_type
) type
);
3819 if (GET_CODE (x
) == PLUS
3820 && GET_CODE (XEXP (x
, 0)) == REG
3821 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
3822 && REG_MODE_OK_FOR_BASE_P (XEXP (x
, 0), mode
)
3823 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3824 && !SPE_VECTOR_MODE (mode
)
3825 && !(TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
3827 && !ALTIVEC_VECTOR_MODE (mode
))
3829 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
3830 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
3832 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3834 /* Check for 32-bit overflow. */
3835 if (high
+ low
!= val
)
3841 /* Reload the high part into a base reg; leave the low part
3842 in the mem directly. */
3844 x
= gen_rtx_PLUS (GET_MODE (x
),
3845 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
3849 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3850 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3851 opnum
, (enum reload_type
)type
);
3856 if (GET_CODE (x
) == SYMBOL_REF
3857 && !ALTIVEC_VECTOR_MODE (mode
)
3858 && !SPE_VECTOR_MODE (mode
)
3860 && DEFAULT_ABI
== ABI_DARWIN
3861 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
3863 && DEFAULT_ABI
== ABI_V4
3866 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
3867 The same goes for DImode without 64-bit gprs and DFmode
3871 && (mode
!= DImode
|| TARGET_POWERPC64
)
3872 && (mode
!= DFmode
|| TARGET_POWERPC64
3873 || (TARGET_FPRS
&& TARGET_HARD_FLOAT
)))
3878 rtx offset
= gen_rtx_CONST (Pmode
,
3879 gen_rtx_MINUS (Pmode
, x
,
3880 machopic_function_base_sym ()));
3881 x
= gen_rtx_LO_SUM (GET_MODE (x
),
3882 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
3883 gen_rtx_HIGH (Pmode
, offset
)), offset
);
3887 x
= gen_rtx_LO_SUM (GET_MODE (x
),
3888 gen_rtx_HIGH (Pmode
, x
), x
);
3890 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3891 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
3892 opnum
, (enum reload_type
)type
);
3897 /* Reload an offset address wrapped by an AND that represents the
3898 masking of the lower bits. Strip the outer AND and let reload
3899 convert the offset address into an indirect address. */
3901 && ALTIVEC_VECTOR_MODE (mode
)
3902 && GET_CODE (x
) == AND
3903 && GET_CODE (XEXP (x
, 0)) == PLUS
3904 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
3905 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3906 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3907 && INTVAL (XEXP (x
, 1)) == -16)
3915 && constant_pool_expr_p (x
)
3916 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), mode
))
3918 x
= create_TOC_reference (x
);
3926 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3927 that is a valid memory address for an instruction.
3928 The MODE argument is the machine mode for the MEM expression
3929 that wants to use this address.
3931 On the RS/6000, there are four valid address: a SYMBOL_REF that
3932 refers to a constant pool entry of an address (or the sum of it
3933 plus a constant), a short (16-bit signed) constant plus a register,
3934 the sum of two registers, or a register indirect, possibly with an
3935 auto-increment. For DFmode and DImode with a constant plus register,
3936 we must ensure that both words are addressable or PowerPC64 with offset
3939 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3940 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
3941 because adjacent memory cells are accessed by adding word-sized offsets
3942 during assembly output. */
3944 rs6000_legitimate_address (enum machine_mode mode
, rtx x
, int reg_ok_strict
)
3946 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3948 && ALTIVEC_VECTOR_MODE (mode
)
3949 && GET_CODE (x
) == AND
3950 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3951 && INTVAL (XEXP (x
, 1)) == -16)
3954 if (RS6000_SYMBOL_REF_TLS_P (x
))
3956 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
3958 if ((GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
3959 && !ALTIVEC_VECTOR_MODE (mode
)
3960 && !SPE_VECTOR_MODE (mode
)
3963 /* Restrict addressing for DI because of our SUBREG hackery. */
3964 && !(TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
3967 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
3969 if (legitimate_small_data_p (mode
, x
))
3971 if (legitimate_constant_pool_address_p (x
))
3973 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3975 && GET_CODE (x
) == PLUS
3976 && GET_CODE (XEXP (x
, 0)) == REG
3977 && (XEXP (x
, 0) == virtual_stack_vars_rtx
3978 || XEXP (x
, 0) == arg_pointer_rtx
)
3979 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3981 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
))
3986 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
3988 || ((mode
!= DFmode
|| TARGET_E500_DOUBLE
) && mode
!= TFmode
))
3989 && (TARGET_POWERPC64
|| mode
!= DImode
)
3990 && legitimate_indexed_address_p (x
, reg_ok_strict
))
3992 if (GET_CODE (x
) == PRE_MODIFY
3996 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
3998 || ((mode
!= DFmode
|| TARGET_E500_DOUBLE
) && mode
!= TFmode
))
3999 && (TARGET_POWERPC64
|| mode
!= DImode
)
4000 && !ALTIVEC_VECTOR_MODE (mode
)
4001 && !SPE_VECTOR_MODE (mode
)
4002 /* Restrict addressing for DI because of our SUBREG hackery. */
4003 && !(TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== DImode
))
4005 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
4006 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1), reg_ok_strict
)
4007 || legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
))
4008 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4010 if (legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
4015 /* Go to LABEL if ADDR (a legitimate address expression)
4016 has an effect that depends on the machine mode it is used for.
4018 On the RS/6000 this is true of all integral offsets (since AltiVec
4019 modes don't allow them) or is a pre-increment or decrement.
4021 ??? Except that due to conceptual problems in offsettable_address_p
4022 we can't really report the problems of integral offsets. So leave
4023 this assuming that the adjustable offset must be valid for the
4024 sub-words of a TFmode operand, which is what we had before. */
4027 rs6000_mode_dependent_address (rtx addr
)
4029 switch (GET_CODE (addr
))
4032 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
4034 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
4035 return val
+ 12 + 0x8000 >= 0x10000;
4045 return TARGET_UPDATE
;
4054 /* More elaborate version of recog's offsettable_memref_p predicate
4055 that works around the ??? note of rs6000_mode_dependent_address.
4056 In particular it accepts
4058 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
4060 in 32-bit mode, that the recog predicate rejects. */
4063 rs6000_offsettable_memref_p (rtx op
)
4068 /* First mimic offsettable_memref_p. */
4069 if (offsettable_address_p (1, GET_MODE (op
), XEXP (op
, 0)))
4072 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
4073 the latter predicate knows nothing about the mode of the memory
4074 reference and, therefore, assumes that it is the largest supported
4075 mode (TFmode). As a consequence, legitimate offsettable memory
4076 references are rejected. rs6000_legitimate_offset_address_p contains
4077 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
4078 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0), 1);
4081 /* Return number of consecutive hard regs needed starting at reg REGNO
4082 to hold something of mode MODE.
4083 This is ordinarily the length in words of a value of mode MODE
4084 but can be less for certain modes in special long registers.
4086 For the SPE, GPRs are 64 bits but only 32 bits are visible in
4087 scalar instructions. The upper 32 bits are only available to the
4090 POWER and PowerPC GPRs hold 32 bits worth;
4091 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
4094 rs6000_hard_regno_nregs (int regno
, enum machine_mode mode
)
4096 if (FP_REGNO_P (regno
))
4097 return (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
4099 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
4100 return (GET_MODE_SIZE (mode
) + UNITS_PER_SPE_WORD
- 1) / UNITS_PER_SPE_WORD
;
4102 if (ALTIVEC_REGNO_P (regno
))
4104 (GET_MODE_SIZE (mode
) + UNITS_PER_ALTIVEC_WORD
- 1) / UNITS_PER_ALTIVEC_WORD
;
4106 /* The value returned for SCmode in the E500 double case is 2 for
4107 ABI compatibility; storing an SCmode value in a single register
4108 would require function_arg and rs6000_spe_function_arg to handle
4109 SCmode so as to pass the value correctly in a pair of
4111 if (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
) && mode
!= SCmode
)
4112 return (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
4114 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4117 /* Change register usage conditional on target flags. */
4119 rs6000_conditional_register_usage (void)
4123 /* Set MQ register fixed (already call_used) if not POWER
4124 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
4129 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
4131 fixed_regs
[13] = call_used_regs
[13]
4132 = call_really_used_regs
[13] = 1;
4134 /* Conditionally disable FPRs. */
4135 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
4136 for (i
= 32; i
< 64; i
++)
4137 fixed_regs
[i
] = call_used_regs
[i
]
4138 = call_really_used_regs
[i
] = 1;
4140 /* The TOC register is not killed across calls in a way that is
4141 visible to the compiler. */
4142 if (DEFAULT_ABI
== ABI_AIX
)
4143 call_really_used_regs
[2] = 0;
4145 if (DEFAULT_ABI
== ABI_V4
4146 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
4148 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4150 if (DEFAULT_ABI
== ABI_V4
4151 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
4153 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4154 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4155 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4157 if (DEFAULT_ABI
== ABI_DARWIN
4158 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
4159 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4160 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4161 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4163 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
4164 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4165 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4168 global_regs
[VSCR_REGNO
] = 1;
4172 global_regs
[SPEFSCR_REGNO
] = 1;
4173 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
4174 registers in prologues and epilogues. We no longer use r14
4175 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
4176 pool for link-compatibility with older versions of GCC. Once
4177 "old" code has died out, we can return r14 to the allocation
4180 = call_used_regs
[14]
4181 = call_really_used_regs
[14] = 1;
4184 if (! TARGET_ALTIVEC
)
4186 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
4187 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
4188 call_really_used_regs
[VRSAVE_REGNO
] = 1;
4191 if (TARGET_ALTIVEC_ABI
)
4192 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
4193 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
4196 /* Try to output insns to set TARGET equal to the constant C if it can
4197 be done in less than N insns. Do all computations in MODE.
4198 Returns the place where the output has been placed if it can be
4199 done and the insns have been emitted. If it would take more than N
4200 insns, zero is returned and no insns and emitted. */
4203 rs6000_emit_set_const (rtx dest
, enum machine_mode mode
,
4204 rtx source
, int n ATTRIBUTE_UNUSED
)
4206 rtx result
, insn
, set
;
4207 HOST_WIDE_INT c0
, c1
;
4214 dest
= gen_reg_rtx (mode
);
4215 emit_insn (gen_rtx_SET (VOIDmode
, dest
, source
));
4219 result
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
4221 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (result
),
4222 GEN_INT (INTVAL (source
)
4223 & (~ (HOST_WIDE_INT
) 0xffff))));
4224 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
4225 gen_rtx_IOR (SImode
, copy_rtx (result
),
4226 GEN_INT (INTVAL (source
) & 0xffff))));
4231 switch (GET_CODE (source
))
4234 c0
= INTVAL (source
);
4239 #if HOST_BITS_PER_WIDE_INT >= 64
4240 c0
= CONST_DOUBLE_LOW (source
);
4243 c0
= CONST_DOUBLE_LOW (source
);
4244 c1
= CONST_DOUBLE_HIGH (source
);
4252 result
= rs6000_emit_set_long_const (dest
, c0
, c1
);
4259 insn
= get_last_insn ();
4260 set
= single_set (insn
);
4261 if (! CONSTANT_P (SET_SRC (set
)))
4262 set_unique_reg_note (insn
, REG_EQUAL
, source
);
4267 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4268 fall back to a straight forward decomposition. We do this to avoid
4269 exponential run times encountered when looking for longer sequences
4270 with rs6000_emit_set_const. */
4272 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
4274 if (!TARGET_POWERPC64
)
4276 rtx operand1
, operand2
;
4278 operand1
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
== 0,
4280 operand2
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
!= 0,
4282 emit_move_insn (operand1
, GEN_INT (c1
));
4283 emit_move_insn (operand2
, GEN_INT (c2
));
4287 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
4290 ud2
= (c1
& 0xffff0000) >> 16;
4291 #if HOST_BITS_PER_WIDE_INT >= 64
4295 ud4
= (c2
& 0xffff0000) >> 16;
4297 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
4298 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
4301 emit_move_insn (dest
, GEN_INT (((ud1
^ 0x8000) - 0x8000)));
4303 emit_move_insn (dest
, GEN_INT (ud1
));
4306 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
4307 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
4310 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
4313 emit_move_insn (dest
, GEN_INT (ud2
<< 16));
4315 emit_move_insn (copy_rtx (dest
),
4316 gen_rtx_IOR (DImode
, copy_rtx (dest
),
4319 else if ((ud4
== 0xffff && (ud3
& 0x8000))
4320 || (ud4
== 0 && ! (ud3
& 0x8000)))
4323 emit_move_insn (dest
, GEN_INT (((ud3
<< 16) ^ 0x80000000)
4326 emit_move_insn (dest
, GEN_INT (ud3
<< 16));
4329 emit_move_insn (copy_rtx (dest
),
4330 gen_rtx_IOR (DImode
, copy_rtx (dest
),
4332 emit_move_insn (copy_rtx (dest
),
4333 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
4336 emit_move_insn (copy_rtx (dest
),
4337 gen_rtx_IOR (DImode
, copy_rtx (dest
),
4343 emit_move_insn (dest
, GEN_INT (((ud4
<< 16) ^ 0x80000000)
4346 emit_move_insn (dest
, GEN_INT (ud4
<< 16));
4349 emit_move_insn (copy_rtx (dest
),
4350 gen_rtx_IOR (DImode
, copy_rtx (dest
),
4353 emit_move_insn (copy_rtx (dest
),
4354 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
4357 emit_move_insn (copy_rtx (dest
),
4358 gen_rtx_IOR (DImode
, copy_rtx (dest
),
4359 GEN_INT (ud2
<< 16)));
4361 emit_move_insn (copy_rtx (dest
),
4362 gen_rtx_IOR (DImode
, copy_rtx (dest
), GEN_INT (ud1
)));
4368 /* Helper for the following. Get rid of [r+r] memory refs
4369 in cases where it won't work (TImode, TFmode, TDmode). */
4372 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
4374 if (GET_CODE (operands
[0]) == MEM
4375 && GET_CODE (XEXP (operands
[0], 0)) != REG
4376 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0))
4377 && ! reload_in_progress
)
4379 = replace_equiv_address (operands
[0],
4380 copy_addr_to_reg (XEXP (operands
[0], 0)));
4382 if (GET_CODE (operands
[1]) == MEM
4383 && GET_CODE (XEXP (operands
[1], 0)) != REG
4384 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0))
4385 && ! reload_in_progress
)
4387 = replace_equiv_address (operands
[1],
4388 copy_addr_to_reg (XEXP (operands
[1], 0)));
4391 /* Emit a move from SOURCE to DEST in mode MODE. */
4393 rs6000_emit_move (rtx dest
, rtx source
, enum machine_mode mode
)
4397 operands
[1] = source
;
4399 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4400 if (GET_CODE (operands
[1]) == CONST_DOUBLE
4401 && ! FLOAT_MODE_P (mode
)
4402 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
4404 /* FIXME. This should never happen. */
4405 /* Since it seems that it does, do the safe thing and convert
4407 operands
[1] = gen_int_mode (CONST_DOUBLE_LOW (operands
[1]), mode
);
4409 gcc_assert (GET_CODE (operands
[1]) != CONST_DOUBLE
4410 || FLOAT_MODE_P (mode
)
4411 || ((CONST_DOUBLE_HIGH (operands
[1]) != 0
4412 || CONST_DOUBLE_LOW (operands
[1]) < 0)
4413 && (CONST_DOUBLE_HIGH (operands
[1]) != -1
4414 || CONST_DOUBLE_LOW (operands
[1]) >= 0)));
4416 /* Check if GCC is setting up a block move that will end up using FP
4417 registers as temporaries. We must make sure this is acceptable. */
4418 if (GET_CODE (operands
[0]) == MEM
4419 && GET_CODE (operands
[1]) == MEM
4421 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
4422 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
4423 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
4424 ? 32 : MEM_ALIGN (operands
[0])))
4425 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
4427 : MEM_ALIGN (operands
[1]))))
4428 && ! MEM_VOLATILE_P (operands
[0])
4429 && ! MEM_VOLATILE_P (operands
[1]))
4431 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
4432 adjust_address (operands
[1], SImode
, 0));
4433 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
4434 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
4438 if (can_create_pseudo_p () && GET_CODE (operands
[0]) == MEM
4439 && !gpc_reg_operand (operands
[1], mode
))
4440 operands
[1] = force_reg (mode
, operands
[1]);
4442 if (mode
== SFmode
&& ! TARGET_POWERPC
4443 && TARGET_HARD_FLOAT
&& TARGET_FPRS
4444 && GET_CODE (operands
[0]) == MEM
)
4448 if (reload_in_progress
|| reload_completed
)
4449 regnum
= true_regnum (operands
[1]);
4450 else if (GET_CODE (operands
[1]) == REG
)
4451 regnum
= REGNO (operands
[1]);
4455 /* If operands[1] is a register, on POWER it may have
4456 double-precision data in it, so truncate it to single
4458 if (FP_REGNO_P (regnum
) || regnum
>= FIRST_PSEUDO_REGISTER
)
4461 newreg
= (!can_create_pseudo_p () ? copy_rtx (operands
[1])
4462 : gen_reg_rtx (mode
));
4463 emit_insn (gen_aux_truncdfsf2 (newreg
, operands
[1]));
4464 operands
[1] = newreg
;
4468 /* Recognize the case where operand[1] is a reference to thread-local
4469 data and load its address to a register. */
4470 if (rs6000_tls_referenced_p (operands
[1]))
4472 enum tls_model model
;
4473 rtx tmp
= operands
[1];
4476 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
4478 addend
= XEXP (XEXP (tmp
, 0), 1);
4479 tmp
= XEXP (XEXP (tmp
, 0), 0);
4482 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
4483 model
= SYMBOL_REF_TLS_MODEL (tmp
);
4484 gcc_assert (model
!= 0);
4486 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
4489 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
4490 tmp
= force_operand (tmp
, operands
[0]);
4495 /* Handle the case where reload calls us with an invalid address. */
4496 if (reload_in_progress
&& mode
== Pmode
4497 && (! general_operand (operands
[1], mode
)
4498 || ! nonimmediate_operand (operands
[0], mode
)))
4501 /* 128-bit constant floating-point values on Darwin should really be
4502 loaded as two parts. */
4503 if (!TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
4504 && mode
== TFmode
&& GET_CODE (operands
[1]) == CONST_DOUBLE
)
4506 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4507 know how to get a DFmode SUBREG of a TFmode. */
4508 enum machine_mode imode
= (TARGET_E500_DOUBLE
? DFmode
: DImode
);
4509 rs6000_emit_move (simplify_gen_subreg (imode
, operands
[0], mode
, 0),
4510 simplify_gen_subreg (imode
, operands
[1], mode
, 0),
4512 rs6000_emit_move (simplify_gen_subreg (imode
, operands
[0], mode
,
4513 GET_MODE_SIZE (imode
)),
4514 simplify_gen_subreg (imode
, operands
[1], mode
,
4515 GET_MODE_SIZE (imode
)),
4520 /* FIXME: In the long term, this switch statement should go away
4521 and be replaced by a sequence of tests based on things like
4527 if (CONSTANT_P (operands
[1])
4528 && GET_CODE (operands
[1]) != CONST_INT
)
4529 operands
[1] = force_const_mem (mode
, operands
[1]);
4534 rs6000_eliminate_indexed_memrefs (operands
);
4540 if (CONSTANT_P (operands
[1])
4541 && ! easy_fp_constant (operands
[1], mode
))
4542 operands
[1] = force_const_mem (mode
, operands
[1]);
4553 if (CONSTANT_P (operands
[1])
4554 && !easy_vector_constant (operands
[1], mode
))
4555 operands
[1] = force_const_mem (mode
, operands
[1]);
4560 /* Use default pattern for address of ELF small data */
4563 && DEFAULT_ABI
== ABI_V4
4564 && (GET_CODE (operands
[1]) == SYMBOL_REF
4565 || GET_CODE (operands
[1]) == CONST
)
4566 && small_data_operand (operands
[1], mode
))
4568 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
4572 if (DEFAULT_ABI
== ABI_V4
4573 && mode
== Pmode
&& mode
== SImode
4574 && flag_pic
== 1 && got_operand (operands
[1], mode
))
4576 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
4580 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
4584 && CONSTANT_P (operands
[1])
4585 && GET_CODE (operands
[1]) != HIGH
4586 && GET_CODE (operands
[1]) != CONST_INT
)
4588 rtx target
= (!can_create_pseudo_p ()
4590 : gen_reg_rtx (mode
));
4592 /* If this is a function address on -mcall-aixdesc,
4593 convert it to the address of the descriptor. */
4594 if (DEFAULT_ABI
== ABI_AIX
4595 && GET_CODE (operands
[1]) == SYMBOL_REF
4596 && XSTR (operands
[1], 0)[0] == '.')
4598 const char *name
= XSTR (operands
[1], 0);
4600 while (*name
== '.')
4602 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
4603 CONSTANT_POOL_ADDRESS_P (new_ref
)
4604 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
4605 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
4606 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
4607 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
4608 operands
[1] = new_ref
;
4611 if (DEFAULT_ABI
== ABI_DARWIN
)
4614 if (MACHO_DYNAMIC_NO_PIC_P
)
4616 /* Take care of any required data indirection. */
4617 operands
[1] = rs6000_machopic_legitimize_pic_address (
4618 operands
[1], mode
, operands
[0]);
4619 if (operands
[0] != operands
[1])
4620 emit_insn (gen_rtx_SET (VOIDmode
,
4621 operands
[0], operands
[1]));
4625 emit_insn (gen_macho_high (target
, operands
[1]));
4626 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
4630 emit_insn (gen_elf_high (target
, operands
[1]));
4631 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
4635 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4636 and we have put it in the TOC, we just need to make a TOC-relative
4639 && GET_CODE (operands
[1]) == SYMBOL_REF
4640 && constant_pool_expr_p (operands
[1])
4641 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands
[1]),
4642 get_pool_mode (operands
[1])))
4644 operands
[1] = create_TOC_reference (operands
[1]);
4646 else if (mode
== Pmode
4647 && CONSTANT_P (operands
[1])
4648 && ((GET_CODE (operands
[1]) != CONST_INT
4649 && ! easy_fp_constant (operands
[1], mode
))
4650 || (GET_CODE (operands
[1]) == CONST_INT
4651 && num_insns_constant (operands
[1], mode
) > 2)
4652 || (GET_CODE (operands
[0]) == REG
4653 && FP_REGNO_P (REGNO (operands
[0]))))
4654 && GET_CODE (operands
[1]) != HIGH
4655 && ! legitimate_constant_pool_address_p (operands
[1])
4656 && ! toc_relative_expr_p (operands
[1]))
4658 /* Emit a USE operation so that the constant isn't deleted if
4659 expensive optimizations are turned on because nobody
4660 references it. This should only be done for operands that
4661 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4662 This should not be done for operands that contain LABEL_REFs.
4663 For now, we just handle the obvious case. */
4664 if (GET_CODE (operands
[1]) != LABEL_REF
)
4665 emit_insn (gen_rtx_USE (VOIDmode
, operands
[1]));
4668 /* Darwin uses a special PIC legitimizer. */
4669 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
4672 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
4674 if (operands
[0] != operands
[1])
4675 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
4680 /* If we are to limit the number of things we put in the TOC and
4681 this is a symbol plus a constant we can add in one insn,
4682 just put the symbol in the TOC and add the constant. Don't do
4683 this if reload is in progress. */
4684 if (GET_CODE (operands
[1]) == CONST
4685 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
4686 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
4687 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
4688 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
4689 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
4690 && ! side_effects_p (operands
[0]))
4693 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
4694 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
4696 sym
= force_reg (mode
, sym
);
4698 emit_insn (gen_addsi3 (operands
[0], sym
, other
));
4700 emit_insn (gen_adddi3 (operands
[0], sym
, other
));
4704 operands
[1] = force_const_mem (mode
, operands
[1]);
4707 && constant_pool_expr_p (XEXP (operands
[1], 0))
4708 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4709 get_pool_constant (XEXP (operands
[1], 0)),
4710 get_pool_mode (XEXP (operands
[1], 0))))
4713 = gen_const_mem (mode
,
4714 create_TOC_reference (XEXP (operands
[1], 0)));
4715 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
4721 rs6000_eliminate_indexed_memrefs (operands
);
4725 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
4727 gen_rtx_SET (VOIDmode
,
4728 operands
[0], operands
[1]),
4729 gen_rtx_CLOBBER (VOIDmode
,
4730 gen_rtx_SCRATCH (SImode
)))));
4739 /* Above, we may have called force_const_mem which may have returned
4740 an invalid address. If we can, fix this up; otherwise, reload will
4741 have to deal with it. */
4742 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
4743 operands
[1] = validize_mem (operands
[1]);
4746 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
4749 /* Nonzero if we can use a floating-point register to pass this arg. */
4750 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4751 (SCALAR_FLOAT_MODE_P (MODE) \
4752 && (MODE) != SDmode \
4753 && (CUM)->fregno <= FP_ARG_MAX_REG \
4754 && TARGET_HARD_FLOAT && TARGET_FPRS)
4756 /* Nonzero if we can use an AltiVec register to pass this arg. */
4757 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4758 (ALTIVEC_VECTOR_MODE (MODE) \
4759 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4760 && TARGET_ALTIVEC_ABI \
4763 /* Return a nonzero value to say to return the function value in
4764 memory, just as large structures are always returned. TYPE will be
4765 the data type of the value, and FNTYPE will be the type of the
4766 function doing the returning, or @code{NULL} for libcalls.
4768 The AIX ABI for the RS/6000 specifies that all structures are
4769 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4770 specifies that structures <= 8 bytes are returned in r3/r4, but a
4771 draft put them in memory, and GCC used to implement the draft
4772 instead of the final standard. Therefore, aix_struct_return
4773 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4774 compatibility can change DRAFT_V4_STRUCT_RET to override the
4775 default, and -m switches get the final word. See
4776 rs6000_override_options for more details.
4778 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4779 long double support is enabled. These values are returned in memory.
4781 int_size_in_bytes returns -1 for variable size objects, which go in
4782 memory always. The cast to unsigned makes -1 > 8. */
4785 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
4787 /* In the darwin64 abi, try to use registers for larger structs
4789 if (rs6000_darwin64_abi
4790 && TREE_CODE (type
) == RECORD_TYPE
4791 && int_size_in_bytes (type
) > 0)
4793 CUMULATIVE_ARGS valcum
;
4797 valcum
.fregno
= FP_ARG_MIN_REG
;
4798 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
4799 /* Do a trial code generation as if this were going to be passed
4800 as an argument; if any part goes in memory, we return NULL. */
4801 valret
= rs6000_darwin64_record_arg (&valcum
, type
, 1, true);
4804 /* Otherwise fall through to more conventional ABI rules. */
4807 if (AGGREGATE_TYPE_P (type
)
4808 && (aix_struct_return
4809 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
4812 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4813 modes only exist for GCC vector types if -maltivec. */
4814 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
4815 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
4818 /* Return synthetic vectors in memory. */
4819 if (TREE_CODE (type
) == VECTOR_TYPE
4820 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
4822 static bool warned_for_return_big_vectors
= false;
4823 if (!warned_for_return_big_vectors
)
4825 warning (0, "GCC vector returned by reference: "
4826 "non-standard ABI extension with no compatibility guarantee");
4827 warned_for_return_big_vectors
= true;
4832 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& TYPE_MODE (type
) == TFmode
)
4838 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4839 for a call to a function whose data type is FNTYPE.
4840 For a library call, FNTYPE is 0.
4842 For incoming args we set the number of arguments in the prototype large
4843 so we never return a PARALLEL. */
4846 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
4847 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
4848 int libcall
, int n_named_args
)
4850 static CUMULATIVE_ARGS zero_cumulative
;
4852 *cum
= zero_cumulative
;
4854 cum
->fregno
= FP_ARG_MIN_REG
;
4855 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
4856 cum
->prototype
= (fntype
&& TYPE_ARG_TYPES (fntype
));
4857 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
4858 ? CALL_LIBCALL
: CALL_NORMAL
);
4859 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
4860 cum
->stdarg
= fntype
4861 && (TYPE_ARG_TYPES (fntype
) != 0
4862 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
4863 != void_type_node
));
4865 cum
->nargs_prototype
= 0;
4866 if (incoming
|| cum
->prototype
)
4867 cum
->nargs_prototype
= n_named_args
;
4869 /* Check for a longcall attribute. */
4870 if ((!fntype
&& rs6000_default_long_calls
)
4872 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
4873 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
4874 cum
->call_cookie
|= CALL_LONG
;
4876 if (TARGET_DEBUG_ARG
)
4878 fprintf (stderr
, "\ninit_cumulative_args:");
4881 tree ret_type
= TREE_TYPE (fntype
);
4882 fprintf (stderr
, " ret code = %s,",
4883 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
4886 if (cum
->call_cookie
& CALL_LONG
)
4887 fprintf (stderr
, " longcall,");
4889 fprintf (stderr
, " proto = %d, nargs = %d\n",
4890 cum
->prototype
, cum
->nargs_prototype
);
4895 && TARGET_ALTIVEC_ABI
4896 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
4898 error ("cannot return value in vector register because"
4899 " altivec instructions are disabled, use -maltivec"
4904 /* Return true if TYPE must be passed on the stack and not in registers. */
4907 rs6000_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
4909 if (DEFAULT_ABI
== ABI_AIX
|| TARGET_64BIT
)
4910 return must_pass_in_stack_var_size (mode
, type
);
4912 return must_pass_in_stack_var_size_or_pad (mode
, type
);
4915 /* If defined, a C expression which determines whether, and in which
4916 direction, to pad out an argument with extra space. The value
4917 should be of type `enum direction': either `upward' to pad above
4918 the argument, `downward' to pad below, or `none' to inhibit
4921 For the AIX ABI structs are always stored left shifted in their
4925 function_arg_padding (enum machine_mode mode
, const_tree type
)
4927 #ifndef AGGREGATE_PADDING_FIXED
4928 #define AGGREGATE_PADDING_FIXED 0
4930 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4931 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4934 if (!AGGREGATE_PADDING_FIXED
)
4936 /* GCC used to pass structures of the same size as integer types as
4937 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4938 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4939 passed padded downward, except that -mstrict-align further
4940 muddied the water in that multi-component structures of 2 and 4
4941 bytes in size were passed padded upward.
4943 The following arranges for best compatibility with previous
4944 versions of gcc, but removes the -mstrict-align dependency. */
4945 if (BYTES_BIG_ENDIAN
)
4947 HOST_WIDE_INT size
= 0;
4949 if (mode
== BLKmode
)
4951 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
4952 size
= int_size_in_bytes (type
);
4955 size
= GET_MODE_SIZE (mode
);
4957 if (size
== 1 || size
== 2 || size
== 4)
4963 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
4965 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
4969 /* Fall back to the default. */
4970 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
4973 /* If defined, a C expression that gives the alignment boundary, in bits,
4974 of an argument with the specified mode and type. If it is not defined,
4975 PARM_BOUNDARY is used for all arguments.
4977 V.4 wants long longs and doubles to be double word aligned. Just
4978 testing the mode size is a boneheaded way to do this as it means
4979 that other types such as complex int are also double word aligned.
4980 However, we're stuck with this because changing the ABI might break
4981 existing library interfaces.
4983 Doubleword align SPE vectors.
4984 Quadword align Altivec vectors.
4985 Quadword align large synthetic vector types. */
4988 function_arg_boundary (enum machine_mode mode
, tree type
)
4990 if (DEFAULT_ABI
== ABI_V4
4991 && (GET_MODE_SIZE (mode
) == 8
4992 || (TARGET_HARD_FLOAT
4994 && (mode
== TFmode
|| mode
== TDmode
))))
4996 else if (SPE_VECTOR_MODE (mode
)
4997 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
4998 && int_size_in_bytes (type
) >= 8
4999 && int_size_in_bytes (type
) < 16))
5001 else if (ALTIVEC_VECTOR_MODE (mode
)
5002 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
5003 && int_size_in_bytes (type
) >= 16))
5005 else if (rs6000_darwin64_abi
&& mode
== BLKmode
5006 && type
&& TYPE_ALIGN (type
) > 64)
5009 return PARM_BOUNDARY
;
5012 /* For a function parm of MODE and TYPE, return the starting word in
5013 the parameter area. NWORDS of the parameter area are already used. */
5016 rs6000_parm_start (enum machine_mode mode
, tree type
, unsigned int nwords
)
5019 unsigned int parm_offset
;
5021 align
= function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
5022 parm_offset
= DEFAULT_ABI
== ABI_V4
? 2 : 6;
5023 return nwords
+ (-(parm_offset
+ nwords
) & align
);
5026 /* Compute the size (in words) of a function argument. */
5028 static unsigned long
5029 rs6000_arg_size (enum machine_mode mode
, tree type
)
5033 if (mode
!= BLKmode
)
5034 size
= GET_MODE_SIZE (mode
);
5036 size
= int_size_in_bytes (type
);
5039 return (size
+ 3) >> 2;
5041 return (size
+ 7) >> 3;
5044 /* Use this to flush pending int fields. */
5047 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
5048 HOST_WIDE_INT bitpos
)
5050 unsigned int startbit
, endbit
;
5051 int intregs
, intoffset
;
5052 enum machine_mode mode
;
5054 if (cum
->intoffset
== -1)
5057 intoffset
= cum
->intoffset
;
5058 cum
->intoffset
= -1;
5060 if (intoffset
% BITS_PER_WORD
!= 0)
5062 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
5064 if (mode
== BLKmode
)
5066 /* We couldn't find an appropriate mode, which happens,
5067 e.g., in packed structs when there are 3 bytes to load.
5068 Back intoffset back to the beginning of the word in this
5070 intoffset
= intoffset
& -BITS_PER_WORD
;
5074 startbit
= intoffset
& -BITS_PER_WORD
;
5075 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5076 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
5077 cum
->words
+= intregs
;
5080 /* The darwin64 ABI calls for us to recurse down through structs,
5081 looking for elements passed in registers. Unfortunately, we have
5082 to track int register count here also because of misalignments
5083 in powerpc alignment mode. */
5086 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
5088 HOST_WIDE_INT startbitpos
)
5092 for (f
= TYPE_FIELDS (type
); f
; f
= TREE_CHAIN (f
))
5093 if (TREE_CODE (f
) == FIELD_DECL
)
5095 HOST_WIDE_INT bitpos
= startbitpos
;
5096 tree ftype
= TREE_TYPE (f
);
5097 enum machine_mode mode
;
5098 if (ftype
== error_mark_node
)
5100 mode
= TYPE_MODE (ftype
);
5102 if (DECL_SIZE (f
) != 0
5103 && host_integerp (bit_position (f
), 1))
5104 bitpos
+= int_bit_position (f
);
5106 /* ??? FIXME: else assume zero offset. */
5108 if (TREE_CODE (ftype
) == RECORD_TYPE
)
5109 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
5110 else if (USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
5112 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
);
5113 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
5114 cum
->words
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
5116 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, 1))
5118 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
);
5122 else if (cum
->intoffset
== -1)
5123 cum
->intoffset
= bitpos
;
5127 /* Update the data in CUM to advance over an argument
5128 of mode MODE and data type TYPE.
5129 (TYPE is null for libcalls where that information may not be available.)
5131 Note that for args passed by reference, function_arg will be called
5132 with MODE and TYPE set to that of the pointer to the arg, not the arg
5136 function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5137 tree type
, int named
, int depth
)
5141 /* Only tick off an argument if we're not recursing. */
5143 cum
->nargs_prototype
--;
5145 if (TARGET_ALTIVEC_ABI
5146 && (ALTIVEC_VECTOR_MODE (mode
)
5147 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
5148 && int_size_in_bytes (type
) == 16)))
5152 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
5155 if (!TARGET_ALTIVEC
)
5156 error ("cannot pass argument in vector register because"
5157 " altivec instructions are disabled, use -maltivec"
5160 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
5161 even if it is going to be passed in a vector register.
5162 Darwin does the same for variable-argument functions. */
5163 if ((DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
5164 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
5174 /* Vector parameters must be 16-byte aligned. This places
5175 them at 2 mod 4 in terms of words in 32-bit mode, since
5176 the parameter save area starts at offset 24 from the
5177 stack. In 64-bit mode, they just have to start on an
5178 even word, since the parameter save area is 16-byte
5179 aligned. Space for GPRs is reserved even if the argument
5180 will be passed in memory. */
5182 align
= (2 - cum
->words
) & 3;
5184 align
= cum
->words
& 1;
5185 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
5187 if (TARGET_DEBUG_ARG
)
5189 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
5191 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
5192 cum
->nargs_prototype
, cum
->prototype
,
5193 GET_MODE_NAME (mode
));
5197 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
5199 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
5202 else if (rs6000_darwin64_abi
5204 && TREE_CODE (type
) == RECORD_TYPE
5205 && (size
= int_size_in_bytes (type
)) > 0)
5207 /* Variable sized types have size == -1 and are
5208 treated as if consisting entirely of ints.
5209 Pad to 16 byte boundary if needed. */
5210 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
5211 && (cum
->words
% 2) != 0)
5213 /* For varargs, we can just go up by the size of the struct. */
5215 cum
->words
+= (size
+ 7) / 8;
5218 /* It is tempting to say int register count just goes up by
5219 sizeof(type)/8, but this is wrong in a case such as
5220 { int; double; int; } [powerpc alignment]. We have to
5221 grovel through the fields for these too. */
5223 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
5224 rs6000_darwin64_record_arg_advance_flush (cum
,
5225 size
* BITS_PER_UNIT
);
5228 else if (DEFAULT_ABI
== ABI_V4
)
5230 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
5231 && (mode
== SFmode
|| mode
== DFmode
5232 || mode
== DDmode
|| mode
== TDmode
5233 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)))
5235 /* _Decimal128 must use an even/odd register pair. This assumes
5236 that the register number is odd when fregno is odd. */
5237 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
5240 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
5241 <= FP_ARG_V4_MAX_REG
)
5242 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
5245 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
5246 if (mode
== DFmode
|| mode
== TFmode
|| mode
== DDmode
|| mode
== TDmode
)
5247 cum
->words
+= cum
->words
& 1;
5248 cum
->words
+= rs6000_arg_size (mode
, type
);
5253 int n_words
= rs6000_arg_size (mode
, type
);
5254 int gregno
= cum
->sysv_gregno
;
5256 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5257 (r7,r8) or (r9,r10). As does any other 2 word item such
5258 as complex int due to a historical mistake. */
5260 gregno
+= (1 - gregno
) & 1;
5262 /* Multi-reg args are not split between registers and stack. */
5263 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
5265 /* Long long and SPE vectors are aligned on the stack.
5266 So are other 2 word items such as complex int due to
5267 a historical mistake. */
5269 cum
->words
+= cum
->words
& 1;
5270 cum
->words
+= n_words
;
5273 /* Note: continuing to accumulate gregno past when we've started
5274 spilling to the stack indicates the fact that we've started
5275 spilling to the stack to expand_builtin_saveregs. */
5276 cum
->sysv_gregno
= gregno
+ n_words
;
5279 if (TARGET_DEBUG_ARG
)
5281 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
5282 cum
->words
, cum
->fregno
);
5283 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
5284 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
5285 fprintf (stderr
, "mode = %4s, named = %d\n",
5286 GET_MODE_NAME (mode
), named
);
5291 int n_words
= rs6000_arg_size (mode
, type
);
5292 int start_words
= cum
->words
;
5293 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
5295 cum
->words
= align_words
+ n_words
;
5297 if (SCALAR_FLOAT_MODE_P (mode
)
5299 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
5301 /* _Decimal128 must be passed in an even/odd float register pair.
5302 This assumes that the register number is odd when fregno is
5304 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
5306 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
5309 if (TARGET_DEBUG_ARG
)
5311 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
5312 cum
->words
, cum
->fregno
);
5313 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
5314 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
5315 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
5316 named
, align_words
- start_words
, depth
);
5322 spe_build_register_parallel (enum machine_mode mode
, int gregno
)
5329 r1
= gen_rtx_REG (DImode
, gregno
);
5330 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
5331 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
5335 r1
= gen_rtx_REG (DImode
, gregno
);
5336 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
5337 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
5338 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
5339 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
5342 r1
= gen_rtx_REG (DImode
, gregno
);
5343 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
5344 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
5345 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
5346 r5
= gen_rtx_REG (DImode
, gregno
+ 4);
5347 r5
= gen_rtx_EXPR_LIST (VOIDmode
, r5
, GEN_INT (16));
5348 r7
= gen_rtx_REG (DImode
, gregno
+ 6);
5349 r7
= gen_rtx_EXPR_LIST (VOIDmode
, r7
, GEN_INT (24));
5350 return gen_rtx_PARALLEL (mode
, gen_rtvec (4, r1
, r3
, r5
, r7
));
5357 /* Determine where to put a SIMD argument on the SPE. */
5359 rs6000_spe_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5362 int gregno
= cum
->sysv_gregno
;
5364 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5365 are passed and returned in a pair of GPRs for ABI compatibility. */
5366 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== DCmode
5367 || mode
== TFmode
|| mode
== TCmode
))
5369 int n_words
= rs6000_arg_size (mode
, type
);
5371 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5373 gregno
+= (1 - gregno
) & 1;
5375 /* Multi-reg args are not split between registers and stack. */
5376 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
5379 return spe_build_register_parallel (mode
, gregno
);
5383 int n_words
= rs6000_arg_size (mode
, type
);
5385 /* SPE vectors are put in odd registers. */
5386 if (n_words
== 2 && (gregno
& 1) == 0)
5389 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
5392 enum machine_mode m
= SImode
;
5394 r1
= gen_rtx_REG (m
, gregno
);
5395 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
5396 r2
= gen_rtx_REG (m
, gregno
+ 1);
5397 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
5398 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
5405 if (gregno
<= GP_ARG_MAX_REG
)
5406 return gen_rtx_REG (mode
, gregno
);
5412 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
5413 structure between cum->intoffset and bitpos to integer registers. */
5416 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
5417 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
5419 enum machine_mode mode
;
5421 unsigned int startbit
, endbit
;
5422 int this_regno
, intregs
, intoffset
;
5425 if (cum
->intoffset
== -1)
5428 intoffset
= cum
->intoffset
;
5429 cum
->intoffset
= -1;
5431 /* If this is the trailing part of a word, try to only load that
5432 much into the register. Otherwise load the whole register. Note
5433 that in the latter case we may pick up unwanted bits. It's not a
5434 problem at the moment but may wish to revisit. */
5436 if (intoffset
% BITS_PER_WORD
!= 0)
5438 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
5440 if (mode
== BLKmode
)
5442 /* We couldn't find an appropriate mode, which happens,
5443 e.g., in packed structs when there are 3 bytes to load.
5444 Back intoffset back to the beginning of the word in this
5446 intoffset
= intoffset
& -BITS_PER_WORD
;
5453 startbit
= intoffset
& -BITS_PER_WORD
;
5454 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5455 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
5456 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
5458 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
5461 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
5465 intoffset
/= BITS_PER_UNIT
;
5468 regno
= GP_ARG_MIN_REG
+ this_regno
;
5469 reg
= gen_rtx_REG (mode
, regno
);
5471 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
5474 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
5478 while (intregs
> 0);
5481 /* Recursive workhorse for the following. */
5484 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
5485 HOST_WIDE_INT startbitpos
, rtx rvec
[],
5490 for (f
= TYPE_FIELDS (type
); f
; f
= TREE_CHAIN (f
))
5491 if (TREE_CODE (f
) == FIELD_DECL
)
5493 HOST_WIDE_INT bitpos
= startbitpos
;
5494 tree ftype
= TREE_TYPE (f
);
5495 enum machine_mode mode
;
5496 if (ftype
== error_mark_node
)
5498 mode
= TYPE_MODE (ftype
);
5500 if (DECL_SIZE (f
) != 0
5501 && host_integerp (bit_position (f
), 1))
5502 bitpos
+= int_bit_position (f
);
5504 /* ??? FIXME: else assume zero offset. */
5506 if (TREE_CODE (ftype
) == RECORD_TYPE
)
5507 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
5508 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
5513 case SCmode
: mode
= SFmode
; break;
5514 case DCmode
: mode
= DFmode
; break;
5515 case TCmode
: mode
= TFmode
; break;
5519 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
5521 = gen_rtx_EXPR_LIST (VOIDmode
,
5522 gen_rtx_REG (mode
, cum
->fregno
++),
5523 GEN_INT (bitpos
/ BITS_PER_UNIT
));
5524 if (mode
== TFmode
|| mode
== TDmode
)
5527 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, ftype
, 1))
5529 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
5531 = gen_rtx_EXPR_LIST (VOIDmode
,
5532 gen_rtx_REG (mode
, cum
->vregno
++),
5533 GEN_INT (bitpos
/ BITS_PER_UNIT
));
5535 else if (cum
->intoffset
== -1)
5536 cum
->intoffset
= bitpos
;
5540 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5541 the register(s) to be used for each field and subfield of a struct
5542 being passed by value, along with the offset of where the
5543 register's value may be found in the block. FP fields go in FP
5544 register, vector fields go in vector registers, and everything
5545 else goes in int registers, packed as in memory.
5547 This code is also used for function return values. RETVAL indicates
5548 whether this is the case.
5550 Much of this is taken from the SPARC V9 port, which has a similar
5551 calling convention. */
5554 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
5555 int named
, bool retval
)
5557 rtx rvec
[FIRST_PSEUDO_REGISTER
];
5558 int k
= 1, kbase
= 1;
5559 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
5560 /* This is a copy; modifications are not visible to our caller. */
5561 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
5562 CUMULATIVE_ARGS
*cum
= ©_cum
;
5564 /* Pad to 16 byte boundary if needed. */
5565 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
5566 && (cum
->words
% 2) != 0)
5573 /* Put entries into rvec[] for individual FP and vector fields, and
5574 for the chunks of memory that go in int regs. Note we start at
5575 element 1; 0 is reserved for an indication of using memory, and
5576 may or may not be filled in below. */
5577 rs6000_darwin64_record_arg_recurse (cum
, type
, 0, rvec
, &k
);
5578 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
5580 /* If any part of the struct went on the stack put all of it there.
5581 This hack is because the generic code for
5582 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
5583 parts of the struct are not at the beginning. */
5587 return NULL_RTX
; /* doesn't go in registers at all */
5589 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5591 if (k
> 1 || cum
->use_stack
)
5592 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
5597 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5600 rs6000_mixed_function_arg (enum machine_mode mode
, tree type
, int align_words
)
5604 rtx rvec
[GP_ARG_NUM_REG
+ 1];
5606 if (align_words
>= GP_ARG_NUM_REG
)
5609 n_units
= rs6000_arg_size (mode
, type
);
5611 /* Optimize the simple case where the arg fits in one gpr, except in
5612 the case of BLKmode due to assign_parms assuming that registers are
5613 BITS_PER_WORD wide. */
5615 || (n_units
== 1 && mode
!= BLKmode
))
5616 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
5619 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
5620 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5621 using a magic NULL_RTX component.
5622 This is not strictly correct. Only some of the arg belongs in
5623 memory, not all of it. However, the normal scheme using
5624 function_arg_partial_nregs can result in unusual subregs, eg.
5625 (subreg:SI (reg:DF) 4), which are not handled well. The code to
5626 store the whole arg to memory is often more efficient than code
5627 to store pieces, and we know that space is available in the right
5628 place for the whole arg. */
5629 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5634 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
5635 rtx off
= GEN_INT (i
++ * 4);
5636 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
5638 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
5640 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
5643 /* Determine where to put an argument to a function.
5644 Value is zero to push the argument on the stack,
5645 or a hard register in which to store the argument.
5647 MODE is the argument's machine mode.
5648 TYPE is the data type of the argument (as a tree).
5649 This is null for libcalls where that information may
5651 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5652 the preceding args and about the function being called. It is
5653 not modified in this routine.
5654 NAMED is nonzero if this argument is a named parameter
5655 (otherwise it is an extra parameter matching an ellipsis).
5657 On RS/6000 the first eight words of non-FP are normally in registers
5658 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5659 Under V.4, the first 8 FP args are in registers.
5661 If this is floating-point and no prototype is specified, we use
5662 both an FP and integer register (or possibly FP reg and stack). Library
5663 functions (when CALL_LIBCALL is set) always have the proper types for args,
5664 so we can pass the FP value just in one register. emit_library_function
5665 doesn't support PARALLEL anyway.
5667 Note that for args passed by reference, function_arg will be called
5668 with MODE and TYPE set to that of the pointer to the arg, not the arg
5672 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5673 tree type
, int named
)
5675 enum rs6000_abi abi
= DEFAULT_ABI
;
5677 /* Return a marker to indicate whether CR1 needs to set or clear the
5678 bit that V.4 uses to say fp args were passed in registers.
5679 Assume that we don't need the marker for software floating point,
5680 or compiler generated library calls. */
5681 if (mode
== VOIDmode
)
5684 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
5686 || (cum
->nargs_prototype
< 0
5687 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))))
5689 /* For the SPE, we need to crxor CR6 always. */
5691 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
5692 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
5693 return GEN_INT (cum
->call_cookie
5694 | ((cum
->fregno
== FP_ARG_MIN_REG
)
5695 ? CALL_V4_SET_FP_ARGS
5696 : CALL_V4_CLEAR_FP_ARGS
));
5699 return GEN_INT (cum
->call_cookie
);
5702 if (rs6000_darwin64_abi
&& mode
== BLKmode
5703 && TREE_CODE (type
) == RECORD_TYPE
)
5705 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, false);
5706 if (rslt
!= NULL_RTX
)
5708 /* Else fall through to usual handling. */
5711 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
5712 if (TARGET_64BIT
&& ! cum
->prototype
)
5714 /* Vector parameters get passed in vector register
5715 and also in GPRs or memory, in absence of prototype. */
5718 align_words
= (cum
->words
+ 1) & ~1;
5720 if (align_words
>= GP_ARG_NUM_REG
)
5726 slot
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
5728 return gen_rtx_PARALLEL (mode
,
5730 gen_rtx_EXPR_LIST (VOIDmode
,
5732 gen_rtx_EXPR_LIST (VOIDmode
,
5733 gen_rtx_REG (mode
, cum
->vregno
),
5737 return gen_rtx_REG (mode
, cum
->vregno
);
5738 else if (TARGET_ALTIVEC_ABI
5739 && (ALTIVEC_VECTOR_MODE (mode
)
5740 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
5741 && int_size_in_bytes (type
) == 16)))
5743 if (named
|| abi
== ABI_V4
)
5747 /* Vector parameters to varargs functions under AIX or Darwin
5748 get passed in memory and possibly also in GPRs. */
5749 int align
, align_words
, n_words
;
5750 enum machine_mode part_mode
;
5752 /* Vector parameters must be 16-byte aligned. This places them at
5753 2 mod 4 in terms of words in 32-bit mode, since the parameter
5754 save area starts at offset 24 from the stack. In 64-bit mode,
5755 they just have to start on an even word, since the parameter
5756 save area is 16-byte aligned. */
5758 align
= (2 - cum
->words
) & 3;
5760 align
= cum
->words
& 1;
5761 align_words
= cum
->words
+ align
;
5763 /* Out of registers? Memory, then. */
5764 if (align_words
>= GP_ARG_NUM_REG
)
5767 if (TARGET_32BIT
&& TARGET_POWERPC64
)
5768 return rs6000_mixed_function_arg (mode
, type
, align_words
);
5770 /* The vector value goes in GPRs. Only the part of the
5771 value in GPRs is reported here. */
5773 n_words
= rs6000_arg_size (mode
, type
);
5774 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
5775 /* Fortunately, there are only two possibilities, the value
5776 is either wholly in GPRs or half in GPRs and half not. */
5779 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
5782 else if (TARGET_SPE_ABI
&& TARGET_SPE
5783 && (SPE_VECTOR_MODE (mode
)
5784 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
5789 || mode
== TCmode
))))
5790 return rs6000_spe_function_arg (cum
, mode
, type
);
5792 else if (abi
== ABI_V4
)
5794 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
5795 && (mode
== SFmode
|| mode
== DFmode
5796 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
5797 || mode
== DDmode
|| mode
== TDmode
))
5799 /* _Decimal128 must use an even/odd register pair. This assumes
5800 that the register number is odd when fregno is odd. */
5801 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
5804 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
5805 <= FP_ARG_V4_MAX_REG
)
5806 return gen_rtx_REG (mode
, cum
->fregno
);
5812 int n_words
= rs6000_arg_size (mode
, type
);
5813 int gregno
= cum
->sysv_gregno
;
5815 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5816 (r7,r8) or (r9,r10). As does any other 2 word item such
5817 as complex int due to a historical mistake. */
5819 gregno
+= (1 - gregno
) & 1;
5821 /* Multi-reg args are not split between registers and stack. */
5822 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
5825 if (TARGET_32BIT
&& TARGET_POWERPC64
)
5826 return rs6000_mixed_function_arg (mode
, type
,
5827 gregno
- GP_ARG_MIN_REG
);
5828 return gen_rtx_REG (mode
, gregno
);
5833 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
5835 /* _Decimal128 must be passed in an even/odd float register pair.
5836 This assumes that the register number is odd when fregno is odd. */
5837 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
5840 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
5842 rtx rvec
[GP_ARG_NUM_REG
+ 1];
5846 enum machine_mode fmode
= mode
;
5847 unsigned long n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
5849 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
5851 /* Currently, we only ever need one reg here because complex
5852 doubles are split. */
5853 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
5854 && (fmode
== TFmode
|| fmode
== TDmode
));
5856 /* Long double or _Decimal128 split over regs and memory. */
5857 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
5860 /* Do we also need to pass this arg in the parameter save
5863 && (cum
->nargs_prototype
<= 0
5864 || (DEFAULT_ABI
== ABI_AIX
5866 && align_words
>= GP_ARG_NUM_REG
)));
5868 if (!needs_psave
&& mode
== fmode
)
5869 return gen_rtx_REG (fmode
, cum
->fregno
);
5874 /* Describe the part that goes in gprs or the stack.
5875 This piece must come first, before the fprs. */
5876 if (align_words
< GP_ARG_NUM_REG
)
5878 unsigned long n_words
= rs6000_arg_size (mode
, type
);
5880 if (align_words
+ n_words
> GP_ARG_NUM_REG
5881 || (TARGET_32BIT
&& TARGET_POWERPC64
))
5883 /* If this is partially on the stack, then we only
5884 include the portion actually in registers here. */
5885 enum machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
5888 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
5889 /* Not all of the arg fits in gprs. Say that it
5890 goes in memory too, using a magic NULL_RTX
5891 component. Also see comment in
5892 rs6000_mixed_function_arg for why the normal
5893 function_arg_partial_nregs scheme doesn't work
5895 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
,
5899 r
= gen_rtx_REG (rmode
,
5900 GP_ARG_MIN_REG
+ align_words
);
5901 off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
5902 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
5904 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
5908 /* The whole arg fits in gprs. */
5909 r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
5910 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
5914 /* It's entirely in memory. */
5915 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5918 /* Describe where this piece goes in the fprs. */
5919 r
= gen_rtx_REG (fmode
, cum
->fregno
);
5920 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
5922 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
5924 else if (align_words
< GP_ARG_NUM_REG
)
5926 if (TARGET_32BIT
&& TARGET_POWERPC64
)
5927 return rs6000_mixed_function_arg (mode
, type
, align_words
);
5929 if (mode
== BLKmode
)
5932 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
5939 /* For an arg passed partly in registers and partly in memory, this is
5940 the number of bytes passed in registers. For args passed entirely in
5941 registers or entirely in memory, zero. When an arg is described by a
5942 PARALLEL, perhaps using more than one register type, this function
5943 returns the number of bytes used by the first element of the PARALLEL. */
5946 rs6000_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5947 tree type
, bool named
)
5952 if (DEFAULT_ABI
== ABI_V4
)
5955 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
)
5956 && cum
->nargs_prototype
>= 0)
5959 /* In this complicated case we just disable the partial_nregs code. */
5960 if (rs6000_darwin64_abi
&& mode
== BLKmode
5961 && TREE_CODE (type
) == RECORD_TYPE
5962 && int_size_in_bytes (type
) > 0)
5965 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
5967 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
5969 /* If we are passing this arg in the fixed parameter save area
5970 (gprs or memory) as well as fprs, then this function should
5971 return the number of partial bytes passed in the parameter
5972 save area rather than partial bytes passed in fprs. */
5974 && (cum
->nargs_prototype
<= 0
5975 || (DEFAULT_ABI
== ABI_AIX
5977 && align_words
>= GP_ARG_NUM_REG
)))
5979 else if (cum
->fregno
+ ((GET_MODE_SIZE (mode
) + 7) >> 3)
5980 > FP_ARG_MAX_REG
+ 1)
5981 ret
= (FP_ARG_MAX_REG
+ 1 - cum
->fregno
) * 8;
5982 else if (cum
->nargs_prototype
>= 0)
5986 if (align_words
< GP_ARG_NUM_REG
5987 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
5988 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
5990 if (ret
!= 0 && TARGET_DEBUG_ARG
)
5991 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
5996 /* A C expression that indicates when an argument must be passed by
5997 reference. If nonzero for an argument, a copy of that argument is
5998 made in memory and a pointer to the argument is passed instead of
5999 the argument itself. The pointer is passed in whatever way is
6000 appropriate for passing a pointer to that type.
6002 Under V.4, aggregates and long double are passed by reference.
6004 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
6005 reference unless the AltiVec vector extension ABI is in force.
6007 As an extension to all ABIs, variable sized types are passed by
6011 rs6000_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
6012 enum machine_mode mode
, const_tree type
,
6013 bool named ATTRIBUTE_UNUSED
)
6015 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& mode
== TFmode
)
6017 if (TARGET_DEBUG_ARG
)
6018 fprintf (stderr
, "function_arg_pass_by_reference: V4 long double\n");
6025 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
6027 if (TARGET_DEBUG_ARG
)
6028 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
6032 if (int_size_in_bytes (type
) < 0)
6034 if (TARGET_DEBUG_ARG
)
6035 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
6039 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
6040 modes only exist for GCC vector types if -maltivec. */
6041 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
6043 if (TARGET_DEBUG_ARG
)
6044 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
6048 /* Pass synthetic vectors in memory. */
6049 if (TREE_CODE (type
) == VECTOR_TYPE
6050 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
6052 static bool warned_for_pass_big_vectors
= false;
6053 if (TARGET_DEBUG_ARG
)
6054 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
6055 if (!warned_for_pass_big_vectors
)
6057 warning (0, "GCC vector passed by reference: "
6058 "non-standard ABI extension with no compatibility guarantee");
6059 warned_for_pass_big_vectors
= true;
6068 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
6071 enum machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
6076 for (i
= 0; i
< nregs
; i
++)
6078 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
6079 if (reload_completed
)
6081 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
6084 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
6085 i
* GET_MODE_SIZE (reg_mode
));
6088 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
6092 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
6096 /* Perform any needed actions needed for a function that is receiving a
6097 variable number of arguments.
6101 MODE and TYPE are the mode and type of the current parameter.
6103 PRETEND_SIZE is a variable that should be set to the amount of stack
6104 that must be pushed by the prolog to pretend that our caller pushed
6107 Normally, this macro will push all remaining incoming registers on the
6108 stack and set PRETEND_SIZE to the length of the registers pushed. */
6111 setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
6112 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
6115 CUMULATIVE_ARGS next_cum
;
6116 int reg_size
= TARGET_32BIT
? 4 : 8;
6117 rtx save_area
= NULL_RTX
, mem
;
6118 int first_reg_offset
;
6121 /* Skip the last named argument. */
6123 function_arg_advance (&next_cum
, mode
, type
, 1, 0);
6125 if (DEFAULT_ABI
== ABI_V4
)
6127 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
6131 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
6132 HOST_WIDE_INT offset
= 0;
6134 /* Try to optimize the size of the varargs save area.
6135 The ABI requires that ap.reg_save_area is doubleword
6136 aligned, but we don't need to allocate space for all
6137 the bytes, only those to which we actually will save
6139 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
6140 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
6141 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
6142 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
6143 && cfun
->va_list_fpr_size
)
6146 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
6147 * UNITS_PER_FP_WORD
;
6148 if (cfun
->va_list_fpr_size
6149 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
6150 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
6152 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
6153 * UNITS_PER_FP_WORD
;
6157 offset
= -((first_reg_offset
* reg_size
) & ~7);
6158 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
6160 gpr_reg_num
= cfun
->va_list_gpr_size
;
6161 if (reg_size
== 4 && (first_reg_offset
& 1))
6164 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
6167 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
6169 - (int) (GP_ARG_NUM_REG
* reg_size
);
6171 if (gpr_size
+ fpr_size
)
6174 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
6175 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
6176 reg_save_area
= XEXP (reg_save_area
, 0);
6177 if (GET_CODE (reg_save_area
) == PLUS
)
6179 gcc_assert (XEXP (reg_save_area
, 0)
6180 == virtual_stack_vars_rtx
);
6181 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
6182 offset
+= INTVAL (XEXP (reg_save_area
, 1));
6185 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
6188 cfun
->machine
->varargs_save_offset
= offset
;
6189 save_area
= plus_constant (virtual_stack_vars_rtx
, offset
);
6194 first_reg_offset
= next_cum
.words
;
6195 save_area
= virtual_incoming_args_rtx
;
6197 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
6198 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
6201 set
= get_varargs_alias_set ();
6202 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
6203 && cfun
->va_list_gpr_size
)
6205 int nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
6207 if (va_list_gpr_counter_field
)
6209 /* V4 va_list_gpr_size counts number of registers needed. */
6210 if (nregs
> cfun
->va_list_gpr_size
)
6211 nregs
= cfun
->va_list_gpr_size
;
6215 /* char * va_list instead counts number of bytes needed. */
6216 if (nregs
> cfun
->va_list_gpr_size
/ reg_size
)
6217 nregs
= cfun
->va_list_gpr_size
/ reg_size
;
6220 mem
= gen_rtx_MEM (BLKmode
,
6221 plus_constant (save_area
,
6222 first_reg_offset
* reg_size
));
6223 MEM_NOTRAP_P (mem
) = 1;
6224 set_mem_alias_set (mem
, set
);
6225 set_mem_align (mem
, BITS_PER_WORD
);
6227 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
6231 /* Save FP registers if needed. */
6232 if (DEFAULT_ABI
== ABI_V4
6233 && TARGET_HARD_FLOAT
&& TARGET_FPRS
6235 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
6236 && cfun
->va_list_fpr_size
)
6238 int fregno
= next_cum
.fregno
, nregs
;
6239 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
6240 rtx lab
= gen_label_rtx ();
6241 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
6242 * UNITS_PER_FP_WORD
);
6245 (gen_rtx_SET (VOIDmode
,
6247 gen_rtx_IF_THEN_ELSE (VOIDmode
,
6248 gen_rtx_NE (VOIDmode
, cr1
,
6250 gen_rtx_LABEL_REF (VOIDmode
, lab
),
6254 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
6255 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
6257 mem
= gen_rtx_MEM (DFmode
, plus_constant (save_area
, off
));
6258 MEM_NOTRAP_P (mem
) = 1;
6259 set_mem_alias_set (mem
, set
);
6260 set_mem_align (mem
, GET_MODE_ALIGNMENT (DFmode
));
6261 emit_move_insn (mem
, gen_rtx_REG (DFmode
, fregno
));
6268 /* Create the va_list data type. */
6271 rs6000_build_builtin_va_list (void)
6273 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
6275 /* For AIX, prefer 'char *' because that's what the system
6276 header files like. */
6277 if (DEFAULT_ABI
!= ABI_V4
)
6278 return build_pointer_type (char_type_node
);
6280 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
6281 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
6283 f_gpr
= build_decl (FIELD_DECL
, get_identifier ("gpr"),
6284 unsigned_char_type_node
);
6285 f_fpr
= build_decl (FIELD_DECL
, get_identifier ("fpr"),
6286 unsigned_char_type_node
);
6287 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
6289 f_res
= build_decl (FIELD_DECL
, get_identifier ("reserved"),
6290 short_unsigned_type_node
);
6291 f_ovf
= build_decl (FIELD_DECL
, get_identifier ("overflow_arg_area"),
6293 f_sav
= build_decl (FIELD_DECL
, get_identifier ("reg_save_area"),
6296 va_list_gpr_counter_field
= f_gpr
;
6297 va_list_fpr_counter_field
= f_fpr
;
6299 DECL_FIELD_CONTEXT (f_gpr
) = record
;
6300 DECL_FIELD_CONTEXT (f_fpr
) = record
;
6301 DECL_FIELD_CONTEXT (f_res
) = record
;
6302 DECL_FIELD_CONTEXT (f_ovf
) = record
;
6303 DECL_FIELD_CONTEXT (f_sav
) = record
;
6305 TREE_CHAIN (record
) = type_decl
;
6306 TYPE_NAME (record
) = type_decl
;
6307 TYPE_FIELDS (record
) = f_gpr
;
6308 TREE_CHAIN (f_gpr
) = f_fpr
;
6309 TREE_CHAIN (f_fpr
) = f_res
;
6310 TREE_CHAIN (f_res
) = f_ovf
;
6311 TREE_CHAIN (f_ovf
) = f_sav
;
6313 layout_type (record
);
6315 /* The correct type is an array type of one element. */
6316 return build_array_type (record
, build_index_type (size_zero_node
));
6319 /* Implement va_start. */
6322 rs6000_va_start (tree valist
, rtx nextarg
)
6324 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
6325 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
6326 tree gpr
, fpr
, ovf
, sav
, t
;
6328 /* Only SVR4 needs something special. */
6329 if (DEFAULT_ABI
!= ABI_V4
)
6331 std_expand_builtin_va_start (valist
, nextarg
);
6335 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
6336 f_fpr
= TREE_CHAIN (f_gpr
);
6337 f_res
= TREE_CHAIN (f_fpr
);
6338 f_ovf
= TREE_CHAIN (f_res
);
6339 f_sav
= TREE_CHAIN (f_ovf
);
6341 valist
= build_va_arg_indirect_ref (valist
);
6342 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
6343 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
6344 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
6345 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
6347 /* Count number of gp and fp argument registers used. */
6348 words
= current_function_args_info
.words
;
6349 n_gpr
= MIN (current_function_args_info
.sysv_gregno
- GP_ARG_MIN_REG
,
6351 n_fpr
= MIN (current_function_args_info
.fregno
- FP_ARG_MIN_REG
,
6354 if (TARGET_DEBUG_ARG
)
6355 fprintf (stderr
, "va_start: words = "HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
6356 HOST_WIDE_INT_PRINT_DEC
", n_fpr = "HOST_WIDE_INT_PRINT_DEC
"\n",
6357 words
, n_gpr
, n_fpr
);
6359 if (cfun
->va_list_gpr_size
)
6361 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (gpr
), gpr
,
6362 build_int_cst (NULL_TREE
, n_gpr
));
6363 TREE_SIDE_EFFECTS (t
) = 1;
6364 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6367 if (cfun
->va_list_fpr_size
)
6369 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (fpr
), fpr
,
6370 build_int_cst (NULL_TREE
, n_fpr
));
6371 TREE_SIDE_EFFECTS (t
) = 1;
6372 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6375 /* Find the overflow area. */
6376 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
6378 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovf
), t
,
6379 size_int (words
* UNITS_PER_WORD
));
6380 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (ovf
), ovf
, t
);
6381 TREE_SIDE_EFFECTS (t
) = 1;
6382 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6384 /* If there were no va_arg invocations, don't set up the register
6386 if (!cfun
->va_list_gpr_size
6387 && !cfun
->va_list_fpr_size
6388 && n_gpr
< GP_ARG_NUM_REG
6389 && n_fpr
< FP_ARG_V4_MAX_REG
)
6392 /* Find the register save area. */
6393 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
6394 if (cfun
->machine
->varargs_save_offset
)
6395 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (sav
), t
,
6396 size_int (cfun
->machine
->varargs_save_offset
));
6397 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (sav
), sav
, t
);
6398 TREE_SIDE_EFFECTS (t
) = 1;
6399 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6402 /* Implement va_arg. */
6405 rs6000_gimplify_va_arg (tree valist
, tree type
, tree
*pre_p
, tree
*post_p
)
6407 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
6408 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
6409 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
6410 tree lab_false
, lab_over
, addr
;
6412 tree ptrtype
= build_pointer_type (type
);
6415 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
6417 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
6418 return build_va_arg_indirect_ref (t
);
6421 if (DEFAULT_ABI
!= ABI_V4
)
6423 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
6425 tree elem_type
= TREE_TYPE (type
);
6426 enum machine_mode elem_mode
= TYPE_MODE (elem_type
);
6427 int elem_size
= GET_MODE_SIZE (elem_mode
);
6429 if (elem_size
< UNITS_PER_WORD
)
6431 tree real_part
, imag_part
;
6432 tree post
= NULL_TREE
;
6434 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
6436 /* Copy the value into a temporary, lest the formal temporary
6437 be reused out from under us. */
6438 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
6439 append_to_statement_list (post
, pre_p
);
6441 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
6444 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
6448 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
6451 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
6452 f_fpr
= TREE_CHAIN (f_gpr
);
6453 f_res
= TREE_CHAIN (f_fpr
);
6454 f_ovf
= TREE_CHAIN (f_res
);
6455 f_sav
= TREE_CHAIN (f_ovf
);
6457 valist
= build_va_arg_indirect_ref (valist
);
6458 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
6459 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
6460 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
6461 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
6463 size
= int_size_in_bytes (type
);
6464 rsize
= (size
+ 3) / 4;
6467 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
6468 && (TYPE_MODE (type
) == SFmode
6469 || TYPE_MODE (type
) == DFmode
6470 || TYPE_MODE (type
) == TFmode
6471 || TYPE_MODE (type
) == DDmode
6472 || TYPE_MODE (type
) == TDmode
))
6474 /* FP args go in FP registers, if present. */
6476 n_reg
= (size
+ 7) / 8;
6479 if (TYPE_MODE (type
) != SFmode
)
6484 /* Otherwise into GP registers. */
6493 /* Pull the value out of the saved registers.... */
6496 addr
= create_tmp_var (ptr_type_node
, "addr");
6497 DECL_POINTER_ALIAS_SET (addr
) = get_varargs_alias_set ();
6499 /* AltiVec vectors never go in registers when -mabi=altivec. */
6500 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
6504 lab_false
= create_artificial_label ();
6505 lab_over
= create_artificial_label ();
6507 /* Long long and SPE vectors are aligned in the registers.
6508 As are any other 2 gpr item such as complex int due to a
6509 historical mistake. */
6511 if (n_reg
== 2 && reg
== gpr
)
6514 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), reg
,
6515 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
6516 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), reg
, u
);
6518 /* _Decimal128 is passed in even/odd fpr pairs; the stored
6519 reg number is 0 for f1, so we want to make it odd. */
6520 else if (reg
== fpr
&& TYPE_MODE (type
) == TDmode
)
6523 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), reg
, size_int (1));
6524 u
= build2 (MODIFY_EXPR
, void_type_node
, reg
, t
);
6527 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
6528 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
6529 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
6530 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
6531 gimplify_and_add (t
, pre_p
);
6535 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, sav
, size_int (sav_ofs
));
6537 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), reg
,
6538 build_int_cst (TREE_TYPE (reg
), n_reg
));
6539 u
= fold_convert (sizetype
, u
);
6540 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
6541 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
, u
);
6543 t
= build2 (GIMPLE_MODIFY_STMT
, void_type_node
, addr
, t
);
6544 gimplify_and_add (t
, pre_p
);
6546 t
= build1 (GOTO_EXPR
, void_type_node
, lab_over
);
6547 gimplify_and_add (t
, pre_p
);
6549 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false
);
6550 append_to_statement_list (t
, pre_p
);
6552 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
6554 /* Ensure that we don't find any more args in regs.
6555 Alignment has taken care of for special cases. */
6556 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (reg
), reg
, size_int (8));
6557 gimplify_and_add (t
, pre_p
);
6561 /* ... otherwise out of the overflow area. */
6563 /* Care for on-stack alignment if needed. */
6567 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, size_int (align
- 1));
6568 t
= fold_convert (sizetype
, t
);
6569 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
6571 t
= fold_convert (TREE_TYPE (ovf
), t
);
6573 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
6575 u
= build2 (GIMPLE_MODIFY_STMT
, void_type_node
, addr
, t
);
6576 gimplify_and_add (u
, pre_p
);
6578 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, size_int (size
));
6579 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (ovf
), ovf
, t
);
6580 gimplify_and_add (t
, pre_p
);
6584 t
= build1 (LABEL_EXPR
, void_type_node
, lab_over
);
6585 append_to_statement_list (t
, pre_p
);
6588 if (STRICT_ALIGNMENT
6589 && (TYPE_ALIGN (type
)
6590 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
6592 /* The value (of type complex double, for example) may not be
6593 aligned in memory in the saved registers, so copy via a
6594 temporary. (This is the same code as used for SPARC.) */
6595 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
6596 tree dest_addr
= build_fold_addr_expr (tmp
);
6598 tree copy
= build_call_expr (implicit_built_in_decls
[BUILT_IN_MEMCPY
],
6599 3, dest_addr
, addr
, size_int (rsize
* 4));
6601 gimplify_and_add (copy
, pre_p
);
6605 addr
= fold_convert (ptrtype
, addr
);
6606 return build_va_arg_indirect_ref (addr
);
6612 def_builtin (int mask
, const char *name
, tree type
, int code
)
6614 if ((mask
& target_flags
) || TARGET_PAIRED_FLOAT
)
6616 if (rs6000_builtin_decls
[code
])
6619 rs6000_builtin_decls
[code
] =
6620 add_builtin_function (name
, type
, code
, BUILT_IN_MD
,
6625 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6627 static const struct builtin_description bdesc_3arg
[] =
6629 { MASK_ALTIVEC
, CODE_FOR_altivec_vmaddfp
, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP
},
6630 { MASK_ALTIVEC
, CODE_FOR_altivec_vmhaddshs
, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS
},
6631 { MASK_ALTIVEC
, CODE_FOR_altivec_vmhraddshs
, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS
},
6632 { MASK_ALTIVEC
, CODE_FOR_altivec_vmladduhm
, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM
},
6633 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumubm
, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM
},
6634 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsummbm
, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM
},
6635 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumuhm
, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM
},
6636 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumshm
, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM
},
6637 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumuhs
, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS
},
6638 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumshs
, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS
},
6639 { MASK_ALTIVEC
, CODE_FOR_altivec_vnmsubfp
, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP
},
6640 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v4sf
, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF
},
6641 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v4si
, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI
},
6642 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v8hi
, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI
},
6643 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v16qi
, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI
},
6644 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v4sf
, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF
},
6645 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v4si
, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI
},
6646 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v8hi
, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI
},
6647 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v16qi
, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI
},
6648 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v16qi
, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI
},
6649 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v8hi
, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI
},
6650 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v4si
, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI
},
6651 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v4sf
, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF
},
6653 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD
},
6654 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS
},
6655 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD
},
6656 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS
},
6657 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM
},
6658 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM
},
6659 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM
},
6660 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM
},
6661 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM
},
6662 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS
},
6663 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS
},
6664 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS
},
6665 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB
},
6666 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM
},
6667 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL
},
6669 { 0, CODE_FOR_paired_msub
, "__builtin_paired_msub", PAIRED_BUILTIN_MSUB
},
6670 { 0, CODE_FOR_paired_madd
, "__builtin_paired_madd", PAIRED_BUILTIN_MADD
},
6671 { 0, CODE_FOR_paired_madds0
, "__builtin_paired_madds0", PAIRED_BUILTIN_MADDS0
},
6672 { 0, CODE_FOR_paired_madds1
, "__builtin_paired_madds1", PAIRED_BUILTIN_MADDS1
},
6673 { 0, CODE_FOR_paired_nmsub
, "__builtin_paired_nmsub", PAIRED_BUILTIN_NMSUB
},
6674 { 0, CODE_FOR_paired_nmadd
, "__builtin_paired_nmadd", PAIRED_BUILTIN_NMADD
},
6675 { 0, CODE_FOR_paired_sum0
, "__builtin_paired_sum0", PAIRED_BUILTIN_SUM0
},
6676 { 0, CODE_FOR_paired_sum1
, "__builtin_paired_sum1", PAIRED_BUILTIN_SUM1
},
6677 { 0, CODE_FOR_selv2sf4
, "__builtin_paired_selv2sf4", PAIRED_BUILTIN_SELV2SF4
},
6680 /* DST operations: void foo (void *, const int, const char). */
6682 static const struct builtin_description bdesc_dst
[] =
6684 { MASK_ALTIVEC
, CODE_FOR_altivec_dst
, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST
},
6685 { MASK_ALTIVEC
, CODE_FOR_altivec_dstt
, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT
},
6686 { MASK_ALTIVEC
, CODE_FOR_altivec_dstst
, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST
},
6687 { MASK_ALTIVEC
, CODE_FOR_altivec_dststt
, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT
},
6689 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST
},
6690 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT
},
6691 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST
},
6692 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT
}
6695 /* Simple binary operations: VECc = foo (VECa, VECb). */
6697 static struct builtin_description bdesc_2arg
[] =
6699 { MASK_ALTIVEC
, CODE_FOR_addv16qi3
, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM
},
6700 { MASK_ALTIVEC
, CODE_FOR_addv8hi3
, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM
},
6701 { MASK_ALTIVEC
, CODE_FOR_addv4si3
, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM
},
6702 { MASK_ALTIVEC
, CODE_FOR_addv4sf3
, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP
},
6703 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddcuw
, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW
},
6704 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddubs
, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS
},
6705 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddsbs
, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS
},
6706 { MASK_ALTIVEC
, CODE_FOR_altivec_vadduhs
, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS
},
6707 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddshs
, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS
},
6708 { MASK_ALTIVEC
, CODE_FOR_altivec_vadduws
, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS
},
6709 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddsws
, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS
},
6710 { MASK_ALTIVEC
, CODE_FOR_andv4si3
, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND
},
6711 { MASK_ALTIVEC
, CODE_FOR_andcv4si3
, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC
},
6712 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgub
, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB
},
6713 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsb
, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB
},
6714 { MASK_ALTIVEC
, CODE_FOR_altivec_vavguh
, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH
},
6715 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsh
, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH
},
6716 { MASK_ALTIVEC
, CODE_FOR_altivec_vavguw
, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW
},
6717 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsw
, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW
},
6718 { MASK_ALTIVEC
, CODE_FOR_altivec_vcfux
, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX
},
6719 { MASK_ALTIVEC
, CODE_FOR_altivec_vcfsx
, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX
},
6720 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpbfp
, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP
},
6721 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequb
, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB
},
6722 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequh
, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH
},
6723 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequw
, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW
},
6724 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpeqfp
, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP
},
6725 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgefp
, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP
},
6726 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtub
, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB
},
6727 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsb
, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB
},
6728 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtuh
, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH
},
6729 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsh
, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH
},
6730 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtuw
, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW
},
6731 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsw
, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW
},
6732 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtfp
, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP
},
6733 { MASK_ALTIVEC
, CODE_FOR_altivec_vctsxs
, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS
},
6734 { MASK_ALTIVEC
, CODE_FOR_altivec_vctuxs
, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS
},
6735 { MASK_ALTIVEC
, CODE_FOR_umaxv16qi3
, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB
},
6736 { MASK_ALTIVEC
, CODE_FOR_smaxv16qi3
, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB
},
6737 { MASK_ALTIVEC
, CODE_FOR_umaxv8hi3
, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH
},
6738 { MASK_ALTIVEC
, CODE_FOR_smaxv8hi3
, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH
},
6739 { MASK_ALTIVEC
, CODE_FOR_umaxv4si3
, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW
},
6740 { MASK_ALTIVEC
, CODE_FOR_smaxv4si3
, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW
},
6741 { MASK_ALTIVEC
, CODE_FOR_smaxv4sf3
, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP
},
6742 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghb
, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB
},
6743 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghh
, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH
},
6744 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghw
, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW
},
6745 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglb
, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB
},
6746 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglh
, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH
},
6747 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglw
, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW
},
6748 { MASK_ALTIVEC
, CODE_FOR_uminv16qi3
, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB
},
6749 { MASK_ALTIVEC
, CODE_FOR_sminv16qi3
, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB
},
6750 { MASK_ALTIVEC
, CODE_FOR_uminv8hi3
, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH
},
6751 { MASK_ALTIVEC
, CODE_FOR_sminv8hi3
, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH
},
6752 { MASK_ALTIVEC
, CODE_FOR_uminv4si3
, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW
},
6753 { MASK_ALTIVEC
, CODE_FOR_sminv4si3
, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW
},
6754 { MASK_ALTIVEC
, CODE_FOR_sminv4sf3
, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP
},
6755 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuleub
, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB
},
6756 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulesb
, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB
},
6757 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuleuh
, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH
},
6758 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulesh
, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH
},
6759 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuloub
, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB
},
6760 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulosb
, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB
},
6761 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulouh
, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH
},
6762 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulosh
, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH
},
6763 { MASK_ALTIVEC
, CODE_FOR_altivec_norv4si3
, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR
},
6764 { MASK_ALTIVEC
, CODE_FOR_iorv4si3
, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR
},
6765 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum
, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM
},
6766 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum
, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM
},
6767 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkpx
, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX
},
6768 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkshss
, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS
},
6769 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkswss
, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS
},
6770 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhus
, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS
},
6771 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkshus
, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS
},
6772 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwus
, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS
},
6773 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkswus
, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS
},
6774 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlb
, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB
},
6775 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlh
, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH
},
6776 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlw
, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW
},
6777 { MASK_ALTIVEC
, CODE_FOR_altivec_vslb
, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB
},
6778 { MASK_ALTIVEC
, CODE_FOR_altivec_vslh
, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH
},
6779 { MASK_ALTIVEC
, CODE_FOR_altivec_vslw
, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW
},
6780 { MASK_ALTIVEC
, CODE_FOR_altivec_vsl
, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL
},
6781 { MASK_ALTIVEC
, CODE_FOR_altivec_vslo
, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO
},
6782 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltb
, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB
},
6783 { MASK_ALTIVEC
, CODE_FOR_altivec_vsplth
, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH
},
6784 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltw
, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW
},
6785 { MASK_ALTIVEC
, CODE_FOR_lshrv16qi3
, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB
},
6786 { MASK_ALTIVEC
, CODE_FOR_lshrv8hi3
, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH
},
6787 { MASK_ALTIVEC
, CODE_FOR_lshrv4si3
, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW
},
6788 { MASK_ALTIVEC
, CODE_FOR_ashrv16qi3
, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB
},
6789 { MASK_ALTIVEC
, CODE_FOR_ashrv8hi3
, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH
},
6790 { MASK_ALTIVEC
, CODE_FOR_ashrv4si3
, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW
},
6791 { MASK_ALTIVEC
, CODE_FOR_altivec_vsr
, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR
},
6792 { MASK_ALTIVEC
, CODE_FOR_altivec_vsro
, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO
},
6793 { MASK_ALTIVEC
, CODE_FOR_subv16qi3
, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM
},
6794 { MASK_ALTIVEC
, CODE_FOR_subv8hi3
, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM
},
6795 { MASK_ALTIVEC
, CODE_FOR_subv4si3
, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM
},
6796 { MASK_ALTIVEC
, CODE_FOR_subv4sf3
, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP
},
6797 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubcuw
, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW
},
6798 { MASK_ALTIVEC
, CODE_FOR_altivec_vsububs
, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS
},
6799 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubsbs
, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS
},
6800 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubuhs
, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS
},
6801 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubshs
, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS
},
6802 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubuws
, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS
},
6803 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubsws
, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS
},
6804 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4ubs
, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS
},
6805 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4sbs
, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS
},
6806 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4shs
, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS
},
6807 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum2sws
, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS
},
6808 { MASK_ALTIVEC
, CODE_FOR_altivec_vsumsws
, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS
},
6809 { MASK_ALTIVEC
, CODE_FOR_xorv4si3
, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR
},
6811 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD
},
6812 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP
},
6813 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM
},
6814 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM
},
6815 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM
},
6816 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC
},
6817 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS
},
6818 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS
},
6819 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS
},
6820 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS
},
6821 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS
},
6822 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS
},
6823 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS
},
6824 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND
},
6825 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC
},
6826 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG
},
6827 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW
},
6828 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW
},
6829 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH
},
6830 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH
},
6831 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB
},
6832 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB
},
6833 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB
},
6834 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ
},
6835 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP
},
6836 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW
},
6837 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH
},
6838 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB
},
6839 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE
},
6840 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT
},
6841 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP
},
6842 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW
},
6843 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW
},
6844 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH
},
6845 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH
},
6846 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB
},
6847 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB
},
6848 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE
},
6849 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT
},
6850 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX
},
6851 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP
},
6852 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW
},
6853 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW
},
6854 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH
},
6855 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH
},
6856 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB
},
6857 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB
},
6858 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH
},
6859 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW
},
6860 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH
},
6861 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB
},
6862 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL
},
6863 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW
},
6864 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH
},
6865 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB
},
6866 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN
},
6867 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP
},
6868 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW
},
6869 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW
},
6870 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH
},
6871 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH
},
6872 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB
},
6873 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB
},
6874 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE
},
6875 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB
},
6876 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB
},
6877 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH
},
6878 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH
},
6879 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO
},
6880 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH
},
6881 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH
},
6882 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB
},
6883 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB
},
6884 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR
},
6885 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR
},
6886 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK
},
6887 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM
},
6888 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM
},
6889 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX
},
6890 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS
},
6891 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS
},
6892 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS
},
6893 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS
},
6894 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS
},
6895 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU
},
6896 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS
},
6897 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS
},
6898 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL
},
6899 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW
},
6900 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH
},
6901 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB
},
6902 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL
},
6903 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW
},
6904 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH
},
6905 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB
},
6906 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL
},
6907 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO
},
6908 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR
},
6909 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW
},
6910 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH
},
6911 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB
},
6912 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA
},
6913 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW
},
6914 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH
},
6915 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB
},
6916 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL
},
6917 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO
},
6918 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB
},
6919 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP
},
6920 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM
},
6921 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM
},
6922 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM
},
6923 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC
},
6924 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS
},
6925 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS
},
6926 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS
},
6927 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS
},
6928 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS
},
6929 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS
},
6930 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS
},
6931 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S
},
6932 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS
},
6933 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS
},
6934 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS
},
6935 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S
},
6936 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS
},
6937 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR
},
6939 { 0, CODE_FOR_divv2sf3
, "__builtin_paired_divv2sf3", PAIRED_BUILTIN_DIVV2SF3
},
6940 { 0, CODE_FOR_addv2sf3
, "__builtin_paired_addv2sf3", PAIRED_BUILTIN_ADDV2SF3
},
6941 { 0, CODE_FOR_subv2sf3
, "__builtin_paired_subv2sf3", PAIRED_BUILTIN_SUBV2SF3
},
6942 { 0, CODE_FOR_mulv2sf3
, "__builtin_paired_mulv2sf3", PAIRED_BUILTIN_MULV2SF3
},
6943 { 0, CODE_FOR_paired_muls0
, "__builtin_paired_muls0", PAIRED_BUILTIN_MULS0
},
6944 { 0, CODE_FOR_paired_muls1
, "__builtin_paired_muls1", PAIRED_BUILTIN_MULS1
},
6945 { 0, CODE_FOR_paired_merge00
, "__builtin_paired_merge00", PAIRED_BUILTIN_MERGE00
},
6946 { 0, CODE_FOR_paired_merge01
, "__builtin_paired_merge01", PAIRED_BUILTIN_MERGE01
},
6947 { 0, CODE_FOR_paired_merge10
, "__builtin_paired_merge10", PAIRED_BUILTIN_MERGE10
},
6948 { 0, CODE_FOR_paired_merge11
, "__builtin_paired_merge11", PAIRED_BUILTIN_MERGE11
},
6950 /* Place holder, leave as first spe builtin. */
6951 { 0, CODE_FOR_spe_evaddw
, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW
},
6952 { 0, CODE_FOR_spe_evand
, "__builtin_spe_evand", SPE_BUILTIN_EVAND
},
6953 { 0, CODE_FOR_spe_evandc
, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC
},
6954 { 0, CODE_FOR_spe_evdivws
, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS
},
6955 { 0, CODE_FOR_spe_evdivwu
, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU
},
6956 { 0, CODE_FOR_spe_eveqv
, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV
},
6957 { 0, CODE_FOR_spe_evfsadd
, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD
},
6958 { 0, CODE_FOR_spe_evfsdiv
, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV
},
6959 { 0, CODE_FOR_spe_evfsmul
, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL
},
6960 { 0, CODE_FOR_spe_evfssub
, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB
},
6961 { 0, CODE_FOR_spe_evmergehi
, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI
},
6962 { 0, CODE_FOR_spe_evmergehilo
, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO
},
6963 { 0, CODE_FOR_spe_evmergelo
, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO
},
6964 { 0, CODE_FOR_spe_evmergelohi
, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI
},
6965 { 0, CODE_FOR_spe_evmhegsmfaa
, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA
},
6966 { 0, CODE_FOR_spe_evmhegsmfan
, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN
},
6967 { 0, CODE_FOR_spe_evmhegsmiaa
, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA
},
6968 { 0, CODE_FOR_spe_evmhegsmian
, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN
},
6969 { 0, CODE_FOR_spe_evmhegumiaa
, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA
},
6970 { 0, CODE_FOR_spe_evmhegumian
, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN
},
6971 { 0, CODE_FOR_spe_evmhesmf
, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF
},
6972 { 0, CODE_FOR_spe_evmhesmfa
, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA
},
6973 { 0, CODE_FOR_spe_evmhesmfaaw
, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW
},
6974 { 0, CODE_FOR_spe_evmhesmfanw
, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW
},
6975 { 0, CODE_FOR_spe_evmhesmi
, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI
},
6976 { 0, CODE_FOR_spe_evmhesmia
, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA
},
6977 { 0, CODE_FOR_spe_evmhesmiaaw
, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW
},
6978 { 0, CODE_FOR_spe_evmhesmianw
, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW
},
6979 { 0, CODE_FOR_spe_evmhessf
, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF
},
6980 { 0, CODE_FOR_spe_evmhessfa
, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA
},
6981 { 0, CODE_FOR_spe_evmhessfaaw
, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW
},
6982 { 0, CODE_FOR_spe_evmhessfanw
, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW
},
6983 { 0, CODE_FOR_spe_evmhessiaaw
, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW
},
6984 { 0, CODE_FOR_spe_evmhessianw
, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW
},
6985 { 0, CODE_FOR_spe_evmheumi
, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI
},
6986 { 0, CODE_FOR_spe_evmheumia
, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA
},
6987 { 0, CODE_FOR_spe_evmheumiaaw
, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW
},
6988 { 0, CODE_FOR_spe_evmheumianw
, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW
},
6989 { 0, CODE_FOR_spe_evmheusiaaw
, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW
},
6990 { 0, CODE_FOR_spe_evmheusianw
, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW
},
6991 { 0, CODE_FOR_spe_evmhogsmfaa
, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA
},
6992 { 0, CODE_FOR_spe_evmhogsmfan
, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN
},
6993 { 0, CODE_FOR_spe_evmhogsmiaa
, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA
},
6994 { 0, CODE_FOR_spe_evmhogsmian
, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN
},
6995 { 0, CODE_FOR_spe_evmhogumiaa
, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA
},
6996 { 0, CODE_FOR_spe_evmhogumian
, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN
},
6997 { 0, CODE_FOR_spe_evmhosmf
, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF
},
6998 { 0, CODE_FOR_spe_evmhosmfa
, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA
},
6999 { 0, CODE_FOR_spe_evmhosmfaaw
, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW
},
7000 { 0, CODE_FOR_spe_evmhosmfanw
, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW
},
7001 { 0, CODE_FOR_spe_evmhosmi
, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI
},
7002 { 0, CODE_FOR_spe_evmhosmia
, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA
},
7003 { 0, CODE_FOR_spe_evmhosmiaaw
, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW
},
7004 { 0, CODE_FOR_spe_evmhosmianw
, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW
},
7005 { 0, CODE_FOR_spe_evmhossf
, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF
},
7006 { 0, CODE_FOR_spe_evmhossfa
, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA
},
7007 { 0, CODE_FOR_spe_evmhossfaaw
, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW
},
7008 { 0, CODE_FOR_spe_evmhossfanw
, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW
},
7009 { 0, CODE_FOR_spe_evmhossiaaw
, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW
},
7010 { 0, CODE_FOR_spe_evmhossianw
, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW
},
7011 { 0, CODE_FOR_spe_evmhoumi
, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI
},
7012 { 0, CODE_FOR_spe_evmhoumia
, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA
},
7013 { 0, CODE_FOR_spe_evmhoumiaaw
, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW
},
7014 { 0, CODE_FOR_spe_evmhoumianw
, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW
},
7015 { 0, CODE_FOR_spe_evmhousiaaw
, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW
},
7016 { 0, CODE_FOR_spe_evmhousianw
, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW
},
7017 { 0, CODE_FOR_spe_evmwhsmf
, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF
},
7018 { 0, CODE_FOR_spe_evmwhsmfa
, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA
},
7019 { 0, CODE_FOR_spe_evmwhsmi
, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI
},
7020 { 0, CODE_FOR_spe_evmwhsmia
, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA
},
7021 { 0, CODE_FOR_spe_evmwhssf
, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF
},
7022 { 0, CODE_FOR_spe_evmwhssfa
, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA
},
7023 { 0, CODE_FOR_spe_evmwhumi
, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI
},
7024 { 0, CODE_FOR_spe_evmwhumia
, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA
},
7025 { 0, CODE_FOR_spe_evmwlsmiaaw
, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW
},
7026 { 0, CODE_FOR_spe_evmwlsmianw
, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW
},
7027 { 0, CODE_FOR_spe_evmwlssiaaw
, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW
},
7028 { 0, CODE_FOR_spe_evmwlssianw
, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW
},
7029 { 0, CODE_FOR_spe_evmwlumi
, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI
},
7030 { 0, CODE_FOR_spe_evmwlumia
, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA
},
7031 { 0, CODE_FOR_spe_evmwlumiaaw
, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW
},
7032 { 0, CODE_FOR_spe_evmwlumianw
, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW
},
7033 { 0, CODE_FOR_spe_evmwlusiaaw
, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW
},
7034 { 0, CODE_FOR_spe_evmwlusianw
, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW
},
7035 { 0, CODE_FOR_spe_evmwsmf
, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF
},
7036 { 0, CODE_FOR_spe_evmwsmfa
, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA
},
7037 { 0, CODE_FOR_spe_evmwsmfaa
, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA
},
7038 { 0, CODE_FOR_spe_evmwsmfan
, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN
},
7039 { 0, CODE_FOR_spe_evmwsmi
, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI
},
7040 { 0, CODE_FOR_spe_evmwsmia
, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA
},
7041 { 0, CODE_FOR_spe_evmwsmiaa
, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA
},
7042 { 0, CODE_FOR_spe_evmwsmian
, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN
},
7043 { 0, CODE_FOR_spe_evmwssf
, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF
},
7044 { 0, CODE_FOR_spe_evmwssfa
, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA
},
7045 { 0, CODE_FOR_spe_evmwssfaa
, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA
},
7046 { 0, CODE_FOR_spe_evmwssfan
, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN
},
7047 { 0, CODE_FOR_spe_evmwumi
, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI
},
7048 { 0, CODE_FOR_spe_evmwumia
, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA
},
7049 { 0, CODE_FOR_spe_evmwumiaa
, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA
},
7050 { 0, CODE_FOR_spe_evmwumian
, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN
},
7051 { 0, CODE_FOR_spe_evnand
, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND
},
7052 { 0, CODE_FOR_spe_evnor
, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR
},
7053 { 0, CODE_FOR_spe_evor
, "__builtin_spe_evor", SPE_BUILTIN_EVOR
},
7054 { 0, CODE_FOR_spe_evorc
, "__builtin_spe_evorc", SPE_BUILTIN_EVORC
},
7055 { 0, CODE_FOR_spe_evrlw
, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW
},
7056 { 0, CODE_FOR_spe_evslw
, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW
},
7057 { 0, CODE_FOR_spe_evsrws
, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS
},
7058 { 0, CODE_FOR_spe_evsrwu
, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU
},
7059 { 0, CODE_FOR_spe_evsubfw
, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW
},
7061 /* SPE binary operations expecting a 5-bit unsigned literal. */
7062 { 0, CODE_FOR_spe_evaddiw
, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW
},
7064 { 0, CODE_FOR_spe_evrlwi
, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI
},
7065 { 0, CODE_FOR_spe_evslwi
, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI
},
7066 { 0, CODE_FOR_spe_evsrwis
, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS
},
7067 { 0, CODE_FOR_spe_evsrwiu
, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU
},
7068 { 0, CODE_FOR_spe_evsubifw
, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW
},
7069 { 0, CODE_FOR_spe_evmwhssfaa
, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA
},
7070 { 0, CODE_FOR_spe_evmwhssmaa
, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA
},
7071 { 0, CODE_FOR_spe_evmwhsmfaa
, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA
},
7072 { 0, CODE_FOR_spe_evmwhsmiaa
, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA
},
7073 { 0, CODE_FOR_spe_evmwhusiaa
, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA
},
7074 { 0, CODE_FOR_spe_evmwhumiaa
, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA
},
7075 { 0, CODE_FOR_spe_evmwhssfan
, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN
},
7076 { 0, CODE_FOR_spe_evmwhssian
, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN
},
7077 { 0, CODE_FOR_spe_evmwhsmfan
, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN
},
7078 { 0, CODE_FOR_spe_evmwhsmian
, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN
},
7079 { 0, CODE_FOR_spe_evmwhusian
, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN
},
7080 { 0, CODE_FOR_spe_evmwhumian
, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN
},
7081 { 0, CODE_FOR_spe_evmwhgssfaa
, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA
},
7082 { 0, CODE_FOR_spe_evmwhgsmfaa
, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA
},
7083 { 0, CODE_FOR_spe_evmwhgsmiaa
, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA
},
7084 { 0, CODE_FOR_spe_evmwhgumiaa
, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA
},
7085 { 0, CODE_FOR_spe_evmwhgssfan
, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN
},
7086 { 0, CODE_FOR_spe_evmwhgsmfan
, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN
},
7087 { 0, CODE_FOR_spe_evmwhgsmian
, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN
},
7088 { 0, CODE_FOR_spe_evmwhgumian
, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN
},
7089 { 0, CODE_FOR_spe_brinc
, "__builtin_spe_brinc", SPE_BUILTIN_BRINC
},
7091 /* Place-holder. Leave as last binary SPE builtin. */
7092 { 0, CODE_FOR_xorv2si3
, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR
}
7095 /* AltiVec predicates. */
7097 struct builtin_description_predicates
7099 const unsigned int mask
;
7100 const enum insn_code icode
;
7102 const char *const name
;
7103 const enum rs6000_builtins code
;
7106 static const struct builtin_description_predicates bdesc_altivec_preds
[] =
7108 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P
},
7109 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P
},
7110 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P
},
7111 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P
},
7112 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P
},
7113 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P
},
7114 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P
},
7115 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P
},
7116 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P
},
7117 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P
},
7118 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P
},
7119 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P
},
7120 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P
},
7122 { MASK_ALTIVEC
, 0, NULL
, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P
},
7123 { MASK_ALTIVEC
, 0, NULL
, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P
},
7124 { MASK_ALTIVEC
, 0, NULL
, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P
}
7127 /* SPE predicates. */
7128 static struct builtin_description bdesc_spe_predicates
[] =
7130 /* Place-holder. Leave as first. */
7131 { 0, CODE_FOR_spe_evcmpeq
, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ
},
7132 { 0, CODE_FOR_spe_evcmpgts
, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS
},
7133 { 0, CODE_FOR_spe_evcmpgtu
, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU
},
7134 { 0, CODE_FOR_spe_evcmplts
, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS
},
7135 { 0, CODE_FOR_spe_evcmpltu
, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU
},
7136 { 0, CODE_FOR_spe_evfscmpeq
, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ
},
7137 { 0, CODE_FOR_spe_evfscmpgt
, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT
},
7138 { 0, CODE_FOR_spe_evfscmplt
, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT
},
7139 { 0, CODE_FOR_spe_evfststeq
, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ
},
7140 { 0, CODE_FOR_spe_evfststgt
, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT
},
7141 /* Place-holder. Leave as last. */
7142 { 0, CODE_FOR_spe_evfststlt
, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT
},
7145 /* SPE evsel predicates. */
7146 static struct builtin_description bdesc_spe_evsel
[] =
7148 /* Place-holder. Leave as first. */
7149 { 0, CODE_FOR_spe_evcmpgts
, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS
},
7150 { 0, CODE_FOR_spe_evcmpgtu
, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU
},
7151 { 0, CODE_FOR_spe_evcmplts
, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS
},
7152 { 0, CODE_FOR_spe_evcmpltu
, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU
},
7153 { 0, CODE_FOR_spe_evcmpeq
, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ
},
7154 { 0, CODE_FOR_spe_evfscmpgt
, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT
},
7155 { 0, CODE_FOR_spe_evfscmplt
, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT
},
7156 { 0, CODE_FOR_spe_evfscmpeq
, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ
},
7157 { 0, CODE_FOR_spe_evfststgt
, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT
},
7158 { 0, CODE_FOR_spe_evfststlt
, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT
},
7159 /* Place-holder. Leave as last. */
7160 { 0, CODE_FOR_spe_evfststeq
, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ
},
7163 /* PAIRED predicates. */
7164 static const struct builtin_description bdesc_paired_preds
[] =
7166 /* Place-holder. Leave as first. */
7167 { 0, CODE_FOR_paired_cmpu0
, "__builtin_paired_cmpu0", PAIRED_BUILTIN_CMPU0
},
7168 /* Place-holder. Leave as last. */
7169 { 0, CODE_FOR_paired_cmpu1
, "__builtin_paired_cmpu1", PAIRED_BUILTIN_CMPU1
},
7172 /* ABS* operations. */
7174 static const struct builtin_description bdesc_abs
[] =
7176 { MASK_ALTIVEC
, CODE_FOR_absv4si2
, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI
},
7177 { MASK_ALTIVEC
, CODE_FOR_absv8hi2
, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI
},
7178 { MASK_ALTIVEC
, CODE_FOR_absv4sf2
, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF
},
7179 { MASK_ALTIVEC
, CODE_FOR_absv16qi2
, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI
},
7180 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v4si
, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI
},
7181 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v8hi
, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI
},
7182 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v16qi
, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI
}
7185 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
7188 static struct builtin_description bdesc_1arg
[] =
7190 { MASK_ALTIVEC
, CODE_FOR_altivec_vexptefp
, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP
},
7191 { MASK_ALTIVEC
, CODE_FOR_altivec_vlogefp
, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP
},
7192 { MASK_ALTIVEC
, CODE_FOR_altivec_vrefp
, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP
},
7193 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfim
, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM
},
7194 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfin
, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN
},
7195 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfip
, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP
},
7196 { MASK_ALTIVEC
, CODE_FOR_ftruncv4sf2
, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ
},
7197 { MASK_ALTIVEC
, CODE_FOR_altivec_vrsqrtefp
, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP
},
7198 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltisb
, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB
},
7199 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltish
, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH
},
7200 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltisw
, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW
},
7201 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhsb
, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB
},
7202 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhpx
, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX
},
7203 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhsh
, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH
},
7204 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklsb
, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB
},
7205 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklpx
, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX
},
7206 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklsh
, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH
},
7208 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS
},
7209 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS
},
7210 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL
},
7211 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE
},
7212 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR
},
7213 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE
},
7214 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR
},
7215 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE
},
7216 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND
},
7217 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE
},
7218 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC
},
7219 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH
},
7220 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH
},
7221 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX
},
7222 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB
},
7223 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL
},
7224 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX
},
7225 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH
},
7226 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB
},
7228 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
7229 end with SPE_BUILTIN_EVSUBFUSIAAW. */
7230 { 0, CODE_FOR_spe_evabs
, "__builtin_spe_evabs", SPE_BUILTIN_EVABS
},
7231 { 0, CODE_FOR_spe_evaddsmiaaw
, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW
},
7232 { 0, CODE_FOR_spe_evaddssiaaw
, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW
},
7233 { 0, CODE_FOR_spe_evaddumiaaw
, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW
},
7234 { 0, CODE_FOR_spe_evaddusiaaw
, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW
},
7235 { 0, CODE_FOR_spe_evcntlsw
, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW
},
7236 { 0, CODE_FOR_spe_evcntlzw
, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW
},
7237 { 0, CODE_FOR_spe_evextsb
, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB
},
7238 { 0, CODE_FOR_spe_evextsh
, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH
},
7239 { 0, CODE_FOR_spe_evfsabs
, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS
},
7240 { 0, CODE_FOR_spe_evfscfsf
, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF
},
7241 { 0, CODE_FOR_spe_evfscfsi
, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI
},
7242 { 0, CODE_FOR_spe_evfscfuf
, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF
},
7243 { 0, CODE_FOR_spe_evfscfui
, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI
},
7244 { 0, CODE_FOR_spe_evfsctsf
, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF
},
7245 { 0, CODE_FOR_spe_evfsctsi
, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI
},
7246 { 0, CODE_FOR_spe_evfsctsiz
, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ
},
7247 { 0, CODE_FOR_spe_evfsctuf
, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF
},
7248 { 0, CODE_FOR_spe_evfsctui
, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI
},
7249 { 0, CODE_FOR_spe_evfsctuiz
, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ
},
7250 { 0, CODE_FOR_spe_evfsnabs
, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS
},
7251 { 0, CODE_FOR_spe_evfsneg
, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG
},
7252 { 0, CODE_FOR_spe_evmra
, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA
},
7253 { 0, CODE_FOR_negv2si2
, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG
},
7254 { 0, CODE_FOR_spe_evrndw
, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW
},
7255 { 0, CODE_FOR_spe_evsubfsmiaaw
, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW
},
7256 { 0, CODE_FOR_spe_evsubfssiaaw
, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW
},
7257 { 0, CODE_FOR_spe_evsubfumiaaw
, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW
},
7259 /* Place-holder. Leave as last unary SPE builtin. */
7260 { 0, CODE_FOR_spe_evsubfusiaaw
, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW
},
7262 { 0, CODE_FOR_absv2sf2
, "__builtin_paired_absv2sf2", PAIRED_BUILTIN_ABSV2SF2
},
7263 { 0, CODE_FOR_nabsv2sf2
, "__builtin_paired_nabsv2sf2", PAIRED_BUILTIN_NABSV2SF2
},
7264 { 0, CODE_FOR_negv2sf2
, "__builtin_paired_negv2sf2", PAIRED_BUILTIN_NEGV2SF2
},
7265 { 0, CODE_FOR_sqrtv2sf2
, "__builtin_paired_sqrtv2sf2", PAIRED_BUILTIN_SQRTV2SF2
},
7266 { 0, CODE_FOR_resv2sf2
, "__builtin_paired_resv2sf2", PAIRED_BUILTIN_RESV2SF2
}
7270 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
7273 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7274 rtx op0
= expand_normal (arg0
);
7275 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7276 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7278 if (icode
== CODE_FOR_nothing
)
7279 /* Builtin not supported on this processor. */
7282 /* If we got invalid arguments bail out before generating bad rtl. */
7283 if (arg0
== error_mark_node
)
7286 if (icode
== CODE_FOR_altivec_vspltisb
7287 || icode
== CODE_FOR_altivec_vspltish
7288 || icode
== CODE_FOR_altivec_vspltisw
7289 || icode
== CODE_FOR_spe_evsplatfi
7290 || icode
== CODE_FOR_spe_evsplati
)
7292 /* Only allow 5-bit *signed* literals. */
7293 if (GET_CODE (op0
) != CONST_INT
7294 || INTVAL (op0
) > 15
7295 || INTVAL (op0
) < -16)
7297 error ("argument 1 must be a 5-bit signed literal");
7303 || GET_MODE (target
) != tmode
7304 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7305 target
= gen_reg_rtx (tmode
);
7307 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7308 op0
= copy_to_mode_reg (mode0
, op0
);
7310 pat
= GEN_FCN (icode
) (target
, op0
);
7319 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
7321 rtx pat
, scratch1
, scratch2
;
7322 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7323 rtx op0
= expand_normal (arg0
);
7324 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7325 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7327 /* If we have invalid arguments, bail out before generating bad rtl. */
7328 if (arg0
== error_mark_node
)
7332 || GET_MODE (target
) != tmode
7333 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7334 target
= gen_reg_rtx (tmode
);
7336 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7337 op0
= copy_to_mode_reg (mode0
, op0
);
7339 scratch1
= gen_reg_rtx (mode0
);
7340 scratch2
= gen_reg_rtx (mode0
);
7342 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
7351 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
7354 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7355 tree arg1
= CALL_EXPR_ARG (exp
, 1);
7356 rtx op0
= expand_normal (arg0
);
7357 rtx op1
= expand_normal (arg1
);
7358 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7359 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7360 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
7362 if (icode
== CODE_FOR_nothing
)
7363 /* Builtin not supported on this processor. */
7366 /* If we got invalid arguments bail out before generating bad rtl. */
7367 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
7370 if (icode
== CODE_FOR_altivec_vcfux
7371 || icode
== CODE_FOR_altivec_vcfsx
7372 || icode
== CODE_FOR_altivec_vctsxs
7373 || icode
== CODE_FOR_altivec_vctuxs
7374 || icode
== CODE_FOR_altivec_vspltb
7375 || icode
== CODE_FOR_altivec_vsplth
7376 || icode
== CODE_FOR_altivec_vspltw
7377 || icode
== CODE_FOR_spe_evaddiw
7378 || icode
== CODE_FOR_spe_evldd
7379 || icode
== CODE_FOR_spe_evldh
7380 || icode
== CODE_FOR_spe_evldw
7381 || icode
== CODE_FOR_spe_evlhhesplat
7382 || icode
== CODE_FOR_spe_evlhhossplat
7383 || icode
== CODE_FOR_spe_evlhhousplat
7384 || icode
== CODE_FOR_spe_evlwhe
7385 || icode
== CODE_FOR_spe_evlwhos
7386 || icode
== CODE_FOR_spe_evlwhou
7387 || icode
== CODE_FOR_spe_evlwhsplat
7388 || icode
== CODE_FOR_spe_evlwwsplat
7389 || icode
== CODE_FOR_spe_evrlwi
7390 || icode
== CODE_FOR_spe_evslwi
7391 || icode
== CODE_FOR_spe_evsrwis
7392 || icode
== CODE_FOR_spe_evsubifw
7393 || icode
== CODE_FOR_spe_evsrwiu
)
7395 /* Only allow 5-bit unsigned literals. */
7397 if (TREE_CODE (arg1
) != INTEGER_CST
7398 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
7400 error ("argument 2 must be a 5-bit unsigned literal");
7406 || GET_MODE (target
) != tmode
7407 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7408 target
= gen_reg_rtx (tmode
);
7410 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7411 op0
= copy_to_mode_reg (mode0
, op0
);
7412 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
7413 op1
= copy_to_mode_reg (mode1
, op1
);
7415 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
7424 altivec_expand_predicate_builtin (enum insn_code icode
, const char *opcode
,
7425 tree exp
, rtx target
)
7428 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
7429 tree arg0
= CALL_EXPR_ARG (exp
, 1);
7430 tree arg1
= CALL_EXPR_ARG (exp
, 2);
7431 rtx op0
= expand_normal (arg0
);
7432 rtx op1
= expand_normal (arg1
);
7433 enum machine_mode tmode
= SImode
;
7434 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7435 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
7438 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
7440 error ("argument 1 of __builtin_altivec_predicate must be a constant");
7444 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
7446 gcc_assert (mode0
== mode1
);
7448 /* If we have invalid arguments, bail out before generating bad rtl. */
7449 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
7453 || GET_MODE (target
) != tmode
7454 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7455 target
= gen_reg_rtx (tmode
);
7457 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7458 op0
= copy_to_mode_reg (mode0
, op0
);
7459 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
7460 op1
= copy_to_mode_reg (mode1
, op1
);
7462 scratch
= gen_reg_rtx (mode0
);
7464 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
,
7465 gen_rtx_SYMBOL_REF (Pmode
, opcode
));
7470 /* The vec_any* and vec_all* predicates use the same opcodes for two
7471 different operations, but the bits in CR6 will be different
7472 depending on what information we want. So we have to play tricks
7473 with CR6 to get the right bits out.
7475 If you think this is disgusting, look at the specs for the
7476 AltiVec predicates. */
7478 switch (cr6_form_int
)
7481 emit_insn (gen_cr6_test_for_zero (target
));
7484 emit_insn (gen_cr6_test_for_zero_reverse (target
));
7487 emit_insn (gen_cr6_test_for_lt (target
));
7490 emit_insn (gen_cr6_test_for_lt_reverse (target
));
7493 error ("argument 1 of __builtin_altivec_predicate is out of range");
7501 paired_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
7504 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7505 tree arg1
= CALL_EXPR_ARG (exp
, 1);
7506 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7507 enum machine_mode mode0
= Pmode
;
7508 enum machine_mode mode1
= Pmode
;
7509 rtx op0
= expand_normal (arg0
);
7510 rtx op1
= expand_normal (arg1
);
7512 if (icode
== CODE_FOR_nothing
)
7513 /* Builtin not supported on this processor. */
7516 /* If we got invalid arguments bail out before generating bad rtl. */
7517 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
7521 || GET_MODE (target
) != tmode
7522 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7523 target
= gen_reg_rtx (tmode
);
7525 op1
= copy_to_mode_reg (mode1
, op1
);
7527 if (op0
== const0_rtx
)
7529 addr
= gen_rtx_MEM (tmode
, op1
);
7533 op0
= copy_to_mode_reg (mode0
, op0
);
7534 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
7537 pat
= GEN_FCN (icode
) (target
, addr
);
7547 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
7550 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7551 tree arg1
= CALL_EXPR_ARG (exp
, 1);
7552 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7553 enum machine_mode mode0
= Pmode
;
7554 enum machine_mode mode1
= Pmode
;
7555 rtx op0
= expand_normal (arg0
);
7556 rtx op1
= expand_normal (arg1
);
7558 if (icode
== CODE_FOR_nothing
)
7559 /* Builtin not supported on this processor. */
7562 /* If we got invalid arguments bail out before generating bad rtl. */
7563 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
7567 || GET_MODE (target
) != tmode
7568 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7569 target
= gen_reg_rtx (tmode
);
7571 op1
= copy_to_mode_reg (mode1
, op1
);
7573 if (op0
== const0_rtx
)
7575 addr
= gen_rtx_MEM (tmode
, op1
);
7579 op0
= copy_to_mode_reg (mode0
, op0
);
7580 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
7583 pat
= GEN_FCN (icode
) (target
, addr
);
7593 spe_expand_stv_builtin (enum insn_code icode
, tree exp
)
7595 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7596 tree arg1
= CALL_EXPR_ARG (exp
, 1);
7597 tree arg2
= CALL_EXPR_ARG (exp
, 2);
7598 rtx op0
= expand_normal (arg0
);
7599 rtx op1
= expand_normal (arg1
);
7600 rtx op2
= expand_normal (arg2
);
7602 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
7603 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
7604 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
7606 /* Invalid arguments. Bail before doing anything stoopid! */
7607 if (arg0
== error_mark_node
7608 || arg1
== error_mark_node
7609 || arg2
== error_mark_node
)
7612 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
7613 op0
= copy_to_mode_reg (mode2
, op0
);
7614 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
7615 op1
= copy_to_mode_reg (mode0
, op1
);
7616 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
7617 op2
= copy_to_mode_reg (mode1
, op2
);
7619 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
7626 paired_expand_stv_builtin (enum insn_code icode
, tree exp
)
7628 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7629 tree arg1
= CALL_EXPR_ARG (exp
, 1);
7630 tree arg2
= CALL_EXPR_ARG (exp
, 2);
7631 rtx op0
= expand_normal (arg0
);
7632 rtx op1
= expand_normal (arg1
);
7633 rtx op2
= expand_normal (arg2
);
7635 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7636 enum machine_mode mode1
= Pmode
;
7637 enum machine_mode mode2
= Pmode
;
7639 /* Invalid arguments. Bail before doing anything stoopid! */
7640 if (arg0
== error_mark_node
7641 || arg1
== error_mark_node
7642 || arg2
== error_mark_node
)
7645 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
7646 op0
= copy_to_mode_reg (tmode
, op0
);
7648 op2
= copy_to_mode_reg (mode2
, op2
);
7650 if (op1
== const0_rtx
)
7652 addr
= gen_rtx_MEM (tmode
, op2
);
7656 op1
= copy_to_mode_reg (mode1
, op1
);
7657 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
7660 pat
= GEN_FCN (icode
) (addr
, op0
);
7667 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
7669 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7670 tree arg1
= CALL_EXPR_ARG (exp
, 1);
7671 tree arg2
= CALL_EXPR_ARG (exp
, 2);
7672 rtx op0
= expand_normal (arg0
);
7673 rtx op1
= expand_normal (arg1
);
7674 rtx op2
= expand_normal (arg2
);
7676 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7677 enum machine_mode mode1
= Pmode
;
7678 enum machine_mode mode2
= Pmode
;
7680 /* Invalid arguments. Bail before doing anything stoopid! */
7681 if (arg0
== error_mark_node
7682 || arg1
== error_mark_node
7683 || arg2
== error_mark_node
)
7686 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
7687 op0
= copy_to_mode_reg (tmode
, op0
);
7689 op2
= copy_to_mode_reg (mode2
, op2
);
7691 if (op1
== const0_rtx
)
7693 addr
= gen_rtx_MEM (tmode
, op2
);
7697 op1
= copy_to_mode_reg (mode1
, op1
);
7698 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
7701 pat
= GEN_FCN (icode
) (addr
, op0
);
7708 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
7711 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7712 tree arg1
= CALL_EXPR_ARG (exp
, 1);
7713 tree arg2
= CALL_EXPR_ARG (exp
, 2);
7714 rtx op0
= expand_normal (arg0
);
7715 rtx op1
= expand_normal (arg1
);
7716 rtx op2
= expand_normal (arg2
);
7717 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7718 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7719 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
7720 enum machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
7722 if (icode
== CODE_FOR_nothing
)
7723 /* Builtin not supported on this processor. */
7726 /* If we got invalid arguments bail out before generating bad rtl. */
7727 if (arg0
== error_mark_node
7728 || arg1
== error_mark_node
7729 || arg2
== error_mark_node
)
7732 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
7733 || icode
== CODE_FOR_altivec_vsldoi_v4si
7734 || icode
== CODE_FOR_altivec_vsldoi_v8hi
7735 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
7737 /* Only allow 4-bit unsigned literals. */
7739 if (TREE_CODE (arg2
) != INTEGER_CST
7740 || TREE_INT_CST_LOW (arg2
) & ~0xf)
7742 error ("argument 3 must be a 4-bit unsigned literal");
7748 || GET_MODE (target
) != tmode
7749 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7750 target
= gen_reg_rtx (tmode
);
7752 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7753 op0
= copy_to_mode_reg (mode0
, op0
);
7754 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
7755 op1
= copy_to_mode_reg (mode1
, op1
);
7756 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
7757 op2
= copy_to_mode_reg (mode2
, op2
);
7759 if (TARGET_PAIRED_FLOAT
&& icode
== CODE_FOR_selv2sf4
)
7760 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
, CONST0_RTX (SFmode
));
7762 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
7770 /* Expand the lvx builtins. */
7772 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
7774 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
7775 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
7777 enum machine_mode tmode
, mode0
;
7779 enum insn_code icode
;
7783 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
7784 icode
= CODE_FOR_altivec_lvx_v16qi
;
7786 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
7787 icode
= CODE_FOR_altivec_lvx_v8hi
;
7789 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
7790 icode
= CODE_FOR_altivec_lvx_v4si
;
7792 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
7793 icode
= CODE_FOR_altivec_lvx_v4sf
;
7802 arg0
= CALL_EXPR_ARG (exp
, 0);
7803 op0
= expand_normal (arg0
);
7804 tmode
= insn_data
[icode
].operand
[0].mode
;
7805 mode0
= insn_data
[icode
].operand
[1].mode
;
7808 || GET_MODE (target
) != tmode
7809 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7810 target
= gen_reg_rtx (tmode
);
7812 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7813 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
7815 pat
= GEN_FCN (icode
) (target
, op0
);
7822 /* Expand the stvx builtins. */
7824 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
7827 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
7828 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
7830 enum machine_mode mode0
, mode1
;
7832 enum insn_code icode
;
7836 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
7837 icode
= CODE_FOR_altivec_stvx_v16qi
;
7839 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
7840 icode
= CODE_FOR_altivec_stvx_v8hi
;
7842 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
7843 icode
= CODE_FOR_altivec_stvx_v4si
;
7845 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
7846 icode
= CODE_FOR_altivec_stvx_v4sf
;
7853 arg0
= CALL_EXPR_ARG (exp
, 0);
7854 arg1
= CALL_EXPR_ARG (exp
, 1);
7855 op0
= expand_normal (arg0
);
7856 op1
= expand_normal (arg1
);
7857 mode0
= insn_data
[icode
].operand
[0].mode
;
7858 mode1
= insn_data
[icode
].operand
[1].mode
;
7860 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
7861 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
7862 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
7863 op1
= copy_to_mode_reg (mode1
, op1
);
7865 pat
= GEN_FCN (icode
) (op0
, op1
);
7873 /* Expand the dst builtins. */
7875 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
7878 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
7879 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
7880 tree arg0
, arg1
, arg2
;
7881 enum machine_mode mode0
, mode1
, mode2
;
7882 rtx pat
, op0
, op1
, op2
;
7883 const struct builtin_description
*d
;
7888 /* Handle DST variants. */
7890 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
7891 if (d
->code
== fcode
)
7893 arg0
= CALL_EXPR_ARG (exp
, 0);
7894 arg1
= CALL_EXPR_ARG (exp
, 1);
7895 arg2
= CALL_EXPR_ARG (exp
, 2);
7896 op0
= expand_normal (arg0
);
7897 op1
= expand_normal (arg1
);
7898 op2
= expand_normal (arg2
);
7899 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
7900 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
7901 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
7903 /* Invalid arguments, bail out before generating bad rtl. */
7904 if (arg0
== error_mark_node
7905 || arg1
== error_mark_node
7906 || arg2
== error_mark_node
)
7911 if (TREE_CODE (arg2
) != INTEGER_CST
7912 || TREE_INT_CST_LOW (arg2
) & ~0x3)
7914 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
7918 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
7919 op0
= copy_to_mode_reg (Pmode
, op0
);
7920 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
7921 op1
= copy_to_mode_reg (mode1
, op1
);
7923 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
7933 /* Expand vec_init builtin. */
7935 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
7937 enum machine_mode tmode
= TYPE_MODE (type
);
7938 enum machine_mode inner_mode
= GET_MODE_INNER (tmode
);
7939 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
7940 rtvec v
= rtvec_alloc (n_elt
);
7942 gcc_assert (VECTOR_MODE_P (tmode
));
7943 gcc_assert (n_elt
== call_expr_nargs (exp
));
7945 for (i
= 0; i
< n_elt
; ++i
)
7947 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
7948 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
7951 if (!target
|| !register_operand (target
, tmode
))
7952 target
= gen_reg_rtx (tmode
);
7954 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
7958 /* Return the integer constant in ARG. Constrain it to be in the range
7959 of the subparts of VEC_TYPE; issue an error if not. */
7962 get_element_number (tree vec_type
, tree arg
)
7964 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
7966 if (!host_integerp (arg
, 1)
7967 || (elt
= tree_low_cst (arg
, 1), elt
> max
))
7969 error ("selector must be an integer constant in the range 0..%wi", max
);
7976 /* Expand vec_set builtin. */
7978 altivec_expand_vec_set_builtin (tree exp
)
7980 enum machine_mode tmode
, mode1
;
7981 tree arg0
, arg1
, arg2
;
7985 arg0
= CALL_EXPR_ARG (exp
, 0);
7986 arg1
= CALL_EXPR_ARG (exp
, 1);
7987 arg2
= CALL_EXPR_ARG (exp
, 2);
7989 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
7990 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
7991 gcc_assert (VECTOR_MODE_P (tmode
));
7993 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, 0);
7994 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, 0);
7995 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
7997 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
7998 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
8000 op0
= force_reg (tmode
, op0
);
8001 op1
= force_reg (mode1
, op1
);
8003 rs6000_expand_vector_set (op0
, op1
, elt
);
8008 /* Expand vec_ext builtin. */
8010 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
8012 enum machine_mode tmode
, mode0
;
8017 arg0
= CALL_EXPR_ARG (exp
, 0);
8018 arg1
= CALL_EXPR_ARG (exp
, 1);
8020 op0
= expand_normal (arg0
);
8021 elt
= get_element_number (TREE_TYPE (arg0
), arg1
);
8023 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
8024 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
8025 gcc_assert (VECTOR_MODE_P (mode0
));
8027 op0
= force_reg (mode0
, op0
);
8029 if (optimize
|| !target
|| !register_operand (target
, tmode
))
8030 target
= gen_reg_rtx (tmode
);
8032 rs6000_expand_vector_extract (target
, op0
, elt
);
8037 /* Expand the builtin in EXP and store the result in TARGET. Store
8038 true in *EXPANDEDP if we found a builtin to expand. */
8040 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
8042 const struct builtin_description
*d
;
8043 const struct builtin_description_predicates
*dp
;
8045 enum insn_code icode
;
8046 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8049 enum machine_mode tmode
, mode0
;
8050 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8052 if (fcode
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8053 && fcode
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
)
8056 error ("unresolved overload for Altivec builtin %qF", fndecl
);
8060 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
8064 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
8068 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
8076 case ALTIVEC_BUILTIN_STVX
:
8077 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx
, exp
);
8078 case ALTIVEC_BUILTIN_STVEBX
:
8079 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
8080 case ALTIVEC_BUILTIN_STVEHX
:
8081 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
8082 case ALTIVEC_BUILTIN_STVEWX
:
8083 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
8084 case ALTIVEC_BUILTIN_STVXL
:
8085 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl
, exp
);
8087 case ALTIVEC_BUILTIN_MFVSCR
:
8088 icode
= CODE_FOR_altivec_mfvscr
;
8089 tmode
= insn_data
[icode
].operand
[0].mode
;
8092 || GET_MODE (target
) != tmode
8093 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8094 target
= gen_reg_rtx (tmode
);
8096 pat
= GEN_FCN (icode
) (target
);
8102 case ALTIVEC_BUILTIN_MTVSCR
:
8103 icode
= CODE_FOR_altivec_mtvscr
;
8104 arg0
= CALL_EXPR_ARG (exp
, 0);
8105 op0
= expand_normal (arg0
);
8106 mode0
= insn_data
[icode
].operand
[0].mode
;
8108 /* If we got invalid arguments bail out before generating bad rtl. */
8109 if (arg0
== error_mark_node
)
8112 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
8113 op0
= copy_to_mode_reg (mode0
, op0
);
8115 pat
= GEN_FCN (icode
) (op0
);
8120 case ALTIVEC_BUILTIN_DSSALL
:
8121 emit_insn (gen_altivec_dssall ());
8124 case ALTIVEC_BUILTIN_DSS
:
8125 icode
= CODE_FOR_altivec_dss
;
8126 arg0
= CALL_EXPR_ARG (exp
, 0);
8128 op0
= expand_normal (arg0
);
8129 mode0
= insn_data
[icode
].operand
[0].mode
;
8131 /* If we got invalid arguments bail out before generating bad rtl. */
8132 if (arg0
== error_mark_node
)
8135 if (TREE_CODE (arg0
) != INTEGER_CST
8136 || TREE_INT_CST_LOW (arg0
) & ~0x3)
8138 error ("argument to dss must be a 2-bit unsigned literal");
8142 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
8143 op0
= copy_to_mode_reg (mode0
, op0
);
8145 emit_insn (gen_altivec_dss (op0
));
8148 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
8149 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
8150 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
8151 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
8152 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
8154 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
8155 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
8156 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
8157 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
8158 return altivec_expand_vec_set_builtin (exp
);
8160 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
8161 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
8162 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
8163 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
8164 return altivec_expand_vec_ext_builtin (exp
, target
);
8171 /* Expand abs* operations. */
8173 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
8174 if (d
->code
== fcode
)
8175 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
8177 /* Expand the AltiVec predicates. */
8178 dp
= bdesc_altivec_preds
;
8179 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, dp
++)
8180 if (dp
->code
== fcode
)
8181 return altivec_expand_predicate_builtin (dp
->icode
, dp
->opcode
,
8184 /* LV* are funky. We initialized them differently. */
8187 case ALTIVEC_BUILTIN_LVSL
:
8188 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
8190 case ALTIVEC_BUILTIN_LVSR
:
8191 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
8193 case ALTIVEC_BUILTIN_LVEBX
:
8194 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
8196 case ALTIVEC_BUILTIN_LVEHX
:
8197 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
8199 case ALTIVEC_BUILTIN_LVEWX
:
8200 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
8202 case ALTIVEC_BUILTIN_LVXL
:
8203 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl
,
8205 case ALTIVEC_BUILTIN_LVX
:
8206 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx
,
8217 /* Expand the builtin in EXP and store the result in TARGET. Store
8218 true in *EXPANDEDP if we found a builtin to expand. */
8220 paired_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
8222 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8223 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8224 const struct builtin_description
*d
;
8231 case PAIRED_BUILTIN_STX
:
8232 return paired_expand_stv_builtin (CODE_FOR_paired_stx
, exp
);
8233 case PAIRED_BUILTIN_LX
:
8234 return paired_expand_lv_builtin (CODE_FOR_paired_lx
, exp
, target
);
8240 /* Expand the paired predicates. */
8241 d
= bdesc_paired_preds
;
8242 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); i
++, d
++)
8243 if (d
->code
== fcode
)
8244 return paired_expand_predicate_builtin (d
->icode
, exp
, target
);
8250 /* Binops that need to be initialized manually, but can be expanded
8251 automagically by rs6000_expand_binop_builtin. */
8252 static struct builtin_description bdesc_2arg_spe
[] =
8254 { 0, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
8255 { 0, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
8256 { 0, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
8257 { 0, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
8258 { 0, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
8259 { 0, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
8260 { 0, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
8261 { 0, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
8262 { 0, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
8263 { 0, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
8264 { 0, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
8265 { 0, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
8266 { 0, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
8267 { 0, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
8268 { 0, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
8269 { 0, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
8270 { 0, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
8271 { 0, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
8272 { 0, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
8273 { 0, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
8274 { 0, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
8275 { 0, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
8278 /* Expand the builtin in EXP and store the result in TARGET. Store
8279 true in *EXPANDEDP if we found a builtin to expand.
8281 This expands the SPE builtins that are not simple unary and binary
8284 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
8286 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8288 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8289 enum insn_code icode
;
8290 enum machine_mode tmode
, mode0
;
8292 struct builtin_description
*d
;
8297 /* Syntax check for a 5-bit unsigned immediate. */
8300 case SPE_BUILTIN_EVSTDD
:
8301 case SPE_BUILTIN_EVSTDH
:
8302 case SPE_BUILTIN_EVSTDW
:
8303 case SPE_BUILTIN_EVSTWHE
:
8304 case SPE_BUILTIN_EVSTWHO
:
8305 case SPE_BUILTIN_EVSTWWE
:
8306 case SPE_BUILTIN_EVSTWWO
:
8307 arg1
= CALL_EXPR_ARG (exp
, 2);
8308 if (TREE_CODE (arg1
) != INTEGER_CST
8309 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
8311 error ("argument 2 must be a 5-bit unsigned literal");
8319 /* The evsplat*i instructions are not quite generic. */
8322 case SPE_BUILTIN_EVSPLATFI
:
8323 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
8325 case SPE_BUILTIN_EVSPLATI
:
8326 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
8332 d
= (struct builtin_description
*) bdesc_2arg_spe
;
8333 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
8334 if (d
->code
== fcode
)
8335 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
8337 d
= (struct builtin_description
*) bdesc_spe_predicates
;
8338 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
8339 if (d
->code
== fcode
)
8340 return spe_expand_predicate_builtin (d
->icode
, exp
, target
);
8342 d
= (struct builtin_description
*) bdesc_spe_evsel
;
8343 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
8344 if (d
->code
== fcode
)
8345 return spe_expand_evsel_builtin (d
->icode
, exp
, target
);
8349 case SPE_BUILTIN_EVSTDDX
:
8350 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, exp
);
8351 case SPE_BUILTIN_EVSTDHX
:
8352 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, exp
);
8353 case SPE_BUILTIN_EVSTDWX
:
8354 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, exp
);
8355 case SPE_BUILTIN_EVSTWHEX
:
8356 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, exp
);
8357 case SPE_BUILTIN_EVSTWHOX
:
8358 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, exp
);
8359 case SPE_BUILTIN_EVSTWWEX
:
8360 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, exp
);
8361 case SPE_BUILTIN_EVSTWWOX
:
8362 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, exp
);
8363 case SPE_BUILTIN_EVSTDD
:
8364 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, exp
);
8365 case SPE_BUILTIN_EVSTDH
:
8366 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, exp
);
8367 case SPE_BUILTIN_EVSTDW
:
8368 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, exp
);
8369 case SPE_BUILTIN_EVSTWHE
:
8370 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, exp
);
8371 case SPE_BUILTIN_EVSTWHO
:
8372 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, exp
);
8373 case SPE_BUILTIN_EVSTWWE
:
8374 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, exp
);
8375 case SPE_BUILTIN_EVSTWWO
:
8376 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, exp
);
8377 case SPE_BUILTIN_MFSPEFSCR
:
8378 icode
= CODE_FOR_spe_mfspefscr
;
8379 tmode
= insn_data
[icode
].operand
[0].mode
;
8382 || GET_MODE (target
) != tmode
8383 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8384 target
= gen_reg_rtx (tmode
);
8386 pat
= GEN_FCN (icode
) (target
);
8391 case SPE_BUILTIN_MTSPEFSCR
:
8392 icode
= CODE_FOR_spe_mtspefscr
;
8393 arg0
= CALL_EXPR_ARG (exp
, 0);
8394 op0
= expand_normal (arg0
);
8395 mode0
= insn_data
[icode
].operand
[0].mode
;
8397 if (arg0
== error_mark_node
)
8400 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
8401 op0
= copy_to_mode_reg (mode0
, op0
);
8403 pat
= GEN_FCN (icode
) (op0
);
8416 paired_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
8418 rtx pat
, scratch
, tmp
;
8419 tree form
= CALL_EXPR_ARG (exp
, 0);
8420 tree arg0
= CALL_EXPR_ARG (exp
, 1);
8421 tree arg1
= CALL_EXPR_ARG (exp
, 2);
8422 rtx op0
= expand_normal (arg0
);
8423 rtx op1
= expand_normal (arg1
);
8424 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
8425 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
8429 if (TREE_CODE (form
) != INTEGER_CST
)
8431 error ("argument 1 of __builtin_paired_predicate must be a constant");
8435 form_int
= TREE_INT_CST_LOW (form
);
8437 gcc_assert (mode0
== mode1
);
8439 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
8443 || GET_MODE (target
) != SImode
8444 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
8445 target
= gen_reg_rtx (SImode
);
8446 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8447 op0
= copy_to_mode_reg (mode0
, op0
);
8448 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
8449 op1
= copy_to_mode_reg (mode1
, op1
);
8451 scratch
= gen_reg_rtx (CCFPmode
);
8453 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
8475 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
8478 error ("argument 1 of __builtin_paired_predicate is out of range");
8482 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
8483 emit_move_insn (target
, tmp
);
8488 spe_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
8490 rtx pat
, scratch
, tmp
;
8491 tree form
= CALL_EXPR_ARG (exp
, 0);
8492 tree arg0
= CALL_EXPR_ARG (exp
, 1);
8493 tree arg1
= CALL_EXPR_ARG (exp
, 2);
8494 rtx op0
= expand_normal (arg0
);
8495 rtx op1
= expand_normal (arg1
);
8496 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
8497 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
8501 if (TREE_CODE (form
) != INTEGER_CST
)
8503 error ("argument 1 of __builtin_spe_predicate must be a constant");
8507 form_int
= TREE_INT_CST_LOW (form
);
8509 gcc_assert (mode0
== mode1
);
8511 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
8515 || GET_MODE (target
) != SImode
8516 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
8517 target
= gen_reg_rtx (SImode
);
8519 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8520 op0
= copy_to_mode_reg (mode0
, op0
);
8521 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
8522 op1
= copy_to_mode_reg (mode1
, op1
);
8524 scratch
= gen_reg_rtx (CCmode
);
8526 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
8531 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
8532 _lower_. We use one compare, but look in different bits of the
8533 CR for each variant.
8535 There are 2 elements in each SPE simd type (upper/lower). The CR
8536 bits are set as follows:
8538 BIT0 | BIT 1 | BIT 2 | BIT 3
8539 U | L | (U | L) | (U & L)
8541 So, for an "all" relationship, BIT 3 would be set.
8542 For an "any" relationship, BIT 2 would be set. Etc.
8544 Following traditional nomenclature, these bits map to:
8546 BIT0 | BIT 1 | BIT 2 | BIT 3
8549 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
8554 /* All variant. OV bit. */
8556 /* We need to get to the OV bit, which is the ORDERED bit. We
8557 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
8558 that's ugly and will make validate_condition_mode die.
8559 So let's just use another pattern. */
8560 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
8562 /* Any variant. EQ bit. */
8566 /* Upper variant. LT bit. */
8570 /* Lower variant. GT bit. */
8575 error ("argument 1 of __builtin_spe_predicate is out of range");
8579 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
8580 emit_move_insn (target
, tmp
);
8585 /* The evsel builtins look like this:
8587 e = __builtin_spe_evsel_OP (a, b, c, d);
8591 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
8592 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
8596 spe_expand_evsel_builtin (enum insn_code icode
, tree exp
, rtx target
)
8599 tree arg0
= CALL_EXPR_ARG (exp
, 0);
8600 tree arg1
= CALL_EXPR_ARG (exp
, 1);
8601 tree arg2
= CALL_EXPR_ARG (exp
, 2);
8602 tree arg3
= CALL_EXPR_ARG (exp
, 3);
8603 rtx op0
= expand_normal (arg0
);
8604 rtx op1
= expand_normal (arg1
);
8605 rtx op2
= expand_normal (arg2
);
8606 rtx op3
= expand_normal (arg3
);
8607 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
8608 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
8610 gcc_assert (mode0
== mode1
);
8612 if (arg0
== error_mark_node
|| arg1
== error_mark_node
8613 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
8617 || GET_MODE (target
) != mode0
8618 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
8619 target
= gen_reg_rtx (mode0
);
8621 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8622 op0
= copy_to_mode_reg (mode0
, op0
);
8623 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
8624 op1
= copy_to_mode_reg (mode0
, op1
);
8625 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
8626 op2
= copy_to_mode_reg (mode0
, op2
);
8627 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
8628 op3
= copy_to_mode_reg (mode0
, op3
);
8630 /* Generate the compare. */
8631 scratch
= gen_reg_rtx (CCmode
);
8632 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
8637 if (mode0
== V2SImode
)
8638 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
8640 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
8645 /* Expand an expression EXP that calls a built-in function,
8646 with result going to TARGET if that's convenient
8647 (and in mode MODE if that's convenient).
8648 SUBTARGET may be used as the target for computing one of EXP's operands.
8649 IGNORE is nonzero if the value is to be ignored. */
8652 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
8653 enum machine_mode mode ATTRIBUTE_UNUSED
,
8654 int ignore ATTRIBUTE_UNUSED
)
8656 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8657 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8658 const struct builtin_description
*d
;
8663 if (fcode
== RS6000_BUILTIN_RECIP
)
8664 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
8666 if (fcode
== RS6000_BUILTIN_RECIPF
)
8667 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
8669 if (fcode
== RS6000_BUILTIN_RSQRTF
)
8670 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
8672 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_LOAD
8673 || fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
8675 int icode
= (int) CODE_FOR_altivec_lvsr
;
8676 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
8677 enum machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
8681 gcc_assert (TARGET_ALTIVEC
);
8683 arg
= CALL_EXPR_ARG (exp
, 0);
8684 gcc_assert (TREE_CODE (TREE_TYPE (arg
)) == POINTER_TYPE
);
8685 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
8686 addr
= memory_address (mode
, op
);
8687 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
8691 /* For the load case need to negate the address. */
8692 op
= gen_reg_rtx (GET_MODE (addr
));
8693 emit_insn (gen_rtx_SET (VOIDmode
, op
,
8694 gen_rtx_NEG (GET_MODE (addr
), addr
)));
8696 op
= gen_rtx_MEM (mode
, op
);
8699 || GET_MODE (target
) != tmode
8700 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8701 target
= gen_reg_rtx (tmode
);
8703 /*pat = gen_altivec_lvsr (target, op);*/
8704 pat
= GEN_FCN (icode
) (target
, op
);
8712 /* FIXME: There's got to be a nicer way to handle this case than
8713 constructing a new CALL_EXPR. */
8714 if (fcode
== ALTIVEC_BUILTIN_VCFUX
8715 || fcode
== ALTIVEC_BUILTIN_VCFSX
)
8717 if (call_expr_nargs (exp
) == 1)
8718 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
8719 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
8724 ret
= altivec_expand_builtin (exp
, target
, &success
);
8731 ret
= spe_expand_builtin (exp
, target
, &success
);
8736 if (TARGET_PAIRED_FLOAT
)
8738 ret
= paired_expand_builtin (exp
, target
, &success
);
8744 gcc_assert (TARGET_ALTIVEC
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
);
8746 /* Handle simple unary operations. */
8747 d
= (struct builtin_description
*) bdesc_1arg
;
8748 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
8749 if (d
->code
== fcode
)
8750 return rs6000_expand_unop_builtin (d
->icode
, exp
, target
);
8752 /* Handle simple binary operations. */
8753 d
= (struct builtin_description
*) bdesc_2arg
;
8754 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
8755 if (d
->code
== fcode
)
8756 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
8758 /* Handle simple ternary operations. */
8760 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
8761 if (d
->code
== fcode
)
8762 return rs6000_expand_ternop_builtin (d
->icode
, exp
, target
);
8768 build_opaque_vector_type (tree node
, int nunits
)
8770 node
= copy_node (node
);
8771 TYPE_MAIN_VARIANT (node
) = node
;
8772 return build_vector_type (node
, nunits
);
8776 rs6000_init_builtins (void)
8778 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
8779 V2SF_type_node
= build_vector_type (float_type_node
, 2);
8780 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
8781 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
8782 V4SF_type_node
= build_vector_type (float_type_node
, 4);
8783 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
8784 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
8786 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
8787 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
8788 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
8790 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
8791 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
8792 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
8793 opaque_V4SI_type_node
= copy_node (V4SI_type_node
);
8795 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
8796 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
8797 'vector unsigned short'. */
8799 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
8800 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
8801 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
8802 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
8804 long_integer_type_internal_node
= long_integer_type_node
;
8805 long_unsigned_type_internal_node
= long_unsigned_type_node
;
8806 intQI_type_internal_node
= intQI_type_node
;
8807 uintQI_type_internal_node
= unsigned_intQI_type_node
;
8808 intHI_type_internal_node
= intHI_type_node
;
8809 uintHI_type_internal_node
= unsigned_intHI_type_node
;
8810 intSI_type_internal_node
= intSI_type_node
;
8811 uintSI_type_internal_node
= unsigned_intSI_type_node
;
8812 float_type_internal_node
= float_type_node
;
8813 void_type_internal_node
= void_type_node
;
8815 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
8816 get_identifier ("__bool char"),
8817 bool_char_type_node
));
8818 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
8819 get_identifier ("__bool short"),
8820 bool_short_type_node
));
8821 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
8822 get_identifier ("__bool int"),
8823 bool_int_type_node
));
8824 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
8825 get_identifier ("__pixel"),
8828 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
8829 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
8830 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
8831 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
8833 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
8834 get_identifier ("__vector unsigned char"),
8835 unsigned_V16QI_type_node
));
8836 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
8837 get_identifier ("__vector signed char"),
8839 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
8840 get_identifier ("__vector __bool char"),
8841 bool_V16QI_type_node
));
8843 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
8844 get_identifier ("__vector unsigned short"),
8845 unsigned_V8HI_type_node
));
8846 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
8847 get_identifier ("__vector signed short"),
8849 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
8850 get_identifier ("__vector __bool short"),
8851 bool_V8HI_type_node
));
8853 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
8854 get_identifier ("__vector unsigned int"),
8855 unsigned_V4SI_type_node
));
8856 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
8857 get_identifier ("__vector signed int"),
8859 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
8860 get_identifier ("__vector __bool int"),
8861 bool_V4SI_type_node
));
8863 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
8864 get_identifier ("__vector float"),
8866 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
8867 get_identifier ("__vector __pixel"),
8868 pixel_V8HI_type_node
));
8870 if (TARGET_PAIRED_FLOAT
)
8871 paired_init_builtins ();
8873 spe_init_builtins ();
8875 altivec_init_builtins ();
8876 if (TARGET_ALTIVEC
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
)
8877 rs6000_common_init_builtins ();
8878 if (TARGET_PPC_GFXOPT
)
8880 tree ftype
= build_function_type_list (float_type_node
,
8884 def_builtin (MASK_PPC_GFXOPT
, "__builtin_recipdivf", ftype
,
8885 RS6000_BUILTIN_RECIPF
);
8887 ftype
= build_function_type_list (float_type_node
,
8890 def_builtin (MASK_PPC_GFXOPT
, "__builtin_rsqrtf", ftype
,
8891 RS6000_BUILTIN_RSQRTF
);
8895 tree ftype
= build_function_type_list (double_type_node
,
8899 def_builtin (MASK_POPCNTB
, "__builtin_recipdiv", ftype
,
8900 RS6000_BUILTIN_RECIP
);
8905 /* AIX libm provides clog as __clog. */
8906 if (built_in_decls
[BUILT_IN_CLOG
])
8907 set_user_assembler_name (built_in_decls
[BUILT_IN_CLOG
], "__clog");
8911 /* Search through a set of builtins and enable the mask bits.
8912 DESC is an array of builtins.
8913 SIZE is the total number of builtins.
8914 START is the builtin enum at which to start.
8915 END is the builtin enum at which to end. */
8917 enable_mask_for_builtins (struct builtin_description
*desc
, int size
,
8918 enum rs6000_builtins start
,
8919 enum rs6000_builtins end
)
8923 for (i
= 0; i
< size
; ++i
)
8924 if (desc
[i
].code
== start
)
8930 for (; i
< size
; ++i
)
8932 /* Flip all the bits on. */
8933 desc
[i
].mask
= target_flags
;
8934 if (desc
[i
].code
== end
)
8940 spe_init_builtins (void)
8942 tree endlink
= void_list_node
;
8943 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
8944 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
8945 struct builtin_description
*d
;
8948 tree v2si_ftype_4_v2si
8949 = build_function_type
8950 (opaque_V2SI_type_node
,
8951 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8952 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8953 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8954 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8957 tree v2sf_ftype_4_v2sf
8958 = build_function_type
8959 (opaque_V2SF_type_node
,
8960 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
8961 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
8962 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
8963 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
8966 tree int_ftype_int_v2si_v2si
8967 = build_function_type
8969 tree_cons (NULL_TREE
, integer_type_node
,
8970 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8971 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8974 tree int_ftype_int_v2sf_v2sf
8975 = build_function_type
8977 tree_cons (NULL_TREE
, integer_type_node
,
8978 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
8979 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
8982 tree void_ftype_v2si_puint_int
8983 = build_function_type (void_type_node
,
8984 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8985 tree_cons (NULL_TREE
, puint_type_node
,
8986 tree_cons (NULL_TREE
,
8990 tree void_ftype_v2si_puint_char
8991 = build_function_type (void_type_node
,
8992 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
8993 tree_cons (NULL_TREE
, puint_type_node
,
8994 tree_cons (NULL_TREE
,
8998 tree void_ftype_v2si_pv2si_int
8999 = build_function_type (void_type_node
,
9000 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9001 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
9002 tree_cons (NULL_TREE
,
9006 tree void_ftype_v2si_pv2si_char
9007 = build_function_type (void_type_node
,
9008 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9009 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
9010 tree_cons (NULL_TREE
,
9015 = build_function_type (void_type_node
,
9016 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
9019 = build_function_type (integer_type_node
, endlink
);
9021 tree v2si_ftype_pv2si_int
9022 = build_function_type (opaque_V2SI_type_node
,
9023 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
9024 tree_cons (NULL_TREE
, integer_type_node
,
9027 tree v2si_ftype_puint_int
9028 = build_function_type (opaque_V2SI_type_node
,
9029 tree_cons (NULL_TREE
, puint_type_node
,
9030 tree_cons (NULL_TREE
, integer_type_node
,
9033 tree v2si_ftype_pushort_int
9034 = build_function_type (opaque_V2SI_type_node
,
9035 tree_cons (NULL_TREE
, pushort_type_node
,
9036 tree_cons (NULL_TREE
, integer_type_node
,
9039 tree v2si_ftype_signed_char
9040 = build_function_type (opaque_V2SI_type_node
,
9041 tree_cons (NULL_TREE
, signed_char_type_node
,
9044 /* The initialization of the simple binary and unary builtins is
9045 done in rs6000_common_init_builtins, but we have to enable the
9046 mask bits here manually because we have run out of `target_flags'
9047 bits. We really need to redesign this mask business. */
9049 enable_mask_for_builtins ((struct builtin_description
*) bdesc_2arg
,
9050 ARRAY_SIZE (bdesc_2arg
),
9053 enable_mask_for_builtins ((struct builtin_description
*) bdesc_1arg
,
9054 ARRAY_SIZE (bdesc_1arg
),
9056 SPE_BUILTIN_EVSUBFUSIAAW
);
9057 enable_mask_for_builtins ((struct builtin_description
*) bdesc_spe_predicates
,
9058 ARRAY_SIZE (bdesc_spe_predicates
),
9059 SPE_BUILTIN_EVCMPEQ
,
9060 SPE_BUILTIN_EVFSTSTLT
);
9061 enable_mask_for_builtins ((struct builtin_description
*) bdesc_spe_evsel
,
9062 ARRAY_SIZE (bdesc_spe_evsel
),
9063 SPE_BUILTIN_EVSEL_CMPGTS
,
9064 SPE_BUILTIN_EVSEL_FSTSTEQ
);
9066 (*lang_hooks
.decls
.pushdecl
)
9067 (build_decl (TYPE_DECL
, get_identifier ("__ev64_opaque__"),
9068 opaque_V2SI_type_node
));
9070 /* Initialize irregular SPE builtins. */
9072 def_builtin (target_flags
, "__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
9073 def_builtin (target_flags
, "__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
9074 def_builtin (target_flags
, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
9075 def_builtin (target_flags
, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
9076 def_builtin (target_flags
, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
9077 def_builtin (target_flags
, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
9078 def_builtin (target_flags
, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
9079 def_builtin (target_flags
, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
9080 def_builtin (target_flags
, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
9081 def_builtin (target_flags
, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
9082 def_builtin (target_flags
, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
9083 def_builtin (target_flags
, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
9084 def_builtin (target_flags
, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
9085 def_builtin (target_flags
, "__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
9086 def_builtin (target_flags
, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
9087 def_builtin (target_flags
, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
9088 def_builtin (target_flags
, "__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
9089 def_builtin (target_flags
, "__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
9092 def_builtin (target_flags
, "__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
9093 def_builtin (target_flags
, "__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
9094 def_builtin (target_flags
, "__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
9095 def_builtin (target_flags
, "__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
9096 def_builtin (target_flags
, "__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
9097 def_builtin (target_flags
, "__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
9098 def_builtin (target_flags
, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
9099 def_builtin (target_flags
, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
9100 def_builtin (target_flags
, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
9101 def_builtin (target_flags
, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
9102 def_builtin (target_flags
, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
9103 def_builtin (target_flags
, "__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
9104 def_builtin (target_flags
, "__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
9105 def_builtin (target_flags
, "__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
9106 def_builtin (target_flags
, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
9107 def_builtin (target_flags
, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
9108 def_builtin (target_flags
, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
9109 def_builtin (target_flags
, "__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
9110 def_builtin (target_flags
, "__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
9111 def_builtin (target_flags
, "__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
9112 def_builtin (target_flags
, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
9113 def_builtin (target_flags
, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
9116 d
= (struct builtin_description
*) bdesc_spe_predicates
;
9117 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
9121 switch (insn_data
[d
->icode
].operand
[1].mode
)
9124 type
= int_ftype_int_v2si_v2si
;
9127 type
= int_ftype_int_v2sf_v2sf
;
9133 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
9136 /* Evsel predicates. */
9137 d
= (struct builtin_description
*) bdesc_spe_evsel
;
9138 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
9142 switch (insn_data
[d
->icode
].operand
[1].mode
)
9145 type
= v2si_ftype_4_v2si
;
9148 type
= v2sf_ftype_4_v2sf
;
9154 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
9159 paired_init_builtins (void)
9161 const struct builtin_description
*d
;
9163 tree endlink
= void_list_node
;
9165 tree int_ftype_int_v2sf_v2sf
9166 = build_function_type
9168 tree_cons (NULL_TREE
, integer_type_node
,
9169 tree_cons (NULL_TREE
, V2SF_type_node
,
9170 tree_cons (NULL_TREE
, V2SF_type_node
,
9172 tree pcfloat_type_node
=
9173 build_pointer_type (build_qualified_type
9174 (float_type_node
, TYPE_QUAL_CONST
));
9176 tree v2sf_ftype_long_pcfloat
= build_function_type_list (V2SF_type_node
,
9177 long_integer_type_node
,
9180 tree void_ftype_v2sf_long_pcfloat
=
9181 build_function_type_list (void_type_node
,
9183 long_integer_type_node
,
9188 def_builtin (0, "__builtin_paired_lx", v2sf_ftype_long_pcfloat
,
9192 def_builtin (0, "__builtin_paired_stx", void_ftype_v2sf_long_pcfloat
,
9193 PAIRED_BUILTIN_STX
);
9196 d
= bdesc_paired_preds
;
9197 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); ++i
, d
++)
9201 switch (insn_data
[d
->icode
].operand
[1].mode
)
9204 type
= int_ftype_int_v2sf_v2sf
;
9210 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
9215 altivec_init_builtins (void)
9217 const struct builtin_description
*d
;
9218 const struct builtin_description_predicates
*dp
;
9222 tree pfloat_type_node
= build_pointer_type (float_type_node
);
9223 tree pint_type_node
= build_pointer_type (integer_type_node
);
9224 tree pshort_type_node
= build_pointer_type (short_integer_type_node
);
9225 tree pchar_type_node
= build_pointer_type (char_type_node
);
9227 tree pvoid_type_node
= build_pointer_type (void_type_node
);
9229 tree pcfloat_type_node
= build_pointer_type (build_qualified_type (float_type_node
, TYPE_QUAL_CONST
));
9230 tree pcint_type_node
= build_pointer_type (build_qualified_type (integer_type_node
, TYPE_QUAL_CONST
));
9231 tree pcshort_type_node
= build_pointer_type (build_qualified_type (short_integer_type_node
, TYPE_QUAL_CONST
));
9232 tree pcchar_type_node
= build_pointer_type (build_qualified_type (char_type_node
, TYPE_QUAL_CONST
));
9234 tree pcvoid_type_node
= build_pointer_type (build_qualified_type (void_type_node
, TYPE_QUAL_CONST
));
9236 tree int_ftype_opaque
9237 = build_function_type_list (integer_type_node
,
9238 opaque_V4SI_type_node
, NULL_TREE
);
9240 tree opaque_ftype_opaque_int
9241 = build_function_type_list (opaque_V4SI_type_node
,
9242 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
9243 tree opaque_ftype_opaque_opaque_int
9244 = build_function_type_list (opaque_V4SI_type_node
,
9245 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
9246 integer_type_node
, NULL_TREE
);
9247 tree int_ftype_int_opaque_opaque
9248 = build_function_type_list (integer_type_node
,
9249 integer_type_node
, opaque_V4SI_type_node
,
9250 opaque_V4SI_type_node
, NULL_TREE
);
9251 tree int_ftype_int_v4si_v4si
9252 = build_function_type_list (integer_type_node
,
9253 integer_type_node
, V4SI_type_node
,
9254 V4SI_type_node
, NULL_TREE
);
9255 tree v4sf_ftype_pcfloat
9256 = build_function_type_list (V4SF_type_node
, pcfloat_type_node
, NULL_TREE
);
9257 tree void_ftype_pfloat_v4sf
9258 = build_function_type_list (void_type_node
,
9259 pfloat_type_node
, V4SF_type_node
, NULL_TREE
);
9260 tree v4si_ftype_pcint
9261 = build_function_type_list (V4SI_type_node
, pcint_type_node
, NULL_TREE
);
9262 tree void_ftype_pint_v4si
9263 = build_function_type_list (void_type_node
,
9264 pint_type_node
, V4SI_type_node
, NULL_TREE
);
9265 tree v8hi_ftype_pcshort
9266 = build_function_type_list (V8HI_type_node
, pcshort_type_node
, NULL_TREE
);
9267 tree void_ftype_pshort_v8hi
9268 = build_function_type_list (void_type_node
,
9269 pshort_type_node
, V8HI_type_node
, NULL_TREE
);
9270 tree v16qi_ftype_pcchar
9271 = build_function_type_list (V16QI_type_node
, pcchar_type_node
, NULL_TREE
);
9272 tree void_ftype_pchar_v16qi
9273 = build_function_type_list (void_type_node
,
9274 pchar_type_node
, V16QI_type_node
, NULL_TREE
);
9275 tree void_ftype_v4si
9276 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
9277 tree v8hi_ftype_void
9278 = build_function_type (V8HI_type_node
, void_list_node
);
9279 tree void_ftype_void
9280 = build_function_type (void_type_node
, void_list_node
);
9282 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
9284 tree opaque_ftype_long_pcvoid
9285 = build_function_type_list (opaque_V4SI_type_node
,
9286 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
9287 tree v16qi_ftype_long_pcvoid
9288 = build_function_type_list (V16QI_type_node
,
9289 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
9290 tree v8hi_ftype_long_pcvoid
9291 = build_function_type_list (V8HI_type_node
,
9292 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
9293 tree v4si_ftype_long_pcvoid
9294 = build_function_type_list (V4SI_type_node
,
9295 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
9297 tree void_ftype_opaque_long_pvoid
9298 = build_function_type_list (void_type_node
,
9299 opaque_V4SI_type_node
, long_integer_type_node
,
9300 pvoid_type_node
, NULL_TREE
);
9301 tree void_ftype_v4si_long_pvoid
9302 = build_function_type_list (void_type_node
,
9303 V4SI_type_node
, long_integer_type_node
,
9304 pvoid_type_node
, NULL_TREE
);
9305 tree void_ftype_v16qi_long_pvoid
9306 = build_function_type_list (void_type_node
,
9307 V16QI_type_node
, long_integer_type_node
,
9308 pvoid_type_node
, NULL_TREE
);
9309 tree void_ftype_v8hi_long_pvoid
9310 = build_function_type_list (void_type_node
,
9311 V8HI_type_node
, long_integer_type_node
,
9312 pvoid_type_node
, NULL_TREE
);
9313 tree int_ftype_int_v8hi_v8hi
9314 = build_function_type_list (integer_type_node
,
9315 integer_type_node
, V8HI_type_node
,
9316 V8HI_type_node
, NULL_TREE
);
9317 tree int_ftype_int_v16qi_v16qi
9318 = build_function_type_list (integer_type_node
,
9319 integer_type_node
, V16QI_type_node
,
9320 V16QI_type_node
, NULL_TREE
);
9321 tree int_ftype_int_v4sf_v4sf
9322 = build_function_type_list (integer_type_node
,
9323 integer_type_node
, V4SF_type_node
,
9324 V4SF_type_node
, NULL_TREE
);
9325 tree v4si_ftype_v4si
9326 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
9327 tree v8hi_ftype_v8hi
9328 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
9329 tree v16qi_ftype_v16qi
9330 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
9331 tree v4sf_ftype_v4sf
9332 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
9333 tree void_ftype_pcvoid_int_int
9334 = build_function_type_list (void_type_node
,
9335 pcvoid_type_node
, integer_type_node
,
9336 integer_type_node
, NULL_TREE
);
9338 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat
,
9339 ALTIVEC_BUILTIN_LD_INTERNAL_4sf
);
9340 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf
,
9341 ALTIVEC_BUILTIN_ST_INTERNAL_4sf
);
9342 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint
,
9343 ALTIVEC_BUILTIN_LD_INTERNAL_4si
);
9344 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si
,
9345 ALTIVEC_BUILTIN_ST_INTERNAL_4si
);
9346 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort
,
9347 ALTIVEC_BUILTIN_LD_INTERNAL_8hi
);
9348 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi
,
9349 ALTIVEC_BUILTIN_ST_INTERNAL_8hi
);
9350 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar
,
9351 ALTIVEC_BUILTIN_LD_INTERNAL_16qi
);
9352 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi
,
9353 ALTIVEC_BUILTIN_ST_INTERNAL_16qi
);
9354 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
9355 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
9356 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
9357 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
9358 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
9359 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
9360 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
9361 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
9362 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
9363 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
9364 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
9365 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
9366 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
9367 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
9368 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
9369 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
9370 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
9371 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
9372 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
9373 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
9374 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
9375 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
9376 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
9377 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
9378 def_builtin (MASK_ALTIVEC
, "__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
9379 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
9380 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
9381 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
9382 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
9383 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
9385 def_builtin (MASK_ALTIVEC
, "__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
9387 def_builtin (MASK_ALTIVEC
, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
9388 def_builtin (MASK_ALTIVEC
, "__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
9389 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
9390 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
9391 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
9392 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
9393 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
9394 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
9395 def_builtin (MASK_ALTIVEC
, "__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
9396 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
9398 /* Add the DST variants. */
9400 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
9401 def_builtin (d
->mask
, d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
9403 /* Initialize the predicates. */
9404 dp
= bdesc_altivec_preds
;
9405 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, dp
++)
9407 enum machine_mode mode1
;
9409 bool is_overloaded
= dp
->code
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9410 && dp
->code
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
;
9415 mode1
= insn_data
[dp
->icode
].operand
[1].mode
;
9420 type
= int_ftype_int_opaque_opaque
;
9423 type
= int_ftype_int_v4si_v4si
;
9426 type
= int_ftype_int_v8hi_v8hi
;
9429 type
= int_ftype_int_v16qi_v16qi
;
9432 type
= int_ftype_int_v4sf_v4sf
;
9438 def_builtin (dp
->mask
, dp
->name
, type
, dp
->code
);
9441 /* Initialize the abs* operators. */
9443 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
9445 enum machine_mode mode0
;
9448 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
9453 type
= v4si_ftype_v4si
;
9456 type
= v8hi_ftype_v8hi
;
9459 type
= v16qi_ftype_v16qi
;
9462 type
= v4sf_ftype_v4sf
;
9468 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
9475 /* Initialize target builtin that implements
9476 targetm.vectorize.builtin_mask_for_load. */
9478 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
9479 v16qi_ftype_long_pcvoid
,
9480 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
9481 BUILT_IN_MD
, NULL
, NULL_TREE
);
9482 TREE_READONLY (decl
) = 1;
9483 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
9484 altivec_builtin_mask_for_load
= decl
;
9487 /* Access to the vec_init patterns. */
9488 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
9489 integer_type_node
, integer_type_node
,
9490 integer_type_node
, NULL_TREE
);
9491 def_builtin (MASK_ALTIVEC
, "__builtin_vec_init_v4si", ftype
,
9492 ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
9494 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
9495 short_integer_type_node
,
9496 short_integer_type_node
,
9497 short_integer_type_node
,
9498 short_integer_type_node
,
9499 short_integer_type_node
,
9500 short_integer_type_node
,
9501 short_integer_type_node
, NULL_TREE
);
9502 def_builtin (MASK_ALTIVEC
, "__builtin_vec_init_v8hi", ftype
,
9503 ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
9505 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
9506 char_type_node
, char_type_node
,
9507 char_type_node
, char_type_node
,
9508 char_type_node
, char_type_node
,
9509 char_type_node
, char_type_node
,
9510 char_type_node
, char_type_node
,
9511 char_type_node
, char_type_node
,
9512 char_type_node
, char_type_node
,
9513 char_type_node
, NULL_TREE
);
9514 def_builtin (MASK_ALTIVEC
, "__builtin_vec_init_v16qi", ftype
,
9515 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
9517 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
9518 float_type_node
, float_type_node
,
9519 float_type_node
, NULL_TREE
);
9520 def_builtin (MASK_ALTIVEC
, "__builtin_vec_init_v4sf", ftype
,
9521 ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
9523 /* Access to the vec_set patterns. */
9524 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
9526 integer_type_node
, NULL_TREE
);
9527 def_builtin (MASK_ALTIVEC
, "__builtin_vec_set_v4si", ftype
,
9528 ALTIVEC_BUILTIN_VEC_SET_V4SI
);
9530 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
9532 integer_type_node
, NULL_TREE
);
9533 def_builtin (MASK_ALTIVEC
, "__builtin_vec_set_v8hi", ftype
,
9534 ALTIVEC_BUILTIN_VEC_SET_V8HI
);
9536 ftype
= build_function_type_list (V8HI_type_node
, V16QI_type_node
,
9538 integer_type_node
, NULL_TREE
);
9539 def_builtin (MASK_ALTIVEC
, "__builtin_vec_set_v16qi", ftype
,
9540 ALTIVEC_BUILTIN_VEC_SET_V16QI
);
9542 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
9544 integer_type_node
, NULL_TREE
);
9545 def_builtin (MASK_ALTIVEC
, "__builtin_vec_set_v4sf", ftype
,
9546 ALTIVEC_BUILTIN_VEC_SET_V4SF
);
9548 /* Access to the vec_extract patterns. */
9549 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
9550 integer_type_node
, NULL_TREE
);
9551 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ext_v4si", ftype
,
9552 ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
9554 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
9555 integer_type_node
, NULL_TREE
);
9556 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ext_v8hi", ftype
,
9557 ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
9559 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
9560 integer_type_node
, NULL_TREE
);
9561 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ext_v16qi", ftype
,
9562 ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
9564 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
9565 integer_type_node
, NULL_TREE
);
9566 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ext_v4sf", ftype
,
9567 ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
9571 rs6000_common_init_builtins (void)
9573 const struct builtin_description
*d
;
9576 tree v2sf_ftype_v2sf_v2sf_v2sf
9577 = build_function_type_list (V2SF_type_node
,
9578 V2SF_type_node
, V2SF_type_node
,
9579 V2SF_type_node
, NULL_TREE
);
9581 tree v4sf_ftype_v4sf_v4sf_v16qi
9582 = build_function_type_list (V4SF_type_node
,
9583 V4SF_type_node
, V4SF_type_node
,
9584 V16QI_type_node
, NULL_TREE
);
9585 tree v4si_ftype_v4si_v4si_v16qi
9586 = build_function_type_list (V4SI_type_node
,
9587 V4SI_type_node
, V4SI_type_node
,
9588 V16QI_type_node
, NULL_TREE
);
9589 tree v8hi_ftype_v8hi_v8hi_v16qi
9590 = build_function_type_list (V8HI_type_node
,
9591 V8HI_type_node
, V8HI_type_node
,
9592 V16QI_type_node
, NULL_TREE
);
9593 tree v16qi_ftype_v16qi_v16qi_v16qi
9594 = build_function_type_list (V16QI_type_node
,
9595 V16QI_type_node
, V16QI_type_node
,
9596 V16QI_type_node
, NULL_TREE
);
9598 = build_function_type_list (V4SI_type_node
, integer_type_node
, NULL_TREE
);
9600 = build_function_type_list (V8HI_type_node
, integer_type_node
, NULL_TREE
);
9601 tree v16qi_ftype_int
9602 = build_function_type_list (V16QI_type_node
, integer_type_node
, NULL_TREE
);
9603 tree v8hi_ftype_v16qi
9604 = build_function_type_list (V8HI_type_node
, V16QI_type_node
, NULL_TREE
);
9605 tree v4sf_ftype_v4sf
9606 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
9608 tree v2si_ftype_v2si_v2si
9609 = build_function_type_list (opaque_V2SI_type_node
,
9610 opaque_V2SI_type_node
,
9611 opaque_V2SI_type_node
, NULL_TREE
);
9613 tree v2sf_ftype_v2sf_v2sf_spe
9614 = build_function_type_list (opaque_V2SF_type_node
,
9615 opaque_V2SF_type_node
,
9616 opaque_V2SF_type_node
, NULL_TREE
);
9618 tree v2sf_ftype_v2sf_v2sf
9619 = build_function_type_list (V2SF_type_node
,
9621 V2SF_type_node
, NULL_TREE
);
9624 tree v2si_ftype_int_int
9625 = build_function_type_list (opaque_V2SI_type_node
,
9626 integer_type_node
, integer_type_node
,
9629 tree opaque_ftype_opaque
9630 = build_function_type_list (opaque_V4SI_type_node
,
9631 opaque_V4SI_type_node
, NULL_TREE
);
9633 tree v2si_ftype_v2si
9634 = build_function_type_list (opaque_V2SI_type_node
,
9635 opaque_V2SI_type_node
, NULL_TREE
);
9637 tree v2sf_ftype_v2sf_spe
9638 = build_function_type_list (opaque_V2SF_type_node
,
9639 opaque_V2SF_type_node
, NULL_TREE
);
9641 tree v2sf_ftype_v2sf
9642 = build_function_type_list (V2SF_type_node
,
9643 V2SF_type_node
, NULL_TREE
);
9645 tree v2sf_ftype_v2si
9646 = build_function_type_list (opaque_V2SF_type_node
,
9647 opaque_V2SI_type_node
, NULL_TREE
);
9649 tree v2si_ftype_v2sf
9650 = build_function_type_list (opaque_V2SI_type_node
,
9651 opaque_V2SF_type_node
, NULL_TREE
);
9653 tree v2si_ftype_v2si_char
9654 = build_function_type_list (opaque_V2SI_type_node
,
9655 opaque_V2SI_type_node
,
9656 char_type_node
, NULL_TREE
);
9658 tree v2si_ftype_int_char
9659 = build_function_type_list (opaque_V2SI_type_node
,
9660 integer_type_node
, char_type_node
, NULL_TREE
);
9662 tree v2si_ftype_char
9663 = build_function_type_list (opaque_V2SI_type_node
,
9664 char_type_node
, NULL_TREE
);
9666 tree int_ftype_int_int
9667 = build_function_type_list (integer_type_node
,
9668 integer_type_node
, integer_type_node
,
9671 tree opaque_ftype_opaque_opaque
9672 = build_function_type_list (opaque_V4SI_type_node
,
9673 opaque_V4SI_type_node
, opaque_V4SI_type_node
, NULL_TREE
);
9674 tree v4si_ftype_v4si_v4si
9675 = build_function_type_list (V4SI_type_node
,
9676 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
9677 tree v4sf_ftype_v4si_int
9678 = build_function_type_list (V4SF_type_node
,
9679 V4SI_type_node
, integer_type_node
, NULL_TREE
);
9680 tree v4si_ftype_v4sf_int
9681 = build_function_type_list (V4SI_type_node
,
9682 V4SF_type_node
, integer_type_node
, NULL_TREE
);
9683 tree v4si_ftype_v4si_int
9684 = build_function_type_list (V4SI_type_node
,
9685 V4SI_type_node
, integer_type_node
, NULL_TREE
);
9686 tree v8hi_ftype_v8hi_int
9687 = build_function_type_list (V8HI_type_node
,
9688 V8HI_type_node
, integer_type_node
, NULL_TREE
);
9689 tree v16qi_ftype_v16qi_int
9690 = build_function_type_list (V16QI_type_node
,
9691 V16QI_type_node
, integer_type_node
, NULL_TREE
);
9692 tree v16qi_ftype_v16qi_v16qi_int
9693 = build_function_type_list (V16QI_type_node
,
9694 V16QI_type_node
, V16QI_type_node
,
9695 integer_type_node
, NULL_TREE
);
9696 tree v8hi_ftype_v8hi_v8hi_int
9697 = build_function_type_list (V8HI_type_node
,
9698 V8HI_type_node
, V8HI_type_node
,
9699 integer_type_node
, NULL_TREE
);
9700 tree v4si_ftype_v4si_v4si_int
9701 = build_function_type_list (V4SI_type_node
,
9702 V4SI_type_node
, V4SI_type_node
,
9703 integer_type_node
, NULL_TREE
);
9704 tree v4sf_ftype_v4sf_v4sf_int
9705 = build_function_type_list (V4SF_type_node
,
9706 V4SF_type_node
, V4SF_type_node
,
9707 integer_type_node
, NULL_TREE
);
9708 tree v4sf_ftype_v4sf_v4sf
9709 = build_function_type_list (V4SF_type_node
,
9710 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
9711 tree opaque_ftype_opaque_opaque_opaque
9712 = build_function_type_list (opaque_V4SI_type_node
,
9713 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
9714 opaque_V4SI_type_node
, NULL_TREE
);
9715 tree v4sf_ftype_v4sf_v4sf_v4si
9716 = build_function_type_list (V4SF_type_node
,
9717 V4SF_type_node
, V4SF_type_node
,
9718 V4SI_type_node
, NULL_TREE
);
9719 tree v4sf_ftype_v4sf_v4sf_v4sf
9720 = build_function_type_list (V4SF_type_node
,
9721 V4SF_type_node
, V4SF_type_node
,
9722 V4SF_type_node
, NULL_TREE
);
9723 tree v4si_ftype_v4si_v4si_v4si
9724 = build_function_type_list (V4SI_type_node
,
9725 V4SI_type_node
, V4SI_type_node
,
9726 V4SI_type_node
, NULL_TREE
);
9727 tree v8hi_ftype_v8hi_v8hi
9728 = build_function_type_list (V8HI_type_node
,
9729 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
9730 tree v8hi_ftype_v8hi_v8hi_v8hi
9731 = build_function_type_list (V8HI_type_node
,
9732 V8HI_type_node
, V8HI_type_node
,
9733 V8HI_type_node
, NULL_TREE
);
9734 tree v4si_ftype_v8hi_v8hi_v4si
9735 = build_function_type_list (V4SI_type_node
,
9736 V8HI_type_node
, V8HI_type_node
,
9737 V4SI_type_node
, NULL_TREE
);
9738 tree v4si_ftype_v16qi_v16qi_v4si
9739 = build_function_type_list (V4SI_type_node
,
9740 V16QI_type_node
, V16QI_type_node
,
9741 V4SI_type_node
, NULL_TREE
);
9742 tree v16qi_ftype_v16qi_v16qi
9743 = build_function_type_list (V16QI_type_node
,
9744 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
9745 tree v4si_ftype_v4sf_v4sf
9746 = build_function_type_list (V4SI_type_node
,
9747 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
9748 tree v8hi_ftype_v16qi_v16qi
9749 = build_function_type_list (V8HI_type_node
,
9750 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
9751 tree v4si_ftype_v8hi_v8hi
9752 = build_function_type_list (V4SI_type_node
,
9753 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
9754 tree v8hi_ftype_v4si_v4si
9755 = build_function_type_list (V8HI_type_node
,
9756 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
9757 tree v16qi_ftype_v8hi_v8hi
9758 = build_function_type_list (V16QI_type_node
,
9759 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
9760 tree v4si_ftype_v16qi_v4si
9761 = build_function_type_list (V4SI_type_node
,
9762 V16QI_type_node
, V4SI_type_node
, NULL_TREE
);
9763 tree v4si_ftype_v16qi_v16qi
9764 = build_function_type_list (V4SI_type_node
,
9765 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
9766 tree v4si_ftype_v8hi_v4si
9767 = build_function_type_list (V4SI_type_node
,
9768 V8HI_type_node
, V4SI_type_node
, NULL_TREE
);
9769 tree v4si_ftype_v8hi
9770 = build_function_type_list (V4SI_type_node
, V8HI_type_node
, NULL_TREE
);
9771 tree int_ftype_v4si_v4si
9772 = build_function_type_list (integer_type_node
,
9773 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
9774 tree int_ftype_v4sf_v4sf
9775 = build_function_type_list (integer_type_node
,
9776 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
9777 tree int_ftype_v16qi_v16qi
9778 = build_function_type_list (integer_type_node
,
9779 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
9780 tree int_ftype_v8hi_v8hi
9781 = build_function_type_list (integer_type_node
,
9782 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
9784 /* Add the simple ternary operators. */
9786 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
9788 enum machine_mode mode0
, mode1
, mode2
, mode3
;
9790 bool is_overloaded
= d
->code
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9791 && d
->code
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
;
9802 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
9805 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
9806 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
9807 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
9808 mode3
= insn_data
[d
->icode
].operand
[3].mode
;
9811 /* When all four are of the same mode. */
9812 if (mode0
== mode1
&& mode1
== mode2
&& mode2
== mode3
)
9817 type
= opaque_ftype_opaque_opaque_opaque
;
9820 type
= v4si_ftype_v4si_v4si_v4si
;
9823 type
= v4sf_ftype_v4sf_v4sf_v4sf
;
9826 type
= v8hi_ftype_v8hi_v8hi_v8hi
;
9829 type
= v16qi_ftype_v16qi_v16qi_v16qi
;
9832 type
= v2sf_ftype_v2sf_v2sf_v2sf
;
9838 else if (mode0
== mode1
&& mode1
== mode2
&& mode3
== V16QImode
)
9843 type
= v4si_ftype_v4si_v4si_v16qi
;
9846 type
= v4sf_ftype_v4sf_v4sf_v16qi
;
9849 type
= v8hi_ftype_v8hi_v8hi_v16qi
;
9852 type
= v16qi_ftype_v16qi_v16qi_v16qi
;
9858 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V16QImode
9859 && mode3
== V4SImode
)
9860 type
= v4si_ftype_v16qi_v16qi_v4si
;
9861 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V8HImode
9862 && mode3
== V4SImode
)
9863 type
= v4si_ftype_v8hi_v8hi_v4si
;
9864 else if (mode0
== V4SFmode
&& mode1
== V4SFmode
&& mode2
== V4SFmode
9865 && mode3
== V4SImode
)
9866 type
= v4sf_ftype_v4sf_v4sf_v4si
;
9868 /* vchar, vchar, vchar, 4-bit literal. */
9869 else if (mode0
== V16QImode
&& mode1
== mode0
&& mode2
== mode0
9871 type
= v16qi_ftype_v16qi_v16qi_int
;
9873 /* vshort, vshort, vshort, 4-bit literal. */
9874 else if (mode0
== V8HImode
&& mode1
== mode0
&& mode2
== mode0
9876 type
= v8hi_ftype_v8hi_v8hi_int
;
9878 /* vint, vint, vint, 4-bit literal. */
9879 else if (mode0
== V4SImode
&& mode1
== mode0
&& mode2
== mode0
9881 type
= v4si_ftype_v4si_v4si_int
;
9883 /* vfloat, vfloat, vfloat, 4-bit literal. */
9884 else if (mode0
== V4SFmode
&& mode1
== mode0
&& mode2
== mode0
9886 type
= v4sf_ftype_v4sf_v4sf_int
;
9891 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
9894 /* Add the simple binary operators. */
9895 d
= (struct builtin_description
*) bdesc_2arg
;
9896 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
9898 enum machine_mode mode0
, mode1
, mode2
;
9900 bool is_overloaded
= d
->code
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9901 && d
->code
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
;
9911 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
9914 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
9915 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
9916 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
9919 /* When all three operands are of the same mode. */
9920 if (mode0
== mode1
&& mode1
== mode2
)
9925 type
= opaque_ftype_opaque_opaque
;
9928 type
= v4sf_ftype_v4sf_v4sf
;
9931 type
= v4si_ftype_v4si_v4si
;
9934 type
= v16qi_ftype_v16qi_v16qi
;
9937 type
= v8hi_ftype_v8hi_v8hi
;
9940 type
= v2si_ftype_v2si_v2si
;
9943 if (TARGET_PAIRED_FLOAT
)
9944 type
= v2sf_ftype_v2sf_v2sf
;
9946 type
= v2sf_ftype_v2sf_v2sf_spe
;
9949 type
= int_ftype_int_int
;
9956 /* A few other combos we really don't want to do manually. */
9958 /* vint, vfloat, vfloat. */
9959 else if (mode0
== V4SImode
&& mode1
== V4SFmode
&& mode2
== V4SFmode
)
9960 type
= v4si_ftype_v4sf_v4sf
;
9962 /* vshort, vchar, vchar. */
9963 else if (mode0
== V8HImode
&& mode1
== V16QImode
&& mode2
== V16QImode
)
9964 type
= v8hi_ftype_v16qi_v16qi
;
9966 /* vint, vshort, vshort. */
9967 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V8HImode
)
9968 type
= v4si_ftype_v8hi_v8hi
;
9970 /* vshort, vint, vint. */
9971 else if (mode0
== V8HImode
&& mode1
== V4SImode
&& mode2
== V4SImode
)
9972 type
= v8hi_ftype_v4si_v4si
;
9974 /* vchar, vshort, vshort. */
9975 else if (mode0
== V16QImode
&& mode1
== V8HImode
&& mode2
== V8HImode
)
9976 type
= v16qi_ftype_v8hi_v8hi
;
9978 /* vint, vchar, vint. */
9979 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V4SImode
)
9980 type
= v4si_ftype_v16qi_v4si
;
9982 /* vint, vchar, vchar. */
9983 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V16QImode
)
9984 type
= v4si_ftype_v16qi_v16qi
;
9986 /* vint, vshort, vint. */
9987 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V4SImode
)
9988 type
= v4si_ftype_v8hi_v4si
;
9990 /* vint, vint, 5-bit literal. */
9991 else if (mode0
== V4SImode
&& mode1
== V4SImode
&& mode2
== QImode
)
9992 type
= v4si_ftype_v4si_int
;
9994 /* vshort, vshort, 5-bit literal. */
9995 else if (mode0
== V8HImode
&& mode1
== V8HImode
&& mode2
== QImode
)
9996 type
= v8hi_ftype_v8hi_int
;
9998 /* vchar, vchar, 5-bit literal. */
9999 else if (mode0
== V16QImode
&& mode1
== V16QImode
&& mode2
== QImode
)
10000 type
= v16qi_ftype_v16qi_int
;
10002 /* vfloat, vint, 5-bit literal. */
10003 else if (mode0
== V4SFmode
&& mode1
== V4SImode
&& mode2
== QImode
)
10004 type
= v4sf_ftype_v4si_int
;
10006 /* vint, vfloat, 5-bit literal. */
10007 else if (mode0
== V4SImode
&& mode1
== V4SFmode
&& mode2
== QImode
)
10008 type
= v4si_ftype_v4sf_int
;
10010 else if (mode0
== V2SImode
&& mode1
== SImode
&& mode2
== SImode
)
10011 type
= v2si_ftype_int_int
;
10013 else if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
10014 type
= v2si_ftype_v2si_char
;
10016 else if (mode0
== V2SImode
&& mode1
== SImode
&& mode2
== QImode
)
10017 type
= v2si_ftype_int_char
;
10022 gcc_assert (mode0
== SImode
);
10026 type
= int_ftype_v4si_v4si
;
10029 type
= int_ftype_v4sf_v4sf
;
10032 type
= int_ftype_v16qi_v16qi
;
10035 type
= int_ftype_v8hi_v8hi
;
10038 gcc_unreachable ();
10042 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
10045 /* Add the simple unary operators. */
10046 d
= (struct builtin_description
*) bdesc_1arg
;
10047 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
10049 enum machine_mode mode0
, mode1
;
10051 bool is_overloaded
= d
->code
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10052 && d
->code
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
;
10061 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
10064 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
10065 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
10068 if (mode0
== V4SImode
&& mode1
== QImode
)
10069 type
= v4si_ftype_int
;
10070 else if (mode0
== V8HImode
&& mode1
== QImode
)
10071 type
= v8hi_ftype_int
;
10072 else if (mode0
== V16QImode
&& mode1
== QImode
)
10073 type
= v16qi_ftype_int
;
10074 else if (mode0
== VOIDmode
&& mode1
== VOIDmode
)
10075 type
= opaque_ftype_opaque
;
10076 else if (mode0
== V4SFmode
&& mode1
== V4SFmode
)
10077 type
= v4sf_ftype_v4sf
;
10078 else if (mode0
== V8HImode
&& mode1
== V16QImode
)
10079 type
= v8hi_ftype_v16qi
;
10080 else if (mode0
== V4SImode
&& mode1
== V8HImode
)
10081 type
= v4si_ftype_v8hi
;
10082 else if (mode0
== V2SImode
&& mode1
== V2SImode
)
10083 type
= v2si_ftype_v2si
;
10084 else if (mode0
== V2SFmode
&& mode1
== V2SFmode
)
10086 if (TARGET_PAIRED_FLOAT
)
10087 type
= v2sf_ftype_v2sf
;
10089 type
= v2sf_ftype_v2sf_spe
;
10091 else if (mode0
== V2SFmode
&& mode1
== V2SImode
)
10092 type
= v2sf_ftype_v2si
;
10093 else if (mode0
== V2SImode
&& mode1
== V2SFmode
)
10094 type
= v2si_ftype_v2sf
;
10095 else if (mode0
== V2SImode
&& mode1
== QImode
)
10096 type
= v2si_ftype_char
;
10098 gcc_unreachable ();
10100 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
10105 rs6000_init_libfuncs (void)
10107 if (DEFAULT_ABI
!= ABI_V4
&& TARGET_XCOFF
10108 && !TARGET_POWER2
&& !TARGET_POWERPC
)
10110 /* AIX library routines for float->int conversion. */
10111 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__itrunc");
10112 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__uitrunc");
10113 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_qitrunc");
10114 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_quitrunc");
10117 if (!TARGET_IEEEQUAD
)
10118 /* AIX/Darwin/64-bit Linux quad floating point routines. */
10119 if (!TARGET_XL_COMPAT
)
10121 set_optab_libfunc (add_optab
, TFmode
, "__gcc_qadd");
10122 set_optab_libfunc (sub_optab
, TFmode
, "__gcc_qsub");
10123 set_optab_libfunc (smul_optab
, TFmode
, "__gcc_qmul");
10124 set_optab_libfunc (sdiv_optab
, TFmode
, "__gcc_qdiv");
10126 if (!(TARGET_HARD_FLOAT
&& (TARGET_FPRS
|| TARGET_E500_DOUBLE
)))
10128 set_optab_libfunc (neg_optab
, TFmode
, "__gcc_qneg");
10129 set_optab_libfunc (eq_optab
, TFmode
, "__gcc_qeq");
10130 set_optab_libfunc (ne_optab
, TFmode
, "__gcc_qne");
10131 set_optab_libfunc (gt_optab
, TFmode
, "__gcc_qgt");
10132 set_optab_libfunc (ge_optab
, TFmode
, "__gcc_qge");
10133 set_optab_libfunc (lt_optab
, TFmode
, "__gcc_qlt");
10134 set_optab_libfunc (le_optab
, TFmode
, "__gcc_qle");
10136 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "__gcc_stoq");
10137 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "__gcc_dtoq");
10138 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "__gcc_qtos");
10139 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "__gcc_qtod");
10140 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "__gcc_qtoi");
10141 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "__gcc_qtou");
10142 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "__gcc_itoq");
10143 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "__gcc_utoq");
10146 if (!(TARGET_HARD_FLOAT
&& TARGET_FPRS
))
10147 set_optab_libfunc (unord_optab
, TFmode
, "__gcc_qunord");
10151 set_optab_libfunc (add_optab
, TFmode
, "_xlqadd");
10152 set_optab_libfunc (sub_optab
, TFmode
, "_xlqsub");
10153 set_optab_libfunc (smul_optab
, TFmode
, "_xlqmul");
10154 set_optab_libfunc (sdiv_optab
, TFmode
, "_xlqdiv");
10158 /* 32-bit SVR4 quad floating point routines. */
10160 set_optab_libfunc (add_optab
, TFmode
, "_q_add");
10161 set_optab_libfunc (sub_optab
, TFmode
, "_q_sub");
10162 set_optab_libfunc (neg_optab
, TFmode
, "_q_neg");
10163 set_optab_libfunc (smul_optab
, TFmode
, "_q_mul");
10164 set_optab_libfunc (sdiv_optab
, TFmode
, "_q_div");
10165 if (TARGET_PPC_GPOPT
|| TARGET_POWER2
)
10166 set_optab_libfunc (sqrt_optab
, TFmode
, "_q_sqrt");
10168 set_optab_libfunc (eq_optab
, TFmode
, "_q_feq");
10169 set_optab_libfunc (ne_optab
, TFmode
, "_q_fne");
10170 set_optab_libfunc (gt_optab
, TFmode
, "_q_fgt");
10171 set_optab_libfunc (ge_optab
, TFmode
, "_q_fge");
10172 set_optab_libfunc (lt_optab
, TFmode
, "_q_flt");
10173 set_optab_libfunc (le_optab
, TFmode
, "_q_fle");
10175 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_q_stoq");
10176 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_q_dtoq");
10177 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_q_qtos");
10178 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_q_qtod");
10179 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_q_qtoi");
10180 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_q_qtou");
10181 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_q_itoq");
10182 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_q_utoq");
10187 /* Expand a block clear operation, and return 1 if successful. Return 0
10188 if we should let the compiler generate normal code.
10190 operands[0] is the destination
10191 operands[1] is the length
10192 operands[3] is the alignment */
10195 expand_block_clear (rtx operands
[])
10197 rtx orig_dest
= operands
[0];
10198 rtx bytes_rtx
= operands
[1];
10199 rtx align_rtx
= operands
[3];
10200 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
10201 HOST_WIDE_INT align
;
10202 HOST_WIDE_INT bytes
;
10207 /* If this is not a fixed size move, just call memcpy */
10211 /* This must be a fixed size alignment */
10212 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
10213 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
10215 /* Anything to clear? */
10216 bytes
= INTVAL (bytes_rtx
);
10220 /* Use the builtin memset after a point, to avoid huge code bloat.
10221 When optimize_size, avoid any significant code bloat; calling
10222 memset is about 4 instructions, so allow for one instruction to
10223 load zero and three to do clearing. */
10224 if (TARGET_ALTIVEC
&& align
>= 128)
10226 else if (TARGET_POWERPC64
&& align
>= 32)
10228 else if (TARGET_SPE
&& align
>= 64)
10233 if (optimize_size
&& bytes
> 3 * clear_step
)
10235 if (! optimize_size
&& bytes
> 8 * clear_step
)
10238 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
10240 enum machine_mode mode
= BLKmode
;
10243 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
10248 else if (bytes
>= 8 && TARGET_SPE
&& align
>= 64)
10253 else if (bytes
>= 8 && TARGET_POWERPC64
10254 /* 64-bit loads and stores require word-aligned
10256 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
10261 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
10262 { /* move 4 bytes */
10266 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
10267 { /* move 2 bytes */
10271 else /* move 1 byte at a time */
10277 dest
= adjust_address (orig_dest
, mode
, offset
);
10279 emit_move_insn (dest
, CONST0_RTX (mode
));
10286 /* Expand a block move operation, and return 1 if successful. Return 0
10287 if we should let the compiler generate normal code.
10289 operands[0] is the destination
10290 operands[1] is the source
10291 operands[2] is the length
10292 operands[3] is the alignment */
10294 #define MAX_MOVE_REG 4
10297 expand_block_move (rtx operands
[])
10299 rtx orig_dest
= operands
[0];
10300 rtx orig_src
= operands
[1];
10301 rtx bytes_rtx
= operands
[2];
10302 rtx align_rtx
= operands
[3];
10303 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
10308 rtx stores
[MAX_MOVE_REG
];
10311 /* If this is not a fixed size move, just call memcpy */
10315 /* This must be a fixed size alignment */
10316 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
10317 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
10319 /* Anything to move? */
10320 bytes
= INTVAL (bytes_rtx
);
10324 /* store_one_arg depends on expand_block_move to handle at least the size of
10325 reg_parm_stack_space. */
10326 if (bytes
> (TARGET_POWERPC64
? 64 : 32))
10329 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
10332 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
10333 rtx (*mov
) (rtx
, rtx
);
10335 enum machine_mode mode
= BLKmode
;
10338 /* Altivec first, since it will be faster than a string move
10339 when it applies, and usually not significantly larger. */
10340 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
10344 gen_func
.mov
= gen_movv4si
;
10346 else if (TARGET_SPE
&& bytes
>= 8 && align
>= 64)
10350 gen_func
.mov
= gen_movv2si
;
10352 else if (TARGET_STRING
10353 && bytes
> 24 /* move up to 32 bytes at a time */
10359 && ! fixed_regs
[10]
10360 && ! fixed_regs
[11]
10361 && ! fixed_regs
[12])
10363 move_bytes
= (bytes
> 32) ? 32 : bytes
;
10364 gen_func
.movmemsi
= gen_movmemsi_8reg
;
10366 else if (TARGET_STRING
10367 && bytes
> 16 /* move up to 24 bytes at a time */
10373 && ! fixed_regs
[10])
10375 move_bytes
= (bytes
> 24) ? 24 : bytes
;
10376 gen_func
.movmemsi
= gen_movmemsi_6reg
;
10378 else if (TARGET_STRING
10379 && bytes
> 8 /* move up to 16 bytes at a time */
10383 && ! fixed_regs
[8])
10385 move_bytes
= (bytes
> 16) ? 16 : bytes
;
10386 gen_func
.movmemsi
= gen_movmemsi_4reg
;
10388 else if (bytes
>= 8 && TARGET_POWERPC64
10389 /* 64-bit loads and stores require word-aligned
10391 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
10395 gen_func
.mov
= gen_movdi
;
10397 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
10398 { /* move up to 8 bytes at a time */
10399 move_bytes
= (bytes
> 8) ? 8 : bytes
;
10400 gen_func
.movmemsi
= gen_movmemsi_2reg
;
10402 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
10403 { /* move 4 bytes */
10406 gen_func
.mov
= gen_movsi
;
10408 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
10409 { /* move 2 bytes */
10412 gen_func
.mov
= gen_movhi
;
10414 else if (TARGET_STRING
&& bytes
> 1)
10415 { /* move up to 4 bytes at a time */
10416 move_bytes
= (bytes
> 4) ? 4 : bytes
;
10417 gen_func
.movmemsi
= gen_movmemsi_1reg
;
10419 else /* move 1 byte at a time */
10423 gen_func
.mov
= gen_movqi
;
10426 src
= adjust_address (orig_src
, mode
, offset
);
10427 dest
= adjust_address (orig_dest
, mode
, offset
);
10429 if (mode
!= BLKmode
)
10431 rtx tmp_reg
= gen_reg_rtx (mode
);
10433 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
10434 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
10437 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
10440 for (i
= 0; i
< num_reg
; i
++)
10441 emit_insn (stores
[i
]);
10445 if (mode
== BLKmode
)
10447 /* Move the address into scratch registers. The movmemsi
10448 patterns require zero offset. */
10449 if (!REG_P (XEXP (src
, 0)))
10451 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
10452 src
= replace_equiv_address (src
, src_reg
);
10454 set_mem_size (src
, GEN_INT (move_bytes
));
10456 if (!REG_P (XEXP (dest
, 0)))
10458 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
10459 dest
= replace_equiv_address (dest
, dest_reg
);
10461 set_mem_size (dest
, GEN_INT (move_bytes
));
10463 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
10464 GEN_INT (move_bytes
& 31),
10473 /* Return a string to perform a load_multiple operation.
10474 operands[0] is the vector.
10475 operands[1] is the source address.
10476 operands[2] is the first destination register. */
10479 rs6000_output_load_multiple (rtx operands
[3])
10481 /* We have to handle the case where the pseudo used to contain the address
10482 is assigned to one of the output registers. */
10484 int words
= XVECLEN (operands
[0], 0);
10487 if (XVECLEN (operands
[0], 0) == 1)
10488 return "{l|lwz} %2,0(%1)";
10490 for (i
= 0; i
< words
; i
++)
10491 if (refers_to_regno_p (REGNO (operands
[2]) + i
,
10492 REGNO (operands
[2]) + i
+ 1, operands
[1], 0))
10496 xop
[0] = GEN_INT (4 * (words
-1));
10497 xop
[1] = operands
[1];
10498 xop
[2] = operands
[2];
10499 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop
);
10504 xop
[0] = GEN_INT (4 * (words
-1));
10505 xop
[1] = operands
[1];
10506 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
10507 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop
);
10512 for (j
= 0; j
< words
; j
++)
10515 xop
[0] = GEN_INT (j
* 4);
10516 xop
[1] = operands
[1];
10517 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
10518 output_asm_insn ("{l|lwz} %2,%0(%1)", xop
);
10520 xop
[0] = GEN_INT (i
* 4);
10521 xop
[1] = operands
[1];
10522 output_asm_insn ("{l|lwz} %1,%0(%1)", xop
);
10527 return "{lsi|lswi} %2,%1,%N0";
10531 /* A validation routine: say whether CODE, a condition code, and MODE
10532 match. The other alternatives either don't make sense or should
10533 never be generated. */
10536 validate_condition_mode (enum rtx_code code
, enum machine_mode mode
)
10538 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
10539 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
10540 && GET_MODE_CLASS (mode
) == MODE_CC
);
10542 /* These don't make sense. */
10543 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
10544 || mode
!= CCUNSmode
);
10546 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
10547 || mode
== CCUNSmode
);
10549 gcc_assert (mode
== CCFPmode
10550 || (code
!= ORDERED
&& code
!= UNORDERED
10551 && code
!= UNEQ
&& code
!= LTGT
10552 && code
!= UNGT
&& code
!= UNLT
10553 && code
!= UNGE
&& code
!= UNLE
));
10555 /* These should never be generated except for
10556 flag_finite_math_only. */
10557 gcc_assert (mode
!= CCFPmode
10558 || flag_finite_math_only
10559 || (code
!= LE
&& code
!= GE
10560 && code
!= UNEQ
&& code
!= LTGT
10561 && code
!= UNGT
&& code
!= UNLT
));
10563 /* These are invalid; the information is not there. */
10564 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
10568 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
10569 mask required to convert the result of a rotate insn into a shift
10570 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
10573 includes_lshift_p (rtx shiftop
, rtx andop
)
10575 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
10577 shift_mask
<<= INTVAL (shiftop
);
10579 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
10582 /* Similar, but for right shift. */
10585 includes_rshift_p (rtx shiftop
, rtx andop
)
10587 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
10589 shift_mask
>>= INTVAL (shiftop
);
10591 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
10594 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
10595 to perform a left shift. It must have exactly SHIFTOP least
10596 significant 0's, then one or more 1's, then zero or more 0's. */
10599 includes_rldic_lshift_p (rtx shiftop
, rtx andop
)
10601 if (GET_CODE (andop
) == CONST_INT
)
10603 HOST_WIDE_INT c
, lsb
, shift_mask
;
10605 c
= INTVAL (andop
);
10606 if (c
== 0 || c
== ~0)
10610 shift_mask
<<= INTVAL (shiftop
);
10612 /* Find the least significant one bit. */
10615 /* It must coincide with the LSB of the shift mask. */
10616 if (-lsb
!= shift_mask
)
10619 /* Invert to look for the next transition (if any). */
10622 /* Remove the low group of ones (originally low group of zeros). */
10625 /* Again find the lsb, and check we have all 1's above. */
10629 else if (GET_CODE (andop
) == CONST_DOUBLE
10630 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
10632 HOST_WIDE_INT low
, high
, lsb
;
10633 HOST_WIDE_INT shift_mask_low
, shift_mask_high
;
10635 low
= CONST_DOUBLE_LOW (andop
);
10636 if (HOST_BITS_PER_WIDE_INT
< 64)
10637 high
= CONST_DOUBLE_HIGH (andop
);
10639 if ((low
== 0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== 0))
10640 || (low
== ~0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0)))
10643 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
10645 shift_mask_high
= ~0;
10646 if (INTVAL (shiftop
) > 32)
10647 shift_mask_high
<<= INTVAL (shiftop
) - 32;
10649 lsb
= high
& -high
;
10651 if (-lsb
!= shift_mask_high
|| INTVAL (shiftop
) < 32)
10657 lsb
= high
& -high
;
10658 return high
== -lsb
;
10661 shift_mask_low
= ~0;
10662 shift_mask_low
<<= INTVAL (shiftop
);
10666 if (-lsb
!= shift_mask_low
)
10669 if (HOST_BITS_PER_WIDE_INT
< 64)
10674 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
10676 lsb
= high
& -high
;
10677 return high
== -lsb
;
10681 return low
== -lsb
&& (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0);
10687 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
10688 to perform a left shift. It must have SHIFTOP or more least
10689 significant 0's, with the remainder of the word 1's. */
10692 includes_rldicr_lshift_p (rtx shiftop
, rtx andop
)
10694 if (GET_CODE (andop
) == CONST_INT
)
10696 HOST_WIDE_INT c
, lsb
, shift_mask
;
10699 shift_mask
<<= INTVAL (shiftop
);
10700 c
= INTVAL (andop
);
10702 /* Find the least significant one bit. */
10705 /* It must be covered by the shift mask.
10706 This test also rejects c == 0. */
10707 if ((lsb
& shift_mask
) == 0)
10710 /* Check we have all 1's above the transition, and reject all 1's. */
10711 return c
== -lsb
&& lsb
!= 1;
10713 else if (GET_CODE (andop
) == CONST_DOUBLE
10714 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
10716 HOST_WIDE_INT low
, lsb
, shift_mask_low
;
10718 low
= CONST_DOUBLE_LOW (andop
);
10720 if (HOST_BITS_PER_WIDE_INT
< 64)
10722 HOST_WIDE_INT high
, shift_mask_high
;
10724 high
= CONST_DOUBLE_HIGH (andop
);
10728 shift_mask_high
= ~0;
10729 if (INTVAL (shiftop
) > 32)
10730 shift_mask_high
<<= INTVAL (shiftop
) - 32;
10732 lsb
= high
& -high
;
10734 if ((lsb
& shift_mask_high
) == 0)
10737 return high
== -lsb
;
10743 shift_mask_low
= ~0;
10744 shift_mask_low
<<= INTVAL (shiftop
);
10748 if ((lsb
& shift_mask_low
) == 0)
10751 return low
== -lsb
&& lsb
!= 1;
10757 /* Return 1 if operands will generate a valid arguments to rlwimi
10758 instruction for insert with right shift in 64-bit mode. The mask may
10759 not start on the first bit or stop on the last bit because wrap-around
10760 effects of instruction do not correspond to semantics of RTL insn. */
10763 insvdi_rshift_rlwimi_p (rtx sizeop
, rtx startop
, rtx shiftop
)
10765 if (INTVAL (startop
) > 32
10766 && INTVAL (startop
) < 64
10767 && INTVAL (sizeop
) > 1
10768 && INTVAL (sizeop
) + INTVAL (startop
) < 64
10769 && INTVAL (shiftop
) > 0
10770 && INTVAL (sizeop
) + INTVAL (shiftop
) < 32
10771 && (64 - (INTVAL (shiftop
) & 63)) >= INTVAL (sizeop
))
10777 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
10778 for lfq and stfq insns iff the registers are hard registers. */
10781 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
10783 /* We might have been passed a SUBREG. */
10784 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
10787 /* We might have been passed non floating point registers. */
10788 if (!FP_REGNO_P (REGNO (reg1
))
10789 || !FP_REGNO_P (REGNO (reg2
)))
10792 return (REGNO (reg1
) == REGNO (reg2
) - 1);
10795 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
10796 addr1 and addr2 must be in consecutive memory locations
10797 (addr2 == addr1 + 8). */
10800 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
10803 unsigned int reg1
, reg2
;
10804 int offset1
, offset2
;
10806 /* The mems cannot be volatile. */
10807 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
10810 addr1
= XEXP (mem1
, 0);
10811 addr2
= XEXP (mem2
, 0);
10813 /* Extract an offset (if used) from the first addr. */
10814 if (GET_CODE (addr1
) == PLUS
)
10816 /* If not a REG, return zero. */
10817 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
10821 reg1
= REGNO (XEXP (addr1
, 0));
10822 /* The offset must be constant! */
10823 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
10825 offset1
= INTVAL (XEXP (addr1
, 1));
10828 else if (GET_CODE (addr1
) != REG
)
10832 reg1
= REGNO (addr1
);
10833 /* This was a simple (mem (reg)) expression. Offset is 0. */
10837 /* And now for the second addr. */
10838 if (GET_CODE (addr2
) == PLUS
)
10840 /* If not a REG, return zero. */
10841 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
10845 reg2
= REGNO (XEXP (addr2
, 0));
10846 /* The offset must be constant. */
10847 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
10849 offset2
= INTVAL (XEXP (addr2
, 1));
10852 else if (GET_CODE (addr2
) != REG
)
10856 reg2
= REGNO (addr2
);
10857 /* This was a simple (mem (reg)) expression. Offset is 0. */
10861 /* Both of these must have the same base register. */
10865 /* The offset for the second addr must be 8 more than the first addr. */
10866 if (offset2
!= offset1
+ 8)
10869 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
10874 /* Return the register class of a scratch register needed to copy IN into
10875 or out of a register in CLASS in MODE. If it can be done directly,
10876 NO_REGS is returned. */
10879 rs6000_secondary_reload_class (enum reg_class
class,
10880 enum machine_mode mode ATTRIBUTE_UNUSED
,
10885 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
10887 && MACHOPIC_INDIRECT
10891 /* We cannot copy a symbolic operand directly into anything
10892 other than BASE_REGS for TARGET_ELF. So indicate that a
10893 register from BASE_REGS is needed as an intermediate
10896 On Darwin, pic addresses require a load from memory, which
10897 needs a base register. */
10898 if (class != BASE_REGS
10899 && (GET_CODE (in
) == SYMBOL_REF
10900 || GET_CODE (in
) == HIGH
10901 || GET_CODE (in
) == LABEL_REF
10902 || GET_CODE (in
) == CONST
))
10906 if (GET_CODE (in
) == REG
)
10908 regno
= REGNO (in
);
10909 if (regno
>= FIRST_PSEUDO_REGISTER
)
10911 regno
= true_regnum (in
);
10912 if (regno
>= FIRST_PSEUDO_REGISTER
)
10916 else if (GET_CODE (in
) == SUBREG
)
10918 regno
= true_regnum (in
);
10919 if (regno
>= FIRST_PSEUDO_REGISTER
)
10925 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
10927 if (class == GENERAL_REGS
|| class == BASE_REGS
10928 || (regno
>= 0 && INT_REGNO_P (regno
)))
10931 /* Constants, memory, and FP registers can go into FP registers. */
10932 if ((regno
== -1 || FP_REGNO_P (regno
))
10933 && (class == FLOAT_REGS
|| class == NON_SPECIAL_REGS
))
10936 /* Memory, and AltiVec registers can go into AltiVec registers. */
10937 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
10938 && class == ALTIVEC_REGS
)
10941 /* We can copy among the CR registers. */
10942 if ((class == CR_REGS
|| class == CR0_REGS
)
10943 && regno
>= 0 && CR_REGNO_P (regno
))
10946 /* Otherwise, we need GENERAL_REGS. */
10947 return GENERAL_REGS
;
10950 /* Given a comparison operation, return the bit number in CCR to test. We
10951 know this is a valid comparison.
10953 SCC_P is 1 if this is for an scc. That means that %D will have been
10954 used instead of %C, so the bits will be in different places.
10956 Return -1 if OP isn't a valid comparison for some reason. */
10959 ccr_bit (rtx op
, int scc_p
)
10961 enum rtx_code code
= GET_CODE (op
);
10962 enum machine_mode cc_mode
;
10967 if (!COMPARISON_P (op
))
10970 reg
= XEXP (op
, 0);
10972 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
10974 cc_mode
= GET_MODE (reg
);
10975 cc_regnum
= REGNO (reg
);
10976 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
10978 validate_condition_mode (code
, cc_mode
);
10980 /* When generating a sCOND operation, only positive conditions are
10983 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
10984 || code
== GTU
|| code
== LTU
);
10989 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
10991 return base_bit
+ 2;
10992 case GT
: case GTU
: case UNLE
:
10993 return base_bit
+ 1;
10994 case LT
: case LTU
: case UNGE
:
10996 case ORDERED
: case UNORDERED
:
10997 return base_bit
+ 3;
11000 /* If scc, we will have done a cror to put the bit in the
11001 unordered position. So test that bit. For integer, this is ! LT
11002 unless this is an scc insn. */
11003 return scc_p
? base_bit
+ 3 : base_bit
;
11006 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
11009 gcc_unreachable ();
11013 /* Return the GOT register. */
11016 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
11018 /* The second flow pass currently (June 1999) can't update
11019 regs_ever_live without disturbing other parts of the compiler, so
11020 update it here to make the prolog/epilogue code happy. */
11021 if (!can_create_pseudo_p ()
11022 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
11023 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
11025 current_function_uses_pic_offset_table
= 1;
11027 return pic_offset_table_rtx
;
11030 /* Function to init struct machine_function.
11031 This will be called, via a pointer variable,
11032 from push_function_context. */
11034 static struct machine_function
*
11035 rs6000_init_machine_status (void)
11037 return ggc_alloc_cleared (sizeof (machine_function
));
11040 /* These macros test for integers and extract the low-order bits. */
11042 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
11043 && GET_MODE (X) == VOIDmode)
11045 #define INT_LOWPART(X) \
11046 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
11049 extract_MB (rtx op
)
11052 unsigned long val
= INT_LOWPART (op
);
11054 /* If the high bit is zero, the value is the first 1 bit we find
11056 if ((val
& 0x80000000) == 0)
11058 gcc_assert (val
& 0xffffffff);
11061 while (((val
<<= 1) & 0x80000000) == 0)
11066 /* If the high bit is set and the low bit is not, or the mask is all
11067 1's, the value is zero. */
11068 if ((val
& 1) == 0 || (val
& 0xffffffff) == 0xffffffff)
11071 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
11074 while (((val
>>= 1) & 1) != 0)
11081 extract_ME (rtx op
)
11084 unsigned long val
= INT_LOWPART (op
);
11086 /* If the low bit is zero, the value is the first 1 bit we find from
11088 if ((val
& 1) == 0)
11090 gcc_assert (val
& 0xffffffff);
11093 while (((val
>>= 1) & 1) == 0)
11099 /* If the low bit is set and the high bit is not, or the mask is all
11100 1's, the value is 31. */
11101 if ((val
& 0x80000000) == 0 || (val
& 0xffffffff) == 0xffffffff)
11104 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
11107 while (((val
<<= 1) & 0x80000000) != 0)
11113 /* Locate some local-dynamic symbol still in use by this function
11114 so that we can print its name in some tls_ld pattern. */
11116 static const char *
11117 rs6000_get_some_local_dynamic_name (void)
11121 if (cfun
->machine
->some_ld_name
)
11122 return cfun
->machine
->some_ld_name
;
11124 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11126 && for_each_rtx (&PATTERN (insn
),
11127 rs6000_get_some_local_dynamic_name_1
, 0))
11128 return cfun
->machine
->some_ld_name
;
11130 gcc_unreachable ();
11133 /* Helper function for rs6000_get_some_local_dynamic_name. */
11136 rs6000_get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
11140 if (GET_CODE (x
) == SYMBOL_REF
)
11142 const char *str
= XSTR (x
, 0);
11143 if (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
11145 cfun
->machine
->some_ld_name
= str
;
11153 /* Write out a function code label. */
11156 rs6000_output_function_entry (FILE *file
, const char *fname
)
11158 if (fname
[0] != '.')
11160 switch (DEFAULT_ABI
)
11163 gcc_unreachable ();
11169 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
11178 RS6000_OUTPUT_BASENAME (file
, fname
);
11180 assemble_name (file
, fname
);
11183 /* Print an operand. Recognize special options, documented below. */
11186 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
11187 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
11189 #define SMALL_DATA_RELOC "sda21"
11190 #define SMALL_DATA_REG 0
11194 print_operand (FILE *file
, rtx x
, int code
)
11198 unsigned HOST_WIDE_INT uval
;
11203 /* Write out an instruction after the call which may be replaced
11204 with glue code by the loader. This depends on the AIX version. */
11205 asm_fprintf (file
, RS6000_CALL_GLUE
);
11208 /* %a is output_address. */
11211 /* If X is a constant integer whose low-order 5 bits are zero,
11212 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
11213 in the AIX assembler where "sri" with a zero shift count
11214 writes a trash instruction. */
11215 if (GET_CODE (x
) == CONST_INT
&& (INTVAL (x
) & 31) == 0)
11222 /* If constant, low-order 16 bits of constant, unsigned.
11223 Otherwise, write normally. */
11225 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 0xffff);
11227 print_operand (file
, x
, 0);
11231 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
11232 for 64-bit mask direction. */
11233 putc (((INT_LOWPART (x
) & 1) == 0 ? 'r' : 'l'), file
);
11236 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
11240 /* X is a CR register. Print the number of the GT bit of the CR. */
11241 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
11242 output_operand_lossage ("invalid %%E value");
11244 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 1);
11248 /* Like 'J' but get to the GT bit only. */
11249 gcc_assert (GET_CODE (x
) == REG
);
11251 /* Bit 1 is GT bit. */
11252 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
11254 /* Add one for shift count in rlinm for scc. */
11255 fprintf (file
, "%d", i
+ 1);
11259 /* X is a CR register. Print the number of the EQ bit of the CR */
11260 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
11261 output_operand_lossage ("invalid %%E value");
11263 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
11267 /* X is a CR register. Print the shift count needed to move it
11268 to the high-order four bits. */
11269 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
11270 output_operand_lossage ("invalid %%f value");
11272 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
11276 /* Similar, but print the count for the rotate in the opposite
11278 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
11279 output_operand_lossage ("invalid %%F value");
11281 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
11285 /* X is a constant integer. If it is negative, print "m",
11286 otherwise print "z". This is to make an aze or ame insn. */
11287 if (GET_CODE (x
) != CONST_INT
)
11288 output_operand_lossage ("invalid %%G value");
11289 else if (INTVAL (x
) >= 0)
11296 /* If constant, output low-order five bits. Otherwise, write
11299 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 31);
11301 print_operand (file
, x
, 0);
11305 /* If constant, output low-order six bits. Otherwise, write
11308 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 63);
11310 print_operand (file
, x
, 0);
11314 /* Print `i' if this is a constant, else nothing. */
11320 /* Write the bit number in CCR for jump. */
11321 i
= ccr_bit (x
, 0);
11323 output_operand_lossage ("invalid %%j code");
11325 fprintf (file
, "%d", i
);
11329 /* Similar, but add one for shift count in rlinm for scc and pass
11330 scc flag to `ccr_bit'. */
11331 i
= ccr_bit (x
, 1);
11333 output_operand_lossage ("invalid %%J code");
11335 /* If we want bit 31, write a shift count of zero, not 32. */
11336 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
11340 /* X must be a constant. Write the 1's complement of the
11343 output_operand_lossage ("invalid %%k value");
11345 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INT_LOWPART (x
));
11349 /* X must be a symbolic constant on ELF. Write an
11350 expression suitable for an 'addi' that adds in the low 16
11351 bits of the MEM. */
11352 if (GET_CODE (x
) != CONST
)
11354 print_operand_address (file
, x
);
11355 fputs ("@l", file
);
11359 if (GET_CODE (XEXP (x
, 0)) != PLUS
11360 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
11361 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
11362 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
11363 output_operand_lossage ("invalid %%K value");
11364 print_operand_address (file
, XEXP (XEXP (x
, 0), 0));
11365 fputs ("@l", file
);
11366 /* For GNU as, there must be a non-alphanumeric character
11367 between 'l' and the number. The '-' is added by
11368 print_operand() already. */
11369 if (INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0)
11371 print_operand (file
, XEXP (XEXP (x
, 0), 1), 0);
11375 /* %l is output_asm_label. */
11378 /* Write second word of DImode or DFmode reference. Works on register
11379 or non-indexed memory only. */
11380 if (GET_CODE (x
) == REG
)
11381 fputs (reg_names
[REGNO (x
) + 1], file
);
11382 else if (GET_CODE (x
) == MEM
)
11384 /* Handle possible auto-increment. Since it is pre-increment and
11385 we have already done it, we can just use an offset of word. */
11386 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
11387 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
11388 output_address (plus_constant (XEXP (XEXP (x
, 0), 0),
11390 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
11391 output_address (plus_constant (XEXP (XEXP (x
, 0), 0),
11394 output_address (XEXP (adjust_address_nv (x
, SImode
,
11398 if (small_data_operand (x
, GET_MODE (x
)))
11399 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
11400 reg_names
[SMALL_DATA_REG
]);
11405 /* MB value for a mask operand. */
11406 if (! mask_operand (x
, SImode
))
11407 output_operand_lossage ("invalid %%m value");
11409 fprintf (file
, "%d", extract_MB (x
));
11413 /* ME value for a mask operand. */
11414 if (! mask_operand (x
, SImode
))
11415 output_operand_lossage ("invalid %%M value");
11417 fprintf (file
, "%d", extract_ME (x
));
11420 /* %n outputs the negative of its operand. */
11423 /* Write the number of elements in the vector times 4. */
11424 if (GET_CODE (x
) != PARALLEL
)
11425 output_operand_lossage ("invalid %%N value");
11427 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
11431 /* Similar, but subtract 1 first. */
11432 if (GET_CODE (x
) != PARALLEL
)
11433 output_operand_lossage ("invalid %%O value");
11435 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
11439 /* X is a CONST_INT that is a power of two. Output the logarithm. */
11441 || INT_LOWPART (x
) < 0
11442 || (i
= exact_log2 (INT_LOWPART (x
))) < 0)
11443 output_operand_lossage ("invalid %%p value");
11445 fprintf (file
, "%d", i
);
11449 /* The operand must be an indirect memory reference. The result
11450 is the register name. */
11451 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
11452 || REGNO (XEXP (x
, 0)) >= 32)
11453 output_operand_lossage ("invalid %%P value");
11455 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
11459 /* This outputs the logical code corresponding to a boolean
11460 expression. The expression may have one or both operands
11461 negated (if one, only the first one). For condition register
11462 logical operations, it will also treat the negated
11463 CR codes as NOTs, but not handle NOTs of them. */
11465 const char *const *t
= 0;
11467 enum rtx_code code
= GET_CODE (x
);
11468 static const char * const tbl
[3][3] = {
11469 { "and", "andc", "nor" },
11470 { "or", "orc", "nand" },
11471 { "xor", "eqv", "xor" } };
11475 else if (code
== IOR
)
11477 else if (code
== XOR
)
11480 output_operand_lossage ("invalid %%q value");
11482 if (GET_CODE (XEXP (x
, 0)) != NOT
)
11486 if (GET_CODE (XEXP (x
, 1)) == NOT
)
11504 /* X is a CR register. Print the mask for `mtcrf'. */
11505 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
11506 output_operand_lossage ("invalid %%R value");
11508 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
11512 /* Low 5 bits of 32 - value */
11514 output_operand_lossage ("invalid %%s value");
11516 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INT_LOWPART (x
)) & 31);
11520 /* PowerPC64 mask position. All 0's is excluded.
11521 CONST_INT 32-bit mask is considered sign-extended so any
11522 transition must occur within the CONST_INT, not on the boundary. */
11523 if (! mask64_operand (x
, DImode
))
11524 output_operand_lossage ("invalid %%S value");
11526 uval
= INT_LOWPART (x
);
11528 if (uval
& 1) /* Clear Left */
11530 #if HOST_BITS_PER_WIDE_INT > 64
11531 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
11535 else /* Clear Right */
11538 #if HOST_BITS_PER_WIDE_INT > 64
11539 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
11545 gcc_assert (i
>= 0);
11546 fprintf (file
, "%d", i
);
11550 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
11551 gcc_assert (GET_CODE (x
) == REG
&& GET_MODE (x
) == CCmode
);
11553 /* Bit 3 is OV bit. */
11554 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
11556 /* If we want bit 31, write a shift count of zero, not 32. */
11557 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
11561 /* Print the symbolic name of a branch target register. */
11562 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LR_REGNO
11563 && REGNO (x
) != CTR_REGNO
))
11564 output_operand_lossage ("invalid %%T value");
11565 else if (REGNO (x
) == LR_REGNO
)
11566 fputs (TARGET_NEW_MNEMONICS
? "lr" : "r", file
);
11568 fputs ("ctr", file
);
11572 /* High-order 16 bits of constant for use in unsigned operand. */
11574 output_operand_lossage ("invalid %%u value");
11576 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
11577 (INT_LOWPART (x
) >> 16) & 0xffff);
11581 /* High-order 16 bits of constant for use in signed operand. */
11583 output_operand_lossage ("invalid %%v value");
11585 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
11586 (INT_LOWPART (x
) >> 16) & 0xffff);
11590 /* Print `u' if this has an auto-increment or auto-decrement. */
11591 if (GET_CODE (x
) == MEM
11592 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
11593 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
11594 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
11599 /* Print the trap code for this operand. */
11600 switch (GET_CODE (x
))
11603 fputs ("eq", file
); /* 4 */
11606 fputs ("ne", file
); /* 24 */
11609 fputs ("lt", file
); /* 16 */
11612 fputs ("le", file
); /* 20 */
11615 fputs ("gt", file
); /* 8 */
11618 fputs ("ge", file
); /* 12 */
11621 fputs ("llt", file
); /* 2 */
11624 fputs ("lle", file
); /* 6 */
11627 fputs ("lgt", file
); /* 1 */
11630 fputs ("lge", file
); /* 5 */
11633 gcc_unreachable ();
11638 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
11641 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
11642 ((INT_LOWPART (x
) & 0xffff) ^ 0x8000) - 0x8000);
11644 print_operand (file
, x
, 0);
11648 /* MB value for a PowerPC64 rldic operand. */
11649 val
= (GET_CODE (x
) == CONST_INT
11650 ? INTVAL (x
) : CONST_DOUBLE_HIGH (x
));
11655 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
; i
++)
11656 if ((val
<<= 1) < 0)
11659 #if HOST_BITS_PER_WIDE_INT == 32
11660 if (GET_CODE (x
) == CONST_INT
&& i
>= 0)
11661 i
+= 32; /* zero-extend high-part was all 0's */
11662 else if (GET_CODE (x
) == CONST_DOUBLE
&& i
== 32)
11664 val
= CONST_DOUBLE_LOW (x
);
11670 for ( ; i
< 64; i
++)
11671 if ((val
<<= 1) < 0)
11676 fprintf (file
, "%d", i
+ 1);
11680 if (GET_CODE (x
) == MEM
11681 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
11682 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
11683 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
11688 /* Like 'L', for third word of TImode */
11689 if (GET_CODE (x
) == REG
)
11690 fputs (reg_names
[REGNO (x
) + 2], file
);
11691 else if (GET_CODE (x
) == MEM
)
11693 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
11694 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
11695 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 8));
11696 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
11697 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 8));
11699 output_address (XEXP (adjust_address_nv (x
, SImode
, 8), 0));
11700 if (small_data_operand (x
, GET_MODE (x
)))
11701 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
11702 reg_names
[SMALL_DATA_REG
]);
11707 /* X is a SYMBOL_REF. Write out the name preceded by a
11708 period and without any trailing data in brackets. Used for function
11709 names. If we are configured for System V (or the embedded ABI) on
11710 the PowerPC, do not emit the period, since those systems do not use
11711 TOCs and the like. */
11712 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
11714 /* Mark the decl as referenced so that cgraph will output the
11716 if (SYMBOL_REF_DECL (x
))
11717 mark_decl_referenced (SYMBOL_REF_DECL (x
));
11719 /* For macho, check to see if we need a stub. */
11722 const char *name
= XSTR (x
, 0);
11724 if (MACHOPIC_INDIRECT
11725 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
11726 name
= machopic_indirection_name (x
, /*stub_p=*/true);
11728 assemble_name (file
, name
);
11730 else if (!DOT_SYMBOLS
)
11731 assemble_name (file
, XSTR (x
, 0));
11733 rs6000_output_function_entry (file
, XSTR (x
, 0));
11737 /* Like 'L', for last word of TImode. */
11738 if (GET_CODE (x
) == REG
)
11739 fputs (reg_names
[REGNO (x
) + 3], file
);
11740 else if (GET_CODE (x
) == MEM
)
11742 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
11743 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
11744 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 12));
11745 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
11746 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 12));
11748 output_address (XEXP (adjust_address_nv (x
, SImode
, 12), 0));
11749 if (small_data_operand (x
, GET_MODE (x
)))
11750 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
11751 reg_names
[SMALL_DATA_REG
]);
11755 /* Print AltiVec or SPE memory operand. */
11760 gcc_assert (GET_CODE (x
) == MEM
);
11764 /* Ugly hack because %y is overloaded. */
11765 if ((TARGET_SPE
|| TARGET_E500_DOUBLE
)
11766 && (GET_MODE_SIZE (GET_MODE (x
)) == 8
11767 || GET_MODE (x
) == TFmode
11768 || GET_MODE (x
) == TImode
))
11770 /* Handle [reg]. */
11771 if (GET_CODE (tmp
) == REG
)
11773 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
11776 /* Handle [reg+UIMM]. */
11777 else if (GET_CODE (tmp
) == PLUS
&&
11778 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
11782 gcc_assert (GET_CODE (XEXP (tmp
, 0)) == REG
);
11784 x
= INTVAL (XEXP (tmp
, 1));
11785 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
11789 /* Fall through. Must be [reg+reg]. */
11792 && GET_CODE (tmp
) == AND
11793 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
11794 && INTVAL (XEXP (tmp
, 1)) == -16)
11795 tmp
= XEXP (tmp
, 0);
11796 if (GET_CODE (tmp
) == REG
)
11797 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
11800 gcc_assert (GET_CODE (tmp
) == PLUS
11801 && REG_P (XEXP (tmp
, 0))
11802 && REG_P (XEXP (tmp
, 1)));
11804 if (REGNO (XEXP (tmp
, 0)) == 0)
11805 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
11806 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
11808 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
11809 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
11815 if (GET_CODE (x
) == REG
)
11816 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
11817 else if (GET_CODE (x
) == MEM
)
11819 /* We need to handle PRE_INC and PRE_DEC here, since we need to
11820 know the width from the mode. */
11821 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
11822 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
11823 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
11824 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
11825 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
11826 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
11827 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
11828 output_address (XEXP (XEXP (x
, 0), 1));
11830 output_address (XEXP (x
, 0));
11833 output_addr_const (file
, x
);
11837 assemble_name (file
, rs6000_get_some_local_dynamic_name ());
11841 output_operand_lossage ("invalid %%xn code");
11845 /* Print the address of an operand. */
11848 print_operand_address (FILE *file
, rtx x
)
11850 if (GET_CODE (x
) == REG
)
11851 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
11852 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
11853 || GET_CODE (x
) == LABEL_REF
)
11855 output_addr_const (file
, x
);
11856 if (small_data_operand (x
, GET_MODE (x
)))
11857 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
11858 reg_names
[SMALL_DATA_REG
]);
11860 gcc_assert (!TARGET_TOC
);
11862 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == REG
)
11864 gcc_assert (REG_P (XEXP (x
, 0)));
11865 if (REGNO (XEXP (x
, 0)) == 0)
11866 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
11867 reg_names
[ REGNO (XEXP (x
, 0)) ]);
11869 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
11870 reg_names
[ REGNO (XEXP (x
, 1)) ]);
11872 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
11873 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
11874 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
11876 else if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == REG
11877 && CONSTANT_P (XEXP (x
, 1)))
11879 output_addr_const (file
, XEXP (x
, 1));
11880 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
11884 else if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == REG
11885 && CONSTANT_P (XEXP (x
, 1)))
11887 fprintf (file
, "lo16(");
11888 output_addr_const (file
, XEXP (x
, 1));
11889 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
11892 else if (legitimate_constant_pool_address_p (x
))
11894 if (TARGET_AIX
&& (!TARGET_ELF
|| !TARGET_MINIMAL_TOC
))
11896 rtx contains_minus
= XEXP (x
, 1);
11900 /* Find the (minus (sym) (toc)) buried in X, and temporarily
11901 turn it into (sym) for output_addr_const. */
11902 while (GET_CODE (XEXP (contains_minus
, 0)) != MINUS
)
11903 contains_minus
= XEXP (contains_minus
, 0);
11905 minus
= XEXP (contains_minus
, 0);
11906 symref
= XEXP (minus
, 0);
11907 XEXP (contains_minus
, 0) = symref
;
11912 name
= XSTR (symref
, 0);
11913 newname
= alloca (strlen (name
) + sizeof ("@toc"));
11914 strcpy (newname
, name
);
11915 strcat (newname
, "@toc");
11916 XSTR (symref
, 0) = newname
;
11918 output_addr_const (file
, XEXP (x
, 1));
11920 XSTR (symref
, 0) = name
;
11921 XEXP (contains_minus
, 0) = minus
;
11924 output_addr_const (file
, XEXP (x
, 1));
11926 fprintf (file
, "(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
11929 gcc_unreachable ();
11932 /* Target hook for assembling integer objects. The PowerPC version has
11933 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
11934 is defined. It also needs to handle DI-mode objects on 64-bit
11938 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
11940 #ifdef RELOCATABLE_NEEDS_FIXUP
11941 /* Special handling for SI values. */
11942 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
11944 static int recurse
= 0;
11946 /* For -mrelocatable, we mark all addresses that need to be fixed up
11947 in the .fixup section. */
11948 if (TARGET_RELOCATABLE
11949 && in_section
!= toc_section
11950 && in_section
!= text_section
11951 && !unlikely_text_section_p (in_section
)
11953 && GET_CODE (x
) != CONST_INT
11954 && GET_CODE (x
) != CONST_DOUBLE
11960 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
11962 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
11963 fprintf (asm_out_file
, "\t.long\t(");
11964 output_addr_const (asm_out_file
, x
);
11965 fprintf (asm_out_file
, ")@fixup\n");
11966 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
11967 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
11968 fprintf (asm_out_file
, "\t.long\t");
11969 assemble_name (asm_out_file
, buf
);
11970 fprintf (asm_out_file
, "\n\t.previous\n");
11974 /* Remove initial .'s to turn a -mcall-aixdesc function
11975 address into the address of the descriptor, not the function
11977 else if (GET_CODE (x
) == SYMBOL_REF
11978 && XSTR (x
, 0)[0] == '.'
11979 && DEFAULT_ABI
== ABI_AIX
)
11981 const char *name
= XSTR (x
, 0);
11982 while (*name
== '.')
11985 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
11989 #endif /* RELOCATABLE_NEEDS_FIXUP */
11990 return default_assemble_integer (x
, size
, aligned_p
);
11993 #ifdef HAVE_GAS_HIDDEN
11994 /* Emit an assembler directive to set symbol visibility for DECL to
11995 VISIBILITY_TYPE. */
11998 rs6000_assemble_visibility (tree decl
, int vis
)
12000 /* Functions need to have their entry point symbol visibility set as
12001 well as their descriptor symbol visibility. */
12002 if (DEFAULT_ABI
== ABI_AIX
12004 && TREE_CODE (decl
) == FUNCTION_DECL
)
12006 static const char * const visibility_types
[] = {
12007 NULL
, "internal", "hidden", "protected"
12010 const char *name
, *type
;
12012 name
= ((* targetm
.strip_name_encoding
)
12013 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
12014 type
= visibility_types
[vis
];
12016 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
12017 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
12020 default_assemble_visibility (decl
, vis
);
12025 rs6000_reverse_condition (enum machine_mode mode
, enum rtx_code code
)
12027 /* Reversal of FP compares takes care -- an ordered compare
12028 becomes an unordered compare and vice versa. */
12029 if (mode
== CCFPmode
12030 && (!flag_finite_math_only
12031 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
12032 || code
== UNEQ
|| code
== LTGT
))
12033 return reverse_condition_maybe_unordered (code
);
12035 return reverse_condition (code
);
12038 /* Generate a compare for CODE. Return a brand-new rtx that
12039 represents the result of the compare. */
12042 rs6000_generate_compare (enum rtx_code code
)
12044 enum machine_mode comp_mode
;
12045 rtx compare_result
;
12047 if (rs6000_compare_fp_p
)
12048 comp_mode
= CCFPmode
;
12049 else if (code
== GTU
|| code
== LTU
12050 || code
== GEU
|| code
== LEU
)
12051 comp_mode
= CCUNSmode
;
12052 else if ((code
== EQ
|| code
== NE
)
12053 && GET_CODE (rs6000_compare_op0
) == SUBREG
12054 && GET_CODE (rs6000_compare_op1
) == SUBREG
12055 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0
)
12056 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1
))
12057 /* These are unsigned values, perhaps there will be a later
12058 ordering compare that can be shared with this one.
12059 Unfortunately we cannot detect the signedness of the operands
12060 for non-subregs. */
12061 comp_mode
= CCUNSmode
;
12063 comp_mode
= CCmode
;
12065 /* First, the compare. */
12066 compare_result
= gen_reg_rtx (comp_mode
);
12068 /* E500 FP compare instructions on the GPRs. Yuck! */
12069 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
)
12070 && rs6000_compare_fp_p
)
12072 rtx cmp
, or_result
, compare_result2
;
12073 enum machine_mode op_mode
= GET_MODE (rs6000_compare_op0
);
12075 if (op_mode
== VOIDmode
)
12076 op_mode
= GET_MODE (rs6000_compare_op1
);
12078 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
12079 This explains the following mess. */
12083 case EQ
: case UNEQ
: case NE
: case LTGT
:
12087 cmp
= flag_unsafe_math_optimizations
12088 ? gen_tstsfeq_gpr (compare_result
, rs6000_compare_op0
,
12089 rs6000_compare_op1
)
12090 : gen_cmpsfeq_gpr (compare_result
, rs6000_compare_op0
,
12091 rs6000_compare_op1
);
12095 cmp
= flag_unsafe_math_optimizations
12096 ? gen_tstdfeq_gpr (compare_result
, rs6000_compare_op0
,
12097 rs6000_compare_op1
)
12098 : gen_cmpdfeq_gpr (compare_result
, rs6000_compare_op0
,
12099 rs6000_compare_op1
);
12103 cmp
= flag_unsafe_math_optimizations
12104 ? gen_tsttfeq_gpr (compare_result
, rs6000_compare_op0
,
12105 rs6000_compare_op1
)
12106 : gen_cmptfeq_gpr (compare_result
, rs6000_compare_op0
,
12107 rs6000_compare_op1
);
12111 gcc_unreachable ();
12115 case GT
: case GTU
: case UNGT
: case UNGE
: case GE
: case GEU
:
12119 cmp
= flag_unsafe_math_optimizations
12120 ? gen_tstsfgt_gpr (compare_result
, rs6000_compare_op0
,
12121 rs6000_compare_op1
)
12122 : gen_cmpsfgt_gpr (compare_result
, rs6000_compare_op0
,
12123 rs6000_compare_op1
);
12127 cmp
= flag_unsafe_math_optimizations
12128 ? gen_tstdfgt_gpr (compare_result
, rs6000_compare_op0
,
12129 rs6000_compare_op1
)
12130 : gen_cmpdfgt_gpr (compare_result
, rs6000_compare_op0
,
12131 rs6000_compare_op1
);
12135 cmp
= flag_unsafe_math_optimizations
12136 ? gen_tsttfgt_gpr (compare_result
, rs6000_compare_op0
,
12137 rs6000_compare_op1
)
12138 : gen_cmptfgt_gpr (compare_result
, rs6000_compare_op0
,
12139 rs6000_compare_op1
);
12143 gcc_unreachable ();
12147 case LT
: case LTU
: case UNLT
: case UNLE
: case LE
: case LEU
:
12151 cmp
= flag_unsafe_math_optimizations
12152 ? gen_tstsflt_gpr (compare_result
, rs6000_compare_op0
,
12153 rs6000_compare_op1
)
12154 : gen_cmpsflt_gpr (compare_result
, rs6000_compare_op0
,
12155 rs6000_compare_op1
);
12159 cmp
= flag_unsafe_math_optimizations
12160 ? gen_tstdflt_gpr (compare_result
, rs6000_compare_op0
,
12161 rs6000_compare_op1
)
12162 : gen_cmpdflt_gpr (compare_result
, rs6000_compare_op0
,
12163 rs6000_compare_op1
);
12167 cmp
= flag_unsafe_math_optimizations
12168 ? gen_tsttflt_gpr (compare_result
, rs6000_compare_op0
,
12169 rs6000_compare_op1
)
12170 : gen_cmptflt_gpr (compare_result
, rs6000_compare_op0
,
12171 rs6000_compare_op1
);
12175 gcc_unreachable ();
12179 gcc_unreachable ();
12182 /* Synthesize LE and GE from LT/GT || EQ. */
12183 if (code
== LE
|| code
== GE
|| code
== LEU
|| code
== GEU
)
12189 case LE
: code
= LT
; break;
12190 case GE
: code
= GT
; break;
12191 case LEU
: code
= LT
; break;
12192 case GEU
: code
= GT
; break;
12193 default: gcc_unreachable ();
12196 compare_result2
= gen_reg_rtx (CCFPmode
);
12202 cmp
= flag_unsafe_math_optimizations
12203 ? gen_tstsfeq_gpr (compare_result2
, rs6000_compare_op0
,
12204 rs6000_compare_op1
)
12205 : gen_cmpsfeq_gpr (compare_result2
, rs6000_compare_op0
,
12206 rs6000_compare_op1
);
12210 cmp
= flag_unsafe_math_optimizations
12211 ? gen_tstdfeq_gpr (compare_result2
, rs6000_compare_op0
,
12212 rs6000_compare_op1
)
12213 : gen_cmpdfeq_gpr (compare_result2
, rs6000_compare_op0
,
12214 rs6000_compare_op1
);
12218 cmp
= flag_unsafe_math_optimizations
12219 ? gen_tsttfeq_gpr (compare_result2
, rs6000_compare_op0
,
12220 rs6000_compare_op1
)
12221 : gen_cmptfeq_gpr (compare_result2
, rs6000_compare_op0
,
12222 rs6000_compare_op1
);
12226 gcc_unreachable ();
12230 /* OR them together. */
12231 or_result
= gen_reg_rtx (CCFPmode
);
12232 cmp
= gen_e500_cr_ior_compare (or_result
, compare_result
,
12234 compare_result
= or_result
;
12239 if (code
== NE
|| code
== LTGT
)
12249 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
12250 CLOBBERs to match cmptf_internal2 pattern. */
12251 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
12252 && GET_MODE (rs6000_compare_op0
) == TFmode
12253 && !TARGET_IEEEQUAD
12254 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
)
12255 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
12257 gen_rtx_SET (VOIDmode
,
12259 gen_rtx_COMPARE (comp_mode
,
12260 rs6000_compare_op0
,
12261 rs6000_compare_op1
)),
12262 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12263 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12264 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12265 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12266 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12267 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12268 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12269 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)))));
12270 else if (GET_CODE (rs6000_compare_op1
) == UNSPEC
12271 && XINT (rs6000_compare_op1
, 1) == UNSPEC_SP_TEST
)
12273 rtx op1
= XVECEXP (rs6000_compare_op1
, 0, 0);
12274 comp_mode
= CCEQmode
;
12275 compare_result
= gen_reg_rtx (CCEQmode
);
12277 emit_insn (gen_stack_protect_testdi (compare_result
,
12278 rs6000_compare_op0
, op1
));
12280 emit_insn (gen_stack_protect_testsi (compare_result
,
12281 rs6000_compare_op0
, op1
));
12284 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
12285 gen_rtx_COMPARE (comp_mode
,
12286 rs6000_compare_op0
,
12287 rs6000_compare_op1
)));
12290 /* Some kinds of FP comparisons need an OR operation;
12291 under flag_finite_math_only we don't bother. */
12292 if (rs6000_compare_fp_p
12293 && !flag_finite_math_only
12294 && !(TARGET_HARD_FLOAT
&& !TARGET_FPRS
)
12295 && (code
== LE
|| code
== GE
12296 || code
== UNEQ
|| code
== LTGT
12297 || code
== UNGT
|| code
== UNLT
))
12299 enum rtx_code or1
, or2
;
12300 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
12301 rtx or_result
= gen_reg_rtx (CCEQmode
);
12305 case LE
: or1
= LT
; or2
= EQ
; break;
12306 case GE
: or1
= GT
; or2
= EQ
; break;
12307 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
12308 case LTGT
: or1
= LT
; or2
= GT
; break;
12309 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
12310 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
12311 default: gcc_unreachable ();
12313 validate_condition_mode (or1
, comp_mode
);
12314 validate_condition_mode (or2
, comp_mode
);
12315 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
12316 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
12317 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
12318 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
12320 emit_insn (gen_rtx_SET (VOIDmode
, or_result
, compare2_rtx
));
12322 compare_result
= or_result
;
12326 validate_condition_mode (code
, GET_MODE (compare_result
));
12328 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
12332 /* Emit the RTL for an sCOND pattern. */
12335 rs6000_emit_sCOND (enum rtx_code code
, rtx result
)
12338 enum machine_mode op_mode
;
12339 enum rtx_code cond_code
;
12341 condition_rtx
= rs6000_generate_compare (code
);
12342 cond_code
= GET_CODE (condition_rtx
);
12344 if (rs6000_compare_fp_p
12345 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
12349 PUT_MODE (condition_rtx
, SImode
);
12350 t
= XEXP (condition_rtx
, 0);
12352 gcc_assert (cond_code
== NE
|| cond_code
== EQ
);
12354 if (cond_code
== NE
)
12355 emit_insn (gen_e500_flip_gt_bit (t
, t
));
12357 emit_insn (gen_move_from_CR_gt_bit (result
, t
));
12361 if (cond_code
== NE
12362 || cond_code
== GE
|| cond_code
== LE
12363 || cond_code
== GEU
|| cond_code
== LEU
12364 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
12366 rtx not_result
= gen_reg_rtx (CCEQmode
);
12367 rtx not_op
, rev_cond_rtx
;
12368 enum machine_mode cc_mode
;
12370 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
12372 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
12373 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
12374 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
12375 emit_insn (gen_rtx_SET (VOIDmode
, not_result
, not_op
));
12376 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
12379 op_mode
= GET_MODE (rs6000_compare_op0
);
12380 if (op_mode
== VOIDmode
)
12381 op_mode
= GET_MODE (rs6000_compare_op1
);
12383 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| rs6000_compare_fp_p
))
12385 PUT_MODE (condition_rtx
, DImode
);
12386 convert_move (result
, condition_rtx
, 0);
12390 PUT_MODE (condition_rtx
, SImode
);
12391 emit_insn (gen_rtx_SET (VOIDmode
, result
, condition_rtx
));
12395 /* Emit a branch of kind CODE to location LOC. */
12398 rs6000_emit_cbranch (enum rtx_code code
, rtx loc
)
12400 rtx condition_rtx
, loc_ref
;
12402 condition_rtx
= rs6000_generate_compare (code
);
12403 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, loc
);
12404 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
12405 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
12406 loc_ref
, pc_rtx
)));
12409 /* Return the string to output a conditional branch to LABEL, which is
12410 the operand number of the label, or -1 if the branch is really a
12411 conditional return.
12413 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
12414 condition code register and its mode specifies what kind of
12415 comparison we made.
12417 REVERSED is nonzero if we should reverse the sense of the comparison.
12419 INSN is the insn. */
12422 output_cbranch (rtx op
, const char *label
, int reversed
, rtx insn
)
12424 static char string
[64];
12425 enum rtx_code code
= GET_CODE (op
);
12426 rtx cc_reg
= XEXP (op
, 0);
12427 enum machine_mode mode
= GET_MODE (cc_reg
);
12428 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
12429 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
12430 int really_reversed
= reversed
^ need_longbranch
;
12436 validate_condition_mode (code
, mode
);
12438 /* Work out which way this really branches. We could use
12439 reverse_condition_maybe_unordered here always but this
12440 makes the resulting assembler clearer. */
12441 if (really_reversed
)
12443 /* Reversal of FP compares takes care -- an ordered compare
12444 becomes an unordered compare and vice versa. */
12445 if (mode
== CCFPmode
)
12446 code
= reverse_condition_maybe_unordered (code
);
12448 code
= reverse_condition (code
);
12451 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
12453 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
12458 /* Opposite of GT. */
12467 gcc_unreachable ();
12473 /* Not all of these are actually distinct opcodes, but
12474 we distinguish them for clarity of the resulting assembler. */
12475 case NE
: case LTGT
:
12476 ccode
= "ne"; break;
12477 case EQ
: case UNEQ
:
12478 ccode
= "eq"; break;
12480 ccode
= "ge"; break;
12481 case GT
: case GTU
: case UNGT
:
12482 ccode
= "gt"; break;
12484 ccode
= "le"; break;
12485 case LT
: case LTU
: case UNLT
:
12486 ccode
= "lt"; break;
12487 case UNORDERED
: ccode
= "un"; break;
12488 case ORDERED
: ccode
= "nu"; break;
12489 case UNGE
: ccode
= "nl"; break;
12490 case UNLE
: ccode
= "ng"; break;
12492 gcc_unreachable ();
12495 /* Maybe we have a guess as to how likely the branch is.
12496 The old mnemonics don't have a way to specify this information. */
12498 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
12499 if (note
!= NULL_RTX
)
12501 /* PROB is the difference from 50%. */
12502 int prob
= INTVAL (XEXP (note
, 0)) - REG_BR_PROB_BASE
/ 2;
12504 /* Only hint for highly probable/improbable branches on newer
12505 cpus as static prediction overrides processor dynamic
12506 prediction. For older cpus we may as well always hint, but
12507 assume not taken for branches that are very close to 50% as a
12508 mispredicted taken branch is more expensive than a
12509 mispredicted not-taken branch. */
12510 if (rs6000_always_hint
12511 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
12512 && br_prob_note_reliable_p (note
)))
12514 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
12515 && ((prob
> 0) ^ need_longbranch
))
12523 s
+= sprintf (s
, "{b%sr|b%slr%s} ", ccode
, ccode
, pred
);
12525 s
+= sprintf (s
, "{b%s|b%s%s} ", ccode
, ccode
, pred
);
12527 /* We need to escape any '%' characters in the reg_names string.
12528 Assume they'd only be the first character.... */
12529 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
12531 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
12535 /* If the branch distance was too far, we may have to use an
12536 unconditional branch to go the distance. */
12537 if (need_longbranch
)
12538 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
12540 s
+= sprintf (s
, ",%s", label
);
12546 /* Return the string to flip the GT bit on a CR. */
12548 output_e500_flip_gt_bit (rtx dst
, rtx src
)
12550 static char string
[64];
12553 gcc_assert (GET_CODE (dst
) == REG
&& CR_REGNO_P (REGNO (dst
))
12554 && GET_CODE (src
) == REG
&& CR_REGNO_P (REGNO (src
)));
12557 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 1;
12558 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 1;
12560 sprintf (string
, "crnot %d,%d", a
, b
);
12564 /* Return insn index for the vector compare instruction for given CODE,
12565 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
12569 get_vec_cmp_insn (enum rtx_code code
,
12570 enum machine_mode dest_mode
,
12571 enum machine_mode op_mode
)
12573 if (!TARGET_ALTIVEC
)
12574 return INSN_NOT_AVAILABLE
;
12579 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
12580 return UNSPEC_VCMPEQUB
;
12581 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
12582 return UNSPEC_VCMPEQUH
;
12583 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
12584 return UNSPEC_VCMPEQUW
;
12585 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
12586 return UNSPEC_VCMPEQFP
;
12589 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
12590 return UNSPEC_VCMPGEFP
;
12592 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
12593 return UNSPEC_VCMPGTSB
;
12594 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
12595 return UNSPEC_VCMPGTSH
;
12596 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
12597 return UNSPEC_VCMPGTSW
;
12598 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
12599 return UNSPEC_VCMPGTFP
;
12602 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
12603 return UNSPEC_VCMPGTUB
;
12604 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
12605 return UNSPEC_VCMPGTUH
;
12606 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
12607 return UNSPEC_VCMPGTUW
;
12612 return INSN_NOT_AVAILABLE
;
12615 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
12616 DMODE is expected destination mode. This is a recursive function. */
12619 rs6000_emit_vector_compare (enum rtx_code rcode
,
12621 enum machine_mode dmode
)
12625 enum machine_mode dest_mode
;
12626 enum machine_mode op_mode
= GET_MODE (op1
);
12628 gcc_assert (TARGET_ALTIVEC
);
12629 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
12631 /* Floating point vector compare instructions uses destination V4SImode.
12632 Move destination to appropriate mode later. */
12633 if (dmode
== V4SFmode
)
12634 dest_mode
= V4SImode
;
12638 mask
= gen_reg_rtx (dest_mode
);
12639 vec_cmp_insn
= get_vec_cmp_insn (rcode
, dest_mode
, op_mode
);
12641 if (vec_cmp_insn
== INSN_NOT_AVAILABLE
)
12643 bool swap_operands
= false;
12644 bool try_again
= false;
12649 swap_operands
= true;
12654 swap_operands
= true;
12662 /* Invert condition and try again.
12663 e.g., A != B becomes ~(A==B). */
12665 enum rtx_code rev_code
;
12666 enum insn_code nor_code
;
12669 rev_code
= reverse_condition_maybe_unordered (rcode
);
12670 eq_rtx
= rs6000_emit_vector_compare (rev_code
, op0
, op1
,
12673 nor_code
= optab_handler (one_cmpl_optab
, (int)dest_mode
)->insn_code
;
12674 gcc_assert (nor_code
!= CODE_FOR_nothing
);
12675 emit_insn (GEN_FCN (nor_code
) (mask
, eq_rtx
));
12677 if (dmode
!= dest_mode
)
12679 rtx temp
= gen_reg_rtx (dest_mode
);
12680 convert_move (temp
, mask
, 0);
12690 /* Try GT/GTU/LT/LTU OR EQ */
12693 enum insn_code ior_code
;
12694 enum rtx_code new_code
;
12715 gcc_unreachable ();
12718 c_rtx
= rs6000_emit_vector_compare (new_code
,
12719 op0
, op1
, dest_mode
);
12720 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
,
12723 ior_code
= optab_handler (ior_optab
, (int)dest_mode
)->insn_code
;
12724 gcc_assert (ior_code
!= CODE_FOR_nothing
);
12725 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
12726 if (dmode
!= dest_mode
)
12728 rtx temp
= gen_reg_rtx (dest_mode
);
12729 convert_move (temp
, mask
, 0);
12736 gcc_unreachable ();
12741 vec_cmp_insn
= get_vec_cmp_insn (rcode
, dest_mode
, op_mode
);
12742 /* You only get two chances. */
12743 gcc_assert (vec_cmp_insn
!= INSN_NOT_AVAILABLE
);
12755 emit_insn (gen_rtx_SET (VOIDmode
, mask
,
12756 gen_rtx_UNSPEC (dest_mode
,
12757 gen_rtvec (2, op0
, op1
),
12759 if (dmode
!= dest_mode
)
12761 rtx temp
= gen_reg_rtx (dest_mode
);
12762 convert_move (temp
, mask
, 0);
12768 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
12769 valid insn doesn exist for given mode. */
12772 get_vsel_insn (enum machine_mode mode
)
12777 return UNSPEC_VSEL4SI
;
12780 return UNSPEC_VSEL4SF
;
12783 return UNSPEC_VSEL8HI
;
12786 return UNSPEC_VSEL16QI
;
12789 return INSN_NOT_AVAILABLE
;
12792 return INSN_NOT_AVAILABLE
;
12795 /* Emit vector select insn where DEST is destination using
12796 operands OP1, OP2 and MASK. */
12799 rs6000_emit_vector_select (rtx dest
, rtx op1
, rtx op2
, rtx mask
)
12802 enum machine_mode dest_mode
= GET_MODE (dest
);
12803 int vsel_insn_index
= get_vsel_insn (GET_MODE (dest
));
12805 temp
= gen_reg_rtx (dest_mode
);
12807 /* For each vector element, select op1 when mask is 1 otherwise
12809 t
= gen_rtx_SET (VOIDmode
, temp
,
12810 gen_rtx_UNSPEC (dest_mode
,
12811 gen_rtvec (3, op2
, op1
, mask
),
12814 emit_move_insn (dest
, temp
);
12818 /* Emit vector conditional expression.
12819 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
12820 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
12823 rs6000_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
12824 rtx cond
, rtx cc_op0
, rtx cc_op1
)
12826 enum machine_mode dest_mode
= GET_MODE (dest
);
12827 enum rtx_code rcode
= GET_CODE (cond
);
12830 if (!TARGET_ALTIVEC
)
12833 /* Get the vector mask for the given relational operations. */
12834 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, dest_mode
);
12836 rs6000_emit_vector_select (dest
, op1
, op2
, mask
);
12841 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
12842 operands of the last comparison is nonzero/true, FALSE_COND if it
12843 is zero/false. Return 0 if the hardware has no such operation. */
12846 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
12848 enum rtx_code code
= GET_CODE (op
);
12849 rtx op0
= rs6000_compare_op0
;
12850 rtx op1
= rs6000_compare_op1
;
12851 REAL_VALUE_TYPE c1
;
12852 enum machine_mode compare_mode
= GET_MODE (op0
);
12853 enum machine_mode result_mode
= GET_MODE (dest
);
12855 bool is_against_zero
;
12857 /* These modes should always match. */
12858 if (GET_MODE (op1
) != compare_mode
12859 /* In the isel case however, we can use a compare immediate, so
12860 op1 may be a small constant. */
12861 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
12863 if (GET_MODE (true_cond
) != result_mode
)
12865 if (GET_MODE (false_cond
) != result_mode
)
12868 /* First, work out if the hardware can do this at all, or
12869 if it's too slow.... */
12870 if (! rs6000_compare_fp_p
)
12873 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
12876 else if (TARGET_HARD_FLOAT
&& !TARGET_FPRS
12877 && SCALAR_FLOAT_MODE_P (compare_mode
))
12880 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
12882 /* A floating-point subtract might overflow, underflow, or produce
12883 an inexact result, thus changing the floating-point flags, so it
12884 can't be generated if we care about that. It's safe if one side
12885 of the construct is zero, since then no subtract will be
12887 if (SCALAR_FLOAT_MODE_P (compare_mode
)
12888 && flag_trapping_math
&& ! is_against_zero
)
12891 /* Eliminate half of the comparisons by switching operands, this
12892 makes the remaining code simpler. */
12893 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
12894 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
12896 code
= reverse_condition_maybe_unordered (code
);
12898 true_cond
= false_cond
;
12902 /* UNEQ and LTGT take four instructions for a comparison with zero,
12903 it'll probably be faster to use a branch here too. */
12904 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
12907 if (GET_CODE (op1
) == CONST_DOUBLE
)
12908 REAL_VALUE_FROM_CONST_DOUBLE (c1
, op1
);
12910 /* We're going to try to implement comparisons by performing
12911 a subtract, then comparing against zero. Unfortunately,
12912 Inf - Inf is NaN which is not zero, and so if we don't
12913 know that the operand is finite and the comparison
12914 would treat EQ different to UNORDERED, we can't do it. */
12915 if (HONOR_INFINITIES (compare_mode
)
12916 && code
!= GT
&& code
!= UNGE
12917 && (GET_CODE (op1
) != CONST_DOUBLE
|| real_isinf (&c1
))
12918 /* Constructs of the form (a OP b ? a : b) are safe. */
12919 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
12920 || (! rtx_equal_p (op0
, true_cond
)
12921 && ! rtx_equal_p (op1
, true_cond
))))
12924 /* At this point we know we can use fsel. */
12926 /* Reduce the comparison to a comparison against zero. */
12927 if (! is_against_zero
)
12929 temp
= gen_reg_rtx (compare_mode
);
12930 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
12931 gen_rtx_MINUS (compare_mode
, op0
, op1
)));
12933 op1
= CONST0_RTX (compare_mode
);
12936 /* If we don't care about NaNs we can reduce some of the comparisons
12937 down to faster ones. */
12938 if (! HONOR_NANS (compare_mode
))
12944 true_cond
= false_cond
;
12957 /* Now, reduce everything down to a GE. */
12964 temp
= gen_reg_rtx (compare_mode
);
12965 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
12970 temp
= gen_reg_rtx (compare_mode
);
12971 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_ABS (compare_mode
, op0
)));
12976 temp
= gen_reg_rtx (compare_mode
);
12977 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
12978 gen_rtx_NEG (compare_mode
,
12979 gen_rtx_ABS (compare_mode
, op0
))));
12984 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
12985 temp
= gen_reg_rtx (result_mode
);
12986 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
12987 gen_rtx_IF_THEN_ELSE (result_mode
,
12988 gen_rtx_GE (VOIDmode
,
12990 true_cond
, false_cond
)));
12991 false_cond
= true_cond
;
12994 temp
= gen_reg_rtx (compare_mode
);
12995 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
13000 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
13001 temp
= gen_reg_rtx (result_mode
);
13002 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
13003 gen_rtx_IF_THEN_ELSE (result_mode
,
13004 gen_rtx_GE (VOIDmode
,
13006 true_cond
, false_cond
)));
13007 true_cond
= false_cond
;
13010 temp
= gen_reg_rtx (compare_mode
);
13011 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
13016 gcc_unreachable ();
13019 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
13020 gen_rtx_IF_THEN_ELSE (result_mode
,
13021 gen_rtx_GE (VOIDmode
,
13023 true_cond
, false_cond
)));
13027 /* Same as above, but for ints (isel). */
13030 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
13032 rtx condition_rtx
, cr
;
13034 /* All isel implementations thus far are 32-bits. */
13035 if (GET_MODE (rs6000_compare_op0
) != SImode
)
13038 /* We still have to do the compare, because isel doesn't do a
13039 compare, it just looks at the CRx bits set by a previous compare
13041 condition_rtx
= rs6000_generate_compare (GET_CODE (op
));
13042 cr
= XEXP (condition_rtx
, 0);
13044 if (GET_MODE (cr
) == CCmode
)
13045 emit_insn (gen_isel_signed (dest
, condition_rtx
,
13046 true_cond
, false_cond
, cr
));
13048 emit_insn (gen_isel_unsigned (dest
, condition_rtx
,
13049 true_cond
, false_cond
, cr
));
13055 output_isel (rtx
*operands
)
13057 enum rtx_code code
;
13059 code
= GET_CODE (operands
[1]);
13060 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
13062 PUT_CODE (operands
[1], reverse_condition (code
));
13063 return "isel %0,%3,%2,%j1";
13066 return "isel %0,%2,%3,%j1";
13070 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
13072 enum machine_mode mode
= GET_MODE (op0
);
13076 if (code
== SMAX
|| code
== SMIN
)
13081 if (code
== SMAX
|| code
== UMAX
)
13082 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
13083 op0
, op1
, mode
, 0);
13085 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
13086 op1
, op0
, mode
, 0);
13087 gcc_assert (target
);
13088 if (target
!= dest
)
13089 emit_move_insn (dest
, target
);
13092 /* Emit instructions to perform a load-reserved/store-conditional operation.
13093 The operation performed is an atomic
13094 (set M (CODE:MODE M OP))
13095 If not NULL, BEFORE is atomically set to M before the operation, and
13096 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
13097 If SYNC_P then a memory barrier is emitted before the operation.
13098 Either OP or M may be wrapped in a NOT operation. */
13101 rs6000_emit_sync (enum rtx_code code
, enum machine_mode mode
,
13102 rtx m
, rtx op
, rtx before_param
, rtx after_param
,
13105 enum machine_mode used_mode
;
13106 rtx the_op
, set_before
, set_after
, set_atomic
, cc_scratch
, before
, after
;
13109 HOST_WIDE_INT imask
= GET_MODE_MASK (mode
);
13110 rtx shift
= NULL_RTX
;
13113 emit_insn (gen_memory_barrier ());
13115 if (GET_CODE (m
) == NOT
)
13116 used_m
= XEXP (m
, 0);
13120 /* If this is smaller than SImode, we'll have to use SImode with
13122 if (mode
== QImode
|| mode
== HImode
)
13126 if (MEM_ALIGN (used_m
) >= 32)
13129 if (BYTES_BIG_ENDIAN
)
13130 ishift
= GET_MODE_BITSIZE (SImode
) - GET_MODE_BITSIZE (mode
);
13132 shift
= GEN_INT (ishift
);
13133 used_m
= change_address (used_m
, SImode
, 0);
13137 rtx addrSI
, aligned_addr
;
13138 int shift_mask
= mode
== QImode
? 0x18 : 0x10;
13140 addrSI
= gen_lowpart_common (SImode
,
13141 force_reg (Pmode
, XEXP (used_m
, 0)));
13142 addrSI
= force_reg (SImode
, addrSI
);
13143 shift
= gen_reg_rtx (SImode
);
13145 emit_insn (gen_rlwinm (shift
, addrSI
, GEN_INT (3),
13146 GEN_INT (shift_mask
)));
13147 emit_insn (gen_xorsi3 (shift
, shift
, GEN_INT (shift_mask
)));
13149 aligned_addr
= expand_binop (Pmode
, and_optab
,
13151 GEN_INT (-4), NULL_RTX
,
13152 1, OPTAB_LIB_WIDEN
);
13153 used_m
= change_address (used_m
, SImode
, aligned_addr
);
13154 set_mem_align (used_m
, 32);
13156 /* It's safe to keep the old alias set of USED_M, because
13157 the operation is atomic and only affects the original
13159 if (GET_CODE (m
) == NOT
)
13160 m
= gen_rtx_NOT (SImode
, used_m
);
13164 if (GET_CODE (op
) == NOT
)
13166 oldop
= lowpart_subreg (SImode
, XEXP (op
, 0), mode
);
13167 oldop
= gen_rtx_NOT (SImode
, oldop
);
13170 oldop
= lowpart_subreg (SImode
, op
, mode
);
13176 newop
= expand_binop (SImode
, and_optab
,
13177 oldop
, GEN_INT (imask
), NULL_RTX
,
13178 1, OPTAB_LIB_WIDEN
);
13179 emit_insn (gen_ashlsi3 (newop
, newop
, shift
));
13183 newop
= expand_binop (SImode
, ior_optab
,
13184 oldop
, GEN_INT (~imask
), NULL_RTX
,
13185 1, OPTAB_LIB_WIDEN
);
13186 emit_insn (gen_rotlsi3 (newop
, newop
, shift
));
13194 newop
= expand_binop (SImode
, and_optab
,
13195 oldop
, GEN_INT (imask
), NULL_RTX
,
13196 1, OPTAB_LIB_WIDEN
);
13197 emit_insn (gen_ashlsi3 (newop
, newop
, shift
));
13199 mask
= gen_reg_rtx (SImode
);
13200 emit_move_insn (mask
, GEN_INT (imask
));
13201 emit_insn (gen_ashlsi3 (mask
, mask
, shift
));
13204 newop
= gen_rtx_PLUS (SImode
, m
, newop
);
13206 newop
= gen_rtx_MINUS (SImode
, m
, newop
);
13207 newop
= gen_rtx_AND (SImode
, newop
, mask
);
13208 newop
= gen_rtx_IOR (SImode
, newop
,
13209 gen_rtx_AND (SImode
,
13210 gen_rtx_NOT (SImode
, mask
),
13216 gcc_unreachable ();
13219 if (GET_CODE (m
) == NOT
)
13223 mask
= gen_reg_rtx (SImode
);
13224 emit_move_insn (mask
, GEN_INT (imask
));
13225 emit_insn (gen_ashlsi3 (mask
, mask
, shift
));
13227 xorm
= gen_rtx_XOR (SImode
, used_m
, mask
);
13228 /* Depending on the value of 'op', the XOR or the operation might
13229 be able to be simplified away. */
13230 newop
= simplify_gen_binary (code
, SImode
, xorm
, newop
);
13233 used_mode
= SImode
;
13234 before
= gen_reg_rtx (used_mode
);
13235 after
= gen_reg_rtx (used_mode
);
13240 before
= before_param
;
13241 after
= after_param
;
13243 if (before
== NULL_RTX
)
13244 before
= gen_reg_rtx (used_mode
);
13245 if (after
== NULL_RTX
)
13246 after
= gen_reg_rtx (used_mode
);
13249 if ((code
== PLUS
|| code
== MINUS
|| GET_CODE (m
) == NOT
)
13250 && used_mode
!= mode
)
13251 the_op
= op
; /* Computed above. */
13252 else if (GET_CODE (op
) == NOT
&& GET_CODE (m
) != NOT
)
13253 the_op
= gen_rtx_fmt_ee (code
, used_mode
, op
, m
);
13255 the_op
= gen_rtx_fmt_ee (code
, used_mode
, m
, op
);
13257 set_after
= gen_rtx_SET (VOIDmode
, after
, the_op
);
13258 set_before
= gen_rtx_SET (VOIDmode
, before
, used_m
);
13259 set_atomic
= gen_rtx_SET (VOIDmode
, used_m
,
13260 gen_rtx_UNSPEC (used_mode
,
13261 gen_rtvec (1, the_op
),
13263 cc_scratch
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (CCmode
));
13265 if ((code
== PLUS
|| code
== MINUS
) && used_mode
!= mode
)
13266 vec
= gen_rtvec (5, set_after
, set_before
, set_atomic
, cc_scratch
,
13267 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (SImode
)));
13269 vec
= gen_rtvec (4, set_after
, set_before
, set_atomic
, cc_scratch
);
13270 emit_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
13272 /* Shift and mask the return values properly. */
13273 if (used_mode
!= mode
&& before_param
)
13275 emit_insn (gen_lshrsi3 (before
, before
, shift
));
13276 convert_move (before_param
, before
, 1);
13279 if (used_mode
!= mode
&& after_param
)
13281 emit_insn (gen_lshrsi3 (after
, after
, shift
));
13282 convert_move (after_param
, after
, 1);
13285 /* The previous sequence will end with a branch that's dependent on
13286 the conditional store, so placing an isync will ensure that no
13287 other instructions (especially, no load or store instructions)
13288 can start before the atomic operation completes. */
13290 emit_insn (gen_isync ());
13293 /* A subroutine of the atomic operation splitters. Jump to LABEL if
13294 COND is true. Mark the jump as unlikely to be taken. */
13297 emit_unlikely_jump (rtx cond
, rtx label
)
13299 rtx very_unlikely
= GEN_INT (REG_BR_PROB_BASE
/ 100 - 1);
13302 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
13303 x
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
13304 REG_NOTES (x
) = gen_rtx_EXPR_LIST (REG_BR_PROB
, very_unlikely
, NULL_RTX
);
13307 /* A subroutine of the atomic operation splitters. Emit a load-locked
13308 instruction in MODE. */
13311 emit_load_locked (enum machine_mode mode
, rtx reg
, rtx mem
)
13313 rtx (*fn
) (rtx
, rtx
) = NULL
;
13314 if (mode
== SImode
)
13315 fn
= gen_load_locked_si
;
13316 else if (mode
== DImode
)
13317 fn
= gen_load_locked_di
;
13318 emit_insn (fn (reg
, mem
));
13321 /* A subroutine of the atomic operation splitters. Emit a store-conditional
13322 instruction in MODE. */
13325 emit_store_conditional (enum machine_mode mode
, rtx res
, rtx mem
, rtx val
)
13327 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
13328 if (mode
== SImode
)
13329 fn
= gen_store_conditional_si
;
13330 else if (mode
== DImode
)
13331 fn
= gen_store_conditional_di
;
13333 /* Emit sync before stwcx. to address PPC405 Erratum. */
13334 if (PPC405_ERRATUM77
)
13335 emit_insn (gen_memory_barrier ());
13337 emit_insn (fn (res
, mem
, val
));
13340 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
13341 to perform. MEM is the memory on which to operate. VAL is the second
13342 operand of the binary operator. BEFORE and AFTER are optional locations to
13343 return the value of MEM either before of after the operation. SCRATCH is
13344 a scratch register. */
13347 rs6000_split_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
13348 rtx before
, rtx after
, rtx scratch
)
13350 enum machine_mode mode
= GET_MODE (mem
);
13351 rtx label
, x
, cond
= gen_rtx_REG (CCmode
, CR0_REGNO
);
13353 emit_insn (gen_memory_barrier ());
13355 label
= gen_label_rtx ();
13356 emit_label (label
);
13357 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
13359 if (before
== NULL_RTX
)
13361 emit_load_locked (mode
, before
, mem
);
13364 x
= gen_rtx_AND (mode
, gen_rtx_NOT (mode
, before
), val
);
13365 else if (code
== AND
)
13366 x
= gen_rtx_UNSPEC (mode
, gen_rtvec (2, before
, val
), UNSPEC_AND
);
13368 x
= gen_rtx_fmt_ee (code
, mode
, before
, val
);
13370 if (after
!= NULL_RTX
)
13371 emit_insn (gen_rtx_SET (VOIDmode
, after
, copy_rtx (x
)));
13372 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, x
));
13374 emit_store_conditional (mode
, cond
, mem
, scratch
);
13376 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
13377 emit_unlikely_jump (x
, label
);
13379 emit_insn (gen_isync ());
13382 /* Expand an atomic compare and swap operation. MEM is the memory on which
13383 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
13384 value to be stored. SCRATCH is a scratch GPR. */
13387 rs6000_split_compare_and_swap (rtx retval
, rtx mem
, rtx oldval
, rtx newval
,
13390 enum machine_mode mode
= GET_MODE (mem
);
13391 rtx label1
, label2
, x
, cond
= gen_rtx_REG (CCmode
, CR0_REGNO
);
13393 emit_insn (gen_memory_barrier ());
13395 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
13396 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
13397 emit_label (XEXP (label1
, 0));
13399 emit_load_locked (mode
, retval
, mem
);
13401 x
= gen_rtx_COMPARE (CCmode
, retval
, oldval
);
13402 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
13404 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
13405 emit_unlikely_jump (x
, label2
);
13407 emit_move_insn (scratch
, newval
);
13408 emit_store_conditional (mode
, cond
, mem
, scratch
);
13410 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
13411 emit_unlikely_jump (x
, label1
);
13413 emit_insn (gen_isync ());
13414 emit_label (XEXP (label2
, 0));
13417 /* Expand an atomic test and set operation. MEM is the memory on which
13418 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
13421 rs6000_split_lock_test_and_set (rtx retval
, rtx mem
, rtx val
, rtx scratch
)
13423 enum machine_mode mode
= GET_MODE (mem
);
13424 rtx label
, x
, cond
= gen_rtx_REG (CCmode
, CR0_REGNO
);
13426 emit_insn (gen_memory_barrier ());
13428 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
13429 emit_label (XEXP (label
, 0));
13431 emit_load_locked (mode
, retval
, mem
);
13432 emit_move_insn (scratch
, val
);
13433 emit_store_conditional (mode
, cond
, mem
, scratch
);
13435 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
13436 emit_unlikely_jump (x
, label
);
13438 emit_insn (gen_isync ());
13442 rs6000_expand_compare_and_swapqhi (rtx dst
, rtx mem
, rtx oldval
, rtx newval
)
13444 enum machine_mode mode
= GET_MODE (mem
);
13445 rtx addrSI
, align
, wdst
, shift
, mask
;
13446 HOST_WIDE_INT shift_mask
= mode
== QImode
? 0x18 : 0x10;
13447 HOST_WIDE_INT imask
= GET_MODE_MASK (mode
);
13449 /* Shift amount for subword relative to aligned word. */
13450 addrSI
= force_reg (SImode
, gen_lowpart_common (SImode
, XEXP (mem
, 0)));
13451 shift
= gen_reg_rtx (SImode
);
13452 emit_insn (gen_rlwinm (shift
, addrSI
, GEN_INT (3),
13453 GEN_INT (shift_mask
)));
13454 emit_insn (gen_xorsi3 (shift
, shift
, GEN_INT (shift_mask
)));
13456 /* Shift and mask old value into position within word. */
13457 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
13458 oldval
= expand_binop (SImode
, and_optab
,
13459 oldval
, GEN_INT (imask
), NULL_RTX
,
13460 1, OPTAB_LIB_WIDEN
);
13461 emit_insn (gen_ashlsi3 (oldval
, oldval
, shift
));
13463 /* Shift and mask new value into position within word. */
13464 newval
= convert_modes (SImode
, mode
, newval
, 1);
13465 newval
= expand_binop (SImode
, and_optab
,
13466 newval
, GEN_INT (imask
), NULL_RTX
,
13467 1, OPTAB_LIB_WIDEN
);
13468 emit_insn (gen_ashlsi3 (newval
, newval
, shift
));
13470 /* Mask for insertion. */
13471 mask
= gen_reg_rtx (SImode
);
13472 emit_move_insn (mask
, GEN_INT (imask
));
13473 emit_insn (gen_ashlsi3 (mask
, mask
, shift
));
13475 /* Address of aligned word containing subword. */
13476 align
= expand_binop (Pmode
, and_optab
, XEXP (mem
, 0), GEN_INT (-4),
13477 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
13478 mem
= change_address (mem
, SImode
, align
);
13479 set_mem_align (mem
, 32);
13480 MEM_VOLATILE_P (mem
) = 1;
13482 wdst
= gen_reg_rtx (SImode
);
13483 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst
, mask
,
13484 oldval
, newval
, mem
));
13486 emit_move_insn (dst
, gen_lowpart (mode
, wdst
));
13490 rs6000_split_compare_and_swapqhi (rtx dest
, rtx mask
,
13491 rtx oldval
, rtx newval
, rtx mem
,
13494 rtx label1
, label2
, x
, cond
= gen_rtx_REG (CCmode
, CR0_REGNO
);
13496 emit_insn (gen_memory_barrier ());
13497 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
13498 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
13499 emit_label (XEXP (label1
, 0));
13501 emit_load_locked (SImode
, scratch
, mem
);
13503 /* Mask subword within loaded value for comparison with oldval.
13504 Use UNSPEC_AND to avoid clobber.*/
13505 emit_insn (gen_rtx_SET (SImode
, dest
,
13506 gen_rtx_UNSPEC (SImode
,
13507 gen_rtvec (2, scratch
, mask
),
13510 x
= gen_rtx_COMPARE (CCmode
, dest
, oldval
);
13511 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
13513 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
13514 emit_unlikely_jump (x
, label2
);
13516 /* Clear subword within loaded value for insertion of new value. */
13517 emit_insn (gen_rtx_SET (SImode
, scratch
,
13518 gen_rtx_AND (SImode
,
13519 gen_rtx_NOT (SImode
, mask
), scratch
)));
13520 emit_insn (gen_iorsi3 (scratch
, scratch
, newval
));
13521 emit_store_conditional (SImode
, cond
, mem
, scratch
);
13523 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
13524 emit_unlikely_jump (x
, label1
);
13526 emit_insn (gen_isync ());
13527 emit_label (XEXP (label2
, 0));
13531 /* Emit instructions to move SRC to DST. Called by splitters for
13532 multi-register moves. It will emit at most one instruction for
13533 each register that is accessed; that is, it won't emit li/lis pairs
13534 (or equivalent for 64-bit code). One of SRC or DST must be a hard
13538 rs6000_split_multireg_move (rtx dst
, rtx src
)
13540 /* The register number of the first register being moved. */
13542 /* The mode that is to be moved. */
13543 enum machine_mode mode
;
13544 /* The mode that the move is being done in, and its size. */
13545 enum machine_mode reg_mode
;
13547 /* The number of registers that will be moved. */
13550 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
13551 mode
= GET_MODE (dst
);
13552 nregs
= hard_regno_nregs
[reg
][mode
];
13553 if (FP_REGNO_P (reg
))
13554 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
13555 else if (ALTIVEC_REGNO_P (reg
))
13556 reg_mode
= V16QImode
;
13557 else if (TARGET_E500_DOUBLE
&& mode
== TFmode
)
13560 reg_mode
= word_mode
;
13561 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
13563 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
13565 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
13567 /* Move register range backwards, if we might have destructive
13570 for (i
= nregs
- 1; i
>= 0; i
--)
13571 emit_insn (gen_rtx_SET (VOIDmode
,
13572 simplify_gen_subreg (reg_mode
, dst
, mode
,
13573 i
* reg_mode_size
),
13574 simplify_gen_subreg (reg_mode
, src
, mode
,
13575 i
* reg_mode_size
)));
13581 bool used_update
= false;
13583 if (MEM_P (src
) && INT_REGNO_P (reg
))
13587 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
13588 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
13591 breg
= XEXP (XEXP (src
, 0), 0);
13592 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
13593 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
13594 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
13595 emit_insn (TARGET_32BIT
13596 ? gen_addsi3 (breg
, breg
, delta_rtx
)
13597 : gen_adddi3 (breg
, breg
, delta_rtx
));
13598 src
= replace_equiv_address (src
, breg
);
13600 else if (! rs6000_offsettable_memref_p (src
))
13603 basereg
= gen_rtx_REG (Pmode
, reg
);
13604 emit_insn (gen_rtx_SET (VOIDmode
, basereg
, XEXP (src
, 0)));
13605 src
= replace_equiv_address (src
, basereg
);
13608 breg
= XEXP (src
, 0);
13609 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
13610 breg
= XEXP (breg
, 0);
13612 /* If the base register we are using to address memory is
13613 also a destination reg, then change that register last. */
13615 && REGNO (breg
) >= REGNO (dst
)
13616 && REGNO (breg
) < REGNO (dst
) + nregs
)
13617 j
= REGNO (breg
) - REGNO (dst
);
13620 if (GET_CODE (dst
) == MEM
&& INT_REGNO_P (reg
))
13624 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
13625 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
13628 breg
= XEXP (XEXP (dst
, 0), 0);
13629 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
13630 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
13631 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
13633 /* We have to update the breg before doing the store.
13634 Use store with update, if available. */
13638 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
13639 emit_insn (TARGET_32BIT
13640 ? (TARGET_POWERPC64
13641 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
13642 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
13643 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
13644 used_update
= true;
13647 emit_insn (TARGET_32BIT
13648 ? gen_addsi3 (breg
, breg
, delta_rtx
)
13649 : gen_adddi3 (breg
, breg
, delta_rtx
));
13650 dst
= replace_equiv_address (dst
, breg
);
13653 gcc_assert (rs6000_offsettable_memref_p (dst
));
13656 for (i
= 0; i
< nregs
; i
++)
13658 /* Calculate index to next subword. */
13663 /* If compiler already emitted move of first word by
13664 store with update, no need to do anything. */
13665 if (j
== 0 && used_update
)
13668 emit_insn (gen_rtx_SET (VOIDmode
,
13669 simplify_gen_subreg (reg_mode
, dst
, mode
,
13670 j
* reg_mode_size
),
13671 simplify_gen_subreg (reg_mode
, src
, mode
,
13672 j
* reg_mode_size
)));
13678 /* This page contains routines that are used to determine what the
13679 function prologue and epilogue code will do and write them out. */
13681 /* Return the first fixed-point register that is required to be
13682 saved. 32 if none. */
13685 first_reg_to_save (void)
13689 /* Find lowest numbered live register. */
13690 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
13691 if (df_regs_ever_live_p (first_reg
)
13692 && (! call_used_regs
[first_reg
]
13693 || (first_reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
13694 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
13695 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
13696 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
)))))
13701 && current_function_uses_pic_offset_table
13702 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
13703 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
13709 /* Similar, for FP regs. */
13712 first_fp_reg_to_save (void)
13716 /* Find lowest numbered live register. */
13717 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
13718 if (df_regs_ever_live_p (first_reg
))
13724 /* Similar, for AltiVec regs. */
13727 first_altivec_reg_to_save (void)
13731 /* Stack frame remains as is unless we are in AltiVec ABI. */
13732 if (! TARGET_ALTIVEC_ABI
)
13733 return LAST_ALTIVEC_REGNO
+ 1;
13735 /* On Darwin, the unwind routines are compiled without
13736 TARGET_ALTIVEC, and use save_world to save/restore the
13737 altivec registers when necessary. */
13738 if (DEFAULT_ABI
== ABI_DARWIN
&& current_function_calls_eh_return
13739 && ! TARGET_ALTIVEC
)
13740 return FIRST_ALTIVEC_REGNO
+ 20;
13742 /* Find lowest numbered live register. */
13743 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
13744 if (df_regs_ever_live_p (i
))
13750 /* Return a 32-bit mask of the AltiVec registers we need to set in
13751 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
13752 the 32-bit word is 0. */
13754 static unsigned int
13755 compute_vrsave_mask (void)
13757 unsigned int i
, mask
= 0;
13759 /* On Darwin, the unwind routines are compiled without
13760 TARGET_ALTIVEC, and use save_world to save/restore the
13761 call-saved altivec registers when necessary. */
13762 if (DEFAULT_ABI
== ABI_DARWIN
&& current_function_calls_eh_return
13763 && ! TARGET_ALTIVEC
)
13766 /* First, find out if we use _any_ altivec registers. */
13767 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
13768 if (df_regs_ever_live_p (i
))
13769 mask
|= ALTIVEC_REG_BIT (i
);
13774 /* Next, remove the argument registers from the set. These must
13775 be in the VRSAVE mask set by the caller, so we don't need to add
13776 them in again. More importantly, the mask we compute here is
13777 used to generate CLOBBERs in the set_vrsave insn, and we do not
13778 wish the argument registers to die. */
13779 for (i
= cfun
->args_info
.vregno
- 1; i
>= ALTIVEC_ARG_MIN_REG
; --i
)
13780 mask
&= ~ALTIVEC_REG_BIT (i
);
13782 /* Similarly, remove the return value from the set. */
13785 diddle_return_value (is_altivec_return_reg
, &yes
);
13787 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
13793 /* For a very restricted set of circumstances, we can cut down the
13794 size of prologues/epilogues by calling our own save/restore-the-world
13798 compute_save_world_info (rs6000_stack_t
*info_ptr
)
13800 info_ptr
->world_save_p
= 1;
13801 info_ptr
->world_save_p
13802 = (WORLD_SAVE_P (info_ptr
)
13803 && DEFAULT_ABI
== ABI_DARWIN
13804 && ! (current_function_calls_setjmp
&& flag_exceptions
)
13805 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
13806 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
13807 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
13808 && info_ptr
->cr_save_p
);
13810 /* This will not work in conjunction with sibcalls. Make sure there
13811 are none. (This check is expensive, but seldom executed.) */
13812 if (WORLD_SAVE_P (info_ptr
))
13815 for ( insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
13816 if ( GET_CODE (insn
) == CALL_INSN
13817 && SIBLING_CALL_P (insn
))
13819 info_ptr
->world_save_p
= 0;
13824 if (WORLD_SAVE_P (info_ptr
))
13826 /* Even if we're not touching VRsave, make sure there's room on the
13827 stack for it, if it looks like we're calling SAVE_WORLD, which
13828 will attempt to save it. */
13829 info_ptr
->vrsave_size
= 4;
13831 /* "Save" the VRsave register too if we're saving the world. */
13832 if (info_ptr
->vrsave_mask
== 0)
13833 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
13835 /* Because the Darwin register save/restore routines only handle
13836 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
13838 gcc_assert (info_ptr
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
13839 && (info_ptr
->first_altivec_reg_save
13840 >= FIRST_SAVED_ALTIVEC_REGNO
));
13847 is_altivec_return_reg (rtx reg
, void *xyes
)
13849 bool *yes
= (bool *) xyes
;
13850 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
13855 /* Calculate the stack information for the current function. This is
13856 complicated by having two separate calling sequences, the AIX calling
13857 sequence and the V.4 calling sequence.
13859 AIX (and Darwin/Mac OS X) stack frames look like:
13861 SP----> +---------------------------------------+
13862 | back chain to caller | 0 0
13863 +---------------------------------------+
13864 | saved CR | 4 8 (8-11)
13865 +---------------------------------------+
13867 +---------------------------------------+
13868 | reserved for compilers | 12 24
13869 +---------------------------------------+
13870 | reserved for binders | 16 32
13871 +---------------------------------------+
13872 | saved TOC pointer | 20 40
13873 +---------------------------------------+
13874 | Parameter save area (P) | 24 48
13875 +---------------------------------------+
13876 | Alloca space (A) | 24+P etc.
13877 +---------------------------------------+
13878 | Local variable space (L) | 24+P+A
13879 +---------------------------------------+
13880 | Float/int conversion temporary (X) | 24+P+A+L
13881 +---------------------------------------+
13882 | Save area for AltiVec registers (W) | 24+P+A+L+X
13883 +---------------------------------------+
13884 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
13885 +---------------------------------------+
13886 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
13887 +---------------------------------------+
13888 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
13889 +---------------------------------------+
13890 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
13891 +---------------------------------------+
13892 old SP->| back chain to caller's caller |
13893 +---------------------------------------+
13895 The required alignment for AIX configurations is two words (i.e., 8
13899 V.4 stack frames look like:
13901 SP----> +---------------------------------------+
13902 | back chain to caller | 0
13903 +---------------------------------------+
13904 | caller's saved LR | 4
13905 +---------------------------------------+
13906 | Parameter save area (P) | 8
13907 +---------------------------------------+
13908 | Alloca space (A) | 8+P
13909 +---------------------------------------+
13910 | Varargs save area (V) | 8+P+A
13911 +---------------------------------------+
13912 | Local variable space (L) | 8+P+A+V
13913 +---------------------------------------+
13914 | Float/int conversion temporary (X) | 8+P+A+V+L
13915 +---------------------------------------+
13916 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
13917 +---------------------------------------+
13918 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
13919 +---------------------------------------+
13920 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
13921 +---------------------------------------+
13922 | SPE: area for 64-bit GP registers |
13923 +---------------------------------------+
13924 | SPE alignment padding |
13925 +---------------------------------------+
13926 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
13927 +---------------------------------------+
13928 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
13929 +---------------------------------------+
13930 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
13931 +---------------------------------------+
13932 old SP->| back chain to caller's caller |
13933 +---------------------------------------+
13935 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
13936 given. (But note below and in sysv4.h that we require only 8 and
13937 may round up the size of our stack frame anyways. The historical
13938 reason is early versions of powerpc-linux which didn't properly
13939 align the stack at program startup. A happy side-effect is that
13940 -mno-eabi libraries can be used with -meabi programs.)
13942 The EABI configuration defaults to the V.4 layout. However,
13943 the stack alignment requirements may differ. If -mno-eabi is not
13944 given, the required stack alignment is 8 bytes; if -mno-eabi is
13945 given, the required alignment is 16 bytes. (But see V.4 comment
13948 #ifndef ABI_STACK_BOUNDARY
13949 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
13952 static rs6000_stack_t
*
13953 rs6000_stack_info (void)
13955 static rs6000_stack_t info
;
13956 rs6000_stack_t
*info_ptr
= &info
;
13957 int reg_size
= TARGET_32BIT
? 4 : 8;
13961 HOST_WIDE_INT non_fixed_size
;
13963 memset (&info
, 0, sizeof (info
));
13967 /* Cache value so we don't rescan instruction chain over and over. */
13968 if (cfun
->machine
->insn_chain_scanned_p
== 0)
13969 cfun
->machine
->insn_chain_scanned_p
13970 = spe_func_has_64bit_regs_p () + 1;
13971 info_ptr
->spe_64bit_regs_used
= cfun
->machine
->insn_chain_scanned_p
- 1;
13974 /* Select which calling sequence. */
13975 info_ptr
->abi
= DEFAULT_ABI
;
13977 /* Calculate which registers need to be saved & save area size. */
13978 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
13979 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
13980 even if it currently looks like we won't. Reload may need it to
13981 get at a constant; if so, it will have already created a constant
13982 pool entry for it. */
13983 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
13984 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
13985 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
13986 && current_function_uses_const_pool
13987 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
13988 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
13990 first_gp
= info_ptr
->first_gp_reg_save
;
13992 info_ptr
->gp_size
= reg_size
* (32 - first_gp
);
13994 /* For the SPE, we have an additional upper 32-bits on each GPR.
13995 Ideally we should save the entire 64-bits only when the upper
13996 half is used in SIMD instructions. Since we only record
13997 registers live (not the size they are used in), this proves
13998 difficult because we'd have to traverse the instruction chain at
13999 the right time, taking reload into account. This is a real pain,
14000 so we opt to save the GPRs in 64-bits always if but one register
14001 gets used in 64-bits. Otherwise, all the registers in the frame
14002 get saved in 32-bits.
14004 So... since when we save all GPRs (except the SP) in 64-bits, the
14005 traditional GP save area will be empty. */
14006 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
14007 info_ptr
->gp_size
= 0;
14009 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
14010 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
14012 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
14013 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
14014 - info_ptr
->first_altivec_reg_save
);
14016 /* Does this function call anything? */
14017 info_ptr
->calls_p
= (! current_function_is_leaf
14018 || cfun
->machine
->ra_needs_full_frame
);
14020 /* Determine if we need to save the link register. */
14021 if ((DEFAULT_ABI
== ABI_AIX
14022 && current_function_profile
14023 && !TARGET_PROFILE_KERNEL
)
14024 #ifdef TARGET_RELOCATABLE
14025 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
14027 || (info_ptr
->first_fp_reg_save
!= 64
14028 && !FP_SAVE_INLINE (info_ptr
->first_fp_reg_save
))
14029 || info_ptr
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
14030 || (DEFAULT_ABI
== ABI_V4
&& current_function_calls_alloca
)
14031 || info_ptr
->calls_p
14032 || rs6000_ra_ever_killed ())
14034 info_ptr
->lr_save_p
= 1;
14035 df_set_regs_ever_live (LR_REGNO
, true);
14038 /* Determine if we need to save the condition code registers. */
14039 if (df_regs_ever_live_p (CR2_REGNO
)
14040 || df_regs_ever_live_p (CR3_REGNO
)
14041 || df_regs_ever_live_p (CR4_REGNO
))
14043 info_ptr
->cr_save_p
= 1;
14044 if (DEFAULT_ABI
== ABI_V4
)
14045 info_ptr
->cr_size
= reg_size
;
14048 /* If the current function calls __builtin_eh_return, then we need
14049 to allocate stack space for registers that will hold data for
14050 the exception handler. */
14051 if (current_function_calls_eh_return
)
14054 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
14057 /* SPE saves EH registers in 64-bits. */
14058 ehrd_size
= i
* (TARGET_SPE_ABI
14059 && info_ptr
->spe_64bit_regs_used
!= 0
14060 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
14065 /* Determine various sizes. */
14066 info_ptr
->reg_size
= reg_size
;
14067 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
14068 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
14069 info_ptr
->parm_size
= RS6000_ALIGN (current_function_outgoing_args_size
,
14070 TARGET_ALTIVEC
? 16 : 8);
14071 if (FRAME_GROWS_DOWNWARD
)
14072 info_ptr
->vars_size
14073 += RS6000_ALIGN (info_ptr
->fixed_size
+ info_ptr
->vars_size
14074 + info_ptr
->parm_size
,
14075 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
14076 - (info_ptr
->fixed_size
+ info_ptr
->vars_size
14077 + info_ptr
->parm_size
);
14079 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
14080 info_ptr
->spe_gp_size
= 8 * (32 - first_gp
);
14082 info_ptr
->spe_gp_size
= 0;
14084 if (TARGET_ALTIVEC_ABI
)
14085 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
14087 info_ptr
->vrsave_mask
= 0;
14089 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
14090 info_ptr
->vrsave_size
= 4;
14092 info_ptr
->vrsave_size
= 0;
14094 compute_save_world_info (info_ptr
);
14096 /* Calculate the offsets. */
14097 switch (DEFAULT_ABI
)
14101 gcc_unreachable ();
14105 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
14106 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
14108 if (TARGET_ALTIVEC_ABI
)
14110 info_ptr
->vrsave_save_offset
14111 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
14113 /* Align stack so vector save area is on a quadword boundary.
14114 The padding goes above the vectors. */
14115 if (info_ptr
->altivec_size
!= 0)
14116 info_ptr
->altivec_padding_size
14117 = info_ptr
->vrsave_save_offset
& 0xF;
14119 info_ptr
->altivec_padding_size
= 0;
14121 info_ptr
->altivec_save_offset
14122 = info_ptr
->vrsave_save_offset
14123 - info_ptr
->altivec_padding_size
14124 - info_ptr
->altivec_size
;
14125 gcc_assert (info_ptr
->altivec_size
== 0
14126 || info_ptr
->altivec_save_offset
% 16 == 0);
14128 /* Adjust for AltiVec case. */
14129 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
14132 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
14133 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
14134 info_ptr
->lr_save_offset
= 2*reg_size
;
14138 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
14139 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
14140 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
14142 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
14144 /* Align stack so SPE GPR save area is aligned on a
14145 double-word boundary. */
14146 if (info_ptr
->spe_gp_size
!= 0)
14147 info_ptr
->spe_padding_size
14148 = 8 - (-info_ptr
->cr_save_offset
% 8);
14150 info_ptr
->spe_padding_size
= 0;
14152 info_ptr
->spe_gp_save_offset
14153 = info_ptr
->cr_save_offset
14154 - info_ptr
->spe_padding_size
14155 - info_ptr
->spe_gp_size
;
14157 /* Adjust for SPE case. */
14158 info_ptr
->ehrd_offset
= info_ptr
->spe_gp_save_offset
;
14160 else if (TARGET_ALTIVEC_ABI
)
14162 info_ptr
->vrsave_save_offset
14163 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
14165 /* Align stack so vector save area is on a quadword boundary. */
14166 if (info_ptr
->altivec_size
!= 0)
14167 info_ptr
->altivec_padding_size
14168 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
14170 info_ptr
->altivec_padding_size
= 0;
14172 info_ptr
->altivec_save_offset
14173 = info_ptr
->vrsave_save_offset
14174 - info_ptr
->altivec_padding_size
14175 - info_ptr
->altivec_size
;
14177 /* Adjust for AltiVec case. */
14178 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
;
14181 info_ptr
->ehrd_offset
= info_ptr
->cr_save_offset
;
14182 info_ptr
->ehrd_offset
-= ehrd_size
;
14183 info_ptr
->lr_save_offset
= reg_size
;
14187 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
14188 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
14189 + info_ptr
->gp_size
14190 + info_ptr
->altivec_size
14191 + info_ptr
->altivec_padding_size
14192 + info_ptr
->spe_gp_size
14193 + info_ptr
->spe_padding_size
14195 + info_ptr
->cr_size
14196 + info_ptr
->vrsave_size
,
14199 non_fixed_size
= (info_ptr
->vars_size
14200 + info_ptr
->parm_size
14201 + info_ptr
->save_size
);
14203 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
14204 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
14206 /* Determine if we need to allocate any stack frame:
14208 For AIX we need to push the stack if a frame pointer is needed
14209 (because the stack might be dynamically adjusted), if we are
14210 debugging, if we make calls, or if the sum of fp_save, gp_save,
14211 and local variables are more than the space needed to save all
14212 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
14213 + 18*8 = 288 (GPR13 reserved).
14215 For V.4 we don't have the stack cushion that AIX uses, but assume
14216 that the debugger can handle stackless frames. */
14218 if (info_ptr
->calls_p
)
14219 info_ptr
->push_p
= 1;
14221 else if (DEFAULT_ABI
== ABI_V4
)
14222 info_ptr
->push_p
= non_fixed_size
!= 0;
14224 else if (frame_pointer_needed
)
14225 info_ptr
->push_p
= 1;
14227 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
14228 info_ptr
->push_p
= 1;
14231 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
14233 /* Zero offsets if we're not saving those registers. */
14234 if (info_ptr
->fp_size
== 0)
14235 info_ptr
->fp_save_offset
= 0;
14237 if (info_ptr
->gp_size
== 0)
14238 info_ptr
->gp_save_offset
= 0;
14240 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->altivec_size
== 0)
14241 info_ptr
->altivec_save_offset
= 0;
14243 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->vrsave_mask
== 0)
14244 info_ptr
->vrsave_save_offset
= 0;
14246 if (! TARGET_SPE_ABI
14247 || info_ptr
->spe_64bit_regs_used
== 0
14248 || info_ptr
->spe_gp_size
== 0)
14249 info_ptr
->spe_gp_save_offset
= 0;
14251 if (! info_ptr
->lr_save_p
)
14252 info_ptr
->lr_save_offset
= 0;
14254 if (! info_ptr
->cr_save_p
)
14255 info_ptr
->cr_save_offset
= 0;
14260 /* Return true if the current function uses any GPRs in 64-bit SIMD
14264 spe_func_has_64bit_regs_p (void)
14268 /* Functions that save and restore all the call-saved registers will
14269 need to save/restore the registers in 64-bits. */
14270 if (current_function_calls_eh_return
14271 || current_function_calls_setjmp
14272 || current_function_has_nonlocal_goto
)
14275 insns
= get_insns ();
14277 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
14283 /* FIXME: This should be implemented with attributes...
14285 (set_attr "spe64" "true")....then,
14286 if (get_spe64(insn)) return true;
14288 It's the only reliable way to do the stuff below. */
14290 i
= PATTERN (insn
);
14291 if (GET_CODE (i
) == SET
)
14293 enum machine_mode mode
= GET_MODE (SET_SRC (i
));
14295 if (SPE_VECTOR_MODE (mode
))
14297 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
))
14307 debug_stack_info (rs6000_stack_t
*info
)
14309 const char *abi_string
;
14312 info
= rs6000_stack_info ();
14314 fprintf (stderr
, "\nStack information for function %s:\n",
14315 ((current_function_decl
&& DECL_NAME (current_function_decl
))
14316 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
14321 default: abi_string
= "Unknown"; break;
14322 case ABI_NONE
: abi_string
= "NONE"; break;
14323 case ABI_AIX
: abi_string
= "AIX"; break;
14324 case ABI_DARWIN
: abi_string
= "Darwin"; break;
14325 case ABI_V4
: abi_string
= "V.4"; break;
14328 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
14330 if (TARGET_ALTIVEC_ABI
)
14331 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
14333 if (TARGET_SPE_ABI
)
14334 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
14336 if (info
->first_gp_reg_save
!= 32)
14337 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
14339 if (info
->first_fp_reg_save
!= 64)
14340 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
14342 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
14343 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
14344 info
->first_altivec_reg_save
);
14346 if (info
->lr_save_p
)
14347 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
14349 if (info
->cr_save_p
)
14350 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
14352 if (info
->vrsave_mask
)
14353 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
14356 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
14359 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
14361 if (info
->gp_save_offset
)
14362 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
14364 if (info
->fp_save_offset
)
14365 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
14367 if (info
->altivec_save_offset
)
14368 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
14369 info
->altivec_save_offset
);
14371 if (info
->spe_gp_save_offset
)
14372 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
14373 info
->spe_gp_save_offset
);
14375 if (info
->vrsave_save_offset
)
14376 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
14377 info
->vrsave_save_offset
);
14379 if (info
->lr_save_offset
)
14380 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
14382 if (info
->cr_save_offset
)
14383 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
14385 if (info
->varargs_save_offset
)
14386 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
14388 if (info
->total_size
)
14389 fprintf (stderr
, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
14392 if (info
->vars_size
)
14393 fprintf (stderr
, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
14396 if (info
->parm_size
)
14397 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
14399 if (info
->fixed_size
)
14400 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
14403 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
14405 if (info
->spe_gp_size
)
14406 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
14409 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
14411 if (info
->altivec_size
)
14412 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
14414 if (info
->vrsave_size
)
14415 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
14417 if (info
->altivec_padding_size
)
14418 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
14419 info
->altivec_padding_size
);
14421 if (info
->spe_padding_size
)
14422 fprintf (stderr
, "\tspe_padding_size = %5d\n",
14423 info
->spe_padding_size
);
14426 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
14428 if (info
->save_size
)
14429 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
14431 if (info
->reg_size
!= 4)
14432 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
14434 fprintf (stderr
, "\n");
14438 rs6000_return_addr (int count
, rtx frame
)
14440 /* Currently we don't optimize very well between prolog and body
14441 code and for PIC code the code can be actually quite bad, so
14442 don't try to be too clever here. */
14443 if (count
!= 0 || (DEFAULT_ABI
!= ABI_AIX
&& flag_pic
))
14445 cfun
->machine
->ra_needs_full_frame
= 1;
14452 plus_constant (copy_to_reg
14453 (gen_rtx_MEM (Pmode
,
14454 memory_address (Pmode
, frame
))),
14455 RETURN_ADDRESS_OFFSET
)));
14458 cfun
->machine
->ra_need_lr
= 1;
14459 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
14462 /* Say whether a function is a candidate for sibcall handling or not.
14463 We do not allow indirect calls to be optimized into sibling calls.
14464 Also, we can't do it if there are any vector parameters; there's
14465 nowhere to put the VRsave code so it works; note that functions with
14466 vector parameters are required to have a prototype, so the argument
14467 type info must be available here. (The tail recursion case can work
14468 with vector parameters, but there's no way to distinguish here.) */
14470 rs6000_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
14475 if (TARGET_ALTIVEC_VRSAVE
)
14477 for (type
= TYPE_ARG_TYPES (TREE_TYPE (decl
));
14478 type
; type
= TREE_CHAIN (type
))
14480 if (TREE_CODE (TREE_VALUE (type
)) == VECTOR_TYPE
)
14484 if (DEFAULT_ABI
== ABI_DARWIN
14485 || ((*targetm
.binds_local_p
) (decl
)
14486 && (DEFAULT_ABI
!= ABI_AIX
|| !DECL_EXTERNAL (decl
))))
14488 tree attr_list
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
14490 if (!lookup_attribute ("longcall", attr_list
)
14491 || lookup_attribute ("shortcall", attr_list
))
14498 /* NULL if INSN insn is valid within a low-overhead loop.
14499 Otherwise return why doloop cannot be applied.
14500 PowerPC uses the COUNT register for branch on table instructions. */
14502 static const char *
14503 rs6000_invalid_within_doloop (const_rtx insn
)
14506 return "Function call in the loop.";
14509 && (GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
14510 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
))
14511 return "Computed branch in the loop.";
14517 rs6000_ra_ever_killed (void)
14523 if (current_function_is_thunk
)
14526 /* regs_ever_live has LR marked as used if any sibcalls are present,
14527 but this should not force saving and restoring in the
14528 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
14529 clobbers LR, so that is inappropriate. */
14531 /* Also, the prologue can generate a store into LR that
14532 doesn't really count, like this:
14535 bcl to set PIC register
14539 When we're called from the epilogue, we need to avoid counting
14540 this as a store. */
14542 push_topmost_sequence ();
14543 top
= get_insns ();
14544 pop_topmost_sequence ();
14545 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
14547 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
14553 if (!SIBLING_CALL_P (insn
))
14556 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
14558 else if (set_of (reg
, insn
) != NULL_RTX
14559 && !prologue_epilogue_contains (insn
))
14566 /* Emit instructions needed to load the TOC register.
14567 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
14568 a constant pool; or for SVR4 -fpic. */
14571 rs6000_emit_load_toc_table (int fromprolog
)
14574 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
14576 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
)
14579 rtx lab
, tmp1
, tmp2
, got
;
14581 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
14582 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
14584 got
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
14586 got
= rs6000_got_sym ();
14587 tmp1
= tmp2
= dest
;
14590 tmp1
= gen_reg_rtx (Pmode
);
14591 tmp2
= gen_reg_rtx (Pmode
);
14593 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
14594 emit_move_insn (tmp1
,
14595 gen_rtx_REG (Pmode
, LR_REGNO
));
14596 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
14597 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
14599 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
14601 emit_insn (gen_load_toc_v4_pic_si ());
14602 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
14604 else if (TARGET_ELF
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
== 2)
14607 rtx temp0
= (fromprolog
14608 ? gen_rtx_REG (Pmode
, 0)
14609 : gen_reg_rtx (Pmode
));
14615 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
14616 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
14618 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
14619 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
14621 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
14622 emit_move_insn (dest
,
14623 gen_rtx_REG (Pmode
, LR_REGNO
));
14624 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
14630 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
14631 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
));
14632 emit_move_insn (dest
,
14633 gen_rtx_REG (Pmode
, LR_REGNO
));
14634 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
14636 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
14638 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
14640 /* This is for AIX code running in non-PIC ELF32. */
14643 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
14644 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
14646 emit_insn (gen_elf_high (dest
, realsym
));
14647 emit_insn (gen_elf_low (dest
, dest
, realsym
));
14651 gcc_assert (DEFAULT_ABI
== ABI_AIX
);
14654 emit_insn (gen_load_toc_aix_si (dest
));
14656 emit_insn (gen_load_toc_aix_di (dest
));
14660 /* Emit instructions to restore the link register after determining where
14661 its value has been stored. */
14664 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
14666 rs6000_stack_t
*info
= rs6000_stack_info ();
14669 operands
[0] = source
;
14670 operands
[1] = scratch
;
14672 if (info
->lr_save_p
)
14674 rtx frame_rtx
= stack_pointer_rtx
;
14675 HOST_WIDE_INT sp_offset
= 0;
14678 if (frame_pointer_needed
14679 || current_function_calls_alloca
14680 || info
->total_size
> 32767)
14682 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
14683 emit_move_insn (operands
[1], tmp
);
14684 frame_rtx
= operands
[1];
14686 else if (info
->push_p
)
14687 sp_offset
= info
->total_size
;
14689 tmp
= plus_constant (frame_rtx
, info
->lr_save_offset
+ sp_offset
);
14690 tmp
= gen_frame_mem (Pmode
, tmp
);
14691 emit_move_insn (tmp
, operands
[0]);
14694 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
14697 static GTY(()) alias_set_type set
= -1;
14700 get_TOC_alias_set (void)
14703 set
= new_alias_set ();
14707 /* This returns nonzero if the current function uses the TOC. This is
14708 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
14709 is generated by the ABI_V4 load_toc_* patterns. */
14716 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14719 rtx pat
= PATTERN (insn
);
14722 if (GET_CODE (pat
) == PARALLEL
)
14723 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
14725 rtx sub
= XVECEXP (pat
, 0, i
);
14726 if (GET_CODE (sub
) == USE
)
14728 sub
= XEXP (sub
, 0);
14729 if (GET_CODE (sub
) == UNSPEC
14730 && XINT (sub
, 1) == UNSPEC_TOC
)
14740 create_TOC_reference (rtx symbol
)
14742 if (!can_create_pseudo_p ())
14743 df_set_regs_ever_live (TOC_REGISTER
, true);
14744 return gen_rtx_PLUS (Pmode
,
14745 gen_rtx_REG (Pmode
, TOC_REGISTER
),
14746 gen_rtx_CONST (Pmode
,
14747 gen_rtx_MINUS (Pmode
, symbol
,
14748 gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
))));
14751 /* If _Unwind_* has been called from within the same module,
14752 toc register is not guaranteed to be saved to 40(1) on function
14753 entry. Save it there in that case. */
14756 rs6000_aix_emit_builtin_unwind_init (void)
14759 rtx stack_top
= gen_reg_rtx (Pmode
);
14760 rtx opcode_addr
= gen_reg_rtx (Pmode
);
14761 rtx opcode
= gen_reg_rtx (SImode
);
14762 rtx tocompare
= gen_reg_rtx (SImode
);
14763 rtx no_toc_save_needed
= gen_label_rtx ();
14765 mem
= gen_frame_mem (Pmode
, hard_frame_pointer_rtx
);
14766 emit_move_insn (stack_top
, mem
);
14768 mem
= gen_frame_mem (Pmode
,
14769 gen_rtx_PLUS (Pmode
, stack_top
,
14770 GEN_INT (2 * GET_MODE_SIZE (Pmode
))));
14771 emit_move_insn (opcode_addr
, mem
);
14772 emit_move_insn (opcode
, gen_rtx_MEM (SImode
, opcode_addr
));
14773 emit_move_insn (tocompare
, gen_int_mode (TARGET_32BIT
? 0x80410014
14774 : 0xE8410028, SImode
));
14776 do_compare_rtx_and_jump (opcode
, tocompare
, EQ
, 1,
14777 SImode
, NULL_RTX
, NULL_RTX
,
14778 no_toc_save_needed
);
14780 mem
= gen_frame_mem (Pmode
,
14781 gen_rtx_PLUS (Pmode
, stack_top
,
14782 GEN_INT (5 * GET_MODE_SIZE (Pmode
))));
14783 emit_move_insn (mem
, gen_rtx_REG (Pmode
, 2));
14784 emit_label (no_toc_save_needed
);
14787 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
14788 and the change to the stack pointer. */
14791 rs6000_emit_stack_tie (void)
14793 rtx mem
= gen_frame_mem (BLKmode
,
14794 gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
14796 emit_insn (gen_stack_tie (mem
));
14799 /* Emit the correct code for allocating stack space, as insns.
14800 If COPY_R12, make sure a copy of the old frame is left in r12.
14801 The generated code may use hard register 0 as a temporary. */
14804 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, int copy_r12
)
14807 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
14808 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
14809 rtx todec
= gen_int_mode (-size
, Pmode
);
14811 if (INTVAL (todec
) != -size
)
14813 warning (0, "stack frame too large");
14814 emit_insn (gen_trap ());
14818 if (current_function_limit_stack
)
14820 if (REG_P (stack_limit_rtx
)
14821 && REGNO (stack_limit_rtx
) > 1
14822 && REGNO (stack_limit_rtx
) <= 31)
14824 emit_insn (TARGET_32BIT
14825 ? gen_addsi3 (tmp_reg
,
14828 : gen_adddi3 (tmp_reg
,
14832 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
14835 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
14837 && DEFAULT_ABI
== ABI_V4
)
14839 rtx toload
= gen_rtx_CONST (VOIDmode
,
14840 gen_rtx_PLUS (Pmode
,
14844 emit_insn (gen_elf_high (tmp_reg
, toload
));
14845 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
14846 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
14850 warning (0, "stack limit expression is not supported");
14853 if (copy_r12
|| ! TARGET_UPDATE
)
14854 emit_move_insn (gen_rtx_REG (Pmode
, 12), stack_reg
);
14860 /* Need a note here so that try_split doesn't get confused. */
14861 if (get_last_insn () == NULL_RTX
)
14862 emit_note (NOTE_INSN_DELETED
);
14863 insn
= emit_move_insn (tmp_reg
, todec
);
14864 try_split (PATTERN (insn
), insn
, 0);
14868 insn
= emit_insn (TARGET_32BIT
14869 ? gen_movsi_update (stack_reg
, stack_reg
,
14871 : gen_movdi_di_update (stack_reg
, stack_reg
,
14872 todec
, stack_reg
));
14876 insn
= emit_insn (TARGET_32BIT
14877 ? gen_addsi3 (stack_reg
, stack_reg
, todec
)
14878 : gen_adddi3 (stack_reg
, stack_reg
, todec
));
14879 emit_move_insn (gen_rtx_MEM (Pmode
, stack_reg
),
14880 gen_rtx_REG (Pmode
, 12));
14883 RTX_FRAME_RELATED_P (insn
) = 1;
14885 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
14886 gen_rtx_SET (VOIDmode
, stack_reg
,
14887 gen_rtx_PLUS (Pmode
, stack_reg
,
14892 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
14893 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
14894 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
14895 deduce these equivalences by itself so it wasn't necessary to hold
14896 its hand so much. */
14899 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
14900 rtx reg2
, rtx rreg
)
14904 /* copy_rtx will not make unique copies of registers, so we need to
14905 ensure we don't have unwanted sharing here. */
14907 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
14910 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
14912 real
= copy_rtx (PATTERN (insn
));
14914 if (reg2
!= NULL_RTX
)
14915 real
= replace_rtx (real
, reg2
, rreg
);
14917 real
= replace_rtx (real
, reg
,
14918 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
14919 STACK_POINTER_REGNUM
),
14922 /* We expect that 'real' is either a SET or a PARALLEL containing
14923 SETs (and possibly other stuff). In a PARALLEL, all the SETs
14924 are important so they all have to be marked RTX_FRAME_RELATED_P. */
14926 if (GET_CODE (real
) == SET
)
14930 temp
= simplify_rtx (SET_SRC (set
));
14932 SET_SRC (set
) = temp
;
14933 temp
= simplify_rtx (SET_DEST (set
));
14935 SET_DEST (set
) = temp
;
14936 if (GET_CODE (SET_DEST (set
)) == MEM
)
14938 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
14940 XEXP (SET_DEST (set
), 0) = temp
;
14947 gcc_assert (GET_CODE (real
) == PARALLEL
);
14948 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
14949 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
14951 rtx set
= XVECEXP (real
, 0, i
);
14953 temp
= simplify_rtx (SET_SRC (set
));
14955 SET_SRC (set
) = temp
;
14956 temp
= simplify_rtx (SET_DEST (set
));
14958 SET_DEST (set
) = temp
;
14959 if (GET_CODE (SET_DEST (set
)) == MEM
)
14961 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
14963 XEXP (SET_DEST (set
), 0) = temp
;
14965 RTX_FRAME_RELATED_P (set
) = 1;
14970 real
= spe_synthesize_frame_save (real
);
14972 RTX_FRAME_RELATED_P (insn
) = 1;
14973 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
14978 /* Given an SPE frame note, return a PARALLEL of SETs with the
14979 original note, plus a synthetic register save. */
14982 spe_synthesize_frame_save (rtx real
)
14984 rtx synth
, offset
, reg
, real2
;
14986 if (GET_CODE (real
) != SET
14987 || GET_MODE (SET_SRC (real
)) != V2SImode
)
14990 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
14991 frame related note. The parallel contains a set of the register
14992 being saved, and another set to a synthetic register (n+1200).
14993 This is so we can differentiate between 64-bit and 32-bit saves.
14994 Words cannot describe this nastiness. */
14996 gcc_assert (GET_CODE (SET_DEST (real
)) == MEM
14997 && GET_CODE (XEXP (SET_DEST (real
), 0)) == PLUS
14998 && GET_CODE (SET_SRC (real
)) == REG
);
15001 (set (mem (plus (reg x) (const y)))
15004 (set (mem (plus (reg x) (const y+4)))
15008 real2
= copy_rtx (real
);
15009 PUT_MODE (SET_DEST (real2
), SImode
);
15010 reg
= SET_SRC (real2
);
15011 real2
= replace_rtx (real2
, reg
, gen_rtx_REG (SImode
, REGNO (reg
)));
15012 synth
= copy_rtx (real2
);
15014 if (BYTES_BIG_ENDIAN
)
15016 offset
= XEXP (XEXP (SET_DEST (real2
), 0), 1);
15017 real2
= replace_rtx (real2
, offset
, GEN_INT (INTVAL (offset
) + 4));
15020 reg
= SET_SRC (synth
);
15022 synth
= replace_rtx (synth
, reg
,
15023 gen_rtx_REG (SImode
, REGNO (reg
) + 1200));
15025 offset
= XEXP (XEXP (SET_DEST (synth
), 0), 1);
15026 synth
= replace_rtx (synth
, offset
,
15027 GEN_INT (INTVAL (offset
)
15028 + (BYTES_BIG_ENDIAN
? 0 : 4)));
15030 RTX_FRAME_RELATED_P (synth
) = 1;
15031 RTX_FRAME_RELATED_P (real2
) = 1;
15032 if (BYTES_BIG_ENDIAN
)
15033 real
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, synth
, real2
));
15035 real
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, real2
, synth
));
15040 /* Returns an insn that has a vrsave set operation with the
15041 appropriate CLOBBERs. */
15044 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
15047 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
15048 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
15051 = gen_rtx_SET (VOIDmode
,
15053 gen_rtx_UNSPEC_VOLATILE (SImode
,
15054 gen_rtvec (2, reg
, vrsave
),
15055 UNSPECV_SET_VRSAVE
));
15059 /* We need to clobber the registers in the mask so the scheduler
15060 does not move sets to VRSAVE before sets of AltiVec registers.
15062 However, if the function receives nonlocal gotos, reload will set
15063 all call saved registers live. We will end up with:
15065 (set (reg 999) (mem))
15066 (parallel [ (set (reg vrsave) (unspec blah))
15067 (clobber (reg 999))])
15069 The clobber will cause the store into reg 999 to be dead, and
15070 flow will attempt to delete an epilogue insn. In this case, we
15071 need an unspec use/set of the register. */
15073 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
15074 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
15076 if (!epiloguep
|| call_used_regs
[i
])
15077 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
15078 gen_rtx_REG (V4SImode
, i
));
15081 rtx reg
= gen_rtx_REG (V4SImode
, i
);
15084 = gen_rtx_SET (VOIDmode
,
15086 gen_rtx_UNSPEC (V4SImode
,
15087 gen_rtvec (1, reg
), 27));
15091 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
15093 for (i
= 0; i
< nclobs
; ++i
)
15094 XVECEXP (insn
, 0, i
) = clobs
[i
];
15099 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
15100 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
15103 emit_frame_save (rtx frame_reg
, rtx frame_ptr
, enum machine_mode mode
,
15104 unsigned int regno
, int offset
, HOST_WIDE_INT total_size
)
15106 rtx reg
, offset_rtx
, insn
, mem
, addr
, int_rtx
;
15107 rtx replacea
, replaceb
;
15109 int_rtx
= GEN_INT (offset
);
15111 /* Some cases that need register indexed addressing. */
15112 if ((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
15113 || (TARGET_E500_DOUBLE
&& mode
== DFmode
)
15115 && SPE_VECTOR_MODE (mode
)
15116 && !SPE_CONST_OFFSET_OK (offset
)))
15118 /* Whomever calls us must make sure r11 is available in the
15119 flow path of instructions in the prologue. */
15120 offset_rtx
= gen_rtx_REG (Pmode
, 11);
15121 emit_move_insn (offset_rtx
, int_rtx
);
15123 replacea
= offset_rtx
;
15124 replaceb
= int_rtx
;
15128 offset_rtx
= int_rtx
;
15129 replacea
= NULL_RTX
;
15130 replaceb
= NULL_RTX
;
15133 reg
= gen_rtx_REG (mode
, regno
);
15134 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, offset_rtx
);
15135 mem
= gen_frame_mem (mode
, addr
);
15137 insn
= emit_move_insn (mem
, reg
);
15139 rs6000_frame_related (insn
, frame_ptr
, total_size
, replacea
, replaceb
);
15142 /* Emit an offset memory reference suitable for a frame store, while
15143 converting to a valid addressing mode. */
15146 gen_frame_mem_offset (enum machine_mode mode
, rtx reg
, int offset
)
15148 rtx int_rtx
, offset_rtx
;
15150 int_rtx
= GEN_INT (offset
);
15152 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
))
15153 || (TARGET_E500_DOUBLE
&& mode
== DFmode
))
15155 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
15156 emit_move_insn (offset_rtx
, int_rtx
);
15159 offset_rtx
= int_rtx
;
15161 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
15164 /* Look for user-defined global regs. We should not save and restore these,
15165 and cannot use stmw/lmw if there are any in its range. */
15168 no_global_regs_above (int first_greg
)
15171 for (i
= 0; i
< 32 - first_greg
; i
++)
15172 if (global_regs
[first_greg
+ i
])
15177 #ifndef TARGET_FIX_AND_CONTINUE
15178 #define TARGET_FIX_AND_CONTINUE 0
15181 /* Determine whether the gp REG is really used. */
15184 rs6000_reg_live_or_pic_offset_p (int reg
)
15186 return ((df_regs_ever_live_p (reg
)
15187 && (!call_used_regs
[reg
]
15188 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
15189 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
15190 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
15191 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
15192 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))));
15195 /* Emit function prologue as insns. */
15198 rs6000_emit_prologue (void)
15200 rs6000_stack_t
*info
= rs6000_stack_info ();
15201 enum machine_mode reg_mode
= Pmode
;
15202 int reg_size
= TARGET_32BIT
? 4 : 8;
15203 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
15204 rtx frame_ptr_rtx
= gen_rtx_REG (Pmode
, 12);
15205 rtx frame_reg_rtx
= sp_reg_rtx
;
15206 rtx cr_save_rtx
= NULL_RTX
;
15208 int saving_FPRs_inline
;
15209 int using_store_multiple
;
15210 HOST_WIDE_INT sp_offset
= 0;
15212 if (TARGET_FIX_AND_CONTINUE
)
15214 /* gdb on darwin arranges to forward a function from the old
15215 address by modifying the first 5 instructions of the function
15216 to branch to the overriding function. This is necessary to
15217 permit function pointers that point to the old function to
15218 actually forward to the new function. */
15219 emit_insn (gen_nop ());
15220 emit_insn (gen_nop ());
15221 emit_insn (gen_nop ());
15222 emit_insn (gen_nop ());
15223 emit_insn (gen_nop ());
15226 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
15228 reg_mode
= V2SImode
;
15232 using_store_multiple
= (TARGET_MULTIPLE
&& ! TARGET_POWERPC64
15233 && (!TARGET_SPE_ABI
15234 || info
->spe_64bit_regs_used
== 0)
15235 && info
->first_gp_reg_save
< 31
15236 && no_global_regs_above (info
->first_gp_reg_save
));
15237 saving_FPRs_inline
= (info
->first_fp_reg_save
== 64
15238 || FP_SAVE_INLINE (info
->first_fp_reg_save
)
15239 || current_function_calls_eh_return
15240 || cfun
->machine
->ra_need_lr
);
15242 /* For V.4, update stack before we do any saving and set back pointer. */
15243 if (! WORLD_SAVE_P (info
)
15245 && (DEFAULT_ABI
== ABI_V4
15246 || current_function_calls_eh_return
))
15248 if (info
->total_size
< 32767)
15249 sp_offset
= info
->total_size
;
15251 frame_reg_rtx
= frame_ptr_rtx
;
15252 rs6000_emit_allocate_stack (info
->total_size
,
15253 (frame_reg_rtx
!= sp_reg_rtx
15254 && (info
->cr_save_p
15256 || info
->first_fp_reg_save
< 64
15257 || info
->first_gp_reg_save
< 32
15259 if (frame_reg_rtx
!= sp_reg_rtx
)
15260 rs6000_emit_stack_tie ();
15263 /* Handle world saves specially here. */
15264 if (WORLD_SAVE_P (info
))
15271 /* save_world expects lr in r0. */
15272 reg0
= gen_rtx_REG (Pmode
, 0);
15273 if (info
->lr_save_p
)
15275 insn
= emit_move_insn (reg0
,
15276 gen_rtx_REG (Pmode
, LR_REGNO
));
15277 RTX_FRAME_RELATED_P (insn
) = 1;
15280 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
15281 assumptions about the offsets of various bits of the stack
15283 gcc_assert (info
->gp_save_offset
== -220
15284 && info
->fp_save_offset
== -144
15285 && info
->lr_save_offset
== 8
15286 && info
->cr_save_offset
== 4
15289 && (!current_function_calls_eh_return
15290 || info
->ehrd_offset
== -432)
15291 && info
->vrsave_save_offset
== -224
15292 && info
->altivec_save_offset
== -416);
15294 treg
= gen_rtx_REG (SImode
, 11);
15295 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
15297 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
15298 in R11. It also clobbers R12, so beware! */
15300 /* Preserve CR2 for save_world prologues */
15302 sz
+= 32 - info
->first_gp_reg_save
;
15303 sz
+= 64 - info
->first_fp_reg_save
;
15304 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
15305 p
= rtvec_alloc (sz
);
15307 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
15308 gen_rtx_REG (SImode
,
15310 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
15311 gen_rtx_SYMBOL_REF (Pmode
,
15313 /* We do floats first so that the instruction pattern matches
15315 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
15317 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
15318 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15319 GEN_INT (info
->fp_save_offset
15320 + sp_offset
+ 8 * i
));
15321 rtx mem
= gen_frame_mem (DFmode
, addr
);
15323 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
15325 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
15327 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
15328 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15329 GEN_INT (info
->altivec_save_offset
15330 + sp_offset
+ 16 * i
));
15331 rtx mem
= gen_frame_mem (V4SImode
, addr
);
15333 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
15335 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
15337 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
15338 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15339 GEN_INT (info
->gp_save_offset
15340 + sp_offset
+ reg_size
* i
));
15341 rtx mem
= gen_frame_mem (reg_mode
, addr
);
15343 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
15347 /* CR register traditionally saved as CR2. */
15348 rtx reg
= gen_rtx_REG (reg_mode
, CR2_REGNO
);
15349 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15350 GEN_INT (info
->cr_save_offset
15352 rtx mem
= gen_frame_mem (reg_mode
, addr
);
15354 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
15356 /* Explain about use of R0. */
15357 if (info
->lr_save_p
)
15359 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15360 GEN_INT (info
->lr_save_offset
15362 rtx mem
= gen_frame_mem (reg_mode
, addr
);
15364 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg0
);
15366 /* Explain what happens to the stack pointer. */
15368 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
15369 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, sp_reg_rtx
, newval
);
15372 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
15373 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
15374 treg
, GEN_INT (-info
->total_size
));
15375 sp_offset
= info
->total_size
;
15378 /* If we use the link register, get it into r0. */
15379 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
15381 rtx addr
, reg
, mem
;
15383 insn
= emit_move_insn (gen_rtx_REG (Pmode
, 0),
15384 gen_rtx_REG (Pmode
, LR_REGNO
));
15385 RTX_FRAME_RELATED_P (insn
) = 1;
15387 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15388 GEN_INT (info
->lr_save_offset
+ sp_offset
));
15389 reg
= gen_rtx_REG (Pmode
, 0);
15390 mem
= gen_rtx_MEM (Pmode
, addr
);
15391 /* This should not be of rs6000_sr_alias_set, because of
15392 __builtin_return_address. */
15394 insn
= emit_move_insn (mem
, reg
);
15395 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
15396 NULL_RTX
, NULL_RTX
);
15399 /* If we need to save CR, put it into r12. */
15400 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
&& frame_reg_rtx
!= frame_ptr_rtx
)
15404 cr_save_rtx
= gen_rtx_REG (SImode
, 12);
15405 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
15406 RTX_FRAME_RELATED_P (insn
) = 1;
15407 /* Now, there's no way that dwarf2out_frame_debug_expr is going
15408 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
15409 But that's OK. All we have to do is specify that _one_ condition
15410 code register is saved in this stack slot. The thrower's epilogue
15411 will then restore all the call-saved registers.
15412 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
15413 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
,
15414 gen_rtx_REG (SImode
, CR2_REGNO
));
15415 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
15420 /* Do any required saving of fpr's. If only one or two to save, do
15421 it ourselves. Otherwise, call function. */
15422 if (!WORLD_SAVE_P (info
) && saving_FPRs_inline
)
15425 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
15426 if ((df_regs_ever_live_p (info
->first_fp_reg_save
+i
)
15427 && ! call_used_regs
[info
->first_fp_reg_save
+i
]))
15428 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, DFmode
,
15429 info
->first_fp_reg_save
+ i
,
15430 info
->fp_save_offset
+ sp_offset
+ 8 * i
,
15433 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
15437 const char *alloc_rname
;
15439 p
= rtvec_alloc (2 + 64 - info
->first_fp_reg_save
);
15441 RTVEC_ELT (p
, 0) = gen_rtx_CLOBBER (VOIDmode
,
15442 gen_rtx_REG (Pmode
,
15444 sprintf (rname
, "%s%d%s", SAVE_FP_PREFIX
,
15445 info
->first_fp_reg_save
- 32, SAVE_FP_SUFFIX
);
15446 alloc_rname
= ggc_strdup (rname
);
15447 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
,
15448 gen_rtx_SYMBOL_REF (Pmode
,
15450 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
15452 rtx addr
, reg
, mem
;
15453 reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
15454 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15455 GEN_INT (info
->fp_save_offset
15456 + sp_offset
+ 8*i
));
15457 mem
= gen_frame_mem (DFmode
, addr
);
15459 RTVEC_ELT (p
, i
+ 2) = gen_rtx_SET (VOIDmode
, mem
, reg
);
15461 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
15462 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
15463 NULL_RTX
, NULL_RTX
);
15466 /* Save GPRs. This is done as a PARALLEL if we are using
15467 the store-multiple instructions. */
15468 if (!WORLD_SAVE_P (info
) && using_store_multiple
)
15472 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
15473 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
15475 rtx addr
, reg
, mem
;
15476 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
15477 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15478 GEN_INT (info
->gp_save_offset
15481 mem
= gen_frame_mem (reg_mode
, addr
);
15483 RTVEC_ELT (p
, i
) = gen_rtx_SET (VOIDmode
, mem
, reg
);
15485 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
15486 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
15487 NULL_RTX
, NULL_RTX
);
15489 else if (!WORLD_SAVE_P (info
)
15491 && info
->spe_64bit_regs_used
!= 0
15492 && info
->first_gp_reg_save
!= 32)
15495 rtx spe_save_area_ptr
;
15496 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
15497 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
15498 && !call_used_regs
[STATIC_CHAIN_REGNUM
]);
15500 /* Determine whether we can address all of the registers that need
15501 to be saved with an offset from the stack pointer that fits in
15502 the small const field for SPE memory instructions. */
15503 int spe_regs_addressable_via_sp
15504 = SPE_CONST_OFFSET_OK(info
->spe_gp_save_offset
+ sp_offset
15505 + (32 - info
->first_gp_reg_save
- 1) * reg_size
);
15508 if (spe_regs_addressable_via_sp
)
15510 spe_save_area_ptr
= sp_reg_rtx
;
15511 spe_offset
= info
->spe_gp_save_offset
+ sp_offset
;
15515 /* Make r11 point to the start of the SPE save area. We need
15516 to be careful here if r11 is holding the static chain. If
15517 it is, then temporarily save it in r0. We would use r0 as
15518 our base register here, but using r0 as a base register in
15519 loads and stores means something different from what we
15521 if (using_static_chain_p
)
15523 rtx r0
= gen_rtx_REG (Pmode
, 0);
15525 gcc_assert (info
->first_gp_reg_save
> 11);
15527 emit_move_insn (r0
, gen_rtx_REG (Pmode
, 11));
15530 spe_save_area_ptr
= gen_rtx_REG (Pmode
, 11);
15531 emit_insn (gen_addsi3 (spe_save_area_ptr
, sp_reg_rtx
,
15532 GEN_INT (info
->spe_gp_save_offset
+ sp_offset
)));
15537 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
15538 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
15540 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
15541 rtx offset
, addr
, mem
;
15543 /* We're doing all this to ensure that the offset fits into
15544 the immediate offset of 'evstdd'. */
15545 gcc_assert (SPE_CONST_OFFSET_OK (reg_size
* i
+ spe_offset
));
15547 offset
= GEN_INT (reg_size
* i
+ spe_offset
);
15548 addr
= gen_rtx_PLUS (Pmode
, spe_save_area_ptr
, offset
);
15549 mem
= gen_rtx_MEM (V2SImode
, addr
);
15551 insn
= emit_move_insn (mem
, reg
);
15553 rs6000_frame_related (insn
, spe_save_area_ptr
,
15554 info
->spe_gp_save_offset
15555 + sp_offset
+ reg_size
* i
,
15556 offset
, const0_rtx
);
15559 /* Move the static chain pointer back. */
15560 if (using_static_chain_p
&& !spe_regs_addressable_via_sp
)
15561 emit_move_insn (gen_rtx_REG (Pmode
, 11), gen_rtx_REG (Pmode
, 0));
15563 else if (!WORLD_SAVE_P (info
))
15566 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
15567 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
15569 rtx addr
, reg
, mem
;
15570 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
15572 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15573 GEN_INT (info
->gp_save_offset
15576 mem
= gen_frame_mem (reg_mode
, addr
);
15578 insn
= emit_move_insn (mem
, reg
);
15579 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
15580 NULL_RTX
, NULL_RTX
);
15584 /* ??? There's no need to emit actual instructions here, but it's the
15585 easiest way to get the frame unwind information emitted. */
15586 if (current_function_calls_eh_return
)
15588 unsigned int i
, regno
;
15590 /* In AIX ABI we need to pretend we save r2 here. */
15593 rtx addr
, reg
, mem
;
15595 reg
= gen_rtx_REG (reg_mode
, 2);
15596 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15597 GEN_INT (sp_offset
+ 5 * reg_size
));
15598 mem
= gen_frame_mem (reg_mode
, addr
);
15600 insn
= emit_move_insn (mem
, reg
);
15601 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
15602 NULL_RTX
, NULL_RTX
);
15603 PATTERN (insn
) = gen_blockage ();
15608 regno
= EH_RETURN_DATA_REGNO (i
);
15609 if (regno
== INVALID_REGNUM
)
15612 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, reg_mode
, regno
,
15613 info
->ehrd_offset
+ sp_offset
15614 + reg_size
* (int) i
,
15619 /* Save CR if we use any that must be preserved. */
15620 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
15622 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15623 GEN_INT (info
->cr_save_offset
+ sp_offset
));
15624 rtx mem
= gen_frame_mem (SImode
, addr
);
15625 /* See the large comment above about why CR2_REGNO is used. */
15626 rtx magic_eh_cr_reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
15628 /* If r12 was used to hold the original sp, copy cr into r0 now
15630 if (REGNO (frame_reg_rtx
) == 12)
15634 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
15635 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
15636 RTX_FRAME_RELATED_P (insn
) = 1;
15637 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
, magic_eh_cr_reg
);
15638 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
15643 insn
= emit_move_insn (mem
, cr_save_rtx
);
15645 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
15646 NULL_RTX
, NULL_RTX
);
15649 /* Update stack and set back pointer unless this is V.4,
15650 for which it was done previously. */
15651 if (!WORLD_SAVE_P (info
) && info
->push_p
15652 && !(DEFAULT_ABI
== ABI_V4
|| current_function_calls_eh_return
))
15654 if (info
->total_size
< 32767)
15655 sp_offset
= info
->total_size
;
15657 frame_reg_rtx
= frame_ptr_rtx
;
15658 rs6000_emit_allocate_stack (info
->total_size
,
15659 (frame_reg_rtx
!= sp_reg_rtx
15660 && ((info
->altivec_size
!= 0)
15661 || (info
->vrsave_mask
!= 0)
15663 if (frame_reg_rtx
!= sp_reg_rtx
)
15664 rs6000_emit_stack_tie ();
15667 /* Set frame pointer, if needed. */
15668 if (frame_pointer_needed
)
15670 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
15672 RTX_FRAME_RELATED_P (insn
) = 1;
15675 /* Save AltiVec registers if needed. Save here because the red zone does
15676 not include AltiVec registers. */
15677 if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
&& info
->altivec_size
!= 0)
15681 /* There should be a non inline version of this, for when we
15682 are saving lots of vector registers. */
15683 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
15684 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
15686 rtx areg
, savereg
, mem
;
15689 offset
= info
->altivec_save_offset
+ sp_offset
15690 + 16 * (i
- info
->first_altivec_reg_save
);
15692 savereg
= gen_rtx_REG (V4SImode
, i
);
15694 areg
= gen_rtx_REG (Pmode
, 0);
15695 emit_move_insn (areg
, GEN_INT (offset
));
15697 /* AltiVec addressing mode is [reg+reg]. */
15698 mem
= gen_frame_mem (V4SImode
,
15699 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
15701 insn
= emit_move_insn (mem
, savereg
);
15703 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
15704 areg
, GEN_INT (offset
));
15708 /* VRSAVE is a bit vector representing which AltiVec registers
15709 are used. The OS uses this to determine which vector
15710 registers to save on a context switch. We need to save
15711 VRSAVE on the stack frame, add whatever AltiVec registers we
15712 used in this function, and do the corresponding magic in the
15715 if (TARGET_ALTIVEC
&& TARGET_ALTIVEC_VRSAVE
15716 && info
->vrsave_mask
!= 0)
15718 rtx reg
, mem
, vrsave
;
15721 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
15722 as frame_reg_rtx and r11 as the static chain pointer for
15723 nested functions. */
15724 reg
= gen_rtx_REG (SImode
, 0);
15725 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
15727 emit_insn (gen_get_vrsave_internal (reg
));
15729 emit_insn (gen_rtx_SET (VOIDmode
, reg
, vrsave
));
15731 if (!WORLD_SAVE_P (info
))
15734 offset
= info
->vrsave_save_offset
+ sp_offset
;
15735 mem
= gen_frame_mem (SImode
,
15736 gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15737 GEN_INT (offset
)));
15738 insn
= emit_move_insn (mem
, reg
);
15741 /* Include the registers in the mask. */
15742 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
15744 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
15747 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
15748 if ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
15749 || (DEFAULT_ABI
== ABI_V4
15750 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
15751 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
)))
15753 /* If emit_load_toc_table will use the link register, we need to save
15754 it. We use R12 for this purpose because emit_load_toc_table
15755 can use register 0. This allows us to use a plain 'blr' to return
15756 from the procedure more often. */
15757 int save_LR_around_toc_setup
= (TARGET_ELF
15758 && DEFAULT_ABI
!= ABI_AIX
15760 && ! info
->lr_save_p
15761 && EDGE_COUNT (EXIT_BLOCK_PTR
->preds
) > 0);
15762 if (save_LR_around_toc_setup
)
15764 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
15766 insn
= emit_move_insn (frame_ptr_rtx
, lr
);
15767 RTX_FRAME_RELATED_P (insn
) = 1;
15769 rs6000_emit_load_toc_table (TRUE
);
15771 insn
= emit_move_insn (lr
, frame_ptr_rtx
);
15772 RTX_FRAME_RELATED_P (insn
) = 1;
15775 rs6000_emit_load_toc_table (TRUE
);
15779 if (DEFAULT_ABI
== ABI_DARWIN
15780 && flag_pic
&& current_function_uses_pic_offset_table
)
15782 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
15783 rtx src
= machopic_function_base_sym ();
15785 /* Save and restore LR locally around this call (in R0). */
15786 if (!info
->lr_save_p
)
15787 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
15789 emit_insn (gen_load_macho_picbase (src
));
15791 emit_move_insn (gen_rtx_REG (Pmode
,
15792 RS6000_PIC_OFFSET_TABLE_REGNUM
),
15795 if (!info
->lr_save_p
)
15796 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
15801 /* Write function prologue. */
15804 rs6000_output_function_prologue (FILE *file
,
15805 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
15807 rs6000_stack_t
*info
= rs6000_stack_info ();
15809 if (TARGET_DEBUG_STACK
)
15810 debug_stack_info (info
);
15812 /* Write .extern for any function we will call to save and restore
15814 if (info
->first_fp_reg_save
< 64
15815 && !FP_SAVE_INLINE (info
->first_fp_reg_save
))
15816 fprintf (file
, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
15817 SAVE_FP_PREFIX
, info
->first_fp_reg_save
- 32, SAVE_FP_SUFFIX
,
15818 RESTORE_FP_PREFIX
, info
->first_fp_reg_save
- 32,
15819 RESTORE_FP_SUFFIX
);
15821 /* Write .extern for AIX common mode routines, if needed. */
15822 if (! TARGET_POWER
&& ! TARGET_POWERPC
&& ! common_mode_defined
)
15824 fputs ("\t.extern __mulh\n", file
);
15825 fputs ("\t.extern __mull\n", file
);
15826 fputs ("\t.extern __divss\n", file
);
15827 fputs ("\t.extern __divus\n", file
);
15828 fputs ("\t.extern __quoss\n", file
);
15829 fputs ("\t.extern __quous\n", file
);
15830 common_mode_defined
= 1;
15833 if (! HAVE_prologue
)
15837 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
15838 the "toplevel" insn chain. */
15839 emit_note (NOTE_INSN_DELETED
);
15840 rs6000_emit_prologue ();
15841 emit_note (NOTE_INSN_DELETED
);
15843 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15847 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
15849 INSN_ADDRESSES_NEW (insn
, addr
);
15854 if (TARGET_DEBUG_STACK
)
15855 debug_rtx_list (get_insns (), 100);
15856 final (get_insns (), file
, FALSE
);
15860 rs6000_pic_labelno
++;
15863 /* Emit function epilogue as insns.
15865 At present, dwarf2out_frame_debug_expr doesn't understand
15866 register restores, so we don't bother setting RTX_FRAME_RELATED_P
15867 anywhere in the epilogue. Most of the insns below would in any case
15868 need special notes to explain where r11 is in relation to the stack. */
15871 rs6000_emit_epilogue (int sibcall
)
15873 rs6000_stack_t
*info
;
15874 int restoring_FPRs_inline
;
15875 int using_load_multiple
;
15876 int using_mtcr_multiple
;
15877 int use_backchain_to_restore_sp
;
15879 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
15880 rtx frame_reg_rtx
= sp_reg_rtx
;
15881 enum machine_mode reg_mode
= Pmode
;
15882 int reg_size
= TARGET_32BIT
? 4 : 8;
15885 info
= rs6000_stack_info ();
15887 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
15889 reg_mode
= V2SImode
;
15893 using_load_multiple
= (TARGET_MULTIPLE
&& ! TARGET_POWERPC64
15894 && (!TARGET_SPE_ABI
15895 || info
->spe_64bit_regs_used
== 0)
15896 && info
->first_gp_reg_save
< 31
15897 && no_global_regs_above (info
->first_gp_reg_save
));
15898 restoring_FPRs_inline
= (sibcall
15899 || current_function_calls_eh_return
15900 || info
->first_fp_reg_save
== 64
15901 || FP_SAVE_INLINE (info
->first_fp_reg_save
));
15902 use_backchain_to_restore_sp
= (frame_pointer_needed
15903 || current_function_calls_alloca
15904 || info
->total_size
> 32767);
15905 using_mtcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
15906 || rs6000_cpu
== PROCESSOR_PPC603
15907 || rs6000_cpu
== PROCESSOR_PPC750
15910 if (WORLD_SAVE_P (info
))
15914 const char *alloc_rname
;
15917 /* eh_rest_world_r10 will return to the location saved in the LR
15918 stack slot (which is not likely to be our caller.)
15919 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
15920 rest_world is similar, except any R10 parameter is ignored.
15921 The exception-handling stuff that was here in 2.95 is no
15922 longer necessary. */
15926 + 32 - info
->first_gp_reg_save
15927 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
15928 + 63 + 1 - info
->first_fp_reg_save
);
15930 strcpy (rname
, ((current_function_calls_eh_return
) ?
15931 "*eh_rest_world_r10" : "*rest_world"));
15932 alloc_rname
= ggc_strdup (rname
);
15935 RTVEC_ELT (p
, j
++) = gen_rtx_RETURN (VOIDmode
);
15936 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
15937 gen_rtx_REG (Pmode
,
15940 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
15941 /* The instruction pattern requires a clobber here;
15942 it is shared with the restVEC helper. */
15944 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
15947 /* CR register traditionally saved as CR2. */
15948 rtx reg
= gen_rtx_REG (reg_mode
, CR2_REGNO
);
15949 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15950 GEN_INT (info
->cr_save_offset
));
15951 rtx mem
= gen_frame_mem (reg_mode
, addr
);
15953 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
15956 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
15958 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
15959 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15960 GEN_INT (info
->gp_save_offset
15962 rtx mem
= gen_frame_mem (reg_mode
, addr
);
15964 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
15966 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
15968 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
15969 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15970 GEN_INT (info
->altivec_save_offset
15972 rtx mem
= gen_frame_mem (V4SImode
, addr
);
15974 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
15976 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
15978 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
15979 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15980 GEN_INT (info
->fp_save_offset
15982 rtx mem
= gen_frame_mem (DFmode
, addr
);
15984 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
15987 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
15989 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
15991 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
15993 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
15995 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
15996 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
16001 /* Set sp_offset based on the stack push from the prologue. */
16002 if (info
->total_size
< 32767)
16003 sp_offset
= info
->total_size
;
16005 /* Restore AltiVec registers if needed. */
16006 if (TARGET_ALTIVEC_ABI
&& info
->altivec_size
!= 0)
16010 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
16011 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
16013 rtx addr
, areg
, mem
;
16015 areg
= gen_rtx_REG (Pmode
, 0);
16017 (areg
, GEN_INT (info
->altivec_save_offset
16019 + 16 * (i
- info
->first_altivec_reg_save
)));
16021 /* AltiVec addressing mode is [reg+reg]. */
16022 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
16023 mem
= gen_frame_mem (V4SImode
, addr
);
16025 emit_move_insn (gen_rtx_REG (V4SImode
, i
), mem
);
16029 /* Restore VRSAVE if needed. */
16030 if (TARGET_ALTIVEC
&& TARGET_ALTIVEC_VRSAVE
16031 && info
->vrsave_mask
!= 0)
16033 rtx addr
, mem
, reg
;
16035 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16036 GEN_INT (info
->vrsave_save_offset
+ sp_offset
));
16037 mem
= gen_frame_mem (SImode
, addr
);
16038 reg
= gen_rtx_REG (SImode
, 12);
16039 emit_move_insn (reg
, mem
);
16041 emit_insn (generate_set_vrsave (reg
, info
, 1));
16046 /* If we have a frame pointer, a call to alloca, or a large stack
16047 frame, restore the old stack pointer using the backchain. Otherwise,
16048 we know what size to update it with. */
16049 if (use_backchain_to_restore_sp
)
16051 /* Under V.4, don't reset the stack pointer until after we're done
16052 loading the saved registers. */
16053 if (DEFAULT_ABI
== ABI_V4
)
16054 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
16056 emit_move_insn (frame_reg_rtx
,
16057 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
16059 else if (info
->push_p
)
16061 if (DEFAULT_ABI
== ABI_V4
16062 || current_function_calls_eh_return
)
16063 sp_offset
= info
->total_size
;
16066 emit_insn (TARGET_32BIT
16067 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
,
16068 GEN_INT (info
->total_size
))
16069 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
,
16070 GEN_INT (info
->total_size
)));
16074 /* Get the old lr if we saved it. */
16075 if (info
->lr_save_p
)
16077 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
,
16078 info
->lr_save_offset
+ sp_offset
);
16080 emit_move_insn (gen_rtx_REG (Pmode
, 0), mem
);
16083 /* Get the old cr if we saved it. */
16084 if (info
->cr_save_p
)
16086 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16087 GEN_INT (info
->cr_save_offset
+ sp_offset
));
16088 rtx mem
= gen_frame_mem (SImode
, addr
);
16090 emit_move_insn (gen_rtx_REG (SImode
, 12), mem
);
16093 /* Set LR here to try to overlap restores below. */
16094 if (info
->lr_save_p
)
16095 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
),
16096 gen_rtx_REG (Pmode
, 0));
16098 /* Load exception handler data registers, if needed. */
16099 if (current_function_calls_eh_return
)
16101 unsigned int i
, regno
;
16105 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16106 GEN_INT (sp_offset
+ 5 * reg_size
));
16107 rtx mem
= gen_frame_mem (reg_mode
, addr
);
16109 emit_move_insn (gen_rtx_REG (reg_mode
, 2), mem
);
16116 regno
= EH_RETURN_DATA_REGNO (i
);
16117 if (regno
== INVALID_REGNUM
)
16120 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
16121 info
->ehrd_offset
+ sp_offset
16122 + reg_size
* (int) i
);
16124 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
16128 /* Restore GPRs. This is done as a PARALLEL if we are using
16129 the load-multiple instructions. */
16130 if (using_load_multiple
)
16133 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
16134 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
16136 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16137 GEN_INT (info
->gp_save_offset
16140 rtx mem
= gen_frame_mem (reg_mode
, addr
);
16143 gen_rtx_SET (VOIDmode
,
16144 gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
16147 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
16149 else if (TARGET_SPE_ABI
16150 && info
->spe_64bit_regs_used
!= 0
16151 && info
->first_gp_reg_save
!= 32)
16153 rtx spe_save_area_ptr
;
16154 /* Determine whether we can address all of the registers that need
16155 to be saved with an offset from the stack pointer that fits in
16156 the small const field for SPE memory instructions. */
16157 int spe_regs_addressable_via_sp
16158 = SPE_CONST_OFFSET_OK(info
->spe_gp_save_offset
+ sp_offset
16159 + (32 - info
->first_gp_reg_save
- 1) * reg_size
);
16162 if (spe_regs_addressable_via_sp
)
16164 spe_save_area_ptr
= frame_reg_rtx
;
16165 spe_offset
= info
->spe_gp_save_offset
+ sp_offset
;
16169 /* Make r11 point to the start of the SPE save area. We worried about
16170 not clobbering it when we were saving registers in the prologue.
16171 There's no need to worry here because the static chain is passed
16172 anew to every function. */
16173 spe_save_area_ptr
= gen_rtx_REG (Pmode
, 11);
16175 emit_insn (gen_addsi3 (spe_save_area_ptr
, frame_reg_rtx
,
16176 GEN_INT (info
->spe_gp_save_offset
+ sp_offset
)));
16181 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
16182 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
16184 rtx offset
, addr
, mem
;
16186 /* We're doing all this to ensure that the immediate offset
16187 fits into the immediate field of 'evldd'. */
16188 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset
+ reg_size
* i
));
16190 offset
= GEN_INT (spe_offset
+ reg_size
* i
);
16191 addr
= gen_rtx_PLUS (Pmode
, spe_save_area_ptr
, offset
);
16192 mem
= gen_rtx_MEM (V2SImode
, addr
);
16194 emit_move_insn (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
16199 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
16200 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
16202 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16203 GEN_INT (info
->gp_save_offset
16206 rtx mem
= gen_frame_mem (reg_mode
, addr
);
16208 emit_move_insn (gen_rtx_REG (reg_mode
,
16209 info
->first_gp_reg_save
+ i
), mem
);
16212 /* Restore fpr's if we need to do it without calling a function. */
16213 if (restoring_FPRs_inline
)
16214 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
16215 if ((df_regs_ever_live_p (info
->first_fp_reg_save
+i
)
16216 && ! call_used_regs
[info
->first_fp_reg_save
+i
]))
16219 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16220 GEN_INT (info
->fp_save_offset
16223 mem
= gen_frame_mem (DFmode
, addr
);
16225 emit_move_insn (gen_rtx_REG (DFmode
,
16226 info
->first_fp_reg_save
+ i
),
16230 /* If we saved cr, restore it here. Just those that were used. */
16231 if (info
->cr_save_p
)
16233 rtx r12_rtx
= gen_rtx_REG (SImode
, 12);
16236 if (using_mtcr_multiple
)
16238 for (i
= 0; i
< 8; i
++)
16239 if (df_regs_ever_live_p (CR0_REGNO
+i
) && ! call_used_regs
[CR0_REGNO
+i
])
16241 gcc_assert (count
);
16244 if (using_mtcr_multiple
&& count
> 1)
16249 p
= rtvec_alloc (count
);
16252 for (i
= 0; i
< 8; i
++)
16253 if (df_regs_ever_live_p (CR0_REGNO
+i
) && ! call_used_regs
[CR0_REGNO
+i
])
16255 rtvec r
= rtvec_alloc (2);
16256 RTVEC_ELT (r
, 0) = r12_rtx
;
16257 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
16258 RTVEC_ELT (p
, ndx
) =
16259 gen_rtx_SET (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+i
),
16260 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
16263 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
16264 gcc_assert (ndx
== count
);
16267 for (i
= 0; i
< 8; i
++)
16268 if (df_regs_ever_live_p (CR0_REGNO
+i
) && ! call_used_regs
[CR0_REGNO
+i
])
16270 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode
,
16276 /* If this is V.4, unwind the stack pointer after all of the loads
16278 if (frame_reg_rtx
!= sp_reg_rtx
)
16280 /* This blockage is needed so that sched doesn't decide to move
16281 the sp change before the register restores. */
16282 rs6000_emit_stack_tie ();
16284 && info
->spe_64bit_regs_used
!= 0
16285 && info
->first_gp_reg_save
!= 32)
16286 emit_insn (gen_addsi3 (sp_reg_rtx
, gen_rtx_REG (Pmode
, 11),
16287 GEN_INT (-(info
->spe_gp_save_offset
+ sp_offset
))));
16289 emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
16291 else if (sp_offset
!= 0)
16292 emit_insn (TARGET_32BIT
16293 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
,
16294 GEN_INT (sp_offset
))
16295 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
,
16296 GEN_INT (sp_offset
)));
16298 if (current_function_calls_eh_return
)
16300 rtx sa
= EH_RETURN_STACKADJ_RTX
;
16301 emit_insn (TARGET_32BIT
16302 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
, sa
)
16303 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
, sa
));
16309 if (! restoring_FPRs_inline
)
16310 p
= rtvec_alloc (3 + 64 - info
->first_fp_reg_save
);
16312 p
= rtvec_alloc (2);
16314 RTVEC_ELT (p
, 0) = gen_rtx_RETURN (VOIDmode
);
16315 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
,
16316 gen_rtx_REG (Pmode
,
16319 /* If we have to restore more than two FP registers, branch to the
16320 restore function. It will return to our caller. */
16321 if (! restoring_FPRs_inline
)
16325 const char *alloc_rname
;
16327 sprintf (rname
, "%s%d%s", RESTORE_FP_PREFIX
,
16328 info
->first_fp_reg_save
- 32, RESTORE_FP_SUFFIX
);
16329 alloc_rname
= ggc_strdup (rname
);
16330 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
,
16331 gen_rtx_SYMBOL_REF (Pmode
,
16334 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
16337 addr
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
,
16338 GEN_INT (info
->fp_save_offset
+ 8*i
));
16339 mem
= gen_frame_mem (DFmode
, addr
);
16341 RTVEC_ELT (p
, i
+3) =
16342 gen_rtx_SET (VOIDmode
,
16343 gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
),
16348 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
16352 /* Write function epilogue. */
16355 rs6000_output_function_epilogue (FILE *file
,
16356 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
16358 if (! HAVE_epilogue
)
16360 rtx insn
= get_last_insn ();
16361 /* If the last insn was a BARRIER, we don't have to write anything except
16362 the trace table. */
16363 if (GET_CODE (insn
) == NOTE
)
16364 insn
= prev_nonnote_insn (insn
);
16365 if (insn
== 0 || GET_CODE (insn
) != BARRIER
)
16367 /* This is slightly ugly, but at least we don't have two
16368 copies of the epilogue-emitting code. */
16371 /* A NOTE_INSN_DELETED is supposed to be at the start
16372 and end of the "toplevel" insn chain. */
16373 emit_note (NOTE_INSN_DELETED
);
16374 rs6000_emit_epilogue (FALSE
);
16375 emit_note (NOTE_INSN_DELETED
);
16377 /* Expand INSN_ADDRESSES so final() doesn't crash. */
16381 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
16383 INSN_ADDRESSES_NEW (insn
, addr
);
16388 if (TARGET_DEBUG_STACK
)
16389 debug_rtx_list (get_insns (), 100);
16390 final (get_insns (), file
, FALSE
);
16396 macho_branch_islands ();
16397 /* Mach-O doesn't support labels at the end of objects, so if
16398 it looks like we might want one, insert a NOP. */
16400 rtx insn
= get_last_insn ();
16403 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
16404 insn
= PREV_INSN (insn
);
16408 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
)))
16409 fputs ("\tnop\n", file
);
16413 /* Output a traceback table here. See /usr/include/sys/debug.h for info
16416 We don't output a traceback table if -finhibit-size-directive was
16417 used. The documentation for -finhibit-size-directive reads
16418 ``don't output a @code{.size} assembler directive, or anything
16419 else that would cause trouble if the function is split in the
16420 middle, and the two halves are placed at locations far apart in
16421 memory.'' The traceback table has this property, since it
16422 includes the offset from the start of the function to the
16423 traceback table itself.
16425 System V.4 Powerpc's (and the embedded ABI derived from it) use a
16426 different traceback table. */
16427 if (DEFAULT_ABI
== ABI_AIX
&& ! flag_inhibit_size_directive
16428 && rs6000_traceback
!= traceback_none
&& !current_function_is_thunk
)
16430 const char *fname
= NULL
;
16431 const char *language_string
= lang_hooks
.name
;
16432 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
16434 int optional_tbtab
;
16435 rs6000_stack_t
*info
= rs6000_stack_info ();
16437 if (rs6000_traceback
== traceback_full
)
16438 optional_tbtab
= 1;
16439 else if (rs6000_traceback
== traceback_part
)
16440 optional_tbtab
= 0;
16442 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
16444 if (optional_tbtab
)
16446 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
16447 while (*fname
== '.') /* V.4 encodes . in the name */
16450 /* Need label immediately before tbtab, so we can compute
16451 its offset from the function start. */
16452 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
16453 ASM_OUTPUT_LABEL (file
, fname
);
16456 /* The .tbtab pseudo-op can only be used for the first eight
16457 expressions, since it can't handle the possibly variable
16458 length fields that follow. However, if you omit the optional
16459 fields, the assembler outputs zeros for all optional fields
16460 anyways, giving each variable length field is minimum length
16461 (as defined in sys/debug.h). Thus we can not use the .tbtab
16462 pseudo-op at all. */
16464 /* An all-zero word flags the start of the tbtab, for debuggers
16465 that have to find it by searching forward from the entry
16466 point or from the current pc. */
16467 fputs ("\t.long 0\n", file
);
16469 /* Tbtab format type. Use format type 0. */
16470 fputs ("\t.byte 0,", file
);
16472 /* Language type. Unfortunately, there does not seem to be any
16473 official way to discover the language being compiled, so we
16474 use language_string.
16475 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
16476 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
16477 a number, so for now use 9. */
16478 if (! strcmp (language_string
, "GNU C"))
16480 else if (! strcmp (language_string
, "GNU F77")
16481 || ! strcmp (language_string
, "GNU F95"))
16483 else if (! strcmp (language_string
, "GNU Pascal"))
16485 else if (! strcmp (language_string
, "GNU Ada"))
16487 else if (! strcmp (language_string
, "GNU C++")
16488 || ! strcmp (language_string
, "GNU Objective-C++"))
16490 else if (! strcmp (language_string
, "GNU Java"))
16492 else if (! strcmp (language_string
, "GNU Objective-C"))
16495 gcc_unreachable ();
16496 fprintf (file
, "%d,", i
);
16498 /* 8 single bit fields: global linkage (not set for C extern linkage,
16499 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
16500 from start of procedure stored in tbtab, internal function, function
16501 has controlled storage, function has no toc, function uses fp,
16502 function logs/aborts fp operations. */
16503 /* Assume that fp operations are used if any fp reg must be saved. */
16504 fprintf (file
, "%d,",
16505 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
16507 /* 6 bitfields: function is interrupt handler, name present in
16508 proc table, function calls alloca, on condition directives
16509 (controls stack walks, 3 bits), saves condition reg, saves
16511 /* The `function calls alloca' bit seems to be set whenever reg 31 is
16512 set up as a frame pointer, even when there is no alloca call. */
16513 fprintf (file
, "%d,",
16514 ((optional_tbtab
<< 6)
16515 | ((optional_tbtab
& frame_pointer_needed
) << 5)
16516 | (info
->cr_save_p
<< 1)
16517 | (info
->lr_save_p
)));
16519 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
16521 fprintf (file
, "%d,",
16522 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
16524 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
16525 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
16527 if (optional_tbtab
)
16529 /* Compute the parameter info from the function decl argument
16532 int next_parm_info_bit
= 31;
16534 for (decl
= DECL_ARGUMENTS (current_function_decl
);
16535 decl
; decl
= TREE_CHAIN (decl
))
16537 rtx parameter
= DECL_INCOMING_RTL (decl
);
16538 enum machine_mode mode
= GET_MODE (parameter
);
16540 if (GET_CODE (parameter
) == REG
)
16542 if (SCALAR_FLOAT_MODE_P (mode
))
16562 gcc_unreachable ();
16565 /* If only one bit will fit, don't or in this entry. */
16566 if (next_parm_info_bit
> 0)
16567 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
16568 next_parm_info_bit
-= 2;
16572 fixed_parms
+= ((GET_MODE_SIZE (mode
)
16573 + (UNITS_PER_WORD
- 1))
16575 next_parm_info_bit
-= 1;
16581 /* Number of fixed point parameters. */
16582 /* This is actually the number of words of fixed point parameters; thus
16583 an 8 byte struct counts as 2; and thus the maximum value is 8. */
16584 fprintf (file
, "%d,", fixed_parms
);
16586 /* 2 bitfields: number of floating point parameters (7 bits), parameters
16588 /* This is actually the number of fp registers that hold parameters;
16589 and thus the maximum value is 13. */
16590 /* Set parameters on stack bit if parameters are not in their original
16591 registers, regardless of whether they are on the stack? Xlc
16592 seems to set the bit when not optimizing. */
16593 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
16595 if (! optional_tbtab
)
16598 /* Optional fields follow. Some are variable length. */
16600 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
16601 11 double float. */
16602 /* There is an entry for each parameter in a register, in the order that
16603 they occur in the parameter list. Any intervening arguments on the
16604 stack are ignored. If the list overflows a long (max possible length
16605 34 bits) then completely leave off all elements that don't fit. */
16606 /* Only emit this long if there was at least one parameter. */
16607 if (fixed_parms
|| float_parms
)
16608 fprintf (file
, "\t.long %d\n", parm_info
);
16610 /* Offset from start of code to tb table. */
16611 fputs ("\t.long ", file
);
16612 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
16614 RS6000_OUTPUT_BASENAME (file
, fname
);
16616 assemble_name (file
, fname
);
16618 rs6000_output_function_entry (file
, fname
);
16621 /* Interrupt handler mask. */
16622 /* Omit this long, since we never set the interrupt handler bit
16625 /* Number of CTL (controlled storage) anchors. */
16626 /* Omit this long, since the has_ctl bit is never set above. */
16628 /* Displacement into stack of each CTL anchor. */
16629 /* Omit this list of longs, because there are no CTL anchors. */
16631 /* Length of function name. */
16634 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
16636 /* Function name. */
16637 assemble_string (fname
, strlen (fname
));
16639 /* Register for alloca automatic storage; this is always reg 31.
16640 Only emit this if the alloca bit was set above. */
16641 if (frame_pointer_needed
)
16642 fputs ("\t.byte 31\n", file
);
16644 fputs ("\t.align 2\n", file
);
16648 /* A C compound statement that outputs the assembler code for a thunk
16649 function, used to implement C++ virtual function calls with
16650 multiple inheritance. The thunk acts as a wrapper around a virtual
16651 function, adjusting the implicit object parameter before handing
16652 control off to the real function.
16654 First, emit code to add the integer DELTA to the location that
16655 contains the incoming first argument. Assume that this argument
16656 contains a pointer, and is the one used to pass the `this' pointer
16657 in C++. This is the incoming argument *before* the function
16658 prologue, e.g. `%o0' on a sparc. The addition must preserve the
16659 values of all other incoming arguments.
16661 After the addition, emit code to jump to FUNCTION, which is a
16662 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
16663 not touch the return address. Hence returning from FUNCTION will
16664 return to whoever called the current `thunk'.
16666 The effect must be as if FUNCTION had been called directly with the
16667 adjusted first argument. This macro is responsible for emitting
16668 all of the code for a thunk function; output_function_prologue()
16669 and output_function_epilogue() are not invoked.
16671 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
16672 been extracted from it.) It might possibly be useful on some
16673 targets, but probably not.
16675 If you do not define this macro, the target-independent code in the
16676 C++ frontend will generate a less efficient heavyweight thunk that
16677 calls FUNCTION instead of jumping to it. The generic approach does
16678 not support varargs. */
16681 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
16682 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
16685 rtx
this, insn
, funexp
;
16687 reload_completed
= 1;
16688 epilogue_completed
= 1;
16690 /* Mark the end of the (empty) prologue. */
16691 emit_note (NOTE_INSN_PROLOGUE_END
);
16693 /* Find the "this" pointer. If the function returns a structure,
16694 the structure return pointer is in r3. */
16695 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
16696 this = gen_rtx_REG (Pmode
, 4);
16698 this = gen_rtx_REG (Pmode
, 3);
16700 /* Apply the constant offset, if required. */
16703 rtx delta_rtx
= GEN_INT (delta
);
16704 emit_insn (TARGET_32BIT
16705 ? gen_addsi3 (this, this, delta_rtx
)
16706 : gen_adddi3 (this, this, delta_rtx
));
16709 /* Apply the offset from the vtable, if required. */
16712 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
16713 rtx tmp
= gen_rtx_REG (Pmode
, 12);
16715 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
16716 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
16718 emit_insn (TARGET_32BIT
16719 ? gen_addsi3 (tmp
, tmp
, vcall_offset_rtx
)
16720 : gen_adddi3 (tmp
, tmp
, vcall_offset_rtx
));
16721 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
16725 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
16727 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
16729 emit_insn (TARGET_32BIT
16730 ? gen_addsi3 (this, this, tmp
)
16731 : gen_adddi3 (this, this, tmp
));
16734 /* Generate a tail call to the target function. */
16735 if (!TREE_USED (function
))
16737 assemble_external (function
);
16738 TREE_USED (function
) = 1;
16740 funexp
= XEXP (DECL_RTL (function
), 0);
16741 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
16744 if (MACHOPIC_INDIRECT
)
16745 funexp
= machopic_indirect_call_target (funexp
);
16748 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
16749 generate sibcall RTL explicitly. */
16750 insn
= emit_call_insn (
16751 gen_rtx_PARALLEL (VOIDmode
,
16753 gen_rtx_CALL (VOIDmode
,
16754 funexp
, const0_rtx
),
16755 gen_rtx_USE (VOIDmode
, const0_rtx
),
16756 gen_rtx_USE (VOIDmode
,
16757 gen_rtx_REG (SImode
,
16759 gen_rtx_RETURN (VOIDmode
))));
16760 SIBLING_CALL_P (insn
) = 1;
16763 /* Run just enough of rest_of_compilation to get the insns emitted.
16764 There's not really enough bulk here to make other passes such as
16765 instruction scheduling worth while. Note that use_thunk calls
16766 assemble_start_function and assemble_end_function. */
16767 insn
= get_insns ();
16768 insn_locators_alloc ();
16769 shorten_branches (insn
);
16770 final_start_function (insn
, file
, 1);
16771 final (insn
, file
, 1);
16772 final_end_function ();
16774 reload_completed
= 0;
16775 epilogue_completed
= 0;
16778 /* A quick summary of the various types of 'constant-pool tables'
16781 Target Flags Name One table per
16782 AIX (none) AIX TOC object file
16783 AIX -mfull-toc AIX TOC object file
16784 AIX -mminimal-toc AIX minimal TOC translation unit
16785 SVR4/EABI (none) SVR4 SDATA object file
16786 SVR4/EABI -fpic SVR4 pic object file
16787 SVR4/EABI -fPIC SVR4 PIC translation unit
16788 SVR4/EABI -mrelocatable EABI TOC function
16789 SVR4/EABI -maix AIX TOC object file
16790 SVR4/EABI -maix -mminimal-toc
16791 AIX minimal TOC translation unit
16793 Name Reg. Set by entries contains:
16794 made by addrs? fp? sum?
16796 AIX TOC 2 crt0 as Y option option
16797 AIX minimal TOC 30 prolog gcc Y Y option
16798 SVR4 SDATA 13 crt0 gcc N Y N
16799 SVR4 pic 30 prolog ld Y not yet N
16800 SVR4 PIC 30 prolog gcc Y option option
16801 EABI TOC 30 prolog gcc Y option option
16805 /* Hash functions for the hash table. */
16808 rs6000_hash_constant (rtx k
)
16810 enum rtx_code code
= GET_CODE (k
);
16811 enum machine_mode mode
= GET_MODE (k
);
16812 unsigned result
= (code
<< 3) ^ mode
;
16813 const char *format
;
16816 format
= GET_RTX_FORMAT (code
);
16817 flen
= strlen (format
);
16823 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
16826 if (mode
!= VOIDmode
)
16827 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
16839 for (; fidx
< flen
; fidx
++)
16840 switch (format
[fidx
])
16845 const char *str
= XSTR (k
, fidx
);
16846 len
= strlen (str
);
16847 result
= result
* 613 + len
;
16848 for (i
= 0; i
< len
; i
++)
16849 result
= result
* 613 + (unsigned) str
[i
];
16854 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
16858 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
16861 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
16862 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
16866 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
16867 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
16874 gcc_unreachable ();
16881 toc_hash_function (const void *hash_entry
)
16883 const struct toc_hash_struct
*thc
=
16884 (const struct toc_hash_struct
*) hash_entry
;
16885 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
16888 /* Compare H1 and H2 for equivalence. */
16891 toc_hash_eq (const void *h1
, const void *h2
)
16893 rtx r1
= ((const struct toc_hash_struct
*) h1
)->key
;
16894 rtx r2
= ((const struct toc_hash_struct
*) h2
)->key
;
16896 if (((const struct toc_hash_struct
*) h1
)->key_mode
16897 != ((const struct toc_hash_struct
*) h2
)->key_mode
)
16900 return rtx_equal_p (r1
, r2
);
16903 /* These are the names given by the C++ front-end to vtables, and
16904 vtable-like objects. Ideally, this logic should not be here;
16905 instead, there should be some programmatic way of inquiring as
16906 to whether or not an object is a vtable. */
16908 #define VTABLE_NAME_P(NAME) \
16909 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
16910 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
16911 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
16912 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
16913 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
16916 rs6000_output_symbol_ref (FILE *file
, rtx x
)
16918 /* Currently C++ toc references to vtables can be emitted before it
16919 is decided whether the vtable is public or private. If this is
16920 the case, then the linker will eventually complain that there is
16921 a reference to an unknown section. Thus, for vtables only,
16922 we emit the TOC reference to reference the symbol and not the
16924 const char *name
= XSTR (x
, 0);
16926 if (VTABLE_NAME_P (name
))
16928 RS6000_OUTPUT_BASENAME (file
, name
);
16931 assemble_name (file
, name
);
16934 /* Output a TOC entry. We derive the entry name from what is being
16938 output_toc (FILE *file
, rtx x
, int labelno
, enum machine_mode mode
)
16941 const char *name
= buf
;
16942 const char *real_name
;
16944 HOST_WIDE_INT offset
= 0;
16946 gcc_assert (!TARGET_NO_TOC
);
16948 /* When the linker won't eliminate them, don't output duplicate
16949 TOC entries (this happens on AIX if there is any kind of TOC,
16950 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
16952 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
16954 struct toc_hash_struct
*h
;
16957 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
16958 time because GGC is not initialized at that point. */
16959 if (toc_hash_table
== NULL
)
16960 toc_hash_table
= htab_create_ggc (1021, toc_hash_function
,
16961 toc_hash_eq
, NULL
);
16963 h
= ggc_alloc (sizeof (*h
));
16965 h
->key_mode
= mode
;
16966 h
->labelno
= labelno
;
16968 found
= htab_find_slot (toc_hash_table
, h
, 1);
16969 if (*found
== NULL
)
16971 else /* This is indeed a duplicate.
16972 Set this label equal to that label. */
16974 fputs ("\t.set ", file
);
16975 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
16976 fprintf (file
, "%d,", labelno
);
16977 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
16978 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
16984 /* If we're going to put a double constant in the TOC, make sure it's
16985 aligned properly when strict alignment is on. */
16986 if (GET_CODE (x
) == CONST_DOUBLE
16987 && STRICT_ALIGNMENT
16988 && GET_MODE_BITSIZE (mode
) >= 64
16989 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
16990 ASM_OUTPUT_ALIGN (file
, 3);
16993 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
16995 /* Handle FP constants specially. Note that if we have a minimal
16996 TOC, things we put here aren't actually in the TOC, so we can allow
16998 if (GET_CODE (x
) == CONST_DOUBLE
&&
16999 (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
))
17001 REAL_VALUE_TYPE rv
;
17004 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
17005 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
17006 REAL_VALUE_TO_TARGET_DECIMAL128 (rv
, k
);
17008 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
17012 if (TARGET_MINIMAL_TOC
)
17013 fputs (DOUBLE_INT_ASM_OP
, file
);
17015 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
17016 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
17017 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
17018 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
17019 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
17020 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
17025 if (TARGET_MINIMAL_TOC
)
17026 fputs ("\t.long ", file
);
17028 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
17029 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
17030 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
17031 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
17032 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
17033 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
17037 else if (GET_CODE (x
) == CONST_DOUBLE
&&
17038 (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
17040 REAL_VALUE_TYPE rv
;
17043 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
17045 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
17046 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, k
);
17048 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
17052 if (TARGET_MINIMAL_TOC
)
17053 fputs (DOUBLE_INT_ASM_OP
, file
);
17055 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
17056 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
17057 fprintf (file
, "0x%lx%08lx\n",
17058 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
17063 if (TARGET_MINIMAL_TOC
)
17064 fputs ("\t.long ", file
);
17066 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
17067 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
17068 fprintf (file
, "0x%lx,0x%lx\n",
17069 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
17073 else if (GET_CODE (x
) == CONST_DOUBLE
&&
17074 (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
17076 REAL_VALUE_TYPE rv
;
17079 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
17080 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
17081 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
17083 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
17087 if (TARGET_MINIMAL_TOC
)
17088 fputs (DOUBLE_INT_ASM_OP
, file
);
17090 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
17091 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
17096 if (TARGET_MINIMAL_TOC
)
17097 fputs ("\t.long ", file
);
17099 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
17100 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
17104 else if (GET_MODE (x
) == VOIDmode
17105 && (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
))
17107 unsigned HOST_WIDE_INT low
;
17108 HOST_WIDE_INT high
;
17110 if (GET_CODE (x
) == CONST_DOUBLE
)
17112 low
= CONST_DOUBLE_LOW (x
);
17113 high
= CONST_DOUBLE_HIGH (x
);
17116 #if HOST_BITS_PER_WIDE_INT == 32
17119 high
= (low
& 0x80000000) ? ~0 : 0;
17123 low
= INTVAL (x
) & 0xffffffff;
17124 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
17128 /* TOC entries are always Pmode-sized, but since this
17129 is a bigendian machine then if we're putting smaller
17130 integer constants in the TOC we have to pad them.
17131 (This is still a win over putting the constants in
17132 a separate constant pool, because then we'd have
17133 to have both a TOC entry _and_ the actual constant.)
17135 For a 32-bit target, CONST_INT values are loaded and shifted
17136 entirely within `low' and can be stored in one TOC entry. */
17138 /* It would be easy to make this work, but it doesn't now. */
17139 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
17141 if (POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
17143 #if HOST_BITS_PER_WIDE_INT == 32
17144 lshift_double (low
, high
, POINTER_SIZE
- GET_MODE_BITSIZE (mode
),
17145 POINTER_SIZE
, &low
, &high
, 0);
17148 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
17149 high
= (HOST_WIDE_INT
) low
>> 32;
17156 if (TARGET_MINIMAL_TOC
)
17157 fputs (DOUBLE_INT_ASM_OP
, file
);
17159 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
17160 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
17161 fprintf (file
, "0x%lx%08lx\n",
17162 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
17167 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
17169 if (TARGET_MINIMAL_TOC
)
17170 fputs ("\t.long ", file
);
17172 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
17173 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
17174 fprintf (file
, "0x%lx,0x%lx\n",
17175 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
17179 if (TARGET_MINIMAL_TOC
)
17180 fputs ("\t.long ", file
);
17182 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
17183 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
17189 if (GET_CODE (x
) == CONST
)
17191 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
);
17193 base
= XEXP (XEXP (x
, 0), 0);
17194 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
17197 switch (GET_CODE (base
))
17200 name
= XSTR (base
, 0);
17204 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
17205 CODE_LABEL_NUMBER (XEXP (base
, 0)));
17209 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
17213 gcc_unreachable ();
17216 real_name
= (*targetm
.strip_name_encoding
) (name
);
17217 if (TARGET_MINIMAL_TOC
)
17218 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
17221 fprintf (file
, "\t.tc %s", real_name
);
17224 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
17226 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
17228 fputs ("[TC],", file
);
17231 /* Currently C++ toc references to vtables can be emitted before it
17232 is decided whether the vtable is public or private. If this is
17233 the case, then the linker will eventually complain that there is
17234 a TOC reference to an unknown section. Thus, for vtables only,
17235 we emit the TOC reference to reference the symbol and not the
17237 if (VTABLE_NAME_P (name
))
17239 RS6000_OUTPUT_BASENAME (file
, name
);
17241 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
17242 else if (offset
> 0)
17243 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
17246 output_addr_const (file
, x
);
17250 /* Output an assembler pseudo-op to write an ASCII string of N characters
17251 starting at P to FILE.
17253 On the RS/6000, we have to do this using the .byte operation and
17254 write out special characters outside the quoted string.
17255 Also, the assembler is broken; very long strings are truncated,
17256 so we must artificially break them up early. */
17259 output_ascii (FILE *file
, const char *p
, int n
)
17262 int i
, count_string
;
17263 const char *for_string
= "\t.byte \"";
17264 const char *for_decimal
= "\t.byte ";
17265 const char *to_close
= NULL
;
17268 for (i
= 0; i
< n
; i
++)
17271 if (c
>= ' ' && c
< 0177)
17274 fputs (for_string
, file
);
17277 /* Write two quotes to get one. */
17285 for_decimal
= "\"\n\t.byte ";
17289 if (count_string
>= 512)
17291 fputs (to_close
, file
);
17293 for_string
= "\t.byte \"";
17294 for_decimal
= "\t.byte ";
17302 fputs (for_decimal
, file
);
17303 fprintf (file
, "%d", c
);
17305 for_string
= "\n\t.byte \"";
17306 for_decimal
= ", ";
17312 /* Now close the string if we have written one. Then end the line. */
17314 fputs (to_close
, file
);
17317 /* Generate a unique section name for FILENAME for a section type
17318 represented by SECTION_DESC. Output goes into BUF.
17320 SECTION_DESC can be any string, as long as it is different for each
17321 possible section type.
17323 We name the section in the same manner as xlc. The name begins with an
17324 underscore followed by the filename (after stripping any leading directory
17325 names) with the last period replaced by the string SECTION_DESC. If
17326 FILENAME does not contain a period, SECTION_DESC is appended to the end of
17330 rs6000_gen_section_name (char **buf
, const char *filename
,
17331 const char *section_desc
)
17333 const char *q
, *after_last_slash
, *last_period
= 0;
17337 after_last_slash
= filename
;
17338 for (q
= filename
; *q
; q
++)
17341 after_last_slash
= q
+ 1;
17342 else if (*q
== '.')
17346 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
17347 *buf
= (char *) xmalloc (len
);
17352 for (q
= after_last_slash
; *q
; q
++)
17354 if (q
== last_period
)
17356 strcpy (p
, section_desc
);
17357 p
+= strlen (section_desc
);
17361 else if (ISALNUM (*q
))
17365 if (last_period
== 0)
17366 strcpy (p
, section_desc
);
17371 /* Emit profile function. */
17374 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
17376 /* Non-standard profiling for kernels, which just saves LR then calls
17377 _mcount without worrying about arg saves. The idea is to change
17378 the function prologue as little as possible as it isn't easy to
17379 account for arg save/restore code added just for _mcount. */
17380 if (TARGET_PROFILE_KERNEL
)
17383 if (DEFAULT_ABI
== ABI_AIX
)
17385 #ifndef NO_PROFILE_COUNTERS
17386 # define NO_PROFILE_COUNTERS 0
17388 if (NO_PROFILE_COUNTERS
)
17389 emit_library_call (init_one_libfunc (RS6000_MCOUNT
), 0, VOIDmode
, 0);
17393 const char *label_name
;
17396 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
17397 label_name
= (*targetm
.strip_name_encoding
) (ggc_strdup (buf
));
17398 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
17400 emit_library_call (init_one_libfunc (RS6000_MCOUNT
), 0, VOIDmode
, 1,
17404 else if (DEFAULT_ABI
== ABI_DARWIN
)
17406 const char *mcount_name
= RS6000_MCOUNT
;
17407 int caller_addr_regno
= LR_REGNO
;
17409 /* Be conservative and always set this, at least for now. */
17410 current_function_uses_pic_offset_table
= 1;
17413 /* For PIC code, set up a stub and collect the caller's address
17414 from r0, which is where the prologue puts it. */
17415 if (MACHOPIC_INDIRECT
17416 && current_function_uses_pic_offset_table
)
17417 caller_addr_regno
= 0;
17419 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
17421 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
17425 /* Write function profiler code. */
17428 output_function_profiler (FILE *file
, int labelno
)
17432 switch (DEFAULT_ABI
)
17435 gcc_unreachable ();
17440 warning (0, "no profiling of 64-bit code for this ABI");
17443 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
17444 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
17445 if (NO_PROFILE_COUNTERS
)
17447 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
17448 reg_names
[0], reg_names
[1]);
17450 else if (TARGET_SECURE_PLT
&& flag_pic
)
17452 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
17453 reg_names
[0], reg_names
[1]);
17454 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
17455 asm_fprintf (file
, "\t{cau|addis} %s,%s,",
17456 reg_names
[12], reg_names
[12]);
17457 assemble_name (file
, buf
);
17458 asm_fprintf (file
, "-1b@ha\n\t{cal|la} %s,", reg_names
[0]);
17459 assemble_name (file
, buf
);
17460 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
17462 else if (flag_pic
== 1)
17464 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
17465 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
17466 reg_names
[0], reg_names
[1]);
17467 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
17468 asm_fprintf (file
, "\t{l|lwz} %s,", reg_names
[0]);
17469 assemble_name (file
, buf
);
17470 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
17472 else if (flag_pic
> 1)
17474 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
17475 reg_names
[0], reg_names
[1]);
17476 /* Now, we need to get the address of the label. */
17477 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
17478 assemble_name (file
, buf
);
17479 fputs ("-.\n1:", file
);
17480 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
17481 asm_fprintf (file
, "\t{l|lwz} %s,0(%s)\n",
17482 reg_names
[0], reg_names
[11]);
17483 asm_fprintf (file
, "\t{cax|add} %s,%s,%s\n",
17484 reg_names
[0], reg_names
[0], reg_names
[11]);
17488 asm_fprintf (file
, "\t{liu|lis} %s,", reg_names
[12]);
17489 assemble_name (file
, buf
);
17490 fputs ("@ha\n", file
);
17491 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
17492 reg_names
[0], reg_names
[1]);
17493 asm_fprintf (file
, "\t{cal|la} %s,", reg_names
[0]);
17494 assemble_name (file
, buf
);
17495 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
17498 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
17499 fprintf (file
, "\tbl %s%s\n",
17500 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
17505 if (!TARGET_PROFILE_KERNEL
)
17507 /* Don't do anything, done in output_profile_hook (). */
17511 gcc_assert (!TARGET_32BIT
);
17513 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
17514 asm_fprintf (file
, "\tstd %s,16(%s)\n", reg_names
[0], reg_names
[1]);
17516 if (cfun
->static_chain_decl
!= NULL
)
17518 asm_fprintf (file
, "\tstd %s,24(%s)\n",
17519 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
17520 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
17521 asm_fprintf (file
, "\tld %s,24(%s)\n",
17522 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
17525 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
17533 /* The following variable value is the last issued insn. */
17535 static rtx last_scheduled_insn
;
17537 /* The following variable helps to balance issuing of load and
17538 store instructions */
17540 static int load_store_pendulum
;
17542 /* Power4 load update and store update instructions are cracked into a
17543 load or store and an integer insn which are executed in the same cycle.
17544 Branches have their own dispatch slot which does not count against the
17545 GCC issue rate, but it changes the program flow so there are no other
17546 instructions to issue in this cycle. */
17549 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED
,
17550 int verbose ATTRIBUTE_UNUSED
,
17551 rtx insn
, int more
)
17553 last_scheduled_insn
= insn
;
17554 if (GET_CODE (PATTERN (insn
)) == USE
17555 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
17557 cached_can_issue_more
= more
;
17558 return cached_can_issue_more
;
17561 if (insn_terminates_group_p (insn
, current_group
))
17563 cached_can_issue_more
= 0;
17564 return cached_can_issue_more
;
17567 /* If no reservation, but reach here */
17568 if (recog_memoized (insn
) < 0)
17571 if (rs6000_sched_groups
)
17573 if (is_microcoded_insn (insn
))
17574 cached_can_issue_more
= 0;
17575 else if (is_cracked_insn (insn
))
17576 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
17578 cached_can_issue_more
= more
- 1;
17580 return cached_can_issue_more
;
17583 if (rs6000_cpu_attr
== CPU_CELL
&& is_nonpipeline_insn (insn
))
17586 cached_can_issue_more
= more
- 1;
17587 return cached_can_issue_more
;
17590 /* Adjust the cost of a scheduling dependency. Return the new cost of
17591 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
17594 rs6000_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
17596 enum attr_type attr_type
;
17598 if (! recog_memoized (insn
))
17601 switch (REG_NOTE_KIND (link
))
17605 /* Data dependency; DEP_INSN writes a register that INSN reads
17606 some cycles later. */
17608 /* Separate a load from a narrower, dependent store. */
17609 if (rs6000_sched_groups
17610 && GET_CODE (PATTERN (insn
)) == SET
17611 && GET_CODE (PATTERN (dep_insn
)) == SET
17612 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
17613 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
17614 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
17615 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
17618 attr_type
= get_attr_type (insn
);
17623 /* Tell the first scheduling pass about the latency between
17624 a mtctr and bctr (and mtlr and br/blr). The first
17625 scheduling pass will not know about this latency since
17626 the mtctr instruction, which has the latency associated
17627 to it, will be generated by reload. */
17628 return TARGET_POWER
? 5 : 4;
17630 /* Leave some extra cycles between a compare and its
17631 dependent branch, to inhibit expensive mispredicts. */
17632 if ((rs6000_cpu_attr
== CPU_PPC603
17633 || rs6000_cpu_attr
== CPU_PPC604
17634 || rs6000_cpu_attr
== CPU_PPC604E
17635 || rs6000_cpu_attr
== CPU_PPC620
17636 || rs6000_cpu_attr
== CPU_PPC630
17637 || rs6000_cpu_attr
== CPU_PPC750
17638 || rs6000_cpu_attr
== CPU_PPC7400
17639 || rs6000_cpu_attr
== CPU_PPC7450
17640 || rs6000_cpu_attr
== CPU_POWER4
17641 || rs6000_cpu_attr
== CPU_POWER5
17642 || rs6000_cpu_attr
== CPU_CELL
)
17643 && recog_memoized (dep_insn
)
17644 && (INSN_CODE (dep_insn
) >= 0))
17646 switch (get_attr_type (dep_insn
))
17650 case TYPE_DELAYED_COMPARE
:
17651 case TYPE_IMUL_COMPARE
:
17652 case TYPE_LMUL_COMPARE
:
17653 case TYPE_FPCOMPARE
:
17654 case TYPE_CR_LOGICAL
:
17655 case TYPE_DELAYED_CR
:
17664 case TYPE_STORE_UX
:
17666 case TYPE_FPSTORE_U
:
17667 case TYPE_FPSTORE_UX
:
17668 if ((rs6000_cpu
== PROCESSOR_POWER6
)
17669 && recog_memoized (dep_insn
)
17670 && (INSN_CODE (dep_insn
) >= 0))
17673 if (GET_CODE (PATTERN (insn
)) != SET
)
17674 /* If this happens, we have to extend this to schedule
17675 optimally. Return default for now. */
17678 /* Adjust the cost for the case where the value written
17679 by a fixed point operation is used as the address
17680 gen value on a store. */
17681 switch (get_attr_type (dep_insn
))
17688 if (! store_data_bypass_p (dep_insn
, insn
))
17692 case TYPE_LOAD_EXT
:
17693 case TYPE_LOAD_EXT_U
:
17694 case TYPE_LOAD_EXT_UX
:
17695 case TYPE_VAR_SHIFT_ROTATE
:
17696 case TYPE_VAR_DELAYED_COMPARE
:
17698 if (! store_data_bypass_p (dep_insn
, insn
))
17704 case TYPE_FAST_COMPARE
:
17707 case TYPE_INSERT_WORD
:
17708 case TYPE_INSERT_DWORD
:
17709 case TYPE_FPLOAD_U
:
17710 case TYPE_FPLOAD_UX
:
17712 case TYPE_STORE_UX
:
17713 case TYPE_FPSTORE_U
:
17714 case TYPE_FPSTORE_UX
:
17716 if (! store_data_bypass_p (dep_insn
, insn
))
17724 case TYPE_IMUL_COMPARE
:
17725 case TYPE_LMUL_COMPARE
:
17727 if (! store_data_bypass_p (dep_insn
, insn
))
17733 if (! store_data_bypass_p (dep_insn
, insn
))
17739 if (! store_data_bypass_p (dep_insn
, insn
))
17752 case TYPE_LOAD_EXT
:
17753 case TYPE_LOAD_EXT_U
:
17754 case TYPE_LOAD_EXT_UX
:
17755 if ((rs6000_cpu
== PROCESSOR_POWER6
)
17756 && recog_memoized (dep_insn
)
17757 && (INSN_CODE (dep_insn
) >= 0))
17760 /* Adjust the cost for the case where the value written
17761 by a fixed point instruction is used within the address
17762 gen portion of a subsequent load(u)(x) */
17763 switch (get_attr_type (dep_insn
))
17770 if (set_to_load_agen (dep_insn
, insn
))
17774 case TYPE_LOAD_EXT
:
17775 case TYPE_LOAD_EXT_U
:
17776 case TYPE_LOAD_EXT_UX
:
17777 case TYPE_VAR_SHIFT_ROTATE
:
17778 case TYPE_VAR_DELAYED_COMPARE
:
17780 if (set_to_load_agen (dep_insn
, insn
))
17786 case TYPE_FAST_COMPARE
:
17789 case TYPE_INSERT_WORD
:
17790 case TYPE_INSERT_DWORD
:
17791 case TYPE_FPLOAD_U
:
17792 case TYPE_FPLOAD_UX
:
17794 case TYPE_STORE_UX
:
17795 case TYPE_FPSTORE_U
:
17796 case TYPE_FPSTORE_UX
:
17798 if (set_to_load_agen (dep_insn
, insn
))
17806 case TYPE_IMUL_COMPARE
:
17807 case TYPE_LMUL_COMPARE
:
17809 if (set_to_load_agen (dep_insn
, insn
))
17815 if (set_to_load_agen (dep_insn
, insn
))
17821 if (set_to_load_agen (dep_insn
, insn
))
17832 if ((rs6000_cpu
== PROCESSOR_POWER6
)
17833 && recog_memoized (dep_insn
)
17834 && (INSN_CODE (dep_insn
) >= 0)
17835 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
17842 /* Fall out to return default cost. */
17846 case REG_DEP_OUTPUT
:
17847 /* Output dependency; DEP_INSN writes a register that INSN writes some
17849 if ((rs6000_cpu
== PROCESSOR_POWER6
)
17850 && recog_memoized (dep_insn
)
17851 && (INSN_CODE (dep_insn
) >= 0))
17853 attr_type
= get_attr_type (insn
);
17858 if (get_attr_type (dep_insn
) == TYPE_FP
)
17862 if (get_attr_type (dep_insn
) == TYPE_MFFGPR
)
17870 /* Anti dependency; DEP_INSN reads a register that INSN writes some
17875 gcc_unreachable ();
17881 /* The function returns a true if INSN is microcoded.
17882 Return false otherwise. */
17885 is_microcoded_insn (rtx insn
)
17887 if (!insn
|| !INSN_P (insn
)
17888 || GET_CODE (PATTERN (insn
)) == USE
17889 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
17892 if (rs6000_cpu_attr
== CPU_CELL
)
17893 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
17895 if (rs6000_sched_groups
)
17897 enum attr_type type
= get_attr_type (insn
);
17898 if (type
== TYPE_LOAD_EXT_U
17899 || type
== TYPE_LOAD_EXT_UX
17900 || type
== TYPE_LOAD_UX
17901 || type
== TYPE_STORE_UX
17902 || type
== TYPE_MFCR
)
17909 /* The function returns true if INSN is cracked into 2 instructions
17910 by the processor (and therefore occupies 2 issue slots). */
17913 is_cracked_insn (rtx insn
)
17915 if (!insn
|| !INSN_P (insn
)
17916 || GET_CODE (PATTERN (insn
)) == USE
17917 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
17920 if (rs6000_sched_groups
)
17922 enum attr_type type
= get_attr_type (insn
);
17923 if (type
== TYPE_LOAD_U
|| type
== TYPE_STORE_U
17924 || type
== TYPE_FPLOAD_U
|| type
== TYPE_FPSTORE_U
17925 || type
== TYPE_FPLOAD_UX
|| type
== TYPE_FPSTORE_UX
17926 || type
== TYPE_LOAD_EXT
|| type
== TYPE_DELAYED_CR
17927 || type
== TYPE_COMPARE
|| type
== TYPE_DELAYED_COMPARE
17928 || type
== TYPE_IMUL_COMPARE
|| type
== TYPE_LMUL_COMPARE
17929 || type
== TYPE_IDIV
|| type
== TYPE_LDIV
17930 || type
== TYPE_INSERT_WORD
)
17937 /* The function returns true if INSN can be issued only from
17938 the branch slot. */
17941 is_branch_slot_insn (rtx insn
)
17943 if (!insn
|| !INSN_P (insn
)
17944 || GET_CODE (PATTERN (insn
)) == USE
17945 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
17948 if (rs6000_sched_groups
)
17950 enum attr_type type
= get_attr_type (insn
);
17951 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
17959 /* The function returns true if out_inst sets a value that is
17960 used in the address generation computation of in_insn */
17962 set_to_load_agen (rtx out_insn
, rtx in_insn
)
17964 rtx out_set
, in_set
;
17966 /* For performance reasons, only handle the simple case where
17967 both loads are a single_set. */
17968 out_set
= single_set (out_insn
);
17971 in_set
= single_set (in_insn
);
17973 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
17979 /* The function returns true if the target storage location of
17980 out_insn is adjacent to the target storage location of in_insn */
17981 /* Return 1 if memory locations are adjacent. */
17984 adjacent_mem_locations (rtx insn1
, rtx insn2
)
17987 rtx a
= get_store_dest (PATTERN (insn1
));
17988 rtx b
= get_store_dest (PATTERN (insn2
));
17990 if ((GET_CODE (XEXP (a
, 0)) == REG
17991 || (GET_CODE (XEXP (a
, 0)) == PLUS
17992 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
17993 && (GET_CODE (XEXP (b
, 0)) == REG
17994 || (GET_CODE (XEXP (b
, 0)) == PLUS
17995 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
17997 HOST_WIDE_INT val0
= 0, val1
= 0;
18001 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
18003 reg0
= XEXP (XEXP (a
, 0), 0);
18004 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
18007 reg0
= XEXP (a
, 0);
18009 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
18011 reg1
= XEXP (XEXP (b
, 0), 0);
18012 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
18015 reg1
= XEXP (b
, 0);
18017 val_diff
= val1
- val0
;
18019 return ((REGNO (reg0
) == REGNO (reg1
))
18020 && (val_diff
== INTVAL (MEM_SIZE (a
))
18021 || val_diff
== -INTVAL (MEM_SIZE (b
))));
18027 /* A C statement (sans semicolon) to update the integer scheduling
18028 priority INSN_PRIORITY (INSN). Increase the priority to execute the
18029 INSN earlier, reduce the priority to execute INSN later. Do not
18030 define this macro if you do not need to adjust the scheduling
18031 priorities of insns. */
18034 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
18036 /* On machines (like the 750) which have asymmetric integer units,
18037 where one integer unit can do multiply and divides and the other
18038 can't, reduce the priority of multiply/divide so it is scheduled
18039 before other integer operations. */
18042 if (! INSN_P (insn
))
18045 if (GET_CODE (PATTERN (insn
)) == USE
)
18048 switch (rs6000_cpu_attr
) {
18050 switch (get_attr_type (insn
))
18057 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
18058 priority
, priority
);
18059 if (priority
>= 0 && priority
< 0x01000000)
18066 if (insn_must_be_first_in_group (insn
)
18067 && reload_completed
18068 && current_sched_info
->sched_max_insns_priority
18069 && rs6000_sched_restricted_insns_priority
)
18072 /* Prioritize insns that can be dispatched only in the first
18074 if (rs6000_sched_restricted_insns_priority
== 1)
18075 /* Attach highest priority to insn. This means that in
18076 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
18077 precede 'priority' (critical path) considerations. */
18078 return current_sched_info
->sched_max_insns_priority
;
18079 else if (rs6000_sched_restricted_insns_priority
== 2)
18080 /* Increase priority of insn by a minimal amount. This means that in
18081 haifa-sched.c:ready_sort(), only 'priority' (critical path)
18082 considerations precede dispatch-slot restriction considerations. */
18083 return (priority
+ 1);
18086 if (rs6000_cpu
== PROCESSOR_POWER6
18087 && ((load_store_pendulum
== -2 && is_load_insn (insn
))
18088 || (load_store_pendulum
== 2 && is_store_insn (insn
))))
18089 /* Attach highest priority to insn if the scheduler has just issued two
18090 stores and this instruction is a load, or two loads and this instruction
18091 is a store. Power6 wants loads and stores scheduled alternately
18093 return current_sched_info
->sched_max_insns_priority
;
18098 /* Return true if the instruction is nonpipelined on the Cell. */
18100 is_nonpipeline_insn (rtx insn
)
18102 enum attr_type type
;
18103 if (!insn
|| !INSN_P (insn
)
18104 || GET_CODE (PATTERN (insn
)) == USE
18105 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
18108 type
= get_attr_type (insn
);
18109 if (type
== TYPE_IMUL
18110 || type
== TYPE_IMUL2
18111 || type
== TYPE_IMUL3
18112 || type
== TYPE_LMUL
18113 || type
== TYPE_IDIV
18114 || type
== TYPE_LDIV
18115 || type
== TYPE_SDIV
18116 || type
== TYPE_DDIV
18117 || type
== TYPE_SSQRT
18118 || type
== TYPE_DSQRT
18119 || type
== TYPE_MFCR
18120 || type
== TYPE_MFCRF
18121 || type
== TYPE_MFJMPR
)
18129 /* Return how many instructions the machine can issue per cycle. */
18132 rs6000_issue_rate (void)
18134 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
18135 if (!reload_completed
)
18138 switch (rs6000_cpu_attr
) {
18139 case CPU_RIOS1
: /* ? */
18141 case CPU_PPC601
: /* ? */
18166 /* Return how many instructions to look ahead for better insn
18170 rs6000_use_sched_lookahead (void)
18172 if (rs6000_cpu_attr
== CPU_PPC8540
)
18174 if (rs6000_cpu_attr
== CPU_CELL
)
18175 return (reload_completed
? 8 : 0);
18179 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
18181 rs6000_use_sched_lookahead_guard (rtx insn
)
18183 if (rs6000_cpu_attr
!= CPU_CELL
)
18186 if (insn
== NULL_RTX
|| !INSN_P (insn
))
18189 if (!reload_completed
18190 || is_nonpipeline_insn (insn
)
18191 || is_microcoded_insn (insn
))
18197 /* Determine is PAT refers to memory. */
18200 is_mem_ref (rtx pat
)
18206 if (GET_CODE (pat
) == MEM
)
18209 /* Recursively process the pattern. */
18210 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
18212 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0 && !ret
; i
--)
18215 ret
|= is_mem_ref (XEXP (pat
, i
));
18216 else if (fmt
[i
] == 'E')
18217 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
18218 ret
|= is_mem_ref (XVECEXP (pat
, i
, j
));
18224 /* Determine if PAT is a PATTERN of a load insn. */
18227 is_load_insn1 (rtx pat
)
18229 if (!pat
|| pat
== NULL_RTX
)
18232 if (GET_CODE (pat
) == SET
)
18233 return is_mem_ref (SET_SRC (pat
));
18235 if (GET_CODE (pat
) == PARALLEL
)
18239 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
18240 if (is_load_insn1 (XVECEXP (pat
, 0, i
)))
18247 /* Determine if INSN loads from memory. */
18250 is_load_insn (rtx insn
)
18252 if (!insn
|| !INSN_P (insn
))
18255 if (GET_CODE (insn
) == CALL_INSN
)
18258 return is_load_insn1 (PATTERN (insn
));
18261 /* Determine if PAT is a PATTERN of a store insn. */
18264 is_store_insn1 (rtx pat
)
18266 if (!pat
|| pat
== NULL_RTX
)
18269 if (GET_CODE (pat
) == SET
)
18270 return is_mem_ref (SET_DEST (pat
));
18272 if (GET_CODE (pat
) == PARALLEL
)
18276 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
18277 if (is_store_insn1 (XVECEXP (pat
, 0, i
)))
18284 /* Determine if INSN stores to memory. */
18287 is_store_insn (rtx insn
)
18289 if (!insn
|| !INSN_P (insn
))
18292 return is_store_insn1 (PATTERN (insn
));
18295 /* Return the dest of a store insn. */
18298 get_store_dest (rtx pat
)
18300 gcc_assert (is_store_insn1 (pat
));
18302 if (GET_CODE (pat
) == SET
)
18303 return SET_DEST (pat
);
18304 else if (GET_CODE (pat
) == PARALLEL
)
18308 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
18310 rtx inner_pat
= XVECEXP (pat
, 0, i
);
18311 if (GET_CODE (inner_pat
) == SET
18312 && is_mem_ref (SET_DEST (inner_pat
)))
18316 /* We shouldn't get here, because we should have either a simple
18317 store insn or a store with update which are covered above. */
18321 /* Returns whether the dependence between INSN and NEXT is considered
18322 costly by the given target. */
18325 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
18330 /* If the flag is not enabled - no dependence is considered costly;
18331 allow all dependent insns in the same group.
18332 This is the most aggressive option. */
18333 if (rs6000_sched_costly_dep
== no_dep_costly
)
18336 /* If the flag is set to 1 - a dependence is always considered costly;
18337 do not allow dependent instructions in the same group.
18338 This is the most conservative option. */
18339 if (rs6000_sched_costly_dep
== all_deps_costly
)
18342 insn
= DEP_PRO (dep
);
18343 next
= DEP_CON (dep
);
18345 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
18346 && is_load_insn (next
)
18347 && is_store_insn (insn
))
18348 /* Prevent load after store in the same group. */
18351 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
18352 && is_load_insn (next
)
18353 && is_store_insn (insn
)
18354 && DEP_TYPE (dep
) == REG_DEP_TRUE
)
18355 /* Prevent load after store in the same group if it is a true
18359 /* The flag is set to X; dependences with latency >= X are considered costly,
18360 and will not be scheduled in the same group. */
18361 if (rs6000_sched_costly_dep
<= max_dep_latency
18362 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
18368 /* Return the next insn after INSN that is found before TAIL is reached,
18369 skipping any "non-active" insns - insns that will not actually occupy
18370 an issue slot. Return NULL_RTX if such an insn is not found. */
18373 get_next_active_insn (rtx insn
, rtx tail
)
18375 if (insn
== NULL_RTX
|| insn
== tail
)
18380 insn
= NEXT_INSN (insn
);
18381 if (insn
== NULL_RTX
|| insn
== tail
)
18386 || (NONJUMP_INSN_P (insn
)
18387 && GET_CODE (PATTERN (insn
)) != USE
18388 && GET_CODE (PATTERN (insn
)) != CLOBBER
18389 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
18395 /* We are about to begin issuing insns for this clock cycle. */
18398 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
18399 rtx
*ready ATTRIBUTE_UNUSED
,
18400 int *pn_ready ATTRIBUTE_UNUSED
,
18401 int clock_var ATTRIBUTE_UNUSED
)
18403 int n_ready
= *pn_ready
;
18406 fprintf (dump
, "// rs6000_sched_reorder :\n");
18408 /* Reorder the ready list, if the second to last ready insn
18409 is a nonepipeline insn. */
18410 if (rs6000_cpu_attr
== CPU_CELL
&& n_ready
> 1)
18412 if (is_nonpipeline_insn (ready
[n_ready
- 1])
18413 && (recog_memoized (ready
[n_ready
- 2]) > 0))
18414 /* Simply swap first two insns. */
18416 rtx tmp
= ready
[n_ready
- 1];
18417 ready
[n_ready
- 1] = ready
[n_ready
- 2];
18418 ready
[n_ready
- 2] = tmp
;
18422 if (rs6000_cpu
== PROCESSOR_POWER6
)
18423 load_store_pendulum
= 0;
18425 return rs6000_issue_rate ();
18428 /* Like rs6000_sched_reorder, but called after issuing each insn. */
18431 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx
*ready
,
18432 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
18435 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
18437 /* For Power6, we need to handle some special cases to try and keep the
18438 store queue from overflowing and triggering expensive flushes.
18440 This code monitors how load and store instructions are being issued
18441 and skews the ready list one way or the other to increase the likelihood
18442 that a desired instruction is issued at the proper time.
18444 A couple of things are done. First, we maintain a "load_store_pendulum"
18445 to track the current state of load/store issue.
18447 - If the pendulum is at zero, then no loads or stores have been
18448 issued in the current cycle so we do nothing.
18450 - If the pendulum is 1, then a single load has been issued in this
18451 cycle and we attempt to locate another load in the ready list to
18454 - If the pendulum is -2, then two stores have already been
18455 issued in this cycle, so we increase the priority of the first load
18456 in the ready list to increase it's likelihood of being chosen first
18459 - If the pendulum is -1, then a single store has been issued in this
18460 cycle and we attempt to locate another store in the ready list to
18461 issue with it, preferring a store to an adjacent memory location to
18462 facilitate store pairing in the store queue.
18464 - If the pendulum is 2, then two loads have already been
18465 issued in this cycle, so we increase the priority of the first store
18466 in the ready list to increase it's likelihood of being chosen first
18469 - If the pendulum < -2 or > 2, then do nothing.
18471 Note: This code covers the most common scenarios. There exist non
18472 load/store instructions which make use of the LSU and which
18473 would need to be accounted for to strictly model the behavior
18474 of the machine. Those instructions are currently unaccounted
18475 for to help minimize compile time overhead of this code.
18477 if (rs6000_cpu
== PROCESSOR_POWER6
&& last_scheduled_insn
)
18483 if (is_store_insn (last_scheduled_insn
))
18484 /* Issuing a store, swing the load_store_pendulum to the left */
18485 load_store_pendulum
--;
18486 else if (is_load_insn (last_scheduled_insn
))
18487 /* Issuing a load, swing the load_store_pendulum to the right */
18488 load_store_pendulum
++;
18490 return cached_can_issue_more
;
18492 /* If the pendulum is balanced, or there is only one instruction on
18493 the ready list, then all is well, so return. */
18494 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
18495 return cached_can_issue_more
;
18497 if (load_store_pendulum
== 1)
18499 /* A load has been issued in this cycle. Scan the ready list
18500 for another load to issue with it */
18505 if (is_load_insn (ready
[pos
]))
18507 /* Found a load. Move it to the head of the ready list,
18508 and adjust it's priority so that it is more likely to
18511 for (i
=pos
; i
<*pn_ready
-1; i
++)
18512 ready
[i
] = ready
[i
+ 1];
18513 ready
[*pn_ready
-1] = tmp
;
18514 if INSN_PRIORITY_KNOWN (tmp
)
18515 INSN_PRIORITY (tmp
)++;
18521 else if (load_store_pendulum
== -2)
18523 /* Two stores have been issued in this cycle. Increase the
18524 priority of the first load in the ready list to favor it for
18525 issuing in the next cycle. */
18530 if (is_load_insn (ready
[pos
])
18531 && INSN_PRIORITY_KNOWN (ready
[pos
]))
18533 INSN_PRIORITY (ready
[pos
])++;
18535 /* Adjust the pendulum to account for the fact that a load
18536 was found and increased in priority. This is to prevent
18537 increasing the priority of multiple loads */
18538 load_store_pendulum
--;
18545 else if (load_store_pendulum
== -1)
18547 /* A store has been issued in this cycle. Scan the ready list for
18548 another store to issue with it, preferring a store to an adjacent
18550 int first_store_pos
= -1;
18556 if (is_store_insn (ready
[pos
]))
18558 /* Maintain the index of the first store found on the
18560 if (first_store_pos
== -1)
18561 first_store_pos
= pos
;
18563 if (is_store_insn (last_scheduled_insn
)
18564 && adjacent_mem_locations (last_scheduled_insn
,ready
[pos
]))
18566 /* Found an adjacent store. Move it to the head of the
18567 ready list, and adjust it's priority so that it is
18568 more likely to stay there */
18570 for (i
=pos
; i
<*pn_ready
-1; i
++)
18571 ready
[i
] = ready
[i
+ 1];
18572 ready
[*pn_ready
-1] = tmp
;
18573 if INSN_PRIORITY_KNOWN (tmp
)
18574 INSN_PRIORITY (tmp
)++;
18575 first_store_pos
= -1;
18583 if (first_store_pos
>= 0)
18585 /* An adjacent store wasn't found, but a non-adjacent store was,
18586 so move the non-adjacent store to the front of the ready
18587 list, and adjust its priority so that it is more likely to
18589 tmp
= ready
[first_store_pos
];
18590 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
18591 ready
[i
] = ready
[i
+ 1];
18592 ready
[*pn_ready
-1] = tmp
;
18593 if INSN_PRIORITY_KNOWN (tmp
)
18594 INSN_PRIORITY (tmp
)++;
18597 else if (load_store_pendulum
== 2)
18599 /* Two loads have been issued in this cycle. Increase the priority
18600 of the first store in the ready list to favor it for issuing in
18606 if (is_store_insn (ready
[pos
])
18607 && INSN_PRIORITY_KNOWN (ready
[pos
]))
18609 INSN_PRIORITY (ready
[pos
])++;
18611 /* Adjust the pendulum to account for the fact that a store
18612 was found and increased in priority. This is to prevent
18613 increasing the priority of multiple stores */
18614 load_store_pendulum
++;
18623 return cached_can_issue_more
;
18626 /* Return whether the presence of INSN causes a dispatch group termination
18627 of group WHICH_GROUP.
18629 If WHICH_GROUP == current_group, this function will return true if INSN
18630 causes the termination of the current group (i.e, the dispatch group to
18631 which INSN belongs). This means that INSN will be the last insn in the
18632 group it belongs to.
18634 If WHICH_GROUP == previous_group, this function will return true if INSN
18635 causes the termination of the previous group (i.e, the dispatch group that
18636 precedes the group to which INSN belongs). This means that INSN will be
18637 the first insn in the group it belongs to). */
18640 insn_terminates_group_p (rtx insn
, enum group_termination which_group
)
18647 first
= insn_must_be_first_in_group (insn
);
18648 last
= insn_must_be_last_in_group (insn
);
18653 if (which_group
== current_group
)
18655 else if (which_group
== previous_group
)
18663 insn_must_be_first_in_group (rtx insn
)
18665 enum attr_type type
;
18668 || insn
== NULL_RTX
18669 || GET_CODE (insn
) == NOTE
18670 || GET_CODE (PATTERN (insn
)) == USE
18671 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
18674 switch (rs6000_cpu
)
18676 case PROCESSOR_POWER5
:
18677 if (is_cracked_insn (insn
))
18679 case PROCESSOR_POWER4
:
18680 if (is_microcoded_insn (insn
))
18683 if (!rs6000_sched_groups
)
18686 type
= get_attr_type (insn
);
18693 case TYPE_DELAYED_CR
:
18694 case TYPE_CR_LOGICAL
:
18708 case PROCESSOR_POWER6
:
18709 type
= get_attr_type (insn
);
18713 case TYPE_INSERT_DWORD
:
18717 case TYPE_VAR_SHIFT_ROTATE
:
18724 case TYPE_INSERT_WORD
:
18725 case TYPE_DELAYED_COMPARE
:
18726 case TYPE_IMUL_COMPARE
:
18727 case TYPE_LMUL_COMPARE
:
18728 case TYPE_FPCOMPARE
:
18739 case TYPE_LOAD_EXT_UX
:
18741 case TYPE_STORE_UX
:
18742 case TYPE_FPLOAD_U
:
18743 case TYPE_FPLOAD_UX
:
18744 case TYPE_FPSTORE_U
:
18745 case TYPE_FPSTORE_UX
:
18759 insn_must_be_last_in_group (rtx insn
)
18761 enum attr_type type
;
18764 || insn
== NULL_RTX
18765 || GET_CODE (insn
) == NOTE
18766 || GET_CODE (PATTERN (insn
)) == USE
18767 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
18770 switch (rs6000_cpu
) {
18771 case PROCESSOR_POWER4
:
18772 case PROCESSOR_POWER5
:
18773 if (is_microcoded_insn (insn
))
18776 if (is_branch_slot_insn (insn
))
18780 case PROCESSOR_POWER6
:
18781 type
= get_attr_type (insn
);
18788 case TYPE_VAR_SHIFT_ROTATE
:
18795 case TYPE_DELAYED_COMPARE
:
18796 case TYPE_IMUL_COMPARE
:
18797 case TYPE_LMUL_COMPARE
:
18798 case TYPE_FPCOMPARE
:
18819 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
18820 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
18823 is_costly_group (rtx
*group_insns
, rtx next_insn
)
18826 int issue_rate
= rs6000_issue_rate ();
18828 for (i
= 0; i
< issue_rate
; i
++)
18830 sd_iterator_def sd_it
;
18832 rtx insn
= group_insns
[i
];
18837 FOR_EACH_DEP (insn
, SD_LIST_FORW
, sd_it
, dep
)
18839 rtx next
= DEP_CON (dep
);
18841 if (next
== next_insn
18842 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
18850 /* Utility of the function redefine_groups.
18851 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
18852 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
18853 to keep it "far" (in a separate group) from GROUP_INSNS, following
18854 one of the following schemes, depending on the value of the flag
18855 -minsert_sched_nops = X:
18856 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
18857 in order to force NEXT_INSN into a separate group.
18858 (2) X < sched_finish_regroup_exact: insert exactly X nops.
18859 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
18860 insertion (has a group just ended, how many vacant issue slots remain in the
18861 last group, and how many dispatch groups were encountered so far). */
18864 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
18865 rtx next_insn
, bool *group_end
, int can_issue_more
,
18870 int issue_rate
= rs6000_issue_rate ();
18871 bool end
= *group_end
;
18874 if (next_insn
== NULL_RTX
)
18875 return can_issue_more
;
18877 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
18878 return can_issue_more
;
18880 force
= is_costly_group (group_insns
, next_insn
);
18882 return can_issue_more
;
18884 if (sched_verbose
> 6)
18885 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
18886 *group_count
,can_issue_more
);
18888 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
18891 can_issue_more
= 0;
18893 /* Since only a branch can be issued in the last issue_slot, it is
18894 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
18895 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
18896 in this case the last nop will start a new group and the branch
18897 will be forced to the new group. */
18898 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
18901 while (can_issue_more
> 0)
18904 emit_insn_before (nop
, next_insn
);
18912 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
18914 int n_nops
= rs6000_sched_insert_nops
;
18916 /* Nops can't be issued from the branch slot, so the effective
18917 issue_rate for nops is 'issue_rate - 1'. */
18918 if (can_issue_more
== 0)
18919 can_issue_more
= issue_rate
;
18921 if (can_issue_more
== 0)
18923 can_issue_more
= issue_rate
- 1;
18926 for (i
= 0; i
< issue_rate
; i
++)
18928 group_insns
[i
] = 0;
18935 emit_insn_before (nop
, next_insn
);
18936 if (can_issue_more
== issue_rate
- 1) /* new group begins */
18939 if (can_issue_more
== 0)
18941 can_issue_more
= issue_rate
- 1;
18944 for (i
= 0; i
< issue_rate
; i
++)
18946 group_insns
[i
] = 0;
18952 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
18955 /* Is next_insn going to start a new group? */
18958 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
18959 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
18960 || (can_issue_more
< issue_rate
&&
18961 insn_terminates_group_p (next_insn
, previous_group
)));
18962 if (*group_end
&& end
)
18965 if (sched_verbose
> 6)
18966 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
18967 *group_count
, can_issue_more
);
18968 return can_issue_more
;
18971 return can_issue_more
;
18974 /* This function tries to synch the dispatch groups that the compiler "sees"
18975 with the dispatch groups that the processor dispatcher is expected to
18976 form in practice. It tries to achieve this synchronization by forcing the
18977 estimated processor grouping on the compiler (as opposed to the function
18978 'pad_goups' which tries to force the scheduler's grouping on the processor).
18980 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
18981 examines the (estimated) dispatch groups that will be formed by the processor
18982 dispatcher. It marks these group boundaries to reflect the estimated
18983 processor grouping, overriding the grouping that the scheduler had marked.
18984 Depending on the value of the flag '-minsert-sched-nops' this function can
18985 force certain insns into separate groups or force a certain distance between
18986 them by inserting nops, for example, if there exists a "costly dependence"
18989 The function estimates the group boundaries that the processor will form as
18990 follows: It keeps track of how many vacant issue slots are available after
18991 each insn. A subsequent insn will start a new group if one of the following
18993 - no more vacant issue slots remain in the current dispatch group.
18994 - only the last issue slot, which is the branch slot, is vacant, but the next
18995 insn is not a branch.
18996 - only the last 2 or less issue slots, including the branch slot, are vacant,
18997 which means that a cracked insn (which occupies two issue slots) can't be
18998 issued in this group.
18999 - less than 'issue_rate' slots are vacant, and the next insn always needs to
19000 start a new group. */
19003 redefine_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
19005 rtx insn
, next_insn
;
19007 int can_issue_more
;
19010 int group_count
= 0;
19014 issue_rate
= rs6000_issue_rate ();
19015 group_insns
= alloca (issue_rate
* sizeof (rtx
));
19016 for (i
= 0; i
< issue_rate
; i
++)
19018 group_insns
[i
] = 0;
19020 can_issue_more
= issue_rate
;
19022 insn
= get_next_active_insn (prev_head_insn
, tail
);
19025 while (insn
!= NULL_RTX
)
19027 slot
= (issue_rate
- can_issue_more
);
19028 group_insns
[slot
] = insn
;
19030 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
19031 if (insn_terminates_group_p (insn
, current_group
))
19032 can_issue_more
= 0;
19034 next_insn
= get_next_active_insn (insn
, tail
);
19035 if (next_insn
== NULL_RTX
)
19036 return group_count
+ 1;
19038 /* Is next_insn going to start a new group? */
19040 = (can_issue_more
== 0
19041 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
19042 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
19043 || (can_issue_more
< issue_rate
&&
19044 insn_terminates_group_p (next_insn
, previous_group
)));
19046 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
19047 next_insn
, &group_end
, can_issue_more
,
19053 can_issue_more
= 0;
19054 for (i
= 0; i
< issue_rate
; i
++)
19056 group_insns
[i
] = 0;
19060 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
19061 PUT_MODE (next_insn
, VOIDmode
);
19062 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
19063 PUT_MODE (next_insn
, TImode
);
19066 if (can_issue_more
== 0)
19067 can_issue_more
= issue_rate
;
19070 return group_count
;
19073 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
19074 dispatch group boundaries that the scheduler had marked. Pad with nops
19075 any dispatch groups which have vacant issue slots, in order to force the
19076 scheduler's grouping on the processor dispatcher. The function
19077 returns the number of dispatch groups found. */
19080 pad_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
19082 rtx insn
, next_insn
;
19085 int can_issue_more
;
19087 int group_count
= 0;
19089 /* Initialize issue_rate. */
19090 issue_rate
= rs6000_issue_rate ();
19091 can_issue_more
= issue_rate
;
19093 insn
= get_next_active_insn (prev_head_insn
, tail
);
19094 next_insn
= get_next_active_insn (insn
, tail
);
19096 while (insn
!= NULL_RTX
)
19099 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
19101 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
19103 if (next_insn
== NULL_RTX
)
19108 /* If the scheduler had marked group termination at this location
19109 (between insn and next_indn), and neither insn nor next_insn will
19110 force group termination, pad the group with nops to force group
19113 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
19114 && !insn_terminates_group_p (insn
, current_group
)
19115 && !insn_terminates_group_p (next_insn
, previous_group
))
19117 if (!is_branch_slot_insn (next_insn
))
19120 while (can_issue_more
)
19123 emit_insn_before (nop
, next_insn
);
19128 can_issue_more
= issue_rate
;
19133 next_insn
= get_next_active_insn (insn
, tail
);
19136 return group_count
;
19139 /* We're beginning a new block. Initialize data structures as necessary. */
19142 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
19143 int sched_verbose ATTRIBUTE_UNUSED
,
19144 int max_ready ATTRIBUTE_UNUSED
)
19146 last_scheduled_insn
= NULL_RTX
;
19147 load_store_pendulum
= 0;
19150 /* The following function is called at the end of scheduling BB.
19151 After reload, it inserts nops at insn group bundling. */
19154 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
19159 fprintf (dump
, "=== Finishing schedule.\n");
19161 if (reload_completed
&& rs6000_sched_groups
)
19163 if (rs6000_sched_insert_nops
== sched_finish_none
)
19166 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
19167 n_groups
= pad_groups (dump
, sched_verbose
,
19168 current_sched_info
->prev_head
,
19169 current_sched_info
->next_tail
);
19171 n_groups
= redefine_groups (dump
, sched_verbose
,
19172 current_sched_info
->prev_head
,
19173 current_sched_info
->next_tail
);
19175 if (sched_verbose
>= 6)
19177 fprintf (dump
, "ngroups = %d\n", n_groups
);
19178 print_rtl (dump
, current_sched_info
->prev_head
);
19179 fprintf (dump
, "Done finish_sched\n");
19184 /* Length in units of the trampoline for entering a nested function. */
19187 rs6000_trampoline_size (void)
19191 switch (DEFAULT_ABI
)
19194 gcc_unreachable ();
19197 ret
= (TARGET_32BIT
) ? 12 : 24;
19202 ret
= (TARGET_32BIT
) ? 40 : 48;
19209 /* Emit RTL insns to initialize the variable parts of a trampoline.
19210 FNADDR is an RTX for the address of the function's pure code.
19211 CXT is an RTX for the static chain value for the function. */
19214 rs6000_initialize_trampoline (rtx addr
, rtx fnaddr
, rtx cxt
)
19216 int regsize
= (TARGET_32BIT
) ? 4 : 8;
19217 rtx ctx_reg
= force_reg (Pmode
, cxt
);
19219 switch (DEFAULT_ABI
)
19222 gcc_unreachable ();
19224 /* Macros to shorten the code expansions below. */
19225 #define MEM_DEREF(addr) gen_rtx_MEM (Pmode, memory_address (Pmode, addr))
19226 #define MEM_PLUS(addr,offset) \
19227 gen_rtx_MEM (Pmode, memory_address (Pmode, plus_constant (addr, offset)))
19229 /* Under AIX, just build the 3 word function descriptor */
19232 rtx fn_reg
= gen_reg_rtx (Pmode
);
19233 rtx toc_reg
= gen_reg_rtx (Pmode
);
19234 emit_move_insn (fn_reg
, MEM_DEREF (fnaddr
));
19235 emit_move_insn (toc_reg
, MEM_PLUS (fnaddr
, regsize
));
19236 emit_move_insn (MEM_DEREF (addr
), fn_reg
);
19237 emit_move_insn (MEM_PLUS (addr
, regsize
), toc_reg
);
19238 emit_move_insn (MEM_PLUS (addr
, 2*regsize
), ctx_reg
);
19242 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
19245 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
19246 FALSE
, VOIDmode
, 4,
19248 GEN_INT (rs6000_trampoline_size ()), SImode
,
19258 /* Table of valid machine attributes. */
19260 const struct attribute_spec rs6000_attribute_table
[] =
19262 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
19263 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
},
19264 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
},
19265 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
},
19266 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
},
19267 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
},
19268 #ifdef SUBTARGET_ATTRIBUTE_TABLE
19269 SUBTARGET_ATTRIBUTE_TABLE
,
19271 { NULL
, 0, 0, false, false, false, NULL
}
19274 /* Handle the "altivec" attribute. The attribute may have
19275 arguments as follows:
19277 __attribute__((altivec(vector__)))
19278 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
19279 __attribute__((altivec(bool__))) (always followed by 'unsigned')
19281 and may appear more than once (e.g., 'vector bool char') in a
19282 given declaration. */
19285 rs6000_handle_altivec_attribute (tree
*node
,
19286 tree name ATTRIBUTE_UNUSED
,
19288 int flags ATTRIBUTE_UNUSED
,
19289 bool *no_add_attrs
)
19291 tree type
= *node
, result
= NULL_TREE
;
19292 enum machine_mode mode
;
19295 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
19296 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
19297 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
19300 while (POINTER_TYPE_P (type
)
19301 || TREE_CODE (type
) == FUNCTION_TYPE
19302 || TREE_CODE (type
) == METHOD_TYPE
19303 || TREE_CODE (type
) == ARRAY_TYPE
)
19304 type
= TREE_TYPE (type
);
19306 mode
= TYPE_MODE (type
);
19308 /* Check for invalid AltiVec type qualifiers. */
19309 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
19312 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
19313 else if (rs6000_warn_altivec_long
)
19314 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
19316 else if (type
== long_long_unsigned_type_node
19317 || type
== long_long_integer_type_node
)
19318 error ("use of %<long long%> in AltiVec types is invalid");
19319 else if (type
== double_type_node
)
19320 error ("use of %<double%> in AltiVec types is invalid");
19321 else if (type
== long_double_type_node
)
19322 error ("use of %<long double%> in AltiVec types is invalid");
19323 else if (type
== boolean_type_node
)
19324 error ("use of boolean types in AltiVec types is invalid");
19325 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
19326 error ("use of %<complex%> in AltiVec types is invalid");
19327 else if (DECIMAL_FLOAT_MODE_P (mode
))
19328 error ("use of decimal floating point types in AltiVec types is invalid");
19330 switch (altivec_type
)
19333 unsigned_p
= TYPE_UNSIGNED (type
);
19337 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
19340 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
19343 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
19345 case SFmode
: result
= V4SF_type_node
; break;
19346 /* If the user says 'vector int bool', we may be handed the 'bool'
19347 attribute _before_ the 'vector' attribute, and so select the
19348 proper type in the 'b' case below. */
19349 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
19357 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
19358 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
19359 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
19366 case V8HImode
: result
= pixel_V8HI_type_node
;
19372 if (result
&& result
!= type
&& TYPE_READONLY (type
))
19373 result
= build_qualified_type (result
, TYPE_QUAL_CONST
);
19375 *no_add_attrs
= true; /* No need to hang on to the attribute. */
19378 *node
= reconstruct_complex_type (*node
, result
);
19383 /* AltiVec defines four built-in scalar types that serve as vector
19384 elements; we must teach the compiler how to mangle them. */
19386 static const char *
19387 rs6000_mangle_type (const_tree type
)
19389 type
= TYPE_MAIN_VARIANT (type
);
19391 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
19392 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
19395 if (type
== bool_char_type_node
) return "U6__boolc";
19396 if (type
== bool_short_type_node
) return "U6__bools";
19397 if (type
== pixel_type_node
) return "u7__pixel";
19398 if (type
== bool_int_type_node
) return "U6__booli";
19400 /* Mangle IBM extended float long double as `g' (__float128) on
19401 powerpc*-linux where long-double-64 previously was the default. */
19402 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
19404 && TARGET_LONG_DOUBLE_128
19405 && !TARGET_IEEEQUAD
)
19408 /* For all other types, use normal C++ mangling. */
19412 /* Handle a "longcall" or "shortcall" attribute; arguments as in
19413 struct attribute_spec.handler. */
19416 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
19417 tree args ATTRIBUTE_UNUSED
,
19418 int flags ATTRIBUTE_UNUSED
,
19419 bool *no_add_attrs
)
19421 if (TREE_CODE (*node
) != FUNCTION_TYPE
19422 && TREE_CODE (*node
) != FIELD_DECL
19423 && TREE_CODE (*node
) != TYPE_DECL
)
19425 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
19426 IDENTIFIER_POINTER (name
));
19427 *no_add_attrs
= true;
19433 /* Set longcall attributes on all functions declared when
19434 rs6000_default_long_calls is true. */
19436 rs6000_set_default_type_attributes (tree type
)
19438 if (rs6000_default_long_calls
19439 && (TREE_CODE (type
) == FUNCTION_TYPE
19440 || TREE_CODE (type
) == METHOD_TYPE
))
19441 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
19443 TYPE_ATTRIBUTES (type
));
19446 darwin_set_default_type_attributes (type
);
19450 /* Return a reference suitable for calling a function with the
19451 longcall attribute. */
19454 rs6000_longcall_ref (rtx call_ref
)
19456 const char *call_name
;
19459 if (GET_CODE (call_ref
) != SYMBOL_REF
)
19462 /* System V adds '.' to the internal name, so skip them. */
19463 call_name
= XSTR (call_ref
, 0);
19464 if (*call_name
== '.')
19466 while (*call_name
== '.')
19469 node
= get_identifier (call_name
);
19470 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
19473 return force_reg (Pmode
, call_ref
);
19476 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
19477 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
19480 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
19481 struct attribute_spec.handler. */
19483 rs6000_handle_struct_attribute (tree
*node
, tree name
,
19484 tree args ATTRIBUTE_UNUSED
,
19485 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
19488 if (DECL_P (*node
))
19490 if (TREE_CODE (*node
) == TYPE_DECL
)
19491 type
= &TREE_TYPE (*node
);
19496 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
19497 || TREE_CODE (*type
) == UNION_TYPE
)))
19499 warning (OPT_Wattributes
, "%qs attribute ignored", IDENTIFIER_POINTER (name
));
19500 *no_add_attrs
= true;
19503 else if ((is_attribute_p ("ms_struct", name
)
19504 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
19505 || ((is_attribute_p ("gcc_struct", name
)
19506 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
19508 warning (OPT_Wattributes
, "%qs incompatible attribute ignored",
19509 IDENTIFIER_POINTER (name
));
19510 *no_add_attrs
= true;
19517 rs6000_ms_bitfield_layout_p (const_tree record_type
)
19519 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
19520 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
19521 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
19524 #ifdef USING_ELFOS_H
19526 /* A get_unnamed_section callback, used for switching to toc_section. */
19529 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
19531 if (DEFAULT_ABI
== ABI_AIX
19532 && TARGET_MINIMAL_TOC
19533 && !TARGET_RELOCATABLE
)
19535 if (!toc_initialized
)
19537 toc_initialized
= 1;
19538 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
19539 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
19540 fprintf (asm_out_file
, "\t.tc ");
19541 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
19542 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
19543 fprintf (asm_out_file
, "\n");
19545 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
19546 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
19547 fprintf (asm_out_file
, " = .+32768\n");
19550 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
19552 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_RELOCATABLE
)
19553 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
19556 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
19557 if (!toc_initialized
)
19559 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
19560 fprintf (asm_out_file
, " = .+32768\n");
19561 toc_initialized
= 1;
19566 /* Implement TARGET_ASM_INIT_SECTIONS. */
19569 rs6000_elf_asm_init_sections (void)
19572 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
19575 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
19576 SDATA2_SECTION_ASM_OP
);
19579 /* Implement TARGET_SELECT_RTX_SECTION. */
19582 rs6000_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
19583 unsigned HOST_WIDE_INT align
)
19585 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
19586 return toc_section
;
19588 return default_elf_select_rtx_section (mode
, x
, align
);
19591 /* For a SYMBOL_REF, set generic flags and then perform some
19592 target-specific processing.
19594 When the AIX ABI is requested on a non-AIX system, replace the
19595 function name with the real name (with a leading .) rather than the
19596 function descriptor name. This saves a lot of overriding code to
19597 read the prefixes. */
19600 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
19602 default_encode_section_info (decl
, rtl
, first
);
19605 && TREE_CODE (decl
) == FUNCTION_DECL
19607 && DEFAULT_ABI
== ABI_AIX
)
19609 rtx sym_ref
= XEXP (rtl
, 0);
19610 size_t len
= strlen (XSTR (sym_ref
, 0));
19611 char *str
= alloca (len
+ 2);
19613 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
19614 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
19619 compare_section_name (const char *section
, const char *template)
19623 len
= strlen (template);
19624 return (strncmp (section
, template, len
) == 0
19625 && (section
[len
] == 0 || section
[len
] == '.'));
19629 rs6000_elf_in_small_data_p (const_tree decl
)
19631 if (rs6000_sdata
== SDATA_NONE
)
19634 /* We want to merge strings, so we never consider them small data. */
19635 if (TREE_CODE (decl
) == STRING_CST
)
19638 /* Functions are never in the small data area. */
19639 if (TREE_CODE (decl
) == FUNCTION_DECL
)
19642 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
19644 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
19645 if (compare_section_name (section
, ".sdata")
19646 || compare_section_name (section
, ".sdata2")
19647 || compare_section_name (section
, ".gnu.linkonce.s")
19648 || compare_section_name (section
, ".sbss")
19649 || compare_section_name (section
, ".sbss2")
19650 || compare_section_name (section
, ".gnu.linkonce.sb")
19651 || strcmp (section
, ".PPC.EMB.sdata0") == 0
19652 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
19657 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
19660 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
19661 /* If it's not public, and we're not going to reference it there,
19662 there's no need to put it in the small data section. */
19663 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
19670 #endif /* USING_ELFOS_H */
19672 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
19675 rs6000_use_blocks_for_constant_p (enum machine_mode mode
, const_rtx x
)
19677 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
19680 /* Return a REG that occurs in ADDR with coefficient 1.
19681 ADDR can be effectively incremented by incrementing REG.
19683 r0 is special and we must not select it as an address
19684 register by this routine since our caller will try to
19685 increment the returned register via an "la" instruction. */
19688 find_addr_reg (rtx addr
)
19690 while (GET_CODE (addr
) == PLUS
)
19692 if (GET_CODE (XEXP (addr
, 0)) == REG
19693 && REGNO (XEXP (addr
, 0)) != 0)
19694 addr
= XEXP (addr
, 0);
19695 else if (GET_CODE (XEXP (addr
, 1)) == REG
19696 && REGNO (XEXP (addr
, 1)) != 0)
19697 addr
= XEXP (addr
, 1);
19698 else if (CONSTANT_P (XEXP (addr
, 0)))
19699 addr
= XEXP (addr
, 1);
19700 else if (CONSTANT_P (XEXP (addr
, 1)))
19701 addr
= XEXP (addr
, 0);
19703 gcc_unreachable ();
19705 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
19710 rs6000_fatal_bad_address (rtx op
)
19712 fatal_insn ("bad address", op
);
19717 static tree branch_island_list
= 0;
19719 /* Remember to generate a branch island for far calls to the given
19723 add_compiler_branch_island (tree label_name
, tree function_name
,
19726 tree branch_island
= build_tree_list (function_name
, label_name
);
19727 TREE_TYPE (branch_island
) = build_int_cst (NULL_TREE
, line_number
);
19728 TREE_CHAIN (branch_island
) = branch_island_list
;
19729 branch_island_list
= branch_island
;
19732 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
19733 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
19734 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
19735 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
19737 /* Generate far-jump branch islands for everything on the
19738 branch_island_list. Invoked immediately after the last instruction
19739 of the epilogue has been emitted; the branch-islands must be
19740 appended to, and contiguous with, the function body. Mach-O stubs
19741 are generated in machopic_output_stub(). */
19744 macho_branch_islands (void)
19747 tree branch_island
;
19749 for (branch_island
= branch_island_list
;
19751 branch_island
= TREE_CHAIN (branch_island
))
19753 const char *label
=
19754 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island
));
19756 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island
));
19757 char name_buf
[512];
19758 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
19759 if (name
[0] == '*' || name
[0] == '&')
19760 strcpy (name_buf
, name
+1);
19764 strcpy (name_buf
+1, name
);
19766 strcpy (tmp_buf
, "\n");
19767 strcat (tmp_buf
, label
);
19768 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
19769 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
19770 dbxout_stabd (N_SLINE
, BRANCH_ISLAND_LINE_NUMBER (branch_island
));
19771 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
19774 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
19775 strcat (tmp_buf
, label
);
19776 strcat (tmp_buf
, "_pic\n");
19777 strcat (tmp_buf
, label
);
19778 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
19780 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
19781 strcat (tmp_buf
, name_buf
);
19782 strcat (tmp_buf
, " - ");
19783 strcat (tmp_buf
, label
);
19784 strcat (tmp_buf
, "_pic)\n");
19786 strcat (tmp_buf
, "\tmtlr r0\n");
19788 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
19789 strcat (tmp_buf
, name_buf
);
19790 strcat (tmp_buf
, " - ");
19791 strcat (tmp_buf
, label
);
19792 strcat (tmp_buf
, "_pic)\n");
19794 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
19798 strcat (tmp_buf
, ":\nlis r12,hi16(");
19799 strcat (tmp_buf
, name_buf
);
19800 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
19801 strcat (tmp_buf
, name_buf
);
19802 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
19804 output_asm_insn (tmp_buf
, 0);
19805 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
19806 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
19807 dbxout_stabd (N_SLINE
, BRANCH_ISLAND_LINE_NUMBER (branch_island
));
19808 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
19811 branch_island_list
= 0;
19814 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
19815 already there or not. */
19818 no_previous_def (tree function_name
)
19820 tree branch_island
;
19821 for (branch_island
= branch_island_list
;
19823 branch_island
= TREE_CHAIN (branch_island
))
19824 if (function_name
== BRANCH_ISLAND_FUNCTION_NAME (branch_island
))
19829 /* GET_PREV_LABEL gets the label name from the previous definition of
19833 get_prev_label (tree function_name
)
19835 tree branch_island
;
19836 for (branch_island
= branch_island_list
;
19838 branch_island
= TREE_CHAIN (branch_island
))
19839 if (function_name
== BRANCH_ISLAND_FUNCTION_NAME (branch_island
))
19840 return BRANCH_ISLAND_LABEL_NAME (branch_island
);
19844 #ifndef DARWIN_LINKER_GENERATES_ISLANDS
19845 #define DARWIN_LINKER_GENERATES_ISLANDS 0
19848 /* KEXTs still need branch islands. */
19849 #define DARWIN_GENERATE_ISLANDS (!DARWIN_LINKER_GENERATES_ISLANDS \
19850 || flag_mkernel || flag_apple_kext)
19852 /* INSN is either a function call or a millicode call. It may have an
19853 unconditional jump in its delay slot.
19855 CALL_DEST is the routine we are calling. */
19858 output_call (rtx insn
, rtx
*operands
, int dest_operand_number
,
19859 int cookie_operand_number
)
19861 static char buf
[256];
19862 if (DARWIN_GENERATE_ISLANDS
19863 && GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
19864 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
19867 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
19869 if (no_previous_def (funname
))
19871 rtx label_rtx
= gen_label_rtx ();
19872 char *label_buf
, temp_buf
[256];
19873 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
19874 CODE_LABEL_NUMBER (label_rtx
));
19875 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
19876 labelname
= get_identifier (label_buf
);
19877 add_compiler_branch_island (labelname
, funname
, insn_line (insn
));
19880 labelname
= get_prev_label (funname
);
19882 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
19883 instruction will reach 'foo', otherwise link as 'bl L42'".
19884 "L42" should be a 'branch island', that will do a far jump to
19885 'foo'. Branch islands are generated in
19886 macho_branch_islands(). */
19887 sprintf (buf
, "jbsr %%z%d,%.246s",
19888 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
19891 sprintf (buf
, "bl %%z%d", dest_operand_number
);
19895 /* Generate PIC and indirect symbol stubs. */
19898 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
19900 unsigned int length
;
19901 char *symbol_name
, *lazy_ptr_name
;
19902 char *local_label_0
;
19903 static int label
= 0;
19905 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
19906 symb
= (*targetm
.strip_name_encoding
) (symb
);
19909 length
= strlen (symb
);
19910 symbol_name
= alloca (length
+ 32);
19911 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
19913 lazy_ptr_name
= alloca (length
+ 32);
19914 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
19917 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
19919 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
19923 fprintf (file
, "\t.align 5\n");
19925 fprintf (file
, "%s:\n", stub
);
19926 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
19929 local_label_0
= alloca (sizeof ("\"L00000000000$spb\""));
19930 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
19932 fprintf (file
, "\tmflr r0\n");
19933 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
19934 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
19935 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
19936 lazy_ptr_name
, local_label_0
);
19937 fprintf (file
, "\tmtlr r0\n");
19938 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
19939 (TARGET_64BIT
? "ldu" : "lwzu"),
19940 lazy_ptr_name
, local_label_0
);
19941 fprintf (file
, "\tmtctr r12\n");
19942 fprintf (file
, "\tbctr\n");
19946 fprintf (file
, "\t.align 4\n");
19948 fprintf (file
, "%s:\n", stub
);
19949 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
19951 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
19952 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
19953 (TARGET_64BIT
? "ldu" : "lwzu"),
19955 fprintf (file
, "\tmtctr r12\n");
19956 fprintf (file
, "\tbctr\n");
19959 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
19960 fprintf (file
, "%s:\n", lazy_ptr_name
);
19961 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
19962 fprintf (file
, "%sdyld_stub_binding_helper\n",
19963 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
19966 /* Legitimize PIC addresses. If the address is already
19967 position-independent, we return ORIG. Newly generated
19968 position-independent addresses go into a reg. This is REG if non
19969 zero, otherwise we allocate register(s) as necessary. */
19971 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
19974 rs6000_machopic_legitimize_pic_address (rtx orig
, enum machine_mode mode
,
19979 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
19980 reg
= gen_reg_rtx (Pmode
);
19982 if (GET_CODE (orig
) == CONST
)
19986 if (GET_CODE (XEXP (orig
, 0)) == PLUS
19987 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
19990 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
19992 /* Use a different reg for the intermediate value, as
19993 it will be marked UNCHANGING. */
19994 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
19995 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
19998 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
20001 if (GET_CODE (offset
) == CONST_INT
)
20003 if (SMALL_INT (offset
))
20004 return plus_constant (base
, INTVAL (offset
));
20005 else if (! reload_in_progress
&& ! reload_completed
)
20006 offset
= force_reg (Pmode
, offset
);
20009 rtx mem
= force_const_mem (Pmode
, orig
);
20010 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
20013 return gen_rtx_PLUS (Pmode
, base
, offset
);
20016 /* Fall back on generic machopic code. */
20017 return machopic_legitimize_pic_address (orig
, mode
, reg
);
20020 /* Output a .machine directive for the Darwin assembler, and call
20021 the generic start_file routine. */
20024 rs6000_darwin_file_start (void)
20026 static const struct
20032 { "ppc64", "ppc64", MASK_64BIT
},
20033 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
20034 { "power4", "ppc970", 0 },
20035 { "G5", "ppc970", 0 },
20036 { "7450", "ppc7450", 0 },
20037 { "7400", "ppc7400", MASK_ALTIVEC
},
20038 { "G4", "ppc7400", 0 },
20039 { "750", "ppc750", 0 },
20040 { "740", "ppc750", 0 },
20041 { "G3", "ppc750", 0 },
20042 { "604e", "ppc604e", 0 },
20043 { "604", "ppc604", 0 },
20044 { "603e", "ppc603", 0 },
20045 { "603", "ppc603", 0 },
20046 { "601", "ppc601", 0 },
20047 { NULL
, "ppc", 0 } };
20048 const char *cpu_id
= "";
20051 rs6000_file_start ();
20052 darwin_file_start ();
20054 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
20055 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
20056 if (rs6000_select
[i
].set_arch_p
&& rs6000_select
[i
].string
20057 && rs6000_select
[i
].string
[0] != '\0')
20058 cpu_id
= rs6000_select
[i
].string
;
20060 /* Look through the mapping array. Pick the first name that either
20061 matches the argument, has a bit set in IF_SET that is also set
20062 in the target flags, or has a NULL name. */
20065 while (mapping
[i
].arg
!= NULL
20066 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
20067 && (mapping
[i
].if_set
& target_flags
) == 0)
20070 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
20073 #endif /* TARGET_MACHO */
20077 rs6000_elf_reloc_rw_mask (void)
20081 else if (DEFAULT_ABI
== ABI_AIX
)
20087 /* Record an element in the table of global constructors. SYMBOL is
20088 a SYMBOL_REF of the function to be called; PRIORITY is a number
20089 between 0 and MAX_INIT_PRIORITY.
20091 This differs from default_named_section_asm_out_constructor in
20092 that we have special handling for -mrelocatable. */
20095 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
20097 const char *section
= ".ctors";
20100 if (priority
!= DEFAULT_INIT_PRIORITY
)
20102 sprintf (buf
, ".ctors.%.5u",
20103 /* Invert the numbering so the linker puts us in the proper
20104 order; constructors are run from right to left, and the
20105 linker sorts in increasing order. */
20106 MAX_INIT_PRIORITY
- priority
);
20110 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
20111 assemble_align (POINTER_SIZE
);
20113 if (TARGET_RELOCATABLE
)
20115 fputs ("\t.long (", asm_out_file
);
20116 output_addr_const (asm_out_file
, symbol
);
20117 fputs (")@fixup\n", asm_out_file
);
20120 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
20124 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
20126 const char *section
= ".dtors";
20129 if (priority
!= DEFAULT_INIT_PRIORITY
)
20131 sprintf (buf
, ".dtors.%.5u",
20132 /* Invert the numbering so the linker puts us in the proper
20133 order; constructors are run from right to left, and the
20134 linker sorts in increasing order. */
20135 MAX_INIT_PRIORITY
- priority
);
20139 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
20140 assemble_align (POINTER_SIZE
);
20142 if (TARGET_RELOCATABLE
)
20144 fputs ("\t.long (", asm_out_file
);
20145 output_addr_const (asm_out_file
, symbol
);
20146 fputs (")@fixup\n", asm_out_file
);
20149 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
20153 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
20157 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
20158 ASM_OUTPUT_LABEL (file
, name
);
20159 fputs (DOUBLE_INT_ASM_OP
, file
);
20160 rs6000_output_function_entry (file
, name
);
20161 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
20164 fputs ("\t.size\t", file
);
20165 assemble_name (file
, name
);
20166 fputs (",24\n\t.type\t.", file
);
20167 assemble_name (file
, name
);
20168 fputs (",@function\n", file
);
20169 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
20171 fputs ("\t.globl\t.", file
);
20172 assemble_name (file
, name
);
20177 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
20178 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
20179 rs6000_output_function_entry (file
, name
);
20180 fputs (":\n", file
);
20184 if (TARGET_RELOCATABLE
20185 && !TARGET_SECURE_PLT
20186 && (get_pool_size () != 0 || current_function_profile
)
20191 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
20193 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
20194 fprintf (file
, "\t.long ");
20195 assemble_name (file
, buf
);
20197 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
20198 assemble_name (file
, buf
);
20202 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
20203 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
20205 if (DEFAULT_ABI
== ABI_AIX
)
20207 const char *desc_name
, *orig_name
;
20209 orig_name
= (*targetm
.strip_name_encoding
) (name
);
20210 desc_name
= orig_name
;
20211 while (*desc_name
== '.')
20214 if (TREE_PUBLIC (decl
))
20215 fprintf (file
, "\t.globl %s\n", desc_name
);
20217 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
20218 fprintf (file
, "%s:\n", desc_name
);
20219 fprintf (file
, "\t.long %s\n", orig_name
);
20220 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
20221 if (DEFAULT_ABI
== ABI_AIX
)
20222 fputs ("\t.long 0\n", file
);
20223 fprintf (file
, "\t.previous\n");
20225 ASM_OUTPUT_LABEL (file
, name
);
20229 rs6000_elf_end_indicate_exec_stack (void)
20232 file_end_indicate_exec_stack ();
20238 rs6000_xcoff_asm_output_anchor (rtx symbol
)
20242 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
20243 SYMBOL_REF_BLOCK_OFFSET (symbol
));
20244 ASM_OUTPUT_DEF (asm_out_file
, XSTR (symbol
, 0), buffer
);
20248 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
20250 fputs (GLOBAL_ASM_OP
, stream
);
20251 RS6000_OUTPUT_BASENAME (stream
, name
);
20252 putc ('\n', stream
);
20255 /* A get_unnamed_decl callback, used for read-only sections. PTR
20256 points to the section string variable. */
20259 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
20261 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
20262 *(const char *const *) directive
,
20263 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
20266 /* Likewise for read-write sections. */
20269 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
20271 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
20272 *(const char *const *) directive
,
20273 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
20276 /* A get_unnamed_section callback, used for switching to toc_section. */
20279 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
20281 if (TARGET_MINIMAL_TOC
)
20283 /* toc_section is always selected at least once from
20284 rs6000_xcoff_file_start, so this is guaranteed to
20285 always be defined once and only once in each file. */
20286 if (!toc_initialized
)
20288 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
20289 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
20290 toc_initialized
= 1;
20292 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
20293 (TARGET_32BIT
? "" : ",3"));
20296 fputs ("\t.toc\n", asm_out_file
);
20299 /* Implement TARGET_ASM_INIT_SECTIONS. */
20302 rs6000_xcoff_asm_init_sections (void)
20304 read_only_data_section
20305 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
20306 &xcoff_read_only_section_name
);
20308 private_data_section
20309 = get_unnamed_section (SECTION_WRITE
,
20310 rs6000_xcoff_output_readwrite_section_asm_op
,
20311 &xcoff_private_data_section_name
);
20313 read_only_private_data_section
20314 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
20315 &xcoff_private_data_section_name
);
20318 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
20320 readonly_data_section
= read_only_data_section
;
20321 exception_section
= data_section
;
20325 rs6000_xcoff_reloc_rw_mask (void)
20331 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
20332 tree decl ATTRIBUTE_UNUSED
)
20335 static const char * const suffix
[3] = { "PR", "RO", "RW" };
20337 if (flags
& SECTION_CODE
)
20339 else if (flags
& SECTION_WRITE
)
20344 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
20345 (flags
& SECTION_CODE
) ? "." : "",
20346 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
20350 rs6000_xcoff_select_section (tree decl
, int reloc
,
20351 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
20353 if (decl_readonly_section (decl
, reloc
))
20355 if (TREE_PUBLIC (decl
))
20356 return read_only_data_section
;
20358 return read_only_private_data_section
;
20362 if (TREE_PUBLIC (decl
))
20363 return data_section
;
20365 return private_data_section
;
20370 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
20374 /* Use select_section for private and uninitialized data. */
20375 if (!TREE_PUBLIC (decl
)
20376 || DECL_COMMON (decl
)
20377 || DECL_INITIAL (decl
) == NULL_TREE
20378 || DECL_INITIAL (decl
) == error_mark_node
20379 || (flag_zero_initialized_in_bss
20380 && initializer_zerop (DECL_INITIAL (decl
))))
20383 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
20384 name
= (*targetm
.strip_name_encoding
) (name
);
20385 DECL_SECTION_NAME (decl
) = build_string (strlen (name
), name
);
20388 /* Select section for constant in constant pool.
20390 On RS/6000, all constants are in the private read-only data area.
20391 However, if this is being placed in the TOC it must be output as a
20395 rs6000_xcoff_select_rtx_section (enum machine_mode mode
, rtx x
,
20396 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
20398 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
20399 return toc_section
;
20401 return read_only_private_data_section
;
20404 /* Remove any trailing [DS] or the like from the symbol name. */
20406 static const char *
20407 rs6000_xcoff_strip_name_encoding (const char *name
)
20412 len
= strlen (name
);
20413 if (name
[len
- 1] == ']')
20414 return ggc_alloc_string (name
, len
- 4);
20419 /* Section attributes. AIX is always PIC. */
20421 static unsigned int
20422 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
20424 unsigned int align
;
20425 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
20427 /* Align to at least UNIT size. */
20428 if (flags
& SECTION_CODE
)
20429 align
= MIN_UNITS_PER_WORD
;
20431 /* Increase alignment of large objects if not already stricter. */
20432 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
20433 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
20434 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
20436 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
20439 /* Output at beginning of assembler file.
20441 Initialize the section names for the RS/6000 at this point.
20443 Specify filename, including full path, to assembler.
20445 We want to go into the TOC section so at least one .toc will be emitted.
20446 Also, in order to output proper .bs/.es pairs, we need at least one static
20447 [RW] section emitted.
20449 Finally, declare mcount when profiling to make the assembler happy. */
20452 rs6000_xcoff_file_start (void)
20454 rs6000_gen_section_name (&xcoff_bss_section_name
,
20455 main_input_filename
, ".bss_");
20456 rs6000_gen_section_name (&xcoff_private_data_section_name
,
20457 main_input_filename
, ".rw_");
20458 rs6000_gen_section_name (&xcoff_read_only_section_name
,
20459 main_input_filename
, ".ro_");
20461 fputs ("\t.file\t", asm_out_file
);
20462 output_quoted_string (asm_out_file
, main_input_filename
);
20463 fputc ('\n', asm_out_file
);
20464 if (write_symbols
!= NO_DEBUG
)
20465 switch_to_section (private_data_section
);
20466 switch_to_section (text_section
);
20468 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
20469 rs6000_file_start ();
20472 /* Output at end of assembler file.
20473 On the RS/6000, referencing data should automatically pull in text. */
20476 rs6000_xcoff_file_end (void)
20478 switch_to_section (text_section
);
20479 fputs ("_section_.text:\n", asm_out_file
);
20480 switch_to_section (data_section
);
20481 fputs (TARGET_32BIT
20482 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
20485 #endif /* TARGET_XCOFF */
20487 /* Compute a (partial) cost for rtx X. Return true if the complete
20488 cost has been computed, and false if subexpressions should be
20489 scanned. In either case, *TOTAL contains the cost result. */
20492 rs6000_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
20494 enum machine_mode mode
= GET_MODE (x
);
20498 /* On the RS/6000, if it is valid in the insn, it is free. */
20500 if (((outer_code
== SET
20501 || outer_code
== PLUS
20502 || outer_code
== MINUS
)
20503 && (satisfies_constraint_I (x
)
20504 || satisfies_constraint_L (x
)))
20505 || (outer_code
== AND
20506 && (satisfies_constraint_K (x
)
20508 ? satisfies_constraint_L (x
)
20509 : satisfies_constraint_J (x
))
20510 || mask_operand (x
, mode
)
20512 && mask64_operand (x
, DImode
))))
20513 || ((outer_code
== IOR
|| outer_code
== XOR
)
20514 && (satisfies_constraint_K (x
)
20516 ? satisfies_constraint_L (x
)
20517 : satisfies_constraint_J (x
))))
20518 || outer_code
== ASHIFT
20519 || outer_code
== ASHIFTRT
20520 || outer_code
== LSHIFTRT
20521 || outer_code
== ROTATE
20522 || outer_code
== ROTATERT
20523 || outer_code
== ZERO_EXTRACT
20524 || (outer_code
== MULT
20525 && satisfies_constraint_I (x
))
20526 || ((outer_code
== DIV
|| outer_code
== UDIV
20527 || outer_code
== MOD
|| outer_code
== UMOD
)
20528 && exact_log2 (INTVAL (x
)) >= 0)
20529 || (outer_code
== COMPARE
20530 && (satisfies_constraint_I (x
)
20531 || satisfies_constraint_K (x
)))
20532 || (outer_code
== EQ
20533 && (satisfies_constraint_I (x
)
20534 || satisfies_constraint_K (x
)
20536 ? satisfies_constraint_L (x
)
20537 : satisfies_constraint_J (x
))))
20538 || (outer_code
== GTU
20539 && satisfies_constraint_I (x
))
20540 || (outer_code
== LTU
20541 && satisfies_constraint_P (x
)))
20546 else if ((outer_code
== PLUS
20547 && reg_or_add_cint_operand (x
, VOIDmode
))
20548 || (outer_code
== MINUS
20549 && reg_or_sub_cint_operand (x
, VOIDmode
))
20550 || ((outer_code
== SET
20551 || outer_code
== IOR
20552 || outer_code
== XOR
)
20554 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
20556 *total
= COSTS_N_INSNS (1);
20562 if (mode
== DImode
&& code
== CONST_DOUBLE
)
20564 if ((outer_code
== IOR
|| outer_code
== XOR
)
20565 && CONST_DOUBLE_HIGH (x
) == 0
20566 && (CONST_DOUBLE_LOW (x
)
20567 & ~ (unsigned HOST_WIDE_INT
) 0xffff) == 0)
20572 else if ((outer_code
== AND
&& and64_2_operand (x
, DImode
))
20573 || ((outer_code
== SET
20574 || outer_code
== IOR
20575 || outer_code
== XOR
)
20576 && CONST_DOUBLE_HIGH (x
) == 0))
20578 *total
= COSTS_N_INSNS (1);
20588 /* When optimizing for size, MEM should be slightly more expensive
20589 than generating address, e.g., (plus (reg) (const)).
20590 L1 cache latency is about two instructions. */
20591 *total
= optimize_size
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
20599 if (mode
== DFmode
)
20601 if (GET_CODE (XEXP (x
, 0)) == MULT
)
20603 /* FNMA accounted in outer NEG. */
20604 if (outer_code
== NEG
)
20605 *total
= rs6000_cost
->dmul
- rs6000_cost
->fp
;
20607 *total
= rs6000_cost
->dmul
;
20610 *total
= rs6000_cost
->fp
;
20612 else if (mode
== SFmode
)
20614 /* FNMA accounted in outer NEG. */
20615 if (outer_code
== NEG
&& GET_CODE (XEXP (x
, 0)) == MULT
)
20618 *total
= rs6000_cost
->fp
;
20621 *total
= COSTS_N_INSNS (1);
20625 if (mode
== DFmode
)
20627 if (GET_CODE (XEXP (x
, 0)) == MULT
20628 || GET_CODE (XEXP (x
, 1)) == MULT
)
20630 /* FNMA accounted in outer NEG. */
20631 if (outer_code
== NEG
)
20632 *total
= rs6000_cost
->dmul
- rs6000_cost
->fp
;
20634 *total
= rs6000_cost
->dmul
;
20637 *total
= rs6000_cost
->fp
;
20639 else if (mode
== SFmode
)
20641 /* FNMA accounted in outer NEG. */
20642 if (outer_code
== NEG
&& GET_CODE (XEXP (x
, 0)) == MULT
)
20645 *total
= rs6000_cost
->fp
;
20648 *total
= COSTS_N_INSNS (1);
20652 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
20653 && satisfies_constraint_I (XEXP (x
, 1)))
20655 if (INTVAL (XEXP (x
, 1)) >= -256
20656 && INTVAL (XEXP (x
, 1)) <= 255)
20657 *total
= rs6000_cost
->mulsi_const9
;
20659 *total
= rs6000_cost
->mulsi_const
;
20661 /* FMA accounted in outer PLUS/MINUS. */
20662 else if ((mode
== DFmode
|| mode
== SFmode
)
20663 && (outer_code
== PLUS
|| outer_code
== MINUS
))
20665 else if (mode
== DFmode
)
20666 *total
= rs6000_cost
->dmul
;
20667 else if (mode
== SFmode
)
20668 *total
= rs6000_cost
->fp
;
20669 else if (mode
== DImode
)
20670 *total
= rs6000_cost
->muldi
;
20672 *total
= rs6000_cost
->mulsi
;
20677 if (FLOAT_MODE_P (mode
))
20679 *total
= mode
== DFmode
? rs6000_cost
->ddiv
20680 : rs6000_cost
->sdiv
;
20687 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
20688 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
20690 if (code
== DIV
|| code
== MOD
)
20692 *total
= COSTS_N_INSNS (2);
20695 *total
= COSTS_N_INSNS (1);
20699 if (GET_MODE (XEXP (x
, 1)) == DImode
)
20700 *total
= rs6000_cost
->divdi
;
20702 *total
= rs6000_cost
->divsi
;
20704 /* Add in shift and subtract for MOD. */
20705 if (code
== MOD
|| code
== UMOD
)
20706 *total
+= COSTS_N_INSNS (2);
20711 *total
= COSTS_N_INSNS (4);
20715 *total
= COSTS_N_INSNS (6);
20719 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
20731 *total
= COSTS_N_INSNS (1);
20739 /* Handle mul_highpart. */
20740 if (outer_code
== TRUNCATE
20741 && GET_CODE (XEXP (x
, 0)) == MULT
)
20743 if (mode
== DImode
)
20744 *total
= rs6000_cost
->muldi
;
20746 *total
= rs6000_cost
->mulsi
;
20749 else if (outer_code
== AND
)
20752 *total
= COSTS_N_INSNS (1);
20757 if (GET_CODE (XEXP (x
, 0)) == MEM
)
20760 *total
= COSTS_N_INSNS (1);
20766 if (!FLOAT_MODE_P (mode
))
20768 *total
= COSTS_N_INSNS (1);
20774 case UNSIGNED_FLOAT
:
20777 case FLOAT_TRUNCATE
:
20778 *total
= rs6000_cost
->fp
;
20782 if (mode
== DFmode
)
20785 *total
= rs6000_cost
->fp
;
20789 switch (XINT (x
, 1))
20792 *total
= rs6000_cost
->fp
;
20804 *total
= COSTS_N_INSNS (1);
20807 else if (FLOAT_MODE_P (mode
)
20808 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
20810 *total
= rs6000_cost
->fp
;
20818 /* Carry bit requires mode == Pmode.
20819 NEG or PLUS already counted so only add one. */
20821 && (outer_code
== NEG
|| outer_code
== PLUS
))
20823 *total
= COSTS_N_INSNS (1);
20826 if (outer_code
== SET
)
20828 if (XEXP (x
, 1) == const0_rtx
)
20830 *total
= COSTS_N_INSNS (2);
20833 else if (mode
== Pmode
)
20835 *total
= COSTS_N_INSNS (3);
20844 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
20846 *total
= COSTS_N_INSNS (2);
20850 if (outer_code
== COMPARE
)
20864 /* A C expression returning the cost of moving data from a register of class
20865 CLASS1 to one of CLASS2. */
20868 rs6000_register_move_cost (enum machine_mode mode
,
20869 enum reg_class from
, enum reg_class to
)
20871 /* Moves from/to GENERAL_REGS. */
20872 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
20873 || reg_classes_intersect_p (from
, GENERAL_REGS
))
20875 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
20878 if (from
== FLOAT_REGS
|| from
== ALTIVEC_REGS
)
20879 return (rs6000_memory_move_cost (mode
, from
, 0)
20880 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, 0));
20882 /* It's more expensive to move CR_REGS than CR0_REGS because of the
20884 else if (from
== CR_REGS
)
20888 /* A move will cost one instruction per GPR moved. */
20889 return 2 * hard_regno_nregs
[0][mode
];
20892 /* Moving between two similar registers is just one instruction. */
20893 else if (reg_classes_intersect_p (to
, from
))
20894 return (mode
== TFmode
|| mode
== TDmode
) ? 4 : 2;
20896 /* Everything else has to go through GENERAL_REGS. */
20898 return (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
20899 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
20902 /* A C expressions returning the cost of moving data of MODE from a register to
20906 rs6000_memory_move_cost (enum machine_mode mode
, enum reg_class
class,
20907 int in ATTRIBUTE_UNUSED
)
20909 if (reg_classes_intersect_p (class, GENERAL_REGS
))
20910 return 4 * hard_regno_nregs
[0][mode
];
20911 else if (reg_classes_intersect_p (class, FLOAT_REGS
))
20912 return 4 * hard_regno_nregs
[32][mode
];
20913 else if (reg_classes_intersect_p (class, ALTIVEC_REGS
))
20914 return 4 * hard_regno_nregs
[FIRST_ALTIVEC_REGNO
][mode
];
20916 return 4 + rs6000_register_move_cost (mode
, class, GENERAL_REGS
);
20919 /* Returns a code for a target-specific builtin that implements
20920 reciprocal of the function, or NULL_TREE if not available. */
20923 rs6000_builtin_reciprocal (unsigned int fn
, bool md_fn
,
20924 bool sqrt ATTRIBUTE_UNUSED
)
20926 if (! (TARGET_RECIP
&& TARGET_PPC_GFXOPT
&& !optimize_size
20927 && flag_finite_math_only
&& !flag_trapping_math
20928 && flag_unsafe_math_optimizations
))
20936 case BUILT_IN_SQRTF
:
20937 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRTF
];
20944 /* Newton-Raphson approximation of single-precision floating point divide n/d.
20945 Assumes no trapping math and finite arguments. */
20948 rs6000_emit_swdivsf (rtx dst
, rtx n
, rtx d
)
20950 rtx x0
, e0
, e1
, y1
, u0
, v0
, one
;
20952 x0
= gen_reg_rtx (SFmode
);
20953 e0
= gen_reg_rtx (SFmode
);
20954 e1
= gen_reg_rtx (SFmode
);
20955 y1
= gen_reg_rtx (SFmode
);
20956 u0
= gen_reg_rtx (SFmode
);
20957 v0
= gen_reg_rtx (SFmode
);
20958 one
= force_reg (SFmode
, CONST_DOUBLE_FROM_REAL_VALUE (dconst1
, SFmode
));
20960 /* x0 = 1./d estimate */
20961 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
20962 gen_rtx_UNSPEC (SFmode
, gen_rtvec (1, d
),
20964 /* e0 = 1. - d * x0 */
20965 emit_insn (gen_rtx_SET (VOIDmode
, e0
,
20966 gen_rtx_MINUS (SFmode
, one
,
20967 gen_rtx_MULT (SFmode
, d
, x0
))));
20968 /* e1 = e0 + e0 * e0 */
20969 emit_insn (gen_rtx_SET (VOIDmode
, e1
,
20970 gen_rtx_PLUS (SFmode
,
20971 gen_rtx_MULT (SFmode
, e0
, e0
), e0
)));
20972 /* y1 = x0 + e1 * x0 */
20973 emit_insn (gen_rtx_SET (VOIDmode
, y1
,
20974 gen_rtx_PLUS (SFmode
,
20975 gen_rtx_MULT (SFmode
, e1
, x0
), x0
)));
20977 emit_insn (gen_rtx_SET (VOIDmode
, u0
,
20978 gen_rtx_MULT (SFmode
, n
, y1
)));
20979 /* v0 = n - d * u0 */
20980 emit_insn (gen_rtx_SET (VOIDmode
, v0
,
20981 gen_rtx_MINUS (SFmode
, n
,
20982 gen_rtx_MULT (SFmode
, d
, u0
))));
20983 /* dst = u0 + v0 * y1 */
20984 emit_insn (gen_rtx_SET (VOIDmode
, dst
,
20985 gen_rtx_PLUS (SFmode
,
20986 gen_rtx_MULT (SFmode
, v0
, y1
), u0
)));
20989 /* Newton-Raphson approximation of double-precision floating point divide n/d.
20990 Assumes no trapping math and finite arguments. */
20993 rs6000_emit_swdivdf (rtx dst
, rtx n
, rtx d
)
20995 rtx x0
, e0
, e1
, e2
, y1
, y2
, y3
, u0
, v0
, one
;
20997 x0
= gen_reg_rtx (DFmode
);
20998 e0
= gen_reg_rtx (DFmode
);
20999 e1
= gen_reg_rtx (DFmode
);
21000 e2
= gen_reg_rtx (DFmode
);
21001 y1
= gen_reg_rtx (DFmode
);
21002 y2
= gen_reg_rtx (DFmode
);
21003 y3
= gen_reg_rtx (DFmode
);
21004 u0
= gen_reg_rtx (DFmode
);
21005 v0
= gen_reg_rtx (DFmode
);
21006 one
= force_reg (DFmode
, CONST_DOUBLE_FROM_REAL_VALUE (dconst1
, DFmode
));
21008 /* x0 = 1./d estimate */
21009 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
21010 gen_rtx_UNSPEC (DFmode
, gen_rtvec (1, d
),
21012 /* e0 = 1. - d * x0 */
21013 emit_insn (gen_rtx_SET (VOIDmode
, e0
,
21014 gen_rtx_MINUS (DFmode
, one
,
21015 gen_rtx_MULT (SFmode
, d
, x0
))));
21016 /* y1 = x0 + e0 * x0 */
21017 emit_insn (gen_rtx_SET (VOIDmode
, y1
,
21018 gen_rtx_PLUS (DFmode
,
21019 gen_rtx_MULT (DFmode
, e0
, x0
), x0
)));
21021 emit_insn (gen_rtx_SET (VOIDmode
, e1
,
21022 gen_rtx_MULT (DFmode
, e0
, e0
)));
21023 /* y2 = y1 + e1 * y1 */
21024 emit_insn (gen_rtx_SET (VOIDmode
, y2
,
21025 gen_rtx_PLUS (DFmode
,
21026 gen_rtx_MULT (DFmode
, e1
, y1
), y1
)));
21028 emit_insn (gen_rtx_SET (VOIDmode
, e2
,
21029 gen_rtx_MULT (DFmode
, e1
, e1
)));
21030 /* y3 = y2 + e2 * y2 */
21031 emit_insn (gen_rtx_SET (VOIDmode
, y3
,
21032 gen_rtx_PLUS (DFmode
,
21033 gen_rtx_MULT (DFmode
, e2
, y2
), y2
)));
21035 emit_insn (gen_rtx_SET (VOIDmode
, u0
,
21036 gen_rtx_MULT (DFmode
, n
, y3
)));
21037 /* v0 = n - d * u0 */
21038 emit_insn (gen_rtx_SET (VOIDmode
, v0
,
21039 gen_rtx_MINUS (DFmode
, n
,
21040 gen_rtx_MULT (DFmode
, d
, u0
))));
21041 /* dst = u0 + v0 * y3 */
21042 emit_insn (gen_rtx_SET (VOIDmode
, dst
,
21043 gen_rtx_PLUS (DFmode
,
21044 gen_rtx_MULT (DFmode
, v0
, y3
), u0
)));
21048 /* Newton-Raphson approximation of single-precision floating point rsqrt.
21049 Assumes no trapping math and finite arguments. */
21052 rs6000_emit_swrsqrtsf (rtx dst
, rtx src
)
21054 rtx x0
, x1
, x2
, y1
, u0
, u1
, u2
, v0
, v1
, v2
, t0
,
21055 half
, one
, halfthree
, c1
, cond
, label
;
21057 x0
= gen_reg_rtx (SFmode
);
21058 x1
= gen_reg_rtx (SFmode
);
21059 x2
= gen_reg_rtx (SFmode
);
21060 y1
= gen_reg_rtx (SFmode
);
21061 u0
= gen_reg_rtx (SFmode
);
21062 u1
= gen_reg_rtx (SFmode
);
21063 u2
= gen_reg_rtx (SFmode
);
21064 v0
= gen_reg_rtx (SFmode
);
21065 v1
= gen_reg_rtx (SFmode
);
21066 v2
= gen_reg_rtx (SFmode
);
21067 t0
= gen_reg_rtx (SFmode
);
21068 halfthree
= gen_reg_rtx (SFmode
);
21069 cond
= gen_rtx_REG (CCFPmode
, CR1_REGNO
);
21070 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
21072 /* check 0.0, 1.0, NaN, Inf by testing src * src = src */
21073 emit_insn (gen_rtx_SET (VOIDmode
, t0
,
21074 gen_rtx_MULT (SFmode
, src
, src
)));
21076 emit_insn (gen_rtx_SET (VOIDmode
, cond
,
21077 gen_rtx_COMPARE (CCFPmode
, t0
, src
)));
21078 c1
= gen_rtx_EQ (VOIDmode
, cond
, const0_rtx
);
21079 emit_unlikely_jump (c1
, label
);
21081 half
= force_reg (SFmode
, CONST_DOUBLE_FROM_REAL_VALUE (dconsthalf
, SFmode
));
21082 one
= force_reg (SFmode
, CONST_DOUBLE_FROM_REAL_VALUE (dconst1
, SFmode
));
21084 /* halfthree = 1.5 = 1.0 + 0.5 */
21085 emit_insn (gen_rtx_SET (VOIDmode
, halfthree
,
21086 gen_rtx_PLUS (SFmode
, one
, half
)));
21088 /* x0 = rsqrt estimate */
21089 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
21090 gen_rtx_UNSPEC (SFmode
, gen_rtvec (1, src
),
21093 /* y1 = 0.5 * src = 1.5 * src - src -> fewer constants */
21094 emit_insn (gen_rtx_SET (VOIDmode
, y1
,
21095 gen_rtx_MINUS (SFmode
,
21096 gen_rtx_MULT (SFmode
, src
, halfthree
),
21099 /* x1 = x0 * (1.5 - y1 * (x0 * x0)) */
21100 emit_insn (gen_rtx_SET (VOIDmode
, u0
,
21101 gen_rtx_MULT (SFmode
, x0
, x0
)));
21102 emit_insn (gen_rtx_SET (VOIDmode
, v0
,
21103 gen_rtx_MINUS (SFmode
,
21105 gen_rtx_MULT (SFmode
, y1
, u0
))));
21106 emit_insn (gen_rtx_SET (VOIDmode
, x1
,
21107 gen_rtx_MULT (SFmode
, x0
, v0
)));
21109 /* x2 = x1 * (1.5 - y1 * (x1 * x1)) */
21110 emit_insn (gen_rtx_SET (VOIDmode
, u1
,
21111 gen_rtx_MULT (SFmode
, x1
, x1
)));
21112 emit_insn (gen_rtx_SET (VOIDmode
, v1
,
21113 gen_rtx_MINUS (SFmode
,
21115 gen_rtx_MULT (SFmode
, y1
, u1
))));
21116 emit_insn (gen_rtx_SET (VOIDmode
, x2
,
21117 gen_rtx_MULT (SFmode
, x1
, v1
)));
21119 /* dst = x2 * (1.5 - y1 * (x2 * x2)) */
21120 emit_insn (gen_rtx_SET (VOIDmode
, u2
,
21121 gen_rtx_MULT (SFmode
, x2
, x2
)));
21122 emit_insn (gen_rtx_SET (VOIDmode
, v2
,
21123 gen_rtx_MINUS (SFmode
,
21125 gen_rtx_MULT (SFmode
, y1
, u2
))));
21126 emit_insn (gen_rtx_SET (VOIDmode
, dst
,
21127 gen_rtx_MULT (SFmode
, x2
, v2
)));
21129 emit_label (XEXP (label
, 0));
21132 /* Emit popcount intrinsic on TARGET_POPCNTB targets. DST is the
21133 target, and SRC is the argument operand. */
21136 rs6000_emit_popcount (rtx dst
, rtx src
)
21138 enum machine_mode mode
= GET_MODE (dst
);
21141 tmp1
= gen_reg_rtx (mode
);
21143 if (mode
== SImode
)
21145 emit_insn (gen_popcntbsi2 (tmp1
, src
));
21146 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
21148 tmp2
= force_reg (SImode
, tmp2
);
21149 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
21153 emit_insn (gen_popcntbdi2 (tmp1
, src
));
21154 tmp2
= expand_mult (DImode
, tmp1
,
21155 GEN_INT ((HOST_WIDE_INT
)
21156 0x01010101 << 32 | 0x01010101),
21158 tmp2
= force_reg (DImode
, tmp2
);
21159 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
21164 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
21165 target, and SRC is the argument operand. */
21168 rs6000_emit_parity (rtx dst
, rtx src
)
21170 enum machine_mode mode
= GET_MODE (dst
);
21173 tmp
= gen_reg_rtx (mode
);
21174 if (mode
== SImode
)
21176 /* Is mult+shift >= shift+xor+shift+xor? */
21177 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
21179 rtx tmp1
, tmp2
, tmp3
, tmp4
;
21181 tmp1
= gen_reg_rtx (SImode
);
21182 emit_insn (gen_popcntbsi2 (tmp1
, src
));
21184 tmp2
= gen_reg_rtx (SImode
);
21185 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
21186 tmp3
= gen_reg_rtx (SImode
);
21187 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
21189 tmp4
= gen_reg_rtx (SImode
);
21190 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
21191 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
21194 rs6000_emit_popcount (tmp
, src
);
21195 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
21199 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
21200 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
21202 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
21204 tmp1
= gen_reg_rtx (DImode
);
21205 emit_insn (gen_popcntbdi2 (tmp1
, src
));
21207 tmp2
= gen_reg_rtx (DImode
);
21208 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
21209 tmp3
= gen_reg_rtx (DImode
);
21210 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
21212 tmp4
= gen_reg_rtx (DImode
);
21213 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
21214 tmp5
= gen_reg_rtx (DImode
);
21215 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
21217 tmp6
= gen_reg_rtx (DImode
);
21218 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
21219 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
21222 rs6000_emit_popcount (tmp
, src
);
21223 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
21227 /* Return an RTX representing where to find the function value of a
21228 function returning MODE. */
21230 rs6000_complex_function_value (enum machine_mode mode
)
21232 unsigned int regno
;
21234 enum machine_mode inner
= GET_MODE_INNER (mode
);
21235 unsigned int inner_bytes
= GET_MODE_SIZE (inner
);
21237 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
21238 regno
= FP_ARG_RETURN
;
21241 regno
= GP_ARG_RETURN
;
21243 /* 32-bit is OK since it'll go in r3/r4. */
21244 if (TARGET_32BIT
&& inner_bytes
>= 4)
21245 return gen_rtx_REG (mode
, regno
);
21248 if (inner_bytes
>= 8)
21249 return gen_rtx_REG (mode
, regno
);
21251 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
21253 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
21254 GEN_INT (inner_bytes
));
21255 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
21258 /* Define how to find the value returned by a function.
21259 VALTYPE is the data type of the value (as a tree).
21260 If the precise function being called is known, FUNC is its FUNCTION_DECL;
21261 otherwise, FUNC is 0.
21263 On the SPE, both FPs and vectors are returned in r3.
21265 On RS/6000 an integer value is in r3 and a floating-point value is in
21266 fp1, unless -msoft-float. */
21269 rs6000_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
21271 enum machine_mode mode
;
21272 unsigned int regno
;
21274 /* Special handling for structs in darwin64. */
21275 if (rs6000_darwin64_abi
21276 && TYPE_MODE (valtype
) == BLKmode
21277 && TREE_CODE (valtype
) == RECORD_TYPE
21278 && int_size_in_bytes (valtype
) > 0)
21280 CUMULATIVE_ARGS valcum
;
21284 valcum
.fregno
= FP_ARG_MIN_REG
;
21285 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
21286 /* Do a trial code generation as if this were going to be passed as
21287 an argument; if any part goes in memory, we return NULL. */
21288 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, 1, true);
21291 /* Otherwise fall through to standard ABI rules. */
21294 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DImode
)
21296 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
21297 return gen_rtx_PARALLEL (DImode
,
21299 gen_rtx_EXPR_LIST (VOIDmode
,
21300 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
21302 gen_rtx_EXPR_LIST (VOIDmode
,
21303 gen_rtx_REG (SImode
,
21304 GP_ARG_RETURN
+ 1),
21307 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DCmode
)
21309 return gen_rtx_PARALLEL (DCmode
,
21311 gen_rtx_EXPR_LIST (VOIDmode
,
21312 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
21314 gen_rtx_EXPR_LIST (VOIDmode
,
21315 gen_rtx_REG (SImode
,
21316 GP_ARG_RETURN
+ 1),
21318 gen_rtx_EXPR_LIST (VOIDmode
,
21319 gen_rtx_REG (SImode
,
21320 GP_ARG_RETURN
+ 2),
21322 gen_rtx_EXPR_LIST (VOIDmode
,
21323 gen_rtx_REG (SImode
,
21324 GP_ARG_RETURN
+ 3),
21328 mode
= TYPE_MODE (valtype
);
21329 if ((INTEGRAL_TYPE_P (valtype
) && GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
)
21330 || POINTER_TYPE_P (valtype
))
21331 mode
= TARGET_32BIT
? SImode
: DImode
;
21333 if (DECIMAL_FLOAT_MODE_P (mode
))
21335 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
21340 gcc_unreachable ();
21342 regno
= GP_ARG_RETURN
;
21345 regno
= FP_ARG_RETURN
;
21348 /* Use f2:f3 specified by the ABI. */
21349 regno
= FP_ARG_RETURN
+ 1;
21354 regno
= GP_ARG_RETURN
;
21356 else if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
21357 regno
= FP_ARG_RETURN
;
21358 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
21359 && targetm
.calls
.split_complex_arg
)
21360 return rs6000_complex_function_value (mode
);
21361 else if (TREE_CODE (valtype
) == VECTOR_TYPE
21362 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
21363 && ALTIVEC_VECTOR_MODE (mode
))
21364 regno
= ALTIVEC_ARG_RETURN
;
21365 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
21366 && (mode
== DFmode
|| mode
== DCmode
21367 || mode
== TFmode
|| mode
== TCmode
))
21368 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
21370 regno
= GP_ARG_RETURN
;
21372 return gen_rtx_REG (mode
, regno
);
21375 /* Define how to find the value returned by a library function
21376 assuming the value has mode MODE. */
21378 rs6000_libcall_value (enum machine_mode mode
)
21380 unsigned int regno
;
21382 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
21384 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
21385 return gen_rtx_PARALLEL (DImode
,
21387 gen_rtx_EXPR_LIST (VOIDmode
,
21388 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
21390 gen_rtx_EXPR_LIST (VOIDmode
,
21391 gen_rtx_REG (SImode
,
21392 GP_ARG_RETURN
+ 1),
21396 if (DECIMAL_FLOAT_MODE_P (mode
))
21398 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
21403 gcc_unreachable ();
21405 regno
= GP_ARG_RETURN
;
21408 regno
= FP_ARG_RETURN
;
21411 /* Use f2:f3 specified by the ABI. */
21412 regno
= FP_ARG_RETURN
+ 1;
21417 regno
= GP_ARG_RETURN
;
21419 else if (SCALAR_FLOAT_MODE_P (mode
)
21420 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
21421 regno
= FP_ARG_RETURN
;
21422 else if (ALTIVEC_VECTOR_MODE (mode
)
21423 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
21424 regno
= ALTIVEC_ARG_RETURN
;
21425 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
21426 return rs6000_complex_function_value (mode
);
21427 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
21428 && (mode
== DFmode
|| mode
== DCmode
21429 || mode
== TFmode
|| mode
== TCmode
))
21430 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
21432 regno
= GP_ARG_RETURN
;
21434 return gen_rtx_REG (mode
, regno
);
21437 /* Define the offset between two registers, FROM to be eliminated and its
21438 replacement TO, at the start of a routine. */
21440 rs6000_initial_elimination_offset (int from
, int to
)
21442 rs6000_stack_t
*info
= rs6000_stack_info ();
21443 HOST_WIDE_INT offset
;
21445 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
21446 offset
= info
->push_p
? 0 : -info
->total_size
;
21447 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
21449 offset
= info
->push_p
? 0 : -info
->total_size
;
21450 if (FRAME_GROWS_DOWNWARD
)
21451 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
21453 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
21454 offset
= FRAME_GROWS_DOWNWARD
21455 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
21457 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
21458 offset
= info
->total_size
;
21459 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
21460 offset
= info
->push_p
? info
->total_size
: 0;
21461 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
21464 gcc_unreachable ();
21469 /* Return true if TYPE is a SPE or AltiVec opaque type. */
21472 rs6000_is_opaque_type (const_tree type
)
21474 return (type
== opaque_V2SI_type_node
21475 || type
== opaque_V2SF_type_node
21476 || type
== opaque_p_V2SI_type_node
21477 || type
== opaque_V4SI_type_node
);
21481 rs6000_dwarf_register_span (rtx reg
)
21486 && (SPE_VECTOR_MODE (GET_MODE (reg
))
21487 || (TARGET_E500_DOUBLE
&& GET_MODE (reg
) == DFmode
)))
21492 regno
= REGNO (reg
);
21494 /* The duality of the SPE register size wreaks all kinds of havoc.
21495 This is a way of distinguishing r0 in 32-bits from r0 in
21498 gen_rtx_PARALLEL (VOIDmode
,
21501 gen_rtx_REG (SImode
, regno
+ 1200),
21502 gen_rtx_REG (SImode
, regno
))
21504 gen_rtx_REG (SImode
, regno
),
21505 gen_rtx_REG (SImode
, regno
+ 1200)));
21508 /* Fill in sizes for SPE register high parts in table used by unwinder. */
21511 rs6000_init_dwarf_reg_sizes_extra (tree address
)
21516 enum machine_mode mode
= TYPE_MODE (char_type_node
);
21517 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, 0);
21518 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
21519 rtx value
= gen_int_mode (4, mode
);
21521 for (i
= 1201; i
< 1232; i
++)
21523 int column
= DWARF_REG_TO_UNWIND_COLUMN (i
);
21524 HOST_WIDE_INT offset
21525 = DWARF_FRAME_REGNUM (column
) * GET_MODE_SIZE (mode
);
21527 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
21532 /* Map internal gcc register numbers to DWARF2 register numbers. */
21535 rs6000_dbx_register_number (unsigned int regno
)
21537 if (regno
<= 63 || write_symbols
!= DWARF2_DEBUG
)
21539 if (regno
== MQ_REGNO
)
21541 if (regno
== LR_REGNO
)
21543 if (regno
== CTR_REGNO
)
21545 if (CR_REGNO_P (regno
))
21546 return regno
- CR0_REGNO
+ 86;
21547 if (regno
== XER_REGNO
)
21549 if (ALTIVEC_REGNO_P (regno
))
21550 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
21551 if (regno
== VRSAVE_REGNO
)
21553 if (regno
== VSCR_REGNO
)
21555 if (regno
== SPE_ACC_REGNO
)
21557 if (regno
== SPEFSCR_REGNO
)
21559 /* SPE high reg number. We get these values of regno from
21560 rs6000_dwarf_register_span. */
21561 gcc_assert (regno
>= 1200 && regno
< 1232);
21565 /* target hook eh_return_filter_mode */
21566 static enum machine_mode
21567 rs6000_eh_return_filter_mode (void)
21569 return TARGET_32BIT
? SImode
: word_mode
;
21572 /* Target hook for scalar_mode_supported_p. */
21574 rs6000_scalar_mode_supported_p (enum machine_mode mode
)
21576 if (DECIMAL_FLOAT_MODE_P (mode
))
21579 return default_scalar_mode_supported_p (mode
);
21582 /* Target hook for vector_mode_supported_p. */
21584 rs6000_vector_mode_supported_p (enum machine_mode mode
)
21587 if (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (mode
))
21590 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
21593 else if (TARGET_ALTIVEC
&& ALTIVEC_VECTOR_MODE (mode
))
21600 /* Target hook for invalid_arg_for_unprototyped_fn. */
21601 static const char *
21602 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
21604 return (!rs6000_darwin64_abi
21606 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
21607 && (funcdecl
== NULL_TREE
21608 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
21609 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
21610 ? N_("AltiVec argument passed to unprototyped function")
21614 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
21615 setup by using __stack_chk_fail_local hidden function instead of
21616 calling __stack_chk_fail directly. Otherwise it is better to call
21617 __stack_chk_fail directly. */
21620 rs6000_stack_protect_fail (void)
21622 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
21623 ? default_hidden_stack_protect_fail ()
21624 : default_external_stack_protect_fail ();
21627 #include "gt-rs6000.h"