| blob | a515980ea74203e787376cf1241703fc5b54e13b |
1 ;;- Machine description for HP PA-RISC architecture for GCC compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 ;; 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 ;; Contributed by the Center for Software Science at the University
5 ;; of Utah.
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; any later version.
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;; This gcc Version 2 machine description is inspired by sparc.md and
24 ;; mips.md.
26 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
28 ;; Uses of UNSPEC in this file:
30 (define_constants
31 [(UNSPEC_CFFC 0) ; canonicalize_funcptr_for_compare
32 (UNSPEC_GOTO 1) ; indirect_goto
33 (UNSPEC_DLTIND14R 2) ;
34 (UNSPEC_TP 3)
35 (UNSPEC_TLSGD 4)
36 (UNSPEC_TLSLDM 5)
37 (UNSPEC_TLSLDO 6)
38 (UNSPEC_TLSLDBASE 7)
39 (UNSPEC_TLSIE 8)
40 (UNSPEC_TLSLE 9)
41 (UNSPEC_TLSGD_PIC 10)
42 (UNSPEC_TLSLDM_PIC 11)
43 (UNSPEC_TLSIE_PIC 12)
44 ])
46 ;; UNSPEC_VOLATILE:
48 (define_constants
49 [(UNSPECV_BLOCKAGE 0) ; blockage
50 (UNSPECV_DCACHE 1) ; dcacheflush
51 (UNSPECV_ICACHE 2) ; icacheflush
52 (UNSPECV_OPC 3) ; outline_prologue_call
53 (UNSPECV_OEC 4) ; outline_epilogue_call
54 (UNSPECV_LONGJMP 5) ; builtin_longjmp
55 ])
57 ;; Maximum pc-relative branch offsets.
59 ;; These numbers are a bit smaller than the maximum allowable offsets
60 ;; so that a few instructions may be inserted before the actual branch.
62 (define_constants
63 [(MAX_12BIT_OFFSET 8184) ; 12-bit branch
64 (MAX_17BIT_OFFSET 262100) ; 17-bit branch
65 ])
67 ;; Insn type. Used to default other attribute values.
69 ;; type "unary" insns have one input operand (1) and one output operand (0)
70 ;; type "binary" insns have two input operands (1,2) and one output (0)
72 (define_attr "type"
73 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch,fpstore_load,store_fpload"
74 (const_string "binary"))
76 (define_attr "pa_combine_type"
77 "fmpy,faddsub,uncond_branch,addmove,none"
78 (const_string "none"))
80 ;; Processor type (for scheduling, not code generation) -- this attribute
81 ;; must exactly match the processor_type enumeration in pa.h.
82 ;;
83 ;; FIXME: Add 800 scheduling for completeness?
85 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
87 ;; Length (in # of bytes).
88 (define_attr "length" ""
89 (cond [(eq_attr "type" "load,fpload")
90 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
91 (const_int 8) (const_int 4))
93 (eq_attr "type" "store,fpstore")
94 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
95 (const_int 8) (const_int 4))
97 (eq_attr "type" "binary,shift,nullshift")
98 (if_then_else (match_operand 2 "arith_operand" "")
99 (const_int 4) (const_int 12))
101 (eq_attr "type" "move,unary,shift,nullshift")
102 (if_then_else (match_operand 1 "arith_operand" "")
103 (const_int 4) (const_int 8))]
105 (const_int 4)))
107 (define_asm_attributes
108 [(set_attr "length" "4")
109 (set_attr "type" "multi")])
111 ;; Attributes for instruction and branch scheduling
113 ;; For conditional branches.
114 (define_attr "in_branch_delay" "false,true"
115 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
116 (eq_attr "length" "4"))
117 (const_string "true")
118 (const_string "false")))
120 ;; Disallow instructions which use the FPU since they will tie up the FPU
121 ;; even if the instruction is nullified.
122 (define_attr "in_nullified_branch_delay" "false,true"
123 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
124 (eq_attr "length" "4"))
125 (const_string "true")
126 (const_string "false")))
128 ;; For calls and millicode calls. Allow unconditional branches in the
129 ;; delay slot.
130 (define_attr "in_call_delay" "false,true"
131 (cond [(and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
132 (eq_attr "length" "4"))
133 (const_string "true")
134 (eq_attr "type" "uncond_branch")
135 (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
136 (const_int 0))
137 (const_string "true")
138 (const_string "false"))]
139 (const_string "false")))
142 ;; Call delay slot description.
143 (define_delay (eq_attr "type" "call")
144 [(eq_attr "in_call_delay" "true") (nil) (nil)])
146 ;; Millicode call delay slot description.
147 (define_delay (eq_attr "type" "milli")
148 [(eq_attr "in_call_delay" "true") (nil) (nil)])
150 ;; Return and other similar instructions.
151 (define_delay (eq_attr "type" "btable_branch,branch,parallel_branch")
152 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
154 ;; Floating point conditional branch delay slot description.
155 (define_delay (eq_attr "type" "fbranch")
156 [(eq_attr "in_branch_delay" "true")
157 (eq_attr "in_nullified_branch_delay" "true")
158 (nil)])
160 ;; Integer conditional branch delay slot description.
161 ;; Nullification of conditional branches on the PA is dependent on the
162 ;; direction of the branch. Forward branches nullify true and
163 ;; backward branches nullify false. If the direction is unknown
164 ;; then nullification is not allowed.
165 (define_delay (eq_attr "type" "cbranch")
166 [(eq_attr "in_branch_delay" "true")
167 (and (eq_attr "in_nullified_branch_delay" "true")
168 (attr_flag "forward"))
169 (and (eq_attr "in_nullified_branch_delay" "true")
170 (attr_flag "backward"))])
172 (define_delay (and (eq_attr "type" "uncond_branch")
173 (eq (symbol_ref "following_call (insn)")
174 (const_int 0)))
175 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
177 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
178 ;; load: 2, fpload: 3
179 ;; store, fpstore: 3, no D-cache operations should be scheduled.
181 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
182 ;; Timings:
183 ;; Instruction Time Unit Minimum Distance (unit contention)
184 ;; fcpy 3 ALU 2
185 ;; fabs 3 ALU 2
186 ;; fadd 3 ALU 2
187 ;; fsub 3 ALU 2
188 ;; fcmp 3 ALU 2
189 ;; fcnv 3 ALU 2
190 ;; fmpyadd 3 ALU,MPY 2
191 ;; fmpysub 3 ALU,MPY 2
192 ;; fmpycfxt 3 ALU,MPY 2
193 ;; fmpy 3 MPY 2
194 ;; fmpyi 3 MPY 2
195 ;; fdiv,sgl 10 MPY 10
196 ;; fdiv,dbl 12 MPY 12
197 ;; fsqrt,sgl 14 MPY 14
198 ;; fsqrt,dbl 18 MPY 18
199 ;;
200 ;; We don't model fmpyadd/fmpysub properly as those instructions
201 ;; keep both the FP ALU and MPY units busy. Given that these
202 ;; processors are obsolete, I'm not going to spend the time to
203 ;; model those instructions correctly.
205 (define_automaton "pa700")
206 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
208 (define_insn_reservation "W0" 4
209 (and (eq_attr "type" "fpcc")
210 (eq_attr "cpu" "700"))
211 "fpalu_700*2")
213 (define_insn_reservation "W1" 3
214 (and (eq_attr "type" "fpalu")
215 (eq_attr "cpu" "700"))
216 "fpalu_700*2")
218 (define_insn_reservation "W2" 3
219 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
220 (eq_attr "cpu" "700"))
221 "fpmpy_700*2")
223 (define_insn_reservation "W3" 10
224 (and (eq_attr "type" "fpdivsgl")
225 (eq_attr "cpu" "700"))
226 "fpmpy_700*10")
228 (define_insn_reservation "W4" 12
229 (and (eq_attr "type" "fpdivdbl")
230 (eq_attr "cpu" "700"))
231 "fpmpy_700*12")
233 (define_insn_reservation "W5" 14
234 (and (eq_attr "type" "fpsqrtsgl")
235 (eq_attr "cpu" "700"))
236 "fpmpy_700*14")
238 (define_insn_reservation "W6" 18
239 (and (eq_attr "type" "fpsqrtdbl")
240 (eq_attr "cpu" "700"))
241 "fpmpy_700*18")
243 (define_insn_reservation "W7" 2
244 (and (eq_attr "type" "load")
245 (eq_attr "cpu" "700"))
246 "mem_700")
248 (define_insn_reservation "W8" 2
249 (and (eq_attr "type" "fpload")
250 (eq_attr "cpu" "700"))
251 "mem_700")
253 (define_insn_reservation "W9" 3
254 (and (eq_attr "type" "store")
255 (eq_attr "cpu" "700"))
256 "mem_700*3")
258 (define_insn_reservation "W10" 3
259 (and (eq_attr "type" "fpstore")
260 (eq_attr "cpu" "700"))
261 "mem_700*3")
263 (define_insn_reservation "W11" 5
264 (and (eq_attr "type" "fpstore_load")
265 (eq_attr "cpu" "700"))
266 "mem_700*5")
268 (define_insn_reservation "W12" 6
269 (and (eq_attr "type" "store_fpload")
270 (eq_attr "cpu" "700"))
271 "mem_700*6")
273 (define_insn_reservation "W13" 1
274 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore,fpstore_load,store_fpload")
275 (eq_attr "cpu" "700"))
276 "dummy_700")
278 ;; We have a bypass for all computations in the FP unit which feed an
279 ;; FP store as long as the sizes are the same.
280 (define_bypass 2 "W1,W2" "W10,W11" "hppa_fpstore_bypass_p")
281 (define_bypass 9 "W3" "W10,W11" "hppa_fpstore_bypass_p")
282 (define_bypass 11 "W4" "W10,W11" "hppa_fpstore_bypass_p")
283 (define_bypass 13 "W5" "W10,W11" "hppa_fpstore_bypass_p")
284 (define_bypass 17 "W6" "W10,W11" "hppa_fpstore_bypass_p")
286 ;; We have an "anti-bypass" for FP loads which feed an FP store.
287 (define_bypass 4 "W8,W12" "W10,W11" "hppa_fpstore_bypass_p")
289 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
290 ;; floating point computations with non-floating point computations (fp loads
291 ;; and stores are not fp computations).
292 ;;
293 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
294 ;; take two cycles, during which no Dcache operations should be scheduled.
295 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
296 ;; all have the same memory characteristics if one disregards cache misses.
297 ;;
298 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
299 ;; There's no value in modeling the ALU and MUL separately though
300 ;; since there can never be a functional unit conflict given the
301 ;; latency and issue rates for those units.
302 ;;
303 ;; Timings:
304 ;; Instruction Time Unit Minimum Distance (unit contention)
305 ;; fcpy 2 ALU 1
306 ;; fabs 2 ALU 1
307 ;; fadd 2 ALU 1
308 ;; fsub 2 ALU 1
309 ;; fcmp 2 ALU 1
310 ;; fcnv 2 ALU 1
311 ;; fmpyadd 2 ALU,MPY 1
312 ;; fmpysub 2 ALU,MPY 1
313 ;; fmpycfxt 2 ALU,MPY 1
314 ;; fmpy 2 MPY 1
315 ;; fmpyi 2 MPY 1
316 ;; fdiv,sgl 8 DIV 8
317 ;; fdiv,dbl 15 DIV 15
318 ;; fsqrt,sgl 8 DIV 8
319 ;; fsqrt,dbl 15 DIV 15
321 (define_automaton "pa7100")
322 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
324 (define_insn_reservation "X0" 2
325 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
326 (eq_attr "cpu" "7100"))
327 "f_7100,fpmac_7100")
329 (define_insn_reservation "X1" 8
330 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
331 (eq_attr "cpu" "7100"))
332 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
334 (define_insn_reservation "X2" 15
335 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
336 (eq_attr "cpu" "7100"))
337 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
339 (define_insn_reservation "X3" 2
340 (and (eq_attr "type" "load")
341 (eq_attr "cpu" "7100"))
342 "i_7100+mem_7100")
344 (define_insn_reservation "X4" 2
345 (and (eq_attr "type" "fpload")
346 (eq_attr "cpu" "7100"))
347 "i_7100+mem_7100")
349 (define_insn_reservation "X5" 2
350 (and (eq_attr "type" "store")
351 (eq_attr "cpu" "7100"))
352 "i_7100+mem_7100,mem_7100")
354 (define_insn_reservation "X6" 2
355 (and (eq_attr "type" "fpstore")
356 (eq_attr "cpu" "7100"))
357 "i_7100+mem_7100,mem_7100")
359 (define_insn_reservation "X7" 4
360 (and (eq_attr "type" "fpstore_load")
361 (eq_attr "cpu" "7100"))
362 "i_7100+mem_7100,mem_7100*3")
364 (define_insn_reservation "X8" 4
365 (and (eq_attr "type" "store_fpload")
366 (eq_attr "cpu" "7100"))
367 "i_7100+mem_7100,mem_7100*3")
369 (define_insn_reservation "X9" 1
370 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,fpstore_load,store_fpload")
371 (eq_attr "cpu" "7100"))
372 "i_7100")
374 ;; We have a bypass for all computations in the FP unit which feed an
375 ;; FP store as long as the sizes are the same.
376 (define_bypass 1 "X0" "X6,X7" "hppa_fpstore_bypass_p")
377 (define_bypass 7 "X1" "X6,X7" "hppa_fpstore_bypass_p")
378 (define_bypass 14 "X2" "X6,X7" "hppa_fpstore_bypass_p")
380 ;; We have an "anti-bypass" for FP loads which feed an FP store.
381 (define_bypass 3 "X4,X8" "X6,X7" "hppa_fpstore_bypass_p")
383 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
384 ;; There's no value in modeling the ALU and MUL separately though
385 ;; since there can never be a functional unit conflict that
386 ;; can be avoided given the latency, issue rates and mandatory
387 ;; one cycle cpu-wide lock for a double precision fp multiply.
388 ;;
389 ;; Timings:
390 ;; Instruction Time Unit Minimum Distance (unit contention)
391 ;; fcpy 2 ALU 1
392 ;; fabs 2 ALU 1
393 ;; fadd 2 ALU 1
394 ;; fsub 2 ALU 1
395 ;; fcmp 2 ALU 1
396 ;; fcnv 2 ALU 1
397 ;; fmpyadd,sgl 2 ALU,MPY 1
398 ;; fmpyadd,dbl 3 ALU,MPY 2
399 ;; fmpysub,sgl 2 ALU,MPY 1
400 ;; fmpysub,dbl 3 ALU,MPY 2
401 ;; fmpycfxt,sgl 2 ALU,MPY 1
402 ;; fmpycfxt,dbl 3 ALU,MPY 2
403 ;; fmpy,sgl 2 MPY 1
404 ;; fmpy,dbl 3 MPY 2
405 ;; fmpyi 3 MPY 2
406 ;; fdiv,sgl 8 DIV 8
407 ;; fdiv,dbl 15 DIV 15
408 ;; fsqrt,sgl 8 DIV 8
409 ;; fsqrt,dbl 15 DIV 15
410 ;;
411 ;; The PA7200 is just like the PA7100LC except that there is
412 ;; no store-store penalty.
413 ;;
414 ;; The PA7300 is just like the PA7200 except that there is
415 ;; no store-load penalty.
416 ;;
417 ;; Note there are some aspects of the 7100LC we are not modeling
418 ;; at the moment. I'll be reviewing the 7100LC scheduling info
419 ;; shortly and updating this description.
420 ;;
421 ;; load-load pairs
422 ;; store-store pairs
423 ;; other issue modeling
425 (define_automaton "pa7100lc")
426 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
427 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
428 (define_cpu_unit "mem_7100lc" "pa7100lc")
430 ;; Double precision multiplies lock the entire CPU for one
431 ;; cycle. There is no way to avoid this lock and trying to
432 ;; schedule around the lock is pointless and thus there is no
433 ;; value in trying to model this lock.
434 ;;
435 ;; Not modeling the lock allows us to treat fp multiplies just
436 ;; like any other FP alu instruction. It allows for a smaller
437 ;; DFA and may reduce register pressure.
438 (define_insn_reservation "Y0" 2
439 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
440 (eq_attr "cpu" "7100LC,7200,7300"))
441 "f_7100lc,fpmac_7100lc")
443 ;; fp division and sqrt instructions lock the entire CPU for
444 ;; 7 cycles (single precision) or 14 cycles (double precision).
445 ;; There is no way to avoid this lock and trying to schedule
446 ;; around the lock is pointless and thus there is no value in
447 ;; trying to model this lock. Not modeling the lock allows
448 ;; for a smaller DFA and may reduce register pressure.
449 (define_insn_reservation "Y1" 1
450 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
451 (eq_attr "cpu" "7100LC,7200,7300"))
452 "f_7100lc")
454 (define_insn_reservation "Y2" 2
455 (and (eq_attr "type" "load")
456 (eq_attr "cpu" "7100LC,7200,7300"))
457 "i1_7100lc+mem_7100lc")
459 (define_insn_reservation "Y3" 2
460 (and (eq_attr "type" "fpload")
461 (eq_attr "cpu" "7100LC,7200,7300"))
462 "i1_7100lc+mem_7100lc")
464 (define_insn_reservation "Y4" 2
465 (and (eq_attr "type" "store")
466 (eq_attr "cpu" "7100LC"))
467 "i1_7100lc+mem_7100lc,mem_7100lc")
469 (define_insn_reservation "Y5" 2
470 (and (eq_attr "type" "fpstore")
471 (eq_attr "cpu" "7100LC"))
472 "i1_7100lc+mem_7100lc,mem_7100lc")
474 (define_insn_reservation "Y6" 4
475 (and (eq_attr "type" "fpstore_load")
476 (eq_attr "cpu" "7100LC"))
477 "i1_7100lc+mem_7100lc,mem_7100lc*3")
479 (define_insn_reservation "Y7" 4
480 (and (eq_attr "type" "store_fpload")
481 (eq_attr "cpu" "7100LC"))
482 "i1_7100lc+mem_7100lc,mem_7100lc*3")
484 (define_insn_reservation "Y8" 1
485 (and (eq_attr "type" "shift,nullshift")
486 (eq_attr "cpu" "7100LC,7200,7300"))
487 "i1_7100lc")
489 (define_insn_reservation "Y9" 1
490 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
491 (eq_attr "cpu" "7100LC,7200,7300"))
492 "(i0_7100lc|i1_7100lc)")
494 ;; The 7200 has a store-load penalty
495 (define_insn_reservation "Y10" 2
496 (and (eq_attr "type" "store")
497 (eq_attr "cpu" "7200"))
498 "i1_7100lc,mem_7100lc")
500 (define_insn_reservation "Y11" 2
501 (and (eq_attr "type" "fpstore")
502 (eq_attr "cpu" "7200"))
503 "i1_7100lc,mem_7100lc")
505 (define_insn_reservation "Y12" 4
506 (and (eq_attr "type" "fpstore_load")
507 (eq_attr "cpu" "7200"))
508 "i1_7100lc,mem_7100lc,i1_7100lc+mem_7100lc")
510 (define_insn_reservation "Y13" 4
511 (and (eq_attr "type" "store_fpload")
512 (eq_attr "cpu" "7200"))
513 "i1_7100lc,mem_7100lc,i1_7100lc+mem_7100lc")
515 ;; The 7300 has no penalty for store-store or store-load
516 (define_insn_reservation "Y14" 2
517 (and (eq_attr "type" "store")
518 (eq_attr "cpu" "7300"))
519 "i1_7100lc")
521 (define_insn_reservation "Y15" 2
522 (and (eq_attr "type" "fpstore")
523 (eq_attr "cpu" "7300"))
524 "i1_7100lc")
526 (define_insn_reservation "Y16" 4
527 (and (eq_attr "type" "fpstore_load")
528 (eq_attr "cpu" "7300"))
529 "i1_7100lc,i1_7100lc+mem_7100lc")
531 (define_insn_reservation "Y17" 4
532 (and (eq_attr "type" "store_fpload")
533 (eq_attr "cpu" "7300"))
534 "i1_7100lc,i1_7100lc+mem_7100lc")
536 ;; We have an "anti-bypass" for FP loads which feed an FP store.
537 (define_bypass 3 "Y3,Y7,Y13,Y17" "Y5,Y6,Y11,Y12,Y15,Y16" "hppa_fpstore_bypass_p")
539 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
540 ;; traditional architecture.
541 ;;
542 ;; The PA8000 has a large (56) entry reorder buffer that is split between
543 ;; memory and non-memory operations.
544 ;;
545 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
546 ;; the function units, with the exception of branches and multi-output
547 ;; instructions. The PA8000 can retire two non-memory operations per cycle
548 ;; and two memory operations per cycle, only one of which may be a store.
549 ;;
550 ;; Given the large reorder buffer, the processor can hide most latencies.
551 ;; According to HP, they've got the best results by scheduling for retirement
552 ;; bandwidth with limited latency scheduling for floating point operations.
553 ;; Latency for integer operations and memory references is ignored.
554 ;;
555 ;;
556 ;; We claim floating point operations have a 2 cycle latency and are
557 ;; fully pipelined, except for div and sqrt which are not pipelined and
558 ;; take from 17 to 31 cycles to complete.
559 ;;
560 ;; It's worth noting that there is no way to saturate all the functional
561 ;; units on the PA8000 as there is not enough issue bandwidth.
563 (define_automaton "pa8000")
564 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
565 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
566 (define_cpu_unit "store_8000" "pa8000")
567 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
568 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
569 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
570 (define_reservation "im_8000" "im0_8000 | im1_8000")
571 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
572 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
573 (define_reservation "f_8000" "f0_8000 | f1_8000")
574 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
576 ;; We can issue any two memops per cycle, but we can only retire
577 ;; one memory store per cycle. We assume that the reorder buffer
578 ;; will hide any memory latencies per HP's recommendation.
579 (define_insn_reservation "Z0" 0
580 (and
581 (eq_attr "type" "load,fpload")
582 (eq_attr "cpu" "8000"))
583 "im_8000,rm_8000")
585 (define_insn_reservation "Z1" 0
586 (and
587 (eq_attr "type" "store,fpstore")
588 (eq_attr "cpu" "8000"))
589 "im_8000,rm_8000+store_8000")
591 (define_insn_reservation "Z2" 0
592 (and (eq_attr "type" "fpstore_load,store_fpload")
593 (eq_attr "cpu" "8000"))
594 "im_8000,rm_8000+store_8000,im_8000,rm_8000")
596 ;; We can issue and retire two non-memory operations per cycle with
597 ;; a few exceptions (branches). This group catches those we want
598 ;; to assume have zero latency.
599 (define_insn_reservation "Z3" 0
600 (and
601 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl,fpstore_load,store_fpload")
602 (eq_attr "cpu" "8000"))
603 "inm_8000,rnm_8000")
605 ;; Branches use both slots in the non-memory issue and
606 ;; retirement unit.
607 (define_insn_reservation "Z4" 0
608 (and
609 (eq_attr "type" "uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
610 (eq_attr "cpu" "8000"))
611 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
613 ;; We partial latency schedule the floating point units.
614 ;; They can issue/retire two at a time in the non-memory
615 ;; units. We fix their latency at 2 cycles and they
616 ;; are fully pipelined.
617 (define_insn_reservation "Z5" 1
618 (and
619 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
620 (eq_attr "cpu" "8000"))
621 "inm_8000,f_8000,rnm_8000")
623 ;; The fdivsqrt units are not pipelined and have a very long latency.
624 ;; To keep the DFA from exploding, we do not show all the
625 ;; reservations for the divsqrt unit.
626 (define_insn_reservation "Z6" 17
627 (and
628 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
629 (eq_attr "cpu" "8000"))
630 "inm_8000,fdivsqrt_8000*6,rnm_8000")
632 (define_insn_reservation "Z7" 31
633 (and
634 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
635 (eq_attr "cpu" "8000"))
636 "inm_8000,fdivsqrt_8000*6,rnm_8000")
638 ;; Operand and operator predicates and constraints
640 (include "predicates.md")
641 (include "constraints.md")
642 \f
643 ;; Compare instructions.
644 ;; This controls RTL generation and register allocation.
646 ;; We generate RTL for comparisons and branches by having the cmpxx
647 ;; patterns store away the operands. Then, the scc and bcc patterns
648 ;; emit RTL for both the compare and the branch.
649 ;;
651 (define_expand "cmpdi"
652 [(set (reg:CC 0)
653 (compare:CC (match_operand:DI 0 "reg_or_0_operand" "")
654 (match_operand:DI 1 "register_operand" "")))]
655 "TARGET_64BIT"
657 "
658 {
659 hppa_compare_op0 = operands[0];
660 hppa_compare_op1 = operands[1];
661 hppa_branch_type = CMP_SI;
662 DONE;
663 }")
665 (define_expand "cmpsi"
666 [(set (reg:CC 0)
667 (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
668 (match_operand:SI 1 "arith5_operand" "")))]
669 ""
670 "
671 {
672 hppa_compare_op0 = operands[0];
673 hppa_compare_op1 = operands[1];
674 hppa_branch_type = CMP_SI;
675 DONE;
676 }")
678 (define_expand "cmpsf"
679 [(set (reg:CCFP 0)
680 (compare:CCFP (match_operand:SF 0 "reg_or_0_operand" "")
681 (match_operand:SF 1 "reg_or_0_operand" "")))]
682 "! TARGET_SOFT_FLOAT"
683 "
684 {
685 hppa_compare_op0 = operands[0];
686 hppa_compare_op1 = operands[1];
687 hppa_branch_type = CMP_SF;
688 DONE;
689 }")
691 (define_expand "cmpdf"
692 [(set (reg:CCFP 0)
693 (compare:CCFP (match_operand:DF 0 "reg_or_0_operand" "")
694 (match_operand:DF 1 "reg_or_0_operand" "")))]
695 "! TARGET_SOFT_FLOAT"
696 "
697 {
698 hppa_compare_op0 = operands[0];
699 hppa_compare_op1 = operands[1];
700 hppa_branch_type = CMP_DF;
701 DONE;
702 }")
704 (define_insn ""
705 [(set (reg:CCFP 0)
706 (match_operator:CCFP 2 "comparison_operator"
707 [(match_operand:SF 0 "reg_or_0_operand" "fG")
708 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
709 "! TARGET_SOFT_FLOAT"
710 "fcmp,sgl,%Y2 %f0,%f1"
711 [(set_attr "length" "4")
712 (set_attr "type" "fpcc")])
714 (define_insn ""
715 [(set (reg:CCFP 0)
716 (match_operator:CCFP 2 "comparison_operator"
717 [(match_operand:DF 0 "reg_or_0_operand" "fG")
718 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
719 "! TARGET_SOFT_FLOAT"
720 "fcmp,dbl,%Y2 %f0,%f1"
721 [(set_attr "length" "4")
722 (set_attr "type" "fpcc")])
724 ;; Provide a means to emit the movccfp0 and movccfp1 optimization
725 ;; placeholders. This is necessary in rare situations when a
726 ;; placeholder is re-emitted (see PR 8705).
728 (define_expand "movccfp"
729 [(set (reg:CCFP 0)
730 (match_operand 0 "const_int_operand" ""))]
731 "! TARGET_SOFT_FLOAT"
732 "
733 {
734 if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1)
735 FAIL;
736 }")
738 ;; The following patterns are optimization placeholders. In almost
739 ;; all cases, the user of the condition code will be simplified and the
740 ;; original condition code setting insn should be eliminated.
742 (define_insn "*movccfp0"
743 [(set (reg:CCFP 0)
744 (const_int 0))]
745 "! TARGET_SOFT_FLOAT"
746 "fcmp,dbl,= %%fr0,%%fr0"
747 [(set_attr "length" "4")
748 (set_attr "type" "fpcc")])
750 (define_insn "*movccfp1"
751 [(set (reg:CCFP 0)
752 (const_int 1))]
753 "! TARGET_SOFT_FLOAT"
754 "fcmp,dbl,!= %%fr0,%%fr0"
755 [(set_attr "length" "4")
756 (set_attr "type" "fpcc")])
758 ;; scc insns.
760 (define_expand "seq"
761 [(set (match_operand:SI 0 "register_operand" "")
762 (eq:SI (match_dup 1)
763 (match_dup 2)))]
764 "!TARGET_64BIT"
765 "
766 {
767 /* fp scc patterns rarely match, and are not a win on the PA. */
768 if (hppa_branch_type != CMP_SI)
769 FAIL;
770 /* set up operands from compare. */
771 operands[1] = hppa_compare_op0;
772 operands[2] = hppa_compare_op1;
773 /* fall through and generate default code */
774 }")
776 (define_expand "sne"
777 [(set (match_operand:SI 0 "register_operand" "")
778 (ne:SI (match_dup 1)
779 (match_dup 2)))]
780 "!TARGET_64BIT"
781 "
782 {
783 /* fp scc patterns rarely match, and are not a win on the PA. */
784 if (hppa_branch_type != CMP_SI)
785 FAIL;
786 operands[1] = hppa_compare_op0;
787 operands[2] = hppa_compare_op1;
788 }")
790 (define_expand "slt"
791 [(set (match_operand:SI 0 "register_operand" "")
792 (lt:SI (match_dup 1)
793 (match_dup 2)))]
794 "!TARGET_64BIT"
795 "
796 {
797 /* fp scc patterns rarely match, and are not a win on the PA. */
798 if (hppa_branch_type != CMP_SI)
799 FAIL;
800 operands[1] = hppa_compare_op0;
801 operands[2] = hppa_compare_op1;
802 }")
804 (define_expand "sgt"
805 [(set (match_operand:SI 0 "register_operand" "")
806 (gt:SI (match_dup 1)
807 (match_dup 2)))]
808 "!TARGET_64BIT"
809 "
810 {
811 /* fp scc patterns rarely match, and are not a win on the PA. */
812 if (hppa_branch_type != CMP_SI)
813 FAIL;
814 operands[1] = hppa_compare_op0;
815 operands[2] = hppa_compare_op1;
816 }")
818 (define_expand "sle"
819 [(set (match_operand:SI 0 "register_operand" "")
820 (le:SI (match_dup 1)
821 (match_dup 2)))]
822 "!TARGET_64BIT"
823 "
824 {
825 /* fp scc patterns rarely match, and are not a win on the PA. */
826 if (hppa_branch_type != CMP_SI)
827 FAIL;
828 operands[1] = hppa_compare_op0;
829 operands[2] = hppa_compare_op1;
830 }")
832 (define_expand "sge"
833 [(set (match_operand:SI 0 "register_operand" "")
834 (ge:SI (match_dup 1)
835 (match_dup 2)))]
836 "!TARGET_64BIT"
837 "
838 {
839 /* fp scc patterns rarely match, and are not a win on the PA. */
840 if (hppa_branch_type != CMP_SI)
841 FAIL;
842 operands[1] = hppa_compare_op0;
843 operands[2] = hppa_compare_op1;
844 }")
846 (define_expand "sltu"
847 [(set (match_operand:SI 0 "register_operand" "")
848 (ltu:SI (match_dup 1)
849 (match_dup 2)))]
850 "!TARGET_64BIT"
851 "
852 {
853 if (hppa_branch_type != CMP_SI)
854 FAIL;
855 operands[1] = hppa_compare_op0;
856 operands[2] = hppa_compare_op1;
857 }")
859 (define_expand "sgtu"
860 [(set (match_operand:SI 0 "register_operand" "")
861 (gtu:SI (match_dup 1)
862 (match_dup 2)))]
863 "!TARGET_64BIT"
864 "
865 {
866 if (hppa_branch_type != CMP_SI)
867 FAIL;
868 operands[1] = hppa_compare_op0;
869 operands[2] = hppa_compare_op1;
870 }")
872 (define_expand "sleu"
873 [(set (match_operand:SI 0 "register_operand" "")
874 (leu:SI (match_dup 1)
875 (match_dup 2)))]
876 "!TARGET_64BIT"
877 "
878 {
879 if (hppa_branch_type != CMP_SI)
880 FAIL;
881 operands[1] = hppa_compare_op0;
882 operands[2] = hppa_compare_op1;
883 }")
885 (define_expand "sgeu"
886 [(set (match_operand:SI 0 "register_operand" "")
887 (geu:SI (match_dup 1)
888 (match_dup 2)))]
889 "!TARGET_64BIT"
890 "
891 {
892 if (hppa_branch_type != CMP_SI)
893 FAIL;
894 operands[1] = hppa_compare_op0;
895 operands[2] = hppa_compare_op1;
896 }")
898 ;; Instruction canonicalization puts immediate operands second, which
899 ;; is the reverse of what we want.
901 (define_insn "scc"
902 [(set (match_operand:SI 0 "register_operand" "=r")
903 (match_operator:SI 3 "comparison_operator"
904 [(match_operand:SI 1 "register_operand" "r")
905 (match_operand:SI 2 "arith11_operand" "rI")]))]
906 ""
907 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
908 [(set_attr "type" "binary")
909 (set_attr "length" "8")])
911 (define_insn ""
912 [(set (match_operand:DI 0 "register_operand" "=r")
913 (match_operator:DI 3 "comparison_operator"
914 [(match_operand:DI 1 "register_operand" "r")
915 (match_operand:DI 2 "arith11_operand" "rI")]))]
916 "TARGET_64BIT"
917 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
918 [(set_attr "type" "binary")
919 (set_attr "length" "8")])
921 (define_insn "iorscc"
922 [(set (match_operand:SI 0 "register_operand" "=r")
923 (ior:SI (match_operator:SI 3 "comparison_operator"
924 [(match_operand:SI 1 "register_operand" "r")
925 (match_operand:SI 2 "arith11_operand" "rI")])
926 (match_operator:SI 6 "comparison_operator"
927 [(match_operand:SI 4 "register_operand" "r")
928 (match_operand:SI 5 "arith11_operand" "rI")])))]
929 ""
930 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
931 [(set_attr "type" "binary")
932 (set_attr "length" "12")])
934 (define_insn ""
935 [(set (match_operand:DI 0 "register_operand" "=r")
936 (ior:DI (match_operator:DI 3 "comparison_operator"
937 [(match_operand:DI 1 "register_operand" "r")
938 (match_operand:DI 2 "arith11_operand" "rI")])
939 (match_operator:DI 6 "comparison_operator"
940 [(match_operand:DI 4 "register_operand" "r")
941 (match_operand:DI 5 "arith11_operand" "rI")])))]
942 "TARGET_64BIT"
943 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
944 [(set_attr "type" "binary")
945 (set_attr "length" "12")])
947 ;; Combiner patterns for common operations performed with the output
948 ;; from an scc insn (negscc and incscc).
949 (define_insn "negscc"
950 [(set (match_operand:SI 0 "register_operand" "=r")
951 (neg:SI (match_operator:SI 3 "comparison_operator"
952 [(match_operand:SI 1 "register_operand" "r")
953 (match_operand:SI 2 "arith11_operand" "rI")])))]
954 ""
955 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
956 [(set_attr "type" "binary")
957 (set_attr "length" "8")])
959 (define_insn ""
960 [(set (match_operand:DI 0 "register_operand" "=r")
961 (neg:DI (match_operator:DI 3 "comparison_operator"
962 [(match_operand:DI 1 "register_operand" "r")
963 (match_operand:DI 2 "arith11_operand" "rI")])))]
964 "TARGET_64BIT"
965 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
966 [(set_attr "type" "binary")
967 (set_attr "length" "8")])
969 ;; Patterns for adding/subtracting the result of a boolean expression from
970 ;; a register. First we have special patterns that make use of the carry
971 ;; bit, and output only two instructions. For the cases we can't in
972 ;; general do in two instructions, the incscc pattern at the end outputs
973 ;; two or three instructions.
975 (define_insn ""
976 [(set (match_operand:SI 0 "register_operand" "=r")
977 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
978 (match_operand:SI 3 "arith11_operand" "rI"))
979 (match_operand:SI 1 "register_operand" "r")))]
980 ""
981 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
982 [(set_attr "type" "binary")
983 (set_attr "length" "8")])
985 (define_insn ""
986 [(set (match_operand:DI 0 "register_operand" "=r")
987 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
988 (match_operand:DI 3 "arith11_operand" "rI"))
989 (match_operand:DI 1 "register_operand" "r")))]
990 "TARGET_64BIT"
991 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
992 [(set_attr "type" "binary")
993 (set_attr "length" "8")])
995 ; This need only accept registers for op3, since canonicalization
996 ; replaces geu with gtu when op3 is an integer.
997 (define_insn ""
998 [(set (match_operand:SI 0 "register_operand" "=r")
999 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
1000 (match_operand:SI 3 "register_operand" "r"))
1001 (match_operand:SI 1 "register_operand" "r")))]
1002 ""
1003 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
1004 [(set_attr "type" "binary")
1005 (set_attr "length" "8")])
1007 (define_insn ""
1008 [(set (match_operand:DI 0 "register_operand" "=r")
1009 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
1010 (match_operand:DI 3 "register_operand" "r"))
1011 (match_operand:DI 1 "register_operand" "r")))]
1012 "TARGET_64BIT"
1013 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
1014 [(set_attr "type" "binary")
1015 (set_attr "length" "8")])
1017 ; Match only integers for op3 here. This is used as canonical form of the
1018 ; geu pattern when op3 is an integer. Don't match registers since we can't
1019 ; make better code than the general incscc pattern.
1020 (define_insn ""
1021 [(set (match_operand:SI 0 "register_operand" "=r")
1022 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
1023 (match_operand:SI 3 "int11_operand" "I"))
1024 (match_operand:SI 1 "register_operand" "r")))]
1025 ""
1026 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
1027 [(set_attr "type" "binary")
1028 (set_attr "length" "8")])
1030 (define_insn ""
1031 [(set (match_operand:DI 0 "register_operand" "=r")
1032 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
1033 (match_operand:DI 3 "int11_operand" "I"))
1034 (match_operand:DI 1 "register_operand" "r")))]
1035 "TARGET_64BIT"
1036 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
1037 [(set_attr "type" "binary")
1038 (set_attr "length" "8")])
1040 (define_insn "incscc"
1041 [(set (match_operand:SI 0 "register_operand" "=r,r")
1042 (plus:SI (match_operator:SI 4 "comparison_operator"
1043 [(match_operand:SI 2 "register_operand" "r,r")
1044 (match_operand:SI 3 "arith11_operand" "rI,rI")])
1045 (match_operand:SI 1 "register_operand" "0,?r")))]
1046 ""
1047 "@
1048 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
1049 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
1050 [(set_attr "type" "binary,binary")
1051 (set_attr "length" "8,12")])
1053 (define_insn ""
1054 [(set (match_operand:DI 0 "register_operand" "=r,r")
1055 (plus:DI (match_operator:DI 4 "comparison_operator"
1056 [(match_operand:DI 2 "register_operand" "r,r")
1057 (match_operand:DI 3 "arith11_operand" "rI,rI")])
1058 (match_operand:DI 1 "register_operand" "0,?r")))]
1059 "TARGET_64BIT"
1060 "@
1061 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
1062 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
1063 [(set_attr "type" "binary,binary")
1064 (set_attr "length" "8,12")])
1066 (define_insn ""
1067 [(set (match_operand:SI 0 "register_operand" "=r")
1068 (minus:SI (match_operand:SI 1 "register_operand" "r")
1069 (gtu:SI (match_operand:SI 2 "register_operand" "r")
1070 (match_operand:SI 3 "arith11_operand" "rI"))))]
1071 ""
1072 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1073 [(set_attr "type" "binary")
1074 (set_attr "length" "8")])
1076 (define_insn ""
1077 [(set (match_operand:DI 0 "register_operand" "=r")
1078 (minus:DI (match_operand:DI 1 "register_operand" "r")
1079 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1080 (match_operand:DI 3 "arith11_operand" "rI"))))]
1081 "TARGET_64BIT"
1082 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
1083 [(set_attr "type" "binary")
1084 (set_attr "length" "8")])
1086 (define_insn ""
1087 [(set (match_operand:SI 0 "register_operand" "=r")
1088 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1089 (gtu:SI (match_operand:SI 2 "register_operand" "r")
1090 (match_operand:SI 3 "arith11_operand" "rI")))
1091 (match_operand:SI 4 "register_operand" "r")))]
1092 ""
1093 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1094 [(set_attr "type" "binary")
1095 (set_attr "length" "8")])
1097 (define_insn ""
1098 [(set (match_operand:DI 0 "register_operand" "=r")
1099 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1100 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1101 (match_operand:DI 3 "arith11_operand" "rI")))
1102 (match_operand:DI 4 "register_operand" "r")))]
1103 "TARGET_64BIT"
1104 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
1105 [(set_attr "type" "binary")
1106 (set_attr "length" "8")])
1108 ; This need only accept registers for op3, since canonicalization
1109 ; replaces ltu with leu when op3 is an integer.
1110 (define_insn ""
1111 [(set (match_operand:SI 0 "register_operand" "=r")
1112 (minus:SI (match_operand:SI 1 "register_operand" "r")
1113 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1114 (match_operand:SI 3 "register_operand" "r"))))]
1115 ""
1116 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
1117 [(set_attr "type" "binary")
1118 (set_attr "length" "8")])
1120 (define_insn ""
1121 [(set (match_operand:DI 0 "register_operand" "=r")
1122 (minus:DI (match_operand:DI 1 "register_operand" "r")
1123 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1124 (match_operand:DI 3 "register_operand" "r"))))]
1125 "TARGET_64BIT"
1126 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
1127 [(set_attr "type" "binary")
1128 (set_attr "length" "8")])
1130 (define_insn ""
1131 [(set (match_operand:SI 0 "register_operand" "=r")
1132 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1133 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1134 (match_operand:SI 3 "register_operand" "r")))
1135 (match_operand:SI 4 "register_operand" "r")))]
1136 ""
1137 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
1138 [(set_attr "type" "binary")
1139 (set_attr "length" "8")])
1141 (define_insn ""
1142 [(set (match_operand:DI 0 "register_operand" "=r")
1143 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1144 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1145 (match_operand:DI 3 "register_operand" "r")))
1146 (match_operand:DI 4 "register_operand" "r")))]
1147 "TARGET_64BIT"
1148 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
1149 [(set_attr "type" "binary")
1150 (set_attr "length" "8")])
1152 ; Match only integers for op3 here. This is used as canonical form of the
1153 ; ltu pattern when op3 is an integer. Don't match registers since we can't
1154 ; make better code than the general incscc pattern.
1155 (define_insn ""
1156 [(set (match_operand:SI 0 "register_operand" "=r")
1157 (minus:SI (match_operand:SI 1 "register_operand" "r")
1158 (leu:SI (match_operand:SI 2 "register_operand" "r")
1159 (match_operand:SI 3 "int11_operand" "I"))))]
1160 ""
1161 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1162 [(set_attr "type" "binary")
1163 (set_attr "length" "8")])
1165 (define_insn ""
1166 [(set (match_operand:DI 0 "register_operand" "=r")
1167 (minus:DI (match_operand:DI 1 "register_operand" "r")
1168 (leu:DI (match_operand:DI 2 "register_operand" "r")
1169 (match_operand:DI 3 "int11_operand" "I"))))]
1170 "TARGET_64BIT"
1171 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
1172 [(set_attr "type" "binary")
1173 (set_attr "length" "8")])
1175 (define_insn ""
1176 [(set (match_operand:SI 0 "register_operand" "=r")
1177 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1178 (leu:SI (match_operand:SI 2 "register_operand" "r")
1179 (match_operand:SI 3 "int11_operand" "I")))
1180 (match_operand:SI 4 "register_operand" "r")))]
1181 ""
1182 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1183 [(set_attr "type" "binary")
1184 (set_attr "length" "8")])
1186 (define_insn ""
1187 [(set (match_operand:DI 0 "register_operand" "=r")
1188 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1189 (leu:DI (match_operand:DI 2 "register_operand" "r")
1190 (match_operand:DI 3 "int11_operand" "I")))
1191 (match_operand:DI 4 "register_operand" "r")))]
1192 "TARGET_64BIT"
1193 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
1194 [(set_attr "type" "binary")
1195 (set_attr "length" "8")])
1197 (define_insn "decscc"
1198 [(set (match_operand:SI 0 "register_operand" "=r,r")
1199 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1200 (match_operator:SI 4 "comparison_operator"
1201 [(match_operand:SI 2 "register_operand" "r,r")
1202 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1203 ""
1204 "@
1205 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1206 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1207 [(set_attr "type" "binary,binary")
1208 (set_attr "length" "8,12")])
1210 (define_insn ""
1211 [(set (match_operand:DI 0 "register_operand" "=r,r")
1212 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1213 (match_operator:DI 4 "comparison_operator"
1214 [(match_operand:DI 2 "register_operand" "r,r")
1215 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1216 "TARGET_64BIT"
1217 "@
1218 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1219 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1220 [(set_attr "type" "binary,binary")
1221 (set_attr "length" "8,12")])
1223 ; Patterns for max and min. (There is no need for an earlyclobber in the
1224 ; last alternative since the middle alternative will match if op0 == op1.)
1226 (define_insn "sminsi3"
1227 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1228 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1229 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1230 ""
1231 "@
1232 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1233 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1234 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1235 [(set_attr "type" "multi,multi,multi")
1236 (set_attr "length" "8,8,8")])
1238 (define_insn "smindi3"
1239 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1240 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1241 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1242 "TARGET_64BIT"
1243 "@
1244 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1245 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1246 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1247 [(set_attr "type" "multi,multi,multi")
1248 (set_attr "length" "8,8,8")])
1250 (define_insn "uminsi3"
1251 [(set (match_operand:SI 0 "register_operand" "=r,r")
1252 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1253 (match_operand:SI 2 "arith11_operand" "r,I")))]
1254 ""
1255 "@
1256 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1257 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1258 [(set_attr "type" "multi,multi")
1259 (set_attr "length" "8,8")])
1261 (define_insn "umindi3"
1262 [(set (match_operand:DI 0 "register_operand" "=r,r")
1263 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1264 (match_operand:DI 2 "arith11_operand" "r,I")))]
1265 "TARGET_64BIT"
1266 "@
1267 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1268 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1269 [(set_attr "type" "multi,multi")
1270 (set_attr "length" "8,8")])
1272 (define_insn "smaxsi3"
1273 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1274 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1275 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1276 ""
1277 "@
1278 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1279 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1280 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1281 [(set_attr "type" "multi,multi,multi")
1282 (set_attr "length" "8,8,8")])
1284 (define_insn "smaxdi3"
1285 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1286 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1287 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1288 "TARGET_64BIT"
1289 "@
1290 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1291 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1292 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1293 [(set_attr "type" "multi,multi,multi")
1294 (set_attr "length" "8,8,8")])
1296 (define_insn "umaxsi3"
1297 [(set (match_operand:SI 0 "register_operand" "=r,r")
1298 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1299 (match_operand:SI 2 "arith11_operand" "r,I")))]
1300 ""
1301 "@
1302 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1303 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1304 [(set_attr "type" "multi,multi")
1305 (set_attr "length" "8,8")])
1307 (define_insn "umaxdi3"
1308 [(set (match_operand:DI 0 "register_operand" "=r,r")
1309 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1310 (match_operand:DI 2 "arith11_operand" "r,I")))]
1311 "TARGET_64BIT"
1312 "@
1313 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1314 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1315 [(set_attr "type" "multi,multi")
1316 (set_attr "length" "8,8")])
1318 (define_insn "abssi2"
1319 [(set (match_operand:SI 0 "register_operand" "=r")
1320 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1321 ""
1322 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1323 [(set_attr "type" "multi")
1324 (set_attr "length" "8")])
1326 (define_insn "absdi2"
1327 [(set (match_operand:DI 0 "register_operand" "=r")
1328 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1329 "TARGET_64BIT"
1330 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1331 [(set_attr "type" "multi")
1332 (set_attr "length" "8")])
1334 ;;; Experimental conditional move patterns
1336 (define_expand "movsicc"
1337 [(set (match_operand:SI 0 "register_operand" "")
1338 (if_then_else:SI
1339 (match_operator 1 "comparison_operator"
1340 [(match_dup 4)
1341 (match_dup 5)])
1342 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1343 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1344 ""
1345 "
1346 {
1347 enum rtx_code code = GET_CODE (operands[1]);
1349 if (hppa_branch_type != CMP_SI)
1350 FAIL;
1352 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1353 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1354 FAIL;
1356 /* operands[1] is currently the result of compare_from_rtx. We want to
1357 emit a compare of the original operands. */
1358 operands[1] = gen_rtx_fmt_ee (code, SImode, hppa_compare_op0, hppa_compare_op1);
1359 operands[4] = hppa_compare_op0;
1360 operands[5] = hppa_compare_op1;
1361 }")
1363 ;; We used to accept any register for op1.
1364 ;;
1365 ;; However, it loses sometimes because the compiler will end up using
1366 ;; different registers for op0 and op1 in some critical cases. local-alloc
1367 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1368 ;;
1369 ;; If/when global register allocation supports tying we should allow any
1370 ;; register for op1 again.
1371 (define_insn ""
1372 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1373 (if_then_else:SI
1374 (match_operator 2 "comparison_operator"
1375 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1376 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1377 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1378 (const_int 0)))]
1379 ""
1380 "@
1381 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1382 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1383 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1384 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1385 [(set_attr "type" "multi,multi,multi,nullshift")
1386 (set_attr "length" "8,8,8,8")])
1388 (define_insn ""
1389 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1390 (if_then_else:SI
1391 (match_operator 5 "comparison_operator"
1392 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1393 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1394 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1395 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1396 ""
1397 "@
1398 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1399 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1400 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1401 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1402 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1403 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1404 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1405 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1406 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1407 (set_attr "length" "8,8,8,8,8,8,8,8")])
1409 (define_expand "movdicc"
1410 [(set (match_operand:DI 0 "register_operand" "")
1411 (if_then_else:DI
1412 (match_operator 1 "comparison_operator"
1413 [(match_dup 4)
1414 (match_dup 5)])
1415 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1416 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1417 "TARGET_64BIT"
1418 "
1419 {
1420 enum rtx_code code = GET_CODE (operands[1]);
1422 if (hppa_branch_type != CMP_SI)
1423 FAIL;
1425 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1426 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1427 FAIL;
1429 /* operands[1] is currently the result of compare_from_rtx. We want to
1430 emit a compare of the original operands. */
1431 operands[1] = gen_rtx_fmt_ee (code, DImode, hppa_compare_op0, hppa_compare_op1);
1432 operands[4] = hppa_compare_op0;
1433 operands[5] = hppa_compare_op1;
1434 }")
1436 ; We need the first constraint alternative in order to avoid
1437 ; earlyclobbers on all other alternatives.
1438 (define_insn ""
1439 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1440 (if_then_else:DI
1441 (match_operator 2 "comparison_operator"
1442 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1443 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1444 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1445 (const_int 0)))]
1446 "TARGET_64BIT"
1447 "@
1448 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1449 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1450 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1451 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1452 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1453 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1454 (set_attr "length" "8,8,8,8,8")])
1456 (define_insn ""
1457 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1458 (if_then_else:DI
1459 (match_operator 5 "comparison_operator"
1460 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1461 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1462 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1463 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1464 "TARGET_64BIT"
1465 "@
1466 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1467 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1468 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1469 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1470 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1471 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1472 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1473 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1474 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1475 (set_attr "length" "8,8,8,8,8,8,8,8")])
1477 ;; Conditional Branches
1479 (define_expand "beq"
1480 [(set (pc)
1481 (if_then_else (eq (match_dup 1) (match_dup 2))
1482 (label_ref (match_operand 0 "" ""))
1483 (pc)))]
1484 ""
1485 "
1486 {
1487 if (hppa_branch_type != CMP_SI)
1488 {
1489 emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
1490 emit_bcond_fp (NE, operands[0]);
1491 DONE;
1492 }
1493 /* set up operands from compare. */
1494 operands[1] = hppa_compare_op0;
1495 operands[2] = hppa_compare_op1;
1496 /* fall through and generate default code */
1497 }")
1499 (define_expand "bne"
1500 [(set (pc)
1501 (if_then_else (ne (match_dup 1) (match_dup 2))
1502 (label_ref (match_operand 0 "" ""))
1503 (pc)))]
1504 ""
1505 "
1506 {
1507 if (hppa_branch_type != CMP_SI)
1508 {
1509 emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
1510 emit_bcond_fp (NE, operands[0]);
1511 DONE;
1512 }
1513 operands[1] = hppa_compare_op0;
1514 operands[2] = hppa_compare_op1;
1515 }")
1517 (define_expand "bgt"
1518 [(set (pc)
1519 (if_then_else (gt (match_dup 1) (match_dup 2))
1520 (label_ref (match_operand 0 "" ""))
1521 (pc)))]
1522 ""
1523 "
1524 {
1525 if (hppa_branch_type != CMP_SI)
1526 {
1527 emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
1528 emit_bcond_fp (NE, operands[0]);
1529 DONE;
1530 }
1531 operands[1] = hppa_compare_op0;
1532 operands[2] = hppa_compare_op1;
1533 }")
1535 (define_expand "blt"
1536 [(set (pc)
1537 (if_then_else (lt (match_dup 1) (match_dup 2))
1538 (label_ref (match_operand 0 "" ""))
1539 (pc)))]
1540 ""
1541 "
1542 {
1543 if (hppa_branch_type != CMP_SI)
1544 {
1545 emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
1546 emit_bcond_fp (NE, operands[0]);
1547 DONE;
1548 }
1549 operands[1] = hppa_compare_op0;
1550 operands[2] = hppa_compare_op1;
1551 }")
1553 (define_expand "bge"
1554 [(set (pc)
1555 (if_then_else (ge (match_dup 1) (match_dup 2))
1556 (label_ref (match_operand 0 "" ""))
1557 (pc)))]
1558 ""
1559 "
1560 {
1561 if (hppa_branch_type != CMP_SI)
1562 {
1563 emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
1564 emit_bcond_fp (NE, operands[0]);
1565 DONE;
1566 }
1567 operands[1] = hppa_compare_op0;
1568 operands[2] = hppa_compare_op1;
1569 }")
1571 (define_expand "ble"
1572 [(set (pc)
1573 (if_then_else (le (match_dup 1) (match_dup 2))
1574 (label_ref (match_operand 0 "" ""))
1575 (pc)))]
1576 ""
1577 "
1578 {
1579 if (hppa_branch_type != CMP_SI)
1580 {
1581 emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
1582 emit_bcond_fp (NE, operands[0]);
1583 DONE;
1584 }
1585 operands[1] = hppa_compare_op0;
1586 operands[2] = hppa_compare_op1;
1587 }")
1589 (define_expand "bgtu"
1590 [(set (pc)
1591 (if_then_else (gtu (match_dup 1) (match_dup 2))
1592 (label_ref (match_operand 0 "" ""))
1593 (pc)))]
1594 ""
1595 "
1596 {
1597 if (hppa_branch_type != CMP_SI)
1598 FAIL;
1599 operands[1] = hppa_compare_op0;
1600 operands[2] = hppa_compare_op1;
1601 }")
1603 (define_expand "bltu"
1604 [(set (pc)
1605 (if_then_else (ltu (match_dup 1) (match_dup 2))
1606 (label_ref (match_operand 0 "" ""))
1607 (pc)))]
1608 ""
1609 "
1610 {
1611 if (hppa_branch_type != CMP_SI)
1612 FAIL;
1613 operands[1] = hppa_compare_op0;
1614 operands[2] = hppa_compare_op1;
1615 }")
1617 (define_expand "bgeu"
1618 [(set (pc)
1619 (if_then_else (geu (match_dup 1) (match_dup 2))
1620 (label_ref (match_operand 0 "" ""))
1621 (pc)))]
1622 ""
1623 "
1624 {
1625 if (hppa_branch_type != CMP_SI)
1626 FAIL;
1627 operands[1] = hppa_compare_op0;
1628 operands[2] = hppa_compare_op1;
1629 }")
1631 (define_expand "bleu"
1632 [(set (pc)
1633 (if_then_else (leu (match_dup 1) (match_dup 2))
1634 (label_ref (match_operand 0 "" ""))
1635 (pc)))]
1636 ""
1637 "
1638 {
1639 if (hppa_branch_type != CMP_SI)
1640 FAIL;
1641 operands[1] = hppa_compare_op0;
1642 operands[2] = hppa_compare_op1;
1643 }")
1645 (define_expand "bltgt"
1646 [(set (pc)
1647 (if_then_else (ltgt (match_dup 1) (match_dup 2))
1648 (label_ref (match_operand 0 "" ""))
1649 (pc)))]
1650 ""
1651 "
1652 {
1653 if (hppa_branch_type == CMP_SI)
1654 FAIL;
1655 emit_insn (gen_cmp_fp (LTGT, hppa_compare_op0, hppa_compare_op1));
1656 emit_bcond_fp (NE, operands[0]);
1657 DONE;
1658 }")
1660 (define_expand "bunle"
1661 [(set (pc)
1662 (if_then_else (unle (match_dup 1) (match_dup 2))
1663 (label_ref (match_operand 0 "" ""))
1664 (pc)))]
1665 ""
1666 "
1667 {
1668 if (hppa_branch_type == CMP_SI)
1669 FAIL;
1670 emit_insn (gen_cmp_fp (UNLE, hppa_compare_op0, hppa_compare_op1));
1671 emit_bcond_fp (NE, operands[0]);
1672 DONE;
1673 }")
1675 (define_expand "bunlt"
1676 [(set (pc)
1677 (if_then_else (unlt (match_dup 1) (match_dup 2))
1678 (label_ref (match_operand 0 "" ""))
1679 (pc)))]
1680 ""
1681 "
1682 {
1683 if (hppa_branch_type == CMP_SI)
1684 FAIL;
1685 emit_insn (gen_cmp_fp (UNLT, hppa_compare_op0, hppa_compare_op1));
1686 emit_bcond_fp (NE, operands[0]);
1687 DONE;
1688 }")
1690 (define_expand "bunge"
1691 [(set (pc)
1692 (if_then_else (unge (match_dup 1) (match_dup 2))
1693 (label_ref (match_operand 0 "" ""))
1694 (pc)))]
1695 ""
1696 "
1697 {
1698 if (hppa_branch_type == CMP_SI)
1699 FAIL;
1700 emit_insn (gen_cmp_fp (UNGE, hppa_compare_op0, hppa_compare_op1));
1701 emit_bcond_fp (NE, operands[0]);
1702 DONE;
1703 }")
1705 (define_expand "bungt"
1706 [(set (pc)
1707 (if_then_else (ungt (match_dup 1) (match_dup 2))
1708 (label_ref (match_operand 0 "" ""))
1709 (pc)))]
1710 ""
1711 "
1712 {
1713 if (hppa_branch_type == CMP_SI)
1714 FAIL;
1715 emit_insn (gen_cmp_fp (UNGT, hppa_compare_op0, hppa_compare_op1));
1716 emit_bcond_fp (NE, operands[0]);
1717 DONE;
1718 }")
1720 (define_expand "buneq"
1721 [(set (pc)
1722 (if_then_else (uneq (match_dup 1) (match_dup 2))
1723 (label_ref (match_operand 0 "" ""))
1724 (pc)))]
1725 ""
1726 "
1727 {
1728 if (hppa_branch_type == CMP_SI)
1729 FAIL;
1730 emit_insn (gen_cmp_fp (UNEQ, hppa_compare_op0, hppa_compare_op1));
1731 emit_bcond_fp (NE, operands[0]);
1732 DONE;
1733 }")
1735 (define_expand "bunordered"
1736 [(set (pc)
1737 (if_then_else (unordered (match_dup 1) (match_dup 2))
1738 (label_ref (match_operand 0 "" ""))
1739 (pc)))]
1740 ""
1741 "
1742 {
1743 if (hppa_branch_type == CMP_SI)
1744 FAIL;
1745 emit_insn (gen_cmp_fp (UNORDERED, hppa_compare_op0, hppa_compare_op1));
1746 emit_bcond_fp (NE, operands[0]);
1747 DONE;
1748 }")
1750 (define_expand "bordered"
1751 [(set (pc)
1752 (if_then_else (ordered (match_dup 1) (match_dup 2))
1753 (label_ref (match_operand 0 "" ""))
1754 (pc)))]
1755 ""
1756 "
1757 {
1758 if (hppa_branch_type == CMP_SI)
1759 FAIL;
1760 emit_insn (gen_cmp_fp (ORDERED, hppa_compare_op0, hppa_compare_op1));
1761 emit_bcond_fp (NE, operands[0]);
1762 DONE;
1763 }")
1765 ;; Match the branch patterns.
1768 ;; Note a long backward conditional branch with an annulled delay slot
1769 ;; has a length of 12.
1770 (define_insn ""
1771 [(set (pc)
1772 (if_then_else
1773 (match_operator 3 "comparison_operator"
1774 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1775 (match_operand:SI 2 "arith5_operand" "rL")])
1776 (label_ref (match_operand 0 "" ""))
1777 (pc)))]
1778 ""
1779 "*
1780 {
1781 return output_cbranch (operands, 0, insn);
1782 }"
1783 [(set_attr "type" "cbranch")
1784 (set (attr "length")
1785 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1786 (const_int MAX_12BIT_OFFSET))
1787 (const_int 4)
1788 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1789 (const_int MAX_17BIT_OFFSET))
1790 (const_int 8)
1791 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1792 (const_int 24)
1793 (eq (symbol_ref "flag_pic") (const_int 0))
1794 (const_int 20)]
1795 (const_int 28)))])
1797 ;; Match the negated branch.
1799 (define_insn ""
1800 [(set (pc)
1801 (if_then_else
1802 (match_operator 3 "comparison_operator"
1803 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1804 (match_operand:SI 2 "arith5_operand" "rL")])
1805 (pc)
1806 (label_ref (match_operand 0 "" ""))))]
1807 ""
1808 "*
1809 {
1810 return output_cbranch (operands, 1, insn);
1811 }"
1812 [(set_attr "type" "cbranch")
1813 (set (attr "length")
1814 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1815 (const_int MAX_12BIT_OFFSET))
1816 (const_int 4)
1817 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1818 (const_int MAX_17BIT_OFFSET))
1819 (const_int 8)
1820 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1821 (const_int 24)
1822 (eq (symbol_ref "flag_pic") (const_int 0))
1823 (const_int 20)]
1824 (const_int 28)))])
1826 (define_insn ""
1827 [(set (pc)
1828 (if_then_else
1829 (match_operator 3 "comparison_operator"
1830 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1831 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1832 (label_ref (match_operand 0 "" ""))
1833 (pc)))]
1834 "TARGET_64BIT"
1835 "*
1836 {
1837 return output_cbranch (operands, 0, insn);
1838 }"
1839 [(set_attr "type" "cbranch")
1840 (set (attr "length")
1841 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1842 (const_int MAX_12BIT_OFFSET))
1843 (const_int 4)
1844 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1845 (const_int MAX_17BIT_OFFSET))
1846 (const_int 8)
1847 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1848 (const_int 24)
1849 (eq (symbol_ref "flag_pic") (const_int 0))
1850 (const_int 20)]
1851 (const_int 28)))])
1853 ;; Match the negated branch.
1855 (define_insn ""
1856 [(set (pc)
1857 (if_then_else
1858 (match_operator 3 "comparison_operator"
1859 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1860 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1861 (pc)
1862 (label_ref (match_operand 0 "" ""))))]
1863 "TARGET_64BIT"
1864 "*
1865 {
1866 return output_cbranch (operands, 1, insn);
1867 }"
1868 [(set_attr "type" "cbranch")
1869 (set (attr "length")
1870 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1871 (const_int MAX_12BIT_OFFSET))
1872 (const_int 4)
1873 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1874 (const_int MAX_17BIT_OFFSET))
1875 (const_int 8)
1876 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1877 (const_int 24)
1878 (eq (symbol_ref "flag_pic") (const_int 0))
1879 (const_int 20)]
1880 (const_int 28)))])
1881 (define_insn ""
1882 [(set (pc)
1883 (if_then_else
1884 (match_operator 3 "cmpib_comparison_operator"
1885 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1886 (match_operand:DI 2 "arith5_operand" "rL")])
1887 (label_ref (match_operand 0 "" ""))
1888 (pc)))]
1889 "TARGET_64BIT"
1890 "*
1891 {
1892 return output_cbranch (operands, 0, insn);
1893 }"
1894 [(set_attr "type" "cbranch")
1895 (set (attr "length")
1896 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1897 (const_int MAX_12BIT_OFFSET))
1898 (const_int 4)
1899 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1900 (const_int MAX_17BIT_OFFSET))
1901 (const_int 8)
1902 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1903 (const_int 24)
1904 (eq (symbol_ref "flag_pic") (const_int 0))
1905 (const_int 20)]
1906 (const_int 28)))])
1908 ;; Match the negated branch.
1910 (define_insn ""
1911 [(set (pc)
1912 (if_then_else
1913 (match_operator 3 "cmpib_comparison_operator"
1914 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1915 (match_operand:DI 2 "arith5_operand" "rL")])
1916 (pc)
1917 (label_ref (match_operand 0 "" ""))))]
1918 "TARGET_64BIT"
1919 "*
1920 {
1921 return output_cbranch (operands, 1, insn);
1922 }"
1923 [(set_attr "type" "cbranch")
1924 (set (attr "length")
1925 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1926 (const_int MAX_12BIT_OFFSET))
1927 (const_int 4)
1928 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1929 (const_int MAX_17BIT_OFFSET))
1930 (const_int 8)
1931 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1932 (const_int 24)
1933 (eq (symbol_ref "flag_pic") (const_int 0))
1934 (const_int 20)]
1935 (const_int 28)))])
1937 ;; Branch on Bit patterns.
1938 (define_insn ""
1939 [(set (pc)
1940 (if_then_else
1941 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1942 (const_int 1)
1943 (match_operand:SI 1 "uint5_operand" ""))
1944 (const_int 0))
1945 (label_ref (match_operand 2 "" ""))
1946 (pc)))]
1947 ""
1948 "*
1949 {
1950 return output_bb (operands, 0, insn, 0);
1951 }"
1952 [(set_attr "type" "cbranch")
1953 (set (attr "length")
1954 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1955 (const_int MAX_12BIT_OFFSET))
1956 (const_int 4)
1957 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1958 (const_int MAX_17BIT_OFFSET))
1959 (const_int 8)
1960 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1961 (const_int 24)
1962 (eq (symbol_ref "flag_pic") (const_int 0))
1963 (const_int 20)]
1964 (const_int 28)))])
1966 (define_insn ""
1967 [(set (pc)
1968 (if_then_else
1969 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1970 (const_int 1)
1971 (match_operand:DI 1 "uint32_operand" ""))
1972 (const_int 0))
1973 (label_ref (match_operand 2 "" ""))
1974 (pc)))]
1975 "TARGET_64BIT"
1976 "*
1977 {
1978 return output_bb (operands, 0, insn, 0);
1979 }"
1980 [(set_attr "type" "cbranch")
1981 (set (attr "length")
1982 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1983 (const_int MAX_12BIT_OFFSET))
1984 (const_int 4)
1985 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1986 (const_int MAX_17BIT_OFFSET))
1987 (const_int 8)
1988 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1989 (const_int 24)
1990 (eq (symbol_ref "flag_pic") (const_int 0))
1991 (const_int 20)]
1992 (const_int 28)))])
1994 (define_insn ""
1995 [(set (pc)
1996 (if_then_else
1997 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1998 (const_int 1)
1999 (match_operand:SI 1 "uint5_operand" ""))
2000 (const_int 0))
2001 (pc)
2002 (label_ref (match_operand 2 "" ""))))]
2003 ""
2004 "*
2005 {
2006 return output_bb (operands, 1, insn, 0);
2007 }"
2008 [(set_attr "type" "cbranch")
2009 (set (attr "length")
2010 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2011 (const_int MAX_12BIT_OFFSET))
2012 (const_int 4)
2013 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2014 (const_int MAX_17BIT_OFFSET))
2015 (const_int 8)
2016 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2017 (const_int 24)
2018 (eq (symbol_ref "flag_pic") (const_int 0))
2019 (const_int 20)]
2020 (const_int 28)))])
2022 (define_insn ""
2023 [(set (pc)
2024 (if_then_else
2025 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2026 (const_int 1)
2027 (match_operand:DI 1 "uint32_operand" ""))
2028 (const_int 0))
2029 (pc)
2030 (label_ref (match_operand 2 "" ""))))]
2031 "TARGET_64BIT"
2032 "*
2033 {
2034 return output_bb (operands, 1, insn, 0);
2035 }"
2036 [(set_attr "type" "cbranch")
2037 (set (attr "length")
2038 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2039 (const_int MAX_12BIT_OFFSET))
2040 (const_int 4)
2041 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2042 (const_int MAX_17BIT_OFFSET))
2043 (const_int 8)
2044 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2045 (const_int 24)
2046 (eq (symbol_ref "flag_pic") (const_int 0))
2047 (const_int 20)]
2048 (const_int 28)))])
2050 (define_insn ""
2051 [(set (pc)
2052 (if_then_else
2053 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2054 (const_int 1)
2055 (match_operand:SI 1 "uint5_operand" ""))
2056 (const_int 0))
2057 (label_ref (match_operand 2 "" ""))
2058 (pc)))]
2059 ""
2060 "*
2061 {
2062 return output_bb (operands, 0, insn, 1);
2063 }"
2064 [(set_attr "type" "cbranch")
2065 (set (attr "length")
2066 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2067 (const_int MAX_12BIT_OFFSET))
2068 (const_int 4)
2069 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2070 (const_int MAX_17BIT_OFFSET))
2071 (const_int 8)
2072 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2073 (const_int 24)
2074 (eq (symbol_ref "flag_pic") (const_int 0))
2075 (const_int 20)]
2076 (const_int 28)))])
2078 (define_insn ""
2079 [(set (pc)
2080 (if_then_else
2081 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2082 (const_int 1)
2083 (match_operand:DI 1 "uint32_operand" ""))
2084 (const_int 0))
2085 (label_ref (match_operand 2 "" ""))
2086 (pc)))]
2087 "TARGET_64BIT"
2088 "*
2089 {
2090 return output_bb (operands, 0, insn, 1);
2091 }"
2092 [(set_attr "type" "cbranch")
2093 (set (attr "length")
2094 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2095 (const_int MAX_12BIT_OFFSET))
2096 (const_int 4)
2097 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2098 (const_int MAX_17BIT_OFFSET))
2099 (const_int 8)
2100 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2101 (const_int 24)
2102 (eq (symbol_ref "flag_pic") (const_int 0))
2103 (const_int 20)]
2104 (const_int 28)))])
2106 (define_insn ""
2107 [(set (pc)
2108 (if_then_else
2109 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2110 (const_int 1)
2111 (match_operand:SI 1 "uint5_operand" ""))
2112 (const_int 0))
2113 (pc)
2114 (label_ref (match_operand 2 "" ""))))]
2115 ""
2116 "*
2117 {
2118 return output_bb (operands, 1, insn, 1);
2119 }"
2120 [(set_attr "type" "cbranch")
2121 (set (attr "length")
2122 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2123 (const_int MAX_12BIT_OFFSET))
2124 (const_int 4)
2125 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2126 (const_int MAX_17BIT_OFFSET))
2127 (const_int 8)
2128 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2129 (const_int 24)
2130 (eq (symbol_ref "flag_pic") (const_int 0))
2131 (const_int 20)]
2132 (const_int 28)))])
2134 (define_insn ""
2135 [(set (pc)
2136 (if_then_else
2137 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2138 (const_int 1)
2139 (match_operand:DI 1 "uint32_operand" ""))
2140 (const_int 0))
2141 (pc)
2142 (label_ref (match_operand 2 "" ""))))]
2143 "TARGET_64BIT"
2144 "*
2145 {
2146 return output_bb (operands, 1, insn, 1);
2147 }"
2148 [(set_attr "type" "cbranch")
2149 (set (attr "length")
2150 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2151 (const_int MAX_12BIT_OFFSET))
2152 (const_int 4)
2153 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2154 (const_int MAX_17BIT_OFFSET))
2155 (const_int 8)
2156 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2157 (const_int 24)
2158 (eq (symbol_ref "flag_pic") (const_int 0))
2159 (const_int 20)]
2160 (const_int 28)))])
2162 ;; Branch on Variable Bit patterns.
2163 (define_insn ""
2164 [(set (pc)
2165 (if_then_else
2166 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2167 (const_int 1)
2168 (match_operand:SI 1 "register_operand" "q"))
2169 (const_int 0))
2170 (label_ref (match_operand 2 "" ""))
2171 (pc)))]
2172 ""
2173 "*
2174 {
2175 return output_bvb (operands, 0, insn, 0);
2176 }"
2177 [(set_attr "type" "cbranch")
2178 (set (attr "length")
2179 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2180 (const_int MAX_12BIT_OFFSET))
2181 (const_int 4)
2182 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2183 (const_int MAX_17BIT_OFFSET))
2184 (const_int 8)
2185 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2186 (const_int 24)
2187 (eq (symbol_ref "flag_pic") (const_int 0))
2188 (const_int 20)]
2189 (const_int 28)))])
2191 (define_insn ""
2192 [(set (pc)
2193 (if_then_else
2194 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2195 (const_int 1)
2196 (match_operand:DI 1 "register_operand" "q"))
2197 (const_int 0))
2198 (label_ref (match_operand 2 "" ""))
2199 (pc)))]
2200 "TARGET_64BIT"
2201 "*
2202 {
2203 return output_bvb (operands, 0, insn, 0);
2204 }"
2205 [(set_attr "type" "cbranch")
2206 (set (attr "length")
2207 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2208 (const_int MAX_12BIT_OFFSET))
2209 (const_int 4)
2210 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2211 (const_int MAX_17BIT_OFFSET))
2212 (const_int 8)
2213 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2214 (const_int 24)
2215 (eq (symbol_ref "flag_pic") (const_int 0))
2216 (const_int 20)]
2217 (const_int 28)))])
2219 (define_insn ""
2220 [(set (pc)
2221 (if_then_else
2222 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2223 (const_int 1)
2224 (match_operand:SI 1 "register_operand" "q"))
2225 (const_int 0))
2226 (pc)
2227 (label_ref (match_operand 2 "" ""))))]
2228 ""
2229 "*
2230 {
2231 return output_bvb (operands, 1, insn, 0);
2232 }"
2233 [(set_attr "type" "cbranch")
2234 (set (attr "length")
2235 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2236 (const_int MAX_12BIT_OFFSET))
2237 (const_int 4)
2238 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2239 (const_int MAX_17BIT_OFFSET))
2240 (const_int 8)
2241 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2242 (const_int 24)
2243 (eq (symbol_ref "flag_pic") (const_int 0))
2244 (const_int 20)]
2245 (const_int 28)))])
2247 (define_insn ""
2248 [(set (pc)
2249 (if_then_else
2250 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2251 (const_int 1)
2252 (match_operand:DI 1 "register_operand" "q"))
2253 (const_int 0))
2254 (pc)
2255 (label_ref (match_operand 2 "" ""))))]
2256 "TARGET_64BIT"
2257 "*
2258 {
2259 return output_bvb (operands, 1, insn, 0);
2260 }"
2261 [(set_attr "type" "cbranch")
2262 (set (attr "length")
2263 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2264 (const_int MAX_12BIT_OFFSET))
2265 (const_int 4)
2266 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2267 (const_int MAX_17BIT_OFFSET))
2268 (const_int 8)
2269 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2270 (const_int 24)
2271 (eq (symbol_ref "flag_pic") (const_int 0))
2272 (const_int 20)]
2273 (const_int 28)))])
2275 (define_insn ""
2276 [(set (pc)
2277 (if_then_else
2278 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2279 (const_int 1)
2280 (match_operand:SI 1 "register_operand" "q"))
2281 (const_int 0))
2282 (label_ref (match_operand 2 "" ""))
2283 (pc)))]
2284 ""
2285 "*
2286 {
2287 return output_bvb (operands, 0, insn, 1);
2288 }"
2289 [(set_attr "type" "cbranch")
2290 (set (attr "length")
2291 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2292 (const_int MAX_12BIT_OFFSET))
2293 (const_int 4)
2294 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2295 (const_int MAX_17BIT_OFFSET))
2296 (const_int 8)
2297 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2298 (const_int 24)
2299 (eq (symbol_ref "flag_pic") (const_int 0))
2300 (const_int 20)]
2301 (const_int 28)))])
2303 (define_insn ""
2304 [(set (pc)
2305 (if_then_else
2306 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2307 (const_int 1)
2308 (match_operand:DI 1 "register_operand" "q"))
2309 (const_int 0))
2310 (label_ref (match_operand 2 "" ""))
2311 (pc)))]
2312 "TARGET_64BIT"
2313 "*
2314 {
2315 return output_bvb (operands, 0, insn, 1);
2316 }"
2317 [(set_attr "type" "cbranch")
2318 (set (attr "length")
2319 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2320 (const_int MAX_12BIT_OFFSET))
2321 (const_int 4)
2322 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2323 (const_int MAX_17BIT_OFFSET))
2324 (const_int 8)
2325 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2326 (const_int 24)
2327 (eq (symbol_ref "flag_pic") (const_int 0))
2328 (const_int 20)]
2329 (const_int 28)))])
2331 (define_insn ""
2332 [(set (pc)
2333 (if_then_else
2334 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2335 (const_int 1)
2336 (match_operand:SI 1 "register_operand" "q"))
2337 (const_int 0))
2338 (pc)
2339 (label_ref (match_operand 2 "" ""))))]
2340 ""
2341 "*
2342 {
2343 return output_bvb (operands, 1, insn, 1);
2344 }"
2345 [(set_attr "type" "cbranch")
2346 (set (attr "length")
2347 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2348 (const_int MAX_12BIT_OFFSET))
2349 (const_int 4)
2350 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2351 (const_int MAX_17BIT_OFFSET))
2352 (const_int 8)
2353 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2354 (const_int 24)
2355 (eq (symbol_ref "flag_pic") (const_int 0))
2356 (const_int 20)]
2357 (const_int 28)))])
2359 (define_insn ""
2360 [(set (pc)
2361 (if_then_else
2362 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2363 (const_int 1)
2364 (match_operand:DI 1 "register_operand" "q"))
2365 (const_int 0))
2366 (pc)
2367 (label_ref (match_operand 2 "" ""))))]
2368 "TARGET_64BIT"
2369 "*
2370 {
2371 return output_bvb (operands, 1, insn, 1);
2372 }"
2373 [(set_attr "type" "cbranch")
2374 (set (attr "length")
2375 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2376 (const_int MAX_12BIT_OFFSET))
2377 (const_int 4)
2378 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2379 (const_int MAX_17BIT_OFFSET))
2380 (const_int 8)
2381 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2382 (const_int 24)
2383 (eq (symbol_ref "flag_pic") (const_int 0))
2384 (const_int 20)]
2385 (const_int 28)))])
2387 ;; Floating point branches
2389 ;; ??? Nullification is handled differently from other branches.
2390 ;; If nullification is specified, the delay slot is nullified on any
2391 ;; taken branch regardless of branch direction.
2392 (define_insn ""
2393 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2394 (label_ref (match_operand 0 "" ""))
2395 (pc)))]
2396 "!TARGET_SOFT_FLOAT"
2397 "*
2398 {
2399 int length = get_attr_length (insn);
2400 rtx xoperands[1];
2401 int nullify, xdelay;
2403 if (length < 16)
2404 return \"ftest\;b%* %l0\";
2406 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
2407 {
2408 nullify = 1;
2409 xdelay = 0;
2410 xoperands[0] = GEN_INT (length - 8);
2411 }
2412 else
2413 {
2414 nullify = 0;
2415 xdelay = 1;
2416 xoperands[0] = GEN_INT (length - 4);
2417 }
2419 if (nullify)
2420 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b,n .+%0\", xoperands);
2421 else
2422 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b .+%0\", xoperands);
2423 return output_lbranch (operands[0], insn, xdelay);
2424 }"
2425 [(set_attr "type" "fbranch")
2426 (set (attr "length")
2427 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
2428 (const_int MAX_17BIT_OFFSET))
2429 (const_int 8)
2430 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2431 (const_int 32)
2432 (eq (symbol_ref "flag_pic") (const_int 0))
2433 (const_int 28)]
2434 (const_int 36)))])
2436 (define_insn ""
2437 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2438 (pc)
2439 (label_ref (match_operand 0 "" ""))))]
2440 "!TARGET_SOFT_FLOAT"
2441 "*
2442 {
2443 int length = get_attr_length (insn);
2444 rtx xoperands[1];
2445 int nullify, xdelay;
2447 if (length < 16)
2448 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2450 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
2451 {
2452 nullify = 1;
2453 xdelay = 0;
2454 xoperands[0] = GEN_INT (length - 4);
2455 }
2456 else
2457 {
2458 nullify = 0;
2459 xdelay = 1;
2460 xoperands[0] = GEN_INT (length);
2461 }
2463 if (nullify)
2464 output_asm_insn (\"ftest\;b,n .+%0\", xoperands);
2465 else
2466 output_asm_insn (\"ftest\;b .+%0\", xoperands);
2467 return output_lbranch (operands[0], insn, xdelay);
2468 }"
2469 [(set_attr "type" "fbranch")
2470 (set (attr "length")
2471 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
2472 (const_int MAX_17BIT_OFFSET))
2473 (const_int 12)
2474 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2475 (const_int 28)
2476 (eq (symbol_ref "flag_pic") (const_int 0))
2477 (const_int 24)]
2478 (const_int 32)))])
2480 ;; Move instructions
2482 (define_expand "movsi"
2483 [(set (match_operand:SI 0 "general_operand" "")
2484 (match_operand:SI 1 "general_operand" ""))]
2485 ""
2486 "
2487 {
2488 if (emit_move_sequence (operands, SImode, 0))
2489 DONE;
2490 }")
2492 ;; Handle SImode input reloads requiring %r1 as a scratch register.
2493 (define_expand "reload_insi_r1"
2494 [(set (match_operand:SI 0 "register_operand" "=Z")
2495 (match_operand:SI 1 "non_hard_reg_operand" ""))
2496 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
2497 ""
2498 "
2499 {
2500 if (emit_move_sequence (operands, SImode, operands[2]))
2501 DONE;
2503 /* We don't want the clobber emitted, so handle this ourselves. */
2504 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2505 DONE;
2506 }")
2508 ;; Handle SImode input reloads requiring a general register as a
2509 ;; scratch register.
2510 (define_expand "reload_insi"
2511 [(set (match_operand:SI 0 "register_operand" "=Z")
2512 (match_operand:SI 1 "non_hard_reg_operand" ""))
2513 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2514 ""
2515 "
2516 {
2517 if (emit_move_sequence (operands, SImode, operands[2]))
2518 DONE;
2520 /* We don't want the clobber emitted, so handle this ourselves. */
2521 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2522 DONE;
2523 }")
2525 ;; Handle SImode output reloads requiring a general register as a
2526 ;; scratch register.
2527 (define_expand "reload_outsi"
2528 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2529 (match_operand:SI 1 "register_operand" "Z"))
2530 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2531 ""
2532 "
2533 {
2534 if (emit_move_sequence (operands, SImode, operands[2]))
2535 DONE;
2537 /* We don't want the clobber emitted, so handle this ourselves. */
2538 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2539 DONE;
2540 }")
2542 (define_insn ""
2543 [(set (match_operand:SI 0 "move_dest_operand"
2544 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,?r,?*f")
2545 (match_operand:SI 1 "move_src_operand"
2546 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,*f,r"))]
2547 "(register_operand (operands[0], SImode)
2548 || reg_or_0_operand (operands[1], SImode))
2549 && !TARGET_SOFT_FLOAT
2550 && !TARGET_64BIT"
2551 "@
2552 ldw RT'%A1,%0
2553 copy %1,%0
2554 ldi %1,%0
2555 ldil L'%1,%0
2556 {zdepi|depwi,z} %Z1,%0
2557 ldw%M1 %1,%0
2558 stw%M0 %r1,%0
2559 mtsar %r1
2560 {mfctl|mfctl,w} %%sar,%0
2561 fcpy,sgl %f1,%0
2562 fldw%F1 %1,%0
2563 fstw%F0 %1,%0
2564 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
2565 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
2566 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore,fpstore_load,store_fpload")
2567 (set_attr "pa_combine_type" "addmove")
2568 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,8,8")])
2570 (define_insn ""
2571 [(set (match_operand:SI 0 "move_dest_operand"
2572 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
2573 (match_operand:SI 1 "move_src_operand"
2574 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
2575 "(register_operand (operands[0], SImode)
2576 || reg_or_0_operand (operands[1], SImode))
2577 && !TARGET_SOFT_FLOAT
2578 && TARGET_64BIT"
2579 "@
2580 ldw RT'%A1,%0
2581 copy %1,%0
2582 ldi %1,%0
2583 ldil L'%1,%0
2584 {zdepi|depwi,z} %Z1,%0
2585 ldw%M1 %1,%0
2586 stw%M0 %r1,%0
2587 mtsar %r1
2588 {mfctl|mfctl,w} %%sar,%0
2589 fcpy,sgl %f1,%0
2590 fldw%F1 %1,%0
2591 fstw%F0 %1,%0"
2592 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
2593 (set_attr "pa_combine_type" "addmove")
2594 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
2596 (define_insn ""
2597 [(set (match_operand:SI 0 "indexed_memory_operand" "=R")
2598 (match_operand:SI 1 "register_operand" "f"))]
2599 "!TARGET_SOFT_FLOAT
2600 && !TARGET_DISABLE_INDEXING
2601 && reload_completed"
2602 "fstw%F0 %1,%0"
2603 [(set_attr "type" "fpstore")
2604 (set_attr "pa_combine_type" "addmove")
2605 (set_attr "length" "4")])
2607 ; Rewrite RTL using an indexed store. This will allow the insn that
2608 ; computes the address to be deleted if the register it sets is dead.
2609 (define_peephole2
2610 [(set (match_operand:SI 0 "register_operand" "")
2611 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
2612 (const_int 4))
2613 (match_operand:SI 2 "register_operand" "")))
2614 (set (mem:SI (match_dup 0))
2615 (match_operand:SI 3 "register_operand" ""))]
2616 "!TARGET_SOFT_FLOAT
2617 && !TARGET_DISABLE_INDEXING
2618 && REG_OK_FOR_BASE_P (operands[2])
2619 && FP_REGNO_P (REGNO (operands[3]))"
2620 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2621 (match_dup 3))
2622 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2623 (match_dup 2)))]
2624 "")
2626 (define_peephole2
2627 [(set (match_operand:SI 0 "register_operand" "")
2628 (plus:SI (match_operand:SI 2 "register_operand" "")
2629 (mult:SI (match_operand:SI 1 "register_operand" "")
2630 (const_int 4))))
2631 (set (mem:SI (match_dup 0))
2632 (match_operand:SI 3 "register_operand" ""))]
2633 "!TARGET_SOFT_FLOAT
2634 && !TARGET_DISABLE_INDEXING
2635 && REG_OK_FOR_BASE_P (operands[2])
2636 && FP_REGNO_P (REGNO (operands[3]))"
2637 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2638 (match_dup 3))
2639 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2640 (match_dup 2)))]
2641 "")
2643 (define_peephole2
2644 [(set (match_operand:DI 0 "register_operand" "")
2645 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2646 (const_int 4))
2647 (match_operand:DI 2 "register_operand" "")))
2648 (set (mem:SI (match_dup 0))
2649 (match_operand:SI 3 "register_operand" ""))]
2650 "!TARGET_SOFT_FLOAT
2651 && !TARGET_DISABLE_INDEXING
2652 && TARGET_64BIT
2653 && REG_OK_FOR_BASE_P (operands[2])
2654 && FP_REGNO_P (REGNO (operands[3]))"
2655 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2656 (match_dup 3))
2657 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2658 (match_dup 2)))]
2659 "")
2661 (define_peephole2
2662 [(set (match_operand:DI 0 "register_operand" "")
2663 (plus:DI (match_operand:DI 2 "register_operand" "")
2664 (mult:DI (match_operand:DI 1 "register_operand" "")
2665 (const_int 4))))
2666 (set (mem:SI (match_dup 0))
2667 (match_operand:SI 3 "register_operand" ""))]
2668 "!TARGET_SOFT_FLOAT
2669 && !TARGET_DISABLE_INDEXING
2670 && TARGET_64BIT
2671 && REG_OK_FOR_BASE_P (operands[2])
2672 && FP_REGNO_P (REGNO (operands[3]))"
2673 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2674 (match_dup 3))
2675 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2676 (match_dup 2)))]
2677 "")
2679 (define_peephole2
2680 [(set (match_operand:SI 0 "register_operand" "")
2681 (plus:SI (match_operand:SI 1 "register_operand" "")
2682 (match_operand:SI 2 "register_operand" "")))
2683 (set (mem:SI (match_dup 0))
2684 (match_operand:SI 3 "register_operand" ""))]
2685 "!TARGET_SOFT_FLOAT
2686 && !TARGET_DISABLE_INDEXING
2687 && TARGET_NO_SPACE_REGS
2688 && REG_OK_FOR_INDEX_P (operands[1])
2689 && REG_OK_FOR_BASE_P (operands[2])
2690 && FP_REGNO_P (REGNO (operands[3]))"
2691 [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2)))
2692 (match_dup 3))
2693 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2694 "")
2696 (define_peephole2
2697 [(set (match_operand:SI 0 "register_operand" "")
2698 (plus:SI (match_operand:SI 1 "register_operand" "")
2699 (match_operand:SI 2 "register_operand" "")))
2700 (set (mem:SI (match_dup 0))
2701 (match_operand:SI 3 "register_operand" ""))]
2702 "!TARGET_SOFT_FLOAT
2703 && !TARGET_DISABLE_INDEXING
2704 && TARGET_NO_SPACE_REGS
2705 && REG_OK_FOR_BASE_P (operands[1])
2706 && REG_OK_FOR_INDEX_P (operands[2])
2707 && FP_REGNO_P (REGNO (operands[3]))"
2708 [(set (mem:SI (plus:SI (match_dup 2) (match_dup 1)))
2709 (match_dup 3))
2710 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
2711 "")
2713 (define_peephole2
2714 [(set (match_operand:DI 0 "register_operand" "")
2715 (plus:DI (match_operand:DI 1 "register_operand" "")
2716 (match_operand:DI 2 "register_operand" "")))
2717 (set (mem:SI (match_dup 0))
2718 (match_operand:SI 3 "register_operand" ""))]
2719 "!TARGET_SOFT_FLOAT
2720 && !TARGET_DISABLE_INDEXING
2721 && TARGET_64BIT
2722 && TARGET_NO_SPACE_REGS
2723 && REG_OK_FOR_INDEX_P (operands[1])
2724 && REG_OK_FOR_BASE_P (operands[2])
2725 && FP_REGNO_P (REGNO (operands[3]))"
2726 [(set (mem:SI (plus:DI (match_dup 1) (match_dup 2)))
2727 (match_dup 3))
2728 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
2729 "")
2731 (define_peephole2
2732 [(set (match_operand:DI 0 "register_operand" "")
2733 (plus:DI (match_operand:DI 1 "register_operand" "")
2734 (match_operand:DI 2 "register_operand" "")))
2735 (set (mem:SI (match_dup 0))
2736 (match_operand:SI 3 "register_operand" ""))]
2737 "!TARGET_SOFT_FLOAT
2738 && !TARGET_DISABLE_INDEXING
2739 && TARGET_64BIT
2740 && TARGET_NO_SPACE_REGS
2741 && REG_OK_FOR_BASE_P (operands[1])
2742 && REG_OK_FOR_INDEX_P (operands[2])
2743 && FP_REGNO_P (REGNO (operands[3]))"
2744 [(set (mem:SI (plus:DI (match_dup 2) (match_dup 1)))
2745 (match_dup 3))
2746 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
2747 "")
2749 (define_insn ""
2750 [(set (match_operand:SI 0 "move_dest_operand"
2751 "=r,r,r,r,r,r,Q,!*q,!r")
2752 (match_operand:SI 1 "move_src_operand"
2753 "A,r,J,N,K,RQ,rM,!rM,!*q"))]
2754 "(register_operand (operands[0], SImode)
2755 || reg_or_0_operand (operands[1], SImode))
2756 && TARGET_SOFT_FLOAT"
2757 "@
2758 ldw RT'%A1,%0
2759 copy %1,%0
2760 ldi %1,%0
2761 ldil L'%1,%0
2762 {zdepi|depwi,z} %Z1,%0
2763 ldw%M1 %1,%0
2764 stw%M0 %r1,%0
2765 mtsar %r1
2766 {mfctl|mfctl,w} %%sar,%0"
2767 [(set_attr "type" "load,move,move,move,move,load,store,move,move")
2768 (set_attr "pa_combine_type" "addmove")
2769 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
2771 ;; Load or store with base-register modification.
2772 (define_insn ""
2773 [(set (match_operand:SI 0 "register_operand" "=r")
2774 (mem:SI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2775 (match_operand:DI 2 "int5_operand" "L"))))
2776 (set (match_dup 1)
2777 (plus:DI (match_dup 1) (match_dup 2)))]
2778 "TARGET_64BIT"
2779 "ldw,mb %2(%1),%0"
2780 [(set_attr "type" "load")
2781 (set_attr "length" "4")])
2783 ; And a zero extended variant.
2784 (define_insn ""
2785 [(set (match_operand:DI 0 "register_operand" "=r")
2786 (zero_extend:DI (mem:SI
2787 (plus:DI
2788 (match_operand:DI 1 "register_operand" "+r")
2789 (match_operand:DI 2 "int5_operand" "L")))))
2790 (set (match_dup 1)
2791 (plus:DI (match_dup 1) (match_dup 2)))]
2792 "TARGET_64BIT"
2793 "ldw,mb %2(%1),%0"
2794 [(set_attr "type" "load")
2795 (set_attr "length" "4")])
2797 (define_expand "pre_load"
2798 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2799 (mem (plus (match_operand 1 "register_operand" "")
2800 (match_operand 2 "pre_cint_operand" ""))))
2801 (set (match_dup 1)
2802 (plus (match_dup 1) (match_dup 2)))])]
2803 ""
2804 "
2805 {
2806 if (TARGET_64BIT)
2807 {
2808 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2809 DONE;
2810 }
2811 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2812 DONE;
2813 }")
2815 (define_insn "pre_ldw"
2816 [(set (match_operand:SI 0 "register_operand" "=r")
2817 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2818 (match_operand:SI 2 "pre_cint_operand" ""))))
2819 (set (match_dup 1)
2820 (plus:SI (match_dup 1) (match_dup 2)))]
2821 ""
2822 "*
2823 {
2824 if (INTVAL (operands[2]) < 0)
2825 return \"{ldwm|ldw,mb} %2(%1),%0\";
2826 return \"{ldws|ldw},mb %2(%1),%0\";
2827 }"
2828 [(set_attr "type" "load")
2829 (set_attr "length" "4")])
2831 (define_insn "pre_ldd"
2832 [(set (match_operand:DI 0 "register_operand" "=r")
2833 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2834 (match_operand:DI 2 "pre_cint_operand" ""))))
2835 (set (match_dup 1)
2836 (plus:DI (match_dup 1) (match_dup 2)))]
2837 "TARGET_64BIT"
2838 "ldd,mb %2(%1),%0"
2839 [(set_attr "type" "load")
2840 (set_attr "length" "4")])
2842 (define_insn ""
2843 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2844 (match_operand:SI 1 "pre_cint_operand" "")))
2845 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2846 (set (match_dup 0)
2847 (plus:SI (match_dup 0) (match_dup 1)))]
2848 ""
2849 "*
2850 {
2851 if (INTVAL (operands[1]) < 0)
2852 return \"{stwm|stw,mb} %r2,%1(%0)\";
2853 return \"{stws|stw},mb %r2,%1(%0)\";
2854 }"
2855 [(set_attr "type" "store")
2856 (set_attr "length" "4")])
2858 (define_insn ""
2859 [(set (match_operand:SI 0 "register_operand" "=r")
2860 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2861 (set (match_dup 1)
2862 (plus:SI (match_dup 1)
2863 (match_operand:SI 2 "post_cint_operand" "")))]
2864 ""
2865 "*
2866 {
2867 if (INTVAL (operands[2]) > 0)
2868 return \"{ldwm|ldw,ma} %2(%1),%0\";
2869 return \"{ldws|ldw},ma %2(%1),%0\";
2870 }"
2871 [(set_attr "type" "load")
2872 (set_attr "length" "4")])
2874 (define_expand "post_store"
2875 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2876 (match_operand 1 "reg_or_0_operand" ""))
2877 (set (match_dup 0)
2878 (plus (match_dup 0)
2879 (match_operand 2 "post_cint_operand" "")))])]
2880 ""
2881 "
2882 {
2883 if (TARGET_64BIT)
2884 {
2885 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2886 DONE;
2887 }
2888 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2889 DONE;
2890 }")
2892 (define_insn "post_stw"
2893 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2894 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2895 (set (match_dup 0)
2896 (plus:SI (match_dup 0)
2897 (match_operand:SI 2 "post_cint_operand" "")))]
2898 ""
2899 "*
2900 {
2901 if (INTVAL (operands[2]) > 0)
2902 return \"{stwm|stw,ma} %r1,%2(%0)\";
2903 return \"{stws|stw},ma %r1,%2(%0)\";
2904 }"
2905 [(set_attr "type" "store")
2906 (set_attr "length" "4")])
2908 (define_insn "post_std"
2909 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2910 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2911 (set (match_dup 0)
2912 (plus:DI (match_dup 0)
2913 (match_operand:DI 2 "post_cint_operand" "")))]
2914 "TARGET_64BIT"
2915 "std,ma %r1,%2(%0)"
2916 [(set_attr "type" "store")
2917 (set_attr "length" "4")])
2919 ;; For loading the address of a label while generating PIC code.
2920 ;; Note since this pattern can be created at reload time (via movsi), all
2921 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2922 (define_insn ""
2923 [(set (match_operand 0 "pmode_register_operand" "=a")
2924 (match_operand 1 "pic_label_operand" ""))]
2925 "TARGET_PA_20"
2926 "*
2927 {
2928 rtx xoperands[3];
2930 xoperands[0] = operands[0];
2931 xoperands[1] = operands[1];
2932 xoperands[2] = gen_label_rtx ();
2934 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2935 CODE_LABEL_NUMBER (xoperands[2]));
2936 output_asm_insn (\"mfia %0\", xoperands);
2938 /* If we're trying to load the address of a label that happens to be
2939 close, then we can use a shorter sequence. */
2940 if (GET_CODE (operands[1]) == LABEL_REF
2941 && !LABEL_REF_NONLOCAL_P (operands[1])
2942 && INSN_ADDRESSES_SET_P ()
2943 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2944 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2945 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2946 else
2947 {
2948 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2949 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2950 }
2951 return \"\";
2952 }"
2953 [(set_attr "type" "multi")
2954 (set_attr "length" "12")]) ; 8 or 12
2956 (define_insn ""
2957 [(set (match_operand 0 "pmode_register_operand" "=a")
2958 (match_operand 1 "pic_label_operand" ""))]
2959 "!TARGET_PA_20"
2960 "*
2961 {
2962 rtx xoperands[3];
2964 xoperands[0] = operands[0];
2965 xoperands[1] = operands[1];
2966 xoperands[2] = gen_label_rtx ();
2968 output_asm_insn (\"bl .+8,%0\", xoperands);
2969 output_asm_insn (\"depi 0,31,2,%0\", xoperands);
2970 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2971 CODE_LABEL_NUMBER (xoperands[2]));
2973 /* If we're trying to load the address of a label that happens to be
2974 close, then we can use a shorter sequence. */
2975 if (GET_CODE (operands[1]) == LABEL_REF
2976 && !LABEL_REF_NONLOCAL_P (operands[1])
2977 && INSN_ADDRESSES_SET_P ()
2978 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2979 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2980 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2981 else
2982 {
2983 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2984 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2985 }
2986 return \"\";
2987 }"
2988 [(set_attr "type" "multi")
2989 (set_attr "length" "16")]) ; 12 or 16
2991 (define_insn ""
2992 [(set (match_operand:SI 0 "register_operand" "=a")
2993 (plus:SI (match_operand:SI 1 "register_operand" "r")
2994 (high:SI (match_operand 2 "" ""))))]
2995 "symbolic_operand (operands[2], Pmode)
2996 && ! function_label_operand (operands[2], Pmode)
2997 && flag_pic"
2998 "addil LT'%G2,%1"
2999 [(set_attr "type" "binary")
3000 (set_attr "length" "4")])
3002 (define_insn ""
3003 [(set (match_operand:DI 0 "register_operand" "=a")
3004 (plus:DI (match_operand:DI 1 "register_operand" "r")
3005 (high:DI (match_operand 2 "" ""))))]
3006 "symbolic_operand (operands[2], Pmode)
3007 && ! function_label_operand (operands[2], Pmode)
3008 && TARGET_64BIT
3009 && flag_pic"
3010 "addil LT'%G2,%1"
3011 [(set_attr "type" "binary")
3012 (set_attr "length" "4")])
3014 ;; Always use addil rather than ldil;add sequences. This allows the
3015 ;; HP linker to eliminate the dp relocation if the symbolic operand
3016 ;; lives in the TEXT space.
3017 (define_insn ""
3018 [(set (match_operand:SI 0 "register_operand" "=a")
3019 (high:SI (match_operand 1 "" "")))]
3020 "symbolic_operand (operands[1], Pmode)
3021 && ! function_label_operand (operands[1], Pmode)
3022 && ! read_only_operand (operands[1], Pmode)
3023 && ! flag_pic"
3024 "*
3025 {
3026 if (TARGET_LONG_LOAD_STORE)
3027 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
3028 else
3029 return \"addil LR'%H1,%%r27\";
3030 }"
3031 [(set_attr "type" "binary")
3032 (set (attr "length")
3033 (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
3034 (const_int 4)
3035 (const_int 8)))])
3038 ;; This is for use in the prologue/epilogue code. We need it
3039 ;; to add large constants to a stack pointer or frame pointer.
3040 ;; Because of the additional %r1 pressure, we probably do not
3041 ;; want to use this in general code, so make it available
3042 ;; only after reload.
3043 (define_insn ""
3044 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
3045 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
3046 (high:SI (match_operand 2 "const_int_operand" ""))))]
3047 "reload_completed"
3048 "@
3049 addil L'%G2,%1
3050 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
3051 [(set_attr "type" "binary,binary")
3052 (set_attr "length" "4,8")])
3054 (define_insn ""
3055 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
3056 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
3057 (high:DI (match_operand 2 "const_int_operand" ""))))]
3058 "reload_completed && TARGET_64BIT"
3059 "@
3060 addil L'%G2,%1
3061 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
3062 [(set_attr "type" "binary,binary")
3063 (set_attr "length" "4,8")])
3065 (define_insn ""
3066 [(set (match_operand:SI 0 "register_operand" "=r")
3067 (high:SI (match_operand 1 "" "")))]
3068 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
3069 && !is_function_label_plus_const (operands[1])"
3070 "*
3071 {
3072 if (symbolic_operand (operands[1], Pmode))
3073 return \"ldil LR'%H1,%0\";
3074 else
3075 return \"ldil L'%G1,%0\";
3076 }"
3077 [(set_attr "type" "move")
3078 (set_attr "length" "4")])
3080 (define_insn ""
3081 [(set (match_operand:DI 0 "register_operand" "=r")
3082 (high:DI (match_operand 1 "const_int_operand" "")))]
3083 "TARGET_64BIT"
3084 "ldil L'%G1,%0";
3085 [(set_attr "type" "move")
3086 (set_attr "length" "4")])
3088 (define_insn ""
3089 [(set (match_operand:DI 0 "register_operand" "=r")
3090 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
3091 (match_operand:DI 2 "const_int_operand" "i")))]
3092 "TARGET_64BIT"
3093 "ldo R'%G2(%1),%0";
3094 [(set_attr "type" "move")
3095 (set_attr "length" "4")])
3097 (define_insn ""
3098 [(set (match_operand:SI 0 "register_operand" "=r")
3099 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
3100 (match_operand:SI 2 "immediate_operand" "i")))]
3101 "!is_function_label_plus_const (operands[2])"
3102 "*
3103 {
3104 gcc_assert (!flag_pic || !symbolic_operand (operands[2], Pmode));
3106 if (symbolic_operand (operands[2], Pmode))
3107 return \"ldo RR'%G2(%1),%0\";
3108 else
3109 return \"ldo R'%G2(%1),%0\";
3110 }"
3111 [(set_attr "type" "move")
3112 (set_attr "length" "4")])
3114 ;; Now that a symbolic_address plus a constant is broken up early
3115 ;; in the compilation phase (for better CSE) we need a special
3116 ;; combiner pattern to load the symbolic address plus the constant
3117 ;; in only 2 instructions. (For cases where the symbolic address
3118 ;; was not a common subexpression.)
3119 (define_split
3120 [(set (match_operand:SI 0 "register_operand" "")
3121 (match_operand:SI 1 "symbolic_operand" ""))
3122 (clobber (match_operand:SI 2 "register_operand" ""))]
3123 "! (flag_pic && pic_label_operand (operands[1], SImode))"
3124 [(set (match_dup 2) (high:SI (match_dup 1)))
3125 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
3126 "")
3128 ;; hppa_legitimize_address goes to a great deal of trouble to
3129 ;; create addresses which use indexing. In some cases, this
3130 ;; is a lose because there isn't any store instructions which
3131 ;; allow indexed addresses (with integer register source).
3132 ;;
3133 ;; These define_splits try to turn a 3 insn store into
3134 ;; a 2 insn store with some creative RTL rewriting.
3135 (define_split
3136 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
3137 (match_operand:SI 1 "shadd_operand" ""))
3138 (plus:SI (match_operand:SI 2 "register_operand" "")
3139 (match_operand:SI 3 "const_int_operand" ""))))
3140 (match_operand:SI 4 "register_operand" ""))
3141 (clobber (match_operand:SI 5 "register_operand" ""))]
3142 ""
3143 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
3144 (match_dup 2)))
3145 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
3146 "")
3148 (define_split
3149 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
3150 (match_operand:SI 1 "shadd_operand" ""))
3151 (plus:SI (match_operand:SI 2 "register_operand" "")
3152 (match_operand:SI 3 "const_int_operand" ""))))
3153 (match_operand:HI 4 "register_operand" ""))
3154 (clobber (match_operand:SI 5 "register_operand" ""))]
3155 ""
3156 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
3157 (match_dup 2)))
3158 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
3159 "")
3161 (define_split
3162 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
3163 (match_operand:SI 1 "shadd_operand" ""))
3164 (plus:SI (match_operand:SI 2 "register_operand" "")
3165 (match_operand:SI 3 "const_int_operand" ""))))
3166 (match_operand:QI 4 "register_operand" ""))
3167 (clobber (match_operand:SI 5 "register_operand" ""))]
3168 ""
3169 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
3170 (match_dup 2)))
3171 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
3172 "")
3174 (define_expand "movhi"
3175 [(set (match_operand:HI 0 "general_operand" "")
3176 (match_operand:HI 1 "general_operand" ""))]
3177 ""
3178 "
3179 {
3180 if (emit_move_sequence (operands, HImode, 0))
3181 DONE;
3182 }")
3184 (define_insn ""
3185 [(set (match_operand:HI 0 "move_dest_operand"
3186 "=r,r,r,r,r,Q,!*q,!r,!*f,?r,?*f")
3187 (match_operand:HI 1 "move_src_operand"
3188 "r,J,N,K,RQ,rM,!rM,!*q,!*fM,*f,r"))]
3189 "(register_operand (operands[0], HImode)
3190 || reg_or_0_operand (operands[1], HImode))
3191 && !TARGET_SOFT_FLOAT
3192 && !TARGET_64BIT"
3193 "@
3194 copy %1,%0
3195 ldi %1,%0
3196 ldil L'%1,%0
3197 {zdepi|depwi,z} %Z1,%0
3198 ldh%M1 %1,%0
3199 sth%M0 %r1,%0
3200 mtsar %r1
3201 {mfctl|mfctl,w} %sar,%0
3202 fcpy,sgl %f1,%0
3203 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
3204 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
3205 [(set_attr "type" "move,move,move,shift,load,store,move,move,move,fpstore_load,store_fpload")
3206 (set_attr "pa_combine_type" "addmove")
3207 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,8")])
3209 (define_insn ""
3210 [(set (match_operand:HI 0 "move_dest_operand"
3211 "=r,r,r,r,r,Q,!*q,!r,!*f")
3212 (match_operand:HI 1 "move_src_operand"
3213 "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))]
3214 "(register_operand (operands[0], HImode)
3215 || reg_or_0_operand (operands[1], HImode))
3216 && !TARGET_SOFT_FLOAT
3217 && TARGET_64BIT"
3218 "@
3219 copy %1,%0
3220 ldi %1,%0
3221 ldil L'%1,%0
3222 {zdepi|depwi,z} %Z1,%0
3223 ldh%M1 %1,%0
3224 sth%M0 %r1,%0
3225 mtsar %r1
3226 {mfctl|mfctl,w} %sar,%0
3227 fcpy,sgl %f1,%0"
3228 [(set_attr "type" "move,move,move,shift,load,store,move,move,move")
3229 (set_attr "pa_combine_type" "addmove")
3230 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
3232 (define_insn ""
3233 [(set (match_operand:HI 0 "move_dest_operand"
3234 "=r,r,r,r,r,Q,!*q,!r")
3235 (match_operand:HI 1 "move_src_operand"
3236 "r,J,N,K,RQ,rM,!rM,!*q"))]
3237 "(register_operand (operands[0], HImode)
3238 || reg_or_0_operand (operands[1], HImode))
3239 && TARGET_SOFT_FLOAT"
3240 "@
3241 copy %1,%0
3242 ldi %1,%0
3243 ldil L'%1,%0
3244 {zdepi|depwi,z} %Z1,%0
3245 ldh%M1 %1,%0
3246 sth%M0 %r1,%0
3247 mtsar %r1
3248 {mfctl|mfctl,w} %sar,%0"
3249 [(set_attr "type" "move,move,move,shift,load,store,move,move")
3250 (set_attr "pa_combine_type" "addmove")
3251 (set_attr "length" "4,4,4,4,4,4,4,4")])
3253 (define_insn ""
3254 [(set (match_operand:HI 0 "register_operand" "=r")
3255 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
3256 (match_operand:SI 2 "int5_operand" "L"))))
3257 (set (match_dup 1)
3258 (plus:SI (match_dup 1) (match_dup 2)))]
3259 ""
3260 "{ldhs|ldh},mb %2(%1),%0"
3261 [(set_attr "type" "load")
3262 (set_attr "length" "4")])
3264 (define_insn ""
3265 [(set (match_operand:HI 0 "register_operand" "=r")
3266 (mem:HI (plus:DI (match_operand:DI 1 "register_operand" "+r")
3267 (match_operand:DI 2 "int5_operand" "L"))))
3268 (set (match_dup 1)
3269 (plus:DI (match_dup 1) (match_dup 2)))]
3270 "TARGET_64BIT"
3271 "ldh,mb %2(%1),%0"
3272 [(set_attr "type" "load")
3273 (set_attr "length" "4")])
3275 ; And a zero extended variant.
3276 (define_insn ""
3277 [(set (match_operand:DI 0 "register_operand" "=r")
3278 (zero_extend:DI (mem:HI
3279 (plus:DI
3280 (match_operand:DI 1 "register_operand" "+r")
3281 (match_operand:DI 2 "int5_operand" "L")))))
3282 (set (match_dup 1)
3283 (plus:DI (match_dup 1) (match_dup 2)))]
3284 "TARGET_64BIT"
3285 "ldh,mb %2(%1),%0"
3286 [(set_attr "type" "load")
3287 (set_attr "length" "4")])
3289 (define_insn ""
3290 [(set (match_operand:SI 0 "register_operand" "=r")
3291 (zero_extend:SI (mem:HI
3292 (plus:SI
3293 (match_operand:SI 1 "register_operand" "+r")
3294 (match_operand:SI 2 "int5_operand" "L")))))
3295 (set (match_dup 1)
3296 (plus:SI (match_dup 1) (match_dup 2)))]
3297 ""
3298 "{ldhs|ldh},mb %2(%1),%0"
3299 [(set_attr "type" "load")
3300 (set_attr "length" "4")])
3302 (define_insn ""
3303 [(set (match_operand:SI 0 "register_operand" "=r")
3304 (zero_extend:SI (mem:HI
3305 (plus:DI
3306 (match_operand:DI 1 "register_operand" "+r")
3307 (match_operand:DI 2 "int5_operand" "L")))))
3308 (set (match_dup 1)
3309 (plus:DI (match_dup 1) (match_dup 2)))]
3310 "TARGET_64BIT"
3311 "ldh,mb %2(%1),%0"
3312 [(set_attr "type" "load")
3313 (set_attr "length" "4")])
3315 (define_insn ""
3316 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3317 (match_operand:SI 1 "int5_operand" "L")))
3318 (match_operand:HI 2 "reg_or_0_operand" "rM"))
3319 (set (match_dup 0)
3320 (plus:SI (match_dup 0) (match_dup 1)))]
3321 ""
3322 "{sths|sth},mb %r2,%1(%0)"
3323 [(set_attr "type" "store")
3324 (set_attr "length" "4")])
3326 (define_insn ""
3327 [(set (mem:HI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3328 (match_operand:DI 1 "int5_operand" "L")))
3329 (match_operand:HI 2 "reg_or_0_operand" "rM"))
3330 (set (match_dup 0)
3331 (plus:DI (match_dup 0) (match_dup 1)))]
3332 "TARGET_64BIT"
3333 "sth,mb %r2,%1(%0)"
3334 [(set_attr "type" "store")
3335 (set_attr "length" "4")])
3337 (define_insn ""
3338 [(set (match_operand:HI 0 "register_operand" "=r")
3339 (plus:HI (match_operand:HI 1 "register_operand" "r")
3340 (match_operand 2 "const_int_operand" "J")))]
3341 ""
3342 "ldo %2(%1),%0"
3343 [(set_attr "type" "binary")
3344 (set_attr "pa_combine_type" "addmove")
3345 (set_attr "length" "4")])
3347 (define_expand "movqi"
3348 [(set (match_operand:QI 0 "general_operand" "")
3349 (match_operand:QI 1 "general_operand" ""))]
3350 ""
3351 "
3352 {
3353 if (emit_move_sequence (operands, QImode, 0))
3354 DONE;
3355 }")
3357 (define_insn ""
3358 [(set (match_operand:QI 0 "move_dest_operand"
3359 "=r,r,r,r,r,Q,!*q,!r,!*f,?r,?*f")
3360 (match_operand:QI 1 "move_src_operand"
3361 "r,J,N,K,RQ,rM,!rM,!*q,!*fM,*f,r"))]
3362 "(register_operand (operands[0], QImode)
3363 || reg_or_0_operand (operands[1], QImode))
3364 && !TARGET_SOFT_FLOAT
3365 && !TARGET_64BIT"
3366 "@
3367 copy %1,%0
3368 ldi %1,%0
3369 ldil L'%1,%0
3370 {zdepi|depwi,z} %Z1,%0
3371 ldb%M1 %1,%0
3372 stb%M0 %r1,%0
3373 mtsar %r1
3374 {mfctl|mfctl,w} %%sar,%0
3375 fcpy,sgl %f1,%0
3376 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
3377 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
3378 [(set_attr "type" "move,move,move,shift,load,store,move,move,move,fpstore_load,store_fpload")
3379 (set_attr "pa_combine_type" "addmove")
3380 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,8")])
3382 (define_insn ""
3383 [(set (match_operand:QI 0 "move_dest_operand"
3384 "=r,r,r,r,r,Q,!*q,!r,!*f")
3385 (match_operand:QI 1 "move_src_operand"
3386 "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))]
3387 "(register_operand (operands[0], QImode)
3388 || reg_or_0_operand (operands[1], QImode))
3389 && !TARGET_SOFT_FLOAT
3390 && TARGET_64BIT"
3391 "@
3392 copy %1,%0
3393 ldi %1,%0
3394 ldil L'%1,%0
3395 {zdepi|depwi,z} %Z1,%0
3396 ldb%M1 %1,%0
3397 stb%M0 %r1,%0
3398 mtsar %r1
3399 {mfctl|mfctl,w} %%sar,%0
3400 fcpy,sgl %f1,%0"
3401 [(set_attr "type" "move,move,move,shift,load,store,move,move,move")
3402 (set_attr "pa_combine_type" "addmove")
3403 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
3405 (define_insn ""
3406 [(set (match_operand:QI 0 "move_dest_operand"
3407 "=r,r,r,r,r,Q,!*q,!r")
3408 (match_operand:QI 1 "move_src_operand"
3409 "r,J,N,K,RQ,rM,!rM,!*q"))]
3410 "(register_operand (operands[0], QImode)
3411 || reg_or_0_operand (operands[1], QImode))
3412 && TARGET_SOFT_FLOAT"
3413 "@
3414 copy %1,%0
3415 ldi %1,%0
3416 ldil L'%1,%0
3417 {zdepi|depwi,z} %Z1,%0
3418 ldb%M1 %1,%0
3419 stb%M0 %r1,%0
3420 mtsar %r1
3421 {mfctl|mfctl,w} %%sar,%0"
3422 [(set_attr "type" "move,move,move,shift,load,store,move,move")
3423 (set_attr "pa_combine_type" "addmove")
3424 (set_attr "length" "4,4,4,4,4,4,4,4")])
3426 (define_insn ""
3427 [(set (match_operand:QI 0 "register_operand" "=r")
3428 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
3429 (match_operand:SI 2 "int5_operand" "L"))))
3430 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3431 ""
3432 "{ldbs|ldb},mb %2(%1),%0"
3433 [(set_attr "type" "load")
3434 (set_attr "length" "4")])
3436 (define_insn ""
3437 [(set (match_operand:QI 0 "register_operand" "=r")
3438 (mem:QI (plus:DI (match_operand:DI 1 "register_operand" "+r")
3439 (match_operand:DI 2 "int5_operand" "L"))))
3440 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3441 "TARGET_64BIT"
3442 "ldb,mb %2(%1),%0"
3443 [(set_attr "type" "load")
3444 (set_attr "length" "4")])
3446 ; Now the same thing with zero extensions.
3447 (define_insn ""
3448 [(set (match_operand:DI 0 "register_operand" "=r")
3449 (zero_extend:DI (mem:QI (plus:DI
3450 (match_operand:DI 1 "register_operand" "+r")
3451 (match_operand:DI 2 "int5_operand" "L")))))
3452 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3453 "TARGET_64BIT"
3454 "ldb,mb %2(%1),%0"
3455 [(set_attr "type" "load")
3456 (set_attr "length" "4")])
3458 (define_insn ""
3459 [(set (match_operand:SI 0 "register_operand" "=r")
3460 (zero_extend:SI (mem:QI (plus:SI
3461 (match_operand:SI 1 "register_operand" "+r")
3462 (match_operand:SI 2 "int5_operand" "L")))))
3463 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3464 ""
3465 "{ldbs|ldb},mb %2(%1),%0"
3466 [(set_attr "type" "load")
3467 (set_attr "length" "4")])
3469 (define_insn ""
3470 [(set (match_operand:SI 0 "register_operand" "=r")
3471 (zero_extend:SI (mem:QI (plus:DI
3472 (match_operand:DI 1 "register_operand" "+r")
3473 (match_operand:DI 2 "int5_operand" "L")))))
3474 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3475 "TARGET_64BIT"
3476 "ldb,mb %2(%1),%0"
3477 [(set_attr "type" "load")
3478 (set_attr "length" "4")])
3480 (define_insn ""
3481 [(set (match_operand:HI 0 "register_operand" "=r")
3482 (zero_extend:HI (mem:QI (plus:SI
3483 (match_operand:SI 1 "register_operand" "+r")
3484 (match_operand:SI 2 "int5_operand" "L")))))
3485 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3486 ""
3487 "{ldbs|ldb},mb %2(%1),%0"
3488 [(set_attr "type" "load")
3489 (set_attr "length" "4")])
3491 (define_insn ""
3492 [(set (match_operand:HI 0 "register_operand" "=r")
3493 (zero_extend:HI (mem:QI (plus:DI
3494 (match_operand:DI 1 "register_operand" "+r")
3495 (match_operand:DI 2 "int5_operand" "L")))))
3496 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3497 "TARGET_64BIT"
3498 "ldb,mb %2(%1),%0"
3499 [(set_attr "type" "load")
3500 (set_attr "length" "4")])
3502 (define_insn ""
3503 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3504 (match_operand:SI 1 "int5_operand" "L")))
3505 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3506 (set (match_dup 0)
3507 (plus:SI (match_dup 0) (match_dup 1)))]
3508 ""
3509 "{stbs|stb},mb %r2,%1(%0)"
3510 [(set_attr "type" "store")
3511 (set_attr "length" "4")])
3513 (define_insn ""
3514 [(set (mem:QI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3515 (match_operand:DI 1 "int5_operand" "L")))
3516 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3517 (set (match_dup 0)
3518 (plus:DI (match_dup 0) (match_dup 1)))]
3519 "TARGET_64BIT"
3520 "stb,mb %r2,%1(%0)"
3521 [(set_attr "type" "store")
3522 (set_attr "length" "4")])
3524 ;; The definition of this insn does not really explain what it does,
3525 ;; but it should suffice that anything generated as this insn will be
3526 ;; recognized as a movmemsi operation, and that it will not successfully
3527 ;; combine with anything.
3528 (define_expand "movmemsi"
3529 [(parallel [(set (match_operand:BLK 0 "" "")
3530 (match_operand:BLK 1 "" ""))
3531 (clobber (match_dup 4))
3532 (clobber (match_dup 5))
3533 (clobber (match_dup 6))
3534 (clobber (match_dup 7))
3535 (clobber (match_dup 8))
3536 (use (match_operand:SI 2 "arith_operand" ""))
3537 (use (match_operand:SI 3 "const_int_operand" ""))])]
3538 "!TARGET_64BIT && optimize > 0"
3539 "
3540 {
3541 int size, align;
3543 /* HP provides very fast block move library routine for the PA;
3544 this routine includes:
3546 4x4 byte at a time block moves,
3547 1x4 byte at a time with alignment checked at runtime with
3548 attempts to align the source and destination as needed
3549 1x1 byte loop
3551 With that in mind, here's the heuristics to try and guess when
3552 the inlined block move will be better than the library block
3553 move:
3555 If the size isn't constant, then always use the library routines.
3557 If the size is large in respect to the known alignment, then use
3558 the library routines.
3560 If the size is small in respect to the known alignment, then open
3561 code the copy (since that will lead to better scheduling).
3563 Else use the block move pattern. */
3565 /* Undetermined size, use the library routine. */
3566 if (GET_CODE (operands[2]) != CONST_INT)
3567 FAIL;
3569 size = INTVAL (operands[2]);
3570 align = INTVAL (operands[3]);
3571 align = align > 4 ? 4 : align;
3573 /* If size/alignment is large, then use the library routines. */
3574 if (size / align > 16)
3575 FAIL;
3577 /* This does happen, but not often enough to worry much about. */
3578 if (size / align < MOVE_RATIO)
3579 FAIL;
3581 /* Fall through means we're going to use our block move pattern. */
3582 operands[0]
3583 = replace_equiv_address (operands[0],
3584 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3585 operands[1]
3586 = replace_equiv_address (operands[1],
3587 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
3588 operands[4] = gen_reg_rtx (SImode);
3589 operands[5] = gen_reg_rtx (SImode);
3590 operands[6] = gen_reg_rtx (SImode);
3591 operands[7] = gen_reg_rtx (SImode);
3592 operands[8] = gen_reg_rtx (SImode);
3593 }")
3595 ;; The operand constraints are written like this to support both compile-time
3596 ;; and run-time determined byte counts. The expander and output_block_move
3597 ;; only support compile-time determined counts at this time.
3598 ;;
3599 ;; If the count is run-time determined, the register with the byte count
3600 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3601 ;;
3602 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3603 ;; broke this semantic for pseudo registers. We can't use match_scratch
3604 ;; as this requires two registers in the class R1_REGS when the MEMs for
3605 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3606 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3607 ;; respectively. We then split or peephole optimize after reload.
3608 (define_insn "movmemsi_prereload"
3609 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3610 (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
3611 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3612 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3613 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3614 (clobber (match_operand:SI 7 "register_operand" "=&r,&r")) ;item tmp3
3615 (clobber (match_operand:SI 8 "register_operand" "=&r,&r")) ;item tmp4
3616 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3617 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
3618 "!TARGET_64BIT"
3619 "#"
3620 [(set_attr "type" "multi,multi")])
3622 (define_split
3623 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3624 (match_operand:BLK 1 "memory_operand" ""))
3625 (clobber (match_operand:SI 2 "register_operand" ""))
3626 (clobber (match_operand:SI 3 "register_operand" ""))
3627 (clobber (match_operand:SI 6 "register_operand" ""))
3628 (clobber (match_operand:SI 7 "register_operand" ""))
3629 (clobber (match_operand:SI 8 "register_operand" ""))
3630 (use (match_operand:SI 4 "arith_operand" ""))
3631 (use (match_operand:SI 5 "const_int_operand" ""))])]
3632 "!TARGET_64BIT && reload_completed && !flag_peephole2
3633 && GET_CODE (operands[0]) == MEM
3634 && register_operand (XEXP (operands[0], 0), SImode)
3635 && GET_CODE (operands[1]) == MEM
3636 && register_operand (XEXP (operands[1], 0), SImode)"
3637 [(set (match_dup 7) (match_dup 9))
3638 (set (match_dup 8) (match_dup 10))
3639 (parallel [(set (match_dup 0) (match_dup 1))
3640 (clobber (match_dup 2))
3641 (clobber (match_dup 3))
3642 (clobber (match_dup 6))
3643 (clobber (match_dup 7))
3644 (clobber (match_dup 8))
3645 (use (match_dup 4))
3646 (use (match_dup 5))
3647 (const_int 0)])]
3648 "
3649 {
3650 operands[9] = XEXP (operands[0], 0);
3651 operands[10] = XEXP (operands[1], 0);
3652 operands[0] = replace_equiv_address (operands[0], operands[7]);
3653 operands[1] = replace_equiv_address (operands[1], operands[8]);
3654 }")
3656 (define_peephole2
3657 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3658 (match_operand:BLK 1 "memory_operand" ""))
3659 (clobber (match_operand:SI 2 "register_operand" ""))
3660 (clobber (match_operand:SI 3 "register_operand" ""))
3661 (clobber (match_operand:SI 6 "register_operand" ""))
3662 (clobber (match_operand:SI 7 "register_operand" ""))
3663 (clobber (match_operand:SI 8 "register_operand" ""))
3664 (use (match_operand:SI 4 "arith_operand" ""))
3665 (use (match_operand:SI 5 "const_int_operand" ""))])]
3666 "!TARGET_64BIT
3667 && GET_CODE (operands[0]) == MEM
3668 && register_operand (XEXP (operands[0], 0), SImode)
3669 && GET_CODE (operands[1]) == MEM
3670 && register_operand (XEXP (operands[1], 0), SImode)"
3671 [(parallel [(set (match_dup 0) (match_dup 1))
3672 (clobber (match_dup 2))
3673 (clobber (match_dup 3))
3674 (clobber (match_dup 6))
3675 (clobber (match_dup 7))
3676 (clobber (match_dup 8))
3677 (use (match_dup 4))
3678 (use (match_dup 5))
3679 (const_int 0)])]
3680 "
3681 {
3682 rtx addr = XEXP (operands[0], 0);
3683 if (dead_or_set_p (curr_insn, addr))
3684 operands[7] = addr;
3685 else
3686 {
3687 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3688 operands[0] = replace_equiv_address (operands[0], operands[7]);
3689 }
3691 addr = XEXP (operands[1], 0);
3692 if (dead_or_set_p (curr_insn, addr))
3693 operands[8] = addr;
3694 else
3695 {
3696 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3697 operands[1] = replace_equiv_address (operands[1], operands[8]);
3698 }
3699 }")
3701 (define_insn "movmemsi_postreload"
3702 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3703 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
3704 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3705 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3706 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3707 (clobber (match_dup 0))
3708 (clobber (match_dup 1))
3709 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3710 (use (match_operand:SI 5 "const_int_operand" "n,n")) ;alignment
3711 (const_int 0)]
3712 "!TARGET_64BIT && reload_completed"
3713 "* return output_block_move (operands, !which_alternative);"
3714 [(set_attr "type" "multi,multi")])
3716 (define_expand "movmemdi"
3717 [(parallel [(set (match_operand:BLK 0 "" "")
3718 (match_operand:BLK 1 "" ""))
3719 (clobber (match_dup 4))
3720 (clobber (match_dup 5))
3721 (clobber (match_dup 6))
3722 (clobber (match_dup 7))
3723 (clobber (match_dup 8))
3724 (use (match_operand:DI 2 "arith_operand" ""))
3725 (use (match_operand:DI 3 "const_int_operand" ""))])]
3726 "TARGET_64BIT && optimize > 0"
3727 "
3728 {
3729 int size, align;
3731 /* HP provides very fast block move library routine for the PA;
3732 this routine includes:
3734 4x4 byte at a time block moves,
3735 1x4 byte at a time with alignment checked at runtime with
3736 attempts to align the source and destination as needed
3737 1x1 byte loop
3739 With that in mind, here's the heuristics to try and guess when
3740 the inlined block move will be better than the library block
3741 move:
3743 If the size isn't constant, then always use the library routines.
3745 If the size is large in respect to the known alignment, then use
3746 the library routines.
3748 If the size is small in respect to the known alignment, then open
3749 code the copy (since that will lead to better scheduling).
3751 Else use the block move pattern. */
3753 /* Undetermined size, use the library routine. */
3754 if (GET_CODE (operands[2]) != CONST_INT)
3755 FAIL;
3757 size = INTVAL (operands[2]);
3758 align = INTVAL (operands[3]);
3759 align = align > 8 ? 8 : align;
3761 /* If size/alignment is large, then use the library routines. */
3762 if (size / align > 16)
3763 FAIL;
3765 /* This does happen, but not often enough to worry much about. */
3766 if (size / align < MOVE_RATIO)
3767 FAIL;
3769 /* Fall through means we're going to use our block move pattern. */
3770 operands[0]
3771 = replace_equiv_address (operands[0],
3772 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3773 operands[1]
3774 = replace_equiv_address (operands[1],
3775 copy_to_mode_reg (DImode, XEXP (operands[1], 0)));
3776 operands[4] = gen_reg_rtx (DImode);
3777 operands[5] = gen_reg_rtx (DImode);
3778 operands[6] = gen_reg_rtx (DImode);
3779 operands[7] = gen_reg_rtx (DImode);
3780 operands[8] = gen_reg_rtx (DImode);
3781 }")
3783 ;; The operand constraints are written like this to support both compile-time
3784 ;; and run-time determined byte counts. The expander and output_block_move
3785 ;; only support compile-time determined counts at this time.
3786 ;;
3787 ;; If the count is run-time determined, the register with the byte count
3788 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3789 ;;
3790 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3791 ;; broke this semantic for pseudo registers. We can't use match_scratch
3792 ;; as this requires two registers in the class R1_REGS when the MEMs for
3793 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3794 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3795 ;; respectively. We then split or peephole optimize after reload.
3796 (define_insn "movmemdi_prereload"
3797 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3798 (mem:BLK (match_operand:DI 1 "register_operand" "r,r")))
3799 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3800 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3801 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3802 (clobber (match_operand:DI 7 "register_operand" "=&r,&r")) ;item tmp3
3803 (clobber (match_operand:DI 8 "register_operand" "=&r,&r")) ;item tmp4
3804 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3805 (use (match_operand:DI 5 "const_int_operand" "n,n"))] ;alignment
3806 "TARGET_64BIT"
3807 "#"
3808 [(set_attr "type" "multi,multi")])
3810 (define_split
3811 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3812 (match_operand:BLK 1 "memory_operand" ""))
3813 (clobber (match_operand:DI 2 "register_operand" ""))
3814 (clobber (match_operand:DI 3 "register_operand" ""))
3815 (clobber (match_operand:DI 6 "register_operand" ""))
3816 (clobber (match_operand:DI 7 "register_operand" ""))
3817 (clobber (match_operand:DI 8 "register_operand" ""))
3818 (use (match_operand:DI 4 "arith_operand" ""))
3819 (use (match_operand:DI 5 "const_int_operand" ""))])]
3820 "TARGET_64BIT && reload_completed && !flag_peephole2
3821 && GET_CODE (operands[0]) == MEM
3822 && register_operand (XEXP (operands[0], 0), DImode)
3823 && GET_CODE (operands[1]) == MEM
3824 && register_operand (XEXP (operands[1], 0), DImode)"
3825 [(set (match_dup 7) (match_dup 9))
3826 (set (match_dup 8) (match_dup 10))
3827 (parallel [(set (match_dup 0) (match_dup 1))
3828 (clobber (match_dup 2))
3829 (clobber (match_dup 3))
3830 (clobber (match_dup 6))
3831 (clobber (match_dup 7))
3832 (clobber (match_dup 8))
3833 (use (match_dup 4))
3834 (use (match_dup 5))
3835 (const_int 0)])]
3836 "
3837 {
3838 operands[9] = XEXP (operands[0], 0);
3839 operands[10] = XEXP (operands[1], 0);
3840 operands[0] = replace_equiv_address (operands[0], operands[7]);
3841 operands[1] = replace_equiv_address (operands[1], operands[8]);
3842 }")
3844 (define_peephole2
3845 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3846 (match_operand:BLK 1 "memory_operand" ""))
3847 (clobber (match_operand:DI 2 "register_operand" ""))
3848 (clobber (match_operand:DI 3 "register_operand" ""))
3849 (clobber (match_operand:DI 6 "register_operand" ""))
3850 (clobber (match_operand:DI 7 "register_operand" ""))
3851 (clobber (match_operand:DI 8 "register_operand" ""))
3852 (use (match_operand:DI 4 "arith_operand" ""))
3853 (use (match_operand:DI 5 "const_int_operand" ""))])]
3854 "TARGET_64BIT
3855 && GET_CODE (operands[0]) == MEM
3856 && register_operand (XEXP (operands[0], 0), DImode)
3857 && GET_CODE (operands[1]) == MEM
3858 && register_operand (XEXP (operands[1], 0), DImode)"
3859 [(parallel [(set (match_dup 0) (match_dup 1))
3860 (clobber (match_dup 2))
3861 (clobber (match_dup 3))
3862 (clobber (match_dup 6))
3863 (clobber (match_dup 7))
3864 (clobber (match_dup 8))
3865 (use (match_dup 4))
3866 (use (match_dup 5))
3867 (const_int 0)])]
3868 "
3869 {
3870 rtx addr = XEXP (operands[0], 0);
3871 if (dead_or_set_p (curr_insn, addr))
3872 operands[7] = addr;
3873 else
3874 {
3875 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3876 operands[0] = replace_equiv_address (operands[0], operands[7]);
3877 }
3879 addr = XEXP (operands[1], 0);
3880 if (dead_or_set_p (curr_insn, addr))
3881 operands[8] = addr;
3882 else
3883 {
3884 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3885 operands[1] = replace_equiv_address (operands[1], operands[8]);
3886 }
3887 }")
3889 (define_insn "movmemdi_postreload"
3890 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3891 (mem:BLK (match_operand:DI 1 "register_operand" "+r,r")))
3892 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3893 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3894 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3895 (clobber (match_dup 0))
3896 (clobber (match_dup 1))
3897 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3898 (use (match_operand:DI 5 "const_int_operand" "n,n")) ;alignment
3899 (const_int 0)]
3900 "TARGET_64BIT && reload_completed"
3901 "* return output_block_move (operands, !which_alternative);"
3902 [(set_attr "type" "multi,multi")])
3904 (define_expand "setmemsi"
3905 [(parallel [(set (match_operand:BLK 0 "" "")
3906 (match_operand 2 "const_int_operand" ""))
3907 (clobber (match_dup 4))
3908 (clobber (match_dup 5))
3909 (use (match_operand:SI 1 "arith_operand" ""))
3910 (use (match_operand:SI 3 "const_int_operand" ""))])]
3911 "!TARGET_64BIT && optimize > 0"
3912 "
3913 {
3914 int size, align;
3916 /* If value to set is not zero, use the library routine. */
3917 if (operands[2] != const0_rtx)
3918 FAIL;
3920 /* Undetermined size, use the library routine. */
3921 if (GET_CODE (operands[1]) != CONST_INT)
3922 FAIL;
3924 size = INTVAL (operands[1]);
3925 align = INTVAL (operands[3]);
3926 align = align > 4 ? 4 : align;
3928 /* If size/alignment is large, then use the library routines. */
3929 if (size / align > 16)
3930 FAIL;
3932 /* This does happen, but not often enough to worry much about. */
3933 if (size / align < MOVE_RATIO)
3934 FAIL;
3936 /* Fall through means we're going to use our block clear pattern. */
3937 operands[0]
3938 = replace_equiv_address (operands[0],
3939 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3940 operands[4] = gen_reg_rtx (SImode);
3941 operands[5] = gen_reg_rtx (SImode);
3942 }")
3944 (define_insn "clrmemsi_prereload"
3945 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3946 (const_int 0))
3947 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3948 (clobber (match_operand:SI 4 "register_operand" "=&r,&r")) ;tmp1
3949 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3950 (use (match_operand:SI 3 "const_int_operand" "n,n"))] ;alignment
3951 "!TARGET_64BIT"
3952 "#"
3953 [(set_attr "type" "multi,multi")])
3955 (define_split
3956 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3957 (const_int 0))
3958 (clobber (match_operand:SI 1 "register_operand" ""))
3959 (clobber (match_operand:SI 4 "register_operand" ""))
3960 (use (match_operand:SI 2 "arith_operand" ""))
3961 (use (match_operand:SI 3 "const_int_operand" ""))])]
3962 "!TARGET_64BIT && reload_completed && !flag_peephole2
3963 && GET_CODE (operands[0]) == MEM
3964 && register_operand (XEXP (operands[0], 0), SImode)"
3965 [(set (match_dup 4) (match_dup 5))
3966 (parallel [(set (match_dup 0) (const_int 0))
3967 (clobber (match_dup 1))
3968 (clobber (match_dup 4))
3969 (use (match_dup 2))
3970 (use (match_dup 3))
3971 (const_int 0)])]
3972 "
3973 {
3974 operands[5] = XEXP (operands[0], 0);
3975 operands[0] = replace_equiv_address (operands[0], operands[4]);
3976 }")
3978 (define_peephole2
3979 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3980 (const_int 0))
3981 (clobber (match_operand:SI 1 "register_operand" ""))
3982 (clobber (match_operand:SI 4 "register_operand" ""))
3983 (use (match_operand:SI 2 "arith_operand" ""))
3984 (use (match_operand:SI 3 "const_int_operand" ""))])]
3985 "!TARGET_64BIT
3986 && GET_CODE (operands[0]) == MEM
3987 && register_operand (XEXP (operands[0], 0), SImode)"
3988 [(parallel [(set (match_dup 0) (const_int 0))
3989 (clobber (match_dup 1))
3990 (clobber (match_dup 4))
3991 (use (match_dup 2))
3992 (use (match_dup 3))
3993 (const_int 0)])]
3994 "
3995 {
3996 rtx addr = XEXP (operands[0], 0);
3997 if (dead_or_set_p (curr_insn, addr))
3998 operands[4] = addr;
3999 else
4000 {
4001 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
4002 operands[0] = replace_equiv_address (operands[0], operands[4]);
4003 }
4004 }")
4006 (define_insn "clrmemsi_postreload"
4007 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
4008 (const_int 0))
4009 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
4010 (clobber (match_dup 0))
4011 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
4012 (use (match_operand:SI 3 "const_int_operand" "n,n")) ;alignment
4013 (const_int 0)]
4014 "!TARGET_64BIT && reload_completed"
4015 "* return output_block_clear (operands, !which_alternative);"
4016 [(set_attr "type" "multi,multi")])
4018 (define_expand "setmemdi"
4019 [(parallel [(set (match_operand:BLK 0 "" "")
4020 (match_operand 2 "const_int_operand" ""))
4021 (clobber (match_dup 4))
4022 (clobber (match_dup 5))
4023 (use (match_operand:DI 1 "arith_operand" ""))
4024 (use (match_operand:DI 3 "const_int_operand" ""))])]
4025 "TARGET_64BIT && optimize > 0"
4026 "
4027 {
4028 int size, align;
4030 /* If value to set is not zero, use the library routine. */
4031 if (operands[2] != const0_rtx)
4032 FAIL;
4034 /* Undetermined size, use the library routine. */
4035 if (GET_CODE (operands[1]) != CONST_INT)
4036 FAIL;
4038 size = INTVAL (operands[1]);
4039 align = INTVAL (operands[3]);
4040 align = align > 8 ? 8 : align;
4042 /* If size/alignment is large, then use the library routines. */
4043 if (size / align > 16)
4044 FAIL;
4046 /* This does happen, but not often enough to worry much about. */
4047 if (size / align < MOVE_RATIO)
4048 FAIL;
4050 /* Fall through means we're going to use our block clear pattern. */
4051 operands[0]
4052 = replace_equiv_address (operands[0],
4053 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
4054 operands[4] = gen_reg_rtx (DImode);
4055 operands[5] = gen_reg_rtx (DImode);
4056 }")
4058 (define_insn "clrmemdi_prereload"
4059 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
4060 (const_int 0))
4061 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
4062 (clobber (match_operand:DI 4 "register_operand" "=&r,&r")) ;item tmp1
4063 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
4064 (use (match_operand:DI 3 "const_int_operand" "n,n"))] ;alignment
4065 "TARGET_64BIT"
4066 "#"
4067 [(set_attr "type" "multi,multi")])
4069 (define_split
4070 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
4071 (const_int 0))
4072 (clobber (match_operand:DI 1 "register_operand" ""))
4073 (clobber (match_operand:DI 4 "register_operand" ""))
4074 (use (match_operand:DI 2 "arith_operand" ""))
4075 (use (match_operand:DI 3 "const_int_operand" ""))])]
4076 "TARGET_64BIT && reload_completed && !flag_peephole2
4077 && GET_CODE (operands[0]) == MEM
4078 && register_operand (XEXP (operands[0], 0), DImode)"
4079 [(set (match_dup 4) (match_dup 5))
4080 (parallel [(set (match_dup 0) (const_int 0))
4081 (clobber (match_dup 1))
4082 (clobber (match_dup 4))
4083 (use (match_dup 2))
4084 (use (match_dup 3))
4085 (const_int 0)])]
4086 "
4087 {
4088 operands[5] = XEXP (operands[0], 0);
4089 operands[0] = replace_equiv_address (operands[0], operands[4]);
4090 }")
4092 (define_peephole2
4093 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
4094 (const_int 0))
4095 (clobber (match_operand:DI 1 "register_operand" ""))
4096 (clobber (match_operand:DI 4 "register_operand" ""))
4097 (use (match_operand:DI 2 "arith_operand" ""))
4098 (use (match_operand:DI 3 "const_int_operand" ""))])]
4099 "TARGET_64BIT
4100 && GET_CODE (operands[0]) == MEM
4101 && register_operand (XEXP (operands[0], 0), DImode)"
4102 [(parallel [(set (match_dup 0) (const_int 0))
4103 (clobber (match_dup 1))
4104 (clobber (match_dup 4))
4105 (use (match_dup 2))
4106 (use (match_dup 3))
4107 (const_int 0)])]
4108 "
4109 {
4110 rtx addr = XEXP (operands[0], 0);
4111 if (dead_or_set_p (curr_insn, addr))
4112 operands[4] = addr;
4113 else
4114 {
4115 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
4116 operands[0] = replace_equiv_address (operands[0], operands[4]);
4117 }
4118 }")
4120 (define_insn "clrmemdi_postreload"
4121 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
4122 (const_int 0))
4123 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
4124 (clobber (match_dup 0))
4125 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
4126 (use (match_operand:DI 3 "const_int_operand" "n,n")) ;alignment
4127 (const_int 0)]
4128 "TARGET_64BIT && reload_completed"
4129 "* return output_block_clear (operands, !which_alternative);"
4130 [(set_attr "type" "multi,multi")])
4131 \f
4132 ;; Floating point move insns
4134 ;; This pattern forces (set (reg:DF ...) (const_double ...))
4135 ;; to be reloaded by putting the constant into memory when
4136 ;; reg is a floating point register.
4137 ;;
4138 ;; For integer registers we use ldil;ldo to set the appropriate
4139 ;; value.
4140 ;;
4141 ;; This must come before the movdf pattern, and it must be present
4142 ;; to handle obscure reloading cases.
4143 (define_insn ""
4144 [(set (match_operand:DF 0 "register_operand" "=?r,f")
4145 (match_operand:DF 1 "" "?F,m"))]
4146 "GET_CODE (operands[1]) == CONST_DOUBLE
4147 && operands[1] != CONST0_RTX (DFmode)
4148 && !TARGET_64BIT
4149 && !TARGET_SOFT_FLOAT"
4150 "* return (which_alternative == 0 ? output_move_double (operands)
4151 : \"fldd%F1 %1,%0\");"
4152 [(set_attr "type" "move,fpload")
4153 (set_attr "length" "16,4")])
4155 (define_expand "movdf"
4156 [(set (match_operand:DF 0 "general_operand" "")
4157 (match_operand:DF 1 "general_operand" ""))]
4158 ""
4159 "
4160 {
4161 if (GET_CODE (operands[1]) == CONST_DOUBLE
4162 && operands[1] != CONST0_RTX (DFmode))
4163 {
4164 /* Reject CONST_DOUBLE loads to all hard registers when
4165 generating 64-bit code and to floating point registers
4166 when generating 32-bit code. */
4167 if (REG_P (operands[0])
4168 && HARD_REGISTER_P (operands[0])
4169 && (TARGET_64BIT || REGNO (operands[0]) >= 32))
4170 FAIL;
4172 if (TARGET_64BIT)
4173 operands[1] = force_const_mem (DFmode, operands[1]);
4174 }
4176 if (emit_move_sequence (operands, DFmode, 0))
4177 DONE;
4178 }")
4180 ;; Handle DFmode input reloads requiring a general register as a
4181 ;; scratch register.
4182 (define_expand "reload_indf"
4183 [(set (match_operand:DF 0 "register_operand" "=Z")
4184 (match_operand:DF 1 "non_hard_reg_operand" ""))
4185 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
4186 ""
4187 "
4188 {
4189 if (emit_move_sequence (operands, DFmode, operands[2]))
4190 DONE;
4192 /* We don't want the clobber emitted, so handle this ourselves. */
4193 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4194 DONE;
4195 }")
4197 ;; Handle DFmode output reloads requiring a general register as a
4198 ;; scratch register.
4199 (define_expand "reload_outdf"
4200 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
4201 (match_operand:DF 1 "register_operand" "Z"))
4202 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
4203 ""
4204 "
4205 {
4206 if (emit_move_sequence (operands, DFmode, operands[2]))
4207 DONE;
4209 /* We don't want the clobber emitted, so handle this ourselves. */
4210 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4211 DONE;
4212 }")
4214 (define_insn ""
4215 [(set (match_operand:DF 0 "move_dest_operand"
4216 "=f,*r,Q,?o,?Q,f,*r,*r,?*r,?f")
4217 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
4218 "fG,*rG,f,*r,*r,RQ,o,RQ,f,*r"))]
4219 "(register_operand (operands[0], DFmode)
4220 || reg_or_0_operand (operands[1], DFmode))
4221 && !(GET_CODE (operands[1]) == CONST_DOUBLE
4222 && GET_CODE (operands[0]) == MEM)
4223 && !TARGET_64BIT
4224 && !TARGET_SOFT_FLOAT"
4225 "*
4226 {
4227 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4228 || operands[1] == CONST0_RTX (DFmode))
4229 && !(REG_P (operands[0]) && REG_P (operands[1])
4230 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
4231 return output_fp_move_double (operands);
4232 return output_move_double (operands);
4233 }"
4234 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load,fpstore_load,store_fpload")
4235 (set_attr "length" "4,8,4,8,16,4,8,16,12,12")])
4237 (define_insn ""
4238 [(set (match_operand:DF 0 "indexed_memory_operand" "=R")
4239 (match_operand:DF 1 "reg_or_0_operand" "f"))]
4240 "!TARGET_SOFT_FLOAT
4241 && !TARGET_DISABLE_INDEXING
4242 && reload_completed"
4243 "fstd%F0 %1,%0"
4244 [(set_attr "type" "fpstore")
4245 (set_attr "pa_combine_type" "addmove")
4246 (set_attr "length" "4")])
4248 (define_peephole2
4249 [(set (match_operand:SI 0 "register_operand" "")
4250 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4251 (const_int 8))
4252 (match_operand:SI 2 "register_operand" "")))
4253 (set (mem:DF (match_dup 0))
4254 (match_operand:DF 3 "register_operand" ""))]
4255 "!TARGET_SOFT_FLOAT
4256 && !TARGET_DISABLE_INDEXING
4257 && REG_OK_FOR_BASE_P (operands[2])
4258 && FP_REGNO_P (REGNO (operands[3]))"
4259 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
4260 (match_dup 3))
4261 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
4262 (match_dup 2)))]
4263 "")
4265 (define_peephole2
4266 [(set (match_operand:SI 0 "register_operand" "")
4267 (plus:SI (match_operand:SI 2 "register_operand" "")
4268 (mult:SI (match_operand:SI 1 "register_operand" "")
4269 (const_int 8))))
4270 (set (mem:DF (match_dup 0))
4271 (match_operand:DF 3 "register_operand" ""))]
4272 "!TARGET_SOFT_FLOAT
4273 && !TARGET_DISABLE_INDEXING
4274 && REG_OK_FOR_BASE_P (operands[2])
4275 && FP_REGNO_P (REGNO (operands[3]))"
4276 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
4277 (match_dup 3))
4278 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
4279 (match_dup 2)))]
4280 "")
4282 (define_peephole2
4283 [(set (match_operand:DI 0 "register_operand" "")
4284 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4285 (const_int 8))
4286 (match_operand:DI 2 "register_operand" "")))
4287 (set (mem:DF (match_dup 0))
4288 (match_operand:DF 3 "register_operand" ""))]
4289 "!TARGET_SOFT_FLOAT
4290 && !TARGET_DISABLE_INDEXING
4291 && TARGET_64BIT
4292 && REG_OK_FOR_BASE_P (operands[2])
4293 && FP_REGNO_P (REGNO (operands[3]))"
4294 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4295 (match_dup 3))
4296 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4297 (match_dup 2)))]
4298 "")
4300 (define_peephole2
4301 [(set (match_operand:DI 0 "register_operand" "")
4302 (plus:DI (match_operand:DI 2 "register_operand" "")
4303 (mult:DI (match_operand:DI 1 "register_operand" "")
4304 (const_int 8))))
4305 (set (mem:DF (match_dup 0))
4306 (match_operand:DF 3 "register_operand" ""))]
4307 "!TARGET_SOFT_FLOAT
4308 && !TARGET_DISABLE_INDEXING
4309 && TARGET_64BIT
4310 && REG_OK_FOR_BASE_P (operands[2])
4311 && FP_REGNO_P (REGNO (operands[3]))"
4312 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4313 (match_dup 3))
4314 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4315 (match_dup 2)))]
4316 "")
4318 (define_peephole2
4319 [(set (match_operand:SI 0 "register_operand" "")
4320 (plus:SI (match_operand:SI 1 "register_operand" "")
4321 (match_operand:SI 2 "register_operand" "")))
4322 (set (mem:DF (match_dup 0))
4323 (match_operand:DF 3 "register_operand" ""))]
4324 "!TARGET_SOFT_FLOAT
4325 && !TARGET_DISABLE_INDEXING
4326 && TARGET_NO_SPACE_REGS
4327 && REG_OK_FOR_INDEX_P (operands[1])
4328 && REG_OK_FOR_BASE_P (operands[2])
4329 && FP_REGNO_P (REGNO (operands[3]))"
4330 [(set (mem:DF (plus:SI (match_dup 1) (match_dup 2)))
4331 (match_dup 3))
4332 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4333 "")
4335 (define_peephole2
4336 [(set (match_operand:SI 0 "register_operand" "")
4337 (plus:SI (match_operand:SI 1 "register_operand" "")
4338 (match_operand:SI 2 "register_operand" "")))
4339 (set (mem:DF (match_dup 0))
4340 (match_operand:DF 3 "register_operand" ""))]
4341 "!TARGET_SOFT_FLOAT
4342 && !TARGET_DISABLE_INDEXING
4343 && TARGET_NO_SPACE_REGS
4344 && REG_OK_FOR_BASE_P (operands[1])
4345 && REG_OK_FOR_INDEX_P (operands[2])
4346 && FP_REGNO_P (REGNO (operands[3]))"
4347 [(set (mem:DF (plus:SI (match_dup 2) (match_dup 1)))
4348 (match_dup 3))
4349 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4350 "")
4352 (define_peephole2
4353 [(set (match_operand:DI 0 "register_operand" "")
4354 (plus:DI (match_operand:DI 1 "register_operand" "")
4355 (match_operand:DI 2 "register_operand" "")))
4356 (set (mem:DF (match_dup 0))
4357 (match_operand:DF 3 "register_operand" ""))]
4358 "!TARGET_SOFT_FLOAT
4359 && !TARGET_DISABLE_INDEXING
4360 && TARGET_64BIT
4361 && TARGET_NO_SPACE_REGS
4362 && REG_OK_FOR_INDEX_P (operands[1])
4363 && REG_OK_FOR_BASE_P (operands[2])
4364 && FP_REGNO_P (REGNO (operands[3]))"
4365 [(set (mem:DF (plus:DI (match_dup 1) (match_dup 2)))
4366 (match_dup 3))
4367 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4368 "")
4370 (define_peephole2
4371 [(set (match_operand:DI 0 "register_operand" "")
4372 (plus:DI (match_operand:DI 1 "register_operand" "")
4373 (match_operand:DI 2 "register_operand" "")))
4374 (set (mem:DF (match_dup 0))
4375 (match_operand:DF 3 "register_operand" ""))]
4376 "!TARGET_SOFT_FLOAT
4377 && !TARGET_DISABLE_INDEXING
4378 && TARGET_64BIT
4379 && TARGET_NO_SPACE_REGS
4380 && REG_OK_FOR_BASE_P (operands[1])
4381 && REG_OK_FOR_INDEX_P (operands[2])
4382 && FP_REGNO_P (REGNO (operands[3]))"
4383 [(set (mem:DF (plus:DI (match_dup 2) (match_dup 1)))
4384 (match_dup 3))
4385 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4386 "")
4388 (define_insn ""
4389 [(set (match_operand:DF 0 "move_dest_operand"
4390 "=r,?o,?Q,r,r")
4391 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
4392 "rG,r,r,o,RQ"))]
4393 "(register_operand (operands[0], DFmode)
4394 || reg_or_0_operand (operands[1], DFmode))
4395 && !TARGET_64BIT
4396 && TARGET_SOFT_FLOAT"
4397 "*
4398 {
4399 return output_move_double (operands);
4400 }"
4401 [(set_attr "type" "move,store,store,load,load")
4402 (set_attr "length" "8,8,16,8,16")])
4404 (define_insn ""
4405 [(set (match_operand:DF 0 "move_dest_operand"
4406 "=!*r,*r,*r,*r,*r,Q,f,f,T")
4407 (match_operand:DF 1 "move_src_operand"
4408 "!*r,J,N,K,RQ,*rG,fG,RT,f"))]
4409 "(register_operand (operands[0], DFmode)
4410 || reg_or_0_operand (operands[1], DFmode))
4411 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4412 "@
4413 copy %1,%0
4414 ldi %1,%0
4415 ldil L'%1,%0
4416 depdi,z %z1,%0
4417 ldd%M1 %1,%0
4418 std%M0 %r1,%0
4419 fcpy,dbl %f1,%0
4420 fldd%F1 %1,%0
4421 fstd%F0 %1,%0"
4422 [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore")
4423 (set_attr "pa_combine_type" "addmove")
4424 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
4426 \f
4427 (define_expand "movdi"
4428 [(set (match_operand:DI 0 "general_operand" "")
4429 (match_operand:DI 1 "general_operand" ""))]
4430 ""
4431 "
4432 {
4433 /* Except for zero, we don't support loading a CONST_INT directly
4434 to a hard floating-point register since a scratch register is
4435 needed for the operation. While the operation could be handled
4436 before register allocation, the simplest solution is to fail. */
4437 if (TARGET_64BIT
4438 && GET_CODE (operands[1]) == CONST_INT
4439 && operands[1] != CONST0_RTX (DImode)
4440 && REG_P (operands[0])
4441 && HARD_REGISTER_P (operands[0])
4442 && REGNO (operands[0]) >= 32)
4443 FAIL;
4445 if (emit_move_sequence (operands, DImode, 0))
4446 DONE;
4447 }")
4449 ;; Handle DImode input reloads requiring %r1 as a scratch register.
4450 (define_expand "reload_indi_r1"
4451 [(set (match_operand:DI 0 "register_operand" "=Z")
4452 (match_operand:DI 1 "non_hard_reg_operand" ""))
4453 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
4454 ""
4455 "
4456 {
4457 if (emit_move_sequence (operands, DImode, operands[2]))
4458 DONE;
4460 /* We don't want the clobber emitted, so handle this ourselves. */
4461 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4462 DONE;
4463 }")
4465 ;; Handle DImode input reloads requiring a general register as a
4466 ;; scratch register.
4467 (define_expand "reload_indi"
4468 [(set (match_operand:DI 0 "register_operand" "=Z")
4469 (match_operand:DI 1 "non_hard_reg_operand" ""))
4470 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4471 ""
4472 "
4473 {
4474 if (emit_move_sequence (operands, DImode, operands[2]))
4475 DONE;
4477 /* We don't want the clobber emitted, so handle this ourselves. */
4478 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4479 DONE;
4480 }")
4482 ;; Handle DImode output reloads requiring a general register as a
4483 ;; scratch register.
4484 (define_expand "reload_outdi"
4485 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
4486 (match_operand:DI 1 "register_operand" "Z"))
4487 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4488 ""
4489 "
4490 {
4491 if (emit_move_sequence (operands, DImode, operands[2]))
4492 DONE;
4494 /* We don't want the clobber emitted, so handle this ourselves. */
4495 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4496 DONE;
4497 }")
4499 (define_insn ""
4500 [(set (match_operand:DI 0 "register_operand" "=r")
4501 (high:DI (match_operand 1 "" "")))]
4502 "!TARGET_64BIT"
4503 "*
4504 {
4505 rtx op0 = operands[0];
4506 rtx op1 = operands[1];
4508 switch (GET_CODE (op1))
4509 {
4510 case CONST_INT:
4511 #if HOST_BITS_PER_WIDE_INT <= 32
4512 operands[0] = operand_subword (op0, 1, 0, DImode);
4513 output_asm_insn (\"ldil L'%1,%0\", operands);
4515 operands[0] = operand_subword (op0, 0, 0, DImode);
4516 if (INTVAL (op1) < 0)
4517 output_asm_insn (\"ldi -1,%0\", operands);
4518 else
4519 output_asm_insn (\"ldi 0,%0\", operands);
4520 #else
4521 operands[0] = operand_subword (op0, 1, 0, DImode);
4522 operands[1] = GEN_INT (INTVAL (op1) & 0xffffffff);
4523 output_asm_insn (\"ldil L'%1,%0\", operands);
4525 operands[0] = operand_subword (op0, 0, 0, DImode);
4526 operands[1] = GEN_INT (INTVAL (op1) >> 32);
4527 output_asm_insn (singlemove_string (operands), operands);
4528 #endif
4529 break;
4531 case CONST_DOUBLE:
4532 operands[0] = operand_subword (op0, 1, 0, DImode);
4533 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
4534 output_asm_insn (\"ldil L'%1,%0\", operands);
4536 operands[0] = operand_subword (op0, 0, 0, DImode);
4537 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
4538 output_asm_insn (singlemove_string (operands), operands);
4539 break;
4541 default:
4542 gcc_unreachable ();
4543 }
4544 return \"\";
4545 }"
4546 [(set_attr "type" "move")
4547 (set_attr "length" "12")])
4549 (define_insn ""
4550 [(set (match_operand:DI 0 "move_dest_operand"
4551 "=r,o,Q,r,r,r,*f,*f,T,?r,?*f")
4552 (match_operand:DI 1 "general_operand"
4553 "rM,r,r,o*R,Q,i,*fM,RT,*f,*f,r"))]
4554 "(register_operand (operands[0], DImode)
4555 || reg_or_0_operand (operands[1], DImode))
4556 && !TARGET_64BIT
4557 && !TARGET_SOFT_FLOAT"
4558 "*
4559 {
4560 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4561 || operands[1] == CONST0_RTX (DFmode))
4562 && !(REG_P (operands[0]) && REG_P (operands[1])
4563 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
4564 return output_fp_move_double (operands);
4565 return output_move_double (operands);
4566 }"
4567 [(set_attr "type"
4568 "move,store,store,load,load,multi,fpalu,fpload,fpstore,fpstore_load,store_fpload")
4569 (set_attr "length" "8,8,16,8,16,16,4,4,4,12,12")])
4571 (define_insn ""
4572 [(set (match_operand:DI 0 "move_dest_operand"
4573 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
4574 (match_operand:DI 1 "move_src_operand"
4575 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
4576 "(register_operand (operands[0], DImode)
4577 || reg_or_0_operand (operands[1], DImode))
4578 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4579 "@
4580 ldd RT'%A1,%0
4581 copy %1,%0
4582 ldi %1,%0
4583 ldil L'%1,%0
4584 depdi,z %z1,%0
4585 ldd%M1 %1,%0
4586 std%M0 %r1,%0
4587 mtsar %r1
4588 {mfctl|mfctl,w} %%sar,%0
4589 fcpy,dbl %f1,%0
4590 fldd%F1 %1,%0
4591 fstd%F0 %1,%0"
4592 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
4593 (set_attr "pa_combine_type" "addmove")
4594 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
4596 (define_insn ""
4597 [(set (match_operand:DI 0 "indexed_memory_operand" "=R")
4598 (match_operand:DI 1 "register_operand" "f"))]
4599 "!TARGET_SOFT_FLOAT
4600 && TARGET_64BIT
4601 && !TARGET_DISABLE_INDEXING
4602 && reload_completed"
4603 "fstd%F0 %1,%0"
4604 [(set_attr "type" "fpstore")
4605 (set_attr "pa_combine_type" "addmove")
4606 (set_attr "length" "4")])
4608 (define_peephole2
4609 [(set (match_operand:DI 0 "register_operand" "")
4610 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4611 (const_int 8))
4612 (match_operand:DI 2 "register_operand" "")))
4613 (set (mem:DI (match_dup 0))
4614 (match_operand:DI 3 "register_operand" ""))]
4615 "!TARGET_SOFT_FLOAT
4616 && !TARGET_DISABLE_INDEXING
4617 && TARGET_64BIT
4618 && REG_OK_FOR_BASE_P (operands[2])
4619 && FP_REGNO_P (REGNO (operands[3]))"
4620 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4621 (match_dup 3))
4622 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4623 (match_dup 2)))]
4624 "")
4626 (define_peephole2
4627 [(set (match_operand:DI 0 "register_operand" "")
4628 (plus:DI (match_operand:DI 2 "register_operand" "")
4629 (mult:DI (match_operand:DI 1 "register_operand" "")
4630 (const_int 8))))
4631 (set (mem:DI (match_dup 0))
4632 (match_operand:DI 3 "register_operand" ""))]
4633 "!TARGET_SOFT_FLOAT
4634 && !TARGET_DISABLE_INDEXING
4635 && TARGET_64BIT
4636 && REG_OK_FOR_BASE_P (operands[2])
4637 && FP_REGNO_P (REGNO (operands[3]))"
4638 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4639 (match_dup 3))
4640 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4641 (match_dup 2)))]
4642 "")
4644 (define_peephole2
4645 [(set (match_operand:DI 0 "register_operand" "")
4646 (plus:DI (match_operand:DI 1 "register_operand" "")
4647 (match_operand:DI 2 "register_operand" "")))
4648 (set (mem:DI (match_dup 0))
4649 (match_operand:DI 3 "register_operand" ""))]
4650 "!TARGET_SOFT_FLOAT
4651 && !TARGET_DISABLE_INDEXING
4652 && TARGET_64BIT
4653 && TARGET_NO_SPACE_REGS
4654 && REG_OK_FOR_INDEX_P (operands[1])
4655 && REG_OK_FOR_BASE_P (operands[2])
4656 && FP_REGNO_P (REGNO (operands[3]))"
4657 [(set (mem:DI (plus:DI (match_dup 1) (match_dup 2)))
4658 (match_dup 3))
4659 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4660 "")
4662 (define_peephole2
4663 [(set (match_operand:DI 0 "register_operand" "")
4664 (plus:DI (match_operand:DI 1 "register_operand" "")
4665 (match_operand:DI 2 "register_operand" "")))
4666 (set (mem:DI (match_dup 0))
4667 (match_operand:DI 3 "register_operand" ""))]
4668 "!TARGET_SOFT_FLOAT
4669 && !TARGET_DISABLE_INDEXING
4670 && TARGET_64BIT
4671 && TARGET_NO_SPACE_REGS
4672 && REG_OK_FOR_BASE_P (operands[1])
4673 && REG_OK_FOR_INDEX_P (operands[2])
4674 && FP_REGNO_P (REGNO (operands[3]))"
4675 [(set (mem:DI (plus:DI (match_dup 2) (match_dup 1)))
4676 (match_dup 3))
4677 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4678 "")
4680 (define_insn ""
4681 [(set (match_operand:DI 0 "move_dest_operand"
4682 "=r,o,Q,r,r,r")
4683 (match_operand:DI 1 "general_operand"
4684 "rM,r,r,o,Q,i"))]
4685 "(register_operand (operands[0], DImode)
4686 || reg_or_0_operand (operands[1], DImode))
4687 && !TARGET_64BIT
4688 && TARGET_SOFT_FLOAT"
4689 "*
4690 {
4691 return output_move_double (operands);
4692 }"
4693 [(set_attr "type" "move,store,store,load,load,multi")
4694 (set_attr "length" "8,8,16,8,16,16")])
4696 (define_insn ""
4697 [(set (match_operand:DI 0 "register_operand" "=r,&r")
4698 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
4699 (match_operand:DI 2 "immediate_operand" "i,i")))]
4700 "!TARGET_64BIT"
4701 "*
4702 {
4703 /* Don't output a 64-bit constant, since we can't trust the assembler to
4704 handle it correctly. */
4705 if (GET_CODE (operands[2]) == CONST_DOUBLE)
4706 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
4707 else if (HOST_BITS_PER_WIDE_INT > 32
4708 && GET_CODE (operands[2]) == CONST_INT)
4709 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffffffff);
4710 if (which_alternative == 1)
4711 output_asm_insn (\"copy %1,%0\", operands);
4712 return \"ldo R'%G2(%R1),%R0\";
4713 }"
4714 [(set_attr "type" "move,move")
4715 (set_attr "length" "4,8")])
4717 ;; This pattern forces (set (reg:SF ...) (const_double ...))
4718 ;; to be reloaded by putting the constant into memory when
4719 ;; reg is a floating point register.
4720 ;;
4721 ;; For integer registers we use ldil;ldo to set the appropriate
4722 ;; value.
4723 ;;
4724 ;; This must come before the movsf pattern, and it must be present
4725 ;; to handle obscure reloading cases.
4726 (define_insn ""
4727 [(set (match_operand:SF 0 "register_operand" "=?r,f")
4728 (match_operand:SF 1 "" "?F,m"))]
4729 "GET_CODE (operands[1]) == CONST_DOUBLE
4730 && operands[1] != CONST0_RTX (SFmode)
4731 && ! TARGET_SOFT_FLOAT"
4732 "* return (which_alternative == 0 ? singlemove_string (operands)
4733 : \" fldw%F1 %1,%0\");"
4734 [(set_attr "type" "move,fpload")
4735 (set_attr "length" "8,4")])
4737 (define_expand "movsf"
4738 [(set (match_operand:SF 0 "general_operand" "")
4739 (match_operand:SF 1 "general_operand" ""))]
4740 ""
4741 "
4742 {
4743 /* Reject CONST_DOUBLE loads to floating point registers. */
4744 if (GET_CODE (operands[1]) == CONST_DOUBLE
4745 && operands[1] != CONST0_RTX (SFmode)
4746 && REG_P (operands[0])
4747 && HARD_REGISTER_P (operands[0])
4748 && REGNO (operands[0]) >= 32)
4749 FAIL;
4751 if (emit_move_sequence (operands, SFmode, 0))
4752 DONE;
4753 }")
4755 ;; Handle SFmode input reloads requiring a general register as a
4756 ;; scratch register.
4757 (define_expand "reload_insf"
4758 [(set (match_operand:SF 0 "register_operand" "=Z")
4759 (match_operand:SF 1 "non_hard_reg_operand" ""))
4760 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4761 ""
4762 "
4763 {
4764 if (emit_move_sequence (operands, SFmode, operands[2]))
4765 DONE;
4767 /* We don't want the clobber emitted, so handle this ourselves. */
4768 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4769 DONE;
4770 }")
4772 ;; Handle SFmode output reloads requiring a general register as a
4773 ;; scratch register.
4774 (define_expand "reload_outsf"
4775 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
4776 (match_operand:SF 1 "register_operand" "Z"))
4777 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4778 ""
4779 "
4780 {
4781 if (emit_move_sequence (operands, SFmode, operands[2]))
4782 DONE;
4784 /* We don't want the clobber emitted, so handle this ourselves. */
4785 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4786 DONE;
4787 }")
4789 (define_insn ""
4790 [(set (match_operand:SF 0 "move_dest_operand"
4791 "=f,!*r,f,*r,Q,Q,?*r,?f")
4792 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4793 "fG,!*rG,RQ,RQ,f,*rG,f,*r"))]
4794 "(register_operand (operands[0], SFmode)
4795 || reg_or_0_operand (operands[1], SFmode))
4796 && !TARGET_SOFT_FLOAT
4797 && !TARGET_64BIT"
4798 "@
4799 fcpy,sgl %f1,%0
4800 copy %r1,%0
4801 fldw%F1 %1,%0
4802 ldw%M1 %1,%0
4803 fstw%F0 %1,%0
4804 stw%M0 %r1,%0
4805 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
4806 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
4807 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store,fpstore_load,store_fpload")
4808 (set_attr "pa_combine_type" "addmove")
4809 (set_attr "length" "4,4,4,4,4,4,8,8")])
4811 (define_insn ""
4812 [(set (match_operand:SF 0 "move_dest_operand"
4813 "=f,!*r,f,*r,Q,Q")
4814 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4815 "fG,!*rG,RQ,RQ,f,*rG"))]
4816 "(register_operand (operands[0], SFmode)
4817 || reg_or_0_operand (operands[1], SFmode))
4818 && !TARGET_SOFT_FLOAT
4819 && TARGET_64BIT"
4820 "@
4821 fcpy,sgl %f1,%0
4822 copy %r1,%0
4823 fldw%F1 %1,%0
4824 ldw%M1 %1,%0
4825 fstw%F0 %1,%0
4826 stw%M0 %r1,%0"
4827 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
4828 (set_attr "pa_combine_type" "addmove")
4829 (set_attr "length" "4,4,4,4,4,4")])
4831 (define_insn ""
4832 [(set (match_operand:SF 0 "indexed_memory_operand" "=R")
4833 (match_operand:SF 1 "register_operand" "f"))]
4834 "!TARGET_SOFT_FLOAT
4835 && !TARGET_DISABLE_INDEXING
4836 && reload_completed"
4837 "fstw%F0 %1,%0"
4838 [(set_attr "type" "fpstore")
4839 (set_attr "pa_combine_type" "addmove")
4840 (set_attr "length" "4")])
4842 (define_peephole2
4843 [(set (match_operand:SI 0 "register_operand" "")
4844 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4845 (const_int 4))
4846 (match_operand:SI 2 "register_operand" "")))
4847 (set (mem:SF (match_dup 0))
4848 (match_operand:SF 3 "register_operand" ""))]
4849 "!TARGET_SOFT_FLOAT
4850 && !TARGET_DISABLE_INDEXING
4851 && REG_OK_FOR_BASE_P (operands[2])
4852 && FP_REGNO_P (REGNO (operands[3]))"
4853 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4854 (match_dup 3))
4855 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4856 (match_dup 2)))]
4857 "")
4859 (define_peephole2
4860 [(set (match_operand:SI 0 "register_operand" "")
4861 (plus:SI (match_operand:SI 2 "register_operand" "")
4862 (mult:SI (match_operand:SI 1 "register_operand" "")
4863 (const_int 4))))
4864 (set (mem:SF (match_dup 0))
4865 (match_operand:SF 3 "register_operand" ""))]
4866 "!TARGET_SOFT_FLOAT
4867 && !TARGET_DISABLE_INDEXING
4868 && REG_OK_FOR_BASE_P (operands[2])
4869 && FP_REGNO_P (REGNO (operands[3]))"
4870 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4871 (match_dup 3))
4872 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4873 (match_dup 2)))]
4874 "")
4876 (define_peephole2
4877 [(set (match_operand:DI 0 "register_operand" "")
4878 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4879 (const_int 4))
4880 (match_operand:DI 2 "register_operand" "")))
4881 (set (mem:SF (match_dup 0))
4882 (match_operand:SF 3 "register_operand" ""))]
4883 "!TARGET_SOFT_FLOAT
4884 && !TARGET_DISABLE_INDEXING
4885 && TARGET_64BIT
4886 && REG_OK_FOR_BASE_P (operands[2])
4887 && FP_REGNO_P (REGNO (operands[3]))"
4888 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4889 (match_dup 3))
4890 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4891 (match_dup 2)))]
4892 "")
4894 (define_peephole2
4895 [(set (match_operand:DI 0 "register_operand" "")
4896 (plus:DI (match_operand:DI 2 "register_operand" "")
4897 (mult:DI (match_operand:DI 1 "register_operand" "")
4898 (const_int 4))))
4899 (set (mem:SF (match_dup 0))
4900 (match_operand:SF 3 "register_operand" ""))]
4901 "!TARGET_SOFT_FLOAT
4902 && !TARGET_DISABLE_INDEXING
4903 && TARGET_64BIT
4904 && REG_OK_FOR_BASE_P (operands[2])
4905 && FP_REGNO_P (REGNO (operands[3]))"
4906 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4907 (match_dup 3))
4908 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4909 (match_dup 2)))]
4910 "")
4912 (define_peephole2
4913 [(set (match_operand:SI 0 "register_operand" "")
4914 (plus:SI (match_operand:SI 1 "register_operand" "")
4915 (match_operand:SI 2 "register_operand" "")))
4916 (set (mem:SF (match_dup 0))
4917 (match_operand:SF 3 "register_operand" ""))]
4918 "!TARGET_SOFT_FLOAT
4919 && !TARGET_DISABLE_INDEXING
4920 && TARGET_NO_SPACE_REGS
4921 && REG_OK_FOR_INDEX_P (operands[1])
4922 && REG_OK_FOR_BASE_P (operands[2])
4923 && FP_REGNO_P (REGNO (operands[3]))"
4924 [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2)))
4925 (match_dup 3))
4926 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4927 "")
4929 (define_peephole2
4930 [(set (match_operand:SI 0 "register_operand" "")
4931 (plus:SI (match_operand:SI 1 "register_operand" "")
4932 (match_operand:SI 2 "register_operand" "")))
4933 (set (mem:SF (match_dup 0))
4934 (match_operand:SF 3 "register_operand" ""))]
4935 "!TARGET_SOFT_FLOAT
4936 && !TARGET_DISABLE_INDEXING
4937 && TARGET_NO_SPACE_REGS
4938 && REG_OK_FOR_BASE_P (operands[1])
4939 && REG_OK_FOR_INDEX_P (operands[2])
4940 && FP_REGNO_P (REGNO (operands[3]))"
4941 [(set (mem:SF (plus:SI (match_dup 2) (match_dup 1)))
4942 (match_dup 3))
4943 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4944 "")
4946 (define_peephole2
4947 [(set (match_operand:DI 0 "register_operand" "")
4948 (plus:DI (match_operand:DI 1 "register_operand" "")
4949 (match_operand:DI 2 "register_operand" "")))
4950 (set (mem:SF (match_dup 0))
4951 (match_operand:SF 3 "register_operand" ""))]
4952 "!TARGET_SOFT_FLOAT
4953 && !TARGET_DISABLE_INDEXING
4954 && TARGET_64BIT
4955 && TARGET_NO_SPACE_REGS
4956 && REG_OK_FOR_INDEX_P (operands[1])
4957 && REG_OK_FOR_BASE_P (operands[2])
4958 && FP_REGNO_P (REGNO (operands[3]))"
4959 [(set (mem:SF (plus:DI (match_dup 1) (match_dup 2)))
4960 (match_dup 3))
4961 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4962 "")
4964 (define_peephole2
4965 [(set (match_operand:DI 0 "register_operand" "")
4966 (plus:DI (match_operand:DI 1 "register_operand" "")
4967 (match_operand:DI 2 "register_operand" "")))
4968 (set (mem:SF (match_dup 0))
4969 (match_operand:SF 3 "register_operand" ""))]
4970 "!TARGET_SOFT_FLOAT
4971 && !TARGET_DISABLE_INDEXING
4972 && TARGET_64BIT
4973 && TARGET_NO_SPACE_REGS
4974 && REG_OK_FOR_BASE_P (operands[1])
4975 && REG_OK_FOR_INDEX_P (operands[2])
4976 && FP_REGNO_P (REGNO (operands[3]))"
4977 [(set (mem:SF (plus:DI (match_dup 2) (match_dup 1)))
4978 (match_dup 3))
4979 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4980 "")
4982 (define_insn ""
4983 [(set (match_operand:SF 0 "move_dest_operand"
4984 "=r,r,Q")
4985 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4986 "rG,RQ,rG"))]
4987 "(register_operand (operands[0], SFmode)
4988 || reg_or_0_operand (operands[1], SFmode))
4989 && TARGET_SOFT_FLOAT"
4990 "@
4991 copy %r1,%0
4992 ldw%M1 %1,%0
4993 stw%M0 %r1,%0"
4994 [(set_attr "type" "move,load,store")
4995 (set_attr "pa_combine_type" "addmove")
4996 (set_attr "length" "4,4,4")])
4998 \f
5000 ;;- zero extension instructions
5001 ;; We have define_expand for zero extension patterns to make sure the
5002 ;; operands get loaded into registers. The define_insns accept
5003 ;; memory operands. This gives us better overall code than just
5004 ;; having a pattern that does or does not accept memory operands.
5006 (define_expand "zero_extendqihi2"
5007 [(set (match_operand:HI 0 "register_operand" "")
5008 (zero_extend:HI
5009 (match_operand:QI 1 "register_operand" "")))]
5010 ""
5011 "")
5013 (define_insn ""
5014 [(set (match_operand:HI 0 "register_operand" "=r,r")
5015 (zero_extend:HI
5016 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
5017 "GET_CODE (operands[1]) != CONST_INT"
5018 "@
5019 {extru|extrw,u} %1,31,8,%0
5020 ldb%M1 %1,%0"
5021 [(set_attr "type" "shift,load")
5022 (set_attr "length" "4,4")])
5024 (define_expand "zero_extendqisi2"
5025 [(set (match_operand:SI 0 "register_operand" "")
5026 (zero_extend:SI
5027 (match_operand:QI 1 "register_operand" "")))]
5028 ""
5029 "")
5031 (define_insn ""
5032 [(set (match_operand:SI 0 "register_operand" "=r,r")
5033 (zero_extend:SI
5034 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
5035 "GET_CODE (operands[1]) != CONST_INT"
5036 "@
5037 {extru|extrw,u} %1,31,8,%0
5038 ldb%M1 %1,%0"
5039 [(set_attr "type" "shift,load")
5040 (set_attr "length" "4,4")])
5042 (define_expand "zero_extendhisi2"
5043 [(set (match_operand:SI 0 "register_operand" "")
5044 (zero_extend:SI
5045 (match_operand:HI 1 "register_operand" "")))]
5046 ""
5047 "")
5049 (define_insn ""
5050 [(set (match_operand:SI 0 "register_operand" "=r,r")
5051 (zero_extend:SI
5052 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
5053 "GET_CODE (operands[1]) != CONST_INT"
5054 "@
5055 {extru|extrw,u} %1,31,16,%0
5056 ldh%M1 %1,%0"
5057 [(set_attr "type" "shift,load")
5058 (set_attr "length" "4,4")])
5060 (define_expand "zero_extendqidi2"
5061 [(set (match_operand:DI 0 "register_operand" "")
5062 (zero_extend:DI
5063 (match_operand:QI 1 "register_operand" "")))]
5064 "TARGET_64BIT"
5065 "")
5067 (define_insn ""
5068 [(set (match_operand:DI 0 "register_operand" "=r,r")
5069 (zero_extend:DI
5070 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
5071 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
5072 "@
5073 extrd,u %1,63,8,%0
5074 ldb%M1 %1,%0"
5075 [(set_attr "type" "shift,load")
5076 (set_attr "length" "4,4")])
5078 (define_expand "zero_extendhidi2"
5079 [(set (match_operand:DI 0 "register_operand" "")
5080 (zero_extend:DI
5081 (match_operand:HI 1 "register_operand" "")))]
5082 "TARGET_64BIT"
5083 "")
5085 (define_insn ""
5086 [(set (match_operand:DI 0 "register_operand" "=r,r")
5087 (zero_extend:DI
5088 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
5089 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
5090 "@
5091 extrd,u %1,63,16,%0
5092 ldh%M1 %1,%0"
5093 [(set_attr "type" "shift,load")
5094 (set_attr "length" "4,4")])
5096 (define_expand "zero_extendsidi2"
5097 [(set (match_operand:DI 0 "register_operand" "")
5098 (zero_extend:DI
5099 (match_operand:SI 1 "register_operand" "")))]
5100 "TARGET_64BIT"
5101 "")
5103 (define_insn ""
5104 [(set (match_operand:DI 0 "register_operand" "=r,r")
5105 (zero_extend:DI
5106 (match_operand:SI 1 "move_src_operand" "r,RQ")))]
5107 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
5108 "@
5109 extrd,u %1,63,32,%0
5110 ldw%M1 %1,%0"
5111 [(set_attr "type" "shift,load")
5112 (set_attr "length" "4,4")])
5114 ;;- sign extension instructions
5116 (define_insn "extendhisi2"
5117 [(set (match_operand:SI 0 "register_operand" "=r")
5118 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
5119 ""
5120 "{extrs|extrw,s} %1,31,16,%0"
5121 [(set_attr "type" "shift")
5122 (set_attr "length" "4")])
5124 (define_insn "extendqihi2"
5125 [(set (match_operand:HI 0 "register_operand" "=r")
5126 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
5127 ""
5128 "{extrs|extrw,s} %1,31,8,%0"
5129 [(set_attr "type" "shift")
5130 (set_attr "length" "4")])
5132 (define_insn "extendqisi2"
5133 [(set (match_operand:SI 0 "register_operand" "=r")
5134 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
5135 ""
5136 "{extrs|extrw,s} %1,31,8,%0"
5137 [(set_attr "type" "shift")
5138 (set_attr "length" "4")])
5140 (define_insn "extendqidi2"
5141 [(set (match_operand:DI 0 "register_operand" "=r")
5142 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
5143 "TARGET_64BIT"
5144 "extrd,s %1,63,8,%0"
5145 [(set_attr "type" "shift")
5146 (set_attr "length" "4")])
5148 (define_insn "extendhidi2"
5149 [(set (match_operand:DI 0 "register_operand" "=r")
5150 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
5151 "TARGET_64BIT"
5152 "extrd,s %1,63,16,%0"
5153 [(set_attr "type" "shift")
5154 (set_attr "length" "4")])
5156 (define_insn "extendsidi2"
5157 [(set (match_operand:DI 0 "register_operand" "=r")
5158 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
5159 "TARGET_64BIT"
5160 "extrd,s %1,63,32,%0"
5161 [(set_attr "type" "shift")
5162 (set_attr "length" "4")])
5164 \f
5165 ;; Conversions between float and double.
5167 (define_insn "extendsfdf2"
5168 [(set (match_operand:DF 0 "register_operand" "=f")
5169 (float_extend:DF
5170 (match_operand:SF 1 "register_operand" "f")))]
5171 "! TARGET_SOFT_FLOAT"
5172 "{fcnvff|fcnv},sgl,dbl %1,%0"
5173 [(set_attr "type" "fpalu")
5174 (set_attr "length" "4")])
5176 (define_insn "truncdfsf2"
5177 [(set (match_operand:SF 0 "register_operand" "=f")
5178 (float_truncate:SF
5179 (match_operand:DF 1 "register_operand" "f")))]
5180 "! TARGET_SOFT_FLOAT"
5181 "{fcnvff|fcnv},dbl,sgl %1,%0"
5182 [(set_attr "type" "fpalu")
5183 (set_attr "length" "4")])
5185 ;; Conversion between fixed point and floating point.
5186 ;; Note that among the fix-to-float insns
5187 ;; the ones that start with SImode come first.
5188 ;; That is so that an operand that is a CONST_INT
5189 ;; (and therefore lacks a specific machine mode).
5190 ;; will be recognized as SImode (which is always valid)
5191 ;; rather than as QImode or HImode.
5193 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
5194 ;; to be reloaded by putting the constant into memory.
5195 ;; It must come before the more general floatsisf2 pattern.
5196 (define_insn ""
5197 [(set (match_operand:SF 0 "register_operand" "=f")
5198 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
5199 "! TARGET_SOFT_FLOAT"
5200 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
5201 [(set_attr "type" "fpalu")
5202 (set_attr "length" "8")])
5204 (define_insn "floatsisf2"
5205 [(set (match_operand:SF 0 "register_operand" "=f")
5206 (float:SF (match_operand:SI 1 "register_operand" "f")))]
5207 "! TARGET_SOFT_FLOAT"
5208 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
5209 [(set_attr "type" "fpalu")
5210 (set_attr "length" "4")])
5212 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
5213 ;; to be reloaded by putting the constant into memory.
5214 ;; It must come before the more general floatsidf2 pattern.
5215 (define_insn ""
5216 [(set (match_operand:DF 0 "register_operand" "=f")
5217 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
5218 "! TARGET_SOFT_FLOAT"
5219 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
5220 [(set_attr "type" "fpalu")
5221 (set_attr "length" "8")])
5223 (define_insn "floatsidf2"
5224 [(set (match_operand:DF 0 "register_operand" "=f")
5225 (float:DF (match_operand:SI 1 "register_operand" "f")))]
5226 "! TARGET_SOFT_FLOAT"
5227 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
5228 [(set_attr "type" "fpalu")
5229 (set_attr "length" "4")])
5231 (define_expand "floatunssisf2"
5232 [(set (subreg:SI (match_dup 2) 4)
5233 (match_operand:SI 1 "register_operand" ""))
5234 (set (subreg:SI (match_dup 2) 0)
5235 (const_int 0))
5236 (set (match_operand:SF 0 "register_operand" "")
5237 (float:SF (match_dup 2)))]
5238 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5239 "
5240 {
5241 if (TARGET_PA_20)
5242 {
5243 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
5244 DONE;
5245 }
5246 operands[2] = gen_reg_rtx (DImode);
5247 }")
5249 (define_expand "floatunssidf2"
5250 [(set (subreg:SI (match_dup 2) 4)
5251 (match_operand:SI 1 "register_operand" ""))
5252 (set (subreg:SI (match_dup 2) 0)
5253 (const_int 0))
5254 (set (match_operand:DF 0 "register_operand" "")
5255 (float:DF (match_dup 2)))]
5256 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5257 "
5258 {
5259 if (TARGET_PA_20)
5260 {
5261 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
5262 DONE;
5263 }
5264 operands[2] = gen_reg_rtx (DImode);
5265 }")
5267 (define_insn "floatdisf2"
5268 [(set (match_operand:SF 0 "register_operand" "=f")
5269 (float:SF (match_operand:DI 1 "register_operand" "f")))]
5270 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5271 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
5272 [(set_attr "type" "fpalu")
5273 (set_attr "length" "4")])
5275 (define_insn "floatdidf2"
5276 [(set (match_operand:DF 0 "register_operand" "=f")
5277 (float:DF (match_operand:DI 1 "register_operand" "f")))]
5278 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5279 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
5280 [(set_attr "type" "fpalu")
5281 (set_attr "length" "4")])
5283 ;; Convert a float to an actual integer.
5284 ;; Truncation is performed as part of the conversion.
5286 (define_insn "fix_truncsfsi2"
5287 [(set (match_operand:SI 0 "register_operand" "=f")
5288 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5289 "! TARGET_SOFT_FLOAT"
5290 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
5291 [(set_attr "type" "fpalu")
5292 (set_attr "length" "4")])
5294 (define_insn "fix_truncdfsi2"
5295 [(set (match_operand:SI 0 "register_operand" "=f")
5296 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5297 "! TARGET_SOFT_FLOAT"
5298 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
5299 [(set_attr "type" "fpalu")
5300 (set_attr "length" "4")])
5302 (define_insn "fix_truncsfdi2"
5303 [(set (match_operand:DI 0 "register_operand" "=f")
5304 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5305 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5306 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
5307 [(set_attr "type" "fpalu")
5308 (set_attr "length" "4")])
5310 (define_insn "fix_truncdfdi2"
5311 [(set (match_operand:DI 0 "register_operand" "=f")
5312 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5313 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5314 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
5315 [(set_attr "type" "fpalu")
5316 (set_attr "length" "4")])
5318 (define_insn "floatunssidf2_pa20"
5319 [(set (match_operand:DF 0 "register_operand" "=f")
5320 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
5321 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5322 "fcnv,uw,dbl %1,%0"
5323 [(set_attr "type" "fpalu")
5324 (set_attr "length" "4")])
5326 (define_insn "floatunssisf2_pa20"
5327 [(set (match_operand:SF 0 "register_operand" "=f")
5328 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
5329 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5330 "fcnv,uw,sgl %1,%0"
5331 [(set_attr "type" "fpalu")
5332 (set_attr "length" "4")])
5334 (define_insn "floatunsdisf2"
5335 [(set (match_operand:SF 0 "register_operand" "=f")
5336 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
5337 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5338 "fcnv,udw,sgl %1,%0"
5339 [(set_attr "type" "fpalu")
5340 (set_attr "length" "4")])
5342 (define_insn "floatunsdidf2"
5343 [(set (match_operand:DF 0 "register_operand" "=f")
5344 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
5345 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5346 "fcnv,udw,dbl %1,%0"
5347 [(set_attr "type" "fpalu")
5348 (set_attr "length" "4")])
5350 (define_insn "fixuns_truncsfsi2"
5351 [(set (match_operand:SI 0 "register_operand" "=f")
5352 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5353 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5354 "fcnv,t,sgl,uw %1,%0"
5355 [(set_attr "type" "fpalu")
5356 (set_attr "length" "4")])
5358 (define_insn "fixuns_truncdfsi2"
5359 [(set (match_operand:SI 0 "register_operand" "=f")
5360 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5361 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5362 "fcnv,t,dbl,uw %1,%0"
5363 [(set_attr "type" "fpalu")
5364 (set_attr "length" "4")])
5366 (define_insn "fixuns_truncsfdi2"
5367 [(set (match_operand:DI 0 "register_operand" "=f")
5368 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5369 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5370 "fcnv,t,sgl,udw %1,%0"
5371 [(set_attr "type" "fpalu")
5372 (set_attr "length" "4")])
5374 (define_insn "fixuns_truncdfdi2"
5375 [(set (match_operand:DI 0 "register_operand" "=f")
5376 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5377 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5378 "fcnv,t,dbl,udw %1,%0"
5379 [(set_attr "type" "fpalu")
5380 (set_attr "length" "4")])
5381 \f
5382 ;;- arithmetic instructions
5384 (define_expand "adddi3"
5385 [(set (match_operand:DI 0 "register_operand" "")
5386 (plus:DI (match_operand:DI 1 "register_operand" "")
5387 (match_operand:DI 2 "adddi3_operand" "")))]
5388 ""
5389 "")
5391 (define_insn ""
5392 [(set (match_operand:DI 0 "register_operand" "=r")
5393 (plus:DI (match_operand:DI 1 "register_operand" "%r")
5394 (match_operand:DI 2 "arith11_operand" "rI")))]
5395 "!TARGET_64BIT"
5396 "*
5397 {
5398 if (GET_CODE (operands[2]) == CONST_INT)
5399 {
5400 if (INTVAL (operands[2]) >= 0)
5401 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
5402 else
5403 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
5404 }
5405 else
5406 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
5407 }"
5408 [(set_attr "type" "binary")
5409 (set_attr "length" "8")])
5411 (define_insn ""
5412 [(set (match_operand:DI 0 "register_operand" "=r,r")
5413 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
5414 (match_operand:DI 2 "arith_operand" "r,J")))]
5415 "TARGET_64BIT"
5416 "@
5417 add,l %1,%2,%0
5418 ldo %2(%1),%0"
5419 [(set_attr "type" "binary,binary")
5420 (set_attr "pa_combine_type" "addmove")
5421 (set_attr "length" "4,4")])
5423 (define_insn ""
5424 [(set (match_operand:DI 0 "register_operand" "=r")
5425 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5426 (match_operand:DI 2 "register_operand" "r")))]
5427 "TARGET_64BIT"
5428 "uaddcm %2,%1,%0"
5429 [(set_attr "type" "binary")
5430 (set_attr "length" "4")])
5432 (define_insn ""
5433 [(set (match_operand:SI 0 "register_operand" "=r")
5434 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5435 (match_operand:SI 2 "register_operand" "r")))]
5436 ""
5437 "uaddcm %2,%1,%0"
5438 [(set_attr "type" "binary")
5439 (set_attr "length" "4")])
5441 (define_expand "addvdi3"
5442 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5443 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "")
5444 (match_operand:DI 2 "arith11_operand" "")))
5445 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5446 (sign_extend:TI (match_dup 2)))
5447 (sign_extend:TI (plus:DI (match_dup 1)
5448 (match_dup 2))))
5449 (const_int 0))])]
5450 ""
5451 "")
5453 (define_insn ""
5454 [(set (match_operand:DI 0 "register_operand" "=r,r")
5455 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM,rM")
5456 (match_operand:DI 2 "arith11_operand" "r,I")))
5457 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5458 (sign_extend:TI (match_dup 2)))
5459 (sign_extend:TI (plus:DI (match_dup 1)
5460 (match_dup 2))))
5461 (const_int 0))]
5462 "TARGET_64BIT"
5463 "@
5464 add,tsv,* %2,%1,%0
5465 addi,tsv,* %2,%1,%0"
5466 [(set_attr "type" "binary,binary")
5467 (set_attr "length" "4,4")])
5469 (define_insn ""
5470 [(set (match_operand:DI 0 "register_operand" "=r")
5471 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM")
5472 (match_operand:DI 2 "arith11_operand" "rI")))
5473 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5474 (sign_extend:TI (match_dup 2)))
5475 (sign_extend:TI (plus:DI (match_dup 1)
5476 (match_dup 2))))
5477 (const_int 0))]
5478 "!TARGET_64BIT"
5479 "*
5480 {
5481 if (GET_CODE (operands[2]) == CONST_INT)
5482 {
5483 if (INTVAL (operands[2]) >= 0)
5484 return \"addi %2,%R1,%R0\;{addco|add,c,tsv} %1,%%r0,%0\";
5485 else
5486 return \"addi %2,%R1,%R0\;{subbo|sub,b,tsv} %1,%%r0,%0\";
5487 }
5488 else
5489 return \"add %R2,%R1,%R0\;{addco|add,c,tsv} %2,%1,%0\";
5490 }"
5491 [(set_attr "type" "binary")
5492 (set_attr "length" "8")])
5494 ;; define_splits to optimize cases of adding a constant integer
5495 ;; to a register when the constant does not fit in 14 bits. */
5496 (define_split
5497 [(set (match_operand:SI 0 "register_operand" "")
5498 (plus:SI (match_operand:SI 1 "register_operand" "")
5499 (match_operand:SI 2 "const_int_operand" "")))
5500 (clobber (match_operand:SI 4 "register_operand" ""))]
5501 "! cint_ok_for_move (INTVAL (operands[2]))
5502 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
5503 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
5504 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
5505 "
5506 {
5507 int val = INTVAL (operands[2]);
5508 int low = (val < 0) ? -0x2000 : 0x1fff;
5509 int rest = val - low;
5511 operands[2] = GEN_INT (rest);
5512 operands[3] = GEN_INT (low);
5513 }")
5515 (define_split
5516 [(set (match_operand:SI 0 "register_operand" "")
5517 (plus:SI (match_operand:SI 1 "register_operand" "")
5518 (match_operand:SI 2 "const_int_operand" "")))
5519 (clobber (match_operand:SI 4 "register_operand" ""))]
5520 "! cint_ok_for_move (INTVAL (operands[2]))"
5521 [(set (match_dup 4) (match_dup 2))
5522 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
5523 (match_dup 1)))]
5524 "
5525 {
5526 HOST_WIDE_INT intval = INTVAL (operands[2]);
5528 /* Try dividing the constant by 2, then 4, and finally 8 to see
5529 if we can get a constant which can be loaded into a register
5530 in a single instruction (cint_ok_for_move).
5532 If that fails, try to negate the constant and subtract it
5533 from our input operand. */
5534 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
5535 {
5536 operands[2] = GEN_INT (intval / 2);
5537 operands[3] = const2_rtx;
5538 }
5539 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
5540 {
5541 operands[2] = GEN_INT (intval / 4);
5542 operands[3] = GEN_INT (4);
5543 }
5544 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
5545 {
5546 operands[2] = GEN_INT (intval / 8);
5547 operands[3] = GEN_INT (8);
5548 }
5549 else if (cint_ok_for_move (-intval))
5550 {
5551 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
5552 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
5553 DONE;
5554 }
5555 else
5556 FAIL;
5557 }")
5559 (define_insn "addsi3"
5560 [(set (match_operand:SI 0 "register_operand" "=r,r")
5561 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
5562 (match_operand:SI 2 "arith_operand" "r,J")))]
5563 ""
5564 "@
5565 {addl|add,l} %1,%2,%0
5566 ldo %2(%1),%0"
5567 [(set_attr "type" "binary,binary")
5568 (set_attr "pa_combine_type" "addmove")
5569 (set_attr "length" "4,4")])
5571 (define_insn "addvsi3"
5572 [(set (match_operand:SI 0 "register_operand" "=r,r")
5573 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rM,rM")
5574 (match_operand:SI 2 "arith11_operand" "r,I")))
5575 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
5576 (sign_extend:DI (match_dup 2)))
5577 (sign_extend:DI (plus:SI (match_dup 1)
5578 (match_dup 2))))
5579 (const_int 0))]
5580 ""
5581 "@
5582 {addo|add,tsv} %2,%1,%0
5583 {addio|addi,tsv} %2,%1,%0"
5584 [(set_attr "type" "binary,binary")
5585 (set_attr "length" "4,4")])
5587 (define_expand "subdi3"
5588 [(set (match_operand:DI 0 "register_operand" "")
5589 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5590 (match_operand:DI 2 "reg_or_0_operand" "")))]
5591 ""
5592 "")
5594 (define_insn ""
5595 [(set (match_operand:DI 0 "register_operand" "=r,r,!q")
5596 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,!U")
5597 (match_operand:DI 2 "reg_or_0_operand" "rM,rM,!rM")))]
5598 "TARGET_64BIT"
5599 "@
5600 sub %1,%2,%0
5601 subi %1,%2,%0
5602 mtsarcm %2"
5603 [(set_attr "type" "binary,binary,move")
5604 (set_attr "length" "4,4,4")])
5606 (define_insn ""
5607 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5608 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5609 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))]
5610 "!TARGET_64BIT"
5611 "*
5612 {
5613 if (GET_CODE (operands[1]) == CONST_INT)
5614 {
5615 if (INTVAL (operands[1]) >= 0)
5616 return \"subi %1,%R2,%R0\;{subb|sub,b} %%r0,%2,%0\";
5617 else
5618 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subb|sub,b} %0,%2,%0\";
5619 }
5620 else
5621 return \"sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0\";
5622 }"
5623 [(set_attr "type" "binary")
5624 (set (attr "length")
5625 (if_then_else (eq_attr "alternative" "0")
5626 (const_int 8)
5627 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5628 (const_int 0))
5629 (const_int 8)
5630 (const_int 12))))])
5632 (define_expand "subvdi3"
5633 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5634 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5635 (match_operand:DI 2 "reg_or_0_operand" "")))
5636 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5637 (sign_extend:TI (match_dup 2)))
5638 (sign_extend:TI (minus:DI (match_dup 1)
5639 (match_dup 2))))
5640 (const_int 0))])]
5641 ""
5642 "")
5644 (define_insn ""
5645 [(set (match_operand:DI 0 "register_operand" "=r,r")
5646 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5647 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5648 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5649 (sign_extend:TI (match_dup 2)))
5650 (sign_extend:TI (minus:DI (match_dup 1)
5651 (match_dup 2))))
5652 (const_int 0))]
5653 "TARGET_64BIT"
5654 "@
5655 {subo|sub,tsv} %1,%2,%0
5656 {subio|subi,tsv} %1,%2,%0"
5657 [(set_attr "type" "binary,binary")
5658 (set_attr "length" "4,4")])
5660 (define_insn ""
5661 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5662 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5663 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5664 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5665 (sign_extend:TI (match_dup 2)))
5666 (sign_extend:TI (minus:DI (match_dup 1)
5667 (match_dup 2))))
5668 (const_int 0))]
5669 "!TARGET_64BIT"
5670 "*
5671 {
5672 if (GET_CODE (operands[1]) == CONST_INT)
5673 {
5674 if (INTVAL (operands[1]) >= 0)
5675 return \"subi %1,%R2,%R0\;{subbo|sub,b,tsv} %%r0,%2,%0\";
5676 else
5677 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subbo|sub,b,tsv} %0,%2,%0\";
5678 }
5679 else
5680 return \"sub %R1,%R2,%R0\;{subbo|sub,b,tsv} %1,%2,%0\";
5681 }"
5682 [(set_attr "type" "binary,binary")
5683 (set (attr "length")
5684 (if_then_else (eq_attr "alternative" "0")
5685 (const_int 8)
5686 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5687 (const_int 0))
5688 (const_int 8)
5689 (const_int 12))))])
5691 (define_expand "subsi3"
5692 [(set (match_operand:SI 0 "register_operand" "")
5693 (minus:SI (match_operand:SI 1 "arith11_operand" "")
5694 (match_operand:SI 2 "register_operand" "")))]
5695 ""
5696 "")
5698 (define_insn ""
5699 [(set (match_operand:SI 0 "register_operand" "=r,r")
5700 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
5701 (match_operand:SI 2 "register_operand" "r,r")))]
5702 "!TARGET_PA_20"
5703 "@
5704 sub %1,%2,%0
5705 subi %1,%2,%0"
5706 [(set_attr "type" "binary,binary")
5707 (set_attr "length" "4,4")])
5709 (define_insn ""
5710 [(set (match_operand:SI 0 "register_operand" "=r,r,!q")
5711 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,!S")
5712 (match_operand:SI 2 "register_operand" "r,r,!r")))]
5713 "TARGET_PA_20"
5714 "@
5715 sub %1,%2,%0
5716 subi %1,%2,%0
5717 mtsarcm %2"
5718 [(set_attr "type" "binary,binary,move")
5719 (set_attr "length" "4,4,4")])
5721 (define_insn "subvsi3"
5722 [(set (match_operand:SI 0 "register_operand" "=r,r")
5723 (minus:SI (match_operand:SI 1 "arith11_operand" "rM,I")
5724 (match_operand:SI 2 "reg_or_0_operand" "rM,rM")))
5725 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
5726 (sign_extend:DI (match_dup 2)))
5727 (sign_extend:DI (minus:SI (match_dup 1)
5728 (match_dup 2))))
5729 (const_int 0))]
5730 ""
5731 "@
5732 {subo|sub,tsv} %1,%2,%0
5733 {subio|subi,tsv} %1,%2,%0"
5734 [(set_attr "type" "binary,binary")
5735 (set_attr "length" "4,4")])
5737 ;; Clobbering a "register_operand" instead of a match_scratch
5738 ;; in operand3 of millicode calls avoids spilling %r1 and
5739 ;; produces better code.
5741 ;; The mulsi3 insns set up registers for the millicode call.
5742 (define_expand "mulsi3"
5743 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5744 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5745 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5746 (clobber (match_dup 3))
5747 (clobber (reg:SI 26))
5748 (clobber (reg:SI 25))
5749 (clobber (match_dup 4))])
5750 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5751 ""
5752 "
5753 {
5754 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5755 if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
5756 {
5757 rtx scratch = gen_reg_rtx (DImode);
5758 operands[1] = force_reg (SImode, operands[1]);
5759 operands[2] = force_reg (SImode, operands[2]);
5760 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
5761 emit_insn (gen_movsi (operands[0],
5762 gen_rtx_SUBREG (SImode, scratch,
5763 GET_MODE_SIZE (SImode))));
5764 DONE;
5765 }
5766 operands[3] = gen_reg_rtx (SImode);
5767 }")
5769 (define_insn "umulsidi3"
5770 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5771 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5772 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
5773 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5774 "xmpyu %1,%2,%0"
5775 [(set_attr "type" "fpmuldbl")
5776 (set_attr "length" "4")])
5778 (define_insn ""
5779 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5780 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5781 (match_operand:DI 2 "uint32_operand" "f")))]
5782 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
5783 "xmpyu %1,%R2,%0"
5784 [(set_attr "type" "fpmuldbl")
5785 (set_attr "length" "4")])
5787 (define_insn ""
5788 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5789 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5790 (match_operand:DI 2 "uint32_operand" "f")))]
5791 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
5792 "xmpyu %1,%2R,%0"
5793 [(set_attr "type" "fpmuldbl")
5794 (set_attr "length" "4")])
5796 (define_insn ""
5797 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5798 (clobber (match_operand:SI 0 "register_operand" "=a"))
5799 (clobber (reg:SI 26))
5800 (clobber (reg:SI 25))
5801 (clobber (reg:SI 31))]
5802 "!TARGET_64BIT"
5803 "* return output_mul_insn (0, insn);"
5804 [(set_attr "type" "milli")
5805 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5807 (define_insn ""
5808 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5809 (clobber (match_operand:SI 0 "register_operand" "=a"))
5810 (clobber (reg:SI 26))
5811 (clobber (reg:SI 25))
5812 (clobber (reg:SI 2))]
5813 "TARGET_64BIT"
5814 "* return output_mul_insn (0, insn);"
5815 [(set_attr "type" "milli")
5816 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5818 (define_expand "muldi3"
5819 [(set (match_operand:DI 0 "register_operand" "")
5820 (mult:DI (match_operand:DI 1 "register_operand" "")
5821 (match_operand:DI 2 "register_operand" "")))]
5822 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5823 "
5824 {
5825 rtx low_product = gen_reg_rtx (DImode);
5826 rtx cross_product1 = gen_reg_rtx (DImode);
5827 rtx cross_product2 = gen_reg_rtx (DImode);
5828 rtx cross_scratch = gen_reg_rtx (DImode);
5829 rtx cross_product = gen_reg_rtx (DImode);
5830 rtx op1l, op1r, op2l, op2r;
5831 rtx op1shifted, op2shifted;
5833 op1shifted = gen_reg_rtx (DImode);
5834 op2shifted = gen_reg_rtx (DImode);
5835 op1l = gen_reg_rtx (SImode);
5836 op1r = gen_reg_rtx (SImode);
5837 op2l = gen_reg_rtx (SImode);
5838 op2r = gen_reg_rtx (SImode);
5840 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
5841 GEN_INT (32)));
5842 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
5843 GEN_INT (32)));
5844 op1r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[1], 4));
5845 op2r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[2], 4));
5846 op1l = force_reg (SImode, gen_rtx_SUBREG (SImode, op1shifted, 4));
5847 op2l = force_reg (SImode, gen_rtx_SUBREG (SImode, op2shifted, 4));
5849 /* Emit multiplies for the cross products. */
5850 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
5851 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
5853 /* Emit a multiply for the low sub-word. */
5854 emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r)));
5856 /* Sum the cross products and shift them into proper position. */
5857 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
5858 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
5860 /* Add the cross product to the low product and store the result
5861 into the output operand . */
5862 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
5863 DONE;
5864 }")
5866 ;;; Division and mod.
5867 (define_expand "divsi3"
5868 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5869 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5870 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
5871 (clobber (match_dup 3))
5872 (clobber (match_dup 4))
5873 (clobber (reg:SI 26))
5874 (clobber (reg:SI 25))
5875 (clobber (match_dup 5))])
5876 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5877 ""
5878 "
5879 {
5880 operands[3] = gen_reg_rtx (SImode);
5881 if (TARGET_64BIT)
5882 {
5883 operands[5] = gen_rtx_REG (SImode, 2);
5884 operands[4] = operands[5];
5885 }
5886 else
5887 {
5888 operands[5] = gen_rtx_REG (SImode, 31);
5889 operands[4] = gen_reg_rtx (SImode);
5890 }
5891 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
5892 DONE;
5893 }")
5895 (define_insn ""
5896 [(set (reg:SI 29)
5897 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5898 (clobber (match_operand:SI 1 "register_operand" "=a"))
5899 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5900 (clobber (reg:SI 26))
5901 (clobber (reg:SI 25))
5902 (clobber (reg:SI 31))]
5903 "!TARGET_64BIT"
5904 "*
5905 return output_div_insn (operands, 0, insn);"
5906 [(set_attr "type" "milli")
5907 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5909 (define_insn ""
5910 [(set (reg:SI 29)
5911 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5912 (clobber (match_operand:SI 1 "register_operand" "=a"))
5913 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5914 (clobber (reg:SI 26))
5915 (clobber (reg:SI 25))
5916 (clobber (reg:SI 2))]
5917 "TARGET_64BIT"
5918 "*
5919 return output_div_insn (operands, 0, insn);"
5920 [(set_attr "type" "milli")
5921 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5923 (define_expand "udivsi3"
5924 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5925 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5926 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
5927 (clobber (match_dup 3))
5928 (clobber (match_dup 4))
5929 (clobber (reg:SI 26))
5930 (clobber (reg:SI 25))
5931 (clobber (match_dup 5))])
5932 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5933 ""
5934 "
5935 {
5936 operands[3] = gen_reg_rtx (SImode);
5938 if (TARGET_64BIT)
5939 {
5940 operands[5] = gen_rtx_REG (SImode, 2);
5941 operands[4] = operands[5];
5942 }
5943 else
5944 {
5945 operands[5] = gen_rtx_REG (SImode, 31);
5946 operands[4] = gen_reg_rtx (SImode);
5947 }
5948 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
5949 DONE;
5950 }")
5952 (define_insn ""
5953 [(set (reg:SI 29)
5954 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5955 (clobber (match_operand:SI 1 "register_operand" "=a"))
5956 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5957 (clobber (reg:SI 26))
5958 (clobber (reg:SI 25))
5959 (clobber (reg:SI 31))]
5960 "!TARGET_64BIT"
5961 "*
5962 return output_div_insn (operands, 1, insn);"
5963 [(set_attr "type" "milli")
5964 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5966 (define_insn ""
5967 [(set (reg:SI 29)
5968 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5969 (clobber (match_operand:SI 1 "register_operand" "=a"))
5970 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5971 (clobber (reg:SI 26))
5972 (clobber (reg:SI 25))
5973 (clobber (reg:SI 2))]
5974 "TARGET_64BIT"
5975 "*
5976 return output_div_insn (operands, 1, insn);"
5977 [(set_attr "type" "milli")
5978 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5980 (define_expand "modsi3"
5981 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5982 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5983 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5984 (clobber (match_dup 3))
5985 (clobber (match_dup 4))
5986 (clobber (reg:SI 26))
5987 (clobber (reg:SI 25))
5988 (clobber (match_dup 5))])
5989 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5990 ""
5991 "
5992 {
5993 if (TARGET_64BIT)
5994 {
5995 operands[5] = gen_rtx_REG (SImode, 2);
5996 operands[4] = operands[5];
5997 }
5998 else
5999 {
6000 operands[5] = gen_rtx_REG (SImode, 31);
6001 operands[4] = gen_reg_rtx (SImode);
6002 }
6003 operands[3] = gen_reg_rtx (SImode);
6004 }")
6006 (define_insn ""
6007 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
6008 (clobber (match_operand:SI 0 "register_operand" "=a"))
6009 (clobber (match_operand:SI 1 "register_operand" "=&r"))
6010 (clobber (reg:SI 26))
6011 (clobber (reg:SI 25))
6012 (clobber (reg:SI 31))]
6013 "!TARGET_64BIT"
6014 "*
6015 return output_mod_insn (0, insn);"
6016 [(set_attr "type" "milli")
6017 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
6019 (define_insn ""
6020 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
6021 (clobber (match_operand:SI 0 "register_operand" "=a"))
6022 (clobber (match_operand:SI 1 "register_operand" "=&r"))
6023 (clobber (reg:SI 26))
6024 (clobber (reg:SI 25))
6025 (clobber (reg:SI 2))]
6026 "TARGET_64BIT"
6027 "*
6028 return output_mod_insn (0, insn);"
6029 [(set_attr "type" "milli")
6030 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
6032 (define_expand "umodsi3"
6033 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
6034 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
6035 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
6036 (clobber (match_dup 3))
6037 (clobber (match_dup 4))
6038 (clobber (reg:SI 26))
6039 (clobber (reg:SI 25))
6040 (clobber (match_dup 5))])
6041 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
6042 ""
6043 "
6044 {
6045 if (TARGET_64BIT)
6046 {
6047 operands[5] = gen_rtx_REG (SImode, 2);
6048 operands[4] = operands[5];
6049 }
6050 else
6051 {
6052 operands[5] = gen_rtx_REG (SImode, 31);
6053 operands[4] = gen_reg_rtx (SImode);
6054 }
6055 operands[3] = gen_reg_rtx (SImode);
6056 }")
6058 (define_insn ""
6059 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
6060 (clobber (match_operand:SI 0 "register_operand" "=a"))
6061 (clobber (match_operand:SI 1 "register_operand" "=&r"))
6062 (clobber (reg:SI 26))
6063 (clobber (reg:SI 25))
6064 (clobber (reg:SI 31))]
6065 "!TARGET_64BIT"
6066 "*
6067 return output_mod_insn (1, insn);"
6068 [(set_attr "type" "milli")
6069 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
6071 (define_insn ""
6072 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
6073 (clobber (match_operand:SI 0 "register_operand" "=a"))
6074 (clobber (match_operand:SI 1 "register_operand" "=&r"))
6075 (clobber (reg:SI 26))
6076 (clobber (reg:SI 25))
6077 (clobber (reg:SI 2))]
6078 "TARGET_64BIT"
6079 "*
6080 return output_mod_insn (1, insn);"
6081 [(set_attr "type" "milli")
6082 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
6084 ;;- and instructions
6085 ;; We define DImode `and` so with DImode `not` we can get
6086 ;; DImode `andn`. Other combinations are possible.
6088 (define_expand "anddi3"
6089 [(set (match_operand:DI 0 "register_operand" "")
6090 (and:DI (match_operand:DI 1 "register_operand" "")
6091 (match_operand:DI 2 "and_operand" "")))]
6092 ""
6093 "
6094 {
6095 /* Both operands must be register operands. */
6096 if (!TARGET_64BIT && !register_operand (operands[2], DImode))
6097 FAIL;
6098 }")
6100 (define_insn ""
6101 [(set (match_operand:DI 0 "register_operand" "=r")
6102 (and:DI (match_operand:DI 1 "register_operand" "%r")
6103 (match_operand:DI 2 "register_operand" "r")))]
6104 "!TARGET_64BIT"
6105 "and %1,%2,%0\;and %R1,%R2,%R0"
6106 [(set_attr "type" "binary")
6107 (set_attr "length" "8")])
6109 (define_insn ""
6110 [(set (match_operand:DI 0 "register_operand" "=r,r")
6111 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
6112 (match_operand:DI 2 "and_operand" "rO,P")))]
6113 "TARGET_64BIT"
6114 "* return output_64bit_and (operands); "
6115 [(set_attr "type" "binary")
6116 (set_attr "length" "4")])
6118 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
6119 ; constant with ldil;ldo.
6120 (define_insn "andsi3"
6121 [(set (match_operand:SI 0 "register_operand" "=r,r")
6122 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
6123 (match_operand:SI 2 "and_operand" "rO,P")))]
6124 ""
6125 "* return output_and (operands); "
6126 [(set_attr "type" "binary,shift")
6127 (set_attr "length" "4,4")])
6129 (define_insn ""
6130 [(set (match_operand:DI 0 "register_operand" "=r")
6131 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
6132 (match_operand:DI 2 "register_operand" "r")))]
6133 "!TARGET_64BIT"
6134 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
6135 [(set_attr "type" "binary")
6136 (set_attr "length" "8")])
6138 (define_insn ""
6139 [(set (match_operand:DI 0 "register_operand" "=r")
6140 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
6141 (match_operand:DI 2 "register_operand" "r")))]
6142 "TARGET_64BIT"
6143 "andcm %2,%1,%0"
6144 [(set_attr "type" "binary")
6145 (set_attr "length" "4")])
6147 (define_insn ""
6148 [(set (match_operand:SI 0 "register_operand" "=r")
6149 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
6150 (match_operand:SI 2 "register_operand" "r")))]
6151 ""
6152 "andcm %2,%1,%0"
6153 [(set_attr "type" "binary")
6154 (set_attr "length" "4")])
6156 (define_expand "iordi3"
6157 [(set (match_operand:DI 0 "register_operand" "")
6158 (ior:DI (match_operand:DI 1 "register_operand" "")
6159 (match_operand:DI 2 "ior_operand" "")))]
6160 ""
6161 "
6162 {
6163 /* Both operands must be register operands. */
6164 if (!TARGET_64BIT && !register_operand (operands[2], DImode))
6165 FAIL;
6166 }")
6168 (define_insn ""
6169 [(set (match_operand:DI 0 "register_operand" "=r")
6170 (ior:DI (match_operand:DI 1 "register_operand" "%r")
6171 (match_operand:DI 2 "register_operand" "r")))]
6172 "!TARGET_64BIT"
6173 "or %1,%2,%0\;or %R1,%R2,%R0"
6174 [(set_attr "type" "binary")
6175 (set_attr "length" "8")])
6177 (define_insn ""
6178 [(set (match_operand:DI 0 "register_operand" "=r,r")
6179 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
6180 (match_operand:DI 2 "ior_operand" "M,i")))]
6181 "TARGET_64BIT"
6182 "* return output_64bit_ior (operands); "
6183 [(set_attr "type" "binary,shift")
6184 (set_attr "length" "4,4")])
6186 (define_insn ""
6187 [(set (match_operand:DI 0 "register_operand" "=r")
6188 (ior:DI (match_operand:DI 1 "register_operand" "%r")
6189 (match_operand:DI 2 "register_operand" "r")))]
6190 "TARGET_64BIT"
6191 "or %1,%2,%0"
6192 [(set_attr "type" "binary")
6193 (set_attr "length" "4")])
6195 ;; Need a define_expand because we've run out of CONST_OK... characters.
6196 (define_expand "iorsi3"
6197 [(set (match_operand:SI 0 "register_operand" "")
6198 (ior:SI (match_operand:SI 1 "register_operand" "")
6199 (match_operand:SI 2 "arith32_operand" "")))]
6200 ""
6201 "
6202 {
6203 if (! (ior_operand (operands[2], SImode)
6204 || register_operand (operands[2], SImode)))
6205 operands[2] = force_reg (SImode, operands[2]);
6206 }")
6208 (define_insn ""
6209 [(set (match_operand:SI 0 "register_operand" "=r,r")
6210 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
6211 (match_operand:SI 2 "ior_operand" "M,i")))]
6212 ""
6213 "* return output_ior (operands); "
6214 [(set_attr "type" "binary,shift")
6215 (set_attr "length" "4,4")])
6217 (define_insn ""
6218 [(set (match_operand:SI 0 "register_operand" "=r")
6219 (ior:SI (match_operand:SI 1 "register_operand" "%r")
6220 (match_operand:SI 2 "register_operand" "r")))]
6221 ""
6222 "or %1,%2,%0"
6223 [(set_attr "type" "binary")
6224 (set_attr "length" "4")])
6226 (define_expand "xordi3"
6227 [(set (match_operand:DI 0 "register_operand" "")
6228 (xor:DI (match_operand:DI 1 "register_operand" "")
6229 (match_operand:DI 2 "register_operand" "")))]
6230 ""
6231 "
6232 {
6233 }")
6235 (define_insn ""
6236 [(set (match_operand:DI 0 "register_operand" "=r")
6237 (xor:DI (match_operand:DI 1 "register_operand" "%r")
6238 (match_operand:DI 2 "register_operand" "r")))]
6239 "!TARGET_64BIT"
6240 "xor %1,%2,%0\;xor %R1,%R2,%R0"
6241 [(set_attr "type" "binary")
6242 (set_attr "length" "8")])
6244 (define_insn ""
6245 [(set (match_operand:DI 0 "register_operand" "=r")
6246 (xor:DI (match_operand:DI 1 "register_operand" "%r")
6247 (match_operand:DI 2 "register_operand" "r")))]
6248 "TARGET_64BIT"
6249 "xor %1,%2,%0"
6250 [(set_attr "type" "binary")
6251 (set_attr "length" "4")])
6253 (define_insn "xorsi3"
6254 [(set (match_operand:SI 0 "register_operand" "=r")
6255 (xor:SI (match_operand:SI 1 "register_operand" "%r")
6256 (match_operand:SI 2 "register_operand" "r")))]
6257 ""
6258 "xor %1,%2,%0"
6259 [(set_attr "type" "binary")
6260 (set_attr "length" "4")])
6262 (define_expand "negdi2"
6263 [(set (match_operand:DI 0 "register_operand" "")
6264 (neg:DI (match_operand:DI 1 "register_operand" "")))]
6265 ""
6266 "")
6268 (define_insn ""
6269 [(set (match_operand:DI 0 "register_operand" "=r")
6270 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
6271 "!TARGET_64BIT"
6272 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
6273 [(set_attr "type" "unary")
6274 (set_attr "length" "8")])
6276 (define_insn ""
6277 [(set (match_operand:DI 0 "register_operand" "=r")
6278 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
6279 "TARGET_64BIT"
6280 "sub %%r0,%1,%0"
6281 [(set_attr "type" "unary")
6282 (set_attr "length" "4")])
6284 (define_expand "negvdi2"
6285 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6286 (neg:DI (match_operand:DI 1 "register_operand" "")))
6287 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
6288 (sign_extend:TI (neg:DI (match_dup 1))))
6289 (const_int 0))])]
6290 ""
6291 "")
6293 (define_insn ""
6294 [(set (match_operand:DI 0 "register_operand" "=r")
6295 (neg:DI (match_operand:DI 1 "register_operand" "r")))
6296 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
6297 (sign_extend:TI (neg:DI (match_dup 1))))
6298 (const_int 0))]
6299 "!TARGET_64BIT"
6300 "sub %%r0,%R1,%R0\;{subbo|sub,b,tsv} %%r0,%1,%0"
6301 [(set_attr "type" "unary")
6302 (set_attr "length" "8")])
6304 (define_insn ""
6305 [(set (match_operand:DI 0 "register_operand" "=r")
6306 (neg:DI (match_operand:DI 1 "register_operand" "r")))
6307 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
6308 (sign_extend:TI (neg:DI (match_dup 1))))
6309 (const_int 0))]
6310 "TARGET_64BIT"
6311 "sub,tsv %%r0,%1,%0"
6312 [(set_attr "type" "unary")
6313 (set_attr "length" "4")])
6315 (define_insn "negsi2"
6316 [(set (match_operand:SI 0 "register_operand" "=r")
6317 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
6318 ""
6319 "sub %%r0,%1,%0"
6320 [(set_attr "type" "unary")
6321 (set_attr "length" "4")])
6323 (define_insn "negvsi2"
6324 [(set (match_operand:SI 0 "register_operand" "=r")
6325 (neg:SI (match_operand:SI 1 "register_operand" "r")))
6326 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
6327 (sign_extend:DI (neg:SI (match_dup 1))))
6328 (const_int 0))]
6329 ""
6330 "{subo|sub,tsv} %%r0,%1,%0"
6331 [(set_attr "type" "unary")
6332 (set_attr "length" "4")])
6334 (define_expand "one_cmpldi2"
6335 [(set (match_operand:DI 0 "register_operand" "")
6336 (not:DI (match_operand:DI 1 "register_operand" "")))]
6337 ""
6338 "
6339 {
6340 }")
6342 (define_insn ""
6343 [(set (match_operand:DI 0 "register_operand" "=r")
6344 (not:DI (match_operand:DI 1 "register_operand" "r")))]
6345 "!TARGET_64BIT"
6346 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
6347 [(set_attr "type" "unary")
6348 (set_attr "length" "8")])
6350 (define_insn ""
6351 [(set (match_operand:DI 0 "register_operand" "=r")
6352 (not:DI (match_operand:DI 1 "register_operand" "r")))]
6353 "TARGET_64BIT"
6354 "uaddcm %%r0,%1,%0"
6355 [(set_attr "type" "unary")
6356 (set_attr "length" "4")])
6358 (define_insn "one_cmplsi2"
6359 [(set (match_operand:SI 0 "register_operand" "=r")
6360 (not:SI (match_operand:SI 1 "register_operand" "r")))]
6361 ""
6362 "uaddcm %%r0,%1,%0"
6363 [(set_attr "type" "unary")
6364 (set_attr "length" "4")])
6365 \f
6366 ;; Floating point arithmetic instructions.
6368 (define_insn "adddf3"
6369 [(set (match_operand:DF 0 "register_operand" "=f")
6370 (plus:DF (match_operand:DF 1 "register_operand" "f")
6371 (match_operand:DF 2 "register_operand" "f")))]
6372 "! TARGET_SOFT_FLOAT"
6373 "fadd,dbl %1,%2,%0"
6374 [(set_attr "type" "fpalu")
6375 (set_attr "pa_combine_type" "faddsub")
6376 (set_attr "length" "4")])
6378 (define_insn "addsf3"
6379 [(set (match_operand:SF 0 "register_operand" "=f")
6380 (plus:SF (match_operand:SF 1 "register_operand" "f")
6381 (match_operand:SF 2 "register_operand" "f")))]
6382 "! TARGET_SOFT_FLOAT"
6383 "fadd,sgl %1,%2,%0"
6384 [(set_attr "type" "fpalu")
6385 (set_attr "pa_combine_type" "faddsub")
6386 (set_attr "length" "4")])
6388 (define_insn "subdf3"
6389 [(set (match_operand:DF 0 "register_operand" "=f")
6390 (minus:DF (match_operand:DF 1 "register_operand" "f")
6391 (match_operand:DF 2 "register_operand" "f")))]
6392 "! TARGET_SOFT_FLOAT"
6393 "fsub,dbl %1,%2,%0"
6394 [(set_attr "type" "fpalu")
6395 (set_attr "pa_combine_type" "faddsub")
6396 (set_attr "length" "4")])
6398 (define_insn "subsf3"
6399 [(set (match_operand:SF 0 "register_operand" "=f")
6400 (minus:SF (match_operand:SF 1 "register_operand" "f")
6401 (match_operand:SF 2 "register_operand" "f")))]
6402 "! TARGET_SOFT_FLOAT"
6403 "fsub,sgl %1,%2,%0"
6404 [(set_attr "type" "fpalu")
6405 (set_attr "pa_combine_type" "faddsub")
6406 (set_attr "length" "4")])
6408 (define_insn "muldf3"
6409 [(set (match_operand:DF 0 "register_operand" "=f")
6410 (mult:DF (match_operand:DF 1 "register_operand" "f")
6411 (match_operand:DF 2 "register_operand" "f")))]
6412 "! TARGET_SOFT_FLOAT"
6413 "fmpy,dbl %1,%2,%0"
6414 [(set_attr "type" "fpmuldbl")
6415 (set_attr "pa_combine_type" "fmpy")
6416 (set_attr "length" "4")])
6418 (define_insn "mulsf3"
6419 [(set (match_operand:SF 0 "register_operand" "=f")
6420 (mult:SF (match_operand:SF 1 "register_operand" "f")
6421 (match_operand:SF 2 "register_operand" "f")))]
6422 "! TARGET_SOFT_FLOAT"
6423 "fmpy,sgl %1,%2,%0"
6424 [(set_attr "type" "fpmulsgl")
6425 (set_attr "pa_combine_type" "fmpy")
6426 (set_attr "length" "4")])
6428 (define_insn "divdf3"
6429 [(set (match_operand:DF 0 "register_operand" "=f")
6430 (div:DF (match_operand:DF 1 "register_operand" "f")
6431 (match_operand:DF 2 "register_operand" "f")))]
6432 "! TARGET_SOFT_FLOAT"
6433 "fdiv,dbl %1,%2,%0"
6434 [(set_attr "type" "fpdivdbl")
6435 (set_attr "length" "4")])
6437 (define_insn "divsf3"
6438 [(set (match_operand:SF 0 "register_operand" "=f")
6439 (div:SF (match_operand:SF 1 "register_operand" "f")
6440 (match_operand:SF 2 "register_operand" "f")))]
6441 "! TARGET_SOFT_FLOAT"
6442 "fdiv,sgl %1,%2,%0"
6443 [(set_attr "type" "fpdivsgl")
6444 (set_attr "length" "4")])
6446 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
6447 ;; negation can be done by subtracting from plus zero. However, this
6448 ;; violates the IEEE standard when negating plus and minus zero.
6449 (define_expand "negdf2"
6450 [(parallel [(set (match_operand:DF 0 "register_operand" "")
6451 (neg:DF (match_operand:DF 1 "register_operand" "")))
6452 (use (match_dup 2))])]
6453 "! TARGET_SOFT_FLOAT"
6454 {
6455 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
6456 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
6457 else
6458 {
6459 operands[2] = force_reg (DFmode,
6460 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, DFmode));
6461 emit_insn (gen_muldf3 (operands[0], operands[1], operands[2]));
6462 }
6463 DONE;
6464 })
6466 (define_insn "negdf2_fast"
6467 [(set (match_operand:DF 0 "register_operand" "=f")
6468 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
6469 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
6470 "*
6471 {
6472 if (TARGET_PA_20)
6473 return \"fneg,dbl %1,%0\";
6474 else
6475 return \"fsub,dbl %%fr0,%1,%0\";
6476 }"
6477 [(set_attr "type" "fpalu")
6478 (set_attr "length" "4")])
6480 (define_expand "negsf2"
6481 [(parallel [(set (match_operand:SF 0 "register_operand" "")
6482 (neg:SF (match_operand:SF 1 "register_operand" "")))
6483 (use (match_dup 2))])]
6484 "! TARGET_SOFT_FLOAT"
6485 {
6486 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
6487 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
6488 else
6489 {
6490 operands[2] = force_reg (SFmode,
6491 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, SFmode));
6492 emit_insn (gen_mulsf3 (operands[0], operands[1], operands[2]));
6493 }
6494 DONE;
6495 })
6497 (define_insn "negsf2_fast"
6498 [(set (match_operand:SF 0 "register_operand" "=f")
6499 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
6500 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
6501 "*
6502 {
6503 if (TARGET_PA_20)
6504 return \"fneg,sgl %1,%0\";
6505 else
6506 return \"fsub,sgl %%fr0,%1,%0\";
6507 }"
6508 [(set_attr "type" "fpalu")
6509 (set_attr "length" "4")])
6511 (define_insn "absdf2"
6512 [(set (match_operand:DF 0 "register_operand" "=f")
6513 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
6514 "! TARGET_SOFT_FLOAT"
6515 "fabs,dbl %1,%0"
6516 [(set_attr "type" "fpalu")
6517 (set_attr "length" "4")])
6519 (define_insn "abssf2"
6520 [(set (match_operand:SF 0 "register_operand" "=f")
6521 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
6522 "! TARGET_SOFT_FLOAT"
6523 "fabs,sgl %1,%0"
6524 [(set_attr "type" "fpalu")
6525 (set_attr "length" "4")])
6527 (define_insn "sqrtdf2"
6528 [(set (match_operand:DF 0 "register_operand" "=f")
6529 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
6530 "! TARGET_SOFT_FLOAT"
6531 "fsqrt,dbl %1,%0"
6532 [(set_attr "type" "fpsqrtdbl")
6533 (set_attr "length" "4")])
6535 (define_insn "sqrtsf2"
6536 [(set (match_operand:SF 0 "register_operand" "=f")
6537 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
6538 "! TARGET_SOFT_FLOAT"
6539 "fsqrt,sgl %1,%0"
6540 [(set_attr "type" "fpsqrtsgl")
6541 (set_attr "length" "4")])
6543 ;; PA 2.0 floating point instructions
6545 ; fmpyfadd patterns
6546 (define_insn ""
6547 [(set (match_operand:DF 0 "register_operand" "=f")
6548 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6549 (match_operand:DF 2 "register_operand" "f"))
6550 (match_operand:DF 3 "register_operand" "f")))]
6551 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6552 "fmpyfadd,dbl %1,%2,%3,%0"
6553 [(set_attr "type" "fpmuldbl")
6554 (set_attr "length" "4")])
6556 (define_insn ""
6557 [(set (match_operand:DF 0 "register_operand" "=f")
6558 (plus:DF (match_operand:DF 1 "register_operand" "f")
6559 (mult:DF (match_operand:DF 2 "register_operand" "f")
6560 (match_operand:DF 3 "register_operand" "f"))))]
6561 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6562 "fmpyfadd,dbl %2,%3,%1,%0"
6563 [(set_attr "type" "fpmuldbl")
6564 (set_attr "length" "4")])
6566 (define_insn ""
6567 [(set (match_operand:SF 0 "register_operand" "=f")
6568 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6569 (match_operand:SF 2 "register_operand" "f"))
6570 (match_operand:SF 3 "register_operand" "f")))]
6571 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6572 "fmpyfadd,sgl %1,%2,%3,%0"
6573 [(set_attr "type" "fpmulsgl")
6574 (set_attr "length" "4")])
6576 (define_insn ""
6577 [(set (match_operand:SF 0 "register_operand" "=f")
6578 (plus:SF (match_operand:SF 1 "register_operand" "f")
6579 (mult:SF (match_operand:SF 2 "register_operand" "f")
6580 (match_operand:SF 3 "register_operand" "f"))))]
6581 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6582 "fmpyfadd,sgl %2,%3,%1,%0"
6583 [(set_attr "type" "fpmulsgl")
6584 (set_attr "length" "4")])
6586 ; fmpynfadd patterns
6587 (define_insn ""
6588 [(set (match_operand:DF 0 "register_operand" "=f")
6589 (minus:DF (match_operand:DF 1 "register_operand" "f")
6590 (mult:DF (match_operand:DF 2 "register_operand" "f")
6591 (match_operand:DF 3 "register_operand" "f"))))]
6592 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6593 "fmpynfadd,dbl %2,%3,%1,%0"
6594 [(set_attr "type" "fpmuldbl")
6595 (set_attr "length" "4")])
6597 (define_insn ""
6598 [(set (match_operand:SF 0 "register_operand" "=f")
6599 (minus:SF (match_operand:SF 1 "register_operand" "f")
6600 (mult:SF (match_operand:SF 2 "register_operand" "f")
6601 (match_operand:SF 3 "register_operand" "f"))))]
6602 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6603 "fmpynfadd,sgl %2,%3,%1,%0"
6604 [(set_attr "type" "fpmulsgl")
6605 (set_attr "length" "4")])
6607 ; fnegabs patterns
6608 (define_insn ""
6609 [(set (match_operand:DF 0 "register_operand" "=f")
6610 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
6611 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6612 "fnegabs,dbl %1,%0"
6613 [(set_attr "type" "fpalu")
6614 (set_attr "length" "4")])
6616 (define_insn ""
6617 [(set (match_operand:SF 0 "register_operand" "=f")
6618 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
6619 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6620 "fnegabs,sgl %1,%0"
6621 [(set_attr "type" "fpalu")
6622 (set_attr "length" "4")])
6624 ;; Generating a fused multiply sequence is a win for this case as it will
6625 ;; reduce the latency for the fused case without impacting the plain
6626 ;; multiply case.
6627 ;;
6628 ;; Similar possibilities exist for fnegabs, shadd and other insns which
6629 ;; perform two operations with the result of the first feeding the second.
6630 (define_insn ""
6631 [(set (match_operand:DF 0 "register_operand" "=f")
6632 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6633 (match_operand:DF 2 "register_operand" "f"))
6634 (match_operand:DF 3 "register_operand" "f")))
6635 (set (match_operand:DF 4 "register_operand" "=&f")
6636 (mult:DF (match_dup 1) (match_dup 2)))]
6637 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6638 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6639 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6640 "#"
6641 [(set_attr "type" "fpmuldbl")
6642 (set_attr "length" "8")])
6644 ;; We want to split this up during scheduling since we want both insns
6645 ;; to schedule independently.
6646 (define_split
6647 [(set (match_operand:DF 0 "register_operand" "")
6648 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6649 (match_operand:DF 2 "register_operand" ""))
6650 (match_operand:DF 3 "register_operand" "")))
6651 (set (match_operand:DF 4 "register_operand" "")
6652 (mult:DF (match_dup 1) (match_dup 2)))]
6653 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6654 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6655 (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
6656 (match_dup 3)))]
6657 "")
6659 (define_insn ""
6660 [(set (match_operand:SF 0 "register_operand" "=f")
6661 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6662 (match_operand:SF 2 "register_operand" "f"))
6663 (match_operand:SF 3 "register_operand" "f")))
6664 (set (match_operand:SF 4 "register_operand" "=&f")
6665 (mult:SF (match_dup 1) (match_dup 2)))]
6666 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6667 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6668 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6669 "#"
6670 [(set_attr "type" "fpmuldbl")
6671 (set_attr "length" "8")])
6673 ;; We want to split this up during scheduling since we want both insns
6674 ;; to schedule independently.
6675 (define_split
6676 [(set (match_operand:SF 0 "register_operand" "")
6677 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6678 (match_operand:SF 2 "register_operand" ""))
6679 (match_operand:SF 3 "register_operand" "")))
6680 (set (match_operand:SF 4 "register_operand" "")
6681 (mult:SF (match_dup 1) (match_dup 2)))]
6682 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6683 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6684 (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
6685 (match_dup 3)))]
6686 "")
6688 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
6689 ;; instruction.
6690 (define_insn ""
6691 [(set (match_operand:DF 0 "register_operand" "=f")
6692 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6693 (match_operand:DF 2 "register_operand" "f"))))]
6694 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6695 "fmpynfadd,dbl %1,%2,%%fr0,%0"
6696 [(set_attr "type" "fpmuldbl")
6697 (set_attr "length" "4")])
6699 (define_insn ""
6700 [(set (match_operand:SF 0 "register_operand" "=f")
6701 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6702 (match_operand:SF 2 "register_operand" "f"))))]
6703 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6704 "fmpynfadd,sgl %1,%2,%%fr0,%0"
6705 [(set_attr "type" "fpmuldbl")
6706 (set_attr "length" "4")])
6708 (define_insn ""
6709 [(set (match_operand:DF 0 "register_operand" "=f")
6710 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6711 (match_operand:DF 2 "register_operand" "f"))))
6712 (set (match_operand:DF 3 "register_operand" "=&f")
6713 (mult:DF (match_dup 1) (match_dup 2)))]
6714 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6715 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6716 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6717 "#"
6718 [(set_attr "type" "fpmuldbl")
6719 (set_attr "length" "8")])
6721 (define_split
6722 [(set (match_operand:DF 0 "register_operand" "")
6723 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6724 (match_operand:DF 2 "register_operand" ""))))
6725 (set (match_operand:DF 3 "register_operand" "")
6726 (mult:DF (match_dup 1) (match_dup 2)))]
6727 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6728 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
6729 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
6730 "")
6732 (define_insn ""
6733 [(set (match_operand:SF 0 "register_operand" "=f")
6734 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6735 (match_operand:SF 2 "register_operand" "f"))))
6736 (set (match_operand:SF 3 "register_operand" "=&f")
6737 (mult:SF (match_dup 1) (match_dup 2)))]
6738 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6739 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6740 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6741 "#"
6742 [(set_attr "type" "fpmuldbl")
6743 (set_attr "length" "8")])
6745 (define_split
6746 [(set (match_operand:SF 0 "register_operand" "")
6747 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6748 (match_operand:SF 2 "register_operand" ""))))
6749 (set (match_operand:SF 3 "register_operand" "")
6750 (mult:SF (match_dup 1) (match_dup 2)))]
6751 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6752 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
6753 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
6754 "")
6756 ;; Now fused multiplies with the result of the multiply negated.
6757 (define_insn ""
6758 [(set (match_operand:DF 0 "register_operand" "=f")
6759 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6760 (match_operand:DF 2 "register_operand" "f")))
6761 (match_operand:DF 3 "register_operand" "f")))]
6762 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6763 "fmpynfadd,dbl %1,%2,%3,%0"
6764 [(set_attr "type" "fpmuldbl")
6765 (set_attr "length" "4")])
6767 (define_insn ""
6768 [(set (match_operand:SF 0 "register_operand" "=f")
6769 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6770 (match_operand:SF 2 "register_operand" "f")))
6771 (match_operand:SF 3 "register_operand" "f")))]
6772 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6773 "fmpynfadd,sgl %1,%2,%3,%0"
6774 [(set_attr "type" "fpmuldbl")
6775 (set_attr "length" "4")])
6777 (define_insn ""
6778 [(set (match_operand:DF 0 "register_operand" "=f")
6779 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6780 (match_operand:DF 2 "register_operand" "f")))
6781 (match_operand:DF 3 "register_operand" "f")))
6782 (set (match_operand:DF 4 "register_operand" "=&f")
6783 (mult:DF (match_dup 1) (match_dup 2)))]
6784 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6785 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6786 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6787 "#"
6788 [(set_attr "type" "fpmuldbl")
6789 (set_attr "length" "8")])
6791 (define_split
6792 [(set (match_operand:DF 0 "register_operand" "")
6793 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6794 (match_operand:DF 2 "register_operand" "")))
6795 (match_operand:DF 3 "register_operand" "")))
6796 (set (match_operand:DF 4 "register_operand" "")
6797 (mult:DF (match_dup 1) (match_dup 2)))]
6798 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6799 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6800 (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
6801 (match_dup 3)))]
6802 "")
6804 (define_insn ""
6805 [(set (match_operand:SF 0 "register_operand" "=f")
6806 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6807 (match_operand:SF 2 "register_operand" "f")))
6808 (match_operand:SF 3 "register_operand" "f")))
6809 (set (match_operand:SF 4 "register_operand" "=&f")
6810 (mult:SF (match_dup 1) (match_dup 2)))]
6811 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6812 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6813 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6814 "#"
6815 [(set_attr "type" "fpmuldbl")
6816 (set_attr "length" "8")])
6818 (define_split
6819 [(set (match_operand:SF 0 "register_operand" "")
6820 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6821 (match_operand:SF 2 "register_operand" "")))
6822 (match_operand:SF 3 "register_operand" "")))
6823 (set (match_operand:SF 4 "register_operand" "")
6824 (mult:SF (match_dup 1) (match_dup 2)))]
6825 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6826 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6827 (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
6828 (match_dup 3)))]
6829 "")
6831 (define_insn ""
6832 [(set (match_operand:DF 0 "register_operand" "=f")
6833 (minus:DF (match_operand:DF 3 "register_operand" "f")
6834 (mult:DF (match_operand:DF 1 "register_operand" "f")
6835 (match_operand:DF 2 "register_operand" "f"))))
6836 (set (match_operand:DF 4 "register_operand" "=&f")
6837 (mult:DF (match_dup 1) (match_dup 2)))]
6838 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6839 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6840 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6841 "#"
6842 [(set_attr "type" "fpmuldbl")
6843 (set_attr "length" "8")])
6845 (define_split
6846 [(set (match_operand:DF 0 "register_operand" "")
6847 (minus:DF (match_operand:DF 3 "register_operand" "")
6848 (mult:DF (match_operand:DF 1 "register_operand" "")
6849 (match_operand:DF 2 "register_operand" ""))))
6850 (set (match_operand:DF 4 "register_operand" "")
6851 (mult:DF (match_dup 1) (match_dup 2)))]
6852 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6853 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6854 (set (match_dup 0) (minus:DF (match_dup 3)
6855 (mult:DF (match_dup 1) (match_dup 2))))]
6856 "")
6858 (define_insn ""
6859 [(set (match_operand:SF 0 "register_operand" "=f")
6860 (minus:SF (match_operand:SF 3 "register_operand" "f")
6861 (mult:SF (match_operand:SF 1 "register_operand" "f")
6862 (match_operand:SF 2 "register_operand" "f"))))
6863 (set (match_operand:SF 4 "register_operand" "=&f")
6864 (mult:SF (match_dup 1) (match_dup 2)))]
6865 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6866 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6867 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6868 "#"
6869 [(set_attr "type" "fpmuldbl")
6870 (set_attr "length" "8")])
6872 (define_split
6873 [(set (match_operand:SF 0 "register_operand" "")
6874 (minus:SF (match_operand:SF 3 "register_operand" "")
6875 (mult:SF (match_operand:SF 1 "register_operand" "")
6876 (match_operand:SF 2 "register_operand" ""))))
6877 (set (match_operand:SF 4 "register_operand" "")
6878 (mult:SF (match_dup 1) (match_dup 2)))]
6879 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6880 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6881 (set (match_dup 0) (minus:SF (match_dup 3)
6882 (mult:SF (match_dup 1) (match_dup 2))))]
6883 "")
6885 (define_insn ""
6886 [(set (match_operand:DF 0 "register_operand" "=f")
6887 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6888 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
6889 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6890 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6891 "#"
6892 [(set_attr "type" "fpalu")
6893 (set_attr "length" "8")])
6895 (define_split
6896 [(set (match_operand:DF 0 "register_operand" "")
6897 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
6898 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
6899 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6900 [(set (match_dup 2) (abs:DF (match_dup 1)))
6901 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
6902 "")
6904 (define_insn ""
6905 [(set (match_operand:SF 0 "register_operand" "=f")
6906 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6907 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
6908 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6909 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6910 "#"
6911 [(set_attr "type" "fpalu")
6912 (set_attr "length" "8")])
6914 (define_split
6915 [(set (match_operand:SF 0 "register_operand" "")
6916 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
6917 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
6918 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6919 [(set (match_dup 2) (abs:SF (match_dup 1)))
6920 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
6921 "")
6922 \f
6923 ;;- Shift instructions
6925 ;; Optimized special case of shifting.
6927 (define_insn ""
6928 [(set (match_operand:SI 0 "register_operand" "=r")
6929 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6930 (const_int 24)))]
6931 ""
6932 "ldb%M1 %1,%0"
6933 [(set_attr "type" "load")
6934 (set_attr "length" "4")])
6936 (define_insn ""
6937 [(set (match_operand:SI 0 "register_operand" "=r")
6938 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6939 (const_int 16)))]
6940 ""
6941 "ldh%M1 %1,%0"
6942 [(set_attr "type" "load")
6943 (set_attr "length" "4")])
6945 (define_insn ""
6946 [(set (match_operand:SI 0 "register_operand" "=r")
6947 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
6948 (match_operand:SI 3 "shadd_operand" ""))
6949 (match_operand:SI 1 "register_operand" "r")))]
6950 ""
6951 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
6952 [(set_attr "type" "binary")
6953 (set_attr "length" "4")])
6955 (define_insn ""
6956 [(set (match_operand:DI 0 "register_operand" "=r")
6957 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
6958 (match_operand:DI 3 "shadd_operand" ""))
6959 (match_operand:DI 1 "register_operand" "r")))]
6960 "TARGET_64BIT"
6961 "shladd,l %2,%O3,%1,%0"
6962 [(set_attr "type" "binary")
6963 (set_attr "length" "4")])
6965 (define_expand "ashlsi3"
6966 [(set (match_operand:SI 0 "register_operand" "")
6967 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
6968 (match_operand:SI 2 "arith32_operand" "")))]
6969 ""
6970 "
6971 {
6972 if (GET_CODE (operands[2]) != CONST_INT)
6973 {
6974 rtx temp = gen_reg_rtx (SImode);
6975 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6976 if (GET_CODE (operands[1]) == CONST_INT)
6977 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
6978 else
6979 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
6980 DONE;
6981 }
6982 /* Make sure both inputs are not constants,
6983 there are no patterns for that. */
6984 operands[1] = force_reg (SImode, operands[1]);
6985 }")
6987 (define_insn ""
6988 [(set (match_operand:SI 0 "register_operand" "=r")
6989 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6990 (match_operand:SI 2 "const_int_operand" "n")))]
6991 ""
6992 "{zdep|depw,z} %1,%P2,%L2,%0"
6993 [(set_attr "type" "shift")
6994 (set_attr "length" "4")])
6996 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
6997 ; Doing it like this makes slightly better code since reload can
6998 ; replace a register with a known value in range -16..15 with a
6999 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
7000 ; but since we have no more CONST_OK... characters, that is not
7001 ; possible.
7002 (define_insn "zvdep32"
7003 [(set (match_operand:SI 0 "register_operand" "=r,r")
7004 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
7005 (minus:SI (const_int 31)
7006 (match_operand:SI 2 "register_operand" "q,q"))))]
7007 ""
7008 "@
7009 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
7010 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
7011 [(set_attr "type" "shift,shift")
7012 (set_attr "length" "4,4")])
7014 (define_insn "zvdep_imm32"
7015 [(set (match_operand:SI 0 "register_operand" "=r")
7016 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
7017 (minus:SI (const_int 31)
7018 (match_operand:SI 2 "register_operand" "q"))))]
7019 ""
7020 "*
7021 {
7022 int x = INTVAL (operands[1]);
7023 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
7024 operands[1] = GEN_INT ((x & 0xf) - 0x10);
7025 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
7026 }"
7027 [(set_attr "type" "shift")
7028 (set_attr "length" "4")])
7030 (define_insn "vdepi_ior"
7031 [(set (match_operand:SI 0 "register_operand" "=r")
7032 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
7033 (minus:SI (const_int 31)
7034 (match_operand:SI 2 "register_operand" "q")))
7035 (match_operand:SI 3 "register_operand" "0")))]
7036 ; accept ...0001...1, can this be generalized?
7037 "exact_log2 (INTVAL (operands[1]) + 1) > 0"
7038 "*
7039 {
7040 int x = INTVAL (operands[1]);
7041 operands[2] = GEN_INT (exact_log2 (x + 1));
7042 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
7043 }"
7044 [(set_attr "type" "shift")
7045 (set_attr "length" "4")])
7047 (define_insn "vdepi_and"
7048 [(set (match_operand:SI 0 "register_operand" "=r")
7049 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
7050 (minus:SI (const_int 31)
7051 (match_operand:SI 2 "register_operand" "q")))
7052 (match_operand:SI 3 "register_operand" "0")))]
7053 ; this can be generalized...!
7054 "INTVAL (operands[1]) == -2"
7055 "*
7056 {
7057 int x = INTVAL (operands[1]);
7058 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
7059 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
7060 }"
7061 [(set_attr "type" "shift")
7062 (set_attr "length" "4")])
7064 (define_expand "ashldi3"
7065 [(set (match_operand:DI 0 "register_operand" "")
7066 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
7067 (match_operand:DI 2 "arith32_operand" "")))]
7068 "TARGET_64BIT"
7069 "
7070 {
7071 if (GET_CODE (operands[2]) != CONST_INT)
7072 {
7073 rtx temp = gen_reg_rtx (DImode);
7074 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
7075 if (GET_CODE (operands[1]) == CONST_INT)
7076 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
7077 else
7078 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
7079 DONE;
7080 }
7081 /* Make sure both inputs are not constants,
7082 there are no patterns for that. */
7083 operands[1] = force_reg (DImode, operands[1]);
7084 }")
7086 (define_insn ""
7087 [(set (match_operand:DI 0 "register_operand" "=r")
7088 (ashift:DI (match_operand:DI 1 "register_operand" "r")
7089 (match_operand:DI 2 "const_int_operand" "n")))]
7090 "TARGET_64BIT"
7091 "depd,z %1,%p2,%Q2,%0"
7092 [(set_attr "type" "shift")
7093 (set_attr "length" "4")])
7095 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
7096 ; Doing it like this makes slightly better code since reload can
7097 ; replace a register with a known value in range -16..15 with a
7098 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
7099 ; but since we have no more CONST_OK... characters, that is not
7100 ; possible.
7101 (define_insn "zvdep64"
7102 [(set (match_operand:DI 0 "register_operand" "=r,r")
7103 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
7104 (minus:DI (const_int 63)
7105 (match_operand:DI 2 "register_operand" "q,q"))))]
7106 "TARGET_64BIT"
7107 "@
7108 depd,z %1,%%sar,64,%0
7109 depdi,z %1,%%sar,64,%0"
7110 [(set_attr "type" "shift,shift")
7111 (set_attr "length" "4,4")])
7113 (define_insn "zvdep_imm64"
7114 [(set (match_operand:DI 0 "register_operand" "=r")
7115 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
7116 (minus:DI (const_int 63)
7117 (match_operand:DI 2 "register_operand" "q"))))]
7118 "TARGET_64BIT"
7119 "*
7120 {
7121 int x = INTVAL (operands[1]);
7122 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
7123 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
7124 return \"depdi,z %1,%%sar,%2,%0\";
7125 }"
7126 [(set_attr "type" "shift")
7127 (set_attr "length" "4")])
7129 (define_insn ""
7130 [(set (match_operand:DI 0 "register_operand" "=r")
7131 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
7132 (minus:DI (const_int 63)
7133 (match_operand:DI 2 "register_operand" "q")))
7134 (match_operand:DI 3 "register_operand" "0")))]
7135 ; accept ...0001...1, can this be generalized?
7136 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) > 0"
7137 "*
7138 {
7139 int x = INTVAL (operands[1]);
7140 operands[2] = GEN_INT (exact_log2 (x + 1));
7141 return \"depdi -1,%%sar,%2,%0\";
7142 }"
7143 [(set_attr "type" "shift")
7144 (set_attr "length" "4")])
7146 (define_insn ""
7147 [(set (match_operand:DI 0 "register_operand" "=r")
7148 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
7149 (minus:DI (const_int 63)
7150 (match_operand:DI 2 "register_operand" "q")))
7151 (match_operand:DI 3 "register_operand" "0")))]
7152 ; this can be generalized...!
7153 "TARGET_64BIT && INTVAL (operands[1]) == -2"
7154 "*
7155 {
7156 int x = INTVAL (operands[1]);
7157 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
7158 return \"depdi 0,%%sar,%2,%0\";
7159 }"
7160 [(set_attr "type" "shift")
7161 (set_attr "length" "4")])
7163 (define_expand "ashrsi3"
7164 [(set (match_operand:SI 0 "register_operand" "")
7165 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
7166 (match_operand:SI 2 "arith32_operand" "")))]
7167 ""
7168 "
7169 {
7170 if (GET_CODE (operands[2]) != CONST_INT)
7171 {
7172 rtx temp = gen_reg_rtx (SImode);
7173 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
7174 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
7175 DONE;
7176 }
7177 }")
7179 (define_insn ""
7180 [(set (match_operand:SI 0 "register_operand" "=r")
7181 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
7182 (match_operand:SI 2 "const_int_operand" "n")))]
7183 ""
7184 "{extrs|extrw,s} %1,%P2,%L2,%0"
7185 [(set_attr "type" "shift")
7186 (set_attr "length" "4")])
7188 (define_insn "vextrs32"
7189 [(set (match_operand:SI 0 "register_operand" "=r")
7190 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
7191 (minus:SI (const_int 31)
7192 (match_operand:SI 2 "register_operand" "q"))))]
7193 ""
7194 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
7195 [(set_attr "type" "shift")
7196 (set_attr "length" "4")])
7198 (define_expand "ashrdi3"
7199 [(set (match_operand:DI 0 "register_operand" "")
7200 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
7201 (match_operand:DI 2 "arith32_operand" "")))]
7202 "TARGET_64BIT"
7203 "
7204 {
7205 if (GET_CODE (operands[2]) != CONST_INT)
7206 {
7207 rtx temp = gen_reg_rtx (DImode);
7208 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
7209 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
7210 DONE;
7211 }
7212 }")
7214 (define_insn ""
7215 [(set (match_operand:DI 0 "register_operand" "=r")
7216 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
7217 (match_operand:DI 2 "const_int_operand" "n")))]
7218 "TARGET_64BIT"
7219 "extrd,s %1,%p2,%Q2,%0"
7220 [(set_attr "type" "shift")
7221 (set_attr "length" "4")])
7223 (define_insn "vextrs64"
7224 [(set (match_operand:DI 0 "register_operand" "=r")
7225 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
7226 (minus:DI (const_int 63)
7227 (match_operand:DI 2 "register_operand" "q"))))]
7228 "TARGET_64BIT"
7229 "extrd,s %1,%%sar,64,%0"
7230 [(set_attr "type" "shift")
7231 (set_attr "length" "4")])
7233 (define_insn "lshrsi3"
7234 [(set (match_operand:SI 0 "register_operand" "=r,r")
7235 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
7236 (match_operand:SI 2 "arith32_operand" "q,n")))]
7237 ""
7238 "@
7239 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
7240 {extru|extrw,u} %1,%P2,%L2,%0"
7241 [(set_attr "type" "shift")
7242 (set_attr "length" "4")])
7244 (define_insn "lshrdi3"
7245 [(set (match_operand:DI 0 "register_operand" "=r,r")
7246 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
7247 (match_operand:DI 2 "arith32_operand" "q,n")))]
7248 "TARGET_64BIT"
7249 "@
7250 shrpd %%r0,%1,%%sar,%0
7251 extrd,u %1,%p2,%Q2,%0"
7252 [(set_attr "type" "shift")
7253 (set_attr "length" "4")])
7255 (define_insn "rotrsi3"
7256 [(set (match_operand:SI 0 "register_operand" "=r,r")
7257 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
7258 (match_operand:SI 2 "arith32_operand" "q,n")))]
7259 ""
7260 "*
7261 {
7262 if (GET_CODE (operands[2]) == CONST_INT)
7263 {
7264 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
7265 return \"{shd|shrpw} %1,%1,%2,%0\";
7266 }
7267 else
7268 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
7269 }"
7270 [(set_attr "type" "shift")
7271 (set_attr "length" "4")])
7273 (define_expand "rotlsi3"
7274 [(set (match_operand:SI 0 "register_operand" "")
7275 (rotate:SI (match_operand:SI 1 "register_operand" "")
7276 (match_operand:SI 2 "arith32_operand" "")))]
7277 ""
7278 "
7279 {
7280 if (GET_CODE (operands[2]) != CONST_INT)
7281 {
7282 rtx temp = gen_reg_rtx (SImode);
7283 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
7284 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
7285 DONE;
7286 }
7287 /* Else expand normally. */
7288 }")
7290 (define_insn ""
7291 [(set (match_operand:SI 0 "register_operand" "=r")
7292 (rotate:SI (match_operand:SI 1 "register_operand" "r")
7293 (match_operand:SI 2 "const_int_operand" "n")))]
7294 ""
7295 "*
7296 {
7297 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
7298 return \"{shd|shrpw} %1,%1,%2,%0\";
7299 }"
7300 [(set_attr "type" "shift")
7301 (set_attr "length" "4")])
7303 (define_insn ""
7304 [(set (match_operand:SI 0 "register_operand" "=r")
7305 (match_operator:SI 5 "plus_xor_ior_operator"
7306 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
7307 (match_operand:SI 3 "const_int_operand" "n"))
7308 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
7309 (match_operand:SI 4 "const_int_operand" "n"))]))]
7310 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
7311 "{shd|shrpw} %1,%2,%4,%0"
7312 [(set_attr "type" "shift")
7313 (set_attr "length" "4")])
7315 (define_insn ""
7316 [(set (match_operand:SI 0 "register_operand" "=r")
7317 (match_operator:SI 5 "plus_xor_ior_operator"
7318 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
7319 (match_operand:SI 4 "const_int_operand" "n"))
7320 (ashift:SI (match_operand:SI 1 "register_operand" "r")
7321 (match_operand:SI 3 "const_int_operand" "n"))]))]
7322 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
7323 "{shd|shrpw} %1,%2,%4,%0"
7324 [(set_attr "type" "shift")
7325 (set_attr "length" "4")])
7327 (define_insn ""
7328 [(set (match_operand:SI 0 "register_operand" "=r")
7329 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
7330 (match_operand:SI 2 "const_int_operand" ""))
7331 (match_operand:SI 3 "const_int_operand" "")))]
7332 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) > 0"
7333 "*
7334 {
7335 int cnt = INTVAL (operands[2]) & 31;
7336 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
7337 operands[2] = GEN_INT (31 - cnt);
7338 return \"{zdep|depw,z} %1,%2,%3,%0\";
7339 }"
7340 [(set_attr "type" "shift")
7341 (set_attr "length" "4")])
7342 \f
7343 ;; Unconditional and other jump instructions.
7345 ;; This is used for most returns.
7346 (define_insn "return_internal"
7347 [(return)
7348 (use (reg:SI 2))]
7349 ""
7350 "*
7351 {
7352 if (TARGET_PA_20)
7353 return \"bve%* (%%r2)\";
7354 return \"bv%* %%r0(%%r2)\";
7355 }"
7356 [(set_attr "type" "branch")
7357 (set_attr "length" "4")])
7359 ;; This is used for eh returns which bypass the return stub.
7360 (define_insn "return_external_pic"
7361 [(return)
7362 (clobber (reg:SI 1))
7363 (use (reg:SI 2))]
7364 "!TARGET_NO_SPACE_REGS
7365 && !TARGET_PA_20
7366 && flag_pic && current_function_calls_eh_return"
7367 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
7368 [(set_attr "type" "branch")
7369 (set_attr "length" "12")])
7371 (define_expand "prologue"
7372 [(const_int 0)]
7373 ""
7374 "hppa_expand_prologue ();DONE;")
7376 (define_expand "sibcall_epilogue"
7377 [(return)]
7378 ""
7379 "
7380 {
7381 hppa_expand_epilogue ();
7382 DONE;
7383 }")
7385 (define_expand "epilogue"
7386 [(return)]
7387 ""
7388 "
7389 {
7390 rtx x;
7392 /* Try to use the trivial return first. Else use the full epilogue. */
7393 if (reload_completed
7394 && !frame_pointer_needed
7395 && !df_regs_ever_live_p (2)
7396 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1))
7397 x = gen_return_internal ();
7398 else
7399 {
7400 hppa_expand_epilogue ();
7402 /* EH returns bypass the normal return stub. Thus, we must do an
7403 interspace branch to return from functions that call eh_return.
7404 This is only a problem for returns from shared code on ports
7405 using space registers. */
7406 if (!TARGET_NO_SPACE_REGS
7407 && !TARGET_PA_20
7408 && flag_pic && current_function_calls_eh_return)
7409 x = gen_return_external_pic ();
7410 else
7411 x = gen_return_internal ();
7412 }
7413 emit_jump_insn (x);
7414 DONE;
7415 }")
7417 ; Used by hppa_profile_hook to load the starting address of the current
7418 ; function; operand 1 contains the address of the label in operand 3
7419 (define_insn "load_offset_label_address"
7420 [(set (match_operand:SI 0 "register_operand" "=r")
7421 (plus:SI (match_operand:SI 1 "register_operand" "r")
7422 (minus:SI (match_operand:SI 2 "" "")
7423 (label_ref:SI (match_operand 3 "" "")))))]
7424 ""
7425 "ldo %2-%l3(%1),%0"
7426 [(set_attr "type" "multi")
7427 (set_attr "length" "4")])
7429 ; Output a code label and load its address.
7430 (define_insn "lcla1"
7431 [(set (match_operand:SI 0 "register_operand" "=r")
7432 (label_ref:SI (match_operand 1 "" "")))
7433 (const_int 0)]
7434 "!TARGET_PA_20"
7435 "*
7436 {
7437 output_asm_insn (\"bl .+8,%0\;depi 0,31,2,%0\", operands);
7438 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
7439 CODE_LABEL_NUMBER (operands[1]));
7440 return \"\";
7441 }"
7442 [(set_attr "type" "multi")
7443 (set_attr "length" "8")])
7445 (define_insn "lcla2"
7446 [(set (match_operand:SI 0 "register_operand" "=r")
7447 (label_ref:SI (match_operand 1 "" "")))
7448 (const_int 0)]
7449 "TARGET_PA_20"
7450 "*
7451 {
7452 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
7453 CODE_LABEL_NUMBER (operands[1]));
7454 return \"mfia %0\";
7455 }"
7456 [(set_attr "type" "move")
7457 (set_attr "length" "4")])
7459 (define_insn "blockage"
7460 [(unspec_volatile [(const_int 2)] UNSPECV_BLOCKAGE)]
7461 ""
7462 ""
7463 [(set_attr "length" "0")])
7465 (define_insn "jump"
7466 [(set (pc) (label_ref (match_operand 0 "" "")))]
7467 ""
7468 "*
7469 {
7470 /* An unconditional branch which can reach its target. */
7471 if (get_attr_length (insn) < 16)
7472 return \"b%* %l0\";
7474 return output_lbranch (operands[0], insn, 1);
7475 }"
7476 [(set_attr "type" "uncond_branch")
7477 (set_attr "pa_combine_type" "uncond_branch")
7478 (set (attr "length")
7479 (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
7480 (if_then_else (lt (abs (minus (match_dup 0)
7481 (plus (pc) (const_int 8))))
7482 (const_int MAX_12BIT_OFFSET))
7483 (const_int 4)
7484 (const_int 8))
7485 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
7486 (const_int MAX_17BIT_OFFSET))
7487 (const_int 4)
7488 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
7489 (const_int 20)
7490 (eq (symbol_ref "flag_pic") (const_int 0))
7491 (const_int 16)]
7492 (const_int 24)))])
7494 ;;; Hope this is only within a function...
7495 (define_insn "indirect_jump"
7496 [(set (pc) (match_operand 0 "register_operand" "r"))]
7497 "GET_MODE (operands[0]) == word_mode"
7498 "bv%* %%r0(%0)"
7499 [(set_attr "type" "branch")
7500 (set_attr "length" "4")])
7502 ;;; An indirect jump can be optimized to a direct jump. GAS for the
7503 ;;; SOM target doesn't allow branching to a label inside a function.
7504 ;;; We also don't correctly compute branch distances for labels
7505 ;;; outside the current function. Thus, we use an indirect jump can't
7506 ;;; be optimized to a direct jump for all targets. We assume that
7507 ;;; the branch target is in the same space (i.e., nested function
7508 ;;; jumping to a label in an outer function in the same translation
7509 ;;; unit).
7510 (define_expand "nonlocal_goto"
7511 [(use (match_operand 0 "general_operand" ""))
7512 (use (match_operand 1 "general_operand" ""))
7513 (use (match_operand 2 "general_operand" ""))
7514 (use (match_operand 3 "general_operand" ""))]
7515 ""
7516 {
7517 rtx lab = operands[1];
7518 rtx stack = operands[2];
7519 rtx fp = operands[3];
7521 lab = copy_to_reg (lab);
7523 emit_insn (gen_rtx_CLOBBER (VOIDmode,
7524 gen_rtx_MEM (BLKmode,
7525 gen_rtx_SCRATCH (VOIDmode))));
7526 emit_insn (gen_rtx_CLOBBER (VOIDmode,
7527 gen_rtx_MEM (BLKmode,
7528 hard_frame_pointer_rtx)));
7530 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
7531 instead of the hard_frame_pointer_rtx in the save area. As a
7532 result, an extra instruction is needed to adjust for the offset
7533 of the virtual stack variables and the frame pointer. */
7534 if (GET_CODE (fp) != REG)
7535 fp = force_reg (Pmode, fp);
7536 emit_move_insn (virtual_stack_vars_rtx, fp);
7538 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
7540 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
7541 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
7543 /* Nonlocal goto jumps are only used between functions in the same
7544 translation unit. Thus, we can avoid the extra overhead of an
7545 interspace jump. */
7546 emit_jump_insn (gen_indirect_goto (lab));
7547 emit_barrier ();
7548 DONE;
7549 })
7551 (define_insn "indirect_goto"
7552 [(unspec [(match_operand 0 "register_operand" "=r")] UNSPEC_GOTO)]
7553 "GET_MODE (operands[0]) == word_mode"
7554 "bv%* %%r0(%0)"
7555 [(set_attr "type" "branch")
7556 (set_attr "length" "4")])
7558 ;;; This jump is used in branch tables where the insn length is fixed.
7559 ;;; The length of this insn is adjusted if the delay slot is not filled.
7560 (define_insn "short_jump"
7561 [(set (pc) (label_ref (match_operand 0 "" "")))
7562 (const_int 0)]
7563 ""
7564 "b%* %l0%#"
7565 [(set_attr "type" "btable_branch")
7566 (set_attr "length" "4")])
7568 ;; Subroutines of "casesi".
7569 ;; operand 0 is index
7570 ;; operand 1 is the minimum bound
7571 ;; operand 2 is the maximum bound - minimum bound + 1
7572 ;; operand 3 is CODE_LABEL for the table;
7573 ;; operand 4 is the CODE_LABEL to go to if index out of range.
7575 (define_expand "casesi"
7576 [(match_operand:SI 0 "general_operand" "")
7577 (match_operand:SI 1 "const_int_operand" "")
7578 (match_operand:SI 2 "const_int_operand" "")
7579 (match_operand 3 "" "")
7580 (match_operand 4 "" "")]
7581 ""
7582 "
7583 {
7584 if (GET_CODE (operands[0]) != REG)
7585 operands[0] = force_reg (SImode, operands[0]);
7587 if (operands[1] != const0_rtx)
7588 {
7589 rtx index = gen_reg_rtx (SImode);
7591 operands[1] = GEN_INT (-INTVAL (operands[1]));
7592 if (!INT_14_BITS (operands[1]))
7593 operands[1] = force_reg (SImode, operands[1]);
7594 emit_insn (gen_addsi3 (index, operands[0], operands[1]));
7595 operands[0] = index;
7596 }
7598 /* In 64bit mode we must make sure to wipe the upper bits of the register
7599 just in case the addition overflowed or we had random bits in the
7600 high part of the register. */
7601 if (TARGET_64BIT)
7602 {
7603 rtx index = gen_reg_rtx (DImode);
7605 emit_insn (gen_extendsidi2 (index, operands[0]));
7606 operands[0] = gen_rtx_SUBREG (SImode, index, 4);
7607 }
7609 if (!INT_5_BITS (operands[2]))
7610 operands[2] = force_reg (SImode, operands[2]);
7612 /* This branch prevents us finding an insn for the delay slot of the
7613 following vectored branch. It might be possible to use the delay
7614 slot if an index value of -1 was used to transfer to the out-of-range
7615 label. In order to do this, we would have to output the -1 vector
7616 element after the delay insn. The casesi output code would have to
7617 check if the casesi insn is in a delay branch sequence and output
7618 the delay insn if one is found. If this was done, then it might
7619 then be worthwhile to split the casesi patterns to improve scheduling.
7620 However, it's not clear that all this extra complexity is worth
7621 the effort. */
7622 emit_insn (gen_cmpsi (operands[0], operands[2]));
7623 emit_jump_insn (gen_bgtu (operands[4]));
7625 if (TARGET_BIG_SWITCH)
7626 {
7627 if (TARGET_64BIT)
7628 emit_jump_insn (gen_casesi64p (operands[0], operands[3]));
7629 else if (flag_pic)
7630 emit_jump_insn (gen_casesi32p (operands[0], operands[3]));
7631 else
7632 emit_jump_insn (gen_casesi32 (operands[0], operands[3]));
7633 }
7634 else
7635 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
7636 DONE;
7637 }")
7639 ;;; The rtl for this pattern doesn't accurately describe what the insn
7640 ;;; actually does, particularly when case-vector elements are exploded
7641 ;;; in pa_reorg. However, the initial SET in these patterns must show
7642 ;;; the connection of the insn to the following jump table.
7643 (define_insn "casesi0"
7644 [(set (pc) (mem:SI (plus:SI
7645 (mult:SI (match_operand:SI 0 "register_operand" "r")
7646 (const_int 4))
7647 (label_ref (match_operand 1 "" "")))))]
7648 ""
7649 "blr,n %0,%%r0\;nop"
7650 [(set_attr "type" "multi")
7651 (set_attr "length" "8")])
7653 ;;; 32-bit code, absolute branch table.
7654 (define_insn "casesi32"
7655 [(set (pc) (mem:SI (plus:SI
7656 (mult:SI (match_operand:SI 0 "register_operand" "r")
7657 (const_int 4))
7658 (label_ref (match_operand 1 "" "")))))
7659 (clobber (match_scratch:SI 2 "=&r"))]
7660 "!flag_pic"
7661 "ldil L'%l1,%2\;ldo R'%l1(%2),%2\;{ldwx|ldw},s %0(%2),%2\;bv,n %%r0(%2)"
7662 [(set_attr "type" "multi")
7663 (set_attr "length" "16")])
7665 ;;; 32-bit code, relative branch table.
7666 (define_insn "casesi32p"
7667 [(set (pc) (mem:SI (plus:SI
7668 (mult:SI (match_operand:SI 0 "register_operand" "r")
7669 (const_int 4))
7670 (label_ref (match_operand 1 "" "")))))
7671 (clobber (match_scratch:SI 2 "=&r"))
7672 (clobber (match_scratch:SI 3 "=&r"))]
7673 "flag_pic"
7674 "{bl .+8,%2\;depi 0,31,2,%2|mfia %2}\;ldo {16|20}(%2),%2\;\
7675 {ldwx|ldw},s %0(%2),%3\;{addl|add,l} %2,%3,%3\;bv,n %%r0(%3)"
7676 [(set_attr "type" "multi")
7677 (set (attr "length")
7678 (if_then_else (ne (symbol_ref "TARGET_PA_20") (const_int 0))
7679 (const_int 20)
7680 (const_int 24)))])
7682 ;;; 64-bit code, 32-bit relative branch table.
7683 (define_insn "casesi64p"
7684 [(set (pc) (mem:DI (plus:DI
7685 (mult:DI (sign_extend:DI
7686 (match_operand:SI 0 "register_operand" "r"))
7687 (const_int 8))
7688 (label_ref (match_operand 1 "" "")))))
7689 (clobber (match_scratch:DI 2 "=&r"))
7690 (clobber (match_scratch:DI 3 "=&r"))]
7691 ""
7692 "mfia %2\;ldo 24(%2),%2\;ldw,s %0(%2),%3\;extrd,s %3,63,32,%3\;\
7693 add,l %2,%3,%3\;bv,n %%r0(%3)"
7694 [(set_attr "type" "multi")
7695 (set_attr "length" "24")])
7698 ;; Call patterns.
7699 ;;- jump to subroutine
7701 (define_expand "call"
7702 [(parallel [(call (match_operand:SI 0 "" "")
7703 (match_operand 1 "" ""))
7704 (clobber (reg:SI 2))])]
7705 ""
7706 "
7707 {
7708 rtx op, call_insn;
7709 rtx nb = operands[1];
7711 if (TARGET_PORTABLE_RUNTIME)
7712 op = force_reg (SImode, XEXP (operands[0], 0));
7713 else
7714 op = XEXP (operands[0], 0);
7716 if (TARGET_64BIT)
7717 {
7718 if (!virtuals_instantiated)
7719 emit_move_insn (arg_pointer_rtx,
7720 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7721 GEN_INT (64)));
7722 else
7723 {
7724 /* The loop pass can generate new libcalls after the virtual
7725 registers are instantiated when fpregs are disabled because
7726 the only method that we have for doing DImode multiplication
7727 is with a libcall. This could be trouble if we haven't
7728 allocated enough space for the outgoing arguments. */
7729 gcc_assert (INTVAL (nb) <= current_function_outgoing_args_size);
7731 emit_move_insn (arg_pointer_rtx,
7732 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7733 GEN_INT (STACK_POINTER_OFFSET + 64)));
7734 }
7735 }
7737 /* Use two different patterns for calls to explicitly named functions
7738 and calls through function pointers. This is necessary as these two
7739 types of calls use different calling conventions, and CSE might try
7740 to change the named call into an indirect call in some cases (using
7741 two patterns keeps CSE from performing this optimization).
7743 We now use even more call patterns as there was a subtle bug in
7744 attempting to restore the pic register after a call using a simple
7745 move insn. During reload, a instruction involving a pseudo register
7746 with no explicit dependence on the PIC register can be converted
7747 to an equivalent load from memory using the PIC register. If we
7748 emit a simple move to restore the PIC register in the initial rtl
7749 generation, then it can potentially be repositioned during scheduling.
7750 and an instruction that eventually uses the PIC register may end up
7751 between the call and the PIC register restore.
7753 This only worked because there is a post call group of instructions
7754 that are scheduled with the call. These instructions are included
7755 in the same basic block as the call. However, calls can throw in
7756 C++ code and a basic block has to terminate at the call if the call
7757 can throw. This results in the PIC register restore being scheduled
7758 independently from the call. So, we now hide the save and restore
7759 of the PIC register in the call pattern until after reload. Then,
7760 we split the moves out. A small side benefit is that we now don't
7761 need to have a use of the PIC register in the return pattern and
7762 the final save/restore operation is not needed.
7764 I elected to just clobber %r4 in the PIC patterns and use it instead
7765 of trying to force hppa_pic_save_rtx () to a callee saved register.
7766 This might have required a new register class and constraint. It
7767 was also simpler to just handle the restore from a register than a
7768 generic pseudo. */
7769 if (TARGET_64BIT)
7770 {
7771 if (GET_CODE (op) == SYMBOL_REF)
7772 call_insn = emit_call_insn (gen_call_symref_64bit (op, nb));
7773 else
7774 {
7775 op = force_reg (word_mode, op);
7776 call_insn = emit_call_insn (gen_call_reg_64bit (op, nb));
7777 }
7778 }
7779 else
7780 {
7781 if (GET_CODE (op) == SYMBOL_REF)
7782 {
7783 if (flag_pic)
7784 call_insn = emit_call_insn (gen_call_symref_pic (op, nb));
7785 else
7786 call_insn = emit_call_insn (gen_call_symref (op, nb));
7787 }
7788 else
7789 {
7790 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7792 emit_move_insn (tmpreg, force_reg (word_mode, op));
7793 if (flag_pic)
7794 call_insn = emit_call_insn (gen_call_reg_pic (nb));
7795 else
7796 call_insn = emit_call_insn (gen_call_reg (nb));
7797 }
7798 }
7800 DONE;
7801 }")
7803 ;; We use function calls to set the attribute length of calls and millicode
7804 ;; calls. This is necessary because of the large variety of call sequences.
7805 ;; Implementing the calculation in rtl is difficult as well as ugly. As
7806 ;; we need the same calculation in several places, maintenance becomes a
7807 ;; nightmare.
7808 ;;
7809 ;; However, this has a subtle impact on branch shortening. When the
7810 ;; expression used to set the length attribute of an instruction depends
7811 ;; on a relative address (e.g., pc or a branch address), genattrtab
7812 ;; notes that the insn's length is variable, and attempts to determine a
7813 ;; worst-case default length and code to compute an insn's current length.
7815 ;; The use of a function call hides the variable dependence of our calls
7816 ;; and millicode calls. The result is genattrtab doesn't treat the operation
7817 ;; as variable and it only generates code for the default case using our
7818 ;; function call. Because of this, calls and millicode calls have a fixed
7819 ;; length in the branch shortening pass, and some branches will use a longer
7820 ;; code sequence than necessary. However, the length of any given call
7821 ;; will still reflect its final code location and it may be shorter than
7822 ;; the initial length estimate.
7824 ;; It's possible to trick genattrtab by adding an expression involving `pc'
7825 ;; in the set. However, when genattrtab hits a function call in its attempt
7826 ;; to compute the default length, it marks the result as unknown and sets
7827 ;; the default result to MAX_INT ;-( One possible fix that would allow
7828 ;; calls to participate in branch shortening would be to make the call to
7829 ;; insn_default_length a target option. Then, we could massage unknown
7830 ;; results. Another fix might be to change genattrtab so that it just does
7831 ;; the call in the variable case as it already does for the fixed case.
7833 (define_insn "call_symref"
7834 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7835 (match_operand 1 "" "i"))
7836 (clobber (reg:SI 1))
7837 (clobber (reg:SI 2))
7838 (use (const_int 0))]
7839 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7840 "*
7841 {
7842 output_arg_descriptor (insn);
7843 return output_call (insn, operands[0], 0);
7844 }"
7845 [(set_attr "type" "call")
7846 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7848 (define_insn "call_symref_pic"
7849 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7850 (match_operand 1 "" "i"))
7851 (clobber (reg:SI 1))
7852 (clobber (reg:SI 2))
7853 (clobber (reg:SI 4))
7854 (use (reg:SI 19))
7855 (use (const_int 0))]
7856 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7857 "*
7858 {
7859 output_arg_descriptor (insn);
7860 return output_call (insn, operands[0], 0);
7861 }"
7862 [(set_attr "type" "call")
7863 (set (attr "length")
7864 (plus (symbol_ref "attr_length_call (insn, 0)")
7865 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7867 ;; Split out the PIC register save and restore after reload. This is
7868 ;; done only if the function returns. As the split is done after reload,
7869 ;; there are some situations in which we unnecessarily save and restore
7870 ;; %r4. This happens when there is a single call and the PIC register
7871 ;; is "dead" after the call. This isn't easy to fix as the usage of
7872 ;; the PIC register isn't completely determined until the reload pass.
7873 (define_split
7874 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7875 (match_operand 1 "" ""))
7876 (clobber (reg:SI 1))
7877 (clobber (reg:SI 2))
7878 (clobber (reg:SI 4))
7879 (use (reg:SI 19))
7880 (use (const_int 0))])]
7881 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
7882 && reload_completed
7883 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7884 [(set (reg:SI 4) (reg:SI 19))
7885 (parallel [(call (mem:SI (match_dup 0))
7886 (match_dup 1))
7887 (clobber (reg:SI 1))
7888 (clobber (reg:SI 2))
7889 (use (reg:SI 19))
7890 (use (const_int 0))])
7891 (set (reg:SI 19) (reg:SI 4))]
7892 "")
7894 ;; Remove the clobber of register 4 when optimizing. This has to be
7895 ;; done with a peephole optimization rather than a split because the
7896 ;; split sequence for a call must be longer than one instruction.
7897 (define_peephole2
7898 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7899 (match_operand 1 "" ""))
7900 (clobber (reg:SI 1))
7901 (clobber (reg:SI 2))
7902 (clobber (reg:SI 4))
7903 (use (reg:SI 19))
7904 (use (const_int 0))])]
7905 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7906 [(parallel [(call (mem:SI (match_dup 0))
7907 (match_dup 1))
7908 (clobber (reg:SI 1))
7909 (clobber (reg:SI 2))
7910 (use (reg:SI 19))
7911 (use (const_int 0))])]
7912 "")
7914 (define_insn "*call_symref_pic_post_reload"
7915 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7916 (match_operand 1 "" "i"))
7917 (clobber (reg:SI 1))
7918 (clobber (reg:SI 2))
7919 (use (reg:SI 19))
7920 (use (const_int 0))]
7921 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7922 "*
7923 {
7924 output_arg_descriptor (insn);
7925 return output_call (insn, operands[0], 0);
7926 }"
7927 [(set_attr "type" "call")
7928 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7930 ;; This pattern is split if it is necessary to save and restore the
7931 ;; PIC register.
7932 (define_insn "call_symref_64bit"
7933 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7934 (match_operand 1 "" "i"))
7935 (clobber (reg:DI 1))
7936 (clobber (reg:DI 2))
7937 (clobber (reg:DI 4))
7938 (use (reg:DI 27))
7939 (use (reg:DI 29))
7940 (use (const_int 0))]
7941 "TARGET_64BIT"
7942 "*
7943 {
7944 output_arg_descriptor (insn);
7945 return output_call (insn, operands[0], 0);
7946 }"
7947 [(set_attr "type" "call")
7948 (set (attr "length")
7949 (plus (symbol_ref "attr_length_call (insn, 0)")
7950 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7952 ;; Split out the PIC register save and restore after reload. This is
7953 ;; done only if the function returns. As the split is done after reload,
7954 ;; there are some situations in which we unnecessarily save and restore
7955 ;; %r4. This happens when there is a single call and the PIC register
7956 ;; is "dead" after the call. This isn't easy to fix as the usage of
7957 ;; the PIC register isn't completely determined until the reload pass.
7958 (define_split
7959 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7960 (match_operand 1 "" ""))
7961 (clobber (reg:DI 1))
7962 (clobber (reg:DI 2))
7963 (clobber (reg:DI 4))
7964 (use (reg:DI 27))
7965 (use (reg:DI 29))
7966 (use (const_int 0))])]
7967 "TARGET_64BIT
7968 && reload_completed
7969 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7970 [(set (reg:DI 4) (reg:DI 27))
7971 (parallel [(call (mem:SI (match_dup 0))
7972 (match_dup 1))
7973 (clobber (reg:DI 1))
7974 (clobber (reg:DI 2))
7975 (use (reg:DI 27))
7976 (use (reg:DI 29))
7977 (use (const_int 0))])
7978 (set (reg:DI 27) (reg:DI 4))]
7979 "")
7981 ;; Remove the clobber of register 4 when optimizing. This has to be
7982 ;; done with a peephole optimization rather than a split because the
7983 ;; split sequence for a call must be longer than one instruction.
7984 (define_peephole2
7985 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7986 (match_operand 1 "" ""))
7987 (clobber (reg:DI 1))
7988 (clobber (reg:DI 2))
7989 (clobber (reg:DI 4))
7990 (use (reg:DI 27))
7991 (use (reg:DI 29))
7992 (use (const_int 0))])]
7993 "TARGET_64BIT && reload_completed"
7994 [(parallel [(call (mem:SI (match_dup 0))
7995 (match_dup 1))
7996 (clobber (reg:DI 1))
7997 (clobber (reg:DI 2))
7998 (use (reg:DI 27))
7999 (use (reg:DI 29))
8000 (use (const_int 0))])]
8001 "")
8003 (define_insn "*call_symref_64bit_post_reload"
8004 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8005 (match_operand 1 "" "i"))
8006 (clobber (reg:DI 1))
8007 (clobber (reg:DI 2))
8008 (use (reg:DI 27))
8009 (use (reg:DI 29))
8010 (use (const_int 0))]
8011 "TARGET_64BIT"
8012 "*
8013 {
8014 output_arg_descriptor (insn);
8015 return output_call (insn, operands[0], 0);
8016 }"
8017 [(set_attr "type" "call")
8018 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
8020 (define_insn "call_reg"
8021 [(call (mem:SI (reg:SI 22))
8022 (match_operand 0 "" "i"))
8023 (clobber (reg:SI 1))
8024 (clobber (reg:SI 2))
8025 (use (const_int 1))]
8026 "!TARGET_64BIT"
8027 "*
8028 {
8029 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8030 }"
8031 [(set_attr "type" "dyncall")
8032 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8034 ;; This pattern is split if it is necessary to save and restore the
8035 ;; PIC register.
8036 (define_insn "call_reg_pic"
8037 [(call (mem:SI (reg:SI 22))
8038 (match_operand 0 "" "i"))
8039 (clobber (reg:SI 1))
8040 (clobber (reg:SI 2))
8041 (clobber (reg:SI 4))
8042 (use (reg:SI 19))
8043 (use (const_int 1))]
8044 "!TARGET_64BIT"
8045 "*
8046 {
8047 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8048 }"
8049 [(set_attr "type" "dyncall")
8050 (set (attr "length")
8051 (plus (symbol_ref "attr_length_indirect_call (insn)")
8052 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8054 ;; Split out the PIC register save and restore after reload. This is
8055 ;; done only if the function returns. As the split is done after reload,
8056 ;; there are some situations in which we unnecessarily save and restore
8057 ;; %r4. This happens when there is a single call and the PIC register
8058 ;; is "dead" after the call. This isn't easy to fix as the usage of
8059 ;; the PIC register isn't completely determined until the reload pass.
8060 (define_split
8061 [(parallel [(call (mem:SI (reg:SI 22))
8062 (match_operand 0 "" ""))
8063 (clobber (reg:SI 1))
8064 (clobber (reg:SI 2))
8065 (clobber (reg:SI 4))
8066 (use (reg:SI 19))
8067 (use (const_int 1))])]
8068 "!TARGET_64BIT
8069 && reload_completed
8070 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8071 [(set (reg:SI 4) (reg:SI 19))
8072 (parallel [(call (mem:SI (reg:SI 22))
8073 (match_dup 0))
8074 (clobber (reg:SI 1))
8075 (clobber (reg:SI 2))
8076 (use (reg:SI 19))
8077 (use (const_int 1))])
8078 (set (reg:SI 19) (reg:SI 4))]
8079 "")
8081 ;; Remove the clobber of register 4 when optimizing. This has to be
8082 ;; done with a peephole optimization rather than a split because the
8083 ;; split sequence for a call must be longer than one instruction.
8084 (define_peephole2
8085 [(parallel [(call (mem:SI (reg:SI 22))
8086 (match_operand 0 "" ""))
8087 (clobber (reg:SI 1))
8088 (clobber (reg:SI 2))
8089 (clobber (reg:SI 4))
8090 (use (reg:SI 19))
8091 (use (const_int 1))])]
8092 "!TARGET_64BIT && reload_completed"
8093 [(parallel [(call (mem:SI (reg:SI 22))
8094 (match_dup 0))
8095 (clobber (reg:SI 1))
8096 (clobber (reg:SI 2))
8097 (use (reg:SI 19))
8098 (use (const_int 1))])]
8099 "")
8101 (define_insn "*call_reg_pic_post_reload"
8102 [(call (mem:SI (reg:SI 22))
8103 (match_operand 0 "" "i"))
8104 (clobber (reg:SI 1))
8105 (clobber (reg:SI 2))
8106 (use (reg:SI 19))
8107 (use (const_int 1))]
8108 "!TARGET_64BIT"
8109 "*
8110 {
8111 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8112 }"
8113 [(set_attr "type" "dyncall")
8114 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8116 ;; This pattern is split if it is necessary to save and restore the
8117 ;; PIC register.
8118 (define_insn "call_reg_64bit"
8119 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
8120 (match_operand 1 "" "i"))
8121 (clobber (reg:DI 2))
8122 (clobber (reg:DI 4))
8123 (use (reg:DI 27))
8124 (use (reg:DI 29))
8125 (use (const_int 1))]
8126 "TARGET_64BIT"
8127 "*
8128 {
8129 return output_indirect_call (insn, operands[0]);
8130 }"
8131 [(set_attr "type" "dyncall")
8132 (set (attr "length")
8133 (plus (symbol_ref "attr_length_indirect_call (insn)")
8134 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8136 ;; Split out the PIC register save and restore after reload. This is
8137 ;; done only if the function returns. As the split is done after reload,
8138 ;; there are some situations in which we unnecessarily save and restore
8139 ;; %r4. This happens when there is a single call and the PIC register
8140 ;; is "dead" after the call. This isn't easy to fix as the usage of
8141 ;; the PIC register isn't completely determined until the reload pass.
8142 (define_split
8143 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
8144 (match_operand 1 "" ""))
8145 (clobber (reg:DI 2))
8146 (clobber (reg:DI 4))
8147 (use (reg:DI 27))
8148 (use (reg:DI 29))
8149 (use (const_int 1))])]
8150 "TARGET_64BIT
8151 && reload_completed
8152 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8153 [(set (reg:DI 4) (reg:DI 27))
8154 (parallel [(call (mem:SI (match_dup 0))
8155 (match_dup 1))
8156 (clobber (reg:DI 2))
8157 (use (reg:DI 27))
8158 (use (reg:DI 29))
8159 (use (const_int 1))])
8160 (set (reg:DI 27) (reg:DI 4))]
8161 "")
8163 ;; Remove the clobber of register 4 when optimizing. This has to be
8164 ;; done with a peephole optimization rather than a split because the
8165 ;; split sequence for a call must be longer than one instruction.
8166 (define_peephole2
8167 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
8168 (match_operand 1 "" ""))
8169 (clobber (reg:DI 2))
8170 (clobber (reg:DI 4))
8171 (use (reg:DI 27))
8172 (use (reg:DI 29))
8173 (use (const_int 1))])]
8174 "TARGET_64BIT && reload_completed"
8175 [(parallel [(call (mem:SI (match_dup 0))
8176 (match_dup 1))
8177 (clobber (reg:DI 2))
8178 (use (reg:DI 27))
8179 (use (reg:DI 29))
8180 (use (const_int 1))])]
8181 "")
8183 (define_insn "*call_reg_64bit_post_reload"
8184 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
8185 (match_operand 1 "" "i"))
8186 (clobber (reg:DI 2))
8187 (use (reg:DI 27))
8188 (use (reg:DI 29))
8189 (use (const_int 1))]
8190 "TARGET_64BIT"
8191 "*
8192 {
8193 return output_indirect_call (insn, operands[0]);
8194 }"
8195 [(set_attr "type" "dyncall")
8196 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8198 (define_expand "call_value"
8199 [(parallel [(set (match_operand 0 "" "")
8200 (call (match_operand:SI 1 "" "")
8201 (match_operand 2 "" "")))
8202 (clobber (reg:SI 2))])]
8203 ""
8204 "
8205 {
8206 rtx op, call_insn;
8207 rtx dst = operands[0];
8208 rtx nb = operands[2];
8210 if (TARGET_PORTABLE_RUNTIME)
8211 op = force_reg (SImode, XEXP (operands[1], 0));
8212 else
8213 op = XEXP (operands[1], 0);
8215 if (TARGET_64BIT)
8216 {
8217 if (!virtuals_instantiated)
8218 emit_move_insn (arg_pointer_rtx,
8219 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8220 GEN_INT (64)));
8221 else
8222 {
8223 /* The loop pass can generate new libcalls after the virtual
8224 registers are instantiated when fpregs are disabled because
8225 the only method that we have for doing DImode multiplication
8226 is with a libcall. This could be trouble if we haven't
8227 allocated enough space for the outgoing arguments. */
8228 gcc_assert (INTVAL (nb) <= current_function_outgoing_args_size);
8230 emit_move_insn (arg_pointer_rtx,
8231 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8232 GEN_INT (STACK_POINTER_OFFSET + 64)));
8233 }
8234 }
8236 /* Use two different patterns for calls to explicitly named functions
8237 and calls through function pointers. This is necessary as these two
8238 types of calls use different calling conventions, and CSE might try
8239 to change the named call into an indirect call in some cases (using
8240 two patterns keeps CSE from performing this optimization).
8242 We now use even more call patterns as there was a subtle bug in
8243 attempting to restore the pic register after a call using a simple
8244 move insn. During reload, a instruction involving a pseudo register
8245 with no explicit dependence on the PIC register can be converted
8246 to an equivalent load from memory using the PIC register. If we
8247 emit a simple move to restore the PIC register in the initial rtl
8248 generation, then it can potentially be repositioned during scheduling.
8249 and an instruction that eventually uses the PIC register may end up
8250 between the call and the PIC register restore.
8252 This only worked because there is a post call group of instructions
8253 that are scheduled with the call. These instructions are included
8254 in the same basic block as the call. However, calls can throw in
8255 C++ code and a basic block has to terminate at the call if the call
8256 can throw. This results in the PIC register restore being scheduled
8257 independently from the call. So, we now hide the save and restore
8258 of the PIC register in the call pattern until after reload. Then,
8259 we split the moves out. A small side benefit is that we now don't
8260 need to have a use of the PIC register in the return pattern and
8261 the final save/restore operation is not needed.
8263 I elected to just clobber %r4 in the PIC patterns and use it instead
8264 of trying to force hppa_pic_save_rtx () to a callee saved register.
8265 This might have required a new register class and constraint. It
8266 was also simpler to just handle the restore from a register than a
8267 generic pseudo. */
8268 if (TARGET_64BIT)
8269 {
8270 if (GET_CODE (op) == SYMBOL_REF)
8271 call_insn = emit_call_insn (gen_call_val_symref_64bit (dst, op, nb));
8272 else
8273 {
8274 op = force_reg (word_mode, op);
8275 call_insn = emit_call_insn (gen_call_val_reg_64bit (dst, op, nb));
8276 }
8277 }
8278 else
8279 {
8280 if (GET_CODE (op) == SYMBOL_REF)
8281 {
8282 if (flag_pic)
8283 call_insn = emit_call_insn (gen_call_val_symref_pic (dst, op, nb));
8284 else
8285 call_insn = emit_call_insn (gen_call_val_symref (dst, op, nb));
8286 }
8287 else
8288 {
8289 rtx tmpreg = gen_rtx_REG (word_mode, 22);
8291 emit_move_insn (tmpreg, force_reg (word_mode, op));
8292 if (flag_pic)
8293 call_insn = emit_call_insn (gen_call_val_reg_pic (dst, nb));
8294 else
8295 call_insn = emit_call_insn (gen_call_val_reg (dst, nb));
8296 }
8297 }
8299 DONE;
8300 }")
8302 (define_insn "call_val_symref"
8303 [(set (match_operand 0 "" "")
8304 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8305 (match_operand 2 "" "i")))
8306 (clobber (reg:SI 1))
8307 (clobber (reg:SI 2))
8308 (use (const_int 0))]
8309 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8310 "*
8311 {
8312 output_arg_descriptor (insn);
8313 return output_call (insn, operands[1], 0);
8314 }"
8315 [(set_attr "type" "call")
8316 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
8318 (define_insn "call_val_symref_pic"
8319 [(set (match_operand 0 "" "")
8320 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8321 (match_operand 2 "" "i")))
8322 (clobber (reg:SI 1))
8323 (clobber (reg:SI 2))
8324 (clobber (reg:SI 4))
8325 (use (reg:SI 19))
8326 (use (const_int 0))]
8327 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8328 "*
8329 {
8330 output_arg_descriptor (insn);
8331 return output_call (insn, operands[1], 0);
8332 }"
8333 [(set_attr "type" "call")
8334 (set (attr "length")
8335 (plus (symbol_ref "attr_length_call (insn, 0)")
8336 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8338 ;; Split out the PIC register save and restore after reload. This is
8339 ;; done only if the function returns. As the split is done after reload,
8340 ;; there are some situations in which we unnecessarily save and restore
8341 ;; %r4. This happens when there is a single call and the PIC register
8342 ;; is "dead" after the call. This isn't easy to fix as the usage of
8343 ;; the PIC register isn't completely determined until the reload pass.
8344 (define_split
8345 [(parallel [(set (match_operand 0 "" "")
8346 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8347 (match_operand 2 "" "")))
8348 (clobber (reg:SI 1))
8349 (clobber (reg:SI 2))
8350 (clobber (reg:SI 4))
8351 (use (reg:SI 19))
8352 (use (const_int 0))])]
8353 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
8354 && reload_completed
8355 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8356 [(set (reg:SI 4) (reg:SI 19))
8357 (parallel [(set (match_dup 0)
8358 (call (mem:SI (match_dup 1))
8359 (match_dup 2)))
8360 (clobber (reg:SI 1))
8361 (clobber (reg:SI 2))
8362 (use (reg:SI 19))
8363 (use (const_int 0))])
8364 (set (reg:SI 19) (reg:SI 4))]
8365 "")
8367 ;; Remove the clobber of register 4 when optimizing. This has to be
8368 ;; done with a peephole optimization rather than a split because the
8369 ;; split sequence for a call must be longer than one instruction.
8370 (define_peephole2
8371 [(parallel [(set (match_operand 0 "" "")
8372 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8373 (match_operand 2 "" "")))
8374 (clobber (reg:SI 1))
8375 (clobber (reg:SI 2))
8376 (clobber (reg:SI 4))
8377 (use (reg:SI 19))
8378 (use (const_int 0))])]
8379 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
8380 [(parallel [(set (match_dup 0)
8381 (call (mem:SI (match_dup 1))
8382 (match_dup 2)))
8383 (clobber (reg:SI 1))
8384 (clobber (reg:SI 2))
8385 (use (reg:SI 19))
8386 (use (const_int 0))])]
8387 "")
8389 (define_insn "*call_val_symref_pic_post_reload"
8390 [(set (match_operand 0 "" "")
8391 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8392 (match_operand 2 "" "i")))
8393 (clobber (reg:SI 1))
8394 (clobber (reg:SI 2))
8395 (use (reg:SI 19))
8396 (use (const_int 0))]
8397 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8398 "*
8399 {
8400 output_arg_descriptor (insn);
8401 return output_call (insn, operands[1], 0);
8402 }"
8403 [(set_attr "type" "call")
8404 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
8406 ;; This pattern is split if it is necessary to save and restore the
8407 ;; PIC register.
8408 (define_insn "call_val_symref_64bit"
8409 [(set (match_operand 0 "" "")
8410 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8411 (match_operand 2 "" "i")))
8412 (clobber (reg:DI 1))
8413 (clobber (reg:DI 2))
8414 (clobber (reg:DI 4))
8415 (use (reg:DI 27))
8416 (use (reg:DI 29))
8417 (use (const_int 0))]
8418 "TARGET_64BIT"
8419 "*
8420 {
8421 output_arg_descriptor (insn);
8422 return output_call (insn, operands[1], 0);
8423 }"
8424 [(set_attr "type" "call")
8425 (set (attr "length")
8426 (plus (symbol_ref "attr_length_call (insn, 0)")
8427 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8429 ;; Split out the PIC register save and restore after reload. This is
8430 ;; done only if the function returns. As the split is done after reload,
8431 ;; there are some situations in which we unnecessarily save and restore
8432 ;; %r4. This happens when there is a single call and the PIC register
8433 ;; is "dead" after the call. This isn't easy to fix as the usage of
8434 ;; the PIC register isn't completely determined until the reload pass.
8435 (define_split
8436 [(parallel [(set (match_operand 0 "" "")
8437 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8438 (match_operand 2 "" "")))
8439 (clobber (reg:DI 1))
8440 (clobber (reg:DI 2))
8441 (clobber (reg:DI 4))
8442 (use (reg:DI 27))
8443 (use (reg:DI 29))
8444 (use (const_int 0))])]
8445 "TARGET_64BIT
8446 && reload_completed
8447 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8448 [(set (reg:DI 4) (reg:DI 27))
8449 (parallel [(set (match_dup 0)
8450 (call (mem:SI (match_dup 1))
8451 (match_dup 2)))
8452 (clobber (reg:DI 1))
8453 (clobber (reg:DI 2))
8454 (use (reg:DI 27))
8455 (use (reg:DI 29))
8456 (use (const_int 0))])
8457 (set (reg:DI 27) (reg:DI 4))]
8458 "")
8460 ;; Remove the clobber of register 4 when optimizing. This has to be
8461 ;; done with a peephole optimization rather than a split because the
8462 ;; split sequence for a call must be longer than one instruction.
8463 (define_peephole2
8464 [(parallel [(set (match_operand 0 "" "")
8465 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8466 (match_operand 2 "" "")))
8467 (clobber (reg:DI 1))
8468 (clobber (reg:DI 2))
8469 (clobber (reg:DI 4))
8470 (use (reg:DI 27))
8471 (use (reg:DI 29))
8472 (use (const_int 0))])]
8473 "TARGET_64BIT && reload_completed"
8474 [(parallel [(set (match_dup 0)
8475 (call (mem:SI (match_dup 1))
8476 (match_dup 2)))
8477 (clobber (reg:DI 1))
8478 (clobber (reg:DI 2))
8479 (use (reg:DI 27))
8480 (use (reg:DI 29))
8481 (use (const_int 0))])]
8482 "")
8484 (define_insn "*call_val_symref_64bit_post_reload"
8485 [(set (match_operand 0 "" "")
8486 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8487 (match_operand 2 "" "i")))
8488 (clobber (reg:DI 1))
8489 (clobber (reg:DI 2))
8490 (use (reg:DI 27))
8491 (use (reg:DI 29))
8492 (use (const_int 0))]
8493 "TARGET_64BIT"
8494 "*
8495 {
8496 output_arg_descriptor (insn);
8497 return output_call (insn, operands[1], 0);
8498 }"
8499 [(set_attr "type" "call")
8500 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
8502 (define_insn "call_val_reg"
8503 [(set (match_operand 0 "" "")
8504 (call (mem:SI (reg:SI 22))
8505 (match_operand 1 "" "i")))
8506 (clobber (reg:SI 1))
8507 (clobber (reg:SI 2))
8508 (use (const_int 1))]
8509 "!TARGET_64BIT"
8510 "*
8511 {
8512 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8513 }"
8514 [(set_attr "type" "dyncall")
8515 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8517 ;; This pattern is split if it is necessary to save and restore the
8518 ;; PIC register.
8519 (define_insn "call_val_reg_pic"
8520 [(set (match_operand 0 "" "")
8521 (call (mem:SI (reg:SI 22))
8522 (match_operand 1 "" "i")))
8523 (clobber (reg:SI 1))
8524 (clobber (reg:SI 2))
8525 (clobber (reg:SI 4))
8526 (use (reg:SI 19))
8527 (use (const_int 1))]
8528 "!TARGET_64BIT"
8529 "*
8530 {
8531 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8532 }"
8533 [(set_attr "type" "dyncall")
8534 (set (attr "length")
8535 (plus (symbol_ref "attr_length_indirect_call (insn)")
8536 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8538 ;; Split out the PIC register save and restore after reload. This is
8539 ;; done only if the function returns. As the split is done after reload,
8540 ;; there are some situations in which we unnecessarily save and restore
8541 ;; %r4. This happens when there is a single call and the PIC register
8542 ;; is "dead" after the call. This isn't easy to fix as the usage of
8543 ;; the PIC register isn't completely determined until the reload pass.
8544 (define_split
8545 [(parallel [(set (match_operand 0 "" "")
8546 (call (mem:SI (reg:SI 22))
8547 (match_operand 1 "" "")))
8548 (clobber (reg:SI 1))
8549 (clobber (reg:SI 2))
8550 (clobber (reg:SI 4))
8551 (use (reg:SI 19))
8552 (use (const_int 1))])]
8553 "!TARGET_64BIT
8554 && reload_completed
8555 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8556 [(set (reg:SI 4) (reg:SI 19))
8557 (parallel [(set (match_dup 0)
8558 (call (mem:SI (reg:SI 22))
8559 (match_dup 1)))
8560 (clobber (reg:SI 1))
8561 (clobber (reg:SI 2))
8562 (use (reg:SI 19))
8563 (use (const_int 1))])
8564 (set (reg:SI 19) (reg:SI 4))]
8565 "")
8567 ;; Remove the clobber of register 4 when optimizing. This has to be
8568 ;; done with a peephole optimization rather than a split because the
8569 ;; split sequence for a call must be longer than one instruction.
8570 (define_peephole2
8571 [(parallel [(set (match_operand 0 "" "")
8572 (call (mem:SI (reg:SI 22))
8573 (match_operand 1 "" "")))
8574 (clobber (reg:SI 1))
8575 (clobber (reg:SI 2))
8576 (clobber (reg:SI 4))
8577 (use (reg:SI 19))
8578 (use (const_int 1))])]
8579 "!TARGET_64BIT && reload_completed"
8580 [(parallel [(set (match_dup 0)
8581 (call (mem:SI (reg:SI 22))
8582 (match_dup 1)))
8583 (clobber (reg:SI 1))
8584 (clobber (reg:SI 2))
8585 (use (reg:SI 19))
8586 (use (const_int 1))])]
8587 "")
8589 (define_insn "*call_val_reg_pic_post_reload"
8590 [(set (match_operand 0 "" "")
8591 (call (mem:SI (reg:SI 22))
8592 (match_operand 1 "" "i")))
8593 (clobber (reg:SI 1))
8594 (clobber (reg:SI 2))
8595 (use (reg:SI 19))
8596 (use (const_int 1))]
8597 "!TARGET_64BIT"
8598 "*
8599 {
8600 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8601 }"
8602 [(set_attr "type" "dyncall")
8603 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8605 ;; This pattern is split if it is necessary to save and restore the
8606 ;; PIC register.
8607 (define_insn "call_val_reg_64bit"
8608 [(set (match_operand 0 "" "")
8609 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8610 (match_operand 2 "" "i")))
8611 (clobber (reg:DI 2))
8612 (clobber (reg:DI 4))
8613 (use (reg:DI 27))
8614 (use (reg:DI 29))
8615 (use (const_int 1))]
8616 "TARGET_64BIT"
8617 "*
8618 {
8619 return output_indirect_call (insn, operands[1]);
8620 }"
8621 [(set_attr "type" "dyncall")
8622 (set (attr "length")
8623 (plus (symbol_ref "attr_length_indirect_call (insn)")
8624 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8626 ;; Split out the PIC register save and restore after reload. This is
8627 ;; done only if the function returns. As the split is done after reload,
8628 ;; there are some situations in which we unnecessarily save and restore
8629 ;; %r4. This happens when there is a single call and the PIC register
8630 ;; is "dead" after the call. This isn't easy to fix as the usage of
8631 ;; the PIC register isn't completely determined until the reload pass.
8632 (define_split
8633 [(parallel [(set (match_operand 0 "" "")
8634 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8635 (match_operand 2 "" "")))
8636 (clobber (reg:DI 2))
8637 (clobber (reg:DI 4))
8638 (use (reg:DI 27))
8639 (use (reg:DI 29))
8640 (use (const_int 1))])]
8641 "TARGET_64BIT
8642 && reload_completed
8643 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8644 [(set (reg:DI 4) (reg:DI 27))
8645 (parallel [(set (match_dup 0)
8646 (call (mem:SI (match_dup 1))
8647 (match_dup 2)))
8648 (clobber (reg:DI 2))
8649 (use (reg:DI 27))
8650 (use (reg:DI 29))
8651 (use (const_int 1))])
8652 (set (reg:DI 27) (reg:DI 4))]
8653 "")
8655 ;; Remove the clobber of register 4 when optimizing. This has to be
8656 ;; done with a peephole optimization rather than a split because the
8657 ;; split sequence for a call must be longer than one instruction.
8658 (define_peephole2
8659 [(parallel [(set (match_operand 0 "" "")
8660 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8661 (match_operand 2 "" "")))
8662 (clobber (reg:DI 2))
8663 (clobber (reg:DI 4))
8664 (use (reg:DI 27))
8665 (use (reg:DI 29))
8666 (use (const_int 1))])]
8667 "TARGET_64BIT && reload_completed"
8668 [(parallel [(set (match_dup 0)
8669 (call (mem:SI (match_dup 1))
8670 (match_dup 2)))
8671 (clobber (reg:DI 2))
8672 (use (reg:DI 27))
8673 (use (reg:DI 29))
8674 (use (const_int 1))])]
8675 "")
8677 (define_insn "*call_val_reg_64bit_post_reload"
8678 [(set (match_operand 0 "" "")
8679 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8680 (match_operand 2 "" "i")))
8681 (clobber (reg:DI 2))
8682 (use (reg:DI 27))
8683 (use (reg:DI 29))
8684 (use (const_int 1))]
8685 "TARGET_64BIT"
8686 "*
8687 {
8688 return output_indirect_call (insn, operands[1]);
8689 }"
8690 [(set_attr "type" "dyncall")
8691 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8693 ;; Call subroutine returning any type.
8695 (define_expand "untyped_call"
8696 [(parallel [(call (match_operand 0 "" "")
8697 (const_int 0))
8698 (match_operand 1 "" "")
8699 (match_operand 2 "" "")])]
8700 ""
8701 "
8702 {
8703 int i;
8705 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
8707 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8708 {
8709 rtx set = XVECEXP (operands[2], 0, i);
8710 emit_move_insn (SET_DEST (set), SET_SRC (set));
8711 }
8713 /* The optimizer does not know that the call sets the function value
8714 registers we stored in the result block. We avoid problems by
8715 claiming that all hard registers are used and clobbered at this
8716 point. */
8717 emit_insn (gen_blockage ());
8719 DONE;
8720 }")
8722 (define_expand "sibcall"
8723 [(call (match_operand:SI 0 "" "")
8724 (match_operand 1 "" ""))]
8725 "!TARGET_PORTABLE_RUNTIME"
8726 "
8727 {
8728 rtx op, call_insn;
8729 rtx nb = operands[1];
8731 op = XEXP (operands[0], 0);
8733 if (TARGET_64BIT)
8734 {
8735 if (!virtuals_instantiated)
8736 emit_move_insn (arg_pointer_rtx,
8737 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8738 GEN_INT (64)));
8739 else
8740 {
8741 /* The loop pass can generate new libcalls after the virtual
8742 registers are instantiated when fpregs are disabled because
8743 the only method that we have for doing DImode multiplication
8744 is with a libcall. This could be trouble if we haven't
8745 allocated enough space for the outgoing arguments. */
8746 gcc_assert (INTVAL (nb) <= current_function_outgoing_args_size);
8748 emit_move_insn (arg_pointer_rtx,
8749 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8750 GEN_INT (STACK_POINTER_OFFSET + 64)));
8751 }
8752 }
8754 /* Indirect sibling calls are not allowed. */
8755 if (TARGET_64BIT)
8756 call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]);
8757 else
8758 call_insn = gen_sibcall_internal_symref (op, operands[1]);
8760 call_insn = emit_call_insn (call_insn);
8762 if (TARGET_64BIT)
8763 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8765 /* We don't have to restore the PIC register. */
8766 if (flag_pic)
8767 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8769 DONE;
8770 }")
8772 (define_insn "sibcall_internal_symref"
8773 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8774 (match_operand 1 "" "i"))
8775 (clobber (reg:SI 1))
8776 (use (reg:SI 2))
8777 (use (const_int 0))]
8778 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8779 "*
8780 {
8781 output_arg_descriptor (insn);
8782 return output_call (insn, operands[0], 1);
8783 }"
8784 [(set_attr "type" "call")
8785 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8787 (define_insn "sibcall_internal_symref_64bit"
8788 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8789 (match_operand 1 "" "i"))
8790 (clobber (reg:DI 1))
8791 (use (reg:DI 2))
8792 (use (const_int 0))]
8793 "TARGET_64BIT"
8794 "*
8795 {
8796 output_arg_descriptor (insn);
8797 return output_call (insn, operands[0], 1);
8798 }"
8799 [(set_attr "type" "call")
8800 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8802 (define_expand "sibcall_value"
8803 [(set (match_operand 0 "" "")
8804 (call (match_operand:SI 1 "" "")
8805 (match_operand 2 "" "")))]
8806 "!TARGET_PORTABLE_RUNTIME"
8807 "
8808 {
8809 rtx op, call_insn;
8810 rtx nb = operands[1];
8812 op = XEXP (operands[1], 0);
8814 if (TARGET_64BIT)
8815 {
8816 if (!virtuals_instantiated)
8817 emit_move_insn (arg_pointer_rtx,
8818 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8819 GEN_INT (64)));
8820 else
8821 {
8822 /* The loop pass can generate new libcalls after the virtual
8823 registers are instantiated when fpregs are disabled because
8824 the only method that we have for doing DImode multiplication
8825 is with a libcall. This could be trouble if we haven't
8826 allocated enough space for the outgoing arguments. */
8827 gcc_assert (INTVAL (nb) <= current_function_outgoing_args_size);
8829 emit_move_insn (arg_pointer_rtx,
8830 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8831 GEN_INT (STACK_POINTER_OFFSET + 64)));
8832 }
8833 }
8835 /* Indirect sibling calls are not allowed. */
8836 if (TARGET_64BIT)
8837 call_insn
8838 = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]);
8839 else
8840 call_insn
8841 = gen_sibcall_value_internal_symref (operands[0], op, operands[2]);
8843 call_insn = emit_call_insn (call_insn);
8845 if (TARGET_64BIT)
8846 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8848 /* We don't have to restore the PIC register. */
8849 if (flag_pic)
8850 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8852 DONE;
8853 }")
8855 (define_insn "sibcall_value_internal_symref"
8856 [(set (match_operand 0 "" "")
8857 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8858 (match_operand 2 "" "i")))
8859 (clobber (reg:SI 1))
8860 (use (reg:SI 2))
8861 (use (const_int 0))]
8862 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8863 "*
8864 {
8865 output_arg_descriptor (insn);
8866 return output_call (insn, operands[1], 1);
8867 }"
8868 [(set_attr "type" "call")
8869 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8871 (define_insn "sibcall_value_internal_symref_64bit"
8872 [(set (match_operand 0 "" "")
8873 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8874 (match_operand 2 "" "i")))
8875 (clobber (reg:DI 1))
8876 (use (reg:DI 2))
8877 (use (const_int 0))]
8878 "TARGET_64BIT"
8879 "*
8880 {
8881 output_arg_descriptor (insn);
8882 return output_call (insn, operands[1], 1);
8883 }"
8884 [(set_attr "type" "call")
8885 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8887 (define_insn "nop"
8888 [(const_int 0)]
8889 ""
8890 "nop"
8891 [(set_attr "type" "move")
8892 (set_attr "length" "4")])
8894 ;; These are just placeholders so we know where branch tables
8895 ;; begin and end.
8896 (define_insn "begin_brtab"
8897 [(const_int 1)]
8898 ""
8899 "*
8900 {
8901 /* Only GAS actually supports this pseudo-op. */
8902 if (TARGET_GAS)
8903 return \".begin_brtab\";
8904 else
8905 return \"\";
8906 }"
8907 [(set_attr "type" "move")
8908 (set_attr "length" "0")])
8910 (define_insn "end_brtab"
8911 [(const_int 2)]
8912 ""
8913 "*
8914 {
8915 /* Only GAS actually supports this pseudo-op. */
8916 if (TARGET_GAS)
8917 return \".end_brtab\";
8918 else
8919 return \"\";
8920 }"
8921 [(set_attr "type" "move")
8922 (set_attr "length" "0")])
8924 ;;; EH does longjmp's from and within the data section. Thus,
8925 ;;; an interspace branch is required for the longjmp implementation.
8926 ;;; Registers r1 and r2 are used as scratch registers for the jump
8927 ;;; when necessary.
8928 (define_expand "interspace_jump"
8929 [(parallel
8930 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8931 (clobber (match_dup 1))])]
8932 ""
8933 "
8934 {
8935 operands[1] = gen_rtx_REG (word_mode, 2);
8936 }")
8938 (define_insn ""
8939 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8940 (clobber (reg:SI 2))]
8941 "TARGET_PA_20 && !TARGET_64BIT"
8942 "bve%* (%0)"
8943 [(set_attr "type" "branch")
8944 (set_attr "length" "4")])
8946 (define_insn ""
8947 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8948 (clobber (reg:SI 2))]
8949 "TARGET_NO_SPACE_REGS && !TARGET_64BIT"
8950 "be%* 0(%%sr4,%0)"
8951 [(set_attr "type" "branch")
8952 (set_attr "length" "4")])
8954 (define_insn ""
8955 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8956 (clobber (reg:SI 2))]
8957 "!TARGET_64BIT"
8958 "ldsid (%%sr0,%0),%%r2\;mtsp %%r2,%%sr0\;be%* 0(%%sr0,%0)"
8959 [(set_attr "type" "branch")
8960 (set_attr "length" "12")])
8962 (define_insn ""
8963 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8964 (clobber (reg:DI 2))]
8965 "TARGET_64BIT"
8966 "bve%* (%0)"
8967 [(set_attr "type" "branch")
8968 (set_attr "length" "4")])
8970 (define_expand "builtin_longjmp"
8971 [(unspec_volatile [(match_operand 0 "register_operand" "r")] UNSPECV_LONGJMP)]
8972 ""
8973 "
8974 {
8975 /* The elements of the buffer are, in order: */
8976 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
8977 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8978 POINTER_SIZE / BITS_PER_UNIT));
8979 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8980 (POINTER_SIZE * 2) / BITS_PER_UNIT));
8981 rtx pv = gen_rtx_REG (Pmode, 1);
8983 emit_insn (gen_rtx_CLOBBER (VOIDmode,
8984 gen_rtx_MEM (BLKmode,
8985 gen_rtx_SCRATCH (VOIDmode))));
8986 emit_insn (gen_rtx_CLOBBER (VOIDmode,
8987 gen_rtx_MEM (BLKmode,
8988 hard_frame_pointer_rtx)));
8990 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
8991 instead of the hard_frame_pointer_rtx in the save area. We need
8992 to adjust for the offset between these two values when we have
8993 a nonlocal_goto pattern. When we don't have a nonlocal_goto
8994 pattern, the receiver performs the adjustment. */
8995 #ifdef HAVE_nonlocal_goto
8996 if (HAVE_nonlocal_goto)
8997 emit_move_insn (virtual_stack_vars_rtx, force_reg (Pmode, fp));
8998 else
8999 #endif
9000 emit_move_insn (hard_frame_pointer_rtx, fp);
9002 /* This bit is the same as expand_builtin_longjmp. */
9003 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
9004 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
9005 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
9007 /* Load the label we are jumping through into r1 so that we know
9008 where to look for it when we get back to setjmp's function for
9009 restoring the gp. */
9010 emit_move_insn (pv, lab);
9012 /* Prevent the insns above from being scheduled into the delay slot
9013 of the interspace jump because the space register could change. */
9014 emit_insn (gen_blockage ());
9016 emit_jump_insn (gen_interspace_jump (pv));
9017 emit_barrier ();
9018 DONE;
9019 }")
9021 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
9022 (define_expand "extzv"
9023 [(set (match_operand 0 "register_operand" "")
9024 (zero_extract (match_operand 1 "register_operand" "")
9025 (match_operand 2 "uint32_operand" "")
9026 (match_operand 3 "uint32_operand" "")))]
9027 ""
9028 "
9029 {
9030 HOST_WIDE_INT len = INTVAL (operands[2]);
9031 HOST_WIDE_INT pos = INTVAL (operands[3]);
9033 /* PA extraction insns don't support zero length bitfields or fields
9034 extending beyond the left or right-most bits. Also, we reject lengths
9035 equal to a word as they are better handled by the move patterns. */
9036 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
9037 FAIL;
9039 /* From mips.md: extract_bit_field doesn't verify that our source
9040 matches the predicate, so check it again here. */
9041 if (!register_operand (operands[1], VOIDmode))
9042 FAIL;
9044 if (TARGET_64BIT)
9045 emit_insn (gen_extzv_64 (operands[0], operands[1],
9046 operands[2], operands[3]));
9047 else
9048 emit_insn (gen_extzv_32 (operands[0], operands[1],
9049 operands[2], operands[3]));
9050 DONE;
9051 }")
9053 (define_insn "extzv_32"
9054 [(set (match_operand:SI 0 "register_operand" "=r")
9055 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
9056 (match_operand:SI 2 "uint5_operand" "")
9057 (match_operand:SI 3 "uint5_operand" "")))]
9058 ""
9059 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
9060 [(set_attr "type" "shift")
9061 (set_attr "length" "4")])
9063 (define_insn ""
9064 [(set (match_operand:SI 0 "register_operand" "=r")
9065 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
9066 (const_int 1)
9067 (match_operand:SI 2 "register_operand" "q")))]
9068 ""
9069 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
9070 [(set_attr "type" "shift")
9071 (set_attr "length" "4")])
9073 (define_insn "extzv_64"
9074 [(set (match_operand:DI 0 "register_operand" "=r")
9075 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
9076 (match_operand:DI 2 "uint32_operand" "")
9077 (match_operand:DI 3 "uint32_operand" "")))]
9078 "TARGET_64BIT"
9079 "extrd,u %1,%3+%2-1,%2,%0"
9080 [(set_attr "type" "shift")
9081 (set_attr "length" "4")])
9083 (define_insn ""
9084 [(set (match_operand:DI 0 "register_operand" "=r")
9085 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
9086 (const_int 1)
9087 (match_operand:DI 2 "register_operand" "q")))]
9088 "TARGET_64BIT"
9089 "extrd,u %1,%%sar,1,%0"
9090 [(set_attr "type" "shift")
9091 (set_attr "length" "4")])
9093 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
9094 (define_expand "extv"
9095 [(set (match_operand 0 "register_operand" "")
9096 (sign_extract (match_operand 1 "register_operand" "")
9097 (match_operand 2 "uint32_operand" "")
9098 (match_operand 3 "uint32_operand" "")))]
9099 ""
9100 "
9101 {
9102 HOST_WIDE_INT len = INTVAL (operands[2]);
9103 HOST_WIDE_INT pos = INTVAL (operands[3]);
9105 /* PA extraction insns don't support zero length bitfields or fields
9106 extending beyond the left or right-most bits. Also, we reject lengths
9107 equal to a word as they are better handled by the move patterns. */
9108 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
9109 FAIL;
9111 /* From mips.md: extract_bit_field doesn't verify that our source
9112 matches the predicate, so check it again here. */
9113 if (!register_operand (operands[1], VOIDmode))
9114 FAIL;
9116 if (TARGET_64BIT)
9117 emit_insn (gen_extv_64 (operands[0], operands[1],
9118 operands[2], operands[3]));
9119 else
9120 emit_insn (gen_extv_32 (operands[0], operands[1],
9121 operands[2], operands[3]));
9122 DONE;
9123 }")
9125 (define_insn "extv_32"
9126 [(set (match_operand:SI 0 "register_operand" "=r")
9127 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
9128 (match_operand:SI 2 "uint5_operand" "")
9129 (match_operand:SI 3 "uint5_operand" "")))]
9130 ""
9131 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
9132 [(set_attr "type" "shift")
9133 (set_attr "length" "4")])
9135 (define_insn ""
9136 [(set (match_operand:SI 0 "register_operand" "=r")
9137 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
9138 (const_int 1)
9139 (match_operand:SI 2 "register_operand" "q")))]
9140 "!TARGET_64BIT"
9141 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
9142 [(set_attr "type" "shift")
9143 (set_attr "length" "4")])
9145 (define_insn "extv_64"
9146 [(set (match_operand:DI 0 "register_operand" "=r")
9147 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
9148 (match_operand:DI 2 "uint32_operand" "")
9149 (match_operand:DI 3 "uint32_operand" "")))]
9150 "TARGET_64BIT"
9151 "extrd,s %1,%3+%2-1,%2,%0"
9152 [(set_attr "type" "shift")
9153 (set_attr "length" "4")])
9155 (define_insn ""
9156 [(set (match_operand:DI 0 "register_operand" "=r")
9157 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
9158 (const_int 1)
9159 (match_operand:DI 2 "register_operand" "q")))]
9160 "TARGET_64BIT"
9161 "extrd,s %1,%%sar,1,%0"
9162 [(set_attr "type" "shift")
9163 (set_attr "length" "4")])
9165 ;;; Operands 1 and 2 are assumed to be CONST_INTs.
9166 (define_expand "insv"
9167 [(set (zero_extract (match_operand 0 "register_operand" "")
9168 (match_operand 1 "uint32_operand" "")
9169 (match_operand 2 "uint32_operand" ""))
9170 (match_operand 3 "arith5_operand" ""))]
9171 ""
9172 "
9173 {
9174 HOST_WIDE_INT len = INTVAL (operands[1]);
9175 HOST_WIDE_INT pos = INTVAL (operands[2]);
9177 /* PA insertion insns don't support zero length bitfields or fields
9178 extending beyond the left or right-most bits. Also, we reject lengths
9179 equal to a word as they are better handled by the move patterns. */
9180 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
9181 FAIL;
9183 /* From mips.md: insert_bit_field doesn't verify that our destination
9184 matches the predicate, so check it again here. */
9185 if (!register_operand (operands[0], VOIDmode))
9186 FAIL;
9188 if (TARGET_64BIT)
9189 emit_insn (gen_insv_64 (operands[0], operands[1],
9190 operands[2], operands[3]));
9191 else
9192 emit_insn (gen_insv_32 (operands[0], operands[1],
9193 operands[2], operands[3]));
9194 DONE;
9195 }")
9197 (define_insn "insv_32"
9198 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
9199 (match_operand:SI 1 "uint5_operand" "")
9200 (match_operand:SI 2 "uint5_operand" ""))
9201 (match_operand:SI 3 "arith5_operand" "r,L"))]
9202 ""
9203 "@
9204 {dep|depw} %3,%2+%1-1,%1,%0
9205 {depi|depwi} %3,%2+%1-1,%1,%0"
9206 [(set_attr "type" "shift,shift")
9207 (set_attr "length" "4,4")])
9209 ;; Optimize insertion of const_int values of type 1...1xxxx.
9210 (define_insn ""
9211 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
9212 (match_operand:SI 1 "uint5_operand" "")
9213 (match_operand:SI 2 "uint5_operand" ""))
9214 (match_operand:SI 3 "const_int_operand" ""))]
9215 "(INTVAL (operands[3]) & 0x10) != 0 &&
9216 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
9217 "*
9218 {
9219 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
9220 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
9221 }"
9222 [(set_attr "type" "shift")
9223 (set_attr "length" "4")])
9225 (define_insn "insv_64"
9226 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
9227 (match_operand:DI 1 "uint32_operand" "")
9228 (match_operand:DI 2 "uint32_operand" ""))
9229 (match_operand:DI 3 "arith32_operand" "r,L"))]
9230 "TARGET_64BIT"
9231 "@
9232 depd %3,%2+%1-1,%1,%0
9233 depdi %3,%2+%1-1,%1,%0"
9234 [(set_attr "type" "shift,shift")
9235 (set_attr "length" "4,4")])
9237 ;; Optimize insertion of const_int values of type 1...1xxxx.
9238 (define_insn ""
9239 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
9240 (match_operand:DI 1 "uint32_operand" "")
9241 (match_operand:DI 2 "uint32_operand" ""))
9242 (match_operand:DI 3 "const_int_operand" ""))]
9243 "(INTVAL (operands[3]) & 0x10) != 0
9244 && TARGET_64BIT
9245 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
9246 "*
9247 {
9248 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
9249 return \"depdi %3,%2+%1-1,%1,%0\";
9250 }"
9251 [(set_attr "type" "shift")
9252 (set_attr "length" "4")])
9254 (define_insn ""
9255 [(set (match_operand:DI 0 "register_operand" "=r")
9256 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
9257 (const_int 32)))]
9258 "TARGET_64BIT"
9259 "depd,z %1,31,32,%0"
9260 [(set_attr "type" "shift")
9261 (set_attr "length" "4")])
9263 ;; This insn is used for some loop tests, typically loops reversed when
9264 ;; strength reduction is used. It is actually created when the instruction
9265 ;; combination phase combines the special loop test. Since this insn
9266 ;; is both a jump insn and has an output, it must deal with its own
9267 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
9268 ;; to not choose the register alternatives in the event a reload is needed.
9269 (define_insn "decrement_and_branch_until_zero"
9270 [(set (pc)
9271 (if_then_else
9272 (match_operator 2 "comparison_operator"
9273 [(plus:SI
9274 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m")
9275 (match_operand:SI 1 "int5_operand" "L,L,L"))
9276 (const_int 0)])
9277 (label_ref (match_operand 3 "" ""))
9278 (pc)))
9279 (set (match_dup 0)
9280 (plus:SI (match_dup 0) (match_dup 1)))
9281 (clobber (match_scratch:SI 4 "=X,r,r"))]
9282 ""
9283 "* return output_dbra (operands, insn, which_alternative); "
9284 ;; Do not expect to understand this the first time through.
9285 [(set_attr "type" "cbranch,multi,multi")
9286 (set (attr "length")
9287 (if_then_else (eq_attr "alternative" "0")
9288 ;; Loop counter in register case
9289 ;; Short branch has length of 4
9290 ;; Long branch has length of 8, 20, 24 or 28
9291 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9292 (const_int MAX_12BIT_OFFSET))
9293 (const_int 4)
9294 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9295 (const_int MAX_17BIT_OFFSET))
9296 (const_int 8)
9297 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9298 (const_int 24)
9299 (eq (symbol_ref "flag_pic") (const_int 0))
9300 (const_int 20)]
9301 (const_int 28))
9303 ;; Loop counter in FP reg case.
9304 ;; Extra goo to deal with additional reload insns.
9305 (if_then_else (eq_attr "alternative" "1")
9306 (if_then_else (lt (match_dup 3) (pc))
9307 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
9308 (const_int MAX_12BIT_OFFSET))
9309 (const_int 24)
9310 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
9311 (const_int MAX_17BIT_OFFSET))
9312 (const_int 28)
9313 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9314 (const_int 44)
9315 (eq (symbol_ref "flag_pic") (const_int 0))
9316 (const_int 40)]
9317 (const_int 48))
9318 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9319 (const_int MAX_12BIT_OFFSET))
9320 (const_int 24)
9321 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9322 (const_int MAX_17BIT_OFFSET))
9323 (const_int 28)
9324 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9325 (const_int 44)
9326 (eq (symbol_ref "flag_pic") (const_int 0))
9327 (const_int 40)]
9328 (const_int 48)))
9330 ;; Loop counter in memory case.
9331 ;; Extra goo to deal with additional reload insns.
9332 (if_then_else (lt (match_dup 3) (pc))
9333 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9334 (const_int MAX_12BIT_OFFSET))
9335 (const_int 12)
9336 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9337 (const_int MAX_17BIT_OFFSET))
9338 (const_int 16)
9339 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9340 (const_int 32)
9341 (eq (symbol_ref "flag_pic") (const_int 0))
9342 (const_int 28)]
9343 (const_int 36))
9344 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9345 (const_int MAX_12BIT_OFFSET))
9346 (const_int 12)
9347 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9348 (const_int MAX_17BIT_OFFSET))
9349 (const_int 16)
9350 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9351 (const_int 32)
9352 (eq (symbol_ref "flag_pic") (const_int 0))
9353 (const_int 28)]
9354 (const_int 36))))))])
9356 (define_insn ""
9357 [(set (pc)
9358 (if_then_else
9359 (match_operator 2 "movb_comparison_operator"
9360 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
9361 (label_ref (match_operand 3 "" ""))
9362 (pc)))
9363 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
9364 (match_dup 1))]
9365 ""
9366 "* return output_movb (operands, insn, which_alternative, 0); "
9367 ;; Do not expect to understand this the first time through.
9368 [(set_attr "type" "cbranch,multi,multi,multi")
9369 (set (attr "length")
9370 (if_then_else (eq_attr "alternative" "0")
9371 ;; Loop counter in register case
9372 ;; Short branch has length of 4
9373 ;; Long branch has length of 8, 20, 24 or 28
9374 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9375 (const_int MAX_12BIT_OFFSET))
9376 (const_int 4)
9377 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9378 (const_int MAX_17BIT_OFFSET))
9379 (const_int 8)
9380 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9381 (const_int 24)
9382 (eq (symbol_ref "flag_pic") (const_int 0))
9383 (const_int 20)]
9384 (const_int 28))
9386 ;; Loop counter in FP reg case.
9387 ;; Extra goo to deal with additional reload insns.
9388 (if_then_else (eq_attr "alternative" "1")
9389 (if_then_else (lt (match_dup 3) (pc))
9390 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9391 (const_int MAX_12BIT_OFFSET))
9392 (const_int 12)
9393 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9394 (const_int MAX_17BIT_OFFSET))
9395 (const_int 16)
9396 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9397 (const_int 32)
9398 (eq (symbol_ref "flag_pic") (const_int 0))
9399 (const_int 28)]
9400 (const_int 36))
9401 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9402 (const_int MAX_12BIT_OFFSET))
9403 (const_int 12)
9404 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9405 (const_int MAX_17BIT_OFFSET))
9406 (const_int 16)
9407 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9408 (const_int 32)
9409 (eq (symbol_ref "flag_pic") (const_int 0))
9410 (const_int 28)]
9411 (const_int 36)))
9413 ;; Loop counter in memory or sar case.
9414 ;; Extra goo to deal with additional reload insns.
9415 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9416 (const_int MAX_12BIT_OFFSET))
9417 (const_int 8)
9418 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9419 (const_int MAX_17BIT_OFFSET))
9420 (const_int 12)
9421 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9422 (const_int 28)
9423 (eq (symbol_ref "flag_pic") (const_int 0))
9424 (const_int 24)]
9425 (const_int 32)))))])
9427 ;; Handle negated branch.
9428 (define_insn ""
9429 [(set (pc)
9430 (if_then_else
9431 (match_operator 2 "movb_comparison_operator"
9432 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
9433 (pc)
9434 (label_ref (match_operand 3 "" ""))))
9435 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
9436 (match_dup 1))]
9437 ""
9438 "* return output_movb (operands, insn, which_alternative, 1); "
9439 ;; Do not expect to understand this the first time through.
9440 [(set_attr "type" "cbranch,multi,multi,multi")
9441 (set (attr "length")
9442 (if_then_else (eq_attr "alternative" "0")
9443 ;; Loop counter in register case
9444 ;; Short branch has length of 4
9445 ;; Long branch has length of 8
9446 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9447 (const_int MAX_12BIT_OFFSET))
9448 (const_int 4)
9449 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9450 (const_int MAX_17BIT_OFFSET))
9451 (const_int 8)
9452 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9453 (const_int 24)
9454 (eq (symbol_ref "flag_pic") (const_int 0))
9455 (const_int 20)]
9456 (const_int 28))
9458 ;; Loop counter in FP reg case.
9459 ;; Extra goo to deal with additional reload insns.
9460 (if_then_else (eq_attr "alternative" "1")
9461 (if_then_else (lt (match_dup 3) (pc))
9462 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9463 (const_int MAX_12BIT_OFFSET))
9464 (const_int 12)
9465 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9466 (const_int MAX_17BIT_OFFSET))
9467 (const_int 16)
9468 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9469 (const_int 32)
9470 (eq (symbol_ref "flag_pic") (const_int 0))
9471 (const_int 28)]
9472 (const_int 36))
9473 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9474 (const_int MAX_12BIT_OFFSET))
9475 (const_int 12)
9476 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9477 (const_int MAX_17BIT_OFFSET))
9478 (const_int 16)
9479 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9480 (const_int 32)
9481 (eq (symbol_ref "flag_pic") (const_int 0))
9482 (const_int 28)]
9483 (const_int 36)))
9485 ;; Loop counter in memory or SAR case.
9486 ;; Extra goo to deal with additional reload insns.
9487 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9488 (const_int MAX_12BIT_OFFSET))
9489 (const_int 8)
9490 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9491 (const_int MAX_17BIT_OFFSET))
9492 (const_int 12)
9493 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9494 (const_int 28)
9495 (eq (symbol_ref "flag_pic") (const_int 0))
9496 (const_int 24)]
9497 (const_int 32)))))])
9499 (define_insn ""
9500 [(set (pc) (label_ref (match_operand 3 "" "" )))
9501 (set (match_operand:SI 0 "ireg_operand" "=r")
9502 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
9503 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
9504 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
9505 "*
9506 {
9507 return output_parallel_addb (operands, insn);
9508 }"
9509 [(set_attr "type" "parallel_branch")
9510 (set (attr "length")
9511 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9512 (const_int MAX_12BIT_OFFSET))
9513 (const_int 4)
9514 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9515 (const_int MAX_17BIT_OFFSET))
9516 (const_int 8)
9517 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9518 (const_int 24)
9519 (eq (symbol_ref "flag_pic") (const_int 0))
9520 (const_int 20)]
9521 (const_int 28)))])
9523 (define_insn ""
9524 [(set (pc) (label_ref (match_operand 2 "" "" )))
9525 (set (match_operand:SF 0 "ireg_operand" "=r")
9526 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
9527 "reload_completed"
9528 "*
9529 {
9530 return output_parallel_movb (operands, insn);
9531 }"
9532 [(set_attr "type" "parallel_branch")
9533 (set (attr "length")
9534 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9535 (const_int MAX_12BIT_OFFSET))
9536 (const_int 4)
9537 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9538 (const_int MAX_17BIT_OFFSET))
9539 (const_int 8)
9540 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9541 (const_int 24)
9542 (eq (symbol_ref "flag_pic") (const_int 0))
9543 (const_int 20)]
9544 (const_int 28)))])
9546 (define_insn ""
9547 [(set (pc) (label_ref (match_operand 2 "" "" )))
9548 (set (match_operand:SI 0 "ireg_operand" "=r")
9549 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
9550 "reload_completed"
9551 "*
9552 {
9553 return output_parallel_movb (operands, insn);
9554 }"
9555 [(set_attr "type" "parallel_branch")
9556 (set (attr "length")
9557 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9558 (const_int MAX_12BIT_OFFSET))
9559 (const_int 4)
9560 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9561 (const_int MAX_17BIT_OFFSET))
9562 (const_int 8)
9563 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9564 (const_int 24)
9565 (eq (symbol_ref "flag_pic") (const_int 0))
9566 (const_int 20)]
9567 (const_int 28)))])
9569 (define_insn ""
9570 [(set (pc) (label_ref (match_operand 2 "" "" )))
9571 (set (match_operand:HI 0 "ireg_operand" "=r")
9572 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
9573 "reload_completed"
9574 "*
9575 {
9576 return output_parallel_movb (operands, insn);
9577 }"
9578 [(set_attr "type" "parallel_branch")
9579 (set (attr "length")
9580 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9581 (const_int MAX_12BIT_OFFSET))
9582 (const_int 4)
9583 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9584 (const_int MAX_17BIT_OFFSET))
9585 (const_int 8)
9586 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9587 (const_int 24)
9588 (eq (symbol_ref "flag_pic") (const_int 0))
9589 (const_int 20)]
9590 (const_int 28)))])
9592 (define_insn ""
9593 [(set (pc) (label_ref (match_operand 2 "" "" )))
9594 (set (match_operand:QI 0 "ireg_operand" "=r")
9595 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
9596 "reload_completed"
9597 "*
9598 {
9599 return output_parallel_movb (operands, insn);
9600 }"
9601 [(set_attr "type" "parallel_branch")
9602 (set (attr "length")
9603 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9604 (const_int MAX_12BIT_OFFSET))
9605 (const_int 4)
9606 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9607 (const_int MAX_17BIT_OFFSET))
9608 (const_int 8)
9609 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9610 (const_int 24)
9611 (eq (symbol_ref "flag_pic") (const_int 0))
9612 (const_int 20)]
9613 (const_int 28)))])
9615 (define_insn ""
9616 [(set (match_operand 0 "register_operand" "=f")
9617 (mult (match_operand 1 "register_operand" "f")
9618 (match_operand 2 "register_operand" "f")))
9619 (set (match_operand 3 "register_operand" "+f")
9620 (plus (match_operand 4 "register_operand" "f")
9621 (match_operand 5 "register_operand" "f")))]
9622 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9623 && reload_completed && fmpyaddoperands (operands)"
9624 "*
9625 {
9626 if (GET_MODE (operands[0]) == DFmode)
9627 {
9628 if (rtx_equal_p (operands[3], operands[5]))
9629 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
9630 else
9631 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
9632 }
9633 else
9634 {
9635 if (rtx_equal_p (operands[3], operands[5]))
9636 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
9637 else
9638 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
9639 }
9640 }"
9641 [(set_attr "type" "fpalu")
9642 (set_attr "length" "4")])
9644 (define_insn ""
9645 [(set (match_operand 3 "register_operand" "+f")
9646 (plus (match_operand 4 "register_operand" "f")
9647 (match_operand 5 "register_operand" "f")))
9648 (set (match_operand 0 "register_operand" "=f")
9649 (mult (match_operand 1 "register_operand" "f")
9650 (match_operand 2 "register_operand" "f")))]
9651 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9652 && reload_completed && fmpyaddoperands (operands)"
9653 "*
9654 {
9655 if (GET_MODE (operands[0]) == DFmode)
9656 {
9657 if (rtx_equal_p (operands[3], operands[5]))
9658 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
9659 else
9660 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
9661 }
9662 else
9663 {
9664 if (rtx_equal_p (operands[3], operands[5]))
9665 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
9666 else
9667 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
9668 }
9669 }"
9670 [(set_attr "type" "fpalu")
9671 (set_attr "length" "4")])
9673 (define_insn ""
9674 [(set (match_operand 0 "register_operand" "=f")
9675 (mult (match_operand 1 "register_operand" "f")
9676 (match_operand 2 "register_operand" "f")))
9677 (set (match_operand 3 "register_operand" "+f")
9678 (minus (match_operand 4 "register_operand" "f")
9679 (match_operand 5 "register_operand" "f")))]
9680 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9681 && reload_completed && fmpysuboperands (operands)"
9682 "*
9683 {
9684 if (GET_MODE (operands[0]) == DFmode)
9685 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9686 else
9687 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9688 }"
9689 [(set_attr "type" "fpalu")
9690 (set_attr "length" "4")])
9692 (define_insn ""
9693 [(set (match_operand 3 "register_operand" "+f")
9694 (minus (match_operand 4 "register_operand" "f")
9695 (match_operand 5 "register_operand" "f")))
9696 (set (match_operand 0 "register_operand" "=f")
9697 (mult (match_operand 1 "register_operand" "f")
9698 (match_operand 2 "register_operand" "f")))]
9699 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9700 && reload_completed && fmpysuboperands (operands)"
9701 "*
9702 {
9703 if (GET_MODE (operands[0]) == DFmode)
9704 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9705 else
9706 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9707 }"
9708 [(set_attr "type" "fpalu")
9709 (set_attr "length" "4")])
9711 ;; Flush the I and D cache lines from the start address (operand0)
9712 ;; to the end address (operand1). No lines are flushed if the end
9713 ;; address is less than the start address (unsigned).
9714 ;;
9715 ;; Because the range of memory flushed is variable and the size of
9716 ;; a MEM can only be a CONST_INT, the patterns specify that they
9717 ;; perform an unspecified volatile operation on all memory.
9718 ;;
9719 ;; The address range for an icache flush must lie within a single
9720 ;; space on targets with non-equivalent space registers.
9721 ;;
9722 ;; This is used by the trampoline code for nested functions.
9723 ;;
9724 ;; Operand 0 contains the start address.
9725 ;; Operand 1 contains the end address.
9726 ;; Operand 2 contains the line length to use.
9727 ;; Operands 3 and 4 (icacheflush) are clobbered scratch registers.
9728 (define_insn "dcacheflush"
9729 [(const_int 1)
9730 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_DCACHE)
9731 (use (match_operand 0 "pmode_register_operand" "r"))
9732 (use (match_operand 1 "pmode_register_operand" "r"))
9733 (use (match_operand 2 "pmode_register_operand" "r"))
9734 (clobber (match_scratch 3 "=&0"))]
9735 ""
9736 "*
9737 {
9738 if (TARGET_64BIT)
9739 return \"cmpb,*<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
9740 else
9741 return \"cmpb,<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
9742 }"
9743 [(set_attr "type" "multi")
9744 (set_attr "length" "12")])
9746 (define_insn "icacheflush"
9747 [(const_int 2)
9748 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
9749 (use (match_operand 0 "pmode_register_operand" "r"))
9750 (use (match_operand 1 "pmode_register_operand" "r"))
9751 (use (match_operand 2 "pmode_register_operand" "r"))
9752 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
9753 (clobber (match_operand 4 "pmode_register_operand" "=&r"))
9754 (clobber (match_scratch 5 "=&0"))]
9755 ""
9756 "*
9757 {
9758 if (TARGET_64BIT)
9759 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,*<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
9760 else
9761 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
9762 }"
9763 [(set_attr "type" "multi")
9764 (set_attr "length" "52")])
9766 ;; An out-of-line prologue.
9767 (define_insn "outline_prologue_call"
9768 [(unspec_volatile [(const_int 0)] UNSPECV_OPC)
9769 (clobber (reg:SI 31))
9770 (clobber (reg:SI 22))
9771 (clobber (reg:SI 21))
9772 (clobber (reg:SI 20))
9773 (clobber (reg:SI 19))
9774 (clobber (reg:SI 1))]
9775 ""
9776 "*
9777 {
9778 extern int frame_pointer_needed;
9780 /* We need two different versions depending on whether or not we
9781 need a frame pointer. Also note that we return to the instruction
9782 immediately after the branch rather than two instructions after the
9783 break as normally is the case. */
9784 if (frame_pointer_needed)
9785 {
9786 /* Must import the magic millicode routine(s). */
9787 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
9789 if (TARGET_PORTABLE_RUNTIME)
9790 {
9791 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
9792 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
9793 NULL);
9794 }
9795 else
9796 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
9797 }
9798 else
9799 {
9800 /* Must import the magic millicode routine(s). */
9801 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
9803 if (TARGET_PORTABLE_RUNTIME)
9804 {
9805 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
9806 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
9807 }
9808 else
9809 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
9810 }
9811 return \"\";
9812 }"
9813 [(set_attr "type" "multi")
9814 (set_attr "length" "8")])
9816 ;; An out-of-line epilogue.
9817 (define_insn "outline_epilogue_call"
9818 [(unspec_volatile [(const_int 1)] UNSPECV_OEC)
9819 (use (reg:SI 29))
9820 (use (reg:SI 28))
9821 (clobber (reg:SI 31))
9822 (clobber (reg:SI 22))
9823 (clobber (reg:SI 21))
9824 (clobber (reg:SI 20))
9825 (clobber (reg:SI 19))
9826 (clobber (reg:SI 2))
9827 (clobber (reg:SI 1))]
9828 ""
9829 "*
9830 {
9831 extern int frame_pointer_needed;
9833 /* We need two different versions depending on whether or not we
9834 need a frame pointer. Also note that we return to the instruction
9835 immediately after the branch rather than two instructions after the
9836 break as normally is the case. */
9837 if (frame_pointer_needed)
9838 {
9839 /* Must import the magic millicode routine. */
9840 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
9842 /* The out-of-line prologue will make sure we return to the right
9843 instruction. */
9844 if (TARGET_PORTABLE_RUNTIME)
9845 {
9846 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
9847 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
9848 NULL);
9849 }
9850 else
9851 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
9852 }
9853 else
9854 {
9855 /* Must import the magic millicode routine. */
9856 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
9858 /* The out-of-line prologue will make sure we return to the right
9859 instruction. */
9860 if (TARGET_PORTABLE_RUNTIME)
9861 {
9862 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
9863 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
9864 }
9865 else
9866 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
9867 }
9868 return \"\";
9869 }"
9870 [(set_attr "type" "multi")
9871 (set_attr "length" "8")])
9873 ;; Given a function pointer, canonicalize it so it can be
9874 ;; reliably compared to another function pointer. */
9875 (define_expand "canonicalize_funcptr_for_compare"
9876 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
9877 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9878 (clobber (match_dup 2))
9879 (clobber (reg:SI 26))
9880 (clobber (reg:SI 22))
9881 (clobber (reg:SI 31))])
9882 (set (match_operand:SI 0 "register_operand" "")
9883 (reg:SI 29))]
9884 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
9885 "
9886 {
9887 if (TARGET_ELF32)
9888 {
9889 rtx canonicalize_funcptr_for_compare_libfunc
9890 = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL);
9892 emit_library_call_value (canonicalize_funcptr_for_compare_libfunc,
9893 operands[0], LCT_NORMAL, Pmode,
9894 1, operands[1], Pmode);
9895 DONE;
9896 }
9898 operands[2] = gen_reg_rtx (SImode);
9899 if (GET_CODE (operands[1]) != REG)
9900 {
9901 rtx tmp = gen_reg_rtx (Pmode);
9902 emit_move_insn (tmp, operands[1]);
9903 operands[1] = tmp;
9904 }
9905 }")
9907 (define_insn "*$$sh_func_adrs"
9908 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9909 (clobber (match_operand:SI 0 "register_operand" "=a"))
9910 (clobber (reg:SI 26))
9911 (clobber (reg:SI 22))
9912 (clobber (reg:SI 31))]
9913 "!TARGET_64BIT"
9914 "*
9915 {
9916 int length = get_attr_length (insn);
9917 rtx xoperands[2];
9919 xoperands[0] = GEN_INT (length - 8);
9920 xoperands[1] = GEN_INT (length - 16);
9922 /* Must import the magic millicode routine. */
9923 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
9925 /* This is absolutely amazing.
9927 First, copy our input parameter into %r29 just in case we don't
9928 need to call $$sh_func_adrs. */
9929 output_asm_insn (\"copy %%r26,%%r29\", NULL);
9930 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL);
9932 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
9933 we use %r26 unchanged. */
9934 output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands);
9935 output_asm_insn (\"ldi 4096,%%r31\", NULL);
9937 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
9938 4096, then again we use %r26 unchanged. */
9939 output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
9941 /* Finally, call $$sh_func_adrs to extract the function's real add24. */
9942 return output_millicode_call (insn,
9943 gen_rtx_SYMBOL_REF (SImode,
9944 \"$$sh_func_adrs\"));
9945 }"
9946 [(set_attr "type" "multi")
9947 (set (attr "length")
9948 (plus (symbol_ref "attr_length_millicode_call (insn)")
9949 (const_int 20)))])
9951 ;; On the PA, the PIC register is call clobbered, so it must
9952 ;; be saved & restored around calls by the caller. If the call
9953 ;; doesn't return normally (nonlocal goto, or an exception is
9954 ;; thrown), then the code at the exception handler label must
9955 ;; restore the PIC register.
9956 (define_expand "exception_receiver"
9957 [(const_int 4)]
9958 "flag_pic"
9959 "
9960 {
9961 /* On the 64-bit port, we need a blockage because there is
9962 confusion regarding the dependence of the restore on the
9963 frame pointer. As a result, the frame pointer and pic
9964 register restores sometimes are interchanged erroneously. */
9965 if (TARGET_64BIT)
9966 emit_insn (gen_blockage ());
9967 /* Restore the PIC register using hppa_pic_save_rtx (). The
9968 PIC register is not saved in the frame in 64-bit ABI. */
9969 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9970 emit_insn (gen_blockage ());
9971 DONE;
9972 }")
9974 (define_expand "builtin_setjmp_receiver"
9975 [(label_ref (match_operand 0 "" ""))]
9976 "flag_pic"
9977 "
9978 {
9979 if (TARGET_64BIT)
9980 emit_insn (gen_blockage ());
9981 /* Restore the PIC register. Hopefully, this will always be from
9982 a stack slot. The only registers that are valid after a
9983 builtin_longjmp are the stack and frame pointers. */
9984 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9985 emit_insn (gen_blockage ());
9986 DONE;
9987 }")
9989 ;; Allocate new stack space and update the saved stack pointer in the
9990 ;; frame marker. The HP C compilers also copy additional words in the
9991 ;; frame marker. The 64-bit compiler copies words at -48, -32 and -24.
9992 ;; The 32-bit compiler copies the word at -16 (Static Link). We
9993 ;; currently don't copy these values.
9994 ;;
9995 ;; Since the copy of the frame marker can't be done atomically, I
9996 ;; suspect that using it for unwind purposes may be somewhat unreliable.
9997 ;; The HP compilers appear to raise the stack and copy the frame
9998 ;; marker in a strict instruction sequence. This suggests that the
9999 ;; unwind library may check for an alloca sequence when ALLOCA_FRAME
10000 ;; is set in the callinfo data. We currently don't set ALLOCA_FRAME
10001 ;; as GAS doesn't support it, or try to keep the instructions emitted
10002 ;; here in strict sequence.
10003 (define_expand "allocate_stack"
10004 [(match_operand 0 "" "")
10005 (match_operand 1 "" "")]
10006 ""
10007 "
10008 {
10009 rtx addr;
10011 /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx
10012 in operand 0 before adjusting the stack. */
10013 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10014 anti_adjust_stack (operands[1]);
10015 if (TARGET_HPUX_UNWIND_LIBRARY)
10016 {
10017 addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
10018 GEN_INT (TARGET_64BIT ? -8 : -4));
10019 emit_move_insn (gen_rtx_MEM (word_mode, addr), frame_pointer_rtx);
10020 }
10021 if (!TARGET_64BIT && flag_pic)
10022 {
10023 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
10024 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
10025 }
10026 DONE;
10027 }")
10029 (define_expand "prefetch"
10030 [(match_operand 0 "address_operand" "")
10031 (match_operand 1 "const_int_operand" "")
10032 (match_operand 2 "const_int_operand" "")]
10033 "TARGET_PA_20"
10034 {
10035 int locality = INTVAL (operands[2]);
10037 gcc_assert (locality >= 0 && locality <= 3);
10039 /* Change operand[0] to a MEM as we don't have the infrastructure
10040 to output all the supported address modes for ldw/ldd when we use
10041 the address directly. However, we do have it for MEMs. */
10042 operands[0] = gen_rtx_MEM (QImode, operands[0]);
10044 /* If the address isn't valid for the prefetch, replace it. */
10045 if (locality)
10046 {
10047 if (!prefetch_nocc_operand (operands[0], QImode))
10048 operands[0]
10049 = replace_equiv_address (operands[0],
10050 copy_to_mode_reg (Pmode,
10051 XEXP (operands[0], 0)));
10052 emit_insn (gen_prefetch_nocc (operands[0], operands[1], operands[2]));
10053 }
10054 else
10055 {
10056 if (!prefetch_cc_operand (operands[0], QImode))
10057 operands[0]
10058 = replace_equiv_address (operands[0],
10059 copy_to_mode_reg (Pmode,
10060 XEXP (operands[0], 0)));
10061 emit_insn (gen_prefetch_cc (operands[0], operands[1], operands[2]));
10062 }
10063 DONE;
10064 })
10066 (define_insn "prefetch_cc"
10067 [(prefetch (match_operand:QI 0 "prefetch_cc_operand" "RW")
10068 (match_operand:SI 1 "const_int_operand" "n")
10069 (match_operand:SI 2 "const_int_operand" "n"))]
10070 "TARGET_PA_20 && operands[2] == const0_rtx"
10071 {
10072 /* The SL cache-control completor indicates good spatial locality but
10073 poor temporal locality. The ldw instruction with a target of general
10074 register 0 prefetches a cache line for a read. The ldd instruction
10075 prefetches a cache line for a write. */
10076 static const char * const instr[2] = {
10077 "ldw%M0,sl %0,%%r0",
10078 "ldd%M0,sl %0,%%r0"
10079 };
10080 int read_or_write = INTVAL (operands[1]);
10082 gcc_assert (read_or_write >= 0 && read_or_write <= 1);
10084 return instr [read_or_write];
10085 }
10086 [(set_attr "type" "load")
10087 (set_attr "length" "4")])
10089 (define_insn "prefetch_nocc"
10090 [(prefetch (match_operand:QI 0 "prefetch_nocc_operand" "A,RQ")
10091 (match_operand:SI 1 "const_int_operand" "n,n")
10092 (match_operand:SI 2 "const_int_operand" "n,n"))]
10093 "TARGET_PA_20 && operands[2] != const0_rtx"
10094 {
10095 /* The ldw instruction with a target of general register 0 prefetches
10096 a cache line for a read. The ldd instruction prefetches a cache line
10097 for a write. */
10098 static const char * const instr[2][2] = {
10099 {
10100 "ldw RT'%A0,%%r0",
10101 "ldd RT'%A0,%%r0",
10102 },
10103 {
10104 "ldw%M0 %0,%%r0",
10105 "ldd%M0 %0,%%r0",
10106 }
10107 };
10108 int read_or_write = INTVAL (operands[1]);
10110 gcc_assert (which_alternative == 0 || which_alternative == 1);
10111 gcc_assert (read_or_write >= 0 && read_or_write <= 1);
10113 return instr [which_alternative][read_or_write];
10114 }
10115 [(set_attr "type" "load")
10116 (set_attr "length" "4")])
10119 ;; TLS Support
10120 (define_insn "tgd_load"
10121 [(set (match_operand:SI 0 "register_operand" "=r")
10122 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD))
10123 (clobber (reg:SI 1))
10124 (use (reg:SI 27))]
10125 ""
10126 "*
10127 {
10128 return \"addil LR'%1-$tls_gdidx$,%%r27\;ldo RR'%1-$tls_gdidx$(%%r1),%0\";
10129 }"
10130 [(set_attr "type" "multi")
10131 (set_attr "length" "8")])
10133 (define_insn "tgd_load_pic"
10134 [(set (match_operand:SI 0 "register_operand" "=r")
10135 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD_PIC))
10136 (clobber (reg:SI 1))
10137 (use (reg:SI 19))]
10138 ""
10139 "*
10140 {
10141 return \"addil LT'%1-$tls_gdidx$,%%r19\;ldo RT'%1-$tls_gdidx$(%%r1),%0\";
10142 }"
10143 [(set_attr "type" "multi")
10144 (set_attr "length" "8")])
10146 (define_insn "tld_load"
10147 [(set (match_operand:SI 0 "register_operand" "=r")
10148 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM))
10149 (clobber (reg:SI 1))
10150 (use (reg:SI 27))]
10151 ""
10152 "*
10153 {
10154 return \"addil LR'%1-$tls_ldidx$,%%r27\;ldo RR'%1-$tls_ldidx$(%%r1),%0\";
10155 }"
10156 [(set_attr "type" "multi")
10157 (set_attr "length" "8")])
10159 (define_insn "tld_load_pic"
10160 [(set (match_operand:SI 0 "register_operand" "=r")
10161 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM_PIC))
10162 (clobber (reg:SI 1))
10163 (use (reg:SI 19))]
10164 ""
10165 "*
10166 {
10167 return \"addil LT'%1-$tls_ldidx$,%%r19\;ldo RT'%1-$tls_ldidx$(%%r1),%0\";
10168 }"
10169 [(set_attr "type" "multi")
10170 (set_attr "length" "8")])
10172 (define_insn "tld_offset_load"
10173 [(set (match_operand:SI 0 "register_operand" "=r")
10174 (plus:SI (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")]
10175 UNSPEC_TLSLDO)
10176 (match_operand:SI 2 "register_operand" "r")))
10177 (clobber (reg:SI 1))]
10178 ""
10179 "*
10180 {
10181 return \"addil LR'%1-$tls_dtpoff$,%2\;ldo RR'%1-$tls_dtpoff$(%%r1),%0\";
10182 }"
10183 [(set_attr "type" "multi")
10184 (set_attr "length" "8")])
10186 (define_insn "tp_load"
10187 [(set (match_operand:SI 0 "register_operand" "=r")
10188 (unspec:SI [(const_int 0)] UNSPEC_TP))]
10189 ""
10190 "mfctl %%cr27,%0"
10191 [(set_attr "type" "multi")
10192 (set_attr "length" "4")])
10194 (define_insn "tie_load"
10195 [(set (match_operand:SI 0 "register_operand" "=r")
10196 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE))
10197 (clobber (reg:SI 1))
10198 (use (reg:SI 27))]
10199 ""
10200 "*
10201 {
10202 return \"addil LR'%1-$tls_ieoff$,%%r27\;ldw RR'%1-$tls_ieoff$(%%r1),%0\";
10203 }"
10204 [(set_attr "type" "multi")
10205 (set_attr "length" "8")])
10207 (define_insn "tie_load_pic"
10208 [(set (match_operand:SI 0 "register_operand" "=r")
10209 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE_PIC))
10210 (clobber (reg:SI 1))
10211 (use (reg:SI 19))]
10212 ""
10213 "*
10214 {
10215 return \"addil LT'%1-$tls_ieoff$,%%r19\;ldw RT'%1-$tls_ieoff$(%%r1),%0\";
10216 }"
10217 [(set_attr "type" "multi")
10218 (set_attr "length" "8")])
10220 (define_insn "tle_load"
10221 [(set (match_operand:SI 0 "register_operand" "=r")
10222 (plus:SI (unspec:SI [(match_operand 1 "tle_symbolic_operand" "")]
10223 UNSPEC_TLSLE)
10224 (match_operand:SI 2 "register_operand" "r")))
10225 (clobber (reg:SI 1))]
10226 ""
10227 "addil LR'%1-$tls_leoff$,%2\;ldo RR'%1-$tls_leoff$(%%r1),%0"
10228 [(set_attr "type" "multi")
10229 (set_attr "length" "8")])