1 ;; GCC machine description for IA-64 synchronization instructions.
2 ;; Copyright (C) 2005, 2007
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_mode_iterator IMODE [QI HI SI DI])
22 (define_mode_iterator I124MODE [QI HI SI])
23 (define_mode_iterator I48MODE [SI DI])
24 (define_mode_attr modesuffix [(QI "1") (HI "2") (SI "4") (DI "8")])
26 (define_code_iterator FETCHOP [plus minus ior xor and])
27 (define_code_attr fetchop_name
28 [(plus "add") (minus "sub") (ior "ior") (xor "xor") (and "and")])
30 (define_insn "memory_barrier"
31 [(set (mem:BLK (match_scratch:DI 0 "X"))
32 (unspec:BLK [(mem:BLK (match_scratch:DI 1 "X"))] UNSPEC_MF))]
35 [(set_attr "itanium_class" "syst_m")])
37 (define_insn "fetchadd_acq_<mode>"
38 [(set (match_operand:I48MODE 0 "gr_register_operand" "=r")
39 (match_operand:I48MODE 1 "not_postinc_memory_operand" "+S"))
41 (unspec:I48MODE [(match_dup 1)
42 (match_operand:I48MODE 2 "fetchadd_operand" "n")]
43 UNSPEC_FETCHADD_ACQ))]
45 "fetchadd<modesuffix>.acq %0 = %1, %2"
46 [(set_attr "itanium_class" "sem")])
48 (define_expand "sync_<fetchop_name><mode>"
49 [(set (match_operand:IMODE 0 "memory_operand" "")
50 (FETCHOP:IMODE (match_dup 0)
51 (match_operand:IMODE 1 "general_operand" "")))]
54 ia64_expand_atomic_op (<CODE>, operands[0], operands[1], NULL, NULL);
58 (define_expand "sync_nand<mode>"
59 [(set (match_operand:IMODE 0 "memory_operand" "")
60 (and:IMODE (not:IMODE (match_dup 0))
61 (match_operand:IMODE 1 "general_operand" "")))]
64 ia64_expand_atomic_op (NOT, operands[0], operands[1], NULL, NULL);
68 (define_expand "sync_old_<fetchop_name><mode>"
69 [(set (match_operand:IMODE 0 "gr_register_operand" "")
71 (match_operand:IMODE 1 "memory_operand" "")
72 (match_operand:IMODE 2 "general_operand" "")))]
75 ia64_expand_atomic_op (<CODE>, operands[1], operands[2], operands[0], NULL);
79 (define_expand "sync_old_nand<mode>"
80 [(set (match_operand:IMODE 0 "gr_register_operand" "")
82 (not:IMODE (match_operand:IMODE 1 "memory_operand" ""))
83 (match_operand:IMODE 2 "general_operand" "")))]
86 ia64_expand_atomic_op (NOT, operands[1], operands[2], operands[0], NULL);
90 (define_expand "sync_new_<fetchop_name><mode>"
91 [(set (match_operand:IMODE 0 "gr_register_operand" "")
93 (match_operand:IMODE 1 "memory_operand" "")
94 (match_operand:IMODE 2 "general_operand" "")))]
97 ia64_expand_atomic_op (<CODE>, operands[1], operands[2], NULL, operands[0]);
101 (define_expand "sync_new_nand<mode>"
102 [(set (match_operand:IMODE 0 "gr_register_operand" "")
104 (not:IMODE (match_operand:IMODE 1 "memory_operand" ""))
105 (match_operand:IMODE 2 "general_operand" "")))]
108 ia64_expand_atomic_op (NOT, operands[1], operands[2], NULL, operands[0]);
112 (define_expand "sync_compare_and_swap<mode>"
113 [(match_operand:IMODE 0 "gr_register_operand" "")
114 (match_operand:IMODE 1 "memory_operand" "")
115 (match_operand:IMODE 2 "gr_register_operand" "")
116 (match_operand:IMODE 3 "gr_register_operand" "")]
119 rtx ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
122 convert_move (ccv, operands[2], 1);
125 if (GET_MODE (dst) != DImode)
126 dst = gen_reg_rtx (DImode);
128 emit_insn (gen_memory_barrier ());
129 emit_insn (gen_cmpxchg_rel_<mode> (dst, operands[1], ccv, operands[3]));
131 if (dst != operands[0])
132 emit_move_insn (operands[0], gen_lowpart (<MODE>mode, dst));
136 (define_insn "cmpxchg_rel_<mode>"
137 [(set (match_operand:DI 0 "gr_register_operand" "=r")
139 (match_operand:I124MODE 1 "not_postinc_memory_operand" "+S")))
143 (match_operand:DI 2 "ar_ccv_reg_operand" "")
144 (match_operand:I124MODE 3 "gr_register_operand" "r")]
145 UNSPEC_CMPXCHG_ACQ))]
147 "cmpxchg<modesuffix>.rel %0 = %1, %3, %2"
148 [(set_attr "itanium_class" "sem")])
150 (define_insn "cmpxchg_rel_di"
151 [(set (match_operand:DI 0 "gr_register_operand" "=r")
152 (match_operand:DI 1 "not_postinc_memory_operand" "+S"))
154 (unspec:DI [(match_dup 1)
155 (match_operand:DI 2 "ar_ccv_reg_operand" "")
156 (match_operand:DI 3 "gr_register_operand" "r")]
157 UNSPEC_CMPXCHG_ACQ))]
159 "cmpxchg8.rel %0 = %1, %3, %2"
160 [(set_attr "itanium_class" "sem")])
162 (define_insn "sync_lock_test_and_set<mode>"
163 [(set (match_operand:IMODE 0 "gr_register_operand" "=r")
164 (match_operand:IMODE 1 "not_postinc_memory_operand" "+S"))
166 (match_operand:IMODE 2 "gr_register_operand" "r"))]
168 "xchg<modesuffix> %0 = %1, %2"
169 [(set_attr "itanium_class" "sem")])
171 (define_expand "sync_lock_release<mode>"
172 [(set (match_operand:IMODE 0 "memory_operand" "")
173 (match_operand:IMODE 1 "gr_reg_or_0_operand" ""))]
176 gcc_assert (MEM_VOLATILE_P (operands[0]));