1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
46 #include "target-def.h"
48 /* Classifies a h8300_src_operand or h8300_dst_operand.
51 A constant operand of some sort.
57 A memory reference with a constant address.
60 A memory reference with a register as its address.
63 Some other kind of memory reference. */
64 enum h8300_operand_class
74 /* For a general two-operand instruction, element [X][Y] gives
75 the length of the opcode fields when the first operand has class
76 (X + 1) and the second has class Y. */
77 typedef unsigned char h8300_length_table
[NUM_H8OPS
- 1][NUM_H8OPS
];
79 /* Forward declarations. */
80 static const char *byte_reg (rtx
, int);
81 static int h8300_interrupt_function_p (tree
);
82 static int h8300_saveall_function_p (tree
);
83 static int h8300_monitor_function_p (tree
);
84 static int h8300_os_task_function_p (tree
);
85 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT
);
86 static HOST_WIDE_INT
round_frame_size (HOST_WIDE_INT
);
87 static unsigned int compute_saved_regs (void);
88 static void push (int);
89 static void pop (int);
90 static const char *cond_string (enum rtx_code
);
91 static unsigned int h8300_asm_insn_count (const char *);
92 static tree
h8300_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
93 static tree
h8300_handle_eightbit_data_attribute (tree
*, tree
, tree
, int, bool *);
94 static tree
h8300_handle_tiny_data_attribute (tree
*, tree
, tree
, int, bool *);
95 #ifndef OBJECT_FORMAT_ELF
96 static void h8300_asm_named_section (const char *, unsigned int, tree
);
98 static int h8300_and_costs (rtx
);
99 static int h8300_shift_costs (rtx
);
100 static void h8300_push_pop (int, int, int, int);
101 static int h8300_stack_offset_p (rtx
, int);
102 static int h8300_ldm_stm_regno (rtx
, int, int, int);
103 static void h8300_reorg (void);
104 static unsigned int h8300_constant_length (rtx
);
105 static unsigned int h8300_displacement_length (rtx
, int);
106 static unsigned int h8300_classify_operand (rtx
, int, enum h8300_operand_class
*);
107 static unsigned int h8300_length_from_table (rtx
, rtx
, const h8300_length_table
*);
108 static unsigned int h8300_unary_length (rtx
);
109 static unsigned int h8300_short_immediate_length (rtx
);
110 static unsigned int h8300_bitfield_length (rtx
, rtx
);
111 static unsigned int h8300_binary_length (rtx
, const h8300_length_table
*);
112 static bool h8300_short_move_mem_p (rtx
, enum rtx_code
);
113 static unsigned int h8300_move_length (rtx
*, const h8300_length_table
*);
115 /* CPU_TYPE, says what cpu we're compiling for. */
118 /* True if a #pragma interrupt has been seen for the current function. */
119 static int pragma_interrupt
;
121 /* True if a #pragma saveall has been seen for the current function. */
122 static int pragma_saveall
;
124 static const char *const names_big
[] =
125 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
127 static const char *const names_extended
[] =
128 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
130 static const char *const names_upper_extended
[] =
131 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
133 /* Points to one of the above. */
134 /* ??? The above could be put in an array indexed by CPU_TYPE. */
135 const char * const *h8_reg_names
;
137 /* Various operations needed by the following, indexed by CPU_TYPE. */
139 const char *h8_push_op
, *h8_pop_op
, *h8_mov_op
;
141 /* Value of MOVE_RATIO. */
142 int h8300_move_ratio
;
144 /* See below where shifts are handled for explanation of this enum. */
154 /* Symbols of the various shifts which can be used as indices. */
158 SHIFT_ASHIFT
, SHIFT_LSHIFTRT
, SHIFT_ASHIFTRT
161 /* Macros to keep the shift algorithm tables small. */
162 #define INL SHIFT_INLINE
163 #define ROT SHIFT_ROT_AND
164 #define LOP SHIFT_LOOP
165 #define SPC SHIFT_SPECIAL
167 /* The shift algorithms for each machine, mode, shift type, and shift
168 count are defined below. The three tables below correspond to
169 QImode, HImode, and SImode, respectively. Each table is organized
170 by, in the order of indices, machine, shift type, and shift count. */
172 static enum shift_alg shift_alg_qi
[3][3][8] = {
175 /* 0 1 2 3 4 5 6 7 */
176 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
177 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
178 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
182 /* 0 1 2 3 4 5 6 7 */
183 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
184 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
185 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
189 /* 0 1 2 3 4 5 6 7 */
190 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_ASHIFT */
191 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
192 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
} /* SHIFT_ASHIFTRT */
196 static enum shift_alg shift_alg_hi
[3][3][16] = {
199 /* 0 1 2 3 4 5 6 7 */
200 /* 8 9 10 11 12 13 14 15 */
201 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
202 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
203 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
204 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
205 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
206 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
210 /* 0 1 2 3 4 5 6 7 */
211 /* 8 9 10 11 12 13 14 15 */
212 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
213 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
214 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
215 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
216 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
217 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
221 /* 0 1 2 3 4 5 6 7 */
222 /* 8 9 10 11 12 13 14 15 */
223 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
224 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
225 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
226 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
227 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
228 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
232 static enum shift_alg shift_alg_si
[3][3][32] = {
235 /* 0 1 2 3 4 5 6 7 */
236 /* 8 9 10 11 12 13 14 15 */
237 /* 16 17 18 19 20 21 22 23 */
238 /* 24 25 26 27 28 29 30 31 */
239 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
240 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
241 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
,
242 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFT */
243 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
244 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
245 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
,
246 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, SPC
}, /* SHIFT_LSHIFTRT */
247 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
248 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
249 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
250 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
254 /* 0 1 2 3 4 5 6 7 */
255 /* 8 9 10 11 12 13 14 15 */
256 /* 16 17 18 19 20 21 22 23 */
257 /* 24 25 26 27 28 29 30 31 */
258 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
259 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
260 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
261 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
262 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
263 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
264 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
265 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
266 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
267 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
268 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
269 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
273 /* 0 1 2 3 4 5 6 7 */
274 /* 8 9 10 11 12 13 14 15 */
275 /* 16 17 18 19 20 21 22 23 */
276 /* 24 25 26 27 28 29 30 31 */
277 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
278 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
279 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
280 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
281 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
282 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
283 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
284 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
285 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
286 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
287 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
288 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
304 /* Initialize various cpu specific globals at start up. */
307 h8300_init_once (void)
309 static const char *const h8_push_ops
[2] = { "push" , "push.l" };
310 static const char *const h8_pop_ops
[2] = { "pop" , "pop.l" };
311 static const char *const h8_mov_ops
[2] = { "mov.w", "mov.l" };
315 cpu_type
= (int) CPU_H8300
;
316 h8_reg_names
= names_big
;
320 /* For this we treat the H8/300H and H8S the same. */
321 cpu_type
= (int) CPU_H8300H
;
322 h8_reg_names
= names_extended
;
324 h8_push_op
= h8_push_ops
[cpu_type
];
325 h8_pop_op
= h8_pop_ops
[cpu_type
];
326 h8_mov_op
= h8_mov_ops
[cpu_type
];
328 if (!TARGET_H8300S
&& TARGET_MAC
)
330 error ("-ms2600 is used without -ms");
331 target_flags
|= MASK_H8300S_1
;
334 if (TARGET_H8300
&& TARGET_NORMAL_MODE
)
336 error ("-mn is used without -mh or -ms");
337 target_flags
^= MASK_NORMAL_MODE
;
340 /* Some of the shifts are optimized for speed by default.
341 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
342 If optimizing for size, change shift_alg for those shift to
347 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
348 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
349 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][13] = SHIFT_LOOP
;
350 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][14] = SHIFT_LOOP
;
352 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][13] = SHIFT_LOOP
;
353 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][14] = SHIFT_LOOP
;
355 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
356 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
359 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
360 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
362 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][5] = SHIFT_LOOP
;
363 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][6] = SHIFT_LOOP
;
365 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][5] = SHIFT_LOOP
;
366 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][6] = SHIFT_LOOP
;
367 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
368 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
371 shift_alg_hi
[H8_S
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
374 /* Work out a value for MOVE_RATIO. */
377 /* Memory-memory moves are quite expensive without the
378 h8sx instructions. */
379 h8300_move_ratio
= 3;
381 else if (flag_omit_frame_pointer
)
383 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
384 sometimes be as short as two individual memory-to-memory moves,
385 but since they use all the call-saved registers, it seems better
386 to allow up to three moves here. */
387 h8300_move_ratio
= 4;
389 else if (optimize_size
)
391 /* In this case we don't use movmd sequences since they tend
392 to be longer than calls to memcpy(). Memory-to-memory
393 moves are cheaper than for !TARGET_H8300SX, so it makes
394 sense to have a slightly higher threshold. */
395 h8300_move_ratio
= 4;
399 /* We use movmd sequences for some moves since it can be quicker
400 than calling memcpy(). The sequences will need to save and
401 restore er6 though, so bump up the cost. */
402 h8300_move_ratio
= 6;
406 /* Implement REG_CLASS_FROM_LETTER.
408 Some patterns need to use er6 as a scratch register. This is
409 difficult to arrange since er6 is the frame pointer and usually
412 Such patterns should define two alternatives, one which allows only
413 er6 and one which allows any general register. The former alternative
414 should have a 'd' constraint while the latter should be disparaged and
417 Normally, 'd' maps to DESTINATION_REGS and 'D' maps to GENERAL_REGS.
418 However, there are cases where they should be NO_REGS:
420 - 'd' should be NO_REGS when reloading a function that uses the
421 frame pointer. In this case, DESTINATION_REGS won't contain any
422 spillable registers, so the first alternative can't be used.
424 - -fno-omit-frame-pointer means that the frame pointer will
425 always be in use. It's therefore better to map 'd' to NO_REGS
426 before reload so that register allocator will pick the second
429 - we would like 'D' to be be NO_REGS when the frame pointer isn't
430 live, but we the frame pointer may turn out to be needed after
431 we start reload, and then we may have already decided we don't
432 have a choice, so we can't do that. Forcing the register
433 allocator to use er6 if possible might produce better code for
434 small functions: it's more efficient to save and restore er6 in
435 the prologue & epilogue than to do it in a define_split.
436 Hopefully disparaging 'D' will have a similar effect, without
437 forcing a reload failure if the frame pointer is found to be
441 h8300_reg_class_from_letter (int c
)
452 if (!flag_omit_frame_pointer
&& !reload_completed
)
454 if (frame_pointer_needed
&& reload_in_progress
)
456 return DESTINATION_REGS
;
459 /* The meaning of a constraint shouldn't change dynamically, so
460 we can't make this NO_REGS. */
471 /* Return the byte register name for a register rtx X. B should be 0
472 if you want a lower byte register. B should be 1 if you want an
473 upper byte register. */
476 byte_reg (rtx x
, int b
)
478 static const char *const names_small
[] = {
479 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
480 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
483 gcc_assert (REG_P (x
));
485 return names_small
[REGNO (x
) * 2 + b
];
488 /* REGNO must be saved/restored across calls if this macro is true. */
490 #define WORD_REG_USED(regno) \
492 /* No need to save registers if this function will not return. */ \
493 && ! TREE_THIS_VOLATILE (current_function_decl) \
494 && (h8300_saveall_function_p (current_function_decl) \
495 /* Save any call saved register that was used. */ \
496 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
497 /* Save the frame pointer if it was used. */ \
498 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
499 /* Save any register used in an interrupt handler. */ \
500 || (h8300_current_function_interrupt_function_p () \
501 && df_regs_ever_live_p (regno)) \
502 /* Save call clobbered registers in non-leaf interrupt \
504 || (h8300_current_function_interrupt_function_p () \
505 && call_used_regs[regno] \
506 && !current_function_is_leaf)))
508 /* Output assembly language to FILE for the operation OP with operand size
509 SIZE to adjust the stack pointer. */
512 h8300_emit_stack_adjustment (int sign
, HOST_WIDE_INT size
)
514 /* If the frame size is 0, we don't have anything to do. */
518 /* H8/300 cannot add/subtract a large constant with a single
519 instruction. If a temporary register is available, load the
520 constant to it and then do the addition. */
523 && !h8300_current_function_interrupt_function_p ()
524 && !(cfun
->static_chain_decl
!= NULL
&& sign
< 0))
526 rtx r3
= gen_rtx_REG (Pmode
, 3);
527 emit_insn (gen_movhi (r3
, GEN_INT (sign
* size
)));
528 emit_insn (gen_addhi3 (stack_pointer_rtx
,
529 stack_pointer_rtx
, r3
));
533 /* The stack adjustment made here is further optimized by the
534 splitter. In case of H8/300, the splitter always splits the
535 addition emitted here to make the adjustment
538 emit_insn (gen_addhi3 (stack_pointer_rtx
,
539 stack_pointer_rtx
, GEN_INT (sign
* size
)));
541 emit_insn (gen_addsi3 (stack_pointer_rtx
,
542 stack_pointer_rtx
, GEN_INT (sign
* size
)));
546 /* Round up frame size SIZE. */
549 round_frame_size (HOST_WIDE_INT size
)
551 return ((size
+ STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
552 & -STACK_BOUNDARY
/ BITS_PER_UNIT
);
555 /* Compute which registers to push/pop.
556 Return a bit vector of registers. */
559 compute_saved_regs (void)
561 unsigned int saved_regs
= 0;
564 /* Construct a bit vector of registers to be pushed/popped. */
565 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
567 if (WORD_REG_USED (regno
))
568 saved_regs
|= 1 << regno
;
571 /* Don't push/pop the frame pointer as it is treated separately. */
572 if (frame_pointer_needed
)
573 saved_regs
&= ~(1 << HARD_FRAME_POINTER_REGNUM
);
578 /* Emit an insn to push register RN. */
583 rtx reg
= gen_rtx_REG (word_mode
, rn
);
587 x
= gen_push_h8300 (reg
);
588 else if (!TARGET_NORMAL_MODE
)
589 x
= gen_push_h8300hs_advanced (reg
);
591 x
= gen_push_h8300hs_normal (reg
);
593 REG_NOTES (x
) = gen_rtx_EXPR_LIST (REG_INC
, stack_pointer_rtx
, 0);
596 /* Emit an insn to pop register RN. */
601 rtx reg
= gen_rtx_REG (word_mode
, rn
);
605 x
= gen_pop_h8300 (reg
);
606 else if (!TARGET_NORMAL_MODE
)
607 x
= gen_pop_h8300hs_advanced (reg
);
609 x
= gen_pop_h8300hs_normal (reg
);
611 REG_NOTES (x
) = gen_rtx_EXPR_LIST (REG_INC
, stack_pointer_rtx
, 0);
614 /* Emit an instruction to push or pop NREGS consecutive registers
615 starting at register REGNO. POP_P selects a pop rather than a
616 push and RETURN_P is true if the instruction should return.
618 It must be possible to do the requested operation in a single
619 instruction. If NREGS == 1 && !RETURN_P, use a normal push
620 or pop insn. Otherwise emit a parallel of the form:
623 [(return) ;; if RETURN_P
624 (save or restore REGNO)
625 (save or restore REGNO + 1)
627 (save or restore REGNO + NREGS - 1)
628 (set sp (plus sp (const_int adjust)))] */
631 h8300_push_pop (int regno
, int nregs
, int pop_p
, int return_p
)
637 /* See whether we can use a simple push or pop. */
638 if (!return_p
&& nregs
== 1)
647 /* We need one element for the return insn, if present, one for each
648 register, and one for stack adjustment. */
649 vec
= rtvec_alloc ((return_p
!= 0) + nregs
+ 1);
650 sp
= stack_pointer_rtx
;
653 /* Add the return instruction. */
656 RTVEC_ELT (vec
, i
) = gen_rtx_RETURN (VOIDmode
);
660 /* Add the register moves. */
661 for (j
= 0; j
< nregs
; j
++)
667 /* Register REGNO + NREGS - 1 is popped first. Before the
668 stack adjustment, its slot is at address @sp. */
669 lhs
= gen_rtx_REG (SImode
, regno
+ j
);
670 rhs
= gen_rtx_MEM (SImode
, plus_constant (sp
, (nregs
- j
- 1) * 4));
674 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
675 lhs
= gen_rtx_MEM (SImode
, plus_constant (sp
, (j
+ 1) * -4));
676 rhs
= gen_rtx_REG (SImode
, regno
+ j
);
678 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (VOIDmode
, lhs
, rhs
);
681 /* Add the stack adjustment. */
682 offset
= GEN_INT ((pop_p
? nregs
: -nregs
) * 4);
683 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (VOIDmode
, sp
,
684 gen_rtx_PLUS (Pmode
, sp
, offset
));
686 emit_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
689 /* Return true if X has the value sp + OFFSET. */
692 h8300_stack_offset_p (rtx x
, int offset
)
695 return x
== stack_pointer_rtx
;
697 return (GET_CODE (x
) == PLUS
698 && XEXP (x
, 0) == stack_pointer_rtx
699 && GET_CODE (XEXP (x
, 1)) == CONST_INT
700 && INTVAL (XEXP (x
, 1)) == offset
);
703 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
704 something that may be an ldm or stm instruction. If it fits
705 the required template, return the register it loads or stores,
708 LOAD_P is true if X should be a load, false if it should be a store.
709 NREGS is the number of registers that the whole instruction is expected
710 to load or store. INDEX is the index of the register that X should
711 load or store, relative to the lowest-numbered register. */
714 h8300_ldm_stm_regno (rtx x
, int load_p
, int index
, int nregs
)
716 int regindex
, memindex
, offset
;
719 regindex
= 0, memindex
= 1, offset
= (nregs
- index
- 1) * 4;
721 memindex
= 0, regindex
= 1, offset
= (index
+ 1) * -4;
723 if (GET_CODE (x
) == SET
724 && GET_CODE (XEXP (x
, regindex
)) == REG
725 && GET_CODE (XEXP (x
, memindex
)) == MEM
726 && h8300_stack_offset_p (XEXP (XEXP (x
, memindex
), 0), offset
))
727 return REGNO (XEXP (x
, regindex
));
732 /* Return true if the elements of VEC starting at FIRST describe an
733 ldm or stm instruction (LOAD_P says which). */
736 h8300_ldm_stm_parallel (rtvec vec
, int load_p
, int first
)
739 int nregs
, i
, regno
, adjust
;
741 /* There must be a stack adjustment, a register move, and at least one
742 other operation (a return or another register move). */
743 if (GET_NUM_ELEM (vec
) < 3)
746 /* Get the range of registers to be pushed or popped. */
747 nregs
= GET_NUM_ELEM (vec
) - first
- 1;
748 regno
= h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
), load_p
, 0, nregs
);
750 /* Check that the call to h8300_ldm_stm_regno succeeded and
751 that we're only dealing with GPRs. */
752 if (regno
< 0 || regno
+ nregs
> 8)
755 /* 2-register h8s instructions must start with an even-numbered register.
756 3- and 4-register instructions must start with er0 or er4. */
759 if ((regno
& 1) != 0)
761 if (nregs
> 2 && (regno
& 3) != 0)
765 /* Check the other loads or stores. */
766 for (i
= 1; i
< nregs
; i
++)
767 if (h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
+ i
), load_p
, i
, nregs
)
771 /* Check the stack adjustment. */
772 last
= RTVEC_ELT (vec
, first
+ nregs
);
773 adjust
= (load_p
? nregs
: -nregs
) * 4;
774 return (GET_CODE (last
) == SET
775 && SET_DEST (last
) == stack_pointer_rtx
776 && h8300_stack_offset_p (SET_SRC (last
), adjust
));
779 /* This is what the stack looks like after the prolog of
780 a function with a frame has been set up:
786 <saved registers> <- sp
788 This is what the stack looks like after the prolog of
789 a function which doesn't have a frame:
794 <saved registers> <- sp
797 /* Generate RTL code for the function prologue. */
800 h8300_expand_prologue (void)
806 /* If the current function has the OS_Task attribute set, then
807 we have a naked prologue. */
808 if (h8300_os_task_function_p (current_function_decl
))
811 if (h8300_monitor_function_p (current_function_decl
))
812 /* My understanding of monitor functions is they act just like
813 interrupt functions, except the prologue must mask
815 emit_insn (gen_monitor_prologue ());
817 if (frame_pointer_needed
)
820 push (HARD_FRAME_POINTER_REGNUM
);
821 emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
824 /* Push the rest of the registers in ascending order. */
825 saved_regs
= compute_saved_regs ();
826 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
+= n_regs
)
829 if (saved_regs
& (1 << regno
))
833 /* See how many registers we can push at the same time. */
834 if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
835 && ((saved_regs
>> regno
) & 0x0f) == 0x0f)
838 else if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
839 && ((saved_regs
>> regno
) & 0x07) == 0x07)
842 else if ((!TARGET_H8300SX
|| (regno
& 1) == 0)
843 && ((saved_regs
>> regno
) & 0x03) == 0x03)
847 h8300_push_pop (regno
, n_regs
, 0, 0);
851 /* Leave room for locals. */
852 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()));
855 /* Return nonzero if we can use "rts" for the function currently being
859 h8300_can_use_return_insn_p (void)
861 return (reload_completed
862 && !frame_pointer_needed
863 && get_frame_size () == 0
864 && compute_saved_regs () == 0);
867 /* Generate RTL code for the function epilogue. */
870 h8300_expand_epilogue (void)
875 HOST_WIDE_INT frame_size
;
878 if (h8300_os_task_function_p (current_function_decl
))
879 /* OS_Task epilogues are nearly naked -- they just have an
883 frame_size
= round_frame_size (get_frame_size ());
886 /* Deallocate locals. */
887 h8300_emit_stack_adjustment (1, frame_size
);
889 /* Pop the saved registers in descending order. */
890 saved_regs
= compute_saved_regs ();
891 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
-= n_regs
)
894 if (saved_regs
& (1 << regno
))
898 /* See how many registers we can pop at the same time. */
899 if ((TARGET_H8300SX
|| (regno
& 3) == 3)
900 && ((saved_regs
<< 3 >> regno
) & 0x0f) == 0x0f)
903 else if ((TARGET_H8300SX
|| (regno
& 3) == 2)
904 && ((saved_regs
<< 2 >> regno
) & 0x07) == 0x07)
907 else if ((TARGET_H8300SX
|| (regno
& 1) == 1)
908 && ((saved_regs
<< 1 >> regno
) & 0x03) == 0x03)
912 /* See if this pop would be the last insn before the return.
913 If so, use rte/l or rts/l instead of pop or ldm.l. */
915 && !frame_pointer_needed
917 && (saved_regs
& ((1 << (regno
- n_regs
+ 1)) - 1)) == 0)
920 h8300_push_pop (regno
- n_regs
+ 1, n_regs
, 1, returned_p
);
924 /* Pop frame pointer if we had one. */
925 if (frame_pointer_needed
)
929 h8300_push_pop (HARD_FRAME_POINTER_REGNUM
, 1, 1, returned_p
);
933 emit_insn (gen_rtx_RETURN (VOIDmode
));
936 /* Return nonzero if the current function is an interrupt
940 h8300_current_function_interrupt_function_p (void)
942 return (h8300_interrupt_function_p (current_function_decl
)
943 || h8300_monitor_function_p (current_function_decl
));
946 /* Output assembly code for the start of the file. */
949 h8300_file_start (void)
951 default_file_start ();
954 fputs (TARGET_NORMAL_MODE
? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file
);
955 else if (TARGET_H8300SX
)
956 fputs (TARGET_NORMAL_MODE
? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file
);
957 else if (TARGET_H8300S
)
958 fputs (TARGET_NORMAL_MODE
? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file
);
961 /* Output assembly language code for the end of file. */
964 h8300_file_end (void)
966 fputs ("\t.end\n", asm_out_file
);
969 /* Split an add of a small constant into two adds/subs insns.
971 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
972 instead of adds/subs. */
975 split_adds_subs (enum machine_mode mode
, rtx
*operands
)
977 HOST_WIDE_INT val
= INTVAL (operands
[1]);
978 rtx reg
= operands
[0];
979 HOST_WIDE_INT sign
= 1;
980 HOST_WIDE_INT amount
;
981 rtx (*gen_add
) (rtx
, rtx
, rtx
);
983 /* Force VAL to be positive so that we do not have to consider the
994 gen_add
= gen_addhi3
;
998 gen_add
= gen_addsi3
;
1005 /* Try different amounts in descending order. */
1006 for (amount
= (TARGET_H8300H
|| TARGET_H8300S
) ? 4 : 2;
1010 for (; val
>= amount
; val
-= amount
)
1011 emit_insn (gen_add (reg
, reg
, GEN_INT (sign
* amount
)));
1017 /* Handle machine specific pragmas for compatibility with existing
1018 compilers for the H8/300.
1020 pragma saveall generates prologue/epilogue code which saves and
1021 restores all the registers on function entry.
1023 pragma interrupt saves and restores all registers, and exits with
1024 an rte instruction rather than an rts. A pointer to a function
1025 with this attribute may be safely used in an interrupt vector. */
1028 h8300_pr_interrupt (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1030 pragma_interrupt
= 1;
1034 h8300_pr_saveall (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1039 /* If the next function argument with MODE and TYPE is to be passed in
1040 a register, return a reg RTX for the hard register in which to pass
1041 the argument. CUM represents the state after the last argument.
1042 If the argument is to be pushed, NULL_RTX is returned. */
1045 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1046 tree type
, int named
)
1048 static const char *const hand_list
[] = {
1067 rtx result
= NULL_RTX
;
1071 /* Never pass unnamed arguments in registers. */
1075 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1076 if (TARGET_QUICKCALL
)
1079 /* If calling hand written assembler, use 4 regs of args. */
1082 const char * const *p
;
1084 fname
= XSTR (cum
->libcall
, 0);
1086 /* See if this libcall is one of the hand coded ones. */
1087 for (p
= hand_list
; *p
&& strcmp (*p
, fname
) != 0; p
++)
1098 if (mode
== BLKmode
)
1099 size
= int_size_in_bytes (type
);
1101 size
= GET_MODE_SIZE (mode
);
1103 if (size
+ cum
->nbytes
<= regpass
* UNITS_PER_WORD
1104 && cum
->nbytes
/ UNITS_PER_WORD
<= 3)
1105 result
= gen_rtx_REG (mode
, cum
->nbytes
/ UNITS_PER_WORD
);
1111 /* Compute the cost of an and insn. */
1114 h8300_and_costs (rtx x
)
1118 if (GET_MODE (x
) == QImode
)
1121 if (GET_MODE (x
) != HImode
1122 && GET_MODE (x
) != SImode
)
1126 operands
[1] = XEXP (x
, 0);
1127 operands
[2] = XEXP (x
, 1);
1129 return compute_logical_op_length (GET_MODE (x
), operands
) / 2;
1132 /* Compute the cost of a shift insn. */
1135 h8300_shift_costs (rtx x
)
1139 if (GET_MODE (x
) != QImode
1140 && GET_MODE (x
) != HImode
1141 && GET_MODE (x
) != SImode
)
1146 operands
[2] = XEXP (x
, 1);
1148 return compute_a_shift_length (NULL
, operands
) / 2;
1151 /* Worker function for TARGET_RTX_COSTS. */
1154 h8300_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1156 if (TARGET_H8300SX
&& outer_code
== MEM
)
1158 /* Estimate the number of execution states needed to calculate
1160 if (register_operand (x
, VOIDmode
)
1161 || GET_CODE (x
) == POST_INC
1162 || GET_CODE (x
) == POST_DEC
1166 *total
= COSTS_N_INSNS (1);
1174 HOST_WIDE_INT n
= INTVAL (x
);
1178 /* Constant operands need the same number of processor
1179 states as register operands. Although we could try to
1180 use a size-based cost for optimize_size, the lack of
1181 of a mode makes the results very unpredictable. */
1185 if (-4 <= n
|| n
<= 4)
1196 *total
= 0 + (outer_code
== SET
);
1200 if (TARGET_H8300H
|| TARGET_H8300S
)
1201 *total
= 0 + (outer_code
== SET
);
1216 /* See comment for CONST_INT. */
1228 if (!h8300_dst_operand (XEXP (x
, 0), VOIDmode
)
1229 || !h8300_src_operand (XEXP (x
, 1), VOIDmode
))
1231 *total
= COSTS_N_INSNS (h8300_and_costs (x
));
1234 /* We say that MOD and DIV are so expensive because otherwise we'll
1235 generate some really horrible code for division of a power of two. */
1241 switch (GET_MODE (x
))
1245 *total
= COSTS_N_INSNS (optimize_size
? 4 : 10);
1249 *total
= COSTS_N_INSNS (optimize_size
? 4 : 18);
1255 *total
= COSTS_N_INSNS (12);
1260 switch (GET_MODE (x
))
1264 *total
= COSTS_N_INSNS (2);
1268 *total
= COSTS_N_INSNS (5);
1274 *total
= COSTS_N_INSNS (4);
1280 if (h8sx_binary_shift_operator (x
, VOIDmode
))
1282 *total
= COSTS_N_INSNS (2);
1285 else if (h8sx_unary_shift_operator (x
, VOIDmode
))
1287 *total
= COSTS_N_INSNS (1);
1290 *total
= COSTS_N_INSNS (h8300_shift_costs (x
));
1295 if (GET_MODE (x
) == HImode
)
1302 *total
= COSTS_N_INSNS (1);
1307 /* Documentation for the machine specific operand escapes:
1309 'E' like s but negative.
1310 'F' like t but negative.
1311 'G' constant just the negative
1312 'R' print operand as a byte:8 address if appropriate, else fall back to
1314 'S' print operand as a long word
1315 'T' print operand as a word
1316 'V' find the set bit, and print its number.
1317 'W' find the clear bit, and print its number.
1318 'X' print operand as a byte
1319 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1320 If this operand isn't a register, fall back to 'R' handling.
1322 'c' print the opcode corresponding to rtl
1323 'e' first word of 32-bit value - if reg, then least reg. if mem
1324 then least. if const then most sig word
1325 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1326 then +2. if const then least sig word
1327 'j' print operand as condition code.
1328 'k' print operand as reverse condition code.
1329 'm' convert an integer operand to a size suffix (.b, .w or .l)
1330 'o' print an integer without a leading '#'
1331 's' print as low byte of 16-bit value
1332 't' print as high byte of 16-bit value
1333 'w' print as low byte of 32-bit value
1334 'x' print as 2nd byte of 32-bit value
1335 'y' print as 3rd byte of 32-bit value
1336 'z' print as msb of 32-bit value
1339 /* Return assembly language string which identifies a comparison type. */
1342 cond_string (enum rtx_code code
)
1371 /* Print operand X using operand code CODE to assembly language output file
1375 print_operand (FILE *file
, rtx x
, int code
)
1377 /* This is used for communication between codes V,W,Z and Y. */
1383 switch (GET_CODE (x
))
1386 fprintf (file
, "%sl", names_big
[REGNO (x
)]);
1389 fprintf (file
, "#%ld", (-INTVAL (x
)) & 0xff);
1396 switch (GET_CODE (x
))
1399 fprintf (file
, "%sh", names_big
[REGNO (x
)]);
1402 fprintf (file
, "#%ld", ((-INTVAL (x
)) & 0xff00) >> 8);
1409 gcc_assert (GET_CODE (x
) == CONST_INT
);
1410 fprintf (file
, "#%ld", 0xff & (-INTVAL (x
)));
1413 if (GET_CODE (x
) == REG
)
1414 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1419 if (GET_CODE (x
) == REG
)
1420 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1425 bitint
= exact_log2 (INTVAL (x
) & 0xff);
1426 gcc_assert (bitint
>= 0);
1427 fprintf (file
, "#%d", bitint
);
1430 bitint
= exact_log2 ((~INTVAL (x
)) & 0xff);
1431 gcc_assert (bitint
>= 0);
1432 fprintf (file
, "#%d", bitint
);
1436 if (GET_CODE (x
) == REG
)
1437 fprintf (file
, "%s", byte_reg (x
, 0));
1442 gcc_assert (bitint
>= 0);
1443 if (GET_CODE (x
) == REG
)
1444 fprintf (file
, "%s%c", names_big
[REGNO (x
)], bitint
> 7 ? 'h' : 'l');
1446 print_operand (file
, x
, 'R');
1450 bitint
= INTVAL (x
);
1451 fprintf (file
, "#%d", bitint
& 7);
1454 switch (GET_CODE (x
))
1457 fprintf (file
, "or");
1460 fprintf (file
, "xor");
1463 fprintf (file
, "and");
1470 switch (GET_CODE (x
))
1474 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1476 fprintf (file
, "%s", names_upper_extended
[REGNO (x
)]);
1479 print_operand (file
, x
, 0);
1482 fprintf (file
, "#%ld", ((INTVAL (x
) >> 16) & 0xffff));
1488 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1489 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1490 fprintf (file
, "#%ld", ((val
>> 16) & 0xffff));
1499 switch (GET_CODE (x
))
1503 fprintf (file
, "%s", names_big
[REGNO (x
) + 1]);
1505 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1508 x
= adjust_address (x
, HImode
, 2);
1509 print_operand (file
, x
, 0);
1512 fprintf (file
, "#%ld", INTVAL (x
) & 0xffff);
1518 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1519 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1520 fprintf (file
, "#%ld", (val
& 0xffff));
1528 fputs (cond_string (GET_CODE (x
)), file
);
1531 fputs (cond_string (reverse_condition (GET_CODE (x
))), file
);
1534 gcc_assert (GET_CODE (x
) == CONST_INT
);
1554 print_operand_address (file
, x
);
1557 if (GET_CODE (x
) == CONST_INT
)
1558 fprintf (file
, "#%ld", (INTVAL (x
)) & 0xff);
1560 fprintf (file
, "%s", byte_reg (x
, 0));
1563 if (GET_CODE (x
) == CONST_INT
)
1564 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1566 fprintf (file
, "%s", byte_reg (x
, 1));
1569 if (GET_CODE (x
) == CONST_INT
)
1570 fprintf (file
, "#%ld", INTVAL (x
) & 0xff);
1572 fprintf (file
, "%s",
1573 byte_reg (x
, TARGET_H8300
? 2 : 0));
1576 if (GET_CODE (x
) == CONST_INT
)
1577 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1579 fprintf (file
, "%s",
1580 byte_reg (x
, TARGET_H8300
? 3 : 1));
1583 if (GET_CODE (x
) == CONST_INT
)
1584 fprintf (file
, "#%ld", (INTVAL (x
) >> 16) & 0xff);
1586 fprintf (file
, "%s", byte_reg (x
, 0));
1589 if (GET_CODE (x
) == CONST_INT
)
1590 fprintf (file
, "#%ld", (INTVAL (x
) >> 24) & 0xff);
1592 fprintf (file
, "%s", byte_reg (x
, 1));
1597 switch (GET_CODE (x
))
1600 switch (GET_MODE (x
))
1603 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1604 fprintf (file
, "%s", byte_reg (x
, 0));
1605 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1606 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1610 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1614 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1623 rtx addr
= XEXP (x
, 0);
1625 fprintf (file
, "@");
1626 output_address (addr
);
1628 /* Add a length suffix to constant addresses. Although this
1629 is often unnecessary, it helps to avoid ambiguity in the
1630 syntax of mova. If we wrote an insn like:
1632 mova/w.l @(1,@foo.b),er0
1634 then .b would be considered part of the symbol name.
1635 Adding a length after foo will avoid this. */
1636 if (CONSTANT_P (addr
))
1640 /* Used for mov.b and bit operations. */
1641 if (h8300_eightbit_constant_address_p (addr
))
1643 fprintf (file
, ":8");
1647 /* Fall through. We should not get here if we are
1648 processing bit operations on H8/300 or H8/300H
1649 because 'U' constraint does not allow bit
1650 operations on the tiny area on these machines. */
1655 if (h8300_constant_length (addr
) == 2)
1656 fprintf (file
, ":16");
1658 fprintf (file
, ":32");
1670 fprintf (file
, "#");
1671 print_operand_address (file
, x
);
1677 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1678 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1679 fprintf (file
, "#%ld", val
);
1688 /* Output assembly language output for the address ADDR to FILE. */
1691 print_operand_address (FILE *file
, rtx addr
)
1696 switch (GET_CODE (addr
))
1699 fprintf (file
, "%s", h8_reg_names
[REGNO (addr
)]);
1703 fprintf (file
, "-%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1707 fprintf (file
, "%s+", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1711 fprintf (file
, "+%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1715 fprintf (file
, "%s-", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1719 fprintf (file
, "(");
1721 index
= h8300_get_index (XEXP (addr
, 0), VOIDmode
, &size
);
1722 if (GET_CODE (index
) == REG
)
1725 print_operand_address (file
, XEXP (addr
, 1));
1726 fprintf (file
, ",");
1730 print_operand_address (file
, index
);
1734 print_operand (file
, index
, 'X');
1739 print_operand (file
, index
, 'T');
1744 print_operand (file
, index
, 'S');
1748 /* print_operand_address (file, XEXP (addr, 0)); */
1753 print_operand_address (file
, XEXP (addr
, 0));
1754 fprintf (file
, "+");
1755 print_operand_address (file
, XEXP (addr
, 1));
1757 fprintf (file
, ")");
1762 /* Since the H8/300 only has 16-bit pointers, negative values are also
1763 those >= 32768. This happens for example with pointer minus a
1764 constant. We don't want to turn (char *p - 2) into
1765 (char *p + 65534) because loop unrolling can build upon this
1766 (IE: char *p + 131068). */
1767 int n
= INTVAL (addr
);
1769 n
= (int) (short) n
;
1770 fprintf (file
, "%d", n
);
1775 output_addr_const (file
, addr
);
1780 /* Output all insn addresses and their sizes into the assembly language
1781 output file. This is helpful for debugging whether the length attributes
1782 in the md file are correct. This is not meant to be a user selectable
1786 final_prescan_insn (rtx insn
, rtx
*operand ATTRIBUTE_UNUSED
,
1787 int num_operands ATTRIBUTE_UNUSED
)
1789 /* This holds the last insn address. */
1790 static int last_insn_address
= 0;
1792 const int uid
= INSN_UID (insn
);
1794 if (TARGET_ADDRESSES
)
1796 fprintf (asm_out_file
, "; 0x%x %d\n", INSN_ADDRESSES (uid
),
1797 INSN_ADDRESSES (uid
) - last_insn_address
);
1798 last_insn_address
= INSN_ADDRESSES (uid
);
1802 /* Prepare for an SI sized move. */
1805 h8300_expand_movsi (rtx operands
[])
1807 rtx src
= operands
[1];
1808 rtx dst
= operands
[0];
1809 if (!reload_in_progress
&& !reload_completed
)
1811 if (!register_operand (dst
, GET_MODE (dst
)))
1813 rtx tmp
= gen_reg_rtx (GET_MODE (dst
));
1814 emit_move_insn (tmp
, src
);
1821 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1822 Define the offset between two registers, one to be eliminated, and
1823 the other its replacement, at the start of a routine. */
1826 h8300_initial_elimination_offset (int from
, int to
)
1828 /* The number of bytes that the return address takes on the stack. */
1829 int pc_size
= POINTER_SIZE
/ BITS_PER_UNIT
;
1831 /* The number of bytes that the saved frame pointer takes on the stack. */
1832 int fp_size
= frame_pointer_needed
* UNITS_PER_WORD
;
1834 /* The number of bytes that the saved registers, excluding the frame
1835 pointer, take on the stack. */
1836 int saved_regs_size
= 0;
1838 /* The number of bytes that the locals takes on the stack. */
1839 int frame_size
= round_frame_size (get_frame_size ());
1843 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
1844 if (WORD_REG_USED (regno
))
1845 saved_regs_size
+= UNITS_PER_WORD
;
1847 /* Adjust saved_regs_size because the above loop took the frame
1848 pointer int account. */
1849 saved_regs_size
-= fp_size
;
1853 case HARD_FRAME_POINTER_REGNUM
:
1856 case ARG_POINTER_REGNUM
:
1857 return pc_size
+ fp_size
;
1858 case RETURN_ADDRESS_POINTER_REGNUM
:
1860 case FRAME_POINTER_REGNUM
:
1861 return -saved_regs_size
;
1866 case STACK_POINTER_REGNUM
:
1869 case ARG_POINTER_REGNUM
:
1870 return pc_size
+ saved_regs_size
+ frame_size
;
1871 case RETURN_ADDRESS_POINTER_REGNUM
:
1872 return saved_regs_size
+ frame_size
;
1873 case FRAME_POINTER_REGNUM
:
1885 /* Worker function for RETURN_ADDR_RTX. */
1888 h8300_return_addr_rtx (int count
, rtx frame
)
1893 ret
= gen_rtx_MEM (Pmode
,
1894 gen_rtx_REG (Pmode
, RETURN_ADDRESS_POINTER_REGNUM
));
1895 else if (flag_omit_frame_pointer
)
1898 ret
= gen_rtx_MEM (Pmode
,
1899 memory_address (Pmode
,
1900 plus_constant (frame
, UNITS_PER_WORD
)));
1901 set_mem_alias_set (ret
, get_frame_alias_set ());
1905 /* Update the condition code from the insn. */
1908 notice_update_cc (rtx body
, rtx insn
)
1912 switch (get_attr_cc (insn
))
1915 /* Insn does not affect CC at all. */
1919 /* Insn does not change CC, but the 0'th operand has been changed. */
1920 if (cc_status
.value1
!= 0
1921 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value1
))
1922 cc_status
.value1
= 0;
1923 if (cc_status
.value2
!= 0
1924 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value2
))
1925 cc_status
.value2
= 0;
1929 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1930 The V flag is unusable. The C flag may or may not be known but
1931 that's ok because alter_cond will change tests to use EQ/NE. */
1933 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
1934 set
= single_set (insn
);
1935 cc_status
.value1
= SET_SRC (set
);
1936 if (SET_DEST (set
) != cc0_rtx
)
1937 cc_status
.value2
= SET_DEST (set
);
1941 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1942 The C flag may or may not be known but that's ok because
1943 alter_cond will change tests to use EQ/NE. */
1945 cc_status
.flags
|= CC_NO_CARRY
;
1946 set
= single_set (insn
);
1947 cc_status
.value1
= SET_SRC (set
);
1948 if (SET_DEST (set
) != cc0_rtx
)
1950 /* If the destination is STRICT_LOW_PART, strip off
1952 if (GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
1953 cc_status
.value2
= XEXP (SET_DEST (set
), 0);
1955 cc_status
.value2
= SET_DEST (set
);
1960 /* The insn is a compare instruction. */
1962 cc_status
.value1
= SET_SRC (body
);
1966 /* Insn doesn't leave CC in a usable state. */
1972 /* Given that X occurs in an address of the form (plus X constant),
1973 return the part of X that is expected to be a register. There are
1974 four kinds of addressing mode to recognize:
1981 If SIZE is nonnull, and the address is one of the last three forms,
1982 set *SIZE to the index multiplication factor. Set it to 0 for
1983 plain @(dd,Rn) addresses.
1985 MODE is the mode of the value being accessed. It can be VOIDmode
1986 if the address is known to be valid, but its mode is unknown. */
1989 h8300_get_index (rtx x
, enum machine_mode mode
, int *size
)
1996 factor
= (mode
== VOIDmode
? 0 : GET_MODE_SIZE (mode
));
1999 && (mode
== VOIDmode
2000 || GET_MODE_CLASS (mode
) == MODE_INT
2001 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
2003 if (factor
<= 1 && GET_CODE (x
) == ZERO_EXTEND
)
2005 /* When accessing byte-sized values, the index can be
2006 a zero-extended QImode or HImode register. */
2007 *size
= GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)));
2012 /* We're looking for addresses of the form:
2015 or (mult (zero_extend X) I)
2017 where I is the size of the operand being accessed.
2018 The canonical form of the second expression is:
2020 (and (mult (subreg X) I) J)
2022 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2025 if (GET_CODE (x
) == AND
2026 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2028 || INTVAL (XEXP (x
, 1)) == 0xff * factor
2029 || INTVAL (XEXP (x
, 1)) == 0xffff * factor
))
2031 index
= XEXP (x
, 0);
2032 *size
= (INTVAL (XEXP (x
, 1)) >= 0xffff ? 2 : 1);
2040 if (GET_CODE (index
) == MULT
2041 && GET_CODE (XEXP (index
, 1)) == CONST_INT
2042 && (factor
== 0 || factor
== INTVAL (XEXP (index
, 1))))
2043 return XEXP (index
, 0);
2050 static const h8300_length_table addb_length_table
=
2052 /* #xx Rs @aa @Rs @xx */
2053 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2054 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2055 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2056 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2059 static const h8300_length_table addw_length_table
=
2061 /* #xx Rs @aa @Rs @xx */
2062 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2063 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2064 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2065 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2068 static const h8300_length_table addl_length_table
=
2070 /* #xx Rs @aa @Rs @xx */
2071 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2072 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2073 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2074 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2077 #define logicb_length_table addb_length_table
2078 #define logicw_length_table addw_length_table
2080 static const h8300_length_table logicl_length_table
=
2082 /* #xx Rs @aa @Rs @xx */
2083 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2084 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2085 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2086 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2089 static const h8300_length_table movb_length_table
=
2091 /* #xx Rs @aa @Rs @xx */
2092 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2093 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2094 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2095 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2098 #define movw_length_table movb_length_table
2100 static const h8300_length_table movl_length_table
=
2102 /* #xx Rs @aa @Rs @xx */
2103 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2104 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2105 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2106 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2109 /* Return the size of the given address or displacement constant. */
2112 h8300_constant_length (rtx constant
)
2114 /* Check for (@d:16,Reg). */
2115 if (GET_CODE (constant
) == CONST_INT
2116 && IN_RANGE (INTVAL (constant
), -0x8000, 0x7fff))
2119 /* Check for (@d:16,Reg) in cases where the displacement is
2120 an absolute address. */
2121 if (Pmode
== HImode
|| h8300_tiny_constant_address_p (constant
))
2127 /* Return the size of a displacement field in address ADDR, which should
2128 have the form (plus X constant). SIZE is the number of bytes being
2132 h8300_displacement_length (rtx addr
, int size
)
2136 offset
= XEXP (addr
, 1);
2138 /* Check for @(d:2,Reg). */
2139 if (register_operand (XEXP (addr
, 0), VOIDmode
)
2140 && GET_CODE (offset
) == CONST_INT
2141 && (INTVAL (offset
) == size
2142 || INTVAL (offset
) == size
* 2
2143 || INTVAL (offset
) == size
* 3))
2146 return h8300_constant_length (offset
);
2149 /* Store the class of operand OP in *CLASS and return the length of any
2150 extra operand fields. SIZE is the number of bytes in OP. CLASS
2151 can be null if only the length is needed. */
2154 h8300_classify_operand (rtx op
, int size
, enum h8300_operand_class
*class)
2156 enum h8300_operand_class dummy
;
2161 if (CONSTANT_P (op
))
2163 *class = H8OP_IMMEDIATE
;
2165 /* Byte-sized immediates are stored in the opcode fields. */
2169 /* If this is a 32-bit instruction, see whether the constant
2170 will fit into a 16-bit immediate field. */
2173 && GET_CODE (op
) == CONST_INT
2174 && IN_RANGE (INTVAL (op
), 0, 0xffff))
2179 else if (GET_CODE (op
) == MEM
)
2182 if (CONSTANT_P (op
))
2184 *class = H8OP_MEM_ABSOLUTE
;
2185 return h8300_constant_length (op
);
2187 else if (GET_CODE (op
) == PLUS
&& CONSTANT_P (XEXP (op
, 1)))
2189 *class = H8OP_MEM_COMPLEX
;
2190 return h8300_displacement_length (op
, size
);
2192 else if (GET_RTX_CLASS (GET_CODE (op
)) == RTX_AUTOINC
)
2194 *class = H8OP_MEM_COMPLEX
;
2197 else if (register_operand (op
, VOIDmode
))
2199 *class = H8OP_MEM_BASE
;
2203 gcc_assert (register_operand (op
, VOIDmode
));
2204 *class = H8OP_REGISTER
;
2208 /* Return the length of the instruction described by TABLE given that
2209 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2210 and OP2 must be an h8300_src_operand. */
2213 h8300_length_from_table (rtx op1
, rtx op2
, const h8300_length_table
*table
)
2215 enum h8300_operand_class op1_class
, op2_class
;
2216 unsigned int size
, immediate_length
;
2218 size
= GET_MODE_SIZE (GET_MODE (op1
));
2219 immediate_length
= (h8300_classify_operand (op1
, size
, &op1_class
)
2220 + h8300_classify_operand (op2
, size
, &op2_class
));
2221 return immediate_length
+ (*table
)[op1_class
- 1][op2_class
];
2224 /* Return the length of a unary instruction such as neg or not given that
2225 its operand is OP. */
2228 h8300_unary_length (rtx op
)
2230 enum h8300_operand_class
class;
2231 unsigned int size
, operand_length
;
2233 size
= GET_MODE_SIZE (GET_MODE (op
));
2234 operand_length
= h8300_classify_operand (op
, size
, &class);
2241 return (size
== 4 ? 6 : 4);
2243 case H8OP_MEM_ABSOLUTE
:
2244 return operand_length
+ (size
== 4 ? 6 : 4);
2246 case H8OP_MEM_COMPLEX
:
2247 return operand_length
+ 6;
2254 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2257 h8300_short_immediate_length (rtx op
)
2259 enum h8300_operand_class
class;
2260 unsigned int size
, operand_length
;
2262 size
= GET_MODE_SIZE (GET_MODE (op
));
2263 operand_length
= h8300_classify_operand (op
, size
, &class);
2271 case H8OP_MEM_ABSOLUTE
:
2272 case H8OP_MEM_COMPLEX
:
2273 return 4 + operand_length
;
2280 /* Likewise bitfield load and store instructions. */
2283 h8300_bitfield_length (rtx op
, rtx op2
)
2285 enum h8300_operand_class
class;
2286 unsigned int size
, operand_length
;
2288 if (GET_CODE (op
) == REG
)
2290 gcc_assert (GET_CODE (op
) != REG
);
2292 size
= GET_MODE_SIZE (GET_MODE (op
));
2293 operand_length
= h8300_classify_operand (op
, size
, &class);
2298 case H8OP_MEM_ABSOLUTE
:
2299 case H8OP_MEM_COMPLEX
:
2300 return 4 + operand_length
;
2307 /* Calculate the length of general binary instruction INSN using TABLE. */
2310 h8300_binary_length (rtx insn
, const h8300_length_table
*table
)
2314 set
= single_set (insn
);
2317 if (BINARY_P (SET_SRC (set
)))
2318 return h8300_length_from_table (XEXP (SET_SRC (set
), 0),
2319 XEXP (SET_SRC (set
), 1), table
);
2322 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set
))) == RTX_TERNARY
);
2323 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set
), 1), 0),
2324 XEXP (XEXP (SET_SRC (set
), 1), 1),
2329 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2330 memory reference and either (1) it has the form @(d:16,Rn) or
2331 (2) its address has the code given by INC_CODE. */
2334 h8300_short_move_mem_p (rtx op
, enum rtx_code inc_code
)
2339 if (GET_CODE (op
) != MEM
)
2342 addr
= XEXP (op
, 0);
2343 size
= GET_MODE_SIZE (GET_MODE (op
));
2344 if (size
!= 1 && size
!= 2)
2347 return (GET_CODE (addr
) == inc_code
2348 || (GET_CODE (addr
) == PLUS
2349 && GET_CODE (XEXP (addr
, 0)) == REG
2350 && h8300_displacement_length (addr
, size
) == 2));
2353 /* Calculate the length of move instruction INSN using the given length
2354 table. Although the tables are correct for most cases, there is some
2355 irregularity in the length of mov.b and mov.w. The following forms:
2362 are two bytes shorter than most other "mov Rs, @complex" or
2363 "mov @complex,Rd" combinations. */
2366 h8300_move_length (rtx
*operands
, const h8300_length_table
*table
)
2370 size
= h8300_length_from_table (operands
[0], operands
[1], table
);
2371 if (REG_P (operands
[0]) && h8300_short_move_mem_p (operands
[1], POST_INC
))
2373 if (REG_P (operands
[1]) && h8300_short_move_mem_p (operands
[0], PRE_DEC
))
2378 /* Return the length of a mova instruction with the given operands.
2379 DEST is the register destination, SRC is the source address and
2380 OFFSET is the 16-bit or 32-bit displacement. */
2383 h8300_mova_length (rtx dest
, rtx src
, rtx offset
)
2388 + h8300_constant_length (offset
)
2389 + h8300_classify_operand (src
, GET_MODE_SIZE (GET_MODE (src
)), 0));
2390 if (!REG_P (dest
) || !REG_P (src
) || REGNO (src
) != REGNO (dest
))
2395 /* Compute the length of INSN based on its length_table attribute.
2396 OPERANDS is the array of its operands. */
2399 h8300_insn_length_from_table (rtx insn
, rtx
* operands
)
2401 switch (get_attr_length_table (insn
))
2403 case LENGTH_TABLE_NONE
:
2406 case LENGTH_TABLE_ADDB
:
2407 return h8300_binary_length (insn
, &addb_length_table
);
2409 case LENGTH_TABLE_ADDW
:
2410 return h8300_binary_length (insn
, &addw_length_table
);
2412 case LENGTH_TABLE_ADDL
:
2413 return h8300_binary_length (insn
, &addl_length_table
);
2415 case LENGTH_TABLE_LOGICB
:
2416 return h8300_binary_length (insn
, &logicb_length_table
);
2418 case LENGTH_TABLE_MOVB
:
2419 return h8300_move_length (operands
, &movb_length_table
);
2421 case LENGTH_TABLE_MOVW
:
2422 return h8300_move_length (operands
, &movw_length_table
);
2424 case LENGTH_TABLE_MOVL
:
2425 return h8300_move_length (operands
, &movl_length_table
);
2427 case LENGTH_TABLE_MOVA
:
2428 return h8300_mova_length (operands
[0], operands
[1], operands
[2]);
2430 case LENGTH_TABLE_MOVA_ZERO
:
2431 return h8300_mova_length (operands
[0], operands
[1], const0_rtx
);
2433 case LENGTH_TABLE_UNARY
:
2434 return h8300_unary_length (operands
[0]);
2436 case LENGTH_TABLE_MOV_IMM4
:
2437 return 2 + h8300_classify_operand (operands
[0], 0, 0);
2439 case LENGTH_TABLE_SHORT_IMMEDIATE
:
2440 return h8300_short_immediate_length (operands
[0]);
2442 case LENGTH_TABLE_BITFIELD
:
2443 return h8300_bitfield_length (operands
[0], operands
[1]);
2445 case LENGTH_TABLE_BITBRANCH
:
2446 return h8300_bitfield_length (operands
[1], operands
[2]) - 2;
2453 /* Return true if LHS and RHS are memory references that can be mapped
2454 to the same h8sx assembly operand. LHS appears as the destination of
2455 an instruction and RHS appears as a source.
2457 Three cases are allowed:
2459 - RHS is @+Rn or @-Rn, LHS is @Rn
2460 - RHS is @Rn, LHS is @Rn+ or @Rn-
2461 - RHS and LHS have the same address and neither has side effects. */
2464 h8sx_mergeable_memrefs_p (rtx lhs
, rtx rhs
)
2466 if (GET_CODE (rhs
) == MEM
&& GET_CODE (lhs
) == MEM
)
2468 rhs
= XEXP (rhs
, 0);
2469 lhs
= XEXP (lhs
, 0);
2471 if (GET_CODE (rhs
) == PRE_INC
|| GET_CODE (rhs
) == PRE_DEC
)
2472 return rtx_equal_p (XEXP (rhs
, 0), lhs
);
2474 if (GET_CODE (lhs
) == POST_INC
|| GET_CODE (lhs
) == POST_DEC
)
2475 return rtx_equal_p (rhs
, XEXP (lhs
, 0));
2477 if (rtx_equal_p (rhs
, lhs
))
2483 /* Return true if OPERANDS[1] can be mapped to the same assembly
2484 operand as OPERANDS[0]. */
2487 h8300_operands_match_p (rtx
*operands
)
2489 if (register_operand (operands
[0], VOIDmode
)
2490 && register_operand (operands
[1], VOIDmode
))
2493 if (h8sx_mergeable_memrefs_p (operands
[0], operands
[1]))
2499 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2500 region DEST. The two regions do not overlap and have the common
2501 alignment given by ALIGNMENT. Return true on success.
2503 Using movmd for variable-length moves seems to involve some
2504 complex trade-offs. For instance:
2506 - Preparing for a movmd instruction is similar to preparing
2507 for a memcpy. The main difference is that the arguments
2508 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2510 - Since movmd clobbers the frame pointer, we need to save
2511 and restore it somehow when frame_pointer_needed. This can
2512 sometimes make movmd sequences longer than calls to memcpy().
2514 - The counter register is 16 bits, so the instruction is only
2515 suitable for variable-length moves when sizeof (size_t) == 2.
2516 That's only true in normal mode.
2518 - We will often lack static alignment information. Falling back
2519 on movmd.b would likely be slower than calling memcpy(), at least
2522 This function therefore only uses movmd when the length is a
2523 known constant, and only then if -fomit-frame-pointer is in
2524 effect or if we're not optimizing for size.
2526 At the moment the function uses movmd for all in-range constants,
2527 but it might be better to fall back on memcpy() for large moves
2528 if ALIGNMENT == 1. */
2531 h8sx_emit_movmd (rtx dest
, rtx src
, rtx length
,
2532 HOST_WIDE_INT alignment
)
2534 if (!flag_omit_frame_pointer
&& optimize_size
)
2537 if (GET_CODE (length
) == CONST_INT
)
2539 rtx dest_reg
, src_reg
, first_dest
, first_src
;
2543 /* Use movmd.l if the alignment allows it, otherwise fall back
2545 factor
= (alignment
>= 2 ? 4 : 1);
2547 /* Make sure the length is within range. We can handle counter
2548 values up to 65536, although HImode truncation will make
2549 the count appear negative in rtl dumps. */
2550 n
= INTVAL (length
);
2551 if (n
<= 0 || n
/ factor
> 65536)
2554 /* Create temporary registers for the source and destination
2555 pointers. Initialize them to the start of each region. */
2556 dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
2557 src_reg
= copy_addr_to_reg (XEXP (src
, 0));
2559 /* Create references to the movmd source and destination blocks. */
2560 first_dest
= replace_equiv_address (dest
, dest_reg
);
2561 first_src
= replace_equiv_address (src
, src_reg
);
2563 set_mem_size (first_dest
, GEN_INT (n
& -factor
));
2564 set_mem_size (first_src
, GEN_INT (n
& -factor
));
2566 length
= copy_to_mode_reg (HImode
, gen_int_mode (n
/ factor
, HImode
));
2567 emit_insn (gen_movmd (first_dest
, first_src
, length
, GEN_INT (factor
)));
2569 if ((n
& -factor
) != n
)
2571 /* Move SRC and DEST past the region we just copied.
2572 This is done to update the memory attributes. */
2573 dest
= adjust_address (dest
, BLKmode
, n
& -factor
);
2574 src
= adjust_address (src
, BLKmode
, n
& -factor
);
2576 /* Replace the addresses with the source and destination
2577 registers, which movmd has left with the right values. */
2578 dest
= replace_equiv_address (dest
, dest_reg
);
2579 src
= replace_equiv_address (src
, src_reg
);
2581 /* Mop up the left-over bytes. */
2583 emit_move_insn (adjust_address (dest
, HImode
, 0),
2584 adjust_address (src
, HImode
, 0));
2586 emit_move_insn (adjust_address (dest
, QImode
, n
& 2),
2587 adjust_address (src
, QImode
, n
& 2));
2594 /* Move ADDR into er6 after pushing its old value onto the stack. */
2597 h8300_swap_into_er6 (rtx addr
)
2599 push (HARD_FRAME_POINTER_REGNUM
);
2600 emit_move_insn (hard_frame_pointer_rtx
, addr
);
2601 if (REGNO (addr
) == SP_REG
)
2602 emit_move_insn (hard_frame_pointer_rtx
,
2603 plus_constant (hard_frame_pointer_rtx
,
2604 GET_MODE_SIZE (word_mode
)));
2607 /* Move the current value of er6 into ADDR and pop its old value
2611 h8300_swap_out_of_er6 (rtx addr
)
2613 if (REGNO (addr
) != SP_REG
)
2614 emit_move_insn (addr
, hard_frame_pointer_rtx
);
2615 pop (HARD_FRAME_POINTER_REGNUM
);
2618 /* Return the length of mov instruction. */
2621 compute_mov_length (rtx
*operands
)
2623 /* If the mov instruction involves a memory operand, we compute the
2624 length, assuming the largest addressing mode is used, and then
2625 adjust later in the function. Otherwise, we compute and return
2626 the exact length in one step. */
2627 enum machine_mode mode
= GET_MODE (operands
[0]);
2628 rtx dest
= operands
[0];
2629 rtx src
= operands
[1];
2632 if (GET_CODE (src
) == MEM
)
2633 addr
= XEXP (src
, 0);
2634 else if (GET_CODE (dest
) == MEM
)
2635 addr
= XEXP (dest
, 0);
2641 unsigned int base_length
;
2646 if (addr
== NULL_RTX
)
2649 /* The eightbit addressing is available only in QImode, so
2650 go ahead and take care of it. */
2651 if (h8300_eightbit_constant_address_p (addr
))
2658 if (addr
== NULL_RTX
)
2663 if (src
== const0_rtx
)
2673 if (addr
== NULL_RTX
)
2678 if (GET_CODE (src
) == CONST_INT
)
2680 if (src
== const0_rtx
)
2683 if ((INTVAL (src
) & 0xffff) == 0)
2686 if ((INTVAL (src
) & 0xffff) == 0)
2689 if ((INTVAL (src
) & 0xffff)
2690 == ((INTVAL (src
) >> 16) & 0xffff))
2700 if (addr
== NULL_RTX
)
2705 if (CONST_DOUBLE_OK_FOR_LETTER_P (src
, 'G'))
2718 /* Adjust the length based on the addressing mode used.
2719 Specifically, we subtract the difference between the actual
2720 length and the longest one, which is @(d:16,Rs). For SImode
2721 and SFmode, we double the adjustment because two mov.w are
2722 used to do the job. */
2724 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2725 if (GET_CODE (addr
) == PRE_DEC
2726 || GET_CODE (addr
) == POST_INC
)
2728 if (mode
== QImode
|| mode
== HImode
)
2729 return base_length
- 2;
2731 /* In SImode and SFmode, we use two mov.w instructions, so
2732 double the adjustment. */
2733 return base_length
- 4;
2736 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2737 in SImode and SFmode, the second mov.w involves an address
2738 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2740 if (GET_CODE (addr
) == REG
)
2741 return base_length
- 2;
2747 unsigned int base_length
;
2752 if (addr
== NULL_RTX
)
2755 /* The eightbit addressing is available only in QImode, so
2756 go ahead and take care of it. */
2757 if (h8300_eightbit_constant_address_p (addr
))
2764 if (addr
== NULL_RTX
)
2769 if (src
== const0_rtx
)
2779 if (addr
== NULL_RTX
)
2783 if (REGNO (src
) == MAC_REG
|| REGNO (dest
) == MAC_REG
)
2789 if (GET_CODE (src
) == CONST_INT
)
2791 int val
= INTVAL (src
);
2796 if (val
== (val
& 0x00ff) || val
== (val
& 0xff00))
2799 switch (val
& 0xffffffff)
2820 if (addr
== NULL_RTX
)
2825 if (CONST_DOUBLE_OK_FOR_LETTER_P (src
, 'G'))
2838 /* Adjust the length based on the addressing mode used.
2839 Specifically, we subtract the difference between the actual
2840 length and the longest one, which is @(d:24,ERs). */
2842 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2843 if (GET_CODE (addr
) == PRE_DEC
2844 || GET_CODE (addr
) == POST_INC
)
2845 return base_length
- 6;
2847 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2848 if (GET_CODE (addr
) == REG
)
2849 return base_length
- 6;
2851 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2853 if (GET_CODE (addr
) == PLUS
2854 && GET_CODE (XEXP (addr
, 0)) == REG
2855 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
2856 && INTVAL (XEXP (addr
, 1)) > -32768
2857 && INTVAL (XEXP (addr
, 1)) < 32767)
2858 return base_length
- 4;
2860 /* @aa:16 is 4 bytes shorter than the longest. */
2861 if (h8300_tiny_constant_address_p (addr
))
2862 return base_length
- 4;
2864 /* @aa:24 is 2 bytes shorter than the longest. */
2865 if (CONSTANT_P (addr
))
2866 return base_length
- 2;
2872 /* Output an addition insn. */
2875 output_plussi (rtx
*operands
)
2877 enum machine_mode mode
= GET_MODE (operands
[0]);
2879 gcc_assert (mode
== SImode
);
2883 if (GET_CODE (operands
[2]) == REG
)
2884 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2886 if (GET_CODE (operands
[2]) == CONST_INT
)
2888 HOST_WIDE_INT n
= INTVAL (operands
[2]);
2890 if ((n
& 0xffffff) == 0)
2891 return "add\t%z2,%z0";
2892 if ((n
& 0xffff) == 0)
2893 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2894 if ((n
& 0xff) == 0)
2895 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2898 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2902 if (GET_CODE (operands
[2]) == CONST_INT
2903 && register_operand (operands
[1], VOIDmode
))
2905 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
2907 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
2908 return "add.l\t%S2,%S0";
2909 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
2910 return "sub.l\t%G2,%S0";
2912 /* See if we can finish with 2 bytes. */
2914 switch ((unsigned int) intval
& 0xffffffff)
2919 return "adds\t%2,%S0";
2924 return "subs\t%G2,%S0";
2928 operands
[2] = GEN_INT (intval
>> 16);
2929 return "inc.w\t%2,%e0";
2933 operands
[2] = GEN_INT (intval
>> 16);
2934 return "dec.w\t%G2,%e0";
2937 /* See if we can finish with 4 bytes. */
2938 if ((intval
& 0xffff) == 0)
2940 operands
[2] = GEN_INT (intval
>> 16);
2941 return "add.w\t%2,%e0";
2945 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
2947 operands
[2] = GEN_INT (-INTVAL (operands
[2]));
2948 return "sub.l\t%S2,%S0";
2950 return "add.l\t%S2,%S0";
2954 /* ??? It would be much easier to add the h8sx stuff if a single function
2955 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
2956 /* Compute the length of an addition insn. */
2959 compute_plussi_length (rtx
*operands
)
2961 enum machine_mode mode
= GET_MODE (operands
[0]);
2963 gcc_assert (mode
== SImode
);
2967 if (GET_CODE (operands
[2]) == REG
)
2970 if (GET_CODE (operands
[2]) == CONST_INT
)
2972 HOST_WIDE_INT n
= INTVAL (operands
[2]);
2974 if ((n
& 0xffffff) == 0)
2976 if ((n
& 0xffff) == 0)
2978 if ((n
& 0xff) == 0)
2986 if (GET_CODE (operands
[2]) == CONST_INT
2987 && register_operand (operands
[1], VOIDmode
))
2989 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
2991 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
2993 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
2996 /* See if we can finish with 2 bytes. */
2998 switch ((unsigned int) intval
& 0xffffffff)
3019 /* See if we can finish with 4 bytes. */
3020 if ((intval
& 0xffff) == 0)
3024 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3025 return h8300_length_from_table (operands
[0],
3026 GEN_INT (-INTVAL (operands
[2])),
3027 &addl_length_table
);
3029 return h8300_length_from_table (operands
[0], operands
[2],
3030 &addl_length_table
);
3035 /* Compute which flag bits are valid after an addition insn. */
3038 compute_plussi_cc (rtx
*operands
)
3040 enum machine_mode mode
= GET_MODE (operands
[0]);
3042 gcc_assert (mode
== SImode
);
3050 if (GET_CODE (operands
[2]) == CONST_INT
3051 && register_operand (operands
[1], VOIDmode
))
3053 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3055 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3057 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3060 /* See if we can finish with 2 bytes. */
3062 switch ((unsigned int) intval
& 0xffffffff)
3067 return CC_NONE_0HIT
;
3072 return CC_NONE_0HIT
;
3083 /* See if we can finish with 4 bytes. */
3084 if ((intval
& 0xffff) == 0)
3092 /* Output a logical insn. */
3095 output_logical_op (enum machine_mode mode
, rtx
*operands
)
3097 /* Figure out the logical op that we need to perform. */
3098 enum rtx_code code
= GET_CODE (operands
[3]);
3099 /* Pretend that every byte is affected if both operands are registers. */
3100 const unsigned HOST_WIDE_INT intval
=
3101 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3102 /* Always use the full instruction if the
3103 first operand is in memory. It is better
3104 to use define_splits to generate the shorter
3105 sequence where valid. */
3106 && register_operand (operands
[1], VOIDmode
)
3107 ? INTVAL (operands
[2]) : 0x55555555);
3108 /* The determinant of the algorithm. If we perform an AND, 0
3109 affects a bit. Otherwise, 1 affects a bit. */
3110 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3111 /* Break up DET into pieces. */
3112 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3113 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3114 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3115 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3116 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3117 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3118 int lower_half_easy_p
= 0;
3119 int upper_half_easy_p
= 0;
3120 /* The name of an insn. */
3142 /* First, see if we can finish with one insn. */
3143 if ((TARGET_H8300H
|| TARGET_H8300S
)
3147 sprintf (insn_buf
, "%s.w\t%%T2,%%T0", opname
);
3148 output_asm_insn (insn_buf
, operands
);
3152 /* Take care of the lower byte. */
3155 sprintf (insn_buf
, "%s\t%%s2,%%s0", opname
);
3156 output_asm_insn (insn_buf
, operands
);
3158 /* Take care of the upper byte. */
3161 sprintf (insn_buf
, "%s\t%%t2,%%t0", opname
);
3162 output_asm_insn (insn_buf
, operands
);
3167 if (TARGET_H8300H
|| TARGET_H8300S
)
3169 /* Determine if the lower half can be taken care of in no more
3171 lower_half_easy_p
= (b0
== 0
3173 || (code
!= IOR
&& w0
== 0xffff));
3175 /* Determine if the upper half can be taken care of in no more
3177 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3178 || (code
== AND
&& w1
== 0xff00));
3181 /* Check if doing everything with one insn is no worse than
3182 using multiple insns. */
3183 if ((TARGET_H8300H
|| TARGET_H8300S
)
3184 && w0
!= 0 && w1
!= 0
3185 && !(lower_half_easy_p
&& upper_half_easy_p
)
3186 && !(code
== IOR
&& w1
== 0xffff
3187 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3189 sprintf (insn_buf
, "%s.l\t%%S2,%%S0", opname
);
3190 output_asm_insn (insn_buf
, operands
);
3194 /* Take care of the lower and upper words individually. For
3195 each word, we try different methods in the order of
3197 1) the special insn (in case of AND or XOR),
3198 2) the word-wise insn, and
3199 3) The byte-wise insn. */
3201 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3202 output_asm_insn ((code
== AND
)
3203 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3205 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3209 sprintf (insn_buf
, "%s.w\t%%f2,%%f0", opname
);
3210 output_asm_insn (insn_buf
, operands
);
3216 sprintf (insn_buf
, "%s\t%%w2,%%w0", opname
);
3217 output_asm_insn (insn_buf
, operands
);
3221 sprintf (insn_buf
, "%s\t%%x2,%%x0", opname
);
3222 output_asm_insn (insn_buf
, operands
);
3227 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3228 output_asm_insn ((code
== AND
)
3229 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3231 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3234 && (w0
& 0x8000) != 0)
3236 output_asm_insn ("exts.l\t%S0", operands
);
3238 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3242 output_asm_insn ("extu.w\t%e0", operands
);
3244 else if (TARGET_H8300H
|| TARGET_H8300S
)
3248 sprintf (insn_buf
, "%s.w\t%%e2,%%e0", opname
);
3249 output_asm_insn (insn_buf
, operands
);
3256 sprintf (insn_buf
, "%s\t%%y2,%%y0", opname
);
3257 output_asm_insn (insn_buf
, operands
);
3261 sprintf (insn_buf
, "%s\t%%z2,%%z0", opname
);
3262 output_asm_insn (insn_buf
, operands
);
3273 /* Compute the length of a logical insn. */
3276 compute_logical_op_length (enum machine_mode mode
, rtx
*operands
)
3278 /* Figure out the logical op that we need to perform. */
3279 enum rtx_code code
= GET_CODE (operands
[3]);
3280 /* Pretend that every byte is affected if both operands are registers. */
3281 const unsigned HOST_WIDE_INT intval
=
3282 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3283 /* Always use the full instruction if the
3284 first operand is in memory. It is better
3285 to use define_splits to generate the shorter
3286 sequence where valid. */
3287 && register_operand (operands
[1], VOIDmode
)
3288 ? INTVAL (operands
[2]) : 0x55555555);
3289 /* The determinant of the algorithm. If we perform an AND, 0
3290 affects a bit. Otherwise, 1 affects a bit. */
3291 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3292 /* Break up DET into pieces. */
3293 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3294 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3295 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3296 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3297 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3298 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3299 int lower_half_easy_p
= 0;
3300 int upper_half_easy_p
= 0;
3302 unsigned int length
= 0;
3307 /* First, see if we can finish with one insn. */
3308 if ((TARGET_H8300H
|| TARGET_H8300S
)
3312 length
= h8300_length_from_table (operands
[1], operands
[2],
3313 &logicw_length_table
);
3317 /* Take care of the lower byte. */
3321 /* Take care of the upper byte. */
3327 if (TARGET_H8300H
|| TARGET_H8300S
)
3329 /* Determine if the lower half can be taken care of in no more
3331 lower_half_easy_p
= (b0
== 0
3333 || (code
!= IOR
&& w0
== 0xffff));
3335 /* Determine if the upper half can be taken care of in no more
3337 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3338 || (code
== AND
&& w1
== 0xff00));
3341 /* Check if doing everything with one insn is no worse than
3342 using multiple insns. */
3343 if ((TARGET_H8300H
|| TARGET_H8300S
)
3344 && w0
!= 0 && w1
!= 0
3345 && !(lower_half_easy_p
&& upper_half_easy_p
)
3346 && !(code
== IOR
&& w1
== 0xffff
3347 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3349 length
= h8300_length_from_table (operands
[1], operands
[2],
3350 &logicl_length_table
);
3354 /* Take care of the lower and upper words individually. For
3355 each word, we try different methods in the order of
3357 1) the special insn (in case of AND or XOR),
3358 2) the word-wise insn, and
3359 3) The byte-wise insn. */
3361 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3365 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3381 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3385 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3388 && (w0
& 0x8000) != 0)
3392 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3398 else if (TARGET_H8300H
|| TARGET_H8300S
)
3419 /* Compute which flag bits are valid after a logical insn. */
3422 compute_logical_op_cc (enum machine_mode mode
, rtx
*operands
)
3424 /* Figure out the logical op that we need to perform. */
3425 enum rtx_code code
= GET_CODE (operands
[3]);
3426 /* Pretend that every byte is affected if both operands are registers. */
3427 const unsigned HOST_WIDE_INT intval
=
3428 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3429 /* Always use the full instruction if the
3430 first operand is in memory. It is better
3431 to use define_splits to generate the shorter
3432 sequence where valid. */
3433 && register_operand (operands
[1], VOIDmode
)
3434 ? INTVAL (operands
[2]) : 0x55555555);
3435 /* The determinant of the algorithm. If we perform an AND, 0
3436 affects a bit. Otherwise, 1 affects a bit. */
3437 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3438 /* Break up DET into pieces. */
3439 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3440 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3441 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3442 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3443 int lower_half_easy_p
= 0;
3444 int upper_half_easy_p
= 0;
3445 /* Condition code. */
3446 enum attr_cc cc
= CC_CLOBBER
;
3451 /* First, see if we can finish with one insn. */
3452 if ((TARGET_H8300H
|| TARGET_H8300S
)
3460 if (TARGET_H8300H
|| TARGET_H8300S
)
3462 /* Determine if the lower half can be taken care of in no more
3464 lower_half_easy_p
= (b0
== 0
3466 || (code
!= IOR
&& w0
== 0xffff));
3468 /* Determine if the upper half can be taken care of in no more
3470 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3471 || (code
== AND
&& w1
== 0xff00));
3474 /* Check if doing everything with one insn is no worse than
3475 using multiple insns. */
3476 if ((TARGET_H8300H
|| TARGET_H8300S
)
3477 && w0
!= 0 && w1
!= 0
3478 && !(lower_half_easy_p
&& upper_half_easy_p
)
3479 && !(code
== IOR
&& w1
== 0xffff
3480 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3486 if ((TARGET_H8300H
|| TARGET_H8300S
)
3489 && (w0
& 0x8000) != 0)
3501 /* Expand a conditional branch. */
3504 h8300_expand_branch (enum rtx_code code
, rtx label
)
3508 tmp
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
3509 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
3510 gen_rtx_LABEL_REF (VOIDmode
, label
),
3512 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
3517 We devote a fair bit of code to getting efficient shifts since we
3518 can only shift one bit at a time on the H8/300 and H8/300H and only
3519 one or two bits at a time on the H8S.
3521 All shift code falls into one of the following ways of
3524 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3525 when a straight line shift is about the same size or smaller than
3528 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3529 off the bits we don't need. This is used when only a few of the
3530 bits in the original value will survive in the shifted value.
3532 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3533 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3534 shifts can be added if the shift count is slightly more than 8 or
3535 16. This case also includes other oddballs that are not worth
3538 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3540 For each shift count, we try to use code that has no trade-off
3541 between code size and speed whenever possible.
3543 If the trade-off is unavoidable, we try to be reasonable.
3544 Specifically, the fastest version is one instruction longer than
3545 the shortest version, we take the fastest version. We also provide
3546 the use a way to switch back to the shortest version with -Os.
3548 For the details of the shift algorithms for various shift counts,
3549 refer to shift_alg_[qhs]i. */
3551 /* Classify a shift with the given mode and code. OP is the shift amount. */
3553 enum h8sx_shift_type
3554 h8sx_classify_shift (enum machine_mode mode
, enum rtx_code code
, rtx op
)
3556 if (!TARGET_H8300SX
)
3557 return H8SX_SHIFT_NONE
;
3563 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3564 if (GET_CODE (op
) != CONST_INT
)
3565 return H8SX_SHIFT_BINARY
;
3567 /* Reject out-of-range shift amounts. */
3568 if (INTVAL (op
) <= 0 || INTVAL (op
) >= GET_MODE_BITSIZE (mode
))
3569 return H8SX_SHIFT_NONE
;
3571 /* Power-of-2 shifts are effectively unary operations. */
3572 if (exact_log2 (INTVAL (op
)) >= 0)
3573 return H8SX_SHIFT_UNARY
;
3575 return H8SX_SHIFT_BINARY
;
3578 if (op
== const1_rtx
|| op
== const2_rtx
)
3579 return H8SX_SHIFT_UNARY
;
3580 return H8SX_SHIFT_NONE
;
3583 if (GET_CODE (op
) == CONST_INT
3584 && (INTVAL (op
) == 1
3586 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 2
3587 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 1))
3588 return H8SX_SHIFT_UNARY
;
3589 return H8SX_SHIFT_NONE
;
3592 return H8SX_SHIFT_NONE
;
3596 /* Return the asm template for a single h8sx shift instruction.
3597 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3598 is the source and OPERANDS[3] is the shift. SUFFIX is the
3599 size suffix ('b', 'w' or 'l') and OPTYPE is the print_operand
3600 prefix for the destination operand. */
3603 output_h8sx_shift (rtx
*operands
, int suffix
, int optype
)
3605 static char buffer
[16];
3608 switch (GET_CODE (operands
[3]))
3624 if (INTVAL (operands
[2]) > 2)
3626 /* This is really a right rotate. */
3627 operands
[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands
[0]))
3628 - INTVAL (operands
[2]));
3636 if (operands
[2] == const1_rtx
)
3637 sprintf (buffer
, "%s.%c\t%%%c0", stem
, suffix
, optype
);
3639 sprintf (buffer
, "%s.%c\t%%X2,%%%c0", stem
, suffix
, optype
);
3643 /* Emit code to do shifts. */
3646 expand_a_shift (enum machine_mode mode
, int code
, rtx operands
[])
3648 switch (h8sx_classify_shift (mode
, code
, operands
[2]))
3650 case H8SX_SHIFT_BINARY
:
3651 operands
[1] = force_reg (mode
, operands
[1]);
3654 case H8SX_SHIFT_UNARY
:
3657 case H8SX_SHIFT_NONE
:
3661 emit_move_insn (operands
[0], operands
[1]);
3663 /* Need a loop to get all the bits we want - we generate the
3664 code at emit time, but need to allocate a scratch reg now. */
3666 emit_insn (gen_rtx_PARALLEL
3669 gen_rtx_SET (VOIDmode
, operands
[0],
3670 gen_rtx_fmt_ee (code
, mode
,
3671 operands
[0], operands
[2])),
3672 gen_rtx_CLOBBER (VOIDmode
,
3673 gen_rtx_SCRATCH (QImode
)))));
3677 /* Symbols of the various modes which can be used as indices. */
3681 QIshift
, HIshift
, SIshift
3684 /* For single bit shift insns, record assembler and what bits of the
3685 condition code are valid afterwards (represented as various CC_FOO
3686 bits, 0 means CC isn't left in a usable state). */
3690 const char *const assembler
;
3694 /* Assembler instruction shift table.
3696 These tables are used to look up the basic shifts.
3697 They are indexed by cpu, shift_type, and mode. */
3699 static const struct shift_insn shift_one
[2][3][3] =
3705 { "shll\t%X0", CC_SET_ZNV
},
3706 { "add.w\t%T0,%T0", CC_SET_ZN
},
3707 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER
}
3709 /* SHIFT_LSHIFTRT */
3711 { "shlr\t%X0", CC_SET_ZNV
},
3712 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3713 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3715 /* SHIFT_ASHIFTRT */
3717 { "shar\t%X0", CC_SET_ZNV
},
3718 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3719 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3726 { "shll.b\t%X0", CC_SET_ZNV
},
3727 { "shll.w\t%T0", CC_SET_ZNV
},
3728 { "shll.l\t%S0", CC_SET_ZNV
}
3730 /* SHIFT_LSHIFTRT */
3732 { "shlr.b\t%X0", CC_SET_ZNV
},
3733 { "shlr.w\t%T0", CC_SET_ZNV
},
3734 { "shlr.l\t%S0", CC_SET_ZNV
}
3736 /* SHIFT_ASHIFTRT */
3738 { "shar.b\t%X0", CC_SET_ZNV
},
3739 { "shar.w\t%T0", CC_SET_ZNV
},
3740 { "shar.l\t%S0", CC_SET_ZNV
}
3745 static const struct shift_insn shift_two
[3][3] =
3749 { "shll.b\t#2,%X0", CC_SET_ZNV
},
3750 { "shll.w\t#2,%T0", CC_SET_ZNV
},
3751 { "shll.l\t#2,%S0", CC_SET_ZNV
}
3753 /* SHIFT_LSHIFTRT */
3755 { "shlr.b\t#2,%X0", CC_SET_ZNV
},
3756 { "shlr.w\t#2,%T0", CC_SET_ZNV
},
3757 { "shlr.l\t#2,%S0", CC_SET_ZNV
}
3759 /* SHIFT_ASHIFTRT */
3761 { "shar.b\t#2,%X0", CC_SET_ZNV
},
3762 { "shar.w\t#2,%T0", CC_SET_ZNV
},
3763 { "shar.l\t#2,%S0", CC_SET_ZNV
}
3767 /* Rotates are organized by which shift they'll be used in implementing.
3768 There's no need to record whether the cc is valid afterwards because
3769 it is the AND insn that will decide this. */
3771 static const char *const rotate_one
[2][3][3] =
3778 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3781 /* SHIFT_LSHIFTRT */
3784 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3787 /* SHIFT_ASHIFTRT */
3790 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3802 /* SHIFT_LSHIFTRT */
3808 /* SHIFT_ASHIFTRT */
3817 static const char *const rotate_two
[3][3] =
3825 /* SHIFT_LSHIFTRT */
3831 /* SHIFT_ASHIFTRT */
3840 /* Shift algorithm. */
3843 /* The number of bits to be shifted by shift1 and shift2. Valid
3844 when ALG is SHIFT_SPECIAL. */
3845 unsigned int remainder
;
3847 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
3848 const char *special
;
3850 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
3851 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3854 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
3855 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3858 /* CC status for SHIFT_INLINE. */
3861 /* CC status for SHIFT_SPECIAL. */
3865 static void get_shift_alg (enum shift_type
,
3866 enum shift_mode
, unsigned int,
3867 struct shift_info
*);
3869 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
3870 best algorithm for doing the shift. The assembler code is stored
3871 in the pointers in INFO. We achieve the maximum efficiency in most
3872 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
3873 SImode in particular have a lot of room to optimize.
3875 We first determine the strategy of the shift algorithm by a table
3876 lookup. If that tells us to use a hand crafted assembly code, we
3877 go into the big switch statement to find what that is. Otherwise,
3878 we resort to a generic way, such as inlining. In either case, the
3879 result is returned through INFO. */
3882 get_shift_alg (enum shift_type shift_type
, enum shift_mode shift_mode
,
3883 unsigned int count
, struct shift_info
*info
)
3887 /* Find the target CPU. */
3890 else if (TARGET_H8300H
)
3895 /* Find the shift algorithm. */
3896 info
->alg
= SHIFT_LOOP
;
3900 if (count
< GET_MODE_BITSIZE (QImode
))
3901 info
->alg
= shift_alg_qi
[cpu
][shift_type
][count
];
3905 if (count
< GET_MODE_BITSIZE (HImode
))
3906 info
->alg
= shift_alg_hi
[cpu
][shift_type
][count
];
3910 if (count
< GET_MODE_BITSIZE (SImode
))
3911 info
->alg
= shift_alg_si
[cpu
][shift_type
][count
];
3918 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
3922 info
->remainder
= count
;
3926 /* It is up to the caller to know that looping clobbers cc. */
3927 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
3928 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
3929 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
3933 info
->shift1
= rotate_one
[cpu_type
][shift_type
][shift_mode
];
3934 info
->shift2
= rotate_two
[shift_type
][shift_mode
];
3935 info
->cc_inline
= CC_CLOBBER
;
3939 /* REMAINDER is 0 for most cases, so initialize it to 0. */
3940 info
->remainder
= 0;
3941 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
3942 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
3943 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
3944 info
->cc_special
= CC_CLOBBER
;
3948 /* Here we only deal with SHIFT_SPECIAL. */
3952 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
3953 through the entire value. */
3954 gcc_assert (shift_type
== SHIFT_ASHIFTRT
&& count
== 7);
3955 info
->special
= "shll\t%X0\n\tsubx\t%X0,%X0";
3965 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
3967 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
3969 case SHIFT_LSHIFTRT
:
3971 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
3973 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
3975 case SHIFT_ASHIFTRT
:
3976 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
3980 else if ((8 <= count
&& count
<= 13)
3981 || (TARGET_H8300S
&& count
== 14))
3983 info
->remainder
= count
- 8;
3988 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
3990 case SHIFT_LSHIFTRT
:
3993 info
->special
= "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
3994 info
->shift1
= "shlr.b\t%s0";
3995 info
->cc_inline
= CC_SET_ZNV
;
3999 info
->special
= "mov.b\t%t0,%s0\n\textu.w\t%T0";
4000 info
->cc_special
= CC_SET_ZNV
;
4003 case SHIFT_ASHIFTRT
:
4006 info
->special
= "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4007 info
->shift1
= "shar.b\t%s0";
4011 info
->special
= "mov.b\t%t0,%s0\n\texts.w\t%T0";
4012 info
->cc_special
= CC_SET_ZNV
;
4017 else if (count
== 14)
4023 info
->special
= "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4025 case SHIFT_LSHIFTRT
:
4027 info
->special
= "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4029 case SHIFT_ASHIFTRT
:
4031 info
->special
= "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4032 else if (TARGET_H8300H
)
4034 info
->special
= "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4035 info
->cc_special
= CC_SET_ZNV
;
4037 else /* TARGET_H8300S */
4042 else if (count
== 15)
4047 info
->special
= "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4049 case SHIFT_LSHIFTRT
:
4050 info
->special
= "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4052 case SHIFT_ASHIFTRT
:
4053 info
->special
= "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4060 if (TARGET_H8300
&& 8 <= count
&& count
<= 9)
4062 info
->remainder
= count
- 8;
4067 info
->special
= "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4069 case SHIFT_LSHIFTRT
:
4070 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4071 info
->shift1
= "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4073 case SHIFT_ASHIFTRT
:
4074 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4078 else if (count
== 8 && !TARGET_H8300
)
4083 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4085 case SHIFT_LSHIFTRT
:
4086 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4088 case SHIFT_ASHIFTRT
:
4089 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4093 else if (count
== 15 && TARGET_H8300
)
4099 case SHIFT_LSHIFTRT
:
4100 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4102 case SHIFT_ASHIFTRT
:
4103 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4107 else if (count
== 15 && !TARGET_H8300
)
4112 info
->special
= "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4113 info
->cc_special
= CC_SET_ZNV
;
4115 case SHIFT_LSHIFTRT
:
4116 info
->special
= "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4117 info
->cc_special
= CC_SET_ZNV
;
4119 case SHIFT_ASHIFTRT
:
4123 else if ((TARGET_H8300
&& 16 <= count
&& count
<= 20)
4124 || (TARGET_H8300H
&& 16 <= count
&& count
<= 19)
4125 || (TARGET_H8300S
&& 16 <= count
&& count
<= 21))
4127 info
->remainder
= count
- 16;
4132 info
->special
= "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4134 info
->shift1
= "add.w\t%e0,%e0";
4136 case SHIFT_LSHIFTRT
:
4139 info
->special
= "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4140 info
->shift1
= "shlr\t%x0\n\trotxr\t%w0";
4144 info
->special
= "mov.w\t%e0,%f0\n\textu.l\t%S0";
4145 info
->cc_special
= CC_SET_ZNV
;
4148 case SHIFT_ASHIFTRT
:
4151 info
->special
= "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4152 info
->shift1
= "shar\t%x0\n\trotxr\t%w0";
4156 info
->special
= "mov.w\t%e0,%f0\n\texts.l\t%S0";
4157 info
->cc_special
= CC_SET_ZNV
;
4162 else if (TARGET_H8300
&& 24 <= count
&& count
<= 28)
4164 info
->remainder
= count
- 24;
4169 info
->special
= "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4170 info
->shift1
= "shll.b\t%z0";
4171 info
->cc_inline
= CC_SET_ZNV
;
4173 case SHIFT_LSHIFTRT
:
4174 info
->special
= "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4175 info
->shift1
= "shlr.b\t%w0";
4176 info
->cc_inline
= CC_SET_ZNV
;
4178 case SHIFT_ASHIFTRT
:
4179 info
->special
= "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
4180 info
->shift1
= "shar.b\t%w0";
4181 info
->cc_inline
= CC_SET_ZNV
;
4185 else if ((TARGET_H8300H
&& count
== 24)
4186 || (TARGET_H8300S
&& 24 <= count
&& count
<= 25))
4188 info
->remainder
= count
- 24;
4193 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4195 case SHIFT_LSHIFTRT
:
4196 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4197 info
->cc_special
= CC_SET_ZNV
;
4199 case SHIFT_ASHIFTRT
:
4200 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4201 info
->cc_special
= CC_SET_ZNV
;
4205 else if (!TARGET_H8300
&& count
== 28)
4211 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4213 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4215 case SHIFT_LSHIFTRT
:
4218 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4219 info
->cc_special
= CC_SET_ZNV
;
4222 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4224 case SHIFT_ASHIFTRT
:
4228 else if (!TARGET_H8300
&& count
== 29)
4234 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4236 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4238 case SHIFT_LSHIFTRT
:
4241 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4242 info
->cc_special
= CC_SET_ZNV
;
4246 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4247 info
->cc_special
= CC_SET_ZNV
;
4250 case SHIFT_ASHIFTRT
:
4254 else if (!TARGET_H8300
&& count
== 30)
4260 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4262 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4264 case SHIFT_LSHIFTRT
:
4266 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4268 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4270 case SHIFT_ASHIFTRT
:
4274 else if (count
== 31)
4281 info
->special
= "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4283 case SHIFT_LSHIFTRT
:
4284 info
->special
= "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4286 case SHIFT_ASHIFTRT
:
4287 info
->special
= "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4296 info
->special
= "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4297 info
->cc_special
= CC_SET_ZNV
;
4299 case SHIFT_LSHIFTRT
:
4300 info
->special
= "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4301 info
->cc_special
= CC_SET_ZNV
;
4303 case SHIFT_ASHIFTRT
:
4304 info
->special
= "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4305 info
->cc_special
= CC_SET_ZNV
;
4318 info
->shift2
= NULL
;
4321 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4322 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4325 h8300_shift_needs_scratch_p (int count
, enum machine_mode mode
)
4330 if (GET_MODE_BITSIZE (mode
) <= count
)
4333 /* Find out the target CPU. */
4336 else if (TARGET_H8300H
)
4341 /* Find the shift algorithm. */
4345 a
= shift_alg_qi
[cpu
][SHIFT_ASHIFT
][count
];
4346 lr
= shift_alg_qi
[cpu
][SHIFT_LSHIFTRT
][count
];
4347 ar
= shift_alg_qi
[cpu
][SHIFT_ASHIFTRT
][count
];
4351 a
= shift_alg_hi
[cpu
][SHIFT_ASHIFT
][count
];
4352 lr
= shift_alg_hi
[cpu
][SHIFT_LSHIFTRT
][count
];
4353 ar
= shift_alg_hi
[cpu
][SHIFT_ASHIFTRT
][count
];
4357 a
= shift_alg_si
[cpu
][SHIFT_ASHIFT
][count
];
4358 lr
= shift_alg_si
[cpu
][SHIFT_LSHIFTRT
][count
];
4359 ar
= shift_alg_si
[cpu
][SHIFT_ASHIFTRT
][count
];
4366 /* On H8/300H, count == 8 uses a scratch register. */
4367 return (a
== SHIFT_LOOP
|| lr
== SHIFT_LOOP
|| ar
== SHIFT_LOOP
4368 || (TARGET_H8300H
&& mode
== SImode
&& count
== 8));
4371 /* Output the assembler code for doing shifts. */
4374 output_a_shift (rtx
*operands
)
4376 static int loopend_lab
;
4377 rtx shift
= operands
[3];
4378 enum machine_mode mode
= GET_MODE (shift
);
4379 enum rtx_code code
= GET_CODE (shift
);
4380 enum shift_type shift_type
;
4381 enum shift_mode shift_mode
;
4382 struct shift_info info
;
4390 shift_mode
= QIshift
;
4393 shift_mode
= HIshift
;
4396 shift_mode
= SIshift
;
4405 shift_type
= SHIFT_ASHIFTRT
;
4408 shift_type
= SHIFT_LSHIFTRT
;
4411 shift_type
= SHIFT_ASHIFT
;
4417 /* This case must be taken care of by one of the two splitters
4418 that convert a variable shift into a loop. */
4419 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4421 n
= INTVAL (operands
[2]);
4423 /* If the count is negative, make it 0. */
4426 /* If the count is too big, truncate it.
4427 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4428 do the intuitive thing. */
4429 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4430 n
= GET_MODE_BITSIZE (mode
);
4432 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4437 output_asm_insn (info
.special
, operands
);
4443 /* Emit two bit shifts first. */
4444 if (info
.shift2
!= NULL
)
4446 for (; n
> 1; n
-= 2)
4447 output_asm_insn (info
.shift2
, operands
);
4450 /* Now emit one bit shifts for any residual. */
4452 output_asm_insn (info
.shift1
, operands
);
4457 int m
= GET_MODE_BITSIZE (mode
) - n
;
4458 const int mask
= (shift_type
== SHIFT_ASHIFT
4459 ? ((1 << m
) - 1) << n
4463 /* Not all possibilities of rotate are supported. They shouldn't
4464 be generated, but let's watch for 'em. */
4465 gcc_assert (info
.shift1
);
4467 /* Emit two bit rotates first. */
4468 if (info
.shift2
!= NULL
)
4470 for (; m
> 1; m
-= 2)
4471 output_asm_insn (info
.shift2
, operands
);
4474 /* Now single bit rotates for any residual. */
4476 output_asm_insn (info
.shift1
, operands
);
4478 /* Now mask off the high bits. */
4482 sprintf (insn_buf
, "and\t#%d,%%X0", mask
);
4486 gcc_assert (TARGET_H8300H
|| TARGET_H8300S
);
4487 sprintf (insn_buf
, "and.w\t#%d,%%T0", mask
);
4494 output_asm_insn (insn_buf
, operands
);
4499 /* A loop to shift by a "large" constant value.
4500 If we have shift-by-2 insns, use them. */
4501 if (info
.shift2
!= NULL
)
4503 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
/ 2,
4504 names_big
[REGNO (operands
[4])]);
4505 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4506 output_asm_insn (info
.shift2
, operands
);
4507 output_asm_insn ("add #0xff,%X4", operands
);
4508 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4510 output_asm_insn (info
.shift1
, operands
);
4514 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
,
4515 names_big
[REGNO (operands
[4])]);
4516 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4517 output_asm_insn (info
.shift1
, operands
);
4518 output_asm_insn ("add #0xff,%X4", operands
);
4519 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4528 /* Count the number of assembly instructions in a string TEMPLATE. */
4531 h8300_asm_insn_count (const char *template)
4533 unsigned int count
= 1;
4535 for (; *template; template++)
4536 if (*template == '\n')
4542 /* Compute the length of a shift insn. */
4545 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4547 rtx shift
= operands
[3];
4548 enum machine_mode mode
= GET_MODE (shift
);
4549 enum rtx_code code
= GET_CODE (shift
);
4550 enum shift_type shift_type
;
4551 enum shift_mode shift_mode
;
4552 struct shift_info info
;
4553 unsigned int wlength
= 0;
4558 shift_mode
= QIshift
;
4561 shift_mode
= HIshift
;
4564 shift_mode
= SIshift
;
4573 shift_type
= SHIFT_ASHIFTRT
;
4576 shift_type
= SHIFT_LSHIFTRT
;
4579 shift_type
= SHIFT_ASHIFT
;
4585 if (GET_CODE (operands
[2]) != CONST_INT
)
4587 /* Get the assembler code to do one shift. */
4588 get_shift_alg (shift_type
, shift_mode
, 1, &info
);
4590 return (4 + h8300_asm_insn_count (info
.shift1
)) * 2;
4594 int n
= INTVAL (operands
[2]);
4596 /* If the count is negative, make it 0. */
4599 /* If the count is too big, truncate it.
4600 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4601 do the intuitive thing. */
4602 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4603 n
= GET_MODE_BITSIZE (mode
);
4605 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4610 wlength
+= h8300_asm_insn_count (info
.special
);
4612 /* Every assembly instruction used in SHIFT_SPECIAL case
4613 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4614 see xor.l, we just pretend that xor.l counts as two insns
4615 so that the insn length will be computed correctly. */
4616 if (strstr (info
.special
, "xor.l") != NULL
)
4624 if (info
.shift2
!= NULL
)
4626 wlength
+= h8300_asm_insn_count (info
.shift2
) * (n
/ 2);
4630 wlength
+= h8300_asm_insn_count (info
.shift1
) * n
;
4636 int m
= GET_MODE_BITSIZE (mode
) - n
;
4638 /* Not all possibilities of rotate are supported. They shouldn't
4639 be generated, but let's watch for 'em. */
4640 gcc_assert (info
.shift1
);
4642 if (info
.shift2
!= NULL
)
4644 wlength
+= h8300_asm_insn_count (info
.shift2
) * (m
/ 2);
4648 wlength
+= h8300_asm_insn_count (info
.shift1
) * m
;
4650 /* Now mask off the high bits. */
4660 gcc_assert (!TARGET_H8300
);
4670 /* A loop to shift by a "large" constant value.
4671 If we have shift-by-2 insns, use them. */
4672 if (info
.shift2
!= NULL
)
4674 wlength
+= 3 + h8300_asm_insn_count (info
.shift2
);
4676 wlength
+= h8300_asm_insn_count (info
.shift1
);
4680 wlength
+= 3 + h8300_asm_insn_count (info
.shift1
);
4690 /* Compute which flag bits are valid after a shift insn. */
4693 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4695 rtx shift
= operands
[3];
4696 enum machine_mode mode
= GET_MODE (shift
);
4697 enum rtx_code code
= GET_CODE (shift
);
4698 enum shift_type shift_type
;
4699 enum shift_mode shift_mode
;
4700 struct shift_info info
;
4706 shift_mode
= QIshift
;
4709 shift_mode
= HIshift
;
4712 shift_mode
= SIshift
;
4721 shift_type
= SHIFT_ASHIFTRT
;
4724 shift_type
= SHIFT_LSHIFTRT
;
4727 shift_type
= SHIFT_ASHIFT
;
4733 /* This case must be taken care of by one of the two splitters
4734 that convert a variable shift into a loop. */
4735 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4737 n
= INTVAL (operands
[2]);
4739 /* If the count is negative, make it 0. */
4742 /* If the count is too big, truncate it.
4743 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4744 do the intuitive thing. */
4745 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4746 n
= GET_MODE_BITSIZE (mode
);
4748 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4753 if (info
.remainder
== 0)
4754 return info
.cc_special
;
4759 return info
.cc_inline
;
4762 /* This case always ends with an and instruction. */
4766 /* A loop to shift by a "large" constant value.
4767 If we have shift-by-2 insns, use them. */
4768 if (info
.shift2
!= NULL
)
4771 return info
.cc_inline
;
4780 /* A rotation by a non-constant will cause a loop to be generated, in
4781 which a rotation by one bit is used. A rotation by a constant,
4782 including the one in the loop, will be taken care of by
4783 output_a_rotate () at the insn emit time. */
4786 expand_a_rotate (rtx operands
[])
4788 rtx dst
= operands
[0];
4789 rtx src
= operands
[1];
4790 rtx rotate_amount
= operands
[2];
4791 enum machine_mode mode
= GET_MODE (dst
);
4793 if (h8sx_classify_shift (mode
, ROTATE
, rotate_amount
) == H8SX_SHIFT_UNARY
)
4796 /* We rotate in place. */
4797 emit_move_insn (dst
, src
);
4799 if (GET_CODE (rotate_amount
) != CONST_INT
)
4801 rtx counter
= gen_reg_rtx (QImode
);
4802 rtx start_label
= gen_label_rtx ();
4803 rtx end_label
= gen_label_rtx ();
4805 /* If the rotate amount is less than or equal to 0,
4806 we go out of the loop. */
4807 emit_cmp_and_jump_insns (rotate_amount
, const0_rtx
, LE
, NULL_RTX
,
4808 QImode
, 0, end_label
);
4810 /* Initialize the loop counter. */
4811 emit_move_insn (counter
, rotate_amount
);
4813 emit_label (start_label
);
4815 /* Rotate by one bit. */
4819 emit_insn (gen_rotlqi3_1 (dst
, dst
, const1_rtx
));
4822 emit_insn (gen_rotlhi3_1 (dst
, dst
, const1_rtx
));
4825 emit_insn (gen_rotlsi3_1 (dst
, dst
, const1_rtx
));
4831 /* Decrement the counter by 1. */
4832 emit_insn (gen_addqi3 (counter
, counter
, constm1_rtx
));
4834 /* If the loop counter is nonzero, we go back to the beginning
4836 emit_cmp_and_jump_insns (counter
, const0_rtx
, NE
, NULL_RTX
, QImode
, 1,
4839 emit_label (end_label
);
4843 /* Rotate by AMOUNT bits. */
4847 emit_insn (gen_rotlqi3_1 (dst
, dst
, rotate_amount
));
4850 emit_insn (gen_rotlhi3_1 (dst
, dst
, rotate_amount
));
4853 emit_insn (gen_rotlsi3_1 (dst
, dst
, rotate_amount
));
4863 /* Output a rotate insn. */
4866 output_a_rotate (enum rtx_code code
, rtx
*operands
)
4868 rtx dst
= operands
[0];
4869 rtx rotate_amount
= operands
[2];
4870 enum shift_mode rotate_mode
;
4871 enum shift_type rotate_type
;
4872 const char *insn_buf
;
4875 enum machine_mode mode
= GET_MODE (dst
);
4877 gcc_assert (GET_CODE (rotate_amount
) == CONST_INT
);
4882 rotate_mode
= QIshift
;
4885 rotate_mode
= HIshift
;
4888 rotate_mode
= SIshift
;
4897 rotate_type
= SHIFT_ASHIFT
;
4900 rotate_type
= SHIFT_LSHIFTRT
;
4906 amount
= INTVAL (rotate_amount
);
4908 /* Clean up AMOUNT. */
4911 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
4912 amount
= GET_MODE_BITSIZE (mode
);
4914 /* Determine the faster direction. After this phase, amount will be
4915 at most a half of GET_MODE_BITSIZE (mode). */
4916 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
4918 /* Flip the direction. */
4919 amount
= GET_MODE_BITSIZE (mode
) - amount
;
4921 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
4924 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4925 boost up the rotation. */
4926 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
4927 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
4928 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
4929 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
4930 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
4935 /* This code works on any family. */
4936 insn_buf
= "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
4937 output_asm_insn (insn_buf
, operands
);
4941 /* This code works on the H8/300H and H8S. */
4942 insn_buf
= "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
4943 output_asm_insn (insn_buf
, operands
);
4950 /* Adjust AMOUNT and flip the direction. */
4951 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
4953 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
4956 /* Output rotate insns. */
4957 for (bits
= TARGET_H8300S
? 2 : 1; bits
> 0; bits
/= 2)
4960 insn_buf
= rotate_two
[rotate_type
][rotate_mode
];
4962 insn_buf
= rotate_one
[cpu_type
][rotate_type
][rotate_mode
];
4964 for (; amount
>= bits
; amount
-= bits
)
4965 output_asm_insn (insn_buf
, operands
);
4971 /* Compute the length of a rotate insn. */
4974 compute_a_rotate_length (rtx
*operands
)
4976 rtx src
= operands
[1];
4977 rtx amount_rtx
= operands
[2];
4978 enum machine_mode mode
= GET_MODE (src
);
4980 unsigned int length
= 0;
4982 gcc_assert (GET_CODE (amount_rtx
) == CONST_INT
);
4984 amount
= INTVAL (amount_rtx
);
4986 /* Clean up AMOUNT. */
4989 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
4990 amount
= GET_MODE_BITSIZE (mode
);
4992 /* Determine the faster direction. After this phase, amount
4993 will be at most a half of GET_MODE_BITSIZE (mode). */
4994 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
4995 /* Flip the direction. */
4996 amount
= GET_MODE_BITSIZE (mode
) - amount
;
4998 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4999 boost up the rotation. */
5000 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5001 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5002 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5003 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5004 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5006 /* Adjust AMOUNT and flip the direction. */
5007 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5011 /* We use 2-bit rotations on the H8S. */
5013 amount
= amount
/ 2 + amount
% 2;
5015 /* The H8/300 uses three insns to rotate one bit, taking 6
5017 length
+= amount
* ((TARGET_H8300
&& mode
== HImode
) ? 6 : 2);
5022 /* Fix the operands of a gen_xxx so that it could become a bit
5026 fix_bit_operand (rtx
*operands
, enum rtx_code code
)
5028 /* The bit_operand predicate accepts any memory during RTL generation, but
5029 only 'U' memory afterwards, so if this is a MEM operand, we must force
5030 it to be valid for 'U' by reloading the address. */
5033 ? single_zero_operand (operands
[2], QImode
)
5034 : single_one_operand (operands
[2], QImode
))
5036 /* OK to have a memory dest. */
5037 if (GET_CODE (operands
[0]) == MEM
5038 && !OK_FOR_U (operands
[0]))
5040 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[0]),
5041 copy_to_mode_reg (Pmode
,
5042 XEXP (operands
[0], 0)));
5043 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5047 if (GET_CODE (operands
[1]) == MEM
5048 && !OK_FOR_U (operands
[1]))
5050 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[1]),
5051 copy_to_mode_reg (Pmode
,
5052 XEXP (operands
[1], 0)));
5053 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5059 /* Dest and src op must be register. */
5061 operands
[1] = force_reg (QImode
, operands
[1]);
5063 rtx res
= gen_reg_rtx (QImode
);
5067 emit_insn (gen_andqi3_1 (res
, operands
[1], operands
[2]));
5070 emit_insn (gen_iorqi3_1 (res
, operands
[1], operands
[2]));
5073 emit_insn (gen_xorqi3_1 (res
, operands
[1], operands
[2]));
5078 emit_insn (gen_movqi (operands
[0], res
));
5083 /* Return nonzero if FUNC is an interrupt function as specified
5084 by the "interrupt" attribute. */
5087 h8300_interrupt_function_p (tree func
)
5091 if (TREE_CODE (func
) != FUNCTION_DECL
)
5094 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
5095 return a
!= NULL_TREE
;
5098 /* Return nonzero if FUNC is a saveall function as specified by the
5099 "saveall" attribute. */
5102 h8300_saveall_function_p (tree func
)
5106 if (TREE_CODE (func
) != FUNCTION_DECL
)
5109 a
= lookup_attribute ("saveall", DECL_ATTRIBUTES (func
));
5110 return a
!= NULL_TREE
;
5113 /* Return nonzero if FUNC is an OS_Task function as specified
5114 by the "OS_Task" attribute. */
5117 h8300_os_task_function_p (tree func
)
5121 if (TREE_CODE (func
) != FUNCTION_DECL
)
5124 a
= lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func
));
5125 return a
!= NULL_TREE
;
5128 /* Return nonzero if FUNC is a monitor function as specified
5129 by the "monitor" attribute. */
5132 h8300_monitor_function_p (tree func
)
5136 if (TREE_CODE (func
) != FUNCTION_DECL
)
5139 a
= lookup_attribute ("monitor", DECL_ATTRIBUTES (func
));
5140 return a
!= NULL_TREE
;
5143 /* Return nonzero if FUNC is a function that should be called
5144 through the function vector. */
5147 h8300_funcvec_function_p (tree func
)
5151 if (TREE_CODE (func
) != FUNCTION_DECL
)
5154 a
= lookup_attribute ("function_vector", DECL_ATTRIBUTES (func
));
5155 return a
!= NULL_TREE
;
5158 /* Return nonzero if DECL is a variable that's in the eight bit
5162 h8300_eightbit_data_p (tree decl
)
5166 if (TREE_CODE (decl
) != VAR_DECL
)
5169 a
= lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl
));
5170 return a
!= NULL_TREE
;
5173 /* Return nonzero if DECL is a variable that's in the tiny
5177 h8300_tiny_data_p (tree decl
)
5181 if (TREE_CODE (decl
) != VAR_DECL
)
5184 a
= lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl
));
5185 return a
!= NULL_TREE
;
5188 /* Generate an 'interrupt_handler' attribute for decls. We convert
5189 all the pragmas to corresponding attributes. */
5192 h8300_insert_attributes (tree node
, tree
*attributes
)
5194 if (TREE_CODE (node
) == FUNCTION_DECL
)
5196 if (pragma_interrupt
)
5198 pragma_interrupt
= 0;
5200 /* Add an 'interrupt_handler' attribute. */
5201 *attributes
= tree_cons (get_identifier ("interrupt_handler"),
5209 /* Add an 'saveall' attribute. */
5210 *attributes
= tree_cons (get_identifier ("saveall"),
5216 /* Supported attributes:
5218 interrupt_handler: output a prologue and epilogue suitable for an
5221 saveall: output a prologue and epilogue that saves and restores
5222 all registers except the stack pointer.
5224 function_vector: This function should be called through the
5227 eightbit_data: This variable lives in the 8-bit data area and can
5228 be referenced with 8-bit absolute memory addresses.
5230 tiny_data: This variable lives in the tiny data area and can be
5231 referenced with 16-bit absolute memory references. */
5233 const struct attribute_spec h8300_attribute_table
[] =
5235 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
5236 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5237 { "saveall", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5238 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5239 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5240 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5241 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute
},
5242 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute
},
5243 { NULL
, 0, 0, false, false, false, NULL
}
5247 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5248 struct attribute_spec.handler. */
5250 h8300_handle_fndecl_attribute (tree
*node
, tree name
,
5251 tree args ATTRIBUTE_UNUSED
,
5252 int flags ATTRIBUTE_UNUSED
,
5255 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5257 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
5258 IDENTIFIER_POINTER (name
));
5259 *no_add_attrs
= true;
5265 /* Handle an "eightbit_data" attribute; arguments as in
5266 struct attribute_spec.handler. */
5268 h8300_handle_eightbit_data_attribute (tree
*node
, tree name
,
5269 tree args ATTRIBUTE_UNUSED
,
5270 int flags ATTRIBUTE_UNUSED
,
5275 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5277 DECL_SECTION_NAME (decl
) = build_string (7, ".eight");
5281 warning (OPT_Wattributes
, "%qs attribute ignored",
5282 IDENTIFIER_POINTER (name
));
5283 *no_add_attrs
= true;
5289 /* Handle an "tiny_data" attribute; arguments as in
5290 struct attribute_spec.handler. */
5292 h8300_handle_tiny_data_attribute (tree
*node
, tree name
,
5293 tree args ATTRIBUTE_UNUSED
,
5294 int flags ATTRIBUTE_UNUSED
,
5299 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5301 DECL_SECTION_NAME (decl
) = build_string (6, ".tiny");
5305 warning (OPT_Wattributes
, "%qs attribute ignored",
5306 IDENTIFIER_POINTER (name
));
5307 *no_add_attrs
= true;
5313 /* Mark function vectors, and various small data objects. */
5316 h8300_encode_section_info (tree decl
, rtx rtl
, int first
)
5318 int extra_flags
= 0;
5320 default_encode_section_info (decl
, rtl
, first
);
5322 if (TREE_CODE (decl
) == FUNCTION_DECL
5323 && h8300_funcvec_function_p (decl
))
5324 extra_flags
= SYMBOL_FLAG_FUNCVEC_FUNCTION
;
5325 else if (TREE_CODE (decl
) == VAR_DECL
5326 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
5328 if (h8300_eightbit_data_p (decl
))
5329 extra_flags
= SYMBOL_FLAG_EIGHTBIT_DATA
;
5330 else if (first
&& h8300_tiny_data_p (decl
))
5331 extra_flags
= SYMBOL_FLAG_TINY_DATA
;
5335 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
5338 /* Output a single-bit extraction. */
5341 output_simode_bld (int bild
, rtx operands
[])
5345 /* Clear the destination register. */
5346 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands
);
5348 /* Now output the bit load or bit inverse load, and store it in
5351 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5353 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5355 output_asm_insn ("bst\t#0,%w0", operands
);
5359 /* Determine if we can clear the destination first. */
5360 int clear_first
= (REG_P (operands
[0]) && REG_P (operands
[1])
5361 && REGNO (operands
[0]) != REGNO (operands
[1]));
5364 output_asm_insn ("sub.l\t%S0,%S0", operands
);
5366 /* Output the bit load or bit inverse load. */
5368 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5370 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5373 output_asm_insn ("xor.l\t%S0,%S0", operands
);
5375 /* Perform the bit store. */
5376 output_asm_insn ("rotxl.l\t%S0", operands
);
5383 /* Delayed-branch scheduling is more effective if we have some idea
5384 how long each instruction will be. Use a shorten_branches pass
5385 to get an initial estimate. */
5390 if (flag_delayed_branch
)
5391 shorten_branches (get_insns ());
5394 #ifndef OBJECT_FORMAT_ELF
5396 h8300_asm_named_section (const char *name
, unsigned int flags ATTRIBUTE_UNUSED
,
5399 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5400 fprintf (asm_out_file
, "\t.section %s\n", name
);
5402 #endif /* ! OBJECT_FORMAT_ELF */
5404 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5405 which is a special case of the 'R' operand. */
5408 h8300_eightbit_constant_address_p (rtx x
)
5410 /* The ranges of the 8-bit area. */
5411 const unsigned HOST_WIDE_INT n1
= trunc_int_for_mode (0xff00, HImode
);
5412 const unsigned HOST_WIDE_INT n2
= trunc_int_for_mode (0xffff, HImode
);
5413 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00ffff00, SImode
);
5414 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00ffffff, SImode
);
5415 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0xffffff00, SImode
);
5416 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0xffffffff, SImode
);
5418 unsigned HOST_WIDE_INT addr
;
5420 /* We accept symbols declared with eightbit_data. */
5421 if (GET_CODE (x
) == SYMBOL_REF
)
5422 return (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_EIGHTBIT_DATA
) != 0;
5424 if (GET_CODE (x
) != CONST_INT
)
5430 || ((TARGET_H8300
|| TARGET_NORMAL_MODE
) && IN_RANGE (addr
, n1
, n2
))
5431 || (TARGET_H8300H
&& IN_RANGE (addr
, h1
, h2
))
5432 || (TARGET_H8300S
&& IN_RANGE (addr
, s1
, s2
)));
5435 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5436 on H8/300H and H8S. */
5439 h8300_tiny_constant_address_p (rtx x
)
5441 /* The ranges of the 16-bit area. */
5442 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00000000, SImode
);
5443 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00007fff, SImode
);
5444 const unsigned HOST_WIDE_INT h3
= trunc_int_for_mode (0x00ff8000, SImode
);
5445 const unsigned HOST_WIDE_INT h4
= trunc_int_for_mode (0x00ffffff, SImode
);
5446 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0x00000000, SImode
);
5447 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0x00007fff, SImode
);
5448 const unsigned HOST_WIDE_INT s3
= trunc_int_for_mode (0xffff8000, SImode
);
5449 const unsigned HOST_WIDE_INT s4
= trunc_int_for_mode (0xffffffff, SImode
);
5451 unsigned HOST_WIDE_INT addr
;
5453 switch (GET_CODE (x
))
5456 /* In the normal mode, any symbol fits in the 16-bit absolute
5457 address range. We also accept symbols declared with
5459 return (TARGET_NORMAL_MODE
5460 || (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_TINY_DATA
) != 0);
5464 return (TARGET_NORMAL_MODE
5466 && (IN_RANGE (addr
, h1
, h2
) || IN_RANGE (addr
, h3
, h4
)))
5468 && (IN_RANGE (addr
, s1
, s2
) || IN_RANGE (addr
, s3
, s4
))));
5471 return TARGET_NORMAL_MODE
;
5479 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5480 locations that can be accessed as a 16-bit word. */
5483 byte_accesses_mergeable_p (rtx addr1
, rtx addr2
)
5485 HOST_WIDE_INT offset1
, offset2
;
5493 else if (GET_CODE (addr1
) == PLUS
5494 && REG_P (XEXP (addr1
, 0))
5495 && GET_CODE (XEXP (addr1
, 1)) == CONST_INT
)
5497 reg1
= XEXP (addr1
, 0);
5498 offset1
= INTVAL (XEXP (addr1
, 1));
5508 else if (GET_CODE (addr2
) == PLUS
5509 && REG_P (XEXP (addr2
, 0))
5510 && GET_CODE (XEXP (addr2
, 1)) == CONST_INT
)
5512 reg2
= XEXP (addr2
, 0);
5513 offset2
= INTVAL (XEXP (addr2
, 1));
5518 if (((reg1
== stack_pointer_rtx
&& reg2
== stack_pointer_rtx
)
5519 || (reg1
== frame_pointer_rtx
&& reg2
== frame_pointer_rtx
))
5521 && offset1
+ 1 == offset2
)
5527 /* Return nonzero if we have the same comparison insn as I3 two insns
5528 before I3. I3 is assumed to be a comparison insn. */
5531 same_cmp_preceding_p (rtx i3
)
5535 /* Make sure we have a sequence of three insns. */
5536 i2
= prev_nonnote_insn (i3
);
5539 i1
= prev_nonnote_insn (i2
);
5543 return (INSN_P (i1
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5544 && any_condjump_p (i2
) && onlyjump_p (i2
));
5547 /* Return nonzero if we have the same comparison insn as I1 two insns
5548 after I1. I1 is assumed to be a comparison insn. */
5551 same_cmp_following_p (rtx i1
)
5555 /* Make sure we have a sequence of three insns. */
5556 i2
= next_nonnote_insn (i1
);
5559 i3
= next_nonnote_insn (i2
);
5563 return (INSN_P (i3
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5564 && any_condjump_p (i2
) && onlyjump_p (i2
));
5567 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5568 (or pops) N registers. OPERANDS are assumed to be an array of
5572 h8300_regs_ok_for_stm (int n
, rtx operands
[])
5577 return ((REGNO (operands
[0]) == 0 && REGNO (operands
[1]) == 1)
5578 || (REGNO (operands
[0]) == 2 && REGNO (operands
[1]) == 3)
5579 || (REGNO (operands
[0]) == 4 && REGNO (operands
[1]) == 5));
5581 return ((REGNO (operands
[0]) == 0
5582 && REGNO (operands
[1]) == 1
5583 && REGNO (operands
[2]) == 2)
5584 || (REGNO (operands
[0]) == 4
5585 && REGNO (operands
[1]) == 5
5586 && REGNO (operands
[2]) == 6));
5589 return (REGNO (operands
[0]) == 0
5590 && REGNO (operands
[1]) == 1
5591 && REGNO (operands
[2]) == 2
5592 && REGNO (operands
[3]) == 3);
5598 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5601 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5602 unsigned int new_reg
)
5604 /* Interrupt functions can only use registers that have already been
5605 saved by the prologue, even if they would normally be
5608 if (h8300_current_function_interrupt_function_p ()
5609 && !df_regs_ever_live_p (new_reg
))
5615 /* Return nonzero if X is a legitimate constant. */
5618 h8300_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED
)
5623 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5626 h8300_rtx_ok_for_base_p (rtx x
, int strict
)
5628 /* Strip off SUBREG if any. */
5629 if (GET_CODE (x
) == SUBREG
)
5634 ? REG_OK_FOR_BASE_STRICT_P (x
)
5635 : REG_OK_FOR_BASE_NONSTRICT_P (x
)));
5638 /* Return nozero if X is a legitimate address. On the H8/300, a
5639 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5640 CONSTANT_ADDRESS. */
5643 h8300_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict
)
5645 /* The register indirect addresses like @er0 is always valid. */
5646 if (h8300_rtx_ok_for_base_p (x
, strict
))
5649 if (CONSTANT_ADDRESS_P (x
))
5653 && ( GET_CODE (x
) == PRE_INC
5654 || GET_CODE (x
) == PRE_DEC
5655 || GET_CODE (x
) == POST_INC
5656 || GET_CODE (x
) == POST_DEC
)
5657 && h8300_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
5660 if (GET_CODE (x
) == PLUS
5661 && CONSTANT_ADDRESS_P (XEXP (x
, 1))
5662 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x
, 0),
5669 /* Worker function for HARD_REGNO_NREGS.
5671 We pretend the MAC register is 32bits -- we don't have any data
5672 types on the H8 series to handle more than 32bits. */
5675 h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED
, enum machine_mode mode
)
5677 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5680 /* Worker function for HARD_REGNO_MODE_OK. */
5683 h8300_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
5686 /* If an even reg, then anything goes. Otherwise the mode must be
5688 return ((regno
& 1) == 0) || (mode
== HImode
) || (mode
== QImode
);
5690 /* MAC register can only be of SImode. Otherwise, anything
5692 return regno
== MAC_REG
? mode
== SImode
: 1;
5695 /* Perform target dependent optabs initialization. */
5697 h8300_init_libfuncs (void)
5699 set_optab_libfunc (smul_optab
, HImode
, "__mulhi3");
5700 set_optab_libfunc (sdiv_optab
, HImode
, "__divhi3");
5701 set_optab_libfunc (udiv_optab
, HImode
, "__udivhi3");
5702 set_optab_libfunc (smod_optab
, HImode
, "__modhi3");
5703 set_optab_libfunc (umod_optab
, HImode
, "__umodhi3");
5706 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5709 h8300_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5711 return (TYPE_MODE (type
) == BLKmode
5712 || GET_MODE_SIZE (TYPE_MODE (type
)) > (TARGET_H8300
? 4 : 8));
5715 /* Initialize the GCC target structure. */
5716 #undef TARGET_ATTRIBUTE_TABLE
5717 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
5719 #undef TARGET_ASM_ALIGNED_HI_OP
5720 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
5722 #undef TARGET_ASM_FILE_START
5723 #define TARGET_ASM_FILE_START h8300_file_start
5724 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
5725 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
5727 #undef TARGET_ASM_FILE_END
5728 #define TARGET_ASM_FILE_END h8300_file_end
5730 #undef TARGET_ENCODE_SECTION_INFO
5731 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
5733 #undef TARGET_INSERT_ATTRIBUTES
5734 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
5736 #undef TARGET_RTX_COSTS
5737 #define TARGET_RTX_COSTS h8300_rtx_costs
5739 #undef TARGET_INIT_LIBFUNCS
5740 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
5742 #undef TARGET_RETURN_IN_MEMORY
5743 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
5745 #undef TARGET_MACHINE_DEPENDENT_REORG
5746 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
5748 #undef TARGET_DEFAULT_TARGET_FLAGS
5749 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
5751 struct gcc_target targetm
= TARGET_INITIALIZER
;