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Merged with mainline at revision 128810.
[official-gcc.git] / gcc / config / arm / arm.h
blob9c8534cbaf9b1ce957c850a745016bf162026a80
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 3, or (at your
14 option) any later version.
15
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING3. If not see
23 <http://www.gnu.org/licenses/>. */
24
25 #ifndef GCC_ARM_H
26 #define GCC_ARM_H
27
28 #include "config/vxworks-dummy.h"
29
30 /* The architecture define. */
31 extern char arm_arch_name[];
32
33 /* Target CPU builtins. */
34 #define TARGET_CPU_CPP_BUILTINS() \
35 do \
36 { \
37 /* Define __arm__ even when in thumb mode, for \
38 consistency with armcc. */ \
39 builtin_define ("__arm__"); \
40 builtin_define ("__APCS_32__"); \
41 if (TARGET_THUMB) \
42 builtin_define ("__thumb__"); \
43 if (TARGET_THUMB2) \
44 builtin_define ("__thumb2__"); \
45 \
46 if (TARGET_BIG_END) \
47 { \
48 builtin_define ("__ARMEB__"); \
49 if (TARGET_THUMB) \
50 builtin_define ("__THUMBEB__"); \
51 if (TARGET_LITTLE_WORDS) \
52 builtin_define ("__ARMWEL__"); \
53 } \
54 else \
55 { \
56 builtin_define ("__ARMEL__"); \
57 if (TARGET_THUMB) \
58 builtin_define ("__THUMBEL__"); \
59 } \
60 \
61 if (TARGET_SOFT_FLOAT) \
62 builtin_define ("__SOFTFP__"); \
63 \
64 if (TARGET_VFP) \
65 builtin_define ("__VFP_FP__"); \
66 \
67 if (TARGET_NEON) \
68 builtin_define ("__ARM_NEON__"); \
69 \
70 /* Add a define for interworking. \
71 Needed when building libgcc.a. */ \
72 if (arm_cpp_interwork) \
73 builtin_define ("__THUMB_INTERWORK__"); \
74 \
75 builtin_assert ("cpu=arm"); \
76 builtin_assert ("machine=arm"); \
77 \
78 builtin_define (arm_arch_name); \
79 if (arm_arch_cirrus) \
80 builtin_define ("__MAVERICK__"); \
81 if (arm_arch_xscale) \
82 builtin_define ("__XSCALE__"); \
83 if (arm_arch_iwmmxt) \
84 builtin_define ("__IWMMXT__"); \
85 if (TARGET_AAPCS_BASED) \
86 builtin_define ("__ARM_EABI__"); \
87 } while (0)
88
89 /* The various ARM cores. */
90 enum processor_type
91 {
92 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
93 IDENT,
94 #include "arm-cores.def"
95 #undef ARM_CORE
96 /* Used to indicate that no processor has been specified. */
97 arm_none
98 };
99
100 enum target_cpus
101 {
102 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
103 TARGET_CPU_##IDENT,
104 #include "arm-cores.def"
105 #undef ARM_CORE
106 TARGET_CPU_generic
107 };
108
109 /* The processor for which instructions should be scheduled. */
110 extern enum processor_type arm_tune;
111
112 typedef enum arm_cond_code
113 {
114 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
115 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
116 }
117 arm_cc;
118
119 extern arm_cc arm_current_cc;
120
121 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
122
123 extern int arm_target_label;
124 extern int arm_ccfsm_state;
125 extern GTY(()) rtx arm_target_insn;
126 /* Define the information needed to generate branch insns. This is
127 stored from the compare operation. */
128 extern GTY(()) rtx arm_compare_op0;
129 extern GTY(()) rtx arm_compare_op1;
130 /* The label of the current constant pool. */
131 extern rtx pool_vector_label;
132 /* Set to 1 when a return insn is output, this means that the epilogue
133 is not needed. */
134 extern int return_used_this_function;
135 \f
136 /* Just in case configure has failed to define anything. */
137 #ifndef TARGET_CPU_DEFAULT
138 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
139 #endif
140
141
142 #undef CPP_SPEC
143 #define CPP_SPEC "%(subtarget_cpp_spec) \
144 %{msoft-float:%{mhard-float: \
145 %e-msoft-float and -mhard_float may not be used together}} \
146 %{mbig-endian:%{mlittle-endian: \
147 %e-mbig-endian and -mlittle-endian may not be used together}}"
148
149 #ifndef CC1_SPEC
150 #define CC1_SPEC ""
151 #endif
152
153 /* This macro defines names of additional specifications to put in the specs
154 that can be used in various specifications like CC1_SPEC. Its definition
155 is an initializer with a subgrouping for each command option.
156
157 Each subgrouping contains a string constant, that defines the
158 specification name, and a string constant that used by the GCC driver
159 program.
160
161 Do not define this macro if it does not need to do anything. */
162 #define EXTRA_SPECS \
163 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
164 SUBTARGET_EXTRA_SPECS
165
166 #ifndef SUBTARGET_EXTRA_SPECS
167 #define SUBTARGET_EXTRA_SPECS
168 #endif
169
170 #ifndef SUBTARGET_CPP_SPEC
171 #define SUBTARGET_CPP_SPEC ""
172 #endif
173 \f
174 /* Run-time Target Specification. */
175 #ifndef TARGET_VERSION
176 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
177 #endif
178
179 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
180 /* Use hardware floating point instructions. */
181 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
182 /* Use hardware floating point calling convention. */
183 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
184 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
185 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
186 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
187 #define TARGET_IWMMXT (arm_arch_iwmmxt)
188 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
189 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
190 #define TARGET_ARM (! TARGET_THUMB)
191 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
192 #define TARGET_BACKTRACE (leaf_function_p () \
193 ? TARGET_TPCS_LEAF_FRAME \
194 : TARGET_TPCS_FRAME)
195 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
196 #define TARGET_AAPCS_BASED \
197 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
198
199 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
200 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
201
202 /* Only 16-bit thumb code. */
203 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
204 /* Arm or Thumb-2 32-bit code. */
205 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
206 /* 32-bit Thumb-2 code. */
207 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
208
209 /* The following two macros concern the ability to execute coprocessor
210 instructions for VFPv3 or NEON. TARGET_VFP3 is currently only ever
211 tested when we know we are generating for VFP hardware; we need to
212 be more careful with TARGET_NEON as noted below. */
213
214 /* FPU is VFPv3 (with twice the number of D registers). Setting the FPU to
215 Neon automatically enables VFPv3 too. */
216 #define TARGET_VFP3 (arm_fp_model == ARM_FP_MODEL_VFP \
217 && (arm_fpu_arch == FPUTYPE_VFP3 \
218 || arm_fpu_arch == FPUTYPE_NEON))
219 /* FPU supports Neon instructions. The setting of this macro gets
220 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
221 and TARGET_HARD_FLOAT to ensure that NEON instructions are
222 available. */
223 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
224 && arm_fp_model == ARM_FP_MODEL_VFP \
225 && arm_fpu_arch == FPUTYPE_NEON)
226
227 /* "DSP" multiply instructions, eg. SMULxy. */
228 #define TARGET_DSP_MULTIPLY \
229 (TARGET_32BIT && arm_arch5e && arm_arch_notm)
230 /* Integer SIMD instructions, and extend-accumulate instructions. */
231 #define TARGET_INT_SIMD \
232 (TARGET_32BIT && arm_arch6 && arm_arch_notm)
233
234 /* We could use unified syntax for arm mode, but for now we just use it
235 for Thumb-2. */
236 #define TARGET_UNIFIED_ASM TARGET_THUMB2
237
238
239 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
240 then TARGET_AAPCS_BASED must be true -- but the converse does not
241 hold. TARGET_BPABI implies the use of the BPABI runtime library,
242 etc., in addition to just the AAPCS calling conventions. */
243 #ifndef TARGET_BPABI
244 #define TARGET_BPABI false
245 #endif
246
247 /* Support for a compile-time default CPU, et cetera. The rules are:
248 --with-arch is ignored if -march or -mcpu are specified.
249 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
250 by --with-arch.
251 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
252 by -march).
253 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
254 specified.
255 --with-fpu is ignored if -mfpu is specified.
256 --with-abi is ignored is -mabi is specified. */
257 #define OPTION_DEFAULT_SPECS \
258 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
259 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
260 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
261 {"float", \
262 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
263 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
264 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
265 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
266
267 /* Which floating point model to use. */
268 enum arm_fp_model
269 {
270 ARM_FP_MODEL_UNKNOWN,
271 /* FPA model (Hardware or software). */
272 ARM_FP_MODEL_FPA,
273 /* Cirrus Maverick floating point model. */
274 ARM_FP_MODEL_MAVERICK,
275 /* VFP floating point model. */
276 ARM_FP_MODEL_VFP
277 };
278
279 extern enum arm_fp_model arm_fp_model;
280
281 /* Which floating point hardware is available. Also update
282 fp_model_for_fpu in arm.c when adding entries to this list. */
283 enum fputype
284 {
285 /* No FP hardware. */
286 FPUTYPE_NONE,
287 /* Full FPA support. */
288 FPUTYPE_FPA,
289 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
290 FPUTYPE_FPA_EMU2,
291 /* Emulated FPA hardware, Issue 3 emulator. */
292 FPUTYPE_FPA_EMU3,
293 /* Cirrus Maverick floating point co-processor. */
294 FPUTYPE_MAVERICK,
295 /* VFP. */
296 FPUTYPE_VFP,
297 /* VFPv3. */
298 FPUTYPE_VFP3,
299 /* Neon. */
300 FPUTYPE_NEON
301 };
302
303 /* Recast the floating point class to be the floating point attribute. */
304 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
305
306 /* What type of floating point to tune for */
307 extern enum fputype arm_fpu_tune;
308
309 /* What type of floating point instructions are available */
310 extern enum fputype arm_fpu_arch;
311
312 enum float_abi_type
313 {
314 ARM_FLOAT_ABI_SOFT,
315 ARM_FLOAT_ABI_SOFTFP,
316 ARM_FLOAT_ABI_HARD
317 };
318
319 extern enum float_abi_type arm_float_abi;
320
321 #ifndef TARGET_DEFAULT_FLOAT_ABI
322 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
323 #endif
324
325 /* Which ABI to use. */
326 enum arm_abi_type
327 {
328 ARM_ABI_APCS,
329 ARM_ABI_ATPCS,
330 ARM_ABI_AAPCS,
331 ARM_ABI_IWMMXT,
332 ARM_ABI_AAPCS_LINUX
333 };
334
335 extern enum arm_abi_type arm_abi;
336
337 #ifndef ARM_DEFAULT_ABI
338 #define ARM_DEFAULT_ABI ARM_ABI_APCS
339 #endif
340
341 /* Which thread pointer access sequence to use. */
342 enum arm_tp_type {
343 TP_AUTO,
344 TP_SOFT,
345 TP_CP15
346 };
347
348 extern enum arm_tp_type target_thread_pointer;
349
350 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
351 extern int arm_arch3m;
352
353 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
354 extern int arm_arch4;
355
356 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
357 extern int arm_arch4t;
358
359 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
360 extern int arm_arch5;
361
362 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
363 extern int arm_arch5e;
364
365 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
366 extern int arm_arch6;
367
368 /* Nonzero if instructions not present in the 'M' profile can be used. */
369 extern int arm_arch_notm;
370
371 /* Nonzero if this chip can benefit from load scheduling. */
372 extern int arm_ld_sched;
373
374 /* Nonzero if generating thumb code. */
375 extern int thumb_code;
376
377 /* Nonzero if this chip is a StrongARM. */
378 extern int arm_tune_strongarm;
379
380 /* Nonzero if this chip is a Cirrus variant. */
381 extern int arm_arch_cirrus;
382
383 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
384 extern int arm_arch_iwmmxt;
385
386 /* Nonzero if this chip is an XScale. */
387 extern int arm_arch_xscale;
388
389 /* Nonzero if tuning for XScale. */
390 extern int arm_tune_xscale;
391
392 /* Nonzero if tuning for stores via the write buffer. */
393 extern int arm_tune_wbuf;
394
395 /* Nonzero if we should define __THUMB_INTERWORK__ in the
396 preprocessor.
397 XXX This is a bit of a hack, it's intended to help work around
398 problems in GLD which doesn't understand that armv5t code is
399 interworking clean. */
400 extern int arm_cpp_interwork;
401
402 /* Nonzero if chip supports Thumb 2. */
403 extern int arm_arch_thumb2;
404
405 /* Nonzero if chip supports integer division instruction. */
406 extern int arm_arch_hwdiv;
407
408 #ifndef TARGET_DEFAULT
409 #define TARGET_DEFAULT (MASK_APCS_FRAME)
410 #endif
411
412 /* The frame pointer register used in gcc has nothing to do with debugging;
413 that is controlled by the APCS-FRAME option. */
414 #define CAN_DEBUG_WITHOUT_FP
415
416 #define OVERRIDE_OPTIONS arm_override_options ()
417
418 /* Nonzero if PIC code requires explicit qualifiers to generate
419 PLT and GOT relocs rather than the assembler doing so implicitly.
420 Subtargets can override these if required. */
421 #ifndef NEED_GOT_RELOC
422 #define NEED_GOT_RELOC 0
423 #endif
424 #ifndef NEED_PLT_RELOC
425 #define NEED_PLT_RELOC 0
426 #endif
427
428 /* Nonzero if we need to refer to the GOT with a PC-relative
429 offset. In other words, generate
430
431 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
432
433 rather than
434
435 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
436
437 The default is true, which matches NetBSD. Subtargets can
438 override this if required. */
439 #ifndef GOT_PCREL
440 #define GOT_PCREL 1
441 #endif
442 \f
443 /* Target machine storage Layout. */
444
445
446 /* Define this macro if it is advisable to hold scalars in registers
447 in a wider mode than that declared by the program. In such cases,
448 the value is constrained to be within the bounds of the declared
449 type, but kept valid in the wider mode. The signedness of the
450 extension may differ from that of the type. */
451
452 /* It is far faster to zero extend chars than to sign extend them */
453
454 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
455 if (GET_MODE_CLASS (MODE) == MODE_INT \
456 && GET_MODE_SIZE (MODE) < 4) \
457 { \
458 if (MODE == QImode) \
459 UNSIGNEDP = 1; \
460 else if (MODE == HImode) \
461 UNSIGNEDP = 1; \
462 (MODE) = SImode; \
463 }
464
465 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
466 if ((GET_MODE_CLASS (MODE) == MODE_INT \
467 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
468 && GET_MODE_SIZE (MODE) < 4) \
469 (MODE) = SImode; \
470
471 /* Define this if most significant bit is lowest numbered
472 in instructions that operate on numbered bit-fields. */
473 #define BITS_BIG_ENDIAN 0
474
475 /* Define this if most significant byte of a word is the lowest numbered.
476 Most ARM processors are run in little endian mode, so that is the default.
477 If you want to have it run-time selectable, change the definition in a
478 cover file to be TARGET_BIG_ENDIAN. */
479 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
480
481 /* Define this if most significant word of a multiword number is the lowest
482 numbered.
483 This is always false, even when in big-endian mode. */
484 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
485
486 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
487 on processor pre-defineds when compiling libgcc2.c. */
488 #if defined(__ARMEB__) && !defined(__ARMWEL__)
489 #define LIBGCC2_WORDS_BIG_ENDIAN 1
490 #else
491 #define LIBGCC2_WORDS_BIG_ENDIAN 0
492 #endif
493
494 /* Define this if most significant word of doubles is the lowest numbered.
495 The rules are different based on whether or not we use FPA-format,
496 VFP-format or some other floating point co-processor's format doubles. */
497 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
498
499 #define UNITS_PER_WORD 4
500
501 /* Use the option -mvectorize-with-neon-quad to override the use of doubleword
502 registers when autovectorizing for Neon, at least until multiple vector
503 widths are supported properly by the middle-end. */
504 #define UNITS_PER_SIMD_WORD \
505 (TARGET_NEON ? (TARGET_NEON_VECTORIZE_QUAD ? 16 : 8) : UNITS_PER_WORD)
506
507 /* True if natural alignment is used for doubleword types. */
508 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
509
510 #define DOUBLEWORD_ALIGNMENT 64
511
512 #define PARM_BOUNDARY 32
513
514 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
515
516 #define PREFERRED_STACK_BOUNDARY \
517 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
518
519 #define FUNCTION_BOUNDARY 32
520
521 /* The lowest bit is used to indicate Thumb-mode functions, so the
522 vbit must go into the delta field of pointers to member
523 functions. */
524 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
525
526 #define EMPTY_FIELD_BOUNDARY 32
527
528 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
529
530 /* XXX Blah -- this macro is used directly by libobjc. Since it
531 supports no vector modes, cut out the complexity and fall back
532 on BIGGEST_FIELD_ALIGNMENT. */
533 #ifdef IN_TARGET_LIBS
534 #define BIGGEST_FIELD_ALIGNMENT 64
535 #endif
536
537 /* Make strings word-aligned so strcpy from constants will be faster. */
538 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
539
540 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
541 ((TREE_CODE (EXP) == STRING_CST \
542 && !optimize_size \
543 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
544 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
545
546 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
547 value set in previous versions of this toolchain was 8, which produces more
548 compact structures. The command line option -mstructure_size_boundary=<n>
549 can be used to change this value. For compatibility with the ARM SDK
550 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
551 0020D) page 2-20 says "Structures are aligned on word boundaries".
552 The AAPCS specifies a value of 8. */
553 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
554 extern int arm_structure_size_boundary;
555
556 /* This is the value used to initialize arm_structure_size_boundary. If a
557 particular arm target wants to change the default value it should change
558 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
559 for an example of this. */
560 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
561 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
562 #endif
563
564 /* Nonzero if move instructions will actually fail to work
565 when given unaligned data. */
566 #define STRICT_ALIGNMENT 1
567
568 /* wchar_t is unsigned under the AAPCS. */
569 #ifndef WCHAR_TYPE
570 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
571
572 #define WCHAR_TYPE_SIZE BITS_PER_WORD
573 #endif
574
575 #ifndef SIZE_TYPE
576 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
577 #endif
578
579 #ifndef PTRDIFF_TYPE
580 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
581 #endif
582
583 /* AAPCS requires that structure alignment is affected by bitfields. */
584 #ifndef PCC_BITFIELD_TYPE_MATTERS
585 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
586 #endif
587
588 \f
589 /* Standard register usage. */
590
591 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
592 (S - saved over call).
593
594 r0 * argument word/integer result
595 r1-r3 argument word
596
597 r4-r8 S register variable
598 r9 S (rfp) register variable (real frame pointer)
599
600 r10 F S (sl) stack limit (used by -mapcs-stack-check)
601 r11 F S (fp) argument pointer
602 r12 (ip) temp workspace
603 r13 F S (sp) lower end of current stack frame
604 r14 (lr) link address/workspace
605 r15 F (pc) program counter
606
607 f0 floating point result
608 f1-f3 floating point scratch
609
610 f4-f7 S floating point variable
611
612 cc This is NOT a real register, but is used internally
613 to represent things that use or set the condition
614 codes.
615 sfp This isn't either. It is used during rtl generation
616 since the offset between the frame pointer and the
617 auto's isn't known until after register allocation.
618 afp Nor this, we only need this because of non-local
619 goto. Without it fp appears to be used and the
620 elimination code won't get rid of sfp. It tracks
621 fp exactly at all times.
622
623 *: See CONDITIONAL_REGISTER_USAGE */
624
625 /*
626 mvf0 Cirrus floating point result
627 mvf1-mvf3 Cirrus floating point scratch
628 mvf4-mvf15 S Cirrus floating point variable. */
629
630 /* s0-s15 VFP scratch (aka d0-d7).
631 s16-s31 S VFP variable (aka d8-d15).
632 vfpcc Not a real register. Represents the VFP condition
633 code flags. */
634
635 /* The stack backtrace structure is as follows:
636 fp points to here: | save code pointer | [fp]
637 | return link value | [fp, #-4]
638 | return sp value | [fp, #-8]
639 | return fp value | [fp, #-12]
640 [| saved r10 value |]
641 [| saved r9 value |]
642 [| saved r8 value |]
643 [| saved r7 value |]
644 [| saved r6 value |]
645 [| saved r5 value |]
646 [| saved r4 value |]
647 [| saved r3 value |]
648 [| saved r2 value |]
649 [| saved r1 value |]
650 [| saved r0 value |]
651 [| saved f7 value |] three words
652 [| saved f6 value |] three words
653 [| saved f5 value |] three words
654 [| saved f4 value |] three words
655 r0-r3 are not normally saved in a C function. */
656
657 /* 1 for registers that have pervasive standard uses
658 and are not available for the register allocator. */
659 #define FIXED_REGISTERS \
660 { \
661 0,0,0,0,0,0,0,0, \
662 0,0,0,0,0,1,0,1, \
663 0,0,0,0,0,0,0,0, \
664 1,1,1, \
665 1,1,1,1,1,1,1,1, \
666 1,1,1,1,1,1,1,1, \
667 1,1,1,1,1,1,1,1, \
668 1,1,1,1,1,1,1,1, \
669 1,1,1,1, \
670 1,1,1,1,1,1,1,1, \
671 1,1,1,1,1,1,1,1, \
672 1,1,1,1,1,1,1,1, \
673 1,1,1,1,1,1,1,1, \
674 1,1,1,1,1,1,1,1, \
675 1,1,1,1,1,1,1,1, \
676 1,1,1,1,1,1,1,1, \
677 1,1,1,1,1,1,1,1, \
678 1 \
679 }
680
681 /* 1 for registers not available across function calls.
682 These must include the FIXED_REGISTERS and also any
683 registers that can be used without being saved.
684 The latter must include the registers where values are returned
685 and the register where structure-value addresses are passed.
686 Aside from that, you can include as many other registers as you like.
687 The CC is not preserved over function calls on the ARM 6, so it is
688 easier to assume this for all. SFP is preserved, since FP is. */
689 #define CALL_USED_REGISTERS \
690 { \
691 1,1,1,1,0,0,0,0, \
692 0,0,0,0,1,1,1,1, \
693 1,1,1,1,0,0,0,0, \
694 1,1,1, \
695 1,1,1,1,1,1,1,1, \
696 1,1,1,1,1,1,1,1, \
697 1,1,1,1,1,1,1,1, \
698 1,1,1,1,1,1,1,1, \
699 1,1,1,1, \
700 1,1,1,1,1,1,1,1, \
701 1,1,1,1,1,1,1,1, \
702 1,1,1,1,1,1,1,1, \
703 1,1,1,1,1,1,1,1, \
704 1,1,1,1,1,1,1,1, \
705 1,1,1,1,1,1,1,1, \
706 1,1,1,1,1,1,1,1, \
707 1,1,1,1,1,1,1,1, \
708 1 \
709 }
710
711 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
712 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
713 #endif
714
715 #define CONDITIONAL_REGISTER_USAGE \
716 { \
717 int regno; \
718 \
719 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \
720 { \
721 for (regno = FIRST_FPA_REGNUM; \
722 regno <= LAST_FPA_REGNUM; ++regno) \
723 fixed_regs[regno] = call_used_regs[regno] = 1; \
724 } \
725 \
726 if (TARGET_THUMB && optimize_size) \
727 { \
728 /* When optimizing for size, it's better not to use \
729 the HI regs, because of the overhead of stacking \
730 them. */ \
731 /* ??? Is this still true for thumb2? */ \
732 for (regno = FIRST_HI_REGNUM; \
733 regno <= LAST_HI_REGNUM; ++regno) \
734 fixed_regs[regno] = call_used_regs[regno] = 1; \
735 } \
736 \
737 /* The link register can be clobbered by any branch insn, \
738 but we have no way to track that at present, so mark \
739 it as unavailable. */ \
740 if (TARGET_THUMB1) \
741 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
742 \
743 if (TARGET_32BIT && TARGET_HARD_FLOAT) \
744 { \
745 if (TARGET_MAVERICK) \
746 { \
747 for (regno = FIRST_FPA_REGNUM; \
748 regno <= LAST_FPA_REGNUM; ++ regno) \
749 fixed_regs[regno] = call_used_regs[regno] = 1; \
750 for (regno = FIRST_CIRRUS_FP_REGNUM; \
751 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
752 { \
753 fixed_regs[regno] = 0; \
754 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
755 } \
756 } \
757 if (TARGET_VFP) \
758 { \
759 /* VFPv3 registers are disabled when earlier VFP \
760 versions are selected due to the definition of \
761 LAST_VFP_REGNUM. */ \
762 for (regno = FIRST_VFP_REGNUM; \
763 regno <= LAST_VFP_REGNUM; ++ regno) \
764 { \
765 fixed_regs[regno] = 0; \
766 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 \
767 || regno >= FIRST_VFP_REGNUM + 32; \
768 } \
769 } \
770 } \
771 \
772 if (TARGET_REALLY_IWMMXT) \
773 { \
774 regno = FIRST_IWMMXT_GR_REGNUM; \
775 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
776 and wCG1 as call-preserved registers. The 2002/11/21 \
777 revision changed this so that all wCG registers are \
778 scratch registers. */ \
779 for (regno = FIRST_IWMMXT_GR_REGNUM; \
780 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
781 fixed_regs[regno] = 0; \
782 /* The XScale ABI has wR0 - wR9 as scratch registers, \
783 the rest as call-preserved registers. */ \
784 for (regno = FIRST_IWMMXT_REGNUM; \
785 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
786 { \
787 fixed_regs[regno] = 0; \
788 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
789 } \
790 } \
791 \
792 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
793 { \
794 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
795 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
796 } \
797 else if (TARGET_APCS_STACK) \
798 { \
799 fixed_regs[10] = 1; \
800 call_used_regs[10] = 1; \
801 } \
802 /* -mcaller-super-interworking reserves r11 for calls to \
803 _interwork_r11_call_via_rN(). Making the register global \
804 is an easy way of ensuring that it remains valid for all \
805 calls. */ \
806 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
807 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
808 { \
809 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
810 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
811 if (TARGET_CALLER_INTERWORKING) \
812 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
813 } \
814 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
815 }
816
817 /* These are a couple of extensions to the formats accepted
818 by asm_fprintf:
819 %@ prints out ASM_COMMENT_START
820 %r prints out REGISTER_PREFIX reg_names[arg] */
821 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
822 case '@': \
823 fputs (ASM_COMMENT_START, FILE); \
824 break; \
825 \
826 case 'r': \
827 fputs (REGISTER_PREFIX, FILE); \
828 fputs (reg_names [va_arg (ARGS, int)], FILE); \
829 break;
830
831 /* Round X up to the nearest word. */
832 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
833
834 /* Convert fron bytes to ints. */
835 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
836
837 /* The number of (integer) registers required to hold a quantity of type MODE.
838 Also used for VFP registers. */
839 #define ARM_NUM_REGS(MODE) \
840 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
841
842 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
843 #define ARM_NUM_REGS2(MODE, TYPE) \
844 ARM_NUM_INTS ((MODE) == BLKmode ? \
845 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
846
847 /* The number of (integer) argument register available. */
848 #define NUM_ARG_REGS 4
849
850 /* Return the register number of the N'th (integer) argument. */
851 #define ARG_REGISTER(N) (N - 1)
852
853 /* Specify the registers used for certain standard purposes.
854 The values of these macros are register numbers. */
855
856 /* The number of the last argument register. */
857 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
858
859 /* The numbers of the Thumb register ranges. */
860 #define FIRST_LO_REGNUM 0
861 #define LAST_LO_REGNUM 7
862 #define FIRST_HI_REGNUM 8
863 #define LAST_HI_REGNUM 11
864
865 #ifndef TARGET_UNWIND_INFO
866 /* We use sjlj exceptions for backwards compatibility. */
867 #define MUST_USE_SJLJ_EXCEPTIONS 1
868 #endif
869
870 /* We can generate DWARF2 Unwind info, even though we don't use it. */
871 #define DWARF2_UNWIND_INFO 1
872
873 /* Use r0 and r1 to pass exception handling information. */
874 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
875
876 /* The register that holds the return address in exception handlers. */
877 #define ARM_EH_STACKADJ_REGNUM 2
878 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
879
880 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
881 as an invisible last argument (possible since varargs don't exist in
882 Pascal), so the following is not true. */
883 #define STATIC_CHAIN_REGNUM 12
884
885 /* Define this to be where the real frame pointer is if it is not possible to
886 work out the offset between the frame pointer and the automatic variables
887 until after register allocation has taken place. FRAME_POINTER_REGNUM
888 should point to a special register that we will make sure is eliminated.
889
890 For the Thumb we have another problem. The TPCS defines the frame pointer
891 as r11, and GCC believes that it is always possible to use the frame pointer
892 as base register for addressing purposes. (See comments in
893 find_reloads_address()). But - the Thumb does not allow high registers,
894 including r11, to be used as base address registers. Hence our problem.
895
896 The solution used here, and in the old thumb port is to use r7 instead of
897 r11 as the hard frame pointer and to have special code to generate
898 backtrace structures on the stack (if required to do so via a command line
899 option) using r11. This is the only 'user visible' use of r11 as a frame
900 pointer. */
901 #define ARM_HARD_FRAME_POINTER_REGNUM 11
902 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
903
904 #define HARD_FRAME_POINTER_REGNUM \
905 (TARGET_ARM \
906 ? ARM_HARD_FRAME_POINTER_REGNUM \
907 : THUMB_HARD_FRAME_POINTER_REGNUM)
908
909 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
910
911 /* Register to use for pushing function arguments. */
912 #define STACK_POINTER_REGNUM SP_REGNUM
913
914 /* ARM floating pointer registers. */
915 #define FIRST_FPA_REGNUM 16
916 #define LAST_FPA_REGNUM 23
917 #define IS_FPA_REGNUM(REGNUM) \
918 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
919
920 #define FIRST_IWMMXT_GR_REGNUM 43
921 #define LAST_IWMMXT_GR_REGNUM 46
922 #define FIRST_IWMMXT_REGNUM 47
923 #define LAST_IWMMXT_REGNUM 62
924 #define IS_IWMMXT_REGNUM(REGNUM) \
925 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
926 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
927 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
928
929 /* Base register for access to local variables of the function. */
930 #define FRAME_POINTER_REGNUM 25
931
932 /* Base register for access to arguments of the function. */
933 #define ARG_POINTER_REGNUM 26
934
935 #define FIRST_CIRRUS_FP_REGNUM 27
936 #define LAST_CIRRUS_FP_REGNUM 42
937 #define IS_CIRRUS_REGNUM(REGNUM) \
938 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
939
940 #define FIRST_VFP_REGNUM 63
941 #define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */
942 #define LAST_VFP_REGNUM \
943 (TARGET_VFP3 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
944
945 #define IS_VFP_REGNUM(REGNUM) \
946 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
947
948 /* VFP registers are split into two types: those defined by VFP versions < 3
949 have D registers overlaid on consecutive pairs of S registers. VFP version 3
950 defines 16 new D registers (d16-d31) which, for simplicity and correctness
951 in various parts of the backend, we implement as "fake" single-precision
952 registers (which would be S32-S63, but cannot be used in that way). The
953 following macros define these ranges of registers. */
954 #define LAST_LO_VFP_REGNUM 94
955 #define FIRST_HI_VFP_REGNUM 95
956 #define LAST_HI_VFP_REGNUM 126
957
958 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
959 ((REGNUM) <= LAST_LO_VFP_REGNUM)
960
961 /* DFmode values are only valid in even register pairs. */
962 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
963 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
964
965 /* Neon Quad values must start at a multiple of four registers. */
966 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
967 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
968
969 /* Neon structures of vectors must be in even register pairs and there
970 must be enough registers available. Because of various patterns
971 requiring quad registers, we require them to start at a multiple of
972 four. */
973 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
974 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
975 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
976
977 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
978 /* + 16 Cirrus registers take us up to 43. */
979 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
980 /* VFP (VFP3) adds 32 (64) + 1 more. */
981 #define FIRST_PSEUDO_REGISTER 128
982
983 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
984
985 /* Value should be nonzero if functions must have frame pointers.
986 Zero means the frame pointer need not be set up (and parms may be accessed
987 via the stack pointer) in functions that seem suitable.
988 If we have to have a frame pointer we might as well make use of it.
989 APCS says that the frame pointer does not need to be pushed in leaf
990 functions, or simple tail call functions. */
991
992 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
993 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
994 #endif
995
996 #define FRAME_POINTER_REQUIRED \
997 (current_function_has_nonlocal_label \
998 || SUBTARGET_FRAME_POINTER_REQUIRED \
999 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
1000
1001 /* Return number of consecutive hard regs needed starting at reg REGNO
1002 to hold something of mode MODE.
1003 This is ordinarily the length in words of a value of mode MODE
1004 but can be less for certain modes in special long registers.
1005
1006 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1007 mode. */
1008 #define HARD_REGNO_NREGS(REGNO, MODE) \
1009 ((TARGET_32BIT \
1010 && REGNO >= FIRST_FPA_REGNUM \
1011 && REGNO != FRAME_POINTER_REGNUM \
1012 && REGNO != ARG_POINTER_REGNUM) \
1013 && !IS_VFP_REGNUM (REGNO) \
1014 ? 1 : ARM_NUM_REGS (MODE))
1015
1016 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1017 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1018 arm_hard_regno_mode_ok ((REGNO), (MODE))
1019
1020 /* Value is 1 if it is a good idea to tie two pseudo registers
1021 when one has mode MODE1 and one has mode MODE2.
1022 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1023 for any hard reg, then this must be 0 for correct output. */
1024 #define MODES_TIEABLE_P(MODE1, MODE2) \
1025 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1026
1027 #define VALID_IWMMXT_REG_MODE(MODE) \
1028 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1029
1030 /* Modes valid for Neon D registers. */
1031 #define VALID_NEON_DREG_MODE(MODE) \
1032 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1033 || (MODE) == V2SFmode || (MODE) == DImode)
1034
1035 /* Modes valid for Neon Q registers. */
1036 #define VALID_NEON_QREG_MODE(MODE) \
1037 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1038 || (MODE) == V4SFmode || (MODE) == V2DImode)
1039
1040 /* Structure modes valid for Neon registers. */
1041 #define VALID_NEON_STRUCT_MODE(MODE) \
1042 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1043 || (MODE) == CImode || (MODE) == XImode)
1044
1045 /* The order in which register should be allocated. It is good to use ip
1046 since no saving is required (though calls clobber it) and it never contains
1047 function parameters. It is quite good to use lr since other calls may
1048 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1049 least likely to contain a function parameter; in addition results are
1050 returned in r0.
1051 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1052 then D8-D15. The reason for doing this is to attempt to reduce register
1053 pressure when both single- and double-precision registers are used in a
1054 function. */
1055
1056 #define REG_ALLOC_ORDER \
1057 { \
1058 3, 2, 1, 0, 12, 14, 4, 5, \
1059 6, 7, 8, 10, 9, 11, 13, 15, \
1060 16, 17, 18, 19, 20, 21, 22, 23, \
1061 27, 28, 29, 30, 31, 32, 33, 34, \
1062 35, 36, 37, 38, 39, 40, 41, 42, \
1063 43, 44, 45, 46, 47, 48, 49, 50, \
1064 51, 52, 53, 54, 55, 56, 57, 58, \
1065 59, 60, 61, 62, \
1066 24, 25, 26, \
1067 95, 96, 97, 98, 99, 100, 101, 102, \
1068 103, 104, 105, 106, 107, 108, 109, 110, \
1069 111, 112, 113, 114, 115, 116, 117, 118, \
1070 119, 120, 121, 122, 123, 124, 125, 126, \
1071 78, 77, 76, 75, 74, 73, 72, 71, \
1072 70, 69, 68, 67, 66, 65, 64, 63, \
1073 79, 80, 81, 82, 83, 84, 85, 86, \
1074 87, 88, 89, 90, 91, 92, 93, 94, \
1075 127 \
1076 }
1077
1078 /* Interrupt functions can only use registers that have already been
1079 saved by the prologue, even if they would normally be
1080 call-clobbered. */
1081 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1082 (! IS_INTERRUPT (cfun->machine->func_type) || \
1083 df_regs_ever_live_p (DST))
1084 \f
1085 /* Register and constant classes. */
1086
1087 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1088 Now that the Thumb is involved it has become more complicated. */
1089 enum reg_class
1090 {
1091 NO_REGS,
1092 FPA_REGS,
1093 CIRRUS_REGS,
1094 VFP_D0_D7_REGS,
1095 VFP_LO_REGS,
1096 VFP_HI_REGS,
1097 VFP_REGS,
1098 IWMMXT_GR_REGS,
1099 IWMMXT_REGS,
1100 LO_REGS,
1101 STACK_REG,
1102 BASE_REGS,
1103 HI_REGS,
1104 CC_REG,
1105 VFPCC_REG,
1106 GENERAL_REGS,
1107 ALL_REGS,
1108 LIM_REG_CLASSES
1109 };
1110
1111 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1112
1113 /* Give names of register classes as strings for dump file. */
1114 #define REG_CLASS_NAMES \
1115 { \
1116 "NO_REGS", \
1117 "FPA_REGS", \
1118 "CIRRUS_REGS", \
1119 "VFP_D0_D7_REGS", \
1120 "VFP_LO_REGS", \
1121 "VFP_HI_REGS", \
1122 "VFP_REGS", \
1123 "IWMMXT_GR_REGS", \
1124 "IWMMXT_REGS", \
1125 "LO_REGS", \
1126 "STACK_REG", \
1127 "BASE_REGS", \
1128 "HI_REGS", \
1129 "CC_REG", \
1130 "VFPCC_REG", \
1131 "GENERAL_REGS", \
1132 "ALL_REGS", \
1133 }
1134
1135 /* Define which registers fit in which classes.
1136 This is an initializer for a vector of HARD_REG_SET
1137 of length N_REG_CLASSES. */
1138 #define REG_CLASS_CONTENTS \
1139 { \
1140 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1141 { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1142 { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \
1143 { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1144 { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \
1145 { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \
1146 { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \
1147 { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1148 { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \
1149 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1150 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1151 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1152 { 0x0000FF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1153 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1154 { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1155 { 0x0200FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1156 { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1157 }
1158
1159 /* Any of the VFP register classes. */
1160 #define IS_VFP_CLASS(X) \
1161 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1162 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1163
1164 /* The same information, inverted:
1165 Return the class number of the smallest class containing
1166 reg number REGNO. This could be a conditional expression
1167 or could index an array. */
1168 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1169
1170 /* FPA registers can't do subreg as all values are reformatted to internal
1171 precision. VFP registers may only be accessed in the mode they
1172 were set. */
1173 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1174 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1175 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1176 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1177 : 0)
1178
1179 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1180 using r0-r4 for function arguments, r7 for the stack frame and don't
1181 have enough left over to do doubleword arithmetic. */
1182 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1183 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1184 || (CLASS) == CC_REG)
1185
1186 /* The class value for index registers, and the one for base regs. */
1187 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1188 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1189
1190 /* For the Thumb the high registers cannot be used as base registers
1191 when addressing quantities in QI or HI mode; if we don't know the
1192 mode, then we must be conservative. */
1193 #define MODE_BASE_REG_CLASS(MODE) \
1194 (TARGET_32BIT ? GENERAL_REGS : \
1195 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1196
1197 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1198 instead of BASE_REGS. */
1199 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1200
1201 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1202 registers explicitly used in the rtl to be used as spill registers
1203 but prevents the compiler from extending the lifetime of these
1204 registers. */
1205 #define SMALL_REGISTER_CLASSES TARGET_THUMB1
1206
1207 /* Given an rtx X being reloaded into a reg required to be
1208 in class CLASS, return the class of reg to actually use.
1209 In general this is just CLASS, but for the Thumb core registers and
1210 immediate constants we prefer a LO_REGS class or a subset. */
1211 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1212 (TARGET_ARM ? (CLASS) : \
1213 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
1214 || (CLASS) == NO_REGS ? LO_REGS : (CLASS)))
1215
1216 /* Must leave BASE_REGS reloads alone */
1217 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1218 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1219 ? ((true_regnum (X) == -1 ? LO_REGS \
1220 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1221 : NO_REGS)) \
1222 : NO_REGS)
1223
1224 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1225 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1226 ? ((true_regnum (X) == -1 ? LO_REGS \
1227 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1228 : NO_REGS)) \
1229 : NO_REGS)
1230
1231 /* Return the register class of a scratch register needed to copy IN into
1232 or out of a register in CLASS in MODE. If it can be done directly,
1233 NO_REGS is returned. */
1234 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1235 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1236 ((TARGET_VFP && TARGET_HARD_FLOAT \
1237 && IS_VFP_CLASS (CLASS)) \
1238 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1239 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1240 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1241 : TARGET_32BIT \
1242 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1243 ? GENERAL_REGS : NO_REGS) \
1244 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1245
1246 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1247 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1248 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1249 ((TARGET_VFP && TARGET_HARD_FLOAT \
1250 && IS_VFP_CLASS (CLASS)) \
1251 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1252 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1253 coproc_secondary_reload_class (MODE, X, TRUE) : \
1254 /* Cannot load constants into Cirrus registers. */ \
1255 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1256 && (CLASS) == CIRRUS_REGS \
1257 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1258 ? GENERAL_REGS : \
1259 (TARGET_32BIT ? \
1260 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1261 && CONSTANT_P (X)) \
1262 ? GENERAL_REGS : \
1263 (((MODE) == HImode && ! arm_arch4 \
1264 && (GET_CODE (X) == MEM \
1265 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1266 && true_regnum (X) == -1))) \
1267 ? GENERAL_REGS : NO_REGS) \
1268 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1269
1270 /* Try a machine-dependent way of reloading an illegitimate address
1271 operand. If we find one, push the reload and jump to WIN. This
1272 macro is used in only one place: `find_reloads_address' in reload.c.
1273
1274 For the ARM, we wish to handle large displacements off a base
1275 register by splitting the addend across a MOV and the mem insn.
1276 This can cut the number of reloads needed. */
1277 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1278 do \
1279 { \
1280 if (GET_CODE (X) == PLUS \
1281 && GET_CODE (XEXP (X, 0)) == REG \
1282 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1283 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1284 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1285 { \
1286 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1287 HOST_WIDE_INT low, high; \
1288 \
1289 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1290 low = ((val & 0xf) ^ 0x8) - 0x8; \
1291 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1292 /* Need to be careful, -256 is not a valid offset. */ \
1293 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1294 else if (MODE == SImode \
1295 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1296 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1297 /* Need to be careful, -4096 is not a valid offset. */ \
1298 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1299 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1300 /* Need to be careful, -256 is not a valid offset. */ \
1301 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1302 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1303 && TARGET_HARD_FLOAT && TARGET_FPA) \
1304 /* Need to be careful, -1024 is not a valid offset. */ \
1305 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1306 else \
1307 break; \
1308 \
1309 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1310 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1311 - (unsigned HOST_WIDE_INT) 0x80000000); \
1312 /* Check for overflow or zero */ \
1313 if (low == 0 || high == 0 || (high + low != val)) \
1314 break; \
1315 \
1316 /* Reload the high part into a base reg; leave the low part \
1317 in the mem. */ \
1318 X = gen_rtx_PLUS (GET_MODE (X), \
1319 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1320 GEN_INT (high)), \
1321 GEN_INT (low)); \
1322 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1323 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1324 VOIDmode, 0, 0, OPNUM, TYPE); \
1325 goto WIN; \
1326 } \
1327 } \
1328 while (0)
1329
1330 /* XXX If an HImode FP+large_offset address is converted to an HImode
1331 SP+large_offset address, then reload won't know how to fix it. It sees
1332 only that SP isn't valid for HImode, and so reloads the SP into an index
1333 register, but the resulting address is still invalid because the offset
1334 is too big. We fix it here instead by reloading the entire address. */
1335 /* We could probably achieve better results by defining PROMOTE_MODE to help
1336 cope with the variances between the Thumb's signed and unsigned byte and
1337 halfword load instructions. */
1338 /* ??? This should be safe for thumb2, but we may be able to do better. */
1339 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1340 do { \
1341 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1342 if (new_x) \
1343 { \
1344 X = new_x; \
1345 goto WIN; \
1346 } \
1347 } while (0)
1348
1349 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1350 if (TARGET_ARM) \
1351 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1352 else \
1353 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1354
1355 /* Return the maximum number of consecutive registers
1356 needed to represent mode MODE in a register of class CLASS.
1357 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1358 #define CLASS_MAX_NREGS(CLASS, MODE) \
1359 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1360
1361 /* If defined, gives a class of registers that cannot be used as the
1362 operand of a SUBREG that changes the mode of the object illegally. */
1363
1364 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1365 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1366 (TARGET_32BIT ? \
1367 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1368 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1369 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 10 : \
1370 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 10 : \
1371 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1372 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1373 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1374 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1375 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1376 2) \
1377 : \
1378 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1379 \f
1380 /* Stack layout; function entry, exit and calling. */
1381
1382 /* Define this if pushing a word on the stack
1383 makes the stack pointer a smaller address. */
1384 #define STACK_GROWS_DOWNWARD 1
1385
1386 /* Define this to nonzero if the nominal address of the stack frame
1387 is at the high-address end of the local variables;
1388 that is, each additional local variable allocated
1389 goes at a more negative offset in the frame. */
1390 #define FRAME_GROWS_DOWNWARD 1
1391
1392 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1393 When present, it is one word in size, and sits at the top of the frame,
1394 between the soft frame pointer and either r7 or r11.
1395
1396 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1397 and only then if some outgoing arguments are passed on the stack. It would
1398 be tempting to also check whether the stack arguments are passed by indirect
1399 calls, but there seems to be no reason in principle why a post-reload pass
1400 couldn't convert a direct call into an indirect one. */
1401 #define CALLER_INTERWORKING_SLOT_SIZE \
1402 (TARGET_CALLER_INTERWORKING \
1403 && current_function_outgoing_args_size != 0 \
1404 ? UNITS_PER_WORD : 0)
1405
1406 /* Offset within stack frame to start allocating local variables at.
1407 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1408 first local allocated. Otherwise, it is the offset to the BEGINNING
1409 of the first local allocated. */
1410 #define STARTING_FRAME_OFFSET 0
1411
1412 /* If we generate an insn to push BYTES bytes,
1413 this says how many the stack pointer really advances by. */
1414 /* The push insns do not do this rounding implicitly.
1415 So don't define this. */
1416 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1417
1418 /* Define this if the maximum size of all the outgoing args is to be
1419 accumulated and pushed during the prologue. The amount can be
1420 found in the variable current_function_outgoing_args_size. */
1421 #define ACCUMULATE_OUTGOING_ARGS 1
1422
1423 /* Offset of first parameter from the argument pointer register value. */
1424 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1425
1426 /* Value is the number of byte of arguments automatically
1427 popped when returning from a subroutine call.
1428 FUNDECL is the declaration node of the function (as a tree),
1429 FUNTYPE is the data type of the function (as a tree),
1430 or for a library call it is an identifier node for the subroutine name.
1431 SIZE is the number of bytes of arguments passed on the stack.
1432
1433 On the ARM, the caller does not pop any of its arguments that were passed
1434 on the stack. */
1435 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1436
1437 /* Define how to find the value returned by a library function
1438 assuming the value has mode MODE. */
1439 #define LIBCALL_VALUE(MODE) \
1440 (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1441 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1442 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1443 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1444 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1445 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1446 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1447 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1448 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1449
1450 /* Define how to find the value returned by a function.
1451 VALTYPE is the data type of the value (as a tree).
1452 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1453 otherwise, FUNC is 0. */
1454 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1455 arm_function_value (VALTYPE, FUNC);
1456
1457 /* 1 if N is a possible register number for a function value.
1458 On the ARM, only r0 and f0 can return results. */
1459 /* On a Cirrus chip, mvf0 can return results. */
1460 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1461 ((REGNO) == ARG_REGISTER (1) \
1462 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1463 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1464 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1465 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
1466 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1467
1468 /* Amount of memory needed for an untyped call to save all possible return
1469 registers. */
1470 #define APPLY_RESULT_SIZE arm_apply_result_size()
1471
1472 /* How large values are returned */
1473 /* A C expression which can inhibit the returning of certain function values
1474 in registers, based on the type of value. */
1475 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1476
1477 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1478 values must be in memory. On the ARM, they need only do so if larger
1479 than a word, or if they contain elements offset from zero in the struct. */
1480 #define DEFAULT_PCC_STRUCT_RETURN 0
1481
1482 /* These bits describe the different types of function supported
1483 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1484 normal function and an interworked function, for example. Knowing the
1485 type of a function is important for determining its prologue and
1486 epilogue sequences.
1487 Note value 7 is currently unassigned. Also note that the interrupt
1488 function types all have bit 2 set, so that they can be tested for easily.
1489 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1490 machine_function structure is initialized (to zero) func_type will
1491 default to unknown. This will force the first use of arm_current_func_type
1492 to call arm_compute_func_type. */
1493 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1494 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1495 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1496 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1497 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1498 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1499
1500 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1501
1502 /* In addition functions can have several type modifiers,
1503 outlined by these bit masks: */
1504 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1505 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1506 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1507 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1508 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1509
1510 /* Some macros to test these flags. */
1511 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1512 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1513 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1514 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1515 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1516 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1517
1518
1519 /* Structure used to hold the function stack frame layout. Offsets are
1520 relative to the stack pointer on function entry. Positive offsets are
1521 in the direction of stack growth.
1522 Only soft_frame is used in thumb mode. */
1523
1524 typedef struct arm_stack_offsets GTY(())
1525 {
1526 int saved_args; /* ARG_POINTER_REGNUM. */
1527 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1528 int saved_regs;
1529 int soft_frame; /* FRAME_POINTER_REGNUM. */
1530 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1531 int outgoing_args; /* STACK_POINTER_REGNUM. */
1532 }
1533 arm_stack_offsets;
1534
1535 /* A C structure for machine-specific, per-function data.
1536 This is added to the cfun structure. */
1537 typedef struct machine_function GTY(())
1538 {
1539 /* Additional stack adjustment in __builtin_eh_throw. */
1540 rtx eh_epilogue_sp_ofs;
1541 /* Records if LR has to be saved for far jumps. */
1542 int far_jump_used;
1543 /* Records if ARG_POINTER was ever live. */
1544 int arg_pointer_live;
1545 /* Records if the save of LR has been eliminated. */
1546 int lr_save_eliminated;
1547 /* The size of the stack frame. Only valid after reload. */
1548 arm_stack_offsets stack_offsets;
1549 /* Records the type of the current function. */
1550 unsigned long func_type;
1551 /* Record if the function has a variable argument list. */
1552 int uses_anonymous_args;
1553 /* Records if sibcalls are blocked because an argument
1554 register is needed to preserve stack alignment. */
1555 int sibcall_blocked;
1556 /* The PIC register for this function. This might be a pseudo. */
1557 rtx pic_reg;
1558 /* Labels for per-function Thumb call-via stubs. One per potential calling
1559 register. We can never call via LR or PC. We can call via SP if a
1560 trampoline happens to be on the top of the stack. */
1561 rtx call_via[14];
1562 }
1563 machine_function;
1564
1565 /* As in the machine_function, a global set of call-via labels, for code
1566 that is in text_section. */
1567 extern GTY(()) rtx thumb_call_via_label[14];
1568
1569 /* A C type for declaring a variable that is used as the first argument of
1570 `FUNCTION_ARG' and other related values. For some target machines, the
1571 type `int' suffices and can hold the number of bytes of argument so far. */
1572 typedef struct
1573 {
1574 /* This is the number of registers of arguments scanned so far. */
1575 int nregs;
1576 /* This is the number of iWMMXt register arguments scanned so far. */
1577 int iwmmxt_nregs;
1578 int named_count;
1579 int nargs;
1580 int can_split;
1581 } CUMULATIVE_ARGS;
1582
1583 /* Define where to put the arguments to a function.
1584 Value is zero to push the argument on the stack,
1585 or a hard register in which to store the argument.
1586
1587 MODE is the argument's machine mode.
1588 TYPE is the data type of the argument (as a tree).
1589 This is null for libcalls where that information may
1590 not be available.
1591 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1592 the preceding args and about the function being called.
1593 NAMED is nonzero if this argument is a named parameter
1594 (otherwise it is an extra parameter matching an ellipsis).
1595
1596 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1597 other arguments are passed on the stack. If (NAMED == 0) (which happens
1598 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1599 defined), say it is passed in the stack (function_prologue will
1600 indeed make it pass in the stack if necessary). */
1601 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1602 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1603
1604 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1605 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1606
1607 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1608 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1609
1610 /* For AAPCS, padding should never be below the argument. For other ABIs,
1611 * mimic the default. */
1612 #define PAD_VARARGS_DOWN \
1613 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1614
1615 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1616 for a call to a function whose data type is FNTYPE.
1617 For a library call, FNTYPE is 0.
1618 On the ARM, the offset starts at 0. */
1619 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1620 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1621
1622 /* Update the data in CUM to advance over an argument
1623 of mode MODE and data type TYPE.
1624 (TYPE is null for libcalls where that information may not be available.) */
1625 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1626 (CUM).nargs += 1; \
1627 if (arm_vector_mode_supported_p (MODE) \
1628 && (CUM).named_count > (CUM).nargs \
1629 && TARGET_IWMMXT_ABI) \
1630 (CUM).iwmmxt_nregs += 1; \
1631 else \
1632 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1633
1634 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1635 argument with the specified mode and type. If it is not defined,
1636 `PARM_BOUNDARY' is used for all arguments. */
1637 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1638 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1639 ? DOUBLEWORD_ALIGNMENT \
1640 : PARM_BOUNDARY )
1641
1642 /* 1 if N is a possible register number for function argument passing.
1643 On the ARM, r0-r3 are used to pass args. */
1644 #define FUNCTION_ARG_REGNO_P(REGNO) \
1645 (IN_RANGE ((REGNO), 0, 3) \
1646 || (TARGET_IWMMXT_ABI \
1647 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1648
1649 \f
1650 /* If your target environment doesn't prefix user functions with an
1651 underscore, you may wish to re-define this to prevent any conflicts. */
1652 #ifndef ARM_MCOUNT_NAME
1653 #define ARM_MCOUNT_NAME "*mcount"
1654 #endif
1655
1656 /* Call the function profiler with a given profile label. The Acorn
1657 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1658 On the ARM the full profile code will look like:
1659 .data
1660 LP1
1661 .word 0
1662 .text
1663 mov ip, lr
1664 bl mcount
1665 .word LP1
1666
1667 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1668 will output the .text section.
1669
1670 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1671 ``prof'' doesn't seem to mind about this!
1672
1673 Note - this version of the code is designed to work in both ARM and
1674 Thumb modes. */
1675 #ifndef ARM_FUNCTION_PROFILER
1676 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1677 { \
1678 char temp[20]; \
1679 rtx sym; \
1680 \
1681 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1682 IP_REGNUM, LR_REGNUM); \
1683 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1684 fputc ('\n', STREAM); \
1685 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1686 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1687 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1688 }
1689 #endif
1690
1691 #ifdef THUMB_FUNCTION_PROFILER
1692 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1693 if (TARGET_ARM) \
1694 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1695 else \
1696 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1697 #else
1698 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1699 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1700 #endif
1701
1702 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1703 the stack pointer does not matter. The value is tested only in
1704 functions that have frame pointers.
1705 No definition is equivalent to always zero.
1706
1707 On the ARM, the function epilogue recovers the stack pointer from the
1708 frame. */
1709 #define EXIT_IGNORE_STACK 1
1710
1711 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM)
1712
1713 /* Determine if the epilogue should be output as RTL.
1714 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1715 /* This is disabled for Thumb-2 because it will confuse the
1716 conditional insn counter. */
1717 #define USE_RETURN_INSN(ISCOND) \
1718 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1719
1720 /* Definitions for register eliminations.
1721
1722 This is an array of structures. Each structure initializes one pair
1723 of eliminable registers. The "from" register number is given first,
1724 followed by "to". Eliminations of the same "from" register are listed
1725 in order of preference.
1726
1727 We have two registers that can be eliminated on the ARM. First, the
1728 arg pointer register can often be eliminated in favor of the stack
1729 pointer register. Secondly, the pseudo frame pointer register can always
1730 be eliminated; it is replaced with either the stack or the real frame
1731 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1732 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1733
1734 #define ELIMINABLE_REGS \
1735 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1736 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1737 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1738 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1739 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1740 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1741 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1742
1743 /* Given FROM and TO register numbers, say whether this elimination is
1744 allowed. Frame pointer elimination is automatically handled.
1745
1746 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1747 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1748 pointer, we must eliminate FRAME_POINTER_REGNUM into
1749 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1750 ARG_POINTER_REGNUM. */
1751 #define CAN_ELIMINATE(FROM, TO) \
1752 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1753 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1754 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1755 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1756 1)
1757
1758 /* Define the offset between two registers, one to be eliminated, and the
1759 other its replacement, at the start of a routine. */
1760 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1761 if (TARGET_ARM) \
1762 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1763 else \
1764 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1765
1766 /* Special case handling of the location of arguments passed on the stack. */
1767 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1768
1769 /* Initialize data used by insn expanders. This is called from insn_emit,
1770 once for every function before code is generated. */
1771 #define INIT_EXPANDERS arm_init_expanders ()
1772
1773 /* Output assembler code for a block containing the constant parts
1774 of a trampoline, leaving space for the variable parts.
1775
1776 On the ARM, (if r8 is the static chain regnum, and remembering that
1777 referencing pc adds an offset of 8) the trampoline looks like:
1778 ldr r8, [pc, #0]
1779 ldr pc, [pc]
1780 .word static chain value
1781 .word function's address
1782 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1783 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1784 { \
1785 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1786 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1787 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1788 PC_REGNUM, PC_REGNUM); \
1789 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1790 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1791 }
1792
1793 /* The Thumb-2 trampoline is similar to the arm implementation.
1794 Unlike 16-bit Thumb, we enter the stub in thumb mode. */
1795 #define THUMB2_TRAMPOLINE_TEMPLATE(FILE) \
1796 { \
1797 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1798 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1799 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1800 PC_REGNUM, PC_REGNUM); \
1801 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1802 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1803 }
1804
1805 #define THUMB1_TRAMPOLINE_TEMPLATE(FILE) \
1806 { \
1807 ASM_OUTPUT_ALIGN(FILE, 2); \
1808 fprintf (FILE, "\t.code\t16\n"); \
1809 fprintf (FILE, ".Ltrampoline_start:\n"); \
1810 asm_fprintf (FILE, "\tpush\t{r0, r1}\n"); \
1811 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1812 PC_REGNUM); \
1813 asm_fprintf (FILE, "\tmov\t%r, r0\n", \
1814 STATIC_CHAIN_REGNUM); \
1815 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1816 PC_REGNUM); \
1817 asm_fprintf (FILE, "\tstr\tr0, [%r, #4]\n", \
1818 SP_REGNUM); \
1819 asm_fprintf (FILE, "\tpop\t{r0, %r}\n", \
1820 PC_REGNUM); \
1821 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1822 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1823 }
1824
1825 #define TRAMPOLINE_TEMPLATE(FILE) \
1826 if (TARGET_ARM) \
1827 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1828 else if (TARGET_THUMB2) \
1829 THUMB2_TRAMPOLINE_TEMPLATE (FILE) \
1830 else \
1831 THUMB1_TRAMPOLINE_TEMPLATE (FILE)
1832
1833 /* Thumb trampolines should be entered in thumb mode, so set the bottom bit
1834 of the address. */
1835 #define TRAMPOLINE_ADJUST_ADDRESS(ADDR) do \
1836 { \
1837 if (TARGET_THUMB) \
1838 (ADDR) = expand_simple_binop (Pmode, IOR, (ADDR), GEN_INT(1), \
1839 gen_reg_rtx (Pmode), 0, OPTAB_LIB_WIDEN); \
1840 } while(0)
1841
1842 /* Length in units of the trampoline for entering a nested function. */
1843 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1844
1845 /* Alignment required for a trampoline in bits. */
1846 #define TRAMPOLINE_ALIGNMENT 32
1847
1848
1849 /* Emit RTL insns to initialize the variable parts of a trampoline.
1850 FNADDR is an RTX for the address of the function's pure code.
1851 CXT is an RTX for the static chain value for the function. */
1852 #ifndef INITIALIZE_TRAMPOLINE
1853 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1854 { \
1855 emit_move_insn (gen_rtx_MEM (SImode, \
1856 plus_constant (TRAMP, \
1857 TARGET_32BIT ? 8 : 12)), \
1858 CXT); \
1859 emit_move_insn (gen_rtx_MEM (SImode, \
1860 plus_constant (TRAMP, \
1861 TARGET_32BIT ? 12 : 16)), \
1862 FNADDR); \
1863 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
1864 0, VOIDmode, 2, TRAMP, Pmode, \
1865 plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \
1866 }
1867 #endif
1868
1869 \f
1870 /* Addressing modes, and classification of registers for them. */
1871 #define HAVE_POST_INCREMENT 1
1872 #define HAVE_PRE_INCREMENT TARGET_32BIT
1873 #define HAVE_POST_DECREMENT TARGET_32BIT
1874 #define HAVE_PRE_DECREMENT TARGET_32BIT
1875 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1876 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1877 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1878 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1879
1880 /* Macros to check register numbers against specific register classes. */
1881
1882 /* These assume that REGNO is a hard or pseudo reg number.
1883 They give nonzero only if REGNO is a hard reg of the suitable class
1884 or a pseudo reg currently allocated to a suitable hard reg.
1885 Since they use reg_renumber, they are safe only once reg_renumber
1886 has been allocated, which happens in local-alloc.c. */
1887 #define TEST_REGNO(R, TEST, VALUE) \
1888 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1889
1890 /* Don't allow the pc to be used. */
1891 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1892 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1893 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1894 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1895
1896 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1897 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1898 || (GET_MODE_SIZE (MODE) >= 4 \
1899 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1900
1901 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1902 (TARGET_THUMB1 \
1903 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1904 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1905
1906 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1907 For Thumb, we can not use SP + reg, so reject SP. */
1908 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1909 REGNO_OK_FOR_INDEX_P (X)
1910
1911 /* For ARM code, we don't care about the mode, but for Thumb, the index
1912 must be suitable for use in a QImode load. */
1913 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1914 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1915
1916 /* Maximum number of registers that can appear in a valid memory address.
1917 Shifts in addresses can't be by a register. */
1918 #define MAX_REGS_PER_ADDRESS 2
1919
1920 /* Recognize any constant value that is a valid address. */
1921 /* XXX We can address any constant, eventually... */
1922 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1923 #define CONSTANT_ADDRESS_P(X) \
1924 (GET_CODE (X) == SYMBOL_REF \
1925 && (CONSTANT_POOL_ADDRESS_P (X) \
1926 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1927
1928 /* True if SYMBOL + OFFSET constants must refer to something within
1929 SYMBOL's section. */
1930 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1931
1932 /* Nonzero if the constant value X is a legitimate general operand.
1933 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1934
1935 On the ARM, allow any integer (invalid ones are removed later by insn
1936 patterns), nice doubles and symbol_refs which refer to the function's
1937 constant pool XXX.
1938
1939 When generating pic allow anything. */
1940 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1941
1942 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1943 ( GET_CODE (X) == CONST_INT \
1944 || GET_CODE (X) == CONST_DOUBLE \
1945 || CONSTANT_ADDRESS_P (X) \
1946 || flag_pic)
1947
1948 #define LEGITIMATE_CONSTANT_P(X) \
1949 (!arm_cannot_force_const_mem (X) \
1950 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
1951 : THUMB_LEGITIMATE_CONSTANT_P (X)))
1952
1953 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1954 #define SUBTARGET_NAME_ENCODING_LENGTHS
1955 #endif
1956
1957 /* This is a C fragment for the inside of a switch statement.
1958 Each case label should return the number of characters to
1959 be stripped from the start of a function's name, if that
1960 name starts with the indicated character. */
1961 #define ARM_NAME_ENCODING_LENGTHS \
1962 case '*': return 1; \
1963 SUBTARGET_NAME_ENCODING_LENGTHS
1964
1965 /* This is how to output a reference to a user-level label named NAME.
1966 `assemble_name' uses this. */
1967 #undef ASM_OUTPUT_LABELREF
1968 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1969 arm_asm_output_labelref (FILE, NAME)
1970
1971 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
1972 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1973 if (TARGET_THUMB2) \
1974 thumb2_asm_output_opcode (STREAM);
1975
1976 /* The EABI specifies that constructors should go in .init_array.
1977 Other targets use .ctors for compatibility. */
1978 #ifndef ARM_EABI_CTORS_SECTION_OP
1979 #define ARM_EABI_CTORS_SECTION_OP \
1980 "\t.section\t.init_array,\"aw\",%init_array"
1981 #endif
1982 #ifndef ARM_EABI_DTORS_SECTION_OP
1983 #define ARM_EABI_DTORS_SECTION_OP \
1984 "\t.section\t.fini_array,\"aw\",%fini_array"
1985 #endif
1986 #define ARM_CTORS_SECTION_OP \
1987 "\t.section\t.ctors,\"aw\",%progbits"
1988 #define ARM_DTORS_SECTION_OP \
1989 "\t.section\t.dtors,\"aw\",%progbits"
1990
1991 /* Define CTORS_SECTION_ASM_OP. */
1992 #undef CTORS_SECTION_ASM_OP
1993 #undef DTORS_SECTION_ASM_OP
1994 #ifndef IN_LIBGCC2
1995 # define CTORS_SECTION_ASM_OP \
1996 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1997 # define DTORS_SECTION_ASM_OP \
1998 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1999 #else /* !defined (IN_LIBGCC2) */
2000 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
2001 so we cannot use the definition above. */
2002 # ifdef __ARM_EABI__
2003 /* The .ctors section is not part of the EABI, so we do not define
2004 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
2005 from trying to use it. We do define it when doing normal
2006 compilation, as .init_array can be used instead of .ctors. */
2007 /* There is no need to emit begin or end markers when using
2008 init_array; the dynamic linker will compute the size of the
2009 array itself based on special symbols created by the static
2010 linker. However, we do need to arrange to set up
2011 exception-handling here. */
2012 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
2013 # define CTOR_LIST_END /* empty */
2014 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
2015 # define DTOR_LIST_END /* empty */
2016 # else /* !defined (__ARM_EABI__) */
2017 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
2018 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
2019 # endif /* !defined (__ARM_EABI__) */
2020 #endif /* !defined (IN_LIBCC2) */
2021
2022 /* True if the operating system can merge entities with vague linkage
2023 (e.g., symbols in COMDAT group) during dynamic linking. */
2024 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
2025 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
2026 #endif
2027
2028 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
2029
2030 #ifdef TARGET_UNWIND_INFO
2031 #define ARM_EABI_UNWIND_TABLES \
2032 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
2033 #else
2034 #define ARM_EABI_UNWIND_TABLES 0
2035 #endif
2036
2037 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2038 and check its validity for a certain class.
2039 We have two alternate definitions for each of them.
2040 The usual definition accepts all pseudo regs; the other rejects
2041 them unless they have been allocated suitable hard regs.
2042 The symbol REG_OK_STRICT causes the latter definition to be used.
2043 Thumb-2 has the same restrictions as arm. */
2044 #ifndef REG_OK_STRICT
2045
2046 #define ARM_REG_OK_FOR_BASE_P(X) \
2047 (REGNO (X) <= LAST_ARM_REGNUM \
2048 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2049 || REGNO (X) == FRAME_POINTER_REGNUM \
2050 || REGNO (X) == ARG_POINTER_REGNUM)
2051
2052 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2053 (REGNO (X) <= LAST_LO_REGNUM \
2054 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2055 || (GET_MODE_SIZE (MODE) >= 4 \
2056 && (REGNO (X) == STACK_POINTER_REGNUM \
2057 || (X) == hard_frame_pointer_rtx \
2058 || (X) == arg_pointer_rtx)))
2059
2060 #define REG_STRICT_P 0
2061
2062 #else /* REG_OK_STRICT */
2063
2064 #define ARM_REG_OK_FOR_BASE_P(X) \
2065 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2066
2067 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2068 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2069
2070 #define REG_STRICT_P 1
2071
2072 #endif /* REG_OK_STRICT */
2073
2074 /* Now define some helpers in terms of the above. */
2075
2076 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2077 (TARGET_THUMB1 \
2078 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2079 : ARM_REG_OK_FOR_BASE_P (X))
2080
2081 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2082
2083 /* For 16-bit Thumb, a valid index register is anything that can be used in
2084 a byte load instruction. */
2085 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
2086 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
2087
2088 /* Nonzero if X is a hard reg that can be used as an index
2089 or if it is a pseudo reg. On the Thumb, the stack pointer
2090 is not suitable. */
2091 #define REG_OK_FOR_INDEX_P(X) \
2092 (TARGET_THUMB1 \
2093 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
2094 : ARM_REG_OK_FOR_INDEX_P (X))
2095
2096 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2097 For Thumb, we can not use SP + reg, so reject SP. */
2098 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2099 REG_OK_FOR_INDEX_P (X)
2100 \f
2101 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2102 that is a valid memory address for an instruction.
2103 The MODE argument is the machine mode for the MEM expression
2104 that wants to use this address. */
2105
2106 #define ARM_BASE_REGISTER_RTX_P(X) \
2107 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2108
2109 #define ARM_INDEX_REGISTER_RTX_P(X) \
2110 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2111
2112 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2113 { \
2114 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2115 goto WIN; \
2116 }
2117
2118 #define THUMB2_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2119 { \
2120 if (thumb2_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2121 goto WIN; \
2122 }
2123
2124 #define THUMB1_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2125 { \
2126 if (thumb1_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2127 goto WIN; \
2128 }
2129
2130 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2131 if (TARGET_ARM) \
2132 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2133 else if (TARGET_THUMB2) \
2134 THUMB2_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2135 else /* if (TARGET_THUMB1) */ \
2136 THUMB1_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2137
2138 \f
2139 /* Try machine-dependent ways of modifying an illegitimate address
2140 to be legitimate. If we find one, return the new, valid address. */
2141 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2142 do { \
2143 X = arm_legitimize_address (X, OLDX, MODE); \
2144 } while (0)
2145
2146 /* ??? Implement LEGITIMIZE_ADDRESS for thumb2. */
2147 #define THUMB2_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2148 do { \
2149 } while (0)
2150
2151 #define THUMB1_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2152 do { \
2153 X = thumb_legitimize_address (X, OLDX, MODE); \
2154 } while (0)
2155
2156 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2157 do { \
2158 if (TARGET_ARM) \
2159 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2160 else if (TARGET_THUMB2) \
2161 THUMB2_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2162 else \
2163 THUMB1_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2164 \
2165 if (memory_address_p (MODE, X)) \
2166 goto WIN; \
2167 } while (0)
2168
2169 /* Go to LABEL if ADDR (a legitimate address expression)
2170 has an effect that depends on the machine mode it is used for. */
2171 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2172 { \
2173 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2174 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2175 goto LABEL; \
2176 }
2177
2178 /* Nothing helpful to do for the Thumb */
2179 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2180 if (TARGET_32BIT) \
2181 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2182 \f
2183
2184 /* Specify the machine mode that this machine uses
2185 for the index in the tablejump instruction. */
2186 #define CASE_VECTOR_MODE Pmode
2187
2188 #define CASE_VECTOR_PC_RELATIVE TARGET_THUMB2
2189
2190 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2191 ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
2192 : (max >= 0x200) ? HImode \
2193 : QImode)
2194
2195 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2196 unsigned is probably best, but may break some code. */
2197 #ifndef DEFAULT_SIGNED_CHAR
2198 #define DEFAULT_SIGNED_CHAR 0
2199 #endif
2200
2201 /* Max number of bytes we can move from memory to memory
2202 in one reasonably fast instruction. */
2203 #define MOVE_MAX 4
2204
2205 #undef MOVE_RATIO
2206 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2207
2208 /* Define if operations between registers always perform the operation
2209 on the full register even if a narrower mode is specified. */
2210 #define WORD_REGISTER_OPERATIONS
2211
2212 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2213 will either zero-extend or sign-extend. The value of this macro should
2214 be the code that says which one of the two operations is implicitly
2215 done, UNKNOWN if none. */
2216 #define LOAD_EXTEND_OP(MODE) \
2217 (TARGET_THUMB ? ZERO_EXTEND : \
2218 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2219 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2220
2221 /* Nonzero if access to memory by bytes is slow and undesirable. */
2222 #define SLOW_BYTE_ACCESS 0
2223
2224 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2225
2226 /* Immediate shift counts are truncated by the output routines (or was it
2227 the assembler?). Shift counts in a register are truncated by ARM. Note
2228 that the native compiler puts too large (> 32) immediate shift counts
2229 into a register and shifts by the register, letting the ARM decide what
2230 to do instead of doing that itself. */
2231 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2232 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2233 On the arm, Y in a register is used modulo 256 for the shift. Only for
2234 rotates is modulo 32 used. */
2235 /* #define SHIFT_COUNT_TRUNCATED 1 */
2236
2237 /* All integers have the same format so truncation is easy. */
2238 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2239
2240 /* Calling from registers is a massive pain. */
2241 #define NO_FUNCTION_CSE 1
2242
2243 /* The machine modes of pointers and functions */
2244 #define Pmode SImode
2245 #define FUNCTION_MODE Pmode
2246
2247 #define ARM_FRAME_RTX(X) \
2248 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2249 || (X) == arg_pointer_rtx)
2250
2251 /* Moves to and from memory are quite expensive */
2252 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2253 (TARGET_32BIT ? 10 : \
2254 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2255 * (CLASS == LO_REGS ? 1 : 2)))
2256
2257 /* Try to generate sequences that don't involve branches, we can then use
2258 conditional instructions */
2259 #define BRANCH_COST \
2260 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
2261 \f
2262 /* Position Independent Code. */
2263 /* We decide which register to use based on the compilation options and
2264 the assembler in use; this is more general than the APCS restriction of
2265 using sb (r9) all the time. */
2266 extern unsigned arm_pic_register;
2267
2268 /* The register number of the register used to address a table of static
2269 data addresses in memory. */
2270 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2271
2272 /* We can't directly access anything that contains a symbol,
2273 nor can we indirect via the constant pool. One exception is
2274 UNSPEC_TLS, which is always PIC. */
2275 #define LEGITIMATE_PIC_OPERAND_P(X) \
2276 (!(symbol_mentioned_p (X) \
2277 || label_mentioned_p (X) \
2278 || (GET_CODE (X) == SYMBOL_REF \
2279 && CONSTANT_POOL_ADDRESS_P (X) \
2280 && (symbol_mentioned_p (get_pool_constant (X)) \
2281 || label_mentioned_p (get_pool_constant (X))))) \
2282 || tls_mentioned_p (X))
2283
2284 /* We need to know when we are making a constant pool; this determines
2285 whether data needs to be in the GOT or can be referenced via a GOT
2286 offset. */
2287 extern int making_const_table;
2288 \f
2289 /* Handle pragmas for compatibility with Intel's compilers. */
2290 #define REGISTER_TARGET_PRAGMAS() do { \
2291 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2292 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2293 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2294 } while (0)
2295
2296 /* Condition code information. */
2297 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2298 return the mode to be used for the comparison. */
2299
2300 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2301
2302 #define REVERSIBLE_CC_MODE(MODE) 1
2303
2304 #define REVERSE_CONDITION(CODE,MODE) \
2305 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2306 ? reverse_condition_maybe_unordered (code) \
2307 : reverse_condition (code))
2308
2309 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2310 do \
2311 { \
2312 if (GET_CODE (OP1) == CONST_INT \
2313 && ! (const_ok_for_arm (INTVAL (OP1)) \
2314 || (const_ok_for_arm (- INTVAL (OP1))))) \
2315 { \
2316 rtx const_op = OP1; \
2317 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \
2318 &const_op); \
2319 OP1 = const_op; \
2320 } \
2321 } \
2322 while (0)
2323
2324 /* The arm5 clz instruction returns 32. */
2325 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2326 \f
2327 #undef ASM_APP_OFF
2328 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2329 TARGET_THUMB2 ? "\t.thumb\n" : "")
2330
2331 /* Output a push or a pop instruction (only used when profiling). */
2332 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2333 do \
2334 { \
2335 if (TARGET_ARM) \
2336 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2337 STACK_POINTER_REGNUM, REGNO); \
2338 else \
2339 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2340 } while (0)
2341
2342
2343 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2344 do \
2345 { \
2346 if (TARGET_ARM) \
2347 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2348 STACK_POINTER_REGNUM, REGNO); \
2349 else \
2350 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2351 } while (0)
2352
2353 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2354 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
2355
2356 /* This is how to output a label which precedes a jumptable. Since
2357 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2358 #undef ASM_OUTPUT_CASE_LABEL
2359 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2360 do \
2361 { \
2362 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2363 ASM_OUTPUT_ALIGN (FILE, 2); \
2364 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2365 } \
2366 while (0)
2367
2368 /* Make sure subsequent insns are aligned after a TBB. */
2369 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2370 do \
2371 { \
2372 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2373 ASM_OUTPUT_ALIGN (FILE, 1); \
2374 } \
2375 while (0)
2376
2377 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2378 do \
2379 { \
2380 if (TARGET_THUMB) \
2381 { \
2382 if (is_called_in_ARM_mode (DECL) \
2383 || (TARGET_THUMB1 && current_function_is_thunk)) \
2384 fprintf (STREAM, "\t.code 32\n") ; \
2385 else if (TARGET_THUMB1) \
2386 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
2387 else \
2388 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
2389 } \
2390 if (TARGET_POKE_FUNCTION_NAME) \
2391 arm_poke_function_name (STREAM, (const char *) NAME); \
2392 } \
2393 while (0)
2394
2395 /* For aliases of functions we use .thumb_set instead. */
2396 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2397 do \
2398 { \
2399 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2400 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2401 \
2402 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2403 { \
2404 fprintf (FILE, "\t.thumb_set "); \
2405 assemble_name (FILE, LABEL1); \
2406 fprintf (FILE, ","); \
2407 assemble_name (FILE, LABEL2); \
2408 fprintf (FILE, "\n"); \
2409 } \
2410 else \
2411 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2412 } \
2413 while (0)
2414
2415 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2416 /* To support -falign-* switches we need to use .p2align so
2417 that alignment directives in code sections will be padded
2418 with no-op instructions, rather than zeroes. */
2419 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2420 if ((LOG) != 0) \
2421 { \
2422 if ((MAX_SKIP) == 0) \
2423 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2424 else \
2425 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2426 (int) (LOG), (int) (MAX_SKIP)); \
2427 }
2428 #endif
2429 \f
2430 /* Add two bytes to the length of conditionally executed Thumb-2
2431 instructions for the IT instruction. */
2432 #define ADJUST_INSN_LENGTH(insn, length) \
2433 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2434 length += 2;
2435
2436 /* Only perform branch elimination (by making instructions conditional) if
2437 we're optimizing. For Thumb-2 check if any IT instructions need
2438 outputting. */
2439 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2440 if (TARGET_ARM && optimize) \
2441 arm_final_prescan_insn (INSN); \
2442 else if (TARGET_THUMB2) \
2443 thumb2_final_prescan_insn (INSN); \
2444 else if (TARGET_THUMB1) \
2445 thumb1_final_prescan_insn (INSN)
2446
2447 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2448 (CODE == '@' || CODE == '|' || CODE == '.' \
2449 || CODE == '(' || CODE == ')' || CODE == '#' \
2450 || (TARGET_32BIT && (CODE == '?')) \
2451 || (TARGET_THUMB2 && (CODE == '!')) \
2452 || (TARGET_THUMB && (CODE == '_')))
2453
2454 /* Output an operand of an instruction. */
2455 #define PRINT_OPERAND(STREAM, X, CODE) \
2456 arm_print_operand (STREAM, X, CODE)
2457
2458 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2459 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2460 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2461 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2462 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2463 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2464 : 0))))
2465
2466 /* Output the address of an operand. */
2467 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2468 { \
2469 int is_minus = GET_CODE (X) == MINUS; \
2470 \
2471 if (GET_CODE (X) == REG) \
2472 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2473 else if (GET_CODE (X) == PLUS || is_minus) \
2474 { \
2475 rtx base = XEXP (X, 0); \
2476 rtx index = XEXP (X, 1); \
2477 HOST_WIDE_INT offset = 0; \
2478 if (GET_CODE (base) != REG) \
2479 { \
2480 /* Ensure that BASE is a register. */ \
2481 /* (one of them must be). */ \
2482 rtx temp = base; \
2483 base = index; \
2484 index = temp; \
2485 } \
2486 switch (GET_CODE (index)) \
2487 { \
2488 case CONST_INT: \
2489 offset = INTVAL (index); \
2490 if (is_minus) \
2491 offset = -offset; \
2492 asm_fprintf (STREAM, "[%r, #%wd]", \
2493 REGNO (base), offset); \
2494 break; \
2495 \
2496 case REG: \
2497 asm_fprintf (STREAM, "[%r, %s%r]", \
2498 REGNO (base), is_minus ? "-" : "", \
2499 REGNO (index)); \
2500 break; \
2501 \
2502 case MULT: \
2503 case ASHIFTRT: \
2504 case LSHIFTRT: \
2505 case ASHIFT: \
2506 case ROTATERT: \
2507 { \
2508 asm_fprintf (STREAM, "[%r, %s%r", \
2509 REGNO (base), is_minus ? "-" : "", \
2510 REGNO (XEXP (index, 0))); \
2511 arm_print_operand (STREAM, index, 'S'); \
2512 fputs ("]", STREAM); \
2513 break; \
2514 } \
2515 \
2516 default: \
2517 gcc_unreachable (); \
2518 } \
2519 } \
2520 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2521 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2522 { \
2523 extern enum machine_mode output_memory_reference_mode; \
2524 \
2525 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2526 \
2527 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2528 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2529 REGNO (XEXP (X, 0)), \
2530 GET_CODE (X) == PRE_DEC ? "-" : "", \
2531 GET_MODE_SIZE (output_memory_reference_mode)); \
2532 else \
2533 asm_fprintf (STREAM, "[%r], #%s%d", \
2534 REGNO (XEXP (X, 0)), \
2535 GET_CODE (X) == POST_DEC ? "-" : "", \
2536 GET_MODE_SIZE (output_memory_reference_mode)); \
2537 } \
2538 else if (GET_CODE (X) == PRE_MODIFY) \
2539 { \
2540 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2541 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2542 asm_fprintf (STREAM, "#%wd]!", \
2543 INTVAL (XEXP (XEXP (X, 1), 1))); \
2544 else \
2545 asm_fprintf (STREAM, "%r]!", \
2546 REGNO (XEXP (XEXP (X, 1), 1))); \
2547 } \
2548 else if (GET_CODE (X) == POST_MODIFY) \
2549 { \
2550 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2551 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2552 asm_fprintf (STREAM, "#%wd", \
2553 INTVAL (XEXP (XEXP (X, 1), 1))); \
2554 else \
2555 asm_fprintf (STREAM, "%r", \
2556 REGNO (XEXP (XEXP (X, 1), 1))); \
2557 } \
2558 else output_addr_const (STREAM, X); \
2559 }
2560
2561 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2562 { \
2563 if (GET_CODE (X) == REG) \
2564 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2565 else if (GET_CODE (X) == POST_INC) \
2566 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2567 else if (GET_CODE (X) == PLUS) \
2568 { \
2569 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2570 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2571 asm_fprintf (STREAM, "[%r, #%wd]", \
2572 REGNO (XEXP (X, 0)), \
2573 INTVAL (XEXP (X, 1))); \
2574 else \
2575 asm_fprintf (STREAM, "[%r, %r]", \
2576 REGNO (XEXP (X, 0)), \
2577 REGNO (XEXP (X, 1))); \
2578 } \
2579 else \
2580 output_addr_const (STREAM, X); \
2581 }
2582
2583 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2584 if (TARGET_32BIT) \
2585 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2586 else \
2587 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2588
2589 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
2590 if (arm_output_addr_const_extra (file, x) == FALSE) \
2591 goto fail
2592
2593 /* A C expression whose value is RTL representing the value of the return
2594 address for the frame COUNT steps up from the current frame. */
2595
2596 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2597 arm_return_addr (COUNT, FRAME)
2598
2599 /* Mask of the bits in the PC that contain the real return address
2600 when running in 26-bit mode. */
2601 #define RETURN_ADDR_MASK26 (0x03fffffc)
2602
2603 /* Pick up the return address upon entry to a procedure. Used for
2604 dwarf2 unwind information. This also enables the table driven
2605 mechanism. */
2606 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2607 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2608
2609 /* Used to mask out junk bits from the return address, such as
2610 processor state, interrupt status, condition codes and the like. */
2611 #define MASK_RETURN_ADDR \
2612 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2613 in 26 bit mode, the condition codes must be masked out of the \
2614 return address. This does not apply to ARM6 and later processors \
2615 when running in 32 bit mode. */ \
2616 ((arm_arch4 || TARGET_THUMB) \
2617 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2618 : arm_gen_return_addr_mask ())
2619
2620 \f
2621 /* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
2622 symbolic names defined here (which would require too much duplication).
2623 FIXME? */
2624 enum arm_builtins
2625 {
2626 ARM_BUILTIN_GETWCX,
2627 ARM_BUILTIN_SETWCX,
2628
2629 ARM_BUILTIN_WZERO,
2630
2631 ARM_BUILTIN_WAVG2BR,
2632 ARM_BUILTIN_WAVG2HR,
2633 ARM_BUILTIN_WAVG2B,
2634 ARM_BUILTIN_WAVG2H,
2635
2636 ARM_BUILTIN_WACCB,
2637 ARM_BUILTIN_WACCH,
2638 ARM_BUILTIN_WACCW,
2639
2640 ARM_BUILTIN_WMACS,
2641 ARM_BUILTIN_WMACSZ,
2642 ARM_BUILTIN_WMACU,
2643 ARM_BUILTIN_WMACUZ,
2644
2645 ARM_BUILTIN_WSADB,
2646 ARM_BUILTIN_WSADBZ,
2647 ARM_BUILTIN_WSADH,
2648 ARM_BUILTIN_WSADHZ,
2649
2650 ARM_BUILTIN_WALIGN,
2651
2652 ARM_BUILTIN_TMIA,
2653 ARM_BUILTIN_TMIAPH,
2654 ARM_BUILTIN_TMIABB,
2655 ARM_BUILTIN_TMIABT,
2656 ARM_BUILTIN_TMIATB,
2657 ARM_BUILTIN_TMIATT,
2658
2659 ARM_BUILTIN_TMOVMSKB,
2660 ARM_BUILTIN_TMOVMSKH,
2661 ARM_BUILTIN_TMOVMSKW,
2662
2663 ARM_BUILTIN_TBCSTB,
2664 ARM_BUILTIN_TBCSTH,
2665 ARM_BUILTIN_TBCSTW,
2666
2667 ARM_BUILTIN_WMADDS,
2668 ARM_BUILTIN_WMADDU,
2669
2670 ARM_BUILTIN_WPACKHSS,
2671 ARM_BUILTIN_WPACKWSS,
2672 ARM_BUILTIN_WPACKDSS,
2673 ARM_BUILTIN_WPACKHUS,
2674 ARM_BUILTIN_WPACKWUS,
2675 ARM_BUILTIN_WPACKDUS,
2676
2677 ARM_BUILTIN_WADDB,
2678 ARM_BUILTIN_WADDH,
2679 ARM_BUILTIN_WADDW,
2680 ARM_BUILTIN_WADDSSB,
2681 ARM_BUILTIN_WADDSSH,
2682 ARM_BUILTIN_WADDSSW,
2683 ARM_BUILTIN_WADDUSB,
2684 ARM_BUILTIN_WADDUSH,
2685 ARM_BUILTIN_WADDUSW,
2686 ARM_BUILTIN_WSUBB,
2687 ARM_BUILTIN_WSUBH,
2688 ARM_BUILTIN_WSUBW,
2689 ARM_BUILTIN_WSUBSSB,
2690 ARM_BUILTIN_WSUBSSH,
2691 ARM_BUILTIN_WSUBSSW,
2692 ARM_BUILTIN_WSUBUSB,
2693 ARM_BUILTIN_WSUBUSH,
2694 ARM_BUILTIN_WSUBUSW,
2695
2696 ARM_BUILTIN_WAND,
2697 ARM_BUILTIN_WANDN,
2698 ARM_BUILTIN_WOR,
2699 ARM_BUILTIN_WXOR,
2700
2701 ARM_BUILTIN_WCMPEQB,
2702 ARM_BUILTIN_WCMPEQH,
2703 ARM_BUILTIN_WCMPEQW,
2704 ARM_BUILTIN_WCMPGTUB,
2705 ARM_BUILTIN_WCMPGTUH,
2706 ARM_BUILTIN_WCMPGTUW,
2707 ARM_BUILTIN_WCMPGTSB,
2708 ARM_BUILTIN_WCMPGTSH,
2709 ARM_BUILTIN_WCMPGTSW,
2710
2711 ARM_BUILTIN_TEXTRMSB,
2712 ARM_BUILTIN_TEXTRMSH,
2713 ARM_BUILTIN_TEXTRMSW,
2714 ARM_BUILTIN_TEXTRMUB,
2715 ARM_BUILTIN_TEXTRMUH,
2716 ARM_BUILTIN_TEXTRMUW,
2717 ARM_BUILTIN_TINSRB,
2718 ARM_BUILTIN_TINSRH,
2719 ARM_BUILTIN_TINSRW,
2720
2721 ARM_BUILTIN_WMAXSW,
2722 ARM_BUILTIN_WMAXSH,
2723 ARM_BUILTIN_WMAXSB,
2724 ARM_BUILTIN_WMAXUW,
2725 ARM_BUILTIN_WMAXUH,
2726 ARM_BUILTIN_WMAXUB,
2727 ARM_BUILTIN_WMINSW,
2728 ARM_BUILTIN_WMINSH,
2729 ARM_BUILTIN_WMINSB,
2730 ARM_BUILTIN_WMINUW,
2731 ARM_BUILTIN_WMINUH,
2732 ARM_BUILTIN_WMINUB,
2733
2734 ARM_BUILTIN_WMULUM,
2735 ARM_BUILTIN_WMULSM,
2736 ARM_BUILTIN_WMULUL,
2737
2738 ARM_BUILTIN_PSADBH,
2739 ARM_BUILTIN_WSHUFH,
2740
2741 ARM_BUILTIN_WSLLH,
2742 ARM_BUILTIN_WSLLW,
2743 ARM_BUILTIN_WSLLD,
2744 ARM_BUILTIN_WSRAH,
2745 ARM_BUILTIN_WSRAW,
2746 ARM_BUILTIN_WSRAD,
2747 ARM_BUILTIN_WSRLH,
2748 ARM_BUILTIN_WSRLW,
2749 ARM_BUILTIN_WSRLD,
2750 ARM_BUILTIN_WRORH,
2751 ARM_BUILTIN_WRORW,
2752 ARM_BUILTIN_WRORD,
2753 ARM_BUILTIN_WSLLHI,
2754 ARM_BUILTIN_WSLLWI,
2755 ARM_BUILTIN_WSLLDI,
2756 ARM_BUILTIN_WSRAHI,
2757 ARM_BUILTIN_WSRAWI,
2758 ARM_BUILTIN_WSRADI,
2759 ARM_BUILTIN_WSRLHI,
2760 ARM_BUILTIN_WSRLWI,
2761 ARM_BUILTIN_WSRLDI,
2762 ARM_BUILTIN_WRORHI,
2763 ARM_BUILTIN_WRORWI,
2764 ARM_BUILTIN_WRORDI,
2765
2766 ARM_BUILTIN_WUNPCKIHB,
2767 ARM_BUILTIN_WUNPCKIHH,
2768 ARM_BUILTIN_WUNPCKIHW,
2769 ARM_BUILTIN_WUNPCKILB,
2770 ARM_BUILTIN_WUNPCKILH,
2771 ARM_BUILTIN_WUNPCKILW,
2772
2773 ARM_BUILTIN_WUNPCKEHSB,
2774 ARM_BUILTIN_WUNPCKEHSH,
2775 ARM_BUILTIN_WUNPCKEHSW,
2776 ARM_BUILTIN_WUNPCKEHUB,
2777 ARM_BUILTIN_WUNPCKEHUH,
2778 ARM_BUILTIN_WUNPCKEHUW,
2779 ARM_BUILTIN_WUNPCKELSB,
2780 ARM_BUILTIN_WUNPCKELSH,
2781 ARM_BUILTIN_WUNPCKELSW,
2782 ARM_BUILTIN_WUNPCKELUB,
2783 ARM_BUILTIN_WUNPCKELUH,
2784 ARM_BUILTIN_WUNPCKELUW,
2785
2786 ARM_BUILTIN_THREAD_POINTER,
2787
2788 ARM_BUILTIN_NEON_BASE,
2789
2790 ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */
2791 };
2792
2793 /* Do not emit .note.GNU-stack by default. */
2794 #ifndef NEED_INDICATE_EXEC_STACK
2795 #define NEED_INDICATE_EXEC_STACK 0
2796 #endif
2797
2798 #endif /* ! GCC_ARM_H */
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