1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
6 ;; Changes by Michael Meissner, meissner@osf.org
7 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 ;; Brendan Eich, brendan@microunity.com.
10 ;; This file is part of GCC.
12 ;; GCC is free software; you can redistribute it and/or modify
13 ;; it under the terms of the GNU General Public License as published by
14 ;; the Free Software Foundation; either version 3, or (at your option)
17 ;; GCC is distributed in the hope that it will be useful,
18 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
19 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 ;; GNU General Public License for more details.
22 ;; You should have received a copy of the GNU General Public License
23 ;; along with GCC; see the file COPYING3. If not see
24 ;; <http://www.gnu.org/licenses/>.
35 (UNSPEC_CONSTTABLE_INT 8)
36 (UNSPEC_CONSTTABLE_FLOAT 9)
40 (UNSPEC_LOAD_RIGHT 19)
41 (UNSPEC_STORE_LEFT 20)
42 (UNSPEC_STORE_RIGHT 21)
51 (UNSPEC_TLS_GET_TP 30)
54 (UNSPEC_CLEAR_HAZARD 33)
58 (UNSPEC_COMPARE_AND_SWAP 37)
59 (UNSPEC_COMPARE_AND_SWAP_12 38)
60 (UNSPEC_SYNC_OLD_OP 39)
61 (UNSPEC_SYNC_NEW_OP 40)
62 (UNSPEC_SYNC_NEW_OP_12 41)
63 (UNSPEC_SYNC_OLD_OP_12 42)
64 (UNSPEC_SYNC_EXCHANGE 43)
65 (UNSPEC_SYNC_EXCHANGE_12 44)
66 (UNSPEC_MEMORY_BARRIER 45)
67 (UNSPEC_SET_GOT_VERSION 46)
68 (UNSPEC_UPDATE_GOT_VERSION 47)
71 (UNSPEC_ADDRESS_FIRST 100)
74 (GOT_VERSION_REGNUM 79)
76 ;; For MIPS Paired-Singled Floating Point Instructions.
78 (UNSPEC_MOVE_TF_PS 200)
81 ;; MIPS64/MIPS32R2 alnv.ps
84 ;; MIPS-3D instructions
88 (UNSPEC_CVT_PW_PS 205)
89 (UNSPEC_CVT_PS_PW 206)
97 (UNSPEC_SINGLE_CC 213)
100 ;; MIPS DSP ASE Revision 0.98 3/24/2005
108 (UNSPEC_RADDU_W_QB 307)
110 (UNSPEC_PRECRQ_QB_PH 309)
111 (UNSPEC_PRECRQ_PH_W 310)
112 (UNSPEC_PRECRQ_RS_PH_W 311)
113 (UNSPEC_PRECRQU_S_QB_PH 312)
114 (UNSPEC_PRECEQ_W_PHL 313)
115 (UNSPEC_PRECEQ_W_PHR 314)
116 (UNSPEC_PRECEQU_PH_QBL 315)
117 (UNSPEC_PRECEQU_PH_QBR 316)
118 (UNSPEC_PRECEQU_PH_QBLA 317)
119 (UNSPEC_PRECEQU_PH_QBRA 318)
120 (UNSPEC_PRECEU_PH_QBL 319)
121 (UNSPEC_PRECEU_PH_QBR 320)
122 (UNSPEC_PRECEU_PH_QBLA 321)
123 (UNSPEC_PRECEU_PH_QBRA 322)
129 (UNSPEC_MULEU_S_PH_QBL 328)
130 (UNSPEC_MULEU_S_PH_QBR 329)
131 (UNSPEC_MULQ_RS_PH 330)
132 (UNSPEC_MULEQ_S_W_PHL 331)
133 (UNSPEC_MULEQ_S_W_PHR 332)
134 (UNSPEC_DPAU_H_QBL 333)
135 (UNSPEC_DPAU_H_QBR 334)
136 (UNSPEC_DPSU_H_QBL 335)
137 (UNSPEC_DPSU_H_QBR 336)
138 (UNSPEC_DPAQ_S_W_PH 337)
139 (UNSPEC_DPSQ_S_W_PH 338)
140 (UNSPEC_MULSAQ_S_W_PH 339)
141 (UNSPEC_DPAQ_SA_L_W 340)
142 (UNSPEC_DPSQ_SA_L_W 341)
143 (UNSPEC_MAQ_S_W_PHL 342)
144 (UNSPEC_MAQ_S_W_PHR 343)
145 (UNSPEC_MAQ_SA_W_PHL 344)
146 (UNSPEC_MAQ_SA_W_PHR 345)
154 (UNSPEC_CMPGU_EQ_QB 353)
155 (UNSPEC_CMPGU_LT_QB 354)
156 (UNSPEC_CMPGU_LE_QB 355)
158 (UNSPEC_PACKRL_PH 357)
160 (UNSPEC_EXTR_R_W 359)
161 (UNSPEC_EXTR_RS_W 360)
162 (UNSPEC_EXTR_S_H 361)
170 ;; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
171 (UNSPEC_ABSQ_S_QB 400)
173 (UNSPEC_ADDU_S_PH 402)
174 (UNSPEC_ADDUH_QB 403)
175 (UNSPEC_ADDUH_R_QB 404)
178 (UNSPEC_CMPGDU_EQ_QB 407)
179 (UNSPEC_CMPGDU_LT_QB 408)
180 (UNSPEC_CMPGDU_LE_QB 409)
181 (UNSPEC_DPA_W_PH 410)
182 (UNSPEC_DPS_W_PH 411)
188 (UNSPEC_MUL_S_PH 417)
189 (UNSPEC_MULQ_RS_W 418)
190 (UNSPEC_MULQ_S_PH 419)
191 (UNSPEC_MULQ_S_W 420)
192 (UNSPEC_MULSA_W_PH 421)
195 (UNSPEC_PRECR_QB_PH 424)
196 (UNSPEC_PRECR_SRA_PH_W 425)
197 (UNSPEC_PRECR_SRA_R_PH_W 426)
200 (UNSPEC_SHRA_R_QB 429)
203 (UNSPEC_SUBU_S_PH 432)
204 (UNSPEC_SUBUH_QB 433)
205 (UNSPEC_SUBUH_R_QB 434)
206 (UNSPEC_ADDQH_PH 435)
207 (UNSPEC_ADDQH_R_PH 436)
209 (UNSPEC_ADDQH_R_W 438)
210 (UNSPEC_SUBQH_PH 439)
211 (UNSPEC_SUBQH_R_PH 440)
213 (UNSPEC_SUBQH_R_W 442)
214 (UNSPEC_DPAX_W_PH 443)
215 (UNSPEC_DPSX_W_PH 444)
216 (UNSPEC_DPAQX_S_W_PH 445)
217 (UNSPEC_DPAQX_SA_W_PH 446)
218 (UNSPEC_DPSQX_S_W_PH 447)
219 (UNSPEC_DPSQX_SA_W_PH 448)
221 ;; ST Microelectronics Loongson-2E/2F.
222 (UNSPEC_LOONGSON_PAVG 500)
223 (UNSPEC_LOONGSON_PCMPEQ 501)
224 (UNSPEC_LOONGSON_PCMPGT 502)
225 (UNSPEC_LOONGSON_PEXTR 503)
226 (UNSPEC_LOONGSON_PINSR_0 504)
227 (UNSPEC_LOONGSON_PINSR_1 505)
228 (UNSPEC_LOONGSON_PINSR_2 506)
229 (UNSPEC_LOONGSON_PINSR_3 507)
230 (UNSPEC_LOONGSON_PMADD 508)
231 (UNSPEC_LOONGSON_PMOVMSK 509)
232 (UNSPEC_LOONGSON_PMULHU 510)
233 (UNSPEC_LOONGSON_PMULH 511)
234 (UNSPEC_LOONGSON_PMULL 512)
235 (UNSPEC_LOONGSON_PMULU 513)
236 (UNSPEC_LOONGSON_PASUBUB 514)
237 (UNSPEC_LOONGSON_BIADD 515)
238 (UNSPEC_LOONGSON_PSADBH 516)
239 (UNSPEC_LOONGSON_PSHUFH 517)
240 (UNSPEC_LOONGSON_PUNPCKH 518)
241 (UNSPEC_LOONGSON_PUNPCKL 519)
242 (UNSPEC_LOONGSON_PADDD 520)
243 (UNSPEC_LOONGSON_PSUBD 521)
245 ;; Used in loongson2ef.md
246 (UNSPEC_LOONGSON_ALU1_TURN_ENABLED_INSN 530)
247 (UNSPEC_LOONGSON_ALU2_TURN_ENABLED_INSN 531)
248 (UNSPEC_LOONGSON_FALU1_TURN_ENABLED_INSN 532)
249 (UNSPEC_LOONGSON_FALU2_TURN_ENABLED_INSN 533)
253 (include "predicates.md")
254 (include "constraints.md")
256 ;; ....................
260 ;; ....................
262 (define_attr "got" "unset,xgot_high,load"
263 (const_string "unset"))
265 ;; For jal instructions, this attribute is DIRECT when the target address
266 ;; is symbolic and INDIRECT when it is a register.
267 (define_attr "jal" "unset,direct,indirect"
268 (const_string "unset"))
270 ;; This attribute is YES if the instruction is a jal macro (not a
271 ;; real jal instruction).
273 ;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
274 ;; an instruction to restore $gp. Direct jals are also macros for
275 ;; flag_pic && !TARGET_ABSOLUTE_ABICALLS because they first load
276 ;; the target address into a register.
277 (define_attr "jal_macro" "no,yes"
278 (cond [(eq_attr "jal" "direct")
279 (symbol_ref "TARGET_CALL_CLOBBERED_GP
280 || (flag_pic && !TARGET_ABSOLUTE_ABICALLS)")
281 (eq_attr "jal" "indirect")
282 (symbol_ref "TARGET_CALL_CLOBBERED_GP")]
283 (const_string "no")))
285 ;; Classification of moves, extensions and truncations. Most values
286 ;; are as for "type" (see below) but there are also the following
287 ;; move-specific values:
289 ;; constN move an N-constraint integer into a MIPS16 register
290 ;; sll0 "sll DEST,SRC,0", which on 64-bit targets is guaranteed
291 ;; to produce a sign-extended DEST, even if SRC is not
292 ;; properly sign-extended
293 ;; andi a single ANDI instruction
294 ;; loadpool move a constant into a MIPS16 register by loading it
296 ;; shift_shift a shift left followed by a shift right
297 ;; lui_movf an LUI followed by a MOVF (for d<-z CC moves)
299 ;; This attribute is used to determine the instruction's length and
300 ;; scheduling type. For doubleword moves, the attribute always describes
301 ;; the split instructions; in some cases, it is more appropriate for the
302 ;; scheduling type to be "multi" instead.
303 (define_attr "move_type"
304 "unknown,load,fpload,store,fpstore,mtc,mfc,mthilo,mfhilo,move,fmove,
305 const,constN,signext,sll0,andi,loadpool,shift_shift,lui_movf"
306 (const_string "unknown"))
308 ;; Main data type used by the insn
309 (define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW"
310 (const_string "unknown"))
312 ;; True if the main data type is twice the size of a word.
313 (define_attr "dword_mode" "no,yes"
314 (cond [(and (eq_attr "mode" "DI,DF")
315 (eq (symbol_ref "TARGET_64BIT") (const_int 0)))
318 (and (eq_attr "mode" "TI,TF")
319 (ne (symbol_ref "TARGET_64BIT") (const_int 0)))
320 (const_string "yes")]
321 (const_string "no")))
323 ;; Classification of each insn.
324 ;; branch conditional branch
325 ;; jump unconditional jump
326 ;; call unconditional call
327 ;; load load instruction(s)
328 ;; fpload floating point load
329 ;; fpidxload floating point indexed load
330 ;; store store instruction(s)
331 ;; fpstore floating point store
332 ;; fpidxstore floating point indexed store
333 ;; prefetch memory prefetch (register + offset)
334 ;; prefetchx memory indexed prefetch (register + register)
335 ;; condmove conditional moves
336 ;; mtc transfer to coprocessor
337 ;; mfc transfer from coprocessor
338 ;; mthilo transfer to hi/lo registers
339 ;; mfhilo transfer from hi/lo registers
340 ;; const load constant
341 ;; arith integer arithmetic instructions
342 ;; logical integer logical instructions
343 ;; shift integer shift instructions
344 ;; slt set less than instructions
345 ;; signext sign extend instructions
346 ;; clz the clz and clo instructions
347 ;; pop the pop instruction
348 ;; trap trap if instructions
349 ;; imul integer multiply 2 operands
350 ;; imul3 integer multiply 3 operands
351 ;; imadd integer multiply-add
352 ;; idiv integer divide
353 ;; move integer register move ({,D}ADD{,U} with rt = 0)
354 ;; fmove floating point register move
355 ;; fadd floating point add/subtract
356 ;; fmul floating point multiply
357 ;; fmadd floating point multiply-add
358 ;; fdiv floating point divide
359 ;; frdiv floating point reciprocal divide
360 ;; frdiv1 floating point reciprocal divide step 1
361 ;; frdiv2 floating point reciprocal divide step 2
362 ;; fabs floating point absolute value
363 ;; fneg floating point negation
364 ;; fcmp floating point compare
365 ;; fcvt floating point convert
366 ;; fsqrt floating point square root
367 ;; frsqrt floating point reciprocal square root
368 ;; frsqrt1 floating point reciprocal square root step1
369 ;; frsqrt2 floating point reciprocal square root step2
370 ;; multi multiword sequence (or user asm statements)
372 ;; ghost an instruction that produces no real code
374 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
375 prefetch,prefetchx,condmove,mtc,mfc,mthilo,mfhilo,const,arith,logical,
376 shift,slt,signext,clz,pop,trap,imul,imul3,imadd,idiv,move,fmove,fadd,fmul,
377 fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,
378 frsqrt2,multi,nop,ghost"
379 (cond [(eq_attr "jal" "!unset") (const_string "call")
380 (eq_attr "got" "load") (const_string "load")
382 ;; If a doubleword move uses these expensive instructions,
383 ;; it is usually better to schedule them in the same way
384 ;; as the singleword form, rather than as "multi".
385 (eq_attr "move_type" "load") (const_string "load")
386 (eq_attr "move_type" "fpload") (const_string "fpload")
387 (eq_attr "move_type" "store") (const_string "store")
388 (eq_attr "move_type" "fpstore") (const_string "fpstore")
389 (eq_attr "move_type" "mtc") (const_string "mtc")
390 (eq_attr "move_type" "mfc") (const_string "mfc")
391 (eq_attr "move_type" "mthilo") (const_string "mthilo")
392 (eq_attr "move_type" "mfhilo") (const_string "mfhilo")
394 ;; These types of move are always single insns.
395 (eq_attr "move_type" "fmove") (const_string "fmove")
396 (eq_attr "move_type" "loadpool") (const_string "load")
397 (eq_attr "move_type" "signext") (const_string "signext")
398 (eq_attr "move_type" "sll0") (const_string "shift")
399 (eq_attr "move_type" "andi") (const_string "logical")
401 ;; These types of move are always split.
402 (eq_attr "move_type" "constN,lui_movf,shift_shift")
403 (const_string "multi")
405 ;; These types of move are split for doubleword modes only.
406 (and (eq_attr "move_type" "move,const")
407 (eq_attr "dword_mode" "yes"))
408 (const_string "multi")
409 (eq_attr "move_type" "move") (const_string "move")
410 (eq_attr "move_type" "const") (const_string "const")]
411 (const_string "unknown")))
413 ;; Mode for conversion types (fcvt)
414 ;; I2S integer to float single (SI/DI to SF)
415 ;; I2D integer to float double (SI/DI to DF)
416 ;; S2I float to integer (SF to SI/DI)
417 ;; D2I float to integer (DF to SI/DI)
418 ;; D2S double to float single
419 ;; S2D float single to double
421 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
422 (const_string "unknown"))
424 ;; Is this an extended instruction in mips16 mode?
425 (define_attr "extended_mips16" "no,yes"
426 (if_then_else (ior (eq_attr "move_type" "sll0")
427 (eq_attr "type" "branch")
428 (eq_attr "jal" "direct"))
430 (const_string "no")))
432 ;; Length of instruction in bytes.
433 (define_attr "length" ""
434 (cond [(and (eq_attr "extended_mips16" "yes")
435 (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
438 ;; Direct branch instructions have a range of [-0x40000,0x3fffc].
439 ;; If a branch is outside this range, we have a choice of two
440 ;; sequences. For PIC, an out-of-range branch like:
445 ;; becomes the equivalent of:
454 ;; where the load address can be up to three instructions long
457 ;; The non-PIC case is similar except that we use a direct
458 ;; jump instead of an la/jr pair. Since the target of this
459 ;; jump is an absolute 28-bit bit address (the other bits
460 ;; coming from the address of the delay slot) this form cannot
461 ;; cross a 256MB boundary. We could provide the option of
462 ;; using la/jr in this case too, but we do not do so at
465 ;; Note that this value does not account for the delay slot
466 ;; instruction, whose length is added separately. If the RTL
467 ;; pattern has no explicit delay slot, mips_adjust_insn_length
468 ;; will add the length of the implicit nop. The values for
469 ;; forward and backward branches will be different as well.
470 (eq_attr "type" "branch")
471 (cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064))
472 (le (minus (pc) (match_dup 1)) (const_int 131068)))
474 (ne (symbol_ref "flag_pic") (const_int 0))
478 ;; "Ghost" instructions occupy no space.
479 (eq_attr "type" "ghost")
482 (eq_attr "got" "load")
483 (if_then_else (ne (symbol_ref "TARGET_MIPS16") (const_int 0))
486 (eq_attr "got" "xgot_high")
489 ;; In general, constant-pool loads are extended instructions.
490 (eq_attr "move_type" "loadpool")
493 ;; LUI_MOVFs are decomposed into two separate instructions.
494 (eq_attr "move_type" "lui_movf")
497 ;; SHIFT_SHIFTs are decomposed into two separate instructions.
498 ;; They are extended instructions on MIPS16 targets.
499 (eq_attr "move_type" "shift_shift")
500 (if_then_else (ne (symbol_ref "TARGET_MIPS16") (const_int 0))
504 ;; Check for doubleword moves that are decomposed into two
506 (and (eq_attr "move_type" "mtc,mfc,mthilo,mfhilo,move")
507 (eq_attr "dword_mode" "yes"))
510 ;; Doubleword CONST{,N} moves are split into two word
512 (and (eq_attr "move_type" "const,constN")
513 (eq_attr "dword_mode" "yes"))
514 (symbol_ref "mips_split_const_insns (operands[1]) * 4")
516 ;; Otherwise, constants, loads and stores are handled by external
518 (eq_attr "move_type" "const,constN")
519 (symbol_ref "mips_const_insns (operands[1]) * 4")
520 (eq_attr "move_type" "load,fpload")
521 (symbol_ref "mips_load_store_insns (operands[1], insn) * 4")
522 (eq_attr "move_type" "store,fpstore")
523 (symbol_ref "mips_load_store_insns (operands[0], insn) * 4")
525 ;; In the worst case, a call macro will take 8 instructions:
527 ;; lui $25,%call_hi(FOO)
529 ;; lw $25,%call_lo(FOO)($25)
535 (eq_attr "jal_macro" "yes")
538 ;; Various VR4120 errata require a nop to be inserted after a macc
539 ;; instruction. The assembler does this for us, so account for
540 ;; the worst-case length here.
541 (and (eq_attr "type" "imadd")
542 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))
545 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
546 ;; the result of the second one is missed. The assembler should work
547 ;; around this by inserting a nop after the first dmult.
548 (and (eq_attr "type" "imul,imul3")
549 (and (eq_attr "mode" "DI")
550 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
553 (eq_attr "type" "idiv")
554 (symbol_ref "mips_idiv_insns () * 4")
557 ;; Attribute describing the processor. This attribute must match exactly
558 ;; with the processor_type enumeration in mips.h.
560 "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,loongson_2e,loongson_2f,m4k,octeon,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000,xlr"
561 (const (symbol_ref "mips_tune")))
563 ;; The type of hardware hazard associated with this instruction.
564 ;; DELAY means that the next instruction cannot read the result
565 ;; of this one. HILO means that the next two instructions cannot
566 ;; write to HI or LO.
567 (define_attr "hazard" "none,delay,hilo"
568 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
569 (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
570 (const_string "delay")
572 (and (eq_attr "type" "mfc,mtc")
573 (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
574 (const_string "delay")
576 (and (eq_attr "type" "fcmp")
577 (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
578 (const_string "delay")
580 ;; The r4000 multiplication patterns include an mflo instruction.
581 (and (eq_attr "type" "imul")
582 (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
583 (const_string "hilo")
585 (and (eq_attr "type" "mfhilo")
586 (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
587 (const_string "hilo")]
588 (const_string "none")))
590 ;; Is it a single instruction?
591 (define_attr "single_insn" "no,yes"
592 (symbol_ref "get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)"))
594 ;; Can the instruction be put into a delay slot?
595 (define_attr "can_delay" "no,yes"
596 (if_then_else (and (eq_attr "type" "!branch,call,jump")
597 (and (eq_attr "hazard" "none")
598 (eq_attr "single_insn" "yes")))
600 (const_string "no")))
602 ;; Attribute defining whether or not we can use the branch-likely
604 (define_attr "branch_likely" "no,yes"
605 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
607 (const_string "no")))
609 ;; True if an instruction might assign to hi or lo when reloaded.
610 ;; This is used by the TUNE_MACC_CHAINS code.
611 (define_attr "may_clobber_hilo" "no,yes"
612 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
614 (const_string "no")))
616 ;; Describe a user's asm statement.
617 (define_asm_attributes
618 [(set_attr "type" "multi")
619 (set_attr "can_delay" "no")])
621 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
622 ;; from the same template.
623 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
625 ;; A copy of GPR that can be used when a pattern has two independent
627 (define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
629 ;; This mode iterator allows :HILO to be used as the mode of the
630 ;; concatenated HI and LO registers.
631 (define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")])
633 ;; This mode iterator allows :P to be used for patterns that operate on
634 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
635 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
637 ;; This mode iterator allows :MOVECC to be used anywhere that a
638 ;; conditional-move-type condition is needed.
639 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
640 (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF")])
642 ;; 64-bit modes for which we provide move patterns.
643 (define_mode_iterator MOVE64
645 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")
646 (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
647 (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
648 (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")])
650 ;; 128-bit modes for which we provide move patterns on 64-bit targets.
651 (define_mode_iterator MOVE128 [TI TF])
653 ;; This mode iterator allows the QI and HI extension patterns to be
654 ;; defined from the same template.
655 (define_mode_iterator SHORT [QI HI])
657 ;; Likewise the 64-bit truncate-and-shift patterns.
658 (define_mode_iterator SUBDI [QI HI SI])
660 ;; This mode iterator allows :ANYF to be used wherever a scalar or vector
661 ;; floating-point mode is allowed.
662 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
663 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
664 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
666 ;; Like ANYF, but only applies to scalar modes.
667 (define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
668 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
670 ;; A floating-point mode for which moves involving FPRs may need to be split.
671 (define_mode_iterator SPLITF
672 [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
673 (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
674 (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT")
675 (V2SI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
676 (V4HI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
677 (V8QI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
678 (TF "TARGET_64BIT && TARGET_FLOAT64")])
680 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
681 ;; 32-bit version and "dsubu" in the 64-bit version.
682 (define_mode_attr d [(SI "") (DI "d")
683 (QQ "") (HQ "") (SQ "") (DQ "d")
684 (UQQ "") (UHQ "") (USQ "") (UDQ "d")
685 (HA "") (SA "") (DA "d")
686 (UHA "") (USA "") (UDA "d")])
688 ;; Same as d but upper-case.
689 (define_mode_attr D [(SI "") (DI "D")
690 (QQ "") (HQ "") (SQ "") (DQ "D")
691 (UQQ "") (UHQ "") (USQ "") (UDQ "D")
692 (HA "") (SA "") (DA "D")
693 (UHA "") (USA "") (UDA "D")])
695 ;; This attribute gives the length suffix for a sign- or zero-extension
697 (define_mode_attr size [(QI "b") (HI "h")])
699 ;; This attributes gives the mode mask of a SHORT.
700 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
702 ;; Mode attributes for GPR loads and stores.
703 (define_mode_attr load [(SI "lw") (DI "ld")])
704 (define_mode_attr store [(SI "sw") (DI "sd")])
706 ;; Similarly for MIPS IV indexed FPR loads and stores.
707 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
708 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
710 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
711 ;; are different. Some forms of unextended addiu have an 8-bit immediate
712 ;; field but the equivalent daddiu has only a 5-bit field.
713 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
715 ;; This attribute gives the best constraint to use for registers of
717 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
719 ;; This attribute gives the format suffix for floating-point operations.
720 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
722 ;; This attribute gives the upper-case mode name for one unit of a
723 ;; floating-point mode.
724 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
726 ;; This attribute gives the integer mode that has the same size as a
728 (define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI")
729 (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI")
730 (HA "HI") (SA "SI") (DA "DI")
731 (UHA "HI") (USA "SI") (UDA "DI")
732 (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")
733 (V2HQ "SI") (V2HA "SI")])
735 ;; This attribute gives the integer mode that has half the size of
736 ;; the controlling mode.
737 (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI")
738 (V2SI "SI") (V4HI "SI") (V8QI "SI")
741 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
743 ;; In certain cases, div.s and div.ps may have a rounding error
744 ;; and/or wrong inexact flag.
746 ;; Therefore, we only allow div.s if not working around SB-1 rev2
747 ;; errata or if a slight loss of precision is OK.
748 (define_mode_attr divide_condition
749 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
750 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
752 ;; This attribute gives the conditions under which SQRT.fmt instructions
754 (define_mode_attr sqrt_condition
755 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
757 ;; This attribute gives the conditions under which RECIP.fmt and RSQRT.fmt
758 ;; instructions can be used. The MIPS32 and MIPS64 ISAs say that RECIP.D
759 ;; and RSQRT.D are unpredictable when doubles are stored in pairs of FPRs,
760 ;; so for safety's sake, we apply this restriction to all targets.
761 (define_mode_attr recip_condition
763 (DF "ISA_HAS_FP4 && TARGET_FLOAT64")
764 (V2SF "TARGET_SB1")])
766 ;; This code iterator allows all branch instructions to be generated from
767 ;; a single define_expand template.
768 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
769 eq ne gt ge lt le gtu geu ltu leu])
771 ;; This code iterator allows signed and unsigned widening multiplications
772 ;; to use the same template.
773 (define_code_iterator any_extend [sign_extend zero_extend])
775 ;; This code iterator allows the three shift instructions to be generated
776 ;; from the same template.
777 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
779 ;; This code iterator allows unsigned and signed division to be generated
780 ;; from the same template.
781 (define_code_iterator any_div [div udiv])
783 ;; This code iterator allows all native floating-point comparisons to be
784 ;; generated from the same template.
785 (define_code_iterator fcond [unordered uneq unlt unle eq lt le])
787 ;; This code iterator is used for comparisons that can be implemented
788 ;; by swapping the operands.
789 (define_code_iterator swapped_fcond [ge gt unge ungt])
791 ;; Equality operators.
792 (define_code_iterator equality_op [eq ne])
794 ;; These code iterators allow the signed and unsigned scc operations to use
795 ;; the same template.
796 (define_code_iterator any_gt [gt gtu])
797 (define_code_iterator any_ge [ge geu])
798 (define_code_iterator any_lt [lt ltu])
799 (define_code_iterator any_le [le leu])
801 ;; <u> expands to an empty string when doing a signed operation and
802 ;; "u" when doing an unsigned operation.
803 (define_code_attr u [(sign_extend "") (zero_extend "u")
810 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
811 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
813 ;; <optab> expands to the name of the optab for a particular code.
814 (define_code_attr optab [(ashift "ashl")
823 ;; <insn> expands to the name of the insn that implements a particular code.
824 (define_code_attr insn [(ashift "sll")
833 ;; <immediate_insn> expands to the name of the insn that implements
834 ;; a particular code to operate on immediate values.
835 (define_code_attr immediate_insn [(ior "ori")
839 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
840 (define_code_attr fcond [(unordered "un")
848 ;; Similar, but for swapped conditions.
849 (define_code_attr swapped_fcond [(ge "le")
854 ;; The value of the bit when the branch is taken for branch_bit patterns.
855 ;; Comparison is always against zero so this depends on the operator.
856 (define_code_attr bbv [(eq "0") (ne "1")])
858 ;; This is the inverse value of bbv.
859 (define_code_attr bbinv [(eq "1") (ne "0")])
861 ;; .........................
863 ;; Branch, call and jump delay slots
865 ;; .........................
867 (define_delay (and (eq_attr "type" "branch")
868 (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
869 (eq_attr "branch_likely" "yes"))
870 [(eq_attr "can_delay" "yes")
872 (eq_attr "can_delay" "yes")])
874 ;; Branches that don't have likely variants do not annul on false.
875 (define_delay (and (eq_attr "type" "branch")
876 (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
877 (eq_attr "branch_likely" "no"))
878 [(eq_attr "can_delay" "yes")
882 (define_delay (eq_attr "type" "jump")
883 [(eq_attr "can_delay" "yes")
887 (define_delay (and (eq_attr "type" "call")
888 (eq_attr "jal_macro" "no"))
889 [(eq_attr "can_delay" "yes")
893 ;; Pipeline descriptions.
895 ;; generic.md provides a fallback for processors without a specific
896 ;; pipeline description. It is derived from the old define_function_unit
897 ;; version and uses the "alu" and "imuldiv" units declared below.
899 ;; Some of the processor-specific files are also derived from old
900 ;; define_function_unit descriptions and simply override the parts of
901 ;; generic.md that don't apply. The other processor-specific files
902 ;; are self-contained.
903 (define_automaton "alu,imuldiv")
905 (define_cpu_unit "alu" "alu")
906 (define_cpu_unit "imuldiv" "imuldiv")
908 ;; Ghost instructions produce no real code and introduce no hazards.
909 ;; They exist purely to express an effect on dataflow.
910 (define_insn_reservation "ghost" 0
911 (eq_attr "type" "ghost")
934 (include "loongson2ef.md")
935 (include "generic.md")
938 ;; ....................
942 ;; ....................
946 [(trap_if (const_int 1) (const_int 0))]
949 if (ISA_HAS_COND_TRAP)
951 else if (TARGET_MIPS16)
956 [(set_attr "type" "trap")])
958 (define_expand "conditional_trap"
959 [(trap_if (match_operator 0 "comparison_operator"
960 [(match_dup 2) (match_dup 3)])
961 (match_operand 1 "const_int_operand"))]
964 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT
965 && operands[1] == const0_rtx)
967 mips_expand_conditional_trap (GET_CODE (operands[0]));
973 (define_insn "*conditional_trap<mode>"
974 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
975 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
976 (match_operand:GPR 2 "arith_operand" "dI")])
980 [(set_attr "type" "trap")])
983 ;; ....................
987 ;; ....................
990 (define_insn "add<mode>3"
991 [(set (match_operand:ANYF 0 "register_operand" "=f")
992 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
993 (match_operand:ANYF 2 "register_operand" "f")))]
995 "add.<fmt>\t%0,%1,%2"
996 [(set_attr "type" "fadd")
997 (set_attr "mode" "<UNITMODE>")])
999 (define_expand "add<mode>3"
1000 [(set (match_operand:GPR 0 "register_operand")
1001 (plus:GPR (match_operand:GPR 1 "register_operand")
1002 (match_operand:GPR 2 "arith_operand")))]
1005 (define_insn "*add<mode>3"
1006 [(set (match_operand:GPR 0 "register_operand" "=d,d")
1007 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
1008 (match_operand:GPR 2 "arith_operand" "d,Q")))]
1013 [(set_attr "type" "arith")
1014 (set_attr "mode" "<MODE>")])
1016 (define_insn "*add<mode>3_mips16"
1017 [(set (match_operand:GPR 0 "register_operand" "=ks,d,d,d,d")
1018 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,0,d,d")
1019 (match_operand:GPR 2 "arith_operand" "Q,Q,Q,O,d")))]
1027 [(set_attr "type" "arith")
1028 (set_attr "mode" "<MODE>")
1029 (set_attr_alternative "length"
1030 [(if_then_else (match_operand 2 "m16_simm8_8")
1033 (if_then_else (match_operand 2 "m16_uimm<si8_di5>_4")
1036 (if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
1039 (if_then_else (match_operand 2 "m16_simm4_1")
1044 ;; On the mips16, we can sometimes split an add of a constant which is
1045 ;; a 4 byte instruction into two adds which are both 2 byte
1046 ;; instructions. There are two cases: one where we are adding a
1047 ;; constant plus a register to another register, and one where we are
1048 ;; simply adding a constant to a register.
1051 [(set (match_operand:SI 0 "d_operand")
1052 (plus:SI (match_dup 0)
1053 (match_operand:SI 1 "const_int_operand")))]
1054 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1055 && ((INTVAL (operands[1]) > 0x7f
1056 && INTVAL (operands[1]) <= 0x7f + 0x7f)
1057 || (INTVAL (operands[1]) < - 0x80
1058 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
1059 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
1060 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1062 HOST_WIDE_INT val = INTVAL (operands[1]);
1066 operands[1] = GEN_INT (0x7f);
1067 operands[2] = GEN_INT (val - 0x7f);
1071 operands[1] = GEN_INT (- 0x80);
1072 operands[2] = GEN_INT (val + 0x80);
1077 [(set (match_operand:SI 0 "d_operand")
1078 (plus:SI (match_operand:SI 1 "d_operand")
1079 (match_operand:SI 2 "const_int_operand")))]
1080 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1081 && REGNO (operands[0]) != REGNO (operands[1])
1082 && ((INTVAL (operands[2]) > 0x7
1083 && INTVAL (operands[2]) <= 0x7 + 0x7f)
1084 || (INTVAL (operands[2]) < - 0x8
1085 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
1086 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
1087 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
1089 HOST_WIDE_INT val = INTVAL (operands[2]);
1093 operands[2] = GEN_INT (0x7);
1094 operands[3] = GEN_INT (val - 0x7);
1098 operands[2] = GEN_INT (- 0x8);
1099 operands[3] = GEN_INT (val + 0x8);
1104 [(set (match_operand:DI 0 "d_operand")
1105 (plus:DI (match_dup 0)
1106 (match_operand:DI 1 "const_int_operand")))]
1107 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1108 && ((INTVAL (operands[1]) > 0xf
1109 && INTVAL (operands[1]) <= 0xf + 0xf)
1110 || (INTVAL (operands[1]) < - 0x10
1111 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
1112 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
1113 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
1115 HOST_WIDE_INT val = INTVAL (operands[1]);
1119 operands[1] = GEN_INT (0xf);
1120 operands[2] = GEN_INT (val - 0xf);
1124 operands[1] = GEN_INT (- 0x10);
1125 operands[2] = GEN_INT (val + 0x10);
1130 [(set (match_operand:DI 0 "d_operand")
1131 (plus:DI (match_operand:DI 1 "d_operand")
1132 (match_operand:DI 2 "const_int_operand")))]
1133 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1134 && REGNO (operands[0]) != REGNO (operands[1])
1135 && ((INTVAL (operands[2]) > 0x7
1136 && INTVAL (operands[2]) <= 0x7 + 0xf)
1137 || (INTVAL (operands[2]) < - 0x8
1138 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
1139 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
1140 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
1142 HOST_WIDE_INT val = INTVAL (operands[2]);
1146 operands[2] = GEN_INT (0x7);
1147 operands[3] = GEN_INT (val - 0x7);
1151 operands[2] = GEN_INT (- 0x8);
1152 operands[3] = GEN_INT (val + 0x8);
1156 (define_insn "*addsi3_extended"
1157 [(set (match_operand:DI 0 "register_operand" "=d,d")
1159 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
1160 (match_operand:SI 2 "arith_operand" "d,Q"))))]
1161 "TARGET_64BIT && !TARGET_MIPS16"
1165 [(set_attr "type" "arith")
1166 (set_attr "mode" "SI")])
1168 ;; Split this insn so that the addiu splitters can have a crack at it.
1169 ;; Use a conservative length estimate until the split.
1170 (define_insn_and_split "*addsi3_extended_mips16"
1171 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1173 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
1174 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
1175 "TARGET_64BIT && TARGET_MIPS16"
1177 "&& reload_completed"
1178 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
1179 { operands[3] = gen_lowpart (SImode, operands[0]); }
1180 [(set_attr "type" "arith")
1181 (set_attr "mode" "SI")
1182 (set_attr "extended_mips16" "yes")])
1185 ;; ....................
1189 ;; ....................
1192 (define_insn "sub<mode>3"
1193 [(set (match_operand:ANYF 0 "register_operand" "=f")
1194 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1195 (match_operand:ANYF 2 "register_operand" "f")))]
1197 "sub.<fmt>\t%0,%1,%2"
1198 [(set_attr "type" "fadd")
1199 (set_attr "mode" "<UNITMODE>")])
1201 (define_insn "sub<mode>3"
1202 [(set (match_operand:GPR 0 "register_operand" "=d")
1203 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
1204 (match_operand:GPR 2 "register_operand" "d")))]
1207 [(set_attr "type" "arith")
1208 (set_attr "mode" "<MODE>")])
1210 (define_insn "*subsi3_extended"
1211 [(set (match_operand:DI 0 "register_operand" "=d")
1213 (minus:SI (match_operand:SI 1 "register_operand" "d")
1214 (match_operand:SI 2 "register_operand" "d"))))]
1217 [(set_attr "type" "arith")
1218 (set_attr "mode" "DI")])
1221 ;; ....................
1225 ;; ....................
1228 (define_expand "mul<mode>3"
1229 [(set (match_operand:SCALARF 0 "register_operand")
1230 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
1231 (match_operand:SCALARF 2 "register_operand")))]
1235 (define_insn "*mul<mode>3"
1236 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1237 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1238 (match_operand:SCALARF 2 "register_operand" "f")))]
1239 "!TARGET_4300_MUL_FIX"
1240 "mul.<fmt>\t%0,%1,%2"
1241 [(set_attr "type" "fmul")
1242 (set_attr "mode" "<MODE>")])
1244 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
1245 ;; operands may corrupt immediately following multiplies. This is a
1246 ;; simple fix to insert NOPs.
1248 (define_insn "*mul<mode>3_r4300"
1249 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1250 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1251 (match_operand:SCALARF 2 "register_operand" "f")))]
1252 "TARGET_4300_MUL_FIX"
1253 "mul.<fmt>\t%0,%1,%2\;nop"
1254 [(set_attr "type" "fmul")
1255 (set_attr "mode" "<MODE>")
1256 (set_attr "length" "8")])
1258 (define_insn "mulv2sf3"
1259 [(set (match_operand:V2SF 0 "register_operand" "=f")
1260 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1261 (match_operand:V2SF 2 "register_operand" "f")))]
1262 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
1264 [(set_attr "type" "fmul")
1265 (set_attr "mode" "SF")])
1267 ;; The original R4000 has a cpu bug. If a double-word or a variable
1268 ;; shift executes while an integer multiplication is in progress, the
1269 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1270 ;; with the mult on the R4000.
1272 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1273 ;; (also valid for MIPS R4000MC processors):
1275 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1276 ;; this errata description.
1277 ;; The following code sequence causes the R4000 to incorrectly
1278 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1279 ;; instruction. If the dsra32 instruction is executed during an
1280 ;; integer multiply, the dsra32 will only shift by the amount in
1281 ;; specified in the instruction rather than the amount plus 32
1283 ;; instruction 1: mult rs,rt integer multiply
1284 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1285 ;; right arithmetic + 32
1286 ;; Workaround: A dsra32 instruction placed after an integer
1287 ;; multiply should not be one of the 11 instructions after the
1288 ;; multiply instruction."
1292 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1293 ;; the following description.
1294 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1295 ;; 64-bit versions) may produce incorrect results under the
1296 ;; following conditions:
1297 ;; 1) An integer multiply is currently executing
1298 ;; 2) These types of shift instructions are executed immediately
1299 ;; following an integer divide instruction.
1301 ;; 1) Make sure no integer multiply is running wihen these
1302 ;; instruction are executed. If this cannot be predicted at
1303 ;; compile time, then insert a "mfhi" to R0 instruction
1304 ;; immediately after the integer multiply instruction. This
1305 ;; will cause the integer multiply to complete before the shift
1307 ;; 2) Separate integer divide and these two classes of shift
1308 ;; instructions by another instruction or a noop."
1310 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1313 (define_expand "mul<mode>3"
1314 [(set (match_operand:GPR 0 "register_operand")
1315 (mult:GPR (match_operand:GPR 1 "register_operand")
1316 (match_operand:GPR 2 "register_operand")))]
1319 if (ISA_HAS_<D>MUL3)
1320 emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2]));
1321 else if (TARGET_FIX_R4000)
1322 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
1325 (gen_mul<mode>3_internal (operands[0], operands[1], operands[2]));
1329 (define_insn "mulsi3_mul3"
1330 [(set (match_operand:SI 0 "register_operand" "=d,l")
1331 (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1332 (match_operand:SI 2 "register_operand" "d,d")))
1333 (clobber (match_scratch:SI 3 "=l,X"))]
1336 if (which_alternative == 1)
1337 return "mult\t%1,%2";
1338 if (TARGET_MIPS3900)
1339 return "mult\t%0,%1,%2";
1340 return "mul\t%0,%1,%2";
1342 [(set_attr "type" "imul3,imul")
1343 (set_attr "mode" "SI")])
1345 (define_insn "muldi3_mul3"
1346 [(set (match_operand:DI 0 "register_operand" "=d,l")
1347 (mult:DI (match_operand:DI 1 "register_operand" "d,d")
1348 (match_operand:DI 2 "register_operand" "d,d")))
1349 (clobber (match_scratch:DI 3 "=l,X"))]
1352 if (which_alternative == 1)
1353 return "dmult\t%1,%2";
1354 return "dmul\t%0,%1,%2";
1356 [(set_attr "type" "imul3,imul")
1357 (set_attr "mode" "DI")])
1359 ;; If a register gets allocated to LO, and we spill to memory, the reload
1360 ;; will include a move from LO to a GPR. Merge it into the multiplication
1361 ;; if it can set the GPR directly.
1364 ;; Operand 1: GPR (1st multiplication operand)
1365 ;; Operand 2: GPR (2nd multiplication operand)
1366 ;; Operand 3: GPR (destination)
1369 [(set (match_operand:SI 0 "lo_operand")
1370 (mult:SI (match_operand:SI 1 "d_operand")
1371 (match_operand:SI 2 "d_operand")))
1372 (clobber (scratch:SI))])
1373 (set (match_operand:SI 3 "d_operand")
1375 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1378 (mult:SI (match_dup 1)
1380 (clobber (match_dup 0))])])
1382 (define_insn "mul<mode>3_internal"
1383 [(set (match_operand:GPR 0 "register_operand" "=l")
1384 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1385 (match_operand:GPR 2 "register_operand" "d")))]
1388 [(set_attr "type" "imul")
1389 (set_attr "mode" "<MODE>")])
1391 (define_insn "mul<mode>3_r4000"
1392 [(set (match_operand:GPR 0 "register_operand" "=d")
1393 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1394 (match_operand:GPR 2 "register_operand" "d")))
1395 (clobber (match_scratch:GPR 3 "=l"))]
1397 "<d>mult\t%1,%2\;mflo\t%0"
1398 [(set_attr "type" "imul")
1399 (set_attr "mode" "<MODE>")
1400 (set_attr "length" "8")])
1402 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1403 ;; of "mult; mflo". They have the same latency, but the first form gives
1404 ;; us an extra cycle to compute the operands.
1407 ;; Operand 1: GPR (1st multiplication operand)
1408 ;; Operand 2: GPR (2nd multiplication operand)
1409 ;; Operand 3: GPR (destination)
1411 [(set (match_operand:SI 0 "lo_operand")
1412 (mult:SI (match_operand:SI 1 "d_operand")
1413 (match_operand:SI 2 "d_operand")))
1414 (set (match_operand:SI 3 "d_operand")
1416 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1421 (plus:SI (mult:SI (match_dup 1)
1425 (plus:SI (mult:SI (match_dup 1)
1429 ;; Multiply-accumulate patterns
1431 ;; For processors that can copy the output to a general register:
1433 ;; The all-d alternative is needed because the combiner will find this
1434 ;; pattern and then register alloc/reload will move registers around to
1435 ;; make them fit, and we don't want to trigger unnecessary loads to LO.
1437 ;; The last alternative should be made slightly less desirable, but adding
1438 ;; "?" to the constraint is too strong, and causes values to be loaded into
1439 ;; LO even when that's more costly. For now, using "*d" mostly does the
1441 (define_insn "*mul_acc_si"
1442 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1443 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1444 (match_operand:SI 2 "register_operand" "d,d,d"))
1445 (match_operand:SI 3 "register_operand" "0,l,*d")))
1446 (clobber (match_scratch:SI 4 "=X,3,l"))
1447 (clobber (match_scratch:SI 5 "=X,X,&d"))]
1449 || GENERATE_MADD_MSUB)
1452 static const char *const madd[] = { "madd\t%1,%2", "madd\t%0,%1,%2" };
1453 if (which_alternative == 2)
1455 if (GENERATE_MADD_MSUB && which_alternative != 0)
1457 return madd[which_alternative];
1459 [(set_attr "type" "imadd")
1460 (set_attr "mode" "SI")
1461 (set_attr "length" "4,4,8")])
1463 ;; Split *mul_acc_si if both the source and destination accumulator
1466 [(set (match_operand:SI 0 "d_operand")
1467 (plus:SI (mult:SI (match_operand:SI 1 "d_operand")
1468 (match_operand:SI 2 "d_operand"))
1469 (match_operand:SI 3 "d_operand")))
1470 (clobber (match_operand:SI 4 "lo_operand"))
1471 (clobber (match_operand:SI 5 "d_operand"))]
1473 [(parallel [(set (match_dup 5)
1474 (mult:SI (match_dup 1) (match_dup 2)))
1475 (clobber (match_dup 4))])
1476 (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))]
1479 ;; Split *mul_acc_si if the destination accumulator value is in a GPR
1480 ;; and the source accumulator value is in LO.
1482 [(set (match_operand:SI 0 "d_operand")
1483 (plus:SI (mult:SI (match_operand:SI 1 "d_operand")
1484 (match_operand:SI 2 "d_operand"))
1485 (match_operand:SI 3 "lo_operand")))
1486 (clobber (match_dup 3))
1487 (clobber (scratch:SI))]
1489 [(parallel [(set (match_dup 3)
1490 (plus:SI (mult:SI (match_dup 1) (match_dup 2))
1492 (clobber (scratch:SI))
1493 (clobber (scratch:SI))])
1494 (set (match_dup 0) (match_dup 3))])
1496 (define_insn "*macc"
1497 [(set (match_operand:SI 0 "register_operand" "=l,d")
1498 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1499 (match_operand:SI 2 "register_operand" "d,d"))
1500 (match_operand:SI 3 "register_operand" "0,l")))
1501 (clobber (match_scratch:SI 4 "=X,3"))]
1504 if (which_alternative == 1)
1505 return "macc\t%0,%1,%2";
1506 else if (TARGET_MIPS5500)
1507 return "madd\t%1,%2";
1509 /* The VR4130 assumes that there is a two-cycle latency between a macc
1510 that "writes" to $0 and an instruction that reads from it. We avoid
1511 this by assigning to $1 instead. */
1512 return "%[macc\t%@,%1,%2%]";
1514 [(set_attr "type" "imadd")
1515 (set_attr "mode" "SI")])
1517 (define_insn "*msac"
1518 [(set (match_operand:SI 0 "register_operand" "=l,d")
1519 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1520 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1521 (match_operand:SI 3 "register_operand" "d,d"))))
1522 (clobber (match_scratch:SI 4 "=X,1"))]
1525 if (which_alternative == 1)
1526 return "msac\t%0,%2,%3";
1527 else if (TARGET_MIPS5500)
1528 return "msub\t%2,%3";
1530 return "msac\t$0,%2,%3";
1532 [(set_attr "type" "imadd")
1533 (set_attr "mode" "SI")])
1535 ;; An msac-like instruction implemented using negation and a macc.
1536 (define_insn_and_split "*msac_using_macc"
1537 [(set (match_operand:SI 0 "register_operand" "=l,d")
1538 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1539 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1540 (match_operand:SI 3 "register_operand" "d,d"))))
1541 (clobber (match_scratch:SI 4 "=X,1"))
1542 (clobber (match_scratch:SI 5 "=d,d"))]
1543 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1545 "&& reload_completed"
1547 (neg:SI (match_dup 3)))
1550 (plus:SI (mult:SI (match_dup 2)
1553 (clobber (match_dup 4))])]
1555 [(set_attr "type" "imadd")
1556 (set_attr "length" "8")])
1558 ;; Patterns generated by the define_peephole2 below.
1560 (define_insn "*macc2"
1561 [(set (match_operand:SI 0 "register_operand" "=l")
1562 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1563 (match_operand:SI 2 "register_operand" "d"))
1565 (set (match_operand:SI 3 "register_operand" "=d")
1566 (plus:SI (mult:SI (match_dup 1)
1569 "ISA_HAS_MACC && reload_completed"
1571 [(set_attr "type" "imadd")
1572 (set_attr "mode" "SI")])
1574 (define_insn "*msac2"
1575 [(set (match_operand:SI 0 "register_operand" "=l")
1576 (minus:SI (match_dup 0)
1577 (mult:SI (match_operand:SI 1 "register_operand" "d")
1578 (match_operand:SI 2 "register_operand" "d"))))
1579 (set (match_operand:SI 3 "register_operand" "=d")
1580 (minus:SI (match_dup 0)
1581 (mult:SI (match_dup 1)
1583 "ISA_HAS_MSAC && reload_completed"
1585 [(set_attr "type" "imadd")
1586 (set_attr "mode" "SI")])
1588 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1592 ;; Operand 1: macc/msac
1593 ;; Operand 2: GPR (destination)
1596 [(set (match_operand:SI 0 "lo_operand")
1597 (match_operand:SI 1 "macc_msac_operand"))
1598 (clobber (scratch:SI))])
1599 (set (match_operand:SI 2 "d_operand")
1602 [(parallel [(set (match_dup 0)
1607 ;; When we have a three-address multiplication instruction, it should
1608 ;; be faster to do a separate multiply and add, rather than moving
1609 ;; something into LO in order to use a macc instruction.
1611 ;; This peephole needs a scratch register to cater for the case when one
1612 ;; of the multiplication operands is the same as the destination.
1614 ;; Operand 0: GPR (scratch)
1616 ;; Operand 2: GPR (addend)
1617 ;; Operand 3: GPR (destination)
1618 ;; Operand 4: macc/msac
1619 ;; Operand 5: new multiplication
1620 ;; Operand 6: new addition/subtraction
1622 [(match_scratch:SI 0 "d")
1623 (set (match_operand:SI 1 "lo_operand")
1624 (match_operand:SI 2 "d_operand"))
1627 [(set (match_operand:SI 3 "d_operand")
1628 (match_operand:SI 4 "macc_msac_operand"))
1629 (clobber (match_dup 1))])]
1630 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])"
1631 [(parallel [(set (match_dup 0)
1633 (clobber (match_dup 1))])
1637 operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1638 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1639 operands[2], operands[0]);
1642 ;; Same as above, except LO is the initial target of the macc.
1644 ;; Operand 0: GPR (scratch)
1646 ;; Operand 2: GPR (addend)
1647 ;; Operand 3: macc/msac
1648 ;; Operand 4: GPR (destination)
1649 ;; Operand 5: new multiplication
1650 ;; Operand 6: new addition/subtraction
1652 [(match_scratch:SI 0 "d")
1653 (set (match_operand:SI 1 "lo_operand")
1654 (match_operand:SI 2 "d_operand"))
1658 (match_operand:SI 3 "macc_msac_operand"))
1659 (clobber (scratch:SI))])
1661 (set (match_operand:SI 4 "d_operand")
1663 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1664 [(parallel [(set (match_dup 0)
1666 (clobber (match_dup 1))])
1670 operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1);
1671 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
1672 operands[2], operands[0]);
1675 (define_insn "*mul_sub_si"
1676 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1677 (minus:SI (match_operand:SI 1 "register_operand" "0,l,*d")
1678 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
1679 (match_operand:SI 3 "register_operand" "d,d,d"))))
1680 (clobber (match_scratch:SI 4 "=X,1,l"))
1681 (clobber (match_scratch:SI 5 "=X,X,&d"))]
1682 "GENERATE_MADD_MSUB"
1687 [(set_attr "type" "imadd")
1688 (set_attr "mode" "SI")
1689 (set_attr "length" "4,8,8")])
1691 ;; Split *mul_sub_si if both the source and destination accumulator
1694 [(set (match_operand:SI 0 "d_operand")
1695 (minus:SI (match_operand:SI 1 "d_operand")
1696 (mult:SI (match_operand:SI 2 "d_operand")
1697 (match_operand:SI 3 "d_operand"))))
1698 (clobber (match_operand:SI 4 "lo_operand"))
1699 (clobber (match_operand:SI 5 "d_operand"))]
1701 [(parallel [(set (match_dup 5)
1702 (mult:SI (match_dup 2) (match_dup 3)))
1703 (clobber (match_dup 4))])
1704 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))]
1707 ;; Split *mul_acc_si if the destination accumulator value is in a GPR
1708 ;; and the source accumulator value is in LO.
1710 [(set (match_operand:SI 0 "d_operand")
1711 (minus:SI (match_operand:SI 1 "lo_operand")
1712 (mult:SI (match_operand:SI 2 "d_operand")
1713 (match_operand:SI 3 "d_operand"))))
1714 (clobber (match_dup 1))
1715 (clobber (scratch:SI))]
1717 [(parallel [(set (match_dup 1)
1718 (minus:SI (match_dup 1)
1719 (mult:SI (match_dup 2) (match_dup 3))))
1720 (clobber (scratch:SI))
1721 (clobber (scratch:SI))])
1722 (set (match_dup 0) (match_dup 1))]
1725 (define_insn "*muls"
1726 [(set (match_operand:SI 0 "register_operand" "=l,d")
1727 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1728 (match_operand:SI 2 "register_operand" "d,d"))))
1729 (clobber (match_scratch:SI 3 "=X,l"))]
1734 [(set_attr "type" "imul,imul3")
1735 (set_attr "mode" "SI")])
1737 (define_expand "<u>mulsidi3"
1738 [(set (match_operand:DI 0 "register_operand")
1739 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1740 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
1741 "!TARGET_64BIT || !TARGET_FIX_R4000"
1744 emit_insn (gen_<u>mulsidi3_64bit (operands[0], operands[1], operands[2]));
1745 else if (TARGET_FIX_R4000)
1746 emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1],
1749 emit_insn (gen_<u>mulsidi3_32bit (operands[0], operands[1], operands[2]));
1753 (define_insn "<u>mulsidi3_32bit"
1754 [(set (match_operand:DI 0 "register_operand" "=x")
1755 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1756 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1757 "!TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DSPR2"
1759 [(set_attr "type" "imul")
1760 (set_attr "mode" "SI")])
1762 (define_insn "<u>mulsidi3_32bit_r4000"
1763 [(set (match_operand:DI 0 "register_operand" "=d")
1764 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1765 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1766 (clobber (match_scratch:DI 3 "=x"))]
1767 "!TARGET_64BIT && TARGET_FIX_R4000"
1768 "mult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
1769 [(set_attr "type" "imul")
1770 (set_attr "mode" "SI")
1771 (set_attr "length" "12")])
1773 (define_insn_and_split "<u>mulsidi3_64bit"
1774 [(set (match_operand:DI 0 "register_operand" "=d")
1775 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1776 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1777 (clobber (match_scratch:TI 3 "=x"))
1778 (clobber (match_scratch:DI 4 "=d"))]
1779 "TARGET_64BIT && !TARGET_FIX_R4000"
1781 "&& reload_completed"
1783 (unspec:TI [(mult:DI (any_extend:DI (match_dup 1))
1784 (any_extend:DI (match_dup 2)))]
1787 ;; OP4 <- LO, OP0 <- HI
1788 (set (match_dup 4) (match_dup 5))
1789 (set (match_dup 0) (unspec:DI [(match_dup 3)] UNSPEC_MFHI))
1793 (ashift:DI (match_dup 4)
1796 (lshiftrt:DI (match_dup 4)
1799 ;; Shift OP0 into place.
1801 (ashift:DI (match_dup 0)
1804 ;; OR the two halves together
1806 (ior:DI (match_dup 0)
1808 { operands[5] = gen_rtx_REG (DImode, LO_REGNUM); }
1809 [(set_attr "type" "imul")
1810 (set_attr "mode" "SI")
1811 (set_attr "length" "24")])
1813 (define_insn "<u>mulsidi3_64bit_hilo"
1814 [(set (match_operand:TI 0 "register_operand" "=x")
1817 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1818 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))]
1820 "TARGET_64BIT && !TARGET_FIX_R4000"
1822 [(set_attr "type" "imul")
1823 (set_attr "mode" "SI")])
1825 ;; Widening multiply with negation.
1826 (define_insn "*muls<u>_di"
1827 [(set (match_operand:DI 0 "register_operand" "=x")
1830 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1831 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1832 "!TARGET_64BIT && ISA_HAS_MULS"
1834 [(set_attr "type" "imul")
1835 (set_attr "mode" "SI")])
1837 (define_insn "<u>msubsidi4"
1838 [(set (match_operand:DI 0 "register_operand" "=ka")
1840 (match_operand:DI 3 "register_operand" "0")
1842 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1843 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1844 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)"
1847 return "msub<u>\t%q0,%1,%2";
1848 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
1849 return "msub<u>\t%1,%2";
1851 return "msac<u>\t$0,%1,%2";
1853 [(set_attr "type" "imadd")
1854 (set_attr "mode" "SI")])
1856 ;; _highpart patterns
1858 (define_expand "<su>mulsi3_highpart"
1859 [(set (match_operand:SI 0 "register_operand")
1862 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1863 (any_extend:DI (match_operand:SI 2 "register_operand")))
1868 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
1872 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
1877 (define_insn_and_split "<su>mulsi3_highpart_internal"
1878 [(set (match_operand:SI 0 "register_operand" "=d")
1881 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1882 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1884 (clobber (match_scratch:SI 3 "=l"))]
1886 { return TARGET_FIX_R4000 ? "mult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
1887 "&& reload_completed && !TARGET_FIX_R4000"
1894 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
1895 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
1896 emit_insn (gen_mfhisi_ti (operands[0], hilo));
1900 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
1901 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
1902 emit_insn (gen_mfhisi_di (operands[0], hilo));
1906 [(set_attr "type" "imul")
1907 (set_attr "mode" "SI")
1908 (set_attr "length" "8")])
1910 (define_insn "<su>mulsi3_highpart_mulhi_internal"
1911 [(set (match_operand:SI 0 "register_operand" "=d")
1915 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1916 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1918 (clobber (match_scratch:SI 3 "=l"))]
1920 "mulhi<u>\t%0,%1,%2"
1921 [(set_attr "type" "imul3")
1922 (set_attr "mode" "SI")])
1924 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
1925 [(set (match_operand:SI 0 "register_operand" "=d")
1930 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1931 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1933 (clobber (match_scratch:SI 3 "=l"))]
1935 "mulshi<u>\t%0,%1,%2"
1936 [(set_attr "type" "imul3")
1937 (set_attr "mode" "SI")])
1939 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
1940 ;; errata MD(0), which says that dmultu does not always produce the
1942 (define_insn_and_split "<su>muldi3_highpart"
1943 [(set (match_operand:DI 0 "register_operand" "=d")
1946 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
1947 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
1949 (clobber (match_scratch:DI 3 "=l"))]
1950 "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1951 { return TARGET_FIX_R4000 ? "dmult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
1952 "&& reload_completed && !TARGET_FIX_R4000"
1957 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
1958 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
1959 emit_insn (gen_mfhidi_ti (operands[0], hilo));
1962 [(set_attr "type" "imul")
1963 (set_attr "mode" "DI")
1964 (set_attr "length" "8")])
1966 (define_expand "<u>mulditi3"
1967 [(set (match_operand:TI 0 "register_operand")
1968 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
1969 (any_extend:TI (match_operand:DI 2 "register_operand"))))]
1970 "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1972 if (TARGET_FIX_R4000)
1973 emit_insn (gen_<u>mulditi3_r4000 (operands[0], operands[1], operands[2]));
1975 emit_insn (gen_<u>mulditi3_internal (operands[0], operands[1],
1980 (define_insn "<u>mulditi3_internal"
1981 [(set (match_operand:TI 0 "register_operand" "=x")
1982 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
1983 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))]
1985 && !TARGET_FIX_R4000
1986 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1988 [(set_attr "type" "imul")
1989 (set_attr "mode" "DI")])
1991 (define_insn "<u>mulditi3_r4000"
1992 [(set (match_operand:TI 0 "register_operand" "=d")
1993 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
1994 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))
1995 (clobber (match_scratch:TI 3 "=x"))]
1998 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1999 "dmult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
2000 [(set_attr "type" "imul")
2001 (set_attr "mode" "DI")
2002 (set_attr "length" "12")])
2004 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
2005 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
2007 (define_insn "madsi"
2008 [(set (match_operand:SI 0 "register_operand" "+l")
2009 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
2010 (match_operand:SI 2 "register_operand" "d"))
2014 [(set_attr "type" "imadd")
2015 (set_attr "mode" "SI")])
2017 (define_insn "<u>maddsidi4"
2018 [(set (match_operand:DI 0 "register_operand" "=ka")
2020 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2021 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2022 (match_operand:DI 3 "register_operand" "0")))]
2023 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)
2027 return "mad<u>\t%1,%2";
2028 else if (ISA_HAS_DSPR2)
2029 return "madd<u>\t%q0,%1,%2";
2030 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
2031 return "madd<u>\t%1,%2";
2033 /* See comment in *macc. */
2034 return "%[macc<u>\t%@,%1,%2%]";
2036 [(set_attr "type" "imadd")
2037 (set_attr "mode" "SI")])
2039 ;; Floating point multiply accumulate instructions.
2041 (define_insn "*madd4<mode>"
2042 [(set (match_operand:ANYF 0 "register_operand" "=f")
2043 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2044 (match_operand:ANYF 2 "register_operand" "f"))
2045 (match_operand:ANYF 3 "register_operand" "f")))]
2046 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2047 "madd.<fmt>\t%0,%3,%1,%2"
2048 [(set_attr "type" "fmadd")
2049 (set_attr "mode" "<UNITMODE>")])
2051 (define_insn "*madd3<mode>"
2052 [(set (match_operand:ANYF 0 "register_operand" "=f")
2053 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2054 (match_operand:ANYF 2 "register_operand" "f"))
2055 (match_operand:ANYF 3 "register_operand" "0")))]
2056 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2057 "madd.<fmt>\t%0,%1,%2"
2058 [(set_attr "type" "fmadd")
2059 (set_attr "mode" "<UNITMODE>")])
2061 (define_insn "*msub4<mode>"
2062 [(set (match_operand:ANYF 0 "register_operand" "=f")
2063 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2064 (match_operand:ANYF 2 "register_operand" "f"))
2065 (match_operand:ANYF 3 "register_operand" "f")))]
2066 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2067 "msub.<fmt>\t%0,%3,%1,%2"
2068 [(set_attr "type" "fmadd")
2069 (set_attr "mode" "<UNITMODE>")])
2071 (define_insn "*msub3<mode>"
2072 [(set (match_operand:ANYF 0 "register_operand" "=f")
2073 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2074 (match_operand:ANYF 2 "register_operand" "f"))
2075 (match_operand:ANYF 3 "register_operand" "0")))]
2076 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2077 "msub.<fmt>\t%0,%1,%2"
2078 [(set_attr "type" "fmadd")
2079 (set_attr "mode" "<UNITMODE>")])
2081 (define_insn "*nmadd4<mode>"
2082 [(set (match_operand:ANYF 0 "register_operand" "=f")
2083 (neg:ANYF (plus:ANYF
2084 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2085 (match_operand:ANYF 2 "register_operand" "f"))
2086 (match_operand:ANYF 3 "register_operand" "f"))))]
2087 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2088 && TARGET_FUSED_MADD
2089 && HONOR_SIGNED_ZEROS (<MODE>mode)
2090 && !HONOR_NANS (<MODE>mode)"
2091 "nmadd.<fmt>\t%0,%3,%1,%2"
2092 [(set_attr "type" "fmadd")
2093 (set_attr "mode" "<UNITMODE>")])
2095 (define_insn "*nmadd3<mode>"
2096 [(set (match_operand:ANYF 0 "register_operand" "=f")
2097 (neg:ANYF (plus:ANYF
2098 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2099 (match_operand:ANYF 2 "register_operand" "f"))
2100 (match_operand:ANYF 3 "register_operand" "0"))))]
2101 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2102 && TARGET_FUSED_MADD
2103 && HONOR_SIGNED_ZEROS (<MODE>mode)
2104 && !HONOR_NANS (<MODE>mode)"
2105 "nmadd.<fmt>\t%0,%1,%2"
2106 [(set_attr "type" "fmadd")
2107 (set_attr "mode" "<UNITMODE>")])
2109 (define_insn "*nmadd4<mode>_fastmath"
2110 [(set (match_operand:ANYF 0 "register_operand" "=f")
2112 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2113 (match_operand:ANYF 2 "register_operand" "f"))
2114 (match_operand:ANYF 3 "register_operand" "f")))]
2115 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2116 && TARGET_FUSED_MADD
2117 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2118 && !HONOR_NANS (<MODE>mode)"
2119 "nmadd.<fmt>\t%0,%3,%1,%2"
2120 [(set_attr "type" "fmadd")
2121 (set_attr "mode" "<UNITMODE>")])
2123 (define_insn "*nmadd3<mode>_fastmath"
2124 [(set (match_operand:ANYF 0 "register_operand" "=f")
2126 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2127 (match_operand:ANYF 2 "register_operand" "f"))
2128 (match_operand:ANYF 3 "register_operand" "0")))]
2129 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2130 && TARGET_FUSED_MADD
2131 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2132 && !HONOR_NANS (<MODE>mode)"
2133 "nmadd.<fmt>\t%0,%1,%2"
2134 [(set_attr "type" "fmadd")
2135 (set_attr "mode" "<UNITMODE>")])
2137 (define_insn "*nmsub4<mode>"
2138 [(set (match_operand:ANYF 0 "register_operand" "=f")
2139 (neg:ANYF (minus:ANYF
2140 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2141 (match_operand:ANYF 3 "register_operand" "f"))
2142 (match_operand:ANYF 1 "register_operand" "f"))))]
2143 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2144 && TARGET_FUSED_MADD
2145 && HONOR_SIGNED_ZEROS (<MODE>mode)
2146 && !HONOR_NANS (<MODE>mode)"
2147 "nmsub.<fmt>\t%0,%1,%2,%3"
2148 [(set_attr "type" "fmadd")
2149 (set_attr "mode" "<UNITMODE>")])
2151 (define_insn "*nmsub3<mode>"
2152 [(set (match_operand:ANYF 0 "register_operand" "=f")
2153 (neg:ANYF (minus:ANYF
2154 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2155 (match_operand:ANYF 3 "register_operand" "f"))
2156 (match_operand:ANYF 1 "register_operand" "0"))))]
2157 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2158 && TARGET_FUSED_MADD
2159 && HONOR_SIGNED_ZEROS (<MODE>mode)
2160 && !HONOR_NANS (<MODE>mode)"
2161 "nmsub.<fmt>\t%0,%1,%2"
2162 [(set_attr "type" "fmadd")
2163 (set_attr "mode" "<UNITMODE>")])
2165 (define_insn "*nmsub4<mode>_fastmath"
2166 [(set (match_operand:ANYF 0 "register_operand" "=f")
2168 (match_operand:ANYF 1 "register_operand" "f")
2169 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2170 (match_operand:ANYF 3 "register_operand" "f"))))]
2171 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2172 && TARGET_FUSED_MADD
2173 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2174 && !HONOR_NANS (<MODE>mode)"
2175 "nmsub.<fmt>\t%0,%1,%2,%3"
2176 [(set_attr "type" "fmadd")
2177 (set_attr "mode" "<UNITMODE>")])
2179 (define_insn "*nmsub3<mode>_fastmath"
2180 [(set (match_operand:ANYF 0 "register_operand" "=f")
2182 (match_operand:ANYF 1 "register_operand" "f")
2183 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2184 (match_operand:ANYF 3 "register_operand" "0"))))]
2185 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2186 && TARGET_FUSED_MADD
2187 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2188 && !HONOR_NANS (<MODE>mode)"
2189 "nmsub.<fmt>\t%0,%1,%2"
2190 [(set_attr "type" "fmadd")
2191 (set_attr "mode" "<UNITMODE>")])
2194 ;; ....................
2196 ;; DIVISION and REMAINDER
2198 ;; ....................
2201 (define_expand "div<mode>3"
2202 [(set (match_operand:ANYF 0 "register_operand")
2203 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
2204 (match_operand:ANYF 2 "register_operand")))]
2205 "<divide_condition>"
2207 if (const_1_operand (operands[1], <MODE>mode))
2208 if (!(<recip_condition> && flag_unsafe_math_optimizations))
2209 operands[1] = force_reg (<MODE>mode, operands[1]);
2212 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
2214 ;; If an mfc1 or dmfc1 happens to access the floating point register
2215 ;; file at the same time a long latency operation (div, sqrt, recip,
2216 ;; sqrt) iterates an intermediate result back through the floating
2217 ;; point register file bypass, then instead returning the correct
2218 ;; register value the mfc1 or dmfc1 operation returns the intermediate
2219 ;; result of the long latency operation.
2221 ;; The workaround is to insert an unconditional 'mov' from/to the
2222 ;; long latency op destination register.
2224 (define_insn "*div<mode>3"
2225 [(set (match_operand:ANYF 0 "register_operand" "=f")
2226 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
2227 (match_operand:ANYF 2 "register_operand" "f")))]
2228 "<divide_condition>"
2231 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
2233 return "div.<fmt>\t%0,%1,%2";
2235 [(set_attr "type" "fdiv")
2236 (set_attr "mode" "<UNITMODE>")
2237 (set (attr "length")
2238 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2242 (define_insn "*recip<mode>3"
2243 [(set (match_operand:ANYF 0 "register_operand" "=f")
2244 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2245 (match_operand:ANYF 2 "register_operand" "f")))]
2246 "<recip_condition> && flag_unsafe_math_optimizations"
2249 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2251 return "recip.<fmt>\t%0,%2";
2253 [(set_attr "type" "frdiv")
2254 (set_attr "mode" "<UNITMODE>")
2255 (set (attr "length")
2256 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2260 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
2261 ;; with negative operands. We use special libgcc functions instead.
2262 (define_insn_and_split "divmod<mode>4"
2263 [(set (match_operand:GPR 0 "register_operand" "=l")
2264 (div:GPR (match_operand:GPR 1 "register_operand" "d")
2265 (match_operand:GPR 2 "register_operand" "d")))
2266 (set (match_operand:GPR 3 "register_operand" "=d")
2267 (mod:GPR (match_dup 1)
2269 "!TARGET_FIX_VR4120"
2271 "&& reload_completed"
2278 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2279 emit_insn (gen_divmod<mode>4_hilo_ti (hilo, operands[1], operands[2]));
2280 emit_insn (gen_mfhi<mode>_ti (operands[3], hilo));
2284 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2285 emit_insn (gen_divmod<mode>4_hilo_di (hilo, operands[1], operands[2]));
2286 emit_insn (gen_mfhi<mode>_di (operands[3], hilo));
2290 [(set_attr "type" "idiv")
2291 (set_attr "mode" "<MODE>")
2292 (set_attr "length" "8")])
2294 (define_insn_and_split "udivmod<mode>4"
2295 [(set (match_operand:GPR 0 "register_operand" "=l")
2296 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
2297 (match_operand:GPR 2 "register_operand" "d")))
2298 (set (match_operand:GPR 3 "register_operand" "=d")
2299 (umod:GPR (match_dup 1)
2310 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2311 emit_insn (gen_udivmod<mode>4_hilo_ti (hilo, operands[1], operands[2]));
2312 emit_insn (gen_mfhi<mode>_ti (operands[3], hilo));
2316 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2317 emit_insn (gen_udivmod<mode>4_hilo_di (hilo, operands[1], operands[2]));
2318 emit_insn (gen_mfhi<mode>_di (operands[3], hilo));
2322 [(set_attr "type" "idiv")
2323 (set_attr "mode" "<MODE>")
2324 (set_attr "length" "8")])
2326 (define_insn "<u>divmod<GPR:mode>4_hilo_<HILO:mode>"
2327 [(set (match_operand:HILO 0 "register_operand" "=x")
2329 [(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
2330 (match_operand:GPR 2 "register_operand" "d"))]
2333 { return mips_output_division ("<GPR:d>div<u>\t%.,%1,%2", operands); }
2334 [(set_attr "type" "idiv")
2335 (set_attr "mode" "<GPR:MODE>")])
2338 ;; ....................
2342 ;; ....................
2344 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
2345 ;; "*div[sd]f3" comment for details).
2347 (define_insn "sqrt<mode>2"
2348 [(set (match_operand:ANYF 0 "register_operand" "=f")
2349 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2353 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
2355 return "sqrt.<fmt>\t%0,%1";
2357 [(set_attr "type" "fsqrt")
2358 (set_attr "mode" "<UNITMODE>")
2359 (set (attr "length")
2360 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2364 (define_insn "*rsqrt<mode>a"
2365 [(set (match_operand:ANYF 0 "register_operand" "=f")
2366 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2367 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
2368 "<recip_condition> && flag_unsafe_math_optimizations"
2371 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2373 return "rsqrt.<fmt>\t%0,%2";
2375 [(set_attr "type" "frsqrt")
2376 (set_attr "mode" "<UNITMODE>")
2377 (set (attr "length")
2378 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2382 (define_insn "*rsqrt<mode>b"
2383 [(set (match_operand:ANYF 0 "register_operand" "=f")
2384 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2385 (match_operand:ANYF 2 "register_operand" "f"))))]
2386 "<recip_condition> && flag_unsafe_math_optimizations"
2389 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2391 return "rsqrt.<fmt>\t%0,%2";
2393 [(set_attr "type" "frsqrt")
2394 (set_attr "mode" "<UNITMODE>")
2395 (set (attr "length")
2396 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2401 ;; ....................
2405 ;; ....................
2407 ;; Do not use the integer abs macro instruction, since that signals an
2408 ;; exception on -2147483648 (sigh).
2410 ;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
2411 ;; invalid; it does not clear their sign bits. We therefore can't use
2412 ;; abs.fmt if the signs of NaNs matter.
2414 (define_insn "abs<mode>2"
2415 [(set (match_operand:ANYF 0 "register_operand" "=f")
2416 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2417 "!HONOR_NANS (<MODE>mode)"
2419 [(set_attr "type" "fabs")
2420 (set_attr "mode" "<UNITMODE>")])
2423 ;; ...................
2425 ;; Count leading zeroes.
2427 ;; ...................
2430 (define_insn "clz<mode>2"
2431 [(set (match_operand:GPR 0 "register_operand" "=d")
2432 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
2435 [(set_attr "type" "clz")
2436 (set_attr "mode" "<MODE>")])
2439 ;; ...................
2441 ;; Count number of set bits.
2443 ;; ...................
2446 (define_insn "popcount<mode>2"
2447 [(set (match_operand:GPR 0 "register_operand" "=d")
2448 (popcount:GPR (match_operand:GPR 1 "register_operand" "d")))]
2451 [(set_attr "type" "pop")
2452 (set_attr "mode" "<MODE>")])
2455 ;; ....................
2457 ;; NEGATION and ONE'S COMPLEMENT
2459 ;; ....................
2461 (define_insn "negsi2"
2462 [(set (match_operand:SI 0 "register_operand" "=d")
2463 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2467 return "neg\t%0,%1";
2469 return "subu\t%0,%.,%1";
2471 [(set_attr "type" "arith")
2472 (set_attr "mode" "SI")])
2474 (define_insn "negdi2"
2475 [(set (match_operand:DI 0 "register_operand" "=d")
2476 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2477 "TARGET_64BIT && !TARGET_MIPS16"
2479 [(set_attr "type" "arith")
2480 (set_attr "mode" "DI")])
2482 ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
2483 ;; invalid; it does not flip their sign bit. We therefore can't use
2484 ;; neg.fmt if the signs of NaNs matter.
2486 (define_insn "neg<mode>2"
2487 [(set (match_operand:ANYF 0 "register_operand" "=f")
2488 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2489 "!HONOR_NANS (<MODE>mode)"
2491 [(set_attr "type" "fneg")
2492 (set_attr "mode" "<UNITMODE>")])
2494 (define_insn "one_cmpl<mode>2"
2495 [(set (match_operand:GPR 0 "register_operand" "=d")
2496 (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
2500 return "not\t%0,%1";
2502 return "nor\t%0,%.,%1";
2504 [(set_attr "type" "logical")
2505 (set_attr "mode" "<MODE>")])
2508 ;; ....................
2512 ;; ....................
2515 ;; Many of these instructions use trivial define_expands, because we
2516 ;; want to use a different set of constraints when TARGET_MIPS16.
2518 (define_expand "and<mode>3"
2519 [(set (match_operand:GPR 0 "register_operand")
2520 (and:GPR (match_operand:GPR 1 "register_operand")
2521 (match_operand:GPR 2 "uns_arith_operand")))]
2525 operands[2] = force_reg (<MODE>mode, operands[2]);
2528 (define_insn "*and<mode>3"
2529 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2530 (and:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2531 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2536 [(set_attr "type" "logical")
2537 (set_attr "mode" "<MODE>")])
2539 (define_insn "*and<mode>3_mips16"
2540 [(set (match_operand:GPR 0 "register_operand" "=d")
2541 (and:GPR (match_operand:GPR 1 "register_operand" "%0")
2542 (match_operand:GPR 2 "register_operand" "d")))]
2545 [(set_attr "type" "logical")
2546 (set_attr "mode" "<MODE>")])
2548 (define_expand "ior<mode>3"
2549 [(set (match_operand:GPR 0 "register_operand")
2550 (ior:GPR (match_operand:GPR 1 "register_operand")
2551 (match_operand:GPR 2 "uns_arith_operand")))]
2555 operands[2] = force_reg (<MODE>mode, operands[2]);
2558 (define_insn "*ior<mode>3"
2559 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2560 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2561 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2566 [(set_attr "type" "logical")
2567 (set_attr "mode" "<MODE>")])
2569 (define_insn "*ior<mode>3_mips16"
2570 [(set (match_operand:GPR 0 "register_operand" "=d")
2571 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2572 (match_operand:GPR 2 "register_operand" "d")))]
2575 [(set_attr "type" "logical")
2576 (set_attr "mode" "<MODE>")])
2578 (define_expand "xor<mode>3"
2579 [(set (match_operand:GPR 0 "register_operand")
2580 (xor:GPR (match_operand:GPR 1 "register_operand")
2581 (match_operand:GPR 2 "uns_arith_operand")))]
2586 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2587 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2588 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2593 [(set_attr "type" "logical")
2594 (set_attr "mode" "<MODE>")])
2597 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2598 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2599 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
2605 [(set_attr "type" "logical,arith,arith")
2606 (set_attr "mode" "<MODE>")
2607 (set_attr_alternative "length"
2609 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2614 (define_insn "*nor<mode>3"
2615 [(set (match_operand:GPR 0 "register_operand" "=d")
2616 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2617 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2620 [(set_attr "type" "logical")
2621 (set_attr "mode" "<MODE>")])
2624 ;; ....................
2628 ;; ....................
2632 (define_insn "truncdfsf2"
2633 [(set (match_operand:SF 0 "register_operand" "=f")
2634 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2635 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2637 [(set_attr "type" "fcvt")
2638 (set_attr "cnv_mode" "D2S")
2639 (set_attr "mode" "SF")])
2641 ;; Integer truncation patterns. Truncating SImode values to smaller
2642 ;; modes is a no-op, as it is for most other GCC ports. Truncating
2643 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
2644 ;; need to make sure that the lower 32 bits are properly sign-extended
2645 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
2646 ;; smaller than SImode is equivalent to two separate truncations:
2649 ;; DI ---> HI == DI ---> SI ---> HI
2650 ;; DI ---> QI == DI ---> SI ---> QI
2652 ;; Step A needs a real instruction but step B does not.
2654 (define_insn "truncdisi2"
2655 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
2656 (truncate:SI (match_operand:DI 1 "register_operand" "d,d")))]
2661 [(set_attr "move_type" "sll0,store")
2662 (set_attr "mode" "SI")])
2664 (define_insn "truncdihi2"
2665 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m")
2666 (truncate:HI (match_operand:DI 1 "register_operand" "d,d")))]
2671 [(set_attr "move_type" "sll0,store")
2672 (set_attr "mode" "SI")])
2674 (define_insn "truncdiqi2"
2675 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m")
2676 (truncate:QI (match_operand:DI 1 "register_operand" "d,d")))]
2681 [(set_attr "move_type" "sll0,store")
2682 (set_attr "mode" "SI")])
2684 ;; Combiner patterns to optimize shift/truncate combinations.
2687 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2689 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2690 (match_operand:DI 2 "const_arith_operand" ""))))]
2691 "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) >= 32"
2693 [(set_attr "type" "shift")
2694 (set_attr "mode" "SI")])
2697 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2699 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2701 "TARGET_64BIT && !TARGET_MIPS16"
2703 [(set_attr "type" "shift")
2704 (set_attr "mode" "SI")])
2707 ;; Combiner patterns for truncate/sign_extend combinations. The SI versions
2708 ;; use the shift/truncate patterns above.
2710 (define_insn_and_split "*extenddi_truncate<mode>"
2711 [(set (match_operand:DI 0 "register_operand" "=d")
2713 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
2714 "TARGET_64BIT && !TARGET_MIPS16"
2716 "&& reload_completed"
2718 (ashift:DI (match_dup 1)
2721 (ashiftrt:DI (match_dup 2)
2724 operands[2] = gen_lowpart (DImode, operands[0]);
2725 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
2728 (define_insn_and_split "*extendsi_truncate<mode>"
2729 [(set (match_operand:SI 0 "register_operand" "=d")
2731 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
2732 "TARGET_64BIT && !TARGET_MIPS16"
2734 "&& reload_completed"
2736 (ashift:DI (match_dup 1)
2739 (truncate:SI (ashiftrt:DI (match_dup 2)
2742 operands[2] = gen_lowpart (DImode, operands[0]);
2743 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
2746 ;; Combiner patterns to optimize truncate/zero_extend combinations.
2748 (define_insn "*zero_extend<mode>_trunchi"
2749 [(set (match_operand:GPR 0 "register_operand" "=d")
2751 (truncate:HI (match_operand:DI 1 "register_operand" "d"))))]
2752 "TARGET_64BIT && !TARGET_MIPS16"
2753 "andi\t%0,%1,0xffff"
2754 [(set_attr "type" "logical")
2755 (set_attr "mode" "<MODE>")])
2757 (define_insn "*zero_extend<mode>_truncqi"
2758 [(set (match_operand:GPR 0 "register_operand" "=d")
2760 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2761 "TARGET_64BIT && !TARGET_MIPS16"
2763 [(set_attr "type" "logical")
2764 (set_attr "mode" "<MODE>")])
2767 [(set (match_operand:HI 0 "register_operand" "=d")
2769 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2770 "TARGET_64BIT && !TARGET_MIPS16"
2772 [(set_attr "type" "logical")
2773 (set_attr "mode" "HI")])
2776 ;; ....................
2780 ;; ....................
2784 (define_insn_and_split "zero_extendsidi2"
2785 [(set (match_operand:DI 0 "register_operand" "=d,d")
2786 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2791 "&& reload_completed && REG_P (operands[1])"
2793 (ashift:DI (match_dup 1) (const_int 32)))
2795 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2796 { operands[1] = gen_lowpart (DImode, operands[1]); }
2797 [(set_attr "move_type" "shift_shift,load")
2798 (set_attr "mode" "DI")])
2800 ;; Combine is not allowed to convert this insn into a zero_extendsidi2
2801 ;; because of TRULY_NOOP_TRUNCATION.
2803 (define_insn_and_split "*clear_upper32"
2804 [(set (match_operand:DI 0 "register_operand" "=d,d")
2805 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,W")
2806 (const_int 4294967295)))]
2809 if (which_alternative == 0)
2812 operands[1] = gen_lowpart (SImode, operands[1]);
2813 return "lwu\t%0,%1";
2815 "&& reload_completed && REG_P (operands[1])"
2817 (ashift:DI (match_dup 1) (const_int 32)))
2819 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2821 [(set_attr "move_type" "shift_shift,load")
2822 (set_attr "mode" "DI")])
2824 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
2825 [(set (match_operand:GPR 0 "register_operand")
2826 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2829 if (TARGET_MIPS16 && !GENERATE_MIPS16E
2830 && !memory_operand (operands[1], <SHORT:MODE>mode))
2832 emit_insn (gen_and<GPR:mode>3 (operands[0],
2833 gen_lowpart (<GPR:MODE>mode, operands[1]),
2834 force_reg (<GPR:MODE>mode,
2835 GEN_INT (<SHORT:mask>))));
2840 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
2841 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2843 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2846 andi\t%0,%1,<SHORT:mask>
2847 l<SHORT:size>u\t%0,%1"
2848 [(set_attr "move_type" "andi,load")
2849 (set_attr "mode" "<GPR:MODE>")])
2851 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
2852 [(set (match_operand:GPR 0 "register_operand" "=d")
2853 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
2855 "ze<SHORT:size>\t%0"
2856 ;; This instruction is effectively a special encoding of ANDI.
2857 [(set_attr "move_type" "andi")
2858 (set_attr "mode" "<GPR:MODE>")])
2860 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
2861 [(set (match_operand:GPR 0 "register_operand" "=d")
2862 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
2864 "l<SHORT:size>u\t%0,%1"
2865 [(set_attr "move_type" "load")
2866 (set_attr "mode" "<GPR:MODE>")])
2868 (define_expand "zero_extendqihi2"
2869 [(set (match_operand:HI 0 "register_operand")
2870 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2873 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
2875 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
2881 (define_insn "*zero_extendqihi2"
2882 [(set (match_operand:HI 0 "register_operand" "=d,d")
2883 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2888 [(set_attr "move_type" "andi,load")
2889 (set_attr "mode" "HI")])
2891 (define_insn "*zero_extendqihi2_mips16"
2892 [(set (match_operand:HI 0 "register_operand" "=d")
2893 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2896 [(set_attr "move_type" "load")
2897 (set_attr "mode" "HI")])
2900 ;; ....................
2904 ;; ....................
2907 ;; Those for integer source operand are ordered widest source type first.
2909 ;; When TARGET_64BIT, all SImode integer registers should already be in
2910 ;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can
2911 ;; therefore get rid of register->register instructions if we constrain
2912 ;; the source to be in the same register as the destination.
2914 ;; The register alternative has type "arith" so that the pre-reload
2915 ;; scheduler will treat it as a move. This reflects what happens if
2916 ;; the register alternative needs a reload.
2917 (define_insn_and_split "extendsidi2"
2918 [(set (match_operand:DI 0 "register_operand" "=d,d")
2919 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
2924 "&& reload_completed && register_operand (operands[1], VOIDmode)"
2927 emit_note (NOTE_INSN_DELETED);
2930 [(set_attr "move_type" "move,load")
2931 (set_attr "mode" "DI")])
2933 (define_expand "extend<SHORT:mode><GPR:mode>2"
2934 [(set (match_operand:GPR 0 "register_operand")
2935 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2938 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
2939 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2940 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
2944 l<SHORT:size>\t%0,%1"
2945 [(set_attr "move_type" "signext,load")
2946 (set_attr "mode" "<GPR:MODE>")])
2948 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
2949 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2951 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2952 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
2955 l<SHORT:size>\t%0,%1"
2956 "&& reload_completed && REG_P (operands[1])"
2957 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
2958 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
2960 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
2961 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
2962 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
2964 [(set_attr "move_type" "shift_shift,load")
2965 (set_attr "mode" "<GPR:MODE>")])
2967 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
2968 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2970 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2973 se<SHORT:size>\t%0,%1
2974 l<SHORT:size>\t%0,%1"
2975 [(set_attr "move_type" "signext,load")
2976 (set_attr "mode" "<GPR:MODE>")])
2978 (define_expand "extendqihi2"
2979 [(set (match_operand:HI 0 "register_operand")
2980 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2983 (define_insn "*extendqihi2_mips16e"
2984 [(set (match_operand:HI 0 "register_operand" "=d,d")
2985 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
2990 [(set_attr "move_type" "signext,load")
2991 (set_attr "mode" "SI")])
2993 (define_insn_and_split "*extendqihi2"
2994 [(set (match_operand:HI 0 "register_operand" "=d,d")
2996 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2997 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3001 "&& reload_completed && REG_P (operands[1])"
3002 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
3003 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
3005 operands[0] = gen_lowpart (SImode, operands[0]);
3006 operands[1] = gen_lowpart (SImode, operands[1]);
3007 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
3008 - GET_MODE_BITSIZE (QImode));
3010 [(set_attr "move_type" "shift_shift,load")
3011 (set_attr "mode" "SI")])
3013 (define_insn "*extendqihi2_seb"
3014 [(set (match_operand:HI 0 "register_operand" "=d,d")
3016 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3021 [(set_attr "move_type" "signext,load")
3022 (set_attr "mode" "SI")])
3024 (define_insn "extendsfdf2"
3025 [(set (match_operand:DF 0 "register_operand" "=f")
3026 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
3027 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3029 [(set_attr "type" "fcvt")
3030 (set_attr "cnv_mode" "S2D")
3031 (set_attr "mode" "DF")])
3034 ;; ....................
3038 ;; ....................
3040 (define_expand "fix_truncdfsi2"
3041 [(set (match_operand:SI 0 "register_operand")
3042 (fix:SI (match_operand:DF 1 "register_operand")))]
3043 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3045 if (!ISA_HAS_TRUNC_W)
3047 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
3052 (define_insn "fix_truncdfsi2_insn"
3053 [(set (match_operand:SI 0 "register_operand" "=f")
3054 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
3055 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
3057 [(set_attr "type" "fcvt")
3058 (set_attr "mode" "DF")
3059 (set_attr "cnv_mode" "D2I")])
3061 (define_insn "fix_truncdfsi2_macro"
3062 [(set (match_operand:SI 0 "register_operand" "=f")
3063 (fix:SI (match_operand:DF 1 "register_operand" "f")))
3064 (clobber (match_scratch:DF 2 "=d"))]
3065 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
3068 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
3070 return "trunc.w.d %0,%1,%2";
3072 [(set_attr "type" "fcvt")
3073 (set_attr "mode" "DF")
3074 (set_attr "cnv_mode" "D2I")
3075 (set_attr "length" "36")])
3077 (define_expand "fix_truncsfsi2"
3078 [(set (match_operand:SI 0 "register_operand")
3079 (fix:SI (match_operand:SF 1 "register_operand")))]
3082 if (!ISA_HAS_TRUNC_W)
3084 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
3089 (define_insn "fix_truncsfsi2_insn"
3090 [(set (match_operand:SI 0 "register_operand" "=f")
3091 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
3092 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
3094 [(set_attr "type" "fcvt")
3095 (set_attr "mode" "SF")
3096 (set_attr "cnv_mode" "S2I")])
3098 (define_insn "fix_truncsfsi2_macro"
3099 [(set (match_operand:SI 0 "register_operand" "=f")
3100 (fix:SI (match_operand:SF 1 "register_operand" "f")))
3101 (clobber (match_scratch:SF 2 "=d"))]
3102 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
3105 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
3107 return "trunc.w.s %0,%1,%2";
3109 [(set_attr "type" "fcvt")
3110 (set_attr "mode" "SF")
3111 (set_attr "cnv_mode" "S2I")
3112 (set_attr "length" "36")])
3115 (define_insn "fix_truncdfdi2"
3116 [(set (match_operand:DI 0 "register_operand" "=f")
3117 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
3118 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3120 [(set_attr "type" "fcvt")
3121 (set_attr "mode" "DF")
3122 (set_attr "cnv_mode" "D2I")])
3125 (define_insn "fix_truncsfdi2"
3126 [(set (match_operand:DI 0 "register_operand" "=f")
3127 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
3128 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3130 [(set_attr "type" "fcvt")
3131 (set_attr "mode" "SF")
3132 (set_attr "cnv_mode" "S2I")])
3135 (define_insn "floatsidf2"
3136 [(set (match_operand:DF 0 "register_operand" "=f")
3137 (float:DF (match_operand:SI 1 "register_operand" "f")))]
3138 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3140 [(set_attr "type" "fcvt")
3141 (set_attr "mode" "DF")
3142 (set_attr "cnv_mode" "I2D")])
3145 (define_insn "floatdidf2"
3146 [(set (match_operand:DF 0 "register_operand" "=f")
3147 (float:DF (match_operand:DI 1 "register_operand" "f")))]
3148 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3150 [(set_attr "type" "fcvt")
3151 (set_attr "mode" "DF")
3152 (set_attr "cnv_mode" "I2D")])
3155 (define_insn "floatsisf2"
3156 [(set (match_operand:SF 0 "register_operand" "=f")
3157 (float:SF (match_operand:SI 1 "register_operand" "f")))]
3160 [(set_attr "type" "fcvt")
3161 (set_attr "mode" "SF")
3162 (set_attr "cnv_mode" "I2S")])
3165 (define_insn "floatdisf2"
3166 [(set (match_operand:SF 0 "register_operand" "=f")
3167 (float:SF (match_operand:DI 1 "register_operand" "f")))]
3168 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3170 [(set_attr "type" "fcvt")
3171 (set_attr "mode" "SF")
3172 (set_attr "cnv_mode" "I2S")])
3175 (define_expand "fixuns_truncdfsi2"
3176 [(set (match_operand:SI 0 "register_operand")
3177 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
3178 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3180 rtx reg1 = gen_reg_rtx (DFmode);
3181 rtx reg2 = gen_reg_rtx (DFmode);
3182 rtx reg3 = gen_reg_rtx (SImode);
3183 rtx label1 = gen_label_rtx ();
3184 rtx label2 = gen_label_rtx ();
3185 REAL_VALUE_TYPE offset;
3187 real_2expN (&offset, 31, DFmode);
3189 if (reg1) /* Turn off complaints about unreached code. */
3191 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3192 do_pending_stack_adjust ();
3194 emit_insn (gen_cmpdf (operands[1], reg1));
3195 emit_jump_insn (gen_bge (label1));
3197 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
3198 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3199 gen_rtx_LABEL_REF (VOIDmode, label2)));
3202 emit_label (label1);
3203 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3204 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3205 (BITMASK_HIGH, SImode)));
3207 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
3208 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3210 emit_label (label2);
3212 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3213 fields, and can't be used for REG_NOTES anyway). */
3214 emit_use (stack_pointer_rtx);
3220 (define_expand "fixuns_truncdfdi2"
3221 [(set (match_operand:DI 0 "register_operand")
3222 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
3223 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3225 rtx reg1 = gen_reg_rtx (DFmode);
3226 rtx reg2 = gen_reg_rtx (DFmode);
3227 rtx reg3 = gen_reg_rtx (DImode);
3228 rtx label1 = gen_label_rtx ();
3229 rtx label2 = gen_label_rtx ();
3230 REAL_VALUE_TYPE offset;
3232 real_2expN (&offset, 63, DFmode);
3234 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3235 do_pending_stack_adjust ();
3237 emit_insn (gen_cmpdf (operands[1], reg1));
3238 emit_jump_insn (gen_bge (label1));
3240 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
3241 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3242 gen_rtx_LABEL_REF (VOIDmode, label2)));
3245 emit_label (label1);
3246 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3247 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3248 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3250 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
3251 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3253 emit_label (label2);
3255 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3256 fields, and can't be used for REG_NOTES anyway). */
3257 emit_use (stack_pointer_rtx);
3262 (define_expand "fixuns_truncsfsi2"
3263 [(set (match_operand:SI 0 "register_operand")
3264 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
3267 rtx reg1 = gen_reg_rtx (SFmode);
3268 rtx reg2 = gen_reg_rtx (SFmode);
3269 rtx reg3 = gen_reg_rtx (SImode);
3270 rtx label1 = gen_label_rtx ();
3271 rtx label2 = gen_label_rtx ();
3272 REAL_VALUE_TYPE offset;
3274 real_2expN (&offset, 31, SFmode);
3276 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3277 do_pending_stack_adjust ();
3279 emit_insn (gen_cmpsf (operands[1], reg1));
3280 emit_jump_insn (gen_bge (label1));
3282 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
3283 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3284 gen_rtx_LABEL_REF (VOIDmode, label2)));
3287 emit_label (label1);
3288 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3289 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3290 (BITMASK_HIGH, SImode)));
3292 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
3293 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3295 emit_label (label2);
3297 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3298 fields, and can't be used for REG_NOTES anyway). */
3299 emit_use (stack_pointer_rtx);
3304 (define_expand "fixuns_truncsfdi2"
3305 [(set (match_operand:DI 0 "register_operand")
3306 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
3307 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3309 rtx reg1 = gen_reg_rtx (SFmode);
3310 rtx reg2 = gen_reg_rtx (SFmode);
3311 rtx reg3 = gen_reg_rtx (DImode);
3312 rtx label1 = gen_label_rtx ();
3313 rtx label2 = gen_label_rtx ();
3314 REAL_VALUE_TYPE offset;
3316 real_2expN (&offset, 63, SFmode);
3318 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3319 do_pending_stack_adjust ();
3321 emit_insn (gen_cmpsf (operands[1], reg1));
3322 emit_jump_insn (gen_bge (label1));
3324 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
3325 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3326 gen_rtx_LABEL_REF (VOIDmode, label2)));
3329 emit_label (label1);
3330 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3331 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3332 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3334 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
3335 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3337 emit_label (label2);
3339 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3340 fields, and can't be used for REG_NOTES anyway). */
3341 emit_use (stack_pointer_rtx);
3346 ;; ....................
3350 ;; ....................
3352 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
3354 (define_expand "extv"
3355 [(set (match_operand 0 "register_operand")
3356 (sign_extract (match_operand:QI 1 "memory_operand")
3357 (match_operand 2 "immediate_operand")
3358 (match_operand 3 "immediate_operand")))]
3361 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3362 INTVAL (operands[2]),
3363 INTVAL (operands[3])))
3369 (define_expand "extzv"
3370 [(set (match_operand 0 "register_operand")
3371 (zero_extract (match_operand 1 "nonimmediate_operand")
3372 (match_operand 2 "immediate_operand")
3373 (match_operand 3 "immediate_operand")))]
3376 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3377 INTVAL (operands[2]),
3378 INTVAL (operands[3])))
3380 else if (mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3381 INTVAL (operands[3])))
3383 if (GET_MODE (operands[0]) == DImode)
3384 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
3387 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
3395 (define_insn "extzv<mode>"
3396 [(set (match_operand:GPR 0 "register_operand" "=d")
3397 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3398 (match_operand:SI 2 "immediate_operand" "I")
3399 (match_operand:SI 3 "immediate_operand" "I")))]
3400 "mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3401 INTVAL (operands[3]))"
3402 "<d>ext\t%0,%1,%3,%2"
3403 [(set_attr "type" "arith")
3404 (set_attr "mode" "<MODE>")])
3407 (define_expand "insv"
3408 [(set (zero_extract (match_operand 0 "nonimmediate_operand")
3409 (match_operand 1 "immediate_operand")
3410 (match_operand 2 "immediate_operand"))
3411 (match_operand 3 "reg_or_0_operand"))]
3414 if (mips_expand_ins_as_unaligned_store (operands[0], operands[3],
3415 INTVAL (operands[1]),
3416 INTVAL (operands[2])))
3418 else if (mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3419 INTVAL (operands[2])))
3421 if (GET_MODE (operands[0]) == DImode)
3422 emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
3425 emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
3433 (define_insn "insv<mode>"
3434 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
3435 (match_operand:SI 1 "immediate_operand" "I")
3436 (match_operand:SI 2 "immediate_operand" "I"))
3437 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
3438 "mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3439 INTVAL (operands[2]))"
3440 "<d>ins\t%0,%z3,%2,%1"
3441 [(set_attr "type" "arith")
3442 (set_attr "mode" "<MODE>")])
3444 ;; Combiner pattern for cins (clear and insert bit field). We can
3445 ;; implement mask-and-shift-left operation with this. Note that if
3446 ;; the upper bit of the mask is set in an SImode operation, the mask
3447 ;; itself will be sign-extended. mask_low_and_shift_len will
3448 ;; therefore be greater than our threshold of 32.
3450 (define_insn "*cins<mode>"
3451 [(set (match_operand:GPR 0 "register_operand" "=d")
3453 (ashift:GPR (match_operand:GPR 1 "register_operand" "d")
3454 (match_operand:GPR 2 "const_int_operand" ""))
3455 (match_operand:GPR 3 "const_int_operand" "")))]
3457 && mask_low_and_shift_p (<MODE>mode, operands[3], operands[2], 32)"
3460 GEN_INT (mask_low_and_shift_len (<MODE>mode, operands[3], operands[2]));
3461 return "cins\t%0,%1,%2,%m3";
3463 [(set_attr "type" "shift")
3464 (set_attr "mode" "<MODE>")])
3466 ;; Unaligned word moves generated by the bit field patterns.
3468 ;; As far as the rtl is concerned, both the left-part and right-part
3469 ;; instructions can access the whole field. However, the real operand
3470 ;; refers to just the first or the last byte (depending on endianness).
3471 ;; We therefore use two memory operands to each instruction, one to
3472 ;; describe the rtl effect and one to use in the assembly output.
3474 ;; Operands 0 and 1 are the rtl-level target and source respectively.
3475 ;; This allows us to use the standard length calculations for the "load"
3476 ;; and "store" type attributes.
3478 (define_insn "mov_<load>l"
3479 [(set (match_operand:GPR 0 "register_operand" "=d")
3480 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3481 (match_operand:QI 2 "memory_operand" "m")]
3483 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3485 [(set_attr "move_type" "load")
3486 (set_attr "mode" "<MODE>")])
3488 (define_insn "mov_<load>r"
3489 [(set (match_operand:GPR 0 "register_operand" "=d")
3490 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3491 (match_operand:QI 2 "memory_operand" "m")
3492 (match_operand:GPR 3 "register_operand" "0")]
3493 UNSPEC_LOAD_RIGHT))]
3494 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3496 [(set_attr "move_type" "load")
3497 (set_attr "mode" "<MODE>")])
3499 (define_insn "mov_<store>l"
3500 [(set (match_operand:BLK 0 "memory_operand" "=m")
3501 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3502 (match_operand:QI 2 "memory_operand" "m")]
3503 UNSPEC_STORE_LEFT))]
3504 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3506 [(set_attr "move_type" "store")
3507 (set_attr "mode" "<MODE>")])
3509 (define_insn "mov_<store>r"
3510 [(set (match_operand:BLK 0 "memory_operand" "+m")
3511 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3512 (match_operand:QI 2 "memory_operand" "m")
3514 UNSPEC_STORE_RIGHT))]
3515 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3517 [(set_attr "move_type" "store")
3518 (set_attr "mode" "<MODE>")])
3520 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
3521 ;; The required value is:
3523 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
3525 ;; which translates to:
3527 ;; lui op0,%highest(op1)
3528 ;; daddiu op0,op0,%higher(op1)
3530 ;; daddiu op0,op0,%hi(op1)
3533 ;; The split is deferred until after flow2 to allow the peephole2 below
3535 (define_insn_and_split "*lea_high64"
3536 [(set (match_operand:DI 0 "register_operand" "=d")
3537 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))]
3538 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3540 "&& epilogue_completed"
3541 [(set (match_dup 0) (high:DI (match_dup 2)))
3542 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
3543 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
3544 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3545 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
3547 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3548 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
3550 [(set_attr "length" "20")])
3552 ;; Use a scratch register to reduce the latency of the above pattern
3553 ;; on superscalar machines. The optimized sequence is:
3555 ;; lui op1,%highest(op2)
3557 ;; daddiu op1,op1,%higher(op2)
3559 ;; daddu op1,op1,op0
3561 [(set (match_operand:DI 1 "d_operand")
3562 (high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
3563 (match_scratch:DI 0 "d")]
3564 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3565 [(set (match_dup 1) (high:DI (match_dup 3)))
3566 (set (match_dup 0) (high:DI (match_dup 4)))
3567 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
3568 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
3569 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
3571 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
3572 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
3575 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
3576 ;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine
3577 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
3578 ;; used once. We can then use the sequence:
3580 ;; lui op0,%highest(op1)
3582 ;; daddiu op0,op0,%higher(op1)
3583 ;; daddiu op2,op2,%lo(op1)
3585 ;; daddu op0,op0,op2
3587 ;; which takes 4 cycles on most superscalar targets.
3588 (define_insn_and_split "*lea64"
3589 [(set (match_operand:DI 0 "register_operand" "=d")
3590 (match_operand:DI 1 "absolute_symbolic_operand" ""))
3591 (clobber (match_scratch:DI 2 "=&d"))]
3592 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
3594 "&& reload_completed"
3595 [(set (match_dup 0) (high:DI (match_dup 3)))
3596 (set (match_dup 2) (high:DI (match_dup 4)))
3597 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3598 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
3599 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
3600 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
3602 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3603 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
3605 [(set_attr "length" "24")])
3607 ;; Split HIGHs into:
3612 ;; on MIPS16 targets.
3614 [(set (match_operand:SI 0 "d_operand")
3615 (high:SI (match_operand:SI 1 "absolute_symbolic_operand")))]
3616 "TARGET_MIPS16 && reload_completed"
3617 [(set (match_dup 0) (match_dup 2))
3618 (set (match_dup 0) (ashift:SI (match_dup 0) (const_int 16)))]
3620 operands[2] = mips_unspec_address (operands[1], SYMBOL_32_HIGH);
3623 ;; Insns to fetch a symbol from a big GOT.
3625 (define_insn_and_split "*xgot_hi<mode>"
3626 [(set (match_operand:P 0 "register_operand" "=d")
3627 (high:P (match_operand:P 1 "got_disp_operand" "")))]
3628 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3630 "&& reload_completed"
3631 [(set (match_dup 0) (high:P (match_dup 2)))
3632 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
3634 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3635 operands[3] = pic_offset_table_rtx;
3637 [(set_attr "got" "xgot_high")
3638 (set_attr "mode" "<MODE>")])
3640 (define_insn_and_split "*xgot_lo<mode>"
3641 [(set (match_operand:P 0 "register_operand" "=d")
3642 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3643 (match_operand:P 2 "got_disp_operand" "")))]
3644 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3646 "&& reload_completed"
3648 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
3649 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
3650 [(set_attr "got" "load")
3651 (set_attr "mode" "<MODE>")])
3653 ;; Insns to fetch a symbol from a normal GOT.
3655 (define_insn_and_split "*got_disp<mode>"
3656 [(set (match_operand:P 0 "register_operand" "=d")
3657 (match_operand:P 1 "got_disp_operand" ""))]
3658 "TARGET_EXPLICIT_RELOCS && !mips_split_p[SYMBOL_GOT_DISP]"
3660 "&& reload_completed"
3661 [(set (match_dup 0) (match_dup 2))]
3662 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_DISP); }
3663 [(set_attr "got" "load")
3664 (set_attr "mode" "<MODE>")])
3666 ;; Insns for loading the "page" part of a page/ofst address from the GOT.
3668 (define_insn_and_split "*got_page<mode>"
3669 [(set (match_operand:P 0 "register_operand" "=d")
3670 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
3671 "TARGET_EXPLICIT_RELOCS && !mips_split_hi_p[SYMBOL_GOT_PAGE_OFST]"
3673 "&& reload_completed"
3674 [(set (match_dup 0) (match_dup 2))]
3675 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_PAGE); }
3676 [(set_attr "got" "load")
3677 (set_attr "mode" "<MODE>")])
3679 ;; Convenience expander that generates the rhs of a load_got<mode> insn.
3680 (define_expand "unspec_got<mode>"
3681 [(unspec:P [(match_operand:P 0)
3682 (match_operand:P 1)] UNSPEC_LOAD_GOT)])
3684 ;; Lower-level instructions for loading an address from the GOT.
3685 ;; We could use MEMs, but an unspec gives more optimization
3688 (define_insn "load_got<mode>"
3689 [(set (match_operand:P 0 "register_operand" "=d")
3690 (unspec:P [(match_operand:P 1 "register_operand" "d")
3691 (match_operand:P 2 "immediate_operand" "")]
3694 "<load>\t%0,%R2(%1)"
3695 [(set_attr "got" "load")
3696 (set_attr "mode" "<MODE>")])
3698 ;; Instructions for adding the low 16 bits of an address to a register.
3699 ;; Operand 2 is the address: mips_print_operand works out which relocation
3700 ;; should be applied.
3702 (define_insn "*low<mode>"
3703 [(set (match_operand:P 0 "register_operand" "=d")
3704 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3705 (match_operand:P 2 "immediate_operand" "")))]
3707 "<d>addiu\t%0,%1,%R2"
3708 [(set_attr "type" "arith")
3709 (set_attr "mode" "<MODE>")])
3711 (define_insn "*low<mode>_mips16"
3712 [(set (match_operand:P 0 "register_operand" "=d")
3713 (lo_sum:P (match_operand:P 1 "register_operand" "0")
3714 (match_operand:P 2 "immediate_operand" "")))]
3717 [(set_attr "type" "arith")
3718 (set_attr "mode" "<MODE>")
3719 (set_attr "extended_mips16" "yes")])
3721 ;; Expose MIPS16 uses of the global pointer after reload if the function
3722 ;; is responsible for setting up the register itself.
3724 [(set (match_operand:GPR 0 "d_operand")
3725 (const:GPR (unspec:GPR [(const_int 0)] UNSPEC_GP)))]
3726 "TARGET_MIPS16 && TARGET_USE_GOT && reload_completed"
3727 [(set (match_dup 0) (match_dup 1))]
3728 { operands[1] = pic_offset_table_rtx; })
3730 ;; Allow combine to split complex const_int load sequences, using operand 2
3731 ;; to store the intermediate results. See move_operand for details.
3733 [(set (match_operand:GPR 0 "register_operand")
3734 (match_operand:GPR 1 "splittable_const_int_operand"))
3735 (clobber (match_operand:GPR 2 "register_operand"))]
3739 mips_move_integer (operands[2], operands[0], INTVAL (operands[1]));
3743 ;; Likewise, for symbolic operands.
3745 [(set (match_operand:P 0 "register_operand")
3746 (match_operand:P 1))
3747 (clobber (match_operand:P 2 "register_operand"))]
3748 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
3749 [(set (match_dup 0) (match_dup 3))]
3751 mips_split_symbol (operands[2], operands[1],
3752 MAX_MACHINE_MODE, &operands[3]);
3755 ;; 64-bit integer moves
3757 ;; Unlike most other insns, the move insns can't be split with
3758 ;; different predicates, because register spilling and other parts of
3759 ;; the compiler, have memoized the insn number already.
3761 (define_expand "movdi"
3762 [(set (match_operand:DI 0 "")
3763 (match_operand:DI 1 ""))]
3766 if (mips_legitimize_move (DImode, operands[0], operands[1]))
3770 ;; For mips16, we need a special case to handle storing $31 into
3771 ;; memory, since we don't have a constraint to match $31. This
3772 ;; instruction can be generated by save_restore_insns.
3774 (define_insn "*mov<mode>_ra"
3775 [(set (match_operand:GPR 0 "stack_operand" "=m")
3779 [(set_attr "move_type" "store")
3780 (set_attr "mode" "<MODE>")])
3782 (define_insn "*movdi_32bit"
3783 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*d,*m,*B*C*D,*B*C*D,*d,*m")
3784 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*J*d,*m,*f,*f,*d,*m,*B*C*D,*B*C*D"))]
3785 "!TARGET_64BIT && !TARGET_MIPS16
3786 && (register_operand (operands[0], DImode)
3787 || reg_or_0_operand (operands[1], DImode))"
3788 { return mips_output_move (operands[0], operands[1]); }
3789 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo,mtc,fpload,mfc,fpstore,mtc,fpload,mfc,fpstore")
3790 (set_attr "mode" "DI")])
3792 (define_insn "*movdi_32bit_mips16"
3793 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
3794 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
3795 "!TARGET_64BIT && TARGET_MIPS16
3796 && (register_operand (operands[0], DImode)
3797 || register_operand (operands[1], DImode))"
3798 { return mips_output_move (operands[0], operands[1]); }
3799 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
3800 (set_attr "mode" "DI")])
3802 (define_insn "*movdi_64bit"
3803 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*a,*d,*B*C*D,*B*C*D,*d,*m")
3804 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
3805 "TARGET_64BIT && !TARGET_MIPS16
3806 && (register_operand (operands[0], DImode)
3807 || reg_or_0_operand (operands[1], DImode))"
3808 { return mips_output_move (operands[0], operands[1]); }
3809 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
3810 (set_attr "mode" "DI")])
3812 (define_insn "*movdi_64bit_mips16"
3813 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
3814 (match_operand:DI 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
3815 "TARGET_64BIT && TARGET_MIPS16
3816 && (register_operand (operands[0], DImode)
3817 || register_operand (operands[1], DImode))"
3818 { return mips_output_move (operands[0], operands[1]); }
3819 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mfhilo")
3820 (set_attr "mode" "DI")])
3822 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
3823 ;; when the original load is a 4 byte instruction but the add and the
3824 ;; load are 2 2 byte instructions.
3827 [(set (match_operand:DI 0 "d_operand")
3828 (mem:DI (plus:DI (match_dup 0)
3829 (match_operand:DI 1 "const_int_operand"))))]
3830 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
3831 && !TARGET_DEBUG_D_MODE
3832 && ((INTVAL (operands[1]) < 0
3833 && INTVAL (operands[1]) >= -0x10)
3834 || (INTVAL (operands[1]) >= 32 * 8
3835 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
3836 || (INTVAL (operands[1]) >= 0
3837 && INTVAL (operands[1]) < 32 * 8
3838 && (INTVAL (operands[1]) & 7) != 0))"
3839 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
3840 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
3842 HOST_WIDE_INT val = INTVAL (operands[1]);
3845 operands[2] = const0_rtx;
3846 else if (val >= 32 * 8)
3850 operands[1] = GEN_INT (0x8 + off);
3851 operands[2] = GEN_INT (val - off - 0x8);
3857 operands[1] = GEN_INT (off);
3858 operands[2] = GEN_INT (val - off);
3862 ;; 32-bit Integer moves
3864 ;; Unlike most other insns, the move insns can't be split with
3865 ;; different predicates, because register spilling and other parts of
3866 ;; the compiler, have memoized the insn number already.
3868 (define_expand "movsi"
3869 [(set (match_operand:SI 0 "")
3870 (match_operand:SI 1 ""))]
3873 if (mips_legitimize_move (SImode, operands[0], operands[1]))
3877 ;; The difference between these two is whether or not ints are allowed
3878 ;; in FP registers (off by default, use -mdebugh to enable).
3880 (define_insn "*movsi_internal"
3881 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
3882 (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
3884 && (register_operand (operands[0], SImode)
3885 || reg_or_0_operand (operands[1], SImode))"
3886 { return mips_output_move (operands[0], operands[1]); }
3887 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
3888 (set_attr "mode" "SI")])
3890 (define_insn "*movsi_mips16"
3891 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
3892 (match_operand:SI 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
3894 && (register_operand (operands[0], SImode)
3895 || register_operand (operands[1], SImode))"
3896 { return mips_output_move (operands[0], operands[1]); }
3897 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mfhilo")
3898 (set_attr "mode" "SI")])
3900 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
3901 ;; when the original load is a 4 byte instruction but the add and the
3902 ;; load are 2 2 byte instructions.
3905 [(set (match_operand:SI 0 "d_operand")
3906 (mem:SI (plus:SI (match_dup 0)
3907 (match_operand:SI 1 "const_int_operand"))))]
3908 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3909 && ((INTVAL (operands[1]) < 0
3910 && INTVAL (operands[1]) >= -0x80)
3911 || (INTVAL (operands[1]) >= 32 * 4
3912 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
3913 || (INTVAL (operands[1]) >= 0
3914 && INTVAL (operands[1]) < 32 * 4
3915 && (INTVAL (operands[1]) & 3) != 0))"
3916 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3917 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
3919 HOST_WIDE_INT val = INTVAL (operands[1]);
3922 operands[2] = const0_rtx;
3923 else if (val >= 32 * 4)
3927 operands[1] = GEN_INT (0x7c + off);
3928 operands[2] = GEN_INT (val - off - 0x7c);
3934 operands[1] = GEN_INT (off);
3935 operands[2] = GEN_INT (val - off);
3939 ;; On the mips16, we can split a load of certain constants into a load
3940 ;; and an add. This turns a 4 byte instruction into 2 2 byte
3944 [(set (match_operand:SI 0 "d_operand")
3945 (match_operand:SI 1 "const_int_operand"))]
3946 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3947 && INTVAL (operands[1]) >= 0x100
3948 && INTVAL (operands[1]) <= 0xff + 0x7f"
3949 [(set (match_dup 0) (match_dup 1))
3950 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3952 int val = INTVAL (operands[1]);
3954 operands[1] = GEN_INT (0xff);
3955 operands[2] = GEN_INT (val - 0xff);
3958 ;; This insn handles moving CCmode values. It's really just a
3959 ;; slightly simplified copy of movsi_internal2, with additional cases
3960 ;; to move a condition register to a general register and to move
3961 ;; between the general registers and the floating point registers.
3963 (define_insn "movcc"
3964 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
3965 (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
3966 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3967 { return mips_output_move (operands[0], operands[1]); }
3968 [(set_attr "move_type" "lui_movf,move,load,store,mfc,mtc,fmove,fpload,fpstore")
3969 (set_attr "mode" "SI")])
3971 ;; Reload condition code registers. reload_incc and reload_outcc
3972 ;; both handle moves from arbitrary operands into condition code
3973 ;; registers. reload_incc handles the more common case in which
3974 ;; a source operand is constrained to be in a condition-code
3975 ;; register, but has not been allocated to one.
3977 ;; Sometimes, such as in movcc, we have a CCmode destination whose
3978 ;; constraints do not include 'z'. reload_outcc handles the case
3979 ;; when such an operand is allocated to a condition-code register.
3981 ;; Note that reloads from a condition code register to some
3982 ;; other location can be done using ordinary moves. Moving
3983 ;; into a GPR takes a single movcc, moving elsewhere takes
3984 ;; two. We can leave these cases to the generic reload code.
3985 (define_expand "reload_incc"
3986 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3987 (match_operand:CC 1 "general_operand" ""))
3988 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3989 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3991 mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
3995 (define_expand "reload_outcc"
3996 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3997 (match_operand:CC 1 "register_operand" ""))
3998 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3999 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4001 mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
4005 ;; MIPS4 supports loading and storing a floating point register from
4006 ;; the sum of two general registers. We use two versions for each of
4007 ;; these four instructions: one where the two general registers are
4008 ;; SImode, and one where they are DImode. This is because general
4009 ;; registers will be in SImode when they hold 32-bit values, but,
4010 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
4011 ;; instructions will still work correctly.
4013 ;; ??? Perhaps it would be better to support these instructions by
4014 ;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since
4015 ;; these instructions can only be used to load and store floating
4016 ;; point registers, that would probably cause trouble in reload.
4018 (define_insn "*<ANYF:loadx>_<P:mode>"
4019 [(set (match_operand:ANYF 0 "register_operand" "=f")
4020 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4021 (match_operand:P 2 "register_operand" "d"))))]
4023 "<ANYF:loadx>\t%0,%1(%2)"
4024 [(set_attr "type" "fpidxload")
4025 (set_attr "mode" "<ANYF:UNITMODE>")])
4027 (define_insn "*<ANYF:storex>_<P:mode>"
4028 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4029 (match_operand:P 2 "register_operand" "d")))
4030 (match_operand:ANYF 0 "register_operand" "f"))]
4032 "<ANYF:storex>\t%0,%1(%2)"
4033 [(set_attr "type" "fpidxstore")
4034 (set_attr "mode" "<ANYF:UNITMODE>")])
4036 ;; Scaled indexed address load.
4037 ;; Per md.texi, we only need to look for a pattern with multiply in the
4038 ;; address expression, not shift.
4040 (define_insn "*lwxs"
4041 [(set (match_operand:SI 0 "register_operand" "=d")
4042 (mem:SI (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
4044 (match_operand:SI 2 "register_operand" "d"))))]
4047 [(set_attr "type" "load")
4048 (set_attr "mode" "SI")])
4050 ;; 16-bit Integer moves
4052 ;; Unlike most other insns, the move insns can't be split with
4053 ;; different predicates, because register spilling and other parts of
4054 ;; the compiler, have memoized the insn number already.
4055 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4057 (define_expand "movhi"
4058 [(set (match_operand:HI 0 "")
4059 (match_operand:HI 1 ""))]
4062 if (mips_legitimize_move (HImode, operands[0], operands[1]))
4066 (define_insn "*movhi_internal"
4067 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4068 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
4070 && (register_operand (operands[0], HImode)
4071 || reg_or_0_operand (operands[1], HImode))"
4072 { return mips_output_move (operands[0], operands[1]); }
4073 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4074 (set_attr "mode" "HI")])
4076 (define_insn "*movhi_mips16"
4077 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4078 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4080 && (register_operand (operands[0], HImode)
4081 || register_operand (operands[1], HImode))"
4082 { return mips_output_move (operands[0], operands[1]); }
4083 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4084 (set_attr "mode" "HI")])
4086 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
4087 ;; when the original load is a 4 byte instruction but the add and the
4088 ;; load are 2 2 byte instructions.
4091 [(set (match_operand:HI 0 "d_operand")
4092 (mem:HI (plus:SI (match_dup 0)
4093 (match_operand:SI 1 "const_int_operand"))))]
4094 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4095 && ((INTVAL (operands[1]) < 0
4096 && INTVAL (operands[1]) >= -0x80)
4097 || (INTVAL (operands[1]) >= 32 * 2
4098 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
4099 || (INTVAL (operands[1]) >= 0
4100 && INTVAL (operands[1]) < 32 * 2
4101 && (INTVAL (operands[1]) & 1) != 0))"
4102 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4103 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
4105 HOST_WIDE_INT val = INTVAL (operands[1]);
4108 operands[2] = const0_rtx;
4109 else if (val >= 32 * 2)
4113 operands[1] = GEN_INT (0x7e + off);
4114 operands[2] = GEN_INT (val - off - 0x7e);
4120 operands[1] = GEN_INT (off);
4121 operands[2] = GEN_INT (val - off);
4125 ;; 8-bit Integer moves
4127 ;; Unlike most other insns, the move insns can't be split with
4128 ;; different predicates, because register spilling and other parts of
4129 ;; the compiler, have memoized the insn number already.
4130 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4132 (define_expand "movqi"
4133 [(set (match_operand:QI 0 "")
4134 (match_operand:QI 1 ""))]
4137 if (mips_legitimize_move (QImode, operands[0], operands[1]))
4141 (define_insn "*movqi_internal"
4142 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4143 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
4145 && (register_operand (operands[0], QImode)
4146 || reg_or_0_operand (operands[1], QImode))"
4147 { return mips_output_move (operands[0], operands[1]); }
4148 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4149 (set_attr "mode" "QI")])
4151 (define_insn "*movqi_mips16"
4152 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4153 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4155 && (register_operand (operands[0], QImode)
4156 || register_operand (operands[1], QImode))"
4157 { return mips_output_move (operands[0], operands[1]); }
4158 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4159 (set_attr "mode" "QI")])
4161 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
4162 ;; when the original load is a 4 byte instruction but the add and the
4163 ;; load are 2 2 byte instructions.
4166 [(set (match_operand:QI 0 "d_operand")
4167 (mem:QI (plus:SI (match_dup 0)
4168 (match_operand:SI 1 "const_int_operand"))))]
4169 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4170 && ((INTVAL (operands[1]) < 0
4171 && INTVAL (operands[1]) >= -0x80)
4172 || (INTVAL (operands[1]) >= 32
4173 && INTVAL (operands[1]) <= 31 + 0x7f))"
4174 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4175 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
4177 HOST_WIDE_INT val = INTVAL (operands[1]);
4180 operands[2] = const0_rtx;
4183 operands[1] = GEN_INT (0x7f);
4184 operands[2] = GEN_INT (val - 0x7f);
4188 ;; 32-bit floating point moves
4190 (define_expand "movsf"
4191 [(set (match_operand:SF 0 "")
4192 (match_operand:SF 1 ""))]
4195 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
4199 (define_insn "*movsf_hardfloat"
4200 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4201 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
4203 && (register_operand (operands[0], SFmode)
4204 || reg_or_0_operand (operands[1], SFmode))"
4205 { return mips_output_move (operands[0], operands[1]); }
4206 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4207 (set_attr "mode" "SF")])
4209 (define_insn "*movsf_softfloat"
4210 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
4211 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
4212 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
4213 && (register_operand (operands[0], SFmode)
4214 || reg_or_0_operand (operands[1], SFmode))"
4215 { return mips_output_move (operands[0], operands[1]); }
4216 [(set_attr "move_type" "move,load,store")
4217 (set_attr "mode" "SF")])
4219 (define_insn "*movsf_mips16"
4220 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
4221 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
4223 && (register_operand (operands[0], SFmode)
4224 || register_operand (operands[1], SFmode))"
4225 { return mips_output_move (operands[0], operands[1]); }
4226 [(set_attr "move_type" "move,move,move,load,store")
4227 (set_attr "mode" "SF")])
4229 ;; 64-bit floating point moves
4231 (define_expand "movdf"
4232 [(set (match_operand:DF 0 "")
4233 (match_operand:DF 1 ""))]
4236 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
4240 (define_insn "*movdf_hardfloat"
4241 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4242 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
4243 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
4244 && (register_operand (operands[0], DFmode)
4245 || reg_or_0_operand (operands[1], DFmode))"
4246 { return mips_output_move (operands[0], operands[1]); }
4247 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4248 (set_attr "mode" "DF")])
4250 (define_insn "*movdf_softfloat"
4251 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m")
4252 (match_operand:DF 1 "move_operand" "dG,m,dG"))]
4253 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
4254 && (register_operand (operands[0], DFmode)
4255 || reg_or_0_operand (operands[1], DFmode))"
4256 { return mips_output_move (operands[0], operands[1]); }
4257 [(set_attr "move_type" "move,load,store")
4258 (set_attr "mode" "DF")])
4260 (define_insn "*movdf_mips16"
4261 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
4262 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
4264 && (register_operand (operands[0], DFmode)
4265 || register_operand (operands[1], DFmode))"
4266 { return mips_output_move (operands[0], operands[1]); }
4267 [(set_attr "move_type" "move,move,move,load,store")
4268 (set_attr "mode" "DF")])
4270 ;; 128-bit integer moves
4272 (define_expand "movti"
4273 [(set (match_operand:TI 0)
4274 (match_operand:TI 1))]
4277 if (mips_legitimize_move (TImode, operands[0], operands[1]))
4281 (define_insn "*movti"
4282 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4283 (match_operand:TI 1 "move_operand" "d,i,m,dJ,*d*J,*a"))]
4286 && (register_operand (operands[0], TImode)
4287 || reg_or_0_operand (operands[1], TImode))"
4289 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4290 (set_attr "mode" "TI")])
4292 (define_insn "*movti_mips16"
4293 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4294 (match_operand:TI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4297 && (register_operand (operands[0], TImode)
4298 || register_operand (operands[1], TImode))"
4300 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4301 (set_attr "mode" "TI")])
4303 ;; 128-bit floating point moves
4305 (define_expand "movtf"
4306 [(set (match_operand:TF 0)
4307 (match_operand:TF 1))]
4310 if (mips_legitimize_move (TFmode, operands[0], operands[1]))
4314 ;; This pattern handles both hard- and soft-float cases.
4315 (define_insn "*movtf"
4316 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,d,m,f,d,f,m")
4317 (match_operand:TF 1 "move_operand" "dG,m,dG,dG,f,m,f"))]
4320 && (register_operand (operands[0], TFmode)
4321 || reg_or_0_operand (operands[1], TFmode))"
4323 [(set_attr "move_type" "move,load,store,mtc,mfc,fpload,fpstore")
4324 (set_attr "mode" "TF")])
4326 (define_insn "*movtf_mips16"
4327 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,y,d,d,m")
4328 (match_operand:TF 1 "move_operand" "d,d,y,m,d"))]
4331 && (register_operand (operands[0], TFmode)
4332 || register_operand (operands[1], TFmode))"
4334 [(set_attr "move_type" "move,move,move,load,store")
4335 (set_attr "mode" "TF")])
4338 [(set (match_operand:MOVE64 0 "nonimmediate_operand")
4339 (match_operand:MOVE64 1 "move_operand"))]
4340 "reload_completed && !TARGET_64BIT
4341 && mips_split_64bit_move_p (operands[0], operands[1])"
4344 mips_split_doubleword_move (operands[0], operands[1]);
4349 [(set (match_operand:MOVE128 0 "nonimmediate_operand")
4350 (match_operand:MOVE128 1 "move_operand"))]
4351 "TARGET_64BIT && reload_completed"
4354 mips_split_doubleword_move (operands[0], operands[1]);
4358 ;; When generating mips16 code, split moves of negative constants into
4359 ;; a positive "li" followed by a negation.
4361 [(set (match_operand 0 "d_operand")
4362 (match_operand 1 "const_int_operand"))]
4363 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
4367 (neg:SI (match_dup 2)))]
4369 operands[2] = gen_lowpart (SImode, operands[0]);
4370 operands[3] = GEN_INT (-INTVAL (operands[1]));
4373 ;; 64-bit paired-single floating point moves
4375 (define_expand "movv2sf"
4376 [(set (match_operand:V2SF 0)
4377 (match_operand:V2SF 1))]
4378 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
4380 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
4384 (define_insn "*movv2sf"
4385 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4386 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
4388 && TARGET_PAIRED_SINGLE_FLOAT
4389 && (register_operand (operands[0], V2SFmode)
4390 || reg_or_0_operand (operands[1], V2SFmode))"
4391 { return mips_output_move (operands[0], operands[1]); }
4392 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4393 (set_attr "mode" "DF")])
4395 ;; Extract the high part of a HI/LO value. See mips_hard_regno_mode_ok_p
4396 ;; for the reason why we can't just use (reg:GPR HI_REGNUM).
4398 ;; When generating VR4120 or VR4130 code, we use MACCHI and DMACCHI
4399 ;; instead of MFHI. This avoids both the normal MIPS III hi/lo hazards
4400 ;; and the errata related to -mfix-vr4130.
4401 (define_insn "mfhi<GPR:mode>_<HILO:mode>"
4402 [(set (match_operand:GPR 0 "register_operand" "=d")
4403 (unspec:GPR [(match_operand:HILO 1 "register_operand" "x")]
4406 { return ISA_HAS_MACCHI ? "<GPR:d>macchi\t%0,%.,%." : "mfhi\t%0"; }
4407 [(set_attr "move_type" "mfhilo")
4408 (set_attr "mode" "<GPR:MODE>")])
4410 ;; Set the high part of a HI/LO value, given that the low part has
4411 ;; already been set. See mips_hard_regno_mode_ok_p for the reason
4412 ;; why we can't just use (reg:GPR HI_REGNUM).
4413 (define_insn "mthi<GPR:mode>_<HILO:mode>"
4414 [(set (match_operand:HILO 0 "register_operand" "=x")
4415 (unspec:HILO [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
4416 (match_operand:GPR 2 "register_operand" "l")]
4420 [(set_attr "move_type" "mthilo")
4421 (set_attr "mode" "SI")])
4423 ;; Emit a doubleword move in which exactly one of the operands is
4424 ;; a floating-point register. We can't just emit two normal moves
4425 ;; because of the constraints imposed by the FPU register model;
4426 ;; see mips_cannot_change_mode_class for details. Instead, we keep
4427 ;; the FPR whole and use special patterns to refer to each word of
4428 ;; the other operand.
4430 (define_expand "move_doubleword_fpr<mode>"
4431 [(set (match_operand:SPLITF 0)
4432 (match_operand:SPLITF 1))]
4435 if (FP_REG_RTX_P (operands[0]))
4437 rtx low = mips_subword (operands[1], 0);
4438 rtx high = mips_subword (operands[1], 1);
4439 emit_insn (gen_load_low<mode> (operands[0], low));
4441 emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
4443 emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
4447 rtx low = mips_subword (operands[0], 0);
4448 rtx high = mips_subword (operands[0], 1);
4449 emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
4451 emit_insn (gen_mfhc1<mode> (high, operands[1]));
4453 emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));
4458 ;; Load the low word of operand 0 with operand 1.
4459 (define_insn "load_low<mode>"
4460 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4461 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")]
4465 operands[0] = mips_subword (operands[0], 0);
4466 return mips_output_move (operands[0], operands[1]);
4468 [(set_attr "move_type" "mtc,fpload")
4469 (set_attr "mode" "<HALFMODE>")])
4471 ;; Load the high word of operand 0 from operand 1, preserving the value
4473 (define_insn "load_high<mode>"
4474 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4475 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")
4476 (match_operand:SPLITF 2 "register_operand" "0,0")]
4480 operands[0] = mips_subword (operands[0], 1);
4481 return mips_output_move (operands[0], operands[1]);
4483 [(set_attr "move_type" "mtc,fpload")
4484 (set_attr "mode" "<HALFMODE>")])
4486 ;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the
4487 ;; high word and 0 to store the low word.
4488 (define_insn "store_word<mode>"
4489 [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=d,m")
4490 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f")
4491 (match_operand 2 "const_int_operand")]
4492 UNSPEC_STORE_WORD))]
4495 operands[1] = mips_subword (operands[1], INTVAL (operands[2]));
4496 return mips_output_move (operands[0], operands[1]);
4498 [(set_attr "move_type" "mfc,fpstore")
4499 (set_attr "mode" "<HALFMODE>")])
4501 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
4502 ;; value in the low word.
4503 (define_insn "mthc1<mode>"
4504 [(set (match_operand:SPLITF 0 "register_operand" "=f")
4505 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ")
4506 (match_operand:SPLITF 2 "register_operand" "0")]
4508 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4510 [(set_attr "move_type" "mtc")
4511 (set_attr "mode" "<HALFMODE>")])
4513 ;; Move high word of operand 1 to operand 0 using mfhc1.
4514 (define_insn "mfhc1<mode>"
4515 [(set (match_operand:<HALFMODE> 0 "register_operand" "=d")
4516 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")]
4518 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4520 [(set_attr "move_type" "mfc")
4521 (set_attr "mode" "<HALFMODE>")])
4523 ;; Move a constant that satisfies CONST_GP_P into operand 0.
4524 (define_expand "load_const_gp_<mode>"
4525 [(set (match_operand:P 0 "register_operand" "=d")
4526 (const:P (unspec:P [(const_int 0)] UNSPEC_GP)))])
4528 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
4529 ;; of _gp from the start of this function. Operand 1 is the incoming
4530 ;; function address.
4531 (define_insn_and_split "loadgp_newabi_<mode>"
4532 [(set (match_operand:P 0 "register_operand" "=d")
4533 (unspec_volatile:P [(match_operand:P 1)
4534 (match_operand:P 2 "register_operand" "d")]
4536 "mips_current_loadgp_style () == LOADGP_NEWABI"
4539 [(set (match_dup 0) (match_dup 3))
4540 (set (match_dup 0) (match_dup 4))
4541 (set (match_dup 0) (match_dup 5))]
4543 operands[3] = gen_rtx_HIGH (Pmode, operands[1]);
4544 operands[4] = gen_rtx_PLUS (Pmode, operands[0], operands[2]);
4545 operands[5] = gen_rtx_LO_SUM (Pmode, operands[0], operands[1]);
4547 [(set_attr "length" "12")])
4549 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
4550 (define_insn_and_split "loadgp_absolute_<mode>"
4551 [(set (match_operand:P 0 "register_operand" "=d")
4552 (unspec_volatile:P [(match_operand:P 1)] UNSPEC_LOADGP))]
4553 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
4558 mips_emit_move (operands[0], operands[1]);
4561 [(set_attr "length" "8")])
4563 ;; This blockage instruction prevents the gp load from being
4564 ;; scheduled after an implicit use of gp. It also prevents
4565 ;; the load from being deleted as dead.
4566 (define_insn "loadgp_blockage"
4567 [(unspec_volatile [(reg:SI 28)] UNSPEC_BLOCKAGE)]
4570 [(set_attr "type" "ghost")
4571 (set_attr "mode" "none")])
4573 ;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
4574 ;; and operand 1 is the __GOTT_INDEX__ symbol.
4575 (define_insn_and_split "loadgp_rtp_<mode>"
4576 [(set (match_operand:P 0 "register_operand" "=d")
4577 (unspec_volatile:P [(match_operand:P 1 "symbol_ref_operand")
4578 (match_operand:P 2 "symbol_ref_operand")]
4580 "mips_current_loadgp_style () == LOADGP_RTP"
4583 [(set (match_dup 0) (high:P (match_dup 3)))
4584 (set (match_dup 0) (unspec:P [(match_dup 0)
4585 (match_dup 3)] UNSPEC_LOAD_GOT))
4586 (set (match_dup 0) (unspec:P [(match_dup 0)
4587 (match_dup 4)] UNSPEC_LOAD_GOT))]
4589 operands[3] = mips_unspec_address (operands[1], SYMBOL_ABSOLUTE);
4590 operands[4] = mips_unspec_address (operands[2], SYMBOL_HALF);
4592 [(set_attr "length" "12")])
4594 ;; Initialize the global pointer for MIPS16 code. Operand 0 is the
4595 ;; global pointer and operand 1 is the MIPS16 register that holds
4596 ;; the required value.
4597 (define_insn_and_split "copygp_mips16"
4598 [(set (match_operand:SI 0 "register_operand" "=y")
4599 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d")]
4603 "&& reload_completed"
4604 [(set (match_dup 0) (match_dup 1))])
4606 ;; Emit a .cprestore directive, which normally expands to a single store
4607 ;; instruction. Note that we continue to use .cprestore for explicit reloc
4608 ;; code so that jals inside inline asms will work correctly.
4609 (define_insn "cprestore"
4610 [(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")
4615 if (set_nomacro && which_alternative == 1)
4616 return ".set\tmacro\;.cprestore\t%0\;.set\tnomacro";
4618 return ".cprestore\t%0";
4620 [(set_attr "type" "store")
4621 (set_attr "length" "4,12")])
4623 ;; Expand in-line code to clear the instruction cache between operand[0] and
4625 (define_expand "clear_cache"
4626 [(match_operand 0 "pmode_register_operand")
4627 (match_operand 1 "pmode_register_operand")]
4633 mips_expand_synci_loop (operands[0], operands[1]);
4634 emit_insn (gen_sync ());
4635 emit_insn (gen_clear_hazard ());
4637 else if (mips_cache_flush_func && mips_cache_flush_func[0])
4639 rtx len = gen_reg_rtx (Pmode);
4640 emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
4641 MIPS_ICACHE_SYNC (operands[0], len);
4647 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
4651 (define_insn "synci"
4652 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
4657 (define_insn "rdhwr"
4658 [(set (match_operand:SI 0 "register_operand" "=d")
4659 (unspec_volatile [(match_operand:SI 1 "const_int_operand" "n")]
4664 (define_insn "clear_hazard"
4665 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
4666 (clobber (reg:SI 31))]
4669 return "%(%<bal\t1f\n"
4671 "1:\taddiu\t$31,$31,12\n"
4675 [(set_attr "length" "20")])
4678 ;; Block moves, see mips.c for more details.
4679 ;; Argument 0 is the destination
4680 ;; Argument 1 is the source
4681 ;; Argument 2 is the length
4682 ;; Argument 3 is the alignment
4684 (define_expand "movmemsi"
4685 [(parallel [(set (match_operand:BLK 0 "general_operand")
4686 (match_operand:BLK 1 "general_operand"))
4687 (use (match_operand:SI 2 ""))
4688 (use (match_operand:SI 3 "const_int_operand"))])]
4689 "!TARGET_MIPS16 && !TARGET_MEMCPY"
4691 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
4698 ;; ....................
4702 ;; ....................
4704 (define_expand "<optab><mode>3"
4705 [(set (match_operand:GPR 0 "register_operand")
4706 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4707 (match_operand:SI 2 "arith_operand")))]
4710 /* On the mips16, a shift of more than 8 is a four byte instruction,
4711 so, for a shift between 8 and 16, it is just as fast to do two
4712 shifts of 8 or less. If there is a lot of shifting going on, we
4713 may win in CSE. Otherwise combine will put the shifts back
4714 together again. This can be called by mips_function_arg, so we must
4715 be careful not to allocate a new register if we've reached the
4719 && GET_CODE (operands[2]) == CONST_INT
4720 && INTVAL (operands[2]) > 8
4721 && INTVAL (operands[2]) <= 16
4722 && !reload_in_progress
4723 && !reload_completed)
4725 rtx temp = gen_reg_rtx (<MODE>mode);
4727 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
4728 emit_insn (gen_<optab><mode>3 (operands[0], temp,
4729 GEN_INT (INTVAL (operands[2]) - 8)));
4734 (define_insn "*<optab><mode>3"
4735 [(set (match_operand:GPR 0 "register_operand" "=d")
4736 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
4737 (match_operand:SI 2 "arith_operand" "dI")))]
4740 if (GET_CODE (operands[2]) == CONST_INT)
4741 operands[2] = GEN_INT (INTVAL (operands[2])
4742 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
4744 return "<d><insn>\t%0,%1,%2";
4746 [(set_attr "type" "shift")
4747 (set_attr "mode" "<MODE>")])
4749 (define_insn "*<optab>si3_extend"
4750 [(set (match_operand:DI 0 "register_operand" "=d")
4752 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
4753 (match_operand:SI 2 "arith_operand" "dI"))))]
4754 "TARGET_64BIT && !TARGET_MIPS16"
4756 if (GET_CODE (operands[2]) == CONST_INT)
4757 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4759 return "<insn>\t%0,%1,%2";
4761 [(set_attr "type" "shift")
4762 (set_attr "mode" "SI")])
4764 (define_insn "*<optab>si3_mips16"
4765 [(set (match_operand:SI 0 "register_operand" "=d,d")
4766 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
4767 (match_operand:SI 2 "arith_operand" "d,I")))]
4770 if (which_alternative == 0)
4771 return "<insn>\t%0,%2";
4773 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4774 return "<insn>\t%0,%1,%2";
4776 [(set_attr "type" "shift")
4777 (set_attr "mode" "SI")
4778 (set_attr_alternative "length"
4780 (if_then_else (match_operand 2 "m16_uimm3_b")
4784 ;; We need separate DImode MIPS16 patterns because of the irregularity
4786 (define_insn "*ashldi3_mips16"
4787 [(set (match_operand:DI 0 "register_operand" "=d,d")
4788 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
4789 (match_operand:SI 2 "arith_operand" "d,I")))]
4790 "TARGET_64BIT && TARGET_MIPS16"
4792 if (which_alternative == 0)
4793 return "dsll\t%0,%2";
4795 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4796 return "dsll\t%0,%1,%2";
4798 [(set_attr "type" "shift")
4799 (set_attr "mode" "DI")
4800 (set_attr_alternative "length"
4802 (if_then_else (match_operand 2 "m16_uimm3_b")
4806 (define_insn "*ashrdi3_mips16"
4807 [(set (match_operand:DI 0 "register_operand" "=d,d")
4808 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4809 (match_operand:SI 2 "arith_operand" "d,I")))]
4810 "TARGET_64BIT && TARGET_MIPS16"
4812 if (GET_CODE (operands[2]) == CONST_INT)
4813 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4815 return "dsra\t%0,%2";
4817 [(set_attr "type" "shift")
4818 (set_attr "mode" "DI")
4819 (set_attr_alternative "length"
4821 (if_then_else (match_operand 2 "m16_uimm3_b")
4825 (define_insn "*lshrdi3_mips16"
4826 [(set (match_operand:DI 0 "register_operand" "=d,d")
4827 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4828 (match_operand:SI 2 "arith_operand" "d,I")))]
4829 "TARGET_64BIT && TARGET_MIPS16"
4831 if (GET_CODE (operands[2]) == CONST_INT)
4832 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4834 return "dsrl\t%0,%2";
4836 [(set_attr "type" "shift")
4837 (set_attr "mode" "DI")
4838 (set_attr_alternative "length"
4840 (if_then_else (match_operand 2 "m16_uimm3_b")
4844 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
4847 [(set (match_operand:GPR 0 "d_operand")
4848 (any_shift:GPR (match_operand:GPR 1 "d_operand")
4849 (match_operand:GPR 2 "const_int_operand")))]
4850 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4851 && INTVAL (operands[2]) > 8
4852 && INTVAL (operands[2]) <= 16"
4853 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
4854 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
4855 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
4857 ;; If we load a byte on the mips16 as a bitfield, the resulting
4858 ;; sequence of instructions is too complicated for combine, because it
4859 ;; involves four instructions: a load, a shift, a constant load into a
4860 ;; register, and an and (the key problem here is that the mips16 does
4861 ;; not have and immediate). We recognize a shift of a load in order
4862 ;; to make it simple enough for combine to understand.
4864 ;; The length here is the worst case: the length of the split version
4865 ;; will be more accurate.
4866 (define_insn_and_split ""
4867 [(set (match_operand:SI 0 "register_operand" "=d")
4868 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
4869 (match_operand:SI 2 "immediate_operand" "I")))]
4873 [(set (match_dup 0) (match_dup 1))
4874 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
4876 [(set_attr "type" "load")
4877 (set_attr "mode" "SI")
4878 (set_attr "length" "16")])
4880 (define_insn "rotr<mode>3"
4881 [(set (match_operand:GPR 0 "register_operand" "=d")
4882 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
4883 (match_operand:SI 2 "arith_operand" "dI")))]
4886 if (GET_CODE (operands[2]) == CONST_INT)
4887 gcc_assert (INTVAL (operands[2]) >= 0
4888 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
4890 return "<d>ror\t%0,%1,%2";
4892 [(set_attr "type" "shift")
4893 (set_attr "mode" "<MODE>")])
4896 ;; ....................
4900 ;; ....................
4902 ;; Flow here is rather complex:
4904 ;; 1) The cmp{si,di,sf,df} routine is called. It deposits the arguments
4905 ;; into cmp_operands[] but generates no RTL.
4907 ;; 2) The appropriate branch define_expand is called, which then
4908 ;; creates the appropriate RTL for the comparison and branch.
4909 ;; Different CC modes are used, based on what type of branch is
4910 ;; done, so that we can constrain things appropriately. There
4911 ;; are assumptions in the rest of GCC that break if we fold the
4912 ;; operands into the branches for integer operations, and use cc0
4913 ;; for floating point, so we use the fp status register instead.
4914 ;; If needed, an appropriate temporary is created to hold the
4915 ;; of the integer compare.
4917 (define_expand "cmp<mode>"
4919 (compare:CC (match_operand:GPR 0 "register_operand")
4920 (match_operand:GPR 1 "nonmemory_operand")))]
4923 cmp_operands[0] = operands[0];
4924 cmp_operands[1] = operands[1];
4928 (define_expand "cmp<mode>"
4930 (compare:CC (match_operand:SCALARF 0 "register_operand")
4931 (match_operand:SCALARF 1 "register_operand")))]
4934 cmp_operands[0] = operands[0];
4935 cmp_operands[1] = operands[1];
4940 ;; ....................
4942 ;; CONDITIONAL BRANCHES
4944 ;; ....................
4946 ;; Conditional branches on floating-point equality tests.
4948 (define_insn "*branch_fp"
4951 (match_operator 0 "equality_operator"
4952 [(match_operand:CC 2 "register_operand" "z")
4954 (label_ref (match_operand 1 "" ""))
4958 return mips_output_conditional_branch (insn, operands,
4959 MIPS_BRANCH ("b%F0", "%Z2%1"),
4960 MIPS_BRANCH ("b%W0", "%Z2%1"));
4962 [(set_attr "type" "branch")
4963 (set_attr "mode" "none")])
4965 (define_insn "*branch_fp_inverted"
4968 (match_operator 0 "equality_operator"
4969 [(match_operand:CC 2 "register_operand" "z")
4972 (label_ref (match_operand 1 "" ""))))]
4975 return mips_output_conditional_branch (insn, operands,
4976 MIPS_BRANCH ("b%W0", "%Z2%1"),
4977 MIPS_BRANCH ("b%F0", "%Z2%1"));
4979 [(set_attr "type" "branch")
4980 (set_attr "mode" "none")])
4982 ;; Conditional branches on ordered comparisons with zero.
4984 (define_insn "*branch_order<mode>"
4987 (match_operator 0 "order_operator"
4988 [(match_operand:GPR 2 "register_operand" "d")
4990 (label_ref (match_operand 1 "" ""))
4993 { return mips_output_order_conditional_branch (insn, operands, false); }
4994 [(set_attr "type" "branch")
4995 (set_attr "mode" "none")])
4997 (define_insn "*branch_order<mode>_inverted"
5000 (match_operator 0 "order_operator"
5001 [(match_operand:GPR 2 "register_operand" "d")
5004 (label_ref (match_operand 1 "" ""))))]
5006 { return mips_output_order_conditional_branch (insn, operands, true); }
5007 [(set_attr "type" "branch")
5008 (set_attr "mode" "none")])
5010 ;; Conditional branch on equality comparison.
5012 (define_insn "*branch_equality<mode>"
5015 (match_operator 0 "equality_operator"
5016 [(match_operand:GPR 2 "register_operand" "d")
5017 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5018 (label_ref (match_operand 1 "" ""))
5022 return mips_output_conditional_branch (insn, operands,
5023 MIPS_BRANCH ("b%C0", "%2,%z3,%1"),
5024 MIPS_BRANCH ("b%N0", "%2,%z3,%1"));
5026 [(set_attr "type" "branch")
5027 (set_attr "mode" "none")])
5029 (define_insn "*branch_equality<mode>_inverted"
5032 (match_operator 0 "equality_operator"
5033 [(match_operand:GPR 2 "register_operand" "d")
5034 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5036 (label_ref (match_operand 1 "" ""))))]
5039 return mips_output_conditional_branch (insn, operands,
5040 MIPS_BRANCH ("b%N0", "%2,%z3,%1"),
5041 MIPS_BRANCH ("b%C0", "%2,%z3,%1"));
5043 [(set_attr "type" "branch")
5044 (set_attr "mode" "none")])
5048 (define_insn "*branch_equality<mode>_mips16"
5051 (match_operator 0 "equality_operator"
5052 [(match_operand:GPR 1 "register_operand" "d,t")
5054 (match_operand 2 "pc_or_label_operand" "")
5055 (match_operand 3 "pc_or_label_operand" "")))]
5058 if (operands[2] != pc_rtx)
5060 if (which_alternative == 0)
5061 return "b%C0z\t%1,%2";
5063 return "bt%C0z\t%2";
5067 if (which_alternative == 0)
5068 return "b%N0z\t%1,%3";
5070 return "bt%N0z\t%3";
5073 [(set_attr "type" "branch")
5074 (set_attr "mode" "none")])
5076 (define_expand "b<code>"
5078 (if_then_else (any_cond:CC (cc0)
5080 (label_ref (match_operand 0 ""))
5084 mips_expand_conditional_branch (operands, <CODE>);
5088 ;; Used to implement built-in functions.
5089 (define_expand "condjump"
5091 (if_then_else (match_operand 0)
5092 (label_ref (match_operand 1))
5095 ;; Branch if bit is set/clear.
5097 (define_insn "*branch_bit<bbv><mode>"
5100 (equality_op (zero_extract:GPR
5101 (match_operand:GPR 1 "register_operand" "d")
5103 (match_operand 2 "const_int_operand" ""))
5105 (label_ref (match_operand 0 ""))
5107 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5110 mips_output_conditional_branch (insn, operands,
5111 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"),
5112 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"));
5114 [(set_attr "type" "branch")
5115 (set_attr "mode" "none")
5116 (set_attr "branch_likely" "no")])
5118 (define_insn "*branch_bit<bbv><mode>_inverted"
5121 (equality_op (zero_extract:GPR
5122 (match_operand:GPR 1 "register_operand" "d")
5124 (match_operand 2 "const_int_operand" ""))
5127 (label_ref (match_operand 0 ""))))]
5128 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5131 mips_output_conditional_branch (insn, operands,
5132 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"),
5133 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"));
5135 [(set_attr "type" "branch")
5136 (set_attr "mode" "none")
5137 (set_attr "branch_likely" "no")])
5140 ;; ....................
5142 ;; SETTING A REGISTER FROM A COMPARISON
5144 ;; ....................
5146 ;; Destination is always set in SI mode.
5148 (define_expand "seq"
5149 [(set (match_operand:SI 0 "register_operand")
5150 (eq:SI (match_dup 1)
5153 { if (mips_expand_scc (EQ, operands[0])) DONE; else FAIL; })
5155 (define_insn "*seq_<GPR:mode><GPR2:mode>"
5156 [(set (match_operand:GPR2 0 "register_operand" "=d")
5157 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5161 [(set_attr "type" "slt")
5162 (set_attr "mode" "<GPR:MODE>")])
5164 (define_insn "*seq_<GPR:mode><GPR2:mode>_mips16"
5165 [(set (match_operand:GPR2 0 "register_operand" "=t")
5166 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5170 [(set_attr "type" "slt")
5171 (set_attr "mode" "<GPR:MODE>")])
5173 ;; "sne" uses sltu instructions in which the first operand is $0.
5174 ;; This isn't possible in mips16 code.
5176 (define_expand "sne"
5177 [(set (match_operand:SI 0 "register_operand")
5178 (ne:SI (match_dup 1)
5181 { if (mips_expand_scc (NE, operands[0])) DONE; else FAIL; })
5183 (define_insn "*sne_<GPR:mode><GPR2:mode>"
5184 [(set (match_operand:GPR2 0 "register_operand" "=d")
5185 (ne:GPR2 (match_operand:GPR 1 "register_operand" "d")
5189 [(set_attr "type" "slt")
5190 (set_attr "mode" "<GPR:MODE>")])
5192 (define_expand "sgt<u>"
5193 [(set (match_operand:SI 0 "register_operand")
5194 (any_gt:SI (match_dup 1)
5197 { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
5199 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>"
5200 [(set (match_operand:GPR2 0 "register_operand" "=d")
5201 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5202 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
5205 [(set_attr "type" "slt")
5206 (set_attr "mode" "<GPR:MODE>")])
5208 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>_mips16"
5209 [(set (match_operand:GPR2 0 "register_operand" "=t")
5210 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5211 (match_operand:GPR 2 "register_operand" "d")))]
5214 [(set_attr "type" "slt")
5215 (set_attr "mode" "<GPR:MODE>")])
5217 (define_expand "sge<u>"
5218 [(set (match_operand:SI 0 "register_operand")
5219 (any_ge:SI (match_dup 1)
5222 { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
5224 (define_insn "*sge<u>_<GPR:mode><GPR2:mode>"
5225 [(set (match_operand:GPR2 0 "register_operand" "=d")
5226 (any_ge:GPR2 (match_operand:GPR 1 "register_operand" "d")
5230 [(set_attr "type" "slt")
5231 (set_attr "mode" "<GPR:MODE>")])
5233 (define_expand "slt<u>"
5234 [(set (match_operand:SI 0 "register_operand")
5235 (any_lt:SI (match_dup 1)
5238 { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
5240 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>"
5241 [(set (match_operand:GPR2 0 "register_operand" "=d")
5242 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5243 (match_operand:GPR 2 "arith_operand" "dI")))]
5246 [(set_attr "type" "slt")
5247 (set_attr "mode" "<GPR:MODE>")])
5249 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>_mips16"
5250 [(set (match_operand:GPR2 0 "register_operand" "=t,t")
5251 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d,d")
5252 (match_operand:GPR 2 "arith_operand" "d,I")))]
5255 [(set_attr "type" "slt")
5256 (set_attr "mode" "<GPR:MODE>")
5257 (set_attr_alternative "length"
5259 (if_then_else (match_operand 2 "m16_uimm8_1")
5263 (define_expand "sle<u>"
5264 [(set (match_operand:SI 0 "register_operand")
5265 (any_le:SI (match_dup 1)
5268 { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
5270 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>"
5271 [(set (match_operand:GPR2 0 "register_operand" "=d")
5272 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5273 (match_operand:GPR 2 "sle_operand" "")))]
5276 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5277 return "slt<u>\t%0,%1,%2";
5279 [(set_attr "type" "slt")
5280 (set_attr "mode" "<GPR:MODE>")])
5282 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>_mips16"
5283 [(set (match_operand:GPR2 0 "register_operand" "=t")
5284 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5285 (match_operand:GPR 2 "sle_operand" "")))]
5288 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5289 return "slt<u>\t%1,%2";
5291 [(set_attr "type" "slt")
5292 (set_attr "mode" "<GPR:MODE>")
5293 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
5298 ;; ....................
5300 ;; FLOATING POINT COMPARISONS
5302 ;; ....................
5304 (define_insn "s<code>_<mode>"
5305 [(set (match_operand:CC 0 "register_operand" "=z")
5306 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5307 (match_operand:SCALARF 2 "register_operand" "f")))]
5309 "c.<fcond>.<fmt>\t%Z0%1,%2"
5310 [(set_attr "type" "fcmp")
5311 (set_attr "mode" "FPSW")])
5313 (define_insn "s<code>_<mode>"
5314 [(set (match_operand:CC 0 "register_operand" "=z")
5315 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5316 (match_operand:SCALARF 2 "register_operand" "f")))]
5318 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
5319 [(set_attr "type" "fcmp")
5320 (set_attr "mode" "FPSW")])
5323 ;; ....................
5325 ;; UNCONDITIONAL BRANCHES
5327 ;; ....................
5329 ;; Unconditional branches.
5333 (label_ref (match_operand 0 "" "")))]
5338 if (get_attr_length (insn) <= 8)
5339 return "%*b\t%l0%/";
5342 output_asm_insn (mips_output_load_label (), operands);
5343 return "%*jr\t%@%/%]";
5347 return "%*j\t%l0%/";
5349 [(set_attr "type" "jump")
5350 (set_attr "mode" "none")
5351 (set (attr "length")
5352 ;; We can't use `j' when emitting PIC. Emit a branch if it's
5353 ;; in range, otherwise load the address of the branch target into
5354 ;; $at and then jump to it.
5356 (ior (eq (symbol_ref "flag_pic") (const_int 0))
5357 (lt (abs (minus (match_dup 0)
5358 (plus (pc) (const_int 4))))
5359 (const_int 131072)))
5360 (const_int 4) (const_int 16)))])
5362 ;; We need a different insn for the mips16, because a mips16 branch
5363 ;; does not have a delay slot.
5367 (label_ref (match_operand 0 "" "")))]
5370 [(set_attr "type" "branch")
5371 (set_attr "mode" "none")])
5373 (define_expand "indirect_jump"
5374 [(set (pc) (match_operand 0 "register_operand"))]
5377 operands[0] = force_reg (Pmode, operands[0]);
5378 if (Pmode == SImode)
5379 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
5381 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
5385 (define_insn "indirect_jump<mode>"
5386 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
5389 [(set_attr "type" "jump")
5390 (set_attr "mode" "none")])
5392 (define_expand "tablejump"
5394 (match_operand 0 "register_operand"))
5395 (use (label_ref (match_operand 1 "")))]
5398 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
5399 operands[0] = expand_binop (Pmode, add_optab,
5400 convert_to_mode (Pmode, operands[0], false),
5401 gen_rtx_LABEL_REF (Pmode, operands[1]),
5403 else if (TARGET_GPWORD)
5404 operands[0] = expand_binop (Pmode, add_optab, operands[0],
5405 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
5406 else if (TARGET_RTP_PIC)
5408 /* When generating RTP PIC, we use case table entries that are relative
5409 to the start of the function. Add the function's address to the
5411 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5412 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
5413 start, 0, 0, OPTAB_WIDEN);
5416 if (Pmode == SImode)
5417 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
5419 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
5423 (define_insn "tablejump<mode>"
5425 (match_operand:P 0 "register_operand" "d"))
5426 (use (label_ref (match_operand 1 "" "")))]
5429 [(set_attr "type" "jump")
5430 (set_attr "mode" "none")])
5432 ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
5433 ;; While it is possible to either pull it off the stack (in the
5434 ;; o32 case) or recalculate it given t9 and our target label,
5435 ;; it takes 3 or 4 insns to do so.
5437 (define_expand "builtin_setjmp_setup"
5438 [(use (match_operand 0 "register_operand"))]
5443 addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
5444 mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
5448 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
5449 ;; that older code did recalculate the gp from $25. Continue to jump through
5450 ;; $25 for compatibility (we lose nothing by doing so).
5452 (define_expand "builtin_longjmp"
5453 [(use (match_operand 0 "register_operand"))]
5456 /* The elements of the buffer are, in order: */
5457 int W = GET_MODE_SIZE (Pmode);
5458 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5459 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
5460 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
5461 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
5462 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5463 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
5464 The target is bound to be using $28 as the global pointer
5465 but the current function might not be. */
5466 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
5468 /* This bit is similar to expand_builtin_longjmp except that it
5469 restores $gp as well. */
5470 mips_emit_move (hard_frame_pointer_rtx, fp);
5471 mips_emit_move (pv, lab);
5472 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5473 mips_emit_move (gp, gpv);
5474 emit_use (hard_frame_pointer_rtx);
5475 emit_use (stack_pointer_rtx);
5477 emit_indirect_jump (pv);
5482 ;; ....................
5484 ;; Function prologue/epilogue
5486 ;; ....................
5489 (define_expand "prologue"
5493 mips_expand_prologue ();
5497 ;; Block any insns from being moved before this point, since the
5498 ;; profiling call to mcount can use various registers that aren't
5499 ;; saved or used to pass arguments.
5501 (define_insn "blockage"
5502 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
5505 [(set_attr "type" "ghost")
5506 (set_attr "mode" "none")])
5508 (define_expand "epilogue"
5512 mips_expand_epilogue (false);
5516 (define_expand "sibcall_epilogue"
5520 mips_expand_epilogue (true);
5524 ;; Trivial return. Make it look like a normal return insn as that
5525 ;; allows jump optimizations to work better.
5527 (define_expand "return"
5529 "mips_can_use_return_insn ()"
5530 { mips_expand_before_return (); })
5532 (define_insn "*return"
5534 "mips_can_use_return_insn ()"
5536 [(set_attr "type" "jump")
5537 (set_attr "mode" "none")])
5541 (define_insn "return_internal"
5543 (use (match_operand 0 "pmode_register_operand" ""))]
5546 [(set_attr "type" "jump")
5547 (set_attr "mode" "none")])
5549 ;; This is used in compiling the unwind routines.
5550 (define_expand "eh_return"
5551 [(use (match_operand 0 "general_operand"))]
5554 if (GET_MODE (operands[0]) != word_mode)
5555 operands[0] = convert_to_mode (word_mode, operands[0], 0);
5557 emit_insn (gen_eh_set_lr_di (operands[0]));
5559 emit_insn (gen_eh_set_lr_si (operands[0]));
5563 ;; Clobber the return address on the stack. We can't expand this
5564 ;; until we know where it will be put in the stack frame.
5566 (define_insn "eh_set_lr_si"
5567 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5568 (clobber (match_scratch:SI 1 "=&d"))]
5572 (define_insn "eh_set_lr_di"
5573 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5574 (clobber (match_scratch:DI 1 "=&d"))]
5579 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
5580 (clobber (match_scratch 1))]
5584 mips_set_return_address (operands[0], operands[1]);
5588 (define_expand "exception_receiver"
5592 /* See the comment above load_call<mode> for details. */
5593 emit_insn (gen_set_got_version ());
5595 /* If we have a call-clobbered $gp, restore it from its save slot. */
5596 if (HAVE_restore_gp)
5597 emit_insn (gen_restore_gp ());
5601 (define_expand "nonlocal_goto_receiver"
5605 /* See the comment above load_call<mode> for details. */
5606 emit_insn (gen_set_got_version ());
5610 ;; Restore $gp from its .cprestore stack slot. The instruction remains
5611 ;; volatile until all uses of $28 are exposed.
5612 (define_insn_and_split "restore_gp"
5614 (unspec_volatile:SI [(const_int 0)] UNSPEC_RESTORE_GP))
5615 (clobber (match_scratch:SI 0 "=&d"))]
5616 "TARGET_CALL_CLOBBERED_GP"
5618 "&& reload_completed"
5621 mips_restore_gp (operands[0]);
5624 [(set_attr "type" "load")
5625 (set_attr "length" "12")])
5628 ;; ....................
5632 ;; ....................
5634 ;; Instructions to load a call address from the GOT. The address might
5635 ;; point to a function or to a lazy binding stub. In the latter case,
5636 ;; the stub will use the dynamic linker to resolve the function, which
5637 ;; in turn will change the GOT entry to point to the function's real
5640 ;; This means that every call, even pure and constant ones, can
5641 ;; potentially modify the GOT entry. And once a stub has been called,
5642 ;; we must not call it again.
5644 ;; We represent this restriction using an imaginary, fixed, call-saved
5645 ;; register called GOT_VERSION_REGNUM. The idea is to make the register
5646 ;; live throughout the function and to change its value after every
5647 ;; potential call site. This stops any rtx value that uses the register
5648 ;; from being computed before an earlier call. To do this, we:
5650 ;; - Ensure that the register is live on entry to the function,
5651 ;; so that it is never thought to be used uninitalized.
5653 ;; - Ensure that the register is live on exit from the function,
5654 ;; so that it is live throughout.
5656 ;; - Make each call (lazily-bound or not) use the current value
5657 ;; of GOT_VERSION_REGNUM, so that updates of the register are
5658 ;; not moved across call boundaries.
5660 ;; - Add "ghost" definitions of the register to the beginning of
5661 ;; blocks reached by EH and ABNORMAL_CALL edges, because those
5662 ;; edges may involve calls that normal paths don't. (E.g. the
5663 ;; unwinding code that handles a non-call exception may change
5664 ;; lazily-bound GOT entries.) We do this by making the
5665 ;; exception_receiver and nonlocal_goto_receiver expanders emit
5666 ;; a set_got_version instruction.
5668 ;; - After each call (lazily-bound or not), use a "ghost"
5669 ;; update_got_version instruction to change the register's value.
5670 ;; This instruction mimics the _possible_ effect of the dynamic
5671 ;; resolver during the call and it remains live even if the call
5672 ;; itself becomes dead.
5674 ;; - Leave GOT_VERSION_REGNUM out of all register classes.
5675 ;; The register is therefore not a valid register_operand
5676 ;; and cannot be moved to or from other registers.
5678 ;; Convenience expander that generates the rhs of a load_call<mode> insn.
5679 (define_expand "unspec_call<mode>"
5680 [(unspec:P [(match_operand:P 0)
5682 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL)])
5684 (define_insn "load_call<mode>"
5685 [(set (match_operand:P 0 "register_operand" "=d")
5686 (unspec:P [(match_operand:P 1 "register_operand" "d")
5687 (match_operand:P 2 "immediate_operand" "")
5688 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL))]
5690 "<load>\t%0,%R2(%1)"
5691 [(set_attr "got" "load")
5692 (set_attr "mode" "<MODE>")])
5694 (define_insn "set_got_version"
5695 [(set (reg:SI GOT_VERSION_REGNUM)
5696 (unspec_volatile:SI [(const_int 0)] UNSPEC_SET_GOT_VERSION))]
5699 [(set_attr "type" "ghost")])
5701 (define_insn "update_got_version"
5702 [(set (reg:SI GOT_VERSION_REGNUM)
5703 (unspec:SI [(reg:SI GOT_VERSION_REGNUM)] UNSPEC_UPDATE_GOT_VERSION))]
5706 [(set_attr "type" "ghost")])
5708 ;; Sibling calls. All these patterns use jump instructions.
5710 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
5711 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
5712 ;; is defined in terms of call_insn_operand, the same is true of the
5715 ;; When we use an indirect jump, we need a register that will be
5716 ;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
5717 ;; us to use $25 for this purpose -- and $25 is never clobbered by the
5718 ;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
5721 (define_expand "sibcall"
5722 [(parallel [(call (match_operand 0 "")
5723 (match_operand 1 ""))
5724 (use (match_operand 2 "")) ;; next_arg_reg
5725 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5728 mips_expand_call (MIPS_CALL_SIBCALL, NULL_RTX, XEXP (operands[0], 0),
5729 operands[1], operands[2], false);
5733 (define_insn "sibcall_internal"
5734 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
5735 (match_operand 1 "" ""))]
5736 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5737 { return MIPS_CALL ("j", operands, 0); }
5738 [(set_attr "type" "call")])
5740 (define_expand "sibcall_value"
5741 [(parallel [(set (match_operand 0 "")
5742 (call (match_operand 1 "")
5743 (match_operand 2 "")))
5744 (use (match_operand 3 ""))])] ;; next_arg_reg
5747 mips_expand_call (MIPS_CALL_SIBCALL, operands[0], XEXP (operands[1], 0),
5748 operands[2], operands[3], false);
5752 (define_insn "sibcall_value_internal"
5753 [(set (match_operand 0 "register_operand" "")
5754 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5755 (match_operand 2 "" "")))]
5756 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5757 { return MIPS_CALL ("j", operands, 1); }
5758 [(set_attr "type" "call")])
5760 (define_insn "sibcall_value_multiple_internal"
5761 [(set (match_operand 0 "register_operand" "")
5762 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5763 (match_operand 2 "" "")))
5764 (set (match_operand 3 "register_operand" "")
5765 (call (mem:SI (match_dup 1))
5767 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5768 { return MIPS_CALL ("j", operands, 1); }
5769 [(set_attr "type" "call")])
5771 (define_expand "call"
5772 [(parallel [(call (match_operand 0 "")
5773 (match_operand 1 ""))
5774 (use (match_operand 2 "")) ;; next_arg_reg
5775 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5778 mips_expand_call (MIPS_CALL_NORMAL, NULL_RTX, XEXP (operands[0], 0),
5779 operands[1], operands[2], false);
5783 ;; This instruction directly corresponds to an assembly-language "jal".
5784 ;; There are four cases:
5787 ;; Both symbolic and register destinations are OK. The pattern
5788 ;; always expands to a single mips instruction.
5790 ;; - -mabicalls/-mno-explicit-relocs:
5791 ;; Again, both symbolic and register destinations are OK.
5792 ;; The call is treated as a multi-instruction black box.
5794 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
5795 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
5798 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
5799 ;; Only "jal $25" is allowed. The call is actually two instructions:
5800 ;; "jalr $25" followed by an insn to reload $gp.
5802 ;; In the last case, we can generate the individual instructions with
5803 ;; a define_split. There are several things to be wary of:
5805 ;; - We can't expose the load of $gp before reload. If we did,
5806 ;; it might get removed as dead, but reload can introduce new
5807 ;; uses of $gp by rematerializing constants.
5809 ;; - We shouldn't restore $gp after calls that never return.
5810 ;; It isn't valid to insert instructions between a noreturn
5811 ;; call and the following barrier.
5813 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
5814 ;; instruction preserves $gp and so have no effect on its liveness.
5815 ;; But once we generate the separate insns, it becomes obvious that
5816 ;; $gp is not live on entry to the call.
5818 ;; ??? The operands[2] = insn check is a hack to make the original insn
5819 ;; available to the splitter.
5820 (define_insn_and_split "call_internal"
5821 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
5822 (match_operand 1 "" ""))
5823 (clobber (reg:SI 31))]
5825 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
5826 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
5829 mips_split_call (operands[2], gen_call_split (operands[0], operands[1]));
5832 [(set_attr "jal" "indirect,direct")])
5834 (define_insn "call_split"
5835 [(call (mem:SI (match_operand 0 "call_insn_operand" "cS"))
5836 (match_operand 1 "" ""))
5837 (clobber (reg:SI 31))
5838 (clobber (reg:SI 28))]
5839 "TARGET_SPLIT_CALLS"
5840 { return MIPS_CALL ("jal", operands, 0); }
5841 [(set_attr "type" "call")])
5843 ;; A pattern for calls that must be made directly. It is used for
5844 ;; MIPS16 calls that the linker may need to redirect to a hard-float
5845 ;; stub; the linker relies on the call relocation type to detect when
5846 ;; such redirection is needed.
5847 (define_insn_and_split "call_internal_direct"
5848 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
5851 (clobber (reg:SI 31))]
5853 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
5854 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
5857 mips_split_call (operands[2],
5858 gen_call_direct_split (operands[0], operands[1]));
5861 [(set_attr "type" "call")])
5863 (define_insn "call_direct_split"
5864 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
5867 (clobber (reg:SI 31))
5868 (clobber (reg:SI 28))]
5869 "TARGET_SPLIT_CALLS"
5870 { return MIPS_CALL ("jal", operands, 0); }
5871 [(set_attr "type" "call")])
5873 (define_expand "call_value"
5874 [(parallel [(set (match_operand 0 "")
5875 (call (match_operand 1 "")
5876 (match_operand 2 "")))
5877 (use (match_operand 3 ""))])] ;; next_arg_reg
5880 mips_expand_call (MIPS_CALL_NORMAL, operands[0], XEXP (operands[1], 0),
5881 operands[2], operands[3], false);
5885 ;; See comment for call_internal.
5886 (define_insn_and_split "call_value_internal"
5887 [(set (match_operand 0 "register_operand" "")
5888 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5889 (match_operand 2 "" "")))
5890 (clobber (reg:SI 31))]
5892 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
5893 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
5896 mips_split_call (operands[3],
5897 gen_call_value_split (operands[0], operands[1],
5901 [(set_attr "jal" "indirect,direct")])
5903 (define_insn "call_value_split"
5904 [(set (match_operand 0 "register_operand" "")
5905 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
5906 (match_operand 2 "" "")))
5907 (clobber (reg:SI 31))
5908 (clobber (reg:SI 28))]
5909 "TARGET_SPLIT_CALLS"
5910 { return MIPS_CALL ("jal", operands, 1); }
5911 [(set_attr "type" "call")])
5913 ;; See call_internal_direct.
5914 (define_insn_and_split "call_value_internal_direct"
5915 [(set (match_operand 0 "register_operand")
5916 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
5919 (clobber (reg:SI 31))]
5921 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
5922 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
5925 mips_split_call (operands[3],
5926 gen_call_value_direct_split (operands[0], operands[1],
5930 [(set_attr "type" "call")])
5932 (define_insn "call_value_direct_split"
5933 [(set (match_operand 0 "register_operand")
5934 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
5937 (clobber (reg:SI 31))
5938 (clobber (reg:SI 28))]
5939 "TARGET_SPLIT_CALLS"
5940 { return MIPS_CALL ("jal", operands, 1); }
5941 [(set_attr "type" "call")])
5943 ;; See comment for call_internal.
5944 (define_insn_and_split "call_value_multiple_internal"
5945 [(set (match_operand 0 "register_operand" "")
5946 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5947 (match_operand 2 "" "")))
5948 (set (match_operand 3 "register_operand" "")
5949 (call (mem:SI (match_dup 1))
5951 (clobber (reg:SI 31))]
5953 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
5954 "reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
5957 mips_split_call (operands[4],
5958 gen_call_value_multiple_split (operands[0], operands[1],
5959 operands[2], operands[3]));
5962 [(set_attr "jal" "indirect,direct")])
5964 (define_insn "call_value_multiple_split"
5965 [(set (match_operand 0 "register_operand" "")
5966 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
5967 (match_operand 2 "" "")))
5968 (set (match_operand 3 "register_operand" "")
5969 (call (mem:SI (match_dup 1))
5971 (clobber (reg:SI 31))
5972 (clobber (reg:SI 28))]
5973 "TARGET_SPLIT_CALLS"
5974 { return MIPS_CALL ("jal", operands, 1); }
5975 [(set_attr "type" "call")])
5977 ;; Call subroutine returning any type.
5979 (define_expand "untyped_call"
5980 [(parallel [(call (match_operand 0 "")
5982 (match_operand 1 "")
5983 (match_operand 2 "")])]
5988 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
5990 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5992 rtx set = XVECEXP (operands[2], 0, i);
5993 mips_emit_move (SET_DEST (set), SET_SRC (set));
5996 emit_insn (gen_blockage ());
6001 ;; ....................
6005 ;; ....................
6009 (define_insn "prefetch"
6010 [(prefetch (match_operand:QI 0 "address_operand" "p")
6011 (match_operand 1 "const_int_operand" "n")
6012 (match_operand 2 "const_int_operand" "n"))]
6013 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
6015 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
6016 return "pref\t%1,%a0";
6018 [(set_attr "type" "prefetch")])
6020 (define_insn "*prefetch_indexed_<mode>"
6021 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
6022 (match_operand:P 1 "register_operand" "d"))
6023 (match_operand 2 "const_int_operand" "n")
6024 (match_operand 3 "const_int_operand" "n"))]
6025 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
6027 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
6028 return "prefx\t%2,%1(%0)";
6030 [(set_attr "type" "prefetchx")])
6036 [(set_attr "type" "nop")
6037 (set_attr "mode" "none")])
6039 ;; Like nop, but commented out when outside a .set noreorder block.
6040 (define_insn "hazard_nop"
6049 [(set_attr "type" "nop")])
6051 ;; MIPS4 Conditional move instructions.
6053 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
6054 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6056 (match_operator:MOVECC 4 "equality_operator"
6057 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6059 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
6060 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
6065 [(set_attr "type" "condmove")
6066 (set_attr "mode" "<GPR:MODE>")])
6068 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
6069 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
6070 (if_then_else:SCALARF
6071 (match_operator:MOVECC 4 "equality_operator"
6072 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6074 (match_operand:SCALARF 2 "register_operand" "f,0")
6075 (match_operand:SCALARF 3 "register_operand" "0,f")))]
6076 "ISA_HAS_FP_CONDMOVE"
6078 mov%T4.<fmt>\t%0,%2,%1
6079 mov%t4.<fmt>\t%0,%3,%1"
6080 [(set_attr "type" "condmove")
6081 (set_attr "mode" "<SCALARF:MODE>")])
6083 ;; These are the main define_expand's used to make conditional moves.
6085 (define_expand "mov<mode>cc"
6086 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6087 (set (match_operand:GPR 0 "register_operand")
6088 (if_then_else:GPR (match_dup 5)
6089 (match_operand:GPR 2 "reg_or_0_operand")
6090 (match_operand:GPR 3 "reg_or_0_operand")))]
6093 mips_expand_conditional_move (operands);
6097 (define_expand "mov<mode>cc"
6098 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6099 (set (match_operand:SCALARF 0 "register_operand")
6100 (if_then_else:SCALARF (match_dup 5)
6101 (match_operand:SCALARF 2 "register_operand")
6102 (match_operand:SCALARF 3 "register_operand")))]
6103 "ISA_HAS_FP_CONDMOVE"
6105 mips_expand_conditional_move (operands);
6110 ;; ....................
6112 ;; mips16 inline constant tables
6114 ;; ....................
6117 (define_insn "consttable_int"
6118 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
6119 (match_operand 1 "const_int_operand" "")]
6120 UNSPEC_CONSTTABLE_INT)]
6123 assemble_integer (operands[0], INTVAL (operands[1]),
6124 BITS_PER_UNIT * INTVAL (operands[1]), 1);
6127 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
6129 (define_insn "consttable_float"
6130 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
6131 UNSPEC_CONSTTABLE_FLOAT)]
6136 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
6137 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
6138 assemble_real (d, GET_MODE (operands[0]),
6139 GET_MODE_BITSIZE (GET_MODE (operands[0])));
6142 [(set (attr "length")
6143 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
6145 (define_insn "align"
6146 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
6149 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
6152 [(match_operand 0 "small_data_pattern")]
6155 { operands[0] = mips_rewrite_small_data (operands[0]); })
6158 ;; ....................
6160 ;; MIPS16e Save/Restore
6162 ;; ....................
6165 (define_insn "*mips16e_save_restore"
6166 [(match_parallel 0 ""
6167 [(set (match_operand:SI 1 "register_operand")
6168 (plus:SI (match_dup 1)
6169 (match_operand:SI 2 "const_int_operand")))])]
6170 "operands[1] == stack_pointer_rtx
6171 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)"
6172 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); }
6173 [(set_attr "type" "arith")
6174 (set_attr "extended_mips16" "yes")])
6176 ;; Thread-Local Storage
6178 ;; The TLS base pointer is accessed via "rdhwr $3, $29". No current
6179 ;; MIPS architecture defines this register, and no current
6180 ;; implementation provides it; instead, any OS which supports TLS is
6181 ;; expected to trap and emulate this instruction. rdhwr is part of the
6182 ;; MIPS 32r2 specification, but we use it on any architecture because
6183 ;; we expect it to be emulated. Use .set to force the assembler to
6186 ;; We do not use a constraint to force the destination to be $3
6187 ;; because $3 can appear explicitly as a function return value.
6188 ;; If we leave the use of $3 implicit in the constraints until
6189 ;; reload, we may end up making a $3 return value live across
6190 ;; the instruction, leading to a spill failure when reloading it.
6191 (define_insn_and_split "tls_get_tp_<mode>"
6192 [(set (match_operand:P 0 "register_operand" "=d")
6193 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6194 (clobber (reg:P TLS_GET_TP_REGNUM))]
6195 "HAVE_AS_TLS && !TARGET_MIPS16"
6197 "&& reload_completed"
6198 [(set (reg:P TLS_GET_TP_REGNUM)
6199 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6200 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
6202 [(set_attr "type" "unknown")
6203 ; Since rdhwr always generates a trap for now, putting it in a delay
6204 ; slot would make the kernel's emulation of it much slower.
6205 (set_attr "can_delay" "no")
6206 (set_attr "mode" "<MODE>")
6207 (set_attr "length" "8")])
6209 (define_insn "*tls_get_tp_<mode>_split"
6210 [(set (reg:P TLS_GET_TP_REGNUM)
6211 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))]
6212 "HAVE_AS_TLS && !TARGET_MIPS16"
6213 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t$3,$29\;.set\tpop"
6214 [(set_attr "type" "unknown")
6215 ; See tls_get_tp_<mode>
6216 (set_attr "can_delay" "no")
6217 (set_attr "mode" "<MODE>")])
6219 ;; Synchronization instructions.
6223 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
6225 (include "mips-ps-3d.md")
6227 ; The MIPS DSP Instructions.
6229 (include "mips-dsp.md")
6231 ; The MIPS DSP REV 2 Instructions.
6233 (include "mips-dspr2.md")
6235 ; MIPS fixed-point instructions.
6236 (include "mips-fixed.md")
6238 ; ST-Microelectronics Loongson-2E/2F-specific patterns.
6239 (include "loongson.md")