gcc/testsuite/gcc.target/powerpc/le-altivec-consts.c

   1 /* { dg-do run { target vmx_hw } } */
   2 /* { dg-do compile } */
   3 /* { dg-require-effective-target powerpc_altivec_ok } */
   4 /* { dg-options "-maltivec -mabi=altivec -O2" } */
   5
   6 /* Check that "easy" AltiVec constants are correctly synthesized.  */
   7
   8 extern void abort (void);
   9 extern int memcmp (const void *, const void *, __SIZE_TYPE__);
  10
  11 typedef __attribute__ ((vector_size (16))) unsigned char v16qi;
  12 typedef __attribute__ ((vector_size (16))) unsigned short v8hi;
  13 typedef __attribute__ ((vector_size (16))) unsigned int v4si;
  14
  15 typedef __attribute__((aligned(16))) char c16[16];
  16 typedef __attribute__((aligned(16))) short s8[8];
  17 typedef __attribute__((aligned(16))) int i4[4];
  18
  19 #define V16QI(V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16)   \
  20   v16qi v = {V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16};   \
  21   static c16 w = {V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16}; \
  22   check_v16qi (v, w);
  23
  24 #define V8HI(V1,V2,V3,V4,V5,V6,V7,V8)           \
  25   v8hi v = {V1,V2,V3,V4,V5,V6,V7,V8};           \
  26   static s8 w = {V1,V2,V3,V4,V5,V6,V7,V8};      \
  27   check_v8hi (v, w);
  28
  29 #define V4SI(V1,V2,V3,V4)       \
  30   v4si v = {V1,V2,V3,V4};       \
  31   static i4 w = {V1,V2,V3,V4};  \
  32   check_v4si (v, w);
  33
  34 \f
  35 /* Use three different check functions for each mode-instruction pair.
  36    The callers have no typecasting and no addressable vectors, to make
  37    the test more robust.  */
  38
  39 void __attribute__ ((noinline)) check_v16qi (v16qi v1, char *v2)
  40 {
  41   if (memcmp (&v1, v2, 16))
  42     abort ();
  43 }
  44
  45 void __attribute__ ((noinline)) check_v8hi (v8hi v1, short *v2)
  46 {
  47   if (memcmp (&v1, v2, 16))
  48     abort ();
  49 }
  50
  51 void __attribute__ ((noinline)) check_v4si (v4si v1, int *v2)
  52 {
  53   if (memcmp (&v1, v2, 16))
  54     abort ();
  55 }
  56
  57 \f
  58 /* V16QI tests.  */
  59
  60 void v16qi_vspltisb ()
  61 {
  62   V16QI (15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15);
  63 }
  64
  65 void v16qi_vspltisb_neg ()
  66 {
  67   V16QI (-5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5);
  68 }
  69
  70 void v16qi_vspltisb_addself ()
  71 {
  72   V16QI (30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30);
  73 }
  74
  75 void v16qi_vspltisb_neg_addself ()
  76 {
  77   V16QI (-24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24);
  78 }
  79
  80 void v16qi_vspltish ()
  81 {
  82   V16QI (15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0);
  83 }
  84
  85 void v16qi_vspltish_addself ()
  86 {
  87   V16QI (30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0);
  88 }
  89
  90 void v16qi_vspltish_neg ()
  91 {
  92   V16QI (-5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1);
  93 }
  94
  95 void v16qi_vspltisw ()
  96 {
  97   V16QI (15, 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0);
  98 }
  99
 100 void v16qi_vspltisw_addself ()
 101 {
 102   V16QI (30, 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0);
 103 }
 104
 105 void v16qi_vspltisw_neg ()
 106 {
 107   V16QI (-5, -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1);
 108 }
 109
 110 \f
 111 /* V8HI tests. */
 112
 113 void v8hi_vspltisb ()
 114 {
 115   V8HI (0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F);
 116 }
 117
 118 void v8hi_vspltisb_addself ()
 119 {
 120   V8HI (0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E);
 121 }
 122
 123 void v8hi_vspltisb_neg ()
 124 {
 125   V8HI (0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB);
 126 }
 127
 128 void v8hi_vspltish ()
 129 {
 130   V8HI (15, 15, 15, 15, 15, 15, 15, 15);
 131 }
 132
 133 void v8hi_vspltish_neg ()
 134 {
 135   V8HI (-5, -5, -5, -5, -5, -5, -5, -5);
 136 }
 137
 138 void v8hi_vspltish_addself ()
 139 {
 140   V8HI (30, 30, 30, 30, 30, 30, 30, 30);
 141 }
 142
 143 void v8hi_vspltish_neg_addself ()
 144 {
 145   V8HI (-24, -24, -24, -24, -24, -24, -24, -24);
 146 }
 147
 148 void v8hi_vspltisw ()
 149 {
 150   V8HI (15, 0, 15, 0, 15, 0, 15, 0);
 151 }
 152
 153 void v8hi_vspltisw_addself ()
 154 {
 155   V8HI (30, 0, 30, 0, 30, 0, 30, 0);
 156 }
 157
 158 void v8hi_vspltisw_neg ()
 159 {
 160   V8HI (-5, -1, -5, -1, -5, -1, -5, -1);
 161 }
 162
 163 /* V4SI tests. */
 164
 165 void v4si_vspltisb ()
 166 {
 167   V4SI (0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F);
 168 }
 169
 170 void v4si_vspltisb_addself ()
 171 {
 172   V4SI (0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E);
 173 }
 174
 175 void v4si_vspltisb_neg ()
 176 {
 177   V4SI (0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB);
 178 }
 179
 180 void v4si_vspltish ()
 181 {
 182   V4SI (0x000F000F, 0x000F000F, 0x000F000F, 0x000F000F);
 183 }
 184
 185 void v4si_vspltish_addself ()
 186 {
 187   V4SI (0x001E001E, 0x001E001E, 0x001E001E, 0x001E001E);
 188 }
 189
 190 void v4si_vspltish_neg ()
 191 {
 192   V4SI (0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB);
 193 }
 194
 195 void v4si_vspltisw ()
 196 {
 197   V4SI (15, 15, 15, 15);
 198 }
 199
 200 void v4si_vspltisw_neg ()
 201 {
 202   V4SI (-5, -5, -5, -5);
 203 }
 204
 205 void v4si_vspltisw_addself ()
 206 {
 207   V4SI (30, 30, 30, 30);
 208 }
 209
 210 void v4si_vspltisw_neg_addself ()
 211 {
 212   V4SI (-24, -24, -24, -24);
 213 }
 214
 215 \f
 216
 217 int main ()
 218 {
 219   v16qi_vspltisb ();
 220   v16qi_vspltisb_neg ();
 221   v16qi_vspltisb_addself ();
 222   v16qi_vspltisb_neg_addself ();
 223   v16qi_vspltish ();
 224   v16qi_vspltish_addself ();
 225   v16qi_vspltish_neg ();
 226   v16qi_vspltisw ();
 227   v16qi_vspltisw_addself ();
 228   v16qi_vspltisw_neg ();
 229
 230   v8hi_vspltisb ();
 231   v8hi_vspltisb_addself ();
 232   v8hi_vspltisb_neg ();
 233   v8hi_vspltish ();
 234   v8hi_vspltish_neg ();
 235   v8hi_vspltish_addself ();
 236   v8hi_vspltish_neg_addself ();
 237   v8hi_vspltisw ();
 238   v8hi_vspltisw_addself ();
 239   v8hi_vspltisw_neg ();
 240
 241   v4si_vspltisb ();
 242   v4si_vspltisb_addself ();
 243   v4si_vspltisb_neg ();
 244   v4si_vspltish ();
 245   v4si_vspltish_addself ();
 246   v4si_vspltish_neg ();
 247   v4si_vspltisw ();
 248   v4si_vspltisw_neg ();
 249   v4si_vspltisw_addself ();
 250   v4si_vspltisw_neg_addself ();
 251   return 0;
 252 }
 253
 254 /* { dg-final { scan-assembler-not "lvx" { target { powerpc*le-*-* } } } } */