1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 88, 93-97, 1998 Free Software Foundation, Inc.
4 ;; This file is part of GNU CC.
6 ;; GNU CC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GNU CC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GNU CC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
19 ;; Boston, MA 02111-1307, USA.
21 ;;- Information about MCF5200 port.
23 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
24 ;;- 68k ISA. Differences include reduced support for byte and word
25 ;;- operands and the removal of BCD, bitfield, rotate, and integer
26 ;;- divide instructions. The TARGET_5200 flag turns the use of the
27 ;;- removed opcodes and addressing modes off.
31 ;;- instruction definitions
33 ;;- @@The original PO technology requires these to be ordered by speed,
34 ;;- @@ so that assigner will pick the fastest.
36 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
38 ;;- When naming insn's (operand 0 of define_insn) be careful about using
39 ;;- names from other targets machine descriptions.
41 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
42 ;;- updates for most instructions.
44 ;;- Operand classes for the register allocator:
45 ;;- 'a' one of the address registers can be used.
46 ;;- 'd' one of the data registers can be used.
47 ;;- 'f' one of the m68881 registers can be used
48 ;;- 'r' either a data or an address register can be used.
49 ;;- 'x' if one of the Sun FPA registers
50 ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
52 ;;- Immediate Floating point operator constraints
53 ;;- 'G' a floating point constant that is *NOT* one of the standard
54 ;; 68881 constant values (to force calling output_move_const_double
55 ;; to get it from rom if it is a 68881 constant).
56 ;;- 'H' one of the standard FPA constant values
58 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
61 ;;- Immediate integer operand constraints:
63 ;;- 'J' -32768 .. 32767
64 ;;- 'K' all integers EXCEPT -128 .. 127
66 ;;- 'M' all integers EXCEPT -256 .. 255
72 ;;- "%." size separator ("." or "") move%.l d0,d1
73 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
74 ;;- "%-" push operand "sp@-" move%.l d0,%-
75 ;;- "%+" pop operand "sp@+" move%.l d0,%+
76 ;;- "%@" top of stack "sp@" move%.l d0,%@
77 ;;- "%!" fpcr register
78 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
79 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
82 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
83 ;; operand 1 is the argument for `sin'.
84 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
85 ;; operand 1 is the argument for `cos'.
87 ;;- Information about 68040 port.
89 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
90 ;;- be emulated in software by the OS. It is faster to avoid these
91 ;;- instructions and issue a library call rather than trapping into
92 ;;- the kernel. The affected instructions are fintrz and fscale. The
93 ;;- TARGET_68040 flag turns the use of the opcodes off.
95 ;;- The '040 also implements a set of new floating-point instructions
96 ;;- which specify the rounding precision in the opcode. This finally
97 ;;- permit the 68k series to be truly IEEE compliant, and solves all
98 ;;- issues of excess precision accumulating in the extended registers.
99 ;;- By default, GCC does not use these instructions, since such code will
100 ;;- not run on an '030. To use these instructions, use the -m68040-only
101 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
102 ;;- you can make these instructions the default.
104 ;;- These new instructions aren't directly in the md. They are brought
105 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
108 ;;- Information about 68060 port.
110 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
111 ;;- be emulated in software by the OS. It is faster to avoid these
112 ;;- instructions and issue a library call rather than trapping into
113 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
114 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
115 ;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
117 ;;- FPA port explanation:
119 ;;- Usage of the Sun FPA and the 68881 together
121 ;;- The current port of gcc to the sun fpa disallows use of the m68881
122 ;;- instructions completely if code is targeted for the fpa. This is
123 ;;- for the following reasons:
125 ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
126 ;;- can, the 68881 otherwise, and data registers only if you are
127 ;;- forced to it) is a bitch with the current constraint scheme,
128 ;;- especially since it would have to work for any combination of
131 ;;- 2) There are no instructions to move between the two types of
132 ;;- registers; the stack must be used as an intermediary.
134 ;;- It could indeed be done; I think the best way would be to have
135 ;;- separate patterns for TARGET_FPA (which implies a 68881),
136 ;;- TARGET_68881, and no floating point co-processor. Use
137 ;;- define_expands for all of the named instruction patterns, and
138 ;;- include code in the FPA instruction to deal with the 68881 with
139 ;;- preferences specifically set to favor the fpa. Some of this has
140 ;;- already been done:
142 ;;- 1) Separation of most of the patterns out into a TARGET_FPA
143 ;;- case and a TARGET_68881 case (the exceptions are the patterns
144 ;;- which would need one define_expand and three define_insn's under
145 ;;- it (with a lot of duplicate code between them) to replace the
146 ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the
147 ;;- first two patterns in the md.
149 ;;- Some would still have to be done:
151 ;;- 1) Add code to the fpa patterns which correspond to 68881
152 ;;- patterns to deal with the 68881 case (including preferences!).
153 ;;- What you might actually do here is combine the fpa and 68881 code
154 ;;- back together into one pattern for those instructions where it's
155 ;;- absolutely necessary and save yourself some duplicate code. I'm
156 ;;- not completely sure as to whether you could get away with doing
157 ;;- this only for the mov* insns, or if you'd have to do it for all
159 ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle
160 ;;- moving between fpa regs and 68881 regs.
162 ;;- Since the fpa is more powerful than the 68881 and also has more
163 ;;- registers, and since I think the resultant md would be medium ugly
164 ;;- (lot's of duplicate code, ugly constraint strings), I elected not
165 ;;- to do this change.
167 ;;- Another reason why someone *might* want to do the change is to
168 ;;- control which register classes are accessed in a slightly cleaner
169 ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in
170 ;;- the internals manual.
172 ;;- Yet another reason why someone might want to do this change is to
173 ;;- allow use of some of the 68881 insns which have no equivalent on
174 ;;- the fpa. The sqrt instruction comes fairly quickly to mind.
176 ;;- If this is ever done, don't forget to change sun3.h so that
177 ;;- it *will* define __HAVE_68881__ when the FPA is in use.
179 ;;- Condition code hack
181 ;;- When a floating point compare is done in the fpa, the resulting
182 ;;- condition codes are left in the fpastatus register. The values in
183 ;;- this register must be moved into the 68000 cc register before any
184 ;;- jump is executed. Once this has been done, regular jump
185 ;;- instructions are fine (ie. floating point jumps are not necessary.
186 ;;- They are only done if the cc is in the 68881).
188 ;;- The instructions that move the fpastatus register to the 68000
189 ;;- register clobber a data register (the move cannot be done direct).
190 ;;- These instructions might be bundled either with the compare
191 ;;- instruction, or the branch instruction. If we were using both the
192 ;;- fpa and the 68881 together, we would wish to only mark the
193 ;;- register clobbered if we were doing the compare in the fpa, but I
194 ;;- think that that decision (whether to clobber the register or not)
195 ;;- must be done before register allocation (makes sense) and hence we
196 ;;- can't know if the floating point compare will be done in the fpa
197 ;;- or the fp. So whenever we are asked for code that uses the fpa,
198 ;;- we will mark a data register as clobbered. This is reasonable, as
199 ;;- almost all floating point compare operations done with fpa code
200 ;;- enabled will be done in the fpa. It's even more reasonable since
201 ;;- we decided to make the 68881 and the fpa mutually exclusive.
203 ;;- We place to code to move the fpastatus register inside of a
204 ;;- define_expand so that we can do it conditionally based on whether
205 ;;- we are targeting an fpa or not.
207 ;;- This still leaves us with the question of where we wish to put the
208 ;;- code to move the fpastatus reg. If we put it in the compare
209 ;;- instruction, we can restrict the clobbering of the register to
210 ;;- floating point compares, but we can't take advantage of floating
211 ;;- point subtracts & etc. that alter the fpastatus register. If we
212 ;;- put it in the branch instruction, all branches compiled with fpa
213 ;;- code enabled will clobber a data register, but we will be able to
214 ;;- take advantage of fpa subtracts. This balance favors putting the
215 ;;- code in with the compare instruction.
217 ;;- Note that if some enterprising hacker should decide to switch
218 ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
220 ;;- Usage of the top 16 fpa registers
222 ;;- The only locations which we may transfer fpa registers 16-31 from
223 ;;- or to are the fpa registers 0-15. (68000 registers and memory
224 ;;- locations are impossible). This causes problems in gcc, which
225 ;;- assumes that mov?? instructions require no additional registers
226 ;;- (see section 11.7) and since floating point moves *must* be
227 ;;- supported into general registers (see section 12.3 under
228 ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
230 ;;- My solution was to reserve fpa0 for moves into or out of these top
231 ;;- 16 registers and to disparage the choice to reload into or out of
232 ;;- these registers as much as I could. That alternative is always
233 ;;- last in the list, so it will not be used unless all else fails. I
234 ;;- will note that according to my current information, sun's compiler
235 ;;- doesn't use these top 16 registers at all.
237 ;;- There is another possible way to do it. I *believe* that if you
238 ;;- make absolutely sure that the code will not be executed in the
239 ;;- reload pass, you can support the mov?? names with define_expands
240 ;;- which require new registers. This may be possible by the
241 ;;- appropriate juggling of constraints. I may come back to this later.
243 ;;- Usage of constant RAM
245 ;;- This has been handled correctly (I believe) but the way I've done
246 ;;- it could use a little explanation. The constant RAM can only be
247 ;;- accessed when the instruction is in "command register" mode.
248 ;;- "command register" mode means that no accessing of memory or the
249 ;;- 68000 registers is being done. This can be expressed easily in
250 ;;- constraints, so generally the mode of the instruction is
251 ;;- determined by a branch off of which_alternative. In outputting
252 ;;- instructions, a 'w' means to output an access to the constant ram
253 ;;- (if the arg is CONST_DOUBLE and is one of the available
254 ;;- constants), and 'x' means to output a register pair (if the arg is
255 ;;- a 68000 register) and a 'y' is the combination of the above two
256 ;;- processes. You use a 'y' in two operand DF instructions where you
257 ;;- *know* the other operand is an fpa register, you use an 'x' in DF
258 ;;- instructions where the arg might be a 68000 register and the
259 ;;- instruction is *not* in "command register" mode, and you use a 'w'
260 ;;- in two situations: 1) The instruction *is* in command register
261 ;;- mode (and hence won't be accessing 68000 registers), or 2) The
262 ;;- instruction is a two operand SF instruction where you know the
263 ;;- other operand is an fpa register.
265 ;;- Optimization issues
267 ;;- I actually think that I've included all of the fpa instructions
268 ;;- that should be included. Note that if someone is interested in
269 ;;- doing serious floating point work on the sun fpa, I would advise
270 ;;- the use of the "asm" instruction in gcc to allow you to use the
271 ;;- sin, cos, and exponential functions on the fpa board.
273 ;;- END FPA Explanation Section.
276 ;;- Some of these insn's are composites of several m68000 op codes.
277 ;;- The assembler (or final @@??) insures that the appropriate one is
281 [(set (match_operand:DF 0 "push_operand" "=m")
282 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
286 if (FP_REG_P (operands[1]))
287 return \"fmove%.d %f1,%0\";
288 if (FPA_REG_P (operands[1]))
289 return \"fpmove%.d %1, %x0\";
290 return output_move_double (operands);
293 (define_insn "pushdi"
294 [(set (match_operand:DI 0 "push_operand" "=m")
295 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
299 return output_move_double (operands);
302 ;; We don't want to allow a constant operand for test insns because
303 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
304 ;; be folded while optimizing anyway.
306 (define_expand "tstdi"
307 [(parallel [(set (cc0)
308 (match_operand:DI 0 "nonimmediate_operand" ""))
309 (clobber (match_scratch:SI 1 ""))
310 (clobber (match_scratch:DI 2 ""))])]
312 "m68k_last_compare_had_fp_operands = 0;")
316 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
317 (clobber (match_scratch:SI 1 "=X,d"))
318 (clobber (match_scratch:DI 2 "=d,X"))]
322 if (which_alternative == 0)
326 xoperands[0] = operands[2];
327 xoperands[1] = operands[0];
328 output_move_double (xoperands);
329 cc_status.flags |= CC_REVERSED;
330 return \"neg%.l %R2\;negx%.l %2\";
332 if (find_reg_note (insn, REG_DEAD, operands[0]))
334 cc_status.flags |= CC_REVERSED;
335 return \"neg%.l %R0\;negx%.l %0\";
339 ** 'sub' clears %1, and also clears the X cc bit
340 ** 'tst' sets the Z cc bit according to the low part of the DImode operand
341 ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
343 return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
346 (define_expand "tstsi"
348 (match_operand:SI 0 "nonimmediate_operand" ""))]
350 "m68k_last_compare_had_fp_operands = 0;")
354 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
359 /* ISI's assembler fails to handle tstl a0. */
360 if (! ADDRESS_REG_P (operands[0]))
362 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
364 return \"tst%.l %0\";
365 /* If you think that the 68020 does not support tstl a0,
366 reread page B-167 of the 68020 manual more carefully. */
367 /* On an address reg, cmpw may replace cmpl. */
369 return \"cmp%.w %0,%#0\";
371 return \"cmp%.w %#0,%0\";
375 ;; This can't use an address register, because comparisons
376 ;; with address registers as second operand always test the whole word.
377 (define_expand "tsthi"
379 (match_operand:HI 0 "nonimmediate_operand" ""))]
381 "m68k_last_compare_had_fp_operands = 0;")
385 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
389 (define_expand "tstqi"
391 (match_operand:QI 0 "nonimmediate_operand" ""))]
393 "m68k_last_compare_had_fp_operands = 0;")
397 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
401 (define_expand "tstsf"
403 (match_operand:SF 0 "general_operand" ""))]
404 "TARGET_68881 || TARGET_FPA"
407 m68k_last_compare_had_fp_operands = 1;
410 emit_insn (gen_tstsf_fpa (operands[0]));
415 (define_insn "tstsf_fpa"
417 (match_operand:SF 0 "general_operand" "xmdF"))
418 (clobber (match_scratch:SI 1 "=d"))]
420 "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
424 (match_operand:SF 0 "general_operand" "fdm"))]
428 cc_status.flags = CC_IN_68881;
429 if (FP_REG_P (operands[0]))
430 return \"ftst%.x %0\";
431 return \"ftst%.s %0\";
434 (define_expand "tstdf"
436 (match_operand:DF 0 "general_operand" ""))]
437 "TARGET_68881 || TARGET_FPA"
440 m68k_last_compare_had_fp_operands = 1;
443 emit_insn (gen_tstsf_fpa (operands[0]));
448 (define_insn "tstdf_fpa"
450 (match_operand:DF 0 "general_operand" "xrmF"))
451 (clobber (match_scratch:SI 1 "=d"))]
453 "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
457 (match_operand:DF 0 "general_operand" "fm"))]
461 cc_status.flags = CC_IN_68881;
462 if (FP_REG_P (operands[0]))
463 return \"ftst%.x %0\";
464 return \"ftst%.d %0\";
467 ;; compare instructions.
469 (define_expand "cmpdi"
472 (compare (match_operand:DI 0 "nonimmediate_operand" "")
473 (match_operand:DI 1 "general_operand" "")))
474 (clobber (match_dup 2))])]
476 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
480 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
481 (match_operand:DI 2 "general_operand" "d,0")))
482 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
486 if (rtx_equal_p (operands[0], operands[1]))
487 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
490 cc_status.flags |= CC_REVERSED;
491 return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
495 ;; This is the second "hook" for PIC code (in addition to movsi). See
496 ;; comment of movsi for a description of PIC handling.
497 (define_expand "cmpsi"
499 (compare (match_operand:SI 0 "nonimmediate_operand" "")
500 (match_operand:SI 1 "general_operand" "")))]
504 m68k_last_compare_had_fp_operands = 0;
505 if (flag_pic && symbolic_operand (operands[1], SImode))
507 /* The source is an address which requires PIC relocation.
508 Call legitimize_pic_address with the source, mode, and a relocation
509 register (a new pseudo, or the final destination if reload_in_progress
510 is set). Then fall through normally */
511 extern rtx legitimize_pic_address();
512 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
513 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
517 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
520 (compare (match_operand:SI 0 "nonimmediate_operand" "rKs,mr,>")
521 (match_operand:SI 1 "general_operand" "mr,rKs,>")))]
525 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
527 return \"cmpm%.l %0,%1\";
529 return \"cmpm%.l %1,%0\";
531 if (REG_P (operands[1])
532 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
533 { cc_status.flags |= CC_REVERSED;
535 return \"cmp%.l %d1,%d0\";
537 return \"cmp%.l %d0,%d1\";
541 return \"cmp%.l %d0,%d1\";
543 return \"cmp%.l %d1,%d0\";
549 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
550 (match_operand:SI 1 "general_operand" "r,mrKs")))]
554 if (REG_P (operands[1])
555 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
556 { cc_status.flags |= CC_REVERSED;
558 return \"cmp%.l %d1,%d0\";
560 return \"cmp%.l %d0,%d1\";
564 return \"cmp%.l %d0,%d1\";
566 return \"cmp%.l %d1,%d0\";
570 (define_expand "cmphi"
572 (compare (match_operand:HI 0 "nonimmediate_operand" "")
573 (match_operand:HI 1 "general_operand" "")))]
575 "m68k_last_compare_had_fp_operands = 0;")
579 (compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m,>")
580 (match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))]
584 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
586 return \"cmpm%.w %0,%1\";
588 return \"cmpm%.w %1,%0\";
590 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
591 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
592 { cc_status.flags |= CC_REVERSED;
594 return \"cmp%.w %d1,%d0\";
596 return \"cmp%.w %d0,%d1\";
600 return \"cmp%.w %d0,%d1\";
602 return \"cmp%.w %d1,%d0\";
606 (define_expand "cmpqi"
608 (compare (match_operand:QI 0 "nonimmediate_operand" "")
609 (match_operand:QI 1 "general_operand" "")))]
611 "m68k_last_compare_had_fp_operands = 0;")
615 (compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>")
616 (match_operand:QI 1 "general_operand" "dm,nd,>")))]
620 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
622 return \"cmpm%.b %0,%1\";
624 return \"cmpm%.b %1,%0\";
626 if (REG_P (operands[1])
627 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
628 { cc_status.flags |= CC_REVERSED;
630 return \"cmp%.b %d1,%d0\";
632 return \"cmp%.b %d0,%d1\";
636 return \"cmp%.b %d0,%d1\";
638 return \"cmp%.b %d1,%d0\";
642 (define_expand "cmpdf"
644 (compare (match_operand:DF 0 "general_operand" "")
645 (match_operand:DF 1 "general_operand" "")))]
646 "TARGET_68881 || TARGET_FPA"
649 m68k_last_compare_had_fp_operands = 1;
652 emit_insn (gen_cmpdf_fpa (operands[0], operands[1]));
657 (define_insn "cmpdf_fpa"
659 (compare (match_operand:DF 0 "general_operand" "x,y")
660 (match_operand:DF 1 "general_operand" "xH,rmF")))
661 (clobber (match_scratch:SI 2 "=d,d"))]
663 "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
667 (compare (match_operand:DF 0 "general_operand" "f,mG")
668 (match_operand:DF 1 "general_operand" "fmG,f")))]
672 cc_status.flags = CC_IN_68881;
674 if (REG_P (operands[0]))
676 if (REG_P (operands[1]))
677 return \"fcmp%.x %0,%1\";
679 return \"fcmp%.d %0,%f1\";
681 cc_status.flags |= CC_REVERSED;
682 return \"fcmp%.d %1,%f0\";
684 if (REG_P (operands[0]))
686 if (REG_P (operands[1]))
687 return \"fcmp%.x %1,%0\";
689 return \"fcmp%.d %f1,%0\";
691 cc_status.flags |= CC_REVERSED;
692 return \"fcmp%.d %f0,%1\";
696 (define_expand "cmpsf"
698 (compare (match_operand:SF 0 "general_operand" "")
699 (match_operand:SF 1 "general_operand" "")))]
700 "TARGET_68881 || TARGET_FPA"
703 m68k_last_compare_had_fp_operands = 1;
706 emit_insn (gen_cmpsf_fpa (operands[0], operands[1]));
711 (define_insn "cmpsf_fpa"
713 (compare (match_operand:SF 0 "general_operand" "x,y")
714 (match_operand:SF 1 "general_operand" "xH,rmF")))
715 (clobber (match_scratch:SI 2 "=d,d"))]
717 "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
721 (compare (match_operand:SF 0 "general_operand" "f,mdG")
722 (match_operand:SF 1 "general_operand" "fmdG,f")))]
726 cc_status.flags = CC_IN_68881;
728 if (FP_REG_P (operands[0]))
730 if (FP_REG_P (operands[1]))
731 return \"fcmp%.x %0,%1\";
733 return \"fcmp%.s %0,%f1\";
735 cc_status.flags |= CC_REVERSED;
736 return \"fcmp%.s %1,%f0\";
738 if (FP_REG_P (operands[0]))
740 if (FP_REG_P (operands[1]))
741 return \"fcmp%.x %1,%0\";
743 return \"fcmp%.s %f1,%0\";
745 cc_status.flags |= CC_REVERSED;
746 return \"fcmp%.s %f0,%1\";
750 ;; Recognizers for btst instructions.
752 ;; Coldfire/5200 only allows "<Q>" type addresses when the bit position is
753 ;; specified as a constant, so we must disable all patterns that may extract
754 ;; from a MEM at a constant bit position if we can't use this as a constraint.
757 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
759 (minus:SI (const_int 7)
760 (match_operand:SI 1 "general_operand" "di"))))]
762 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
764 ;; This is the same as the above pattern except for the constraints. The 'i'
768 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
770 (minus:SI (const_int 7)
771 (match_operand:SI 1 "general_operand" "d"))))]
773 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
776 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
778 (minus:SI (const_int 31)
779 (match_operand:SI 1 "general_operand" "di"))))]
781 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
783 ;; The following two patterns are like the previous two
784 ;; except that they use the fact that bit-number operands
785 ;; are automatically masked to 3 or 5 bits.
788 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
790 (minus:SI (const_int 7)
792 (match_operand:SI 1 "register_operand" "d")
795 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
798 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
800 (minus:SI (const_int 31)
802 (match_operand:SI 1 "register_operand" "d")
805 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
807 ;; Nonoffsettable mem refs are ok in this one pattern
808 ;; since we don't try to adjust them.
810 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
812 (match_operand:SI 1 "const_int_operand" "n")))]
813 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_5200"
816 operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1]));
817 return output_btst (operands, operands[1], operands[0], insn, 7);
821 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
823 (match_operand:SI 1 "const_int_operand" "n")))]
827 if (GET_CODE (operands[0]) == MEM)
829 operands[0] = adj_offsettable_operand (operands[0],
830 INTVAL (operands[1]) / 8);
831 operands[1] = gen_rtx (CONST_INT, VOIDmode,
832 7 - INTVAL (operands[1]) % 8);
833 return output_btst (operands, operands[1], operands[0], insn, 7);
835 operands[1] = gen_rtx (CONST_INT, VOIDmode,
836 31 - INTVAL (operands[1]));
837 return output_btst (operands, operands[1], operands[0], insn, 31);
840 ;; This is the same as the above pattern except for the constraints.
841 ;; The 'o' has been replaced with 'Q'.
844 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
846 (match_operand:SI 1 "const_int_operand" "n")))]
850 if (GET_CODE (operands[0]) == MEM)
852 operands[0] = adj_offsettable_operand (operands[0],
853 INTVAL (operands[1]) / 8);
854 operands[1] = gen_rtx (CONST_INT, VOIDmode,
855 7 - INTVAL (operands[1]) % 8);
856 return output_btst (operands, operands[1], operands[0], insn, 7);
858 operands[1] = gen_rtx (CONST_INT, VOIDmode,
859 31 - INTVAL (operands[1]));
860 return output_btst (operands, operands[1], operands[0], insn, 31);
866 ;; A special case in which it is not desirable
867 ;; to reload the constant into a data register.
868 (define_insn "pushexthisi_const"
869 [(set (match_operand:SI 0 "push_operand" "=m")
870 (match_operand:SI 1 "const_int_operand" "J"))]
871 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
874 if (operands[1] == const0_rtx)
875 return \"clr%.l %0\";
880 ;(define_insn "swapsi"
881 ; [(set (match_operand:SI 0 "general_operand" "+r")
882 ; (match_operand:SI 1 "general_operand" "+r"))
883 ; (set (match_dup 1) (match_dup 0))]
887 ;; Special case of fullword move when source is zero.
888 ;; The reason this is special is to avoid loading a zero
889 ;; into a data reg with moveq in order to store it elsewhere.
891 (define_insn "movsi_const0"
892 [(set (match_operand:SI 0 "general_operand" "=g")
894 ;; clr insns on 68000 read before writing.
895 ;; This isn't so on the 68010, but we have no TARGET_68010.
896 "((TARGET_68020 || TARGET_5200)
897 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
900 if (ADDRESS_REG_P (operands[0]))
902 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
903 if (!TARGET_68040 && !TARGET_68060)
904 return \"sub%.l %0,%0\";
909 /* Many SGS assemblers croak on size specifiers for constants. */
912 return \"lea 0.w,%0\";
915 return \"lea 0:w,%0\";
919 /* moveq is faster on the 68000. */
920 if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
921 #if defined(MOTOROLA) && !defined(CRDS)
922 return \"moveq%.l %#0,%0\";
924 return \"moveq %#0,%0\";
926 return \"clr%.l %0\";
929 ;; General case of fullword move.
931 ;; This is the main "hook" for PIC code. When generating
932 ;; PIC, movsi is responsible for determining when the source address
933 ;; needs PIC relocation and appropriately calling legitimize_pic_address
934 ;; to perform the actual relocation.
936 ;; In both the PIC and non-PIC cases the patterns generated will
937 ;; matched by the next define_insn.
938 (define_expand "movsi"
939 [(set (match_operand:SI 0 "general_operand" "")
940 (match_operand:SI 1 "general_operand" ""))]
944 if (flag_pic && symbolic_operand (operands[1], SImode))
946 /* The source is an address which requires PIC relocation.
947 Call legitimize_pic_address with the source, mode, and a relocation
948 register (a new pseudo, or the final destination if reload_in_progress
949 is set). Then fall through normally */
950 extern rtx legitimize_pic_address();
951 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
952 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
956 ;; General case of fullword move. The register constraints
957 ;; force integer constants in range for a moveq to be reloaded
958 ;; if they are headed for memory.
960 ;; Notes: make sure no alternative allows g vs g.
961 ;; We don't allow f-regs since fixed point cannot go in them.
962 ;; We do allow y and x regs since fixed point is allowed in them.
963 [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m")
964 (match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))]
968 if (which_alternative == 3)
969 return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
970 if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
971 return \"fpmove%.l %x1,%x0\";
972 return output_move_simode (operands);
976 [(set (match_operand:SI 0 "general_operand" "=r<Q>,g")
977 (match_operand:SI 1 "general_operand" "g,r<Q>"))]
979 "* return output_move_simode (operands);")
981 (define_expand "movhi"
982 [(set (match_operand:HI 0 "general_operand" "")
983 (match_operand:HI 1 "general_operand" ""))]
988 [(set (match_operand:HI 0 "general_operand" "=g")
989 (match_operand:HI 1 "general_operand" "g"))]
991 "* return output_move_himode (operands);")
994 [(set (match_operand:HI 0 "general_operand" "=r<Q>,g")
995 (match_operand:HI 1 "general_operand" "g,r<Q>"))]
997 "* return output_move_himode (operands);")
999 (define_expand "movstricthi"
1000 [(set (strict_low_part (match_operand:HI 0 "general_operand" ""))
1001 (match_operand:HI 1 "general_operand" ""))]
1006 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
1007 (match_operand:HI 1 "general_operand" "rmn"))]
1009 "* return output_move_stricthi (operands);")
1012 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+d,m"))
1013 (match_operand:HI 1 "general_operand" "rmn,r"))]
1015 "* return output_move_stricthi (operands);")
1017 (define_expand "movqi"
1018 [(set (match_operand:QI 0 "general_operand" "")
1019 (match_operand:QI 1 "general_operand" ""))]
1024 [(set (match_operand:QI 0 "general_operand" "=d,*a,m")
1025 (match_operand:QI 1 "general_operand" "dmi*a,di*a,dmi"))]
1027 "* return output_move_qimode (operands);")
1030 [(set (match_operand:QI 0 "general_operand" "=d*a<Q>,d*am")
1031 (match_operand:QI 1 "general_operand" "d*ami,d*a<Q>"))]
1033 "* return output_move_qimode (operands);")
1035 (define_expand "movstrictqi"
1036 [(set (strict_low_part (match_operand:QI 0 "general_operand" ""))
1037 (match_operand:QI 1 "general_operand" ""))]
1042 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
1043 (match_operand:QI 1 "general_operand" "dmn"))]
1045 "* return output_move_strictqi (operands);")
1048 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+d,m"))
1049 (match_operand:QI 1 "general_operand" "dmn,d"))]
1051 "* return output_move_strictqi (operands);")
1053 (define_expand "movsf"
1054 [(set (match_operand:SF 0 "general_operand" "")
1055 (match_operand:SF 1 "general_operand" ""))]
1060 [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm")
1061 (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
1062 ; [(set (match_operand:SF 0 "general_operand" "=rmf")
1063 ; (match_operand:SF 1 "general_operand" "rmfF"))]
1067 if (which_alternative >= 4)
1068 return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
1069 if (FPA_REG_P (operands[0]))
1071 if (FPA_REG_P (operands[1]))
1072 return \"fpmove%.s %x1,%x0\";
1073 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1074 return output_move_const_single (operands);
1075 else if (FP_REG_P (operands[1]))
1076 return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
1077 return \"fpmove%.s %x1,%x0\";
1079 if (FPA_REG_P (operands[1]))
1081 if (FP_REG_P (operands[0]))
1082 return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
1084 return \"fpmove%.s %x1,%x0\";
1086 if (FP_REG_P (operands[0]))
1088 if (FP_REG_P (operands[1]))
1089 return \"f%$move%.x %1,%0\";
1090 else if (ADDRESS_REG_P (operands[1]))
1091 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
1092 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1093 return output_move_const_single (operands);
1094 return \"f%$move%.s %f1,%0\";
1096 if (FP_REG_P (operands[1]))
1098 if (ADDRESS_REG_P (operands[0]))
1099 return \"fmove%.s %1,%-\;move%.l %+,%0\";
1100 return \"fmove%.s %f1,%0\";
1102 if (operands[1] == CONST0_RTX (SFmode)
1103 /* clr insns on 68000 read before writing.
1104 This isn't so on the 68010, but we have no TARGET_68010. */
1105 && ((TARGET_68020 || TARGET_5200)
1106 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1108 if (ADDRESS_REG_P (operands[0]))
1110 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
1111 if (!TARGET_68040 && !TARGET_68060)
1112 return \"sub%.l %0,%0\";
1117 /* Many SGS assemblers croak on size specifiers for constants. */
1118 return \"lea 0,%0\";
1120 return \"lea 0.w,%0\";
1123 return \"lea 0:w,%0\";
1127 /* moveq is faster on the 68000. */
1128 if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_5200))
1130 #if defined(MOTOROLA) && !defined(CRDS)
1131 return \"moveq%.l %#0,%0\";
1133 return \"moveq %#0,%0\";
1136 return \"clr%.l %0\";
1138 return \"move%.l %1,%0\";
1142 [(set (match_operand:SF 0 "general_operand" "=r,g")
1143 (match_operand:SF 1 "general_operand" "g,r"))]
1145 "* return \"move%.l %1,%0\";")
1147 (define_expand "movdf"
1148 [(set (match_operand:DF 0 "general_operand" "")
1149 (match_operand:DF 1 "general_operand" ""))]
1154 [(set (match_operand:DF 0 "general_operand" "=rm,rf,rf,&rof<>,y,rm,x,!x,!rm")
1155 (match_operand:DF 1 "general_operand" "rf,m,0,rofE<>,rmE,y,xH,rm,x"))]
1156 ; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>")
1157 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1161 if (which_alternative == 7)
1162 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1163 if (FPA_REG_P (operands[0]))
1165 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1166 return output_move_const_double (operands);
1167 if (FP_REG_P (operands[1]))
1168 return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
1169 return \"fpmove%.d %x1,%x0\";
1171 else if (FPA_REG_P (operands[1]))
1173 if (FP_REG_P(operands[0]))
1174 return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
1176 return \"fpmove%.d %x1,%x0\";
1178 if (FP_REG_P (operands[0]))
1180 if (FP_REG_P (operands[1]))
1181 return \"f%&move%.x %1,%0\";
1182 if (REG_P (operands[1]))
1185 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1186 output_asm_insn (\"move%.l %1,%-\", xoperands);
1187 output_asm_insn (\"move%.l %1,%-\", operands);
1188 return \"f%&move%.d %+,%0\";
1190 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1191 return output_move_const_double (operands);
1192 return \"f%&move%.d %f1,%0\";
1194 else if (FP_REG_P (operands[1]))
1196 if (REG_P (operands[0]))
1198 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1199 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1200 return \"move%.l %+,%0\";
1203 return \"fmove%.d %f1,%0\";
1205 return output_move_double (operands);
1209 [(set (match_operand:DF 0 "general_operand" "=r,g")
1210 (match_operand:DF 1 "general_operand" "g,r"))]
1212 "* return output_move_double (operands);")
1214 (define_expand "movxf"
1215 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1216 (match_operand:XF 1 "general_operand" ""))]
1220 if (CONSTANT_P (operands[1]))
1222 operands[1] = force_const_mem (XFmode, operands[1]);
1223 if (! memory_address_p (XFmode, XEXP (operands[1], 0))
1224 && ! reload_in_progress)
1225 operands[1] = change_address (operands[1], XFmode,
1226 XEXP (operands[1], 0));
1231 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f")
1232 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r"))]
1236 if (FP_REG_P (operands[0]))
1238 if (FP_REG_P (operands[1]))
1239 return \"fmove%.x %1,%0\";
1240 if (REG_P (operands[1]))
1243 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1244 output_asm_insn (\"move%.l %1,%-\", xoperands);
1245 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1246 output_asm_insn (\"move%.l %1,%-\", xoperands);
1247 output_asm_insn (\"move%.l %1,%-\", operands);
1248 return \"fmove%.x %+,%0\";
1250 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1251 return \"fmove%.x %1,%0\";
1252 return \"fmove%.x %f1,%0\";
1254 if (REG_P (operands[0]))
1256 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1257 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1258 output_asm_insn (\"move%.l %+,%0\", operands);
1259 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1260 return \"move%.l %+,%0\";
1262 return \"fmove%.x %f1,%0\";
1267 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1268 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1269 "! TARGET_68881 && ! TARGET_5200"
1272 if (FP_REG_P (operands[0]))
1274 if (FP_REG_P (operands[1]))
1275 return \"fmove%.x %1,%0\";
1276 if (REG_P (operands[1]))
1279 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1280 output_asm_insn (\"move%.l %1,%-\", xoperands);
1281 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1282 output_asm_insn (\"move%.l %1,%-\", xoperands);
1283 output_asm_insn (\"move%.l %1,%-\", operands);
1284 return \"fmove%.x %+,%0\";
1286 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1287 return \"fmove%.x %1,%0\";
1288 return \"fmove%.x %f1,%0\";
1290 if (FP_REG_P (operands[1]))
1292 if (REG_P (operands[0]))
1294 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1295 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1296 output_asm_insn (\"move%.l %+,%0\", operands);
1297 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1298 return \"move%.l %+,%0\";
1301 return \"fmove%.x %f1,%0\";
1303 return output_move_double (operands);
1308 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
1309 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
1310 "! TARGET_68881 && TARGET_5200"
1311 "* return output_move_double (operands);")
1313 (define_expand "movdi"
1314 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1315 [(set (match_operand:DI 0 "general_operand" "")
1316 (match_operand:DI 1 "general_operand" ""))]
1320 ;; movdi can apply to fp regs in some cases
1322 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1323 [(set (match_operand:DI 0 "general_operand" "=rm,r,&ro<>,y,rm,!*x,!rm")
1324 (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
1325 ; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
1326 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
1327 ; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1328 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1332 if (which_alternative == 8)
1333 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1334 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1335 return \"fpmove%.d %x1,%x0\";
1336 if (FP_REG_P (operands[0]))
1338 if (FP_REG_P (operands[1]))
1339 return \"fmove%.x %1,%0\";
1340 if (REG_P (operands[1]))
1343 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1344 output_asm_insn (\"move%.l %1,%-\", xoperands);
1345 output_asm_insn (\"move%.l %1,%-\", operands);
1346 return \"fmove%.d %+,%0\";
1348 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1349 return output_move_const_double (operands);
1350 return \"fmove%.d %f1,%0\";
1352 else if (FP_REG_P (operands[1]))
1354 if (REG_P (operands[0]))
1356 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1357 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1358 return \"move%.l %+,%0\";
1361 return \"fmove%.d %f1,%0\";
1363 return output_move_double (operands);
1367 [(set (match_operand:DI 0 "general_operand" "=r,g")
1368 (match_operand:DI 1 "general_operand" "g,r"))]
1370 "* return output_move_double (operands);")
1372 ;; Thus goes after the move instructions
1373 ;; because the move instructions are better (require no spilling)
1374 ;; when they can apply. It goes before the add/sub insns
1375 ;; so we will prefer it to them.
1377 (define_insn "pushasi"
1378 [(set (match_operand:SI 0 "push_operand" "=m")
1379 (match_operand:SI 1 "address_operand" "p"))]
1383 ;; truncation instructions
1384 (define_insn "truncsiqi2"
1385 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1387 (match_operand:SI 1 "general_operand" "doJ,i")))]
1391 if (GET_CODE (operands[0]) == REG)
1393 /* Must clear condition codes, since the move.l bases them on
1394 the entire 32 bits, not just the desired 8 bits. */
1396 return \"move%.l %1,%0\";
1398 if (GET_CODE (operands[1]) == MEM)
1399 operands[1] = adj_offsettable_operand (operands[1], 3);
1400 return \"move%.b %1,%0\";
1403 (define_insn "trunchiqi2"
1404 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1406 (match_operand:HI 1 "general_operand" "doJ,i")))]
1410 if (GET_CODE (operands[0]) == REG
1411 && (GET_CODE (operands[1]) == MEM
1412 || GET_CODE (operands[1]) == CONST_INT))
1414 /* Must clear condition codes, since the move.w bases them on
1415 the entire 16 bits, not just the desired 8 bits. */
1417 return \"move%.w %1,%0\";
1419 if (GET_CODE (operands[0]) == REG)
1421 /* Must clear condition codes, since the move.l bases them on
1422 the entire 32 bits, not just the desired 8 bits. */
1424 return \"move%.l %1,%0\";
1426 if (GET_CODE (operands[1]) == MEM)
1427 operands[1] = adj_offsettable_operand (operands[1], 1);
1428 return \"move%.b %1,%0\";
1431 (define_insn "truncsihi2"
1432 [(set (match_operand:HI 0 "general_operand" "=dm,d")
1434 (match_operand:SI 1 "general_operand" "roJ,i")))]
1438 if (GET_CODE (operands[0]) == REG)
1440 /* Must clear condition codes, since the move.l bases them on
1441 the entire 32 bits, not just the desired 8 bits. */
1443 return \"move%.l %1,%0\";
1445 if (GET_CODE (operands[1]) == MEM)
1446 operands[1] = adj_offsettable_operand (operands[1], 2);
1447 return \"move%.w %1,%0\";
1450 ;; zero extension instructions
1452 (define_insn "zero_extendqidi2"
1453 [(set (match_operand:DI 0 "general_operand" "=&d")
1454 (zero_extend:DI (match_operand:QI 1 "general_operand" "dm")))]
1459 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1460 return \"moveq %#0,%0\;moveq %#0,%2\;move%.b %1,%2\";
1463 (define_insn "zero_extendhidi2"
1464 [(set (match_operand:DI 0 "general_operand" "=&d")
1465 (zero_extend:DI (match_operand:HI 1 "general_operand" "rm")))]
1470 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1471 return \"moveq %#0,%0\;moveq %#0,%2\;move%.w %1,%2\";
1474 ;; this is the canonical form for (lshiftrt:DI x 32)
1475 (define_insn "zero_extendsidi2"
1476 [(set (match_operand:DI 0 "general_operand" "rm")
1477 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
1482 if (GET_CODE (operands[0]) == REG)
1483 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1484 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1485 return \"move%.l %1,%0\;clr%.l %0\";
1486 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1487 return \"clr%.l %0\;move%.l %1,%0\";
1489 operands[2] = adj_offsettable_operand (operands[0], 4);
1490 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[1]) != REG
1491 || REGNO (operands[1]) != REGNO (operands[2]))
1492 output_asm_insn (\"move%.l %1,%2\", operands);
1493 if (ADDRESS_REG_P (operands[0]))
1494 return \"sub%.l %0,%0\";
1496 return \"clr%.l %0\";
1499 (define_expand "zero_extendhisi2"
1500 [(set (match_operand:SI 0 "register_operand" "")
1502 (set (strict_low_part (match_dup 2))
1503 (match_operand:HI 1 "general_operand" ""))]
1507 operands[1] = make_safe_from (operands[1], operands[0]);
1508 if (GET_CODE (operands[0]) == SUBREG)
1509 operands[2] = gen_rtx (SUBREG, HImode, SUBREG_REG (operands[0]),
1510 SUBREG_WORD (operands[0]));
1512 operands[2] = gen_rtx (SUBREG, HImode, operands[0], 0);
1515 (define_expand "zero_extendqihi2"
1516 [(set (match_operand:HI 0 "register_operand" "")
1518 (set (strict_low_part (match_dup 2))
1519 (match_operand:QI 1 "general_operand" ""))]
1523 operands[1] = make_safe_from (operands[1], operands[0]);
1524 if (GET_CODE (operands[0]) == SUBREG)
1525 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
1526 SUBREG_WORD (operands[0]));
1528 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
1531 (define_expand "zero_extendqisi2"
1532 [(set (match_operand:SI 0 "register_operand" "")
1534 (set (strict_low_part (match_dup 2))
1535 (match_operand:QI 1 "general_operand" ""))]
1539 operands[1] = make_safe_from (operands[1], operands[0]);
1540 if (GET_CODE (operands[0]) == SUBREG)
1541 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
1542 SUBREG_WORD (operands[0]));
1544 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
1547 ;; Patterns to recognize zero-extend insns produced by the combiner.
1548 ;; We don't allow both operands in memory, because of aliasing problems.
1549 ;; Explicitly disallow two memory operands via the condition since reloading
1550 ;; of this case will result in worse code than the uncombined patterns.
1553 [(set (match_operand:SI 0 "general_operand" "=do<>,d<")
1554 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1555 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1558 if (DATA_REG_P (operands[0]))
1560 if (GET_CODE (operands[1]) == REG
1561 && REGNO (operands[0]) == REGNO (operands[1]))
1562 return \"and%.l %#0xFFFF,%0\";
1563 if (reg_mentioned_p (operands[0], operands[1]))
1564 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1565 return \"clr%.l %0\;move%.w %1,%0\";
1567 else if (GET_CODE (operands[0]) == MEM
1568 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1569 return \"move%.w %1,%0\;clr%.w %0\";
1570 else if (GET_CODE (operands[0]) == MEM
1571 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1572 return \"clr%.w %0\;move%.w %1,%0\";
1575 output_asm_insn (\"clr%.w %0\", operands);
1576 operands[0] = adj_offsettable_operand (operands[0], 2);
1577 return \"move%.w %1,%0\";
1582 [(set (match_operand:HI 0 "general_operand" "=do<>,d")
1583 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1584 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1587 if (DATA_REG_P (operands[0]))
1589 if (GET_CODE (operands[1]) == REG
1590 && REGNO (operands[0]) == REGNO (operands[1]))
1591 return \"and%.w %#0xFF,%0\";
1592 if (reg_mentioned_p (operands[0], operands[1]))
1593 return \"move%.b %1,%0\;and%.w %#0xFF,%0\";
1594 return \"clr%.w %0\;move%.b %1,%0\";
1596 else if (GET_CODE (operands[0]) == MEM
1597 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1599 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1600 == STACK_POINTER_REGNUM)
1602 output_asm_insn (\"clr%.w %-\", operands);
1603 operands[0] = gen_rtx (MEM, GET_MODE (operands[0]),
1604 plus_constant (stack_pointer_rtx, 1));
1605 return \"move%.b %1,%0\";
1608 return \"move%.b %1,%0\;clr%.b %0\";
1610 else if (GET_CODE (operands[0]) == MEM
1611 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1612 return \"clr%.b %0\;move%.b %1,%0\";
1615 output_asm_insn (\"clr%.b %0\", operands);
1616 operands[0] = adj_offsettable_operand (operands[0], 1);
1617 return \"move%.b %1,%0\";
1622 [(set (match_operand:SI 0 "general_operand" "=do<>,d")
1623 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1624 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1627 if (DATA_REG_P (operands[0]))
1629 if (GET_CODE (operands[1]) == REG
1630 && REGNO (operands[0]) == REGNO (operands[1]))
1631 return \"and%.l %#0xFF,%0\";
1632 if (reg_mentioned_p (operands[0], operands[1]))
1633 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1634 return \"clr%.l %0\;move%.b %1,%0\";
1636 else if (GET_CODE (operands[0]) == MEM
1637 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1639 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1642 return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
1644 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
1647 return \"clrl %0@-\;moveb %1,%0@(3)\";
1650 else if (GET_CODE (operands[0]) == MEM
1651 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1653 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1656 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
1658 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
1661 return \"clrl %0@+\;moveb %1,%0@(-1)\";
1666 output_asm_insn (\"clr%.l %0\", operands);
1667 operands[0] = adj_offsettable_operand (operands[0], 3);
1668 return \"move%.b %1,%0\";
1672 ;; sign extension instructions
1674 (define_insn "extendqidi2"
1675 [(set (match_operand:DI 0 "general_operand" "=d")
1677 (match_operand:QI 1 "general_operand" "rm")))]
1682 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1683 if (TARGET_68020 || TARGET_5200)
1684 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1686 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
1689 (define_insn "extendhidi2"
1690 [(set (match_operand:DI 0 "general_operand" "=d")
1692 (match_operand:HI 1 "general_operand" "rm")))]
1697 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1698 if (TARGET_68020 || TARGET_5200)
1699 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1701 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1704 (define_insn "extendsidi2"
1705 [(set (match_operand:DI 0 "general_operand" "=d")
1707 (match_operand:SI 1 "general_operand" "rm")))]
1712 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1713 if (TARGET_68020 || TARGET_5200)
1714 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1716 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1719 ;; Special case when one can avoid register clobbering, copy and test
1720 ;; Maybe there is a way to make that the general case, by forcing the
1721 ;; result of the SI tree to be in the lower register of the DI target
1723 (define_insn "extendplussidi"
1724 [(set (match_operand:DI 0 "register_operand" "=d")
1725 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1726 (match_operand:SI 2 "general_operand" "rmn"))))]
1731 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1732 if (GET_CODE (operands[1]) == CONST_INT
1733 && (unsigned) INTVAL (operands[1]) > 8)
1735 rtx tmp = operands[1];
1737 operands[1] = operands[2];
1740 if (GET_CODE (operands[1]) == REG
1741 && REGNO (operands[1]) == REGNO (operands[3]))
1742 output_asm_insn (\"add%.l %2,%3\", operands);
1744 output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
1745 if (TARGET_68020 || TARGET_5200)
1746 return \"smi %0\;extb%.l %0\";
1748 return \"smi %0\;ext%.w %0\;ext%.l %0\";
1751 (define_insn "extendhisi2"
1752 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1754 (match_operand:HI 1 "nonimmediate_operand" "0,rm")))]
1758 if (ADDRESS_REG_P (operands[0]))
1759 return \"move%.w %1,%0\";
1760 return \"ext%.l %0\";
1763 (define_insn "extendqihi2"
1764 [(set (match_operand:HI 0 "general_operand" "=d")
1765 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1769 (define_insn "extendqisi2"
1770 [(set (match_operand:SI 0 "general_operand" "=d")
1771 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1772 "TARGET_68020 || TARGET_5200"
1775 ;; Conversions between float and double.
1777 (define_expand "extendsfdf2"
1778 [(set (match_operand:DF 0 "general_operand" "")
1780 (match_operand:SF 1 "general_operand" "")))]
1781 "TARGET_68881 || TARGET_FPA"
1785 [(set (match_operand:DF 0 "general_operand" "=x,y")
1787 (match_operand:SF 1 "general_operand" "xH,rmF")))]
1792 [(set (match_operand:DF 0 "general_operand" "=*fdm,f")
1794 (match_operand:SF 1 "general_operand" "f,dmF")))]
1798 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1800 if (REGNO (operands[0]) == REGNO (operands[1]))
1802 /* Extending float to double in an fp-reg is a no-op.
1803 NOTICE_UPDATE_CC has already assumed that the
1804 cc will be set. So cancel what it did. */
1805 cc_status = cc_prev_status;
1808 return \"f%&move%.x %1,%0\";
1810 if (FP_REG_P (operands[0]))
1811 return \"f%&move%.s %f1,%0\";
1812 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1814 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1815 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1816 return \"move%.l %+,%0\";
1818 return \"fmove%.d %f1,%0\";
1821 ;; This cannot output into an f-reg because there is no way to be
1822 ;; sure of truncating in that case.
1823 ;; But on the Sun FPA, we can be sure.
1824 (define_expand "truncdfsf2"
1825 [(set (match_operand:SF 0 "general_operand" "")
1827 (match_operand:DF 1 "general_operand" "")))]
1828 "TARGET_68881 || TARGET_FPA"
1832 [(set (match_operand:SF 0 "general_operand" "=x,y")
1834 (match_operand:DF 1 "general_operand" "xH,rmF")))]
1838 ;; On the '040 we can truncate in a register accurately and easily.
1840 [(set (match_operand:SF 0 "general_operand" "=f")
1842 (match_operand:DF 1 "general_operand" "fmG")))]
1846 if (FP_REG_P (operands[1]))
1847 return \"f%$move%.x %1,%0\";
1848 return \"f%$move%.d %f1,%0\";
1852 [(set (match_operand:SF 0 "general_operand" "=dm")
1854 (match_operand:DF 1 "general_operand" "f")))]
1858 ;; Conversion between fixed point and floating point.
1859 ;; Note that among the fix-to-float insns
1860 ;; the ones that start with SImode come first.
1861 ;; That is so that an operand that is a CONST_INT
1862 ;; (and therefore lacks a specific machine mode).
1863 ;; will be recognized as SImode (which is always valid)
1864 ;; rather than as QImode or HImode.
1866 (define_expand "floatsisf2"
1867 [(set (match_operand:SF 0 "general_operand" "")
1868 (float:SF (match_operand:SI 1 "general_operand" "")))]
1869 "TARGET_68881 || TARGET_FPA"
1873 [(set (match_operand:SF 0 "general_operand" "=y,x")
1874 (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
1879 [(set (match_operand:SF 0 "general_operand" "=f")
1880 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1884 (define_expand "floatsidf2"
1885 [(set (match_operand:DF 0 "general_operand" "")
1886 (float:DF (match_operand:SI 1 "general_operand" "")))]
1887 "TARGET_68881 || TARGET_FPA"
1891 [(set (match_operand:DF 0 "general_operand" "=y,x")
1892 (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
1897 [(set (match_operand:DF 0 "general_operand" "=f")
1898 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1902 (define_insn "floathisf2"
1903 [(set (match_operand:SF 0 "general_operand" "=f")
1904 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1908 (define_insn "floathidf2"
1909 [(set (match_operand:DF 0 "general_operand" "=f")
1910 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1914 (define_insn "floatqisf2"
1915 [(set (match_operand:SF 0 "general_operand" "=f")
1916 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1920 (define_insn "floatqidf2"
1921 [(set (match_operand:DF 0 "general_operand" "=f")
1922 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1926 ;; New routines to convert floating-point values to integers
1927 ;; to be used on the '040. These should be faster than trapping
1928 ;; into the kernel to emulate fintrz. They should also be faster
1929 ;; than calling the subroutines fixsfsi or fixdfsi.
1931 (define_insn "fix_truncdfsi2"
1932 [(set (match_operand:SI 0 "general_operand" "=dm")
1933 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1934 (clobber (match_scratch:SI 2 "=d"))
1935 (clobber (match_scratch:SI 3 "=d"))]
1936 "TARGET_68881 && TARGET_68040"
1940 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
1943 (define_insn "fix_truncdfhi2"
1944 [(set (match_operand:HI 0 "general_operand" "=dm")
1945 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1946 (clobber (match_scratch:SI 2 "=d"))
1947 (clobber (match_scratch:SI 3 "=d"))]
1948 "TARGET_68881 && TARGET_68040"
1952 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
1955 (define_insn "fix_truncdfqi2"
1956 [(set (match_operand:QI 0 "general_operand" "=dm")
1957 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1958 (clobber (match_scratch:SI 2 "=d"))
1959 (clobber (match_scratch:SI 3 "=d"))]
1960 "TARGET_68881 && TARGET_68040"
1964 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
1967 ;; Convert a float to a float whose value is an integer.
1968 ;; This is the first stage of converting it to an integer type.
1970 (define_insn "ftruncdf2"
1971 [(set (match_operand:DF 0 "general_operand" "=f")
1972 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
1973 "TARGET_68881 && !TARGET_68040"
1976 if (FP_REG_P (operands[1]))
1977 return \"fintrz%.x %f1,%0\";
1978 return \"fintrz%.d %f1,%0\";
1981 (define_insn "ftruncsf2"
1982 [(set (match_operand:SF 0 "general_operand" "=f")
1983 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
1984 "TARGET_68881 && !TARGET_68040"
1987 if (FP_REG_P (operands[1]))
1988 return \"fintrz%.x %f1,%0\";
1989 return \"fintrz%.s %f1,%0\";
1992 ;; Convert a float whose value is an integer
1993 ;; to an actual integer. Second stage of converting float to integer type.
1994 (define_insn "fixsfqi2"
1995 [(set (match_operand:QI 0 "general_operand" "=dm")
1996 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
2000 (define_insn "fixsfhi2"
2001 [(set (match_operand:HI 0 "general_operand" "=dm")
2002 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
2006 (define_insn "fixsfsi2"
2007 [(set (match_operand:SI 0 "general_operand" "=dm")
2008 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
2012 (define_insn "fixdfqi2"
2013 [(set (match_operand:QI 0 "general_operand" "=dm")
2014 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
2018 (define_insn "fixdfhi2"
2019 [(set (match_operand:HI 0 "general_operand" "=dm")
2020 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
2024 (define_insn "fixdfsi2"
2025 [(set (match_operand:SI 0 "general_operand" "=dm")
2026 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
2030 ;; Convert a float to an integer.
2031 ;; On the Sun FPA, this is done in one step.
2034 [(set (match_operand:SI 0 "general_operand" "=x,y")
2035 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
2040 [(set (match_operand:SI 0 "general_operand" "=x,y")
2041 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
2047 (define_insn "adddi_lshrdi_63"
2048 [(set (match_operand:DI 0 "general_operand" "=d")
2049 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
2052 (clobber (match_scratch:SI 2 "=d"))]
2056 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
2057 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
2059 \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
2060 if (GET_CODE (operands[1]) == REG)
2061 operands[4] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2062 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
2063 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2064 operands[4] = operands[1];
2066 operands[4] = adj_offsettable_operand (operands[1], 4);
2067 if (GET_CODE (operands[1]) == MEM
2068 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2069 output_asm_insn (\"move%.l %4,%3\", operands);
2070 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
2071 if (TARGET_68020 || TARGET_5200)
2072 output_asm_insn (\"extb%.l %2\", operands);
2074 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
2075 if (GET_CODE (operands[1]) != MEM
2076 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
2077 output_asm_insn (\"move%.l %4,%3\", operands);
2078 return \"sub%.l %2,%3\;subx%.l %2,%0\";
2081 (define_insn "adddi_sexthishl32"
2082 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2083 (plus:DI (ashift:DI (sign_extend:DI
2084 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
2086 (match_operand:DI 2 "general_operand" "0,0,0,0")))
2087 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2092 if (ADDRESS_REG_P (operands[0]))
2093 return \"add%.w %1,%0\";
2094 else if (ADDRESS_REG_P (operands[3]))
2095 return \"move%.w %1,%3\;add%.l %3,%0\";
2097 return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
2100 (define_insn "adddi_dilshr32"
2101 [(set (match_operand:DI 0 "general_operand" "=do")
2102 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2103 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2104 ;; (const_int 32))))]
2105 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2107 (match_operand:DI 2 "general_operand" "0")))]
2112 if (GET_CODE (operands[0]) == REG)
2113 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
2115 operands[2] = adj_offsettable_operand (operands[0], 4);
2116 return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
2119 (define_insn "adddi_dishl32"
2120 [(set (match_operand:DI 0 "general_operand" "=ro")
2121 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2122 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2123 ;; (const_int 32))))]
2124 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2126 (match_operand:DI 2 "general_operand" "0")))]
2131 if (GET_CODE (operands[1]) == REG)
2132 operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2134 operands[1] = adj_offsettable_operand (operands[1], 4);
2135 return \"add%.l %1,%0\";
2138 (define_insn "adddi3"
2139 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2140 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
2141 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2142 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2146 if (DATA_REG_P (operands[0]))
2148 if (DATA_REG_P (operands[2]))
2149 return \"add%.l %R2,%R0\;addx%.l %2,%0\";
2150 else if (GET_CODE (operands[2]) == MEM
2151 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2153 return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
2157 if (GET_CODE (operands[2]) == REG)
2158 operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2159 else if (GET_CODE (operands[2]) == CONST_DOUBLE)
2161 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
2162 operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
2164 else if (GET_CODE (operands[2]) == CONST_INT)
2166 operands[1] = operands[2];
2167 operands[2] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
2170 operands[1] = adj_offsettable_operand (operands[2], 4);
2171 /* TODO : for consts, optimize move and add */
2172 return \"move%.l %2,%3\;add%.l %1,%R0\;addx%.l %3,%0\";
2175 else if (GET_CODE (operands[0]) == MEM)
2177 if (GET_CODE (operands[2]) == MEM
2178 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2179 return \"add%.l %2,%0\;addx%.l %2,%0\";
2181 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2183 operands[1] = gen_rtx (MEM, SImode,
2184 gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
2185 gen_rtx (CONST_INT, VOIDmode, -8)));
2186 return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
2188 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2190 operands[1] = XEXP(operands[0], 0);
2191 return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
2195 operands[1] = adj_offsettable_operand (operands[0], 4);
2196 return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
2201 (define_insn "addsi_lshrsi_31"
2202 [(set (match_operand:SI 0 "general_operand" "=dm")
2203 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2209 operands[2] = operands[0];
2210 operands[3] = gen_label_rtx();
2211 if (GET_CODE (operands[0]) == MEM)
2213 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2214 operands[0] = gen_rtx (MEM, SImode, XEXP (XEXP (operands[0], 0), 0));
2215 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2216 operands[2] = gen_rtx (MEM, SImode, XEXP (XEXP (operands[0], 0), 0));
2218 output_asm_insn (\"move%.l %1,%0\", operands);
2220 output_asm_insn (\"jbpl %l3\", operands);
2222 output_asm_insn (\"jpl %l3\", operands);
2225 output_asm_insn (\"addq%.l %#1,%2\", operands);
2227 output_asm_insn (\"add%.l %#1,%2\", operands);
2229 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
2230 CODE_LABEL_NUMBER (operands[3]));
2234 (define_expand "addsi3"
2235 [(set (match_operand:SI 0 "general_operand" "")
2236 (plus:SI (match_operand:SI 1 "general_operand" "")
2237 (match_operand:SI 2 "general_operand" "")))]
2241 ;; Note that the middle two alternatives are near-duplicates
2242 ;; in order to handle insns generated by reload.
2243 ;; This is needed since they are not themselves reloaded,
2244 ;; so commutativity won't apply to them.
2245 (define_insn "*addsi3_internal"
2246 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2247 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2248 (match_operand:SI 2 "general_operand" "dIKLs,rJK,a,mrIKLs")))]
2250 "* return output_addsi3 (operands);")
2252 (define_insn "*addsi3_5200"
2253 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2254 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2255 (match_operand:SI 2 "general_operand" "d,rJK,a,mrIKLs")))]
2257 "* return output_addsi3 (operands);")
2260 [(set (match_operand:SI 0 "general_operand" "=a")
2261 (plus:SI (match_operand:SI 1 "general_operand" "0")
2263 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2267 (define_insn "addhi3"
2268 [(set (match_operand:HI 0 "general_operand" "=m,r")
2269 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2270 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2274 if (GET_CODE (operands[2]) == CONST_INT)
2277 /* If the constant would be a negative number when interpreted as
2278 HImode, make it negative. This is usually, but not always, done
2279 elsewhere in the compiler. First check for constants out of range,
2280 which could confuse us. */
2282 if (INTVAL (operands[2]) >= 32768)
2283 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2284 INTVAL (operands[2]) - 65536);
2286 if (INTVAL (operands[2]) > 0
2287 && INTVAL (operands[2]) <= 8)
2288 return \"addq%.w %2,%0\";
2289 if (INTVAL (operands[2]) < 0
2290 && INTVAL (operands[2]) >= -8)
2292 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2293 - INTVAL (operands[2]));
2294 return \"subq%.w %2,%0\";
2296 /* On the CPU32 it is faster to use two addqw instructions to
2297 add a small integer (8 < N <= 16) to a register.
2298 Likewise for subqw. */
2299 if (TARGET_CPU32 && REG_P (operands[0]))
2301 if (INTVAL (operands[2]) > 8
2302 && INTVAL (operands[2]) <= 16)
2304 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2305 INTVAL (operands[2]) - 8);
2306 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2308 if (INTVAL (operands[2]) < -8
2309 && INTVAL (operands[2]) >= -16)
2311 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2312 - INTVAL (operands[2]) - 8);
2313 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2317 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2319 return \"lea (%c2,%0),%0\";
2321 return \"lea %0@(%c2),%0\";
2324 return \"add%.w %2,%0\";
2327 ;; These insns must use MATCH_DUP instead of the more expected
2328 ;; use of a matching constraint because the "output" here is also
2329 ;; an input, so you can't use the matching constraint. That also means
2330 ;; that you can't use the "%", so you need patterns with the matched
2331 ;; operand in both positions.
2334 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2335 (plus:HI (match_dup 0)
2336 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2340 if (GET_CODE (operands[1]) == CONST_INT)
2343 /* If the constant would be a negative number when interpreted as
2344 HImode, make it negative. This is usually, but not always, done
2345 elsewhere in the compiler. First check for constants out of range,
2346 which could confuse us. */
2348 if (INTVAL (operands[1]) >= 32768)
2349 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2350 INTVAL (operands[1]) - 65536);
2352 if (INTVAL (operands[1]) > 0
2353 && INTVAL (operands[1]) <= 8)
2354 return \"addq%.w %1,%0\";
2355 if (INTVAL (operands[1]) < 0
2356 && INTVAL (operands[1]) >= -8)
2358 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2359 - INTVAL (operands[1]));
2360 return \"subq%.w %1,%0\";
2362 /* On the CPU32 it is faster to use two addqw instructions to
2363 add a small integer (8 < N <= 16) to a register.
2364 Likewise for subqw. */
2365 if (TARGET_CPU32 && REG_P (operands[0]))
2367 if (INTVAL (operands[1]) > 8
2368 && INTVAL (operands[1]) <= 16)
2370 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2371 INTVAL (operands[1]) - 8);
2372 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2374 if (INTVAL (operands[1]) < -8
2375 && INTVAL (operands[1]) >= -16)
2377 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2378 - INTVAL (operands[1]) - 8);
2379 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2383 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2385 return \"lea (%c1,%0),%0\";
2387 return \"lea %0@(%c1),%0\";
2390 return \"add%.w %1,%0\";
2394 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2395 (plus:HI (match_operand:HI 1 "general_operand" "dn,rmn")
2400 if (GET_CODE (operands[1]) == CONST_INT)
2403 /* If the constant would be a negative number when interpreted as
2404 HImode, make it negative. This is usually, but not always, done
2405 elsewhere in the compiler. First check for constants out of range,
2406 which could confuse us. */
2408 if (INTVAL (operands[1]) >= 32768)
2409 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2410 INTVAL (operands[1]) - 65536);
2412 if (INTVAL (operands[1]) > 0
2413 && INTVAL (operands[1]) <= 8)
2414 return \"addq%.w %1,%0\";
2415 if (INTVAL (operands[1]) < 0
2416 && INTVAL (operands[1]) >= -8)
2418 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2419 - INTVAL (operands[1]));
2420 return \"subq%.w %1,%0\";
2422 /* On the CPU32 it is faster to use two addqw instructions to
2423 add a small integer (8 < N <= 16) to a register.
2424 Likewise for subqw. */
2425 if (TARGET_CPU32 && REG_P (operands[0]))
2427 if (INTVAL (operands[1]) > 8
2428 && INTVAL (operands[1]) <= 16)
2430 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2431 INTVAL (operands[1]) - 8);
2432 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2434 if (INTVAL (operands[1]) < -8
2435 && INTVAL (operands[1]) >= -16)
2437 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2438 - INTVAL (operands[1]) - 8);
2439 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2443 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2445 return \"lea (%c1,%0),%0\";
2447 return \"lea %0@(%c1),%0\";
2450 return \"add%.w %1,%0\";
2453 (define_insn "addqi3"
2454 [(set (match_operand:QI 0 "general_operand" "=m,d")
2455 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2456 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2461 if (GET_CODE (operands[2]) == CONST_INT)
2463 if (INTVAL (operands[2]) >= 128)
2464 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2465 INTVAL (operands[2]) - 256);
2467 if (INTVAL (operands[2]) > 0
2468 && INTVAL (operands[2]) <= 8)
2469 return \"addq%.b %2,%0\";
2470 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2472 operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]));
2473 return \"subq%.b %2,%0\";
2477 return \"add%.b %2,%0\";
2481 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2482 (plus:QI (match_dup 0)
2483 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2488 if (GET_CODE (operands[1]) == CONST_INT)
2490 if (INTVAL (operands[1]) >= 128)
2491 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2492 INTVAL (operands[1]) - 256);
2494 if (INTVAL (operands[1]) > 0
2495 && INTVAL (operands[1]) <= 8)
2496 return \"addq%.b %1,%0\";
2497 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2499 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
2500 return \"subq%.b %1,%0\";
2504 return \"add%.b %1,%0\";
2508 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2509 (plus:QI (match_operand:QI 1 "general_operand" "dn,dmn")
2515 if (GET_CODE (operands[1]) == CONST_INT)
2517 if (INTVAL (operands[1]) >= 128)
2518 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2519 INTVAL (operands[1]) - 256);
2521 if (INTVAL (operands[1]) > 0
2522 && INTVAL (operands[1]) <= 8)
2523 return \"addq%.b %1,%0\";
2524 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2526 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
2527 return \"subq%.b %1,%0\";
2531 return \"add%.b %1,%0\";
2534 (define_expand "adddf3"
2535 [(set (match_operand:DF 0 "general_operand" "")
2536 (plus:DF (match_operand:DF 1 "general_operand" "")
2537 (match_operand:DF 2 "general_operand" "")))]
2538 "TARGET_68881 || TARGET_FPA"
2542 [(set (match_operand:DF 0 "general_operand" "=x,y")
2543 (plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
2544 (match_operand:DF 2 "general_operand" "xH,dmF")))]
2548 if (rtx_equal_p (operands[0], operands[1]))
2549 return \"fpadd%.d %y2,%0\";
2550 if (rtx_equal_p (operands[0], operands[2]))
2551 return \"fpadd%.d %y1,%0\";
2552 if (which_alternative == 0)
2553 return \"fpadd3%.d %w2,%w1,%0\";
2554 return \"fpadd3%.d %x2,%x1,%0\";
2558 [(set (match_operand:DF 0 "general_operand" "=f")
2559 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2560 (match_operand:DF 1 "general_operand" "0")))]
2565 [(set (match_operand:DF 0 "general_operand" "=f")
2566 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2567 (match_operand:DF 1 "general_operand" "0")))]
2572 [(set (match_operand:DF 0 "general_operand" "=f")
2573 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2574 (match_operand:DF 1 "general_operand" "0")))]
2579 [(set (match_operand:DF 0 "general_operand" "=f")
2580 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2581 (match_operand:DF 2 "general_operand" "fmG")))]
2585 if (REG_P (operands[2]))
2586 return \"f%&add%.x %2,%0\";
2587 return \"f%&add%.d %f2,%0\";
2590 (define_expand "addsf3"
2591 [(set (match_operand:SF 0 "general_operand" "")
2592 (plus:SF (match_operand:SF 1 "general_operand" "")
2593 (match_operand:SF 2 "general_operand" "")))]
2594 "TARGET_68881 || TARGET_FPA"
2598 [(set (match_operand:SF 0 "general_operand" "=x,y")
2599 (plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
2600 (match_operand:SF 2 "general_operand" "xH,rmF")))]
2604 if (rtx_equal_p (operands[0], operands[1]))
2605 return \"fpadd%.s %w2,%0\";
2606 if (rtx_equal_p (operands[0], operands[2]))
2607 return \"fpadd%.s %w1,%0\";
2608 if (which_alternative == 0)
2609 return \"fpadd3%.s %w2,%w1,%0\";
2610 return \"fpadd3%.s %2,%1,%0\";
2614 [(set (match_operand:SF 0 "general_operand" "=f")
2615 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2616 (match_operand:SF 1 "general_operand" "0")))]
2621 [(set (match_operand:SF 0 "general_operand" "=f")
2622 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2623 (match_operand:SF 1 "general_operand" "0")))]
2628 [(set (match_operand:SF 0 "general_operand" "=f")
2629 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2630 (match_operand:SF 1 "general_operand" "0")))]
2635 [(set (match_operand:SF 0 "general_operand" "=f")
2636 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2637 (match_operand:SF 2 "general_operand" "fdmF")))]
2641 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2642 return \"f%$add%.x %2,%0\";
2643 return \"f%$add%.s %f2,%0\";
2646 ;; subtract instructions
2648 (define_insn "subdi_sexthishl32"
2649 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2650 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2651 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2653 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2658 if (ADDRESS_REG_P (operands[0]))
2659 return \"sub%.w %2,%0\";
2660 else if (ADDRESS_REG_P (operands[3]))
2661 return \"move%.w %2,%3\;sub%.l %3,%0\";
2663 return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
2666 (define_insn "subdi_dishl32"
2667 [(set (match_operand:DI 0 "general_operand" "+ro")
2668 (minus:DI (match_dup 0)
2669 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2675 if (GET_CODE (operands[1]) == REG)
2676 operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2678 operands[1] = adj_offsettable_operand (operands[1], 4);
2679 return \"sub%.l %1,%0\";
2682 (define_insn "subdi3"
2683 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2684 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2685 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2686 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2690 if (DATA_REG_P (operands[0]))
2692 if (DATA_REG_P (operands[2]))
2693 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
2694 else if (GET_CODE (operands[2]) == MEM
2695 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2697 return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
2701 if (GET_CODE (operands[2]) == REG)
2702 operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2703 else if (GET_CODE (operands[2]) == CONST_DOUBLE)
2705 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
2706 operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
2708 else if (GET_CODE (operands[2]) == CONST_INT)
2710 operands[1] = operands[2];
2711 operands[2] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
2714 operands[1] = adj_offsettable_operand (operands[2], 4);
2715 /* TODO : for consts, optimize move and sub */
2716 return \"move%.l %2,%3\;sub%.l %1,%R0\;subx%.l %3,%0\";
2719 else if (GET_CODE (operands[0]) == MEM)
2721 if (GET_CODE (operands[2]) == MEM
2722 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2723 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2725 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2727 operands[1] = gen_rtx (MEM, SImode,
2728 gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
2729 gen_rtx (CONST_INT, VOIDmode, -8)));
2730 return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
2732 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2734 operands[1] = XEXP(operands[0], 0);
2735 return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
2739 operands[1] = adj_offsettable_operand (operands[0], 4);
2740 return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2745 (define_insn "subsi3"
2746 [(set (match_operand:SI 0 "general_operand" "=m,r")
2747 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
2748 (match_operand:SI 2 "general_operand" "ds,mrs")))]
2753 [(set (match_operand:SI 0 "general_operand" "=a")
2754 (minus:SI (match_operand:SI 1 "general_operand" "0")
2756 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2760 (define_insn "subhi3"
2761 [(set (match_operand:HI 0 "general_operand" "=m,r")
2762 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2763 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2768 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2769 (minus:HI (match_dup 0)
2770 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2774 (define_insn "subqi3"
2775 [(set (match_operand:QI 0 "general_operand" "=m,d")
2776 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2777 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2782 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2783 (minus:QI (match_dup 0)
2784 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2788 (define_expand "subdf3"
2789 [(set (match_operand:DF 0 "general_operand" "")
2790 (minus:DF (match_operand:DF 1 "general_operand" "")
2791 (match_operand:DF 2 "general_operand" "")))]
2792 "TARGET_68881 || TARGET_FPA"
2796 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
2797 (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
2798 (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
2802 if (rtx_equal_p (operands[0], operands[2]))
2803 return \"fprsub%.d %y1,%0\";
2804 if (rtx_equal_p (operands[0], operands[1]))
2805 return \"fpsub%.d %y2,%0\";
2806 if (which_alternative == 0)
2807 return \"fpsub3%.d %w2,%w1,%0\";
2808 return \"fpsub3%.d %x2,%x1,%0\";
2812 [(set (match_operand:DF 0 "general_operand" "=f")
2813 (minus:DF (match_operand:DF 1 "general_operand" "0")
2814 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2819 [(set (match_operand:DF 0 "general_operand" "=f")
2820 (minus:DF (match_operand:DF 1 "general_operand" "0")
2821 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2826 [(set (match_operand:DF 0 "general_operand" "=f")
2827 (minus:DF (match_operand:DF 1 "general_operand" "0")
2828 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2833 [(set (match_operand:DF 0 "general_operand" "=f")
2834 (minus:DF (match_operand:DF 1 "general_operand" "0")
2835 (match_operand:DF 2 "general_operand" "fmG")))]
2839 if (REG_P (operands[2]))
2840 return \"f%&sub%.x %2,%0\";
2841 return \"f%&sub%.d %f2,%0\";
2844 (define_expand "subsf3"
2845 [(set (match_operand:SF 0 "general_operand" "")
2846 (minus:SF (match_operand:SF 1 "general_operand" "")
2847 (match_operand:SF 2 "general_operand" "")))]
2848 "TARGET_68881 || TARGET_FPA"
2852 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
2853 (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
2854 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
2858 if (rtx_equal_p (operands[0], operands[2]))
2859 return \"fprsub%.s %w1,%0\";
2860 if (rtx_equal_p (operands[0], operands[1]))
2861 return \"fpsub%.s %w2,%0\";
2862 if (which_alternative == 0)
2863 return \"fpsub3%.s %w2,%w1,%0\";
2864 return \"fpsub3%.s %2,%1,%0\";
2868 [(set (match_operand:SF 0 "general_operand" "=f")
2869 (minus:SF (match_operand:SF 1 "general_operand" "0")
2870 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2875 [(set (match_operand:SF 0 "general_operand" "=f")
2876 (minus:SF (match_operand:SF 1 "general_operand" "0")
2877 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2882 [(set (match_operand:SF 0 "general_operand" "=f")
2883 (minus:SF (match_operand:SF 1 "general_operand" "0")
2884 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2889 [(set (match_operand:SF 0 "general_operand" "=f")
2890 (minus:SF (match_operand:SF 1 "general_operand" "0")
2891 (match_operand:SF 2 "general_operand" "fdmF")))]
2895 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2896 return \"f%$sub%.x %2,%0\";
2897 return \"f%$sub%.s %f2,%0\";
2900 ;; multiply instructions
2902 (define_insn "mulhi3"
2903 [(set (match_operand:HI 0 "general_operand" "=d")
2904 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2905 (match_operand:HI 2 "general_operand" "dmn")))]
2909 #if defined(MOTOROLA) && !defined(CRDS)
2910 return \"muls%.w %2,%0\";
2912 return \"muls %2,%0\";
2916 (define_insn "mulhisi3"
2917 [(set (match_operand:SI 0 "general_operand" "=d")
2918 (mult:SI (sign_extend:SI
2919 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2921 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2925 #if defined(MOTOROLA) && !defined(CRDS)
2926 return \"muls%.w %2,%0\";
2928 return \"muls %2,%0\";
2933 [(set (match_operand:SI 0 "general_operand" "=d")
2934 (mult:SI (sign_extend:SI
2935 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2936 (match_operand:SI 2 "const_int_operand" "n")))]
2937 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
2940 #if defined(MOTOROLA) && !defined(CRDS)
2941 return \"muls%.w %2,%0\";
2943 return \"muls %2,%0\";
2947 (define_expand "mulsi3"
2948 [(set (match_operand:SI 0 "general_operand" "")
2949 (mult:SI (match_operand:SI 1 "general_operand" "")
2950 (match_operand:SI 2 "general_operand" "")))]
2951 "TARGET_68020 || TARGET_5200"
2955 [(set (match_operand:SI 0 "general_operand" "=d")
2956 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2957 (match_operand:SI 2 "general_operand" "dmsK")))]
2962 [(set (match_operand:SI 0 "general_operand" "=d")
2963 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2964 (match_operand:SI 2 "general_operand" "d<Q>")))]
2968 (define_insn "umulhisi3"
2969 [(set (match_operand:SI 0 "general_operand" "=d")
2970 (mult:SI (zero_extend:SI
2971 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2973 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2977 #if defined(MOTOROLA) && !defined(CRDS)
2978 return \"mulu%.w %2,%0\";
2980 return \"mulu %2,%0\";
2985 [(set (match_operand:SI 0 "general_operand" "=d")
2986 (mult:SI (zero_extend:SI
2987 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2988 (match_operand:SI 2 "const_int_operand" "n")))]
2989 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
2992 #if defined(MOTOROLA) && !defined(CRDS)
2993 return \"mulu%.w %2,%0\";
2995 return \"mulu %2,%0\";
2999 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
3000 ;; proper matching constraint. This is because the matching is between
3001 ;; the high-numbered word of the DImode operand[0] and operand[1].
3002 (define_expand "umulsidi3"
3004 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
3005 (mult:SI (match_operand:SI 1 "register_operand" "")
3006 (match_operand:SI 2 "nonimmediate_operand" "")))
3007 (set (subreg:SI (match_dup 0) 0)
3008 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3009 (zero_extend:DI (match_dup 2)))
3010 (const_int 32))))])]
3011 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3015 [(set (match_operand:SI 0 "register_operand" "=d")
3016 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3017 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3018 (set (match_operand:SI 3 "register_operand" "=d")
3019 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3020 (zero_extend:DI (match_dup 2)))
3022 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3025 ; Match immediate case. For 2.4 only match things < 2^31.
3026 ; It's tricky with larger values in these patterns since we need to match
3027 ; values between the two parallel multiplies, between a CONST_DOUBLE and
3030 [(set (match_operand:SI 0 "register_operand" "=d")
3031 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3032 (match_operand:SI 2 "const_int_operand" "n")))
3033 (set (match_operand:SI 3 "register_operand" "=d")
3034 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3037 "TARGET_68020 && !TARGET_68060 && !TARGET_5200
3038 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
3041 (define_expand "mulsidi3"
3043 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
3044 (mult:SI (match_operand:SI 1 "register_operand" "")
3045 (match_operand:SI 2 "nonimmediate_operand" "")))
3046 (set (subreg:SI (match_dup 0) 0)
3047 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3048 (sign_extend:DI (match_dup 2)))
3049 (const_int 32))))])]
3050 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3054 [(set (match_operand:SI 0 "register_operand" "=d")
3055 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3056 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3057 (set (match_operand:SI 3 "register_operand" "=d")
3058 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3059 (sign_extend:DI (match_dup 2)))
3061 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3065 [(set (match_operand:SI 0 "register_operand" "=d")
3066 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3067 (match_operand:SI 2 "const_sint32_operand" "")))
3068 (set (match_operand:SI 3 "register_operand" "=d")
3069 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3072 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3075 (define_expand "umulsi3_highpart"
3077 [(set (match_operand:SI 0 "register_operand" "")
3080 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
3081 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
3083 (clobber (match_dup 3))])]
3084 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3087 operands[3] = gen_reg_rtx (SImode);
3088 if (GET_CODE (operands[2]) == CONST_INT
3089 || GET_CODE (operands[2]) == CONST_DOUBLE)
3091 if (! const_uint32_operand (operands[2], VOIDmode))
3093 /* We have to adjust the operand order for the matching constraints. */
3094 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
3095 operands[1], operands[2]));
3101 [(set (match_operand:SI 0 "register_operand" "=d")
3104 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3105 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3107 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3108 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3111 (define_insn "const_umulsi3_highpart"
3112 [(set (match_operand:SI 0 "register_operand" "=d")
3115 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
3116 (match_operand 3 "const_uint32_operand" ""))
3118 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3119 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3122 (define_expand "smulsi3_highpart"
3124 [(set (match_operand:SI 0 "register_operand" "")
3127 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3128 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
3130 (clobber (match_dup 3))])]
3131 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3134 operands[3] = gen_reg_rtx (SImode);
3135 if (GET_CODE (operands[2]) == CONST_INT
3136 || GET_CODE (operands[2]) == CONST_DOUBLE)
3138 if (! const_sint32_operand (operands[2], VOIDmode))
3140 /* We have to adjust the operand order for the matching constraints. */
3141 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
3142 operands[1], operands[2]));
3148 [(set (match_operand:SI 0 "register_operand" "=d")
3151 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3152 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3154 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3155 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3158 (define_insn "const_smulsi3_highpart"
3159 [(set (match_operand:SI 0 "register_operand" "=d")
3162 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
3163 (match_operand 3 "const_sint32_operand" ""))
3165 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3166 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3169 (define_expand "muldf3"
3170 [(set (match_operand:DF 0 "general_operand" "")
3171 (mult:DF (match_operand:DF 1 "general_operand" "")
3172 (match_operand:DF 2 "general_operand" "")))]
3173 "TARGET_68881 || TARGET_FPA"
3177 [(set (match_operand:DF 0 "general_operand" "=x,y")
3178 (mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
3179 (match_operand:DF 2 "general_operand" "xH,rmF")))]
3183 if (rtx_equal_p (operands[1], operands[2]))
3184 return \"fpsqr%.d %y1,%0\";
3185 if (rtx_equal_p (operands[0], operands[1]))
3186 return \"fpmul%.d %y2,%0\";
3187 if (rtx_equal_p (operands[0], operands[2]))
3188 return \"fpmul%.d %y1,%0\";
3189 if (which_alternative == 0)
3190 return \"fpmul3%.d %w2,%w1,%0\";
3191 return \"fpmul3%.d %x2,%x1,%0\";
3195 [(set (match_operand:DF 0 "general_operand" "=f")
3196 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
3197 (match_operand:DF 1 "general_operand" "0")))]
3202 [(set (match_operand:DF 0 "general_operand" "=f")
3203 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
3204 (match_operand:DF 1 "general_operand" "0")))]
3209 [(set (match_operand:DF 0 "general_operand" "=f")
3210 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
3211 (match_operand:DF 1 "general_operand" "0")))]
3216 [(set (match_operand:DF 0 "general_operand" "=f")
3217 (mult:DF (match_operand:DF 1 "general_operand" "%0")
3218 (match_operand:DF 2 "general_operand" "fmG")))]
3222 if (GET_CODE (operands[2]) == CONST_DOUBLE
3223 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
3225 int i = floating_exact_log2 (operands[2]);
3226 operands[2] = gen_rtx (CONST_INT, VOIDmode, i);
3227 return \"fscale%.l %2,%0\";
3229 if (REG_P (operands[2]))
3230 return \"f%&mul%.x %2,%0\";
3231 return \"f%&mul%.d %f2,%0\";
3234 (define_expand "mulsf3"
3235 [(set (match_operand:SF 0 "general_operand" "")
3236 (mult:SF (match_operand:SF 1 "general_operand" "")
3237 (match_operand:SF 2 "general_operand" "")))]
3238 "TARGET_68881 || TARGET_FPA"
3242 [(set (match_operand:SF 0 "general_operand" "=x,y")
3243 (mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
3244 (match_operand:SF 2 "general_operand" "xH,rmF")))]
3248 if (rtx_equal_p (operands[1], operands[2]))
3249 return \"fpsqr%.s %w1,%0\";
3250 if (rtx_equal_p (operands[0], operands[1]))
3251 return \"fpmul%.s %w2,%0\";
3252 if (rtx_equal_p (operands[0], operands[2]))
3253 return \"fpmul%.s %w1,%0\";
3254 if (which_alternative == 0)
3255 return \"fpmul3%.s %w2,%w1,%0\";
3256 return \"fpmul3%.s %2,%1,%0\";
3260 [(set (match_operand:SF 0 "general_operand" "=f")
3261 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
3262 (match_operand:SF 1 "general_operand" "0")))]
3266 return (TARGET_68040_ONLY
3267 ? \"fsmul%.l %2,%0\"
3268 : \"fsglmul%.l %2,%0\");
3272 [(set (match_operand:SF 0 "general_operand" "=f")
3273 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
3274 (match_operand:SF 1 "general_operand" "0")))]
3278 return (TARGET_68040_ONLY
3279 ? \"fsmul%.w %2,%0\"
3280 : \"fsglmul%.w %2,%0\");
3284 [(set (match_operand:SF 0 "general_operand" "=f")
3285 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
3286 (match_operand:SF 1 "general_operand" "0")))]
3290 return (TARGET_68040_ONLY
3291 ? \"fsmul%.b %2,%0\"
3292 : \"fsglmul%.b %2,%0\");
3296 [(set (match_operand:SF 0 "general_operand" "=f")
3297 (mult:SF (match_operand:SF 1 "general_operand" "%0")
3298 (match_operand:SF 2 "general_operand" "fdmF")))]
3302 #ifdef FSGLMUL_USE_S
3303 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3304 return (TARGET_68040_ONLY
3305 ? \"fsmul%.s %2,%0\"
3306 : \"fsglmul%.s %2,%0\");
3308 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3309 return (TARGET_68040_ONLY
3310 ? \"fsmul%.x %2,%0\"
3311 : \"fsglmul%.x %2,%0\");
3313 return (TARGET_68040_ONLY
3314 ? \"fsmul%.s %f2,%0\"
3315 : \"fsglmul%.s %f2,%0\");
3318 ;; divide instructions
3320 (define_expand "divdf3"
3321 [(set (match_operand:DF 0 "general_operand" "")
3322 (div:DF (match_operand:DF 1 "general_operand" "")
3323 (match_operand:DF 2 "general_operand" "")))]
3324 "TARGET_68881 || TARGET_FPA"
3328 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
3329 (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
3330 (match_operand:DF 2 "general_operand" "xH,rmF,0")))]
3334 if (rtx_equal_p (operands[0], operands[2]))
3335 return \"fprdiv%.d %y1,%0\";
3336 if (rtx_equal_p (operands[0], operands[1]))
3337 return \"fpdiv%.d %y2,%0\";
3338 if (which_alternative == 0)
3339 return \"fpdiv3%.d %w2,%w1,%0\";
3340 return \"fpdiv3%.d %x2,%x1,%x0\";
3344 [(set (match_operand:DF 0 "general_operand" "=f")
3345 (div:DF (match_operand:DF 1 "general_operand" "0")
3346 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
3351 [(set (match_operand:DF 0 "general_operand" "=f")
3352 (div:DF (match_operand:DF 1 "general_operand" "0")
3353 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
3358 [(set (match_operand:DF 0 "general_operand" "=f")
3359 (div:DF (match_operand:DF 1 "general_operand" "0")
3360 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
3365 [(set (match_operand:DF 0 "general_operand" "=f")
3366 (div:DF (match_operand:DF 1 "general_operand" "0")
3367 (match_operand:DF 2 "general_operand" "fmG")))]
3371 if (REG_P (operands[2]))
3372 return \"f%&div%.x %2,%0\";
3373 return \"f%&div%.d %f2,%0\";
3376 (define_expand "divsf3"
3377 [(set (match_operand:SF 0 "general_operand" "")
3378 (div:SF (match_operand:SF 1 "general_operand" "")
3379 (match_operand:SF 2 "general_operand" "")))]
3380 "TARGET_68881 || TARGET_FPA"
3384 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
3385 (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
3386 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
3390 if (rtx_equal_p (operands[0], operands[1]))
3391 return \"fpdiv%.s %w2,%0\";
3392 if (rtx_equal_p (operands[0], operands[2]))
3393 return \"fprdiv%.s %w1,%0\";
3394 if (which_alternative == 0)
3395 return \"fpdiv3%.s %w2,%w1,%0\";
3396 return \"fpdiv3%.s %2,%1,%0\";
3400 [(set (match_operand:SF 0 "general_operand" "=f")
3401 (div:SF (match_operand:SF 1 "general_operand" "0")
3402 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
3406 return (TARGET_68040_ONLY
3407 ? \"fsdiv%.l %2,%0\"
3408 : \"fsgldiv%.l %2,%0\");
3412 [(set (match_operand:SF 0 "general_operand" "=f")
3413 (div:SF (match_operand:SF 1 "general_operand" "0")
3414 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3418 return (TARGET_68040_ONLY
3419 ? \"fsdiv%.w %2,%0\"
3420 : \"fsgldiv%.w %2,%0\");
3424 [(set (match_operand:SF 0 "general_operand" "=f")
3425 (div:SF (match_operand:SF 1 "general_operand" "0")
3426 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3430 return (TARGET_68040_ONLY
3431 ? \"fsdiv%.b %2,%0\"
3432 : \"fsgldiv%.b %2,%0\");
3436 [(set (match_operand:SF 0 "general_operand" "=f")
3437 (div:SF (match_operand:SF 1 "general_operand" "0")
3438 (match_operand:SF 2 "general_operand" "fdmF")))]
3442 #ifdef FSGLDIV_USE_S
3443 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3444 return (TARGET_68040_ONLY
3445 ? \"fsdiv%.s %2,%0\"
3446 : \"fsgldiv%.s %2,%0\");
3448 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3449 return (TARGET_68040_ONLY
3450 ? \"fsdiv%.x %2,%0\"
3451 : \"fsgldiv%.x %2,%0\");
3453 return (TARGET_68040_ONLY
3454 ? \"fsdiv%.s %f2,%0\"
3455 : \"fsgldiv%.s %f2,%0\");
3458 ;; Remainder instructions.
3460 (define_insn "divmodsi4"
3461 [(set (match_operand:SI 0 "general_operand" "=d")
3462 (div:SI (match_operand:SI 1 "general_operand" "0")
3463 (match_operand:SI 2 "general_operand" "dmsK")))
3464 (set (match_operand:SI 3 "general_operand" "=d")
3465 (mod:SI (match_dup 1) (match_dup 2)))]
3466 "TARGET_68020 && !TARGET_5200"
3469 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3470 return \"divs%.l %2,%0\";
3472 return \"divsl%.l %2,%3:%0\";
3475 (define_insn "udivmodsi4"
3476 [(set (match_operand:SI 0 "general_operand" "=d")
3477 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3478 (match_operand:SI 2 "general_operand" "dmsK")))
3479 (set (match_operand:SI 3 "general_operand" "=d")
3480 (umod:SI (match_dup 1) (match_dup 2)))]
3481 "TARGET_68020 && !TARGET_5200"
3484 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3485 return \"divu%.l %2,%0\";
3487 return \"divul%.l %2,%3:%0\";
3490 (define_insn "divmodhi4"
3491 [(set (match_operand:HI 0 "general_operand" "=d")
3492 (div:HI (match_operand:HI 1 "general_operand" "0")
3493 (match_operand:HI 2 "general_operand" "dmsK")))
3494 (set (match_operand:HI 3 "general_operand" "=d")
3495 (mod:HI (match_dup 1) (match_dup 2)))]
3500 output_asm_insn (\"ext%.l %0\;divs%.w %2,%0\", operands);
3502 output_asm_insn (\"extl %0\;divs %2,%0\", operands);
3504 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3507 return \"move%.l %0,%3\;swap %3\";
3513 (define_insn "udivmodhi4"
3514 [(set (match_operand:HI 0 "general_operand" "=d")
3515 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3516 (match_operand:HI 2 "general_operand" "dmsK")))
3517 (set (match_operand:HI 3 "general_operand" "=d")
3518 (umod:HI (match_dup 1) (match_dup 2)))]
3523 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
3525 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
3527 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3530 return \"move%.l %0,%3\;swap %3\";
3536 ;; logical-and instructions
3538 ;; "anddi3" is mainly here to help combine().
3539 (define_insn "anddi3"
3540 [(set (match_operand:DI 0 "general_operand" "=o,d")
3541 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
3542 (match_operand:DI 2 "general_operand" "dn,don")))]
3547 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3548 if (GET_CODE (operands[2]) == CONST_DOUBLE
3549 || GET_CODE (operands[2]) == CONST_INT)
3553 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3555 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3556 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3561 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3563 switch (INTVAL (hi))
3566 output_asm_insn (\"clr%.l %0\", operands);
3574 xoperands[0] = operands[0];
3576 output_asm_insn (output_andsi3 (xoperands), xoperands);
3579 if (GET_CODE (operands[0]) == REG)
3580 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3582 operands[0] = adj_offsettable_operand (operands[0], 4);
3583 switch (INTVAL (lo))
3586 output_asm_insn (\"clr%.l %0\", operands);
3594 xoperands[0] = operands[0];
3596 output_asm_insn (output_andsi3 (xoperands), xoperands);
3601 if (GET_CODE (operands[0]) != REG)
3603 operands[1] = adj_offsettable_operand (operands[0], 4);
3604 return \"and%.l %2,%0\;and%.l %R2,%1\";
3606 if (GET_CODE (operands[2]) != REG)
3608 operands[1] = adj_offsettable_operand (operands[2], 4);
3609 return \"and%.l %2,%0\;and%.l %1,%R0\";
3611 return \"and%.l %2,%0\;and%.l %R2,%R0\";
3614 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3615 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3616 ;; can't allocate pseudos into it.
3618 (define_expand "andsi3"
3619 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3620 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3621 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3625 (define_insn "andsi3_internal"
3626 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3627 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3628 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3632 return output_andsi3 (operands);
3635 (define_insn "andsi3_5200"
3636 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3637 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3638 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3642 (define_insn "andhi3"
3643 [(set (match_operand:HI 0 "general_operand" "=m,d")
3644 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3645 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3650 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3651 (and:HI (match_dup 0)
3652 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3657 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3658 (and:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3663 (define_insn "andqi3"
3664 [(set (match_operand:QI 0 "general_operand" "=m,d")
3665 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3666 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3671 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3672 (and:QI (match_dup 0)
3673 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3678 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3679 (and:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3684 ;; inclusive-or instructions
3686 (define_insn "iordi_zext"
3687 [(set (match_operand:DI 0 "general_operand" "=o,d")
3688 (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
3689 (match_operand:DI 2 "general_operand" "0,0")))]
3696 if (GET_CODE (operands[0]) == REG)
3697 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3699 operands[0] = adj_offsettable_operand (operands[0], 4);
3700 if (GET_MODE (operands[1]) == SImode)
3701 return \"or%.l %1,%0\";
3702 byte_mode = (GET_MODE (operands[1]) == QImode);
3703 if (GET_CODE (operands[0]) == MEM)
3704 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3706 return \"or%.b %1,%0\";
3708 return \"or%.w %1,%0\";
3711 ;; "iordi3" is mainly here to help combine().
3712 (define_insn "iordi3"
3713 [(set (match_operand:DI 0 "general_operand" "=o,d")
3714 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
3715 (match_operand:DI 2 "general_operand" "dn,don")))]
3720 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3721 if (GET_CODE (operands[2]) == CONST_DOUBLE
3722 || GET_CODE (operands[2]) == CONST_INT)
3726 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3728 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3729 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3734 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3736 switch (INTVAL (hi))
3741 /* FIXME : a scratch register would be welcome here if operand[0]
3742 is not a register */
3743 output_asm_insn (\"move%.l %#-1,%0\", operands);
3749 xoperands[0] = operands[0];
3751 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3754 if (GET_CODE (operands[0]) == REG)
3755 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3757 operands[0] = adj_offsettable_operand (operands[0], 4);
3758 switch (INTVAL (lo))
3763 /* FIXME : a scratch register would be welcome here if operand[0]
3764 is not a register */
3765 output_asm_insn (\"move%.l %#-1,%R0\", operands);
3771 xoperands[0] = operands[0];
3773 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3778 if (GET_CODE (operands[0]) != REG)
3780 operands[1] = adj_offsettable_operand (operands[0], 4);
3781 return \"or%.l %2,%0\;or%.l %R2,%1\";
3783 if (GET_CODE (operands[2]) != REG)
3785 operands[1] = adj_offsettable_operand (operands[2], 4);
3786 return \"or%.l %2,%0\;or%.l %1,%R0\";
3788 return \"or%.l %2,%0\;or%.l %R2,%R0\";
3791 (define_expand "iorsi3"
3792 [(set (match_operand:SI 0 "general_operand" "")
3793 (ior:SI (match_operand:SI 1 "general_operand" "")
3794 (match_operand:SI 2 "general_operand" "")))]
3798 (define_insn "iorsi3_internal"
3799 [(set (match_operand:SI 0 "general_operand" "=m,d")
3800 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3801 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3805 return output_iorsi3 (operands);
3808 (define_insn "iorsi3_5200"
3809 [(set (match_operand:SI 0 "general_operand" "=m,d")
3810 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3811 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3815 (define_insn "iorhi3"
3816 [(set (match_operand:HI 0 "general_operand" "=m,d")
3817 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3818 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3823 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3824 (ior:HI (match_dup 0)
3825 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3830 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3831 (ior:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3836 (define_insn "iorqi3"
3837 [(set (match_operand:QI 0 "general_operand" "=m,d")
3838 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3839 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3844 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3845 (ior:QI (match_dup 0)
3846 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3851 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3852 (ior:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3857 ;; On all 68k models, this makes faster code in a special case.
3858 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3860 (define_insn "iorsi_zexthi_ashl16"
3861 [(set (match_operand:SI 0 "general_operand" "=&d")
3862 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rmn"))
3863 (ashift:SI (match_operand:SI 2 "general_operand" "or")
3869 if (GET_CODE (operands[2]) != REG)
3870 operands[2] = adj_offsettable_operand (operands[2], 2);
3871 if (GET_CODE (operands[2]) != REG
3872 || REGNO (operands[2]) != REGNO (operands[0]))
3873 output_asm_insn (\"move%.w %2,%0\", operands);
3874 return \"swap %0\;mov%.w %1,%0\";
3877 (define_insn "iorsi_zext"
3878 [(set (match_operand:SI 0 "general_operand" "=o,d")
3879 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3880 (match_operand:SI 2 "general_operand" "0,0")))]
3887 byte_mode = (GET_MODE (operands[1]) == QImode);
3888 if (GET_CODE (operands[0]) == MEM)
3889 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3891 return \"or%.b %1,%0\";
3893 return \"or%.w %1,%0\";
3898 ;; "xordi3" is mainly here to help combine().
3899 (define_insn "xordi3"
3900 [(set (match_operand:DI 0 "general_operand" "=od")
3901 (xor:DI (match_operand:DI 1 "general_operand" "%0")
3902 (match_operand:DI 2 "general_operand" "dn")))]
3907 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3908 if (GET_CODE (operands[2]) == CONST_DOUBLE
3909 || GET_CODE (operands[2]) == CONST_INT)
3913 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3915 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3916 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3921 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3923 switch (INTVAL (hi))
3928 output_asm_insn (\"not%.l %0\", operands);
3931 /* FIXME : a scratch register would be welcome here if
3932 -128 <= INTVAL (hi) < -1 */
3936 xoperands[0] = operands[0];
3938 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3941 if (GET_CODE (operands[0]) == REG)
3942 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3944 operands[0] = adj_offsettable_operand (operands[0], 4);
3945 switch (INTVAL (lo))
3950 output_asm_insn (\"not%.l %0\", operands);
3953 /* FIXME : a scratch register would be welcome here if
3954 -128 <= INTVAL (lo) < -1 */
3956 /* FIXME : this should be merged with xorsi3 */
3960 xoperands[0] = operands[0];
3962 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3967 if (GET_CODE (operands[0]) != REG)
3969 operands[1] = adj_offsettable_operand (operands[0], 4);
3970 return \"eor%.l %2,%0\;eor%.l %R2,%1\";
3972 if (GET_CODE (operands[2]) != REG)
3974 operands[1] = adj_offsettable_operand (operands[2], 4);
3975 return \"eor%.l %2,%0\;eor%.l %1,%R0\";
3977 return \"eor%.l %2,%0\;eor%.l %R2,%R0\";
3980 (define_expand "xorsi3"
3981 [(set (match_operand:SI 0 "general_operand" "")
3982 (xor:SI (match_operand:SI 1 "general_operand" "")
3983 (match_operand:SI 2 "general_operand" "")))]
3987 (define_insn "xorsi3_internal"
3988 [(set (match_operand:SI 0 "general_operand" "=do,m")
3989 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3990 (match_operand:SI 2 "general_operand" "di,dKs")))]
3994 return output_xorsi3 (operands);
3997 (define_insn "xorsi3_5200"
3998 [(set (match_operand:SI 0 "general_operand" "=dm,d")
3999 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
4000 (match_operand:SI 2 "general_operand" "d,Ks")))]
4004 (define_insn "xorhi3"
4005 [(set (match_operand:HI 0 "general_operand" "=dm")
4006 (xor:HI (match_operand:HI 1 "general_operand" "%0")
4007 (match_operand:HI 2 "general_operand" "dn")))]
4012 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4013 (xor:HI (match_dup 0)
4014 (match_operand:HI 1 "general_operand" "dn")))]
4019 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4020 (xor:HI (match_operand:HI 1 "general_operand" "dn")
4025 (define_insn "xorqi3"
4026 [(set (match_operand:QI 0 "general_operand" "=dm")
4027 (xor:QI (match_operand:QI 1 "general_operand" "%0")
4028 (match_operand:QI 2 "general_operand" "dn")))]
4033 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4034 (xor:QI (match_dup 0)
4035 (match_operand:QI 1 "general_operand" "dn")))]
4040 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4041 (xor:QI (match_operand:QI 1 "general_operand" "dn")
4046 ;; negation instructions
4048 (define_expand "negdi2"
4049 [(set (match_operand:DI 0 "general_operand" "")
4050 (neg:DI (match_operand:DI 1 "general_operand" "")))]
4055 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
4057 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
4061 (define_insn "negdi2_internal"
4062 [(set (match_operand:DI 0 "general_operand" "=<,do,!*a")
4063 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
4067 if (which_alternative == 0)
4068 return \"neg%.l %0\;negx%.l %0\";
4069 if (GET_CODE (operands[0]) == REG)
4070 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4072 operands[1] = adj_offsettable_operand (operands[0], 4);
4073 if (ADDRESS_REG_P (operands[0]))
4074 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
4076 return \"neg%.l %1\;negx%.l %0\";
4079 (define_insn "negdi2_5200"
4080 [(set (match_operand:DI 0 "general_operand" "=d")
4081 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
4085 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4086 return \"neg%.l %1\;negx%.l %0\";
4089 (define_expand "negsi2"
4090 [(set (match_operand:SI 0 "general_operand" "")
4091 (neg:SI (match_operand:SI 1 "general_operand" "")))]
4096 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
4098 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
4102 (define_insn "negsi2_internal"
4103 [(set (match_operand:SI 0 "general_operand" "=dm")
4104 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4108 (define_insn "negsi2_5200"
4109 [(set (match_operand:SI 0 "general_operand" "=d")
4110 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4114 (define_insn "neghi2"
4115 [(set (match_operand:HI 0 "general_operand" "=dm")
4116 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
4121 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4122 (neg:HI (match_dup 0)))]
4126 (define_insn "negqi2"
4127 [(set (match_operand:QI 0 "general_operand" "=dm")
4128 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
4133 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4134 (neg:QI (match_dup 0)))]
4138 ;; If using software floating point, just flip the sign bit.
4140 (define_expand "negsf2"
4141 [(set (match_operand:SF 0 "general_operand" "")
4142 (neg:SF (match_operand:SF 1 "general_operand" "")))]
4146 if (!TARGET_FPA && !TARGET_68881)
4151 target = operand_subword_force (operands[0], 0, SFmode);
4152 result = expand_binop (SImode, xor_optab,
4153 operand_subword_force (operands[1], 0, SFmode),
4154 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
4158 if (result != target)
4159 emit_move_insn (result, target);
4161 /* Make a place for REG_EQUAL. */
4162 emit_move_insn (operands[0], operands[0]);
4168 [(set (match_operand:SF 0 "general_operand" "=x,y")
4169 (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4174 [(set (match_operand:SF 0 "general_operand" "=f,d")
4175 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
4179 if (DATA_REG_P (operands[0]))
4181 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
4182 return \"bchg %1,%0\";
4184 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4185 return \"f%$neg%.x %1,%0\";
4186 return \"f%$neg%.s %f1,%0\";
4189 (define_expand "negdf2"
4190 [(set (match_operand:DF 0 "general_operand" "")
4191 (neg:DF (match_operand:DF 1 "general_operand" "")))]
4195 if (!TARGET_FPA && !TARGET_68881)
4202 target = operand_subword (operands[0], 0, 1, DFmode);
4203 result = expand_binop (SImode, xor_optab,
4204 operand_subword_force (operands[1], 0, DFmode),
4205 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
4209 if (result != target)
4210 emit_move_insn (result, target);
4212 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4213 operand_subword_force (operands[1], 1, DFmode));
4215 insns = get_insns ();
4218 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4224 [(set (match_operand:DF 0 "general_operand" "=x,y")
4225 (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4230 [(set (match_operand:DF 0 "general_operand" "=f,d")
4231 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
4235 if (DATA_REG_P (operands[0]))
4237 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
4238 return \"bchg %1,%0\";
4240 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4241 return \"f%&neg%.x %1,%0\";
4242 return \"f%&neg%.d %f1,%0\";
4245 ;; Sqrt instruction for the 68881
4247 (define_insn "sqrtsf2"
4248 [(set (match_operand:SF 0 "general_operand" "=f")
4249 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
4253 if (FP_REG_P (operands[1]))
4254 return \"f%$sqrt%.x %1,%0\";
4256 return \"f%$sqrt%.s %1,%0\";
4259 (define_insn "sqrtdf2"
4260 [(set (match_operand:DF 0 "general_operand" "=f")
4261 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
4265 if (FP_REG_P (operands[1]))
4266 return \"f%&sqrt%.x %1,%0\";
4268 return \"f%&sqrt%.d %1,%0\";
4271 ;; Absolute value instructions
4272 ;; If using software floating point, just zero the sign bit.
4274 (define_expand "abssf2"
4275 [(set (match_operand:SF 0 "general_operand" "")
4276 (abs:SF (match_operand:SF 1 "general_operand" "")))]
4280 if (!TARGET_FPA && !TARGET_68881)
4285 target = operand_subword_force (operands[0], 0, SFmode);
4286 result = expand_binop (SImode, and_optab,
4287 operand_subword_force (operands[1], 0, SFmode),
4288 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4292 if (result != target)
4293 emit_move_insn (result, target);
4295 /* Make a place for REG_EQUAL. */
4296 emit_move_insn (operands[0], operands[0]);
4302 [(set (match_operand:SF 0 "general_operand" "=x,y")
4303 (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4308 [(set (match_operand:SF 0 "general_operand" "=f")
4309 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
4313 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4314 return \"f%$abs%.x %1,%0\";
4315 return \"f%$abs%.s %f1,%0\";
4318 (define_expand "absdf2"
4319 [(set (match_operand:DF 0 "general_operand" "")
4320 (abs:DF (match_operand:DF 1 "general_operand" "")))]
4324 if (!TARGET_FPA && !TARGET_68881)
4331 target = operand_subword (operands[0], 0, 1, DFmode);
4332 result = expand_binop (SImode, and_optab,
4333 operand_subword_force (operands[1], 0, DFmode),
4334 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4338 if (result != target)
4339 emit_move_insn (result, target);
4341 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4342 operand_subword_force (operands[1], 1, DFmode));
4344 insns = get_insns ();
4347 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4353 [(set (match_operand:DF 0 "general_operand" "=x,y")
4354 (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4359 [(set (match_operand:DF 0 "general_operand" "=f")
4360 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
4364 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4365 return \"f%&abs%.x %1,%0\";
4366 return \"f%&abs%.d %f1,%0\";
4369 ;; one complement instructions
4371 ;; "one_cmpldi2" is mainly here to help combine().
4372 (define_insn "one_cmpldi2"
4373 [(set (match_operand:DI 0 "general_operand" "=dm")
4374 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4379 if (GET_CODE (operands[0]) == REG)
4380 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4381 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4382 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4383 operands[1] = operands[0];
4385 operands[1] = adj_offsettable_operand (operands[0], 4);
4386 return \"not%.l %1\;not%.l %0\";
4389 (define_expand "one_cmplsi2"
4390 [(set (match_operand:SI 0 "general_operand" "")
4391 (not:SI (match_operand:SI 1 "general_operand" "")))]
4396 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4398 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4402 (define_insn "one_cmplsi2_internal"
4403 [(set (match_operand:SI 0 "general_operand" "=dm")
4404 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4408 (define_insn "one_cmplsi2_5200"
4409 [(set (match_operand:SI 0 "general_operand" "=d")
4410 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4414 (define_insn "one_cmplhi2"
4415 [(set (match_operand:HI 0 "general_operand" "=dm")
4416 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4421 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4422 (not:HI (match_dup 0)))]
4426 (define_insn "one_cmplqi2"
4427 [(set (match_operand:QI 0 "general_operand" "=dm")
4428 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4433 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4434 (not:QI (match_dup 0)))]
4438 ;; arithmetic shift instructions
4439 ;; We don't need the shift memory by 1 bit instruction
4441 (define_insn "ashldi_extsi"
4442 [(set (match_operand:DI 0 "general_operand" "=ro")
4444 (match_operator:DI 2 "extend_operator"
4445 [(match_operand:SI 1 "general_operand" "rm")])
4451 if (GET_CODE (operands[0]) == REG)
4452 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4454 operands[2] = adj_offsettable_operand (operands[0], 4);
4455 if (ADDRESS_REG_P (operands[0]))
4456 return \"move%.l %1,%0\;sub%.l %2,%2\";
4458 return \"move%.l %1,%0\;clr%.l %2\";
4461 (define_insn "ashldi_sexthi"
4462 [(set (match_operand:DI 0 "general_operand" "=m,a*d")
4463 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4465 (clobber (match_scratch:SI 2 "=a,X"))]
4470 if (GET_CODE (operands[0]) == MEM)
4472 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4473 return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
4474 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4475 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
4478 operands[3] = adj_offsettable_operand (operands[0], 4);
4479 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
4482 else if (DATA_REG_P (operands[0]))
4483 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
4485 return \"move%.w %1,%0\;sub%.l %R0,%R0\";
4488 (define_insn "ashldi_const32"
4489 [(set (match_operand:DI 0 "general_operand" "=rm")
4490 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
4496 if (GET_CODE (operands[1]) == REG)
4497 operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4499 operands[3] = adj_offsettable_operand (operands[1], 4);
4500 if (GET_CODE (operands[0]) == REG)
4501 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4502 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4503 return \"clr%.l %0\;move%.l %3,%0\";
4504 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4505 return \"move%.l %3,%0\;clr%.l %0\";
4507 operands[2] = adj_offsettable_operand (operands[0], 4);
4508 if (ADDRESS_REG_P (operands[2]))
4509 return \"move%.l %3,%0\;sub%.l %2,%2\";
4511 return \"move%.l %3,%0\;clr%.l %2\";
4514 ;; The predicate below must be general_operand, because ashldi3 allows that
4515 (define_insn "ashldi_const"
4516 [(set (match_operand:DI 0 "general_operand" "=d")
4517 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4518 (match_operand 2 "const_int_operand" "n")))]
4519 "((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4520 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4521 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
4524 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4525 if (INTVAL (operands[2]) == 1)
4526 return \"add%.l %1,%1\;addx%.l %0,%0\";
4527 else if (INTVAL (operands[2]) == 8)
4528 return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
4529 else if (INTVAL (operands[2]) == 16)
4530 return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
4531 else if (INTVAL (operands[2]) == 48)
4532 return \"mov%.l %1,%0\;swap %0\;clr%.l %1\;clr%.w %0\";
4533 else if (INTVAL (operands[2]) == 2)
4534 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4535 else if (INTVAL (operands[2]) == 3)
4536 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4537 else /* 32 < INTVAL (operands[2]) <= 63 */
4539 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 32);
4540 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asl%.l %2,%1\" :
4541 \"moveq %2,%0\;asl%.l %0,%1\", operands);
4542 return \"mov%.l %1,%0\;moveq %#0,%1\";
4546 (define_expand "ashldi3"
4547 [(set (match_operand:DI 0 "general_operand" "")
4548 (ashift:DI (match_operand:DI 1 "general_operand" "")
4549 (match_operand 2 "const_int_operand" "")))]
4553 if (GET_CODE (operands[2]) != CONST_INT
4554 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4555 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4556 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4560 ;; On most 68k models, this makes faster code in a special case.
4562 (define_insn "ashlsi_16"
4563 [(set (match_operand:SI 0 "register_operand" "=d")
4564 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4570 return \"swap %0\;clr%.w %0\";
4573 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4574 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4576 ;; On the 68000, this makes faster code in a special case.
4578 (define_insn "ashlsi_17_24"
4579 [(set (match_operand:SI 0 "register_operand" "=d")
4580 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4581 (match_operand:SI 2 "const_int_operand" "n")))]
4582 "(! TARGET_68020 && !TARGET_5200
4583 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4588 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4589 return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
4592 (define_insn "ashlsi3"
4593 [(set (match_operand:SI 0 "register_operand" "=d")
4594 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4595 (match_operand:SI 2 "general_operand" "dI")))]
4599 if (operands[2] == const1_rtx)
4601 cc_status.flags = CC_NO_OVERFLOW;
4602 return \"add%.l %0,%0\";
4604 return \"lsl%.l %2,%0\";
4607 (define_insn "ashlhi3"
4608 [(set (match_operand:HI 0 "register_operand" "=d")
4609 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4610 (match_operand:HI 2 "general_operand" "dI")))]
4615 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4616 (ashift:HI (match_dup 0)
4617 (match_operand:HI 1 "general_operand" "dI")))]
4621 (define_insn "ashlqi3"
4622 [(set (match_operand:QI 0 "register_operand" "=d")
4623 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4624 (match_operand:QI 2 "general_operand" "dI")))]
4629 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4630 (ashift:QI (match_dup 0)
4631 (match_operand:QI 1 "general_operand" "dI")))]
4635 ;; On most 68k models, this makes faster code in a special case.
4637 (define_insn "ashrsi_16"
4638 [(set (match_operand:SI 0 "register_operand" "=d")
4639 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4642 "swap %0\;ext%.l %0")
4644 ;; On the 68000, this makes faster code in a special case.
4647 [(set (match_operand:SI 0 "register_operand" "=d")
4648 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4649 (match_operand:SI 2 "const_int_operand" "n")))]
4650 "(! TARGET_68020 && !TARGET_5200
4651 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4654 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4655 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4658 (define_insn "subreghi1ashrdi_const32"
4659 [(set (match_operand:HI 0 "general_operand" "=rm")
4660 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4661 (const_int 32)) 1))]
4665 if (GET_CODE (operands[1]) != REG)
4666 operands[1] = adj_offsettable_operand (operands[1], 2);
4667 return \"move%.w %1,%0\";
4670 (define_insn "subregsi1ashrdi_const32"
4671 [(set (match_operand:SI 0 "general_operand" "=rm")
4672 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4673 (const_int 32)) 1))]
4677 return \"move%.l %1,%0\";
4680 (define_insn "ashrdi_const32"
4681 [(set (match_operand:DI 0 "register_operand" "=d")
4682 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4688 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4690 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4692 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4695 (define_insn "ashrdi_const32_mem"
4696 [(set (match_operand:DI 0 "general_operand" "=o,<")
4697 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4699 (clobber (match_scratch:SI 2 "=d,d"))]
4704 if (which_alternative == 1)
4705 operands[3] = operands[0];
4707 operands[3] = adj_offsettable_operand (operands[0], 4);
4709 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4711 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4714 ;; The predicate below must be general_operand, because ashrdi3 allows that
4715 (define_insn "ashrdi_const"
4716 [(set (match_operand:DI 0 "general_operand" "=d")
4717 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4718 (match_operand 2 "const_int_operand" "n")))]
4720 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4721 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4722 || INTVAL (operands[2]) == 31
4723 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
4726 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4727 if (INTVAL (operands[2]) == 63)
4728 return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
4730 if (INTVAL (operands[2]) == 1)
4731 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4732 else if (INTVAL (operands[2]) == 8)
4733 return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
4734 else if (INTVAL (operands[2]) == 16)
4735 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;ext%.l %0\";
4736 else if (INTVAL (operands[2]) == 48)
4737 return \"swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0\";
4738 else if (INTVAL (operands[2]) == 31)
4739 return \"add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0\";
4740 else if (INTVAL (operands[2]) == 2)
4741 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4742 else if (INTVAL (operands[2]) == 3)
4743 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4744 else /* 32 < INTVAL (operands[2]) <= 63 */
4746 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 32);
4747 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asr%.l %2,%0\" :
4748 \"moveq %2,%1\;asr%.l %1,%0\", operands);
4749 output_asm_insn (\"mov%.l %0,%1\;smi %0\", operands);
4750 return INTVAL (operands[2]) >= 15 ? \"ext%.w %d0\" :
4751 TARGET_68020 ? \"extb%.l %0\" : \"ext%.w %0\;ext%.l %0\";
4755 (define_expand "ashrdi3"
4756 [(set (match_operand:DI 0 "general_operand" "")
4757 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4758 (match_operand 2 "const_int_operand" "")))]
4762 if (GET_CODE (operands[2]) != CONST_INT
4763 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4764 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4765 && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
4769 ;; On all 68k models, this makes faster code in a special case.
4771 (define_insn "ashrsi_31"
4772 [(set (match_operand:SI 0 "register_operand" "=d")
4773 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4778 return \"add%.l %0,%0\;subx%.l %0,%0\";
4781 (define_insn "ashrsi3"
4782 [(set (match_operand:SI 0 "register_operand" "=d")
4783 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4784 (match_operand:SI 2 "general_operand" "dI")))]
4788 (define_insn "ashrhi3"
4789 [(set (match_operand:HI 0 "register_operand" "=d")
4790 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4791 (match_operand:HI 2 "general_operand" "dI")))]
4796 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4797 (ashiftrt:HI (match_dup 0)
4798 (match_operand:HI 1 "general_operand" "dI")))]
4802 (define_insn "ashrqi3"
4803 [(set (match_operand:QI 0 "register_operand" "=d")
4804 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4805 (match_operand:QI 2 "general_operand" "dI")))]
4810 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4811 (ashiftrt:QI (match_dup 0)
4812 (match_operand:QI 1 "general_operand" "dI")))]
4816 ;; logical shift instructions
4818 ;; commented out because of reload problems in 950612-1.c
4821 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4822 ;; (const_int 32)) 1))
4823 ;; (set (match_operand:SI 1 "general_operand" "=dm")
4824 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4825 ;; (const_int 32)) 1))]
4829 ;; return \"move%.l %0,%1\";
4834 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4835 ;; (const_int 32)) 0))
4836 ;; (set (match_operand:DI 1 "general_operand" "=do")
4837 ;; (lshiftrt:DI (match_dup 0)
4838 ;; (const_int 32)))]
4842 ;; if (GET_CODE (operands[1]) == REG)
4843 ;; operands[2] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4845 ;; operands[2] = adj_offsettable_operand (operands[1], 4);
4846 ;; return \"move%.l %0,%2\;clr%.l %1\";
4849 (define_insn "subreg1lshrdi_const32"
4850 [(set (match_operand:SI 0 "general_operand" "=rm")
4851 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4852 (const_int 32)) 1))]
4856 return \"move%.l %1,%0\";
4859 (define_insn "lshrdi_const32"
4860 [(set (match_operand:DI 0 "general_operand" "=ro,<,>")
4861 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4867 if (which_alternative == 1)
4868 return \"move%.l %1,%0\;clr%.l %0\";
4869 if (which_alternative == 2)
4870 return \"clr%.l %0\;move%.l %1,%0\";
4871 if (GET_CODE (operands[0]) == REG)
4872 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4874 operands[2] = adj_offsettable_operand (operands[0], 4);
4875 if (GET_CODE (operands[1]) == REG)
4876 operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4878 operands[3] = adj_offsettable_operand (operands[1], 4);
4879 if (ADDRESS_REG_P (operands[0]))
4880 return \"move%.l %1,%2\;sub%.l %0,%0\";
4882 return \"move%.l %1,%2\;clr%.l %0\";
4885 ;; The predicate below must be general_operand, because lshrdi3 allows that
4886 (define_insn "lshrdi_const"
4887 [(set (match_operand:DI 0 "general_operand" "=d")
4888 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4889 (match_operand 2 "const_int_operand" "n")))]
4891 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4892 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4893 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
4896 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4897 if (INTVAL (operands[2]) == 63)
4898 return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
4900 if (INTVAL (operands[2]) == 1)
4901 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4902 else if (INTVAL (operands[2]) == 8)
4903 return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
4904 else if (INTVAL (operands[2]) == 16)
4905 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
4906 else if (INTVAL (operands[2]) == 48)
4907 return \"move%.l %0,%1\;clr%.w %1\;clr%.l %0\;swap %1\";
4908 else if (INTVAL (operands[2]) == 2)
4909 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4910 else if (INTVAL (operands[2]) == 3)
4911 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4912 else /* 32 < INTVAL (operands[2]) <= 63 */
4914 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 32);
4915 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"lsr%.l %2,%0\" :
4916 \"moveq %2,%1\;lsr%.l %1,%0\", operands);
4917 return \"mov%.l %0,%1\;moveq %#0,%0\";
4921 (define_expand "lshrdi3"
4922 [(set (match_operand:DI 0 "general_operand" "")
4923 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
4924 (match_operand 2 "const_int_operand" "")))]
4928 if (GET_CODE (operands[2]) != CONST_INT
4929 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4930 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4931 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4935 ;; On all 68k models, this makes faster code in a special case.
4937 (define_insn "lshrsi_31"
4938 [(set (match_operand:SI 0 "register_operand" "=d")
4939 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4944 return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
4947 ;; On most 68k models, this makes faster code in a special case.
4949 (define_insn "lshrsi_16"
4950 [(set (match_operand:SI 0 "register_operand" "=d")
4951 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4957 return \"clr%.w %0\;swap %0\";
4960 ;; On the 68000, this makes faster code in a special case.
4962 (define_insn "lshrsi_17_24"
4963 [(set (match_operand:SI 0 "register_operand" "=d")
4964 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4965 (match_operand:SI 2 "const_int_operand" "n")))]
4966 "(! TARGET_68020 && !TARGET_5200
4967 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4970 /* I think lsr%.w sets the CC properly. */
4971 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4972 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
4975 (define_insn "lshrsi3"
4976 [(set (match_operand:SI 0 "register_operand" "=d")
4977 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4978 (match_operand:SI 2 "general_operand" "dI")))]
4982 (define_insn "lshrhi3"
4983 [(set (match_operand:HI 0 "register_operand" "=d")
4984 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
4985 (match_operand:HI 2 "general_operand" "dI")))]
4990 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4991 (lshiftrt:HI (match_dup 0)
4992 (match_operand:HI 1 "general_operand" "dI")))]
4996 (define_insn "lshrqi3"
4997 [(set (match_operand:QI 0 "register_operand" "=d")
4998 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
4999 (match_operand:QI 2 "general_operand" "dI")))]
5004 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5005 (lshiftrt:QI (match_dup 0)
5006 (match_operand:QI 1 "general_operand" "dI")))]
5010 ;; rotate instructions
5012 (define_insn "rotlsi3"
5013 [(set (match_operand:SI 0 "register_operand" "=d")
5014 (rotate:SI (match_operand:SI 1 "register_operand" "0")
5015 (match_operand:SI 2 "general_operand" "dINO")))]
5019 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
5021 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
5023 operands[2] = gen_rtx (CONST_INT, VOIDmode, 32 - INTVAL (operands[2]));
5024 return \"ror%.l %2,%0\";
5027 return \"rol%.l %2,%0\";
5030 (define_insn "rotlhi3"
5031 [(set (match_operand:HI 0 "register_operand" "=d")
5032 (rotate:HI (match_operand:HI 1 "register_operand" "0")
5033 (match_operand:HI 2 "general_operand" "dIP")))]
5037 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5039 operands[2] = gen_rtx (CONST_INT, VOIDmode, 16 - INTVAL (operands[2]));
5040 return \"ror%.w %2,%0\";
5043 return \"rol%.w %2,%0\";
5047 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5048 (rotate:HI (match_dup 0)
5049 (match_operand:HI 1 "general_operand" "dIP")))]
5053 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5055 operands[2] = gen_rtx (CONST_INT, VOIDmode, 16 - INTVAL (operands[2]));
5056 return \"ror%.w %2,%0\";
5059 return \"rol%.w %2,%0\";
5062 (define_insn "rotlqi3"
5063 [(set (match_operand:QI 0 "register_operand" "=d")
5064 (rotate:QI (match_operand:QI 1 "register_operand" "0")
5065 (match_operand:QI 2 "general_operand" "dI")))]
5069 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5071 operands[2] = gen_rtx (CONST_INT, VOIDmode, 8 - INTVAL (operands[2]));
5072 return \"ror%.b %2,%0\";
5075 return \"rol%.b %2,%0\";
5079 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5080 (rotate:QI (match_dup 0)
5081 (match_operand:QI 1 "general_operand" "dI")))]
5085 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5087 operands[2] = gen_rtx (CONST_INT, VOIDmode, 8 - INTVAL (operands[2]));
5088 return \"ror%.b %2,%0\";
5091 return \"rol%.b %2,%0\";
5094 (define_insn "rotrsi3"
5095 [(set (match_operand:SI 0 "register_operand" "=d")
5096 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
5097 (match_operand:SI 2 "general_operand" "dI")))]
5101 (define_insn "rotrhi3"
5102 [(set (match_operand:HI 0 "register_operand" "=d")
5103 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
5104 (match_operand:HI 2 "general_operand" "dI")))]
5109 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5110 (rotatert:HI (match_dup 0)
5111 (match_operand:HI 1 "general_operand" "dI")))]
5115 (define_insn "rotrqi3"
5116 [(set (match_operand:QI 0 "register_operand" "=d")
5117 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
5118 (match_operand:QI 2 "general_operand" "dI")))]
5123 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5124 (rotatert:QI (match_dup 0)
5125 (match_operand:QI 1 "general_operand" "dI")))]
5130 ;; Bit set/clear in memory byte.
5132 ;; set bit, bit number is int
5133 (define_insn "bsetmemqi"
5134 [(set (match_operand:QI 0 "memory_operand" "+m")
5135 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5136 (match_operand:SI 1 "general_operand" "d")) 0)
5142 return \"bset %1,%0\";
5145 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
5147 [(set (match_operand:QI 0 "memory_operand" "+m")
5148 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5149 (match_operator:SI 2 "extend_operator"
5150 [(match_operand 1 "general_operand" "d")])) 0)
5156 return \"bset %1,%0\";
5159 ;; clear bit, bit number is int
5160 (define_insn "bclrmemqi"
5161 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5163 (minus:SI (const_int 7)
5164 (match_operand:SI 1 "general_operand" "d")))
5170 return \"bclr %1,%0\";
5173 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
5175 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5177 (minus:SI (const_int 7)
5178 (match_operator:SI 2 "extend_operator"
5179 [(match_operand 1 "general_operand" "d")])))
5185 return \"bclr %1,%0\";
5188 ;; Special cases of bit-field insns which we should
5189 ;; recognize in preference to the general case.
5190 ;; These handle aligned 8-bit and 16-bit fields,
5191 ;; which can usually be done with move instructions.
5194 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5195 ; alignment of structure members is specified.
5197 ; The move is allowed to be odd byte aligned, because that's still faster
5198 ; than an odd byte aligned bit field instruction.
5201 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5203 (match_operand:SI 2 "const_int_operand" "n"))
5204 (match_operand:SI 3 "general_operand" "rmi"))]
5205 "TARGET_68020 && TARGET_BITFIELD
5206 && (INTVAL (operands[2]) % 8) == 0
5207 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
5211 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
5213 return \"move%.l %3,%0\";
5217 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
5218 (match_operand:SI 1 "const_int_operand" "n")
5219 (match_operand:SI 2 "const_int_operand" "n"))
5220 (match_operand:SI 3 "register_operand" "d"))]
5221 "TARGET_68020 && TARGET_BITFIELD
5222 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
5223 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
5224 && (GET_CODE (operands[0]) == REG
5225 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
5228 if (REG_P (operands[0]))
5230 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
5231 return \"bfins %3,%0{%b2:%b1}\";
5235 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
5237 if (GET_CODE (operands[3]) == MEM)
5238 operands[3] = adj_offsettable_operand (operands[3],
5239 (32 - INTVAL (operands[1])) / 8);
5240 if (INTVAL (operands[1]) == 8)
5241 return \"move%.b %3,%0\";
5242 return \"move%.w %3,%0\";
5247 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5248 ; alignment of structure members is specified.
5250 ; The move is allowed to be odd byte aligned, because that's still faster
5251 ; than an odd byte aligned bit field instruction.
5254 [(set (match_operand:SI 0 "general_operand" "=rm")
5255 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
5257 (match_operand:SI 3 "const_int_operand" "n")))]
5258 "TARGET_68020 && TARGET_BITFIELD
5259 && (INTVAL (operands[3]) % 8) == 0
5260 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5264 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5266 return \"move%.l %1,%0\";
5270 [(set (match_operand:SI 0 "general_operand" "=&d")
5271 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
5272 (match_operand:SI 2 "const_int_operand" "n")
5273 (match_operand:SI 3 "const_int_operand" "n")))]
5274 "TARGET_68020 && TARGET_BITFIELD
5275 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5276 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5277 && (GET_CODE (operands[1]) == REG
5278 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5281 cc_status.flags |= CC_NOT_NEGATIVE;
5282 if (REG_P (operands[1]))
5284 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5285 return \"bfextu %1{%b3:%b2},%0\";
5289 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5291 output_asm_insn (\"clr%.l %0\", operands);
5292 if (GET_CODE (operands[0]) == MEM)
5293 operands[0] = adj_offsettable_operand (operands[0],
5294 (32 - INTVAL (operands[1])) / 8);
5295 if (INTVAL (operands[2]) == 8)
5296 return \"move%.b %1,%0\";
5297 return \"move%.w %1,%0\";
5301 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5302 ; alignment of structure members is specified.
5304 ; The move is allowed to be odd byte aligned, because that's still faster
5305 ; than an odd byte aligned bit field instruction.
5308 [(set (match_operand:SI 0 "general_operand" "=rm")
5309 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5311 (match_operand:SI 3 "const_int_operand" "n")))]
5312 "TARGET_68020 && TARGET_BITFIELD
5313 && (INTVAL (operands[3]) % 8) == 0
5314 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5318 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5320 return \"move%.l %1,%0\";
5324 [(set (match_operand:SI 0 "general_operand" "=d")
5325 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
5326 (match_operand:SI 2 "const_int_operand" "n")
5327 (match_operand:SI 3 "const_int_operand" "n")))]
5328 "TARGET_68020 && TARGET_BITFIELD
5329 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5330 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5331 && (GET_CODE (operands[1]) == REG
5332 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5335 if (REG_P (operands[1]))
5337 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5338 return \"bfexts %1{%b3:%b2},%0\";
5342 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5344 if (INTVAL (operands[2]) == 8)
5345 return \"move%.b %1,%0\;extb%.l %0\";
5346 return \"move%.w %1,%0\;ext%.l %0\";
5349 ;; Bit field instructions, general cases.
5350 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5351 ;; so that its address is reloaded.
5353 (define_expand "extv"
5354 [(set (match_operand:SI 0 "general_operand" "")
5355 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5356 (match_operand:SI 2 "general_operand" "")
5357 (match_operand:SI 3 "general_operand" "")))]
5358 "TARGET_68020 && TARGET_BITFIELD"
5362 [(set (match_operand:SI 0 "general_operand" "=d")
5363 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5364 (match_operand:SI 2 "general_operand" "di")
5365 (match_operand:SI 3 "general_operand" "di")))]
5366 "TARGET_68020 && TARGET_BITFIELD"
5367 "bfexts %1{%b3:%b2},%0")
5369 (define_expand "extzv"
5370 [(set (match_operand:SI 0 "general_operand" "")
5371 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5372 (match_operand:SI 2 "general_operand" "")
5373 (match_operand:SI 3 "general_operand" "")))]
5374 "TARGET_68020 && TARGET_BITFIELD"
5378 [(set (match_operand:SI 0 "general_operand" "=d,d")
5379 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
5380 (match_operand:SI 2 "general_operand" "di,di")
5381 (match_operand:SI 3 "general_operand" "di,di")))]
5382 "TARGET_68020 && TARGET_BITFIELD"
5385 if (GET_CODE (operands[2]) == CONST_INT)
5387 if (INTVAL (operands[2]) != 32)
5388 cc_status.flags |= CC_NOT_NEGATIVE;
5394 return \"bfextu %1{%b3:%b2},%0\";
5398 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5399 (match_operand:SI 1 "general_operand" "di")
5400 (match_operand:SI 2 "general_operand" "di"))
5401 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5402 (match_operand 3 "const_int_operand" "n")))]
5403 "TARGET_68020 && TARGET_BITFIELD
5404 && (INTVAL (operands[3]) == -1
5405 || (GET_CODE (operands[1]) == CONST_INT
5406 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5410 return \"bfchg %0{%b2:%b1}\";
5414 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5415 (match_operand:SI 1 "general_operand" "di")
5416 (match_operand:SI 2 "general_operand" "di"))
5418 "TARGET_68020 && TARGET_BITFIELD"
5422 return \"bfclr %0{%b2:%b1}\";
5426 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5427 (match_operand:SI 1 "general_operand" "di")
5428 (match_operand:SI 2 "general_operand" "di"))
5430 "TARGET_68020 && TARGET_BITFIELD"
5434 return \"bfset %0{%b2:%b1}\";
5437 (define_expand "insv"
5438 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
5439 (match_operand:SI 1 "general_operand" "")
5440 (match_operand:SI 2 "general_operand" ""))
5441 (match_operand:SI 3 "register_operand" ""))]
5442 "TARGET_68020 && TARGET_BITFIELD"
5446 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5447 (match_operand:SI 1 "general_operand" "di")
5448 (match_operand:SI 2 "general_operand" "di"))
5449 (match_operand:SI 3 "register_operand" "d"))]
5450 "TARGET_68020 && TARGET_BITFIELD"
5451 "bfins %3,%0{%b2:%b1}")
5453 ;; Now recognize bit field insns that operate on registers
5454 ;; (or at least were intended to do so).
5457 [(set (match_operand:SI 0 "general_operand" "=d")
5458 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5459 (match_operand:SI 2 "general_operand" "di")
5460 (match_operand:SI 3 "general_operand" "di")))]
5461 "TARGET_68020 && TARGET_BITFIELD"
5462 "bfexts %1{%b3:%b2},%0")
5465 [(set (match_operand:SI 0 "general_operand" "=d")
5466 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5467 (match_operand:SI 2 "general_operand" "di")
5468 (match_operand:SI 3 "general_operand" "di")))]
5469 "TARGET_68020 && TARGET_BITFIELD"
5472 if (GET_CODE (operands[2]) == CONST_INT)
5474 if (INTVAL (operands[2]) != 32)
5475 cc_status.flags |= CC_NOT_NEGATIVE;
5481 return \"bfextu %1{%b3:%b2},%0\";
5485 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5486 (match_operand:SI 1 "general_operand" "di")
5487 (match_operand:SI 2 "general_operand" "di"))
5489 "TARGET_68020 && TARGET_BITFIELD"
5493 return \"bfclr %0{%b2:%b1}\";
5497 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5498 (match_operand:SI 1 "general_operand" "di")
5499 (match_operand:SI 2 "general_operand" "di"))
5501 "TARGET_68020 && TARGET_BITFIELD"
5505 return \"bfset %0{%b2:%b1}\";
5509 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5510 (match_operand:SI 1 "general_operand" "di")
5511 (match_operand:SI 2 "general_operand" "di"))
5512 (match_operand:SI 3 "register_operand" "d"))]
5513 "TARGET_68020 && TARGET_BITFIELD"
5517 /* These special cases are now recognized by a specific pattern. */
5518 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5519 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5520 return \"move%.w %3,%0\";
5521 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5522 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5523 return \"move%.b %3,%0\";
5525 return \"bfins %3,%0{%b2:%b1}\";
5528 ;; Special patterns for optimizing bit-field instructions.
5532 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5533 (match_operand:SI 1 "const_int_operand" "n")
5534 (match_operand:SI 2 "general_operand" "di")))]
5535 "TARGET_68020 && TARGET_BITFIELD"
5538 if (operands[1] == const1_rtx
5539 && GET_CODE (operands[2]) == CONST_INT)
5541 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5542 return output_btst (operands,
5543 gen_rtx (CONST_INT, VOIDmode,
5544 width - INTVAL (operands[2])),
5547 /* Pass 1000 as SIGNPOS argument so that btst will
5548 not think we are testing the sign bit for an `and'
5549 and assume that nonzero implies a negative result. */
5551 if (INTVAL (operands[1]) != 32)
5552 cc_status.flags = CC_NOT_NEGATIVE;
5553 return \"bftst %0{%b2:%b1}\";
5557 ;;; now handle the register cases
5560 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5561 (match_operand:SI 1 "const_int_operand" "n")
5562 (match_operand:SI 2 "general_operand" "di")))]
5563 "TARGET_68020 && TARGET_BITFIELD"
5566 if (operands[1] == const1_rtx
5567 && GET_CODE (operands[2]) == CONST_INT)
5569 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5570 return output_btst (operands,
5571 gen_rtx (CONST_INT, VOIDmode,
5572 width - INTVAL (operands[2])),
5575 /* Pass 1000 as SIGNPOS argument so that btst will
5576 not think we are testing the sign bit for an `and'
5577 and assume that nonzero implies a negative result. */
5579 if (INTVAL (operands[1]) != 32)
5580 cc_status.flags = CC_NOT_NEGATIVE;
5581 return \"bftst %0{%b2:%b1}\";
5584 (define_insn "scc0_di"
5585 [(set (match_operand:QI 0 "general_operand" "=dm")
5586 (match_operator 1 "valid_dbcc_comparison_p"
5587 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5591 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5594 (define_insn "scc0_di_5200"
5595 [(set (match_operand:QI 0 "general_operand" "=d")
5596 (match_operator 1 "valid_dbcc_comparison_p"
5597 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5601 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5604 (define_insn "scc_di"
5605 [(set (match_operand:QI 0 "general_operand" "=dm,dm")
5606 (match_operator 1 "valid_dbcc_comparison_p"
5607 [(match_operand:DI 2 "general_operand" "ro,r")
5608 (match_operand:DI 3 "general_operand" "r,ro")]))]
5612 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5615 (define_insn "scc_di_5200"
5616 [(set (match_operand:QI 0 "general_operand" "=d,d")
5617 (match_operator 1 "valid_dbcc_comparison_p"
5618 [(match_operand:DI 2 "general_operand" "ro,r")
5619 (match_operand:DI 3 "general_operand" "r,ro")]))]
5623 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5626 (define_expand "seq"
5627 [(set (match_operand:QI 0 "general_operand" "")
5628 (eq:QI (cc0) (const_int 0)))]
5632 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5634 m68k_last_compare_had_fp_operands = 0;
5640 [(set (match_operand:QI 0 "general_operand" "=dm")
5641 (eq:QI (cc0) (const_int 0)))]
5644 cc_status = cc_prev_status;
5645 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5649 [(set (match_operand:QI 0 "general_operand" "=d")
5650 (eq:QI (cc0) (const_int 0)))]
5653 cc_status = cc_prev_status;
5654 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5657 (define_expand "sne"
5658 [(set (match_operand:QI 0 "general_operand" "")
5659 (ne:QI (cc0) (const_int 0)))]
5663 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5665 m68k_last_compare_had_fp_operands = 0;
5671 [(set (match_operand:QI 0 "general_operand" "=dm")
5672 (ne:QI (cc0) (const_int 0)))]
5675 cc_status = cc_prev_status;
5676 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5680 [(set (match_operand:QI 0 "general_operand" "=d")
5681 (ne:QI (cc0) (const_int 0)))]
5684 cc_status = cc_prev_status;
5685 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5688 (define_expand "sgt"
5689 [(set (match_operand:QI 0 "general_operand" "")
5690 (gt:QI (cc0) (const_int 0)))]
5694 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5696 m68k_last_compare_had_fp_operands = 0;
5702 [(set (match_operand:QI 0 "general_operand" "=dm")
5703 (gt:QI (cc0) (const_int 0)))]
5706 cc_status = cc_prev_status;
5707 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5711 [(set (match_operand:QI 0 "general_operand" "=d")
5712 (gt:QI (cc0) (const_int 0)))]
5715 cc_status = cc_prev_status;
5716 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5719 (define_expand "sgtu"
5720 [(set (match_operand:QI 0 "general_operand" "")
5721 (gtu:QI (cc0) (const_int 0)))]
5726 [(set (match_operand:QI 0 "general_operand" "=dm")
5727 (gtu:QI (cc0) (const_int 0)))]
5729 "* cc_status = cc_prev_status;
5730 return \"shi %0\"; ")
5733 [(set (match_operand:QI 0 "general_operand" "=d")
5734 (gtu:QI (cc0) (const_int 0)))]
5736 "* cc_status = cc_prev_status;
5737 return \"shi %0\"; ")
5739 (define_expand "slt"
5740 [(set (match_operand:QI 0 "general_operand" "")
5741 (lt:QI (cc0) (const_int 0)))]
5745 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5747 m68k_last_compare_had_fp_operands = 0;
5753 [(set (match_operand:QI 0 "general_operand" "=dm")
5754 (lt:QI (cc0) (const_int 0)))]
5756 "* cc_status = cc_prev_status;
5757 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5760 [(set (match_operand:QI 0 "general_operand" "=d")
5761 (lt:QI (cc0) (const_int 0)))]
5763 "* cc_status = cc_prev_status;
5764 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5766 (define_expand "sltu"
5767 [(set (match_operand:QI 0 "general_operand" "")
5768 (ltu:QI (cc0) (const_int 0)))]
5773 [(set (match_operand:QI 0 "general_operand" "=dm")
5774 (ltu:QI (cc0) (const_int 0)))]
5776 "* cc_status = cc_prev_status;
5777 return \"scs %0\"; ")
5780 [(set (match_operand:QI 0 "general_operand" "=d")
5781 (ltu:QI (cc0) (const_int 0)))]
5783 "* cc_status = cc_prev_status;
5784 return \"scs %0\"; ")
5786 (define_expand "sge"
5787 [(set (match_operand:QI 0 "general_operand" "")
5788 (ge:QI (cc0) (const_int 0)))]
5792 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5794 m68k_last_compare_had_fp_operands = 0;
5800 [(set (match_operand:QI 0 "general_operand" "=dm")
5801 (ge:QI (cc0) (const_int 0)))]
5803 "* cc_status = cc_prev_status;
5804 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5807 [(set (match_operand:QI 0 "general_operand" "=d")
5808 (ge:QI (cc0) (const_int 0)))]
5810 "* cc_status = cc_prev_status;
5811 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5813 (define_expand "sgeu"
5814 [(set (match_operand:QI 0 "general_operand" "")
5815 (geu:QI (cc0) (const_int 0)))]
5820 [(set (match_operand:QI 0 "general_operand" "=dm")
5821 (geu:QI (cc0) (const_int 0)))]
5823 "* cc_status = cc_prev_status;
5824 return \"scc %0\"; ")
5827 [(set (match_operand:QI 0 "general_operand" "=d")
5828 (geu:QI (cc0) (const_int 0)))]
5830 "* cc_status = cc_prev_status;
5831 return \"scc %0\"; ")
5833 (define_expand "sle"
5834 [(set (match_operand:QI 0 "general_operand" "")
5835 (le:QI (cc0) (const_int 0)))]
5839 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5841 m68k_last_compare_had_fp_operands = 0;
5847 [(set (match_operand:QI 0 "general_operand" "=dm")
5848 (le:QI (cc0) (const_int 0)))]
5851 cc_status = cc_prev_status;
5852 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5856 [(set (match_operand:QI 0 "general_operand" "=d")
5857 (le:QI (cc0) (const_int 0)))]
5860 cc_status = cc_prev_status;
5861 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5864 (define_expand "sleu"
5865 [(set (match_operand:QI 0 "general_operand" "")
5866 (leu:QI (cc0) (const_int 0)))]
5871 [(set (match_operand:QI 0 "general_operand" "=dm")
5872 (leu:QI (cc0) (const_int 0)))]
5874 "* cc_status = cc_prev_status;
5875 return \"sls %0\"; ")
5878 [(set (match_operand:QI 0 "general_operand" "=d")
5879 (leu:QI (cc0) (const_int 0)))]
5881 "* cc_status = cc_prev_status;
5882 return \"sls %0\"; ")
5884 ;; Basic conditional jump instructions.
5886 (define_insn "beq0_di"
5888 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5890 (label_ref (match_operand 1 "" ","))
5892 (clobber (match_scratch:SI 2 "=d,d"))]
5897 if (which_alternative == 1)
5899 return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
5901 return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
5903 if ((cc_prev_status.value1
5904 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5905 || (cc_prev_status.value2
5906 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5908 cc_status = cc_prev_status;
5910 return \"jbeq %l1\";
5915 if (GET_CODE (operands[0]) == REG)
5916 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
5918 operands[3] = adj_offsettable_operand (operands[0], 4);
5919 if (! ADDRESS_REG_P (operands[0]))
5922 return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
5924 return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
5927 operands[4] = gen_label_rtx();
5928 if (TARGET_68020 || TARGET_5200)
5931 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
5933 output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
5939 #ifdef SGS_CMP_ORDER
5940 output_asm_insn (\"cmp%.w %0,%#0\;jbne %l4\;cmp%.w %3,%#0\;jbeq %l1\", operands);
5942 output_asm_insn (\"cmp%.w %#0,%0\;jbne %l4\;cmp%.w %#0,%3\;jbeq %l1\", operands);
5945 output_asm_insn (\"cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1\", operands);
5948 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5949 CODE_LABEL_NUMBER (operands[4]));
5953 (define_insn "bne0_di"
5955 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5957 (label_ref (match_operand 1 "" ","))
5959 (clobber (match_scratch:SI 2 "=d,X"))]
5963 if ((cc_prev_status.value1
5964 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5965 || (cc_prev_status.value2
5966 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5968 cc_status = cc_prev_status;
5970 return \"jbne %l1\";
5976 if (GET_CODE (operands[0]) == REG)
5977 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
5979 operands[3] = adj_offsettable_operand (operands[0], 4);
5980 if (!ADDRESS_REG_P (operands[0]))
5983 return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
5985 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
5988 if (TARGET_68020 || TARGET_5200)
5991 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
5993 return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
5999 #ifdef SGS_CMP_ORDER
6000 return \"cmp%.w %0,%#0\;jbne %l1\;cmp%.w %3,%#0\;jbne %l1\";
6002 return \"cmp%.w %#0,%0\;jbne %l1\;cmp%.w %#0,%3\;jbne %l1\";
6005 return \"cmp%.w %#0,%0\;jne %l1\;cmp%.w %#0,%3\;jne %l1\";
6010 (define_insn "bge0_di"
6012 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
6014 (label_ref (match_operand 1 "" ""))
6019 if ((cc_prev_status.value1
6020 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6021 || (cc_prev_status.value2
6022 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6024 cc_status = cc_prev_status;
6025 if (cc_status.flags & CC_REVERSED)
6028 return \"jble %l1\";
6036 return \"jbpl %l1\";
6043 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
6044 output_asm_insn(\"tst%.l %0\", operands);
6047 /* On an address reg, cmpw may replace cmpl. */
6048 #ifdef SGS_CMP_ORDER
6049 output_asm_insn(\"cmp%.w %0,%#0\", operands);
6051 output_asm_insn(\"cmp%.w %#0,%0\", operands);
6056 return \"jbpl %l1\";
6062 (define_insn "blt0_di"
6064 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
6066 (label_ref (match_operand 1 "" ""))
6071 if ((cc_prev_status.value1
6072 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6073 || (cc_prev_status.value2
6074 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6076 cc_status = cc_prev_status;
6077 if (cc_status.flags & CC_REVERSED)
6080 return \"jbgt %l1\";
6088 return \"jbmi %l1\";
6095 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
6096 output_asm_insn(\"tst%.l %0\", operands);
6099 /* On an address reg, cmpw may replace cmpl. */
6100 #ifdef SGS_CMP_ORDER
6101 output_asm_insn(\"cmp%.w %0,%#0\", operands);
6103 output_asm_insn(\"cmp%.w %#0,%0\", operands);
6108 return \"jbmi %l1\";
6116 (if_then_else (eq (cc0)
6118 (label_ref (match_operand 0 "" ""))
6124 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6126 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6132 (if_then_else (ne (cc0)
6134 (label_ref (match_operand 0 "" ""))
6140 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6142 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6148 (if_then_else (gt (cc0)
6150 (label_ref (match_operand 0 "" ""))
6155 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
6157 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
6163 (if_then_else (gtu (cc0)
6165 (label_ref (match_operand 0 "" ""))
6170 return \"jbhi %l0\";
6178 (if_then_else (lt (cc0)
6180 (label_ref (match_operand 0 "" ""))
6185 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
6187 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
6193 (if_then_else (ltu (cc0)
6195 (label_ref (match_operand 0 "" ""))
6200 return \"jbcs %l0\";
6208 (if_then_else (ge (cc0)
6210 (label_ref (match_operand 0 "" ""))
6215 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
6217 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
6223 (if_then_else (geu (cc0)
6225 (label_ref (match_operand 0 "" ""))
6230 return \"jbcc %l0\";
6238 (if_then_else (le (cc0)
6240 (label_ref (match_operand 0 "" ""))
6245 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
6247 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
6253 (if_then_else (leu (cc0)
6255 (label_ref (match_operand 0 "" ""))
6260 return \"jbls %l0\";
6266 ;; Negated conditional jump instructions.
6270 (if_then_else (eq (cc0)
6273 (label_ref (match_operand 0 "" ""))))]
6278 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6280 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6286 (if_then_else (ne (cc0)
6289 (label_ref (match_operand 0 "" ""))))]
6294 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6296 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6302 (if_then_else (gt (cc0)
6305 (label_ref (match_operand 0 "" ""))))]
6309 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
6311 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
6317 (if_then_else (gtu (cc0)
6320 (label_ref (match_operand 0 "" ""))))]
6324 return \"jbls %l0\";
6332 (if_then_else (lt (cc0)
6335 (label_ref (match_operand 0 "" ""))))]
6339 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
6341 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
6347 (if_then_else (ltu (cc0)
6350 (label_ref (match_operand 0 "" ""))))]
6354 return \"jbcc %l0\";
6362 (if_then_else (ge (cc0)
6365 (label_ref (match_operand 0 "" ""))))]
6369 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
6371 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
6377 (if_then_else (geu (cc0)
6380 (label_ref (match_operand 0 "" ""))))]
6384 return \"jbcs %l0\";
6392 (if_then_else (le (cc0)
6395 (label_ref (match_operand 0 "" ""))))]
6399 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
6401 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
6407 (if_then_else (leu (cc0)
6410 (label_ref (match_operand 0 "" ""))))]
6414 return \"jbhi %l0\";
6420 ;; Unconditional and other jump instructions
6423 (label_ref (match_operand 0 "" "")))]
6427 return \"jbra %l0\";
6433 ;; We support two different ways of handling dispatch tables.
6434 ;; The NeXT uses absolute tables, and other machines use relative.
6435 ;; This define_expand can generate either kind.
6436 (define_expand "tablejump"
6437 [(parallel [(set (pc) (match_operand 0 "" ""))
6438 (use (label_ref (match_operand 1 "" "")))])]
6442 #ifdef CASE_VECTOR_PC_RELATIVE
6443 operands[0] = gen_rtx (PLUS, SImode, pc_rtx,
6444 gen_rtx (SIGN_EXTEND, SImode, operands[0]));
6448 ;; Jump to variable address from dispatch table of absolute addresses.
6450 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6451 (use (label_ref (match_operand 1 "" "")))]
6455 return \"jmp (%0)\";
6461 ;; Jump to variable address from dispatch table of relative addresses.
6465 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6466 (use (label_ref (match_operand 1 "" "")))]
6469 #ifdef ASM_RETURN_CASE_JUMP
6470 ASM_RETURN_CASE_JUMP;
6473 #ifdef ASM_OUTPUT_CASE_LABEL
6475 return \"ext%.l %0\;jmp 6(%%pc,%0.l)\";
6477 return \"jmp 6(%%pc,%0.w)\";
6482 return \"ext%.l %0\;jmp 2(pc,%0.l)\";
6484 return \"extl %0\;jmp 2(%%pc,%0.l)\";
6485 #endif /* end !CRDS */
6490 return \"jmp 2(pc,%0.w)\";
6492 return \"jmp 2(%%pc,%0.w)\";
6493 #endif /* end !CRDS */
6500 return \"ext%.l %0\;jmp (2,pc,%0.l)\";
6502 return \"extl %0\;jmp pc@(2,%0:l)\";
6508 return \"jmp (2,pc,%0.w)\";
6510 return \"jmp pc@(2,%0:w)\";
6517 ;; Decrement-and-branch insns.
6521 (ne (match_operand:HI 0 "general_operand" "+d*g")
6523 (label_ref (match_operand 1 "" ""))
6526 (plus:HI (match_dup 0)
6532 if (DATA_REG_P (operands[0]))
6533 return \"dbra %0,%l1\";
6534 if (GET_CODE (operands[0]) == MEM)
6538 return \"sub%.w %#1,%0\;jbcc %l1\";
6540 return \"subq%.w %#1,%0\;jbcc %l1\";
6542 #else /* not MOTOROLA */
6543 return \"subqw %#1,%0\;jcc %l1\";
6547 #ifdef SGS_CMP_ORDER
6549 return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6551 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6553 #else /* not SGS_CMP_ORDER */
6554 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
6556 #else /* not MOTOROLA */
6557 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6564 (ne (match_operand:SI 0 "general_operand" "+d*g")
6566 (label_ref (match_operand 1 "" ""))
6569 (plus:SI (match_dup 0)
6577 if (DATA_REG_P (operands[0]))
6578 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6579 if (GET_CODE (operands[0]) == MEM)
6580 return \"sub%.l %#1,%0\;jbcc %l1\";
6582 if (DATA_REG_P (operands[0]))
6583 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6584 if (GET_CODE (operands[0]) == MEM)
6585 return \"subq%.l %#1,%0\;jbcc %l1\";
6586 #endif /* NO_ADDSUB_Q */
6587 #ifdef SGS_CMP_ORDER
6589 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6591 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6593 #else /* not SGS_CMP_ORDER */
6594 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6595 #endif /* not SGS_CMP_ORDER */
6596 #else /* not MOTOROLA */
6597 if (DATA_REG_P (operands[0]))
6598 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6599 if (GET_CODE (operands[0]) == MEM)
6600 return \"subql %#1,%0\;jcc %l1\";
6601 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6602 #endif /* not MOTOROLA */
6605 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6610 (ge (plus:HI (match_operand:HI 0 "general_operand" "+d*am")
6613 (label_ref (match_operand 1 "" ""))
6616 (plus:HI (match_dup 0)
6618 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6624 if (DATA_REG_P (operands[0]))
6625 return \"dbra %0,%l1\";
6626 if (GET_CODE (operands[0]) == MEM)
6627 return \"sub%.w %#1,%0\;jbcc %l1\";
6629 if (DATA_REG_P (operands[0]))
6630 return \"dbra %0,%l1\";
6631 if (GET_CODE (operands[0]) == MEM)
6632 return \"subq%.w %#1,%0\;jbcc %l1\";
6634 #ifdef SGS_CMP_ORDER
6636 return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6638 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6640 #else /* not SGS_CMP_ORDER */
6641 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
6642 #endif /* not SGS_CMP_ORDER */
6643 #else /* not MOTOROLA */
6644 if (DATA_REG_P (operands[0]))
6645 return \"dbra %0,%l1\";
6646 if (GET_CODE (operands[0]) == MEM)
6647 return \"subqw %#1,%0\;jcc %l1\";
6648 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6649 #endif /* not MOTOROLA */
6652 (define_expand "decrement_and_branch_until_zero"
6653 [(parallel [(set (pc)
6655 (ge (plus:SI (match_operand:SI 0 "general_operand" "")
6658 (label_ref (match_operand 1 "" ""))
6661 (plus:SI (match_dup 0)
6669 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6672 (label_ref (match_operand 1 "" ""))
6675 (plus:SI (match_dup 0)
6677 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6683 if (DATA_REG_P (operands[0]))
6684 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6685 if (GET_CODE (operands[0]) == MEM)
6686 return \"sub%.l %#1,%0\;jbcc %l1\";
6688 if (DATA_REG_P (operands[0]))
6689 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6690 if (GET_CODE (operands[0]) == MEM)
6691 return \"subq%.l %#1,%0\;jbcc %l1\";
6693 #ifdef SGS_CMP_ORDER
6695 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6697 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6699 #else /* not SGS_CMP_ORDER */
6700 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6701 #endif /* not SGS_CMP_ORDER */
6702 #else /* not MOTOROLA */
6703 if (DATA_REG_P (operands[0]))
6704 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6705 if (GET_CODE (operands[0]) == MEM)
6706 return \"subql %#1,%0\;jcc %l1\";
6707 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6708 #endif /* not MOTOROLA */
6712 ;; For PIC calls, in order to be able to support
6713 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
6714 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
6716 ;; PIC calls are handled by loading the address of the function into a
6717 ;; register (via movsi), then emitting a register indirect call using
6718 ;; the "jsr" function call syntax.
6720 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
6721 ;; operand to the jbsr statement to indicate that this call should
6722 ;; go through the PLT (why? because this is the way that Sun does it).
6724 ;; We have different patterns for PIC calls and non-PIC calls. The
6725 ;; different patterns are only used to choose the right syntax.
6727 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
6728 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
6729 ;; that tells the linker editor to create an entry for `FUNC' in PLT
6730 ;; section at link time. However, all global objects reference are still
6731 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
6732 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
6733 ;; We need to have a way to differentiate these two different operands.
6735 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
6736 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
6737 ;; to be changed to recognize function calls symbol_ref operand as a valid
6738 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
6739 ;; avoid the compiler to load this symbol_ref operand into a register.
6740 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
6741 ;; since the value is a PC relative offset, not a real address.
6743 ;; All global objects are treated in the similar way as in SUN3. The only
6744 ;; difference is: on m68k svr4, the reference of such global object needs
6745 ;; to end with a suffix "@GOT" so the assembler and linker know to create
6746 ;; an entry for it in GOT (Global Offset Table) section. This is done in
6749 ;; Call subroutine with no return value.
6750 (define_expand "call"
6751 [(call (match_operand:QI 0 "memory_operand" "")
6752 (match_operand:SI 1 "general_operand" ""))]
6753 ;; Operand 1 not really used on the m68000.
6758 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6759 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
6762 ;; This is a normal call sequence.
6764 [(call (match_operand:QI 0 "memory_operand" "o")
6765 (match_operand:SI 1 "general_operand" "g"))]
6766 ;; Operand 1 not really used on the m68000.
6770 #if defined (MOTOROLA) && !defined (USE_GAS)
6772 if (GET_CODE (operands[0]) == MEM
6773 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6782 ;; This is a PIC call sequence.
6784 [(call (match_operand:QI 0 "memory_operand" "o")
6785 (match_operand:SI 1 "general_operand" "g"))]
6786 ;; Operand 1 not really used on the m68000.
6790 if (GET_CODE (operands[0]) == MEM
6791 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6794 return \"bsr.l %0\";
6797 return \"bsr.l %0@PLTPC\";
6799 return \"bsr %0@PLTPC\";
6803 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
6804 GAS just plain ignores it. */
6805 return \"jbsr %0,a1\";
6810 ;; Call subroutine, returning value in operand 0
6811 ;; (which must be a hard register).
6812 ;; See comments before "call" regarding PIC calls.
6813 (define_expand "call_value"
6814 [(set (match_operand 0 "" "")
6815 (call (match_operand:QI 1 "memory_operand" "")
6816 (match_operand:SI 2 "general_operand" "")))]
6817 ;; Operand 2 not really used on the m68000.
6821 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6822 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6825 ;; This is a normal call_value
6827 [(set (match_operand 0 "" "=rf")
6828 (call (match_operand:QI 1 "memory_operand" "o")
6829 (match_operand:SI 2 "general_operand" "g")))]
6830 ;; Operand 2 not really used on the m68000.
6833 #if defined (MOTOROLA) && !defined (USE_GAS)
6835 if (GET_CODE (operands[1]) == MEM
6836 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6845 ;; This is a PIC call_value
6847 [(set (match_operand 0 "" "=rf")
6848 (call (match_operand:QI 1 "memory_operand" "o")
6849 (match_operand:SI 2 "general_operand" "g")))]
6850 ;; Operand 2 not really used on the m68000.
6853 if (GET_CODE (operands[1]) == MEM
6854 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6858 return \"bsr.l %1\";
6861 return \"bsr.l %1@PLTPC\";
6863 return \"bsr %1@PLTPC\";
6867 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
6868 GAS just plain ignores it. */
6869 return \"jbsr %1,a1\";
6875 ;; Call subroutine returning any type.
6877 (define_expand "untyped_call"
6878 [(parallel [(call (match_operand 0 "" "")
6880 (match_operand 1 "" "")
6881 (match_operand 2 "" "")])]
6882 "NEEDS_UNTYPED_CALL"
6887 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
6889 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6891 rtx set = XVECEXP (operands[2], 0, i);
6892 emit_move_insn (SET_DEST (set), SET_SRC (set));
6895 /* The optimizer does not know that the call sets the function value
6896 registers we stored in the result block. We avoid problems by
6897 claiming that all hard registers are used and clobbered at this
6899 emit_insn (gen_blockage ());
6904 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6905 ;; all of memory. This blocks insns from being moved across this point.
6907 (define_insn "blockage"
6908 [(unspec_volatile [(const_int 0)] 0)]
6917 (define_insn "probe"
6922 operands[0] = gen_rtx (PLUS, SImode, stack_pointer_rtx,
6923 gen_rtx (CONST_INT, VOIDmode, NEED_PROBE));
6924 return \"tstl %a0\";
6927 ;; Used for frameless functions which save no regs and allocate no locals.
6928 (define_insn "return"
6933 if (current_function_pops_args == 0)
6935 operands[0] = gen_rtx (CONST_INT, VOIDmode, current_function_pops_args);
6939 (define_insn "indirect_jump"
6940 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6944 ;; This should not be used unless the add/sub insns can't be.
6947 [(set (match_operand:SI 0 "general_operand" "=a")
6948 (match_operand:QI 1 "address_operand" "p"))]
6953 /* Recognize an insn that refers to a table of offsets. Such an insn will
6954 need to refer to a label on the insn. So output one. Use the
6955 label-number of the table of offsets to generate this label. This code,
6956 and similar code above, assumes that there will be at most one reference
6958 if (GET_CODE (operands[1]) == PLUS
6959 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
6960 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
6962 rtx labelref = XEXP (operands[1], 1);
6963 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
6965 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
6966 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6968 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
6969 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6970 #endif /* not SGS */
6971 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
6972 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
6973 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6974 #ifdef SGS_SWITCH_TABLES
6975 /* Set flag saying we need to define the symbol
6976 LD%n (with value L%n-LI%n) at the end of the switch table. */
6977 switch_table_difference_label_flag = 1;
6978 #endif /* SGS_SWITCH_TABLES */
6979 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
6981 #endif /* SGS_NO_LI */
6983 return \"lea %a1,%0\";
6986 ;; This is the first machine-dependent peephole optimization.
6987 ;; It is useful when a floating value is returned from a function call
6988 ;; and then is moved into an FP register.
6989 ;; But it is mainly intended to test the support for these optimizations.
6992 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
6993 (set (match_operand:DF 0 "register_operand" "=f")
6994 (match_operand:DF 1 "register_operand" "ad"))]
6995 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
6999 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
7000 output_asm_insn (\"move%.l %1,%@\", xoperands);
7001 output_asm_insn (\"move%.l %1,%-\", operands);
7002 return \"fmove%.d %+,%0\";
7006 ;; Optimize a stack-adjust followed by a push of an argument.
7007 ;; This is said to happen frequently with -msoft-float
7008 ;; when there are consecutive library calls.
7011 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7012 (match_operand:SI 0 "const_int_operand" "n")))
7013 (set (match_operand:SF 1 "push_operand" "=m")
7014 (match_operand:SF 2 "general_operand" "rmfF"))]
7015 "INTVAL (operands[0]) >= 4
7016 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7019 if (INTVAL (operands[0]) > 4)
7022 xoperands[0] = stack_pointer_rtx;
7023 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
7025 if (INTVAL (xoperands[1]) <= 8)
7028 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7030 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7032 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7034 xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
7035 INTVAL (xoperands[1]) - 8);
7036 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7040 if (INTVAL (xoperands[1]) <= 0x7FFF)
7043 output_asm_insn (\"add%.w %1,%0\", xoperands);
7046 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7048 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7052 output_asm_insn (\"add%.l %1,%0\", xoperands);
7054 if (FP_REG_P (operands[2]))
7055 return \"fmove%.s %2,%@\";
7056 return \"move%.l %2,%@\";
7059 ;; Speed up stack adjust followed by a fullword fixedpoint push.
7062 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7063 (match_operand:SI 0 "const_int_operand" "n")))
7064 (set (match_operand:SI 1 "push_operand" "=m")
7065 (match_operand:SI 2 "general_operand" "g"))]
7066 "INTVAL (operands[0]) >= 4
7067 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7070 if (INTVAL (operands[0]) > 4)
7073 xoperands[0] = stack_pointer_rtx;
7074 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
7076 if (INTVAL (xoperands[1]) <= 8)
7079 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7081 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7083 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7085 xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
7086 INTVAL (xoperands[1]) - 8);
7087 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7091 if (INTVAL (xoperands[1]) <= 0x7FFF)
7094 output_asm_insn (\"add%.w %1,%0\", xoperands);
7098 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7100 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7105 output_asm_insn (\"add%.l %1,%0\", xoperands);
7107 if (operands[2] == const0_rtx)
7108 return \"clr%.l %@\";
7109 return \"move%.l %2,%@\";
7112 ;; Speed up pushing a single byte but leaving four bytes of space.
7115 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
7116 (match_operand:QI 1 "general_operand" "dami"))
7117 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
7118 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
7123 if (GET_CODE (operands[1]) == REG)
7124 return \"move%.l %1,%-\";
7126 xoperands[1] = operands[1];
7128 = gen_rtx (MEM, QImode,
7129 gen_rtx (PLUS, VOIDmode, stack_pointer_rtx,
7130 gen_rtx (CONST_INT, VOIDmode, 3)));
7131 xoperands[3] = stack_pointer_rtx;
7133 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
7135 output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
7140 [(set (match_operand:SI 0 "register_operand" "=d")
7142 (set (strict_low_part (subreg:HI (match_dup 0) 0))
7143 (match_operand:HI 1 "general_operand" "rmn"))]
7144 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
7147 if (GET_CODE (operands[1]) == CONST_INT)
7149 if (operands[1] == const0_rtx
7150 && (DATA_REG_P (operands[0])
7151 || GET_CODE (operands[0]) == MEM)
7152 /* clr insns on 68000 read before writing.
7153 This isn't so on the 68010, but we have no TARGET_68010. */
7154 && ((TARGET_68020 || TARGET_5200)
7155 || !(GET_CODE (operands[0]) == MEM
7156 && MEM_VOLATILE_P (operands[0]))))
7157 return \"clr%.w %0\";
7159 return \"move%.w %1,%0\";
7167 ;; jCC label ; abnormal loop termination
7168 ;; dbra dN, loop ; normal loop termination
7176 ;; Which moves the jCC condition outside the inner loop for free.
7179 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7180 [(cc0) (const_int 0)])
7181 (label_ref (match_operand 2 "" ""))
7186 (ge (plus:HI (match_operand:HI 0 "register_operand" "+d")
7189 (label_ref (match_operand 1 "" ""))
7192 (plus:HI (match_dup 0)
7194 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7198 output_dbcc_and_branch (operands);
7203 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7204 [(cc0) (const_int 0)])
7205 (label_ref (match_operand 2 "" ""))
7210 (ge (plus:SI (match_operand:SI 0 "register_operand" "+d")
7213 (label_ref (match_operand 1 "" ""))
7216 (plus:SI (match_dup 0)
7218 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7222 output_dbcc_and_branch (operands);
7227 ;; FPA multiply and add.
7229 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7230 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
7231 (match_operand:DF 2 "general_operand" "xH,y,y"))
7232 (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
7235 fpma%.d %1,%w2,%w3,%0
7236 fpma%.d %x1,%x2,%x3,%0
7237 fpma%.d %x1,%x2,%x3,%0")
7240 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7241 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
7242 (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
7243 (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
7246 fpma%.s %1,%w2,%w3,%0
7248 fpma%.s %1,%2,%3,%0")
7250 ;; FPA Multiply and subtract
7252 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7253 (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7254 (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y")
7255 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7258 fpms%.d %3,%w2,%w1,%0
7259 fpms%.d %x3,%2,%x1,%0
7260 fpms%.d %x3,%2,%x1,%0")
7263 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7264 (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7265 (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y")
7266 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7269 fpms%.s %3,%w2,%w1,%0
7271 fpms%.s %3,%2,%1,%0")
7274 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7275 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7276 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7277 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7280 fpmr%.d %2,%w1,%w3,%0
7281 fpmr%.d %x2,%1,%x3,%0
7282 fpmr%.d %x2,%1,%x3,%0")
7285 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7286 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7287 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7288 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7291 fpmr%.s %2,%w1,%w3,%0
7292 fpmr%.s %x2,%1,%x3,%0
7293 fpmr%.s %x2,%1,%x3,%0")
7295 ;; FPA Add and multiply
7297 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7298 (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7299 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7300 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7303 fpam%.d %2,%w1,%w3,%0
7304 fpam%.d %x2,%1,%x3,%0
7305 fpam%.d %x2,%1,%x3,%0")
7308 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7309 (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7310 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7311 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7314 fpam%.s %2,%w1,%w3,%0
7315 fpam%.s %x2,%1,%x3,%0
7316 fpam%.s %x2,%1,%x3,%0")
7318 ;;FPA Subtract and multiply
7320 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7321 (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y")
7322 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7323 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7326 fpsm%.d %2,%w1,%w3,%0
7327 fpsm%.d %x2,%1,%x3,%0
7328 fpsm%.d %x2,%1,%x3,%0")
7331 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7332 (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7333 (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y")
7334 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7337 fpsm%.d %3,%w2,%w1,%0
7338 fpsm%.d %x3,%2,%x1,%0
7339 fpsm%.d %x3,%2,%x1,%0")
7342 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7343 (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y")
7344 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7345 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7348 fpsm%.s %2,%w1,%w3,%0
7349 fpsm%.s %x2,%1,%x3,%0
7350 fpsm%.s %x2,%1,%x3,%0")
7353 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7354 (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7355 (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y")
7356 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7359 fpsm%.s %3,%w2,%w1,%0
7360 fpsm%.s %x3,%2,%x1,%0
7361 fpsm%.s %x3,%2,%x1,%0")
7363 (define_expand "tstxf"
7365 (match_operand:XF 0 "nonimmediate_operand" ""))]
7367 "m68k_last_compare_had_fp_operands = 1;")
7371 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
7375 cc_status.flags = CC_IN_68881;
7376 return \"ftst%.x %0\";
7379 (define_expand "cmpxf"
7381 (compare (match_operand:XF 0 "nonimmediate_operand" "")
7382 (match_operand:XF 1 "nonimmediate_operand" "")))]
7384 "m68k_last_compare_had_fp_operands = 1;")
7388 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
7389 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
7393 cc_status.flags = CC_IN_68881;
7394 #ifdef SGS_CMP_ORDER
7395 if (REG_P (operands[0]))
7397 if (REG_P (operands[1]))
7398 return \"fcmp%.x %0,%1\";
7400 return \"fcmp%.x %0,%f1\";
7402 cc_status.flags |= CC_REVERSED;
7403 return \"fcmp%.x %1,%f0\";
7405 if (REG_P (operands[0]))
7407 if (REG_P (operands[1]))
7408 return \"fcmp%.x %1,%0\";
7410 return \"fcmp%.x %f1,%0\";
7412 cc_status.flags |= CC_REVERSED;
7413 return \"fcmp%.x %f0,%1\";
7417 (define_insn "extendsfxf2"
7418 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7419 (float_extend:XF (match_operand:SF 1 "general_operand" "f,m")))]
7423 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7425 if (REGNO (operands[0]) == REGNO (operands[1]))
7427 /* Extending float to double in an fp-reg is a no-op.
7428 NOTICE_UPDATE_CC has already assumed that the
7429 cc will be set. So cancel what it did. */
7430 cc_status = cc_prev_status;
7433 return \"f%$move%.x %1,%0\";
7435 if (FP_REG_P (operands[0]))
7436 return \"f%$move%.s %f1,%0\";
7437 return \"fmove%.x %f1,%0\";
7441 (define_insn "extenddfxf2"
7442 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7444 (match_operand:DF 1 "general_operand" "f,m")))]
7448 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7450 if (REGNO (operands[0]) == REGNO (operands[1]))
7452 /* Extending float to double in an fp-reg is a no-op.
7453 NOTICE_UPDATE_CC has already assumed that the
7454 cc will be set. So cancel what it did. */
7455 cc_status = cc_prev_status;
7458 return \"fmove%.x %1,%0\";
7460 if (FP_REG_P (operands[0]))
7461 return \"f%&move%.d %f1,%0\";
7462 return \"fmove%.x %f1,%0\";
7465 (define_insn "truncxfdf2"
7466 [(set (match_operand:DF 0 "general_operand" "=m,!r")
7468 (match_operand:XF 1 "general_operand" "f,f")))]
7472 if (REG_P (operands[0]))
7474 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
7475 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
7476 return \"move%.l %+,%0\";
7478 return \"fmove%.d %f1,%0\";
7481 (define_insn "truncxfsf2"
7482 [(set (match_operand:SF 0 "general_operand" "=dm")
7484 (match_operand:XF 1 "general_operand" "f")))]
7488 (define_insn "floatsixf2"
7489 [(set (match_operand:XF 0 "general_operand" "=f")
7490 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
7494 (define_insn "floathixf2"
7495 [(set (match_operand:XF 0 "general_operand" "=f")
7496 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
7500 (define_insn "floatqixf2"
7501 [(set (match_operand:XF 0 "general_operand" "=f")
7502 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
7506 (define_insn "ftruncxf2"
7507 [(set (match_operand:XF 0 "general_operand" "=f")
7508 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
7512 if (FP_REG_P (operands[1]))
7513 return \"fintrz%.x %f1,%0\";
7514 return \"fintrz%.x %f1,%0\";
7517 (define_insn "fixxfqi2"
7518 [(set (match_operand:QI 0 "general_operand" "=dm")
7519 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
7523 (define_insn "fixxfhi2"
7524 [(set (match_operand:HI 0 "general_operand" "=dm")
7525 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
7529 (define_insn "fixxfsi2"
7530 [(set (match_operand:SI 0 "general_operand" "=dm")
7531 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
7536 [(set (match_operand:XF 0 "general_operand" "=f")
7537 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7538 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7543 [(set (match_operand:XF 0 "general_operand" "=f")
7544 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7545 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7550 [(set (match_operand:XF 0 "general_operand" "=f")
7551 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7552 (match_operand:XF 1 "general_operand" "0")))]
7556 (define_insn "addxf3"
7557 [(set (match_operand:XF 0 "general_operand" "=f")
7558 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7559 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7563 if (REG_P (operands[2]))
7564 return \"fadd%.x %2,%0\";
7565 return \"fadd%.x %f2,%0\";
7569 [(set (match_operand:XF 0 "general_operand" "=f")
7570 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7571 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7576 [(set (match_operand:XF 0 "general_operand" "=f")
7577 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7578 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7583 [(set (match_operand:XF 0 "general_operand" "=f")
7584 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7585 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7589 (define_insn "subxf3"
7590 [(set (match_operand:XF 0 "general_operand" "=f")
7591 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7592 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7596 if (REG_P (operands[2]))
7597 return \"fsub%.x %2,%0\";
7598 return \"fsub%.x %f2,%0\";
7602 [(set (match_operand:XF 0 "general_operand" "=f")
7603 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7604 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7609 [(set (match_operand:XF 0 "general_operand" "=f")
7610 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7611 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7616 [(set (match_operand:XF 0 "general_operand" "=f")
7617 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7618 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7622 (define_insn "mulxf3"
7623 [(set (match_operand:XF 0 "general_operand" "=f")
7624 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7625 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7629 if (REG_P (operands[2]))
7630 return \"fmul%.x %2,%0\";
7631 return \"fmul%.x %f2,%0\";
7635 [(set (match_operand:XF 0 "general_operand" "=f")
7636 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7637 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7642 [(set (match_operand:XF 0 "general_operand" "=f")
7643 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7644 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7649 [(set (match_operand:XF 0 "general_operand" "=f")
7650 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7651 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7655 (define_insn "divxf3"
7656 [(set (match_operand:XF 0 "general_operand" "=f")
7657 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7658 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7662 if (REG_P (operands[2]))
7663 return \"fdiv%.x %2,%0\";
7664 return \"fdiv%.x %f2,%0\";
7667 (define_expand "negxf2"
7668 [(set (match_operand:XF 0 "general_operand" "")
7669 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7673 /* ??? There isn't an FPA define_insn so we could handle it here too.
7674 For now we don't (paranoia). */
7682 target = operand_subword (operands[0], 0, 1, XFmode);
7683 result = expand_binop (SImode, xor_optab,
7684 operand_subword_force (operands[1], 0, XFmode),
7685 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
7689 if (result != target)
7690 emit_move_insn (result, target);
7692 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7693 operand_subword_force (operands[1], 1, XFmode));
7694 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7695 operand_subword_force (operands[1], 2, XFmode));
7697 insns = get_insns ();
7700 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7705 (define_insn "negxf2_68881"
7706 [(set (match_operand:XF 0 "general_operand" "=f")
7707 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7711 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7712 return \"fneg%.x %1,%0\";
7713 return \"fneg%.x %f1,%0\";
7716 (define_expand "absxf2"
7717 [(set (match_operand:XF 0 "general_operand" "")
7718 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7722 /* ??? There isn't an FPA define_insn so we could handle it here too.
7723 For now we don't (paranoia). */
7731 target = operand_subword (operands[0], 0, 1, XFmode);
7732 result = expand_binop (SImode, and_optab,
7733 operand_subword_force (operands[1], 0, XFmode),
7734 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
7738 if (result != target)
7739 emit_move_insn (result, target);
7741 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7742 operand_subword_force (operands[1], 1, XFmode));
7743 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7744 operand_subword_force (operands[1], 2, XFmode));
7746 insns = get_insns ();
7749 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7754 (define_insn "absxf2_68881"
7755 [(set (match_operand:XF 0 "general_operand" "=f")
7756 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7760 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7761 return \"fabs%.x %1,%0\";
7762 return \"fabs%.x %f1,%0\";
7765 (define_insn "sqrtxf2"
7766 [(set (match_operand:XF 0 "general_operand" "=f")
7767 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7771 (define_insn "sinsf2"
7772 [(set (match_operand:SF 0 "general_operand" "=f")
7773 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 1))]
7774 "TARGET_68881 && flag_fast_math"
7777 if (FP_REG_P (operands[1]))
7778 return \"fsin%.x %1,%0\";
7780 return \"fsin%.s %1,%0\";
7783 (define_insn "sindf2"
7784 [(set (match_operand:DF 0 "general_operand" "=f")
7785 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 1))]
7786 "TARGET_68881 && flag_fast_math"
7789 if (FP_REG_P (operands[1]))
7790 return \"fsin%.x %1,%0\";
7792 return \"fsin%.d %1,%0\";
7795 (define_insn "sinxf2"
7796 [(set (match_operand:XF 0 "general_operand" "=f")
7797 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 1))]
7798 "TARGET_68881 && flag_fast_math"
7801 (define_insn "cossf2"
7802 [(set (match_operand:SF 0 "general_operand" "=f")
7803 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 2))]
7804 "TARGET_68881 && flag_fast_math"
7807 if (FP_REG_P (operands[1]))
7808 return \"fcos%.x %1,%0\";
7810 return \"fcos%.s %1,%0\";
7813 (define_insn "cosdf2"
7814 [(set (match_operand:DF 0 "general_operand" "=f")
7815 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 2))]
7816 "TARGET_68881 && flag_fast_math"
7819 if (FP_REG_P (operands[1]))
7820 return \"fcos%.x %1,%0\";
7822 return \"fcos%.d %1,%0\";
7825 (define_insn "cosxf2"
7826 [(set (match_operand:XF 0 "general_operand" "=f")
7827 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 2))]
7828 "TARGET_68881 && flag_fast_math"