1 ;; Constraint definitions for MIPS.
2 ;; Copyright (C) 2006-2014 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Register constraints
22 (define_register_constraint "d" "BASE_REG_CLASS"
23 "An address register. This is equivalent to @code{r} unless
24 generating MIPS16 code.")
26 (define_register_constraint "t" "T_REG"
29 (define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
30 "A floating-point register (if available).")
32 (define_register_constraint "h" "NO_REGS"
33 "Formerly the @code{hi} register. This constraint is no longer supported.")
35 (define_register_constraint "l" "TARGET_BIG_ENDIAN ? MD1_REG : MD0_REG"
36 "The @code{lo} register. Use this register to store values that are
37 no bigger than a word.")
39 (define_register_constraint "x" "MD_REGS"
40 "The concatenated @code{hi} and @code{lo} registers. Use this register
41 to store doubleword values.")
43 (define_register_constraint "b" "ALL_REGS"
46 (define_register_constraint "u" "M16_REGS"
49 ;; MIPS16 code always calls through a MIPS16 register; see mips_emit_call_insn
51 (define_register_constraint "c" "TARGET_MIPS16 ? M16_REGS
52 : TARGET_USE_PIC_FN_ADDR_REG ? PIC_FN_ADDR_REG
54 "A register suitable for use in an indirect jump. This will always be
55 @code{$25} for @option{-mabicalls}.")
57 (define_register_constraint "e" "LEA_REGS"
60 (define_register_constraint "j" "PIC_FN_ADDR_REG"
63 ;; Don't use this constraint in gcc code! It runs the risk of
64 ;; introducing a spill failure; see tls_get_tp_<mode>.
65 (define_register_constraint "v" "V1_REG"
66 "Register @code{$3}. Do not use this constraint in new code;
67 it is retained only for compatibility with glibc.")
69 (define_register_constraint "y" "GR_REGS"
70 "Equivalent to @code{r}; retained for backwards compatibility.")
72 (define_register_constraint "z" "ST_REGS"
73 "A floating-point condition code register.")
75 (define_register_constraint "A" "DSP_ACC_REGS"
78 (define_register_constraint "a" "ACC_REGS"
81 (define_register_constraint "B" "COP0_REGS"
84 (define_register_constraint "C" "COP2_REGS"
87 (define_register_constraint "D" "COP3_REGS"
90 ;; Registers that can be used as the target of multiply-accumulate
91 ;; instructions. The core MIPS32 ISA provides a hi/lo madd,
92 ;; but the DSP version allows any accumulator target.
93 (define_register_constraint "ka" "ISA_HAS_DSP_MULT ? ACC_REGS : MD_REGS")
95 (define_constraint "kf"
97 (match_operand 0 "force_to_mem_operand"))
99 ;; This is a normal rather than a register constraint because we can
100 ;; never use the stack pointer as a reload register.
101 (define_constraint "ks"
103 (and (match_code "reg")
104 (match_test "REGNO (op) == STACK_POINTER_REGNUM")))
106 ;; Integer constraints
108 (define_constraint "I"
109 "A signed 16-bit constant (for arithmetic instructions)."
110 (and (match_code "const_int")
111 (match_test "SMALL_OPERAND (ival)")))
113 (define_constraint "J"
115 (and (match_code "const_int")
116 (match_test "ival == 0")))
118 (define_constraint "K"
119 "An unsigned 16-bit constant (for logic instructions)."
120 (and (match_code "const_int")
121 (match_test "SMALL_OPERAND_UNSIGNED (ival)")))
123 (define_constraint "L"
124 "A signed 32-bit constant in which the lower 16 bits are zero.
125 Such constants can be loaded using @code{lui}."
126 (and (match_code "const_int")
127 (match_test "LUI_OPERAND (ival)")))
129 (define_constraint "M"
130 "A constant that cannot be loaded using @code{lui}, @code{addiu}
132 (and (match_code "const_int")
133 (not (match_test "SMALL_OPERAND (ival)"))
134 (not (match_test "SMALL_OPERAND_UNSIGNED (ival)"))
135 (not (match_test "LUI_OPERAND (ival)"))))
137 (define_constraint "N"
138 "A constant in the range -65535 to -1 (inclusive)."
139 (and (match_code "const_int")
140 (match_test "ival >= -0xffff && ival < 0")))
142 (define_constraint "O"
143 "A signed 15-bit constant."
144 (and (match_code "const_int")
145 (match_test "ival >= -0x4000 && ival < 0x4000")))
147 (define_constraint "P"
148 "A constant in the range 1 to 65535 (inclusive)."
149 (and (match_code "const_int")
150 (match_test "ival > 0 && ival < 0x10000")))
152 ;; Floating-point constraints
154 (define_constraint "G"
155 "Floating-point zero."
156 (and (match_code "const_double")
157 (match_test "op == CONST0_RTX (mode)")))
159 ;; General constraints
161 (define_constraint "Q"
163 (match_operand 0 "const_arith_operand"))
165 (define_memory_constraint "R"
166 "An address that can be used in a non-macro load or store."
167 (and (match_code "mem")
168 (match_test "mips_address_insns (XEXP (op, 0), mode, false) == 1")))
170 (define_constraint "S"
172 A constant call address."
173 (and (match_operand 0 "call_insn_operand")
174 (match_test "CONSTANT_P (op)")))
176 (define_constraint "Udb7"
178 A decremented unsigned constant of 7 bits."
179 (match_operand 0 "db7_operand"))
181 (define_constraint "Udb8"
183 A decremented unsigned constant of 8 bits."
184 (match_operand 0 "db8_operand"))
186 (define_constraint "Uead"
188 A microMIPS encoded ADDIUR2 immediate operand."
189 (match_operand 0 "addiur2_operand"))
191 (define_constraint "Uean"
193 A microMIPS encoded ANDI operand."
194 (match_operand 0 "andi16_operand"))
196 (define_constraint "Uesp"
198 A microMIPS encoded ADDIUSP operand."
199 (match_operand 0 "addiusp_operand"))
201 (define_constraint "Uib3"
203 An unsigned, incremented constant of 3 bits."
204 (match_operand 0 "ib3_operand"))
206 (define_constraint "Usb4"
208 A signed constant of 4 bits."
209 (match_operand 0 "sb4_operand"))
211 (define_constraint "Usb5"
213 A signed constant of 5 bits."
214 (match_operand 0 "sb5_operand"))
216 (define_constraint "Usb8"
218 A signed constant of 8 bits."
219 (match_operand 0 "sb8_operand"))
221 (define_constraint "Usd8"
223 A signed constant of 8 bits, shifted left three places."
224 (match_operand 0 "sd8_operand"))
226 (define_constraint "Uub8"
228 An unsigned constant of 8 bits."
229 (match_operand 0 "ub8_operand"))
231 (define_constraint "Uuw5"
233 An unsigned constant of 5 bits, shifted left two places."
234 (match_operand 0 "uw5_operand"))
236 (define_constraint "Uuw6"
238 An unsigned constant of 6 bits, shifted left two places."
239 (match_operand 0 "uw6_operand"))
241 (define_constraint "Uuw8"
243 An unsigned constant of 8 bits, shifted left two places."
244 (match_operand 0 "uw8_operand"))
246 (define_memory_constraint "W"
248 A memory address based on a member of @code{BASE_REG_CLASS}. This is
249 true for all non-mips16 references (although it can sometimes be implicit
250 if @samp{!TARGET_EXPLICIT_RELOCS}). For MIPS16, it excludes stack and
251 constant-pool references."
252 (and (match_code "mem")
253 (match_operand 0 "memory_operand")
254 (ior (not (match_test "TARGET_MIPS16"))
255 (and (not (match_operand 0 "stack_operand"))
256 (not (match_test "CONSTANT_P (XEXP (op, 0))"))))))
258 (define_constraint "YG"
261 (and (match_code "const_vector")
262 (match_test "op == CONST0_RTX (mode)")))
264 (define_constraint "YA"
266 An unsigned 6-bit constant."
267 (and (match_code "const_int")
268 (match_test "UIMM6_OPERAND (ival)")))
270 (define_constraint "YB"
272 A signed 10-bit constant."
273 (and (match_code "const_int")
274 (match_test "IMM10_OPERAND (ival)")))
276 (define_constraint "Yb"
278 (match_operand 0 "qi_mask_operand"))
280 (define_constraint "Yd"
282 A constant @code{move_operand} that can be safely loaded into @code{$25}
284 (and (match_operand 0 "move_operand")
285 (match_test "CONSTANT_P (op)")
286 (not (match_test "mips_dangerous_for_la25_p (op)"))))
288 (define_constraint "Yf"
290 A constant @code{move_operand} that cannot be safely loaded into @code{$25}
292 (and (match_operand 0 "move_operand")
293 (match_test "CONSTANT_P (op)")
294 (match_test "mips_dangerous_for_la25_p (op)")))
296 (define_constraint "Yh"
298 (match_operand 0 "hi_mask_operand"))
300 (define_constraint "Yw"
302 (match_operand 0 "si_mask_operand"))
304 (define_constraint "Yx"
306 (match_operand 0 "low_bitmask_operand"))
308 (define_memory_constraint "ZC"
309 "When compiling microMIPS code, this constraint matches a memory operand
310 whose address is formed from a base register and a 12-bit offset. These
311 operands can be used for microMIPS instructions such as @code{ll} and
312 @code{sc}. When not compiling for microMIPS code, @code{ZC} is
313 equivalent to @code{R}."
314 (and (match_code "mem")
316 (match_test "TARGET_MICROMIPS")
317 (match_test "umips_12bit_offset_address_p (XEXP (op, 0), mode)")
318 (match_test "mips_address_insns (XEXP (op, 0), mode, false)"))))
320 (define_address_constraint "ZD"
321 "When compiling microMIPS code, this constraint matches an address operand
322 that is formed from a base register and a 12-bit offset. These operands
323 can be used for microMIPS instructions such as @code{prefetch}. When
324 not compiling for microMIPS code, @code{ZD} is equivalent to @code{p}."
325 (if_then_else (match_test "TARGET_MICROMIPS")
326 (match_test "umips_12bit_offset_address_p (op, mode)")
327 (match_test "mips_address_insns (op, mode, false)")))
329 (define_memory_constraint "ZR"
331 An address valid for loading/storing register exclusive"
332 (match_operand 0 "mem_noofs_operand"))
334 (define_memory_constraint "ZS"
336 A microMIPS memory operand for use with the LWSP/SWSP insns."
337 (and (match_code "mem")
338 (match_operand 0 "lwsp_swsp_operand")))
340 (define_memory_constraint "ZT"
342 A microMIPS memory operand for use with the LW16/SW16 insns."
343 (and (match_code "mem")
344 (match_operand 0 "lw16_sw16_operand")))
346 (define_memory_constraint "ZU"
348 A microMIPS memory operand for use with the LHU16/SH16 insns."
349 (and (match_code "mem")
350 (match_operand 0 "lhu16_sh16_operand")))
352 (define_memory_constraint "ZV"
354 A microMIPS memory operand for use with the SB16 insn."
355 (and (match_code "mem")
356 (match_operand 0 "sb16_operand")))
358 (define_memory_constraint "ZW"
360 A microMIPS memory operand for use with the LBU16 insn."
361 (and (match_code "mem")
362 (match_operand 0 "lbu16_operand")))