1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
81 #include "hard-reg-set.h"
82 #include "basic-block.h"
83 #include "insn-config.h"
85 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
87 #include "insn-attr.h"
92 /* It is not safe to use ordinary gen_lowpart in combine.
93 Use gen_lowpart_for_combine instead. See comments there. */
94 #define gen_lowpart dont_use_gen_lowpart_you_dummy
96 /* Number of attempts to combine instructions in this function. */
98 static int combine_attempts
;
100 /* Number of attempts that got as far as substitution in this function. */
102 static int combine_merges
;
104 /* Number of instructions combined with added SETs in this function. */
106 static int combine_extras
;
108 /* Number of instructions combined in this function. */
110 static int combine_successes
;
112 /* Totals over entire compilation. */
114 static int total_attempts
, total_merges
, total_extras
, total_successes
;
117 /* Vector mapping INSN_UIDs to cuids.
118 The cuids are like uids but increase monotonically always.
119 Combine always uses cuids so that it can compare them.
120 But actually renumbering the uids, which we used to do,
121 proves to be a bad idea because it makes it hard to compare
122 the dumps produced by earlier passes with those from later passes. */
124 static int *uid_cuid
;
125 static int max_uid_cuid
;
127 /* Get the cuid of an insn. */
129 #define INSN_CUID(INSN) \
130 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
132 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
133 BITS_PER_WORD would invoke undefined behavior. Work around it. */
135 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
136 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
138 #define nonzero_bits(X, M) \
139 cached_nonzero_bits (X, M, NULL_RTX, VOIDmode, 0)
141 #define num_sign_bit_copies(X, M) \
142 cached_num_sign_bit_copies (X, M, NULL_RTX, VOIDmode, 0)
144 /* Maximum register number, which is the size of the tables below. */
146 static unsigned int combine_max_regno
;
148 /* Record last point of death of (hard or pseudo) register n. */
150 static rtx
*reg_last_death
;
152 /* Record last point of modification of (hard or pseudo) register n. */
154 static rtx
*reg_last_set
;
156 /* Record the cuid of the last insn that invalidated memory
157 (anything that writes memory, and subroutine calls, but not pushes). */
159 static int mem_last_set
;
161 /* Record the cuid of the last CALL_INSN
162 so we can tell whether a potential combination crosses any calls. */
164 static int last_call_cuid
;
166 /* When `subst' is called, this is the insn that is being modified
167 (by combining in a previous insn). The PATTERN of this insn
168 is still the old pattern partially modified and it should not be
169 looked at, but this may be used to examine the successors of the insn
170 to judge whether a simplification is valid. */
172 static rtx subst_insn
;
174 /* This is the lowest CUID that `subst' is currently dealing with.
175 get_last_value will not return a value if the register was set at or
176 after this CUID. If not for this mechanism, we could get confused if
177 I2 or I1 in try_combine were an insn that used the old value of a register
178 to obtain a new value. In that case, we might erroneously get the
179 new value of the register when we wanted the old one. */
181 static int subst_low_cuid
;
183 /* This contains any hard registers that are used in newpat; reg_dead_at_p
184 must consider all these registers to be always live. */
186 static HARD_REG_SET newpat_used_regs
;
188 /* This is an insn to which a LOG_LINKS entry has been added. If this
189 insn is the earlier than I2 or I3, combine should rescan starting at
192 static rtx added_links_insn
;
194 /* Basic block in which we are performing combines. */
195 static basic_block this_basic_block
;
197 /* A bitmap indicating which blocks had registers go dead at entry.
198 After combine, we'll need to re-do global life analysis with
199 those blocks as starting points. */
200 static sbitmap refresh_blocks
;
202 /* The next group of arrays allows the recording of the last value assigned
203 to (hard or pseudo) register n. We use this information to see if an
204 operation being processed is redundant given a prior operation performed
205 on the register. For example, an `and' with a constant is redundant if
206 all the zero bits are already known to be turned off.
208 We use an approach similar to that used by cse, but change it in the
211 (1) We do not want to reinitialize at each label.
212 (2) It is useful, but not critical, to know the actual value assigned
213 to a register. Often just its form is helpful.
215 Therefore, we maintain the following arrays:
217 reg_last_set_value the last value assigned
218 reg_last_set_label records the value of label_tick when the
219 register was assigned
220 reg_last_set_table_tick records the value of label_tick when a
221 value using the register is assigned
222 reg_last_set_invalid set to nonzero when it is not valid
223 to use the value of this register in some
226 To understand the usage of these tables, it is important to understand
227 the distinction between the value in reg_last_set_value being valid
228 and the register being validly contained in some other expression in the
231 Entry I in reg_last_set_value is valid if it is nonzero, and either
232 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
234 Register I may validly appear in any expression returned for the value
235 of another register if reg_n_sets[i] is 1. It may also appear in the
236 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
237 reg_last_set_invalid[j] is zero.
239 If an expression is found in the table containing a register which may
240 not validly appear in an expression, the register is replaced by
241 something that won't match, (clobber (const_int 0)).
243 reg_last_set_invalid[i] is set nonzero when register I is being assigned
244 to and reg_last_set_table_tick[i] == label_tick. */
246 /* Record last value assigned to (hard or pseudo) register n. */
248 static rtx
*reg_last_set_value
;
250 /* Record the value of label_tick when the value for register n is placed in
251 reg_last_set_value[n]. */
253 static int *reg_last_set_label
;
255 /* Record the value of label_tick when an expression involving register n
256 is placed in reg_last_set_value. */
258 static int *reg_last_set_table_tick
;
260 /* Set nonzero if references to register n in expressions should not be
263 static char *reg_last_set_invalid
;
265 /* Incremented for each label. */
267 static int label_tick
;
269 /* Some registers that are set more than once and used in more than one
270 basic block are nevertheless always set in similar ways. For example,
271 a QImode register may be loaded from memory in two places on a machine
272 where byte loads zero extend.
274 We record in the following array what we know about the nonzero
275 bits of a register, specifically which bits are known to be zero.
277 If an entry is zero, it means that we don't know anything special. */
279 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
281 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
282 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
284 static enum machine_mode nonzero_bits_mode
;
286 /* Nonzero if we know that a register has some leading bits that are always
287 equal to the sign bit. */
289 static unsigned char *reg_sign_bit_copies
;
291 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
292 It is zero while computing them and after combine has completed. This
293 former test prevents propagating values based on previously set values,
294 which can be incorrect if a variable is modified in a loop. */
296 static int nonzero_sign_valid
;
298 /* These arrays are maintained in parallel with reg_last_set_value
299 and are used to store the mode in which the register was last set,
300 the bits that were known to be zero when it was last set, and the
301 number of sign bits copies it was known to have when it was last set. */
303 static enum machine_mode
*reg_last_set_mode
;
304 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
305 static char *reg_last_set_sign_bit_copies
;
307 /* Record one modification to rtl structure
308 to be undone by storing old_contents into *where.
309 is_int is 1 if the contents are an int. */
315 union {rtx r
; int i
;} old_contents
;
316 union {rtx
*r
; int *i
;} where
;
319 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
320 num_undo says how many are currently recorded.
322 other_insn is nonzero if we have modified some other insn in the process
323 of working on subst_insn. It must be verified too. */
332 static struct undobuf undobuf
;
334 /* Number of times the pseudo being substituted for
335 was found and replaced. */
337 static int n_occurrences
;
339 static void do_SUBST (rtx
*, rtx
);
340 static void do_SUBST_INT (int *, int);
341 static void init_reg_last_arrays (void);
342 static void setup_incoming_promotions (void);
343 static void set_nonzero_bits_and_sign_copies (rtx
, rtx
, void *);
344 static int cant_combine_insn_p (rtx
);
345 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
346 static int sets_function_arg_p (rtx
);
347 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, int, rtx
*);
348 static int contains_muldiv (rtx
);
349 static rtx
try_combine (rtx
, rtx
, rtx
, int *);
350 static void undo_all (void);
351 static void undo_commit (void);
352 static rtx
*find_split_point (rtx
*, rtx
);
353 static rtx
subst (rtx
, rtx
, rtx
, int, int);
354 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int, int);
355 static rtx
simplify_if_then_else (rtx
);
356 static rtx
simplify_set (rtx
);
357 static rtx
simplify_logical (rtx
, int);
358 static rtx
expand_compound_operation (rtx
);
359 static rtx
expand_field_assignment (rtx
);
360 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
361 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
362 static rtx
extract_left_shift (rtx
, int);
363 static rtx
make_compound_operation (rtx
, enum rtx_code
);
364 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
365 unsigned HOST_WIDE_INT
*);
366 static rtx
force_to_mode (rtx
, enum machine_mode
,
367 unsigned HOST_WIDE_INT
, rtx
, int);
368 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
369 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
370 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
371 static rtx
make_field_assignment (rtx
);
372 static rtx
apply_distributive_law (rtx
);
373 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
374 unsigned HOST_WIDE_INT
);
375 static unsigned HOST_WIDE_INT
cached_nonzero_bits (rtx
, enum machine_mode
,
376 rtx
, enum machine_mode
,
377 unsigned HOST_WIDE_INT
);
378 static unsigned HOST_WIDE_INT
nonzero_bits1 (rtx
, enum machine_mode
, rtx
,
380 unsigned HOST_WIDE_INT
);
381 static unsigned int cached_num_sign_bit_copies (rtx
, enum machine_mode
, rtx
,
384 static unsigned int num_sign_bit_copies1 (rtx
, enum machine_mode
, rtx
,
385 enum machine_mode
, unsigned int);
386 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
387 HOST_WIDE_INT
, enum machine_mode
, int *);
388 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
390 static int recog_for_combine (rtx
*, rtx
, rtx
*);
391 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
392 static rtx
gen_binary (enum rtx_code
, enum machine_mode
, rtx
, rtx
);
393 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
394 static void update_table_tick (rtx
);
395 static void record_value_for_reg (rtx
, rtx
, rtx
);
396 static void check_promoted_subreg (rtx
, rtx
);
397 static void record_dead_and_set_regs_1 (rtx
, rtx
, void *);
398 static void record_dead_and_set_regs (rtx
);
399 static int get_last_value_validate (rtx
*, rtx
, int, int);
400 static rtx
get_last_value (rtx
);
401 static int use_crosses_set_p (rtx
, int);
402 static void reg_dead_at_p_1 (rtx
, rtx
, void *);
403 static int reg_dead_at_p (rtx
, rtx
);
404 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
405 static int reg_bitfield_target_p (rtx
, rtx
);
406 static void distribute_notes (rtx
, rtx
, rtx
, rtx
);
407 static void distribute_links (rtx
);
408 static void mark_used_regs_combine (rtx
);
409 static int insn_cuid (rtx
);
410 static void record_promoted_value (rtx
, rtx
);
411 static rtx
reversed_comparison (rtx
, enum machine_mode
, rtx
, rtx
);
412 static enum rtx_code
combine_reversed_comparison_code (rtx
);
414 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
415 insn. The substitution can be undone by undo_all. If INTO is already
416 set to NEWVAL, do not record this change. Because computing NEWVAL might
417 also call SUBST, we have to compute it before we put anything into
421 do_SUBST (rtx
*into
, rtx newval
)
426 if (oldval
== newval
)
429 /* We'd like to catch as many invalid transformations here as
430 possible. Unfortunately, there are way too many mode changes
431 that are perfectly valid, so we'd waste too much effort for
432 little gain doing the checks here. Focus on catching invalid
433 transformations involving integer constants. */
434 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
435 && GET_CODE (newval
) == CONST_INT
)
437 /* Sanity check that we're replacing oldval with a CONST_INT
438 that is a valid sign-extension for the original mode. */
439 if (INTVAL (newval
) != trunc_int_for_mode (INTVAL (newval
),
443 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
444 CONST_INT is not valid, because after the replacement, the
445 original mode would be gone. Unfortunately, we can't tell
446 when do_SUBST is called to replace the operand thereof, so we
447 perform this test on oldval instead, checking whether an
448 invalid replacement took place before we got here. */
449 if ((GET_CODE (oldval
) == SUBREG
450 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
)
451 || (GET_CODE (oldval
) == ZERO_EXTEND
452 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
))
457 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
459 buf
= xmalloc (sizeof (struct undo
));
463 buf
->old_contents
.r
= oldval
;
466 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
469 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
471 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
472 for the value of a HOST_WIDE_INT value (including CONST_INT) is
476 do_SUBST_INT (int *into
, int newval
)
481 if (oldval
== newval
)
485 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
487 buf
= xmalloc (sizeof (struct undo
));
491 buf
->old_contents
.i
= oldval
;
494 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
497 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
499 /* Main entry point for combiner. F is the first insn of the function.
500 NREGS is the first unused pseudo-reg number.
502 Return nonzero if the combiner has turned an indirect jump
503 instruction into a direct jump. */
505 combine_instructions (rtx f
, unsigned int nregs
)
512 rtx links
, nextlinks
;
514 int new_direct_jump_p
= 0;
516 combine_attempts
= 0;
519 combine_successes
= 0;
521 combine_max_regno
= nregs
;
523 reg_nonzero_bits
= xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
));
524 reg_sign_bit_copies
= xcalloc (nregs
, sizeof (unsigned char));
526 reg_last_death
= xmalloc (nregs
* sizeof (rtx
));
527 reg_last_set
= xmalloc (nregs
* sizeof (rtx
));
528 reg_last_set_value
= xmalloc (nregs
* sizeof (rtx
));
529 reg_last_set_table_tick
= xmalloc (nregs
* sizeof (int));
530 reg_last_set_label
= xmalloc (nregs
* sizeof (int));
531 reg_last_set_invalid
= xmalloc (nregs
* sizeof (char));
532 reg_last_set_mode
= xmalloc (nregs
* sizeof (enum machine_mode
));
533 reg_last_set_nonzero_bits
= xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
534 reg_last_set_sign_bit_copies
= xmalloc (nregs
* sizeof (char));
536 init_reg_last_arrays ();
538 init_recog_no_volatile ();
540 /* Compute maximum uid value so uid_cuid can be allocated. */
542 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
543 if (INSN_UID (insn
) > i
)
546 uid_cuid
= xmalloc ((i
+ 1) * sizeof (int));
549 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
551 /* Don't use reg_nonzero_bits when computing it. This can cause problems
552 when, for example, we have j <<= 1 in a loop. */
554 nonzero_sign_valid
= 0;
556 /* Compute the mapping from uids to cuids.
557 Cuids are numbers assigned to insns, like uids,
558 except that cuids increase monotonically through the code.
560 Scan all SETs and see if we can deduce anything about what
561 bits are known to be zero for some registers and how many copies
562 of the sign bit are known to exist for those registers.
564 Also set any known values so that we can use it while searching
565 for what bits are known to be set. */
569 setup_incoming_promotions ();
571 refresh_blocks
= sbitmap_alloc (last_basic_block
);
572 sbitmap_zero (refresh_blocks
);
574 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
576 uid_cuid
[INSN_UID (insn
)] = ++i
;
582 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
584 record_dead_and_set_regs (insn
);
587 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
588 if (REG_NOTE_KIND (links
) == REG_INC
)
589 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
594 if (GET_CODE (insn
) == CODE_LABEL
)
598 nonzero_sign_valid
= 1;
600 /* Now scan all the insns in forward order. */
605 init_reg_last_arrays ();
606 setup_incoming_promotions ();
608 FOR_EACH_BB (this_basic_block
)
610 for (insn
= this_basic_block
->head
;
611 insn
!= NEXT_INSN (this_basic_block
->end
);
612 insn
= next
? next
: NEXT_INSN (insn
))
616 if (GET_CODE (insn
) == CODE_LABEL
)
619 else if (INSN_P (insn
))
621 /* See if we know about function return values before this
622 insn based upon SUBREG flags. */
623 check_promoted_subreg (insn
, PATTERN (insn
));
625 /* Try this insn with each insn it links back to. */
627 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
628 if ((next
= try_combine (insn
, XEXP (links
, 0),
629 NULL_RTX
, &new_direct_jump_p
)) != 0)
632 /* Try each sequence of three linked insns ending with this one. */
634 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
636 rtx link
= XEXP (links
, 0);
638 /* If the linked insn has been replaced by a note, then there
639 is no point in pursuing this chain any further. */
640 if (GET_CODE (link
) == NOTE
)
643 for (nextlinks
= LOG_LINKS (link
);
645 nextlinks
= XEXP (nextlinks
, 1))
646 if ((next
= try_combine (insn
, link
,
648 &new_direct_jump_p
)) != 0)
653 /* Try to combine a jump insn that uses CC0
654 with a preceding insn that sets CC0, and maybe with its
655 logical predecessor as well.
656 This is how we make decrement-and-branch insns.
657 We need this special code because data flow connections
658 via CC0 do not get entered in LOG_LINKS. */
660 if (GET_CODE (insn
) == JUMP_INSN
661 && (prev
= prev_nonnote_insn (insn
)) != 0
662 && GET_CODE (prev
) == INSN
663 && sets_cc0_p (PATTERN (prev
)))
665 if ((next
= try_combine (insn
, prev
,
666 NULL_RTX
, &new_direct_jump_p
)) != 0)
669 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
670 nextlinks
= XEXP (nextlinks
, 1))
671 if ((next
= try_combine (insn
, prev
,
673 &new_direct_jump_p
)) != 0)
677 /* Do the same for an insn that explicitly references CC0. */
678 if (GET_CODE (insn
) == INSN
679 && (prev
= prev_nonnote_insn (insn
)) != 0
680 && GET_CODE (prev
) == INSN
681 && sets_cc0_p (PATTERN (prev
))
682 && GET_CODE (PATTERN (insn
)) == SET
683 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
685 if ((next
= try_combine (insn
, prev
,
686 NULL_RTX
, &new_direct_jump_p
)) != 0)
689 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
690 nextlinks
= XEXP (nextlinks
, 1))
691 if ((next
= try_combine (insn
, prev
,
693 &new_direct_jump_p
)) != 0)
697 /* Finally, see if any of the insns that this insn links to
698 explicitly references CC0. If so, try this insn, that insn,
699 and its predecessor if it sets CC0. */
700 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
701 if (GET_CODE (XEXP (links
, 0)) == INSN
702 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
703 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
704 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
705 && GET_CODE (prev
) == INSN
706 && sets_cc0_p (PATTERN (prev
))
707 && (next
= try_combine (insn
, XEXP (links
, 0),
708 prev
, &new_direct_jump_p
)) != 0)
712 /* Try combining an insn with two different insns whose results it
714 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
715 for (nextlinks
= XEXP (links
, 1); nextlinks
;
716 nextlinks
= XEXP (nextlinks
, 1))
717 if ((next
= try_combine (insn
, XEXP (links
, 0),
719 &new_direct_jump_p
)) != 0)
722 if (GET_CODE (insn
) != NOTE
)
723 record_dead_and_set_regs (insn
);
732 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks
, 0, i
,
733 BASIC_BLOCK (i
)->flags
|= BB_DIRTY
);
734 new_direct_jump_p
|= purge_all_dead_edges (0);
735 delete_noop_moves (f
);
737 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES
,
738 PROP_DEATH_NOTES
| PROP_SCAN_DEAD_CODE
739 | PROP_KILL_DEAD_CODE
);
742 sbitmap_free (refresh_blocks
);
743 free (reg_nonzero_bits
);
744 free (reg_sign_bit_copies
);
745 free (reg_last_death
);
747 free (reg_last_set_value
);
748 free (reg_last_set_table_tick
);
749 free (reg_last_set_label
);
750 free (reg_last_set_invalid
);
751 free (reg_last_set_mode
);
752 free (reg_last_set_nonzero_bits
);
753 free (reg_last_set_sign_bit_copies
);
757 struct undo
*undo
, *next
;
758 for (undo
= undobuf
.frees
; undo
; undo
= next
)
766 total_attempts
+= combine_attempts
;
767 total_merges
+= combine_merges
;
768 total_extras
+= combine_extras
;
769 total_successes
+= combine_successes
;
771 nonzero_sign_valid
= 0;
773 /* Make recognizer allow volatile MEMs again. */
776 return new_direct_jump_p
;
779 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
782 init_reg_last_arrays (void)
784 unsigned int nregs
= combine_max_regno
;
786 memset (reg_last_death
, 0, nregs
* sizeof (rtx
));
787 memset (reg_last_set
, 0, nregs
* sizeof (rtx
));
788 memset (reg_last_set_value
, 0, nregs
* sizeof (rtx
));
789 memset (reg_last_set_table_tick
, 0, nregs
* sizeof (int));
790 memset (reg_last_set_label
, 0, nregs
* sizeof (int));
791 memset (reg_last_set_invalid
, 0, nregs
* sizeof (char));
792 memset (reg_last_set_mode
, 0, nregs
* sizeof (enum machine_mode
));
793 memset (reg_last_set_nonzero_bits
, 0, nregs
* sizeof (HOST_WIDE_INT
));
794 memset (reg_last_set_sign_bit_copies
, 0, nregs
* sizeof (char));
797 /* Set up any promoted values for incoming argument registers. */
800 setup_incoming_promotions (void)
802 #ifdef PROMOTE_FUNCTION_ARGS
805 enum machine_mode mode
;
807 rtx first
= get_insns ();
809 #ifndef OUTGOING_REGNO
810 #define OUTGOING_REGNO(N) N
812 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
813 /* Check whether this register can hold an incoming pointer
814 argument. FUNCTION_ARG_REGNO_P tests outgoing register
815 numbers, so translate if necessary due to register windows. */
816 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
817 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
820 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
823 gen_rtx_CLOBBER (mode
, const0_rtx
)));
828 /* Called via note_stores. If X is a pseudo that is narrower than
829 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
831 If we are setting only a portion of X and we can't figure out what
832 portion, assume all bits will be used since we don't know what will
835 Similarly, set how many bits of X are known to be copies of the sign bit
836 at all locations in the function. This is the smallest number implied
840 set_nonzero_bits_and_sign_copies (rtx x
, rtx set
,
841 void *data ATTRIBUTE_UNUSED
)
845 if (GET_CODE (x
) == REG
846 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
847 /* If this register is undefined at the start of the file, we can't
848 say what its contents were. */
849 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, REGNO (x
))
850 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
852 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
854 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
855 reg_sign_bit_copies
[REGNO (x
)] = 1;
859 /* If this is a complex assignment, see if we can convert it into a
860 simple assignment. */
861 set
= expand_field_assignment (set
);
863 /* If this is a simple assignment, or we have a paradoxical SUBREG,
864 set what we know about X. */
866 if (SET_DEST (set
) == x
867 || (GET_CODE (SET_DEST (set
)) == SUBREG
868 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
869 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
870 && SUBREG_REG (SET_DEST (set
)) == x
))
872 rtx src
= SET_SRC (set
);
874 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
875 /* If X is narrower than a word and SRC is a non-negative
876 constant that would appear negative in the mode of X,
877 sign-extend it for use in reg_nonzero_bits because some
878 machines (maybe most) will actually do the sign-extension
879 and this is the conservative approach.
881 ??? For 2.5, try to tighten up the MD files in this regard
882 instead of this kludge. */
884 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
885 && GET_CODE (src
) == CONST_INT
887 && 0 != (INTVAL (src
)
889 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
890 src
= GEN_INT (INTVAL (src
)
891 | ((HOST_WIDE_INT
) (-1)
892 << GET_MODE_BITSIZE (GET_MODE (x
))));
895 /* Don't call nonzero_bits if it cannot change anything. */
896 if (reg_nonzero_bits
[REGNO (x
)] != ~(unsigned HOST_WIDE_INT
) 0)
897 reg_nonzero_bits
[REGNO (x
)]
898 |= nonzero_bits (src
, nonzero_bits_mode
);
899 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
900 if (reg_sign_bit_copies
[REGNO (x
)] == 0
901 || reg_sign_bit_copies
[REGNO (x
)] > num
)
902 reg_sign_bit_copies
[REGNO (x
)] = num
;
906 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
907 reg_sign_bit_copies
[REGNO (x
)] = 1;
912 /* See if INSN can be combined into I3. PRED and SUCC are optionally
913 insns that were previously combined into I3 or that will be combined
914 into the merger of INSN and I3.
916 Return 0 if the combination is not allowed for any reason.
918 If the combination is allowed, *PDEST will be set to the single
919 destination of INSN and *PSRC to the single source, and this function
923 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
, rtx succ
,
924 rtx
*pdest
, rtx
*psrc
)
927 rtx set
= 0, src
, dest
;
932 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
933 && next_active_insn (succ
) == i3
)
934 : next_active_insn (insn
) == i3
);
936 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
937 or a PARALLEL consisting of such a SET and CLOBBERs.
939 If INSN has CLOBBER parallel parts, ignore them for our processing.
940 By definition, these happen during the execution of the insn. When it
941 is merged with another insn, all bets are off. If they are, in fact,
942 needed and aren't also supplied in I3, they may be added by
943 recog_for_combine. Otherwise, it won't match.
945 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
948 Get the source and destination of INSN. If more than one, can't
951 if (GET_CODE (PATTERN (insn
)) == SET
)
952 set
= PATTERN (insn
);
953 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
954 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
956 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
958 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
960 switch (GET_CODE (elt
))
962 /* This is important to combine floating point insns
965 /* Combining an isolated USE doesn't make sense.
966 We depend here on combinable_i3pat to reject them. */
967 /* The code below this loop only verifies that the inputs of
968 the SET in INSN do not change. We call reg_set_between_p
969 to verify that the REG in the USE does not change between
971 If the USE in INSN was for a pseudo register, the matching
972 insn pattern will likely match any register; combining this
973 with any other USE would only be safe if we knew that the
974 used registers have identical values, or if there was
975 something to tell them apart, e.g. different modes. For
976 now, we forgo such complicated tests and simply disallow
977 combining of USES of pseudo registers with any other USE. */
978 if (GET_CODE (XEXP (elt
, 0)) == REG
979 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
981 rtx i3pat
= PATTERN (i3
);
982 int i
= XVECLEN (i3pat
, 0) - 1;
983 unsigned int regno
= REGNO (XEXP (elt
, 0));
987 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
989 if (GET_CODE (i3elt
) == USE
990 && GET_CODE (XEXP (i3elt
, 0)) == REG
991 && (REGNO (XEXP (i3elt
, 0)) == regno
992 ? reg_set_between_p (XEXP (elt
, 0),
993 PREV_INSN (insn
), i3
)
994 : regno
>= FIRST_PSEUDO_REGISTER
))
1001 /* We can ignore CLOBBERs. */
1006 /* Ignore SETs whose result isn't used but not those that
1007 have side-effects. */
1008 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1009 && ! side_effects_p (elt
))
1012 /* If we have already found a SET, this is a second one and
1013 so we cannot combine with this insn. */
1021 /* Anything else means we can't combine. */
1027 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1028 so don't do anything with it. */
1029 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1038 set
= expand_field_assignment (set
);
1039 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1041 /* Don't eliminate a store in the stack pointer. */
1042 if (dest
== stack_pointer_rtx
1043 /* Don't combine with an insn that sets a register to itself if it has
1044 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1045 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1046 /* Can't merge an ASM_OPERANDS. */
1047 || GET_CODE (src
) == ASM_OPERANDS
1048 /* Can't merge a function call. */
1049 || GET_CODE (src
) == CALL
1050 /* Don't eliminate a function call argument. */
1051 || (GET_CODE (i3
) == CALL_INSN
1052 && (find_reg_fusage (i3
, USE
, dest
)
1053 || (GET_CODE (dest
) == REG
1054 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1055 && global_regs
[REGNO (dest
)])))
1056 /* Don't substitute into an incremented register. */
1057 || FIND_REG_INC_NOTE (i3
, dest
)
1058 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1060 /* Don't combine the end of a libcall into anything. */
1061 /* ??? This gives worse code, and appears to be unnecessary, since no
1062 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1063 use REG_RETVAL notes for noconflict blocks, but other code here
1064 makes sure that those insns don't disappear. */
1065 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1067 /* Make sure that DEST is not used after SUCC but before I3. */
1068 || (succ
&& ! all_adjacent
1069 && reg_used_between_p (dest
, succ
, i3
))
1070 /* Make sure that the value that is to be substituted for the register
1071 does not use any registers whose values alter in between. However,
1072 If the insns are adjacent, a use can't cross a set even though we
1073 think it might (this can happen for a sequence of insns each setting
1074 the same destination; reg_last_set of that register might point to
1075 a NOTE). If INSN has a REG_EQUIV note, the register is always
1076 equivalent to the memory so the substitution is valid even if there
1077 are intervening stores. Also, don't move a volatile asm or
1078 UNSPEC_VOLATILE across any other insns. */
1080 && (((GET_CODE (src
) != MEM
1081 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1082 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1083 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1084 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1085 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1086 better register allocation by not doing the combine. */
1087 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1088 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1089 /* Don't combine across a CALL_INSN, because that would possibly
1090 change whether the life span of some REGs crosses calls or not,
1091 and it is a pain to update that information.
1092 Exception: if source is a constant, moving it later can't hurt.
1093 Accept that special case, because it helps -fforce-addr a lot. */
1094 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1097 /* DEST must either be a REG or CC0. */
1098 if (GET_CODE (dest
) == REG
)
1100 /* If register alignment is being enforced for multi-word items in all
1101 cases except for parameters, it is possible to have a register copy
1102 insn referencing a hard register that is not allowed to contain the
1103 mode being copied and which would not be valid as an operand of most
1104 insns. Eliminate this problem by not combining with such an insn.
1106 Also, on some machines we don't want to extend the life of a hard
1109 if (GET_CODE (src
) == REG
1110 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1111 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1112 /* Don't extend the life of a hard register unless it is
1113 user variable (if we have few registers) or it can't
1114 fit into the desired register (meaning something special
1116 Also avoid substituting a return register into I3, because
1117 reload can't handle a conflict with constraints of other
1119 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1120 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1123 else if (GET_CODE (dest
) != CC0
)
1126 /* Don't substitute for a register intended as a clobberable operand.
1127 Similarly, don't substitute an expression containing a register that
1128 will be clobbered in I3. */
1129 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1130 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1131 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1132 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1134 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1137 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1138 or not), reject, unless nothing volatile comes between it and I3 */
1140 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1142 /* Make sure succ doesn't contain a volatile reference. */
1143 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1146 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1147 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1151 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1152 to be an explicit register variable, and was chosen for a reason. */
1154 if (GET_CODE (src
) == ASM_OPERANDS
1155 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1158 /* If there are any volatile insns between INSN and I3, reject, because
1159 they might affect machine state. */
1161 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1162 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1165 /* If INSN or I2 contains an autoincrement or autodecrement,
1166 make sure that register is not used between there and I3,
1167 and not already used in I3 either.
1168 Also insist that I3 not be a jump; if it were one
1169 and the incremented register were spilled, we would lose. */
1172 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1173 if (REG_NOTE_KIND (link
) == REG_INC
1174 && (GET_CODE (i3
) == JUMP_INSN
1175 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1176 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1181 /* Don't combine an insn that follows a CC0-setting insn.
1182 An insn that uses CC0 must not be separated from the one that sets it.
1183 We do, however, allow I2 to follow a CC0-setting insn if that insn
1184 is passed as I1; in that case it will be deleted also.
1185 We also allow combining in this case if all the insns are adjacent
1186 because that would leave the two CC0 insns adjacent as well.
1187 It would be more logical to test whether CC0 occurs inside I1 or I2,
1188 but that would be much slower, and this ought to be equivalent. */
1190 p
= prev_nonnote_insn (insn
);
1191 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1196 /* If we get here, we have passed all the tests and the combination is
1205 /* Check if PAT is an insn - or a part of it - used to set up an
1206 argument for a function in a hard register. */
1209 sets_function_arg_p (rtx pat
)
1214 switch (GET_CODE (pat
))
1217 return sets_function_arg_p (PATTERN (pat
));
1220 for (i
= XVECLEN (pat
, 0); --i
>= 0;)
1221 if (sets_function_arg_p (XVECEXP (pat
, 0, i
)))
1227 inner_dest
= SET_DEST (pat
);
1228 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1229 || GET_CODE (inner_dest
) == SUBREG
1230 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1231 inner_dest
= XEXP (inner_dest
, 0);
1233 return (GET_CODE (inner_dest
) == REG
1234 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1235 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest
)));
1244 /* LOC is the location within I3 that contains its pattern or the component
1245 of a PARALLEL of the pattern. We validate that it is valid for combining.
1247 One problem is if I3 modifies its output, as opposed to replacing it
1248 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1249 so would produce an insn that is not equivalent to the original insns.
1253 (set (reg:DI 101) (reg:DI 100))
1254 (set (subreg:SI (reg:DI 101) 0) <foo>)
1256 This is NOT equivalent to:
1258 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1259 (set (reg:DI 101) (reg:DI 100))])
1261 Not only does this modify 100 (in which case it might still be valid
1262 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1264 We can also run into a problem if I2 sets a register that I1
1265 uses and I1 gets directly substituted into I3 (not via I2). In that
1266 case, we would be getting the wrong value of I2DEST into I3, so we
1267 must reject the combination. This case occurs when I2 and I1 both
1268 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1269 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1270 of a SET must prevent combination from occurring.
1272 Before doing the above check, we first try to expand a field assignment
1273 into a set of logical operations.
1275 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1276 we place a register that is both set and used within I3. If more than one
1277 such register is detected, we fail.
1279 Return 1 if the combination is valid, zero otherwise. */
1282 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
,
1283 int i1_not_in_src
, rtx
*pi3dest_killed
)
1287 if (GET_CODE (x
) == SET
)
1290 rtx dest
= SET_DEST (set
);
1291 rtx src
= SET_SRC (set
);
1292 rtx inner_dest
= dest
;
1294 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1295 || GET_CODE (inner_dest
) == SUBREG
1296 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1297 inner_dest
= XEXP (inner_dest
, 0);
1299 /* Check for the case where I3 modifies its output, as discussed
1300 above. We don't want to prevent pseudos from being combined
1301 into the address of a MEM, so only prevent the combination if
1302 i1 or i2 set the same MEM. */
1303 if ((inner_dest
!= dest
&&
1304 (GET_CODE (inner_dest
) != MEM
1305 || rtx_equal_p (i2dest
, inner_dest
)
1306 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
)))
1307 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1308 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1310 /* This is the same test done in can_combine_p except we can't test
1311 all_adjacent; we don't have to, since this instruction will stay
1312 in place, thus we are not considering increasing the lifetime of
1315 Also, if this insn sets a function argument, combining it with
1316 something that might need a spill could clobber a previous
1317 function argument; the all_adjacent test in can_combine_p also
1318 checks this; here, we do a more specific test for this case. */
1320 || (GET_CODE (inner_dest
) == REG
1321 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1322 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1323 GET_MODE (inner_dest
))))
1324 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1327 /* If DEST is used in I3, it is being killed in this insn,
1328 so record that for later.
1329 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1330 STACK_POINTER_REGNUM, since these are always considered to be
1331 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1332 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1333 && reg_referenced_p (dest
, PATTERN (i3
))
1334 && REGNO (dest
) != FRAME_POINTER_REGNUM
1335 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1336 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1338 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1339 && (REGNO (dest
) != ARG_POINTER_REGNUM
1340 || ! fixed_regs
[REGNO (dest
)])
1342 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1344 if (*pi3dest_killed
)
1347 *pi3dest_killed
= dest
;
1351 else if (GET_CODE (x
) == PARALLEL
)
1355 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1356 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1357 i1_not_in_src
, pi3dest_killed
))
1364 /* Return 1 if X is an arithmetic expression that contains a multiplication
1365 and division. We don't count multiplications by powers of two here. */
1368 contains_muldiv (rtx x
)
1370 switch (GET_CODE (x
))
1372 case MOD
: case DIV
: case UMOD
: case UDIV
:
1376 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1377 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1379 switch (GET_RTX_CLASS (GET_CODE (x
)))
1381 case 'c': case '<': case '2':
1382 return contains_muldiv (XEXP (x
, 0))
1383 || contains_muldiv (XEXP (x
, 1));
1386 return contains_muldiv (XEXP (x
, 0));
1394 /* Determine whether INSN can be used in a combination. Return nonzero if
1395 not. This is used in try_combine to detect early some cases where we
1396 can't perform combinations. */
1399 cant_combine_insn_p (rtx insn
)
1404 /* If this isn't really an insn, we can't do anything.
1405 This can occur when flow deletes an insn that it has merged into an
1406 auto-increment address. */
1407 if (! INSN_P (insn
))
1410 /* Never combine loads and stores involving hard regs that are likely
1411 to be spilled. The register allocator can usually handle such
1412 reg-reg moves by tying. If we allow the combiner to make
1413 substitutions of likely-spilled regs, we may abort in reload.
1414 As an exception, we allow combinations involving fixed regs; these are
1415 not available to the register allocator so there's no risk involved. */
1417 set
= single_set (insn
);
1420 src
= SET_SRC (set
);
1421 dest
= SET_DEST (set
);
1422 if (GET_CODE (src
) == SUBREG
)
1423 src
= SUBREG_REG (src
);
1424 if (GET_CODE (dest
) == SUBREG
)
1425 dest
= SUBREG_REG (dest
);
1426 if (REG_P (src
) && REG_P (dest
)
1427 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1428 && ! fixed_regs
[REGNO (src
)]
1429 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src
))))
1430 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1431 && ! fixed_regs
[REGNO (dest
)]
1432 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest
))))))
1438 /* Try to combine the insns I1 and I2 into I3.
1439 Here I1 and I2 appear earlier than I3.
1440 I1 can be zero; then we combine just I2 into I3.
1442 If we are combining three insns and the resulting insn is not recognized,
1443 try splitting it into two insns. If that happens, I2 and I3 are retained
1444 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1447 Return 0 if the combination does not work. Then nothing is changed.
1448 If we did the combination, return the insn at which combine should
1451 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1452 new direct jump instruction. */
1455 try_combine (rtx i3
, rtx i2
, rtx i1
, int *new_direct_jump_p
)
1457 /* New patterns for I3 and I2, respectively. */
1458 rtx newpat
, newi2pat
= 0;
1459 int substed_i2
= 0, substed_i1
= 0;
1460 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1461 int added_sets_1
, added_sets_2
;
1462 /* Total number of SETs to put into I3. */
1464 /* Nonzero is I2's body now appears in I3. */
1466 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1467 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1468 /* Contains I3 if the destination of I3 is used in its source, which means
1469 that the old life of I3 is being killed. If that usage is placed into
1470 I2 and not in I3, a REG_DEAD note must be made. */
1471 rtx i3dest_killed
= 0;
1472 /* SET_DEST and SET_SRC of I2 and I1. */
1473 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1474 /* PATTERN (I2), or a copy of it in certain cases. */
1476 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1477 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1478 int i1_feeds_i3
= 0;
1479 /* Notes that must be added to REG_NOTES in I3 and I2. */
1480 rtx new_i3_notes
, new_i2_notes
;
1481 /* Notes that we substituted I3 into I2 instead of the normal case. */
1482 int i3_subst_into_i2
= 0;
1483 /* Notes that I1, I2 or I3 is a MULT operation. */
1491 /* Exit early if one of the insns involved can't be used for
1493 if (cant_combine_insn_p (i3
)
1494 || cant_combine_insn_p (i2
)
1495 || (i1
&& cant_combine_insn_p (i1
))
1496 /* We also can't do anything if I3 has a
1497 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1500 /* ??? This gives worse code, and appears to be unnecessary, since no
1501 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1502 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1508 undobuf
.other_insn
= 0;
1510 /* Reset the hard register usage information. */
1511 CLEAR_HARD_REG_SET (newpat_used_regs
);
1513 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1514 code below, set I1 to be the earlier of the two insns. */
1515 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1516 temp
= i1
, i1
= i2
, i2
= temp
;
1518 added_links_insn
= 0;
1520 /* First check for one important special-case that the code below will
1521 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1522 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1523 we may be able to replace that destination with the destination of I3.
1524 This occurs in the common code where we compute both a quotient and
1525 remainder into a structure, in which case we want to do the computation
1526 directly into the structure to avoid register-register copies.
1528 Note that this case handles both multiple sets in I2 and also
1529 cases where I2 has a number of CLOBBER or PARALLELs.
1531 We make very conservative checks below and only try to handle the
1532 most common cases of this. For example, we only handle the case
1533 where I2 and I3 are adjacent to avoid making difficult register
1536 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1537 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1538 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1539 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1540 && GET_CODE (PATTERN (i2
)) == PARALLEL
1541 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1542 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1543 below would need to check what is inside (and reg_overlap_mentioned_p
1544 doesn't support those codes anyway). Don't allow those destinations;
1545 the resulting insn isn't likely to be recognized anyway. */
1546 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1547 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1548 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1549 SET_DEST (PATTERN (i3
)))
1550 && next_real_insn (i2
) == i3
)
1552 rtx p2
= PATTERN (i2
);
1554 /* Make sure that the destination of I3,
1555 which we are going to substitute into one output of I2,
1556 is not used within another output of I2. We must avoid making this:
1557 (parallel [(set (mem (reg 69)) ...)
1558 (set (reg 69) ...)])
1559 which is not well-defined as to order of actions.
1560 (Besides, reload can't handle output reloads for this.)
1562 The problem can also happen if the dest of I3 is a memory ref,
1563 if another dest in I2 is an indirect memory ref. */
1564 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1565 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1566 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1567 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1568 SET_DEST (XVECEXP (p2
, 0, i
))))
1571 if (i
== XVECLEN (p2
, 0))
1572 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1573 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1574 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1575 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1580 subst_low_cuid
= INSN_CUID (i2
);
1582 added_sets_2
= added_sets_1
= 0;
1583 i2dest
= SET_SRC (PATTERN (i3
));
1585 /* Replace the dest in I2 with our dest and make the resulting
1586 insn the new pattern for I3. Then skip to where we
1587 validate the pattern. Everything was set up above. */
1588 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1589 SET_DEST (PATTERN (i3
)));
1592 i3_subst_into_i2
= 1;
1593 goto validate_replacement
;
1597 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1598 one of those words to another constant, merge them by making a new
1601 && (temp
= single_set (i2
)) != 0
1602 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1603 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1604 && GET_CODE (SET_DEST (temp
)) == REG
1605 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1606 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1607 && GET_CODE (PATTERN (i3
)) == SET
1608 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1609 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1610 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1611 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1612 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1614 HOST_WIDE_INT lo
, hi
;
1616 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1617 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1620 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1621 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1624 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1626 /* We don't handle the case of the target word being wider
1627 than a host wide int. */
1628 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1631 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1632 lo
|= (INTVAL (SET_SRC (PATTERN (i3
)))
1633 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1635 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1636 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1637 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1639 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1640 >> (HOST_BITS_PER_WIDE_INT
- 1));
1642 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1643 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1644 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1645 (INTVAL (SET_SRC (PATTERN (i3
)))));
1647 hi
= lo
< 0 ? -1 : 0;
1650 /* We don't handle the case of the higher word not fitting
1651 entirely in either hi or lo. */
1656 subst_low_cuid
= INSN_CUID (i2
);
1657 added_sets_2
= added_sets_1
= 0;
1658 i2dest
= SET_DEST (temp
);
1660 SUBST (SET_SRC (temp
),
1661 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1663 newpat
= PATTERN (i2
);
1664 goto validate_replacement
;
1668 /* If we have no I1 and I2 looks like:
1669 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1671 make up a dummy I1 that is
1674 (set (reg:CC X) (compare:CC Y (const_int 0)))
1676 (We can ignore any trailing CLOBBERs.)
1678 This undoes a previous combination and allows us to match a branch-and-
1681 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1682 && XVECLEN (PATTERN (i2
), 0) >= 2
1683 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1684 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1686 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1687 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1688 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1689 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1690 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1691 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1693 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1694 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1699 /* We make I1 with the same INSN_UID as I2. This gives it
1700 the same INSN_CUID for value tracking. Our fake I1 will
1701 never appear in the insn stream so giving it the same INSN_UID
1702 as I2 will not cause a problem. */
1704 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1705 BLOCK_FOR_INSN (i2
), INSN_LOCATOR (i2
),
1706 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1709 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1710 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1711 SET_DEST (PATTERN (i1
)));
1716 /* Verify that I2 and I1 are valid for combining. */
1717 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1718 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1724 /* Record whether I2DEST is used in I2SRC and similarly for the other
1725 cases. Knowing this will help in register status updating below. */
1726 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1727 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1728 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1730 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1732 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1734 /* Ensure that I3's pattern can be the destination of combines. */
1735 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1736 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1743 /* See if any of the insns is a MULT operation. Unless one is, we will
1744 reject a combination that is, since it must be slower. Be conservative
1746 if (GET_CODE (i2src
) == MULT
1747 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1748 || (GET_CODE (PATTERN (i3
)) == SET
1749 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1752 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1753 We used to do this EXCEPT in one case: I3 has a post-inc in an
1754 output operand. However, that exception can give rise to insns like
1756 which is a famous insn on the PDP-11 where the value of r3 used as the
1757 source was model-dependent. Avoid this sort of thing. */
1760 if (!(GET_CODE (PATTERN (i3
)) == SET
1761 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1762 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1763 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1764 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1765 /* It's not the exception. */
1768 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1769 if (REG_NOTE_KIND (link
) == REG_INC
1770 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1772 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1779 /* See if the SETs in I1 or I2 need to be kept around in the merged
1780 instruction: whenever the value set there is still needed past I3.
1781 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1783 For the SET in I1, we have two cases: If I1 and I2 independently
1784 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1785 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1786 in I1 needs to be kept around unless I1DEST dies or is set in either
1787 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1788 I1DEST. If so, we know I1 feeds into I2. */
1790 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1793 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1794 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1796 /* If the set in I2 needs to be kept around, we must make a copy of
1797 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1798 PATTERN (I2), we are only substituting for the original I1DEST, not into
1799 an already-substituted copy. This also prevents making self-referential
1800 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1803 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1804 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1808 i2pat
= copy_rtx (i2pat
);
1812 /* Substitute in the latest insn for the regs set by the earlier ones. */
1814 maxreg
= max_reg_num ();
1818 /* It is possible that the source of I2 or I1 may be performing an
1819 unneeded operation, such as a ZERO_EXTEND of something that is known
1820 to have the high part zero. Handle that case by letting subst look at
1821 the innermost one of them.
1823 Another way to do this would be to have a function that tries to
1824 simplify a single insn instead of merging two or more insns. We don't
1825 do this because of the potential of infinite loops and because
1826 of the potential extra memory required. However, doing it the way
1827 we are is a bit of a kludge and doesn't catch all cases.
1829 But only do this if -fexpensive-optimizations since it slows things down
1830 and doesn't usually win. */
1832 if (flag_expensive_optimizations
)
1834 /* Pass pc_rtx so no substitutions are done, just simplifications.
1835 The cases that we are interested in here do not involve the few
1836 cases were is_replaced is checked. */
1839 subst_low_cuid
= INSN_CUID (i1
);
1840 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1844 subst_low_cuid
= INSN_CUID (i2
);
1845 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1850 /* Many machines that don't use CC0 have insns that can both perform an
1851 arithmetic operation and set the condition code. These operations will
1852 be represented as a PARALLEL with the first element of the vector
1853 being a COMPARE of an arithmetic operation with the constant zero.
1854 The second element of the vector will set some pseudo to the result
1855 of the same arithmetic operation. If we simplify the COMPARE, we won't
1856 match such a pattern and so will generate an extra insn. Here we test
1857 for this case, where both the comparison and the operation result are
1858 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1859 I2SRC. Later we will make the PARALLEL that contains I2. */
1861 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1862 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1863 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1864 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1866 #ifdef EXTRA_CC_MODES
1868 enum machine_mode compare_mode
;
1871 newpat
= PATTERN (i3
);
1872 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1876 #ifdef EXTRA_CC_MODES
1877 /* See if a COMPARE with the operand we substituted in should be done
1878 with the mode that is currently being used. If not, do the same
1879 processing we do in `subst' for a SET; namely, if the destination
1880 is used only once, try to replace it with a register of the proper
1881 mode and also replace the COMPARE. */
1882 if (undobuf
.other_insn
== 0
1883 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1884 &undobuf
.other_insn
))
1885 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1887 != GET_MODE (SET_DEST (newpat
))))
1889 unsigned int regno
= REGNO (SET_DEST (newpat
));
1890 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1892 if (regno
< FIRST_PSEUDO_REGISTER
1893 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1894 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1896 if (regno
>= FIRST_PSEUDO_REGISTER
)
1897 SUBST (regno_reg_rtx
[regno
], new_dest
);
1899 SUBST (SET_DEST (newpat
), new_dest
);
1900 SUBST (XEXP (*cc_use
, 0), new_dest
);
1901 SUBST (SET_SRC (newpat
),
1902 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
1905 undobuf
.other_insn
= 0;
1912 n_occurrences
= 0; /* `subst' counts here */
1914 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1915 need to make a unique copy of I2SRC each time we substitute it
1916 to avoid self-referential rtl. */
1918 subst_low_cuid
= INSN_CUID (i2
);
1919 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1920 ! i1_feeds_i3
&& i1dest_in_i1src
);
1923 /* Record whether i2's body now appears within i3's body. */
1924 i2_is_used
= n_occurrences
;
1927 /* If we already got a failure, don't try to do more. Otherwise,
1928 try to substitute in I1 if we have it. */
1930 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1932 /* Before we can do this substitution, we must redo the test done
1933 above (see detailed comments there) that ensures that I1DEST
1934 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1936 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1944 subst_low_cuid
= INSN_CUID (i1
);
1945 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1949 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1950 to count all the ways that I2SRC and I1SRC can be used. */
1951 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1952 && i2_is_used
+ added_sets_2
> 1)
1953 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1954 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1956 /* Fail if we tried to make a new register (we used to abort, but there's
1957 really no reason to). */
1958 || max_reg_num () != maxreg
1959 /* Fail if we couldn't do something and have a CLOBBER. */
1960 || GET_CODE (newpat
) == CLOBBER
1961 /* Fail if this new pattern is a MULT and we didn't have one before
1962 at the outer level. */
1963 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
1970 /* If the actions of the earlier insns must be kept
1971 in addition to substituting them into the latest one,
1972 we must make a new PARALLEL for the latest insn
1973 to hold additional the SETs. */
1975 if (added_sets_1
|| added_sets_2
)
1979 if (GET_CODE (newpat
) == PARALLEL
)
1981 rtvec old
= XVEC (newpat
, 0);
1982 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
1983 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1984 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
1985 sizeof (old
->elem
[0]) * old
->num_elem
);
1990 total_sets
= 1 + added_sets_1
+ added_sets_2
;
1991 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1992 XVECEXP (newpat
, 0, 0) = old
;
1996 XVECEXP (newpat
, 0, --total_sets
)
1997 = (GET_CODE (PATTERN (i1
)) == PARALLEL
1998 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
2002 /* If there is no I1, use I2's body as is. We used to also not do
2003 the subst call below if I2 was substituted into I3,
2004 but that could lose a simplification. */
2006 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2008 /* See comment where i2pat is assigned. */
2009 XVECEXP (newpat
, 0, --total_sets
)
2010 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2014 /* We come here when we are replacing a destination in I2 with the
2015 destination of I3. */
2016 validate_replacement
:
2018 /* Note which hard regs this insn has as inputs. */
2019 mark_used_regs_combine (newpat
);
2021 /* Is the result of combination a valid instruction? */
2022 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2024 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2025 the second SET's destination is a register that is unused. In that case,
2026 we just need the first SET. This can occur when simplifying a divmod
2027 insn. We *must* test for this case here because the code below that
2028 splits two independent SETs doesn't handle this case correctly when it
2029 updates the register status. Also check the case where the first
2030 SET's destination is unused. That would not cause incorrect code, but
2031 does cause an unneeded insn to remain. */
2033 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2034 && XVECLEN (newpat
, 0) == 2
2035 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2036 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2037 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
2038 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
2039 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
2040 && asm_noperands (newpat
) < 0)
2042 newpat
= XVECEXP (newpat
, 0, 0);
2043 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2046 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2047 && XVECLEN (newpat
, 0) == 2
2048 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2049 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2050 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
2051 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
2052 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
2053 && asm_noperands (newpat
) < 0)
2055 newpat
= XVECEXP (newpat
, 0, 1);
2056 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2059 /* If we were combining three insns and the result is a simple SET
2060 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2061 insns. There are two ways to do this. It can be split using a
2062 machine-specific method (like when you have an addition of a large
2063 constant) or by combine in the function find_split_point. */
2065 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2066 && asm_noperands (newpat
) < 0)
2068 rtx m_split
, *split
;
2069 rtx ni2dest
= i2dest
;
2071 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2072 use I2DEST as a scratch register will help. In the latter case,
2073 convert I2DEST to the mode of the source of NEWPAT if we can. */
2075 m_split
= split_insns (newpat
, i3
);
2077 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2078 inputs of NEWPAT. */
2080 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2081 possible to try that as a scratch reg. This would require adding
2082 more code to make it work though. */
2084 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2086 /* If I2DEST is a hard register or the only use of a pseudo,
2087 we can change its mode. */
2088 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2089 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2090 && GET_CODE (i2dest
) == REG
2091 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2092 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2093 && ! REG_USERVAR_P (i2dest
))))
2094 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2097 m_split
= split_insns (gen_rtx_PARALLEL
2099 gen_rtvec (2, newpat
,
2100 gen_rtx_CLOBBER (VOIDmode
,
2103 /* If the split with the mode-changed register didn't work, try
2104 the original register. */
2105 if (! m_split
&& ni2dest
!= i2dest
)
2108 m_split
= split_insns (gen_rtx_PARALLEL
2110 gen_rtvec (2, newpat
,
2111 gen_rtx_CLOBBER (VOIDmode
,
2117 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2119 m_split
= PATTERN (m_split
);
2120 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2121 if (insn_code_number
>= 0)
2124 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2125 && (next_real_insn (i2
) == i3
2126 || ! use_crosses_set_p (PATTERN (m_split
), INSN_CUID (i2
))))
2129 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2130 newi2pat
= PATTERN (m_split
);
2132 i3set
= single_set (NEXT_INSN (m_split
));
2133 i2set
= single_set (m_split
);
2135 /* In case we changed the mode of I2DEST, replace it in the
2136 pseudo-register table here. We can't do it above in case this
2137 code doesn't get executed and we do a split the other way. */
2139 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2140 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2142 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2144 /* If I2 or I3 has multiple SETs, we won't know how to track
2145 register status, so don't use these insns. If I2's destination
2146 is used between I2 and I3, we also can't use these insns. */
2148 if (i2_code_number
>= 0 && i2set
&& i3set
2149 && (next_real_insn (i2
) == i3
2150 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2151 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2153 if (insn_code_number
>= 0)
2156 /* It is possible that both insns now set the destination of I3.
2157 If so, we must show an extra use of it. */
2159 if (insn_code_number
>= 0)
2161 rtx new_i3_dest
= SET_DEST (i3set
);
2162 rtx new_i2_dest
= SET_DEST (i2set
);
2164 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2165 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2166 || GET_CODE (new_i3_dest
) == SUBREG
)
2167 new_i3_dest
= XEXP (new_i3_dest
, 0);
2169 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2170 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2171 || GET_CODE (new_i2_dest
) == SUBREG
)
2172 new_i2_dest
= XEXP (new_i2_dest
, 0);
2174 if (GET_CODE (new_i3_dest
) == REG
2175 && GET_CODE (new_i2_dest
) == REG
2176 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2177 REG_N_SETS (REGNO (new_i2_dest
))++;
2181 /* If we can split it and use I2DEST, go ahead and see if that
2182 helps things be recognized. Verify that none of the registers
2183 are set between I2 and I3. */
2184 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2186 && GET_CODE (i2dest
) == REG
2188 /* We need I2DEST in the proper mode. If it is a hard register
2189 or the only use of a pseudo, we can change its mode. */
2190 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2191 || GET_MODE (*split
) == VOIDmode
2192 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2193 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2194 && ! REG_USERVAR_P (i2dest
)))
2195 && (next_real_insn (i2
) == i3
2196 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2197 /* We can't overwrite I2DEST if its value is still used by
2199 && ! reg_referenced_p (i2dest
, newpat
))
2201 rtx newdest
= i2dest
;
2202 enum rtx_code split_code
= GET_CODE (*split
);
2203 enum machine_mode split_mode
= GET_MODE (*split
);
2205 /* Get NEWDEST as a register in the proper mode. We have already
2206 validated that we can do this. */
2207 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2209 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2211 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2212 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2215 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2216 an ASHIFT. This can occur if it was inside a PLUS and hence
2217 appeared to be a memory address. This is a kludge. */
2218 if (split_code
== MULT
2219 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2220 && INTVAL (XEXP (*split
, 1)) > 0
2221 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2223 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2224 XEXP (*split
, 0), GEN_INT (i
)));
2225 /* Update split_code because we may not have a multiply
2227 split_code
= GET_CODE (*split
);
2230 #ifdef INSN_SCHEDULING
2231 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2232 be written as a ZERO_EXTEND. */
2233 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2235 #ifdef LOAD_EXTEND_OP
2236 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2237 what it really is. */
2238 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
2240 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
2241 SUBREG_REG (*split
)));
2244 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2245 SUBREG_REG (*split
)));
2249 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2250 SUBST (*split
, newdest
);
2251 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2253 /* If the split point was a MULT and we didn't have one before,
2254 don't use one now. */
2255 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2256 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2260 /* Check for a case where we loaded from memory in a narrow mode and
2261 then sign extended it, but we need both registers. In that case,
2262 we have a PARALLEL with both loads from the same memory location.
2263 We can split this into a load from memory followed by a register-register
2264 copy. This saves at least one insn, more if register allocation can
2267 We cannot do this if the destination of the first assignment is a
2268 condition code register or cc0. We eliminate this case by making sure
2269 the SET_DEST and SET_SRC have the same mode.
2271 We cannot do this if the destination of the second assignment is
2272 a register that we have already assumed is zero-extended. Similarly
2273 for a SUBREG of such a register. */
2275 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2276 && GET_CODE (newpat
) == PARALLEL
2277 && XVECLEN (newpat
, 0) == 2
2278 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2279 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2280 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
2281 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
2282 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2283 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2284 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2285 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2287 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2288 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2289 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2290 (GET_CODE (temp
) == REG
2291 && reg_nonzero_bits
[REGNO (temp
)] != 0
2292 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2293 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2294 && (reg_nonzero_bits
[REGNO (temp
)]
2295 != GET_MODE_MASK (word_mode
))))
2296 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2297 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2298 (GET_CODE (temp
) == REG
2299 && reg_nonzero_bits
[REGNO (temp
)] != 0
2300 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2301 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2302 && (reg_nonzero_bits
[REGNO (temp
)]
2303 != GET_MODE_MASK (word_mode
)))))
2304 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2305 SET_SRC (XVECEXP (newpat
, 0, 1)))
2306 && ! find_reg_note (i3
, REG_UNUSED
,
2307 SET_DEST (XVECEXP (newpat
, 0, 0))))
2311 newi2pat
= XVECEXP (newpat
, 0, 0);
2312 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2313 newpat
= XVECEXP (newpat
, 0, 1);
2314 SUBST (SET_SRC (newpat
),
2315 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2316 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2318 if (i2_code_number
>= 0)
2319 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2321 if (insn_code_number
>= 0)
2326 /* If we will be able to accept this, we have made a change to the
2327 destination of I3. This can invalidate a LOG_LINKS pointing
2328 to I3. No other part of combine.c makes such a transformation.
2330 The new I3 will have a destination that was previously the
2331 destination of I1 or I2 and which was used in i2 or I3. Call
2332 distribute_links to make a LOG_LINK from the next use of
2333 that destination. */
2335 PATTERN (i3
) = newpat
;
2336 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, i3
, NULL_RTX
));
2338 /* I3 now uses what used to be its destination and which is
2339 now I2's destination. That means we need a LOG_LINK from
2340 I3 to I2. But we used to have one, so we still will.
2342 However, some later insn might be using I2's dest and have
2343 a LOG_LINK pointing at I3. We must remove this link.
2344 The simplest way to remove the link is to point it at I1,
2345 which we know will be a NOTE. */
2347 for (insn
= NEXT_INSN (i3
);
2348 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2349 || insn
!= this_basic_block
->next_bb
->head
);
2350 insn
= NEXT_INSN (insn
))
2352 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2354 for (link
= LOG_LINKS (insn
); link
;
2355 link
= XEXP (link
, 1))
2356 if (XEXP (link
, 0) == i3
)
2357 XEXP (link
, 0) = i1
;
2365 /* Similarly, check for a case where we have a PARALLEL of two independent
2366 SETs but we started with three insns. In this case, we can do the sets
2367 as two separate insns. This case occurs when some SET allows two
2368 other insns to combine, but the destination of that SET is still live. */
2370 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2371 && GET_CODE (newpat
) == PARALLEL
2372 && XVECLEN (newpat
, 0) == 2
2373 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2374 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2375 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2376 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2377 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2378 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2379 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2381 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2382 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2383 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2384 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2385 XVECEXP (newpat
, 0, 0))
2386 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2387 XVECEXP (newpat
, 0, 1))
2388 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2389 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2391 /* Normally, it doesn't matter which of the two is done first,
2392 but it does if one references cc0. In that case, it has to
2395 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2397 newi2pat
= XVECEXP (newpat
, 0, 0);
2398 newpat
= XVECEXP (newpat
, 0, 1);
2403 newi2pat
= XVECEXP (newpat
, 0, 1);
2404 newpat
= XVECEXP (newpat
, 0, 0);
2407 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2409 if (i2_code_number
>= 0)
2410 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2413 /* If it still isn't recognized, fail and change things back the way they
2415 if ((insn_code_number
< 0
2416 /* Is the result a reasonable ASM_OPERANDS? */
2417 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2423 /* If we had to change another insn, make sure it is valid also. */
2424 if (undobuf
.other_insn
)
2426 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2427 rtx new_other_notes
;
2430 CLEAR_HARD_REG_SET (newpat_used_regs
);
2432 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2435 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2441 PATTERN (undobuf
.other_insn
) = other_pat
;
2443 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2444 are still valid. Then add any non-duplicate notes added by
2445 recog_for_combine. */
2446 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2448 next
= XEXP (note
, 1);
2450 if (REG_NOTE_KIND (note
) == REG_UNUSED
2451 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2453 if (GET_CODE (XEXP (note
, 0)) == REG
)
2454 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2456 remove_note (undobuf
.other_insn
, note
);
2460 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2461 if (GET_CODE (XEXP (note
, 0)) == REG
)
2462 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2464 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2465 undobuf
.other_insn
, NULL_RTX
);
2468 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2469 they are adjacent to each other or not. */
2471 rtx p
= prev_nonnote_insn (i3
);
2472 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2473 && sets_cc0_p (newi2pat
))
2481 /* We now know that we can do this combination. Merge the insns and
2482 update the status of registers and LOG_LINKS. */
2485 rtx i3notes
, i2notes
, i1notes
= 0;
2486 rtx i3links
, i2links
, i1links
= 0;
2490 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2492 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2493 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2495 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2497 /* Ensure that we do not have something that should not be shared but
2498 occurs multiple times in the new insns. Check this by first
2499 resetting all the `used' flags and then copying anything is shared. */
2501 reset_used_flags (i3notes
);
2502 reset_used_flags (i2notes
);
2503 reset_used_flags (i1notes
);
2504 reset_used_flags (newpat
);
2505 reset_used_flags (newi2pat
);
2506 if (undobuf
.other_insn
)
2507 reset_used_flags (PATTERN (undobuf
.other_insn
));
2509 i3notes
= copy_rtx_if_shared (i3notes
);
2510 i2notes
= copy_rtx_if_shared (i2notes
);
2511 i1notes
= copy_rtx_if_shared (i1notes
);
2512 newpat
= copy_rtx_if_shared (newpat
);
2513 newi2pat
= copy_rtx_if_shared (newi2pat
);
2514 if (undobuf
.other_insn
)
2515 reset_used_flags (PATTERN (undobuf
.other_insn
));
2517 INSN_CODE (i3
) = insn_code_number
;
2518 PATTERN (i3
) = newpat
;
2520 if (GET_CODE (i3
) == CALL_INSN
&& CALL_INSN_FUNCTION_USAGE (i3
))
2522 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
2524 reset_used_flags (call_usage
);
2525 call_usage
= copy_rtx (call_usage
);
2528 replace_rtx (call_usage
, i2dest
, i2src
);
2531 replace_rtx (call_usage
, i1dest
, i1src
);
2533 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
2536 if (undobuf
.other_insn
)
2537 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2539 /* We had one special case above where I2 had more than one set and
2540 we replaced a destination of one of those sets with the destination
2541 of I3. In that case, we have to update LOG_LINKS of insns later
2542 in this basic block. Note that this (expensive) case is rare.
2544 Also, in this case, we must pretend that all REG_NOTEs for I2
2545 actually came from I3, so that REG_UNUSED notes from I2 will be
2546 properly handled. */
2548 if (i3_subst_into_i2
)
2550 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2551 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2552 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2553 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2554 && ! find_reg_note (i2
, REG_UNUSED
,
2555 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2556 for (temp
= NEXT_INSN (i2
);
2557 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2558 || this_basic_block
->head
!= temp
);
2559 temp
= NEXT_INSN (temp
))
2560 if (temp
!= i3
&& INSN_P (temp
))
2561 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2562 if (XEXP (link
, 0) == i2
)
2563 XEXP (link
, 0) = i3
;
2568 while (XEXP (link
, 1))
2569 link
= XEXP (link
, 1);
2570 XEXP (link
, 1) = i2notes
;
2584 INSN_CODE (i2
) = i2_code_number
;
2585 PATTERN (i2
) = newi2pat
;
2589 PUT_CODE (i2
, NOTE
);
2590 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2591 NOTE_SOURCE_FILE (i2
) = 0;
2598 PUT_CODE (i1
, NOTE
);
2599 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2600 NOTE_SOURCE_FILE (i1
) = 0;
2603 /* Get death notes for everything that is now used in either I3 or
2604 I2 and used to die in a previous insn. If we built two new
2605 patterns, move from I1 to I2 then I2 to I3 so that we get the
2606 proper movement on registers that I2 modifies. */
2610 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2611 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2614 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2617 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2619 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
);
2621 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
);
2623 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
);
2625 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2627 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2628 know these are REG_UNUSED and want them to go to the desired insn,
2629 so we always pass it as i3. We have not counted the notes in
2630 reg_n_deaths yet, so we need to do so now. */
2632 if (newi2pat
&& new_i2_notes
)
2634 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2635 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2636 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2638 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
);
2643 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2644 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2645 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2647 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
);
2650 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2651 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2652 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2653 in that case, it might delete I2. Similarly for I2 and I1.
2654 Show an additional death due to the REG_DEAD note we make here. If
2655 we discard it in distribute_notes, we will decrement it again. */
2659 if (GET_CODE (i3dest_killed
) == REG
)
2660 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2662 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2663 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2665 NULL_RTX
, i2
, NULL_RTX
);
2667 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2669 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2672 if (i2dest_in_i2src
)
2674 if (GET_CODE (i2dest
) == REG
)
2675 REG_N_DEATHS (REGNO (i2dest
))++;
2677 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2678 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2679 NULL_RTX
, i2
, NULL_RTX
);
2681 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2682 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2685 if (i1dest_in_i1src
)
2687 if (GET_CODE (i1dest
) == REG
)
2688 REG_N_DEATHS (REGNO (i1dest
))++;
2690 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2691 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2692 NULL_RTX
, i2
, NULL_RTX
);
2694 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2695 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2698 distribute_links (i3links
);
2699 distribute_links (i2links
);
2700 distribute_links (i1links
);
2702 if (GET_CODE (i2dest
) == REG
)
2705 rtx i2_insn
= 0, i2_val
= 0, set
;
2707 /* The insn that used to set this register doesn't exist, and
2708 this life of the register may not exist either. See if one of
2709 I3's links points to an insn that sets I2DEST. If it does,
2710 that is now the last known value for I2DEST. If we don't update
2711 this and I2 set the register to a value that depended on its old
2712 contents, we will get confused. If this insn is used, thing
2713 will be set correctly in combine_instructions. */
2715 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2716 if ((set
= single_set (XEXP (link
, 0))) != 0
2717 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2718 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2720 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2722 /* If the reg formerly set in I2 died only once and that was in I3,
2723 zero its use count so it won't make `reload' do any work. */
2725 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2726 && ! i2dest_in_i2src
)
2728 regno
= REGNO (i2dest
);
2729 REG_N_SETS (regno
)--;
2733 if (i1
&& GET_CODE (i1dest
) == REG
)
2736 rtx i1_insn
= 0, i1_val
= 0, set
;
2738 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2739 if ((set
= single_set (XEXP (link
, 0))) != 0
2740 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2741 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2743 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2745 regno
= REGNO (i1dest
);
2746 if (! added_sets_1
&& ! i1dest_in_i1src
)
2747 REG_N_SETS (regno
)--;
2750 /* Update reg_nonzero_bits et al for any changes that may have been made
2751 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2752 important. Because newi2pat can affect nonzero_bits of newpat */
2754 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2755 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2757 /* Set new_direct_jump_p if a new return or simple jump instruction
2760 If I3 is now an unconditional jump, ensure that it has a
2761 BARRIER following it since it may have initially been a
2762 conditional jump. It may also be the last nonnote insn. */
2764 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
2766 *new_direct_jump_p
= 1;
2767 mark_jump_label (PATTERN (i3
), i3
, 0);
2769 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2770 || GET_CODE (temp
) != BARRIER
)
2771 emit_barrier_after (i3
);
2774 if (undobuf
.other_insn
!= NULL_RTX
2775 && (returnjump_p (undobuf
.other_insn
)
2776 || any_uncondjump_p (undobuf
.other_insn
)))
2778 *new_direct_jump_p
= 1;
2780 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
2781 || GET_CODE (temp
) != BARRIER
)
2782 emit_barrier_after (undobuf
.other_insn
);
2785 /* An NOOP jump does not need barrier, but it does need cleaning up
2787 if (GET_CODE (newpat
) == SET
2788 && SET_SRC (newpat
) == pc_rtx
2789 && SET_DEST (newpat
) == pc_rtx
)
2790 *new_direct_jump_p
= 1;
2793 combine_successes
++;
2796 if (added_links_insn
2797 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2798 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2799 return added_links_insn
;
2801 return newi2pat
? i2
: i3
;
2804 /* Undo all the modifications recorded in undobuf. */
2809 struct undo
*undo
, *next
;
2811 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2815 *undo
->where
.i
= undo
->old_contents
.i
;
2817 *undo
->where
.r
= undo
->old_contents
.r
;
2819 undo
->next
= undobuf
.frees
;
2820 undobuf
.frees
= undo
;
2826 /* We've committed to accepting the changes we made. Move all
2827 of the undos to the free list. */
2832 struct undo
*undo
, *next
;
2834 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2837 undo
->next
= undobuf
.frees
;
2838 undobuf
.frees
= undo
;
2844 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2845 where we have an arithmetic expression and return that point. LOC will
2848 try_combine will call this function to see if an insn can be split into
2852 find_split_point (rtx
*loc
, rtx insn
)
2855 enum rtx_code code
= GET_CODE (x
);
2857 unsigned HOST_WIDE_INT len
= 0;
2858 HOST_WIDE_INT pos
= 0;
2860 rtx inner
= NULL_RTX
;
2862 /* First special-case some codes. */
2866 #ifdef INSN_SCHEDULING
2867 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2869 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2872 return find_split_point (&SUBREG_REG (x
), insn
);
2876 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2877 using LO_SUM and HIGH. */
2878 if (GET_CODE (XEXP (x
, 0)) == CONST
2879 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2882 gen_rtx_LO_SUM (Pmode
,
2883 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
2885 return &XEXP (XEXP (x
, 0), 0);
2889 /* If we have a PLUS whose second operand is a constant and the
2890 address is not valid, perhaps will can split it up using
2891 the machine-specific way to split large constants. We use
2892 the first pseudo-reg (one of the virtual regs) as a placeholder;
2893 it will not remain in the result. */
2894 if (GET_CODE (XEXP (x
, 0)) == PLUS
2895 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2896 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2898 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2899 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2902 /* This should have produced two insns, each of which sets our
2903 placeholder. If the source of the second is a valid address,
2904 we can make put both sources together and make a split point
2908 && NEXT_INSN (seq
) != NULL_RTX
2909 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
2910 && GET_CODE (seq
) == INSN
2911 && GET_CODE (PATTERN (seq
)) == SET
2912 && SET_DEST (PATTERN (seq
)) == reg
2913 && ! reg_mentioned_p (reg
,
2914 SET_SRC (PATTERN (seq
)))
2915 && GET_CODE (NEXT_INSN (seq
)) == INSN
2916 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
2917 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
2918 && memory_address_p (GET_MODE (x
),
2919 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
2921 rtx src1
= SET_SRC (PATTERN (seq
));
2922 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
2924 /* Replace the placeholder in SRC2 with SRC1. If we can
2925 find where in SRC2 it was placed, that can become our
2926 split point and we can replace this address with SRC2.
2927 Just try two obvious places. */
2929 src2
= replace_rtx (src2
, reg
, src1
);
2931 if (XEXP (src2
, 0) == src1
)
2932 split
= &XEXP (src2
, 0);
2933 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2934 && XEXP (XEXP (src2
, 0), 0) == src1
)
2935 split
= &XEXP (XEXP (src2
, 0), 0);
2939 SUBST (XEXP (x
, 0), src2
);
2944 /* If that didn't work, perhaps the first operand is complex and
2945 needs to be computed separately, so make a split point there.
2946 This will occur on machines that just support REG + CONST
2947 and have a constant moved through some previous computation. */
2949 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2950 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2951 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2953 return &XEXP (XEXP (x
, 0), 0);
2959 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2960 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2961 we need to put the operand into a register. So split at that
2964 if (SET_DEST (x
) == cc0_rtx
2965 && GET_CODE (SET_SRC (x
)) != COMPARE
2966 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2967 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2968 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2969 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2970 return &SET_SRC (x
);
2973 /* See if we can split SET_SRC as it stands. */
2974 split
= find_split_point (&SET_SRC (x
), insn
);
2975 if (split
&& split
!= &SET_SRC (x
))
2978 /* See if we can split SET_DEST as it stands. */
2979 split
= find_split_point (&SET_DEST (x
), insn
);
2980 if (split
&& split
!= &SET_DEST (x
))
2983 /* See if this is a bitfield assignment with everything constant. If
2984 so, this is an IOR of an AND, so split it into that. */
2985 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2986 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2987 <= HOST_BITS_PER_WIDE_INT
)
2988 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2989 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2990 && GET_CODE (SET_SRC (x
)) == CONST_INT
2991 && ((INTVAL (XEXP (SET_DEST (x
), 1))
2992 + INTVAL (XEXP (SET_DEST (x
), 2)))
2993 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
2994 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
2996 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
2997 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
2998 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
2999 rtx dest
= XEXP (SET_DEST (x
), 0);
3000 enum machine_mode mode
= GET_MODE (dest
);
3001 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3003 if (BITS_BIG_ENDIAN
)
3004 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3008 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3011 gen_binary (IOR
, mode
,
3012 gen_binary (AND
, mode
, dest
,
3013 gen_int_mode (~(mask
<< pos
),
3015 GEN_INT (src
<< pos
)));
3017 SUBST (SET_DEST (x
), dest
);
3019 split
= find_split_point (&SET_SRC (x
), insn
);
3020 if (split
&& split
!= &SET_SRC (x
))
3024 /* Otherwise, see if this is an operation that we can split into two.
3025 If so, try to split that. */
3026 code
= GET_CODE (SET_SRC (x
));
3031 /* If we are AND'ing with a large constant that is only a single
3032 bit and the result is only being used in a context where we
3033 need to know if it is zero or nonzero, replace it with a bit
3034 extraction. This will avoid the large constant, which might
3035 have taken more than one insn to make. If the constant were
3036 not a valid argument to the AND but took only one insn to make,
3037 this is no worse, but if it took more than one insn, it will
3040 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3041 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3042 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3043 && GET_CODE (SET_DEST (x
)) == REG
3044 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3045 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3046 && XEXP (*split
, 0) == SET_DEST (x
)
3047 && XEXP (*split
, 1) == const0_rtx
)
3049 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3050 XEXP (SET_SRC (x
), 0),
3051 pos
, NULL_RTX
, 1, 1, 0, 0);
3052 if (extraction
!= 0)
3054 SUBST (SET_SRC (x
), extraction
);
3055 return find_split_point (loc
, insn
);
3061 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3062 is known to be on, this can be converted into a NEG of a shift. */
3063 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3064 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3065 && 1 <= (pos
= exact_log2
3066 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3067 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3069 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3073 gen_rtx_LSHIFTRT (mode
,
3074 XEXP (SET_SRC (x
), 0),
3077 split
= find_split_point (&SET_SRC (x
), insn
);
3078 if (split
&& split
!= &SET_SRC (x
))
3084 inner
= XEXP (SET_SRC (x
), 0);
3086 /* We can't optimize if either mode is a partial integer
3087 mode as we don't know how many bits are significant
3089 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3090 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3094 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3100 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3101 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3103 inner
= XEXP (SET_SRC (x
), 0);
3104 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3105 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3107 if (BITS_BIG_ENDIAN
)
3108 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3109 unsignedp
= (code
== ZERO_EXTRACT
);
3117 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3119 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3121 /* For unsigned, we have a choice of a shift followed by an
3122 AND or two shifts. Use two shifts for field sizes where the
3123 constant might be too large. We assume here that we can
3124 always at least get 8-bit constants in an AND insn, which is
3125 true for every current RISC. */
3127 if (unsignedp
&& len
<= 8)
3132 (mode
, gen_lowpart_for_combine (mode
, inner
),
3134 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3136 split
= find_split_point (&SET_SRC (x
), insn
);
3137 if (split
&& split
!= &SET_SRC (x
))
3144 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3145 gen_rtx_ASHIFT (mode
,
3146 gen_lowpart_for_combine (mode
, inner
),
3147 GEN_INT (GET_MODE_BITSIZE (mode
)
3149 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3151 split
= find_split_point (&SET_SRC (x
), insn
);
3152 if (split
&& split
!= &SET_SRC (x
))
3157 /* See if this is a simple operation with a constant as the second
3158 operand. It might be that this constant is out of range and hence
3159 could be used as a split point. */
3160 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3161 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3162 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3163 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3164 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3165 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3166 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3168 return &XEXP (SET_SRC (x
), 1);
3170 /* Finally, see if this is a simple operation with its first operand
3171 not in a register. The operation might require this operand in a
3172 register, so return it as a split point. We can always do this
3173 because if the first operand were another operation, we would have
3174 already found it as a split point. */
3175 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3176 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3177 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3178 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3179 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3180 return &XEXP (SET_SRC (x
), 0);
3186 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3187 it is better to write this as (not (ior A B)) so we can split it.
3188 Similarly for IOR. */
3189 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3192 gen_rtx_NOT (GET_MODE (x
),
3193 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3195 XEXP (XEXP (x
, 0), 0),
3196 XEXP (XEXP (x
, 1), 0))));
3197 return find_split_point (loc
, insn
);
3200 /* Many RISC machines have a large set of logical insns. If the
3201 second operand is a NOT, put it first so we will try to split the
3202 other operand first. */
3203 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3205 rtx tem
= XEXP (x
, 0);
3206 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3207 SUBST (XEXP (x
, 1), tem
);
3215 /* Otherwise, select our actions depending on our rtx class. */
3216 switch (GET_RTX_CLASS (code
))
3218 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3220 split
= find_split_point (&XEXP (x
, 2), insn
);
3223 /* ... fall through ... */
3227 split
= find_split_point (&XEXP (x
, 1), insn
);
3230 /* ... fall through ... */
3232 /* Some machines have (and (shift ...) ...) insns. If X is not
3233 an AND, but XEXP (X, 0) is, use it as our split point. */
3234 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3235 return &XEXP (x
, 0);
3237 split
= find_split_point (&XEXP (x
, 0), insn
);
3243 /* Otherwise, we don't have a split point. */
3247 /* Throughout X, replace FROM with TO, and return the result.
3248 The result is TO if X is FROM;
3249 otherwise the result is X, but its contents may have been modified.
3250 If they were modified, a record was made in undobuf so that
3251 undo_all will (among other things) return X to its original state.
3253 If the number of changes necessary is too much to record to undo,
3254 the excess changes are not made, so the result is invalid.
3255 The changes already made can still be undone.
3256 undobuf.num_undo is incremented for such changes, so by testing that
3257 the caller can tell whether the result is valid.
3259 `n_occurrences' is incremented each time FROM is replaced.
3261 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3263 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3264 by copying if `n_occurrences' is nonzero. */
3267 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
3269 enum rtx_code code
= GET_CODE (x
);
3270 enum machine_mode op0_mode
= VOIDmode
;
3275 /* Two expressions are equal if they are identical copies of a shared
3276 RTX or if they are both registers with the same register number
3279 #define COMBINE_RTX_EQUAL_P(X,Y) \
3281 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3282 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3284 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3287 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3290 /* If X and FROM are the same register but different modes, they will
3291 not have been seen as equal above. However, flow.c will make a
3292 LOG_LINKS entry for that case. If we do nothing, we will try to
3293 rerecognize our original insn and, when it succeeds, we will
3294 delete the feeding insn, which is incorrect.
3296 So force this insn not to match in this (rare) case. */
3297 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3298 && REGNO (x
) == REGNO (from
))
3299 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3301 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3302 of which may contain things that can be combined. */
3303 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3306 /* It is possible to have a subexpression appear twice in the insn.
3307 Suppose that FROM is a register that appears within TO.
3308 Then, after that subexpression has been scanned once by `subst',
3309 the second time it is scanned, TO may be found. If we were
3310 to scan TO here, we would find FROM within it and create a
3311 self-referent rtl structure which is completely wrong. */
3312 if (COMBINE_RTX_EQUAL_P (x
, to
))
3315 /* Parallel asm_operands need special attention because all of the
3316 inputs are shared across the arms. Furthermore, unsharing the
3317 rtl results in recognition failures. Failure to handle this case
3318 specially can result in circular rtl.
3320 Solve this by doing a normal pass across the first entry of the
3321 parallel, and only processing the SET_DESTs of the subsequent
3324 if (code
== PARALLEL
3325 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3326 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3328 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3330 /* If this substitution failed, this whole thing fails. */
3331 if (GET_CODE (new) == CLOBBER
3332 && XEXP (new, 0) == const0_rtx
)
3335 SUBST (XVECEXP (x
, 0, 0), new);
3337 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3339 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3341 if (GET_CODE (dest
) != REG
3342 && GET_CODE (dest
) != CC0
3343 && GET_CODE (dest
) != PC
)
3345 new = subst (dest
, from
, to
, 0, unique_copy
);
3347 /* If this substitution failed, this whole thing fails. */
3348 if (GET_CODE (new) == CLOBBER
3349 && XEXP (new, 0) == const0_rtx
)
3352 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3358 len
= GET_RTX_LENGTH (code
);
3359 fmt
= GET_RTX_FORMAT (code
);
3361 /* We don't need to process a SET_DEST that is a register, CC0,
3362 or PC, so set up to skip this common case. All other cases
3363 where we want to suppress replacing something inside a
3364 SET_SRC are handled via the IN_DEST operand. */
3366 && (GET_CODE (SET_DEST (x
)) == REG
3367 || GET_CODE (SET_DEST (x
)) == CC0
3368 || GET_CODE (SET_DEST (x
)) == PC
))
3371 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3374 op0_mode
= GET_MODE (XEXP (x
, 0));
3376 for (i
= 0; i
< len
; i
++)
3381 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3383 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3385 new = (unique_copy
&& n_occurrences
3386 ? copy_rtx (to
) : to
);
3391 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3394 /* If this substitution failed, this whole thing
3396 if (GET_CODE (new) == CLOBBER
3397 && XEXP (new, 0) == const0_rtx
)
3401 SUBST (XVECEXP (x
, i
, j
), new);
3404 else if (fmt
[i
] == 'e')
3406 /* If this is a register being set, ignore it. */
3409 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3410 || code
== ZERO_EXTRACT
)
3412 && GET_CODE (new) == REG
)
3415 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3417 /* In general, don't install a subreg involving two
3418 modes not tieable. It can worsen register
3419 allocation, and can even make invalid reload
3420 insns, since the reg inside may need to be copied
3421 from in the outside mode, and that may be invalid
3422 if it is an fp reg copied in integer mode.
3424 We allow two exceptions to this: It is valid if
3425 it is inside another SUBREG and the mode of that
3426 SUBREG and the mode of the inside of TO is
3427 tieable and it is valid if X is a SET that copies
3430 if (GET_CODE (to
) == SUBREG
3431 && ! MODES_TIEABLE_P (GET_MODE (to
),
3432 GET_MODE (SUBREG_REG (to
)))
3433 && ! (code
== SUBREG
3434 && MODES_TIEABLE_P (GET_MODE (x
),
3435 GET_MODE (SUBREG_REG (to
))))
3437 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3440 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3442 #ifdef CANNOT_CHANGE_MODE_CLASS
3444 && GET_CODE (to
) == REG
3445 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3446 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
3449 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3452 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3456 /* If we are in a SET_DEST, suppress most cases unless we
3457 have gone inside a MEM, in which case we want to
3458 simplify the address. We assume here that things that
3459 are actually part of the destination have their inner
3460 parts in the first expression. This is true for SUBREG,
3461 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3462 things aside from REG and MEM that should appear in a
3464 new = subst (XEXP (x
, i
), from
, to
,
3466 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3467 || code
== ZERO_EXTRACT
))
3469 && i
== 0), unique_copy
);
3471 /* If we found that we will have to reject this combination,
3472 indicate that by returning the CLOBBER ourselves, rather than
3473 an expression containing it. This will speed things up as
3474 well as prevent accidents where two CLOBBERs are considered
3475 to be equal, thus producing an incorrect simplification. */
3477 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3480 if (GET_CODE (x
) == SUBREG
3481 && (GET_CODE (new) == CONST_INT
3482 || GET_CODE (new) == CONST_DOUBLE
))
3484 enum machine_mode mode
= GET_MODE (x
);
3486 x
= simplify_subreg (GET_MODE (x
), new,
3487 GET_MODE (SUBREG_REG (x
)),
3490 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
3492 else if (GET_CODE (new) == CONST_INT
3493 && GET_CODE (x
) == ZERO_EXTEND
)
3495 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3496 new, GET_MODE (XEXP (x
, 0)));
3501 SUBST (XEXP (x
, i
), new);
3506 /* Try to simplify X. If the simplification changed the code, it is likely
3507 that further simplification will help, so loop, but limit the number
3508 of repetitions that will be performed. */
3510 for (i
= 0; i
< 4; i
++)
3512 /* If X is sufficiently simple, don't bother trying to do anything
3514 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3515 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3517 if (GET_CODE (x
) == code
)
3520 code
= GET_CODE (x
);
3522 /* We no longer know the original mode of operand 0 since we
3523 have changed the form of X) */
3524 op0_mode
= VOIDmode
;
3530 /* Simplify X, a piece of RTL. We just operate on the expression at the
3531 outer level; call `subst' to simplify recursively. Return the new
3534 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3535 will be the iteration even if an expression with a code different from
3536 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3539 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int last
,
3542 enum rtx_code code
= GET_CODE (x
);
3543 enum machine_mode mode
= GET_MODE (x
);
3548 /* If this is a commutative operation, put a constant last and a complex
3549 expression first. We don't need to do this for comparisons here. */
3550 if (GET_RTX_CLASS (code
) == 'c'
3551 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3554 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3555 SUBST (XEXP (x
, 1), temp
);
3558 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3559 sign extension of a PLUS with a constant, reverse the order of the sign
3560 extension and the addition. Note that this not the same as the original
3561 code, but overflow is undefined for signed values. Also note that the
3562 PLUS will have been partially moved "inside" the sign-extension, so that
3563 the first operand of X will really look like:
3564 (ashiftrt (plus (ashift A C4) C5) C4).
3566 (plus (ashiftrt (ashift A C4) C2) C4)
3567 and replace the first operand of X with that expression. Later parts
3568 of this function may simplify the expression further.
3570 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3571 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3572 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3574 We do this to simplify address expressions. */
3576 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3577 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3578 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3579 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3580 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3581 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3582 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3583 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3584 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3585 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3586 XEXP (XEXP (x
, 0), 1))) != 0)
3589 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3590 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3591 INTVAL (XEXP (XEXP (x
, 0), 1)));
3593 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3594 INTVAL (XEXP (XEXP (x
, 0), 1)));
3596 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3599 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3600 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3601 things. Check for cases where both arms are testing the same
3604 Don't do anything if all operands are very simple. */
3606 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3607 || GET_RTX_CLASS (code
) == '<')
3608 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3609 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3610 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3612 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3613 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3614 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3616 || (GET_RTX_CLASS (code
) == '1'
3617 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3618 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3619 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3622 rtx cond
, true_rtx
, false_rtx
;
3624 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3626 /* If everything is a comparison, what we have is highly unlikely
3627 to be simpler, so don't use it. */
3628 && ! (GET_RTX_CLASS (code
) == '<'
3629 && (GET_RTX_CLASS (GET_CODE (true_rtx
)) == '<'
3630 || GET_RTX_CLASS (GET_CODE (false_rtx
)) == '<')))
3632 rtx cop1
= const0_rtx
;
3633 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3635 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3638 /* Simplify the alternative arms; this may collapse the true and
3639 false arms to store-flag values. */
3640 true_rtx
= subst (true_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3641 false_rtx
= subst (false_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3643 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3644 is unlikely to be simpler. */
3645 if (general_operand (true_rtx
, VOIDmode
)
3646 && general_operand (false_rtx
, VOIDmode
))
3648 enum rtx_code reversed
;
3650 /* Restarting if we generate a store-flag expression will cause
3651 us to loop. Just drop through in this case. */
3653 /* If the result values are STORE_FLAG_VALUE and zero, we can
3654 just make the comparison operation. */
3655 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3656 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3657 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3658 && ((reversed
= reversed_comparison_code_parts
3659 (cond_code
, cond
, cop1
, NULL
))
3661 x
= gen_binary (reversed
, mode
, cond
, cop1
);
3663 /* Likewise, we can make the negate of a comparison operation
3664 if the result values are - STORE_FLAG_VALUE and zero. */
3665 else if (GET_CODE (true_rtx
) == CONST_INT
3666 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3667 && false_rtx
== const0_rtx
)
3668 x
= simplify_gen_unary (NEG
, mode
,
3669 gen_binary (cond_code
, mode
, cond
,
3672 else if (GET_CODE (false_rtx
) == CONST_INT
3673 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3674 && true_rtx
== const0_rtx
3675 && ((reversed
= reversed_comparison_code_parts
3676 (cond_code
, cond
, cop1
, NULL
))
3678 x
= simplify_gen_unary (NEG
, mode
,
3679 gen_binary (reversed
, mode
,
3683 return gen_rtx_IF_THEN_ELSE (mode
,
3684 gen_binary (cond_code
, VOIDmode
,
3686 true_rtx
, false_rtx
);
3688 code
= GET_CODE (x
);
3689 op0_mode
= VOIDmode
;
3694 /* Try to fold this expression in case we have constants that weren't
3697 switch (GET_RTX_CLASS (code
))
3700 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3704 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3705 if (cmp_mode
== VOIDmode
)
3707 cmp_mode
= GET_MODE (XEXP (x
, 1));
3708 if (cmp_mode
== VOIDmode
)
3709 cmp_mode
= op0_mode
;
3711 temp
= simplify_relational_operation (code
, cmp_mode
,
3712 XEXP (x
, 0), XEXP (x
, 1));
3714 #ifdef FLOAT_STORE_FLAG_VALUE
3715 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3717 if (temp
== const0_rtx
)
3718 temp
= CONST0_RTX (mode
);
3720 temp
= CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode
),
3727 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3731 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3732 XEXP (x
, 1), XEXP (x
, 2));
3739 code
= GET_CODE (temp
);
3740 op0_mode
= VOIDmode
;
3741 mode
= GET_MODE (temp
);
3744 /* First see if we can apply the inverse distributive law. */
3745 if (code
== PLUS
|| code
== MINUS
3746 || code
== AND
|| code
== IOR
|| code
== XOR
)
3748 x
= apply_distributive_law (x
);
3749 code
= GET_CODE (x
);
3750 op0_mode
= VOIDmode
;
3753 /* If CODE is an associative operation not otherwise handled, see if we
3754 can associate some operands. This can win if they are constants or
3755 if they are logically related (i.e. (a & b) & a). */
3756 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3757 || code
== AND
|| code
== IOR
|| code
== XOR
3758 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3759 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3760 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3762 if (GET_CODE (XEXP (x
, 0)) == code
)
3764 rtx other
= XEXP (XEXP (x
, 0), 0);
3765 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3766 rtx inner_op1
= XEXP (x
, 1);
3769 /* Make sure we pass the constant operand if any as the second
3770 one if this is a commutative operation. */
3771 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3773 rtx tem
= inner_op0
;
3774 inner_op0
= inner_op1
;
3777 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3778 : code
== DIV
? MULT
3780 mode
, inner_op0
, inner_op1
);
3782 /* For commutative operations, try the other pair if that one
3784 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3786 other
= XEXP (XEXP (x
, 0), 1);
3787 inner
= simplify_binary_operation (code
, mode
,
3788 XEXP (XEXP (x
, 0), 0),
3793 return gen_binary (code
, mode
, other
, inner
);
3797 /* A little bit of algebraic simplification here. */
3801 /* Ensure that our address has any ASHIFTs converted to MULT in case
3802 address-recognizing predicates are called later. */
3803 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3804 SUBST (XEXP (x
, 0), temp
);
3808 if (op0_mode
== VOIDmode
)
3809 op0_mode
= GET_MODE (SUBREG_REG (x
));
3811 /* simplify_subreg can't use gen_lowpart_for_combine. */
3812 if (CONSTANT_P (SUBREG_REG (x
))
3813 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
3814 /* Don't call gen_lowpart_for_combine if the inner mode
3815 is VOIDmode and we cannot simplify it, as SUBREG without
3816 inner mode is invalid. */
3817 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
3818 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
3819 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3821 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
3825 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
3831 /* Don't change the mode of the MEM if that would change the meaning
3833 if (GET_CODE (SUBREG_REG (x
)) == MEM
3834 && (MEM_VOLATILE_P (SUBREG_REG (x
))
3835 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
3836 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3838 /* Note that we cannot do any narrowing for non-constants since
3839 we might have been counting on using the fact that some bits were
3840 zero. We now do this in the SET. */
3845 /* (not (plus X -1)) can become (neg X). */
3846 if (GET_CODE (XEXP (x
, 0)) == PLUS
3847 && XEXP (XEXP (x
, 0), 1) == constm1_rtx
)
3848 return gen_rtx_NEG (mode
, XEXP (XEXP (x
, 0), 0));
3850 /* Similarly, (not (neg X)) is (plus X -1). */
3851 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3852 return gen_rtx_PLUS (mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3854 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3855 if (GET_CODE (XEXP (x
, 0)) == XOR
3856 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3857 && (temp
= simplify_unary_operation (NOT
, mode
,
3858 XEXP (XEXP (x
, 0), 1),
3860 return gen_binary (XOR
, mode
, XEXP (XEXP (x
, 0), 0), temp
);
3862 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3863 other than 1, but that is not valid. We could do a similar
3864 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3865 but this doesn't seem common enough to bother with. */
3866 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
3867 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
3868 return gen_rtx_ROTATE (mode
, simplify_gen_unary (NOT
, mode
,
3870 XEXP (XEXP (x
, 0), 1));
3872 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3873 && subreg_lowpart_p (XEXP (x
, 0))
3874 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3875 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3876 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3877 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3879 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3881 x
= gen_rtx_ROTATE (inner_mode
,
3882 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
3884 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3885 return gen_lowpart_for_combine (mode
, x
);
3888 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3889 reversing the comparison code if valid. */
3890 if (STORE_FLAG_VALUE
== -1
3891 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3892 && (reversed
= reversed_comparison (x
, mode
, XEXP (XEXP (x
, 0), 0),
3893 XEXP (XEXP (x
, 0), 1))))
3896 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3897 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3898 perform the above simplification. */
3900 if (STORE_FLAG_VALUE
== -1
3901 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3902 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3903 && INTVAL (XEXP (XEXP (x
, 0), 1)) == GET_MODE_BITSIZE (mode
) - 1)
3904 return gen_rtx_GE (mode
, XEXP (XEXP (x
, 0), 0), const0_rtx
);
3906 /* Apply De Morgan's laws to reduce number of patterns for machines
3907 with negating logical insns (and-not, nand, etc.). If result has
3908 only one NOT, put it first, since that is how the patterns are
3911 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3913 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3914 enum machine_mode op_mode
;
3916 op_mode
= GET_MODE (in1
);
3917 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
3919 op_mode
= GET_MODE (in2
);
3920 if (op_mode
== VOIDmode
)
3922 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
3924 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
3927 in2
= in1
; in1
= tem
;
3930 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3936 /* (neg (plus X 1)) can become (not X). */
3937 if (GET_CODE (XEXP (x
, 0)) == PLUS
3938 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
3939 return gen_rtx_NOT (mode
, XEXP (XEXP (x
, 0), 0));
3941 /* Similarly, (neg (not X)) is (plus X 1). */
3942 if (GET_CODE (XEXP (x
, 0)) == NOT
)
3943 return plus_constant (XEXP (XEXP (x
, 0), 0), 1);
3945 /* (neg (minus X Y)) can become (minus Y X). This transformation
3946 isn't safe for modes with signed zeros, since if X and Y are
3947 both +0, (minus Y X) is the same as (minus X Y). If the rounding
3948 mode is towards +infinity (or -infinity) then the two expressions
3949 will be rounded differently. */
3950 if (GET_CODE (XEXP (x
, 0)) == MINUS
3951 && !HONOR_SIGNED_ZEROS (mode
)
3952 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
3953 return gen_binary (MINUS
, mode
, XEXP (XEXP (x
, 0), 1),
3954 XEXP (XEXP (x
, 0), 0));
3956 /* (neg (plus A B)) is canonicalized to (minus (neg A) B). */
3957 if (GET_CODE (XEXP (x
, 0)) == PLUS
3958 && !HONOR_SIGNED_ZEROS (mode
)
3959 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
3961 temp
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 0), 0), mode
);
3962 temp
= combine_simplify_rtx (temp
, mode
, last
, in_dest
);
3963 return gen_binary (MINUS
, mode
, temp
, XEXP (XEXP (x
, 0), 1));
3966 /* (neg (mult A B)) becomes (mult (neg A) B).
3967 This works even for floating-point values. */
3968 if (GET_CODE (XEXP (x
, 0)) == MULT
)
3970 temp
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 0), 0), mode
);
3971 return gen_binary (MULT
, mode
, temp
, XEXP (XEXP (x
, 0), 1));
3974 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3975 if (GET_CODE (XEXP (x
, 0)) == XOR
&& XEXP (XEXP (x
, 0), 1) == const1_rtx
3976 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
3977 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3979 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3980 if we can then eliminate the NEG (e.g.,
3981 if the operand is a constant). */
3983 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
3985 temp
= simplify_unary_operation (NEG
, mode
,
3986 XEXP (XEXP (x
, 0), 0), mode
);
3988 return gen_binary (ASHIFT
, mode
, temp
, XEXP (XEXP (x
, 0), 1));
3991 temp
= expand_compound_operation (XEXP (x
, 0));
3993 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3994 replaced by (lshiftrt X C). This will convert
3995 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3997 if (GET_CODE (temp
) == ASHIFTRT
3998 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3999 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
4000 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
4001 INTVAL (XEXP (temp
, 1)));
4003 /* If X has only a single bit that might be nonzero, say, bit I, convert
4004 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4005 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4006 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4007 or a SUBREG of one since we'd be making the expression more
4008 complex if it was just a register. */
4010 if (GET_CODE (temp
) != REG
4011 && ! (GET_CODE (temp
) == SUBREG
4012 && GET_CODE (SUBREG_REG (temp
)) == REG
)
4013 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
4015 rtx temp1
= simplify_shift_const
4016 (NULL_RTX
, ASHIFTRT
, mode
,
4017 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
4018 GET_MODE_BITSIZE (mode
) - 1 - i
),
4019 GET_MODE_BITSIZE (mode
) - 1 - i
);
4021 /* If all we did was surround TEMP with the two shifts, we
4022 haven't improved anything, so don't use it. Otherwise,
4023 we are better off with TEMP1. */
4024 if (GET_CODE (temp1
) != ASHIFTRT
4025 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
4026 || XEXP (XEXP (temp1
, 0), 0) != temp
)
4032 /* We can't handle truncation to a partial integer mode here
4033 because we don't know the real bitsize of the partial
4035 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
4038 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4039 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4040 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
4042 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
4043 GET_MODE_MASK (mode
), NULL_RTX
, 0));
4045 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4046 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4047 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4048 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4049 return XEXP (XEXP (x
, 0), 0);
4051 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4052 (OP:SI foo:SI) if OP is NEG or ABS. */
4053 if ((GET_CODE (XEXP (x
, 0)) == ABS
4054 || GET_CODE (XEXP (x
, 0)) == NEG
)
4055 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
4056 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
4057 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4058 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4059 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4061 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4063 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4064 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
4065 && subreg_lowpart_p (XEXP (x
, 0)))
4066 return SUBREG_REG (XEXP (x
, 0));
4068 /* If we know that the value is already truncated, we can
4069 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4070 is nonzero for the corresponding modes. But don't do this
4071 for an (LSHIFTRT (MULT ...)) since this will cause problems
4072 with the umulXi3_highpart patterns. */
4073 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4074 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4075 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4076 >= (unsigned int) (GET_MODE_BITSIZE (mode
) + 1)
4077 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4078 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4079 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4081 /* A truncate of a comparison can be replaced with a subreg if
4082 STORE_FLAG_VALUE permits. This is like the previous test,
4083 but it works even if the comparison is done in a mode larger
4084 than HOST_BITS_PER_WIDE_INT. */
4085 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4086 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4087 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4088 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4090 /* Similarly, a truncate of a register whose value is a
4091 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4093 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4094 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4095 && (temp
= get_last_value (XEXP (x
, 0)))
4096 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
4097 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4101 case FLOAT_TRUNCATE
:
4102 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4103 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4104 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4105 return XEXP (XEXP (x
, 0), 0);
4107 /* (float_truncate:SF (float_truncate:DF foo:XF))
4108 = (float_truncate:SF foo:XF).
4109 This may eliminate double rounding, so it is unsafe.
4111 (float_truncate:SF (float_extend:XF foo:DF))
4112 = (float_truncate:SF foo:DF).
4114 (float_truncate:DF (float_extend:XF foo:SF))
4115 = (float_extend:SF foo:DF). */
4116 if ((GET_CODE (XEXP (x
, 0)) == FLOAT_TRUNCATE
4117 && flag_unsafe_math_optimizations
)
4118 || GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
)
4119 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x
, 0),
4121 > GET_MODE_SIZE (mode
)
4122 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
4124 XEXP (XEXP (x
, 0), 0), mode
);
4126 /* (float_truncate (float x)) is (float x) */
4127 if (GET_CODE (XEXP (x
, 0)) == FLOAT
4128 && (flag_unsafe_math_optimizations
4129 || ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4130 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4131 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4132 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4133 return simplify_gen_unary (FLOAT
, mode
,
4134 XEXP (XEXP (x
, 0), 0),
4135 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4137 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4138 (OP:SF foo:SF) if OP is NEG or ABS. */
4139 if ((GET_CODE (XEXP (x
, 0)) == ABS
4140 || GET_CODE (XEXP (x
, 0)) == NEG
)
4141 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4142 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4143 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4144 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4146 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4147 is (float_truncate:SF x). */
4148 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4149 && subreg_lowpart_p (XEXP (x
, 0))
4150 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4151 return SUBREG_REG (XEXP (x
, 0));
4154 /* (float_extend (float_extend x)) is (float_extend x)
4156 (float_extend (float x)) is (float x) assuming that double
4157 rounding can't happen.
4159 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4160 || (GET_CODE (XEXP (x
, 0)) == FLOAT
4161 && ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4162 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4163 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4164 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4165 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4166 XEXP (XEXP (x
, 0), 0),
4167 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4172 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4173 using cc0, in which case we want to leave it as a COMPARE
4174 so we can distinguish it from a register-register-copy. */
4175 if (XEXP (x
, 1) == const0_rtx
)
4178 /* x - 0 is the same as x unless x's mode has signed zeros and
4179 allows rounding towards -infinity. Under those conditions,
4181 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4182 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4183 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4189 /* (const (const X)) can become (const X). Do it this way rather than
4190 returning the inner CONST since CONST can be shared with a
4192 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4193 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4198 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4199 can add in an offset. find_split_point will split this address up
4200 again if it doesn't match. */
4201 if (GET_CODE (XEXP (x
, 0)) == HIGH
4202 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4208 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4210 if (GET_CODE (XEXP (x
, 0)) == MULT
4211 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == NEG
)
4215 in1
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
4216 in2
= XEXP (XEXP (x
, 0), 1);
4217 return gen_binary (MINUS
, mode
, XEXP (x
, 1),
4218 gen_binary (MULT
, mode
, in1
, in2
));
4221 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4222 outermost. That's because that's the way indexed addresses are
4223 supposed to appear. This code used to check many more cases, but
4224 they are now checked elsewhere. */
4225 if (GET_CODE (XEXP (x
, 0)) == PLUS
4226 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4227 return gen_binary (PLUS
, mode
,
4228 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4230 XEXP (XEXP (x
, 0), 1));
4232 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4233 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4234 bit-field and can be replaced by either a sign_extend or a
4235 sign_extract. The `and' may be a zero_extend and the two
4236 <c>, -<c> constants may be reversed. */
4237 if (GET_CODE (XEXP (x
, 0)) == XOR
4238 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4239 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4240 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4241 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4242 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4243 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4244 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4245 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4246 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4247 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4248 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4249 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4250 == (unsigned int) i
+ 1))))
4251 return simplify_shift_const
4252 (NULL_RTX
, ASHIFTRT
, mode
,
4253 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4254 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4255 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4256 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4258 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4259 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4260 is 1. This produces better code than the alternative immediately
4262 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4263 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4264 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4265 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4266 XEXP (XEXP (x
, 0), 0),
4267 XEXP (XEXP (x
, 0), 1))))
4269 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4271 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4272 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4273 the bitsize of the mode - 1. This allows simplification of
4274 "a = (b & 8) == 0;" */
4275 if (XEXP (x
, 1) == constm1_rtx
4276 && GET_CODE (XEXP (x
, 0)) != REG
4277 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4278 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4279 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4280 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4281 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4282 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4283 GET_MODE_BITSIZE (mode
) - 1),
4284 GET_MODE_BITSIZE (mode
) - 1);
4286 /* If we are adding two things that have no bits in common, convert
4287 the addition into an IOR. This will often be further simplified,
4288 for example in cases like ((a & 1) + (a & 2)), which can
4291 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4292 && (nonzero_bits (XEXP (x
, 0), mode
)
4293 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4295 /* Try to simplify the expression further. */
4296 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4297 temp
= combine_simplify_rtx (tor
, mode
, last
, in_dest
);
4299 /* If we could, great. If not, do not go ahead with the IOR
4300 replacement, since PLUS appears in many special purpose
4301 address arithmetic instructions. */
4302 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4308 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4309 by reversing the comparison code if valid. */
4310 if (STORE_FLAG_VALUE
== 1
4311 && XEXP (x
, 0) == const1_rtx
4312 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4313 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4314 XEXP (XEXP (x
, 1), 0),
4315 XEXP (XEXP (x
, 1), 1))))
4318 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4319 (and <foo> (const_int pow2-1)) */
4320 if (GET_CODE (XEXP (x
, 1)) == AND
4321 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4322 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4323 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4324 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4325 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4327 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4329 if (GET_CODE (XEXP (x
, 1)) == MULT
4330 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == NEG
)
4334 in1
= XEXP (XEXP (XEXP (x
, 1), 0), 0);
4335 in2
= XEXP (XEXP (x
, 1), 1);
4336 return gen_binary (PLUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4340 /* Canonicalize (minus (neg A) (mult B C)) to
4341 (minus (mult (neg B) C) A). */
4342 if (GET_CODE (XEXP (x
, 1)) == MULT
4343 && GET_CODE (XEXP (x
, 0)) == NEG
)
4347 in1
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 1), 0), mode
);
4348 in2
= XEXP (XEXP (x
, 1), 1);
4349 return gen_binary (MINUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4350 XEXP (XEXP (x
, 0), 0));
4353 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4355 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4356 return gen_binary (MINUS
, mode
,
4357 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4358 XEXP (XEXP (x
, 1), 0)),
4359 XEXP (XEXP (x
, 1), 1));
4363 /* If we have (mult (plus A B) C), apply the distributive law and then
4364 the inverse distributive law to see if things simplify. This
4365 occurs mostly in addresses, often when unrolling loops. */
4367 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4369 x
= apply_distributive_law
4370 (gen_binary (PLUS
, mode
,
4371 gen_binary (MULT
, mode
,
4372 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4373 gen_binary (MULT
, mode
,
4374 XEXP (XEXP (x
, 0), 1),
4375 copy_rtx (XEXP (x
, 1)))));
4377 if (GET_CODE (x
) != MULT
)
4380 /* Try simplify a*(b/c) as (a*b)/c. */
4381 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4382 && GET_CODE (XEXP (x
, 0)) == DIV
)
4384 rtx tem
= simplify_binary_operation (MULT
, mode
,
4385 XEXP (XEXP (x
, 0), 0),
4388 return gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4393 /* If this is a divide by a power of two, treat it as a shift if
4394 its first operand is a shift. */
4395 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4396 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4397 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4398 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4399 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4400 || GET_CODE (XEXP (x
, 0)) == ROTATE
4401 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4402 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4406 case GT
: case GTU
: case GE
: case GEU
:
4407 case LT
: case LTU
: case LE
: case LEU
:
4408 case UNEQ
: case LTGT
:
4409 case UNGT
: case UNGE
:
4410 case UNLT
: case UNLE
:
4411 case UNORDERED
: case ORDERED
:
4412 /* If the first operand is a condition code, we can't do anything
4414 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4415 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4416 && ! CC0_P (XEXP (x
, 0))))
4418 rtx op0
= XEXP (x
, 0);
4419 rtx op1
= XEXP (x
, 1);
4420 enum rtx_code new_code
;
4422 if (GET_CODE (op0
) == COMPARE
)
4423 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4425 /* Simplify our comparison, if possible. */
4426 new_code
= simplify_comparison (code
, &op0
, &op1
);
4428 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4429 if only the low-order bit is possibly nonzero in X (such as when
4430 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4431 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4432 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4435 Remove any ZERO_EXTRACT we made when thinking this was a
4436 comparison. It may now be simpler to use, e.g., an AND. If a
4437 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4438 the call to make_compound_operation in the SET case. */
4440 if (STORE_FLAG_VALUE
== 1
4441 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4442 && op1
== const0_rtx
4443 && mode
== GET_MODE (op0
)
4444 && nonzero_bits (op0
, mode
) == 1)
4445 return gen_lowpart_for_combine (mode
,
4446 expand_compound_operation (op0
));
4448 else if (STORE_FLAG_VALUE
== 1
4449 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4450 && op1
== const0_rtx
4451 && mode
== GET_MODE (op0
)
4452 && (num_sign_bit_copies (op0
, mode
)
4453 == GET_MODE_BITSIZE (mode
)))
4455 op0
= expand_compound_operation (op0
);
4456 return simplify_gen_unary (NEG
, mode
,
4457 gen_lowpart_for_combine (mode
, op0
),
4461 else if (STORE_FLAG_VALUE
== 1
4462 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4463 && op1
== const0_rtx
4464 && mode
== GET_MODE (op0
)
4465 && nonzero_bits (op0
, mode
) == 1)
4467 op0
= expand_compound_operation (op0
);
4468 return gen_binary (XOR
, mode
,
4469 gen_lowpart_for_combine (mode
, op0
),
4473 else if (STORE_FLAG_VALUE
== 1
4474 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4475 && op1
== const0_rtx
4476 && mode
== GET_MODE (op0
)
4477 && (num_sign_bit_copies (op0
, mode
)
4478 == GET_MODE_BITSIZE (mode
)))
4480 op0
= expand_compound_operation (op0
);
4481 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
4484 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4486 if (STORE_FLAG_VALUE
== -1
4487 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4488 && op1
== const0_rtx
4489 && (num_sign_bit_copies (op0
, mode
)
4490 == GET_MODE_BITSIZE (mode
)))
4491 return gen_lowpart_for_combine (mode
,
4492 expand_compound_operation (op0
));
4494 else if (STORE_FLAG_VALUE
== -1
4495 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4496 && op1
== const0_rtx
4497 && mode
== GET_MODE (op0
)
4498 && nonzero_bits (op0
, mode
) == 1)
4500 op0
= expand_compound_operation (op0
);
4501 return simplify_gen_unary (NEG
, mode
,
4502 gen_lowpart_for_combine (mode
, op0
),
4506 else if (STORE_FLAG_VALUE
== -1
4507 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4508 && op1
== const0_rtx
4509 && mode
== GET_MODE (op0
)
4510 && (num_sign_bit_copies (op0
, mode
)
4511 == GET_MODE_BITSIZE (mode
)))
4513 op0
= expand_compound_operation (op0
);
4514 return simplify_gen_unary (NOT
, mode
,
4515 gen_lowpart_for_combine (mode
, op0
),
4519 /* If X is 0/1, (eq X 0) is X-1. */
4520 else if (STORE_FLAG_VALUE
== -1
4521 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4522 && op1
== const0_rtx
4523 && mode
== GET_MODE (op0
)
4524 && nonzero_bits (op0
, mode
) == 1)
4526 op0
= expand_compound_operation (op0
);
4527 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
4530 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4531 one bit that might be nonzero, we can convert (ne x 0) to
4532 (ashift x c) where C puts the bit in the sign bit. Remove any
4533 AND with STORE_FLAG_VALUE when we are done, since we are only
4534 going to test the sign bit. */
4535 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4536 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4537 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4538 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
4539 && op1
== const0_rtx
4540 && mode
== GET_MODE (op0
)
4541 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4543 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4544 expand_compound_operation (op0
),
4545 GET_MODE_BITSIZE (mode
) - 1 - i
);
4546 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4552 /* If the code changed, return a whole new comparison. */
4553 if (new_code
!= code
)
4554 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4556 /* Otherwise, keep this operation, but maybe change its operands.
4557 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4558 SUBST (XEXP (x
, 0), op0
);
4559 SUBST (XEXP (x
, 1), op1
);
4564 return simplify_if_then_else (x
);
4570 /* If we are processing SET_DEST, we are done. */
4574 return expand_compound_operation (x
);
4577 return simplify_set (x
);
4582 return simplify_logical (x
, last
);
4585 /* (abs (neg <foo>)) -> (abs <foo>) */
4586 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4587 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4589 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4591 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4594 /* If operand is something known to be positive, ignore the ABS. */
4595 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4596 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4597 <= HOST_BITS_PER_WIDE_INT
)
4598 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4599 & ((HOST_WIDE_INT
) 1
4600 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4604 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4605 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4606 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4611 /* (ffs (*_extend <X>)) = (ffs <X>) */
4612 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4613 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4614 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4619 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4620 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4621 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4625 /* (float (sign_extend <X>)) = (float <X>). */
4626 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4627 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4635 /* If this is a shift by a constant amount, simplify it. */
4636 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4637 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4638 INTVAL (XEXP (x
, 1)));
4640 #ifdef SHIFT_COUNT_TRUNCATED
4641 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4643 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
4645 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4654 rtx op0
= XEXP (x
, 0);
4655 rtx op1
= XEXP (x
, 1);
4658 if (GET_CODE (op1
) != PARALLEL
)
4660 len
= XVECLEN (op1
, 0);
4662 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4663 && GET_CODE (op0
) == VEC_CONCAT
)
4665 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4667 /* Try to find the element in the VEC_CONCAT. */
4670 if (GET_MODE (op0
) == GET_MODE (x
))
4672 if (GET_CODE (op0
) == VEC_CONCAT
)
4674 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4675 if (op0_size
< offset
)
4676 op0
= XEXP (op0
, 0);
4680 op0
= XEXP (op0
, 1);
4698 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4701 simplify_if_then_else (rtx x
)
4703 enum machine_mode mode
= GET_MODE (x
);
4704 rtx cond
= XEXP (x
, 0);
4705 rtx true_rtx
= XEXP (x
, 1);
4706 rtx false_rtx
= XEXP (x
, 2);
4707 enum rtx_code true_code
= GET_CODE (cond
);
4708 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4711 enum rtx_code false_code
;
4714 /* Simplify storing of the truth value. */
4715 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4716 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4718 /* Also when the truth value has to be reversed. */
4720 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4721 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4725 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4726 in it is being compared against certain values. Get the true and false
4727 comparisons and see if that says anything about the value of each arm. */
4730 && ((false_code
= combine_reversed_comparison_code (cond
))
4732 && GET_CODE (XEXP (cond
, 0)) == REG
)
4735 rtx from
= XEXP (cond
, 0);
4736 rtx true_val
= XEXP (cond
, 1);
4737 rtx false_val
= true_val
;
4740 /* If FALSE_CODE is EQ, swap the codes and arms. */
4742 if (false_code
== EQ
)
4744 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4745 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4748 /* If we are comparing against zero and the expression being tested has
4749 only a single bit that might be nonzero, that is its value when it is
4750 not equal to zero. Similarly if it is known to be -1 or 0. */
4752 if (true_code
== EQ
&& true_val
== const0_rtx
4753 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4754 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4755 else if (true_code
== EQ
&& true_val
== const0_rtx
4756 && (num_sign_bit_copies (from
, GET_MODE (from
))
4757 == GET_MODE_BITSIZE (GET_MODE (from
))))
4758 false_code
= EQ
, false_val
= constm1_rtx
;
4760 /* Now simplify an arm if we know the value of the register in the
4761 branch and it is used in the arm. Be careful due to the potential
4762 of locally-shared RTL. */
4764 if (reg_mentioned_p (from
, true_rtx
))
4765 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4767 pc_rtx
, pc_rtx
, 0, 0);
4768 if (reg_mentioned_p (from
, false_rtx
))
4769 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4771 pc_rtx
, pc_rtx
, 0, 0);
4773 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4774 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4776 true_rtx
= XEXP (x
, 1);
4777 false_rtx
= XEXP (x
, 2);
4778 true_code
= GET_CODE (cond
);
4781 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4782 reversed, do so to avoid needing two sets of patterns for
4783 subtract-and-branch insns. Similarly if we have a constant in the true
4784 arm, the false arm is the same as the first operand of the comparison, or
4785 the false arm is more complicated than the true arm. */
4788 && combine_reversed_comparison_code (cond
) != UNKNOWN
4789 && (true_rtx
== pc_rtx
4790 || (CONSTANT_P (true_rtx
)
4791 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4792 || true_rtx
== const0_rtx
4793 || (GET_RTX_CLASS (GET_CODE (true_rtx
)) == 'o'
4794 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4795 || (GET_CODE (true_rtx
) == SUBREG
4796 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx
))) == 'o'
4797 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4798 || reg_mentioned_p (true_rtx
, false_rtx
)
4799 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4801 true_code
= reversed_comparison_code (cond
, NULL
);
4803 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4806 SUBST (XEXP (x
, 1), false_rtx
);
4807 SUBST (XEXP (x
, 2), true_rtx
);
4809 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4812 /* It is possible that the conditional has been simplified out. */
4813 true_code
= GET_CODE (cond
);
4814 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4817 /* If the two arms are identical, we don't need the comparison. */
4819 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4822 /* Convert a == b ? b : a to "a". */
4823 if (true_code
== EQ
&& ! side_effects_p (cond
)
4824 && !HONOR_NANS (mode
)
4825 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4826 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4828 else if (true_code
== NE
&& ! side_effects_p (cond
)
4829 && !HONOR_NANS (mode
)
4830 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4831 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4834 /* Look for cases where we have (abs x) or (neg (abs X)). */
4836 if (GET_MODE_CLASS (mode
) == MODE_INT
4837 && GET_CODE (false_rtx
) == NEG
4838 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4840 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4841 && ! side_effects_p (true_rtx
))
4846 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4850 simplify_gen_unary (NEG
, mode
,
4851 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4857 /* Look for MIN or MAX. */
4859 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4861 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4862 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4863 && ! side_effects_p (cond
))
4868 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4871 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4874 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4877 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4882 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4883 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4884 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4885 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4886 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4887 neither 1 or -1, but it isn't worth checking for. */
4889 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4891 && GET_MODE_CLASS (mode
) == MODE_INT
4892 && ! side_effects_p (x
))
4894 rtx t
= make_compound_operation (true_rtx
, SET
);
4895 rtx f
= make_compound_operation (false_rtx
, SET
);
4896 rtx cond_op0
= XEXP (cond
, 0);
4897 rtx cond_op1
= XEXP (cond
, 1);
4898 enum rtx_code op
= NIL
, extend_op
= NIL
;
4899 enum machine_mode m
= mode
;
4900 rtx z
= 0, c1
= NULL_RTX
;
4902 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4903 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4904 || GET_CODE (t
) == ASHIFT
4905 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4906 && rtx_equal_p (XEXP (t
, 0), f
))
4907 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4909 /* If an identity-zero op is commutative, check whether there
4910 would be a match if we swapped the operands. */
4911 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4912 || GET_CODE (t
) == XOR
)
4913 && rtx_equal_p (XEXP (t
, 1), f
))
4914 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4915 else if (GET_CODE (t
) == SIGN_EXTEND
4916 && (GET_CODE (XEXP (t
, 0)) == PLUS
4917 || GET_CODE (XEXP (t
, 0)) == MINUS
4918 || GET_CODE (XEXP (t
, 0)) == IOR
4919 || GET_CODE (XEXP (t
, 0)) == XOR
4920 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4921 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4922 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4923 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4924 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4925 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4926 && (num_sign_bit_copies (f
, GET_MODE (f
))
4928 (GET_MODE_BITSIZE (mode
)
4929 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4931 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4932 extend_op
= SIGN_EXTEND
;
4933 m
= GET_MODE (XEXP (t
, 0));
4935 else if (GET_CODE (t
) == SIGN_EXTEND
4936 && (GET_CODE (XEXP (t
, 0)) == PLUS
4937 || GET_CODE (XEXP (t
, 0)) == IOR
4938 || GET_CODE (XEXP (t
, 0)) == XOR
)
4939 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4940 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4941 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4942 && (num_sign_bit_copies (f
, GET_MODE (f
))
4944 (GET_MODE_BITSIZE (mode
)
4945 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4947 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4948 extend_op
= SIGN_EXTEND
;
4949 m
= GET_MODE (XEXP (t
, 0));
4951 else if (GET_CODE (t
) == ZERO_EXTEND
4952 && (GET_CODE (XEXP (t
, 0)) == PLUS
4953 || GET_CODE (XEXP (t
, 0)) == MINUS
4954 || GET_CODE (XEXP (t
, 0)) == IOR
4955 || GET_CODE (XEXP (t
, 0)) == XOR
4956 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4957 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4958 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4959 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4960 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4961 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4962 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4963 && ((nonzero_bits (f
, GET_MODE (f
))
4964 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4967 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4968 extend_op
= ZERO_EXTEND
;
4969 m
= GET_MODE (XEXP (t
, 0));
4971 else if (GET_CODE (t
) == ZERO_EXTEND
4972 && (GET_CODE (XEXP (t
, 0)) == PLUS
4973 || GET_CODE (XEXP (t
, 0)) == IOR
4974 || GET_CODE (XEXP (t
, 0)) == XOR
)
4975 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4976 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4977 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4978 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4979 && ((nonzero_bits (f
, GET_MODE (f
))
4980 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4983 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4984 extend_op
= ZERO_EXTEND
;
4985 m
= GET_MODE (XEXP (t
, 0));
4990 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4991 pc_rtx
, pc_rtx
, 0, 0);
4992 temp
= gen_binary (MULT
, m
, temp
,
4993 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4994 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4995 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
4997 if (extend_op
!= NIL
)
4998 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
5004 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5005 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5006 negation of a single bit, we can convert this operation to a shift. We
5007 can actually do this more generally, but it doesn't seem worth it. */
5009 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5010 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
5011 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
5012 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
5013 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
5014 == GET_MODE_BITSIZE (mode
))
5015 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
5017 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5018 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
5020 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5021 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5022 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
5023 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
5024 == nonzero_bits (XEXP (cond
, 0), mode
)
5025 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
5026 return XEXP (cond
, 0);
5031 /* Simplify X, a SET expression. Return the new expression. */
5034 simplify_set (rtx x
)
5036 rtx src
= SET_SRC (x
);
5037 rtx dest
= SET_DEST (x
);
5038 enum machine_mode mode
5039 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
5043 /* (set (pc) (return)) gets written as (return). */
5044 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
5047 /* Now that we know for sure which bits of SRC we are using, see if we can
5048 simplify the expression for the object knowing that we only need the
5051 if (GET_MODE_CLASS (mode
) == MODE_INT
5052 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
5054 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
5055 SUBST (SET_SRC (x
), src
);
5058 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5059 the comparison result and try to simplify it unless we already have used
5060 undobuf.other_insn. */
5061 if ((GET_MODE_CLASS (mode
) == MODE_CC
5062 || GET_CODE (src
) == COMPARE
5064 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
5065 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
5066 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
5067 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
5069 enum rtx_code old_code
= GET_CODE (*cc_use
);
5070 enum rtx_code new_code
;
5072 int other_changed
= 0;
5073 enum machine_mode compare_mode
= GET_MODE (dest
);
5074 enum machine_mode tmp_mode
;
5076 if (GET_CODE (src
) == COMPARE
)
5077 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
5079 op0
= src
, op1
= const0_rtx
;
5081 /* Check whether the comparison is known at compile time. */
5082 if (GET_MODE (op0
) != VOIDmode
)
5083 tmp_mode
= GET_MODE (op0
);
5084 else if (GET_MODE (op1
) != VOIDmode
)
5085 tmp_mode
= GET_MODE (op1
);
5087 tmp_mode
= compare_mode
;
5088 tmp
= simplify_relational_operation (old_code
, tmp_mode
, op0
, op1
);
5089 if (tmp
!= NULL_RTX
)
5091 rtx pat
= PATTERN (other_insn
);
5092 undobuf
.other_insn
= other_insn
;
5093 SUBST (*cc_use
, tmp
);
5095 /* Attempt to simplify CC user. */
5096 if (GET_CODE (pat
) == SET
)
5098 rtx
new = simplify_rtx (SET_SRC (pat
));
5099 if (new != NULL_RTX
)
5100 SUBST (SET_SRC (pat
), new);
5103 /* Convert X into a no-op move. */
5104 SUBST (SET_DEST (x
), pc_rtx
);
5105 SUBST (SET_SRC (x
), pc_rtx
);
5109 /* Simplify our comparison, if possible. */
5110 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
5112 #ifdef EXTRA_CC_MODES
5113 /* If this machine has CC modes other than CCmode, check to see if we
5114 need to use a different CC mode here. */
5115 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5116 #endif /* EXTRA_CC_MODES */
5118 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5119 /* If the mode changed, we have to change SET_DEST, the mode in the
5120 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5121 a hard register, just build new versions with the proper mode. If it
5122 is a pseudo, we lose unless it is only time we set the pseudo, in
5123 which case we can safely change its mode. */
5124 if (compare_mode
!= GET_MODE (dest
))
5126 unsigned int regno
= REGNO (dest
);
5127 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5129 if (regno
< FIRST_PSEUDO_REGISTER
5130 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5132 if (regno
>= FIRST_PSEUDO_REGISTER
)
5133 SUBST (regno_reg_rtx
[regno
], new_dest
);
5135 SUBST (SET_DEST (x
), new_dest
);
5136 SUBST (XEXP (*cc_use
, 0), new_dest
);
5144 /* If the code changed, we have to build a new comparison in
5145 undobuf.other_insn. */
5146 if (new_code
!= old_code
)
5148 unsigned HOST_WIDE_INT mask
;
5150 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5153 /* If the only change we made was to change an EQ into an NE or
5154 vice versa, OP0 has only one bit that might be nonzero, and OP1
5155 is zero, check if changing the user of the condition code will
5156 produce a valid insn. If it won't, we can keep the original code
5157 in that insn by surrounding our operation with an XOR. */
5159 if (((old_code
== NE
&& new_code
== EQ
)
5160 || (old_code
== EQ
&& new_code
== NE
))
5161 && ! other_changed
&& op1
== const0_rtx
5162 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5163 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5165 rtx pat
= PATTERN (other_insn
), note
= 0;
5167 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5168 && ! check_asm_operands (pat
)))
5170 PUT_CODE (*cc_use
, old_code
);
5173 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
5181 undobuf
.other_insn
= other_insn
;
5184 /* If we are now comparing against zero, change our source if
5185 needed. If we do not use cc0, we always have a COMPARE. */
5186 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5188 SUBST (SET_SRC (x
), op0
);
5194 /* Otherwise, if we didn't previously have a COMPARE in the
5195 correct mode, we need one. */
5196 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5198 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5203 /* Otherwise, update the COMPARE if needed. */
5204 SUBST (XEXP (src
, 0), op0
);
5205 SUBST (XEXP (src
, 1), op1
);
5210 /* Get SET_SRC in a form where we have placed back any
5211 compound expressions. Then do the checks below. */
5212 src
= make_compound_operation (src
, SET
);
5213 SUBST (SET_SRC (x
), src
);
5216 #ifdef WORD_REGISTER_OPERATIONS
5217 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5218 and X being a REG or (subreg (reg)), we may be able to convert this to
5219 (set (subreg:m2 x) (op)).
5221 On a machine where WORD_REGISTER_OPERATIONS is defined, this
5222 transformation is safe as long as M1 and M2 have the same number
5225 However, on a machine without WORD_REGISTER_OPERATIONS defined,
5226 we cannot apply this transformation because it would create a
5227 paradoxical subreg in SET_DEST. */
5229 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5230 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
5231 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5233 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5234 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5235 #ifdef CANNOT_CHANGE_MODE_CLASS
5236 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5237 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5238 GET_MODE (SUBREG_REG (src
)),
5241 && (GET_CODE (dest
) == REG
5242 || (GET_CODE (dest
) == SUBREG
5243 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5245 SUBST (SET_DEST (x
),
5246 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
5248 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5250 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5255 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5258 && GET_CODE (src
) == SUBREG
5259 && subreg_lowpart_p (src
)
5260 && (GET_MODE_BITSIZE (GET_MODE (src
))
5261 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5263 rtx inner
= SUBREG_REG (src
);
5264 enum machine_mode inner_mode
= GET_MODE (inner
);
5266 /* Here we make sure that we don't have a sign bit on. */
5267 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5268 && (nonzero_bits (inner
, inner_mode
)
5269 < ((unsigned HOST_WIDE_INT
) 1
5270 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5272 SUBST (SET_SRC (x
), inner
);
5278 #ifdef LOAD_EXTEND_OP
5279 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5280 would require a paradoxical subreg. Replace the subreg with a
5281 zero_extend to avoid the reload that would otherwise be required. */
5283 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5284 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5285 && SUBREG_BYTE (src
) == 0
5286 && (GET_MODE_SIZE (GET_MODE (src
))
5287 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5288 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5291 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5292 GET_MODE (src
), SUBREG_REG (src
)));
5298 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5299 are comparing an item known to be 0 or -1 against 0, use a logical
5300 operation instead. Check for one of the arms being an IOR of the other
5301 arm with some value. We compute three terms to be IOR'ed together. In
5302 practice, at most two will be nonzero. Then we do the IOR's. */
5304 if (GET_CODE (dest
) != PC
5305 && GET_CODE (src
) == IF_THEN_ELSE
5306 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5307 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5308 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5309 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5310 #ifdef HAVE_conditional_move
5311 && ! can_conditionally_move_p (GET_MODE (src
))
5313 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5314 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5315 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5316 && ! side_effects_p (src
))
5318 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5319 ? XEXP (src
, 1) : XEXP (src
, 2));
5320 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5321 ? XEXP (src
, 2) : XEXP (src
, 1));
5322 rtx term1
= const0_rtx
, term2
, term3
;
5324 if (GET_CODE (true_rtx
) == IOR
5325 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5326 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
5327 else if (GET_CODE (true_rtx
) == IOR
5328 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5329 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
5330 else if (GET_CODE (false_rtx
) == IOR
5331 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5332 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
5333 else if (GET_CODE (false_rtx
) == IOR
5334 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5335 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
5337 term2
= gen_binary (AND
, GET_MODE (src
),
5338 XEXP (XEXP (src
, 0), 0), true_rtx
);
5339 term3
= gen_binary (AND
, GET_MODE (src
),
5340 simplify_gen_unary (NOT
, GET_MODE (src
),
5341 XEXP (XEXP (src
, 0), 0),
5346 gen_binary (IOR
, GET_MODE (src
),
5347 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5353 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5354 whole thing fail. */
5355 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5357 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5360 /* Convert this into a field assignment operation, if possible. */
5361 return make_field_assignment (x
);
5364 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5365 result. LAST is nonzero if this is the last retry. */
5368 simplify_logical (rtx x
, int last
)
5370 enum machine_mode mode
= GET_MODE (x
);
5371 rtx op0
= XEXP (x
, 0);
5372 rtx op1
= XEXP (x
, 1);
5375 switch (GET_CODE (x
))
5378 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5379 insn (and may simplify more). */
5380 if (GET_CODE (op0
) == XOR
5381 && rtx_equal_p (XEXP (op0
, 0), op1
)
5382 && ! side_effects_p (op1
))
5383 x
= gen_binary (AND
, mode
,
5384 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5387 if (GET_CODE (op0
) == XOR
5388 && rtx_equal_p (XEXP (op0
, 1), op1
)
5389 && ! side_effects_p (op1
))
5390 x
= gen_binary (AND
, mode
,
5391 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5394 /* Similarly for (~(A ^ B)) & A. */
5395 if (GET_CODE (op0
) == NOT
5396 && GET_CODE (XEXP (op0
, 0)) == XOR
5397 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5398 && ! side_effects_p (op1
))
5399 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5401 if (GET_CODE (op0
) == NOT
5402 && GET_CODE (XEXP (op0
, 0)) == XOR
5403 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5404 && ! side_effects_p (op1
))
5405 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5407 /* We can call simplify_and_const_int only if we don't lose
5408 any (sign) bits when converting INTVAL (op1) to
5409 "unsigned HOST_WIDE_INT". */
5410 if (GET_CODE (op1
) == CONST_INT
5411 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5412 || INTVAL (op1
) > 0))
5414 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5416 /* If we have (ior (and (X C1) C2)) and the next restart would be
5417 the last, simplify this by making C1 as small as possible
5420 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5421 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5422 && GET_CODE (op1
) == CONST_INT
)
5423 return gen_binary (IOR
, mode
,
5424 gen_binary (AND
, mode
, XEXP (op0
, 0),
5425 GEN_INT (INTVAL (XEXP (op0
, 1))
5426 & ~INTVAL (op1
))), op1
);
5428 if (GET_CODE (x
) != AND
)
5431 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5432 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5433 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5436 /* Convert (A | B) & A to A. */
5437 if (GET_CODE (op0
) == IOR
5438 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5439 || rtx_equal_p (XEXP (op0
, 1), op1
))
5440 && ! side_effects_p (XEXP (op0
, 0))
5441 && ! side_effects_p (XEXP (op0
, 1)))
5444 /* In the following group of tests (and those in case IOR below),
5445 we start with some combination of logical operations and apply
5446 the distributive law followed by the inverse distributive law.
5447 Most of the time, this results in no change. However, if some of
5448 the operands are the same or inverses of each other, simplifications
5451 For example, (and (ior A B) (not B)) can occur as the result of
5452 expanding a bit field assignment. When we apply the distributive
5453 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5454 which then simplifies to (and (A (not B))).
5456 If we have (and (ior A B) C), apply the distributive law and then
5457 the inverse distributive law to see if things simplify. */
5459 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5461 x
= apply_distributive_law
5462 (gen_binary (GET_CODE (op0
), mode
,
5463 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5464 gen_binary (AND
, mode
, XEXP (op0
, 1),
5466 if (GET_CODE (x
) != AND
)
5470 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5471 return apply_distributive_law
5472 (gen_binary (GET_CODE (op1
), mode
,
5473 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5474 gen_binary (AND
, mode
, XEXP (op1
, 1),
5477 /* Similarly, taking advantage of the fact that
5478 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5480 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5481 return apply_distributive_law
5482 (gen_binary (XOR
, mode
,
5483 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5484 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5487 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5488 return apply_distributive_law
5489 (gen_binary (XOR
, mode
,
5490 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5491 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5495 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5496 if (GET_CODE (op1
) == CONST_INT
5497 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5498 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5501 /* Convert (A & B) | A to A. */
5502 if (GET_CODE (op0
) == AND
5503 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5504 || rtx_equal_p (XEXP (op0
, 1), op1
))
5505 && ! side_effects_p (XEXP (op0
, 0))
5506 && ! side_effects_p (XEXP (op0
, 1)))
5509 /* If we have (ior (and A B) C), apply the distributive law and then
5510 the inverse distributive law to see if things simplify. */
5512 if (GET_CODE (op0
) == AND
)
5514 x
= apply_distributive_law
5515 (gen_binary (AND
, mode
,
5516 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5517 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5520 if (GET_CODE (x
) != IOR
)
5524 if (GET_CODE (op1
) == AND
)
5526 x
= apply_distributive_law
5527 (gen_binary (AND
, mode
,
5528 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5529 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5532 if (GET_CODE (x
) != IOR
)
5536 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5537 mode size to (rotate A CX). */
5539 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5540 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5541 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5542 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5543 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5544 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5545 == GET_MODE_BITSIZE (mode
)))
5546 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5547 (GET_CODE (op0
) == ASHIFT
5548 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5550 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5551 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5552 does not affect any of the bits in OP1, it can really be done
5553 as a PLUS and we can associate. We do this by seeing if OP1
5554 can be safely shifted left C bits. */
5555 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5556 && GET_CODE (XEXP (op0
, 0)) == PLUS
5557 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5558 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5559 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5561 int count
= INTVAL (XEXP (op0
, 1));
5562 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5564 if (mask
>> count
== INTVAL (op1
)
5565 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5567 SUBST (XEXP (XEXP (op0
, 0), 1),
5568 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5575 /* If we are XORing two things that have no bits in common,
5576 convert them into an IOR. This helps to detect rotation encoded
5577 using those methods and possibly other simplifications. */
5579 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5580 && (nonzero_bits (op0
, mode
)
5581 & nonzero_bits (op1
, mode
)) == 0)
5582 return (gen_binary (IOR
, mode
, op0
, op1
));
5584 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5585 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5588 int num_negated
= 0;
5590 if (GET_CODE (op0
) == NOT
)
5591 num_negated
++, op0
= XEXP (op0
, 0);
5592 if (GET_CODE (op1
) == NOT
)
5593 num_negated
++, op1
= XEXP (op1
, 0);
5595 if (num_negated
== 2)
5597 SUBST (XEXP (x
, 0), op0
);
5598 SUBST (XEXP (x
, 1), op1
);
5600 else if (num_negated
== 1)
5602 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5606 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5607 correspond to a machine insn or result in further simplifications
5608 if B is a constant. */
5610 if (GET_CODE (op0
) == AND
5611 && rtx_equal_p (XEXP (op0
, 1), op1
)
5612 && ! side_effects_p (op1
))
5613 return gen_binary (AND
, mode
,
5614 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5617 else if (GET_CODE (op0
) == AND
5618 && rtx_equal_p (XEXP (op0
, 0), op1
)
5619 && ! side_effects_p (op1
))
5620 return gen_binary (AND
, mode
,
5621 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5624 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5625 comparison if STORE_FLAG_VALUE is 1. */
5626 if (STORE_FLAG_VALUE
== 1
5627 && op1
== const1_rtx
5628 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5629 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5633 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5634 is (lt foo (const_int 0)), so we can perform the above
5635 simplification if STORE_FLAG_VALUE is 1. */
5637 if (STORE_FLAG_VALUE
== 1
5638 && op1
== const1_rtx
5639 && GET_CODE (op0
) == LSHIFTRT
5640 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5641 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5642 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5644 /* (xor (comparison foo bar) (const_int sign-bit))
5645 when STORE_FLAG_VALUE is the sign bit. */
5646 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5647 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5648 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5649 && op1
== const_true_rtx
5650 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5651 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5664 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5665 operations" because they can be replaced with two more basic operations.
5666 ZERO_EXTEND is also considered "compound" because it can be replaced with
5667 an AND operation, which is simpler, though only one operation.
5669 The function expand_compound_operation is called with an rtx expression
5670 and will convert it to the appropriate shifts and AND operations,
5671 simplifying at each stage.
5673 The function make_compound_operation is called to convert an expression
5674 consisting of shifts and ANDs into the equivalent compound expression.
5675 It is the inverse of this function, loosely speaking. */
5678 expand_compound_operation (rtx x
)
5680 unsigned HOST_WIDE_INT pos
= 0, len
;
5682 unsigned int modewidth
;
5685 switch (GET_CODE (x
))
5690 /* We can't necessarily use a const_int for a multiword mode;
5691 it depends on implicitly extending the value.
5692 Since we don't know the right way to extend it,
5693 we can't tell whether the implicit way is right.
5695 Even for a mode that is no wider than a const_int,
5696 we can't win, because we need to sign extend one of its bits through
5697 the rest of it, and we don't know which bit. */
5698 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5701 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5702 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5703 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5704 reloaded. If not for that, MEM's would very rarely be safe.
5706 Reject MODEs bigger than a word, because we might not be able
5707 to reference a two-register group starting with an arbitrary register
5708 (and currently gen_lowpart might crash for a SUBREG). */
5710 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5713 /* Reject MODEs that aren't scalar integers because turning vector
5714 or complex modes into shifts causes problems. */
5716 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5719 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5720 /* If the inner object has VOIDmode (the only way this can happen
5721 is if it is an ASM_OPERANDS), we can't do anything since we don't
5722 know how much masking to do. */
5731 /* If the operand is a CLOBBER, just return it. */
5732 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5735 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5736 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5737 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5740 /* Reject MODEs that aren't scalar integers because turning vector
5741 or complex modes into shifts causes problems. */
5743 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5746 len
= INTVAL (XEXP (x
, 1));
5747 pos
= INTVAL (XEXP (x
, 2));
5749 /* If this goes outside the object being extracted, replace the object
5750 with a (use (mem ...)) construct that only combine understands
5751 and is used only for this purpose. */
5752 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5753 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5755 if (BITS_BIG_ENDIAN
)
5756 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5763 /* Convert sign extension to zero extension, if we know that the high
5764 bit is not set, as this is easier to optimize. It will be converted
5765 back to cheaper alternative in make_extraction. */
5766 if (GET_CODE (x
) == SIGN_EXTEND
5767 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5768 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5769 & ~(((unsigned HOST_WIDE_INT
)
5770 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5774 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5775 rtx temp2
= expand_compound_operation (temp
);
5777 /* Make sure this is a profitable operation. */
5778 if (rtx_cost (x
, SET
) > rtx_cost (temp2
, SET
))
5780 else if (rtx_cost (x
, SET
) > rtx_cost (temp
, SET
))
5786 /* We can optimize some special cases of ZERO_EXTEND. */
5787 if (GET_CODE (x
) == ZERO_EXTEND
)
5789 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5790 know that the last value didn't have any inappropriate bits
5792 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5793 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5794 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5795 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5796 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5797 return XEXP (XEXP (x
, 0), 0);
5799 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5800 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5801 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5802 && subreg_lowpart_p (XEXP (x
, 0))
5803 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5804 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5805 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5806 return SUBREG_REG (XEXP (x
, 0));
5808 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5809 is a comparison and STORE_FLAG_VALUE permits. This is like
5810 the first case, but it works even when GET_MODE (x) is larger
5811 than HOST_WIDE_INT. */
5812 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5813 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5814 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5815 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5816 <= HOST_BITS_PER_WIDE_INT
)
5817 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5818 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5819 return XEXP (XEXP (x
, 0), 0);
5821 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5822 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5823 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5824 && subreg_lowpart_p (XEXP (x
, 0))
5825 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5826 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5827 <= HOST_BITS_PER_WIDE_INT
)
5828 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5829 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5830 return SUBREG_REG (XEXP (x
, 0));
5834 /* If we reach here, we want to return a pair of shifts. The inner
5835 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5836 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5837 logical depending on the value of UNSIGNEDP.
5839 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5840 converted into an AND of a shift.
5842 We must check for the case where the left shift would have a negative
5843 count. This can happen in a case like (x >> 31) & 255 on machines
5844 that can't shift by a constant. On those machines, we would first
5845 combine the shift with the AND to produce a variable-position
5846 extraction. Then the constant of 31 would be substituted in to produce
5847 a such a position. */
5849 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5850 if (modewidth
+ len
>= pos
)
5851 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5853 simplify_shift_const (NULL_RTX
, ASHIFT
,
5856 modewidth
- pos
- len
),
5859 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5860 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5861 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5864 ((HOST_WIDE_INT
) 1 << len
) - 1);
5866 /* Any other cases we can't handle. */
5869 /* If we couldn't do this for some reason, return the original
5871 if (GET_CODE (tem
) == CLOBBER
)
5877 /* X is a SET which contains an assignment of one object into
5878 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5879 or certain SUBREGS). If possible, convert it into a series of
5882 We half-heartedly support variable positions, but do not at all
5883 support variable lengths. */
5886 expand_field_assignment (rtx x
)
5889 rtx pos
; /* Always counts from low bit. */
5892 enum machine_mode compute_mode
;
5894 /* Loop until we find something we can't simplify. */
5897 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5898 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5900 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5901 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5902 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
5904 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5905 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5907 inner
= XEXP (SET_DEST (x
), 0);
5908 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5909 pos
= XEXP (SET_DEST (x
), 2);
5911 /* If the position is constant and spans the width of INNER,
5912 surround INNER with a USE to indicate this. */
5913 if (GET_CODE (pos
) == CONST_INT
5914 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5915 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5917 if (BITS_BIG_ENDIAN
)
5919 if (GET_CODE (pos
) == CONST_INT
)
5920 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5922 else if (GET_CODE (pos
) == MINUS
5923 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5924 && (INTVAL (XEXP (pos
, 1))
5925 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5926 /* If position is ADJUST - X, new position is X. */
5927 pos
= XEXP (pos
, 0);
5929 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5930 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5936 /* A SUBREG between two modes that occupy the same numbers of words
5937 can be done by moving the SUBREG to the source. */
5938 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5939 /* We need SUBREGs to compute nonzero_bits properly. */
5940 && nonzero_sign_valid
5941 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5942 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5943 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5944 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5946 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5947 gen_lowpart_for_combine
5948 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5955 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5956 inner
= SUBREG_REG (inner
);
5958 compute_mode
= GET_MODE (inner
);
5960 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5961 if (! SCALAR_INT_MODE_P (compute_mode
))
5963 enum machine_mode imode
;
5965 /* Don't do anything for vector or complex integral types. */
5966 if (! FLOAT_MODE_P (compute_mode
))
5969 /* Try to find an integral mode to pun with. */
5970 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5971 if (imode
== BLKmode
)
5974 compute_mode
= imode
;
5975 inner
= gen_lowpart_for_combine (imode
, inner
);
5978 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5979 if (len
< HOST_BITS_PER_WIDE_INT
)
5980 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5984 /* Now compute the equivalent expression. Make a copy of INNER
5985 for the SET_DEST in case it is a MEM into which we will substitute;
5986 we don't want shared RTL in that case. */
5988 (VOIDmode
, copy_rtx (inner
),
5989 gen_binary (IOR
, compute_mode
,
5990 gen_binary (AND
, compute_mode
,
5991 simplify_gen_unary (NOT
, compute_mode
,
5997 gen_binary (ASHIFT
, compute_mode
,
5998 gen_binary (AND
, compute_mode
,
5999 gen_lowpart_for_combine
6000 (compute_mode
, SET_SRC (x
)),
6008 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6009 it is an RTX that represents a variable starting position; otherwise,
6010 POS is the (constant) starting bit position (counted from the LSB).
6012 INNER may be a USE. This will occur when we started with a bitfield
6013 that went outside the boundary of the object in memory, which is
6014 allowed on most machines. To isolate this case, we produce a USE
6015 whose mode is wide enough and surround the MEM with it. The only
6016 code that understands the USE is this routine. If it is not removed,
6017 it will cause the resulting insn not to match.
6019 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6022 IN_DEST is nonzero if this is a reference in the destination of a
6023 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6024 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6027 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6028 ZERO_EXTRACT should be built even for bits starting at bit 0.
6030 MODE is the desired mode of the result (if IN_DEST == 0).
6032 The result is an RTX for the extraction or NULL_RTX if the target
6036 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
6037 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
6038 int in_dest
, int in_compare
)
6040 /* This mode describes the size of the storage area
6041 to fetch the overall value from. Within that, we
6042 ignore the POS lowest bits, etc. */
6043 enum machine_mode is_mode
= GET_MODE (inner
);
6044 enum machine_mode inner_mode
;
6045 enum machine_mode wanted_inner_mode
= byte_mode
;
6046 enum machine_mode wanted_inner_reg_mode
= word_mode
;
6047 enum machine_mode pos_mode
= word_mode
;
6048 enum machine_mode extraction_mode
= word_mode
;
6049 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
6052 rtx orig_pos_rtx
= pos_rtx
;
6053 HOST_WIDE_INT orig_pos
;
6055 /* Get some information about INNER and get the innermost object. */
6056 if (GET_CODE (inner
) == USE
)
6057 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6058 /* We don't need to adjust the position because we set up the USE
6059 to pretend that it was a full-word object. */
6060 spans_byte
= 1, inner
= XEXP (inner
, 0);
6061 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6063 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6064 consider just the QI as the memory to extract from.
6065 The subreg adds or removes high bits; its mode is
6066 irrelevant to the meaning of this extraction,
6067 since POS and LEN count from the lsb. */
6068 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
6069 is_mode
= GET_MODE (SUBREG_REG (inner
));
6070 inner
= SUBREG_REG (inner
);
6072 else if (GET_CODE (inner
) == ASHIFT
6073 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
6074 && pos_rtx
== 0 && pos
== 0
6075 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
6077 /* We're extracting the least significant bits of an rtx
6078 (ashift X (const_int C)), where LEN > C. Extract the
6079 least significant (LEN - C) bits of X, giving an rtx
6080 whose mode is MODE, then shift it left C times. */
6081 new = make_extraction (mode
, XEXP (inner
, 0),
6082 0, 0, len
- INTVAL (XEXP (inner
, 1)),
6083 unsignedp
, in_dest
, in_compare
);
6085 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
6088 inner_mode
= GET_MODE (inner
);
6090 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
6091 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6093 /* See if this can be done without an extraction. We never can if the
6094 width of the field is not the same as that of some integer mode. For
6095 registers, we can only avoid the extraction if the position is at the
6096 low-order bit and this is either not in the destination or we have the
6097 appropriate STRICT_LOW_PART operation available.
6099 For MEM, we can avoid an extract if the field starts on an appropriate
6100 boundary and we can change the mode of the memory reference. However,
6101 we cannot directly access the MEM if we have a USE and the underlying
6102 MEM is not TMODE. This combination means that MEM was being used in a
6103 context where bits outside its mode were being referenced; that is only
6104 valid in bit-field insns. */
6106 if (tmode
!= BLKmode
6107 && ! (spans_byte
&& inner_mode
!= tmode
)
6108 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6109 && GET_CODE (inner
) != MEM
6111 || (GET_CODE (inner
) == REG
6112 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6113 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
6115 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6116 : BITS_PER_UNIT
)) == 0
6117 /* We can't do this if we are widening INNER_MODE (it
6118 may not be aligned, for one thing). */
6119 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6120 && (inner_mode
== tmode
6121 || (! mode_dependent_address_p (XEXP (inner
, 0))
6122 && ! MEM_VOLATILE_P (inner
))))))
6124 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6125 field. If the original and current mode are the same, we need not
6126 adjust the offset. Otherwise, we do if bytes big endian.
6128 If INNER is not a MEM, get a piece consisting of just the field
6129 of interest (in this case POS % BITS_PER_WORD must be 0). */
6131 if (GET_CODE (inner
) == MEM
)
6133 HOST_WIDE_INT offset
;
6135 /* POS counts from lsb, but make OFFSET count in memory order. */
6136 if (BYTES_BIG_ENDIAN
)
6137 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6139 offset
= pos
/ BITS_PER_UNIT
;
6141 new = adjust_address_nv (inner
, tmode
, offset
);
6143 else if (GET_CODE (inner
) == REG
)
6145 if (tmode
!= inner_mode
)
6149 /* We can't call gen_lowpart_for_combine here since we always want
6150 a SUBREG and it would sometimes return a new hard register. */
6151 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6153 if (WORDS_BIG_ENDIAN
6154 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6155 final_word
= ((GET_MODE_SIZE (inner_mode
)
6156 - GET_MODE_SIZE (tmode
))
6157 / UNITS_PER_WORD
) - final_word
;
6159 final_word
*= UNITS_PER_WORD
;
6160 if (BYTES_BIG_ENDIAN
&&
6161 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6162 final_word
+= (GET_MODE_SIZE (inner_mode
)
6163 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6165 /* Avoid creating invalid subregs, for example when
6166 simplifying (x>>32)&255. */
6167 if (final_word
>= GET_MODE_SIZE (inner_mode
))
6170 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6173 new = gen_lowpart_for_combine (tmode
, inner
);
6179 new = force_to_mode (inner
, tmode
,
6180 len
>= HOST_BITS_PER_WIDE_INT
6181 ? ~(unsigned HOST_WIDE_INT
) 0
6182 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6185 /* If this extraction is going into the destination of a SET,
6186 make a STRICT_LOW_PART unless we made a MEM. */
6189 return (GET_CODE (new) == MEM
? new
6190 : (GET_CODE (new) != SUBREG
6191 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6192 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6197 if (GET_CODE (new) == CONST_INT
)
6198 return gen_int_mode (INTVAL (new), mode
);
6200 /* If we know that no extraneous bits are set, and that the high
6201 bit is not set, convert the extraction to the cheaper of
6202 sign and zero extension, that are equivalent in these cases. */
6203 if (flag_expensive_optimizations
6204 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6205 && ((nonzero_bits (new, tmode
)
6206 & ~(((unsigned HOST_WIDE_INT
)
6207 GET_MODE_MASK (tmode
))
6211 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6212 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6214 /* Prefer ZERO_EXTENSION, since it gives more information to
6216 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6221 /* Otherwise, sign- or zero-extend unless we already are in the
6224 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6228 /* Unless this is a COMPARE or we have a funny memory reference,
6229 don't do anything with zero-extending field extracts starting at
6230 the low-order bit since they are simple AND operations. */
6231 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6232 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6235 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6236 we would be spanning bytes or if the position is not a constant and the
6237 length is not 1. In all other cases, we would only be going outside
6238 our object in cases when an original shift would have been
6240 if (! spans_byte
&& GET_CODE (inner
) == MEM
6241 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6242 || (pos_rtx
!= 0 && len
!= 1)))
6245 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6246 and the mode for the result. */
6247 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6249 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6250 pos_mode
= mode_for_extraction (EP_insv
, 2);
6251 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6254 if (! in_dest
&& unsignedp
6255 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6257 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6258 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6259 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6262 if (! in_dest
&& ! unsignedp
6263 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6265 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6266 pos_mode
= mode_for_extraction (EP_extv
, 3);
6267 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6270 /* Never narrow an object, since that might not be safe. */
6272 if (mode
!= VOIDmode
6273 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6274 extraction_mode
= mode
;
6276 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6277 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6278 pos_mode
= GET_MODE (pos_rtx
);
6280 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6281 if we have to change the mode of memory and cannot, the desired mode is
6283 if (GET_CODE (inner
) != MEM
)
6284 wanted_inner_mode
= wanted_inner_reg_mode
;
6285 else if (inner_mode
!= wanted_inner_mode
6286 && (mode_dependent_address_p (XEXP (inner
, 0))
6287 || MEM_VOLATILE_P (inner
)))
6288 wanted_inner_mode
= extraction_mode
;
6292 if (BITS_BIG_ENDIAN
)
6294 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6295 BITS_BIG_ENDIAN style. If position is constant, compute new
6296 position. Otherwise, build subtraction.
6297 Note that POS is relative to the mode of the original argument.
6298 If it's a MEM we need to recompute POS relative to that.
6299 However, if we're extracting from (or inserting into) a register,
6300 we want to recompute POS relative to wanted_inner_mode. */
6301 int width
= (GET_CODE (inner
) == MEM
6302 ? GET_MODE_BITSIZE (is_mode
)
6303 : GET_MODE_BITSIZE (wanted_inner_mode
));
6306 pos
= width
- len
- pos
;
6309 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6310 /* POS may be less than 0 now, but we check for that below.
6311 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6314 /* If INNER has a wider mode, make it smaller. If this is a constant
6315 extract, try to adjust the byte to point to the byte containing
6317 if (wanted_inner_mode
!= VOIDmode
6318 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6319 && ((GET_CODE (inner
) == MEM
6320 && (inner_mode
== wanted_inner_mode
6321 || (! mode_dependent_address_p (XEXP (inner
, 0))
6322 && ! MEM_VOLATILE_P (inner
))))))
6326 /* The computations below will be correct if the machine is big
6327 endian in both bits and bytes or little endian in bits and bytes.
6328 If it is mixed, we must adjust. */
6330 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6331 adjust OFFSET to compensate. */
6332 if (BYTES_BIG_ENDIAN
6334 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6335 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6337 /* If this is a constant position, we can move to the desired byte. */
6340 offset
+= pos
/ BITS_PER_UNIT
;
6341 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6344 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6346 && is_mode
!= wanted_inner_mode
)
6347 offset
= (GET_MODE_SIZE (is_mode
)
6348 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6350 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6351 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6354 /* If INNER is not memory, we can always get it into the proper mode. If we
6355 are changing its mode, POS must be a constant and smaller than the size
6357 else if (GET_CODE (inner
) != MEM
)
6359 if (GET_MODE (inner
) != wanted_inner_mode
6361 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6364 inner
= force_to_mode (inner
, wanted_inner_mode
,
6366 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6367 ? ~(unsigned HOST_WIDE_INT
) 0
6368 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6373 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6374 have to zero extend. Otherwise, we can just use a SUBREG. */
6376 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6378 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6380 /* If we know that no extraneous bits are set, and that the high
6381 bit is not set, convert extraction to cheaper one - either
6382 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6384 if (flag_expensive_optimizations
6385 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6386 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6387 & ~(((unsigned HOST_WIDE_INT
)
6388 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6392 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6394 /* Prefer ZERO_EXTENSION, since it gives more information to
6396 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6401 else if (pos_rtx
!= 0
6402 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6403 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
6405 /* Make POS_RTX unless we already have it and it is correct. If we don't
6406 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6408 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6409 pos_rtx
= orig_pos_rtx
;
6411 else if (pos_rtx
== 0)
6412 pos_rtx
= GEN_INT (pos
);
6414 /* Make the required operation. See if we can use existing rtx. */
6415 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6416 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6418 new = gen_lowpart_for_combine (mode
, new);
6423 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6424 with any other operations in X. Return X without that shift if so. */
6427 extract_left_shift (rtx x
, int count
)
6429 enum rtx_code code
= GET_CODE (x
);
6430 enum machine_mode mode
= GET_MODE (x
);
6436 /* This is the shift itself. If it is wide enough, we will return
6437 either the value being shifted if the shift count is equal to
6438 COUNT or a shift for the difference. */
6439 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6440 && INTVAL (XEXP (x
, 1)) >= count
)
6441 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6442 INTVAL (XEXP (x
, 1)) - count
);
6446 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6447 return simplify_gen_unary (code
, mode
, tem
, mode
);
6451 case PLUS
: case IOR
: case XOR
: case AND
:
6452 /* If we can safely shift this constant and we find the inner shift,
6453 make a new operation. */
6454 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6455 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6456 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6457 return gen_binary (code
, mode
, tem
,
6458 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6469 /* Look at the expression rooted at X. Look for expressions
6470 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6471 Form these expressions.
6473 Return the new rtx, usually just X.
6475 Also, for machines like the VAX that don't have logical shift insns,
6476 try to convert logical to arithmetic shift operations in cases where
6477 they are equivalent. This undoes the canonicalizations to logical
6478 shifts done elsewhere.
6480 We try, as much as possible, to re-use rtl expressions to save memory.
6482 IN_CODE says what kind of expression we are processing. Normally, it is
6483 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6484 being kludges), it is MEM. When processing the arguments of a comparison
6485 or a COMPARE against zero, it is COMPARE. */
6488 make_compound_operation (rtx x
, enum rtx_code in_code
)
6490 enum rtx_code code
= GET_CODE (x
);
6491 enum machine_mode mode
= GET_MODE (x
);
6492 int mode_width
= GET_MODE_BITSIZE (mode
);
6494 enum rtx_code next_code
;
6500 /* Select the code to be used in recursive calls. Once we are inside an
6501 address, we stay there. If we have a comparison, set to COMPARE,
6502 but once inside, go back to our default of SET. */
6504 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6505 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6506 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6507 : in_code
== COMPARE
? SET
: in_code
);
6509 /* Process depending on the code of this operation. If NEW is set
6510 nonzero, it will be returned. */
6515 /* Convert shifts by constants into multiplications if inside
6517 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6518 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6519 && INTVAL (XEXP (x
, 1)) >= 0)
6521 new = make_compound_operation (XEXP (x
, 0), next_code
);
6522 new = gen_rtx_MULT (mode
, new,
6523 GEN_INT ((HOST_WIDE_INT
) 1
6524 << INTVAL (XEXP (x
, 1))));
6529 /* If the second operand is not a constant, we can't do anything
6531 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6534 /* If the constant is a power of two minus one and the first operand
6535 is a logical right shift, make an extraction. */
6536 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6537 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6539 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6540 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6541 0, in_code
== COMPARE
);
6544 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6545 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6546 && subreg_lowpart_p (XEXP (x
, 0))
6547 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6548 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6550 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6552 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6553 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6554 0, in_code
== COMPARE
);
6556 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6557 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6558 || GET_CODE (XEXP (x
, 0)) == IOR
)
6559 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6560 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6561 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6563 /* Apply the distributive law, and then try to make extractions. */
6564 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6565 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6567 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6569 new = make_compound_operation (new, in_code
);
6572 /* If we are have (and (rotate X C) M) and C is larger than the number
6573 of bits in M, this is an extraction. */
6575 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6576 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6577 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6578 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6580 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6581 new = make_extraction (mode
, new,
6582 (GET_MODE_BITSIZE (mode
)
6583 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6584 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6587 /* On machines without logical shifts, if the operand of the AND is
6588 a logical shift and our mask turns off all the propagated sign
6589 bits, we can replace the logical shift with an arithmetic shift. */
6590 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6591 && !have_insn_for (LSHIFTRT
, mode
)
6592 && have_insn_for (ASHIFTRT
, mode
)
6593 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6594 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6595 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6596 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6598 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6600 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6601 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6603 gen_rtx_ASHIFTRT (mode
,
6604 make_compound_operation
6605 (XEXP (XEXP (x
, 0), 0), next_code
),
6606 XEXP (XEXP (x
, 0), 1)));
6609 /* If the constant is one less than a power of two, this might be
6610 representable by an extraction even if no shift is present.
6611 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6612 we are in a COMPARE. */
6613 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6614 new = make_extraction (mode
,
6615 make_compound_operation (XEXP (x
, 0),
6617 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6619 /* If we are in a comparison and this is an AND with a power of two,
6620 convert this into the appropriate bit extract. */
6621 else if (in_code
== COMPARE
6622 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6623 new = make_extraction (mode
,
6624 make_compound_operation (XEXP (x
, 0),
6626 i
, NULL_RTX
, 1, 1, 0, 1);
6631 /* If the sign bit is known to be zero, replace this with an
6632 arithmetic shift. */
6633 if (have_insn_for (ASHIFTRT
, mode
)
6634 && ! have_insn_for (LSHIFTRT
, mode
)
6635 && mode_width
<= HOST_BITS_PER_WIDE_INT
6636 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6638 new = gen_rtx_ASHIFTRT (mode
,
6639 make_compound_operation (XEXP (x
, 0),
6645 /* ... fall through ... */
6651 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6652 this is a SIGN_EXTRACT. */
6653 if (GET_CODE (rhs
) == CONST_INT
6654 && GET_CODE (lhs
) == ASHIFT
6655 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6656 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6658 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6659 new = make_extraction (mode
, new,
6660 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6661 NULL_RTX
, mode_width
- INTVAL (rhs
),
6662 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6666 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6667 If so, try to merge the shifts into a SIGN_EXTEND. We could
6668 also do this for some cases of SIGN_EXTRACT, but it doesn't
6669 seem worth the effort; the case checked for occurs on Alpha. */
6671 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6672 && ! (GET_CODE (lhs
) == SUBREG
6673 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6674 && GET_CODE (rhs
) == CONST_INT
6675 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6676 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6677 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6678 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6679 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6684 /* Call ourselves recursively on the inner expression. If we are
6685 narrowing the object and it has a different RTL code from
6686 what it originally did, do this SUBREG as a force_to_mode. */
6688 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6689 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6690 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6691 && subreg_lowpart_p (x
))
6693 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6696 /* If we have something other than a SUBREG, we might have
6697 done an expansion, so rerun ourselves. */
6698 if (GET_CODE (newer
) != SUBREG
)
6699 newer
= make_compound_operation (newer
, in_code
);
6704 /* If this is a paradoxical subreg, and the new code is a sign or
6705 zero extension, omit the subreg and widen the extension. If it
6706 is a regular subreg, we can still get rid of the subreg by not
6707 widening so much, or in fact removing the extension entirely. */
6708 if ((GET_CODE (tem
) == SIGN_EXTEND
6709 || GET_CODE (tem
) == ZERO_EXTEND
)
6710 && subreg_lowpart_p (x
))
6712 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6713 || (GET_MODE_SIZE (mode
) >
6714 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6716 if (! SCALAR_INT_MODE_P (mode
))
6718 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6721 tem
= gen_lowpart_for_combine (mode
, XEXP (tem
, 0));
6732 x
= gen_lowpart_for_combine (mode
, new);
6733 code
= GET_CODE (x
);
6736 /* Now recursively process each operand of this operation. */
6737 fmt
= GET_RTX_FORMAT (code
);
6738 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6741 new = make_compound_operation (XEXP (x
, i
), next_code
);
6742 SUBST (XEXP (x
, i
), new);
6748 /* Given M see if it is a value that would select a field of bits
6749 within an item, but not the entire word. Return -1 if not.
6750 Otherwise, return the starting position of the field, where 0 is the
6753 *PLEN is set to the length of the field. */
6756 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
6758 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6759 int pos
= exact_log2 (m
& -m
);
6765 /* Now shift off the low-order zero bits and see if we have a power of
6767 len
= exact_log2 ((m
>> pos
) + 1);
6776 /* See if X can be simplified knowing that we will only refer to it in
6777 MODE and will only refer to those bits that are nonzero in MASK.
6778 If other bits are being computed or if masking operations are done
6779 that select a superset of the bits in MASK, they can sometimes be
6782 Return a possibly simplified expression, but always convert X to
6783 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6785 Also, if REG is nonzero and X is a register equal in value to REG,
6788 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6789 are all off in X. This is used when X will be complemented, by either
6790 NOT, NEG, or XOR. */
6793 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
6794 rtx reg
, int just_select
)
6796 enum rtx_code code
= GET_CODE (x
);
6797 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6798 enum machine_mode op_mode
;
6799 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6802 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6803 code below will do the wrong thing since the mode of such an
6804 expression is VOIDmode.
6806 Also do nothing if X is a CLOBBER; this can happen if X was
6807 the return value from a call to gen_lowpart_for_combine. */
6808 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6811 /* We want to perform the operation is its present mode unless we know
6812 that the operation is valid in MODE, in which case we do the operation
6814 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6815 && have_insn_for (code
, mode
))
6816 ? mode
: GET_MODE (x
));
6818 /* It is not valid to do a right-shift in a narrower mode
6819 than the one it came in with. */
6820 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6821 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6822 op_mode
= GET_MODE (x
);
6824 /* Truncate MASK to fit OP_MODE. */
6826 mask
&= GET_MODE_MASK (op_mode
);
6828 /* When we have an arithmetic operation, or a shift whose count we
6829 do not know, we need to assume that all bit the up to the highest-order
6830 bit in MASK will be needed. This is how we form such a mask. */
6832 fuller_mask
= (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
6833 ? GET_MODE_MASK (op_mode
)
6834 : (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6837 fuller_mask
= ~(HOST_WIDE_INT
) 0;
6839 /* Determine what bits of X are guaranteed to be (non)zero. */
6840 nonzero
= nonzero_bits (x
, mode
);
6842 /* If none of the bits in X are needed, return a zero. */
6843 if (! just_select
&& (nonzero
& mask
) == 0)
6846 /* If X is a CONST_INT, return a new one. Do this here since the
6847 test below will fail. */
6848 if (GET_CODE (x
) == CONST_INT
)
6850 if (SCALAR_INT_MODE_P (mode
))
6851 return gen_int_mode (INTVAL (x
) & mask
, mode
);
6854 x
= GEN_INT (INTVAL (x
) & mask
);
6855 return gen_lowpart_common (mode
, x
);
6859 /* If X is narrower than MODE and we want all the bits in X's mode, just
6860 get X in the proper mode. */
6861 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6862 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6863 return gen_lowpart_for_combine (mode
, x
);
6865 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6866 MASK are already known to be zero in X, we need not do anything. */
6867 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6873 /* If X is a (clobber (const_int)), return it since we know we are
6874 generating something that won't match. */
6878 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6879 spanned the boundary of the MEM. If we are now masking so it is
6880 within that boundary, we don't need the USE any more. */
6881 if (! BITS_BIG_ENDIAN
6882 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6883 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6890 x
= expand_compound_operation (x
);
6891 if (GET_CODE (x
) != code
)
6892 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6896 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6897 || rtx_equal_p (reg
, get_last_value (x
))))
6902 if (subreg_lowpart_p (x
)
6903 /* We can ignore the effect of this SUBREG if it narrows the mode or
6904 if the constant masks to zero all the bits the mode doesn't
6906 && ((GET_MODE_SIZE (GET_MODE (x
))
6907 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6909 & GET_MODE_MASK (GET_MODE (x
))
6910 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6911 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6915 /* If this is an AND with a constant, convert it into an AND
6916 whose constant is the AND of that constant with MASK. If it
6917 remains an AND of MASK, delete it since it is redundant. */
6919 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6921 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6922 mask
& INTVAL (XEXP (x
, 1)));
6924 /* If X is still an AND, see if it is an AND with a mask that
6925 is just some low-order bits. If so, and it is MASK, we don't
6928 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6929 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
6933 /* If it remains an AND, try making another AND with the bits
6934 in the mode mask that aren't in MASK turned on. If the
6935 constant in the AND is wide enough, this might make a
6936 cheaper constant. */
6938 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6939 && GET_MODE_MASK (GET_MODE (x
)) != mask
6940 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6942 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6943 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6944 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6947 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6948 number, sign extend it. */
6949 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6950 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6951 cval
|= (HOST_WIDE_INT
) -1 << width
;
6953 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6954 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6964 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6965 low-order bits (as in an alignment operation) and FOO is already
6966 aligned to that boundary, mask C1 to that boundary as well.
6967 This may eliminate that PLUS and, later, the AND. */
6970 unsigned int width
= GET_MODE_BITSIZE (mode
);
6971 unsigned HOST_WIDE_INT smask
= mask
;
6973 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6974 number, sign extend it. */
6976 if (width
< HOST_BITS_PER_WIDE_INT
6977 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6978 smask
|= (HOST_WIDE_INT
) -1 << width
;
6980 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6981 && exact_log2 (- smask
) >= 0
6982 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6983 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6984 return force_to_mode (plus_constant (XEXP (x
, 0),
6985 (INTVAL (XEXP (x
, 1)) & smask
)),
6986 mode
, smask
, reg
, next_select
);
6989 /* ... fall through ... */
6992 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6993 most significant bit in MASK since carries from those bits will
6994 affect the bits we are interested in. */
6999 /* If X is (minus C Y) where C's least set bit is larger than any bit
7000 in the mask, then we may replace with (neg Y). */
7001 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
7002 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
7003 & -INTVAL (XEXP (x
, 0))))
7006 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
7008 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7011 /* Similarly, if C contains every bit in the fuller_mask, then we may
7012 replace with (not Y). */
7013 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
7014 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
7015 == INTVAL (XEXP (x
, 0))))
7017 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
7018 XEXP (x
, 1), GET_MODE (x
));
7019 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7027 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7028 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7029 operation which may be a bitfield extraction. Ensure that the
7030 constant we form is not wider than the mode of X. */
7032 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7033 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7034 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7035 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7036 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7037 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
7038 + floor_log2 (INTVAL (XEXP (x
, 1))))
7039 < GET_MODE_BITSIZE (GET_MODE (x
)))
7040 && (INTVAL (XEXP (x
, 1))
7041 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
7043 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
7044 << INTVAL (XEXP (XEXP (x
, 0), 1)));
7045 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
7046 XEXP (XEXP (x
, 0), 0), temp
);
7047 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
7048 XEXP (XEXP (x
, 0), 1));
7049 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7053 /* For most binary operations, just propagate into the operation and
7054 change the mode if we have an operation of that mode. */
7056 op0
= gen_lowpart_for_combine (op_mode
,
7057 force_to_mode (XEXP (x
, 0), mode
, mask
,
7059 op1
= gen_lowpart_for_combine (op_mode
,
7060 force_to_mode (XEXP (x
, 1), mode
, mask
,
7063 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7064 x
= gen_binary (code
, op_mode
, op0
, op1
);
7068 /* For left shifts, do the same, but just for the first operand.
7069 However, we cannot do anything with shifts where we cannot
7070 guarantee that the counts are smaller than the size of the mode
7071 because such a count will have a different meaning in a
7074 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
7075 && INTVAL (XEXP (x
, 1)) >= 0
7076 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7077 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7078 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7079 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7082 /* If the shift count is a constant and we can do arithmetic in
7083 the mode of the shift, refine which bits we need. Otherwise, use the
7084 conservative form of the mask. */
7085 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7086 && INTVAL (XEXP (x
, 1)) >= 0
7087 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7088 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7089 mask
>>= INTVAL (XEXP (x
, 1));
7093 op0
= gen_lowpart_for_combine (op_mode
,
7094 force_to_mode (XEXP (x
, 0), op_mode
,
7095 mask
, reg
, next_select
));
7097 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7098 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7102 /* Here we can only do something if the shift count is a constant,
7103 this shift constant is valid for the host, and we can do arithmetic
7106 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7107 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7108 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7110 rtx inner
= XEXP (x
, 0);
7111 unsigned HOST_WIDE_INT inner_mask
;
7113 /* Select the mask of the bits we need for the shift operand. */
7114 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7116 /* We can only change the mode of the shift if we can do arithmetic
7117 in the mode of the shift and INNER_MASK is no wider than the
7118 width of OP_MODE. */
7119 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
7120 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
7121 op_mode
= GET_MODE (x
);
7123 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7125 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7126 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7129 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7130 shift and AND produces only copies of the sign bit (C2 is one less
7131 than a power of two), we can do this with just a shift. */
7133 if (GET_CODE (x
) == LSHIFTRT
7134 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7135 /* The shift puts one of the sign bit copies in the least significant
7137 && ((INTVAL (XEXP (x
, 1))
7138 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7139 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7140 && exact_log2 (mask
+ 1) >= 0
7141 /* Number of bits left after the shift must be more than the mask
7143 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7144 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7145 /* Must be more sign bit copies than the mask needs. */
7146 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7147 >= exact_log2 (mask
+ 1)))
7148 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7149 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7150 - exact_log2 (mask
+ 1)));
7155 /* If we are just looking for the sign bit, we don't need this shift at
7156 all, even if it has a variable count. */
7157 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7158 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7159 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7160 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7162 /* If this is a shift by a constant, get a mask that contains those bits
7163 that are not copies of the sign bit. We then have two cases: If
7164 MASK only includes those bits, this can be a logical shift, which may
7165 allow simplifications. If MASK is a single-bit field not within
7166 those bits, we are requesting a copy of the sign bit and hence can
7167 shift the sign bit to the appropriate location. */
7169 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7170 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7174 /* If the considered data is wider than HOST_WIDE_INT, we can't
7175 represent a mask for all its bits in a single scalar.
7176 But we only care about the lower bits, so calculate these. */
7178 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7180 nonzero
= ~(HOST_WIDE_INT
) 0;
7182 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7183 is the number of bits a full-width mask would have set.
7184 We need only shift if these are fewer than nonzero can
7185 hold. If not, we must keep all bits set in nonzero. */
7187 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7188 < HOST_BITS_PER_WIDE_INT
)
7189 nonzero
>>= INTVAL (XEXP (x
, 1))
7190 + HOST_BITS_PER_WIDE_INT
7191 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7195 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7196 nonzero
>>= INTVAL (XEXP (x
, 1));
7199 if ((mask
& ~nonzero
) == 0
7200 || (i
= exact_log2 (mask
)) >= 0)
7202 x
= simplify_shift_const
7203 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7204 i
< 0 ? INTVAL (XEXP (x
, 1))
7205 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7207 if (GET_CODE (x
) != ASHIFTRT
)
7208 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7212 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7213 even if the shift count isn't a constant. */
7215 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7219 /* If this is a zero- or sign-extension operation that just affects bits
7220 we don't care about, remove it. Be sure the call above returned
7221 something that is still a shift. */
7223 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7224 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7225 && INTVAL (XEXP (x
, 1)) >= 0
7226 && (INTVAL (XEXP (x
, 1))
7227 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7228 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7229 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
7230 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7237 /* If the shift count is constant and we can do computations
7238 in the mode of X, compute where the bits we care about are.
7239 Otherwise, we can't do anything. Don't change the mode of
7240 the shift or propagate MODE into the shift, though. */
7241 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7242 && INTVAL (XEXP (x
, 1)) >= 0)
7244 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7245 GET_MODE (x
), GEN_INT (mask
),
7247 if (temp
&& GET_CODE (temp
) == CONST_INT
)
7249 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7250 INTVAL (temp
), reg
, next_select
));
7255 /* If we just want the low-order bit, the NEG isn't needed since it
7256 won't change the low-order bit. */
7258 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7260 /* We need any bits less significant than the most significant bit in
7261 MASK since carries from those bits will affect the bits we are
7267 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7268 same as the XOR case above. Ensure that the constant we form is not
7269 wider than the mode of X. */
7271 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7272 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7273 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7274 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7275 < GET_MODE_BITSIZE (GET_MODE (x
)))
7276 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7278 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
7280 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7281 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7283 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7286 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7287 use the full mask inside the NOT. */
7291 op0
= gen_lowpart_for_combine (op_mode
,
7292 force_to_mode (XEXP (x
, 0), mode
, mask
,
7294 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7295 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7299 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7300 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7301 which is equal to STORE_FLAG_VALUE. */
7302 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7303 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7304 && (nonzero_bits (XEXP (x
, 0), mode
)
7305 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
7306 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7311 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7312 written in a narrower mode. We play it safe and do not do so. */
7315 gen_lowpart_for_combine (GET_MODE (x
),
7316 force_to_mode (XEXP (x
, 1), mode
,
7317 mask
, reg
, next_select
)));
7319 gen_lowpart_for_combine (GET_MODE (x
),
7320 force_to_mode (XEXP (x
, 2), mode
,
7321 mask
, reg
, next_select
)));
7328 /* Ensure we return a value of the proper mode. */
7329 return gen_lowpart_for_combine (mode
, x
);
7332 /* Return nonzero if X is an expression that has one of two values depending on
7333 whether some other value is zero or nonzero. In that case, we return the
7334 value that is being tested, *PTRUE is set to the value if the rtx being
7335 returned has a nonzero value, and *PFALSE is set to the other alternative.
7337 If we return zero, we set *PTRUE and *PFALSE to X. */
7340 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
7342 enum machine_mode mode
= GET_MODE (x
);
7343 enum rtx_code code
= GET_CODE (x
);
7344 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7345 unsigned HOST_WIDE_INT nz
;
7347 /* If we are comparing a value against zero, we are done. */
7348 if ((code
== NE
|| code
== EQ
)
7349 && XEXP (x
, 1) == const0_rtx
)
7351 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7352 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7356 /* If this is a unary operation whose operand has one of two values, apply
7357 our opcode to compute those values. */
7358 else if (GET_RTX_CLASS (code
) == '1'
7359 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7361 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7362 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7363 GET_MODE (XEXP (x
, 0)));
7367 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7368 make can't possibly match and would suppress other optimizations. */
7369 else if (code
== COMPARE
)
7372 /* If this is a binary operation, see if either side has only one of two
7373 values. If either one does or if both do and they are conditional on
7374 the same value, compute the new true and false values. */
7375 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7376 || GET_RTX_CLASS (code
) == '<')
7378 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7379 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7381 if ((cond0
!= 0 || cond1
!= 0)
7382 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7384 /* If if_then_else_cond returned zero, then true/false are the
7385 same rtl. We must copy one of them to prevent invalid rtl
7388 true0
= copy_rtx (true0
);
7389 else if (cond1
== 0)
7390 true1
= copy_rtx (true1
);
7392 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7393 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7394 return cond0
? cond0
: cond1
;
7397 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7398 operands is zero when the other is nonzero, and vice-versa,
7399 and STORE_FLAG_VALUE is 1 or -1. */
7401 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7402 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7404 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7406 rtx op0
= XEXP (XEXP (x
, 0), 1);
7407 rtx op1
= XEXP (XEXP (x
, 1), 1);
7409 cond0
= XEXP (XEXP (x
, 0), 0);
7410 cond1
= XEXP (XEXP (x
, 1), 0);
7412 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7413 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7414 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7415 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7416 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7417 || ((swap_condition (GET_CODE (cond0
))
7418 == combine_reversed_comparison_code (cond1
))
7419 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7420 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7421 && ! side_effects_p (x
))
7423 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7424 *pfalse
= gen_binary (MULT
, mode
,
7426 ? simplify_gen_unary (NEG
, mode
, op1
,
7434 /* Similarly for MULT, AND and UMIN, except that for these the result
7436 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7437 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7438 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7440 cond0
= XEXP (XEXP (x
, 0), 0);
7441 cond1
= XEXP (XEXP (x
, 1), 0);
7443 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7444 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7445 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7446 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7447 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7448 || ((swap_condition (GET_CODE (cond0
))
7449 == combine_reversed_comparison_code (cond1
))
7450 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7451 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7452 && ! side_effects_p (x
))
7454 *ptrue
= *pfalse
= const0_rtx
;
7460 else if (code
== IF_THEN_ELSE
)
7462 /* If we have IF_THEN_ELSE already, extract the condition and
7463 canonicalize it if it is NE or EQ. */
7464 cond0
= XEXP (x
, 0);
7465 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7466 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7467 return XEXP (cond0
, 0);
7468 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7470 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7471 return XEXP (cond0
, 0);
7477 /* If X is a SUBREG, we can narrow both the true and false values
7478 if the inner expression, if there is a condition. */
7479 else if (code
== SUBREG
7480 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7483 *ptrue
= simplify_gen_subreg (mode
, true0
,
7484 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7485 *pfalse
= simplify_gen_subreg (mode
, false0
,
7486 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7491 /* If X is a constant, this isn't special and will cause confusions
7492 if we treat it as such. Likewise if it is equivalent to a constant. */
7493 else if (CONSTANT_P (x
)
7494 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7497 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7498 will be least confusing to the rest of the compiler. */
7499 else if (mode
== BImode
)
7501 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7505 /* If X is known to be either 0 or -1, those are the true and
7506 false values when testing X. */
7507 else if (x
== constm1_rtx
|| x
== const0_rtx
7508 || (mode
!= VOIDmode
7509 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7511 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7515 /* Likewise for 0 or a single bit. */
7516 else if (mode
!= VOIDmode
7517 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7518 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7520 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7524 /* Otherwise fail; show no condition with true and false values the same. */
7525 *ptrue
= *pfalse
= x
;
7529 /* Return the value of expression X given the fact that condition COND
7530 is known to be true when applied to REG as its first operand and VAL
7531 as its second. X is known to not be shared and so can be modified in
7534 We only handle the simplest cases, and specifically those cases that
7535 arise with IF_THEN_ELSE expressions. */
7538 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
7540 enum rtx_code code
= GET_CODE (x
);
7545 if (side_effects_p (x
))
7548 /* If either operand of the condition is a floating point value,
7549 then we have to avoid collapsing an EQ comparison. */
7551 && rtx_equal_p (x
, reg
)
7552 && ! FLOAT_MODE_P (GET_MODE (x
))
7553 && ! FLOAT_MODE_P (GET_MODE (val
)))
7556 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7559 /* If X is (abs REG) and we know something about REG's relationship
7560 with zero, we may be able to simplify this. */
7562 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7565 case GE
: case GT
: case EQ
:
7568 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7570 GET_MODE (XEXP (x
, 0)));
7575 /* The only other cases we handle are MIN, MAX, and comparisons if the
7576 operands are the same as REG and VAL. */
7578 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7580 if (rtx_equal_p (XEXP (x
, 0), val
))
7581 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7583 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7585 if (GET_RTX_CLASS (code
) == '<')
7587 if (comparison_dominates_p (cond
, code
))
7588 return const_true_rtx
;
7590 code
= combine_reversed_comparison_code (x
);
7592 && comparison_dominates_p (cond
, code
))
7597 else if (code
== SMAX
|| code
== SMIN
7598 || code
== UMIN
|| code
== UMAX
)
7600 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7602 /* Do not reverse the condition when it is NE or EQ.
7603 This is because we cannot conclude anything about
7604 the value of 'SMAX (x, y)' when x is not equal to y,
7605 but we can when x equals y. */
7606 if ((code
== SMAX
|| code
== UMAX
)
7607 && ! (cond
== EQ
|| cond
== NE
))
7608 cond
= reverse_condition (cond
);
7613 return unsignedp
? x
: XEXP (x
, 1);
7615 return unsignedp
? x
: XEXP (x
, 0);
7617 return unsignedp
? XEXP (x
, 1) : x
;
7619 return unsignedp
? XEXP (x
, 0) : x
;
7626 else if (code
== SUBREG
)
7628 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7629 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
7631 if (SUBREG_REG (x
) != r
)
7633 /* We must simplify subreg here, before we lose track of the
7634 original inner_mode. */
7635 new = simplify_subreg (GET_MODE (x
), r
,
7636 inner_mode
, SUBREG_BYTE (x
));
7640 SUBST (SUBREG_REG (x
), r
);
7645 /* We don't have to handle SIGN_EXTEND here, because even in the
7646 case of replacing something with a modeless CONST_INT, a
7647 CONST_INT is already (supposed to be) a valid sign extension for
7648 its narrower mode, which implies it's already properly
7649 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7650 story is different. */
7651 else if (code
== ZERO_EXTEND
)
7653 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
7654 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
7656 if (XEXP (x
, 0) != r
)
7658 /* We must simplify the zero_extend here, before we lose
7659 track of the original inner_mode. */
7660 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7665 SUBST (XEXP (x
, 0), r
);
7671 fmt
= GET_RTX_FORMAT (code
);
7672 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7675 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7676 else if (fmt
[i
] == 'E')
7677 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7678 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7685 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7686 assignment as a field assignment. */
7689 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
7691 if (x
== y
|| rtx_equal_p (x
, y
))
7694 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7697 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7698 Note that all SUBREGs of MEM are paradoxical; otherwise they
7699 would have been rewritten. */
7700 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7701 && GET_CODE (SUBREG_REG (y
)) == MEM
7702 && rtx_equal_p (SUBREG_REG (y
),
7703 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y
)), x
)))
7706 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7707 && GET_CODE (SUBREG_REG (x
)) == MEM
7708 && rtx_equal_p (SUBREG_REG (x
),
7709 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x
)), y
)))
7712 /* We used to see if get_last_value of X and Y were the same but that's
7713 not correct. In one direction, we'll cause the assignment to have
7714 the wrong destination and in the case, we'll import a register into this
7715 insn that might have already have been dead. So fail if none of the
7716 above cases are true. */
7720 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7721 Return that assignment if so.
7723 We only handle the most common cases. */
7726 make_field_assignment (rtx x
)
7728 rtx dest
= SET_DEST (x
);
7729 rtx src
= SET_SRC (x
);
7734 unsigned HOST_WIDE_INT len
;
7736 enum machine_mode mode
;
7738 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7739 a clear of a one-bit field. We will have changed it to
7740 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7743 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7744 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7745 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7746 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7748 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7751 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7755 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7756 && subreg_lowpart_p (XEXP (src
, 0))
7757 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7758 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7759 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7760 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7761 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7763 assign
= make_extraction (VOIDmode
, dest
, 0,
7764 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7767 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7771 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7773 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7774 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7775 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7777 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7780 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7784 /* The other case we handle is assignments into a constant-position
7785 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7786 a mask that has all one bits except for a group of zero bits and
7787 OTHER is known to have zeros where C1 has ones, this is such an
7788 assignment. Compute the position and length from C1. Shift OTHER
7789 to the appropriate position, force it to the required mode, and
7790 make the extraction. Check for the AND in both operands. */
7792 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7795 rhs
= expand_compound_operation (XEXP (src
, 0));
7796 lhs
= expand_compound_operation (XEXP (src
, 1));
7798 if (GET_CODE (rhs
) == AND
7799 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7800 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7801 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7802 else if (GET_CODE (lhs
) == AND
7803 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7804 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7805 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7809 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7810 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7811 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7812 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7815 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7819 /* The mode to use for the source is the mode of the assignment, or of
7820 what is inside a possible STRICT_LOW_PART. */
7821 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7822 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7824 /* Shift OTHER right POS places and make it the source, restricting it
7825 to the proper length and mode. */
7827 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7828 GET_MODE (src
), other
, pos
),
7830 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7831 ? ~(unsigned HOST_WIDE_INT
) 0
7832 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7835 /* If SRC is masked by an AND that does not make a difference in
7836 the value being stored, strip it. */
7837 if (GET_CODE (assign
) == ZERO_EXTRACT
7838 && GET_CODE (XEXP (assign
, 1)) == CONST_INT
7839 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
7840 && GET_CODE (src
) == AND
7841 && GET_CODE (XEXP (src
, 1)) == CONST_INT
7842 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
7843 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
7844 src
= XEXP (src
, 0);
7846 return gen_rtx_SET (VOIDmode
, assign
, src
);
7849 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7853 apply_distributive_law (rtx x
)
7855 enum rtx_code code
= GET_CODE (x
);
7856 rtx lhs
, rhs
, other
;
7858 enum rtx_code inner_code
;
7860 /* Distributivity is not true for floating point.
7861 It can change the value. So don't do it.
7862 -- rms and moshier@world.std.com. */
7863 if (FLOAT_MODE_P (GET_MODE (x
)))
7866 /* The outer operation can only be one of the following: */
7867 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7868 && code
!= PLUS
&& code
!= MINUS
)
7871 lhs
= XEXP (x
, 0), rhs
= XEXP (x
, 1);
7873 /* If either operand is a primitive we can't do anything, so get out
7875 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7876 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7879 lhs
= expand_compound_operation (lhs
);
7880 rhs
= expand_compound_operation (rhs
);
7881 inner_code
= GET_CODE (lhs
);
7882 if (inner_code
!= GET_CODE (rhs
))
7885 /* See if the inner and outer operations distribute. */
7892 /* These all distribute except over PLUS. */
7893 if (code
== PLUS
|| code
== MINUS
)
7898 if (code
!= PLUS
&& code
!= MINUS
)
7903 /* This is also a multiply, so it distributes over everything. */
7907 /* Non-paradoxical SUBREGs distributes over all operations, provided
7908 the inner modes and byte offsets are the same, this is an extraction
7909 of a low-order part, we don't convert an fp operation to int or
7910 vice versa, and we would not be converting a single-word
7911 operation into a multi-word operation. The latter test is not
7912 required, but it prevents generating unneeded multi-word operations.
7913 Some of the previous tests are redundant given the latter test, but
7914 are retained because they are required for correctness.
7916 We produce the result slightly differently in this case. */
7918 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7919 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7920 || ! subreg_lowpart_p (lhs
)
7921 || (GET_MODE_CLASS (GET_MODE (lhs
))
7922 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7923 || (GET_MODE_SIZE (GET_MODE (lhs
))
7924 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7925 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7928 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7929 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7930 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
7936 /* Set LHS and RHS to the inner operands (A and B in the example
7937 above) and set OTHER to the common operand (C in the example).
7938 These is only one way to do this unless the inner operation is
7940 if (GET_RTX_CLASS (inner_code
) == 'c'
7941 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7942 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7943 else if (GET_RTX_CLASS (inner_code
) == 'c'
7944 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7945 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7946 else if (GET_RTX_CLASS (inner_code
) == 'c'
7947 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7948 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7949 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7950 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7954 /* Form the new inner operation, seeing if it simplifies first. */
7955 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7957 /* There is one exception to the general way of distributing:
7958 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7959 if (code
== XOR
&& inner_code
== IOR
)
7962 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
7965 /* We may be able to continuing distributing the result, so call
7966 ourselves recursively on the inner operation before forming the
7967 outer operation, which we return. */
7968 return gen_binary (inner_code
, GET_MODE (x
),
7969 apply_distributive_law (tem
), other
);
7972 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7975 Return an equivalent form, if different from X. Otherwise, return X. If
7976 X is zero, we are to always construct the equivalent form. */
7979 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
7980 unsigned HOST_WIDE_INT constop
)
7982 unsigned HOST_WIDE_INT nonzero
;
7985 /* Simplify VAROP knowing that we will be only looking at some of the
7988 Note by passing in CONSTOP, we guarantee that the bits not set in
7989 CONSTOP are not significant and will never be examined. We must
7990 ensure that is the case by explicitly masking out those bits
7991 before returning. */
7992 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7994 /* If VAROP is a CLOBBER, we will fail so return it. */
7995 if (GET_CODE (varop
) == CLOBBER
)
7998 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7999 to VAROP and return the new constant. */
8000 if (GET_CODE (varop
) == CONST_INT
)
8001 return GEN_INT (trunc_int_for_mode (INTVAL (varop
) & constop
, mode
));
8003 /* See what bits may be nonzero in VAROP. Unlike the general case of
8004 a call to nonzero_bits, here we don't care about bits outside
8007 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
8009 /* Turn off all bits in the constant that are known to already be zero.
8010 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8011 which is tested below. */
8015 /* If we don't have any bits left, return zero. */
8019 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8020 a power of two, we can replace this with an ASHIFT. */
8021 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
8022 && (i
= exact_log2 (constop
)) >= 0)
8023 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
8025 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8026 or XOR, then try to apply the distributive law. This may eliminate
8027 operations if either branch can be simplified because of the AND.
8028 It may also make some cases more complex, but those cases probably
8029 won't match a pattern either with or without this. */
8031 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
8033 gen_lowpart_for_combine
8035 apply_distributive_law
8036 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
8037 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
8038 XEXP (varop
, 0), constop
),
8039 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
8040 XEXP (varop
, 1), constop
))));
8042 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8043 the AND and see if one of the operands simplifies to zero. If so, we
8044 may eliminate it. */
8046 if (GET_CODE (varop
) == PLUS
8047 && exact_log2 (constop
+ 1) >= 0)
8051 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
8052 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
8053 if (o0
== const0_rtx
)
8055 if (o1
== const0_rtx
)
8059 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8060 if we already had one (just check for the simplest cases). */
8061 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
8062 && GET_MODE (XEXP (x
, 0)) == mode
8063 && SUBREG_REG (XEXP (x
, 0)) == varop
)
8064 varop
= XEXP (x
, 0);
8066 varop
= gen_lowpart_for_combine (mode
, varop
);
8068 /* If we can't make the SUBREG, try to return what we were given. */
8069 if (GET_CODE (varop
) == CLOBBER
)
8070 return x
? x
: varop
;
8072 /* If we are only masking insignificant bits, return VAROP. */
8073 if (constop
== nonzero
)
8077 /* Otherwise, return an AND. */
8078 constop
= trunc_int_for_mode (constop
, mode
);
8079 /* See how much, if any, of X we can use. */
8080 if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
8081 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
8085 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8086 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
8087 SUBST (XEXP (x
, 1), GEN_INT (constop
));
8089 SUBST (XEXP (x
, 0), varop
);
8096 #define nonzero_bits_with_known(X, MODE) \
8097 cached_nonzero_bits (X, MODE, known_x, known_mode, known_ret)
8099 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
8100 It avoids exponential behavior in nonzero_bits1 when X has
8101 identical subexpressions on the first or the second level. */
8103 static unsigned HOST_WIDE_INT
8104 cached_nonzero_bits (rtx x
, enum machine_mode mode
, rtx known_x
,
8105 enum machine_mode known_mode
,
8106 unsigned HOST_WIDE_INT known_ret
)
8108 if (x
== known_x
&& mode
== known_mode
)
8111 /* Try to find identical subexpressions. If found call
8112 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
8113 precomputed value for the subexpression as KNOWN_RET. */
8115 if (GET_RTX_CLASS (GET_CODE (x
)) == '2'
8116 || GET_RTX_CLASS (GET_CODE (x
)) == 'c')
8118 rtx x0
= XEXP (x
, 0);
8119 rtx x1
= XEXP (x
, 1);
8121 /* Check the first level. */
8123 return nonzero_bits1 (x
, mode
, x0
, mode
,
8124 nonzero_bits_with_known (x0
, mode
));
8126 /* Check the second level. */
8127 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
8128 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
8129 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8130 return nonzero_bits1 (x
, mode
, x1
, mode
,
8131 nonzero_bits_with_known (x1
, mode
));
8133 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
8134 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
8135 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8136 return nonzero_bits1 (x
, mode
, x0
, mode
,
8137 nonzero_bits_with_known (x0
, mode
));
8140 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
8143 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8144 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8145 is less useful. We can't allow both, because that results in exponential
8146 run time recursion. There is a nullstone testcase that triggered
8147 this. This macro avoids accidental uses of num_sign_bit_copies. */
8148 #define cached_num_sign_bit_copies()
8150 /* Given an expression, X, compute which bits in X can be nonzero.
8151 We don't care about bits outside of those defined in MODE.
8153 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8154 a shift, AND, or zero_extract, we can do better. */
8156 static unsigned HOST_WIDE_INT
8157 nonzero_bits1 (rtx x
, enum machine_mode mode
, rtx known_x
,
8158 enum machine_mode known_mode
,
8159 unsigned HOST_WIDE_INT known_ret
)
8161 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
8162 unsigned HOST_WIDE_INT inner_nz
;
8164 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
8167 /* For floating-point values, assume all bits are needed. */
8168 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
8171 /* If X is wider than MODE, use its mode instead. */
8172 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
8174 mode
= GET_MODE (x
);
8175 nonzero
= GET_MODE_MASK (mode
);
8176 mode_width
= GET_MODE_BITSIZE (mode
);
8179 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
8180 /* Our only callers in this case look for single bit values. So
8181 just return the mode mask. Those tests will then be false. */
8184 #ifndef WORD_REGISTER_OPERATIONS
8185 /* If MODE is wider than X, but both are a single word for both the host
8186 and target machines, we can compute this from which bits of the
8187 object might be nonzero in its own mode, taking into account the fact
8188 that on many CISC machines, accessing an object in a wider mode
8189 causes the high-order bits to become undefined. So they are
8190 not known to be zero. */
8192 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
8193 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
8194 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8195 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
8197 nonzero
&= nonzero_bits_with_known (x
, GET_MODE (x
));
8198 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
8203 code
= GET_CODE (x
);
8207 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8208 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8209 all the bits above ptr_mode are known to be zero. */
8210 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8212 nonzero
&= GET_MODE_MASK (ptr_mode
);
8215 /* Include declared information about alignment of pointers. */
8216 /* ??? We don't properly preserve REG_POINTER changes across
8217 pointer-to-integer casts, so we can't trust it except for
8218 things that we know must be pointers. See execute/960116-1.c. */
8219 if ((x
== stack_pointer_rtx
8220 || x
== frame_pointer_rtx
8221 || x
== arg_pointer_rtx
)
8222 && REGNO_POINTER_ALIGN (REGNO (x
)))
8224 unsigned HOST_WIDE_INT alignment
8225 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
8227 #ifdef PUSH_ROUNDING
8228 /* If PUSH_ROUNDING is defined, it is possible for the
8229 stack to be momentarily aligned only to that amount,
8230 so we pick the least alignment. */
8231 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
8232 alignment
= MIN ((unsigned HOST_WIDE_INT
) PUSH_ROUNDING (1),
8236 nonzero
&= ~(alignment
- 1);
8239 /* If X is a register whose nonzero bits value is current, use it.
8240 Otherwise, if X is a register whose value we can find, use that
8241 value. Otherwise, use the previously-computed global nonzero bits
8242 for this register. */
8244 if (reg_last_set_value
[REGNO (x
)] != 0
8245 && (reg_last_set_mode
[REGNO (x
)] == mode
8246 || (GET_MODE_CLASS (reg_last_set_mode
[REGNO (x
)]) == MODE_INT
8247 && GET_MODE_CLASS (mode
) == MODE_INT
))
8248 && (reg_last_set_label
[REGNO (x
)] == label_tick
8249 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8250 && REG_N_SETS (REGNO (x
)) == 1
8251 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8253 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8254 return reg_last_set_nonzero_bits
[REGNO (x
)] & nonzero
;
8256 tem
= get_last_value (x
);
8260 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8261 /* If X is narrower than MODE and TEM is a non-negative
8262 constant that would appear negative in the mode of X,
8263 sign-extend it for use in reg_nonzero_bits because some
8264 machines (maybe most) will actually do the sign-extension
8265 and this is the conservative approach.
8267 ??? For 2.5, try to tighten up the MD files in this regard
8268 instead of this kludge. */
8270 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
8271 && GET_CODE (tem
) == CONST_INT
8273 && 0 != (INTVAL (tem
)
8274 & ((HOST_WIDE_INT
) 1
8275 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8276 tem
= GEN_INT (INTVAL (tem
)
8277 | ((HOST_WIDE_INT
) (-1)
8278 << GET_MODE_BITSIZE (GET_MODE (x
))));
8280 return nonzero_bits_with_known (tem
, mode
) & nonzero
;
8282 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
8284 unsigned HOST_WIDE_INT mask
= reg_nonzero_bits
[REGNO (x
)];
8286 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
)
8287 /* We don't know anything about the upper bits. */
8288 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8289 return nonzero
& mask
;
8295 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8296 /* If X is negative in MODE, sign-extend the value. */
8297 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
8298 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
8299 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
8305 #ifdef LOAD_EXTEND_OP
8306 /* In many, if not most, RISC machines, reading a byte from memory
8307 zeros the rest of the register. Noticing that fact saves a lot
8308 of extra zero-extends. */
8309 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
8310 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
8315 case UNEQ
: case LTGT
:
8316 case GT
: case GTU
: case UNGT
:
8317 case LT
: case LTU
: case UNLT
:
8318 case GE
: case GEU
: case UNGE
:
8319 case LE
: case LEU
: case UNLE
:
8320 case UNORDERED
: case ORDERED
:
8322 /* If this produces an integer result, we know which bits are set.
8323 Code here used to clear bits outside the mode of X, but that is
8326 if (GET_MODE_CLASS (mode
) == MODE_INT
8327 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8328 nonzero
= STORE_FLAG_VALUE
;
8333 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8334 and num_sign_bit_copies. */
8335 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8336 == GET_MODE_BITSIZE (GET_MODE (x
)))
8340 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8341 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8346 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8347 and num_sign_bit_copies. */
8348 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8349 == GET_MODE_BITSIZE (GET_MODE (x
)))
8355 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8356 & GET_MODE_MASK (mode
));
8360 nonzero
&= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8361 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8362 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8366 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8367 Otherwise, show all the bits in the outer mode but not the inner
8369 inner_nz
= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8370 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8372 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8374 & (((HOST_WIDE_INT
) 1
8375 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8376 inner_nz
|= (GET_MODE_MASK (mode
)
8377 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8380 nonzero
&= inner_nz
;
8384 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8385 & nonzero_bits_with_known (XEXP (x
, 1), mode
));
8389 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8391 unsigned HOST_WIDE_INT nonzero0
=
8392 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8394 /* Don't call nonzero_bits for the second time if it cannot change
8396 if ((nonzero
& nonzero0
) != nonzero
)
8397 nonzero
&= (nonzero0
8398 | nonzero_bits_with_known (XEXP (x
, 1), mode
));
8402 case PLUS
: case MINUS
:
8404 case DIV
: case UDIV
:
8405 case MOD
: case UMOD
:
8406 /* We can apply the rules of arithmetic to compute the number of
8407 high- and low-order zero bits of these operations. We start by
8408 computing the width (position of the highest-order nonzero bit)
8409 and the number of low-order zero bits for each value. */
8411 unsigned HOST_WIDE_INT nz0
=
8412 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8413 unsigned HOST_WIDE_INT nz1
=
8414 nonzero_bits_with_known (XEXP (x
, 1), mode
);
8415 int sign_index
= GET_MODE_BITSIZE (GET_MODE (x
)) - 1;
8416 int width0
= floor_log2 (nz0
) + 1;
8417 int width1
= floor_log2 (nz1
) + 1;
8418 int low0
= floor_log2 (nz0
& -nz0
);
8419 int low1
= floor_log2 (nz1
& -nz1
);
8420 HOST_WIDE_INT op0_maybe_minusp
8421 = (nz0
& ((HOST_WIDE_INT
) 1 << sign_index
));
8422 HOST_WIDE_INT op1_maybe_minusp
8423 = (nz1
& ((HOST_WIDE_INT
) 1 << sign_index
));
8424 unsigned int result_width
= mode_width
;
8430 result_width
= MAX (width0
, width1
) + 1;
8431 result_low
= MIN (low0
, low1
);
8434 result_low
= MIN (low0
, low1
);
8437 result_width
= width0
+ width1
;
8438 result_low
= low0
+ low1
;
8443 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8444 result_width
= width0
;
8449 result_width
= width0
;
8454 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8455 result_width
= MIN (width0
, width1
);
8456 result_low
= MIN (low0
, low1
);
8461 result_width
= MIN (width0
, width1
);
8462 result_low
= MIN (low0
, low1
);
8468 if (result_width
< mode_width
)
8469 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8472 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8474 #ifdef POINTERS_EXTEND_UNSIGNED
8475 /* If pointers extend unsigned and this is an addition or subtraction
8476 to a pointer in Pmode, all the bits above ptr_mode are known to be
8478 if (POINTERS_EXTEND_UNSIGNED
> 0 && GET_MODE (x
) == Pmode
8479 && (code
== PLUS
|| code
== MINUS
)
8480 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8481 nonzero
&= GET_MODE_MASK (ptr_mode
);
8487 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8488 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8489 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8493 /* If this is a SUBREG formed for a promoted variable that has
8494 been zero-extended, we know that at least the high-order bits
8495 are zero, though others might be too. */
8497 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
) > 0)
8498 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8499 & nonzero_bits_with_known (SUBREG_REG (x
), GET_MODE (x
)));
8501 /* If the inner mode is a single word for both the host and target
8502 machines, we can compute this from which bits of the inner
8503 object might be nonzero. */
8504 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8505 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8506 <= HOST_BITS_PER_WIDE_INT
))
8508 nonzero
&= nonzero_bits_with_known (SUBREG_REG (x
), mode
);
8510 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8511 /* If this is a typical RISC machine, we only have to worry
8512 about the way loads are extended. */
8513 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8515 & (((unsigned HOST_WIDE_INT
) 1
8516 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8518 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8519 || GET_CODE (SUBREG_REG (x
)) != MEM
)
8522 /* On many CISC machines, accessing an object in a wider mode
8523 causes the high-order bits to become undefined. So they are
8524 not known to be zero. */
8525 if (GET_MODE_SIZE (GET_MODE (x
))
8526 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8527 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8528 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8537 /* The nonzero bits are in two classes: any bits within MODE
8538 that aren't in GET_MODE (x) are always significant. The rest of the
8539 nonzero bits are those that are significant in the operand of
8540 the shift when shifted the appropriate number of bits. This
8541 shows that high-order bits are cleared by the right shift and
8542 low-order bits by left shifts. */
8543 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8544 && INTVAL (XEXP (x
, 1)) >= 0
8545 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8547 enum machine_mode inner_mode
= GET_MODE (x
);
8548 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8549 int count
= INTVAL (XEXP (x
, 1));
8550 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8551 unsigned HOST_WIDE_INT op_nonzero
=
8552 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8553 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8554 unsigned HOST_WIDE_INT outer
= 0;
8556 if (mode_width
> width
)
8557 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8559 if (code
== LSHIFTRT
)
8561 else if (code
== ASHIFTRT
)
8565 /* If the sign bit may have been nonzero before the shift, we
8566 need to mark all the places it could have been copied to
8567 by the shift as possibly nonzero. */
8568 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8569 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8571 else if (code
== ASHIFT
)
8574 inner
= ((inner
<< (count
% width
)
8575 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8577 nonzero
&= (outer
| inner
);
8583 /* This is at most the number of bits in the mode. */
8584 nonzero
= ((HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
8588 /* If CLZ has a known value at zero, then the nonzero bits are
8589 that value, plus the number of bits in the mode minus one. */
8590 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8591 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8597 /* If CTZ has a known value at zero, then the nonzero bits are
8598 that value, plus the number of bits in the mode minus one. */
8599 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8600 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8610 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 1), mode
)
8611 | nonzero_bits_with_known (XEXP (x
, 2), mode
));
8621 /* See the macro definition above. */
8622 #undef cached_num_sign_bit_copies
8624 #define num_sign_bit_copies_with_known(X, M) \
8625 cached_num_sign_bit_copies (X, M, known_x, known_mode, known_ret)
8627 /* The function cached_num_sign_bit_copies is a wrapper around
8628 num_sign_bit_copies1. It avoids exponential behavior in
8629 num_sign_bit_copies1 when X has identical subexpressions on the
8630 first or the second level. */
8633 cached_num_sign_bit_copies (rtx x
, enum machine_mode mode
, rtx known_x
,
8634 enum machine_mode known_mode
,
8635 unsigned int known_ret
)
8637 if (x
== known_x
&& mode
== known_mode
)
8640 /* Try to find identical subexpressions. If found call
8641 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
8642 the precomputed value for the subexpression as KNOWN_RET. */
8644 if (GET_RTX_CLASS (GET_CODE (x
)) == '2'
8645 || GET_RTX_CLASS (GET_CODE (x
)) == 'c')
8647 rtx x0
= XEXP (x
, 0);
8648 rtx x1
= XEXP (x
, 1);
8650 /* Check the first level. */
8653 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8654 num_sign_bit_copies_with_known (x0
, mode
));
8656 /* Check the second level. */
8657 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
8658 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
8659 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8661 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
8662 num_sign_bit_copies_with_known (x1
, mode
));
8664 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
8665 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
8666 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8668 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8669 num_sign_bit_copies_with_known (x0
, mode
));
8672 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
8675 /* Return the number of bits at the high-order end of X that are known to
8676 be equal to the sign bit. X will be used in mode MODE; if MODE is
8677 VOIDmode, X will be used in its own mode. The returned value will always
8678 be between 1 and the number of bits in MODE. */
8681 num_sign_bit_copies1 (rtx x
, enum machine_mode mode
, rtx known_x
,
8682 enum machine_mode known_mode
,
8683 unsigned int known_ret
)
8685 enum rtx_code code
= GET_CODE (x
);
8686 unsigned int bitwidth
;
8687 int num0
, num1
, result
;
8688 unsigned HOST_WIDE_INT nonzero
;
8691 /* If we weren't given a mode, use the mode of X. If the mode is still
8692 VOIDmode, we don't know anything. Likewise if one of the modes is
8695 if (mode
== VOIDmode
)
8696 mode
= GET_MODE (x
);
8698 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8701 bitwidth
= GET_MODE_BITSIZE (mode
);
8703 /* For a smaller object, just ignore the high bits. */
8704 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8706 num0
= num_sign_bit_copies_with_known (x
, GET_MODE (x
));
8708 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8711 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8713 #ifndef WORD_REGISTER_OPERATIONS
8714 /* If this machine does not do all register operations on the entire
8715 register and MODE is wider than the mode of X, we can say nothing
8716 at all about the high-order bits. */
8719 /* Likewise on machines that do, if the mode of the object is smaller
8720 than a word and loads of that size don't sign extend, we can say
8721 nothing about the high order bits. */
8722 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8723 #ifdef LOAD_EXTEND_OP
8724 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8735 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8736 /* If pointers extend signed and this is a pointer in Pmode, say that
8737 all the bits above ptr_mode are known to be sign bit copies. */
8738 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8740 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8743 if (reg_last_set_value
[REGNO (x
)] != 0
8744 && reg_last_set_mode
[REGNO (x
)] == mode
8745 && (reg_last_set_label
[REGNO (x
)] == label_tick
8746 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8747 && REG_N_SETS (REGNO (x
)) == 1
8748 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8750 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8751 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8753 tem
= get_last_value (x
);
8755 return num_sign_bit_copies_with_known (tem
, mode
);
8757 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0
8758 && GET_MODE_BITSIZE (GET_MODE (x
)) == bitwidth
)
8759 return reg_sign_bit_copies
[REGNO (x
)];
8763 #ifdef LOAD_EXTEND_OP
8764 /* Some RISC machines sign-extend all loads of smaller than a word. */
8765 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8766 return MAX (1, ((int) bitwidth
8767 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8772 /* If the constant is negative, take its 1's complement and remask.
8773 Then see how many zero bits we have. */
8774 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8775 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8776 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8777 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8779 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8782 /* If this is a SUBREG for a promoted object that is sign-extended
8783 and we are looking at it in a wider mode, we know that at least the
8784 high-order bits are known to be sign bit copies. */
8786 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8788 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8789 return MAX ((int) bitwidth
8790 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8794 /* For a smaller object, just ignore the high bits. */
8795 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8797 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), VOIDmode
);
8798 return MAX (1, (num0
8799 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8803 #ifdef WORD_REGISTER_OPERATIONS
8804 #ifdef LOAD_EXTEND_OP
8805 /* For paradoxical SUBREGs on machines where all register operations
8806 affect the entire register, just look inside. Note that we are
8807 passing MODE to the recursive call, so the number of sign bit copies
8808 will remain relative to that mode, not the inner mode. */
8810 /* This works only if loads sign extend. Otherwise, if we get a
8811 reload for the inner part, it may be loaded from the stack, and
8812 then we lose all sign bit copies that existed before the store
8815 if ((GET_MODE_SIZE (GET_MODE (x
))
8816 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8817 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8818 && GET_CODE (SUBREG_REG (x
)) == MEM
)
8819 return num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8825 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8826 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8830 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8831 + num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
));
8834 /* For a smaller object, just ignore the high bits. */
8835 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
);
8836 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8840 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8842 case ROTATE
: case ROTATERT
:
8843 /* If we are rotating left by a number of bits less than the number
8844 of sign bit copies, we can just subtract that amount from the
8846 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8847 && INTVAL (XEXP (x
, 1)) >= 0
8848 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
8850 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8851 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8852 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8857 /* In general, this subtracts one sign bit copy. But if the value
8858 is known to be positive, the number of sign bit copies is the
8859 same as that of the input. Finally, if the input has just one bit
8860 that might be nonzero, all the bits are copies of the sign bit. */
8861 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8862 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8863 return num0
> 1 ? num0
- 1 : 1;
8865 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8870 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8875 case IOR
: case AND
: case XOR
:
8876 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8877 /* Logical operations will preserve the number of sign-bit copies.
8878 MIN and MAX operations always return one of the operands. */
8879 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8880 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8881 return MIN (num0
, num1
);
8883 case PLUS
: case MINUS
:
8884 /* For addition and subtraction, we can have a 1-bit carry. However,
8885 if we are subtracting 1 from a positive number, there will not
8886 be such a carry. Furthermore, if the positive number is known to
8887 be 0 or 1, we know the result is either -1 or 0. */
8889 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8890 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8892 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8893 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8894 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8895 : bitwidth
- floor_log2 (nonzero
) - 1);
8898 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8899 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8900 result
= MAX (1, MIN (num0
, num1
) - 1);
8902 #ifdef POINTERS_EXTEND_UNSIGNED
8903 /* If pointers extend signed and this is an addition or subtraction
8904 to a pointer in Pmode, all the bits above ptr_mode are known to be
8906 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8907 && (code
== PLUS
|| code
== MINUS
)
8908 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8909 result
= MAX ((int) (GET_MODE_BITSIZE (Pmode
)
8910 - GET_MODE_BITSIZE (ptr_mode
) + 1),
8916 /* The number of bits of the product is the sum of the number of
8917 bits of both terms. However, unless one of the terms if known
8918 to be positive, we must allow for an additional bit since negating
8919 a negative number can remove one sign bit copy. */
8921 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8922 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8924 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8926 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8927 || (((nonzero_bits (XEXP (x
, 0), mode
)
8928 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8929 && ((nonzero_bits (XEXP (x
, 1), mode
)
8930 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8933 return MAX (1, result
);
8936 /* The result must be <= the first operand. If the first operand
8937 has the high bit set, we know nothing about the number of sign
8939 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8941 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8942 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8945 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8948 /* The result must be <= the second operand. */
8949 return num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8952 /* Similar to unsigned division, except that we have to worry about
8953 the case where the divisor is negative, in which case we have
8955 result
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8957 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8958 || (nonzero_bits (XEXP (x
, 1), mode
)
8959 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8965 result
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8967 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8968 || (nonzero_bits (XEXP (x
, 1), mode
)
8969 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8975 /* Shifts by a constant add to the number of bits equal to the
8977 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8978 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8979 && INTVAL (XEXP (x
, 1)) > 0)
8980 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8985 /* Left shifts destroy copies. */
8986 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8987 || INTVAL (XEXP (x
, 1)) < 0
8988 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
)
8991 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8992 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8995 num0
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8996 num1
= num_sign_bit_copies_with_known (XEXP (x
, 2), mode
);
8997 return MIN (num0
, num1
);
8999 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
9000 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
9001 case GEU
: case GTU
: case LEU
: case LTU
:
9002 case UNORDERED
: case ORDERED
:
9003 /* If the constant is negative, take its 1's complement and remask.
9004 Then see how many zero bits we have. */
9005 nonzero
= STORE_FLAG_VALUE
;
9006 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
9007 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
9008 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
9010 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
9017 /* If we haven't been able to figure it out by one of the above rules,
9018 see if some of the high-order bits are known to be zero. If so,
9019 count those bits and return one less than that amount. If we can't
9020 safely compute the mask for this mode, always return BITWIDTH. */
9022 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
9025 nonzero
= nonzero_bits (x
, mode
);
9026 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
9027 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
9030 /* Return the number of "extended" bits there are in X, when interpreted
9031 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9032 unsigned quantities, this is the number of high-order zero bits.
9033 For signed quantities, this is the number of copies of the sign bit
9034 minus 1. In both case, this function returns the number of "spare"
9035 bits. For example, if two quantities for which this function returns
9036 at least 1 are added, the addition is known not to overflow.
9038 This function will always return 0 unless called during combine, which
9039 implies that it must be called from a define_split. */
9042 extended_count (rtx x
, enum machine_mode mode
, int unsignedp
)
9044 if (nonzero_sign_valid
== 0)
9048 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9049 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
9050 - floor_log2 (nonzero_bits (x
, mode
)))
9052 : num_sign_bit_copies (x
, mode
) - 1);
9055 /* This function is called from `simplify_shift_const' to merge two
9056 outer operations. Specifically, we have already found that we need
9057 to perform operation *POP0 with constant *PCONST0 at the outermost
9058 position. We would now like to also perform OP1 with constant CONST1
9059 (with *POP0 being done last).
9061 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9062 the resulting operation. *PCOMP_P is set to 1 if we would need to
9063 complement the innermost operand, otherwise it is unchanged.
9065 MODE is the mode in which the operation will be done. No bits outside
9066 the width of this mode matter. It is assumed that the width of this mode
9067 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9069 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
9070 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9071 result is simply *PCONST0.
9073 If the resulting operation cannot be expressed as one operation, we
9074 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9077 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
9079 enum rtx_code op0
= *pop0
;
9080 HOST_WIDE_INT const0
= *pconst0
;
9082 const0
&= GET_MODE_MASK (mode
);
9083 const1
&= GET_MODE_MASK (mode
);
9085 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9089 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
9092 if (op1
== NIL
|| op0
== SET
)
9095 else if (op0
== NIL
)
9096 op0
= op1
, const0
= const1
;
9098 else if (op0
== op1
)
9122 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9123 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9126 /* If the two constants aren't the same, we can't do anything. The
9127 remaining six cases can all be done. */
9128 else if (const0
!= const1
)
9136 /* (a & b) | b == b */
9138 else /* op1 == XOR */
9139 /* (a ^ b) | b == a | b */
9145 /* (a & b) ^ b == (~a) & b */
9146 op0
= AND
, *pcomp_p
= 1;
9147 else /* op1 == IOR */
9148 /* (a | b) ^ b == a & ~b */
9149 op0
= AND
, const0
= ~const0
;
9154 /* (a | b) & b == b */
9156 else /* op1 == XOR */
9157 /* (a ^ b) & b) == (~a) & b */
9164 /* Check for NO-OP cases. */
9165 const0
&= GET_MODE_MASK (mode
);
9167 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9169 else if (const0
== 0 && op0
== AND
)
9171 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9175 /* ??? Slightly redundant with the above mask, but not entirely.
9176 Moving this above means we'd have to sign-extend the mode mask
9177 for the final test. */
9178 const0
= trunc_int_for_mode (const0
, mode
);
9186 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9187 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9188 that we started with.
9190 The shift is normally computed in the widest mode we find in VAROP, as
9191 long as it isn't a different number of words than RESULT_MODE. Exceptions
9192 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9195 simplify_shift_const (rtx x
, enum rtx_code code
,
9196 enum machine_mode result_mode
, rtx varop
,
9199 enum rtx_code orig_code
= code
;
9202 enum machine_mode mode
= result_mode
;
9203 enum machine_mode shift_mode
, tmode
;
9204 unsigned int mode_words
9205 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9206 /* We form (outer_op (code varop count) (outer_const)). */
9207 enum rtx_code outer_op
= NIL
;
9208 HOST_WIDE_INT outer_const
= 0;
9210 int complement_p
= 0;
9213 /* Make sure and truncate the "natural" shift on the way in. We don't
9214 want to do this inside the loop as it makes it more difficult to
9216 #ifdef SHIFT_COUNT_TRUNCATED
9217 if (SHIFT_COUNT_TRUNCATED
)
9218 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9221 /* If we were given an invalid count, don't do anything except exactly
9222 what was requested. */
9224 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
9229 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (orig_count
));
9234 /* Unless one of the branches of the `if' in this loop does a `continue',
9235 we will `break' the loop after the `if'. */
9239 /* If we have an operand of (clobber (const_int 0)), just return that
9241 if (GET_CODE (varop
) == CLOBBER
)
9244 /* If we discovered we had to complement VAROP, leave. Making a NOT
9245 here would cause an infinite loop. */
9249 /* Convert ROTATERT to ROTATE. */
9250 if (code
== ROTATERT
)
9252 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
9254 if (VECTOR_MODE_P (result_mode
))
9255 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9257 count
= bitsize
- count
;
9260 /* We need to determine what mode we will do the shift in. If the
9261 shift is a right shift or a ROTATE, we must always do it in the mode
9262 it was originally done in. Otherwise, we can do it in MODE, the
9263 widest mode encountered. */
9265 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9266 ? result_mode
: mode
);
9268 /* Handle cases where the count is greater than the size of the mode
9269 minus 1. For ASHIFT, use the size minus one as the count (this can
9270 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9271 take the count modulo the size. For other shifts, the result is
9274 Since these shifts are being produced by the compiler by combining
9275 multiple operations, each of which are defined, we know what the
9276 result is supposed to be. */
9278 if (count
> (unsigned int) (GET_MODE_BITSIZE (shift_mode
) - 1))
9280 if (code
== ASHIFTRT
)
9281 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9282 else if (code
== ROTATE
|| code
== ROTATERT
)
9283 count
%= GET_MODE_BITSIZE (shift_mode
);
9286 /* We can't simply return zero because there may be an
9294 /* An arithmetic right shift of a quantity known to be -1 or 0
9296 if (code
== ASHIFTRT
9297 && (num_sign_bit_copies (varop
, shift_mode
)
9298 == GET_MODE_BITSIZE (shift_mode
)))
9304 /* If we are doing an arithmetic right shift and discarding all but
9305 the sign bit copies, this is equivalent to doing a shift by the
9306 bitsize minus one. Convert it into that shift because it will often
9307 allow other simplifications. */
9309 if (code
== ASHIFTRT
9310 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9311 >= GET_MODE_BITSIZE (shift_mode
)))
9312 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9314 /* We simplify the tests below and elsewhere by converting
9315 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9316 `make_compound_operation' will convert it to an ASHIFTRT for
9317 those machines (such as VAX) that don't have an LSHIFTRT. */
9318 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9320 && ((nonzero_bits (varop
, shift_mode
)
9321 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9325 if (code
== LSHIFTRT
9326 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9327 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9330 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9331 && !((nonzero_bits (varop
, shift_mode
) << count
)
9332 & GET_MODE_MASK (shift_mode
)))
9335 switch (GET_CODE (varop
))
9341 new = expand_compound_operation (varop
);
9350 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9351 minus the width of a smaller mode, we can do this with a
9352 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9353 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9354 && ! mode_dependent_address_p (XEXP (varop
, 0))
9355 && ! MEM_VOLATILE_P (varop
)
9356 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9357 MODE_INT
, 1)) != BLKmode
)
9359 new = adjust_address_nv (varop
, tmode
,
9360 BYTES_BIG_ENDIAN
? 0
9361 : count
/ BITS_PER_UNIT
);
9363 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9364 : ZERO_EXTEND
, mode
, new);
9371 /* Similar to the case above, except that we can only do this if
9372 the resulting mode is the same as that of the underlying
9373 MEM and adjust the address depending on the *bits* endianness
9374 because of the way that bit-field extract insns are defined. */
9375 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9376 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9377 MODE_INT
, 1)) != BLKmode
9378 && tmode
== GET_MODE (XEXP (varop
, 0)))
9380 if (BITS_BIG_ENDIAN
)
9381 new = XEXP (varop
, 0);
9384 new = copy_rtx (XEXP (varop
, 0));
9385 SUBST (XEXP (new, 0),
9386 plus_constant (XEXP (new, 0),
9387 count
/ BITS_PER_UNIT
));
9390 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9391 : ZERO_EXTEND
, mode
, new);
9398 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9399 the same number of words as what we've seen so far. Then store
9400 the widest mode in MODE. */
9401 if (subreg_lowpart_p (varop
)
9402 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9403 > GET_MODE_SIZE (GET_MODE (varop
)))
9404 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9405 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9408 varop
= SUBREG_REG (varop
);
9409 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9410 mode
= GET_MODE (varop
);
9416 /* Some machines use MULT instead of ASHIFT because MULT
9417 is cheaper. But it is still better on those machines to
9418 merge two shifts into one. */
9419 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9420 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9423 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9424 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9430 /* Similar, for when divides are cheaper. */
9431 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9432 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9435 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9436 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9442 /* If we are extracting just the sign bit of an arithmetic
9443 right shift, that shift is not needed. However, the sign
9444 bit of a wider mode may be different from what would be
9445 interpreted as the sign bit in a narrower mode, so, if
9446 the result is narrower, don't discard the shift. */
9447 if (code
== LSHIFTRT
9448 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9449 && (GET_MODE_BITSIZE (result_mode
)
9450 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9452 varop
= XEXP (varop
, 0);
9456 /* ... fall through ... */
9461 /* Here we have two nested shifts. The result is usually the
9462 AND of a new shift with a mask. We compute the result below. */
9463 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9464 && INTVAL (XEXP (varop
, 1)) >= 0
9465 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9466 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9467 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9469 enum rtx_code first_code
= GET_CODE (varop
);
9470 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9471 unsigned HOST_WIDE_INT mask
;
9474 /* We have one common special case. We can't do any merging if
9475 the inner code is an ASHIFTRT of a smaller mode. However, if
9476 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9477 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9478 we can convert it to
9479 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9480 This simplifies certain SIGN_EXTEND operations. */
9481 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9482 && count
== (unsigned int)
9483 (GET_MODE_BITSIZE (result_mode
)
9484 - GET_MODE_BITSIZE (GET_MODE (varop
))))
9486 /* C3 has the low-order C1 bits zero. */
9488 mask
= (GET_MODE_MASK (mode
)
9489 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9491 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9492 XEXP (varop
, 0), mask
);
9493 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9495 count
= first_count
;
9500 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9501 than C1 high-order bits equal to the sign bit, we can convert
9502 this to either an ASHIFT or an ASHIFTRT depending on the
9505 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9507 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9508 && GET_MODE (varop
) == shift_mode
9509 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9512 varop
= XEXP (varop
, 0);
9514 signed_count
= count
- first_count
;
9515 if (signed_count
< 0)
9516 count
= -signed_count
, code
= ASHIFT
;
9518 count
= signed_count
;
9523 /* There are some cases we can't do. If CODE is ASHIFTRT,
9524 we can only do this if FIRST_CODE is also ASHIFTRT.
9526 We can't do the case when CODE is ROTATE and FIRST_CODE is
9529 If the mode of this shift is not the mode of the outer shift,
9530 we can't do this if either shift is a right shift or ROTATE.
9532 Finally, we can't do any of these if the mode is too wide
9533 unless the codes are the same.
9535 Handle the case where the shift codes are the same
9538 if (code
== first_code
)
9540 if (GET_MODE (varop
) != result_mode
9541 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9545 count
+= first_count
;
9546 varop
= XEXP (varop
, 0);
9550 if (code
== ASHIFTRT
9551 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9552 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9553 || (GET_MODE (varop
) != result_mode
9554 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9555 || first_code
== ROTATE
9556 || code
== ROTATE
)))
9559 /* To compute the mask to apply after the shift, shift the
9560 nonzero bits of the inner shift the same way the
9561 outer shift will. */
9563 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9566 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9569 /* Give up if we can't compute an outer operation to use. */
9571 || GET_CODE (mask_rtx
) != CONST_INT
9572 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9574 result_mode
, &complement_p
))
9577 /* If the shifts are in the same direction, we add the
9578 counts. Otherwise, we subtract them. */
9579 signed_count
= count
;
9580 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9581 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9582 signed_count
+= first_count
;
9584 signed_count
-= first_count
;
9586 /* If COUNT is positive, the new shift is usually CODE,
9587 except for the two exceptions below, in which case it is
9588 FIRST_CODE. If the count is negative, FIRST_CODE should
9590 if (signed_count
> 0
9591 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9592 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9593 code
= first_code
, count
= signed_count
;
9594 else if (signed_count
< 0)
9595 code
= first_code
, count
= -signed_count
;
9597 count
= signed_count
;
9599 varop
= XEXP (varop
, 0);
9603 /* If we have (A << B << C) for any shift, we can convert this to
9604 (A << C << B). This wins if A is a constant. Only try this if
9605 B is not a constant. */
9607 else if (GET_CODE (varop
) == code
9608 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9610 = simplify_binary_operation (code
, mode
,
9614 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9621 /* Make this fit the case below. */
9622 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9623 GEN_INT (GET_MODE_MASK (mode
)));
9629 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9630 with C the size of VAROP - 1 and the shift is logical if
9631 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9632 we have an (le X 0) operation. If we have an arithmetic shift
9633 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9634 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9636 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9637 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9638 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9639 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9640 && count
== (unsigned int)
9641 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9642 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9645 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9648 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9649 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9654 /* If we have (shift (logical)), move the logical to the outside
9655 to allow it to possibly combine with another logical and the
9656 shift to combine with another shift. This also canonicalizes to
9657 what a ZERO_EXTRACT looks like. Also, some machines have
9658 (and (shift)) insns. */
9660 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9661 && (new = simplify_binary_operation (code
, result_mode
,
9663 GEN_INT (count
))) != 0
9664 && GET_CODE (new) == CONST_INT
9665 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9666 INTVAL (new), result_mode
, &complement_p
))
9668 varop
= XEXP (varop
, 0);
9672 /* If we can't do that, try to simplify the shift in each arm of the
9673 logical expression, make a new logical expression, and apply
9674 the inverse distributive law. */
9676 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9677 XEXP (varop
, 0), count
);
9678 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9679 XEXP (varop
, 1), count
);
9681 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9682 varop
= apply_distributive_law (varop
);
9689 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9690 says that the sign bit can be tested, FOO has mode MODE, C is
9691 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9692 that may be nonzero. */
9693 if (code
== LSHIFTRT
9694 && XEXP (varop
, 1) == const0_rtx
9695 && GET_MODE (XEXP (varop
, 0)) == result_mode
9696 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9697 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9698 && ((STORE_FLAG_VALUE
9699 & ((HOST_WIDE_INT
) 1
9700 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9701 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9702 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9703 (HOST_WIDE_INT
) 1, result_mode
,
9706 varop
= XEXP (varop
, 0);
9713 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9714 than the number of bits in the mode is equivalent to A. */
9715 if (code
== LSHIFTRT
9716 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9717 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9719 varop
= XEXP (varop
, 0);
9724 /* NEG commutes with ASHIFT since it is multiplication. Move the
9725 NEG outside to allow shifts to combine. */
9727 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9728 (HOST_WIDE_INT
) 0, result_mode
,
9731 varop
= XEXP (varop
, 0);
9737 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9738 is one less than the number of bits in the mode is
9739 equivalent to (xor A 1). */
9740 if (code
== LSHIFTRT
9741 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9742 && XEXP (varop
, 1) == constm1_rtx
9743 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9744 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9745 (HOST_WIDE_INT
) 1, result_mode
,
9749 varop
= XEXP (varop
, 0);
9753 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9754 that might be nonzero in BAR are those being shifted out and those
9755 bits are known zero in FOO, we can replace the PLUS with FOO.
9756 Similarly in the other operand order. This code occurs when
9757 we are computing the size of a variable-size array. */
9759 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9760 && count
< HOST_BITS_PER_WIDE_INT
9761 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9762 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9763 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9765 varop
= XEXP (varop
, 0);
9768 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9769 && count
< HOST_BITS_PER_WIDE_INT
9770 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9771 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9773 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9774 & nonzero_bits (XEXP (varop
, 1),
9777 varop
= XEXP (varop
, 1);
9781 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9783 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9784 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9786 GEN_INT (count
))) != 0
9787 && GET_CODE (new) == CONST_INT
9788 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9789 INTVAL (new), result_mode
, &complement_p
))
9791 varop
= XEXP (varop
, 0);
9797 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9798 with C the size of VAROP - 1 and the shift is logical if
9799 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9800 we have a (gt X 0) operation. If the shift is arithmetic with
9801 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9802 we have a (neg (gt X 0)) operation. */
9804 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9805 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9806 && count
== (unsigned int)
9807 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9808 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9809 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9810 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (varop
, 0), 1))
9812 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9815 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9818 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9819 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9826 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9827 if the truncate does not affect the value. */
9828 if (code
== LSHIFTRT
9829 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9830 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9831 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9832 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9833 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9835 rtx varop_inner
= XEXP (varop
, 0);
9838 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9839 XEXP (varop_inner
, 0),
9841 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9842 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9855 /* We need to determine what mode to do the shift in. If the shift is
9856 a right shift or ROTATE, we must always do it in the mode it was
9857 originally done in. Otherwise, we can do it in MODE, the widest mode
9858 encountered. The code we care about is that of the shift that will
9859 actually be done, not the shift that was originally requested. */
9861 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9862 ? result_mode
: mode
);
9864 /* We have now finished analyzing the shift. The result should be
9865 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9866 OUTER_OP is non-NIL, it is an operation that needs to be applied
9867 to the result of the shift. OUTER_CONST is the relevant constant,
9868 but we must turn off all bits turned off in the shift.
9870 If we were passed a value for X, see if we can use any pieces of
9871 it. If not, make new rtx. */
9873 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9874 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9875 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == count
)
9876 const_rtx
= XEXP (x
, 1);
9878 const_rtx
= GEN_INT (count
);
9880 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9881 && GET_MODE (XEXP (x
, 0)) == shift_mode
9882 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9883 varop
= XEXP (x
, 0);
9884 else if (GET_MODE (varop
) != shift_mode
)
9885 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
9887 /* If we can't make the SUBREG, try to return what we were given. */
9888 if (GET_CODE (varop
) == CLOBBER
)
9889 return x
? x
: varop
;
9891 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9895 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9897 /* If we have an outer operation and we just made a shift, it is
9898 possible that we could have simplified the shift were it not
9899 for the outer operation. So try to do the simplification
9902 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9903 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9904 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9905 INTVAL (XEXP (x
, 1)));
9907 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9908 turn off all the bits that the shift would have turned off. */
9909 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9910 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9911 GET_MODE_MASK (result_mode
) >> orig_count
);
9913 /* Do the remainder of the processing in RESULT_MODE. */
9914 x
= gen_lowpart_for_combine (result_mode
, x
);
9916 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9919 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9921 if (outer_op
!= NIL
)
9923 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9924 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9926 if (outer_op
== AND
)
9927 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9928 else if (outer_op
== SET
)
9929 /* This means that we have determined that the result is
9930 equivalent to a constant. This should be rare. */
9931 x
= GEN_INT (outer_const
);
9932 else if (GET_RTX_CLASS (outer_op
) == '1')
9933 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9935 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9941 /* Like recog, but we receive the address of a pointer to a new pattern.
9942 We try to match the rtx that the pointer points to.
9943 If that fails, we may try to modify or replace the pattern,
9944 storing the replacement into the same pointer object.
9946 Modifications include deletion or addition of CLOBBERs.
9948 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9949 the CLOBBERs are placed.
9951 The value is the final insn code from the pattern ultimately matched,
9955 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
9958 int insn_code_number
;
9959 int num_clobbers_to_add
= 0;
9964 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9965 we use to indicate that something didn't match. If we find such a
9966 thing, force rejection. */
9967 if (GET_CODE (pat
) == PARALLEL
)
9968 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9969 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9970 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9973 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9974 instruction for pattern recognition. */
9975 dummy_insn
= shallow_copy_rtx (insn
);
9976 PATTERN (dummy_insn
) = pat
;
9977 REG_NOTES (dummy_insn
) = 0;
9979 insn_code_number
= recog (pat
, dummy_insn
, &num_clobbers_to_add
);
9981 /* If it isn't, there is the possibility that we previously had an insn
9982 that clobbered some register as a side effect, but the combined
9983 insn doesn't need to do that. So try once more without the clobbers
9984 unless this represents an ASM insn. */
9986 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9987 && GET_CODE (pat
) == PARALLEL
)
9991 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9992 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9995 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9999 SUBST_INT (XVECLEN (pat
, 0), pos
);
10002 pat
= XVECEXP (pat
, 0, 0);
10004 PATTERN (dummy_insn
) = pat
;
10005 insn_code_number
= recog (pat
, dummy_insn
, &num_clobbers_to_add
);
10008 /* Recognize all noop sets, these will be killed by followup pass. */
10009 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10010 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10012 /* If we had any clobbers to add, make a new pattern than contains
10013 them. Then check to make sure that all of them are dead. */
10014 if (num_clobbers_to_add
)
10016 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10017 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10018 ? (XVECLEN (pat
, 0)
10019 + num_clobbers_to_add
)
10020 : num_clobbers_to_add
+ 1));
10022 if (GET_CODE (pat
) == PARALLEL
)
10023 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10024 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10026 XVECEXP (newpat
, 0, 0) = pat
;
10028 add_clobbers (newpat
, insn_code_number
);
10030 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10031 i
< XVECLEN (newpat
, 0); i
++)
10033 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
10034 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10036 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
10037 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
10045 return insn_code_number
;
10048 /* Like gen_lowpart but for use by combine. In combine it is not possible
10049 to create any new pseudoregs. However, it is safe to create
10050 invalid memory addresses, because combine will try to recognize
10051 them and all they will do is make the combine attempt fail.
10053 If for some reason this cannot do its job, an rtx
10054 (clobber (const_int 0)) is returned.
10055 An insn containing that will not be recognized. */
10060 gen_lowpart_for_combine (enum machine_mode mode
, rtx x
)
10064 if (GET_MODE (x
) == mode
)
10067 /* Return identity if this is a CONST or symbolic
10070 && (GET_CODE (x
) == CONST
10071 || GET_CODE (x
) == SYMBOL_REF
10072 || GET_CODE (x
) == LABEL_REF
))
10075 /* We can only support MODE being wider than a word if X is a
10076 constant integer or has a mode the same size. */
10078 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
10079 && ! ((GET_MODE (x
) == VOIDmode
10080 && (GET_CODE (x
) == CONST_INT
10081 || GET_CODE (x
) == CONST_DOUBLE
))
10082 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
10083 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10085 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10086 won't know what to do. So we will strip off the SUBREG here and
10087 process normally. */
10088 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
10090 x
= SUBREG_REG (x
);
10091 if (GET_MODE (x
) == mode
)
10095 result
= gen_lowpart_common (mode
, x
);
10096 #ifdef CANNOT_CHANGE_MODE_CLASS
10098 && GET_CODE (result
) == SUBREG
10099 && GET_CODE (SUBREG_REG (result
)) == REG
10100 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
)
10101 bitmap_set_bit (&subregs_of_mode
, REGNO (SUBREG_REG (result
))
10103 + GET_MODE (result
));
10109 if (GET_CODE (x
) == MEM
)
10113 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10115 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
10116 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10118 /* If we want to refer to something bigger than the original memref,
10119 generate a perverse subreg instead. That will force a reload
10120 of the original memref X. */
10121 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
10122 return gen_rtx_SUBREG (mode
, x
, 0);
10124 if (WORDS_BIG_ENDIAN
)
10125 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
10126 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
10128 if (BYTES_BIG_ENDIAN
)
10130 /* Adjust the address so that the address-after-the-data is
10132 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
10133 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
10136 return adjust_address_nv (x
, mode
, offset
);
10139 /* If X is a comparison operator, rewrite it in a new mode. This
10140 probably won't match, but may allow further simplifications. */
10141 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
10142 return gen_rtx_fmt_ee (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
10144 /* If we couldn't simplify X any other way, just enclose it in a
10145 SUBREG. Normally, this SUBREG won't match, but some patterns may
10146 include an explicit SUBREG or we may simplify it further in combine. */
10151 enum machine_mode sub_mode
= GET_MODE (x
);
10153 offset
= subreg_lowpart_offset (mode
, sub_mode
);
10154 if (sub_mode
== VOIDmode
)
10156 sub_mode
= int_mode_for_mode (mode
);
10157 x
= gen_lowpart_common (sub_mode
, x
);
10159 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
10161 res
= simplify_gen_subreg (mode
, x
, sub_mode
, offset
);
10164 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10168 /* These routines make binary and unary operations by first seeing if they
10169 fold; if not, a new expression is allocated. */
10172 gen_binary (enum rtx_code code
, enum machine_mode mode
, rtx op0
, rtx op1
)
10177 if (GET_CODE (op0
) == CLOBBER
)
10179 else if (GET_CODE (op1
) == CLOBBER
)
10182 if (GET_RTX_CLASS (code
) == 'c'
10183 && swap_commutative_operands_p (op0
, op1
))
10184 tem
= op0
, op0
= op1
, op1
= tem
;
10186 if (GET_RTX_CLASS (code
) == '<')
10188 enum machine_mode op_mode
= GET_MODE (op0
);
10190 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10191 just (REL_OP X Y). */
10192 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
10194 op1
= XEXP (op0
, 1);
10195 op0
= XEXP (op0
, 0);
10196 op_mode
= GET_MODE (op0
);
10199 if (op_mode
== VOIDmode
)
10200 op_mode
= GET_MODE (op1
);
10201 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
10204 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
10209 /* Put complex operands first and constants second. */
10210 if (GET_RTX_CLASS (code
) == 'c'
10211 && swap_commutative_operands_p (op0
, op1
))
10212 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
10214 /* If we are turning off bits already known off in OP0, we need not do
10216 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
10217 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10218 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
10221 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
10224 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10225 comparison code that will be tested.
10227 The result is a possibly different comparison code to use. *POP0 and
10228 *POP1 may be updated.
10230 It is possible that we might detect that a comparison is either always
10231 true or always false. However, we do not perform general constant
10232 folding in combine, so this knowledge isn't useful. Such tautologies
10233 should have been detected earlier. Hence we ignore all such cases. */
10235 static enum rtx_code
10236 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
10242 enum machine_mode mode
, tmode
;
10244 /* Try a few ways of applying the same transformation to both operands. */
10247 #ifndef WORD_REGISTER_OPERATIONS
10248 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10249 so check specially. */
10250 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10251 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10252 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10253 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10254 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10255 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10256 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10257 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10258 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10259 && XEXP (op0
, 1) == XEXP (op1
, 1)
10260 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10261 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
10262 && (INTVAL (XEXP (op0
, 1))
10263 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10264 - (GET_MODE_BITSIZE
10265 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10267 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10268 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10272 /* If both operands are the same constant shift, see if we can ignore the
10273 shift. We can if the shift is a rotate or if the bits shifted out of
10274 this shift are known to be zero for both inputs and if the type of
10275 comparison is compatible with the shift. */
10276 if (GET_CODE (op0
) == GET_CODE (op1
)
10277 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10278 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10279 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10280 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10281 || (GET_CODE (op0
) == ASHIFTRT
10282 && (code
!= GTU
&& code
!= LTU
10283 && code
!= GEU
&& code
!= LEU
)))
10284 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10285 && INTVAL (XEXP (op0
, 1)) >= 0
10286 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10287 && XEXP (op0
, 1) == XEXP (op1
, 1))
10289 enum machine_mode mode
= GET_MODE (op0
);
10290 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10291 int shift_count
= INTVAL (XEXP (op0
, 1));
10293 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10294 mask
&= (mask
>> shift_count
) << shift_count
;
10295 else if (GET_CODE (op0
) == ASHIFT
)
10296 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10298 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10299 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10300 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10305 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10306 SUBREGs are of the same mode, and, in both cases, the AND would
10307 be redundant if the comparison was done in the narrower mode,
10308 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10309 and the operand's possibly nonzero bits are 0xffffff01; in that case
10310 if we only care about QImode, we don't need the AND). This case
10311 occurs if the output mode of an scc insn is not SImode and
10312 STORE_FLAG_VALUE == 1 (e.g., the 386).
10314 Similarly, check for a case where the AND's are ZERO_EXTEND
10315 operations from some narrower mode even though a SUBREG is not
10318 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10319 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10320 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
10322 rtx inner_op0
= XEXP (op0
, 0);
10323 rtx inner_op1
= XEXP (op1
, 0);
10324 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10325 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10328 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10329 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10330 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10331 && (GET_MODE (SUBREG_REG (inner_op0
))
10332 == GET_MODE (SUBREG_REG (inner_op1
)))
10333 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10334 <= HOST_BITS_PER_WIDE_INT
)
10335 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10336 GET_MODE (SUBREG_REG (inner_op0
)))))
10337 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10338 GET_MODE (SUBREG_REG (inner_op1
))))))
10340 op0
= SUBREG_REG (inner_op0
);
10341 op1
= SUBREG_REG (inner_op1
);
10343 /* The resulting comparison is always unsigned since we masked
10344 off the original sign bit. */
10345 code
= unsigned_condition (code
);
10351 for (tmode
= GET_CLASS_NARROWEST_MODE
10352 (GET_MODE_CLASS (GET_MODE (op0
)));
10353 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10354 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10356 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
10357 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
10358 code
= unsigned_condition (code
);
10367 /* If both operands are NOT, we can strip off the outer operation
10368 and adjust the comparison code for swapped operands; similarly for
10369 NEG, except that this must be an equality comparison. */
10370 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10371 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10372 && (code
== EQ
|| code
== NE
)))
10373 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10379 /* If the first operand is a constant, swap the operands and adjust the
10380 comparison code appropriately, but don't do this if the second operand
10381 is already a constant integer. */
10382 if (swap_commutative_operands_p (op0
, op1
))
10384 tem
= op0
, op0
= op1
, op1
= tem
;
10385 code
= swap_condition (code
);
10388 /* We now enter a loop during which we will try to simplify the comparison.
10389 For the most part, we only are concerned with comparisons with zero,
10390 but some things may really be comparisons with zero but not start
10391 out looking that way. */
10393 while (GET_CODE (op1
) == CONST_INT
)
10395 enum machine_mode mode
= GET_MODE (op0
);
10396 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10397 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10398 int equality_comparison_p
;
10399 int sign_bit_comparison_p
;
10400 int unsigned_comparison_p
;
10401 HOST_WIDE_INT const_op
;
10403 /* We only want to handle integral modes. This catches VOIDmode,
10404 CCmode, and the floating-point modes. An exception is that we
10405 can handle VOIDmode if OP0 is a COMPARE or a comparison
10408 if (GET_MODE_CLASS (mode
) != MODE_INT
10409 && ! (mode
== VOIDmode
10410 && (GET_CODE (op0
) == COMPARE
10411 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
10414 /* Get the constant we are comparing against and turn off all bits
10415 not on in our mode. */
10416 const_op
= INTVAL (op1
);
10417 if (mode
!= VOIDmode
)
10418 const_op
= trunc_int_for_mode (const_op
, mode
);
10419 op1
= GEN_INT (const_op
);
10421 /* If we are comparing against a constant power of two and the value
10422 being compared can only have that single bit nonzero (e.g., it was
10423 `and'ed with that bit), we can replace this with a comparison
10426 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10427 || code
== LT
|| code
== LTU
)
10428 && mode_width
<= HOST_BITS_PER_WIDE_INT
10429 && exact_log2 (const_op
) >= 0
10430 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10432 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10433 op1
= const0_rtx
, const_op
= 0;
10436 /* Similarly, if we are comparing a value known to be either -1 or
10437 0 with -1, change it to the opposite comparison against zero. */
10440 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10441 || code
== GEU
|| code
== LTU
)
10442 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10444 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10445 op1
= const0_rtx
, const_op
= 0;
10448 /* Do some canonicalizations based on the comparison code. We prefer
10449 comparisons against zero and then prefer equality comparisons.
10450 If we can reduce the size of a constant, we will do that too. */
10455 /* < C is equivalent to <= (C - 1) */
10459 op1
= GEN_INT (const_op
);
10461 /* ... fall through to LE case below. */
10467 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10471 op1
= GEN_INT (const_op
);
10475 /* If we are doing a <= 0 comparison on a value known to have
10476 a zero sign bit, we can replace this with == 0. */
10477 else if (const_op
== 0
10478 && mode_width
<= HOST_BITS_PER_WIDE_INT
10479 && (nonzero_bits (op0
, mode
)
10480 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10485 /* >= C is equivalent to > (C - 1). */
10489 op1
= GEN_INT (const_op
);
10491 /* ... fall through to GT below. */
10497 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10501 op1
= GEN_INT (const_op
);
10505 /* If we are doing a > 0 comparison on a value known to have
10506 a zero sign bit, we can replace this with != 0. */
10507 else if (const_op
== 0
10508 && mode_width
<= HOST_BITS_PER_WIDE_INT
10509 && (nonzero_bits (op0
, mode
)
10510 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10515 /* < C is equivalent to <= (C - 1). */
10519 op1
= GEN_INT (const_op
);
10521 /* ... fall through ... */
10524 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10525 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10526 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10528 const_op
= 0, op1
= const0_rtx
;
10536 /* unsigned <= 0 is equivalent to == 0 */
10540 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10541 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10542 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10544 const_op
= 0, op1
= const0_rtx
;
10550 /* >= C is equivalent to < (C - 1). */
10554 op1
= GEN_INT (const_op
);
10556 /* ... fall through ... */
10559 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10560 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10561 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10563 const_op
= 0, op1
= const0_rtx
;
10571 /* unsigned > 0 is equivalent to != 0 */
10575 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10576 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10577 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10579 const_op
= 0, op1
= const0_rtx
;
10588 /* Compute some predicates to simplify code below. */
10590 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10591 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10592 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10595 /* If this is a sign bit comparison and we can do arithmetic in
10596 MODE, say that we will only be needing the sign bit of OP0. */
10597 if (sign_bit_comparison_p
10598 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10599 op0
= force_to_mode (op0
, mode
,
10601 << (GET_MODE_BITSIZE (mode
) - 1)),
10604 /* Now try cases based on the opcode of OP0. If none of the cases
10605 does a "continue", we exit this loop immediately after the
10608 switch (GET_CODE (op0
))
10611 /* If we are extracting a single bit from a variable position in
10612 a constant that has only a single bit set and are comparing it
10613 with zero, we can convert this into an equality comparison
10614 between the position and the location of the single bit. */
10616 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
10617 && XEXP (op0
, 1) == const1_rtx
10618 && equality_comparison_p
&& const_op
== 0
10619 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10621 if (BITS_BIG_ENDIAN
)
10623 enum machine_mode new_mode
10624 = mode_for_extraction (EP_extzv
, 1);
10625 if (new_mode
== MAX_MACHINE_MODE
)
10626 i
= BITS_PER_WORD
- 1 - i
;
10630 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10634 op0
= XEXP (op0
, 2);
10638 /* Result is nonzero iff shift count is equal to I. */
10639 code
= reverse_condition (code
);
10643 /* ... fall through ... */
10646 tem
= expand_compound_operation (op0
);
10655 /* If testing for equality, we can take the NOT of the constant. */
10656 if (equality_comparison_p
10657 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10659 op0
= XEXP (op0
, 0);
10664 /* If just looking at the sign bit, reverse the sense of the
10666 if (sign_bit_comparison_p
)
10668 op0
= XEXP (op0
, 0);
10669 code
= (code
== GE
? LT
: GE
);
10675 /* If testing for equality, we can take the NEG of the constant. */
10676 if (equality_comparison_p
10677 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10679 op0
= XEXP (op0
, 0);
10684 /* The remaining cases only apply to comparisons with zero. */
10688 /* When X is ABS or is known positive,
10689 (neg X) is < 0 if and only if X != 0. */
10691 if (sign_bit_comparison_p
10692 && (GET_CODE (XEXP (op0
, 0)) == ABS
10693 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10694 && (nonzero_bits (XEXP (op0
, 0), mode
)
10695 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10697 op0
= XEXP (op0
, 0);
10698 code
= (code
== LT
? NE
: EQ
);
10702 /* If we have NEG of something whose two high-order bits are the
10703 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10704 if (num_sign_bit_copies (op0
, mode
) >= 2)
10706 op0
= XEXP (op0
, 0);
10707 code
= swap_condition (code
);
10713 /* If we are testing equality and our count is a constant, we
10714 can perform the inverse operation on our RHS. */
10715 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10716 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10717 op1
, XEXP (op0
, 1))) != 0)
10719 op0
= XEXP (op0
, 0);
10724 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10725 a particular bit. Convert it to an AND of a constant of that
10726 bit. This will be converted into a ZERO_EXTRACT. */
10727 if (const_op
== 0 && sign_bit_comparison_p
10728 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10729 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10731 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10734 - INTVAL (XEXP (op0
, 1)))));
10735 code
= (code
== LT
? NE
: EQ
);
10739 /* Fall through. */
10742 /* ABS is ignorable inside an equality comparison with zero. */
10743 if (const_op
== 0 && equality_comparison_p
)
10745 op0
= XEXP (op0
, 0);
10751 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10752 to (compare FOO CONST) if CONST fits in FOO's mode and we
10753 are either testing inequality or have an unsigned comparison
10754 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10755 if (! unsigned_comparison_p
10756 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10757 <= HOST_BITS_PER_WIDE_INT
)
10758 && ((unsigned HOST_WIDE_INT
) const_op
10759 < (((unsigned HOST_WIDE_INT
) 1
10760 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10762 op0
= XEXP (op0
, 0);
10768 /* Check for the case where we are comparing A - C1 with C2,
10769 both constants are smaller than 1/2 the maximum positive
10770 value in MODE, and the comparison is equality or unsigned.
10771 In that case, if A is either zero-extended to MODE or has
10772 sufficient sign bits so that the high-order bit in MODE
10773 is a copy of the sign in the inner mode, we can prove that it is
10774 safe to do the operation in the wider mode. This simplifies
10775 many range checks. */
10777 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10778 && subreg_lowpart_p (op0
)
10779 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10780 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10781 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10782 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10783 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10784 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10785 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10786 GET_MODE (SUBREG_REG (op0
)))
10787 & ~GET_MODE_MASK (mode
))
10788 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10789 GET_MODE (SUBREG_REG (op0
)))
10791 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10792 - GET_MODE_BITSIZE (mode
)))))
10794 op0
= SUBREG_REG (op0
);
10798 /* If the inner mode is narrower and we are extracting the low part,
10799 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10800 if (subreg_lowpart_p (op0
)
10801 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10802 /* Fall through */ ;
10806 /* ... fall through ... */
10809 if ((unsigned_comparison_p
|| equality_comparison_p
)
10810 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10811 <= HOST_BITS_PER_WIDE_INT
)
10812 && ((unsigned HOST_WIDE_INT
) const_op
10813 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10815 op0
= XEXP (op0
, 0);
10821 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10822 this for equality comparisons due to pathological cases involving
10824 if (equality_comparison_p
10825 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10826 op1
, XEXP (op0
, 1))))
10828 op0
= XEXP (op0
, 0);
10833 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10834 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10835 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10837 op0
= XEXP (XEXP (op0
, 0), 0);
10838 code
= (code
== LT
? EQ
: NE
);
10844 /* We used to optimize signed comparisons against zero, but that
10845 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10846 arrive here as equality comparisons, or (GEU, LTU) are
10847 optimized away. No need to special-case them. */
10849 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10850 (eq B (minus A C)), whichever simplifies. We can only do
10851 this for equality comparisons due to pathological cases involving
10853 if (equality_comparison_p
10854 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10855 XEXP (op0
, 1), op1
)))
10857 op0
= XEXP (op0
, 0);
10862 if (equality_comparison_p
10863 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10864 XEXP (op0
, 0), op1
)))
10866 op0
= XEXP (op0
, 1);
10871 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10872 of bits in X minus 1, is one iff X > 0. */
10873 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10874 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10875 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10877 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10879 op0
= XEXP (op0
, 1);
10880 code
= (code
== GE
? LE
: GT
);
10886 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10887 if C is zero or B is a constant. */
10888 if (equality_comparison_p
10889 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10890 XEXP (op0
, 1), op1
)))
10892 op0
= XEXP (op0
, 0);
10899 case UNEQ
: case LTGT
:
10900 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10901 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10902 case UNORDERED
: case ORDERED
:
10903 /* We can't do anything if OP0 is a condition code value, rather
10904 than an actual data value. */
10906 || CC0_P (XEXP (op0
, 0))
10907 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10910 /* Get the two operands being compared. */
10911 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10912 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10914 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10916 /* Check for the cases where we simply want the result of the
10917 earlier test or the opposite of that result. */
10918 if (code
== NE
|| code
== EQ
10919 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10920 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10921 && (STORE_FLAG_VALUE
10922 & (((HOST_WIDE_INT
) 1
10923 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10924 && (code
== LT
|| code
== GE
)))
10926 enum rtx_code new_code
;
10927 if (code
== LT
|| code
== NE
)
10928 new_code
= GET_CODE (op0
);
10930 new_code
= combine_reversed_comparison_code (op0
);
10932 if (new_code
!= UNKNOWN
)
10943 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10945 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10946 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10947 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10949 op0
= XEXP (op0
, 1);
10950 code
= (code
== GE
? GT
: LE
);
10956 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10957 will be converted to a ZERO_EXTRACT later. */
10958 if (const_op
== 0 && equality_comparison_p
10959 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10960 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10962 op0
= simplify_and_const_int
10963 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10965 XEXP (XEXP (op0
, 0), 1)),
10966 (HOST_WIDE_INT
) 1);
10970 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10971 zero and X is a comparison and C1 and C2 describe only bits set
10972 in STORE_FLAG_VALUE, we can compare with X. */
10973 if (const_op
== 0 && equality_comparison_p
10974 && mode_width
<= HOST_BITS_PER_WIDE_INT
10975 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10976 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10977 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10978 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10979 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10981 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10982 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10983 if ((~STORE_FLAG_VALUE
& mask
) == 0
10984 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10985 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10986 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10988 op0
= XEXP (XEXP (op0
, 0), 0);
10993 /* If we are doing an equality comparison of an AND of a bit equal
10994 to the sign bit, replace this with a LT or GE comparison of
10995 the underlying value. */
10996 if (equality_comparison_p
10998 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10999 && mode_width
<= HOST_BITS_PER_WIDE_INT
11000 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11001 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11003 op0
= XEXP (op0
, 0);
11004 code
= (code
== EQ
? GE
: LT
);
11008 /* If this AND operation is really a ZERO_EXTEND from a narrower
11009 mode, the constant fits within that mode, and this is either an
11010 equality or unsigned comparison, try to do this comparison in
11011 the narrower mode. */
11012 if ((equality_comparison_p
|| unsigned_comparison_p
)
11013 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11014 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
11015 & GET_MODE_MASK (mode
))
11017 && const_op
>> i
== 0
11018 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
11020 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
11024 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11025 fits in both M1 and M2 and the SUBREG is either paradoxical
11026 or represents the low part, permute the SUBREG and the AND
11028 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
11030 unsigned HOST_WIDE_INT c1
;
11031 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
11032 /* Require an integral mode, to avoid creating something like
11034 if (SCALAR_INT_MODE_P (tmode
)
11035 /* It is unsafe to commute the AND into the SUBREG if the
11036 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11037 not defined. As originally written the upper bits
11038 have a defined value due to the AND operation.
11039 However, if we commute the AND inside the SUBREG then
11040 they no longer have defined values and the meaning of
11041 the code has been changed. */
11043 #ifdef WORD_REGISTER_OPERATIONS
11044 || (mode_width
> GET_MODE_BITSIZE (tmode
)
11045 && mode_width
<= BITS_PER_WORD
)
11047 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
11048 && subreg_lowpart_p (XEXP (op0
, 0))))
11049 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11050 && mode_width
<= HOST_BITS_PER_WIDE_INT
11051 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
11052 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
11053 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
11055 && c1
!= GET_MODE_MASK (tmode
))
11057 op0
= gen_binary (AND
, tmode
,
11058 SUBREG_REG (XEXP (op0
, 0)),
11059 gen_int_mode (c1
, tmode
));
11060 op0
= gen_lowpart_for_combine (mode
, op0
);
11065 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11066 if (const_op
== 0 && equality_comparison_p
11067 && XEXP (op0
, 1) == const1_rtx
11068 && GET_CODE (XEXP (op0
, 0)) == NOT
)
11070 op0
= simplify_and_const_int
11071 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
11072 code
= (code
== NE
? EQ
: NE
);
11076 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11077 (eq (and (lshiftrt X) 1) 0). */
11078 if (const_op
== 0 && equality_comparison_p
11079 && XEXP (op0
, 1) == const1_rtx
11080 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
11081 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == NOT
)
11083 op0
= simplify_and_const_int
11085 gen_rtx_LSHIFTRT (mode
, XEXP (XEXP (XEXP (op0
, 0), 0), 0),
11086 XEXP (XEXP (op0
, 0), 1)),
11087 (HOST_WIDE_INT
) 1);
11088 code
= (code
== NE
? EQ
: NE
);
11094 /* If we have (compare (ashift FOO N) (const_int C)) and
11095 the high order N bits of FOO (N+1 if an inequality comparison)
11096 are known to be zero, we can do this by comparing FOO with C
11097 shifted right N bits so long as the low-order N bits of C are
11099 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11100 && INTVAL (XEXP (op0
, 1)) >= 0
11101 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11102 < HOST_BITS_PER_WIDE_INT
)
11104 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
11105 && mode_width
<= HOST_BITS_PER_WIDE_INT
11106 && (nonzero_bits (XEXP (op0
, 0), mode
)
11107 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11108 + ! equality_comparison_p
))) == 0)
11110 /* We must perform a logical shift, not an arithmetic one,
11111 as we want the top N bits of C to be zero. */
11112 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11114 temp
>>= INTVAL (XEXP (op0
, 1));
11115 op1
= gen_int_mode (temp
, mode
);
11116 op0
= XEXP (op0
, 0);
11120 /* If we are doing a sign bit comparison, it means we are testing
11121 a particular bit. Convert it to the appropriate AND. */
11122 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
11123 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11125 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11128 - INTVAL (XEXP (op0
, 1)))));
11129 code
= (code
== LT
? NE
: EQ
);
11133 /* If this an equality comparison with zero and we are shifting
11134 the low bit to the sign bit, we can convert this to an AND of the
11136 if (const_op
== 0 && equality_comparison_p
11137 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11138 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11141 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11142 (HOST_WIDE_INT
) 1);
11148 /* If this is an equality comparison with zero, we can do this
11149 as a logical shift, which might be much simpler. */
11150 if (equality_comparison_p
&& const_op
== 0
11151 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
11153 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11155 INTVAL (XEXP (op0
, 1)));
11159 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11160 do the comparison in a narrower mode. */
11161 if (! unsigned_comparison_p
11162 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11163 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11164 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11165 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11166 MODE_INT
, 1)) != BLKmode
11167 && (((unsigned HOST_WIDE_INT
) const_op
11168 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11169 <= GET_MODE_MASK (tmode
)))
11171 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
11175 /* Likewise if OP0 is a PLUS of a sign extension with a
11176 constant, which is usually represented with the PLUS
11177 between the shifts. */
11178 if (! unsigned_comparison_p
11179 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11180 && GET_CODE (XEXP (op0
, 0)) == PLUS
11181 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
11182 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11183 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11184 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11185 MODE_INT
, 1)) != BLKmode
11186 && (((unsigned HOST_WIDE_INT
) const_op
11187 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11188 <= GET_MODE_MASK (tmode
)))
11190 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11191 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11192 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
11195 op0
= gen_binary (PLUS
, tmode
,
11196 gen_lowpart_for_combine (tmode
, inner
),
11201 /* ... fall through ... */
11203 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11204 the low order N bits of FOO are known to be zero, we can do this
11205 by comparing FOO with C shifted left N bits so long as no
11206 overflow occurs. */
11207 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11208 && INTVAL (XEXP (op0
, 1)) >= 0
11209 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11210 && mode_width
<= HOST_BITS_PER_WIDE_INT
11211 && (nonzero_bits (XEXP (op0
, 0), mode
)
11212 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
11213 && (((unsigned HOST_WIDE_INT
) const_op
11214 + (GET_CODE (op0
) != LSHIFTRT
11215 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11218 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11220 /* If the shift was logical, then we must make the condition
11222 if (GET_CODE (op0
) == LSHIFTRT
)
11223 code
= unsigned_condition (code
);
11225 const_op
<<= INTVAL (XEXP (op0
, 1));
11226 op1
= GEN_INT (const_op
);
11227 op0
= XEXP (op0
, 0);
11231 /* If we are using this shift to extract just the sign bit, we
11232 can replace this with an LT or GE comparison. */
11234 && (equality_comparison_p
|| sign_bit_comparison_p
)
11235 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11236 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11239 op0
= XEXP (op0
, 0);
11240 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11252 /* Now make any compound operations involved in this comparison. Then,
11253 check for an outmost SUBREG on OP0 that is not doing anything or is
11254 paradoxical. The latter transformation must only be performed when
11255 it is known that the "extra" bits will be the same in op0 and op1 or
11256 that they don't matter. There are three cases to consider:
11258 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11259 care bits and we can assume they have any convenient value. So
11260 making the transformation is safe.
11262 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11263 In this case the upper bits of op0 are undefined. We should not make
11264 the simplification in that case as we do not know the contents of
11267 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11268 NIL. In that case we know those bits are zeros or ones. We must
11269 also be sure that they are the same as the upper bits of op1.
11271 We can never remove a SUBREG for a non-equality comparison because
11272 the sign bit is in a different place in the underlying object. */
11274 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11275 op1
= make_compound_operation (op1
, SET
);
11277 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11278 /* Case 3 above, to sometimes allow (subreg (mem x)), isn't
11280 && GET_CODE (SUBREG_REG (op0
)) == REG
11281 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11282 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11283 && (code
== NE
|| code
== EQ
))
11285 if (GET_MODE_SIZE (GET_MODE (op0
))
11286 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
11288 op0
= SUBREG_REG (op0
);
11289 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
11291 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11292 <= HOST_BITS_PER_WIDE_INT
)
11293 && (nonzero_bits (SUBREG_REG (op0
),
11294 GET_MODE (SUBREG_REG (op0
)))
11295 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11297 tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)), op1
);
11299 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11300 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11301 op0
= SUBREG_REG (op0
), op1
= tem
;
11305 /* We now do the opposite procedure: Some machines don't have compare
11306 insns in all modes. If OP0's mode is an integer mode smaller than a
11307 word and we can't do a compare in that mode, see if there is a larger
11308 mode for which we can do the compare. There are a number of cases in
11309 which we can use the wider mode. */
11311 mode
= GET_MODE (op0
);
11312 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11313 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11314 && ! have_insn_for (COMPARE
, mode
))
11315 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11317 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11318 tmode
= GET_MODE_WIDER_MODE (tmode
))
11319 if (have_insn_for (COMPARE
, tmode
))
11323 /* If the only nonzero bits in OP0 and OP1 are those in the
11324 narrower mode and this is an equality or unsigned comparison,
11325 we can use the wider mode. Similarly for sign-extended
11326 values, in which case it is true for all comparisons. */
11327 zero_extended
= ((code
== EQ
|| code
== NE
11328 || code
== GEU
|| code
== GTU
11329 || code
== LEU
|| code
== LTU
)
11330 && (nonzero_bits (op0
, tmode
)
11331 & ~GET_MODE_MASK (mode
)) == 0
11332 && ((GET_CODE (op1
) == CONST_INT
11333 || (nonzero_bits (op1
, tmode
)
11334 & ~GET_MODE_MASK (mode
)) == 0)));
11337 || ((num_sign_bit_copies (op0
, tmode
)
11338 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11339 - GET_MODE_BITSIZE (mode
)))
11340 && (num_sign_bit_copies (op1
, tmode
)
11341 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11342 - GET_MODE_BITSIZE (mode
)))))
11344 /* If OP0 is an AND and we don't have an AND in MODE either,
11345 make a new AND in the proper mode. */
11346 if (GET_CODE (op0
) == AND
11347 && !have_insn_for (AND
, mode
))
11348 op0
= gen_binary (AND
, tmode
,
11349 gen_lowpart_for_combine (tmode
,
11351 gen_lowpart_for_combine (tmode
,
11354 op0
= gen_lowpart_for_combine (tmode
, op0
);
11355 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
11356 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
11357 op1
= gen_lowpart_for_combine (tmode
, op1
);
11361 /* If this is a test for negative, we can make an explicit
11362 test of the sign bit. */
11364 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11365 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11367 op0
= gen_binary (AND
, tmode
,
11368 gen_lowpart_for_combine (tmode
, op0
),
11369 GEN_INT ((HOST_WIDE_INT
) 1
11370 << (GET_MODE_BITSIZE (mode
) - 1)));
11371 code
= (code
== LT
) ? NE
: EQ
;
11376 #ifdef CANONICALIZE_COMPARISON
11377 /* If this machine only supports a subset of valid comparisons, see if we
11378 can convert an unsupported one into a supported one. */
11379 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11388 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11389 searching backward. */
11390 static enum rtx_code
11391 combine_reversed_comparison_code (rtx exp
)
11393 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
11396 if (code1
!= UNKNOWN
11397 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
11399 /* Otherwise try and find where the condition codes were last set and
11401 x
= get_last_value (XEXP (exp
, 0));
11402 if (!x
|| GET_CODE (x
) != COMPARE
)
11404 return reversed_comparison_code_parts (GET_CODE (exp
),
11405 XEXP (x
, 0), XEXP (x
, 1), NULL
);
11408 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11409 Return NULL_RTX in case we fail to do the reversal. */
11411 reversed_comparison (rtx exp
, enum machine_mode mode
, rtx op0
, rtx op1
)
11413 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
11414 if (reversed_code
== UNKNOWN
)
11417 return gen_binary (reversed_code
, mode
, op0
, op1
);
11420 /* Utility function for following routine. Called when X is part of a value
11421 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11422 for each register mentioned. Similar to mention_regs in cse.c */
11425 update_table_tick (rtx x
)
11427 enum rtx_code code
= GET_CODE (x
);
11428 const char *fmt
= GET_RTX_FORMAT (code
);
11433 unsigned int regno
= REGNO (x
);
11434 unsigned int endregno
11435 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11436 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11439 for (r
= regno
; r
< endregno
; r
++)
11440 reg_last_set_table_tick
[r
] = label_tick
;
11445 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11446 /* Note that we can't have an "E" in values stored; see
11447 get_last_value_validate. */
11450 /* Check for identical subexpressions. If x contains
11451 identical subexpression we only have to traverse one of
11454 && (GET_RTX_CLASS (code
) == '2'
11455 || GET_RTX_CLASS (code
) == 'c'))
11457 /* Note that at this point x1 has already been
11459 rtx x0
= XEXP (x
, 0);
11460 rtx x1
= XEXP (x
, 1);
11462 /* If x0 and x1 are identical then there is no need to
11467 /* If x0 is identical to a subexpression of x1 then while
11468 processing x1, x0 has already been processed. Thus we
11469 are done with x. */
11470 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11471 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11472 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11475 /* If x1 is identical to a subexpression of x0 then we
11476 still have to process the rest of x0. */
11477 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11478 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11479 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11481 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
11486 update_table_tick (XEXP (x
, i
));
11490 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11491 are saying that the register is clobbered and we no longer know its
11492 value. If INSN is zero, don't update reg_last_set; this is only permitted
11493 with VALUE also zero and is used to invalidate the register. */
11496 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
11498 unsigned int regno
= REGNO (reg
);
11499 unsigned int endregno
11500 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11501 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
11504 /* If VALUE contains REG and we have a previous value for REG, substitute
11505 the previous value. */
11506 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11510 /* Set things up so get_last_value is allowed to see anything set up to
11512 subst_low_cuid
= INSN_CUID (insn
);
11513 tem
= get_last_value (reg
);
11515 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11516 it isn't going to be useful and will take a lot of time to process,
11517 so just use the CLOBBER. */
11521 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
11522 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
11523 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11524 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11525 tem
= XEXP (tem
, 0);
11527 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11531 /* For each register modified, show we don't know its value, that
11532 we don't know about its bitwise content, that its value has been
11533 updated, and that we don't know the location of the death of the
11535 for (i
= regno
; i
< endregno
; i
++)
11538 reg_last_set
[i
] = insn
;
11540 reg_last_set_value
[i
] = 0;
11541 reg_last_set_mode
[i
] = 0;
11542 reg_last_set_nonzero_bits
[i
] = 0;
11543 reg_last_set_sign_bit_copies
[i
] = 0;
11544 reg_last_death
[i
] = 0;
11547 /* Mark registers that are being referenced in this value. */
11549 update_table_tick (value
);
11551 /* Now update the status of each register being set.
11552 If someone is using this register in this block, set this register
11553 to invalid since we will get confused between the two lives in this
11554 basic block. This makes using this register always invalid. In cse, we
11555 scan the table to invalidate all entries using this register, but this
11556 is too much work for us. */
11558 for (i
= regno
; i
< endregno
; i
++)
11560 reg_last_set_label
[i
] = label_tick
;
11561 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11562 reg_last_set_invalid
[i
] = 1;
11564 reg_last_set_invalid
[i
] = 0;
11567 /* The value being assigned might refer to X (like in "x++;"). In that
11568 case, we must replace it with (clobber (const_int 0)) to prevent
11570 if (value
&& ! get_last_value_validate (&value
, insn
,
11571 reg_last_set_label
[regno
], 0))
11573 value
= copy_rtx (value
);
11574 if (! get_last_value_validate (&value
, insn
,
11575 reg_last_set_label
[regno
], 1))
11579 /* For the main register being modified, update the value, the mode, the
11580 nonzero bits, and the number of sign bit copies. */
11582 reg_last_set_value
[regno
] = value
;
11586 enum machine_mode mode
= GET_MODE (reg
);
11587 subst_low_cuid
= INSN_CUID (insn
);
11588 reg_last_set_mode
[regno
] = mode
;
11589 if (GET_MODE_CLASS (mode
) == MODE_INT
11590 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11591 mode
= nonzero_bits_mode
;
11592 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, mode
);
11593 reg_last_set_sign_bit_copies
[regno
]
11594 = num_sign_bit_copies (value
, GET_MODE (reg
));
11598 /* Called via note_stores from record_dead_and_set_regs to handle one
11599 SET or CLOBBER in an insn. DATA is the instruction in which the
11600 set is occurring. */
11603 record_dead_and_set_regs_1 (rtx dest
, rtx setter
, void *data
)
11605 rtx record_dead_insn
= (rtx
) data
;
11607 if (GET_CODE (dest
) == SUBREG
)
11608 dest
= SUBREG_REG (dest
);
11610 if (GET_CODE (dest
) == REG
)
11612 /* If we are setting the whole register, we know its value. Otherwise
11613 show that we don't know the value. We can handle SUBREG in
11615 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11616 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11617 else if (GET_CODE (setter
) == SET
11618 && GET_CODE (SET_DEST (setter
)) == SUBREG
11619 && SUBREG_REG (SET_DEST (setter
)) == dest
11620 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11621 && subreg_lowpart_p (SET_DEST (setter
)))
11622 record_value_for_reg (dest
, record_dead_insn
,
11623 gen_lowpart_for_combine (GET_MODE (dest
),
11624 SET_SRC (setter
)));
11626 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11628 else if (GET_CODE (dest
) == MEM
11629 /* Ignore pushes, they clobber nothing. */
11630 && ! push_operand (dest
, GET_MODE (dest
)))
11631 mem_last_set
= INSN_CUID (record_dead_insn
);
11634 /* Update the records of when each REG was most recently set or killed
11635 for the things done by INSN. This is the last thing done in processing
11636 INSN in the combiner loop.
11638 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11639 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11640 and also the similar information mem_last_set (which insn most recently
11641 modified memory) and last_call_cuid (which insn was the most recent
11642 subroutine call). */
11645 record_dead_and_set_regs (rtx insn
)
11650 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11652 if (REG_NOTE_KIND (link
) == REG_DEAD
11653 && GET_CODE (XEXP (link
, 0)) == REG
)
11655 unsigned int regno
= REGNO (XEXP (link
, 0));
11656 unsigned int endregno
11657 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11658 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
11661 for (i
= regno
; i
< endregno
; i
++)
11662 reg_last_death
[i
] = insn
;
11664 else if (REG_NOTE_KIND (link
) == REG_INC
)
11665 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11668 if (GET_CODE (insn
) == CALL_INSN
)
11670 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11671 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11673 reg_last_set_value
[i
] = 0;
11674 reg_last_set_mode
[i
] = 0;
11675 reg_last_set_nonzero_bits
[i
] = 0;
11676 reg_last_set_sign_bit_copies
[i
] = 0;
11677 reg_last_death
[i
] = 0;
11680 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11682 /* Don't bother recording what this insn does. It might set the
11683 return value register, but we can't combine into a call
11684 pattern anyway, so there's no point trying (and it may cause
11685 a crash, if e.g. we wind up asking for last_set_value of a
11686 SUBREG of the return value register). */
11690 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11693 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11694 register present in the SUBREG, so for each such SUBREG go back and
11695 adjust nonzero and sign bit information of the registers that are
11696 known to have some zero/sign bits set.
11698 This is needed because when combine blows the SUBREGs away, the
11699 information on zero/sign bits is lost and further combines can be
11700 missed because of that. */
11703 record_promoted_value (rtx insn
, rtx subreg
)
11706 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11707 enum machine_mode mode
= GET_MODE (subreg
);
11709 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11712 for (links
= LOG_LINKS (insn
); links
;)
11714 insn
= XEXP (links
, 0);
11715 set
= single_set (insn
);
11717 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11718 || REGNO (SET_DEST (set
)) != regno
11719 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11721 links
= XEXP (links
, 1);
11725 if (reg_last_set
[regno
] == insn
)
11727 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11728 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11731 if (GET_CODE (SET_SRC (set
)) == REG
)
11733 regno
= REGNO (SET_SRC (set
));
11734 links
= LOG_LINKS (insn
);
11741 /* Scan X for promoted SUBREGs. For each one found,
11742 note what it implies to the registers used in it. */
11745 check_promoted_subreg (rtx insn
, rtx x
)
11747 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11748 && GET_CODE (SUBREG_REG (x
)) == REG
)
11749 record_promoted_value (insn
, x
);
11752 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11755 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11759 check_promoted_subreg (insn
, XEXP (x
, i
));
11763 if (XVEC (x
, i
) != 0)
11764 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11765 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11771 /* Utility routine for the following function. Verify that all the registers
11772 mentioned in *LOC are valid when *LOC was part of a value set when
11773 label_tick == TICK. Return 0 if some are not.
11775 If REPLACE is nonzero, replace the invalid reference with
11776 (clobber (const_int 0)) and return 1. This replacement is useful because
11777 we often can get useful information about the form of a value (e.g., if
11778 it was produced by a shift that always produces -1 or 0) even though
11779 we don't know exactly what registers it was produced from. */
11782 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
11785 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11786 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11789 if (GET_CODE (x
) == REG
)
11791 unsigned int regno
= REGNO (x
);
11792 unsigned int endregno
11793 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11794 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11797 for (j
= regno
; j
< endregno
; j
++)
11798 if (reg_last_set_invalid
[j
]
11799 /* If this is a pseudo-register that was only set once and not
11800 live at the beginning of the function, it is always valid. */
11801 || (! (regno
>= FIRST_PSEUDO_REGISTER
11802 && REG_N_SETS (regno
) == 1
11803 && (! REGNO_REG_SET_P
11804 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))
11805 && reg_last_set_label
[j
] > tick
))
11808 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11814 /* If this is a memory reference, make sure that there were
11815 no stores after it that might have clobbered the value. We don't
11816 have alias info, so we assume any store invalidates it. */
11817 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11818 && INSN_CUID (insn
) <= mem_last_set
)
11821 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11825 for (i
= 0; i
< len
; i
++)
11829 /* Check for identical subexpressions. If x contains
11830 identical subexpression we only have to traverse one of
11833 && (GET_RTX_CLASS (GET_CODE (x
)) == '2'
11834 || GET_RTX_CLASS (GET_CODE (x
)) == 'c'))
11836 /* Note that at this point x0 has already been checked
11837 and found valid. */
11838 rtx x0
= XEXP (x
, 0);
11839 rtx x1
= XEXP (x
, 1);
11841 /* If x0 and x1 are identical then x is also valid. */
11845 /* If x1 is identical to a subexpression of x0 then
11846 while checking x0, x1 has already been checked. Thus
11847 it is valid and so as x. */
11848 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11849 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11850 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11853 /* If x0 is identical to a subexpression of x1 then x is
11854 valid iff the rest of x1 is valid. */
11855 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11856 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11857 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11859 get_last_value_validate (&XEXP (x1
,
11860 x0
== XEXP (x1
, 0) ? 1 : 0),
11861 insn
, tick
, replace
);
11864 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
11868 /* Don't bother with these. They shouldn't occur anyway. */
11869 else if (fmt
[i
] == 'E')
11873 /* If we haven't found a reason for it to be invalid, it is valid. */
11877 /* Get the last value assigned to X, if known. Some registers
11878 in the value may be replaced with (clobber (const_int 0)) if their value
11879 is known longer known reliably. */
11882 get_last_value (rtx x
)
11884 unsigned int regno
;
11887 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11888 then convert it to the desired mode. If this is a paradoxical SUBREG,
11889 we cannot predict what values the "extra" bits might have. */
11890 if (GET_CODE (x
) == SUBREG
11891 && subreg_lowpart_p (x
)
11892 && (GET_MODE_SIZE (GET_MODE (x
))
11893 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11894 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11895 return gen_lowpart_for_combine (GET_MODE (x
), value
);
11897 if (GET_CODE (x
) != REG
)
11901 value
= reg_last_set_value
[regno
];
11903 /* If we don't have a value, or if it isn't for this basic block and
11904 it's either a hard register, set more than once, or it's a live
11905 at the beginning of the function, return 0.
11907 Because if it's not live at the beginning of the function then the reg
11908 is always set before being used (is never used without being set).
11909 And, if it's set only once, and it's always set before use, then all
11910 uses must have the same last value, even if it's not from this basic
11914 || (reg_last_set_label
[regno
] != label_tick
11915 && (regno
< FIRST_PSEUDO_REGISTER
11916 || REG_N_SETS (regno
) != 1
11917 || (REGNO_REG_SET_P
11918 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))))
11921 /* If the value was set in a later insn than the ones we are processing,
11922 we can't use it even if the register was only set once. */
11923 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11926 /* If the value has all its registers valid, return it. */
11927 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11928 reg_last_set_label
[regno
], 0))
11931 /* Otherwise, make a copy and replace any invalid register with
11932 (clobber (const_int 0)). If that fails for some reason, return 0. */
11934 value
= copy_rtx (value
);
11935 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11936 reg_last_set_label
[regno
], 1))
11942 /* Return nonzero if expression X refers to a REG or to memory
11943 that is set in an instruction more recent than FROM_CUID. */
11946 use_crosses_set_p (rtx x
, int from_cuid
)
11950 enum rtx_code code
= GET_CODE (x
);
11954 unsigned int regno
= REGNO (x
);
11955 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11956 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11958 #ifdef PUSH_ROUNDING
11959 /* Don't allow uses of the stack pointer to be moved,
11960 because we don't know whether the move crosses a push insn. */
11961 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11964 for (; regno
< endreg
; regno
++)
11965 if (reg_last_set
[regno
]
11966 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11971 if (code
== MEM
&& mem_last_set
> from_cuid
)
11974 fmt
= GET_RTX_FORMAT (code
);
11976 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11981 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11982 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11985 else if (fmt
[i
] == 'e'
11986 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11992 /* Define three variables used for communication between the following
11995 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11996 static int reg_dead_flag
;
11998 /* Function called via note_stores from reg_dead_at_p.
12000 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12001 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12004 reg_dead_at_p_1 (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
12006 unsigned int regno
, endregno
;
12008 if (GET_CODE (dest
) != REG
)
12011 regno
= REGNO (dest
);
12012 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
12013 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
12015 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
12016 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
12019 /* Return nonzero if REG is known to be dead at INSN.
12021 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12022 referencing REG, it is dead. If we hit a SET referencing REG, it is
12023 live. Otherwise, see if it is live or dead at the start of the basic
12024 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12025 must be assumed to be always live. */
12028 reg_dead_at_p (rtx reg
, rtx insn
)
12033 /* Set variables for reg_dead_at_p_1. */
12034 reg_dead_regno
= REGNO (reg
);
12035 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
12036 ? HARD_REGNO_NREGS (reg_dead_regno
,
12042 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
12043 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
12045 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12046 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
12050 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
12051 beginning of function. */
12052 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
12053 insn
= prev_nonnote_insn (insn
))
12055 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
12057 return reg_dead_flag
== 1 ? 1 : 0;
12059 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
12063 /* Get the basic block that we were in. */
12065 block
= ENTRY_BLOCK_PTR
->next_bb
;
12068 FOR_EACH_BB (block
)
12069 if (insn
== block
->head
)
12072 if (block
== EXIT_BLOCK_PTR
)
12076 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12077 if (REGNO_REG_SET_P (block
->global_live_at_start
, i
))
12083 /* Note hard registers in X that are used. This code is similar to
12084 that in flow.c, but much simpler since we don't care about pseudos. */
12087 mark_used_regs_combine (rtx x
)
12089 RTX_CODE code
= GET_CODE (x
);
12090 unsigned int regno
;
12103 case ADDR_DIFF_VEC
:
12106 /* CC0 must die in the insn after it is set, so we don't need to take
12107 special note of it here. */
12113 /* If we are clobbering a MEM, mark any hard registers inside the
12114 address as used. */
12115 if (GET_CODE (XEXP (x
, 0)) == MEM
)
12116 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12121 /* A hard reg in a wide mode may really be multiple registers.
12122 If so, mark all of them just like the first. */
12123 if (regno
< FIRST_PSEUDO_REGISTER
)
12125 unsigned int endregno
, r
;
12127 /* None of this applies to the stack, frame or arg pointers. */
12128 if (regno
== STACK_POINTER_REGNUM
12129 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12130 || regno
== HARD_FRAME_POINTER_REGNUM
12132 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12133 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12135 || regno
== FRAME_POINTER_REGNUM
)
12138 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12139 for (r
= regno
; r
< endregno
; r
++)
12140 SET_HARD_REG_BIT (newpat_used_regs
, r
);
12146 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12148 rtx testreg
= SET_DEST (x
);
12150 while (GET_CODE (testreg
) == SUBREG
12151 || GET_CODE (testreg
) == ZERO_EXTRACT
12152 || GET_CODE (testreg
) == SIGN_EXTRACT
12153 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12154 testreg
= XEXP (testreg
, 0);
12156 if (GET_CODE (testreg
) == MEM
)
12157 mark_used_regs_combine (XEXP (testreg
, 0));
12159 mark_used_regs_combine (SET_SRC (x
));
12167 /* Recursively scan the operands of this expression. */
12170 const char *fmt
= GET_RTX_FORMAT (code
);
12172 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12175 mark_used_regs_combine (XEXP (x
, i
));
12176 else if (fmt
[i
] == 'E')
12180 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12181 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12187 /* Remove register number REGNO from the dead registers list of INSN.
12189 Return the note used to record the death, if there was one. */
12192 remove_death (unsigned int regno
, rtx insn
)
12194 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12198 REG_N_DEATHS (regno
)--;
12199 remove_note (insn
, note
);
12205 /* For each register (hardware or pseudo) used within expression X, if its
12206 death is in an instruction with cuid between FROM_CUID (inclusive) and
12207 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12208 list headed by PNOTES.
12210 That said, don't move registers killed by maybe_kill_insn.
12212 This is done when X is being merged by combination into TO_INSN. These
12213 notes will then be distributed as needed. */
12216 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_cuid
, rtx to_insn
,
12221 enum rtx_code code
= GET_CODE (x
);
12225 unsigned int regno
= REGNO (x
);
12226 rtx where_dead
= reg_last_death
[regno
];
12227 rtx before_dead
, after_dead
;
12229 /* Don't move the register if it gets killed in between from and to. */
12230 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12231 && ! reg_referenced_p (x
, maybe_kill_insn
))
12234 /* WHERE_DEAD could be a USE insn made by combine, so first we
12235 make sure that we have insns with valid INSN_CUID values. */
12236 before_dead
= where_dead
;
12237 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
12238 before_dead
= PREV_INSN (before_dead
);
12240 after_dead
= where_dead
;
12241 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
12242 after_dead
= NEXT_INSN (after_dead
);
12244 if (before_dead
&& after_dead
12245 && INSN_CUID (before_dead
) >= from_cuid
12246 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
12247 || (where_dead
!= after_dead
12248 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
12250 rtx note
= remove_death (regno
, where_dead
);
12252 /* It is possible for the call above to return 0. This can occur
12253 when reg_last_death points to I2 or I1 that we combined with.
12254 In that case make a new note.
12256 We must also check for the case where X is a hard register
12257 and NOTE is a death note for a range of hard registers
12258 including X. In that case, we must put REG_DEAD notes for
12259 the remaining registers in place of NOTE. */
12261 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12262 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12263 > GET_MODE_SIZE (GET_MODE (x
))))
12265 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12266 unsigned int deadend
12267 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
12268 GET_MODE (XEXP (note
, 0))));
12269 unsigned int ourend
12270 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12273 for (i
= deadregno
; i
< deadend
; i
++)
12274 if (i
< regno
|| i
>= ourend
)
12275 REG_NOTES (where_dead
)
12276 = gen_rtx_EXPR_LIST (REG_DEAD
,
12278 REG_NOTES (where_dead
));
12281 /* If we didn't find any note, or if we found a REG_DEAD note that
12282 covers only part of the given reg, and we have a multi-reg hard
12283 register, then to be safe we must check for REG_DEAD notes
12284 for each register other than the first. They could have
12285 their own REG_DEAD notes lying around. */
12286 else if ((note
== 0
12288 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12289 < GET_MODE_SIZE (GET_MODE (x
)))))
12290 && regno
< FIRST_PSEUDO_REGISTER
12291 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
12293 unsigned int ourend
12294 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12295 unsigned int i
, offset
;
12299 offset
= HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0)));
12303 for (i
= regno
+ offset
; i
< ourend
; i
++)
12304 move_deaths (regno_reg_rtx
[i
],
12305 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
12308 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12310 XEXP (note
, 1) = *pnotes
;
12314 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
12316 REG_N_DEATHS (regno
)++;
12322 else if (GET_CODE (x
) == SET
)
12324 rtx dest
= SET_DEST (x
);
12326 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12328 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12329 that accesses one word of a multi-word item, some
12330 piece of everything register in the expression is used by
12331 this insn, so remove any old death. */
12332 /* ??? So why do we test for equality of the sizes? */
12334 if (GET_CODE (dest
) == ZERO_EXTRACT
12335 || GET_CODE (dest
) == STRICT_LOW_PART
12336 || (GET_CODE (dest
) == SUBREG
12337 && (((GET_MODE_SIZE (GET_MODE (dest
))
12338 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
12339 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
12340 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
12342 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12346 /* If this is some other SUBREG, we know it replaces the entire
12347 value, so use that as the destination. */
12348 if (GET_CODE (dest
) == SUBREG
)
12349 dest
= SUBREG_REG (dest
);
12351 /* If this is a MEM, adjust deaths of anything used in the address.
12352 For a REG (the only other possibility), the entire value is
12353 being replaced so the old value is not used in this insn. */
12355 if (GET_CODE (dest
) == MEM
)
12356 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
12361 else if (GET_CODE (x
) == CLOBBER
)
12364 len
= GET_RTX_LENGTH (code
);
12365 fmt
= GET_RTX_FORMAT (code
);
12367 for (i
= 0; i
< len
; i
++)
12372 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12373 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
12376 else if (fmt
[i
] == 'e')
12377 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12381 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12382 pattern of an insn. X must be a REG. */
12385 reg_bitfield_target_p (rtx x
, rtx body
)
12389 if (GET_CODE (body
) == SET
)
12391 rtx dest
= SET_DEST (body
);
12393 unsigned int regno
, tregno
, endregno
, endtregno
;
12395 if (GET_CODE (dest
) == ZERO_EXTRACT
)
12396 target
= XEXP (dest
, 0);
12397 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
12398 target
= SUBREG_REG (XEXP (dest
, 0));
12402 if (GET_CODE (target
) == SUBREG
)
12403 target
= SUBREG_REG (target
);
12405 if (GET_CODE (target
) != REG
)
12408 tregno
= REGNO (target
), regno
= REGNO (x
);
12409 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
12410 return target
== x
;
12412 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
12413 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12415 return endregno
> tregno
&& regno
< endtregno
;
12418 else if (GET_CODE (body
) == PARALLEL
)
12419 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
12420 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
12426 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12427 as appropriate. I3 and I2 are the insns resulting from the combination
12428 insns including FROM (I2 may be zero).
12430 Each note in the list is either ignored or placed on some insns, depending
12431 on the type of note. */
12434 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
)
12436 rtx note
, next_note
;
12439 for (note
= notes
; note
; note
= next_note
)
12441 rtx place
= 0, place2
= 0;
12443 /* If this NOTE references a pseudo register, ensure it references
12444 the latest copy of that register. */
12445 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
12446 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
12447 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
12449 next_note
= XEXP (note
, 1);
12450 switch (REG_NOTE_KIND (note
))
12454 /* Doesn't matter much where we put this, as long as it's somewhere.
12455 It is preferable to keep these notes on branches, which is most
12456 likely to be i3. */
12460 case REG_VALUE_PROFILE
:
12461 /* Just get rid of this note, as it is unused later anyway. */
12464 case REG_VTABLE_REF
:
12465 /* ??? Should remain with *a particular* memory load. Given the
12466 nature of vtable data, the last insn seems relatively safe. */
12470 case REG_NON_LOCAL_GOTO
:
12471 if (GET_CODE (i3
) == JUMP_INSN
)
12473 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
12479 case REG_EH_REGION
:
12480 /* These notes must remain with the call or trapping instruction. */
12481 if (GET_CODE (i3
) == CALL_INSN
)
12483 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12485 else if (flag_non_call_exceptions
)
12487 if (may_trap_p (i3
))
12489 else if (i2
&& may_trap_p (i2
))
12491 /* ??? Otherwise assume we've combined things such that we
12492 can now prove that the instructions can't trap. Drop the
12493 note in this case. */
12501 /* These notes must remain with the call. It should not be
12502 possible for both I2 and I3 to be a call. */
12503 if (GET_CODE (i3
) == CALL_INSN
)
12505 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12512 /* Any clobbers for i3 may still exist, and so we must process
12513 REG_UNUSED notes from that insn.
12515 Any clobbers from i2 or i1 can only exist if they were added by
12516 recog_for_combine. In that case, recog_for_combine created the
12517 necessary REG_UNUSED notes. Trying to keep any original
12518 REG_UNUSED notes from these insns can cause incorrect output
12519 if it is for the same register as the original i3 dest.
12520 In that case, we will notice that the register is set in i3,
12521 and then add a REG_UNUSED note for the destination of i3, which
12522 is wrong. However, it is possible to have REG_UNUSED notes from
12523 i2 or i1 for register which were both used and clobbered, so
12524 we keep notes from i2 or i1 if they will turn into REG_DEAD
12527 /* If this register is set or clobbered in I3, put the note there
12528 unless there is one already. */
12529 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12531 if (from_insn
!= i3
)
12534 if (! (GET_CODE (XEXP (note
, 0)) == REG
12535 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12536 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12539 /* Otherwise, if this register is used by I3, then this register
12540 now dies here, so we must put a REG_DEAD note here unless there
12542 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12543 && ! (GET_CODE (XEXP (note
, 0)) == REG
12544 ? find_regno_note (i3
, REG_DEAD
,
12545 REGNO (XEXP (note
, 0)))
12546 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12548 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12556 /* These notes say something about results of an insn. We can
12557 only support them if they used to be on I3 in which case they
12558 remain on I3. Otherwise they are ignored.
12560 If the note refers to an expression that is not a constant, we
12561 must also ignore the note since we cannot tell whether the
12562 equivalence is still true. It might be possible to do
12563 slightly better than this (we only have a problem if I2DEST
12564 or I1DEST is present in the expression), but it doesn't
12565 seem worth the trouble. */
12567 if (from_insn
== i3
12568 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12573 case REG_NO_CONFLICT
:
12574 /* These notes say something about how a register is used. They must
12575 be present on any use of the register in I2 or I3. */
12576 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12579 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12589 /* This can show up in several ways -- either directly in the
12590 pattern, or hidden off in the constant pool with (or without?)
12591 a REG_EQUAL note. */
12592 /* ??? Ignore the without-reg_equal-note problem for now. */
12593 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12594 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12595 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12596 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12600 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12601 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12602 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12603 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12611 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12612 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12613 if (place
&& GET_CODE (place
) == JUMP_INSN
&& JUMP_LABEL (place
))
12615 if (JUMP_LABEL (place
) != XEXP (note
, 0))
12617 if (GET_CODE (JUMP_LABEL (place
)) == CODE_LABEL
)
12618 LABEL_NUSES (JUMP_LABEL (place
))--;
12621 if (place2
&& GET_CODE (place2
) == JUMP_INSN
&& JUMP_LABEL (place2
))
12623 if (JUMP_LABEL (place2
) != XEXP (note
, 0))
12625 if (GET_CODE (JUMP_LABEL (place2
)) == CODE_LABEL
)
12626 LABEL_NUSES (JUMP_LABEL (place2
))--;
12632 /* This note says something about the value of a register prior
12633 to the execution of an insn. It is too much trouble to see
12634 if the note is still correct in all situations. It is better
12635 to simply delete it. */
12639 /* If the insn previously containing this note still exists,
12640 put it back where it was. Otherwise move it to the previous
12641 insn. Adjust the corresponding REG_LIBCALL note. */
12642 if (GET_CODE (from_insn
) != NOTE
)
12646 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12647 place
= prev_real_insn (from_insn
);
12649 XEXP (tem
, 0) = place
;
12650 /* If we're deleting the last remaining instruction of a
12651 libcall sequence, don't add the notes. */
12652 else if (XEXP (note
, 0) == from_insn
)
12658 /* This is handled similarly to REG_RETVAL. */
12659 if (GET_CODE (from_insn
) != NOTE
)
12663 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12664 place
= next_real_insn (from_insn
);
12666 XEXP (tem
, 0) = place
;
12667 /* If we're deleting the last remaining instruction of a
12668 libcall sequence, don't add the notes. */
12669 else if (XEXP (note
, 0) == from_insn
)
12675 /* If the register is used as an input in I3, it dies there.
12676 Similarly for I2, if it is nonzero and adjacent to I3.
12678 If the register is not used as an input in either I3 or I2
12679 and it is not one of the registers we were supposed to eliminate,
12680 there are two possibilities. We might have a non-adjacent I2
12681 or we might have somehow eliminated an additional register
12682 from a computation. For example, we might have had A & B where
12683 we discover that B will always be zero. In this case we will
12684 eliminate the reference to A.
12686 In both cases, we must search to see if we can find a previous
12687 use of A and put the death note there. */
12690 && GET_CODE (from_insn
) == CALL_INSN
12691 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12693 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12695 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12696 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12701 basic_block bb
= this_basic_block
;
12703 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12705 if (! INSN_P (tem
))
12707 if (tem
== bb
->head
)
12712 /* If the register is being set at TEM, see if that is all
12713 TEM is doing. If so, delete TEM. Otherwise, make this
12714 into a REG_UNUSED note instead. */
12715 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12717 rtx set
= single_set (tem
);
12718 rtx inner_dest
= 0;
12720 rtx cc0_setter
= NULL_RTX
;
12724 for (inner_dest
= SET_DEST (set
);
12725 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12726 || GET_CODE (inner_dest
) == SUBREG
12727 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12728 inner_dest
= XEXP (inner_dest
, 0))
12731 /* Verify that it was the set, and not a clobber that
12732 modified the register.
12734 CC0 targets must be careful to maintain setter/user
12735 pairs. If we cannot delete the setter due to side
12736 effects, mark the user with an UNUSED note instead
12739 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12740 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12742 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12743 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12744 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12748 /* Move the notes and links of TEM elsewhere.
12749 This might delete other dead insns recursively.
12750 First set the pattern to something that won't use
12753 PATTERN (tem
) = pc_rtx
;
12755 distribute_notes (REG_NOTES (tem
), tem
, tem
,
12757 distribute_links (LOG_LINKS (tem
));
12759 PUT_CODE (tem
, NOTE
);
12760 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12761 NOTE_SOURCE_FILE (tem
) = 0;
12764 /* Delete the setter too. */
12767 PATTERN (cc0_setter
) = pc_rtx
;
12769 distribute_notes (REG_NOTES (cc0_setter
),
12770 cc0_setter
, cc0_setter
,
12772 distribute_links (LOG_LINKS (cc0_setter
));
12774 PUT_CODE (cc0_setter
, NOTE
);
12775 NOTE_LINE_NUMBER (cc0_setter
)
12776 = NOTE_INSN_DELETED
;
12777 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12781 /* If the register is both set and used here, put the
12782 REG_DEAD note here, but place a REG_UNUSED note
12783 here too unless there already is one. */
12784 else if (reg_referenced_p (XEXP (note
, 0),
12789 if (! find_regno_note (tem
, REG_UNUSED
,
12790 REGNO (XEXP (note
, 0))))
12792 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
12797 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12799 /* If there isn't already a REG_UNUSED note, put one
12801 if (! find_regno_note (tem
, REG_UNUSED
,
12802 REGNO (XEXP (note
, 0))))
12807 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12808 || (GET_CODE (tem
) == CALL_INSN
12809 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12813 /* If we are doing a 3->2 combination, and we have a
12814 register which formerly died in i3 and was not used
12815 by i2, which now no longer dies in i3 and is used in
12816 i2 but does not die in i2, and place is between i2
12817 and i3, then we may need to move a link from place to
12819 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12820 && INSN_CUID (place
) > INSN_CUID (i2
)
12822 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12823 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12825 rtx links
= LOG_LINKS (place
);
12826 LOG_LINKS (place
) = 0;
12827 distribute_links (links
);
12832 if (tem
== bb
->head
)
12836 /* We haven't found an insn for the death note and it
12837 is still a REG_DEAD note, but we have hit the beginning
12838 of the block. If the existing life info says the reg
12839 was dead, there's nothing left to do. Otherwise, we'll
12840 need to do a global life update after combine. */
12841 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12842 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12843 REGNO (XEXP (note
, 0))))
12844 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12847 /* If the register is set or already dead at PLACE, we needn't do
12848 anything with this note if it is still a REG_DEAD note.
12849 We can here if it is set at all, not if is it totally replace,
12850 which is what `dead_or_set_p' checks, so also check for it being
12853 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12855 unsigned int regno
= REGNO (XEXP (note
, 0));
12857 /* Similarly, if the instruction on which we want to place
12858 the note is a noop, we'll need do a global live update
12859 after we remove them in delete_noop_moves. */
12860 if (noop_move_p (place
))
12861 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12863 if (dead_or_set_p (place
, XEXP (note
, 0))
12864 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12866 /* Unless the register previously died in PLACE, clear
12867 reg_last_death. [I no longer understand why this is
12869 if (reg_last_death
[regno
] != place
)
12870 reg_last_death
[regno
] = 0;
12874 reg_last_death
[regno
] = place
;
12876 /* If this is a death note for a hard reg that is occupying
12877 multiple registers, ensure that we are still using all
12878 parts of the object. If we find a piece of the object
12879 that is unused, we must arrange for an appropriate REG_DEAD
12880 note to be added for it. However, we can't just emit a USE
12881 and tag the note to it, since the register might actually
12882 be dead; so we recourse, and the recursive call then finds
12883 the previous insn that used this register. */
12885 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12886 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
12888 unsigned int endregno
12889 = regno
+ HARD_REGNO_NREGS (regno
,
12890 GET_MODE (XEXP (note
, 0)));
12894 for (i
= regno
; i
< endregno
; i
++)
12895 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12896 && ! find_regno_fusage (place
, USE
, i
))
12897 || dead_or_set_regno_p (place
, i
))
12902 /* Put only REG_DEAD notes for pieces that are
12903 not already dead or set. */
12905 for (i
= regno
; i
< endregno
;
12906 i
+= HARD_REGNO_NREGS (i
, reg_raw_mode
[i
]))
12908 rtx piece
= regno_reg_rtx
[i
];
12909 basic_block bb
= this_basic_block
;
12911 if (! dead_or_set_p (place
, piece
)
12912 && ! reg_bitfield_target_p (piece
,
12916 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12918 distribute_notes (new_note
, place
, place
,
12921 else if (! refers_to_regno_p (i
, i
+ 1,
12922 PATTERN (place
), 0)
12923 && ! find_regno_fusage (place
, USE
, i
))
12924 for (tem
= PREV_INSN (place
); ;
12925 tem
= PREV_INSN (tem
))
12927 if (! INSN_P (tem
))
12929 if (tem
== bb
->head
)
12931 SET_BIT (refresh_blocks
,
12932 this_basic_block
->index
);
12937 if (dead_or_set_p (tem
, piece
)
12938 || reg_bitfield_target_p (piece
,
12942 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12957 /* Any other notes should not be present at this point in the
12964 XEXP (note
, 1) = REG_NOTES (place
);
12965 REG_NOTES (place
) = note
;
12967 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12968 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12969 && GET_CODE (XEXP (note
, 0)) == REG
)
12970 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12974 if ((REG_NOTE_KIND (note
) == REG_DEAD
12975 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12976 && GET_CODE (XEXP (note
, 0)) == REG
)
12977 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12979 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12980 REG_NOTE_KIND (note
),
12982 REG_NOTES (place2
));
12987 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12988 I3, I2, and I1 to new locations. This is also called in one case to
12989 add a link pointing at I3 when I3's destination is changed. */
12992 distribute_links (rtx links
)
12994 rtx link
, next_link
;
12996 for (link
= links
; link
; link
= next_link
)
13002 next_link
= XEXP (link
, 1);
13004 /* If the insn that this link points to is a NOTE or isn't a single
13005 set, ignore it. In the latter case, it isn't clear what we
13006 can do other than ignore the link, since we can't tell which
13007 register it was for. Such links wouldn't be used by combine
13010 It is not possible for the destination of the target of the link to
13011 have been changed by combine. The only potential of this is if we
13012 replace I3, I2, and I1 by I3 and I2. But in that case the
13013 destination of I2 also remains unchanged. */
13015 if (GET_CODE (XEXP (link
, 0)) == NOTE
13016 || (set
= single_set (XEXP (link
, 0))) == 0)
13019 reg
= SET_DEST (set
);
13020 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
13021 || GET_CODE (reg
) == SIGN_EXTRACT
13022 || GET_CODE (reg
) == STRICT_LOW_PART
)
13023 reg
= XEXP (reg
, 0);
13025 /* A LOG_LINK is defined as being placed on the first insn that uses
13026 a register and points to the insn that sets the register. Start
13027 searching at the next insn after the target of the link and stop
13028 when we reach a set of the register or the end of the basic block.
13030 Note that this correctly handles the link that used to point from
13031 I3 to I2. Also note that not much searching is typically done here
13032 since most links don't point very far away. */
13034 for (insn
= NEXT_INSN (XEXP (link
, 0));
13035 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
13036 || this_basic_block
->next_bb
->head
!= insn
));
13037 insn
= NEXT_INSN (insn
))
13038 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
13040 if (reg_referenced_p (reg
, PATTERN (insn
)))
13044 else if (GET_CODE (insn
) == CALL_INSN
13045 && find_reg_fusage (insn
, USE
, reg
))
13051 /* If we found a place to put the link, place it there unless there
13052 is already a link to the same insn as LINK at that point. */
13058 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
13059 if (XEXP (link2
, 0) == XEXP (link
, 0))
13064 XEXP (link
, 1) = LOG_LINKS (place
);
13065 LOG_LINKS (place
) = link
;
13067 /* Set added_links_insn to the earliest insn we added a
13069 if (added_links_insn
== 0
13070 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
13071 added_links_insn
= place
;
13077 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
13080 insn_cuid (rtx insn
)
13082 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
13083 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
13084 insn
= NEXT_INSN (insn
);
13086 if (INSN_UID (insn
) > max_uid_cuid
)
13089 return INSN_CUID (insn
);
13093 dump_combine_stats (FILE *file
)
13097 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13098 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13102 dump_combine_total_stats (FILE *file
)
13106 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13107 total_attempts
, total_merges
, total_extras
, total_successes
);