1 /* Redundant Extension Elimination pass for the GNU compiler.
2 Copyright (C) 2010-2014 Free Software Foundation, Inc.
3 Contributed by Ilya Enkovich (ilya.enkovich@intel.com)
5 Based on the Redundant Zero-extension elimination pass contributed by
6 Sriraman Tallam (tmsriram@google.com) and Silvius Rus (rus@google.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
25 /* Problem Description :
27 This pass is intended to remove redundant extension instructions.
28 Such instructions appear for different reasons. We expect some of
29 them due to implicit zero-extension in 64-bit registers after writing
30 to their lower 32-bit half (e.g. for the x86-64 architecture).
31 Another possible reason is a type cast which follows a load (for
32 instance a register restore) and which can be combined into a single
33 instruction, and for which earlier local passes, e.g. the combiner,
34 weren't able to optimize.
36 How does this pass work ?
37 --------------------------
39 This pass is run after register allocation. Hence, all registers that
40 this pass deals with are hard registers. This pass first looks for an
41 extension instruction that could possibly be redundant. Such extension
42 instructions show up in RTL with the pattern :
43 (set (reg:<SWI248> x) (any_extend:<SWI248> (reg:<SWI124> x))),
44 where x can be any hard register.
45 Now, this pass tries to eliminate this instruction by merging the
46 extension with the definitions of register x. For instance, if
47 one of the definitions of register x was :
48 (set (reg:SI x) (plus:SI (reg:SI z1) (reg:SI z2))),
49 followed by extension :
50 (set (reg:DI x) (zero_extend:DI (reg:SI x)))
51 then the combination converts this into :
52 (set (reg:DI x) (zero_extend:DI (plus:SI (reg:SI z1) (reg:SI z2)))).
53 If all the merged definitions are recognizable assembly instructions,
54 the extension is effectively eliminated.
56 For example, for the x86-64 architecture, implicit zero-extensions
57 are captured with appropriate patterns in the i386.md file. Hence,
58 these merged definition can be matched to a single assembly instruction.
59 The original extension instruction is then deleted if all the
60 definitions can be merged.
62 However, there are cases where the definition instruction cannot be
63 merged with an extension. Examples are CALL instructions. In such
64 cases, the original extension is not redundant and this pass does
67 Handling conditional moves :
68 ----------------------------
70 Architectures like x86-64 support conditional moves whose semantics for
71 extension differ from the other instructions. For instance, the
72 instruction *cmov ebx, eax*
73 zero-extends eax onto rax only when the move from ebx to eax happens.
74 Otherwise, eax may not be zero-extended. Consider conditional moves as
75 RTL instructions of the form
76 (set (reg:SI x) (if_then_else (cond) (reg:SI y) (reg:SI z))).
77 This pass tries to merge an extension with a conditional move by
78 actually merging the definitions of y and z with an extension and then
79 converting the conditional move into :
80 (set (reg:DI x) (if_then_else (cond) (reg:DI y) (reg:DI z))).
81 Since registers y and z are extended, register x will also be extended
82 after the conditional move. Note that this step has to be done
83 transitively since the definition of a conditional copy can be
84 another conditional copy.
86 Motivating Example I :
89 **********************************************
102 **********************************************
106 400315: b8 4e 00 00 00 mov $0x4e,%eax
107 40031a: 0f af f8 imul %eax,%edi
108 40031d: 89 ff mov %edi,%edi - useless extension
109 40031f: 8b 04 bd 60 19 40 00 mov 0x401960(,%rdi,4),%eax
112 400330: ba 2d 00 00 00 mov $0x2d,%edx
113 400335: 0f af fa imul %edx,%edi
114 400338: 89 ff mov %edi,%edi - useless extension
115 40033a: 8b 04 bd 60 19 40 00 mov 0x401960(,%rdi,4),%eax
118 $ gcc -O2 -free bad_code.c
120 400315: 6b ff 4e imul $0x4e,%edi,%edi
121 400318: 8b 04 bd 40 19 40 00 mov 0x401940(,%rdi,4),%eax
123 400320: 6b ff 2d imul $0x2d,%edi,%edi
124 400323: 8b 04 bd 40 19 40 00 mov 0x401940(,%rdi,4),%eax
127 Motivating Example II :
128 ---------------------
130 Here is an example with a conditional move.
133 **********************************************
135 unsigned long long foo(unsigned x , unsigned y)
142 return (unsigned long long)(z);
147 400360: 8d 14 3e lea (%rsi,%rdi,1),%edx
148 400363: 89 f8 mov %edi,%eax
149 400365: 29 f0 sub %esi,%eax
150 400367: 83 ff 65 cmp $0x65,%edi
151 40036a: 0f 43 c2 cmovae %edx,%eax
152 40036d: 89 c0 mov %eax,%eax - useless extension
155 $ gcc -O2 -free bad_code.c
157 400360: 89 fa mov %edi,%edx
158 400362: 8d 04 3e lea (%rsi,%rdi,1),%eax
159 400365: 29 f2 sub %esi,%edx
160 400367: 83 ff 65 cmp $0x65,%edi
161 40036a: 89 d6 mov %edx,%esi
162 40036c: 48 0f 42 c6 cmovb %rsi,%rax
165 Motivating Example III :
166 ---------------------
168 Here is an example with a type cast.
171 **********************************************
173 void test(int size, unsigned char *in, unsigned char *out)
176 unsigned char xr, xg, xy=0;
178 for (i = 0; i < size; i++) {
181 xy = (unsigned char) ((19595*xr + 38470*xg) >> 16);
188 10: 0f b6 0e movzbl (%rsi),%ecx
189 13: 0f b6 46 01 movzbl 0x1(%rsi),%eax
190 17: 48 83 c6 02 add $0x2,%rsi
191 1b: 0f b6 c9 movzbl %cl,%ecx - useless extension
192 1e: 0f b6 c0 movzbl %al,%eax - useless extension
193 21: 69 c9 8b 4c 00 00 imul $0x4c8b,%ecx,%ecx
194 27: 69 c0 46 96 00 00 imul $0x9646,%eax,%eax
196 $ gcc -O2 -free bad_code.c
198 10: 0f b6 0e movzbl (%rsi),%ecx
199 13: 0f b6 46 01 movzbl 0x1(%rsi),%eax
200 17: 48 83 c6 02 add $0x2,%rsi
201 1b: 69 c9 8b 4c 00 00 imul $0x4c8b,%ecx,%ecx
202 21: 69 c0 46 96 00 00 imul $0x9646,%eax,%eax
207 The original redundant zero-extension elimination pass reported reduction
208 of the dynamic instruction count of a compression benchmark by 2.8% and
209 improvement of its run time by about 1%.
211 The additional performance gain with the enhanced pass is mostly expected
212 on in-order architectures where redundancy cannot be compensated by out of
213 order execution. Measurements showed up to 10% performance gain (reduced
214 run time) on EEMBC 2.0 benchmarks on Atom processor with geomean performance
220 #include "coretypes.h"
227 #include "hard-reg-set.h"
228 #include "basic-block.h"
229 #include "insn-config.h"
230 #include "function.h"
232 #include "insn-attr.h"
234 #include "diagnostic-core.h"
237 #include "insn-codes.h"
238 #include "rtlhooks-def.h"
240 #include "tree-pass.h"
244 /* This structure represents a candidate for elimination. */
246 typedef struct ext_cand
248 /* The expression. */
251 /* The kind of extension. */
254 /* The destination mode. */
255 enum machine_mode mode
;
257 /* The instruction where it lives. */
262 static int max_insn_uid
;
264 /* Given a insn (CURR_INSN), an extension candidate for removal (CAND)
265 and a pointer to the SET rtx (ORIG_SET) that needs to be modified,
266 this code modifies the SET rtx to a new SET rtx that extends the
267 right hand expression into a register on the left hand side. Note
268 that multiple assumptions are made about the nature of the set that
269 needs to be true for this to work and is called from merge_def_and_ext.
272 (set (reg a) (expression))
275 (set (reg a) (any_extend (expression)))
278 If the expression is a constant or another extension, then directly
279 assign it to the register. */
282 combine_set_extension (ext_cand
*cand
, rtx curr_insn
, rtx
*orig_set
)
284 rtx orig_src
= SET_SRC (*orig_set
);
286 rtx cand_pat
= PATTERN (cand
->insn
);
288 /* If the extension's source/destination registers are not the same
289 then we need to change the original load to reference the destination
290 of the extension. Then we need to emit a copy from that destination
291 to the original destination of the load. */
294 = (REGNO (SET_DEST (cand_pat
)) != REGNO (XEXP (SET_SRC (cand_pat
), 0)));
296 new_reg
= gen_rtx_REG (cand
->mode
, REGNO (SET_DEST (cand_pat
)));
298 new_reg
= gen_rtx_REG (cand
->mode
, REGNO (SET_DEST (*orig_set
)));
301 /* Rethinking test. Temporarily disabled. */
302 /* We're going to be widening the result of DEF_INSN, ensure that doing so
303 doesn't change the number of hard registers needed for the result. */
304 if (HARD_REGNO_NREGS (REGNO (new_reg
), cand
->mode
)
305 != HARD_REGNO_NREGS (REGNO (SET_DEST (*orig_set
)),
306 GET_MODE (SET_DEST (*orig_set
))))
310 /* Merge constants by directly moving the constant into the register under
311 some conditions. Recall that RTL constants are sign-extended. */
312 if (GET_CODE (orig_src
) == CONST_INT
313 && HOST_BITS_PER_WIDE_INT
>= GET_MODE_BITSIZE (cand
->mode
))
315 if (INTVAL (orig_src
) >= 0 || cand
->code
== SIGN_EXTEND
)
316 new_set
= gen_rtx_SET (VOIDmode
, new_reg
, orig_src
);
319 /* Zero-extend the negative constant by masking out the bits outside
321 enum machine_mode src_mode
= GET_MODE (SET_DEST (*orig_set
));
323 = gen_int_mode (INTVAL (orig_src
) & GET_MODE_MASK (src_mode
),
325 new_set
= gen_rtx_SET (VOIDmode
, new_reg
, new_const_int
);
328 else if (GET_MODE (orig_src
) == VOIDmode
)
330 /* This is mostly due to a call insn that should not be optimized. */
333 else if (GET_CODE (orig_src
) == cand
->code
)
335 /* Here is a sequence of two extensions. Try to merge them. */
337 = gen_rtx_fmt_e (cand
->code
, cand
->mode
, XEXP (orig_src
, 0));
338 rtx simplified_temp_extension
= simplify_rtx (temp_extension
);
339 if (simplified_temp_extension
)
340 temp_extension
= simplified_temp_extension
;
341 new_set
= gen_rtx_SET (VOIDmode
, new_reg
, temp_extension
);
343 else if (GET_CODE (orig_src
) == IF_THEN_ELSE
)
345 /* Only IF_THEN_ELSE of phi-type copies are combined. Otherwise,
346 in general, IF_THEN_ELSE should not be combined. */
351 /* This is the normal case. */
353 = gen_rtx_fmt_e (cand
->code
, cand
->mode
, orig_src
);
354 rtx simplified_temp_extension
= simplify_rtx (temp_extension
);
355 if (simplified_temp_extension
)
356 temp_extension
= simplified_temp_extension
;
357 new_set
= gen_rtx_SET (VOIDmode
, new_reg
, temp_extension
);
360 /* This change is a part of a group of changes. Hence,
361 validate_change will not try to commit the change. */
362 if (validate_change (curr_insn
, orig_set
, new_set
, true))
367 "Tentatively merged extension with definition %s:\n",
368 (copy_needed
) ? "(copy needed)" : "");
369 print_rtl_single (dump_file
, curr_insn
);
377 /* Treat if_then_else insns, where the operands of both branches
378 are registers, as copies. For instance,
380 (set (reg:SI a) (if_then_else (cond) (reg:SI b) (reg:SI c)))
382 (set (reg:DI a) (if_then_else (cond) (reg:DI b) (reg:DI c)))
383 DEF_INSN is the if_then_else insn. */
386 transform_ifelse (ext_cand
*cand
, rtx def_insn
)
388 rtx set_insn
= PATTERN (def_insn
);
389 rtx srcreg
, dstreg
, srcreg2
;
390 rtx map_srcreg
, map_dstreg
, map_srcreg2
;
395 gcc_assert (GET_CODE (set_insn
) == SET
);
397 cond
= XEXP (SET_SRC (set_insn
), 0);
398 dstreg
= SET_DEST (set_insn
);
399 srcreg
= XEXP (SET_SRC (set_insn
), 1);
400 srcreg2
= XEXP (SET_SRC (set_insn
), 2);
401 /* If the conditional move already has the right or wider mode,
402 there is nothing to do. */
403 if (GET_MODE_SIZE (GET_MODE (dstreg
)) >= GET_MODE_SIZE (cand
->mode
))
406 map_srcreg
= gen_rtx_REG (cand
->mode
, REGNO (srcreg
));
407 map_srcreg2
= gen_rtx_REG (cand
->mode
, REGNO (srcreg2
));
408 map_dstreg
= gen_rtx_REG (cand
->mode
, REGNO (dstreg
));
409 ifexpr
= gen_rtx_IF_THEN_ELSE (cand
->mode
, cond
, map_srcreg
, map_srcreg2
);
410 new_set
= gen_rtx_SET (VOIDmode
, map_dstreg
, ifexpr
);
412 if (validate_change (def_insn
, &PATTERN (def_insn
), new_set
, true))
417 "Mode of conditional move instruction extended:\n");
418 print_rtl_single (dump_file
, def_insn
);
426 /* Get all the reaching definitions of an instruction. The definitions are
427 desired for REG used in INSN. Return the definition list or NULL if a
428 definition is missing. If DEST is non-NULL, additionally push the INSN
429 of the definitions onto DEST. */
431 static struct df_link
*
432 get_defs (rtx insn
, rtx reg
, vec
<rtx
> *dest
)
434 df_ref reg_info
, *uses
;
435 struct df_link
*ref_chain
, *ref_link
;
439 for (uses
= DF_INSN_USES (insn
); *uses
; uses
++)
442 if (GET_CODE (DF_REF_REG (reg_info
)) == SUBREG
)
444 if (REGNO (DF_REF_REG (reg_info
)) == REGNO (reg
))
448 gcc_assert (reg_info
!= NULL
&& uses
!= NULL
);
450 ref_chain
= DF_REF_CHAIN (reg_info
);
452 for (ref_link
= ref_chain
; ref_link
; ref_link
= ref_link
->next
)
454 /* Problem getting some definition for this instruction. */
455 if (ref_link
->ref
== NULL
)
457 if (DF_REF_INSN_INFO (ref_link
->ref
) == NULL
)
462 for (ref_link
= ref_chain
; ref_link
; ref_link
= ref_link
->next
)
463 dest
->safe_push (DF_REF_INSN (ref_link
->ref
));
468 /* Return true if INSN is
469 (SET (reg REGNO (def_reg)) (if_then_else (cond) (REG x1) (REG x2)))
470 and store x1 and x2 in REG_1 and REG_2. */
473 is_cond_copy_insn (rtx insn
, rtx
*reg1
, rtx
*reg2
)
475 rtx expr
= single_set (insn
);
478 && GET_CODE (expr
) == SET
479 && GET_CODE (SET_DEST (expr
)) == REG
480 && GET_CODE (SET_SRC (expr
)) == IF_THEN_ELSE
481 && GET_CODE (XEXP (SET_SRC (expr
), 1)) == REG
482 && GET_CODE (XEXP (SET_SRC (expr
), 2)) == REG
)
484 *reg1
= XEXP (SET_SRC (expr
), 1);
485 *reg2
= XEXP (SET_SRC (expr
), 2);
492 enum ext_modified_kind
494 /* The insn hasn't been modified by ree pass yet. */
496 /* Changed into zero extension. */
498 /* Changed into sign extension. */
502 struct ATTRIBUTE_PACKED ext_modified
504 /* Mode from which ree has zero or sign extended the destination. */
505 ENUM_BITFIELD(machine_mode
) mode
: 8;
507 /* Kind of modification of the insn. */
508 ENUM_BITFIELD(ext_modified_kind
) kind
: 2;
510 /* True if the insn is scheduled to be deleted. */
511 unsigned int deleted
: 1;
514 /* Vectors used by combine_reaching_defs and its helpers. */
515 typedef struct ext_state
517 /* In order to avoid constant alloc/free, we keep these
518 4 vectors live through the entire find_and_remove_re and just
519 truncate them each time. */
521 vec
<rtx
> copies_list
;
522 vec
<rtx
> modified_list
;
525 /* For instructions that have been successfully modified, this is
526 the original mode from which the insn is extending and
527 kind of extension. */
528 struct ext_modified
*modified
;
531 /* Reaching Definitions of the extended register could be conditional copies
532 or regular definitions. This function separates the two types into two
533 lists, STATE->DEFS_LIST and STATE->COPIES_LIST. This is necessary because,
534 if a reaching definition is a conditional copy, merging the extension with
535 this definition is wrong. Conditional copies are merged by transitively
536 merging their definitions. The defs_list is populated with all the reaching
537 definitions of the extension instruction (EXTEND_INSN) which must be merged
538 with an extension. The copies_list contains all the conditional moves that
539 will later be extended into a wider mode conditional move if all the merges
540 are successful. The function returns false upon failure, true upon
544 make_defs_and_copies_lists (rtx extend_insn
, const_rtx set_pat
,
547 rtx src_reg
= XEXP (SET_SRC (set_pat
), 0);
548 bool *is_insn_visited
;
551 state
->work_list
.truncate (0);
553 /* Initialize the work list. */
554 if (!get_defs (extend_insn
, src_reg
, &state
->work_list
))
557 is_insn_visited
= XCNEWVEC (bool, max_insn_uid
);
559 /* Perform transitive closure for conditional copies. */
560 while (!state
->work_list
.is_empty ())
562 rtx def_insn
= state
->work_list
.pop ();
565 gcc_assert (INSN_UID (def_insn
) < max_insn_uid
);
567 if (is_insn_visited
[INSN_UID (def_insn
)])
569 is_insn_visited
[INSN_UID (def_insn
)] = true;
571 if (is_cond_copy_insn (def_insn
, ®1
, ®2
))
573 /* Push it onto the copy list first. */
574 state
->copies_list
.safe_push (def_insn
);
576 /* Now perform the transitive closure. */
577 if (!get_defs (def_insn
, reg1
, &state
->work_list
)
578 || !get_defs (def_insn
, reg2
, &state
->work_list
))
585 state
->defs_list
.safe_push (def_insn
);
588 XDELETEVEC (is_insn_visited
);
593 /* If DEF_INSN has single SET expression, possibly buried inside
594 a PARALLEL, return the address of the SET expression, else
595 return NULL. This is similar to single_set, except that
596 single_set allows multiple SETs when all but one is dead. */
598 get_sub_rtx (rtx def_insn
)
600 enum rtx_code code
= GET_CODE (PATTERN (def_insn
));
603 if (code
== PARALLEL
)
605 for (int i
= 0; i
< XVECLEN (PATTERN (def_insn
), 0); i
++)
607 rtx s_expr
= XVECEXP (PATTERN (def_insn
), 0, i
);
608 if (GET_CODE (s_expr
) != SET
)
612 sub_rtx
= &XVECEXP (PATTERN (def_insn
), 0, i
);
615 /* PARALLEL with multiple SETs. */
620 else if (code
== SET
)
621 sub_rtx
= &PATTERN (def_insn
);
624 /* It is not a PARALLEL or a SET, what could it be ? */
628 gcc_assert (sub_rtx
!= NULL
);
632 /* Merge the DEF_INSN with an extension. Calls combine_set_extension
633 on the SET pattern. */
636 merge_def_and_ext (ext_cand
*cand
, rtx def_insn
, ext_state
*state
)
638 enum machine_mode ext_src_mode
;
641 ext_src_mode
= GET_MODE (XEXP (SET_SRC (cand
->expr
), 0));
642 sub_rtx
= get_sub_rtx (def_insn
);
647 if (REG_P (SET_DEST (*sub_rtx
))
648 && (GET_MODE (SET_DEST (*sub_rtx
)) == ext_src_mode
649 || ((state
->modified
[INSN_UID (def_insn
)].kind
650 == (cand
->code
== ZERO_EXTEND
651 ? EXT_MODIFIED_ZEXT
: EXT_MODIFIED_SEXT
))
652 && state
->modified
[INSN_UID (def_insn
)].mode
655 if (GET_MODE_SIZE (GET_MODE (SET_DEST (*sub_rtx
)))
656 >= GET_MODE_SIZE (cand
->mode
))
658 /* If def_insn is already scheduled to be deleted, don't attempt
660 if (state
->modified
[INSN_UID (def_insn
)].deleted
)
662 if (combine_set_extension (cand
, def_insn
, sub_rtx
))
664 if (state
->modified
[INSN_UID (def_insn
)].kind
== EXT_MODIFIED_NONE
)
665 state
->modified
[INSN_UID (def_insn
)].mode
= ext_src_mode
;
673 /* This function goes through all reaching defs of the source
674 of the candidate for elimination (CAND) and tries to combine
675 the extension with the definition instruction. The changes
676 are made as a group so that even if one definition cannot be
677 merged, all reaching definitions end up not being merged.
678 When a conditional copy is encountered, merging is attempted
679 transitively on its definitions. It returns true upon success
680 and false upon failure. */
683 combine_reaching_defs (ext_cand
*cand
, const_rtx set_pat
, ext_state
*state
)
686 bool merge_successful
= true;
691 state
->defs_list
.truncate (0);
692 state
->copies_list
.truncate (0);
694 outcome
= make_defs_and_copies_lists (cand
->insn
, set_pat
, state
);
699 /* If the destination operand of the extension is a different
700 register than the source operand, then additional restrictions
702 if ((REGNO (SET_DEST (PATTERN (cand
->insn
)))
703 != REGNO (XEXP (SET_SRC (PATTERN (cand
->insn
)), 0))))
705 /* In theory we could handle more than one reaching def, it
706 just makes the code to update the insn stream more complex. */
707 if (state
->defs_list
.length () != 1)
710 /* We require the candidate not already be modified. This may
711 be overly conservative. */
712 if (state
->modified
[INSN_UID (cand
->insn
)].kind
!= EXT_MODIFIED_NONE
)
716 (set (reg1) (expression))
717 (set (reg2) (any_extend (reg1)))
719 (set (reg2) (any_extend (expression)))
721 is only valid for scalar integral modes, as it relies on the low
722 subreg of reg1 to have the value of (expression), which is not true
723 e.g. for vector modes. */
724 if (!SCALAR_INT_MODE_P (GET_MODE (SET_DEST (PATTERN (cand
->insn
)))))
727 /* There's only one reaching def. */
728 rtx def_insn
= state
->defs_list
[0];
730 /* The defining statement must not have been modified either. */
731 if (state
->modified
[INSN_UID (def_insn
)].kind
!= EXT_MODIFIED_NONE
)
734 /* The defining statement and candidate insn must be in the same block.
735 This is merely to keep the test for safety and updating the insn
736 stream simple. Also ensure that within the block the candidate
737 follows the defining insn. */
738 if (BLOCK_FOR_INSN (cand
->insn
) != BLOCK_FOR_INSN (def_insn
)
739 || DF_INSN_LUID (def_insn
) > DF_INSN_LUID (cand
->insn
))
742 /* If there is an overlap between the destination of DEF_INSN and
743 CAND->insn, then this transformation is not safe. Note we have
744 to test in the widened mode. */
745 rtx
*dest_sub_rtx
= get_sub_rtx (def_insn
);
746 if (dest_sub_rtx
== NULL
747 || !REG_P (SET_DEST (*dest_sub_rtx
)))
750 rtx tmp_reg
= gen_rtx_REG (GET_MODE (SET_DEST (PATTERN (cand
->insn
))),
751 REGNO (SET_DEST (*dest_sub_rtx
)));
752 if (reg_overlap_mentioned_p (tmp_reg
, SET_DEST (PATTERN (cand
->insn
))))
755 /* The destination register of the extension insn must not be
756 used or set between the def_insn and cand->insn exclusive. */
757 if (reg_used_between_p (SET_DEST (PATTERN (cand
->insn
)),
758 def_insn
, cand
->insn
)
759 || reg_set_between_p (SET_DEST (PATTERN (cand
->insn
)),
760 def_insn
, cand
->insn
))
765 /* If cand->insn has been already modified, update cand->mode to a wider
766 mode if possible, or punt. */
767 if (state
->modified
[INSN_UID (cand
->insn
)].kind
!= EXT_MODIFIED_NONE
)
769 enum machine_mode mode
;
772 if (state
->modified
[INSN_UID (cand
->insn
)].kind
773 != (cand
->code
== ZERO_EXTEND
774 ? EXT_MODIFIED_ZEXT
: EXT_MODIFIED_SEXT
)
775 || state
->modified
[INSN_UID (cand
->insn
)].mode
!= cand
->mode
776 || (set
= single_set (cand
->insn
)) == NULL_RTX
)
778 mode
= GET_MODE (SET_DEST (set
));
779 gcc_assert (GET_MODE_SIZE (mode
) >= GET_MODE_SIZE (cand
->mode
));
783 merge_successful
= true;
785 /* Go through the defs vector and try to merge all the definitions
787 state
->modified_list
.truncate (0);
788 FOR_EACH_VEC_ELT (state
->defs_list
, defs_ix
, def_insn
)
790 if (merge_def_and_ext (cand
, def_insn
, state
))
791 state
->modified_list
.safe_push (def_insn
);
794 merge_successful
= false;
799 /* Now go through the conditional copies vector and try to merge all
800 the copies in this vector. */
801 if (merge_successful
)
803 FOR_EACH_VEC_ELT (state
->copies_list
, i
, def_insn
)
805 if (transform_ifelse (cand
, def_insn
))
806 state
->modified_list
.safe_push (def_insn
);
809 merge_successful
= false;
815 if (merge_successful
)
817 /* Commit the changes here if possible
818 FIXME: It's an all-or-nothing scenario. Even if only one definition
819 cannot be merged, we entirely give up. In the future, we should allow
820 extensions to be partially eliminated along those paths where the
821 definitions could be merged. */
822 if (apply_change_group ())
825 fprintf (dump_file
, "All merges were successful.\n");
827 FOR_EACH_VEC_ELT (state
->modified_list
, i
, def_insn
)
828 if (state
->modified
[INSN_UID (def_insn
)].kind
== EXT_MODIFIED_NONE
)
829 state
->modified
[INSN_UID (def_insn
)].kind
830 = (cand
->code
== ZERO_EXTEND
831 ? EXT_MODIFIED_ZEXT
: EXT_MODIFIED_SEXT
);
837 /* Changes need not be cancelled explicitly as apply_change_group
838 does it. Print list of definitions in the dump_file for debug
839 purposes. This extension cannot be deleted. */
843 "Merge cancelled, non-mergeable definitions:\n");
844 FOR_EACH_VEC_ELT (state
->modified_list
, i
, def_insn
)
845 print_rtl_single (dump_file
, def_insn
);
851 /* Cancel any changes that have been made so far. */
858 /* Add an extension pattern that could be eliminated. */
861 add_removable_extension (const_rtx expr
, rtx insn
,
862 vec
<ext_cand
> *insn_list
,
866 enum machine_mode mode
;
870 /* We are looking for SET (REG N) (ANY_EXTEND (REG N)). */
871 if (GET_CODE (expr
) != SET
)
874 src
= SET_SRC (expr
);
875 code
= GET_CODE (src
);
876 dest
= SET_DEST (expr
);
877 mode
= GET_MODE (dest
);
880 && (code
== SIGN_EXTEND
|| code
== ZERO_EXTEND
)
881 && REG_P (XEXP (src
, 0)))
883 struct df_link
*defs
, *def
;
886 /* First, make sure we can get all the reaching definitions. */
887 defs
= get_defs (insn
, XEXP (src
, 0), NULL
);
892 fprintf (dump_file
, "Cannot eliminate extension:\n");
893 print_rtl_single (dump_file
, insn
);
894 fprintf (dump_file
, " because of missing definition(s)\n");
899 /* Second, make sure the reaching definitions don't feed another and
900 different extension. FIXME: this obviously can be improved. */
901 for (def
= defs
; def
; def
= def
->next
)
902 if ((idx
= def_map
[INSN_UID (DF_REF_INSN (def
->ref
))])
903 && (cand
= &(*insn_list
)[idx
- 1])
904 && cand
->code
!= code
)
908 fprintf (dump_file
, "Cannot eliminate extension:\n");
909 print_rtl_single (dump_file
, insn
);
910 fprintf (dump_file
, " because of other extension\n");
915 /* Then add the candidate to the list and insert the reaching definitions
916 into the definition map. */
917 ext_cand e
= {expr
, code
, mode
, insn
};
918 insn_list
->safe_push (e
);
919 idx
= insn_list
->length ();
921 for (def
= defs
; def
; def
= def
->next
)
922 def_map
[INSN_UID (DF_REF_INSN (def
->ref
))] = idx
;
926 /* Traverse the instruction stream looking for extensions and return the
927 list of candidates. */
930 find_removable_extensions (void)
932 vec
<ext_cand
> insn_list
= vNULL
;
935 unsigned *def_map
= XCNEWVEC (unsigned, max_insn_uid
);
937 FOR_EACH_BB_FN (bb
, cfun
)
938 FOR_BB_INSNS (bb
, insn
)
940 if (!NONDEBUG_INSN_P (insn
))
943 set
= single_set (insn
);
946 add_removable_extension (set
, insn
, &insn_list
, def_map
);
949 XDELETEVEC (def_map
);
954 /* This is the main function that checks the insn stream for redundant
955 extensions and tries to remove them if possible. */
958 find_and_remove_re (void)
961 rtx curr_insn
= NULL_RTX
;
962 int num_re_opportunities
= 0, num_realized
= 0, i
;
963 vec
<ext_cand
> reinsn_list
;
964 auto_vec
<rtx
> reinsn_del_list
;
965 auto_vec
<rtx
> reinsn_copy_list
;
968 /* Construct DU chain to get all reaching definitions of each
969 extension instruction. */
970 df_set_flags (DF_RD_PRUNE_DEAD_DEFS
);
971 df_chain_add_problem (DF_UD_CHAIN
+ DF_DU_CHAIN
);
973 df_set_flags (DF_DEFER_INSN_RESCAN
);
975 max_insn_uid
= get_max_uid ();
976 reinsn_list
= find_removable_extensions ();
977 state
.defs_list
.create (0);
978 state
.copies_list
.create (0);
979 state
.modified_list
.create (0);
980 state
.work_list
.create (0);
981 if (reinsn_list
.is_empty ())
982 state
.modified
= NULL
;
984 state
.modified
= XCNEWVEC (struct ext_modified
, max_insn_uid
);
986 FOR_EACH_VEC_ELT (reinsn_list
, i
, curr_cand
)
988 num_re_opportunities
++;
990 /* Try to combine the extension with the definition. */
993 fprintf (dump_file
, "Trying to eliminate extension:\n");
994 print_rtl_single (dump_file
, curr_cand
->insn
);
997 if (combine_reaching_defs (curr_cand
, curr_cand
->expr
, &state
))
1000 fprintf (dump_file
, "Eliminated the extension.\n");
1002 if (REGNO (SET_DEST (PATTERN (curr_cand
->insn
)))
1003 != REGNO (XEXP (SET_SRC (PATTERN (curr_cand
->insn
)), 0)))
1005 reinsn_copy_list
.safe_push (curr_cand
->insn
);
1006 reinsn_copy_list
.safe_push (state
.defs_list
[0]);
1008 reinsn_del_list
.safe_push (curr_cand
->insn
);
1009 state
.modified
[INSN_UID (curr_cand
->insn
)].deleted
= 1;
1013 /* The copy list contains pairs of insns which describe copies we
1014 need to insert into the INSN stream.
1016 The first insn in each pair is the extension insn, from which
1017 we derive the source and destination of the copy.
1019 The second insn in each pair is the memory reference where the
1020 extension will ultimately happen. We emit the new copy
1021 immediately after this insn.
1023 It may first appear that the arguments for the copy are reversed.
1024 Remember that the memory reference will be changed to refer to the
1025 destination of the extention. So we're actually emitting a copy
1026 from the new destination to the old destination. */
1027 for (unsigned int i
= 0; i
< reinsn_copy_list
.length (); i
+= 2)
1029 rtx curr_insn
= reinsn_copy_list
[i
];
1030 rtx def_insn
= reinsn_copy_list
[i
+ 1];
1032 /* Use the mode of the destination of the defining insn
1033 for the mode of the copy. This is necessary if the
1034 defining insn was used to eliminate a second extension
1035 that was wider than the first. */
1036 rtx sub_rtx
= *get_sub_rtx (def_insn
);
1037 rtx pat
= PATTERN (curr_insn
);
1038 rtx new_dst
= gen_rtx_REG (GET_MODE (SET_DEST (sub_rtx
)),
1039 REGNO (XEXP (SET_SRC (pat
), 0)));
1040 rtx new_src
= gen_rtx_REG (GET_MODE (SET_DEST (sub_rtx
)),
1041 REGNO (SET_DEST (pat
)));
1042 rtx set
= gen_rtx_SET (VOIDmode
, new_dst
, new_src
);
1043 emit_insn_after (set
, def_insn
);
1046 /* Delete all useless extensions here in one sweep. */
1047 FOR_EACH_VEC_ELT (reinsn_del_list
, i
, curr_insn
)
1048 delete_insn (curr_insn
);
1050 reinsn_list
.release ();
1051 state
.defs_list
.release ();
1052 state
.copies_list
.release ();
1053 state
.modified_list
.release ();
1054 state
.work_list
.release ();
1055 XDELETEVEC (state
.modified
);
1057 if (dump_file
&& num_re_opportunities
> 0)
1058 fprintf (dump_file
, "Elimination opportunities = %d realized = %d\n",
1059 num_re_opportunities
, num_realized
);
1062 /* Find and remove redundant extensions. */
1065 rest_of_handle_ree (void)
1067 timevar_push (TV_REE
);
1068 find_and_remove_re ();
1069 timevar_pop (TV_REE
);
1073 /* Run REE pass when flag_ree is set at optimization level > 0. */
1076 gate_handle_ree (void)
1078 return (optimize
> 0 && flag_ree
);
1083 const pass_data pass_data_ree
=
1085 RTL_PASS
, /* type */
1087 OPTGROUP_NONE
, /* optinfo_flags */
1088 true, /* has_gate */
1089 true, /* has_execute */
1091 0, /* properties_required */
1092 0, /* properties_provided */
1093 0, /* properties_destroyed */
1094 0, /* todo_flags_start */
1095 ( TODO_df_finish
| TODO_verify_rtl_sharing
), /* todo_flags_finish */
1098 class pass_ree
: public rtl_opt_pass
1101 pass_ree (gcc::context
*ctxt
)
1102 : rtl_opt_pass (pass_data_ree
, ctxt
)
1105 /* opt_pass methods: */
1106 bool gate () { return gate_handle_ree (); }
1107 unsigned int execute () { return rest_of_handle_ree (); }
1109 }; // class pass_ree
1114 make_pass_ree (gcc::context
*ctxt
)
1116 return new pass_ree (ctxt
);