1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
6 ;; Changes by Michael Meissner, meissner@osf.org
7 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 ;; Brendan Eich, brendan@microunity.com.
10 ;; This file is part of GCC.
12 ;; GCC is free software; you can redistribute it and/or modify
13 ;; it under the terms of the GNU General Public License as published by
14 ;; the Free Software Foundation; either version 3, or (at your option)
17 ;; GCC is distributed in the hope that it will be useful,
18 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
19 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 ;; GNU General Public License for more details.
22 ;; You should have received a copy of the GNU General Public License
23 ;; along with GCC; see the file COPYING3. If not see
24 ;; <http://www.gnu.org/licenses/>.
27 [(UNSPEC_LOAD_DF_LOW 0)
28 (UNSPEC_LOAD_DF_HIGH 1)
29 (UNSPEC_STORE_DF_HIGH 2)
33 (UNSPEC_NONLOCAL_GOTO_RECEIVER 6)
35 (UNSPEC_CONSTTABLE_INT 8)
36 (UNSPEC_CONSTTABLE_FLOAT 9)
40 (UNSPEC_LOAD_RIGHT 19)
41 (UNSPEC_STORE_LEFT 20)
42 (UNSPEC_STORE_RIGHT 21)
49 (UNSPEC_TLS_GET_TP 28)
52 (UNSPEC_CLEAR_HAZARD 33)
56 (UNSPEC_COMPARE_AND_SWAP 37)
57 (UNSPEC_SYNC_OLD_OP 38)
58 (UNSPEC_SYNC_NEW_OP 39)
59 (UNSPEC_SYNC_EXCHANGE 40)
60 (UNSPEC_MEMORY_BARRIER 41)
62 (UNSPEC_ADDRESS_FIRST 100)
66 ;; For MIPS Paired-Singled Floating Point Instructions.
68 (UNSPEC_MOVE_TF_PS 200)
71 ;; MIPS64/MIPS32R2 alnv.ps
74 ;; MIPS-3D instructions
78 (UNSPEC_CVT_PW_PS 205)
79 (UNSPEC_CVT_PS_PW 206)
87 (UNSPEC_SINGLE_CC 213)
90 ;; MIPS DSP ASE Revision 0.98 3/24/2005
98 (UNSPEC_RADDU_W_QB 307)
100 (UNSPEC_PRECRQ_QB_PH 309)
101 (UNSPEC_PRECRQ_PH_W 310)
102 (UNSPEC_PRECRQ_RS_PH_W 311)
103 (UNSPEC_PRECRQU_S_QB_PH 312)
104 (UNSPEC_PRECEQ_W_PHL 313)
105 (UNSPEC_PRECEQ_W_PHR 314)
106 (UNSPEC_PRECEQU_PH_QBL 315)
107 (UNSPEC_PRECEQU_PH_QBR 316)
108 (UNSPEC_PRECEQU_PH_QBLA 317)
109 (UNSPEC_PRECEQU_PH_QBRA 318)
110 (UNSPEC_PRECEU_PH_QBL 319)
111 (UNSPEC_PRECEU_PH_QBR 320)
112 (UNSPEC_PRECEU_PH_QBLA 321)
113 (UNSPEC_PRECEU_PH_QBRA 322)
119 (UNSPEC_MULEU_S_PH_QBL 328)
120 (UNSPEC_MULEU_S_PH_QBR 329)
121 (UNSPEC_MULQ_RS_PH 330)
122 (UNSPEC_MULEQ_S_W_PHL 331)
123 (UNSPEC_MULEQ_S_W_PHR 332)
124 (UNSPEC_DPAU_H_QBL 333)
125 (UNSPEC_DPAU_H_QBR 334)
126 (UNSPEC_DPSU_H_QBL 335)
127 (UNSPEC_DPSU_H_QBR 336)
128 (UNSPEC_DPAQ_S_W_PH 337)
129 (UNSPEC_DPSQ_S_W_PH 338)
130 (UNSPEC_MULSAQ_S_W_PH 339)
131 (UNSPEC_DPAQ_SA_L_W 340)
132 (UNSPEC_DPSQ_SA_L_W 341)
133 (UNSPEC_MAQ_S_W_PHL 342)
134 (UNSPEC_MAQ_S_W_PHR 343)
135 (UNSPEC_MAQ_SA_W_PHL 344)
136 (UNSPEC_MAQ_SA_W_PHR 345)
144 (UNSPEC_CMPGU_EQ_QB 353)
145 (UNSPEC_CMPGU_LT_QB 354)
146 (UNSPEC_CMPGU_LE_QB 355)
148 (UNSPEC_PACKRL_PH 357)
150 (UNSPEC_EXTR_R_W 359)
151 (UNSPEC_EXTR_RS_W 360)
152 (UNSPEC_EXTR_S_H 361)
160 ;; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
161 (UNSPEC_ABSQ_S_QB 400)
163 (UNSPEC_ADDU_S_PH 402)
164 (UNSPEC_ADDUH_QB 403)
165 (UNSPEC_ADDUH_R_QB 404)
168 (UNSPEC_CMPGDU_EQ_QB 407)
169 (UNSPEC_CMPGDU_LT_QB 408)
170 (UNSPEC_CMPGDU_LE_QB 409)
171 (UNSPEC_DPA_W_PH 410)
172 (UNSPEC_DPS_W_PH 411)
178 (UNSPEC_MUL_S_PH 417)
179 (UNSPEC_MULQ_RS_W 418)
180 (UNSPEC_MULQ_S_PH 419)
181 (UNSPEC_MULQ_S_W 420)
182 (UNSPEC_MULSA_W_PH 421)
185 (UNSPEC_PRECR_QB_PH 424)
186 (UNSPEC_PRECR_SRA_PH_W 425)
187 (UNSPEC_PRECR_SRA_R_PH_W 426)
190 (UNSPEC_SHRA_R_QB 429)
193 (UNSPEC_SUBU_S_PH 432)
194 (UNSPEC_SUBUH_QB 433)
195 (UNSPEC_SUBUH_R_QB 434)
196 (UNSPEC_ADDQH_PH 435)
197 (UNSPEC_ADDQH_R_PH 436)
199 (UNSPEC_ADDQH_R_W 438)
200 (UNSPEC_SUBQH_PH 439)
201 (UNSPEC_SUBQH_R_PH 440)
203 (UNSPEC_SUBQH_R_W 442)
204 (UNSPEC_DPAX_W_PH 443)
205 (UNSPEC_DPSX_W_PH 444)
206 (UNSPEC_DPAQX_S_W_PH 445)
207 (UNSPEC_DPAQX_SA_W_PH 446)
208 (UNSPEC_DPSQX_S_W_PH 447)
209 (UNSPEC_DPSQX_SA_W_PH 448)
213 (include "predicates.md")
214 (include "constraints.md")
216 ;; ....................
220 ;; ....................
222 (define_attr "got" "unset,xgot_high,load"
223 (const_string "unset"))
225 ;; For jal instructions, this attribute is DIRECT when the target address
226 ;; is symbolic and INDIRECT when it is a register.
227 (define_attr "jal" "unset,direct,indirect"
228 (const_string "unset"))
230 ;; This attribute is YES if the instruction is a jal macro (not a
231 ;; real jal instruction).
233 ;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
234 ;; an instruction to restore $gp. Direct jals are also macros for
235 ;; flag_pic && !TARGET_ABSOLUTE_ABICALLS because they first load
236 ;; the target address into a register.
237 (define_attr "jal_macro" "no,yes"
238 (cond [(eq_attr "jal" "direct")
239 (symbol_ref "TARGET_CALL_CLOBBERED_GP
240 || (flag_pic && !TARGET_ABSOLUTE_ABICALLS)")
241 (eq_attr "jal" "indirect")
242 (symbol_ref "TARGET_CALL_CLOBBERED_GP")]
243 (const_string "no")))
245 ;; Classification of each insn.
246 ;; branch conditional branch
247 ;; jump unconditional jump
248 ;; call unconditional call
249 ;; load load instruction(s)
250 ;; fpload floating point load
251 ;; fpidxload floating point indexed load
252 ;; store store instruction(s)
253 ;; fpstore floating point store
254 ;; fpidxstore floating point indexed store
255 ;; prefetch memory prefetch (register + offset)
256 ;; prefetchx memory indexed prefetch (register + register)
257 ;; condmove conditional moves
258 ;; mfc transfer from coprocessor
259 ;; mtc transfer to coprocessor
260 ;; mthilo transfer to hi/lo registers
261 ;; mfhilo transfer from hi/lo registers
262 ;; const load constant
263 ;; arith integer arithmetic instructions
264 ;; logical integer logical instructions
265 ;; shift integer shift instructions
266 ;; slt set less than instructions
267 ;; signext sign extend instructions
268 ;; clz the clz and clo instructions
269 ;; trap trap if instructions
270 ;; imul integer multiply 2 operands
271 ;; imul3 integer multiply 3 operands
272 ;; imadd integer multiply-add
273 ;; idiv integer divide
274 ;; move integer register move ({,D}ADD{,U} with rt = 0)
275 ;; fmove floating point register move
276 ;; fadd floating point add/subtract
277 ;; fmul floating point multiply
278 ;; fmadd floating point multiply-add
279 ;; fdiv floating point divide
280 ;; frdiv floating point reciprocal divide
281 ;; frdiv1 floating point reciprocal divide step 1
282 ;; frdiv2 floating point reciprocal divide step 2
283 ;; fabs floating point absolute value
284 ;; fneg floating point negation
285 ;; fcmp floating point compare
286 ;; fcvt floating point convert
287 ;; fsqrt floating point square root
288 ;; frsqrt floating point reciprocal square root
289 ;; frsqrt1 floating point reciprocal square root step1
290 ;; frsqrt2 floating point reciprocal square root step2
291 ;; multi multiword sequence (or user asm statements)
294 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,mfc,mtc,mthilo,mfhilo,const,arith,logical,shift,slt,signext,clz,trap,imul,imul3,imadd,idiv,move,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"
295 (cond [(eq_attr "jal" "!unset") (const_string "call")
296 (eq_attr "got" "load") (const_string "load")]
297 (const_string "unknown")))
299 ;; Main data type used by the insn
300 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW"
301 (const_string "unknown"))
303 ;; Mode for conversion types (fcvt)
304 ;; I2S integer to float single (SI/DI to SF)
305 ;; I2D integer to float double (SI/DI to DF)
306 ;; S2I float to integer (SF to SI/DI)
307 ;; D2I float to integer (DF to SI/DI)
308 ;; D2S double to float single
309 ;; S2D float single to double
311 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
312 (const_string "unknown"))
314 ;; Is this an extended instruction in mips16 mode?
315 (define_attr "extended_mips16" "no,yes"
318 ;; Length of instruction in bytes.
319 (define_attr "length" ""
320 (cond [;; Direct branch instructions have a range of [-0x40000,0x3fffc].
321 ;; If a branch is outside this range, we have a choice of two
322 ;; sequences. For PIC, an out-of-range branch like:
327 ;; becomes the equivalent of:
336 ;; where the load address can be up to three instructions long
339 ;; The non-PIC case is similar except that we use a direct
340 ;; jump instead of an la/jr pair. Since the target of this
341 ;; jump is an absolute 28-bit bit address (the other bits
342 ;; coming from the address of the delay slot) this form cannot
343 ;; cross a 256MB boundary. We could provide the option of
344 ;; using la/jr in this case too, but we do not do so at
347 ;; Note that this value does not account for the delay slot
348 ;; instruction, whose length is added separately. If the RTL
349 ;; pattern has no explicit delay slot, mips_adjust_insn_length
350 ;; will add the length of the implicit nop. The values for
351 ;; forward and backward branches will be different as well.
352 (eq_attr "type" "branch")
353 (cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064))
354 (le (minus (pc) (match_dup 1)) (const_int 131068)))
356 (ne (symbol_ref "flag_pic") (const_int 0))
360 (eq_attr "got" "load")
362 (eq_attr "got" "xgot_high")
365 (eq_attr "type" "const")
366 (symbol_ref "mips_const_insns (operands[1]) * 4")
367 (eq_attr "type" "load,fpload")
368 (symbol_ref "mips_load_store_insns (operands[1], insn) * 4")
369 (eq_attr "type" "store,fpstore")
370 (symbol_ref "mips_load_store_insns (operands[0], insn) * 4")
372 ;; In the worst case, a call macro will take 8 instructions:
374 ;; lui $25,%call_hi(FOO)
376 ;; lw $25,%call_lo(FOO)($25)
382 (eq_attr "jal_macro" "yes")
385 (and (eq_attr "extended_mips16" "yes")
386 (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
389 ;; Various VR4120 errata require a nop to be inserted after a macc
390 ;; instruction. The assembler does this for us, so account for
391 ;; the worst-case length here.
392 (and (eq_attr "type" "imadd")
393 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))
396 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
397 ;; the result of the second one is missed. The assembler should work
398 ;; around this by inserting a nop after the first dmult.
399 (and (eq_attr "type" "imul,imul3")
400 (and (eq_attr "mode" "DI")
401 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
404 (eq_attr "type" "idiv")
405 (symbol_ref "mips_idiv_insns () * 4")
408 ;; Attribute describing the processor. This attribute must match exactly
409 ;; with the processor_type enumeration in mips.h.
411 "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000"
412 (const (symbol_ref "mips_tune")))
414 ;; The type of hardware hazard associated with this instruction.
415 ;; DELAY means that the next instruction cannot read the result
416 ;; of this one. HILO means that the next two instructions cannot
417 ;; write to HI or LO.
418 (define_attr "hazard" "none,delay,hilo"
419 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
420 (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
421 (const_string "delay")
423 (and (eq_attr "type" "mfc,mtc")
424 (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
425 (const_string "delay")
427 (and (eq_attr "type" "fcmp")
428 (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
429 (const_string "delay")
431 ;; The r4000 multiplication patterns include an mflo instruction.
432 (and (eq_attr "type" "imul")
433 (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
434 (const_string "hilo")
436 (and (eq_attr "type" "mfhilo")
437 (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
438 (const_string "hilo")]
439 (const_string "none")))
441 ;; Is it a single instruction?
442 (define_attr "single_insn" "no,yes"
443 (symbol_ref "get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)"))
445 ;; Can the instruction be put into a delay slot?
446 (define_attr "can_delay" "no,yes"
447 (if_then_else (and (eq_attr "type" "!branch,call,jump")
448 (and (eq_attr "hazard" "none")
449 (eq_attr "single_insn" "yes")))
451 (const_string "no")))
453 ;; Attribute defining whether or not we can use the branch-likely instructions
454 (define_attr "branch_likely" "no,yes"
456 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
458 (const_string "no"))))
460 ;; True if an instruction might assign to hi or lo when reloaded.
461 ;; This is used by the TUNE_MACC_CHAINS code.
462 (define_attr "may_clobber_hilo" "no,yes"
463 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
465 (const_string "no")))
467 ;; Describe a user's asm statement.
468 (define_asm_attributes
469 [(set_attr "type" "multi")
470 (set_attr "can_delay" "no")])
472 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
473 ;; from the same template.
474 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
476 ;; This mode iterator allows :P to be used for patterns that operate on
477 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
478 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
480 ;; This mode iterator allows :MOVECC to be used anywhere that a
481 ;; conditional-move-type condition is needed.
482 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
484 ;; This mode iterator allows the QI and HI extension patterns to be
485 ;; defined from the same template.
486 (define_mode_iterator SHORT [QI HI])
488 ;; Likewise the 64-bit truncate-and-shift patterns.
489 (define_mode_iterator SUBDI [QI HI SI])
491 ;; This mode iterator allows :ANYF to be used wherever a scalar or vector
492 ;; floating-point mode is allowed.
493 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
494 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
495 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
497 ;; Like ANYF, but only applies to scalar modes.
498 (define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
499 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
501 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
502 ;; 32-bit version and "dsubu" in the 64-bit version.
503 (define_mode_attr d [(SI "") (DI "d")
504 (QQ "") (HQ "") (SQ "") (DQ "d")
505 (UQQ "") (UHQ "") (USQ "") (UDQ "d")
506 (HA "") (SA "") (DA "d")
507 (UHA "") (USA "") (UDA "d")])
509 ;; This attribute gives the length suffix for a sign- or zero-extension
511 (define_mode_attr size [(QI "b") (HI "h")])
513 ;; This attributes gives the mode mask of a SHORT.
514 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
516 ;; Mode attributes for GPR loads and stores.
517 (define_mode_attr load [(SI "lw") (DI "ld")])
518 (define_mode_attr store [(SI "sw") (DI "sd")])
520 ;; Similarly for MIPS IV indexed FPR loads and stores.
521 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
522 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
524 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
525 ;; are different. Some forms of unextended addiu have an 8-bit immediate
526 ;; field but the equivalent daddiu has only a 5-bit field.
527 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
529 ;; This attribute gives the best constraint to use for registers of
531 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
533 ;; This attribute gives the format suffix for floating-point operations.
534 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
536 ;; This attribute gives the upper-case mode name for one unit of a
537 ;; floating-point mode.
538 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
540 ;; This attribute gives the integer mode that has the same size as a
542 (define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI")
543 (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI")
544 (HA "HI") (SA "SI") (DA "DI")
545 (UHA "HI") (USA "SI") (UDA "DI")
546 (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")
547 (V2HQ "SI") (V2HA "SI")])
549 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
551 ;; In certain cases, div.s and div.ps may have a rounding error
552 ;; and/or wrong inexact flag.
554 ;; Therefore, we only allow div.s if not working around SB-1 rev2
555 ;; errata or if a slight loss of precision is OK.
556 (define_mode_attr divide_condition
557 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
558 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
560 ; This attribute gives the condition for which sqrt instructions exist.
561 (define_mode_attr sqrt_condition
562 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
564 ; This attribute gives the condition for which recip and rsqrt instructions
566 (define_mode_attr recip_condition
567 [(SF "ISA_HAS_FP4") (DF "ISA_HAS_FP4") (V2SF "TARGET_SB1")])
569 ;; This code iterator allows all branch instructions to be generated from
570 ;; a single define_expand template.
571 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
572 eq ne gt ge lt le gtu geu ltu leu])
574 ;; This code iterator allows signed and unsigned widening multiplications
575 ;; to use the same template.
576 (define_code_iterator any_extend [sign_extend zero_extend])
578 ;; This code iterator allows the three shift instructions to be generated
579 ;; from the same template.
580 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
582 ;; This code iterator allows all native floating-point comparisons to be
583 ;; generated from the same template.
584 (define_code_iterator fcond [unordered uneq unlt unle eq lt le])
586 ;; This code iterator is used for comparisons that can be implemented
587 ;; by swapping the operands.
588 (define_code_iterator swapped_fcond [ge gt unge ungt])
590 ;; <u> expands to an empty string when doing a signed operation and
591 ;; "u" when doing an unsigned operation.
592 (define_code_attr u [(sign_extend "") (zero_extend "u")])
594 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
595 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
597 ;; <optab> expands to the name of the optab for a particular code.
598 (define_code_attr optab [(ashift "ashl")
605 ;; <insn> expands to the name of the insn that implements a particular code.
606 (define_code_attr insn [(ashift "sll")
613 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
614 (define_code_attr fcond [(unordered "un")
622 ;; Similar, but for swapped conditions.
623 (define_code_attr swapped_fcond [(ge "le")
628 ;; Atomic fetch bitwise operations.
629 (define_code_iterator fetchop_bit [ior xor and])
631 ;; <immediate_insn> expands to the name of the insn that implements
632 ;; a particular code to operate in immediate values.
633 (define_code_attr immediate_insn [(ior "ori") (xor "xori") (and "andi")])
636 ;; .........................
638 ;; Branch, call and jump delay slots
640 ;; .........................
642 (define_delay (and (eq_attr "type" "branch")
643 (eq (symbol_ref "TARGET_MIPS16") (const_int 0)))
644 [(eq_attr "can_delay" "yes")
646 (and (eq_attr "branch_likely" "yes")
647 (eq_attr "can_delay" "yes"))])
649 (define_delay (eq_attr "type" "jump")
650 [(eq_attr "can_delay" "yes")
654 (define_delay (and (eq_attr "type" "call")
655 (eq_attr "jal_macro" "no"))
656 [(eq_attr "can_delay" "yes")
660 ;; Pipeline descriptions.
662 ;; generic.md provides a fallback for processors without a specific
663 ;; pipeline description. It is derived from the old define_function_unit
664 ;; version and uses the "alu" and "imuldiv" units declared below.
666 ;; Some of the processor-specific files are also derived from old
667 ;; define_function_unit descriptions and simply override the parts of
668 ;; generic.md that don't apply. The other processor-specific files
669 ;; are self-contained.
670 (define_automaton "alu,imuldiv")
672 (define_cpu_unit "alu" "alu")
673 (define_cpu_unit "imuldiv" "imuldiv")
694 (include "generic.md")
697 ;; ....................
701 ;; ....................
705 [(trap_if (const_int 1) (const_int 0))]
708 if (ISA_HAS_COND_TRAP)
710 else if (TARGET_MIPS16)
715 [(set_attr "type" "trap")])
717 (define_expand "conditional_trap"
718 [(trap_if (match_operator 0 "comparison_operator"
719 [(match_dup 2) (match_dup 3)])
720 (match_operand 1 "const_int_operand"))]
723 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT
724 && operands[1] == const0_rtx)
726 mips_gen_conditional_trap (operands);
733 (define_insn "*conditional_trap<mode>"
734 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
735 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
736 (match_operand:GPR 2 "arith_operand" "dI")])
740 [(set_attr "type" "trap")])
743 ;; ....................
747 ;; ....................
750 (define_insn "add<mode>3"
751 [(set (match_operand:ANYF 0 "register_operand" "=f")
752 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
753 (match_operand:ANYF 2 "register_operand" "f")))]
755 "add.<fmt>\t%0,%1,%2"
756 [(set_attr "type" "fadd")
757 (set_attr "mode" "<UNITMODE>")])
759 (define_expand "add<mode>3"
760 [(set (match_operand:GPR 0 "register_operand")
761 (plus:GPR (match_operand:GPR 1 "register_operand")
762 (match_operand:GPR 2 "arith_operand")))]
765 (define_insn "*add<mode>3"
766 [(set (match_operand:GPR 0 "register_operand" "=d,d")
767 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
768 (match_operand:GPR 2 "arith_operand" "d,Q")))]
773 [(set_attr "type" "arith")
774 (set_attr "mode" "<MODE>")])
776 (define_insn "*add<mode>3_mips16"
777 [(set (match_operand:GPR 0 "register_operand" "=ks,d,d,d,d")
778 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,0,d,d")
779 (match_operand:GPR 2 "arith_operand" "Q,Q,Q,O,d")))]
787 [(set_attr "type" "arith")
788 (set_attr "mode" "<MODE>")
789 (set_attr_alternative "length"
790 [(if_then_else (match_operand 2 "m16_simm8_8")
793 (if_then_else (match_operand 2 "m16_uimm<si8_di5>_4")
796 (if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
799 (if_then_else (match_operand 2 "m16_simm4_1")
804 ;; On the mips16, we can sometimes split an add of a constant which is
805 ;; a 4 byte instruction into two adds which are both 2 byte
806 ;; instructions. There are two cases: one where we are adding a
807 ;; constant plus a register to another register, and one where we are
808 ;; simply adding a constant to a register.
811 [(set (match_operand:SI 0 "register_operand")
812 (plus:SI (match_dup 0)
813 (match_operand:SI 1 "const_int_operand")))]
814 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
815 && REG_P (operands[0])
816 && M16_REG_P (REGNO (operands[0]))
817 && GET_CODE (operands[1]) == CONST_INT
818 && ((INTVAL (operands[1]) > 0x7f
819 && INTVAL (operands[1]) <= 0x7f + 0x7f)
820 || (INTVAL (operands[1]) < - 0x80
821 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
822 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
823 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
825 HOST_WIDE_INT val = INTVAL (operands[1]);
829 operands[1] = GEN_INT (0x7f);
830 operands[2] = GEN_INT (val - 0x7f);
834 operands[1] = GEN_INT (- 0x80);
835 operands[2] = GEN_INT (val + 0x80);
840 [(set (match_operand:SI 0 "register_operand")
841 (plus:SI (match_operand:SI 1 "register_operand")
842 (match_operand:SI 2 "const_int_operand")))]
843 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
844 && REG_P (operands[0])
845 && M16_REG_P (REGNO (operands[0]))
846 && REG_P (operands[1])
847 && M16_REG_P (REGNO (operands[1]))
848 && REGNO (operands[0]) != REGNO (operands[1])
849 && GET_CODE (operands[2]) == CONST_INT
850 && ((INTVAL (operands[2]) > 0x7
851 && INTVAL (operands[2]) <= 0x7 + 0x7f)
852 || (INTVAL (operands[2]) < - 0x8
853 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
854 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
855 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
857 HOST_WIDE_INT val = INTVAL (operands[2]);
861 operands[2] = GEN_INT (0x7);
862 operands[3] = GEN_INT (val - 0x7);
866 operands[2] = GEN_INT (- 0x8);
867 operands[3] = GEN_INT (val + 0x8);
872 [(set (match_operand:DI 0 "register_operand")
873 (plus:DI (match_dup 0)
874 (match_operand:DI 1 "const_int_operand")))]
875 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
876 && REG_P (operands[0])
877 && M16_REG_P (REGNO (operands[0]))
878 && GET_CODE (operands[1]) == CONST_INT
879 && ((INTVAL (operands[1]) > 0xf
880 && INTVAL (operands[1]) <= 0xf + 0xf)
881 || (INTVAL (operands[1]) < - 0x10
882 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
883 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
884 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
886 HOST_WIDE_INT val = INTVAL (operands[1]);
890 operands[1] = GEN_INT (0xf);
891 operands[2] = GEN_INT (val - 0xf);
895 operands[1] = GEN_INT (- 0x10);
896 operands[2] = GEN_INT (val + 0x10);
901 [(set (match_operand:DI 0 "register_operand")
902 (plus:DI (match_operand:DI 1 "register_operand")
903 (match_operand:DI 2 "const_int_operand")))]
904 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
905 && REG_P (operands[0])
906 && M16_REG_P (REGNO (operands[0]))
907 && REG_P (operands[1])
908 && M16_REG_P (REGNO (operands[1]))
909 && REGNO (operands[0]) != REGNO (operands[1])
910 && GET_CODE (operands[2]) == CONST_INT
911 && ((INTVAL (operands[2]) > 0x7
912 && INTVAL (operands[2]) <= 0x7 + 0xf)
913 || (INTVAL (operands[2]) < - 0x8
914 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
915 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
916 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
918 HOST_WIDE_INT val = INTVAL (operands[2]);
922 operands[2] = GEN_INT (0x7);
923 operands[3] = GEN_INT (val - 0x7);
927 operands[2] = GEN_INT (- 0x8);
928 operands[3] = GEN_INT (val + 0x8);
932 (define_insn "*addsi3_extended"
933 [(set (match_operand:DI 0 "register_operand" "=d,d")
935 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
936 (match_operand:SI 2 "arith_operand" "d,Q"))))]
937 "TARGET_64BIT && !TARGET_MIPS16"
941 [(set_attr "type" "arith")
942 (set_attr "mode" "SI")])
944 ;; Split this insn so that the addiu splitters can have a crack at it.
945 ;; Use a conservative length estimate until the split.
946 (define_insn_and_split "*addsi3_extended_mips16"
947 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
949 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
950 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
951 "TARGET_64BIT && TARGET_MIPS16"
953 "&& reload_completed"
954 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
955 { operands[3] = gen_lowpart (SImode, operands[0]); }
956 [(set_attr "type" "arith")
957 (set_attr "mode" "SI")
958 (set_attr "extended_mips16" "yes")])
961 ;; ....................
965 ;; ....................
968 (define_insn "sub<mode>3"
969 [(set (match_operand:ANYF 0 "register_operand" "=f")
970 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
971 (match_operand:ANYF 2 "register_operand" "f")))]
973 "sub.<fmt>\t%0,%1,%2"
974 [(set_attr "type" "fadd")
975 (set_attr "mode" "<UNITMODE>")])
977 (define_insn "sub<mode>3"
978 [(set (match_operand:GPR 0 "register_operand" "=d")
979 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
980 (match_operand:GPR 2 "register_operand" "d")))]
983 [(set_attr "type" "arith")
984 (set_attr "mode" "<MODE>")])
986 (define_insn "*subsi3_extended"
987 [(set (match_operand:DI 0 "register_operand" "=d")
989 (minus:SI (match_operand:SI 1 "register_operand" "d")
990 (match_operand:SI 2 "register_operand" "d"))))]
993 [(set_attr "type" "arith")
994 (set_attr "mode" "DI")])
997 ;; ....................
1001 ;; ....................
1004 (define_expand "mul<mode>3"
1005 [(set (match_operand:SCALARF 0 "register_operand")
1006 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
1007 (match_operand:SCALARF 2 "register_operand")))]
1011 (define_insn "*mul<mode>3"
1012 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1013 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1014 (match_operand:SCALARF 2 "register_operand" "f")))]
1015 "!TARGET_4300_MUL_FIX"
1016 "mul.<fmt>\t%0,%1,%2"
1017 [(set_attr "type" "fmul")
1018 (set_attr "mode" "<MODE>")])
1020 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
1021 ;; operands may corrupt immediately following multiplies. This is a
1022 ;; simple fix to insert NOPs.
1024 (define_insn "*mul<mode>3_r4300"
1025 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1026 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1027 (match_operand:SCALARF 2 "register_operand" "f")))]
1028 "TARGET_4300_MUL_FIX"
1029 "mul.<fmt>\t%0,%1,%2\;nop"
1030 [(set_attr "type" "fmul")
1031 (set_attr "mode" "<MODE>")
1032 (set_attr "length" "8")])
1034 (define_insn "mulv2sf3"
1035 [(set (match_operand:V2SF 0 "register_operand" "=f")
1036 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1037 (match_operand:V2SF 2 "register_operand" "f")))]
1038 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
1040 [(set_attr "type" "fmul")
1041 (set_attr "mode" "SF")])
1043 ;; The original R4000 has a cpu bug. If a double-word or a variable
1044 ;; shift executes while an integer multiplication is in progress, the
1045 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1046 ;; with the mult on the R4000.
1048 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1049 ;; (also valid for MIPS R4000MC processors):
1051 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1052 ;; this errata description.
1053 ;; The following code sequence causes the R4000 to incorrectly
1054 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1055 ;; instruction. If the dsra32 instruction is executed during an
1056 ;; integer multiply, the dsra32 will only shift by the amount in
1057 ;; specified in the instruction rather than the amount plus 32
1059 ;; instruction 1: mult rs,rt integer multiply
1060 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1061 ;; right arithmetic + 32
1062 ;; Workaround: A dsra32 instruction placed after an integer
1063 ;; multiply should not be one of the 11 instructions after the
1064 ;; multiply instruction."
1068 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1069 ;; the following description.
1070 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1071 ;; 64-bit versions) may produce incorrect results under the
1072 ;; following conditions:
1073 ;; 1) An integer multiply is currently executing
1074 ;; 2) These types of shift instructions are executed immediately
1075 ;; following an integer divide instruction.
1077 ;; 1) Make sure no integer multiply is running wihen these
1078 ;; instruction are executed. If this cannot be predicted at
1079 ;; compile time, then insert a "mfhi" to R0 instruction
1080 ;; immediately after the integer multiply instruction. This
1081 ;; will cause the integer multiply to complete before the shift
1083 ;; 2) Separate integer divide and these two classes of shift
1084 ;; instructions by another instruction or a noop."
1086 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1089 (define_expand "mulsi3"
1090 [(set (match_operand:SI 0 "register_operand")
1091 (mult:SI (match_operand:SI 1 "register_operand")
1092 (match_operand:SI 2 "register_operand")))]
1096 emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
1097 else if (TARGET_FIX_R4000)
1098 emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
1100 emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
1104 (define_expand "muldi3"
1105 [(set (match_operand:DI 0 "register_operand")
1106 (mult:DI (match_operand:DI 1 "register_operand")
1107 (match_operand:DI 2 "register_operand")))]
1110 if (TARGET_FIX_R4000)
1111 emit_insn (gen_muldi3_r4000 (operands[0], operands[1], operands[2]));
1113 emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
1117 (define_insn "mulsi3_mult3"
1118 [(set (match_operand:SI 0 "register_operand" "=d,l")
1119 (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1120 (match_operand:SI 2 "register_operand" "d,d")))
1121 (clobber (match_scratch:SI 3 "=h,h"))
1122 (clobber (match_scratch:SI 4 "=l,X"))]
1125 if (which_alternative == 1)
1126 return "mult\t%1,%2";
1127 if (TARGET_MIPS3900)
1128 return "mult\t%0,%1,%2";
1129 return "mul\t%0,%1,%2";
1131 [(set_attr "type" "imul3,imul")
1132 (set_attr "mode" "SI")])
1134 ;; If a register gets allocated to LO, and we spill to memory, the reload
1135 ;; will include a move from LO to a GPR. Merge it into the multiplication
1136 ;; if it can set the GPR directly.
1139 ;; Operand 1: GPR (1st multiplication operand)
1140 ;; Operand 2: GPR (2nd multiplication operand)
1142 ;; Operand 4: GPR (destination)
1145 [(set (match_operand:SI 0 "register_operand")
1146 (mult:SI (match_operand:SI 1 "register_operand")
1147 (match_operand:SI 2 "register_operand")))
1148 (clobber (match_operand:SI 3 "register_operand"))
1149 (clobber (scratch:SI))])
1150 (set (match_operand:SI 4 "register_operand")
1151 (unspec [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1152 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1155 (mult:SI (match_dup 1)
1157 (clobber (match_dup 3))
1158 (clobber (match_dup 0))])])
1160 (define_insn "mul<mode>3_internal"
1161 [(set (match_operand:GPR 0 "register_operand" "=l")
1162 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1163 (match_operand:GPR 2 "register_operand" "d")))
1164 (clobber (match_scratch:GPR 3 "=h"))]
1167 [(set_attr "type" "imul")
1168 (set_attr "mode" "<MODE>")])
1170 (define_insn "mul<mode>3_r4000"
1171 [(set (match_operand:GPR 0 "register_operand" "=d")
1172 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1173 (match_operand:GPR 2 "register_operand" "d")))
1174 (clobber (match_scratch:GPR 3 "=h"))
1175 (clobber (match_scratch:GPR 4 "=l"))]
1177 "<d>mult\t%1,%2\;mflo\t%0"
1178 [(set_attr "type" "imul")
1179 (set_attr "mode" "<MODE>")
1180 (set_attr "length" "8")])
1182 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1183 ;; of "mult; mflo". They have the same latency, but the first form gives
1184 ;; us an extra cycle to compute the operands.
1187 ;; Operand 1: GPR (1st multiplication operand)
1188 ;; Operand 2: GPR (2nd multiplication operand)
1190 ;; Operand 4: GPR (destination)
1193 [(set (match_operand:SI 0 "register_operand")
1194 (mult:SI (match_operand:SI 1 "register_operand")
1195 (match_operand:SI 2 "register_operand")))
1196 (clobber (match_operand:SI 3 "register_operand"))])
1197 (set (match_operand:SI 4 "register_operand")
1198 (unspec:SI [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1199 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1204 (plus:SI (mult:SI (match_dup 1)
1208 (plus:SI (mult:SI (match_dup 1)
1211 (clobber (match_dup 3))])])
1213 ;; Multiply-accumulate patterns
1215 ;; For processors that can copy the output to a general register:
1217 ;; The all-d alternative is needed because the combiner will find this
1218 ;; pattern and then register alloc/reload will move registers around to
1219 ;; make them fit, and we don't want to trigger unnecessary loads to LO.
1221 ;; The last alternative should be made slightly less desirable, but adding
1222 ;; "?" to the constraint is too strong, and causes values to be loaded into
1223 ;; LO even when that's more costly. For now, using "*d" mostly does the
1225 (define_insn "*mul_acc_si"
1226 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1227 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1228 (match_operand:SI 2 "register_operand" "d,d,d"))
1229 (match_operand:SI 3 "register_operand" "0,l,*d")))
1230 (clobber (match_scratch:SI 4 "=h,h,h"))
1231 (clobber (match_scratch:SI 5 "=X,3,l"))
1232 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1234 || GENERATE_MADD_MSUB)
1237 static const char *const madd[] = { "madd\t%1,%2", "madd\t%0,%1,%2" };
1238 if (which_alternative == 2)
1240 if (GENERATE_MADD_MSUB && which_alternative != 0)
1242 return madd[which_alternative];
1244 [(set_attr "type" "imadd")
1245 (set_attr "mode" "SI")
1246 (set_attr "length" "4,4,8")])
1248 ;; Split the above insn if we failed to get LO allocated.
1250 [(set (match_operand:SI 0 "register_operand")
1251 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1252 (match_operand:SI 2 "register_operand"))
1253 (match_operand:SI 3 "register_operand")))
1254 (clobber (match_scratch:SI 4))
1255 (clobber (match_scratch:SI 5))
1256 (clobber (match_scratch:SI 6))]
1257 "reload_completed && !TARGET_DEBUG_D_MODE
1258 && GP_REG_P (true_regnum (operands[0]))
1259 && GP_REG_P (true_regnum (operands[3]))"
1260 [(parallel [(set (match_dup 6)
1261 (mult:SI (match_dup 1) (match_dup 2)))
1262 (clobber (match_dup 4))
1263 (clobber (match_dup 5))])
1264 (set (match_dup 0) (plus:SI (match_dup 6) (match_dup 3)))]
1267 ;; Splitter to copy result of MADD to a general register
1269 [(set (match_operand:SI 0 "register_operand")
1270 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1271 (match_operand:SI 2 "register_operand"))
1272 (match_operand:SI 3 "register_operand")))
1273 (clobber (match_scratch:SI 4))
1274 (clobber (match_scratch:SI 5))
1275 (clobber (match_scratch:SI 6))]
1276 "reload_completed && !TARGET_DEBUG_D_MODE
1277 && GP_REG_P (true_regnum (operands[0]))
1278 && true_regnum (operands[3]) == LO_REGNUM"
1279 [(parallel [(set (match_dup 3)
1280 (plus:SI (mult:SI (match_dup 1) (match_dup 2))
1282 (clobber (match_dup 4))
1283 (clobber (match_dup 5))
1284 (clobber (match_dup 6))])
1285 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1288 (define_insn "*macc"
1289 [(set (match_operand:SI 0 "register_operand" "=l,d")
1290 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1291 (match_operand:SI 2 "register_operand" "d,d"))
1292 (match_operand:SI 3 "register_operand" "0,l")))
1293 (clobber (match_scratch:SI 4 "=h,h"))
1294 (clobber (match_scratch:SI 5 "=X,3"))]
1297 if (which_alternative == 1)
1298 return "macc\t%0,%1,%2";
1299 else if (TARGET_MIPS5500)
1300 return "madd\t%1,%2";
1302 /* The VR4130 assumes that there is a two-cycle latency between a macc
1303 that "writes" to $0 and an instruction that reads from it. We avoid
1304 this by assigning to $1 instead. */
1305 return "%[macc\t%@,%1,%2%]";
1307 [(set_attr "type" "imadd")
1308 (set_attr "mode" "SI")])
1310 (define_insn "*msac"
1311 [(set (match_operand:SI 0 "register_operand" "=l,d")
1312 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1313 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1314 (match_operand:SI 3 "register_operand" "d,d"))))
1315 (clobber (match_scratch:SI 4 "=h,h"))
1316 (clobber (match_scratch:SI 5 "=X,1"))]
1319 if (which_alternative == 1)
1320 return "msac\t%0,%2,%3";
1321 else if (TARGET_MIPS5500)
1322 return "msub\t%2,%3";
1324 return "msac\t$0,%2,%3";
1326 [(set_attr "type" "imadd")
1327 (set_attr "mode" "SI")])
1329 ;; An msac-like instruction implemented using negation and a macc.
1330 (define_insn_and_split "*msac_using_macc"
1331 [(set (match_operand:SI 0 "register_operand" "=l,d")
1332 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1333 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1334 (match_operand:SI 3 "register_operand" "d,d"))))
1335 (clobber (match_scratch:SI 4 "=h,h"))
1336 (clobber (match_scratch:SI 5 "=X,1"))
1337 (clobber (match_scratch:SI 6 "=d,d"))]
1338 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1340 "&& reload_completed"
1342 (neg:SI (match_dup 3)))
1345 (plus:SI (mult:SI (match_dup 2)
1348 (clobber (match_dup 4))
1349 (clobber (match_dup 5))])]
1351 [(set_attr "type" "imadd")
1352 (set_attr "length" "8")])
1354 ;; Patterns generated by the define_peephole2 below.
1356 (define_insn "*macc2"
1357 [(set (match_operand:SI 0 "register_operand" "=l")
1358 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1359 (match_operand:SI 2 "register_operand" "d"))
1361 (set (match_operand:SI 3 "register_operand" "=d")
1362 (plus:SI (mult:SI (match_dup 1)
1365 (clobber (match_scratch:SI 4 "=h"))]
1366 "ISA_HAS_MACC && reload_completed"
1368 [(set_attr "type" "imadd")
1369 (set_attr "mode" "SI")])
1371 (define_insn "*msac2"
1372 [(set (match_operand:SI 0 "register_operand" "=l")
1373 (minus:SI (match_dup 0)
1374 (mult:SI (match_operand:SI 1 "register_operand" "d")
1375 (match_operand:SI 2 "register_operand" "d"))))
1376 (set (match_operand:SI 3 "register_operand" "=d")
1377 (minus:SI (match_dup 0)
1378 (mult:SI (match_dup 1)
1380 (clobber (match_scratch:SI 4 "=h"))]
1381 "ISA_HAS_MSAC && reload_completed"
1383 [(set_attr "type" "imadd")
1384 (set_attr "mode" "SI")])
1386 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1390 ;; Operand 1: macc/msac
1392 ;; Operand 3: GPR (destination)
1395 [(set (match_operand:SI 0 "register_operand")
1396 (match_operand:SI 1 "macc_msac_operand"))
1397 (clobber (match_operand:SI 2 "register_operand"))
1398 (clobber (scratch:SI))])
1399 (set (match_operand:SI 3 "register_operand")
1400 (unspec:SI [(match_dup 0) (match_dup 2)] UNSPEC_MFHILO))]
1402 [(parallel [(set (match_dup 0)
1406 (clobber (match_dup 2))])]
1409 ;; When we have a three-address multiplication instruction, it should
1410 ;; be faster to do a separate multiply and add, rather than moving
1411 ;; something into LO in order to use a macc instruction.
1413 ;; This peephole needs a scratch register to cater for the case when one
1414 ;; of the multiplication operands is the same as the destination.
1416 ;; Operand 0: GPR (scratch)
1418 ;; Operand 2: GPR (addend)
1419 ;; Operand 3: GPR (destination)
1420 ;; Operand 4: macc/msac
1422 ;; Operand 6: new multiplication
1423 ;; Operand 7: new addition/subtraction
1425 [(match_scratch:SI 0 "d")
1426 (set (match_operand:SI 1 "register_operand")
1427 (match_operand:SI 2 "register_operand"))
1430 [(set (match_operand:SI 3 "register_operand")
1431 (match_operand:SI 4 "macc_msac_operand"))
1432 (clobber (match_operand:SI 5 "register_operand"))
1433 (clobber (match_dup 1))])]
1435 && true_regnum (operands[1]) == LO_REGNUM
1436 && peep2_reg_dead_p (2, operands[1])
1437 && GP_REG_P (true_regnum (operands[3]))"
1438 [(parallel [(set (match_dup 0)
1440 (clobber (match_dup 5))
1441 (clobber (match_dup 1))])
1445 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1446 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1447 operands[2], operands[0]);
1450 ;; Same as above, except LO is the initial target of the macc.
1452 ;; Operand 0: GPR (scratch)
1454 ;; Operand 2: GPR (addend)
1455 ;; Operand 3: macc/msac
1457 ;; Operand 5: GPR (destination)
1458 ;; Operand 6: new multiplication
1459 ;; Operand 7: new addition/subtraction
1461 [(match_scratch:SI 0 "d")
1462 (set (match_operand:SI 1 "register_operand")
1463 (match_operand:SI 2 "register_operand"))
1467 (match_operand:SI 3 "macc_msac_operand"))
1468 (clobber (match_operand:SI 4 "register_operand"))
1469 (clobber (scratch:SI))])
1471 (set (match_operand:SI 5 "register_operand")
1472 (unspec:SI [(match_dup 1) (match_dup 4)] UNSPEC_MFHILO))]
1473 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1474 [(parallel [(set (match_dup 0)
1476 (clobber (match_dup 4))
1477 (clobber (match_dup 1))])
1481 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1482 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1483 operands[2], operands[0]);
1486 (define_insn "*mul_sub_si"
1487 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1488 (minus:SI (match_operand:SI 1 "register_operand" "0,l,*d")
1489 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
1490 (match_operand:SI 3 "register_operand" "d,d,d"))))
1491 (clobber (match_scratch:SI 4 "=h,h,h"))
1492 (clobber (match_scratch:SI 5 "=X,1,l"))
1493 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1494 "GENERATE_MADD_MSUB"
1499 [(set_attr "type" "imadd")
1500 (set_attr "mode" "SI")
1501 (set_attr "length" "4,8,8")])
1503 ;; Split the above insn if we failed to get LO allocated.
1505 [(set (match_operand:SI 0 "register_operand")
1506 (minus:SI (match_operand:SI 1 "register_operand")
1507 (mult:SI (match_operand:SI 2 "register_operand")
1508 (match_operand:SI 3 "register_operand"))))
1509 (clobber (match_scratch:SI 4))
1510 (clobber (match_scratch:SI 5))
1511 (clobber (match_scratch:SI 6))]
1512 "reload_completed && !TARGET_DEBUG_D_MODE
1513 && GP_REG_P (true_regnum (operands[0]))
1514 && GP_REG_P (true_regnum (operands[1]))"
1515 [(parallel [(set (match_dup 6)
1516 (mult:SI (match_dup 2) (match_dup 3)))
1517 (clobber (match_dup 4))
1518 (clobber (match_dup 5))])
1519 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 6)))]
1522 ;; Splitter to copy result of MSUB to a general register
1524 [(set (match_operand:SI 0 "register_operand")
1525 (minus:SI (match_operand:SI 1 "register_operand")
1526 (mult:SI (match_operand:SI 2 "register_operand")
1527 (match_operand:SI 3 "register_operand"))))
1528 (clobber (match_scratch:SI 4))
1529 (clobber (match_scratch:SI 5))
1530 (clobber (match_scratch:SI 6))]
1531 "reload_completed && !TARGET_DEBUG_D_MODE
1532 && GP_REG_P (true_regnum (operands[0]))
1533 && true_regnum (operands[1]) == LO_REGNUM"
1534 [(parallel [(set (match_dup 1)
1535 (minus:SI (match_dup 1)
1536 (mult:SI (match_dup 2) (match_dup 3))))
1537 (clobber (match_dup 4))
1538 (clobber (match_dup 5))
1539 (clobber (match_dup 6))])
1540 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1543 (define_insn "*muls"
1544 [(set (match_operand:SI 0 "register_operand" "=l,d")
1545 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1546 (match_operand:SI 2 "register_operand" "d,d"))))
1547 (clobber (match_scratch:SI 3 "=h,h"))
1548 (clobber (match_scratch:SI 4 "=X,l"))]
1553 [(set_attr "type" "imul,imul3")
1554 (set_attr "mode" "SI")])
1556 ;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
1558 (define_expand "<u>mulsidi3"
1560 [(set (match_operand:DI 0 "register_operand")
1561 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1562 (any_extend:DI (match_operand:SI 2 "register_operand"))))
1563 (clobber (scratch:DI))
1564 (clobber (scratch:DI))
1565 (clobber (scratch:DI))])]
1566 "!TARGET_64BIT || !TARGET_FIX_R4000"
1570 if (!TARGET_FIX_R4000)
1571 emit_insn (gen_<u>mulsidi3_32bit_internal (operands[0], operands[1],
1574 emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1],
1580 (define_insn "<u>mulsidi3_32bit_internal"
1581 [(set (match_operand:DI 0 "register_operand" "=x")
1582 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1583 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1584 "!TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DSPR2"
1586 [(set_attr "type" "imul")
1587 (set_attr "mode" "SI")])
1589 (define_insn "<u>mulsidi3_32bit_r4000"
1590 [(set (match_operand:DI 0 "register_operand" "=d")
1591 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1592 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1593 (clobber (match_scratch:DI 3 "=x"))]
1594 "!TARGET_64BIT && TARGET_FIX_R4000"
1595 "mult<u>\t%1,%2\;mflo\t%L0;mfhi\t%M0"
1596 [(set_attr "type" "imul")
1597 (set_attr "mode" "SI")
1598 (set_attr "length" "12")])
1600 (define_insn_and_split "*<u>mulsidi3_64bit"
1601 [(set (match_operand:DI 0 "register_operand" "=d")
1602 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1603 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1604 (clobber (match_scratch:DI 3 "=l"))
1605 (clobber (match_scratch:DI 4 "=h"))
1606 (clobber (match_scratch:DI 5 "=d"))]
1607 "TARGET_64BIT && !TARGET_FIX_R4000"
1609 "&& reload_completed"
1613 (mult:SI (match_dup 1)
1617 (mult:DI (any_extend:DI (match_dup 1))
1618 (any_extend:DI (match_dup 2)))
1621 ;; OP5 <- LO, OP0 <- HI
1622 (set (match_dup 5) (unspec:DI [(match_dup 3) (match_dup 4)] UNSPEC_MFHILO))
1623 (set (match_dup 0) (unspec:DI [(match_dup 4) (match_dup 3)] UNSPEC_MFHILO))
1627 (ashift:DI (match_dup 5)
1630 (lshiftrt:DI (match_dup 5)
1633 ;; Shift OP0 into place.
1635 (ashift:DI (match_dup 0)
1638 ;; OR the two halves together
1640 (ior:DI (match_dup 0)
1643 [(set_attr "type" "imul")
1644 (set_attr "mode" "SI")
1645 (set_attr "length" "24")])
1647 (define_insn "*<u>mulsidi3_64bit_parts"
1648 [(set (match_operand:DI 0 "register_operand" "=l")
1650 (mult:SI (match_operand:SI 2 "register_operand" "d")
1651 (match_operand:SI 3 "register_operand" "d"))))
1652 (set (match_operand:DI 1 "register_operand" "=h")
1654 (mult:DI (any_extend:DI (match_dup 2))
1655 (any_extend:DI (match_dup 3)))
1657 "TARGET_64BIT && !TARGET_FIX_R4000"
1659 [(set_attr "type" "imul")
1660 (set_attr "mode" "SI")])
1662 ;; Widening multiply with negation.
1663 (define_insn "*muls<u>_di"
1664 [(set (match_operand:DI 0 "register_operand" "=x")
1667 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1668 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1669 "!TARGET_64BIT && ISA_HAS_MULS"
1671 [(set_attr "type" "imul")
1672 (set_attr "mode" "SI")])
1674 (define_insn "<u>msubsidi4"
1675 [(set (match_operand:DI 0 "register_operand" "=ka")
1677 (match_operand:DI 3 "register_operand" "0")
1679 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1680 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1681 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)"
1684 return "msub<u>\t%q0,%1,%2";
1685 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
1686 return "msub<u>\t%1,%2";
1688 return "msac<u>\t$0,%1,%2";
1690 [(set_attr "type" "imadd")
1691 (set_attr "mode" "SI")])
1693 ;; _highpart patterns
1695 (define_expand "<su>mulsi3_highpart"
1696 [(set (match_operand:SI 0 "register_operand")
1699 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1700 (any_extend:DI (match_operand:SI 2 "register_operand")))
1702 "ISA_HAS_MULHI || !TARGET_FIX_R4000"
1705 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
1709 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
1714 (define_insn "<su>mulsi3_highpart_internal"
1715 [(set (match_operand:SI 0 "register_operand" "=h")
1718 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1719 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1721 (clobber (match_scratch:SI 3 "=l"))]
1722 "!ISA_HAS_MULHI && !TARGET_FIX_R4000"
1724 [(set_attr "type" "imul")
1725 (set_attr "mode" "SI")])
1727 (define_insn "<su>mulsi3_highpart_mulhi_internal"
1728 [(set (match_operand:SI 0 "register_operand" "=h,d")
1732 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1733 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d")))
1735 (clobber (match_scratch:SI 3 "=l,l"))
1736 (clobber (match_scratch:SI 4 "=X,h"))]
1741 [(set_attr "type" "imul,imul3")
1742 (set_attr "mode" "SI")])
1744 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
1745 [(set (match_operand:SI 0 "register_operand" "=h,d")
1750 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1751 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d"))))
1753 (clobber (match_scratch:SI 3 "=l,l"))
1754 (clobber (match_scratch:SI 4 "=X,h"))]
1758 mulshi<u>\t%0,%1,%2"
1759 [(set_attr "type" "imul,imul3")
1760 (set_attr "mode" "SI")])
1762 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
1763 ;; errata MD(0), which says that dmultu does not always produce the
1765 (define_insn "<su>muldi3_highpart"
1766 [(set (match_operand:DI 0 "register_operand" "=h")
1770 (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
1771 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
1773 (clobber (match_scratch:DI 3 "=l"))]
1774 "TARGET_64BIT && !TARGET_FIX_R4000
1775 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1777 [(set_attr "type" "imul")
1778 (set_attr "mode" "DI")])
1780 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
1781 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
1783 (define_insn "madsi"
1784 [(set (match_operand:SI 0 "register_operand" "+l")
1785 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1786 (match_operand:SI 2 "register_operand" "d"))
1788 (clobber (match_scratch:SI 3 "=h"))]
1791 [(set_attr "type" "imadd")
1792 (set_attr "mode" "SI")])
1794 (define_insn "<u>maddsidi4"
1795 [(set (match_operand:DI 0 "register_operand" "=ka")
1797 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1798 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1799 (match_operand:DI 3 "register_operand" "0")))]
1800 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)
1804 return "mad<u>\t%1,%2";
1805 else if (ISA_HAS_DSPR2)
1806 return "madd<u>\t%q0,%1,%2";
1807 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
1808 return "madd<u>\t%1,%2";
1810 /* See comment in *macc. */
1811 return "%[macc<u>\t%@,%1,%2%]";
1813 [(set_attr "type" "imadd")
1814 (set_attr "mode" "SI")])
1816 ;; Floating point multiply accumulate instructions.
1818 (define_insn "*madd<mode>"
1819 [(set (match_operand:ANYF 0 "register_operand" "=f")
1820 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1821 (match_operand:ANYF 2 "register_operand" "f"))
1822 (match_operand:ANYF 3 "register_operand" "f")))]
1823 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1824 "madd.<fmt>\t%0,%3,%1,%2"
1825 [(set_attr "type" "fmadd")
1826 (set_attr "mode" "<UNITMODE>")])
1828 (define_insn "*msub<mode>"
1829 [(set (match_operand:ANYF 0 "register_operand" "=f")
1830 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1831 (match_operand:ANYF 2 "register_operand" "f"))
1832 (match_operand:ANYF 3 "register_operand" "f")))]
1833 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1834 "msub.<fmt>\t%0,%3,%1,%2"
1835 [(set_attr "type" "fmadd")
1836 (set_attr "mode" "<UNITMODE>")])
1838 (define_insn "*nmadd<mode>"
1839 [(set (match_operand:ANYF 0 "register_operand" "=f")
1840 (neg:ANYF (plus:ANYF
1841 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1842 (match_operand:ANYF 2 "register_operand" "f"))
1843 (match_operand:ANYF 3 "register_operand" "f"))))]
1844 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1845 && HONOR_SIGNED_ZEROS (<MODE>mode)
1846 && !HONOR_NANS (<MODE>mode)"
1847 "nmadd.<fmt>\t%0,%3,%1,%2"
1848 [(set_attr "type" "fmadd")
1849 (set_attr "mode" "<UNITMODE>")])
1851 (define_insn "*nmadd<mode>_fastmath"
1852 [(set (match_operand:ANYF 0 "register_operand" "=f")
1854 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
1855 (match_operand:ANYF 2 "register_operand" "f"))
1856 (match_operand:ANYF 3 "register_operand" "f")))]
1857 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1858 && !HONOR_SIGNED_ZEROS (<MODE>mode)
1859 && !HONOR_NANS (<MODE>mode)"
1860 "nmadd.<fmt>\t%0,%3,%1,%2"
1861 [(set_attr "type" "fmadd")
1862 (set_attr "mode" "<UNITMODE>")])
1864 (define_insn "*nmsub<mode>"
1865 [(set (match_operand:ANYF 0 "register_operand" "=f")
1866 (neg:ANYF (minus:ANYF
1867 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1868 (match_operand:ANYF 3 "register_operand" "f"))
1869 (match_operand:ANYF 1 "register_operand" "f"))))]
1870 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1871 && HONOR_SIGNED_ZEROS (<MODE>mode)
1872 && !HONOR_NANS (<MODE>mode)"
1873 "nmsub.<fmt>\t%0,%1,%2,%3"
1874 [(set_attr "type" "fmadd")
1875 (set_attr "mode" "<UNITMODE>")])
1877 (define_insn "*nmsub<mode>_fastmath"
1878 [(set (match_operand:ANYF 0 "register_operand" "=f")
1880 (match_operand:ANYF 1 "register_operand" "f")
1881 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1882 (match_operand:ANYF 3 "register_operand" "f"))))]
1883 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1884 && !HONOR_SIGNED_ZEROS (<MODE>mode)
1885 && !HONOR_NANS (<MODE>mode)"
1886 "nmsub.<fmt>\t%0,%1,%2,%3"
1887 [(set_attr "type" "fmadd")
1888 (set_attr "mode" "<UNITMODE>")])
1891 ;; ....................
1893 ;; DIVISION and REMAINDER
1895 ;; ....................
1898 (define_expand "div<mode>3"
1899 [(set (match_operand:ANYF 0 "register_operand")
1900 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
1901 (match_operand:ANYF 2 "register_operand")))]
1902 "<divide_condition>"
1904 if (const_1_operand (operands[1], <MODE>mode))
1905 if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
1906 operands[1] = force_reg (<MODE>mode, operands[1]);
1909 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
1911 ;; If an mfc1 or dmfc1 happens to access the floating point register
1912 ;; file at the same time a long latency operation (div, sqrt, recip,
1913 ;; sqrt) iterates an intermediate result back through the floating
1914 ;; point register file bypass, then instead returning the correct
1915 ;; register value the mfc1 or dmfc1 operation returns the intermediate
1916 ;; result of the long latency operation.
1918 ;; The workaround is to insert an unconditional 'mov' from/to the
1919 ;; long latency op destination register.
1921 (define_insn "*div<mode>3"
1922 [(set (match_operand:ANYF 0 "register_operand" "=f")
1923 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
1924 (match_operand:ANYF 2 "register_operand" "f")))]
1925 "<divide_condition>"
1928 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
1930 return "div.<fmt>\t%0,%1,%2";
1932 [(set_attr "type" "fdiv")
1933 (set_attr "mode" "<UNITMODE>")
1934 (set (attr "length")
1935 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1939 (define_insn "*recip<mode>3"
1940 [(set (match_operand:ANYF 0 "register_operand" "=f")
1941 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1942 (match_operand:ANYF 2 "register_operand" "f")))]
1943 "<recip_condition> && flag_unsafe_math_optimizations"
1946 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
1948 return "recip.<fmt>\t%0,%2";
1950 [(set_attr "type" "frdiv")
1951 (set_attr "mode" "<UNITMODE>")
1952 (set (attr "length")
1953 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1957 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
1958 ;; with negative operands. We use special libgcc functions instead.
1959 (define_insn "divmod<mode>4"
1960 [(set (match_operand:GPR 0 "register_operand" "=l")
1961 (div:GPR (match_operand:GPR 1 "register_operand" "d")
1962 (match_operand:GPR 2 "register_operand" "d")))
1963 (set (match_operand:GPR 3 "register_operand" "=h")
1964 (mod:GPR (match_dup 1)
1966 "!TARGET_FIX_VR4120"
1967 { return mips_output_division ("<d>div\t$0,%1,%2", operands); }
1968 [(set_attr "type" "idiv")
1969 (set_attr "mode" "<MODE>")])
1971 (define_insn "udivmod<mode>4"
1972 [(set (match_operand:GPR 0 "register_operand" "=l")
1973 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
1974 (match_operand:GPR 2 "register_operand" "d")))
1975 (set (match_operand:GPR 3 "register_operand" "=h")
1976 (umod:GPR (match_dup 1)
1979 { return mips_output_division ("<d>divu\t$0,%1,%2", operands); }
1980 [(set_attr "type" "idiv")
1981 (set_attr "mode" "<MODE>")])
1984 ;; ....................
1988 ;; ....................
1990 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
1991 ;; "*div[sd]f3" comment for details).
1993 (define_insn "sqrt<mode>2"
1994 [(set (match_operand:ANYF 0 "register_operand" "=f")
1995 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
1999 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
2001 return "sqrt.<fmt>\t%0,%1";
2003 [(set_attr "type" "fsqrt")
2004 (set_attr "mode" "<UNITMODE>")
2005 (set (attr "length")
2006 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2010 (define_insn "*rsqrt<mode>a"
2011 [(set (match_operand:ANYF 0 "register_operand" "=f")
2012 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2013 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
2014 "<recip_condition> && flag_unsafe_math_optimizations"
2017 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2019 return "rsqrt.<fmt>\t%0,%2";
2021 [(set_attr "type" "frsqrt")
2022 (set_attr "mode" "<UNITMODE>")
2023 (set (attr "length")
2024 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2028 (define_insn "*rsqrt<mode>b"
2029 [(set (match_operand:ANYF 0 "register_operand" "=f")
2030 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2031 (match_operand:ANYF 2 "register_operand" "f"))))]
2032 "<recip_condition> && flag_unsafe_math_optimizations"
2035 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2037 return "rsqrt.<fmt>\t%0,%2";
2039 [(set_attr "type" "frsqrt")
2040 (set_attr "mode" "<UNITMODE>")
2041 (set (attr "length")
2042 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2047 ;; ....................
2051 ;; ....................
2053 ;; Do not use the integer abs macro instruction, since that signals an
2054 ;; exception on -2147483648 (sigh).
2056 ;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
2057 ;; invalid; it does not clear their sign bits. We therefore can't use
2058 ;; abs.fmt if the signs of NaNs matter.
2060 (define_insn "abs<mode>2"
2061 [(set (match_operand:ANYF 0 "register_operand" "=f")
2062 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2063 "!HONOR_NANS (<MODE>mode)"
2065 [(set_attr "type" "fabs")
2066 (set_attr "mode" "<UNITMODE>")])
2069 ;; ...................
2071 ;; Count leading zeroes.
2073 ;; ...................
2076 (define_insn "clz<mode>2"
2077 [(set (match_operand:GPR 0 "register_operand" "=d")
2078 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
2081 [(set_attr "type" "clz")
2082 (set_attr "mode" "<MODE>")])
2085 ;; ....................
2087 ;; NEGATION and ONE'S COMPLEMENT
2089 ;; ....................
2091 (define_insn "negsi2"
2092 [(set (match_operand:SI 0 "register_operand" "=d")
2093 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2097 return "neg\t%0,%1";
2099 return "subu\t%0,%.,%1";
2101 [(set_attr "type" "arith")
2102 (set_attr "mode" "SI")])
2104 (define_insn "negdi2"
2105 [(set (match_operand:DI 0 "register_operand" "=d")
2106 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2107 "TARGET_64BIT && !TARGET_MIPS16"
2109 [(set_attr "type" "arith")
2110 (set_attr "mode" "DI")])
2112 ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
2113 ;; invalid; it does not flip their sign bit. We therefore can't use
2114 ;; neg.fmt if the signs of NaNs matter.
2116 (define_insn "neg<mode>2"
2117 [(set (match_operand:ANYF 0 "register_operand" "=f")
2118 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2119 "!HONOR_NANS (<MODE>mode)"
2121 [(set_attr "type" "fneg")
2122 (set_attr "mode" "<UNITMODE>")])
2124 (define_insn "one_cmpl<mode>2"
2125 [(set (match_operand:GPR 0 "register_operand" "=d")
2126 (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
2130 return "not\t%0,%1";
2132 return "nor\t%0,%.,%1";
2134 [(set_attr "type" "logical")
2135 (set_attr "mode" "<MODE>")])
2138 ;; ....................
2142 ;; ....................
2145 ;; Many of these instructions use trivial define_expands, because we
2146 ;; want to use a different set of constraints when TARGET_MIPS16.
2148 (define_expand "and<mode>3"
2149 [(set (match_operand:GPR 0 "register_operand")
2150 (and:GPR (match_operand:GPR 1 "register_operand")
2151 (match_operand:GPR 2 "uns_arith_operand")))]
2155 operands[2] = force_reg (<MODE>mode, operands[2]);
2158 (define_insn "*and<mode>3"
2159 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2160 (and:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2161 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2166 [(set_attr "type" "logical")
2167 (set_attr "mode" "<MODE>")])
2169 (define_insn "*and<mode>3_mips16"
2170 [(set (match_operand:GPR 0 "register_operand" "=d")
2171 (and:GPR (match_operand:GPR 1 "register_operand" "%0")
2172 (match_operand:GPR 2 "register_operand" "d")))]
2175 [(set_attr "type" "logical")
2176 (set_attr "mode" "<MODE>")])
2178 (define_expand "ior<mode>3"
2179 [(set (match_operand:GPR 0 "register_operand")
2180 (ior:GPR (match_operand:GPR 1 "register_operand")
2181 (match_operand:GPR 2 "uns_arith_operand")))]
2185 operands[2] = force_reg (<MODE>mode, operands[2]);
2188 (define_insn "*ior<mode>3"
2189 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2190 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2191 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2196 [(set_attr "type" "logical")
2197 (set_attr "mode" "<MODE>")])
2199 (define_insn "*ior<mode>3_mips16"
2200 [(set (match_operand:GPR 0 "register_operand" "=d")
2201 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2202 (match_operand:GPR 2 "register_operand" "d")))]
2205 [(set_attr "type" "logical")
2206 (set_attr "mode" "<MODE>")])
2208 (define_expand "xor<mode>3"
2209 [(set (match_operand:GPR 0 "register_operand")
2210 (xor:GPR (match_operand:GPR 1 "register_operand")
2211 (match_operand:GPR 2 "uns_arith_operand")))]
2216 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2217 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2218 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2223 [(set_attr "type" "logical")
2224 (set_attr "mode" "<MODE>")])
2227 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2228 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2229 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
2235 [(set_attr "type" "logical,arith,arith")
2236 (set_attr "mode" "<MODE>")
2237 (set_attr_alternative "length"
2239 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2244 (define_insn "*nor<mode>3"
2245 [(set (match_operand:GPR 0 "register_operand" "=d")
2246 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2247 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2250 [(set_attr "type" "logical")
2251 (set_attr "mode" "<MODE>")])
2254 ;; ....................
2258 ;; ....................
2262 (define_insn "truncdfsf2"
2263 [(set (match_operand:SF 0 "register_operand" "=f")
2264 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2265 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2267 [(set_attr "type" "fcvt")
2268 (set_attr "cnv_mode" "D2S")
2269 (set_attr "mode" "SF")])
2271 ;; Integer truncation patterns. Truncating SImode values to smaller
2272 ;; modes is a no-op, as it is for most other GCC ports. Truncating
2273 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
2274 ;; need to make sure that the lower 32 bits are properly sign-extended
2275 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
2276 ;; smaller than SImode is equivalent to two separate truncations:
2279 ;; DI ---> HI == DI ---> SI ---> HI
2280 ;; DI ---> QI == DI ---> SI ---> QI
2282 ;; Step A needs a real instruction but step B does not.
2284 (define_insn "truncdisi2"
2285 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
2286 (truncate:SI (match_operand:DI 1 "register_operand" "d,d")))]
2291 [(set_attr "type" "shift,store")
2292 (set_attr "mode" "SI")
2293 (set_attr "extended_mips16" "yes,*")])
2295 (define_insn "truncdihi2"
2296 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m")
2297 (truncate:HI (match_operand:DI 1 "register_operand" "d,d")))]
2302 [(set_attr "type" "shift,store")
2303 (set_attr "mode" "SI")
2304 (set_attr "extended_mips16" "yes,*")])
2306 (define_insn "truncdiqi2"
2307 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m")
2308 (truncate:QI (match_operand:DI 1 "register_operand" "d,d")))]
2313 [(set_attr "type" "shift,store")
2314 (set_attr "mode" "SI")
2315 (set_attr "extended_mips16" "yes,*")])
2317 ;; Combiner patterns to optimize shift/truncate combinations.
2320 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2322 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2323 (match_operand:DI 2 "const_arith_operand" ""))))]
2324 "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) >= 32"
2326 [(set_attr "type" "shift")
2327 (set_attr "mode" "SI")])
2330 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2332 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2334 "TARGET_64BIT && !TARGET_MIPS16"
2336 [(set_attr "type" "shift")
2337 (set_attr "mode" "SI")])
2340 ;; Combiner patterns for truncate/sign_extend combinations. They use
2341 ;; the shift/truncate patterns above.
2343 (define_insn_and_split ""
2344 [(set (match_operand:SI 0 "register_operand" "=d")
2346 (truncate:HI (match_operand:DI 1 "register_operand" "d"))))]
2347 "TARGET_64BIT && !TARGET_MIPS16"
2349 "&& reload_completed"
2351 (ashift:DI (match_dup 1)
2354 (truncate:SI (ashiftrt:DI (match_dup 2)
2356 { operands[2] = gen_lowpart (DImode, operands[0]); })
2358 (define_insn_and_split ""
2359 [(set (match_operand:SI 0 "register_operand" "=d")
2361 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2362 "TARGET_64BIT && !TARGET_MIPS16"
2364 "&& reload_completed"
2366 (ashift:DI (match_dup 1)
2369 (truncate:SI (ashiftrt:DI (match_dup 2)
2371 { operands[2] = gen_lowpart (DImode, operands[0]); })
2374 ;; Combiner patterns to optimize truncate/zero_extend combinations.
2377 [(set (match_operand:SI 0 "register_operand" "=d")
2378 (zero_extend:SI (truncate:HI
2379 (match_operand:DI 1 "register_operand" "d"))))]
2380 "TARGET_64BIT && !TARGET_MIPS16"
2381 "andi\t%0,%1,0xffff"
2382 [(set_attr "type" "logical")
2383 (set_attr "mode" "SI")])
2386 [(set (match_operand:SI 0 "register_operand" "=d")
2387 (zero_extend:SI (truncate:QI
2388 (match_operand:DI 1 "register_operand" "d"))))]
2389 "TARGET_64BIT && !TARGET_MIPS16"
2391 [(set_attr "type" "logical")
2392 (set_attr "mode" "SI")])
2395 [(set (match_operand:HI 0 "register_operand" "=d")
2396 (zero_extend:HI (truncate:QI
2397 (match_operand:DI 1 "register_operand" "d"))))]
2398 "TARGET_64BIT && !TARGET_MIPS16"
2400 [(set_attr "type" "logical")
2401 (set_attr "mode" "HI")])
2404 ;; ....................
2408 ;; ....................
2412 (define_insn_and_split "zero_extendsidi2"
2413 [(set (match_operand:DI 0 "register_operand" "=d,d")
2414 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2419 "&& reload_completed && REG_P (operands[1])"
2421 (ashift:DI (match_dup 1) (const_int 32)))
2423 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2424 { operands[1] = gen_lowpart (DImode, operands[1]); }
2425 [(set_attr "type" "multi,load")
2426 (set_attr "mode" "DI")
2427 (set_attr "length" "8,*")])
2429 ;; Combine is not allowed to convert this insn into a zero_extendsidi2
2430 ;; because of TRULY_NOOP_TRUNCATION.
2432 (define_insn_and_split "*clear_upper32"
2433 [(set (match_operand:DI 0 "register_operand" "=d,d")
2434 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,W")
2435 (const_int 4294967295)))]
2438 if (which_alternative == 0)
2441 operands[1] = gen_lowpart (SImode, operands[1]);
2442 return "lwu\t%0,%1";
2444 "&& reload_completed && REG_P (operands[1])"
2446 (ashift:DI (match_dup 1) (const_int 32)))
2448 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2450 [(set_attr "type" "multi,load")
2451 (set_attr "mode" "DI")
2452 (set_attr "length" "8,*")])
2454 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
2455 [(set (match_operand:GPR 0 "register_operand")
2456 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2459 if (TARGET_MIPS16 && !GENERATE_MIPS16E
2460 && !memory_operand (operands[1], <SHORT:MODE>mode))
2462 emit_insn (gen_and<GPR:mode>3 (operands[0],
2463 gen_lowpart (<GPR:MODE>mode, operands[1]),
2464 force_reg (<GPR:MODE>mode,
2465 GEN_INT (<SHORT:mask>))));
2470 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
2471 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2473 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2476 andi\t%0,%1,<SHORT:mask>
2477 l<SHORT:size>u\t%0,%1"
2478 [(set_attr "type" "logical,load")
2479 (set_attr "mode" "<GPR:MODE>")])
2481 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
2482 [(set (match_operand:GPR 0 "register_operand" "=d")
2483 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
2485 "ze<SHORT:size>\t%0"
2486 [(set_attr "type" "arith")
2487 (set_attr "mode" "<GPR:MODE>")])
2489 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
2490 [(set (match_operand:GPR 0 "register_operand" "=d")
2491 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
2493 "l<SHORT:size>u\t%0,%1"
2494 [(set_attr "type" "load")
2495 (set_attr "mode" "<GPR:MODE>")])
2497 (define_expand "zero_extendqihi2"
2498 [(set (match_operand:HI 0 "register_operand")
2499 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2502 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
2504 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
2510 (define_insn "*zero_extendqihi2"
2511 [(set (match_operand:HI 0 "register_operand" "=d,d")
2512 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2517 [(set_attr "type" "logical,load")
2518 (set_attr "mode" "HI")])
2520 (define_insn "*zero_extendqihi2_mips16"
2521 [(set (match_operand:HI 0 "register_operand" "=d")
2522 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2525 [(set_attr "type" "load")
2526 (set_attr "mode" "HI")])
2529 ;; ....................
2533 ;; ....................
2536 ;; Those for integer source operand are ordered widest source type first.
2538 ;; When TARGET_64BIT, all SImode integer registers should already be in
2539 ;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can
2540 ;; therefore get rid of register->register instructions if we constrain
2541 ;; the source to be in the same register as the destination.
2543 ;; The register alternative has type "arith" so that the pre-reload
2544 ;; scheduler will treat it as a move. This reflects what happens if
2545 ;; the register alternative needs a reload.
2546 (define_insn_and_split "extendsidi2"
2547 [(set (match_operand:DI 0 "register_operand" "=d,d")
2548 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
2553 "&& reload_completed && register_operand (operands[1], VOIDmode)"
2556 emit_note (NOTE_INSN_DELETED);
2559 [(set_attr "type" "arith,load")
2560 (set_attr "mode" "DI")])
2562 (define_expand "extend<SHORT:mode><GPR:mode>2"
2563 [(set (match_operand:GPR 0 "register_operand")
2564 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2567 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
2568 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2569 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
2573 l<SHORT:size>\t%0,%1"
2574 [(set_attr "type" "signext,load")
2575 (set_attr "mode" "<GPR:MODE>")])
2577 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
2578 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2580 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2581 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
2584 l<SHORT:size>\t%0,%1"
2585 "&& reload_completed && REG_P (operands[1])"
2586 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
2587 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
2589 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
2590 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
2591 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
2593 [(set_attr "type" "arith,load")
2594 (set_attr "mode" "<GPR:MODE>")
2595 (set_attr "length" "8,*")])
2597 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
2598 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2600 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2603 se<SHORT:size>\t%0,%1
2604 l<SHORT:size>\t%0,%1"
2605 [(set_attr "type" "signext,load")
2606 (set_attr "mode" "<GPR:MODE>")])
2608 (define_expand "extendqihi2"
2609 [(set (match_operand:HI 0 "register_operand")
2610 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2613 (define_insn "*extendqihi2_mips16e"
2614 [(set (match_operand:HI 0 "register_operand" "=d,d")
2615 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
2620 [(set_attr "type" "signext,load")
2621 (set_attr "mode" "SI")])
2623 (define_insn_and_split "*extendqihi2"
2624 [(set (match_operand:HI 0 "register_operand" "=d,d")
2626 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2627 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
2631 "&& reload_completed && REG_P (operands[1])"
2632 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
2633 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
2635 operands[0] = gen_lowpart (SImode, operands[0]);
2636 operands[1] = gen_lowpart (SImode, operands[1]);
2637 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
2638 - GET_MODE_BITSIZE (QImode));
2640 [(set_attr "type" "multi,load")
2641 (set_attr "mode" "SI")
2642 (set_attr "length" "8,*")])
2644 (define_insn "*extendqihi2_seb"
2645 [(set (match_operand:HI 0 "register_operand" "=d,d")
2647 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2652 [(set_attr "type" "signext,load")
2653 (set_attr "mode" "SI")])
2655 (define_insn "extendsfdf2"
2656 [(set (match_operand:DF 0 "register_operand" "=f")
2657 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2658 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2660 [(set_attr "type" "fcvt")
2661 (set_attr "cnv_mode" "S2D")
2662 (set_attr "mode" "DF")])
2665 ;; ....................
2669 ;; ....................
2671 (define_expand "fix_truncdfsi2"
2672 [(set (match_operand:SI 0 "register_operand")
2673 (fix:SI (match_operand:DF 1 "register_operand")))]
2674 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2676 if (!ISA_HAS_TRUNC_W)
2678 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
2683 (define_insn "fix_truncdfsi2_insn"
2684 [(set (match_operand:SI 0 "register_operand" "=f")
2685 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
2686 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
2688 [(set_attr "type" "fcvt")
2689 (set_attr "mode" "DF")
2690 (set_attr "cnv_mode" "D2I")
2691 (set_attr "length" "4")])
2693 (define_insn "fix_truncdfsi2_macro"
2694 [(set (match_operand:SI 0 "register_operand" "=f")
2695 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2696 (clobber (match_scratch:DF 2 "=d"))]
2697 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
2700 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
2702 return "trunc.w.d %0,%1,%2";
2704 [(set_attr "type" "fcvt")
2705 (set_attr "mode" "DF")
2706 (set_attr "cnv_mode" "D2I")
2707 (set_attr "length" "36")])
2709 (define_expand "fix_truncsfsi2"
2710 [(set (match_operand:SI 0 "register_operand")
2711 (fix:SI (match_operand:SF 1 "register_operand")))]
2714 if (!ISA_HAS_TRUNC_W)
2716 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
2721 (define_insn "fix_truncsfsi2_insn"
2722 [(set (match_operand:SI 0 "register_operand" "=f")
2723 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
2724 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
2726 [(set_attr "type" "fcvt")
2727 (set_attr "mode" "SF")
2728 (set_attr "cnv_mode" "S2I")
2729 (set_attr "length" "4")])
2731 (define_insn "fix_truncsfsi2_macro"
2732 [(set (match_operand:SI 0 "register_operand" "=f")
2733 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2734 (clobber (match_scratch:SF 2 "=d"))]
2735 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
2738 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
2740 return "trunc.w.s %0,%1,%2";
2742 [(set_attr "type" "fcvt")
2743 (set_attr "mode" "SF")
2744 (set_attr "cnv_mode" "S2I")
2745 (set_attr "length" "36")])
2748 (define_insn "fix_truncdfdi2"
2749 [(set (match_operand:DI 0 "register_operand" "=f")
2750 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
2751 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2753 [(set_attr "type" "fcvt")
2754 (set_attr "mode" "DF")
2755 (set_attr "cnv_mode" "D2I")
2756 (set_attr "length" "4")])
2759 (define_insn "fix_truncsfdi2"
2760 [(set (match_operand:DI 0 "register_operand" "=f")
2761 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
2762 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2764 [(set_attr "type" "fcvt")
2765 (set_attr "mode" "SF")
2766 (set_attr "cnv_mode" "S2I")
2767 (set_attr "length" "4")])
2770 (define_insn "floatsidf2"
2771 [(set (match_operand:DF 0 "register_operand" "=f")
2772 (float:DF (match_operand:SI 1 "register_operand" "f")))]
2773 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2775 [(set_attr "type" "fcvt")
2776 (set_attr "mode" "DF")
2777 (set_attr "cnv_mode" "I2D")
2778 (set_attr "length" "4")])
2781 (define_insn "floatdidf2"
2782 [(set (match_operand:DF 0 "register_operand" "=f")
2783 (float:DF (match_operand:DI 1 "register_operand" "f")))]
2784 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2786 [(set_attr "type" "fcvt")
2787 (set_attr "mode" "DF")
2788 (set_attr "cnv_mode" "I2D")
2789 (set_attr "length" "4")])
2792 (define_insn "floatsisf2"
2793 [(set (match_operand:SF 0 "register_operand" "=f")
2794 (float:SF (match_operand:SI 1 "register_operand" "f")))]
2797 [(set_attr "type" "fcvt")
2798 (set_attr "mode" "SF")
2799 (set_attr "cnv_mode" "I2S")
2800 (set_attr "length" "4")])
2803 (define_insn "floatdisf2"
2804 [(set (match_operand:SF 0 "register_operand" "=f")
2805 (float:SF (match_operand:DI 1 "register_operand" "f")))]
2806 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2808 [(set_attr "type" "fcvt")
2809 (set_attr "mode" "SF")
2810 (set_attr "cnv_mode" "I2S")
2811 (set_attr "length" "4")])
2814 (define_expand "fixuns_truncdfsi2"
2815 [(set (match_operand:SI 0 "register_operand")
2816 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
2817 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2819 rtx reg1 = gen_reg_rtx (DFmode);
2820 rtx reg2 = gen_reg_rtx (DFmode);
2821 rtx reg3 = gen_reg_rtx (SImode);
2822 rtx label1 = gen_label_rtx ();
2823 rtx label2 = gen_label_rtx ();
2824 REAL_VALUE_TYPE offset;
2826 real_2expN (&offset, 31, DFmode);
2828 if (reg1) /* Turn off complaints about unreached code. */
2830 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2831 do_pending_stack_adjust ();
2833 emit_insn (gen_cmpdf (operands[1], reg1));
2834 emit_jump_insn (gen_bge (label1));
2836 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
2837 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2838 gen_rtx_LABEL_REF (VOIDmode, label2)));
2841 emit_label (label1);
2842 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2843 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
2844 (BITMASK_HIGH, SImode)));
2846 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
2847 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2849 emit_label (label2);
2851 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2852 fields, and can't be used for REG_NOTES anyway). */
2853 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2859 (define_expand "fixuns_truncdfdi2"
2860 [(set (match_operand:DI 0 "register_operand")
2861 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
2862 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2864 rtx reg1 = gen_reg_rtx (DFmode);
2865 rtx reg2 = gen_reg_rtx (DFmode);
2866 rtx reg3 = gen_reg_rtx (DImode);
2867 rtx label1 = gen_label_rtx ();
2868 rtx label2 = gen_label_rtx ();
2869 REAL_VALUE_TYPE offset;
2871 real_2expN (&offset, 63, DFmode);
2873 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2874 do_pending_stack_adjust ();
2876 emit_insn (gen_cmpdf (operands[1], reg1));
2877 emit_jump_insn (gen_bge (label1));
2879 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
2880 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2881 gen_rtx_LABEL_REF (VOIDmode, label2)));
2884 emit_label (label1);
2885 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2886 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
2887 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2889 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
2890 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2892 emit_label (label2);
2894 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2895 fields, and can't be used for REG_NOTES anyway). */
2896 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2901 (define_expand "fixuns_truncsfsi2"
2902 [(set (match_operand:SI 0 "register_operand")
2903 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
2906 rtx reg1 = gen_reg_rtx (SFmode);
2907 rtx reg2 = gen_reg_rtx (SFmode);
2908 rtx reg3 = gen_reg_rtx (SImode);
2909 rtx label1 = gen_label_rtx ();
2910 rtx label2 = gen_label_rtx ();
2911 REAL_VALUE_TYPE offset;
2913 real_2expN (&offset, 31, SFmode);
2915 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2916 do_pending_stack_adjust ();
2918 emit_insn (gen_cmpsf (operands[1], reg1));
2919 emit_jump_insn (gen_bge (label1));
2921 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
2922 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2923 gen_rtx_LABEL_REF (VOIDmode, label2)));
2926 emit_label (label1);
2927 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
2928 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
2929 (BITMASK_HIGH, SImode)));
2931 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
2932 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2934 emit_label (label2);
2936 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2937 fields, and can't be used for REG_NOTES anyway). */
2938 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2943 (define_expand "fixuns_truncsfdi2"
2944 [(set (match_operand:DI 0 "register_operand")
2945 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
2946 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2948 rtx reg1 = gen_reg_rtx (SFmode);
2949 rtx reg2 = gen_reg_rtx (SFmode);
2950 rtx reg3 = gen_reg_rtx (DImode);
2951 rtx label1 = gen_label_rtx ();
2952 rtx label2 = gen_label_rtx ();
2953 REAL_VALUE_TYPE offset;
2955 real_2expN (&offset, 63, SFmode);
2957 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2958 do_pending_stack_adjust ();
2960 emit_insn (gen_cmpsf (operands[1], reg1));
2961 emit_jump_insn (gen_bge (label1));
2963 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
2964 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2965 gen_rtx_LABEL_REF (VOIDmode, label2)));
2968 emit_label (label1);
2969 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
2970 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
2971 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2973 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
2974 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2976 emit_label (label2);
2978 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2979 fields, and can't be used for REG_NOTES anyway). */
2980 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2985 ;; ....................
2989 ;; ....................
2991 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
2993 (define_expand "extv"
2994 [(set (match_operand 0 "register_operand")
2995 (sign_extract (match_operand:QI 1 "memory_operand")
2996 (match_operand 2 "immediate_operand")
2997 (match_operand 3 "immediate_operand")))]
3000 if (mips_expand_unaligned_load (operands[0], operands[1],
3001 INTVAL (operands[2]),
3002 INTVAL (operands[3])))
3008 (define_expand "extzv"
3009 [(set (match_operand 0 "register_operand")
3010 (zero_extract (match_operand 1 "nonimmediate_operand")
3011 (match_operand 2 "immediate_operand")
3012 (match_operand 3 "immediate_operand")))]
3015 if (mips_expand_unaligned_load (operands[0], operands[1],
3016 INTVAL (operands[2]),
3017 INTVAL (operands[3])))
3019 else if (mips_use_ins_ext_p (operands[1], operands[2], operands[3]))
3021 if (GET_MODE (operands[0]) == DImode)
3022 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
3025 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
3033 (define_insn "extzv<mode>"
3034 [(set (match_operand:GPR 0 "register_operand" "=d")
3035 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3036 (match_operand:SI 2 "immediate_operand" "I")
3037 (match_operand:SI 3 "immediate_operand" "I")))]
3038 "mips_use_ins_ext_p (operands[1], operands[2], operands[3])"
3039 "<d>ext\t%0,%1,%3,%2"
3040 [(set_attr "type" "arith")
3041 (set_attr "mode" "<MODE>")])
3044 (define_expand "insv"
3045 [(set (zero_extract (match_operand 0 "nonimmediate_operand")
3046 (match_operand 1 "immediate_operand")
3047 (match_operand 2 "immediate_operand"))
3048 (match_operand 3 "reg_or_0_operand"))]
3051 if (mips_expand_unaligned_store (operands[0], operands[3],
3052 INTVAL (operands[1]),
3053 INTVAL (operands[2])))
3055 else if (mips_use_ins_ext_p (operands[0], operands[1], operands[2]))
3057 if (GET_MODE (operands[0]) == DImode)
3058 emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
3061 emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
3069 (define_insn "insv<mode>"
3070 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
3071 (match_operand:SI 1 "immediate_operand" "I")
3072 (match_operand:SI 2 "immediate_operand" "I"))
3073 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
3074 "mips_use_ins_ext_p (operands[0], operands[1], operands[2])"
3075 "<d>ins\t%0,%z3,%2,%1"
3076 [(set_attr "type" "arith")
3077 (set_attr "mode" "<MODE>")])
3079 ;; Unaligned word moves generated by the bit field patterns.
3081 ;; As far as the rtl is concerned, both the left-part and right-part
3082 ;; instructions can access the whole field. However, the real operand
3083 ;; refers to just the first or the last byte (depending on endianness).
3084 ;; We therefore use two memory operands to each instruction, one to
3085 ;; describe the rtl effect and one to use in the assembly output.
3087 ;; Operands 0 and 1 are the rtl-level target and source respectively.
3088 ;; This allows us to use the standard length calculations for the "load"
3089 ;; and "store" type attributes.
3091 (define_insn "mov_<load>l"
3092 [(set (match_operand:GPR 0 "register_operand" "=d")
3093 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3094 (match_operand:QI 2 "memory_operand" "m")]
3096 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3098 [(set_attr "type" "load")
3099 (set_attr "mode" "<MODE>")])
3101 (define_insn "mov_<load>r"
3102 [(set (match_operand:GPR 0 "register_operand" "=d")
3103 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3104 (match_operand:QI 2 "memory_operand" "m")
3105 (match_operand:GPR 3 "register_operand" "0")]
3106 UNSPEC_LOAD_RIGHT))]
3107 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3109 [(set_attr "type" "load")
3110 (set_attr "mode" "<MODE>")])
3112 (define_insn "mov_<store>l"
3113 [(set (match_operand:BLK 0 "memory_operand" "=m")
3114 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3115 (match_operand:QI 2 "memory_operand" "m")]
3116 UNSPEC_STORE_LEFT))]
3117 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3119 [(set_attr "type" "store")
3120 (set_attr "mode" "<MODE>")])
3122 (define_insn "mov_<store>r"
3123 [(set (match_operand:BLK 0 "memory_operand" "+m")
3124 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3125 (match_operand:QI 2 "memory_operand" "m")
3127 UNSPEC_STORE_RIGHT))]
3128 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3130 [(set_attr "type" "store")
3131 (set_attr "mode" "<MODE>")])
3133 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
3134 ;; The required value is:
3136 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
3138 ;; which translates to:
3140 ;; lui op0,%highest(op1)
3141 ;; daddiu op0,op0,%higher(op1)
3143 ;; daddiu op0,op0,%hi(op1)
3146 ;; The split is deferred until after flow2 to allow the peephole2 below
3148 (define_insn_and_split "*lea_high64"
3149 [(set (match_operand:DI 0 "register_operand" "=d")
3150 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))]
3151 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3153 "&& epilogue_completed"
3154 [(set (match_dup 0) (high:DI (match_dup 2)))
3155 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
3156 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
3157 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3158 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
3160 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3161 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
3163 [(set_attr "length" "20")])
3165 ;; Use a scratch register to reduce the latency of the above pattern
3166 ;; on superscalar machines. The optimized sequence is:
3168 ;; lui op1,%highest(op2)
3170 ;; daddiu op1,op1,%higher(op2)
3172 ;; daddu op1,op1,op0
3174 [(set (match_operand:DI 1 "register_operand")
3175 (high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
3176 (match_scratch:DI 0 "d")]
3177 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3178 [(set (match_dup 1) (high:DI (match_dup 3)))
3179 (set (match_dup 0) (high:DI (match_dup 4)))
3180 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
3181 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
3182 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
3184 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
3185 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
3188 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
3189 ;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine
3190 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
3191 ;; used once. We can then use the sequence:
3193 ;; lui op0,%highest(op1)
3195 ;; daddiu op0,op0,%higher(op1)
3196 ;; daddiu op2,op2,%lo(op1)
3198 ;; daddu op0,op0,op2
3200 ;; which takes 4 cycles on most superscalar targets.
3201 (define_insn_and_split "*lea64"
3202 [(set (match_operand:DI 0 "register_operand" "=d")
3203 (match_operand:DI 1 "absolute_symbolic_operand" ""))
3204 (clobber (match_scratch:DI 2 "=&d"))]
3205 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
3207 "&& reload_completed"
3208 [(set (match_dup 0) (high:DI (match_dup 3)))
3209 (set (match_dup 2) (high:DI (match_dup 4)))
3210 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3211 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
3212 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
3213 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
3215 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3216 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
3218 [(set_attr "length" "24")])
3220 ;; Split HIGHs into:
3225 ;; on MIPS16 targets.
3227 [(set (match_operand:SI 0 "register_operand" "=d")
3228 (high:SI (match_operand:SI 1 "absolute_symbolic_operand" "")))]
3229 "TARGET_MIPS16 && reload_completed"
3230 [(set (match_dup 0) (match_dup 2))
3231 (set (match_dup 0) (ashift:SI (match_dup 0) (const_int 16)))]
3233 operands[2] = mips_unspec_address (operands[1], SYMBOL_32_HIGH);
3236 ;; Insns to fetch a symbol from a big GOT.
3238 (define_insn_and_split "*xgot_hi<mode>"
3239 [(set (match_operand:P 0 "register_operand" "=d")
3240 (high:P (match_operand:P 1 "got_disp_operand" "")))]
3241 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3243 "&& reload_completed"
3244 [(set (match_dup 0) (high:P (match_dup 2)))
3245 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
3247 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3248 operands[3] = pic_offset_table_rtx;
3250 [(set_attr "got" "xgot_high")
3251 (set_attr "mode" "<MODE>")])
3253 (define_insn_and_split "*xgot_lo<mode>"
3254 [(set (match_operand:P 0 "register_operand" "=d")
3255 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3256 (match_operand:P 2 "got_disp_operand" "")))]
3257 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3259 "&& reload_completed"
3261 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
3262 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
3263 [(set_attr "got" "load")
3264 (set_attr "mode" "<MODE>")])
3266 ;; Insns to fetch a symbol from a normal GOT.
3268 (define_insn_and_split "*got_disp<mode>"
3269 [(set (match_operand:P 0 "register_operand" "=d")
3270 (match_operand:P 1 "got_disp_operand" ""))]
3271 "TARGET_EXPLICIT_RELOCS && !TARGET_XGOT"
3273 "&& reload_completed"
3275 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3277 operands[2] = pic_offset_table_rtx;
3278 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3280 [(set_attr "got" "load")
3281 (set_attr "mode" "<MODE>")])
3283 ;; Insns for loading the "page" part of a page/ofst address from the GOT.
3285 (define_insn_and_split "*got_page<mode>"
3286 [(set (match_operand:P 0 "register_operand" "=d")
3287 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
3288 "TARGET_EXPLICIT_RELOCS"
3290 "&& reload_completed"
3292 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3294 operands[2] = pic_offset_table_rtx;
3295 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_PAGE);
3297 [(set_attr "got" "load")
3298 (set_attr "mode" "<MODE>")])
3300 ;; Lower-level instructions for loading an address from the GOT.
3301 ;; We could use MEMs, but an unspec gives more optimization
3304 (define_insn "load_got<mode>"
3305 [(set (match_operand:P 0 "register_operand" "=d")
3306 (unspec:P [(match_operand:P 1 "register_operand" "d")
3307 (match_operand:P 2 "immediate_operand" "")]
3310 "<load>\t%0,%R2(%1)"
3311 [(set_attr "type" "load")
3312 (set_attr "mode" "<MODE>")
3313 (set_attr "length" "4")])
3315 ;; Instructions for adding the low 16 bits of an address to a register.
3316 ;; Operand 2 is the address: print_operand works out which relocation
3317 ;; should be applied.
3319 (define_insn "*low<mode>"
3320 [(set (match_operand:P 0 "register_operand" "=d")
3321 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3322 (match_operand:P 2 "immediate_operand" "")))]
3324 "<d>addiu\t%0,%1,%R2"
3325 [(set_attr "type" "arith")
3326 (set_attr "mode" "<MODE>")])
3328 (define_insn "*low<mode>_mips16"
3329 [(set (match_operand:P 0 "register_operand" "=d")
3330 (lo_sum:P (match_operand:P 1 "register_operand" "0")
3331 (match_operand:P 2 "immediate_operand" "")))]
3334 [(set_attr "type" "arith")
3335 (set_attr "mode" "<MODE>")
3336 (set_attr "length" "8")])
3338 ;; Allow combine to split complex const_int load sequences, using operand 2
3339 ;; to store the intermediate results. See move_operand for details.
3341 [(set (match_operand:GPR 0 "register_operand")
3342 (match_operand:GPR 1 "splittable_const_int_operand"))
3343 (clobber (match_operand:GPR 2 "register_operand"))]
3347 mips_move_integer (operands[0], operands[2], INTVAL (operands[1]));
3351 ;; Likewise, for symbolic operands.
3353 [(set (match_operand:P 0 "register_operand")
3354 (match_operand:P 1))
3355 (clobber (match_operand:P 2 "register_operand"))]
3356 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
3357 [(set (match_dup 0) (match_dup 3))]
3359 mips_split_symbol (operands[2], operands[1],
3360 MAX_MACHINE_MODE, &operands[3]);
3363 ;; 64-bit integer moves
3365 ;; Unlike most other insns, the move insns can't be split with
3366 ;; different predicates, because register spilling and other parts of
3367 ;; the compiler, have memoized the insn number already.
3369 (define_expand "movdi"
3370 [(set (match_operand:DI 0 "")
3371 (match_operand:DI 1 ""))]
3374 if (mips_legitimize_move (DImode, operands[0], operands[1]))
3378 ;; For mips16, we need a special case to handle storing $31 into
3379 ;; memory, since we don't have a constraint to match $31. This
3380 ;; instruction can be generated by save_restore_insns.
3382 (define_insn "*mov<mode>_ra"
3383 [(set (match_operand:GPR 0 "stack_operand" "=m")
3387 [(set_attr "type" "store")
3388 (set_attr "mode" "<MODE>")])
3390 (define_insn "*movdi_32bit"
3391 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*B*C*D,*B*C*D,*d,*m")
3392 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
3393 "!TARGET_64BIT && !TARGET_FLOAT64 && !TARGET_MIPS16
3394 && (register_operand (operands[0], DImode)
3395 || reg_or_0_operand (operands[1], DImode))"
3396 { return mips_output_move (operands[0], operands[1]); }
3397 [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,mtc,load,mfc,store")
3398 (set_attr "mode" "DI")
3399 (set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
3401 (define_insn "*movdi_gp32_fp64"
3402 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*f,*d,*m")
3403 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*f,*J*d,*m,*f,*f"))]
3404 "!TARGET_64BIT && TARGET_FLOAT64 && !TARGET_MIPS16
3405 && (register_operand (operands[0], DImode)
3406 || reg_or_0_operand (operands[1], DImode))"
3407 { return mips_output_move (operands[0], operands[1]); }
3408 [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,fmove,mtc,fpload,mfc,fpstore")
3409 (set_attr "mode" "DI")
3410 (set_attr "length" "8,16,*,*,8,8,4,8,*,8,*")])
3412 (define_insn "*movdi_32bit_mips16"
3413 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
3414 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
3415 "!TARGET_64BIT && TARGET_MIPS16
3416 && (register_operand (operands[0], DImode)
3417 || register_operand (operands[1], DImode))"
3418 { return mips_output_move (operands[0], operands[1]); }
3419 [(set_attr "type" "multi,multi,multi,multi,multi,load,store,mfhilo")
3420 (set_attr "mode" "DI")
3421 (set_attr "length" "8,8,8,8,12,*,*,8")])
3423 (define_insn "*movdi_64bit"
3424 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*x,*B*C*D,*B*C*D,*d,*m")
3425 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*J*d,*d,*m,*B*C*D,*B*C*D"))]
3426 "TARGET_64BIT && !TARGET_MIPS16
3427 && (register_operand (operands[0], DImode)
3428 || reg_or_0_operand (operands[1], DImode))"
3429 { return mips_output_move (operands[0], operands[1]); }
3430 [(set_attr "type" "move,const,const,load,store,fmove,mtc,fpload,mfc,fpstore,mthilo,mtc,load,mfc,store")
3431 (set_attr "mode" "DI")
3432 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,8,*,8,*")])
3434 (define_insn "*movdi_64bit_mips16"
3435 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m")
3436 (match_operand:DI 1 "move_operand" "d,d,y,K,N,kf,U,m,d"))]
3437 "TARGET_64BIT && TARGET_MIPS16
3438 && (register_operand (operands[0], DImode)
3439 || register_operand (operands[1], DImode))"
3440 { return mips_output_move (operands[0], operands[1]); }
3441 [(set_attr "type" "move,move,move,arith,arith,load,const,load,store")
3442 (set_attr "mode" "DI")
3443 (set_attr_alternative "length"
3447 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3450 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3456 (const_string "*")])])
3459 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
3460 ;; when the original load is a 4 byte instruction but the add and the
3461 ;; load are 2 2 byte instructions.
3464 [(set (match_operand:DI 0 "register_operand")
3465 (mem:DI (plus:DI (match_dup 0)
3466 (match_operand:DI 1 "const_int_operand"))))]
3467 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
3468 && !TARGET_DEBUG_D_MODE
3469 && REG_P (operands[0])
3470 && M16_REG_P (REGNO (operands[0]))
3471 && GET_CODE (operands[1]) == CONST_INT
3472 && ((INTVAL (operands[1]) < 0
3473 && INTVAL (operands[1]) >= -0x10)
3474 || (INTVAL (operands[1]) >= 32 * 8
3475 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
3476 || (INTVAL (operands[1]) >= 0
3477 && INTVAL (operands[1]) < 32 * 8
3478 && (INTVAL (operands[1]) & 7) != 0))"
3479 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
3480 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
3482 HOST_WIDE_INT val = INTVAL (operands[1]);
3485 operands[2] = const0_rtx;
3486 else if (val >= 32 * 8)
3490 operands[1] = GEN_INT (0x8 + off);
3491 operands[2] = GEN_INT (val - off - 0x8);
3497 operands[1] = GEN_INT (off);
3498 operands[2] = GEN_INT (val - off);
3502 ;; 32-bit Integer moves
3504 ;; Unlike most other insns, the move insns can't be split with
3505 ;; different predicates, because register spilling and other parts of
3506 ;; the compiler, have memoized the insn number already.
3508 (define_expand "movsi"
3509 [(set (match_operand:SI 0 "")
3510 (match_operand:SI 1 ""))]
3513 if (mips_legitimize_move (SImode, operands[0], operands[1]))
3517 ;; The difference between these two is whether or not ints are allowed
3518 ;; in FP registers (off by default, use -mdebugh to enable).
3520 (define_insn "*movsi_internal"
3521 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
3522 (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*z,*d,*J*d,*A,*d,*m,*B*C*D,*B*C*D"))]
3524 && (register_operand (operands[0], SImode)
3525 || reg_or_0_operand (operands[1], SImode))"
3526 { return mips_output_move (operands[0], operands[1]); }
3527 [(set_attr "type" "move,const,const,load,store,fmove,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,load,mfc,store")
3528 (set_attr "mode" "SI")
3529 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,4,4,*,4,*")])
3531 (define_insn "*movsi_mips16"
3532 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m")
3533 (match_operand:SI 1 "move_operand" "d,d,y,K,N,kf,U,m,d"))]
3535 && (register_operand (operands[0], SImode)
3536 || register_operand (operands[1], SImode))"
3537 { return mips_output_move (operands[0], operands[1]); }
3538 [(set_attr "type" "move,move,move,arith,arith,load,const,load,store")
3539 (set_attr "mode" "SI")
3540 (set_attr_alternative "length"
3544 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3547 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3553 (const_string "*")])])
3555 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
3556 ;; when the original load is a 4 byte instruction but the add and the
3557 ;; load are 2 2 byte instructions.
3560 [(set (match_operand:SI 0 "register_operand")
3561 (mem:SI (plus:SI (match_dup 0)
3562 (match_operand:SI 1 "const_int_operand"))))]
3563 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3564 && REG_P (operands[0])
3565 && M16_REG_P (REGNO (operands[0]))
3566 && GET_CODE (operands[1]) == CONST_INT
3567 && ((INTVAL (operands[1]) < 0
3568 && INTVAL (operands[1]) >= -0x80)
3569 || (INTVAL (operands[1]) >= 32 * 4
3570 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
3571 || (INTVAL (operands[1]) >= 0
3572 && INTVAL (operands[1]) < 32 * 4
3573 && (INTVAL (operands[1]) & 3) != 0))"
3574 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3575 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
3577 HOST_WIDE_INT val = INTVAL (operands[1]);
3580 operands[2] = const0_rtx;
3581 else if (val >= 32 * 4)
3585 operands[1] = GEN_INT (0x7c + off);
3586 operands[2] = GEN_INT (val - off - 0x7c);
3592 operands[1] = GEN_INT (off);
3593 operands[2] = GEN_INT (val - off);
3597 ;; On the mips16, we can split a load of certain constants into a load
3598 ;; and an add. This turns a 4 byte instruction into 2 2 byte
3602 [(set (match_operand:SI 0 "register_operand")
3603 (match_operand:SI 1 "const_int_operand"))]
3604 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3605 && REG_P (operands[0])
3606 && M16_REG_P (REGNO (operands[0]))
3607 && GET_CODE (operands[1]) == CONST_INT
3608 && INTVAL (operands[1]) >= 0x100
3609 && INTVAL (operands[1]) <= 0xff + 0x7f"
3610 [(set (match_dup 0) (match_dup 1))
3611 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3613 int val = INTVAL (operands[1]);
3615 operands[1] = GEN_INT (0xff);
3616 operands[2] = GEN_INT (val - 0xff);
3619 ;; This insn handles moving CCmode values. It's really just a
3620 ;; slightly simplified copy of movsi_internal2, with additional cases
3621 ;; to move a condition register to a general register and to move
3622 ;; between the general registers and the floating point registers.
3624 (define_insn "movcc"
3625 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
3626 (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
3627 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3628 { return mips_output_move (operands[0], operands[1]); }
3629 [(set_attr "type" "multi,move,load,store,mfc,mtc,fmove,fpload,fpstore")
3630 (set_attr "mode" "SI")
3631 (set_attr "length" "8,4,*,*,4,4,4,*,*")])
3633 ;; Reload condition code registers. reload_incc and reload_outcc
3634 ;; both handle moves from arbitrary operands into condition code
3635 ;; registers. reload_incc handles the more common case in which
3636 ;; a source operand is constrained to be in a condition-code
3637 ;; register, but has not been allocated to one.
3639 ;; Sometimes, such as in movcc, we have a CCmode destination whose
3640 ;; constraints do not include 'z'. reload_outcc handles the case
3641 ;; when such an operand is allocated to a condition-code register.
3643 ;; Note that reloads from a condition code register to some
3644 ;; other location can be done using ordinary moves. Moving
3645 ;; into a GPR takes a single movcc, moving elsewhere takes
3646 ;; two. We can leave these cases to the generic reload code.
3647 (define_expand "reload_incc"
3648 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3649 (match_operand:CC 1 "general_operand" ""))
3650 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3651 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3653 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
3657 (define_expand "reload_outcc"
3658 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3659 (match_operand:CC 1 "register_operand" ""))
3660 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3661 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3663 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
3667 ;; MIPS4 supports loading and storing a floating point register from
3668 ;; the sum of two general registers. We use two versions for each of
3669 ;; these four instructions: one where the two general registers are
3670 ;; SImode, and one where they are DImode. This is because general
3671 ;; registers will be in SImode when they hold 32-bit values, but,
3672 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
3673 ;; instructions will still work correctly.
3675 ;; ??? Perhaps it would be better to support these instructions by
3676 ;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since
3677 ;; these instructions can only be used to load and store floating
3678 ;; point registers, that would probably cause trouble in reload.
3680 (define_insn "*<ANYF:loadx>_<P:mode>"
3681 [(set (match_operand:ANYF 0 "register_operand" "=f")
3682 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3683 (match_operand:P 2 "register_operand" "d"))))]
3685 "<ANYF:loadx>\t%0,%1(%2)"
3686 [(set_attr "type" "fpidxload")
3687 (set_attr "mode" "<ANYF:UNITMODE>")])
3689 (define_insn "*<ANYF:storex>_<P:mode>"
3690 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3691 (match_operand:P 2 "register_operand" "d")))
3692 (match_operand:ANYF 0 "register_operand" "f"))]
3694 "<ANYF:storex>\t%0,%1(%2)"
3695 [(set_attr "type" "fpidxstore")
3696 (set_attr "mode" "<ANYF:UNITMODE>")])
3698 ;; Scaled indexed address load.
3699 ;; Per md.texi, we only need to look for a pattern with multiply in the
3700 ;; address expression, not shift.
3702 (define_insn "*lwxs"
3703 [(set (match_operand:SI 0 "register_operand" "=d")
3704 (mem:SI (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
3706 (match_operand:SI 2 "register_operand" "d"))))]
3709 [(set_attr "type" "load")
3710 (set_attr "mode" "SI")
3711 (set_attr "length" "4")])
3713 ;; 16-bit Integer moves
3715 ;; Unlike most other insns, the move insns can't be split with
3716 ;; different predicates, because register spilling and other parts of
3717 ;; the compiler, have memoized the insn number already.
3718 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3720 (define_expand "movhi"
3721 [(set (match_operand:HI 0 "")
3722 (match_operand:HI 1 ""))]
3725 if (mips_legitimize_move (HImode, operands[0], operands[1]))
3729 (define_insn "*movhi_internal"
3730 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x")
3731 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))]
3733 && (register_operand (operands[0], HImode)
3734 || reg_or_0_operand (operands[1], HImode))"
3744 [(set_attr "type" "move,arith,load,store,mfc,mtc,fmove,mthilo")
3745 (set_attr "mode" "HI")
3746 (set_attr "length" "4,4,*,*,4,4,4,4")])
3748 (define_insn "*movhi_mips16"
3749 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3750 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d"))]
3752 && (register_operand (operands[0], HImode)
3753 || register_operand (operands[1], HImode))"
3762 [(set_attr "type" "move,move,move,arith,arith,load,store")
3763 (set_attr "mode" "HI")
3764 (set_attr_alternative "length"
3768 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3771 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3775 (const_string "*")])])
3778 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
3779 ;; when the original load is a 4 byte instruction but the add and the
3780 ;; load are 2 2 byte instructions.
3783 [(set (match_operand:HI 0 "register_operand")
3784 (mem:HI (plus:SI (match_dup 0)
3785 (match_operand:SI 1 "const_int_operand"))))]
3786 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3787 && REG_P (operands[0])
3788 && M16_REG_P (REGNO (operands[0]))
3789 && GET_CODE (operands[1]) == CONST_INT
3790 && ((INTVAL (operands[1]) < 0
3791 && INTVAL (operands[1]) >= -0x80)
3792 || (INTVAL (operands[1]) >= 32 * 2
3793 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
3794 || (INTVAL (operands[1]) >= 0
3795 && INTVAL (operands[1]) < 32 * 2
3796 && (INTVAL (operands[1]) & 1) != 0))"
3797 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3798 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
3800 HOST_WIDE_INT val = INTVAL (operands[1]);
3803 operands[2] = const0_rtx;
3804 else if (val >= 32 * 2)
3808 operands[1] = GEN_INT (0x7e + off);
3809 operands[2] = GEN_INT (val - off - 0x7e);
3815 operands[1] = GEN_INT (off);
3816 operands[2] = GEN_INT (val - off);
3820 ;; 8-bit Integer moves
3822 ;; Unlike most other insns, the move insns can't be split with
3823 ;; different predicates, because register spilling and other parts of
3824 ;; the compiler, have memoized the insn number already.
3825 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3827 (define_expand "movqi"
3828 [(set (match_operand:QI 0 "")
3829 (match_operand:QI 1 ""))]
3832 if (mips_legitimize_move (QImode, operands[0], operands[1]))
3836 (define_insn "*movqi_internal"
3837 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x")
3838 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))]
3840 && (register_operand (operands[0], QImode)
3841 || reg_or_0_operand (operands[1], QImode))"
3851 [(set_attr "type" "move,arith,load,store,mfc,mtc,fmove,mthilo")
3852 (set_attr "mode" "QI")
3853 (set_attr "length" "4,4,*,*,4,4,4,4")])
3855 (define_insn "*movqi_mips16"
3856 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3857 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d"))]
3859 && (register_operand (operands[0], QImode)
3860 || register_operand (operands[1], QImode))"
3869 [(set_attr "type" "move,move,move,arith,arith,load,store")
3870 (set_attr "mode" "QI")
3871 (set_attr "length" "4,4,4,4,8,*,*")])
3873 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
3874 ;; when the original load is a 4 byte instruction but the add and the
3875 ;; load are 2 2 byte instructions.
3878 [(set (match_operand:QI 0 "register_operand")
3879 (mem:QI (plus:SI (match_dup 0)
3880 (match_operand:SI 1 "const_int_operand"))))]
3881 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3882 && REG_P (operands[0])
3883 && M16_REG_P (REGNO (operands[0]))
3884 && GET_CODE (operands[1]) == CONST_INT
3885 && ((INTVAL (operands[1]) < 0
3886 && INTVAL (operands[1]) >= -0x80)
3887 || (INTVAL (operands[1]) >= 32
3888 && INTVAL (operands[1]) <= 31 + 0x7f))"
3889 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3890 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
3892 HOST_WIDE_INT val = INTVAL (operands[1]);
3895 operands[2] = const0_rtx;
3898 operands[1] = GEN_INT (0x7f);
3899 operands[2] = GEN_INT (val - 0x7f);
3903 ;; 32-bit floating point moves
3905 (define_expand "movsf"
3906 [(set (match_operand:SF 0 "")
3907 (match_operand:SF 1 ""))]
3910 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
3914 (define_insn "*movsf_hardfloat"
3915 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3916 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
3918 && (register_operand (operands[0], SFmode)
3919 || reg_or_0_operand (operands[1], SFmode))"
3920 { return mips_output_move (operands[0], operands[1]); }
3921 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
3922 (set_attr "mode" "SF")
3923 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3925 (define_insn "*movsf_softfloat"
3926 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
3927 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
3928 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
3929 && (register_operand (operands[0], SFmode)
3930 || reg_or_0_operand (operands[1], SFmode))"
3931 { return mips_output_move (operands[0], operands[1]); }
3932 [(set_attr "type" "move,load,store")
3933 (set_attr "mode" "SF")
3934 (set_attr "length" "4,*,*")])
3936 (define_insn "*movsf_mips16"
3937 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
3938 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
3940 && (register_operand (operands[0], SFmode)
3941 || register_operand (operands[1], SFmode))"
3942 { return mips_output_move (operands[0], operands[1]); }
3943 [(set_attr "type" "move,move,move,load,store")
3944 (set_attr "mode" "SF")
3945 (set_attr "length" "4,4,4,*,*")])
3948 ;; 64-bit floating point moves
3950 (define_expand "movdf"
3951 [(set (match_operand:DF 0 "")
3952 (match_operand:DF 1 ""))]
3955 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
3959 (define_insn "*movdf_hardfloat_64bit"
3960 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3961 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
3962 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_64BIT
3963 && (register_operand (operands[0], DFmode)
3964 || reg_or_0_operand (operands[1], DFmode))"
3965 { return mips_output_move (operands[0], operands[1]); }
3966 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
3967 (set_attr "mode" "DF")
3968 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3970 ;; This pattern applies to both !TARGET_FLOAT64 and TARGET_FLOAT64.
3971 (define_insn "*movdf_hardfloat_32bit"
3972 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3973 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
3974 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT
3975 && (register_operand (operands[0], DFmode)
3976 || reg_or_0_operand (operands[1], DFmode))"
3977 { return mips_output_move (operands[0], operands[1]); }
3978 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
3979 (set_attr "mode" "DF")
3980 (set_attr "length" "4,8,*,*,*,8,8,8,*,*")])
3982 (define_insn "*movdf_softfloat"
3983 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m,d,f,f")
3984 (match_operand:DF 1 "move_operand" "dG,m,dG,f,d,f"))]
3985 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
3986 && (register_operand (operands[0], DFmode)
3987 || reg_or_0_operand (operands[1], DFmode))"
3988 { return mips_output_move (operands[0], operands[1]); }
3989 [(set_attr "type" "multi,load,store,mfc,mtc,fmove")
3990 (set_attr "mode" "DF")
3991 (set_attr "length" "8,*,*,4,4,4")])
3993 (define_insn "*movdf_mips16"
3994 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
3995 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
3997 && (register_operand (operands[0], DFmode)
3998 || register_operand (operands[1], DFmode))"
3999 { return mips_output_move (operands[0], operands[1]); }
4000 [(set_attr "type" "multi,multi,multi,load,store")
4001 (set_attr "mode" "DF")
4002 (set_attr "length" "8,8,8,*,*")])
4005 [(set (match_operand:DI 0 "nonimmediate_operand")
4006 (match_operand:DI 1 "move_operand"))]
4007 "reload_completed && !TARGET_64BIT
4008 && mips_split_64bit_move_p (operands[0], operands[1])"
4011 mips_split_64bit_move (operands[0], operands[1]);
4016 [(set (match_operand:DF 0 "nonimmediate_operand")
4017 (match_operand:DF 1 "move_operand"))]
4018 "reload_completed && !TARGET_64BIT
4019 && mips_split_64bit_move_p (operands[0], operands[1])"
4022 mips_split_64bit_move (operands[0], operands[1]);
4026 ;; When generating mips16 code, split moves of negative constants into
4027 ;; a positive "li" followed by a negation.
4029 [(set (match_operand 0 "register_operand")
4030 (match_operand 1 "const_int_operand"))]
4031 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
4035 (neg:SI (match_dup 2)))]
4037 operands[2] = gen_lowpart (SImode, operands[0]);
4038 operands[3] = GEN_INT (-INTVAL (operands[1]));
4041 ;; 64-bit paired-single floating point moves
4043 (define_expand "movv2sf"
4044 [(set (match_operand:V2SF 0)
4045 (match_operand:V2SF 1))]
4046 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
4048 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
4052 (define_insn "movv2sf_hardfloat_64bit"
4053 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4054 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
4057 && TARGET_PAIRED_SINGLE_FLOAT
4058 && (register_operand (operands[0], V2SFmode)
4059 || reg_or_0_operand (operands[1], V2SFmode))"
4060 { return mips_output_move (operands[0], operands[1]); }
4061 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4062 (set_attr "mode" "SF")
4063 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
4065 ;; The HI and LO registers are not truly independent. If we move an mthi
4066 ;; instruction before an mflo instruction, it will make the result of the
4067 ;; mflo unpredictable. The same goes for mtlo and mfhi.
4069 ;; We cope with this by making the mflo and mfhi patterns use both HI and LO.
4070 ;; Operand 1 is the register we want, operand 2 is the other one.
4072 ;; When generating VR4120 or VR4130 code, we use macc{,hi} and
4073 ;; dmacc{,hi} instead of mfhi and mflo. This avoids both the normal
4074 ;; MIPS III hi/lo hazards and the errata related to -mfix-vr4130.
4076 (define_expand "mfhilo_<mode>"
4077 [(set (match_operand:GPR 0 "register_operand")
4078 (unspec:GPR [(match_operand:GPR 1 "register_operand")
4079 (match_operand:GPR 2 "register_operand")]
4082 (define_insn "*mfhilo_<mode>"
4083 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4084 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
4085 (match_operand:GPR 2 "register_operand" "l,h")]
4089 [(set_attr "type" "mfhilo")
4090 (set_attr "mode" "<MODE>")])
4092 (define_insn "*mfhilo_<mode>_macc"
4093 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4094 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
4095 (match_operand:GPR 2 "register_operand" "l,h")]
4101 [(set_attr "type" "mfhilo")
4102 (set_attr "mode" "<MODE>")])
4104 ;; Patterns for loading or storing part of a paired floating point
4105 ;; register. We need them because odd-numbered floating-point registers
4106 ;; are not fully independent: see mips_split_64bit_move.
4108 ;; Load the low word of operand 0 with operand 1.
4109 (define_insn "load_df_low"
4110 [(set (match_operand:DF 0 "register_operand" "=f,f")
4111 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")]
4112 UNSPEC_LOAD_DF_LOW))]
4113 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
4115 operands[0] = mips_subword (operands[0], 0);
4116 return mips_output_move (operands[0], operands[1]);
4118 [(set_attr "type" "mtc,fpload")
4119 (set_attr "mode" "SF")])
4121 ;; Load the high word of operand 0 from operand 1, preserving the value
4123 (define_insn "load_df_high"
4124 [(set (match_operand:DF 0 "register_operand" "=f,f")
4125 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")
4126 (match_operand:DF 2 "register_operand" "0,0")]
4127 UNSPEC_LOAD_DF_HIGH))]
4128 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
4130 operands[0] = mips_subword (operands[0], 1);
4131 return mips_output_move (operands[0], operands[1]);
4133 [(set_attr "type" "mtc,fpload")
4134 (set_attr "mode" "SF")])
4136 ;; Store the high word of operand 1 in operand 0. The corresponding
4137 ;; low-word move is done in the normal way.
4138 (define_insn "store_df_high"
4139 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
4140 (unspec:SI [(match_operand:DF 1 "register_operand" "f,f")]
4141 UNSPEC_STORE_DF_HIGH))]
4142 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
4144 operands[1] = mips_subword (operands[1], 1);
4145 return mips_output_move (operands[0], operands[1]);
4147 [(set_attr "type" "mfc,fpstore")
4148 (set_attr "mode" "SF")])
4150 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
4151 ;; value in the low word.
4152 (define_insn "mthc1"
4153 [(set (match_operand:DF 0 "register_operand" "=f")
4154 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ")
4155 (match_operand:DF 2 "register_operand" "0")]
4157 "TARGET_HARD_FLOAT && !TARGET_64BIT && ISA_HAS_MXHC1"
4159 [(set_attr "type" "mtc")
4160 (set_attr "mode" "SF")])
4162 ;; Move high word of operand 1 to operand 0 using mfhc1. The corresponding
4163 ;; low-word move is done in the normal way.
4164 (define_insn "mfhc1"
4165 [(set (match_operand:SI 0 "register_operand" "=d")
4166 (unspec:SI [(match_operand:DF 1 "register_operand" "f")]
4168 "TARGET_HARD_FLOAT && !TARGET_64BIT && ISA_HAS_MXHC1"
4170 [(set_attr "type" "mfc")
4171 (set_attr "mode" "SF")])
4173 ;; Move a constant that satisfies CONST_GP_P into operand 0.
4174 (define_expand "load_const_gp"
4175 [(set (match_operand 0 "register_operand" "=d")
4176 (const (unspec [(const_int 0)] UNSPEC_GP)))])
4178 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
4179 ;; of _gp from the start of this function. Operand 1 is the incoming
4180 ;; function address.
4181 (define_insn_and_split "loadgp_newabi"
4182 [(unspec_volatile [(match_operand 0 "" "")
4183 (match_operand 1 "register_operand" "")] UNSPEC_LOADGP)]
4184 "mips_current_loadgp_style () == LOADGP_NEWABI"
4187 [(set (match_dup 2) (match_dup 3))
4188 (set (match_dup 2) (match_dup 4))
4189 (set (match_dup 2) (match_dup 5))]
4191 operands[2] = pic_offset_table_rtx;
4192 operands[3] = gen_rtx_HIGH (Pmode, operands[0]);
4193 operands[4] = gen_rtx_PLUS (Pmode, operands[2], operands[1]);
4194 operands[5] = gen_rtx_LO_SUM (Pmode, operands[2], operands[0]);
4196 [(set_attr "length" "12")])
4198 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
4199 (define_insn_and_split "loadgp_absolute"
4200 [(unspec_volatile [(match_operand 0 "" "")] UNSPEC_LOADGP)]
4201 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
4206 mips_emit_move (pic_offset_table_rtx, operands[0]);
4209 [(set_attr "length" "8")])
4211 ;; The use of gp is hidden when not using explicit relocations.
4212 ;; This blockage instruction prevents the gp load from being
4213 ;; scheduled after an implicit use of gp. It also prevents
4214 ;; the load from being deleted as dead.
4215 (define_insn "loadgp_blockage"
4216 [(unspec_volatile [(reg:DI 28)] UNSPEC_BLOCKAGE)]
4219 [(set_attr "type" "unknown")
4220 (set_attr "mode" "none")
4221 (set_attr "length" "0")])
4223 ;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
4224 ;; and operand 1 is the __GOTT_INDEX__ symbol.
4225 (define_insn "loadgp_rtp"
4226 [(unspec_volatile [(match_operand 0 "symbol_ref_operand")
4227 (match_operand 1 "symbol_ref_operand")] UNSPEC_LOADGP)]
4228 "mips_current_loadgp_style () == LOADGP_RTP"
4230 [(set_attr "length" "12")])
4233 [(unspec_volatile [(match_operand:P 0 "symbol_ref_operand")
4234 (match_operand:P 1 "symbol_ref_operand")] UNSPEC_LOADGP)]
4235 "mips_current_loadgp_style () == LOADGP_RTP"
4236 [(set (match_dup 2) (high:P (match_dup 3)))
4237 (set (match_dup 2) (unspec:P [(match_dup 2)
4238 (match_dup 3)] UNSPEC_LOAD_GOT))
4239 (set (match_dup 2) (unspec:P [(match_dup 2)
4240 (match_dup 4)] UNSPEC_LOAD_GOT))]
4242 operands[2] = pic_offset_table_rtx;
4243 operands[3] = mips_unspec_address (operands[0], SYMBOL_ABSOLUTE);
4244 operands[4] = mips_unspec_address (operands[1], SYMBOL_HALF);
4247 ;; Emit a .cprestore directive, which normally expands to a single store
4248 ;; instruction. Note that we continue to use .cprestore for explicit reloc
4249 ;; code so that jals inside inline asms will work correctly.
4250 (define_insn "cprestore"
4251 [(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")
4256 if (set_nomacro && which_alternative == 1)
4257 return ".set\tmacro\;.cprestore\t%0\;.set\tnomacro";
4259 return ".cprestore\t%0";
4261 [(set_attr "type" "store")
4262 (set_attr "length" "4,12")])
4264 ;; Expand in-line code to clear the instruction cache between operand[0] and
4266 (define_expand "clear_cache"
4267 [(match_operand 0 "pmode_register_operand")
4268 (match_operand 1 "pmode_register_operand")]
4274 mips_expand_synci_loop (operands[0], operands[1]);
4275 emit_insn (gen_sync ());
4276 emit_insn (gen_clear_hazard ());
4278 else if (mips_cache_flush_func && mips_cache_flush_func[0])
4280 rtx len = gen_reg_rtx (Pmode);
4281 emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
4282 MIPS_ICACHE_SYNC (operands[0], len);
4288 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
4292 (define_insn "synci"
4293 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
4298 (define_insn "rdhwr"
4299 [(set (match_operand:SI 0 "register_operand" "=d")
4300 (unspec_volatile [(match_operand:SI 1 "const_int_operand" "n")]
4305 (define_insn "clear_hazard"
4306 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
4307 (clobber (reg:SI 31))]
4310 return ".set\tpush\n"
4311 "\t.set\tnoreorder\n"
4315 "1:\taddiu\t$31,$31,12\n"
4320 [(set_attr "length" "20")])
4322 ;; Atomic memory operations.
4324 (define_insn "memory_barrier"
4325 [(set (mem:BLK (scratch))
4326 (unspec:BLK [(const_int 0)] UNSPEC_MEMORY_BARRIER))]
4330 (define_insn "sync_compare_and_swap<mode>"
4331 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
4332 (match_operand:GPR 1 "memory_operand" "+R,R"))
4334 (unspec_volatile:GPR [(match_operand:GPR 2 "register_operand" "d,d")
4335 (match_operand:GPR 3 "arith_operand" "I,d")]
4336 UNSPEC_COMPARE_AND_SWAP))]
4339 if (which_alternative == 0)
4340 return MIPS_COMPARE_AND_SWAP ("<d>", "li");
4342 return MIPS_COMPARE_AND_SWAP ("<d>", "move");
4344 [(set_attr "length" "32")])
4346 (define_insn "sync_add<mode>"
4347 [(set (match_operand:GPR 0 "memory_operand" "+R,R")
4348 (unspec_volatile:GPR
4349 [(plus:GPR (match_dup 0)
4350 (match_operand:GPR 1 "arith_operand" "I,d"))]
4351 UNSPEC_SYNC_OLD_OP))]
4354 if (which_alternative == 0)
4355 return MIPS_SYNC_OP ("<d>", "<d>addiu");
4357 return MIPS_SYNC_OP ("<d>", "<d>addu");
4359 [(set_attr "length" "28")])
4361 (define_insn "sync_sub<mode>"
4362 [(set (match_operand:GPR 0 "memory_operand" "+R")
4363 (unspec_volatile:GPR
4364 [(minus:GPR (match_dup 0)
4365 (match_operand:GPR 1 "register_operand" "d"))]
4366 UNSPEC_SYNC_OLD_OP))]
4369 return MIPS_SYNC_OP ("<d>", "<d>subu");
4371 [(set_attr "length" "28")])
4373 (define_insn "sync_old_add<mode>"
4374 [(set (match_operand:GPR 0 "register_operand" "=d,&d")
4375 (match_operand:GPR 1 "memory_operand" "+R,R"))
4377 (unspec_volatile:GPR
4378 [(plus:GPR (match_dup 1)
4379 (match_operand:GPR 2 "arith_operand" "I,d"))]
4380 UNSPEC_SYNC_OLD_OP))]
4383 if (which_alternative == 0)
4384 return MIPS_SYNC_OLD_OP ("<d>", "<d>addiu");
4386 return MIPS_SYNC_OLD_OP ("<d>", "<d>addu");
4388 [(set_attr "length" "28")])
4390 (define_insn "sync_old_sub<mode>"
4391 [(set (match_operand:GPR 0 "register_operand" "=&d")
4392 (match_operand:GPR 1 "memory_operand" "+R"))
4394 (unspec_volatile:GPR
4395 [(minus:GPR (match_dup 1)
4396 (match_operand:GPR 2 "register_operand" "d"))]
4397 UNSPEC_SYNC_OLD_OP))]
4400 return MIPS_SYNC_OLD_OP ("<d>", "<d>subu");
4402 [(set_attr "length" "28")])
4404 (define_insn "sync_new_add<mode>"
4405 [(set (match_operand:GPR 0 "register_operand" "=d,&d")
4406 (plus:GPR (match_operand:GPR 1 "memory_operand" "+R,R")
4407 (match_operand:GPR 2 "arith_operand" "I,d")))
4409 (unspec_volatile:GPR
4410 [(plus:GPR (match_dup 1) (match_dup 2))]
4411 UNSPEC_SYNC_NEW_OP))]
4414 if (which_alternative == 0)
4415 return MIPS_SYNC_NEW_OP ("<d>", "<d>addiu");
4417 return MIPS_SYNC_NEW_OP ("<d>", "<d>addu");
4419 [(set_attr "length" "28")])
4421 (define_insn "sync_new_sub<mode>"
4422 [(set (match_operand:GPR 0 "register_operand" "=&d")
4423 (minus:GPR (match_operand:GPR 1 "memory_operand" "+R")
4424 (match_operand:GPR 2 "register_operand" "d")))
4426 (unspec_volatile:GPR
4427 [(minus:GPR (match_dup 1) (match_dup 2))]
4428 UNSPEC_SYNC_NEW_OP))]
4431 return MIPS_SYNC_NEW_OP ("<d>", "<d>subu");
4433 [(set_attr "length" "28")])
4435 (define_insn "sync_<optab><mode>"
4436 [(set (match_operand:GPR 0 "memory_operand" "+R,R")
4437 (unspec_volatile:GPR
4438 [(fetchop_bit:GPR (match_operand:GPR 1 "uns_arith_operand" "K,d")
4440 UNSPEC_SYNC_OLD_OP))]
4443 if (which_alternative == 0)
4444 return MIPS_SYNC_OP ("<d>", "<immediate_insn>");
4446 return MIPS_SYNC_OP ("<d>", "<insn>");
4448 [(set_attr "length" "28")])
4450 (define_insn "sync_old_<optab><mode>"
4451 [(set (match_operand:GPR 0 "register_operand" "=d,&d")
4452 (match_operand:GPR 1 "memory_operand" "+R,R"))
4454 (unspec_volatile:GPR
4455 [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
4457 UNSPEC_SYNC_OLD_OP))]
4460 if (which_alternative == 0)
4461 return MIPS_SYNC_OLD_OP ("<d>", "<immediate_insn>");
4463 return MIPS_SYNC_OLD_OP ("<d>", "<insn>");
4465 [(set_attr "length" "28")])
4467 (define_insn "sync_new_<optab><mode>"
4468 [(set (match_operand:GPR 0 "register_operand" "=d,&d")
4469 (match_operand:GPR 1 "memory_operand" "+R,R"))
4471 (unspec_volatile:GPR
4472 [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
4474 UNSPEC_SYNC_NEW_OP))]
4477 if (which_alternative == 0)
4478 return MIPS_SYNC_NEW_OP ("<d>", "<immediate_insn>");
4480 return MIPS_SYNC_NEW_OP ("<d>", "<insn>");
4482 [(set_attr "length" "28")])
4484 (define_insn "sync_nand<mode>"
4485 [(set (match_operand:GPR 0 "memory_operand" "+R,R")
4486 (unspec_volatile:GPR [(match_operand:GPR 1 "uns_arith_operand" "K,d")]
4487 UNSPEC_SYNC_OLD_OP))]
4490 if (which_alternative == 0)
4491 return MIPS_SYNC_NAND ("<d>", "andi");
4493 return MIPS_SYNC_NAND ("<d>", "and");
4495 [(set_attr "length" "32")])
4497 (define_insn "sync_old_nand<mode>"
4498 [(set (match_operand:GPR 0 "register_operand" "=d,&d")
4499 (match_operand:GPR 1 "memory_operand" "+R,R"))
4501 (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
4502 UNSPEC_SYNC_OLD_OP))]
4505 if (which_alternative == 0)
4506 return MIPS_SYNC_OLD_NAND ("<d>", "andi");
4508 return MIPS_SYNC_OLD_NAND ("<d>", "and");
4510 [(set_attr "length" "32")])
4512 (define_insn "sync_new_nand<mode>"
4513 [(set (match_operand:GPR 0 "register_operand" "=d,&d")
4514 (match_operand:GPR 1 "memory_operand" "+R,R"))
4516 (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
4517 UNSPEC_SYNC_NEW_OP))]
4520 if (which_alternative == 0)
4521 return MIPS_SYNC_NEW_NAND ("<d>", "andi");
4523 return MIPS_SYNC_NEW_NAND ("<d>", "and");
4525 [(set_attr "length" "32")])
4527 (define_insn "sync_lock_test_and_set<mode>"
4528 [(set (match_operand:GPR 0 "register_operand" "=d,&d")
4529 (match_operand:GPR 1 "memory_operand" "+R,R"))
4531 (unspec_volatile:GPR [(match_operand:GPR 2 "arith_operand" "I,d")]
4532 UNSPEC_SYNC_EXCHANGE))]
4535 if (which_alternative == 0)
4536 return MIPS_SYNC_EXCHANGE ("<d>", "li");
4538 return MIPS_SYNC_EXCHANGE ("<d>", "move");
4540 [(set_attr "length" "24")])
4542 ;; Block moves, see mips.c for more details.
4543 ;; Argument 0 is the destination
4544 ;; Argument 1 is the source
4545 ;; Argument 2 is the length
4546 ;; Argument 3 is the alignment
4548 (define_expand "movmemsi"
4549 [(parallel [(set (match_operand:BLK 0 "general_operand")
4550 (match_operand:BLK 1 "general_operand"))
4551 (use (match_operand:SI 2 ""))
4552 (use (match_operand:SI 3 "const_int_operand"))])]
4553 "!TARGET_MIPS16 && !TARGET_MEMCPY"
4555 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
4562 ;; ....................
4566 ;; ....................
4568 (define_expand "<optab><mode>3"
4569 [(set (match_operand:GPR 0 "register_operand")
4570 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4571 (match_operand:SI 2 "arith_operand")))]
4574 /* On the mips16, a shift of more than 8 is a four byte instruction,
4575 so, for a shift between 8 and 16, it is just as fast to do two
4576 shifts of 8 or less. If there is a lot of shifting going on, we
4577 may win in CSE. Otherwise combine will put the shifts back
4578 together again. This can be called by function_arg, so we must
4579 be careful not to allocate a new register if we've reached the
4583 && GET_CODE (operands[2]) == CONST_INT
4584 && INTVAL (operands[2]) > 8
4585 && INTVAL (operands[2]) <= 16
4586 && !reload_in_progress
4587 && !reload_completed)
4589 rtx temp = gen_reg_rtx (<MODE>mode);
4591 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
4592 emit_insn (gen_<optab><mode>3 (operands[0], temp,
4593 GEN_INT (INTVAL (operands[2]) - 8)));
4598 (define_insn "*<optab><mode>3"
4599 [(set (match_operand:GPR 0 "register_operand" "=d")
4600 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
4601 (match_operand:SI 2 "arith_operand" "dI")))]
4604 if (GET_CODE (operands[2]) == CONST_INT)
4605 operands[2] = GEN_INT (INTVAL (operands[2])
4606 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
4608 return "<d><insn>\t%0,%1,%2";
4610 [(set_attr "type" "shift")
4611 (set_attr "mode" "<MODE>")])
4613 (define_insn "*<optab>si3_extend"
4614 [(set (match_operand:DI 0 "register_operand" "=d")
4616 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
4617 (match_operand:SI 2 "arith_operand" "dI"))))]
4618 "TARGET_64BIT && !TARGET_MIPS16"
4620 if (GET_CODE (operands[2]) == CONST_INT)
4621 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4623 return "<insn>\t%0,%1,%2";
4625 [(set_attr "type" "shift")
4626 (set_attr "mode" "SI")])
4628 (define_insn "*<optab>si3_mips16"
4629 [(set (match_operand:SI 0 "register_operand" "=d,d")
4630 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
4631 (match_operand:SI 2 "arith_operand" "d,I")))]
4634 if (which_alternative == 0)
4635 return "<insn>\t%0,%2";
4637 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4638 return "<insn>\t%0,%1,%2";
4640 [(set_attr "type" "shift")
4641 (set_attr "mode" "SI")
4642 (set_attr_alternative "length"
4644 (if_then_else (match_operand 2 "m16_uimm3_b")
4648 ;; We need separate DImode MIPS16 patterns because of the irregularity
4650 (define_insn "*ashldi3_mips16"
4651 [(set (match_operand:DI 0 "register_operand" "=d,d")
4652 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
4653 (match_operand:SI 2 "arith_operand" "d,I")))]
4654 "TARGET_64BIT && TARGET_MIPS16"
4656 if (which_alternative == 0)
4657 return "dsll\t%0,%2";
4659 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4660 return "dsll\t%0,%1,%2";
4662 [(set_attr "type" "shift")
4663 (set_attr "mode" "DI")
4664 (set_attr_alternative "length"
4666 (if_then_else (match_operand 2 "m16_uimm3_b")
4670 (define_insn "*ashrdi3_mips16"
4671 [(set (match_operand:DI 0 "register_operand" "=d,d")
4672 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4673 (match_operand:SI 2 "arith_operand" "d,I")))]
4674 "TARGET_64BIT && TARGET_MIPS16"
4676 if (GET_CODE (operands[2]) == CONST_INT)
4677 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4679 return "dsra\t%0,%2";
4681 [(set_attr "type" "shift")
4682 (set_attr "mode" "DI")
4683 (set_attr_alternative "length"
4685 (if_then_else (match_operand 2 "m16_uimm3_b")
4689 (define_insn "*lshrdi3_mips16"
4690 [(set (match_operand:DI 0 "register_operand" "=d,d")
4691 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4692 (match_operand:SI 2 "arith_operand" "d,I")))]
4693 "TARGET_64BIT && TARGET_MIPS16"
4695 if (GET_CODE (operands[2]) == CONST_INT)
4696 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4698 return "dsrl\t%0,%2";
4700 [(set_attr "type" "shift")
4701 (set_attr "mode" "DI")
4702 (set_attr_alternative "length"
4704 (if_then_else (match_operand 2 "m16_uimm3_b")
4708 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
4711 [(set (match_operand:GPR 0 "register_operand")
4712 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4713 (match_operand:GPR 2 "const_int_operand")))]
4714 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4715 && GET_CODE (operands[2]) == CONST_INT
4716 && INTVAL (operands[2]) > 8
4717 && INTVAL (operands[2]) <= 16"
4718 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
4719 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
4720 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
4722 ;; If we load a byte on the mips16 as a bitfield, the resulting
4723 ;; sequence of instructions is too complicated for combine, because it
4724 ;; involves four instructions: a load, a shift, a constant load into a
4725 ;; register, and an and (the key problem here is that the mips16 does
4726 ;; not have and immediate). We recognize a shift of a load in order
4727 ;; to make it simple enough for combine to understand.
4729 ;; The length here is the worst case: the length of the split version
4730 ;; will be more accurate.
4731 (define_insn_and_split ""
4732 [(set (match_operand:SI 0 "register_operand" "=d")
4733 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
4734 (match_operand:SI 2 "immediate_operand" "I")))]
4738 [(set (match_dup 0) (match_dup 1))
4739 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
4741 [(set_attr "type" "load")
4742 (set_attr "mode" "SI")
4743 (set_attr "length" "16")])
4745 (define_insn "rotr<mode>3"
4746 [(set (match_operand:GPR 0 "register_operand" "=d")
4747 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
4748 (match_operand:SI 2 "arith_operand" "dI")))]
4751 if (GET_CODE (operands[2]) == CONST_INT)
4752 gcc_assert (INTVAL (operands[2]) >= 0
4753 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
4755 return "<d>ror\t%0,%1,%2";
4757 [(set_attr "type" "shift")
4758 (set_attr "mode" "<MODE>")])
4761 ;; ....................
4765 ;; ....................
4767 ;; Flow here is rather complex:
4769 ;; 1) The cmp{si,di,sf,df} routine is called. It deposits the arguments
4770 ;; into cmp_operands[] but generates no RTL.
4772 ;; 2) The appropriate branch define_expand is called, which then
4773 ;; creates the appropriate RTL for the comparison and branch.
4774 ;; Different CC modes are used, based on what type of branch is
4775 ;; done, so that we can constrain things appropriately. There
4776 ;; are assumptions in the rest of GCC that break if we fold the
4777 ;; operands into the branches for integer operations, and use cc0
4778 ;; for floating point, so we use the fp status register instead.
4779 ;; If needed, an appropriate temporary is created to hold the
4780 ;; of the integer compare.
4782 (define_expand "cmp<mode>"
4784 (compare:CC (match_operand:GPR 0 "register_operand")
4785 (match_operand:GPR 1 "nonmemory_operand")))]
4788 cmp_operands[0] = operands[0];
4789 cmp_operands[1] = operands[1];
4793 (define_expand "cmp<mode>"
4795 (compare:CC (match_operand:SCALARF 0 "register_operand")
4796 (match_operand:SCALARF 1 "register_operand")))]
4799 cmp_operands[0] = operands[0];
4800 cmp_operands[1] = operands[1];
4805 ;; ....................
4807 ;; CONDITIONAL BRANCHES
4809 ;; ....................
4811 ;; Conditional branches on floating-point equality tests.
4813 (define_insn "*branch_fp"
4816 (match_operator 0 "equality_operator"
4817 [(match_operand:CC 2 "register_operand" "z")
4819 (label_ref (match_operand 1 "" ""))
4823 return mips_output_conditional_branch (insn, operands,
4824 MIPS_BRANCH ("b%F0", "%Z2%1"),
4825 MIPS_BRANCH ("b%W0", "%Z2%1"));
4827 [(set_attr "type" "branch")
4828 (set_attr "mode" "none")])
4830 (define_insn "*branch_fp_inverted"
4833 (match_operator 0 "equality_operator"
4834 [(match_operand:CC 2 "register_operand" "z")
4837 (label_ref (match_operand 1 "" ""))))]
4840 return mips_output_conditional_branch (insn, operands,
4841 MIPS_BRANCH ("b%W0", "%Z2%1"),
4842 MIPS_BRANCH ("b%F0", "%Z2%1"));
4844 [(set_attr "type" "branch")
4845 (set_attr "mode" "none")])
4847 ;; Conditional branches on ordered comparisons with zero.
4849 (define_insn "*branch_order<mode>"
4852 (match_operator 0 "order_operator"
4853 [(match_operand:GPR 2 "register_operand" "d")
4855 (label_ref (match_operand 1 "" ""))
4858 { return mips_output_order_conditional_branch (insn, operands, false); }
4859 [(set_attr "type" "branch")
4860 (set_attr "mode" "none")])
4862 (define_insn "*branch_order<mode>_inverted"
4865 (match_operator 0 "order_operator"
4866 [(match_operand:GPR 2 "register_operand" "d")
4869 (label_ref (match_operand 1 "" ""))))]
4871 { return mips_output_order_conditional_branch (insn, operands, true); }
4872 [(set_attr "type" "branch")
4873 (set_attr "mode" "none")])
4875 ;; Conditional branch on equality comparison.
4877 (define_insn "*branch_equality<mode>"
4880 (match_operator 0 "equality_operator"
4881 [(match_operand:GPR 2 "register_operand" "d")
4882 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
4883 (label_ref (match_operand 1 "" ""))
4887 return mips_output_conditional_branch (insn, operands,
4888 MIPS_BRANCH ("b%C0", "%2,%z3,%1"),
4889 MIPS_BRANCH ("b%N0", "%2,%z3,%1"));
4891 [(set_attr "type" "branch")
4892 (set_attr "mode" "none")])
4894 (define_insn "*branch_equality<mode>_inverted"
4897 (match_operator 0 "equality_operator"
4898 [(match_operand:GPR 2 "register_operand" "d")
4899 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
4901 (label_ref (match_operand 1 "" ""))))]
4904 return mips_output_conditional_branch (insn, operands,
4905 MIPS_BRANCH ("b%N0", "%2,%z3,%1"),
4906 MIPS_BRANCH ("b%C0", "%2,%z3,%1"));
4908 [(set_attr "type" "branch")
4909 (set_attr "mode" "none")])
4913 (define_insn "*branch_equality<mode>_mips16"
4916 (match_operator 0 "equality_operator"
4917 [(match_operand:GPR 1 "register_operand" "d,t")
4919 (match_operand 2 "pc_or_label_operand" "")
4920 (match_operand 3 "pc_or_label_operand" "")))]
4923 if (operands[2] != pc_rtx)
4925 if (which_alternative == 0)
4926 return "b%C0z\t%1,%2";
4928 return "bt%C0z\t%2";
4932 if (which_alternative == 0)
4933 return "b%N0z\t%1,%3";
4935 return "bt%N0z\t%3";
4938 [(set_attr "type" "branch")
4939 (set_attr "mode" "none")
4940 (set_attr "length" "8")])
4942 (define_expand "b<code>"
4944 (if_then_else (any_cond:CC (cc0)
4946 (label_ref (match_operand 0 ""))
4950 gen_conditional_branch (operands, <CODE>);
4954 ;; Used to implement built-in functions.
4955 (define_expand "condjump"
4957 (if_then_else (match_operand 0)
4958 (label_ref (match_operand 1))
4962 ;; ....................
4964 ;; SETTING A REGISTER FROM A COMPARISON
4966 ;; ....................
4968 (define_expand "seq"
4969 [(set (match_operand:SI 0 "register_operand")
4970 (eq:SI (match_dup 1)
4973 { if (mips_emit_scc (EQ, operands[0])) DONE; else FAIL; })
4975 (define_insn "*seq_<mode>"
4976 [(set (match_operand:GPR 0 "register_operand" "=d")
4977 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
4981 [(set_attr "type" "slt")
4982 (set_attr "mode" "<MODE>")])
4984 (define_insn "*seq_<mode>_mips16"
4985 [(set (match_operand:GPR 0 "register_operand" "=t")
4986 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
4990 [(set_attr "type" "slt")
4991 (set_attr "mode" "<MODE>")])
4993 ;; "sne" uses sltu instructions in which the first operand is $0.
4994 ;; This isn't possible in mips16 code.
4996 (define_expand "sne"
4997 [(set (match_operand:SI 0 "register_operand")
4998 (ne:SI (match_dup 1)
5001 { if (mips_emit_scc (NE, operands[0])) DONE; else FAIL; })
5003 (define_insn "*sne_<mode>"
5004 [(set (match_operand:GPR 0 "register_operand" "=d")
5005 (ne:GPR (match_operand:GPR 1 "register_operand" "d")
5009 [(set_attr "type" "slt")
5010 (set_attr "mode" "<MODE>")])
5012 (define_expand "sgt"
5013 [(set (match_operand:SI 0 "register_operand")
5014 (gt:SI (match_dup 1)
5017 { if (mips_emit_scc (GT, operands[0])) DONE; else FAIL; })
5019 (define_insn "*sgt_<mode>"
5020 [(set (match_operand:GPR 0 "register_operand" "=d")
5021 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
5022 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
5025 [(set_attr "type" "slt")
5026 (set_attr "mode" "<MODE>")])
5028 (define_insn "*sgt_<mode>_mips16"
5029 [(set (match_operand:GPR 0 "register_operand" "=t")
5030 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
5031 (match_operand:GPR 2 "register_operand" "d")))]
5034 [(set_attr "type" "slt")
5035 (set_attr "mode" "<MODE>")])
5037 (define_expand "sge"
5038 [(set (match_operand:SI 0 "register_operand")
5039 (ge:SI (match_dup 1)
5042 { if (mips_emit_scc (GE, operands[0])) DONE; else FAIL; })
5044 (define_insn "*sge_<mode>"
5045 [(set (match_operand:GPR 0 "register_operand" "=d")
5046 (ge:GPR (match_operand:GPR 1 "register_operand" "d")
5050 [(set_attr "type" "slt")
5051 (set_attr "mode" "<MODE>")])
5053 (define_expand "slt"
5054 [(set (match_operand:SI 0 "register_operand")
5055 (lt:SI (match_dup 1)
5058 { if (mips_emit_scc (LT, operands[0])) DONE; else FAIL; })
5060 (define_insn "*slt_<mode>"
5061 [(set (match_operand:GPR 0 "register_operand" "=d")
5062 (lt:GPR (match_operand:GPR 1 "register_operand" "d")
5063 (match_operand:GPR 2 "arith_operand" "dI")))]
5066 [(set_attr "type" "slt")
5067 (set_attr "mode" "<MODE>")])
5069 (define_insn "*slt_<mode>_mips16"
5070 [(set (match_operand:GPR 0 "register_operand" "=t,t")
5071 (lt:GPR (match_operand:GPR 1 "register_operand" "d,d")
5072 (match_operand:GPR 2 "arith_operand" "d,I")))]
5075 [(set_attr "type" "slt")
5076 (set_attr "mode" "<MODE>")
5077 (set_attr_alternative "length"
5079 (if_then_else (match_operand 2 "m16_uimm8_1")
5083 (define_expand "sle"
5084 [(set (match_operand:SI 0 "register_operand")
5085 (le:SI (match_dup 1)
5088 { if (mips_emit_scc (LE, operands[0])) DONE; else FAIL; })
5090 (define_insn "*sle_<mode>"
5091 [(set (match_operand:GPR 0 "register_operand" "=d")
5092 (le:GPR (match_operand:GPR 1 "register_operand" "d")
5093 (match_operand:GPR 2 "sle_operand" "")))]
5096 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5097 return "slt\t%0,%1,%2";
5099 [(set_attr "type" "slt")
5100 (set_attr "mode" "<MODE>")])
5102 (define_insn "*sle_<mode>_mips16"
5103 [(set (match_operand:GPR 0 "register_operand" "=t")
5104 (le:GPR (match_operand:GPR 1 "register_operand" "d")
5105 (match_operand:GPR 2 "sle_operand" "")))]
5108 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5109 return "slt\t%1,%2";
5111 [(set_attr "type" "slt")
5112 (set_attr "mode" "<MODE>")
5113 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
5117 (define_expand "sgtu"
5118 [(set (match_operand:SI 0 "register_operand")
5119 (gtu:SI (match_dup 1)
5122 { if (mips_emit_scc (GTU, operands[0])) DONE; else FAIL; })
5124 (define_insn "*sgtu_<mode>"
5125 [(set (match_operand:GPR 0 "register_operand" "=d")
5126 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
5127 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
5130 [(set_attr "type" "slt")
5131 (set_attr "mode" "<MODE>")])
5133 (define_insn "*sgtu_<mode>_mips16"
5134 [(set (match_operand:GPR 0 "register_operand" "=t")
5135 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
5136 (match_operand:GPR 2 "register_operand" "d")))]
5139 [(set_attr "type" "slt")
5140 (set_attr "mode" "<MODE>")])
5142 (define_expand "sgeu"
5143 [(set (match_operand:SI 0 "register_operand")
5144 (geu:SI (match_dup 1)
5147 { if (mips_emit_scc (GEU, operands[0])) DONE; else FAIL; })
5149 (define_insn "*sge_<mode>"
5150 [(set (match_operand:GPR 0 "register_operand" "=d")
5151 (geu:GPR (match_operand:GPR 1 "register_operand" "d")
5155 [(set_attr "type" "slt")
5156 (set_attr "mode" "<MODE>")])
5158 (define_expand "sltu"
5159 [(set (match_operand:SI 0 "register_operand")
5160 (ltu:SI (match_dup 1)
5163 { if (mips_emit_scc (LTU, operands[0])) DONE; else FAIL; })
5165 (define_insn "*sltu_<mode>"
5166 [(set (match_operand:GPR 0 "register_operand" "=d")
5167 (ltu:GPR (match_operand:GPR 1 "register_operand" "d")
5168 (match_operand:GPR 2 "arith_operand" "dI")))]
5171 [(set_attr "type" "slt")
5172 (set_attr "mode" "<MODE>")])
5174 (define_insn "*sltu_<mode>_mips16"
5175 [(set (match_operand:GPR 0 "register_operand" "=t,t")
5176 (ltu:GPR (match_operand:GPR 1 "register_operand" "d,d")
5177 (match_operand:GPR 2 "arith_operand" "d,I")))]
5180 [(set_attr "type" "slt")
5181 (set_attr "mode" "<MODE>")
5182 (set_attr_alternative "length"
5184 (if_then_else (match_operand 2 "m16_uimm8_1")
5188 (define_expand "sleu"
5189 [(set (match_operand:SI 0 "register_operand")
5190 (leu:SI (match_dup 1)
5193 { if (mips_emit_scc (LEU, operands[0])) DONE; else FAIL; })
5195 (define_insn "*sleu_<mode>"
5196 [(set (match_operand:GPR 0 "register_operand" "=d")
5197 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
5198 (match_operand:GPR 2 "sleu_operand" "")))]
5201 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5202 return "sltu\t%0,%1,%2";
5204 [(set_attr "type" "slt")
5205 (set_attr "mode" "<MODE>")])
5207 (define_insn "*sleu_<mode>_mips16"
5208 [(set (match_operand:GPR 0 "register_operand" "=t")
5209 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
5210 (match_operand:GPR 2 "sleu_operand" "")))]
5213 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5214 return "sltu\t%1,%2";
5216 [(set_attr "type" "slt")
5217 (set_attr "mode" "<MODE>")
5218 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
5223 ;; ....................
5225 ;; FLOATING POINT COMPARISONS
5227 ;; ....................
5229 (define_insn "s<code>_<mode>"
5230 [(set (match_operand:CC 0 "register_operand" "=z")
5231 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5232 (match_operand:SCALARF 2 "register_operand" "f")))]
5234 "c.<fcond>.<fmt>\t%Z0%1,%2"
5235 [(set_attr "type" "fcmp")
5236 (set_attr "mode" "FPSW")])
5238 (define_insn "s<code>_<mode>"
5239 [(set (match_operand:CC 0 "register_operand" "=z")
5240 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5241 (match_operand:SCALARF 2 "register_operand" "f")))]
5243 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
5244 [(set_attr "type" "fcmp")
5245 (set_attr "mode" "FPSW")])
5248 ;; ....................
5250 ;; UNCONDITIONAL BRANCHES
5252 ;; ....................
5254 ;; Unconditional branches.
5258 (label_ref (match_operand 0 "" "")))]
5263 if (get_attr_length (insn) <= 8)
5264 return "%*b\t%l0%/";
5267 output_asm_insn (mips_output_load_label (), operands);
5268 return "%*jr\t%@%/%]";
5272 return "%*j\t%l0%/";
5274 [(set_attr "type" "jump")
5275 (set_attr "mode" "none")
5276 (set (attr "length")
5277 ;; We can't use `j' when emitting PIC. Emit a branch if it's
5278 ;; in range, otherwise load the address of the branch target into
5279 ;; $at and then jump to it.
5281 (ior (eq (symbol_ref "flag_pic") (const_int 0))
5282 (lt (abs (minus (match_dup 0)
5283 (plus (pc) (const_int 4))))
5284 (const_int 131072)))
5285 (const_int 4) (const_int 16)))])
5287 ;; We need a different insn for the mips16, because a mips16 branch
5288 ;; does not have a delay slot.
5292 (label_ref (match_operand 0 "" "")))]
5295 [(set_attr "type" "branch")
5296 (set_attr "mode" "none")
5297 (set_attr "length" "8")])
5299 (define_expand "indirect_jump"
5300 [(set (pc) (match_operand 0 "register_operand"))]
5303 operands[0] = force_reg (Pmode, operands[0]);
5304 if (Pmode == SImode)
5305 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
5307 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
5311 (define_insn "indirect_jump<mode>"
5312 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
5315 [(set_attr "type" "jump")
5316 (set_attr "mode" "none")])
5318 (define_expand "tablejump"
5320 (match_operand 0 "register_operand"))
5321 (use (label_ref (match_operand 1 "")))]
5324 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
5325 operands[0] = expand_binop (Pmode, add_optab,
5326 convert_to_mode (Pmode, operands[0], false),
5327 gen_rtx_LABEL_REF (Pmode, operands[1]),
5329 else if (TARGET_GPWORD)
5330 operands[0] = expand_binop (Pmode, add_optab, operands[0],
5331 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
5332 else if (TARGET_RTP_PIC)
5334 /* When generating RTP PIC, we use case table entries that are relative
5335 to the start of the function. Add the function's address to the
5337 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5338 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
5339 start, 0, 0, OPTAB_WIDEN);
5342 if (Pmode == SImode)
5343 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
5345 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
5349 (define_insn "tablejump<mode>"
5351 (match_operand:P 0 "register_operand" "d"))
5352 (use (label_ref (match_operand 1 "" "")))]
5355 [(set_attr "type" "jump")
5356 (set_attr "mode" "none")])
5358 ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
5359 ;; While it is possible to either pull it off the stack (in the
5360 ;; o32 case) or recalculate it given t9 and our target label,
5361 ;; it takes 3 or 4 insns to do so.
5363 (define_expand "builtin_setjmp_setup"
5364 [(use (match_operand 0 "register_operand"))]
5369 addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
5370 mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
5374 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
5375 ;; that older code did recalculate the gp from $25. Continue to jump through
5376 ;; $25 for compatibility (we lose nothing by doing so).
5378 (define_expand "builtin_longjmp"
5379 [(use (match_operand 0 "register_operand"))]
5382 /* The elements of the buffer are, in order: */
5383 int W = GET_MODE_SIZE (Pmode);
5384 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5385 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
5386 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
5387 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
5388 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5389 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
5390 The target is bound to be using $28 as the global pointer
5391 but the current function might not be. */
5392 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
5394 /* This bit is similar to expand_builtin_longjmp except that it
5395 restores $gp as well. */
5396 mips_emit_move (hard_frame_pointer_rtx, fp);
5397 mips_emit_move (pv, lab);
5398 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5399 mips_emit_move (gp, gpv);
5400 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
5401 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
5402 emit_insn (gen_rtx_USE (VOIDmode, gp));
5403 emit_indirect_jump (pv);
5408 ;; ....................
5410 ;; Function prologue/epilogue
5412 ;; ....................
5415 (define_expand "prologue"
5419 mips_expand_prologue ();
5423 ;; Block any insns from being moved before this point, since the
5424 ;; profiling call to mcount can use various registers that aren't
5425 ;; saved or used to pass arguments.
5427 (define_insn "blockage"
5428 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
5431 [(set_attr "type" "unknown")
5432 (set_attr "mode" "none")
5433 (set_attr "length" "0")])
5435 (define_expand "epilogue"
5439 mips_expand_epilogue (false);
5443 (define_expand "sibcall_epilogue"
5447 mips_expand_epilogue (true);
5451 ;; Trivial return. Make it look like a normal return insn as that
5452 ;; allows jump optimizations to work better.
5454 (define_insn "return"
5456 "mips_can_use_return_insn ()"
5458 [(set_attr "type" "jump")
5459 (set_attr "mode" "none")])
5463 (define_insn "return_internal"
5465 (use (match_operand 0 "pmode_register_operand" ""))]
5468 [(set_attr "type" "jump")
5469 (set_attr "mode" "none")])
5471 ;; This is used in compiling the unwind routines.
5472 (define_expand "eh_return"
5473 [(use (match_operand 0 "general_operand"))]
5476 enum machine_mode gpr_mode = TARGET_64BIT ? DImode : SImode;
5478 if (GET_MODE (operands[0]) != gpr_mode)
5479 operands[0] = convert_to_mode (gpr_mode, operands[0], 0);
5481 emit_insn (gen_eh_set_lr_di (operands[0]));
5483 emit_insn (gen_eh_set_lr_si (operands[0]));
5488 ;; Clobber the return address on the stack. We can't expand this
5489 ;; until we know where it will be put in the stack frame.
5491 (define_insn "eh_set_lr_si"
5492 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5493 (clobber (match_scratch:SI 1 "=&d"))]
5497 (define_insn "eh_set_lr_di"
5498 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5499 (clobber (match_scratch:DI 1 "=&d"))]
5504 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
5505 (clobber (match_scratch 1))]
5506 "reload_completed && !TARGET_DEBUG_D_MODE"
5509 mips_set_return_address (operands[0], operands[1]);
5513 (define_insn_and_split "nonlocal_goto_receiver"
5515 (unspec_volatile:SI [(const_int 0)] UNSPEC_NONLOCAL_GOTO_RECEIVER))]
5516 "TARGET_CALL_CLOBBERED_GP"
5518 "&& reload_completed"
5524 [(set_attr "type" "load")
5525 (set_attr "length" "12")])
5528 ;; ....................
5532 ;; ....................
5534 ;; Instructions to load a call address from the GOT. The address might
5535 ;; point to a function or to a lazy binding stub. In the latter case,
5536 ;; the stub will use the dynamic linker to resolve the function, which
5537 ;; in turn will change the GOT entry to point to the function's real
5540 ;; This means that every call, even pure and constant ones, can
5541 ;; potentially modify the GOT entry. And once a stub has been called,
5542 ;; we must not call it again.
5544 ;; We represent this restriction using an imaginary fixed register that
5545 ;; acts like a GOT version number. By making the register call-clobbered,
5546 ;; we tell the target-independent code that the address could be changed
5547 ;; by any call insn.
5548 (define_insn "load_call<mode>"
5549 [(set (match_operand:P 0 "register_operand" "=d")
5550 (unspec:P [(match_operand:P 1 "register_operand" "r")
5551 (match_operand:P 2 "immediate_operand" "")
5552 (reg:P FAKE_CALL_REGNO)]
5555 "<load>\t%0,%R2(%1)"
5556 [(set_attr "type" "load")
5557 (set_attr "mode" "<MODE>")
5558 (set_attr "length" "4")])
5560 ;; Sibling calls. All these patterns use jump instructions.
5562 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
5563 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
5564 ;; is defined in terms of call_insn_operand, the same is true of the
5567 ;; When we use an indirect jump, we need a register that will be
5568 ;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
5569 ;; us to use $25 for this purpose -- and $25 is never clobbered by the
5570 ;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
5573 (define_expand "sibcall"
5574 [(parallel [(call (match_operand 0 "")
5575 (match_operand 1 ""))
5576 (use (match_operand 2 "")) ;; next_arg_reg
5577 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5580 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], true);
5584 (define_insn "sibcall_internal"
5585 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
5586 (match_operand 1 "" ""))]
5587 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5588 { return MIPS_CALL ("j", operands, 0); }
5589 [(set_attr "type" "call")])
5591 (define_expand "sibcall_value"
5592 [(parallel [(set (match_operand 0 "")
5593 (call (match_operand 1 "")
5594 (match_operand 2 "")))
5595 (use (match_operand 3 ""))])] ;; next_arg_reg
5598 mips_expand_call (operands[0], XEXP (operands[1], 0),
5599 operands[2], operands[3], true);
5603 (define_insn "sibcall_value_internal"
5604 [(set (match_operand 0 "register_operand" "")
5605 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5606 (match_operand 2 "" "")))]
5607 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5608 { return MIPS_CALL ("j", operands, 1); }
5609 [(set_attr "type" "call")])
5611 (define_insn "sibcall_value_multiple_internal"
5612 [(set (match_operand 0 "register_operand" "")
5613 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5614 (match_operand 2 "" "")))
5615 (set (match_operand 3 "register_operand" "")
5616 (call (mem:SI (match_dup 1))
5618 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5619 { return MIPS_CALL ("j", operands, 1); }
5620 [(set_attr "type" "call")])
5622 (define_expand "call"
5623 [(parallel [(call (match_operand 0 "")
5624 (match_operand 1 ""))
5625 (use (match_operand 2 "")) ;; next_arg_reg
5626 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5629 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], false);
5633 ;; This instruction directly corresponds to an assembly-language "jal".
5634 ;; There are four cases:
5637 ;; Both symbolic and register destinations are OK. The pattern
5638 ;; always expands to a single mips instruction.
5640 ;; - -mabicalls/-mno-explicit-relocs:
5641 ;; Again, both symbolic and register destinations are OK.
5642 ;; The call is treated as a multi-instruction black box.
5644 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
5645 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
5648 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
5649 ;; Only "jal $25" is allowed. The call is actually two instructions:
5650 ;; "jalr $25" followed by an insn to reload $gp.
5652 ;; In the last case, we can generate the individual instructions with
5653 ;; a define_split. There are several things to be wary of:
5655 ;; - We can't expose the load of $gp before reload. If we did,
5656 ;; it might get removed as dead, but reload can introduce new
5657 ;; uses of $gp by rematerializing constants.
5659 ;; - We shouldn't restore $gp after calls that never return.
5660 ;; It isn't valid to insert instructions between a noreturn
5661 ;; call and the following barrier.
5663 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
5664 ;; instruction preserves $gp and so have no effect on its liveness.
5665 ;; But once we generate the separate insns, it becomes obvious that
5666 ;; $gp is not live on entry to the call.
5668 ;; ??? The operands[2] = insn check is a hack to make the original insn
5669 ;; available to the splitter.
5670 (define_insn_and_split "call_internal"
5671 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
5672 (match_operand 1 "" ""))
5673 (clobber (reg:SI 31))]
5675 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
5676 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
5679 emit_call_insn (gen_call_split (operands[0], operands[1]));
5680 if (!find_reg_note (operands[2], REG_NORETURN, 0))
5684 [(set_attr "jal" "indirect,direct")
5685 (set_attr "extended_mips16" "no,yes")])
5687 ;; A pattern for calls that must be made directly. It is used for
5688 ;; MIPS16 calls that the linker may need to redirect to a hard-float
5689 ;; stub; the linker relies on the call relocation type to detect when
5690 ;; such redirection is needed.
5691 (define_insn "call_internal_direct"
5692 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
5695 (clobber (reg:SI 31))]
5697 { return MIPS_CALL ("jal", operands, 0); })
5699 (define_insn "call_split"
5700 [(call (mem:SI (match_operand 0 "call_insn_operand" "cS"))
5701 (match_operand 1 "" ""))
5702 (clobber (reg:SI 31))
5703 (clobber (reg:SI 28))]
5704 "TARGET_SPLIT_CALLS"
5705 { return MIPS_CALL ("jal", operands, 0); }
5706 [(set_attr "type" "call")])
5708 (define_expand "call_value"
5709 [(parallel [(set (match_operand 0 "")
5710 (call (match_operand 1 "")
5711 (match_operand 2 "")))
5712 (use (match_operand 3 ""))])] ;; next_arg_reg
5715 mips_expand_call (operands[0], XEXP (operands[1], 0),
5716 operands[2], operands[3], false);
5720 ;; See comment for call_internal.
5721 (define_insn_and_split "call_value_internal"
5722 [(set (match_operand 0 "register_operand" "")
5723 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5724 (match_operand 2 "" "")))
5725 (clobber (reg:SI 31))]
5727 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
5728 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
5731 emit_call_insn (gen_call_value_split (operands[0], operands[1],
5733 if (!find_reg_note (operands[3], REG_NORETURN, 0))
5737 [(set_attr "jal" "indirect,direct")
5738 (set_attr "extended_mips16" "no,yes")])
5740 (define_insn "call_value_split"
5741 [(set (match_operand 0 "register_operand" "")
5742 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
5743 (match_operand 2 "" "")))
5744 (clobber (reg:SI 31))
5745 (clobber (reg:SI 28))]
5746 "TARGET_SPLIT_CALLS"
5747 { return MIPS_CALL ("jal", operands, 1); }
5748 [(set_attr "type" "call")])
5750 ;; See call_internal_direct.
5751 (define_insn "call_value_internal_direct"
5752 [(set (match_operand 0 "register_operand")
5753 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
5756 (clobber (reg:SI 31))]
5758 { return MIPS_CALL ("jal", operands, 1); })
5760 ;; See comment for call_internal.
5761 (define_insn_and_split "call_value_multiple_internal"
5762 [(set (match_operand 0 "register_operand" "")
5763 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5764 (match_operand 2 "" "")))
5765 (set (match_operand 3 "register_operand" "")
5766 (call (mem:SI (match_dup 1))
5768 (clobber (reg:SI 31))]
5770 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
5771 "reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
5774 emit_call_insn (gen_call_value_multiple_split (operands[0], operands[1],
5775 operands[2], operands[3]));
5776 if (!find_reg_note (operands[4], REG_NORETURN, 0))
5780 [(set_attr "jal" "indirect,direct")
5781 (set_attr "extended_mips16" "no,yes")])
5783 (define_insn "call_value_multiple_split"
5784 [(set (match_operand 0 "register_operand" "")
5785 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
5786 (match_operand 2 "" "")))
5787 (set (match_operand 3 "register_operand" "")
5788 (call (mem:SI (match_dup 1))
5790 (clobber (reg:SI 31))
5791 (clobber (reg:SI 28))]
5792 "TARGET_SPLIT_CALLS"
5793 { return MIPS_CALL ("jal", operands, 1); }
5794 [(set_attr "type" "call")])
5796 ;; Call subroutine returning any type.
5798 (define_expand "untyped_call"
5799 [(parallel [(call (match_operand 0 "")
5801 (match_operand 1 "")
5802 (match_operand 2 "")])]
5807 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
5809 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5811 rtx set = XVECEXP (operands[2], 0, i);
5812 mips_emit_move (SET_DEST (set), SET_SRC (set));
5815 emit_insn (gen_blockage ());
5820 ;; ....................
5824 ;; ....................
5828 (define_insn "prefetch"
5829 [(prefetch (match_operand:QI 0 "address_operand" "p")
5830 (match_operand 1 "const_int_operand" "n")
5831 (match_operand 2 "const_int_operand" "n"))]
5832 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
5834 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
5835 return "pref\t%1,%a0";
5837 [(set_attr "type" "prefetch")])
5839 (define_insn "*prefetch_indexed_<mode>"
5840 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
5841 (match_operand:P 1 "register_operand" "d"))
5842 (match_operand 2 "const_int_operand" "n")
5843 (match_operand 3 "const_int_operand" "n"))]
5844 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
5846 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
5847 return "prefx\t%2,%1(%0)";
5849 [(set_attr "type" "prefetchx")])
5855 [(set_attr "type" "nop")
5856 (set_attr "mode" "none")])
5858 ;; Like nop, but commented out when outside a .set noreorder block.
5859 (define_insn "hazard_nop"
5868 [(set_attr "type" "nop")])
5870 ;; MIPS4 Conditional move instructions.
5872 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
5873 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5875 (match_operator:MOVECC 4 "equality_operator"
5876 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
5878 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
5879 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
5884 [(set_attr "type" "condmove")
5885 (set_attr "mode" "<GPR:MODE>")])
5887 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
5888 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
5889 (if_then_else:SCALARF
5890 (match_operator:MOVECC 4 "equality_operator"
5891 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
5893 (match_operand:SCALARF 2 "register_operand" "f,0")
5894 (match_operand:SCALARF 3 "register_operand" "0,f")))]
5897 mov%T4.<fmt>\t%0,%2,%1
5898 mov%t4.<fmt>\t%0,%3,%1"
5899 [(set_attr "type" "condmove")
5900 (set_attr "mode" "<SCALARF:MODE>")])
5902 ;; These are the main define_expand's used to make conditional moves.
5904 (define_expand "mov<mode>cc"
5905 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
5906 (set (match_operand:GPR 0 "register_operand")
5907 (if_then_else:GPR (match_dup 5)
5908 (match_operand:GPR 2 "reg_or_0_operand")
5909 (match_operand:GPR 3 "reg_or_0_operand")))]
5912 gen_conditional_move (operands);
5916 (define_expand "mov<mode>cc"
5917 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
5918 (set (match_operand:SCALARF 0 "register_operand")
5919 (if_then_else:SCALARF (match_dup 5)
5920 (match_operand:SCALARF 2 "register_operand")
5921 (match_operand:SCALARF 3 "register_operand")))]
5924 gen_conditional_move (operands);
5929 ;; ....................
5931 ;; mips16 inline constant tables
5933 ;; ....................
5936 (define_insn "consttable_int"
5937 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
5938 (match_operand 1 "const_int_operand" "")]
5939 UNSPEC_CONSTTABLE_INT)]
5942 assemble_integer (operands[0], INTVAL (operands[1]),
5943 BITS_PER_UNIT * INTVAL (operands[1]), 1);
5946 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
5948 (define_insn "consttable_float"
5949 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
5950 UNSPEC_CONSTTABLE_FLOAT)]
5955 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
5956 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
5957 assemble_real (d, GET_MODE (operands[0]),
5958 GET_MODE_BITSIZE (GET_MODE (operands[0])));
5961 [(set (attr "length")
5962 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
5964 (define_insn "align"
5965 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
5968 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
5971 [(match_operand 0 "small_data_pattern")]
5974 { operands[0] = mips_rewrite_small_data (operands[0]); })
5977 ;; ....................
5979 ;; MIPS16e Save/Restore
5981 ;; ....................
5984 (define_insn "*mips16e_save_restore"
5985 [(match_parallel 0 ""
5986 [(set (match_operand:SI 1 "register_operand")
5987 (plus:SI (match_dup 1)
5988 (match_operand:SI 2 "const_int_operand")))])]
5989 "operands[1] == stack_pointer_rtx
5990 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)"
5991 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); }
5992 [(set_attr "type" "arith")
5993 (set_attr "extended_mips16" "yes")])
5995 ; Thread-Local Storage
5997 ; The TLS base pointer is accessed via "rdhwr $v1, $29". No current
5998 ; MIPS architecture defines this register, and no current
5999 ; implementation provides it; instead, any OS which supports TLS is
6000 ; expected to trap and emulate this instruction. rdhwr is part of the
6001 ; MIPS 32r2 specification, but we use it on any architecture because
6002 ; we expect it to be emulated. Use .set to force the assembler to
6005 (define_insn "tls_get_tp_<mode>"
6006 [(set (match_operand:P 0 "register_operand" "=v")
6007 (unspec:P [(const_int 0)]
6008 UNSPEC_TLS_GET_TP))]
6009 "HAVE_AS_TLS && !TARGET_MIPS16"
6010 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t%0,$29\;.set\tpop"
6011 [(set_attr "type" "unknown")
6012 ; Since rdhwr always generates a trap for now, putting it in a delay
6013 ; slot would make the kernel's emulation of it much slower.
6014 (set_attr "can_delay" "no")
6015 (set_attr "mode" "<MODE>")])
6017 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
6019 (include "mips-ps-3d.md")
6021 ; The MIPS DSP Instructions.
6023 (include "mips-dsp.md")
6025 ; The MIPS DSP REV 2 Instructions.
6027 (include "mips-dspr2.md")
6029 ; MIPS fixed-point instructions.
6030 (include "mips-fixed.md")