| blob | 0dc4d34dda7e627185fa3bf5d14e3ee8a42f919c |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990-2012 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;;
24 ;; REGNOS
25 ;;
27 (define_constants
28 [(STACK_POINTER_REGNUM 1)
29 (TOC_REGNUM 2)
30 (STATIC_CHAIN_REGNUM 11)
31 (HARD_FRAME_POINTER_REGNUM 31)
32 (MQ_REGNO 64)
33 (LR_REGNO 65)
34 (CTR_REGNO 66)
35 (ARG_POINTER_REGNUM 67)
36 (CR0_REGNO 68)
37 (CR1_REGNO 69)
38 (CR2_REGNO 70)
39 (CR3_REGNO 71)
40 (CR4_REGNO 72)
41 (CR5_REGNO 73)
42 (CR6_REGNO 74)
43 (CR7_REGNO 75)
44 (MAX_CR_REGNO 75)
45 (CA_REGNO 76)
46 (FIRST_ALTIVEC_REGNO 77)
47 (LAST_ALTIVEC_REGNO 108)
48 (VRSAVE_REGNO 109)
49 (VSCR_REGNO 110)
50 (SPE_ACC_REGNO 111)
51 (SPEFSCR_REGNO 112)
52 (FRAME_POINTER_REGNUM 113)
54 ; ABI defined stack offsets for storing the TOC pointer with AIX calls.
55 (TOC_SAVE_OFFSET_32BIT 20)
56 (TOC_SAVE_OFFSET_64BIT 40)
58 ; Function TOC offset in the AIX function descriptor.
59 (AIX_FUNC_DESC_TOC_32BIT 4)
60 (AIX_FUNC_DESC_TOC_64BIT 8)
62 ; Static chain offset in the AIX function descriptor.
63 (AIX_FUNC_DESC_SC_32BIT 8)
64 (AIX_FUNC_DESC_SC_64BIT 16)
65 ])
67 ;;
68 ;; UNSPEC usage
69 ;;
71 (define_c_enum "unspec"
72 [UNSPEC_FRSP ; frsp for POWER machines
73 UNSPEC_PROBE_STACK ; probe stack memory reference
74 UNSPEC_TOCPTR ; address of a word pointing to the TOC
75 UNSPEC_TOC ; address of the TOC (more-or-less)
76 UNSPEC_MOVSI_GOT
77 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
78 UNSPEC_FCTIWZ
79 UNSPEC_FRIM
80 UNSPEC_FRIN
81 UNSPEC_FRIP
82 UNSPEC_FRIZ
83 UNSPEC_LD_MPIC ; load_macho_picbase
84 UNSPEC_MPIC_CORRECT ; macho_correct_pic
85 UNSPEC_TLSGD
86 UNSPEC_TLSLD
87 UNSPEC_MOVESI_FROM_CR
88 UNSPEC_MOVESI_TO_CR
89 UNSPEC_TLSDTPREL
90 UNSPEC_TLSDTPRELHA
91 UNSPEC_TLSDTPRELLO
92 UNSPEC_TLSGOTDTPREL
93 UNSPEC_TLSTPREL
94 UNSPEC_TLSTPRELHA
95 UNSPEC_TLSTPRELLO
96 UNSPEC_TLSGOTTPREL
97 UNSPEC_TLSTLS
98 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
99 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
100 UNSPEC_STFIWX
101 UNSPEC_POPCNTB
102 UNSPEC_FRES
103 UNSPEC_SP_SET
104 UNSPEC_SP_TEST
105 UNSPEC_SYNC
106 UNSPEC_LWSYNC
107 UNSPEC_SYNC_OP
108 UNSPEC_ATOMIC
109 UNSPEC_CMPXCHG
110 UNSPEC_XCHG
111 UNSPEC_AND
112 UNSPEC_DLMZB
113 UNSPEC_DLMZB_CR
114 UNSPEC_DLMZB_STRLEN
115 UNSPEC_RSQRT
116 UNSPEC_TOCREL
117 UNSPEC_MACHOPIC_OFFSET
118 UNSPEC_BPERM
119 UNSPEC_COPYSIGN
120 UNSPEC_PARITY
121 UNSPEC_FCTIW
122 UNSPEC_FCTID
123 UNSPEC_LFIWAX
124 UNSPEC_LFIWZX
125 UNSPEC_FCTIWUZ
126 UNSPEC_GRP_END_NOP
127 ])
129 ;;
130 ;; UNSPEC_VOLATILE usage
131 ;;
133 (define_c_enum "unspecv"
134 [UNSPECV_BLOCK
135 UNSPECV_LL ; load-locked
136 UNSPECV_SC ; store-conditional
137 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
138 UNSPECV_EH_RR ; eh_reg_restore
139 UNSPECV_ISYNC ; isync instruction
140 ])
142 \f
143 ;; Define an insn type attribute. This is used in function unit delay
144 ;; computations.
145 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt"
146 (const_string "integer"))
148 ;; Define floating point instruction sub-types for use with Xfpu.md
149 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
151 ;; Length (in bytes).
152 ; '(pc)' in the following doesn't include the instruction itself; it is
153 ; calculated as if the instruction had zero size.
154 (define_attr "length" ""
155 (if_then_else (eq_attr "type" "branch")
156 (if_then_else (and (ge (minus (match_dup 0) (pc))
157 (const_int -32768))
158 (lt (minus (match_dup 0) (pc))
159 (const_int 32764)))
160 (const_int 4)
161 (const_int 8))
162 (const_int 4)))
164 ;; Processor type -- this attribute must exactly match the processor_type
165 ;; enumeration in rs6000.h.
167 (define_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,power4,power5,power6,power7,cell,ppca2,titan"
168 (const (symbol_ref "rs6000_cpu_attr")))
171 ;; If this instruction is microcoded on the CELL processor
172 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
173 (define_attr "cell_micro" "not,conditional,always"
174 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
175 (const_string "always")
176 (const_string "not")))
178 (automata_option "ndfa")
180 (include "rs64.md")
181 (include "mpc.md")
182 (include "40x.md")
183 (include "440.md")
184 (include "476.md")
185 (include "601.md")
186 (include "603.md")
187 (include "6xx.md")
188 (include "7xx.md")
189 (include "7450.md")
190 (include "8540.md")
191 (include "e300c2c3.md")
192 (include "e500mc.md")
193 (include "e500mc64.md")
194 (include "e5500.md")
195 (include "e6500.md")
196 (include "power4.md")
197 (include "power5.md")
198 (include "power6.md")
199 (include "power7.md")
200 (include "cell.md")
201 (include "xfpu.md")
202 (include "a2.md")
203 (include "titan.md")
205 (include "predicates.md")
206 (include "constraints.md")
208 (include "darwin.md")
210 \f
211 ;; Mode iterators
213 ; This mode iterator allows :GPR to be used to indicate the allowable size
214 ; of whole values in GPRs.
215 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
217 ; Any supported integer mode.
218 (define_mode_iterator INT [QI HI SI DI TI])
220 ; Any supported integer mode that fits in one register.
221 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
223 ; extend modes for DImode
224 (define_mode_iterator QHSI [QI HI SI])
226 ; SImode or DImode, even if DImode doesn't fit in GPRs.
227 (define_mode_iterator SDI [SI DI])
229 ; The size of a pointer. Also, the size of the value that a record-condition
230 ; (one with a '.') will compare; and the size used for arithmetic carries.
231 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
233 ; Any hardware-supported floating-point mode
234 (define_mode_iterator FP [
235 (SF "TARGET_HARD_FLOAT
236 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
237 (DF "TARGET_HARD_FLOAT
238 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
239 (TF "!TARGET_IEEEQUAD
240 && TARGET_HARD_FLOAT
241 && (TARGET_FPRS || TARGET_E500_DOUBLE)
242 && TARGET_LONG_DOUBLE_128")
243 (DD "TARGET_DFP")
244 (TD "TARGET_DFP")])
246 ; Any fma capable floating-point mode.
247 (define_mode_iterator FMA_F [
248 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
249 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
250 || VECTOR_UNIT_VSX_P (DFmode)")
251 (V2SF "TARGET_PAIRED_FLOAT")
252 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
253 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
254 ])
256 ; These modes do not fit in integer registers in 32-bit mode.
257 ; but on e500v2, the gpr are 64 bit registers
258 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
260 ; Iterator for reciprocal estimate instructions
261 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
263 ; Iterator for just SF/DF
264 (define_mode_iterator SFDF [SF DF])
266 ; Conditional returns.
267 (define_code_iterator any_return [return simple_return])
268 (define_code_attr return_pred [(return "direct_return ()")
269 (simple_return "")])
270 (define_code_attr return_str [(return "") (simple_return "simple_")])
272 ; Various instructions that come in SI and DI forms.
273 ; A generic w/d attribute, for things like cmpw/cmpd.
274 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
276 ; DImode bits
277 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
279 ;; ISEL/ISEL64 target selection
280 (define_mode_attr sel [(SI "") (DI "64")])
282 ;; Suffix for reload patterns
283 (define_mode_attr ptrsize [(SI "32bit")
284 (DI "64bit")])
286 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
287 (DI "TARGET_64BIT")])
289 (define_mode_attr mptrsize [(SI "si")
290 (DI "di")])
292 (define_mode_attr ptrload [(SI "{l|lwz}")
293 (DI "ld")])
295 (define_mode_attr rreg [(SF "f")
296 (DF "ws")
297 (V4SF "wf")
298 (V2DF "wd")])
300 (define_mode_attr rreg2 [(SF "f")
301 (DF "d")])
303 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
304 (DF "TARGET_FCFID")])
306 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
307 (DF "TARGET_E500_DOUBLE")])
309 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
310 (DF "TARGET_DOUBLE_FLOAT")])
311 \f
312 ;; Start with fixed-point load and store insns. Here we put only the more
313 ;; complex forms. Basic data transfer is done later.
315 (define_expand "zero_extend<mode>di2"
316 [(set (match_operand:DI 0 "gpc_reg_operand" "")
317 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
318 "TARGET_POWERPC64"
319 "")
321 (define_insn "*zero_extend<mode>di2_internal1"
322 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
323 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
324 "TARGET_POWERPC64"
325 "@
326 l<wd>z%U1%X1 %0,%1
327 rldicl %0,%1,0,<dbits>"
328 [(set_attr "type" "load,*")])
330 (define_insn "*zero_extend<mode>di2_internal2"
331 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
332 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
333 (const_int 0)))
334 (clobber (match_scratch:DI 2 "=r,r"))]
335 "TARGET_64BIT"
336 "@
337 rldicl. %2,%1,0,<dbits>
338 #"
339 [(set_attr "type" "compare")
340 (set_attr "length" "4,8")])
342 (define_split
343 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
344 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
345 (const_int 0)))
346 (clobber (match_scratch:DI 2 ""))]
347 "TARGET_POWERPC64 && reload_completed"
348 [(set (match_dup 2)
349 (zero_extend:DI (match_dup 1)))
350 (set (match_dup 0)
351 (compare:CC (match_dup 2)
352 (const_int 0)))]
353 "")
355 (define_insn "*zero_extend<mode>di2_internal3"
356 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
357 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
358 (const_int 0)))
359 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
360 (zero_extend:DI (match_dup 1)))]
361 "TARGET_64BIT"
362 "@
363 rldicl. %0,%1,0,<dbits>
364 #"
365 [(set_attr "type" "compare")
366 (set_attr "length" "4,8")])
368 (define_split
369 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
370 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
371 (const_int 0)))
372 (set (match_operand:DI 0 "gpc_reg_operand" "")
373 (zero_extend:DI (match_dup 1)))]
374 "TARGET_POWERPC64 && reload_completed"
375 [(set (match_dup 0)
376 (zero_extend:DI (match_dup 1)))
377 (set (match_dup 2)
378 (compare:CC (match_dup 0)
379 (const_int 0)))]
380 "")
382 (define_insn "extendqidi2"
383 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
384 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
385 "TARGET_POWERPC64"
386 "extsb %0,%1"
387 [(set_attr "type" "exts")])
389 (define_insn ""
390 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
391 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
392 (const_int 0)))
393 (clobber (match_scratch:DI 2 "=r,r"))]
394 "TARGET_64BIT"
395 "@
396 extsb. %2,%1
397 #"
398 [(set_attr "type" "compare")
399 (set_attr "length" "4,8")])
401 (define_split
402 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
403 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
404 (const_int 0)))
405 (clobber (match_scratch:DI 2 ""))]
406 "TARGET_POWERPC64 && reload_completed"
407 [(set (match_dup 2)
408 (sign_extend:DI (match_dup 1)))
409 (set (match_dup 0)
410 (compare:CC (match_dup 2)
411 (const_int 0)))]
412 "")
414 (define_insn ""
415 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
416 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
417 (const_int 0)))
418 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
419 (sign_extend:DI (match_dup 1)))]
420 "TARGET_64BIT"
421 "@
422 extsb. %0,%1
423 #"
424 [(set_attr "type" "compare")
425 (set_attr "length" "4,8")])
427 (define_split
428 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
429 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
430 (const_int 0)))
431 (set (match_operand:DI 0 "gpc_reg_operand" "")
432 (sign_extend:DI (match_dup 1)))]
433 "TARGET_POWERPC64 && reload_completed"
434 [(set (match_dup 0)
435 (sign_extend:DI (match_dup 1)))
436 (set (match_dup 2)
437 (compare:CC (match_dup 0)
438 (const_int 0)))]
439 "")
441 (define_expand "extendhidi2"
442 [(set (match_operand:DI 0 "gpc_reg_operand" "")
443 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
444 "TARGET_POWERPC64"
445 "")
447 (define_insn ""
448 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
449 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
450 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
451 "@
452 lha%U1%X1 %0,%1
453 extsh %0,%1"
454 [(set_attr "type" "load_ext,exts")])
456 (define_insn ""
457 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
458 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
459 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
460 "extsh %0,%1"
461 [(set_attr "type" "exts")])
463 (define_insn ""
464 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
465 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
466 (const_int 0)))
467 (clobber (match_scratch:DI 2 "=r,r"))]
468 "TARGET_64BIT"
469 "@
470 extsh. %2,%1
471 #"
472 [(set_attr "type" "compare")
473 (set_attr "length" "4,8")])
475 (define_split
476 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
477 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
478 (const_int 0)))
479 (clobber (match_scratch:DI 2 ""))]
480 "TARGET_POWERPC64 && reload_completed"
481 [(set (match_dup 2)
482 (sign_extend:DI (match_dup 1)))
483 (set (match_dup 0)
484 (compare:CC (match_dup 2)
485 (const_int 0)))]
486 "")
488 (define_insn ""
489 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
490 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
491 (const_int 0)))
492 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
493 (sign_extend:DI (match_dup 1)))]
494 "TARGET_64BIT"
495 "@
496 extsh. %0,%1
497 #"
498 [(set_attr "type" "compare")
499 (set_attr "length" "4,8")])
501 (define_split
502 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
503 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
504 (const_int 0)))
505 (set (match_operand:DI 0 "gpc_reg_operand" "")
506 (sign_extend:DI (match_dup 1)))]
507 "TARGET_POWERPC64 && reload_completed"
508 [(set (match_dup 0)
509 (sign_extend:DI (match_dup 1)))
510 (set (match_dup 2)
511 (compare:CC (match_dup 0)
512 (const_int 0)))]
513 "")
515 (define_expand "extendsidi2"
516 [(set (match_operand:DI 0 "gpc_reg_operand" "")
517 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
518 "TARGET_POWERPC64"
519 "")
521 (define_insn ""
522 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
523 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
524 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
525 "@
526 lwa%U1%X1 %0,%1
527 extsw %0,%1"
528 [(set_attr "type" "load_ext,exts")])
530 (define_insn ""
531 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
532 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
533 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
534 "extsw %0,%1"
535 [(set_attr "type" "exts")])
537 (define_insn ""
538 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
539 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
540 (const_int 0)))
541 (clobber (match_scratch:DI 2 "=r,r"))]
542 "TARGET_64BIT"
543 "@
544 extsw. %2,%1
545 #"
546 [(set_attr "type" "compare")
547 (set_attr "length" "4,8")])
549 (define_split
550 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
551 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
552 (const_int 0)))
553 (clobber (match_scratch:DI 2 ""))]
554 "TARGET_POWERPC64 && reload_completed"
555 [(set (match_dup 2)
556 (sign_extend:DI (match_dup 1)))
557 (set (match_dup 0)
558 (compare:CC (match_dup 2)
559 (const_int 0)))]
560 "")
562 (define_insn ""
563 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
564 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
565 (const_int 0)))
566 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
567 (sign_extend:DI (match_dup 1)))]
568 "TARGET_64BIT"
569 "@
570 extsw. %0,%1
571 #"
572 [(set_attr "type" "compare")
573 (set_attr "length" "4,8")])
575 (define_split
576 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
577 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
578 (const_int 0)))
579 (set (match_operand:DI 0 "gpc_reg_operand" "")
580 (sign_extend:DI (match_dup 1)))]
581 "TARGET_POWERPC64 && reload_completed"
582 [(set (match_dup 0)
583 (sign_extend:DI (match_dup 1)))
584 (set (match_dup 2)
585 (compare:CC (match_dup 0)
586 (const_int 0)))]
587 "")
589 (define_expand "zero_extendqisi2"
590 [(set (match_operand:SI 0 "gpc_reg_operand" "")
591 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
592 ""
593 "")
595 (define_insn ""
596 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
597 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
598 ""
599 "@
600 lbz%U1%X1 %0,%1
601 {rlinm|rlwinm} %0,%1,0,0xff"
602 [(set_attr "type" "load,*")])
604 (define_insn ""
605 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
606 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
607 (const_int 0)))
608 (clobber (match_scratch:SI 2 "=r,r"))]
609 ""
610 "@
611 {andil.|andi.} %2,%1,0xff
612 #"
613 [(set_attr "type" "fast_compare,compare")
614 (set_attr "length" "4,8")])
616 (define_split
617 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
618 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
619 (const_int 0)))
620 (clobber (match_scratch:SI 2 ""))]
621 "reload_completed"
622 [(set (match_dup 2)
623 (zero_extend:SI (match_dup 1)))
624 (set (match_dup 0)
625 (compare:CC (match_dup 2)
626 (const_int 0)))]
627 "")
629 (define_insn ""
630 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
631 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
632 (const_int 0)))
633 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
634 (zero_extend:SI (match_dup 1)))]
635 ""
636 "@
637 {andil.|andi.} %0,%1,0xff
638 #"
639 [(set_attr "type" "fast_compare,compare")
640 (set_attr "length" "4,8")])
642 (define_split
643 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
644 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
645 (const_int 0)))
646 (set (match_operand:SI 0 "gpc_reg_operand" "")
647 (zero_extend:SI (match_dup 1)))]
648 "reload_completed"
649 [(set (match_dup 0)
650 (zero_extend:SI (match_dup 1)))
651 (set (match_dup 2)
652 (compare:CC (match_dup 0)
653 (const_int 0)))]
654 "")
656 (define_expand "extendqisi2"
657 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
658 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
659 ""
660 "
661 {
662 if (TARGET_POWERPC)
663 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
664 else if (TARGET_POWER)
665 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
666 else
667 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
668 DONE;
669 }")
671 (define_insn "extendqisi2_ppc"
672 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
673 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
674 "TARGET_POWERPC"
675 "extsb %0,%1"
676 [(set_attr "type" "exts")])
678 (define_insn ""
679 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
680 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
681 (const_int 0)))
682 (clobber (match_scratch:SI 2 "=r,r"))]
683 "TARGET_POWERPC"
684 "@
685 extsb. %2,%1
686 #"
687 [(set_attr "type" "compare")
688 (set_attr "length" "4,8")])
690 (define_split
691 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
692 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
693 (const_int 0)))
694 (clobber (match_scratch:SI 2 ""))]
695 "TARGET_POWERPC && reload_completed"
696 [(set (match_dup 2)
697 (sign_extend:SI (match_dup 1)))
698 (set (match_dup 0)
699 (compare:CC (match_dup 2)
700 (const_int 0)))]
701 "")
703 (define_insn ""
704 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
705 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
706 (const_int 0)))
707 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
708 (sign_extend:SI (match_dup 1)))]
709 "TARGET_POWERPC"
710 "@
711 extsb. %0,%1
712 #"
713 [(set_attr "type" "compare")
714 (set_attr "length" "4,8")])
716 (define_split
717 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
718 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
719 (const_int 0)))
720 (set (match_operand:SI 0 "gpc_reg_operand" "")
721 (sign_extend:SI (match_dup 1)))]
722 "TARGET_POWERPC && reload_completed"
723 [(set (match_dup 0)
724 (sign_extend:SI (match_dup 1)))
725 (set (match_dup 2)
726 (compare:CC (match_dup 0)
727 (const_int 0)))]
728 "")
730 (define_expand "extendqisi2_power"
731 [(parallel [(set (match_dup 2)
732 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
733 (const_int 24)))
734 (clobber (scratch:SI))])
735 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
736 (ashiftrt:SI (match_dup 2)
737 (const_int 24)))
738 (clobber (scratch:SI))])]
739 "TARGET_POWER"
740 "
741 { operands[1] = gen_lowpart (SImode, operands[1]);
742 operands[2] = gen_reg_rtx (SImode); }")
744 (define_expand "extendqisi2_no_power"
745 [(set (match_dup 2)
746 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
747 (const_int 24)))
748 (set (match_operand:SI 0 "gpc_reg_operand" "")
749 (ashiftrt:SI (match_dup 2)
750 (const_int 24)))]
751 "! TARGET_POWER && ! TARGET_POWERPC"
752 "
753 { operands[1] = gen_lowpart (SImode, operands[1]);
754 operands[2] = gen_reg_rtx (SImode); }")
756 (define_expand "zero_extendqihi2"
757 [(set (match_operand:HI 0 "gpc_reg_operand" "")
758 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
759 ""
760 "")
762 (define_insn ""
763 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
764 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
765 ""
766 "@
767 lbz%U1%X1 %0,%1
768 {rlinm|rlwinm} %0,%1,0,0xff"
769 [(set_attr "type" "load,*")])
771 (define_insn ""
772 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
773 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
774 (const_int 0)))
775 (clobber (match_scratch:HI 2 "=r,r"))]
776 ""
777 "@
778 {andil.|andi.} %2,%1,0xff
779 #"
780 [(set_attr "type" "fast_compare,compare")
781 (set_attr "length" "4,8")])
783 (define_split
784 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
785 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
786 (const_int 0)))
787 (clobber (match_scratch:HI 2 ""))]
788 "reload_completed"
789 [(set (match_dup 2)
790 (zero_extend:HI (match_dup 1)))
791 (set (match_dup 0)
792 (compare:CC (match_dup 2)
793 (const_int 0)))]
794 "")
796 (define_insn ""
797 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
798 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
799 (const_int 0)))
800 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
801 (zero_extend:HI (match_dup 1)))]
802 ""
803 "@
804 {andil.|andi.} %0,%1,0xff
805 #"
806 [(set_attr "type" "fast_compare,compare")
807 (set_attr "length" "4,8")])
809 (define_split
810 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
811 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
812 (const_int 0)))
813 (set (match_operand:HI 0 "gpc_reg_operand" "")
814 (zero_extend:HI (match_dup 1)))]
815 "reload_completed"
816 [(set (match_dup 0)
817 (zero_extend:HI (match_dup 1)))
818 (set (match_dup 2)
819 (compare:CC (match_dup 0)
820 (const_int 0)))]
821 "")
823 (define_expand "extendqihi2"
824 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
825 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
826 ""
827 "
828 {
829 if (TARGET_POWERPC)
830 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
831 else if (TARGET_POWER)
832 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
833 else
834 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
835 DONE;
836 }")
838 (define_insn "extendqihi2_ppc"
839 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
840 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
841 "TARGET_POWERPC"
842 "extsb %0,%1"
843 [(set_attr "type" "exts")])
845 (define_insn ""
846 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
847 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
848 (const_int 0)))
849 (clobber (match_scratch:HI 2 "=r,r"))]
850 "TARGET_POWERPC"
851 "@
852 extsb. %2,%1
853 #"
854 [(set_attr "type" "compare")
855 (set_attr "length" "4,8")])
857 (define_split
858 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
859 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
860 (const_int 0)))
861 (clobber (match_scratch:HI 2 ""))]
862 "TARGET_POWERPC && reload_completed"
863 [(set (match_dup 2)
864 (sign_extend:HI (match_dup 1)))
865 (set (match_dup 0)
866 (compare:CC (match_dup 2)
867 (const_int 0)))]
868 "")
870 (define_insn ""
871 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
872 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
873 (const_int 0)))
874 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
875 (sign_extend:HI (match_dup 1)))]
876 "TARGET_POWERPC"
877 "@
878 extsb. %0,%1
879 #"
880 [(set_attr "type" "compare")
881 (set_attr "length" "4,8")])
883 (define_split
884 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
885 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
886 (const_int 0)))
887 (set (match_operand:HI 0 "gpc_reg_operand" "")
888 (sign_extend:HI (match_dup 1)))]
889 "TARGET_POWERPC && reload_completed"
890 [(set (match_dup 0)
891 (sign_extend:HI (match_dup 1)))
892 (set (match_dup 2)
893 (compare:CC (match_dup 0)
894 (const_int 0)))]
895 "")
897 (define_expand "extendqihi2_power"
898 [(parallel [(set (match_dup 2)
899 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
900 (const_int 24)))
901 (clobber (scratch:SI))])
902 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
903 (ashiftrt:SI (match_dup 2)
904 (const_int 24)))
905 (clobber (scratch:SI))])]
906 "TARGET_POWER"
907 "
908 { operands[0] = gen_lowpart (SImode, operands[0]);
909 operands[1] = gen_lowpart (SImode, operands[1]);
910 operands[2] = gen_reg_rtx (SImode); }")
912 (define_expand "extendqihi2_no_power"
913 [(set (match_dup 2)
914 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
915 (const_int 24)))
916 (set (match_operand:HI 0 "gpc_reg_operand" "")
917 (ashiftrt:SI (match_dup 2)
918 (const_int 24)))]
919 "! TARGET_POWER && ! TARGET_POWERPC"
920 "
921 { operands[0] = gen_lowpart (SImode, operands[0]);
922 operands[1] = gen_lowpart (SImode, operands[1]);
923 operands[2] = gen_reg_rtx (SImode); }")
925 (define_expand "zero_extendhisi2"
926 [(set (match_operand:SI 0 "gpc_reg_operand" "")
927 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
928 ""
929 "")
931 (define_insn ""
932 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
933 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
934 ""
935 "@
936 lhz%U1%X1 %0,%1
937 {rlinm|rlwinm} %0,%1,0,0xffff"
938 [(set_attr "type" "load,*")])
940 (define_insn ""
941 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
942 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
943 (const_int 0)))
944 (clobber (match_scratch:SI 2 "=r,r"))]
945 ""
946 "@
947 {andil.|andi.} %2,%1,0xffff
948 #"
949 [(set_attr "type" "fast_compare,compare")
950 (set_attr "length" "4,8")])
952 (define_split
953 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
954 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
955 (const_int 0)))
956 (clobber (match_scratch:SI 2 ""))]
957 "reload_completed"
958 [(set (match_dup 2)
959 (zero_extend:SI (match_dup 1)))
960 (set (match_dup 0)
961 (compare:CC (match_dup 2)
962 (const_int 0)))]
963 "")
965 (define_insn ""
966 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
967 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
968 (const_int 0)))
969 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
970 (zero_extend:SI (match_dup 1)))]
971 ""
972 "@
973 {andil.|andi.} %0,%1,0xffff
974 #"
975 [(set_attr "type" "fast_compare,compare")
976 (set_attr "length" "4,8")])
978 (define_split
979 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
980 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
981 (const_int 0)))
982 (set (match_operand:SI 0 "gpc_reg_operand" "")
983 (zero_extend:SI (match_dup 1)))]
984 "reload_completed"
985 [(set (match_dup 0)
986 (zero_extend:SI (match_dup 1)))
987 (set (match_dup 2)
988 (compare:CC (match_dup 0)
989 (const_int 0)))]
990 "")
992 (define_expand "extendhisi2"
993 [(set (match_operand:SI 0 "gpc_reg_operand" "")
994 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
995 ""
996 "")
998 (define_insn ""
999 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1000 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1001 "rs6000_gen_cell_microcode"
1002 "@
1003 lha%U1%X1 %0,%1
1004 {exts|extsh} %0,%1"
1005 [(set_attr "type" "load_ext,exts")])
1007 (define_insn ""
1008 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1009 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
1010 "!rs6000_gen_cell_microcode"
1011 "{exts|extsh} %0,%1"
1012 [(set_attr "type" "exts")])
1014 (define_insn ""
1015 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1016 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1017 (const_int 0)))
1018 (clobber (match_scratch:SI 2 "=r,r"))]
1019 ""
1020 "@
1021 {exts.|extsh.} %2,%1
1022 #"
1023 [(set_attr "type" "compare")
1024 (set_attr "length" "4,8")])
1026 (define_split
1027 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1028 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1029 (const_int 0)))
1030 (clobber (match_scratch:SI 2 ""))]
1031 "reload_completed"
1032 [(set (match_dup 2)
1033 (sign_extend:SI (match_dup 1)))
1034 (set (match_dup 0)
1035 (compare:CC (match_dup 2)
1036 (const_int 0)))]
1037 "")
1039 (define_insn ""
1040 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1041 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1042 (const_int 0)))
1043 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1044 (sign_extend:SI (match_dup 1)))]
1045 ""
1046 "@
1047 {exts.|extsh.} %0,%1
1048 #"
1049 [(set_attr "type" "compare")
1050 (set_attr "length" "4,8")])
1051 \f
1052 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
1054 (define_insn "*macchwc"
1055 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1056 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1057 (match_operand:SI 2 "gpc_reg_operand" "r")
1058 (const_int 16))
1059 (sign_extend:SI
1060 (match_operand:HI 1 "gpc_reg_operand" "r")))
1061 (match_operand:SI 4 "gpc_reg_operand" "0"))
1062 (const_int 0)))
1063 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1064 (plus:SI (mult:SI (ashiftrt:SI
1065 (match_dup 2)
1066 (const_int 16))
1067 (sign_extend:SI
1068 (match_dup 1)))
1069 (match_dup 4)))]
1070 "TARGET_MULHW"
1071 "macchw. %0, %1, %2"
1072 [(set_attr "type" "imul3")])
1074 (define_insn "*macchw"
1075 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1076 (plus:SI (mult:SI (ashiftrt:SI
1077 (match_operand:SI 2 "gpc_reg_operand" "r")
1078 (const_int 16))
1079 (sign_extend:SI
1080 (match_operand:HI 1 "gpc_reg_operand" "r")))
1081 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1082 "TARGET_MULHW"
1083 "macchw %0, %1, %2"
1084 [(set_attr "type" "imul3")])
1086 (define_insn "*macchwuc"
1087 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1088 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1089 (match_operand:SI 2 "gpc_reg_operand" "r")
1090 (const_int 16))
1091 (zero_extend:SI
1092 (match_operand:HI 1 "gpc_reg_operand" "r")))
1093 (match_operand:SI 4 "gpc_reg_operand" "0"))
1094 (const_int 0)))
1095 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1096 (plus:SI (mult:SI (lshiftrt:SI
1097 (match_dup 2)
1098 (const_int 16))
1099 (zero_extend:SI
1100 (match_dup 1)))
1101 (match_dup 4)))]
1102 "TARGET_MULHW"
1103 "macchwu. %0, %1, %2"
1104 [(set_attr "type" "imul3")])
1106 (define_insn "*macchwu"
1107 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1108 (plus:SI (mult:SI (lshiftrt:SI
1109 (match_operand:SI 2 "gpc_reg_operand" "r")
1110 (const_int 16))
1111 (zero_extend:SI
1112 (match_operand:HI 1 "gpc_reg_operand" "r")))
1113 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1114 "TARGET_MULHW"
1115 "macchwu %0, %1, %2"
1116 [(set_attr "type" "imul3")])
1118 (define_insn "*machhwc"
1119 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1120 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1121 (match_operand:SI 1 "gpc_reg_operand" "%r")
1122 (const_int 16))
1123 (ashiftrt:SI
1124 (match_operand:SI 2 "gpc_reg_operand" "r")
1125 (const_int 16)))
1126 (match_operand:SI 4 "gpc_reg_operand" "0"))
1127 (const_int 0)))
1128 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1129 (plus:SI (mult:SI (ashiftrt:SI
1130 (match_dup 1)
1131 (const_int 16))
1132 (ashiftrt:SI
1133 (match_dup 2)
1134 (const_int 16)))
1135 (match_dup 4)))]
1136 "TARGET_MULHW"
1137 "machhw. %0, %1, %2"
1138 [(set_attr "type" "imul3")])
1140 (define_insn "*machhw"
1141 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1142 (plus:SI (mult:SI (ashiftrt:SI
1143 (match_operand:SI 1 "gpc_reg_operand" "%r")
1144 (const_int 16))
1145 (ashiftrt:SI
1146 (match_operand:SI 2 "gpc_reg_operand" "r")
1147 (const_int 16)))
1148 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1149 "TARGET_MULHW"
1150 "machhw %0, %1, %2"
1151 [(set_attr "type" "imul3")])
1153 (define_insn "*machhwuc"
1154 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1155 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1156 (match_operand:SI 1 "gpc_reg_operand" "%r")
1157 (const_int 16))
1158 (lshiftrt:SI
1159 (match_operand:SI 2 "gpc_reg_operand" "r")
1160 (const_int 16)))
1161 (match_operand:SI 4 "gpc_reg_operand" "0"))
1162 (const_int 0)))
1163 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1164 (plus:SI (mult:SI (lshiftrt:SI
1165 (match_dup 1)
1166 (const_int 16))
1167 (lshiftrt:SI
1168 (match_dup 2)
1169 (const_int 16)))
1170 (match_dup 4)))]
1171 "TARGET_MULHW"
1172 "machhwu. %0, %1, %2"
1173 [(set_attr "type" "imul3")])
1175 (define_insn "*machhwu"
1176 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1177 (plus:SI (mult:SI (lshiftrt:SI
1178 (match_operand:SI 1 "gpc_reg_operand" "%r")
1179 (const_int 16))
1180 (lshiftrt:SI
1181 (match_operand:SI 2 "gpc_reg_operand" "r")
1182 (const_int 16)))
1183 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1184 "TARGET_MULHW"
1185 "machhwu %0, %1, %2"
1186 [(set_attr "type" "imul3")])
1188 (define_insn "*maclhwc"
1189 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1190 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1191 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1192 (sign_extend:SI
1193 (match_operand:HI 2 "gpc_reg_operand" "r")))
1194 (match_operand:SI 4 "gpc_reg_operand" "0"))
1195 (const_int 0)))
1196 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1197 (plus:SI (mult:SI (sign_extend:SI
1198 (match_dup 1))
1199 (sign_extend:SI
1200 (match_dup 2)))
1201 (match_dup 4)))]
1202 "TARGET_MULHW"
1203 "maclhw. %0, %1, %2"
1204 [(set_attr "type" "imul3")])
1206 (define_insn "*maclhw"
1207 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1208 (plus:SI (mult:SI (sign_extend:SI
1209 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1210 (sign_extend:SI
1211 (match_operand:HI 2 "gpc_reg_operand" "r")))
1212 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1213 "TARGET_MULHW"
1214 "maclhw %0, %1, %2"
1215 [(set_attr "type" "imul3")])
1217 (define_insn "*maclhwuc"
1218 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1219 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1220 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1221 (zero_extend:SI
1222 (match_operand:HI 2 "gpc_reg_operand" "r")))
1223 (match_operand:SI 4 "gpc_reg_operand" "0"))
1224 (const_int 0)))
1225 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1226 (plus:SI (mult:SI (zero_extend:SI
1227 (match_dup 1))
1228 (zero_extend:SI
1229 (match_dup 2)))
1230 (match_dup 4)))]
1231 "TARGET_MULHW"
1232 "maclhwu. %0, %1, %2"
1233 [(set_attr "type" "imul3")])
1235 (define_insn "*maclhwu"
1236 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1237 (plus:SI (mult:SI (zero_extend:SI
1238 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1239 (zero_extend:SI
1240 (match_operand:HI 2 "gpc_reg_operand" "r")))
1241 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1242 "TARGET_MULHW"
1243 "maclhwu %0, %1, %2"
1244 [(set_attr "type" "imul3")])
1246 (define_insn "*nmacchwc"
1247 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1248 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1249 (mult:SI (ashiftrt:SI
1250 (match_operand:SI 2 "gpc_reg_operand" "r")
1251 (const_int 16))
1252 (sign_extend:SI
1253 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1254 (const_int 0)))
1255 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1256 (minus:SI (match_dup 4)
1257 (mult:SI (ashiftrt:SI
1258 (match_dup 2)
1259 (const_int 16))
1260 (sign_extend:SI
1261 (match_dup 1)))))]
1262 "TARGET_MULHW"
1263 "nmacchw. %0, %1, %2"
1264 [(set_attr "type" "imul3")])
1266 (define_insn "*nmacchw"
1267 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1268 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1269 (mult:SI (ashiftrt:SI
1270 (match_operand:SI 2 "gpc_reg_operand" "r")
1271 (const_int 16))
1272 (sign_extend:SI
1273 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1274 "TARGET_MULHW"
1275 "nmacchw %0, %1, %2"
1276 [(set_attr "type" "imul3")])
1278 (define_insn "*nmachhwc"
1279 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1280 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1281 (mult:SI (ashiftrt:SI
1282 (match_operand:SI 1 "gpc_reg_operand" "%r")
1283 (const_int 16))
1284 (ashiftrt:SI
1285 (match_operand:SI 2 "gpc_reg_operand" "r")
1286 (const_int 16))))
1287 (const_int 0)))
1288 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1289 (minus:SI (match_dup 4)
1290 (mult:SI (ashiftrt:SI
1291 (match_dup 1)
1292 (const_int 16))
1293 (ashiftrt:SI
1294 (match_dup 2)
1295 (const_int 16)))))]
1296 "TARGET_MULHW"
1297 "nmachhw. %0, %1, %2"
1298 [(set_attr "type" "imul3")])
1300 (define_insn "*nmachhw"
1301 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1302 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1303 (mult:SI (ashiftrt:SI
1304 (match_operand:SI 1 "gpc_reg_operand" "%r")
1305 (const_int 16))
1306 (ashiftrt:SI
1307 (match_operand:SI 2 "gpc_reg_operand" "r")
1308 (const_int 16)))))]
1309 "TARGET_MULHW"
1310 "nmachhw %0, %1, %2"
1311 [(set_attr "type" "imul3")])
1313 (define_insn "*nmaclhwc"
1314 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1315 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1316 (mult:SI (sign_extend:SI
1317 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1318 (sign_extend:SI
1319 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1320 (const_int 0)))
1321 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1322 (minus:SI (match_dup 4)
1323 (mult:SI (sign_extend:SI
1324 (match_dup 1))
1325 (sign_extend:SI
1326 (match_dup 2)))))]
1327 "TARGET_MULHW"
1328 "nmaclhw. %0, %1, %2"
1329 [(set_attr "type" "imul3")])
1331 (define_insn "*nmaclhw"
1332 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1333 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1334 (mult:SI (sign_extend:SI
1335 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1336 (sign_extend:SI
1337 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1338 "TARGET_MULHW"
1339 "nmaclhw %0, %1, %2"
1340 [(set_attr "type" "imul3")])
1342 (define_insn "*mulchwc"
1343 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1344 (compare:CC (mult:SI (ashiftrt:SI
1345 (match_operand:SI 2 "gpc_reg_operand" "r")
1346 (const_int 16))
1347 (sign_extend:SI
1348 (match_operand:HI 1 "gpc_reg_operand" "r")))
1349 (const_int 0)))
1350 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1351 (mult:SI (ashiftrt:SI
1352 (match_dup 2)
1353 (const_int 16))
1354 (sign_extend:SI
1355 (match_dup 1))))]
1356 "TARGET_MULHW"
1357 "mulchw. %0, %1, %2"
1358 [(set_attr "type" "imul3")])
1360 (define_insn "*mulchw"
1361 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1362 (mult:SI (ashiftrt:SI
1363 (match_operand:SI 2 "gpc_reg_operand" "r")
1364 (const_int 16))
1365 (sign_extend:SI
1366 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1367 "TARGET_MULHW"
1368 "mulchw %0, %1, %2"
1369 [(set_attr "type" "imul3")])
1371 (define_insn "*mulchwuc"
1372 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1373 (compare:CC (mult:SI (lshiftrt:SI
1374 (match_operand:SI 2 "gpc_reg_operand" "r")
1375 (const_int 16))
1376 (zero_extend:SI
1377 (match_operand:HI 1 "gpc_reg_operand" "r")))
1378 (const_int 0)))
1379 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1380 (mult:SI (lshiftrt:SI
1381 (match_dup 2)
1382 (const_int 16))
1383 (zero_extend:SI
1384 (match_dup 1))))]
1385 "TARGET_MULHW"
1386 "mulchwu. %0, %1, %2"
1387 [(set_attr "type" "imul3")])
1389 (define_insn "*mulchwu"
1390 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1391 (mult:SI (lshiftrt:SI
1392 (match_operand:SI 2 "gpc_reg_operand" "r")
1393 (const_int 16))
1394 (zero_extend:SI
1395 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1396 "TARGET_MULHW"
1397 "mulchwu %0, %1, %2"
1398 [(set_attr "type" "imul3")])
1400 (define_insn "*mulhhwc"
1401 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1402 (compare:CC (mult:SI (ashiftrt:SI
1403 (match_operand:SI 1 "gpc_reg_operand" "%r")
1404 (const_int 16))
1405 (ashiftrt:SI
1406 (match_operand:SI 2 "gpc_reg_operand" "r")
1407 (const_int 16)))
1408 (const_int 0)))
1409 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1410 (mult:SI (ashiftrt:SI
1411 (match_dup 1)
1412 (const_int 16))
1413 (ashiftrt:SI
1414 (match_dup 2)
1415 (const_int 16))))]
1416 "TARGET_MULHW"
1417 "mulhhw. %0, %1, %2"
1418 [(set_attr "type" "imul3")])
1420 (define_insn "*mulhhw"
1421 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1422 (mult:SI (ashiftrt:SI
1423 (match_operand:SI 1 "gpc_reg_operand" "%r")
1424 (const_int 16))
1425 (ashiftrt:SI
1426 (match_operand:SI 2 "gpc_reg_operand" "r")
1427 (const_int 16))))]
1428 "TARGET_MULHW"
1429 "mulhhw %0, %1, %2"
1430 [(set_attr "type" "imul3")])
1432 (define_insn "*mulhhwuc"
1433 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1434 (compare:CC (mult:SI (lshiftrt:SI
1435 (match_operand:SI 1 "gpc_reg_operand" "%r")
1436 (const_int 16))
1437 (lshiftrt:SI
1438 (match_operand:SI 2 "gpc_reg_operand" "r")
1439 (const_int 16)))
1440 (const_int 0)))
1441 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1442 (mult:SI (lshiftrt:SI
1443 (match_dup 1)
1444 (const_int 16))
1445 (lshiftrt:SI
1446 (match_dup 2)
1447 (const_int 16))))]
1448 "TARGET_MULHW"
1449 "mulhhwu. %0, %1, %2"
1450 [(set_attr "type" "imul3")])
1452 (define_insn "*mulhhwu"
1453 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1454 (mult:SI (lshiftrt:SI
1455 (match_operand:SI 1 "gpc_reg_operand" "%r")
1456 (const_int 16))
1457 (lshiftrt:SI
1458 (match_operand:SI 2 "gpc_reg_operand" "r")
1459 (const_int 16))))]
1460 "TARGET_MULHW"
1461 "mulhhwu %0, %1, %2"
1462 [(set_attr "type" "imul3")])
1464 (define_insn "*mullhwc"
1465 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1466 (compare:CC (mult:SI (sign_extend:SI
1467 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1468 (sign_extend:SI
1469 (match_operand:HI 2 "gpc_reg_operand" "r")))
1470 (const_int 0)))
1471 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1472 (mult:SI (sign_extend:SI
1473 (match_dup 1))
1474 (sign_extend:SI
1475 (match_dup 2))))]
1476 "TARGET_MULHW"
1477 "mullhw. %0, %1, %2"
1478 [(set_attr "type" "imul3")])
1480 (define_insn "*mullhw"
1481 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1482 (mult:SI (sign_extend:SI
1483 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1484 (sign_extend:SI
1485 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1486 "TARGET_MULHW"
1487 "mullhw %0, %1, %2"
1488 [(set_attr "type" "imul3")])
1490 (define_insn "*mullhwuc"
1491 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1492 (compare:CC (mult:SI (zero_extend:SI
1493 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1494 (zero_extend:SI
1495 (match_operand:HI 2 "gpc_reg_operand" "r")))
1496 (const_int 0)))
1497 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1498 (mult:SI (zero_extend:SI
1499 (match_dup 1))
1500 (zero_extend:SI
1501 (match_dup 2))))]
1502 "TARGET_MULHW"
1503 "mullhwu. %0, %1, %2"
1504 [(set_attr "type" "imul3")])
1506 (define_insn "*mullhwu"
1507 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1508 (mult:SI (zero_extend:SI
1509 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1510 (zero_extend:SI
1511 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1512 "TARGET_MULHW"
1513 "mullhwu %0, %1, %2"
1514 [(set_attr "type" "imul3")])
1515 \f
1516 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1517 (define_insn "dlmzb"
1518 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1519 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1520 (match_operand:SI 2 "gpc_reg_operand" "r")]
1521 UNSPEC_DLMZB_CR))
1522 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1523 (unspec:SI [(match_dup 1)
1524 (match_dup 2)]
1525 UNSPEC_DLMZB))]
1526 "TARGET_DLMZB"
1527 "dlmzb. %0, %1, %2")
1529 (define_expand "strlensi"
1530 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1531 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1532 (match_operand:QI 2 "const_int_operand" "")
1533 (match_operand 3 "const_int_operand" "")]
1534 UNSPEC_DLMZB_STRLEN))
1535 (clobber (match_scratch:CC 4 "=x"))]
1536 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1537 {
1538 rtx result = operands[0];
1539 rtx src = operands[1];
1540 rtx search_char = operands[2];
1541 rtx align = operands[3];
1542 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1543 rtx loop_label, end_label, mem, cr0, cond;
1544 if (search_char != const0_rtx
1545 || GET_CODE (align) != CONST_INT
1546 || INTVAL (align) < 8)
1547 FAIL;
1548 word1 = gen_reg_rtx (SImode);
1549 word2 = gen_reg_rtx (SImode);
1550 scratch_dlmzb = gen_reg_rtx (SImode);
1551 scratch_string = gen_reg_rtx (Pmode);
1552 loop_label = gen_label_rtx ();
1553 end_label = gen_label_rtx ();
1554 addr = force_reg (Pmode, XEXP (src, 0));
1555 emit_move_insn (scratch_string, addr);
1556 emit_label (loop_label);
1557 mem = change_address (src, SImode, scratch_string);
1558 emit_move_insn (word1, mem);
1559 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1560 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1561 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1562 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1563 emit_jump_insn (gen_rtx_SET (VOIDmode,
1564 pc_rtx,
1565 gen_rtx_IF_THEN_ELSE (VOIDmode,
1566 cond,
1567 gen_rtx_LABEL_REF
1568 (VOIDmode,
1569 end_label),
1570 pc_rtx)));
1571 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1572 emit_jump_insn (gen_rtx_SET (VOIDmode,
1573 pc_rtx,
1574 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1575 emit_barrier ();
1576 emit_label (end_label);
1577 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1578 emit_insn (gen_subsi3 (result, scratch_string, addr));
1579 emit_insn (gen_subsi3 (result, result, const1_rtx));
1580 DONE;
1581 })
1582 \f
1583 (define_split
1584 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1585 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1586 (const_int 0)))
1587 (set (match_operand:SI 0 "gpc_reg_operand" "")
1588 (sign_extend:SI (match_dup 1)))]
1589 "reload_completed"
1590 [(set (match_dup 0)
1591 (sign_extend:SI (match_dup 1)))
1592 (set (match_dup 2)
1593 (compare:CC (match_dup 0)
1594 (const_int 0)))]
1595 "")
1597 ;; Fixed-point arithmetic insns.
1599 (define_expand "add<mode>3"
1600 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1601 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1602 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1603 ""
1604 {
1605 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1606 {
1607 if (non_short_cint_operand (operands[2], DImode))
1608 FAIL;
1609 }
1610 else if (GET_CODE (operands[2]) == CONST_INT
1611 && ! add_operand (operands[2], <MODE>mode))
1612 {
1613 rtx tmp = ((!can_create_pseudo_p ()
1614 || rtx_equal_p (operands[0], operands[1]))
1615 ? operands[0] : gen_reg_rtx (<MODE>mode));
1617 HOST_WIDE_INT val = INTVAL (operands[2]);
1618 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1619 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1621 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1622 FAIL;
1624 /* The ordering here is important for the prolog expander.
1625 When space is allocated from the stack, adding 'low' first may
1626 produce a temporary deallocation (which would be bad). */
1627 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1628 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1629 DONE;
1630 }
1631 })
1633 ;; Discourage ai/addic because of carry but provide it in an alternative
1634 ;; allowing register zero as source.
1635 (define_insn "*add<mode>3_internal1"
1636 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1637 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1638 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1639 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1640 "@
1641 {cax|add} %0,%1,%2
1642 {cal %0,%2(%1)|addi %0,%1,%2}
1643 {ai|addic} %0,%1,%2
1644 {cau|addis} %0,%1,%v2"
1645 [(set_attr "length" "4,4,4,4")])
1647 (define_insn "addsi3_high"
1648 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1649 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1650 (high:SI (match_operand 2 "" ""))))]
1651 "TARGET_MACHO && !TARGET_64BIT"
1652 "{cau|addis} %0,%1,ha16(%2)"
1653 [(set_attr "length" "4")])
1655 (define_insn "*add<mode>3_internal2"
1656 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1657 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1658 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1659 (const_int 0)))
1660 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1661 ""
1662 "@
1663 {cax.|add.} %3,%1,%2
1664 {ai.|addic.} %3,%1,%2
1665 #
1666 #"
1667 [(set_attr "type" "fast_compare,compare,compare,compare")
1668 (set_attr "length" "4,4,8,8")])
1670 (define_split
1671 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1672 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1673 (match_operand:GPR 2 "reg_or_short_operand" ""))
1674 (const_int 0)))
1675 (clobber (match_scratch:GPR 3 ""))]
1676 "reload_completed"
1677 [(set (match_dup 3)
1678 (plus:GPR (match_dup 1)
1679 (match_dup 2)))
1680 (set (match_dup 0)
1681 (compare:CC (match_dup 3)
1682 (const_int 0)))]
1683 "")
1685 (define_insn "*add<mode>3_internal3"
1686 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1687 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1688 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1689 (const_int 0)))
1690 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1691 (plus:P (match_dup 1)
1692 (match_dup 2)))]
1693 ""
1694 "@
1695 {cax.|add.} %0,%1,%2
1696 {ai.|addic.} %0,%1,%2
1697 #
1698 #"
1699 [(set_attr "type" "fast_compare,compare,compare,compare")
1700 (set_attr "length" "4,4,8,8")])
1702 (define_split
1703 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1704 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1705 (match_operand:P 2 "reg_or_short_operand" ""))
1706 (const_int 0)))
1707 (set (match_operand:P 0 "gpc_reg_operand" "")
1708 (plus:P (match_dup 1) (match_dup 2)))]
1709 "reload_completed"
1710 [(set (match_dup 0)
1711 (plus:P (match_dup 1)
1712 (match_dup 2)))
1713 (set (match_dup 3)
1714 (compare:CC (match_dup 0)
1715 (const_int 0)))]
1716 "")
1718 ;; Split an add that we can't do in one insn into two insns, each of which
1719 ;; does one 16-bit part. This is used by combine. Note that the low-order
1720 ;; add should be last in case the result gets used in an address.
1722 (define_split
1723 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1724 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1725 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1726 ""
1727 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1728 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1729 {
1730 HOST_WIDE_INT val = INTVAL (operands[2]);
1731 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1732 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1734 operands[4] = GEN_INT (low);
1735 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1736 operands[3] = GEN_INT (rest);
1737 else if (can_create_pseudo_p ())
1738 {
1739 operands[3] = gen_reg_rtx (DImode);
1740 emit_move_insn (operands[3], operands[2]);
1741 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1742 DONE;
1743 }
1744 else
1745 FAIL;
1746 })
1748 (define_insn "one_cmpl<mode>2"
1749 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1750 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1751 ""
1752 "nor %0,%1,%1")
1754 (define_insn ""
1755 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1756 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1757 (const_int 0)))
1758 (clobber (match_scratch:P 2 "=r,r"))]
1759 ""
1760 "@
1761 nor. %2,%1,%1
1762 #"
1763 [(set_attr "type" "fast_compare,compare")
1764 (set_attr "length" "4,8")])
1766 (define_split
1767 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1768 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1769 (const_int 0)))
1770 (clobber (match_scratch:P 2 ""))]
1771 "reload_completed"
1772 [(set (match_dup 2)
1773 (not:P (match_dup 1)))
1774 (set (match_dup 0)
1775 (compare:CC (match_dup 2)
1776 (const_int 0)))]
1777 "")
1779 (define_insn ""
1780 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1781 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1782 (const_int 0)))
1783 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1784 (not:P (match_dup 1)))]
1785 ""
1786 "@
1787 nor. %0,%1,%1
1788 #"
1789 [(set_attr "type" "fast_compare,compare")
1790 (set_attr "length" "4,8")])
1792 (define_split
1793 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1794 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1795 (const_int 0)))
1796 (set (match_operand:P 0 "gpc_reg_operand" "")
1797 (not:P (match_dup 1)))]
1798 "reload_completed"
1799 [(set (match_dup 0)
1800 (not:P (match_dup 1)))
1801 (set (match_dup 2)
1802 (compare:CC (match_dup 0)
1803 (const_int 0)))]
1804 "")
1806 (define_insn ""
1807 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1808 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1809 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1810 "! TARGET_POWERPC"
1811 "{sf%I1|subf%I1c} %0,%2,%1")
1813 (define_insn ""
1814 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1815 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1816 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1817 "TARGET_POWERPC"
1818 "@
1819 subf %0,%2,%1
1820 subfic %0,%2,%1")
1822 (define_insn ""
1823 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1824 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1825 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1826 (const_int 0)))
1827 (clobber (match_scratch:SI 3 "=r,r"))]
1828 "! TARGET_POWERPC"
1829 "@
1830 {sf.|subfc.} %3,%2,%1
1831 #"
1832 [(set_attr "type" "compare")
1833 (set_attr "length" "4,8")])
1835 (define_insn ""
1836 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1837 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1838 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1839 (const_int 0)))
1840 (clobber (match_scratch:P 3 "=r,r"))]
1841 "TARGET_POWERPC"
1842 "@
1843 subf. %3,%2,%1
1844 #"
1845 [(set_attr "type" "fast_compare")
1846 (set_attr "length" "4,8")])
1848 (define_split
1849 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1850 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1851 (match_operand:P 2 "gpc_reg_operand" ""))
1852 (const_int 0)))
1853 (clobber (match_scratch:P 3 ""))]
1854 "reload_completed"
1855 [(set (match_dup 3)
1856 (minus:P (match_dup 1)
1857 (match_dup 2)))
1858 (set (match_dup 0)
1859 (compare:CC (match_dup 3)
1860 (const_int 0)))]
1861 "")
1863 (define_insn ""
1864 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1865 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1866 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1867 (const_int 0)))
1868 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1869 (minus:SI (match_dup 1) (match_dup 2)))]
1870 "! TARGET_POWERPC"
1871 "@
1872 {sf.|subfc.} %0,%2,%1
1873 #"
1874 [(set_attr "type" "compare")
1875 (set_attr "length" "4,8")])
1877 (define_insn ""
1878 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1879 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1880 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1881 (const_int 0)))
1882 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1883 (minus:P (match_dup 1)
1884 (match_dup 2)))]
1885 "TARGET_POWERPC"
1886 "@
1887 subf. %0,%2,%1
1888 #"
1889 [(set_attr "type" "fast_compare")
1890 (set_attr "length" "4,8")])
1892 (define_split
1893 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1894 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1895 (match_operand:P 2 "gpc_reg_operand" ""))
1896 (const_int 0)))
1897 (set (match_operand:P 0 "gpc_reg_operand" "")
1898 (minus:P (match_dup 1)
1899 (match_dup 2)))]
1900 "reload_completed"
1901 [(set (match_dup 0)
1902 (minus:P (match_dup 1)
1903 (match_dup 2)))
1904 (set (match_dup 3)
1905 (compare:CC (match_dup 0)
1906 (const_int 0)))]
1907 "")
1909 (define_expand "sub<mode>3"
1910 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1911 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1912 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1913 ""
1914 "
1915 {
1916 if (GET_CODE (operands[2]) == CONST_INT)
1917 {
1918 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1919 negate_rtx (<MODE>mode, operands[2])));
1920 DONE;
1921 }
1922 }")
1924 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1925 ;; instruction and some auxiliary computations. Then we just have a single
1926 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1927 ;; combine.
1929 (define_expand "sminsi3"
1930 [(set (match_dup 3)
1931 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1932 (match_operand:SI 2 "reg_or_short_operand" ""))
1933 (const_int 0)
1934 (minus:SI (match_dup 2) (match_dup 1))))
1935 (set (match_operand:SI 0 "gpc_reg_operand" "")
1936 (minus:SI (match_dup 2) (match_dup 3)))]
1937 "TARGET_POWER || TARGET_ISEL"
1938 "
1939 {
1940 if (TARGET_ISEL)
1941 {
1942 operands[2] = force_reg (SImode, operands[2]);
1943 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1944 DONE;
1945 }
1947 operands[3] = gen_reg_rtx (SImode);
1948 }")
1950 (define_split
1951 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1952 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1953 (match_operand:SI 2 "reg_or_short_operand" "")))
1954 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1955 "TARGET_POWER"
1956 [(set (match_dup 3)
1957 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1958 (const_int 0)
1959 (minus:SI (match_dup 2) (match_dup 1))))
1960 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1961 "")
1963 (define_expand "smaxsi3"
1964 [(set (match_dup 3)
1965 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1966 (match_operand:SI 2 "reg_or_short_operand" ""))
1967 (const_int 0)
1968 (minus:SI (match_dup 2) (match_dup 1))))
1969 (set (match_operand:SI 0 "gpc_reg_operand" "")
1970 (plus:SI (match_dup 3) (match_dup 1)))]
1971 "TARGET_POWER || TARGET_ISEL"
1972 "
1973 {
1974 if (TARGET_ISEL)
1975 {
1976 operands[2] = force_reg (SImode, operands[2]);
1977 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1978 DONE;
1979 }
1980 operands[3] = gen_reg_rtx (SImode);
1981 }")
1983 (define_split
1984 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1985 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1986 (match_operand:SI 2 "reg_or_short_operand" "")))
1987 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1988 "TARGET_POWER"
1989 [(set (match_dup 3)
1990 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1991 (const_int 0)
1992 (minus:SI (match_dup 2) (match_dup 1))))
1993 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1994 "")
1996 (define_expand "uminsi3"
1997 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1998 (match_dup 5)))
1999 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
2000 (match_dup 5)))
2001 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
2002 (const_int 0)
2003 (minus:SI (match_dup 4) (match_dup 3))))
2004 (set (match_operand:SI 0 "gpc_reg_operand" "")
2005 (minus:SI (match_dup 2) (match_dup 3)))]
2006 "TARGET_POWER || TARGET_ISEL"
2007 "
2008 {
2009 if (TARGET_ISEL)
2010 {
2011 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
2012 DONE;
2013 }
2014 operands[3] = gen_reg_rtx (SImode);
2015 operands[4] = gen_reg_rtx (SImode);
2016 operands[5] = GEN_INT (-2147483647 - 1);
2017 }")
2019 (define_expand "umaxsi3"
2020 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2021 (match_dup 5)))
2022 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
2023 (match_dup 5)))
2024 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
2025 (const_int 0)
2026 (minus:SI (match_dup 4) (match_dup 3))))
2027 (set (match_operand:SI 0 "gpc_reg_operand" "")
2028 (plus:SI (match_dup 3) (match_dup 1)))]
2029 "TARGET_POWER || TARGET_ISEL"
2030 "
2031 {
2032 if (TARGET_ISEL)
2033 {
2034 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
2035 DONE;
2036 }
2037 operands[3] = gen_reg_rtx (SImode);
2038 operands[4] = gen_reg_rtx (SImode);
2039 operands[5] = GEN_INT (-2147483647 - 1);
2040 }")
2042 (define_insn ""
2043 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2044 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
2045 (match_operand:SI 2 "reg_or_short_operand" "rI"))
2046 (const_int 0)
2047 (minus:SI (match_dup 2) (match_dup 1))))]
2048 "TARGET_POWER"
2049 "doz%I2 %0,%1,%2")
2051 (define_insn ""
2052 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2053 (compare:CC
2054 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2055 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2056 (const_int 0)
2057 (minus:SI (match_dup 2) (match_dup 1)))
2058 (const_int 0)))
2059 (clobber (match_scratch:SI 3 "=r,r"))]
2060 "TARGET_POWER"
2061 "@
2062 doz%I2. %3,%1,%2
2063 #"
2064 [(set_attr "type" "delayed_compare")
2065 (set_attr "length" "4,8")])
2067 (define_split
2068 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2069 (compare:CC
2070 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2071 (match_operand:SI 2 "reg_or_short_operand" ""))
2072 (const_int 0)
2073 (minus:SI (match_dup 2) (match_dup 1)))
2074 (const_int 0)))
2075 (clobber (match_scratch:SI 3 ""))]
2076 "TARGET_POWER && reload_completed"
2077 [(set (match_dup 3)
2078 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2079 (const_int 0)
2080 (minus:SI (match_dup 2) (match_dup 1))))
2081 (set (match_dup 0)
2082 (compare:CC (match_dup 3)
2083 (const_int 0)))]
2084 "")
2086 (define_insn ""
2087 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2088 (compare:CC
2089 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2090 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2091 (const_int 0)
2092 (minus:SI (match_dup 2) (match_dup 1)))
2093 (const_int 0)))
2094 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2095 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2096 (const_int 0)
2097 (minus:SI (match_dup 2) (match_dup 1))))]
2098 "TARGET_POWER"
2099 "@
2100 doz%I2. %0,%1,%2
2101 #"
2102 [(set_attr "type" "delayed_compare")
2103 (set_attr "length" "4,8")])
2105 (define_split
2106 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2107 (compare:CC
2108 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2109 (match_operand:SI 2 "reg_or_short_operand" ""))
2110 (const_int 0)
2111 (minus:SI (match_dup 2) (match_dup 1)))
2112 (const_int 0)))
2113 (set (match_operand:SI 0 "gpc_reg_operand" "")
2114 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2115 (const_int 0)
2116 (minus:SI (match_dup 2) (match_dup 1))))]
2117 "TARGET_POWER && reload_completed"
2118 [(set (match_dup 0)
2119 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2120 (const_int 0)
2121 (minus:SI (match_dup 2) (match_dup 1))))
2122 (set (match_dup 3)
2123 (compare:CC (match_dup 0)
2124 (const_int 0)))]
2125 "")
2127 ;; We don't need abs with condition code because such comparisons should
2128 ;; never be done.
2129 (define_expand "abssi2"
2130 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2131 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2132 ""
2133 "
2134 {
2135 if (TARGET_ISEL)
2136 {
2137 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2138 DONE;
2139 }
2140 else if (! TARGET_POWER)
2141 {
2142 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2143 DONE;
2144 }
2145 }")
2147 (define_insn "*abssi2_power"
2148 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2149 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2150 "TARGET_POWER"
2151 "abs %0,%1")
2153 (define_insn_and_split "abs<mode>2_isel"
2154 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2155 (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b")))
2156 (clobber (match_scratch:GPR 2 "=&b"))
2157 (clobber (match_scratch:CC 3 "=y"))]
2158 "TARGET_ISEL"
2159 "#"
2160 "&& reload_completed"
2161 [(set (match_dup 2) (neg:GPR (match_dup 1)))
2162 (set (match_dup 3)
2163 (compare:CC (match_dup 1)
2164 (const_int 0)))
2165 (set (match_dup 0)
2166 (if_then_else:GPR (lt (match_dup 3)
2167 (const_int 0))
2168 (match_dup 2)
2169 (match_dup 1)))]
2170 "")
2172 (define_insn_and_split "nabs<mode>2_isel"
2173 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2174 (neg:GPR (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b"))))
2175 (clobber (match_scratch:GPR 2 "=&b"))
2176 (clobber (match_scratch:CC 3 "=y"))]
2177 "TARGET_ISEL"
2178 "#"
2179 "&& reload_completed"
2180 [(set (match_dup 2) (neg:GPR (match_dup 1)))
2181 (set (match_dup 3)
2182 (compare:CC (match_dup 1)
2183 (const_int 0)))
2184 (set (match_dup 0)
2185 (if_then_else:GPR (lt (match_dup 3)
2186 (const_int 0))
2187 (match_dup 1)
2188 (match_dup 2)))]
2189 "")
2191 (define_insn_and_split "abssi2_nopower"
2192 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2193 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2194 (clobber (match_scratch:SI 2 "=&r,&r"))]
2195 "! TARGET_POWER && ! TARGET_ISEL"
2196 "#"
2197 "&& reload_completed"
2198 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2199 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2200 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2201 "")
2203 (define_insn "*nabs_power"
2204 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2205 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2206 "TARGET_POWER"
2207 "nabs %0,%1")
2209 (define_insn_and_split "*nabs_nopower"
2210 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2211 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2212 (clobber (match_scratch:SI 2 "=&r,&r"))]
2213 "! TARGET_POWER"
2214 "#"
2215 "&& reload_completed"
2216 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2217 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2218 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2219 "")
2221 (define_expand "neg<mode>2"
2222 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2223 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2224 ""
2225 "")
2227 (define_insn "*neg<mode>2_internal"
2228 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2229 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2230 ""
2231 "neg %0,%1")
2233 (define_insn ""
2234 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2235 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2236 (const_int 0)))
2237 (clobber (match_scratch:P 2 "=r,r"))]
2238 ""
2239 "@
2240 neg. %2,%1
2241 #"
2242 [(set_attr "type" "fast_compare")
2243 (set_attr "length" "4,8")])
2245 (define_split
2246 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2247 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2248 (const_int 0)))
2249 (clobber (match_scratch:P 2 ""))]
2250 "reload_completed"
2251 [(set (match_dup 2)
2252 (neg:P (match_dup 1)))
2253 (set (match_dup 0)
2254 (compare:CC (match_dup 2)
2255 (const_int 0)))]
2256 "")
2258 (define_insn ""
2259 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2260 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2261 (const_int 0)))
2262 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2263 (neg:P (match_dup 1)))]
2264 ""
2265 "@
2266 neg. %0,%1
2267 #"
2268 [(set_attr "type" "fast_compare")
2269 (set_attr "length" "4,8")])
2271 (define_split
2272 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2273 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2274 (const_int 0)))
2275 (set (match_operand:P 0 "gpc_reg_operand" "")
2276 (neg:P (match_dup 1)))]
2277 "reload_completed"
2278 [(set (match_dup 0)
2279 (neg:P (match_dup 1)))
2280 (set (match_dup 2)
2281 (compare:CC (match_dup 0)
2282 (const_int 0)))]
2283 "")
2285 (define_insn "clz<mode>2"
2286 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2287 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2288 ""
2289 "{cntlz|cntlz<wd>} %0,%1"
2290 [(set_attr "type" "cntlz")])
2292 (define_expand "ctz<mode>2"
2293 [(set (match_dup 2)
2294 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2295 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2296 (match_dup 2)))
2297 (clobber (scratch:CC))])
2298 (set (match_dup 4) (clz:GPR (match_dup 3)))
2299 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2300 (minus:GPR (match_dup 5) (match_dup 4)))]
2301 ""
2302 {
2303 operands[2] = gen_reg_rtx (<MODE>mode);
2304 operands[3] = gen_reg_rtx (<MODE>mode);
2305 operands[4] = gen_reg_rtx (<MODE>mode);
2306 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2307 })
2309 (define_expand "ffs<mode>2"
2310 [(set (match_dup 2)
2311 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2312 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2313 (match_dup 2)))
2314 (clobber (scratch:CC))])
2315 (set (match_dup 4) (clz:GPR (match_dup 3)))
2316 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2317 (minus:GPR (match_dup 5) (match_dup 4)))]
2318 ""
2319 {
2320 operands[2] = gen_reg_rtx (<MODE>mode);
2321 operands[3] = gen_reg_rtx (<MODE>mode);
2322 operands[4] = gen_reg_rtx (<MODE>mode);
2323 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2324 })
2326 (define_insn "popcntb<mode>2"
2327 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2328 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2329 UNSPEC_POPCNTB))]
2330 "TARGET_POPCNTB"
2331 "popcntb %0,%1"
2332 [(set_attr "length" "4")
2333 (set_attr "type" "popcnt")])
2335 (define_insn "popcntd<mode>2"
2336 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2337 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2338 "TARGET_POPCNTD"
2339 "popcnt<wd> %0,%1"
2340 [(set_attr "length" "4")
2341 (set_attr "type" "popcnt")])
2343 (define_expand "popcount<mode>2"
2344 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2345 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2346 "TARGET_POPCNTB || TARGET_POPCNTD"
2347 {
2348 rs6000_emit_popcount (operands[0], operands[1]);
2349 DONE;
2350 })
2352 (define_insn "parity<mode>2_cmpb"
2353 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2354 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
2355 "TARGET_CMPB && TARGET_POPCNTB"
2356 "prty<wd> %0,%1")
2358 (define_expand "parity<mode>2"
2359 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2360 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2361 "TARGET_POPCNTB"
2362 {
2363 rs6000_emit_parity (operands[0], operands[1]);
2364 DONE;
2365 })
2367 ;; Since the hardware zeros the upper part of the register, save generating the
2368 ;; AND immediate if we are converting to unsigned
2369 (define_insn "*bswaphi2_extenddi"
2370 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2371 (zero_extend:DI
2372 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2373 "TARGET_POWERPC64"
2374 "lhbrx %0,%y1"
2375 [(set_attr "length" "4")
2376 (set_attr "type" "load")])
2378 (define_insn "*bswaphi2_extendsi"
2379 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2380 (zero_extend:SI
2381 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2382 "TARGET_POWERPC"
2383 "lhbrx %0,%y1"
2384 [(set_attr "length" "4")
2385 (set_attr "type" "load")])
2387 (define_expand "bswaphi2"
2388 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2389 (bswap:HI
2390 (match_operand:HI 1 "reg_or_mem_operand" "")))
2391 (clobber (match_scratch:SI 2 ""))])]
2392 "TARGET_POWERPC"
2393 {
2394 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2395 operands[1] = force_reg (HImode, operands[1]);
2396 })
2398 (define_insn "bswaphi2_internal"
2399 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2400 (bswap:HI
2401 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2402 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2403 "TARGET_POWERPC"
2404 "@
2405 lhbrx %0,%y1
2406 sthbrx %1,%y0
2407 #"
2408 [(set_attr "length" "4,4,12")
2409 (set_attr "type" "load,store,*")])
2411 (define_split
2412 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2413 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2414 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2415 "TARGET_POWERPC && reload_completed"
2416 [(set (match_dup 3)
2417 (zero_extract:SI (match_dup 4)
2418 (const_int 8)
2419 (const_int 16)))
2420 (set (match_dup 2)
2421 (and:SI (ashift:SI (match_dup 4)
2422 (const_int 8))
2423 (const_int 65280))) ;; 0xff00
2424 (set (match_dup 3)
2425 (ior:SI (match_dup 3)
2426 (match_dup 2)))]
2427 "
2428 {
2429 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2430 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2431 }")
2433 (define_insn "*bswapsi2_extenddi"
2434 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2435 (zero_extend:DI
2436 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2437 "TARGET_POWERPC64"
2438 "lwbrx %0,%y1"
2439 [(set_attr "length" "4")
2440 (set_attr "type" "load")])
2442 (define_expand "bswapsi2"
2443 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2444 (bswap:SI
2445 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2446 ""
2447 {
2448 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2449 operands[1] = force_reg (SImode, operands[1]);
2450 })
2452 (define_insn "*bswapsi2_internal"
2453 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2454 (bswap:SI
2455 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2456 ""
2457 "@
2458 {lbrx|lwbrx} %0,%y1
2459 {stbrx|stwbrx} %1,%y0
2460 #"
2461 [(set_attr "length" "4,4,12")
2462 (set_attr "type" "load,store,*")])
2464 (define_split
2465 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2466 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2467 "reload_completed"
2468 [(set (match_dup 0)
2469 (rotate:SI (match_dup 1) (const_int 8)))
2470 (set (zero_extract:SI (match_dup 0)
2471 (const_int 8)
2472 (const_int 0))
2473 (match_dup 1))
2474 (set (zero_extract:SI (match_dup 0)
2475 (const_int 8)
2476 (const_int 16))
2477 (rotate:SI (match_dup 1)
2478 (const_int 16)))]
2479 "")
2481 (define_expand "bswapdi2"
2482 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2483 (bswap:DI
2484 (match_operand:DI 1 "reg_or_mem_operand" "")))
2485 (clobber (match_scratch:DI 2 ""))
2486 (clobber (match_scratch:DI 3 ""))
2487 (clobber (match_scratch:DI 4 ""))])]
2488 ""
2489 {
2490 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2491 operands[1] = force_reg (DImode, operands[1]);
2493 if (!TARGET_POWERPC64)
2494 {
2495 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2496 that uses 64-bit registers needs the same scratch registers as 64-bit
2497 mode. */
2498 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2499 DONE;
2500 }
2501 })
2503 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2504 (define_insn "*bswapdi2_ldbrx"
2505 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2506 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2507 (clobber (match_scratch:DI 2 "=X,X,&r"))
2508 (clobber (match_scratch:DI 3 "=X,X,&r"))
2509 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2510 "TARGET_POWERPC64 && TARGET_LDBRX
2511 && (REG_P (operands[0]) || REG_P (operands[1]))"
2512 "@
2513 ldbrx %0,%y1
2514 stdbrx %1,%y0
2515 #"
2516 [(set_attr "length" "4,4,36")
2517 (set_attr "type" "load,store,*")])
2519 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2520 (define_insn "*bswapdi2_64bit"
2521 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2522 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2523 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2524 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2525 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2526 "TARGET_POWERPC64 && !TARGET_LDBRX
2527 && (REG_P (operands[0]) || REG_P (operands[1]))"
2528 "#"
2529 [(set_attr "length" "16,12,36")])
2531 (define_split
2532 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2533 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2534 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2535 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2536 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2537 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2538 [(const_int 0)]
2539 "
2540 {
2541 rtx dest = operands[0];
2542 rtx src = operands[1];
2543 rtx op2 = operands[2];
2544 rtx op3 = operands[3];
2545 rtx op4 = operands[4];
2546 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode, 4);
2547 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode, 4);
2548 rtx addr1;
2549 rtx addr2;
2550 rtx word_high;
2551 rtx word_low;
2553 addr1 = XEXP (src, 0);
2554 if (GET_CODE (addr1) == PLUS)
2555 {
2556 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2557 if (TARGET_AVOID_XFORM)
2558 {
2559 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2560 addr2 = op2;
2561 }
2562 else
2563 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2564 }
2565 else if (TARGET_AVOID_XFORM)
2566 {
2567 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2568 addr2 = op2;
2569 }
2570 else
2571 {
2572 emit_move_insn (op2, GEN_INT (4));
2573 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2574 }
2576 if (BYTES_BIG_ENDIAN)
2577 {
2578 word_high = change_address (src, SImode, addr1);
2579 word_low = change_address (src, SImode, addr2);
2580 }
2581 else
2582 {
2583 word_high = change_address (src, SImode, addr2);
2584 word_low = change_address (src, SImode, addr1);
2585 }
2587 emit_insn (gen_bswapsi2 (op3_32, word_low));
2588 emit_insn (gen_bswapsi2 (op4_32, word_high));
2589 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2590 emit_insn (gen_iordi3 (dest, dest, op4));
2591 }")
2593 (define_split
2594 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2595 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2596 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2597 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2598 (clobber (match_operand:DI 4 "" ""))]
2599 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2600 [(const_int 0)]
2601 "
2602 {
2603 rtx dest = operands[0];
2604 rtx src = operands[1];
2605 rtx op2 = operands[2];
2606 rtx op3 = operands[3];
2607 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2608 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2609 rtx addr1;
2610 rtx addr2;
2611 rtx word_high;
2612 rtx word_low;
2614 addr1 = XEXP (dest, 0);
2615 if (GET_CODE (addr1) == PLUS)
2616 {
2617 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2618 if (TARGET_AVOID_XFORM)
2619 {
2620 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2621 addr2 = op2;
2622 }
2623 else
2624 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2625 }
2626 else if (TARGET_AVOID_XFORM)
2627 {
2628 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2629 addr2 = op2;
2630 }
2631 else
2632 {
2633 emit_move_insn (op2, GEN_INT (4));
2634 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2635 }
2637 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2638 if (BYTES_BIG_ENDIAN)
2639 {
2640 word_high = change_address (dest, SImode, addr1);
2641 word_low = change_address (dest, SImode, addr2);
2642 emit_insn (gen_bswapsi2 (word_high, src_si));
2643 emit_insn (gen_bswapsi2 (word_low, op3_si));
2644 }
2645 else
2646 {
2647 word_high = change_address (dest, SImode, addr2);
2648 word_low = change_address (dest, SImode, addr1);
2649 emit_insn (gen_bswapsi2 (word_low, src_si));
2650 emit_insn (gen_bswapsi2 (word_high, op3_si));
2651 }
2652 }")
2654 (define_split
2655 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2656 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2657 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2658 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2659 (clobber (match_operand:DI 4 "" ""))]
2660 "TARGET_POWERPC64 && reload_completed"
2661 [(const_int 0)]
2662 "
2663 {
2664 rtx dest = operands[0];
2665 rtx src = operands[1];
2666 rtx op2 = operands[2];
2667 rtx op3 = operands[3];
2668 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, 4);
2669 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2670 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, 4);
2671 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2673 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2674 emit_insn (gen_bswapsi2 (dest_si, src_si));
2675 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2676 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2677 emit_insn (gen_iordi3 (dest, dest, op3));
2678 }")
2680 (define_insn "bswapdi2_32bit"
2681 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2682 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2683 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2684 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2685 "#"
2686 [(set_attr "length" "16,12,36")])
2688 (define_split
2689 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2690 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2691 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2692 "!TARGET_POWERPC64 && reload_completed"
2693 [(const_int 0)]
2694 "
2695 {
2696 rtx dest = operands[0];
2697 rtx src = operands[1];
2698 rtx op2 = operands[2];
2699 rtx dest_hi = simplify_gen_subreg (SImode, dest, DImode, 0);
2700 rtx dest_lo = simplify_gen_subreg (SImode, dest, DImode, 4);
2701 rtx addr1;
2702 rtx addr2;
2703 rtx word_high;
2704 rtx word_low;
2706 addr1 = XEXP (src, 0);
2707 if (GET_CODE (addr1) == PLUS)
2708 {
2709 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2710 if (TARGET_AVOID_XFORM)
2711 {
2712 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2713 addr2 = op2;
2714 }
2715 else
2716 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2717 }
2718 else if (TARGET_AVOID_XFORM)
2719 {
2720 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2721 addr2 = op2;
2722 }
2723 else
2724 {
2725 emit_move_insn (op2, GEN_INT (4));
2726 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2727 }
2729 if (BYTES_BIG_ENDIAN)
2730 {
2731 word_high = change_address (src, SImode, addr1);
2732 word_low = change_address (src, SImode, addr2);
2733 }
2734 else
2735 {
2736 word_high = change_address (src, SImode, addr2);
2737 word_low = change_address (src, SImode, addr1);
2738 }
2740 emit_insn (gen_bswapsi2 (dest_hi, word_low));
2741 emit_insn (gen_bswapsi2 (dest_lo, word_high));
2742 }")
2744 (define_split
2745 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2746 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2747 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2748 "!TARGET_POWERPC64 && reload_completed"
2749 [(const_int 0)]
2750 "
2751 {
2752 rtx dest = operands[0];
2753 rtx src = operands[1];
2754 rtx op2 = operands[2];
2755 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2756 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2757 rtx addr1;
2758 rtx addr2;
2759 rtx word_high;
2760 rtx word_low;
2762 addr1 = XEXP (dest, 0);
2763 if (GET_CODE (addr1) == PLUS)
2764 {
2765 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2766 if (TARGET_AVOID_XFORM)
2767 {
2768 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2769 addr2 = op2;
2770 }
2771 else
2772 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2773 }
2774 else if (TARGET_AVOID_XFORM)
2775 {
2776 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2777 addr2 = op2;
2778 }
2779 else
2780 {
2781 emit_move_insn (op2, GEN_INT (4));
2782 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2783 }
2785 if (BYTES_BIG_ENDIAN)
2786 {
2787 word_high = change_address (dest, SImode, addr1);
2788 word_low = change_address (dest, SImode, addr2);
2789 }
2790 else
2791 {
2792 word_high = change_address (dest, SImode, addr2);
2793 word_low = change_address (dest, SImode, addr1);
2794 }
2796 emit_insn (gen_bswapsi2 (word_high, src_low));
2797 emit_insn (gen_bswapsi2 (word_low, src_high));
2798 }")
2800 (define_split
2801 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2802 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2803 (clobber (match_operand:SI 2 "" ""))]
2804 "!TARGET_POWERPC64 && reload_completed"
2805 [(const_int 0)]
2806 "
2807 {
2808 rtx dest = operands[0];
2809 rtx src = operands[1];
2810 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2811 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2812 rtx dest_high = simplify_gen_subreg (SImode, dest, DImode, 0);
2813 rtx dest_low = simplify_gen_subreg (SImode, dest, DImode, 4);
2815 emit_insn (gen_bswapsi2 (dest_high, src_low));
2816 emit_insn (gen_bswapsi2 (dest_low, src_high));
2817 }")
2819 (define_expand "mulsi3"
2820 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2821 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2822 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2823 ""
2824 "
2825 {
2826 if (TARGET_POWER)
2827 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2828 else
2829 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2830 DONE;
2831 }")
2833 (define_insn "mulsi3_mq"
2834 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2835 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2836 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2837 (clobber (match_scratch:SI 3 "=q,q"))]
2838 "TARGET_POWER"
2839 "@
2840 {muls|mullw} %0,%1,%2
2841 {muli|mulli} %0,%1,%2"
2842 [(set (attr "type")
2843 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2844 (const_string "imul3")
2845 (match_operand:SI 2 "short_cint_operand" "")
2846 (const_string "imul2")]
2847 (const_string "imul")))])
2849 (define_insn "mulsi3_no_mq"
2850 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2851 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2852 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2853 "! TARGET_POWER"
2854 "@
2855 {muls|mullw} %0,%1,%2
2856 {muli|mulli} %0,%1,%2"
2857 [(set (attr "type")
2858 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2859 (const_string "imul3")
2860 (match_operand:SI 2 "short_cint_operand" "")
2861 (const_string "imul2")]
2862 (const_string "imul")))])
2864 (define_insn "*mulsi3_mq_internal1"
2865 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2866 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2867 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2868 (const_int 0)))
2869 (clobber (match_scratch:SI 3 "=r,r"))
2870 (clobber (match_scratch:SI 4 "=q,q"))]
2871 "TARGET_POWER"
2872 "@
2873 {muls.|mullw.} %3,%1,%2
2874 #"
2875 [(set_attr "type" "imul_compare")
2876 (set_attr "length" "4,8")])
2878 (define_split
2879 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2880 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2881 (match_operand:SI 2 "gpc_reg_operand" ""))
2882 (const_int 0)))
2883 (clobber (match_scratch:SI 3 ""))
2884 (clobber (match_scratch:SI 4 ""))]
2885 "TARGET_POWER && reload_completed"
2886 [(parallel [(set (match_dup 3)
2887 (mult:SI (match_dup 1) (match_dup 2)))
2888 (clobber (match_dup 4))])
2889 (set (match_dup 0)
2890 (compare:CC (match_dup 3)
2891 (const_int 0)))]
2892 "")
2894 (define_insn "*mulsi3_no_mq_internal1"
2895 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2896 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2897 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2898 (const_int 0)))
2899 (clobber (match_scratch:SI 3 "=r,r"))]
2900 "! TARGET_POWER"
2901 "@
2902 {muls.|mullw.} %3,%1,%2
2903 #"
2904 [(set_attr "type" "imul_compare")
2905 (set_attr "length" "4,8")])
2907 (define_split
2908 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2909 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2910 (match_operand:SI 2 "gpc_reg_operand" ""))
2911 (const_int 0)))
2912 (clobber (match_scratch:SI 3 ""))]
2913 "! TARGET_POWER && reload_completed"
2914 [(set (match_dup 3)
2915 (mult:SI (match_dup 1) (match_dup 2)))
2916 (set (match_dup 0)
2917 (compare:CC (match_dup 3)
2918 (const_int 0)))]
2919 "")
2921 (define_insn "*mulsi3_mq_internal2"
2922 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2923 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2924 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2925 (const_int 0)))
2926 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2927 (mult:SI (match_dup 1) (match_dup 2)))
2928 (clobber (match_scratch:SI 4 "=q,q"))]
2929 "TARGET_POWER"
2930 "@
2931 {muls.|mullw.} %0,%1,%2
2932 #"
2933 [(set_attr "type" "imul_compare")
2934 (set_attr "length" "4,8")])
2936 (define_split
2937 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2938 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2939 (match_operand:SI 2 "gpc_reg_operand" ""))
2940 (const_int 0)))
2941 (set (match_operand:SI 0 "gpc_reg_operand" "")
2942 (mult:SI (match_dup 1) (match_dup 2)))
2943 (clobber (match_scratch:SI 4 ""))]
2944 "TARGET_POWER && reload_completed"
2945 [(parallel [(set (match_dup 0)
2946 (mult:SI (match_dup 1) (match_dup 2)))
2947 (clobber (match_dup 4))])
2948 (set (match_dup 3)
2949 (compare:CC (match_dup 0)
2950 (const_int 0)))]
2951 "")
2953 (define_insn "*mulsi3_no_mq_internal2"
2954 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2955 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2956 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2957 (const_int 0)))
2958 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2959 (mult:SI (match_dup 1) (match_dup 2)))]
2960 "! TARGET_POWER"
2961 "@
2962 {muls.|mullw.} %0,%1,%2
2963 #"
2964 [(set_attr "type" "imul_compare")
2965 (set_attr "length" "4,8")])
2967 (define_split
2968 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2969 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2970 (match_operand:SI 2 "gpc_reg_operand" ""))
2971 (const_int 0)))
2972 (set (match_operand:SI 0 "gpc_reg_operand" "")
2973 (mult:SI (match_dup 1) (match_dup 2)))]
2974 "! TARGET_POWER && reload_completed"
2975 [(set (match_dup 0)
2976 (mult:SI (match_dup 1) (match_dup 2)))
2977 (set (match_dup 3)
2978 (compare:CC (match_dup 0)
2979 (const_int 0)))]
2980 "")
2982 ;; Operand 1 is divided by operand 2; quotient goes to operand
2983 ;; 0 and remainder to operand 3.
2984 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2986 (define_expand "divmodsi4"
2987 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2988 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2989 (match_operand:SI 2 "gpc_reg_operand" "")))
2990 (set (match_operand:SI 3 "register_operand" "")
2991 (mod:SI (match_dup 1) (match_dup 2)))])]
2992 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2993 "
2994 {
2995 if (! TARGET_POWER && ! TARGET_POWERPC)
2996 {
2997 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2998 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2999 emit_insn (gen_divss_call ());
3000 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
3001 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
3002 DONE;
3003 }
3004 }")
3006 (define_insn "*divmodsi4_internal"
3007 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3008 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3009 (match_operand:SI 2 "gpc_reg_operand" "r")))
3010 (set (match_operand:SI 3 "register_operand" "=q")
3011 (mod:SI (match_dup 1) (match_dup 2)))]
3012 "TARGET_POWER"
3013 "divs %0,%1,%2"
3014 [(set_attr "type" "idiv")])
3016 (define_expand "udiv<mode>3"
3017 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
3018 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3019 (match_operand:GPR 2 "gpc_reg_operand" "")))]
3020 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
3021 "
3022 {
3023 if (! TARGET_POWER && ! TARGET_POWERPC)
3024 {
3025 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
3026 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
3027 emit_insn (gen_quous_call ());
3028 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
3029 DONE;
3030 }
3031 else if (TARGET_POWER)
3032 {
3033 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
3034 DONE;
3035 }
3036 }")
3038 (define_insn "udivsi3_mq"
3039 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3040 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3041 (match_operand:SI 2 "gpc_reg_operand" "r")))
3042 (clobber (match_scratch:SI 3 "=q"))]
3043 "TARGET_POWERPC && TARGET_POWER"
3044 "divwu %0,%1,%2"
3045 [(set_attr "type" "idiv")])
3047 (define_insn "*udivsi3_no_mq"
3048 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3049 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3050 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
3051 "TARGET_POWERPC && ! TARGET_POWER"
3052 "div<wd>u %0,%1,%2"
3053 [(set (attr "type")
3054 (cond [(match_operand:SI 0 "" "")
3055 (const_string "idiv")]
3056 (const_string "ldiv")))])
3059 ;; For powers of two we can do srai/aze for divide and then adjust for
3060 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
3061 ;; used; for PowerPC, force operands into register and do a normal divide;
3062 ;; for AIX common-mode, use quoss call on register operands.
3063 (define_expand "div<mode>3"
3064 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
3065 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3066 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
3067 ""
3068 "
3069 {
3070 if (GET_CODE (operands[2]) == CONST_INT
3071 && INTVAL (operands[2]) > 0
3072 && exact_log2 (INTVAL (operands[2])) >= 0)
3073 ;
3074 else if (TARGET_POWERPC)
3075 {
3076 operands[2] = force_reg (<MODE>mode, operands[2]);
3077 if (TARGET_POWER)
3078 {
3079 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
3080 DONE;
3081 }
3082 }
3083 else if (TARGET_POWER)
3084 FAIL;
3085 else
3086 {
3087 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
3088 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
3089 emit_insn (gen_quoss_call ());
3090 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
3091 DONE;
3092 }
3093 }")
3095 (define_insn "divsi3_mq"
3096 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3097 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3098 (match_operand:SI 2 "gpc_reg_operand" "r")))
3099 (clobber (match_scratch:SI 3 "=q"))]
3100 "TARGET_POWERPC && TARGET_POWER"
3101 "divw %0,%1,%2"
3102 [(set_attr "type" "idiv")])
3104 (define_insn "*div<mode>3_no_mq"
3105 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3106 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3107 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
3108 "TARGET_POWERPC && ! TARGET_POWER"
3109 "div<wd> %0,%1,%2"
3110 [(set (attr "type")
3111 (cond [(match_operand:SI 0 "" "")
3112 (const_string "idiv")]
3113 (const_string "ldiv")))])
3115 (define_expand "mod<mode>3"
3116 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
3117 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
3118 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
3119 ""
3120 "
3121 {
3122 int i;
3123 rtx temp1;
3124 rtx temp2;
3126 if (GET_CODE (operands[2]) != CONST_INT
3127 || INTVAL (operands[2]) <= 0
3128 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
3129 FAIL;
3131 temp1 = gen_reg_rtx (<MODE>mode);
3132 temp2 = gen_reg_rtx (<MODE>mode);
3134 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
3135 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
3136 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
3137 DONE;
3138 }")
3140 (define_insn ""
3141 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3142 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3143 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
3144 ""
3145 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
3146 [(set_attr "type" "two")
3147 (set_attr "length" "8")])
3149 (define_insn ""
3150 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3151 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3152 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3153 (const_int 0)))
3154 (clobber (match_scratch:P 3 "=r,r"))]
3155 ""
3156 "@
3157 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
3158 #"
3159 [(set_attr "type" "compare")
3160 (set_attr "length" "8,12")
3161 (set_attr "cell_micro" "not")])
3163 (define_split
3164 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3165 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3166 (match_operand:GPR 2 "exact_log2_cint_operand"
3167 ""))
3168 (const_int 0)))
3169 (clobber (match_scratch:GPR 3 ""))]
3170 "reload_completed"
3171 [(set (match_dup 3)
3172 (div:<MODE> (match_dup 1) (match_dup 2)))
3173 (set (match_dup 0)
3174 (compare:CC (match_dup 3)
3175 (const_int 0)))]
3176 "")
3178 (define_insn ""
3179 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3180 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3181 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3182 (const_int 0)))
3183 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
3184 (div:P (match_dup 1) (match_dup 2)))]
3185 ""
3186 "@
3187 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
3188 #"
3189 [(set_attr "type" "compare")
3190 (set_attr "length" "8,12")
3191 (set_attr "cell_micro" "not")])
3193 (define_split
3194 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3195 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3196 (match_operand:GPR 2 "exact_log2_cint_operand"
3197 ""))
3198 (const_int 0)))
3199 (set (match_operand:GPR 0 "gpc_reg_operand" "")
3200 (div:GPR (match_dup 1) (match_dup 2)))]
3201 "reload_completed"
3202 [(set (match_dup 0)
3203 (div:<MODE> (match_dup 1) (match_dup 2)))
3204 (set (match_dup 3)
3205 (compare:CC (match_dup 0)
3206 (const_int 0)))]
3207 "")
3209 (define_insn ""
3210 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3211 (udiv:SI
3212 (plus:DI (ashift:DI
3213 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
3214 (const_int 32))
3215 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
3216 (match_operand:SI 3 "gpc_reg_operand" "r")))
3217 (set (match_operand:SI 2 "register_operand" "=*q")
3218 (umod:SI
3219 (plus:DI (ashift:DI
3220 (zero_extend:DI (match_dup 1)) (const_int 32))
3221 (zero_extend:DI (match_dup 4)))
3222 (match_dup 3)))]
3223 "TARGET_POWER"
3224 "div %0,%1,%3"
3225 [(set_attr "type" "idiv")])
3227 ;; To do unsigned divide we handle the cases of the divisor looking like a
3228 ;; negative number. If it is a constant that is less than 2**31, we don't
3229 ;; have to worry about the branches. So make a few subroutines here.
3230 ;;
3231 ;; First comes the normal case.
3232 (define_expand "udivmodsi4_normal"
3233 [(set (match_dup 4) (const_int 0))
3234 (parallel [(set (match_operand:SI 0 "" "")
3235 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3236 (const_int 32))
3237 (zero_extend:DI (match_operand:SI 1 "" "")))
3238 (match_operand:SI 2 "" "")))
3239 (set (match_operand:SI 3 "" "")
3240 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3241 (const_int 32))
3242 (zero_extend:DI (match_dup 1)))
3243 (match_dup 2)))])]
3244 "TARGET_POWER"
3245 "
3246 { operands[4] = gen_reg_rtx (SImode); }")
3248 ;; This handles the branches.
3249 (define_expand "udivmodsi4_tests"
3250 [(set (match_operand:SI 0 "" "") (const_int 0))
3251 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
3252 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
3253 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
3254 (label_ref (match_operand:SI 4 "" "")) (pc)))
3255 (set (match_dup 0) (const_int 1))
3256 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
3257 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
3258 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
3259 (label_ref (match_dup 4)) (pc)))]
3260 "TARGET_POWER"
3261 "
3262 { operands[5] = gen_reg_rtx (CCUNSmode);
3263 operands[6] = gen_reg_rtx (CCmode);
3264 }")
3266 (define_expand "udivmodsi4"
3267 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
3268 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
3269 (match_operand:SI 2 "reg_or_cint_operand" "")))
3270 (set (match_operand:SI 3 "gpc_reg_operand" "")
3271 (umod:SI (match_dup 1) (match_dup 2)))])]
3272 ""
3273 "
3274 {
3275 rtx label = 0;
3277 if (! TARGET_POWER)
3278 {
3279 if (! TARGET_POWERPC)
3280 {
3281 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
3282 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
3283 emit_insn (gen_divus_call ());
3284 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
3285 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
3286 DONE;
3287 }
3288 else
3289 FAIL;
3290 }
3292 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
3293 {
3294 operands[2] = force_reg (SImode, operands[2]);
3295 label = gen_label_rtx ();
3296 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
3297 operands[3], label));
3298 }
3299 else
3300 operands[2] = force_reg (SImode, operands[2]);
3302 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
3303 operands[3]));
3304 if (label)
3305 emit_label (label);
3307 DONE;
3308 }")
3310 ;; AIX architecture-independent common-mode multiply (DImode),
3311 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
3312 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
3313 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
3314 ;; assumed unused if generating common-mode, so ignore.
3315 (define_insn "mulh_call"
3316 [(set (reg:SI 3)
3317 (truncate:SI
3318 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
3319 (sign_extend:DI (reg:SI 4)))
3320 (const_int 32))))
3321 (clobber (reg:SI LR_REGNO))]
3322 "! TARGET_POWER && ! TARGET_POWERPC"
3323 "bla __mulh"
3324 [(set_attr "type" "imul")])
3326 (define_insn "mull_call"
3327 [(set (reg:DI 3)
3328 (mult:DI (sign_extend:DI (reg:SI 3))
3329 (sign_extend:DI (reg:SI 4))))
3330 (clobber (reg:SI LR_REGNO))
3331 (clobber (reg:SI 0))]
3332 "! TARGET_POWER && ! TARGET_POWERPC"
3333 "bla __mull"
3334 [(set_attr "type" "imul")])
3336 (define_insn "divss_call"
3337 [(set (reg:SI 3)
3338 (div:SI (reg:SI 3) (reg:SI 4)))
3339 (set (reg:SI 4)
3340 (mod:SI (reg:SI 3) (reg:SI 4)))
3341 (clobber (reg:SI LR_REGNO))
3342 (clobber (reg:SI 0))]
3343 "! TARGET_POWER && ! TARGET_POWERPC"
3344 "bla __divss"
3345 [(set_attr "type" "idiv")])
3347 (define_insn "divus_call"
3348 [(set (reg:SI 3)
3349 (udiv:SI (reg:SI 3) (reg:SI 4)))
3350 (set (reg:SI 4)
3351 (umod:SI (reg:SI 3) (reg:SI 4)))
3352 (clobber (reg:SI LR_REGNO))
3353 (clobber (reg:SI 0))
3354 (clobber (match_scratch:CC 0 "=x"))
3355 (clobber (reg:CC CR1_REGNO))]
3356 "! TARGET_POWER && ! TARGET_POWERPC"
3357 "bla __divus"
3358 [(set_attr "type" "idiv")])
3360 (define_insn "quoss_call"
3361 [(set (reg:SI 3)
3362 (div:SI (reg:SI 3) (reg:SI 4)))
3363 (clobber (reg:SI LR_REGNO))]
3364 "! TARGET_POWER && ! TARGET_POWERPC"
3365 "bla __quoss"
3366 [(set_attr "type" "idiv")])
3368 (define_insn "quous_call"
3369 [(set (reg:SI 3)
3370 (udiv:SI (reg:SI 3) (reg:SI 4)))
3371 (clobber (reg:SI LR_REGNO))
3372 (clobber (reg:SI 0))
3373 (clobber (match_scratch:CC 0 "=x"))
3374 (clobber (reg:CC CR1_REGNO))]
3375 "! TARGET_POWER && ! TARGET_POWERPC"
3376 "bla __quous"
3377 [(set_attr "type" "idiv")])
3378 \f
3379 ;; Logical instructions
3380 ;; The logical instructions are mostly combined by using match_operator,
3381 ;; but the plain AND insns are somewhat different because there is no
3382 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
3383 ;; those rotate-and-mask operations. Thus, the AND insns come first.
3385 (define_expand "andsi3"
3386 [(parallel
3387 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3388 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3389 (match_operand:SI 2 "and_operand" "")))
3390 (clobber (match_scratch:CC 3 ""))])]
3391 ""
3392 "")
3394 (define_insn "andsi3_mc"
3395 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3396 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
3397 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
3398 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
3399 "rs6000_gen_cell_microcode"
3400 "@
3401 and %0,%1,%2
3402 {rlinm|rlwinm} %0,%1,0,%m2,%M2
3403 {andil.|andi.} %0,%1,%b2
3404 {andiu.|andis.} %0,%1,%u2"
3405 [(set_attr "type" "*,*,fast_compare,fast_compare")])
3407 (define_insn "andsi3_nomc"
3408 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3409 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3410 (match_operand:SI 2 "and_operand" "?r,T")))
3411 (clobber (match_scratch:CC 3 "=X,X"))]
3412 "!rs6000_gen_cell_microcode"
3413 "@
3414 and %0,%1,%2
3415 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3417 (define_insn "andsi3_internal0_nomc"
3418 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3419 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3420 (match_operand:SI 2 "and_operand" "?r,T")))]
3421 "!rs6000_gen_cell_microcode"
3422 "@
3423 and %0,%1,%2
3424 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3427 ;; Note to set cr's other than cr0 we do the and immediate and then
3428 ;; the test again -- this avoids a mfcr which on the higher end
3429 ;; machines causes an execution serialization
3431 (define_insn "*andsi3_internal2_mc"
3432 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3433 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3434 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3435 (const_int 0)))
3436 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3437 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3438 "TARGET_32BIT && rs6000_gen_cell_microcode"
3439 "@
3440 and. %3,%1,%2
3441 {andil.|andi.} %3,%1,%b2
3442 {andiu.|andis.} %3,%1,%u2
3443 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3444 #
3445 #
3446 #
3447 #"
3448 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3449 compare,compare,compare,compare")
3450 (set_attr "length" "4,4,4,4,8,8,8,8")])
3452 (define_insn "*andsi3_internal3_mc"
3453 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3454 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3455 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3456 (const_int 0)))
3457 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3458 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3459 "TARGET_64BIT && rs6000_gen_cell_microcode"
3460 "@
3461 #
3462 {andil.|andi.} %3,%1,%b2
3463 {andiu.|andis.} %3,%1,%u2
3464 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3465 #
3466 #
3467 #
3468 #"
3469 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3470 compare,compare,compare")
3471 (set_attr "length" "8,4,4,4,8,8,8,8")])
3473 (define_split
3474 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3475 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3476 (match_operand:GPR 2 "and_operand" ""))
3477 (const_int 0)))
3478 (clobber (match_scratch:GPR 3 ""))
3479 (clobber (match_scratch:CC 4 ""))]
3480 "reload_completed"
3481 [(parallel [(set (match_dup 3)
3482 (and:<MODE> (match_dup 1)
3483 (match_dup 2)))
3484 (clobber (match_dup 4))])
3485 (set (match_dup 0)
3486 (compare:CC (match_dup 3)
3487 (const_int 0)))]
3488 "")
3490 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
3491 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
3493 (define_split
3494 [(set (match_operand:CC 0 "cc_reg_operand" "")
3495 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3496 (match_operand:SI 2 "gpc_reg_operand" ""))
3497 (const_int 0)))
3498 (clobber (match_scratch:SI 3 ""))
3499 (clobber (match_scratch:CC 4 ""))]
3500 "TARGET_POWERPC64 && reload_completed"
3501 [(parallel [(set (match_dup 3)
3502 (and:SI (match_dup 1)
3503 (match_dup 2)))
3504 (clobber (match_dup 4))])
3505 (set (match_dup 0)
3506 (compare:CC (match_dup 3)
3507 (const_int 0)))]
3508 "")
3510 (define_insn "*andsi3_internal4"
3511 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3512 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3513 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3514 (const_int 0)))
3515 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3516 (and:SI (match_dup 1)
3517 (match_dup 2)))
3518 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3519 "TARGET_32BIT && rs6000_gen_cell_microcode"
3520 "@
3521 and. %0,%1,%2
3522 {andil.|andi.} %0,%1,%b2
3523 {andiu.|andis.} %0,%1,%u2
3524 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3525 #
3526 #
3527 #
3528 #"
3529 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3530 compare,compare,compare,compare")
3531 (set_attr "length" "4,4,4,4,8,8,8,8")])
3533 (define_insn "*andsi3_internal5_mc"
3534 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3535 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3536 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3537 (const_int 0)))
3538 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3539 (and:SI (match_dup 1)
3540 (match_dup 2)))
3541 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3542 "TARGET_64BIT && rs6000_gen_cell_microcode"
3543 "@
3544 #
3545 {andil.|andi.} %0,%1,%b2
3546 {andiu.|andis.} %0,%1,%u2
3547 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3548 #
3549 #
3550 #
3551 #"
3552 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3553 compare,compare,compare")
3554 (set_attr "length" "8,4,4,4,8,8,8,8")])
3556 (define_split
3557 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3558 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3559 (match_operand:SI 2 "and_operand" ""))
3560 (const_int 0)))
3561 (set (match_operand:SI 0 "gpc_reg_operand" "")
3562 (and:SI (match_dup 1)
3563 (match_dup 2)))
3564 (clobber (match_scratch:CC 4 ""))]
3565 "reload_completed"
3566 [(parallel [(set (match_dup 0)
3567 (and:SI (match_dup 1)
3568 (match_dup 2)))
3569 (clobber (match_dup 4))])
3570 (set (match_dup 3)
3571 (compare:CC (match_dup 0)
3572 (const_int 0)))]
3573 "")
3575 (define_split
3576 [(set (match_operand:CC 3 "cc_reg_operand" "")
3577 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3578 (match_operand:SI 2 "gpc_reg_operand" ""))
3579 (const_int 0)))
3580 (set (match_operand:SI 0 "gpc_reg_operand" "")
3581 (and:SI (match_dup 1)
3582 (match_dup 2)))
3583 (clobber (match_scratch:CC 4 ""))]
3584 "TARGET_POWERPC64 && reload_completed"
3585 [(parallel [(set (match_dup 0)
3586 (and:SI (match_dup 1)
3587 (match_dup 2)))
3588 (clobber (match_dup 4))])
3589 (set (match_dup 3)
3590 (compare:CC (match_dup 0)
3591 (const_int 0)))]
3592 "")
3594 ;; Handle the PowerPC64 rlwinm corner case
3596 (define_insn_and_split "*andsi3_internal6"
3597 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3598 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3599 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3600 "TARGET_POWERPC64"
3601 "#"
3602 "TARGET_POWERPC64"
3603 [(set (match_dup 0)
3604 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3605 (match_dup 4)))
3606 (set (match_dup 0)
3607 (rotate:SI (match_dup 0) (match_dup 5)))]
3608 "
3609 {
3610 int mb = extract_MB (operands[2]);
3611 int me = extract_ME (operands[2]);
3612 operands[3] = GEN_INT (me + 1);
3613 operands[5] = GEN_INT (32 - (me + 1));
3614 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3615 }"
3616 [(set_attr "length" "8")])
3618 (define_expand "iorsi3"
3619 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3620 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3621 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3622 ""
3623 "
3624 {
3625 if (GET_CODE (operands[2]) == CONST_INT
3626 && ! logical_operand (operands[2], SImode))
3627 {
3628 HOST_WIDE_INT value = INTVAL (operands[2]);
3629 rtx tmp = ((!can_create_pseudo_p ()
3630 || rtx_equal_p (operands[0], operands[1]))
3631 ? operands[0] : gen_reg_rtx (SImode));
3633 emit_insn (gen_iorsi3 (tmp, operands[1],
3634 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3635 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3636 DONE;
3637 }
3638 }")
3640 (define_expand "xorsi3"
3641 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3642 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3643 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3644 ""
3645 "
3646 {
3647 if (GET_CODE (operands[2]) == CONST_INT
3648 && ! logical_operand (operands[2], SImode))
3649 {
3650 HOST_WIDE_INT value = INTVAL (operands[2]);
3651 rtx tmp = ((!can_create_pseudo_p ()
3652 || rtx_equal_p (operands[0], operands[1]))
3653 ? operands[0] : gen_reg_rtx (SImode));
3655 emit_insn (gen_xorsi3 (tmp, operands[1],
3656 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3657 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3658 DONE;
3659 }
3660 }")
3662 (define_insn "*boolsi3_internal1"
3663 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3664 (match_operator:SI 3 "boolean_or_operator"
3665 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3666 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3667 ""
3668 "@
3669 %q3 %0,%1,%2
3670 {%q3il|%q3i} %0,%1,%b2
3671 {%q3iu|%q3is} %0,%1,%u2")
3673 (define_insn "*boolsi3_internal2"
3674 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3675 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3676 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3677 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3678 (const_int 0)))
3679 (clobber (match_scratch:SI 3 "=r,r"))]
3680 "TARGET_32BIT"
3681 "@
3682 %q4. %3,%1,%2
3683 #"
3684 [(set_attr "type" "fast_compare,compare")
3685 (set_attr "length" "4,8")])
3687 (define_split
3688 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3689 (compare:CC (match_operator:SI 4 "boolean_operator"
3690 [(match_operand:SI 1 "gpc_reg_operand" "")
3691 (match_operand:SI 2 "gpc_reg_operand" "")])
3692 (const_int 0)))
3693 (clobber (match_scratch:SI 3 ""))]
3694 "TARGET_32BIT && reload_completed"
3695 [(set (match_dup 3) (match_dup 4))
3696 (set (match_dup 0)
3697 (compare:CC (match_dup 3)
3698 (const_int 0)))]
3699 "")
3701 (define_insn "*boolsi3_internal3"
3702 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3703 (compare:CC (match_operator:SI 4 "boolean_operator"
3704 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3705 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3706 (const_int 0)))
3707 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3708 (match_dup 4))]
3709 "TARGET_32BIT"
3710 "@
3711 %q4. %0,%1,%2
3712 #"
3713 [(set_attr "type" "fast_compare,compare")
3714 (set_attr "length" "4,8")])
3716 (define_split
3717 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3718 (compare:CC (match_operator:SI 4 "boolean_operator"
3719 [(match_operand:SI 1 "gpc_reg_operand" "")
3720 (match_operand:SI 2 "gpc_reg_operand" "")])
3721 (const_int 0)))
3722 (set (match_operand:SI 0 "gpc_reg_operand" "")
3723 (match_dup 4))]
3724 "TARGET_32BIT && reload_completed"
3725 [(set (match_dup 0) (match_dup 4))
3726 (set (match_dup 3)
3727 (compare:CC (match_dup 0)
3728 (const_int 0)))]
3729 "")
3731 ;; Split a logical operation that we can't do in one insn into two insns,
3732 ;; each of which does one 16-bit part. This is used by combine.
3734 (define_split
3735 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3736 (match_operator:SI 3 "boolean_or_operator"
3737 [(match_operand:SI 1 "gpc_reg_operand" "")
3738 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3739 ""
3740 [(set (match_dup 0) (match_dup 4))
3741 (set (match_dup 0) (match_dup 5))]
3742 "
3743 {
3744 rtx i;
3745 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3746 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3747 operands[1], i);
3748 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3749 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3750 operands[0], i);
3751 }")
3753 (define_insn "*boolcsi3_internal1"
3754 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3755 (match_operator:SI 3 "boolean_operator"
3756 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3757 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3758 ""
3759 "%q3 %0,%2,%1")
3761 (define_insn "*boolcsi3_internal2"
3762 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3763 (compare:CC (match_operator:SI 4 "boolean_operator"
3764 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3765 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3766 (const_int 0)))
3767 (clobber (match_scratch:SI 3 "=r,r"))]
3768 "TARGET_32BIT"
3769 "@
3770 %q4. %3,%2,%1
3771 #"
3772 [(set_attr "type" "compare")
3773 (set_attr "length" "4,8")])
3775 (define_split
3776 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3777 (compare:CC (match_operator:SI 4 "boolean_operator"
3778 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3779 (match_operand:SI 2 "gpc_reg_operand" "")])
3780 (const_int 0)))
3781 (clobber (match_scratch:SI 3 ""))]
3782 "TARGET_32BIT && reload_completed"
3783 [(set (match_dup 3) (match_dup 4))
3784 (set (match_dup 0)
3785 (compare:CC (match_dup 3)
3786 (const_int 0)))]
3787 "")
3789 (define_insn "*boolcsi3_internal3"
3790 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3791 (compare:CC (match_operator:SI 4 "boolean_operator"
3792 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3793 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3794 (const_int 0)))
3795 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3796 (match_dup 4))]
3797 "TARGET_32BIT"
3798 "@
3799 %q4. %0,%2,%1
3800 #"
3801 [(set_attr "type" "compare")
3802 (set_attr "length" "4,8")])
3804 (define_split
3805 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3806 (compare:CC (match_operator:SI 4 "boolean_operator"
3807 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3808 (match_operand:SI 2 "gpc_reg_operand" "")])
3809 (const_int 0)))
3810 (set (match_operand:SI 0 "gpc_reg_operand" "")
3811 (match_dup 4))]
3812 "TARGET_32BIT && reload_completed"
3813 [(set (match_dup 0) (match_dup 4))
3814 (set (match_dup 3)
3815 (compare:CC (match_dup 0)
3816 (const_int 0)))]
3817 "")
3819 (define_insn "*boolccsi3_internal1"
3820 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3821 (match_operator:SI 3 "boolean_operator"
3822 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3823 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3824 ""
3825 "%q3 %0,%1,%2")
3827 (define_insn "*boolccsi3_internal2"
3828 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3829 (compare:CC (match_operator:SI 4 "boolean_operator"
3830 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3831 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3832 (const_int 0)))
3833 (clobber (match_scratch:SI 3 "=r,r"))]
3834 "TARGET_32BIT"
3835 "@
3836 %q4. %3,%1,%2
3837 #"
3838 [(set_attr "type" "fast_compare,compare")
3839 (set_attr "length" "4,8")])
3841 (define_split
3842 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3843 (compare:CC (match_operator:SI 4 "boolean_operator"
3844 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3845 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3846 (const_int 0)))
3847 (clobber (match_scratch:SI 3 ""))]
3848 "TARGET_32BIT && reload_completed"
3849 [(set (match_dup 3) (match_dup 4))
3850 (set (match_dup 0)
3851 (compare:CC (match_dup 3)
3852 (const_int 0)))]
3853 "")
3855 (define_insn "*boolccsi3_internal3"
3856 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3857 (compare:CC (match_operator:SI 4 "boolean_operator"
3858 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3859 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3860 (const_int 0)))
3861 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3862 (match_dup 4))]
3863 "TARGET_32BIT"
3864 "@
3865 %q4. %0,%1,%2
3866 #"
3867 [(set_attr "type" "fast_compare,compare")
3868 (set_attr "length" "4,8")])
3870 (define_split
3871 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3872 (compare:CC (match_operator:SI 4 "boolean_operator"
3873 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3874 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3875 (const_int 0)))
3876 (set (match_operand:SI 0 "gpc_reg_operand" "")
3877 (match_dup 4))]
3878 "TARGET_32BIT && reload_completed"
3879 [(set (match_dup 0) (match_dup 4))
3880 (set (match_dup 3)
3881 (compare:CC (match_dup 0)
3882 (const_int 0)))]
3883 "")
3885 ;; maskir insn. We need four forms because things might be in arbitrary
3886 ;; orders. Don't define forms that only set CR fields because these
3887 ;; would modify an input register.
3889 (define_insn "*maskir_internal1"
3890 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3891 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3892 (match_operand:SI 1 "gpc_reg_operand" "0"))
3893 (and:SI (match_dup 2)
3894 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3895 "TARGET_POWER"
3896 "maskir %0,%3,%2")
3898 (define_insn "*maskir_internal2"
3899 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3900 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3901 (match_operand:SI 1 "gpc_reg_operand" "0"))
3902 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3903 (match_dup 2))))]
3904 "TARGET_POWER"
3905 "maskir %0,%3,%2")
3907 (define_insn "*maskir_internal3"
3908 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3909 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3910 (match_operand:SI 3 "gpc_reg_operand" "r"))
3911 (and:SI (not:SI (match_dup 2))
3912 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3913 "TARGET_POWER"
3914 "maskir %0,%3,%2")
3916 (define_insn "*maskir_internal4"
3917 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3918 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3919 (match_operand:SI 2 "gpc_reg_operand" "r"))
3920 (and:SI (not:SI (match_dup 2))
3921 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3922 "TARGET_POWER"
3923 "maskir %0,%3,%2")
3925 (define_insn "*maskir_internal5"
3926 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3927 (compare:CC
3928 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3929 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3930 (and:SI (match_dup 2)
3931 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3932 (const_int 0)))
3933 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3934 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3935 (and:SI (match_dup 2) (match_dup 3))))]
3936 "TARGET_POWER"
3937 "@
3938 maskir. %0,%3,%2
3939 #"
3940 [(set_attr "type" "compare")
3941 (set_attr "length" "4,8")])
3943 (define_split
3944 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3945 (compare:CC
3946 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3947 (match_operand:SI 1 "gpc_reg_operand" ""))
3948 (and:SI (match_dup 2)
3949 (match_operand:SI 3 "gpc_reg_operand" "")))
3950 (const_int 0)))
3951 (set (match_operand:SI 0 "gpc_reg_operand" "")
3952 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3953 (and:SI (match_dup 2) (match_dup 3))))]
3954 "TARGET_POWER && reload_completed"
3955 [(set (match_dup 0)
3956 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3957 (and:SI (match_dup 2) (match_dup 3))))
3958 (set (match_dup 4)
3959 (compare:CC (match_dup 0)
3960 (const_int 0)))]
3961 "")
3963 (define_insn "*maskir_internal6"
3964 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3965 (compare:CC
3966 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3967 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3968 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3969 (match_dup 2)))
3970 (const_int 0)))
3971 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3972 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3973 (and:SI (match_dup 3) (match_dup 2))))]
3974 "TARGET_POWER"
3975 "@
3976 maskir. %0,%3,%2
3977 #"
3978 [(set_attr "type" "compare")
3979 (set_attr "length" "4,8")])
3981 (define_split
3982 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3983 (compare:CC
3984 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3985 (match_operand:SI 1 "gpc_reg_operand" ""))
3986 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3987 (match_dup 2)))
3988 (const_int 0)))
3989 (set (match_operand:SI 0 "gpc_reg_operand" "")
3990 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3991 (and:SI (match_dup 3) (match_dup 2))))]
3992 "TARGET_POWER && reload_completed"
3993 [(set (match_dup 0)
3994 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3995 (and:SI (match_dup 3) (match_dup 2))))
3996 (set (match_dup 4)
3997 (compare:CC (match_dup 0)
3998 (const_int 0)))]
3999 "")
4001 (define_insn "*maskir_internal7"
4002 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4003 (compare:CC
4004 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
4005 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
4006 (and:SI (not:SI (match_dup 2))
4007 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
4008 (const_int 0)))
4009 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4010 (ior:SI (and:SI (match_dup 2) (match_dup 3))
4011 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
4012 "TARGET_POWER"
4013 "@
4014 maskir. %0,%3,%2
4015 #"
4016 [(set_attr "type" "compare")
4017 (set_attr "length" "4,8")])
4019 (define_split
4020 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4021 (compare:CC
4022 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
4023 (match_operand:SI 3 "gpc_reg_operand" ""))
4024 (and:SI (not:SI (match_dup 2))
4025 (match_operand:SI 1 "gpc_reg_operand" "")))
4026 (const_int 0)))
4027 (set (match_operand:SI 0 "gpc_reg_operand" "")
4028 (ior:SI (and:SI (match_dup 2) (match_dup 3))
4029 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
4030 "TARGET_POWER && reload_completed"
4031 [(set (match_dup 0)
4032 (ior:SI (and:SI (match_dup 2) (match_dup 3))
4033 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
4034 (set (match_dup 4)
4035 (compare:CC (match_dup 0)
4036 (const_int 0)))]
4037 "")
4039 (define_insn "*maskir_internal8"
4040 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4041 (compare:CC
4042 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
4043 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
4044 (and:SI (not:SI (match_dup 2))
4045 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
4046 (const_int 0)))
4047 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4048 (ior:SI (and:SI (match_dup 3) (match_dup 2))
4049 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
4050 "TARGET_POWER"
4051 "@
4052 maskir. %0,%3,%2
4053 #"
4054 [(set_attr "type" "compare")
4055 (set_attr "length" "4,8")])
4057 (define_split
4058 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4059 (compare:CC
4060 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
4061 (match_operand:SI 2 "gpc_reg_operand" ""))
4062 (and:SI (not:SI (match_dup 2))
4063 (match_operand:SI 1 "gpc_reg_operand" "")))
4064 (const_int 0)))
4065 (set (match_operand:SI 0 "gpc_reg_operand" "")
4066 (ior:SI (and:SI (match_dup 3) (match_dup 2))
4067 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
4068 "TARGET_POWER && reload_completed"
4069 [(set (match_dup 0)
4070 (ior:SI (and:SI (match_dup 3) (match_dup 2))
4071 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
4072 (set (match_dup 4)
4073 (compare:CC (match_dup 0)
4074 (const_int 0)))]
4075 "")
4076 \f
4077 ;; Rotate and shift insns, in all their variants. These support shifts,
4078 ;; field inserts and extracts, and various combinations thereof.
4079 (define_expand "insv"
4080 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
4081 (match_operand:SI 1 "const_int_operand" "")
4082 (match_operand:SI 2 "const_int_operand" ""))
4083 (match_operand 3 "gpc_reg_operand" ""))]
4084 ""
4085 "
4086 {
4087 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
4088 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
4089 compiler if the address of the structure is taken later. Likewise, do
4090 not handle invalid E500 subregs. */
4091 if (GET_CODE (operands[0]) == SUBREG
4092 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
4093 || ((TARGET_E500_DOUBLE || TARGET_SPE)
4094 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
4095 FAIL;
4097 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
4098 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
4099 else
4100 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
4101 DONE;
4102 }")
4104 (define_insn "insvsi"
4105 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4106 (match_operand:SI 1 "const_int_operand" "i")
4107 (match_operand:SI 2 "const_int_operand" "i"))
4108 (match_operand:SI 3 "gpc_reg_operand" "r"))]
4109 ""
4110 "*
4111 {
4112 int start = INTVAL (operands[2]) & 31;
4113 int size = INTVAL (operands[1]) & 31;
4115 operands[4] = GEN_INT (32 - start - size);
4116 operands[1] = GEN_INT (start + size - 1);
4117 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4118 }"
4119 [(set_attr "type" "insert_word")])
4121 (define_insn "*insvsi_internal1"
4122 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4123 (match_operand:SI 1 "const_int_operand" "i")
4124 (match_operand:SI 2 "const_int_operand" "i"))
4125 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4126 (match_operand:SI 4 "const_int_operand" "i")))]
4127 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4128 "*
4129 {
4130 int shift = INTVAL (operands[4]) & 31;
4131 int start = INTVAL (operands[2]) & 31;
4132 int size = INTVAL (operands[1]) & 31;
4134 operands[4] = GEN_INT (shift - start - size);
4135 operands[1] = GEN_INT (start + size - 1);
4136 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4137 }"
4138 [(set_attr "type" "insert_word")])
4140 (define_insn "*insvsi_internal2"
4141 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4142 (match_operand:SI 1 "const_int_operand" "i")
4143 (match_operand:SI 2 "const_int_operand" "i"))
4144 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4145 (match_operand:SI 4 "const_int_operand" "i")))]
4146 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4147 "*
4148 {
4149 int shift = INTVAL (operands[4]) & 31;
4150 int start = INTVAL (operands[2]) & 31;
4151 int size = INTVAL (operands[1]) & 31;
4153 operands[4] = GEN_INT (32 - shift - start - size);
4154 operands[1] = GEN_INT (start + size - 1);
4155 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4156 }"
4157 [(set_attr "type" "insert_word")])
4159 (define_insn "*insvsi_internal3"
4160 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4161 (match_operand:SI 1 "const_int_operand" "i")
4162 (match_operand:SI 2 "const_int_operand" "i"))
4163 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4164 (match_operand:SI 4 "const_int_operand" "i")))]
4165 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4166 "*
4167 {
4168 int shift = INTVAL (operands[4]) & 31;
4169 int start = INTVAL (operands[2]) & 31;
4170 int size = INTVAL (operands[1]) & 31;
4172 operands[4] = GEN_INT (32 - shift - start - size);
4173 operands[1] = GEN_INT (start + size - 1);
4174 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4175 }"
4176 [(set_attr "type" "insert_word")])
4178 (define_insn "*insvsi_internal4"
4179 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4180 (match_operand:SI 1 "const_int_operand" "i")
4181 (match_operand:SI 2 "const_int_operand" "i"))
4182 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4183 (match_operand:SI 4 "const_int_operand" "i")
4184 (match_operand:SI 5 "const_int_operand" "i")))]
4185 "INTVAL (operands[4]) >= INTVAL (operands[1])"
4186 "*
4187 {
4188 int extract_start = INTVAL (operands[5]) & 31;
4189 int extract_size = INTVAL (operands[4]) & 31;
4190 int insert_start = INTVAL (operands[2]) & 31;
4191 int insert_size = INTVAL (operands[1]) & 31;
4193 /* Align extract field with insert field */
4194 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
4195 operands[1] = GEN_INT (insert_start + insert_size - 1);
4196 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
4197 }"
4198 [(set_attr "type" "insert_word")])
4200 ;; combine patterns for rlwimi
4201 (define_insn "*insvsi_internal5"
4202 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4203 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4204 (match_operand:SI 1 "mask_operand" "i"))
4205 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4206 (match_operand:SI 2 "const_int_operand" "i"))
4207 (match_operand:SI 5 "mask_operand" "i"))))]
4208 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4209 "*
4210 {
4211 int me = extract_ME(operands[5]);
4212 int mb = extract_MB(operands[5]);
4213 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4214 operands[2] = GEN_INT(mb);
4215 operands[1] = GEN_INT(me);
4216 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4217 }"
4218 [(set_attr "type" "insert_word")])
4220 (define_insn "*insvsi_internal6"
4221 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4222 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4223 (match_operand:SI 2 "const_int_operand" "i"))
4224 (match_operand:SI 5 "mask_operand" "i"))
4225 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4226 (match_operand:SI 1 "mask_operand" "i"))))]
4227 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4228 "*
4229 {
4230 int me = extract_ME(operands[5]);
4231 int mb = extract_MB(operands[5]);
4232 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4233 operands[2] = GEN_INT(mb);
4234 operands[1] = GEN_INT(me);
4235 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4236 }"
4237 [(set_attr "type" "insert_word")])
4239 (define_insn "insvdi"
4240 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4241 (match_operand:SI 1 "const_int_operand" "i")
4242 (match_operand:SI 2 "const_int_operand" "i"))
4243 (match_operand:DI 3 "gpc_reg_operand" "r"))]
4244 "TARGET_POWERPC64"
4245 "*
4246 {
4247 int start = INTVAL (operands[2]) & 63;
4248 int size = INTVAL (operands[1]) & 63;
4250 operands[1] = GEN_INT (64 - start - size);
4251 return \"rldimi %0,%3,%H1,%H2\";
4252 }"
4253 [(set_attr "type" "insert_dword")])
4255 (define_insn "*insvdi_internal2"
4256 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4257 (match_operand:SI 1 "const_int_operand" "i")
4258 (match_operand:SI 2 "const_int_operand" "i"))
4259 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4260 (match_operand:SI 4 "const_int_operand" "i")))]
4261 "TARGET_POWERPC64
4262 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4263 "*
4264 {
4265 int shift = INTVAL (operands[4]) & 63;
4266 int start = (INTVAL (operands[2]) & 63) - 32;
4267 int size = INTVAL (operands[1]) & 63;
4269 operands[4] = GEN_INT (64 - shift - start - size);
4270 operands[2] = GEN_INT (start);
4271 operands[1] = GEN_INT (start + size - 1);
4272 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4273 }")
4275 (define_insn "*insvdi_internal3"
4276 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4277 (match_operand:SI 1 "const_int_operand" "i")
4278 (match_operand:SI 2 "const_int_operand" "i"))
4279 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4280 (match_operand:SI 4 "const_int_operand" "i")))]
4281 "TARGET_POWERPC64
4282 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4283 "*
4284 {
4285 int shift = INTVAL (operands[4]) & 63;
4286 int start = (INTVAL (operands[2]) & 63) - 32;
4287 int size = INTVAL (operands[1]) & 63;
4289 operands[4] = GEN_INT (64 - shift - start - size);
4290 operands[2] = GEN_INT (start);
4291 operands[1] = GEN_INT (start + size - 1);
4292 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4293 }")
4295 (define_expand "extzv"
4296 [(set (match_operand 0 "gpc_reg_operand" "")
4297 (zero_extract (match_operand 1 "gpc_reg_operand" "")
4298 (match_operand:SI 2 "const_int_operand" "")
4299 (match_operand:SI 3 "const_int_operand" "")))]
4300 ""
4301 "
4302 {
4303 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
4304 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
4305 compiler if the address of the structure is taken later. */
4306 if (GET_CODE (operands[0]) == SUBREG
4307 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
4308 FAIL;
4310 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
4311 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
4312 else
4313 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
4314 DONE;
4315 }")
4317 (define_insn "extzvsi"
4318 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4319 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4320 (match_operand:SI 2 "const_int_operand" "i")
4321 (match_operand:SI 3 "const_int_operand" "i")))]
4322 ""
4323 "*
4324 {
4325 int start = INTVAL (operands[3]) & 31;
4326 int size = INTVAL (operands[2]) & 31;
4328 if (start + size >= 32)
4329 operands[3] = const0_rtx;
4330 else
4331 operands[3] = GEN_INT (start + size);
4332 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
4333 }")
4335 (define_insn "*extzvsi_internal1"
4336 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4337 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4338 (match_operand:SI 2 "const_int_operand" "i,i")
4339 (match_operand:SI 3 "const_int_operand" "i,i"))
4340 (const_int 0)))
4341 (clobber (match_scratch:SI 4 "=r,r"))]
4342 ""
4343 "*
4344 {
4345 int start = INTVAL (operands[3]) & 31;
4346 int size = INTVAL (operands[2]) & 31;
4348 /* Force split for non-cc0 compare. */
4349 if (which_alternative == 1)
4350 return \"#\";
4352 /* If the bit-field being tested fits in the upper or lower half of a
4353 word, it is possible to use andiu. or andil. to test it. This is
4354 useful because the condition register set-use delay is smaller for
4355 andi[ul]. than for rlinm. This doesn't work when the starting bit
4356 position is 0 because the LT and GT bits may be set wrong. */
4358 if ((start > 0 && start + size <= 16) || start >= 16)
4359 {
4360 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
4361 - (1 << (16 - (start & 15) - size))));
4362 if (start < 16)
4363 return \"{andiu.|andis.} %4,%1,%3\";
4364 else
4365 return \"{andil.|andi.} %4,%1,%3\";
4366 }
4368 if (start + size >= 32)
4369 operands[3] = const0_rtx;
4370 else
4371 operands[3] = GEN_INT (start + size);
4372 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
4373 }"
4374 [(set_attr "type" "delayed_compare")
4375 (set_attr "length" "4,8")])
4377 (define_split
4378 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4379 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4380 (match_operand:SI 2 "const_int_operand" "")
4381 (match_operand:SI 3 "const_int_operand" ""))
4382 (const_int 0)))
4383 (clobber (match_scratch:SI 4 ""))]
4384 "reload_completed"
4385 [(set (match_dup 4)
4386 (zero_extract:SI (match_dup 1) (match_dup 2)
4387 (match_dup 3)))
4388 (set (match_dup 0)
4389 (compare:CC (match_dup 4)
4390 (const_int 0)))]
4391 "")
4393 (define_insn "*extzvsi_internal2"
4394 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4395 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4396 (match_operand:SI 2 "const_int_operand" "i,i")
4397 (match_operand:SI 3 "const_int_operand" "i,i"))
4398 (const_int 0)))
4399 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4400 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4401 ""
4402 "*
4403 {
4404 int start = INTVAL (operands[3]) & 31;
4405 int size = INTVAL (operands[2]) & 31;
4407 /* Force split for non-cc0 compare. */
4408 if (which_alternative == 1)
4409 return \"#\";
4411 /* Since we are using the output value, we can't ignore any need for
4412 a shift. The bit-field must end at the LSB. */
4413 if (start >= 16 && start + size == 32)
4414 {
4415 operands[3] = GEN_INT ((1 << size) - 1);
4416 return \"{andil.|andi.} %0,%1,%3\";
4417 }
4419 if (start + size >= 32)
4420 operands[3] = const0_rtx;
4421 else
4422 operands[3] = GEN_INT (start + size);
4423 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
4424 }"
4425 [(set_attr "type" "delayed_compare")
4426 (set_attr "length" "4,8")])
4428 (define_split
4429 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4430 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4431 (match_operand:SI 2 "const_int_operand" "")
4432 (match_operand:SI 3 "const_int_operand" ""))
4433 (const_int 0)))
4434 (set (match_operand:SI 0 "gpc_reg_operand" "")
4435 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4436 "reload_completed"
4437 [(set (match_dup 0)
4438 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
4439 (set (match_dup 4)
4440 (compare:CC (match_dup 0)
4441 (const_int 0)))]
4442 "")
4444 (define_insn "extzvdi"
4445 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4446 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4447 (match_operand:SI 2 "const_int_operand" "i")
4448 (match_operand:SI 3 "const_int_operand" "i")))]
4449 "TARGET_POWERPC64"
4450 "*
4451 {
4452 int start = INTVAL (operands[3]) & 63;
4453 int size = INTVAL (operands[2]) & 63;
4455 if (start + size >= 64)
4456 operands[3] = const0_rtx;
4457 else
4458 operands[3] = GEN_INT (start + size);
4459 operands[2] = GEN_INT (64 - size);
4460 return \"rldicl %0,%1,%3,%2\";
4461 }")
4463 (define_insn "*extzvdi_internal1"
4464 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
4465 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4466 (match_operand:SI 2 "const_int_operand" "i")
4467 (match_operand:SI 3 "const_int_operand" "i"))
4468 (const_int 0)))
4469 (clobber (match_scratch:DI 4 "=r"))]
4470 "TARGET_64BIT && rs6000_gen_cell_microcode"
4471 "*
4472 {
4473 int start = INTVAL (operands[3]) & 63;
4474 int size = INTVAL (operands[2]) & 63;
4476 if (start + size >= 64)
4477 operands[3] = const0_rtx;
4478 else
4479 operands[3] = GEN_INT (start + size);
4480 operands[2] = GEN_INT (64 - size);
4481 return \"rldicl. %4,%1,%3,%2\";
4482 }"
4483 [(set_attr "type" "compare")])
4485 (define_insn "*extzvdi_internal2"
4486 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
4487 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4488 (match_operand:SI 2 "const_int_operand" "i")
4489 (match_operand:SI 3 "const_int_operand" "i"))
4490 (const_int 0)))
4491 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4492 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
4493 "TARGET_64BIT && rs6000_gen_cell_microcode"
4494 "*
4495 {
4496 int start = INTVAL (operands[3]) & 63;
4497 int size = INTVAL (operands[2]) & 63;
4499 if (start + size >= 64)
4500 operands[3] = const0_rtx;
4501 else
4502 operands[3] = GEN_INT (start + size);
4503 operands[2] = GEN_INT (64 - size);
4504 return \"rldicl. %0,%1,%3,%2\";
4505 }"
4506 [(set_attr "type" "compare")])
4508 (define_insn "rotlsi3"
4509 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4510 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4511 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4512 ""
4513 "@
4514 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4515 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4516 [(set_attr "type" "var_shift_rotate,integer")])
4518 (define_insn "*rotlsi3_64"
4519 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4520 (zero_extend:DI
4521 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4522 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4523 "TARGET_64BIT"
4524 "@
4525 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4526 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4527 [(set_attr "type" "var_shift_rotate,integer")])
4529 (define_insn "*rotlsi3_internal2"
4530 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4531 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4532 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4533 (const_int 0)))
4534 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4535 ""
4536 "@
4537 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
4538 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
4539 #
4540 #"
4541 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4542 (set_attr "length" "4,4,8,8")])
4544 (define_split
4545 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4546 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4547 (match_operand:SI 2 "reg_or_cint_operand" ""))
4548 (const_int 0)))
4549 (clobber (match_scratch:SI 3 ""))]
4550 "reload_completed"
4551 [(set (match_dup 3)
4552 (rotate:SI (match_dup 1) (match_dup 2)))
4553 (set (match_dup 0)
4554 (compare:CC (match_dup 3)
4555 (const_int 0)))]
4556 "")
4558 (define_insn "*rotlsi3_internal3"
4559 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4560 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4561 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4562 (const_int 0)))
4563 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4564 (rotate:SI (match_dup 1) (match_dup 2)))]
4565 ""
4566 "@
4567 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
4568 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
4569 #
4570 #"
4571 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4572 (set_attr "length" "4,4,8,8")])
4574 (define_split
4575 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4576 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4577 (match_operand:SI 2 "reg_or_cint_operand" ""))
4578 (const_int 0)))
4579 (set (match_operand:SI 0 "gpc_reg_operand" "")
4580 (rotate:SI (match_dup 1) (match_dup 2)))]
4581 "reload_completed"
4582 [(set (match_dup 0)
4583 (rotate:SI (match_dup 1) (match_dup 2)))
4584 (set (match_dup 3)
4585 (compare:CC (match_dup 0)
4586 (const_int 0)))]
4587 "")
4589 (define_insn "*rotlsi3_internal4"
4590 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4591 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4592 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
4593 (match_operand:SI 3 "mask_operand" "n,n")))]
4594 ""
4595 "@
4596 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
4597 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
4598 [(set_attr "type" "var_shift_rotate,integer")])
4600 (define_insn "*rotlsi3_internal5"
4601 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4602 (compare:CC (and:SI
4603 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4604 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4605 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4606 (const_int 0)))
4607 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
4608 ""
4609 "@
4610 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
4611 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4612 #
4613 #"
4614 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4615 (set_attr "length" "4,4,8,8")])
4617 (define_split
4618 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4619 (compare:CC (and:SI
4620 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4621 (match_operand:SI 2 "reg_or_cint_operand" ""))
4622 (match_operand:SI 3 "mask_operand" ""))
4623 (const_int 0)))
4624 (clobber (match_scratch:SI 4 ""))]
4625 "reload_completed"
4626 [(set (match_dup 4)
4627 (and:SI (rotate:SI (match_dup 1)
4628 (match_dup 2))
4629 (match_dup 3)))
4630 (set (match_dup 0)
4631 (compare:CC (match_dup 4)
4632 (const_int 0)))]
4633 "")
4635 (define_insn "*rotlsi3_internal6"
4636 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
4637 (compare:CC (and:SI
4638 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4639 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4640 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4641 (const_int 0)))
4642 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4643 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4644 ""
4645 "@
4646 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4647 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4648 #
4649 #"
4650 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4651 (set_attr "length" "4,4,8,8")])
4653 (define_split
4654 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4655 (compare:CC (and:SI
4656 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4657 (match_operand:SI 2 "reg_or_cint_operand" ""))
4658 (match_operand:SI 3 "mask_operand" ""))
4659 (const_int 0)))
4660 (set (match_operand:SI 0 "gpc_reg_operand" "")
4661 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4662 "reload_completed"
4663 [(set (match_dup 0)
4664 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4665 (set (match_dup 4)
4666 (compare:CC (match_dup 0)
4667 (const_int 0)))]
4668 "")
4670 (define_insn "*rotlsi3_internal7"
4671 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4672 (zero_extend:SI
4673 (subreg:QI
4674 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4675 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4676 ""
4677 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff"
4678 [(set (attr "cell_micro")
4679 (if_then_else (match_operand:SI 2 "const_int_operand" "")
4680 (const_string "not")
4681 (const_string "always")))])
4683 (define_insn "*rotlsi3_internal8"
4684 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4685 (compare:CC (zero_extend:SI
4686 (subreg:QI
4687 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4688 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4689 (const_int 0)))
4690 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4691 ""
4692 "@
4693 {rlnm.|rlwnm.} %3,%1,%2,0xff
4694 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4695 #
4696 #"
4697 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4698 (set_attr "length" "4,4,8,8")])
4700 (define_split
4701 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4702 (compare:CC (zero_extend:SI
4703 (subreg:QI
4704 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4705 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4706 (const_int 0)))
4707 (clobber (match_scratch:SI 3 ""))]
4708 "reload_completed"
4709 [(set (match_dup 3)
4710 (zero_extend:SI (subreg:QI
4711 (rotate:SI (match_dup 1)
4712 (match_dup 2)) 0)))
4713 (set (match_dup 0)
4714 (compare:CC (match_dup 3)
4715 (const_int 0)))]
4716 "")
4718 (define_insn "*rotlsi3_internal9"
4719 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4720 (compare:CC (zero_extend:SI
4721 (subreg:QI
4722 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4723 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4724 (const_int 0)))
4725 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4726 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4727 ""
4728 "@
4729 {rlnm.|rlwnm.} %0,%1,%2,0xff
4730 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4731 #
4732 #"
4733 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4734 (set_attr "length" "4,4,8,8")])
4736 (define_split
4737 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4738 (compare:CC (zero_extend:SI
4739 (subreg:QI
4740 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4741 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4742 (const_int 0)))
4743 (set (match_operand:SI 0 "gpc_reg_operand" "")
4744 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4745 "reload_completed"
4746 [(set (match_dup 0)
4747 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4748 (set (match_dup 3)
4749 (compare:CC (match_dup 0)
4750 (const_int 0)))]
4751 "")
4753 (define_insn "*rotlsi3_internal10"
4754 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4755 (zero_extend:SI
4756 (subreg:HI
4757 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4758 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4759 ""
4760 "@
4761 {rlnm|rlwnm} %0,%1,%2,0xffff
4762 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4763 [(set_attr "type" "var_shift_rotate,integer")])
4766 (define_insn "*rotlsi3_internal11"
4767 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4768 (compare:CC (zero_extend:SI
4769 (subreg:HI
4770 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4771 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4772 (const_int 0)))
4773 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4774 ""
4775 "@
4776 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4777 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4778 #
4779 #"
4780 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4781 (set_attr "length" "4,4,8,8")])
4783 (define_split
4784 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4785 (compare:CC (zero_extend:SI
4786 (subreg:HI
4787 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4788 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4789 (const_int 0)))
4790 (clobber (match_scratch:SI 3 ""))]
4791 "reload_completed"
4792 [(set (match_dup 3)
4793 (zero_extend:SI (subreg:HI
4794 (rotate:SI (match_dup 1)
4795 (match_dup 2)) 0)))
4796 (set (match_dup 0)
4797 (compare:CC (match_dup 3)
4798 (const_int 0)))]
4799 "")
4801 (define_insn "*rotlsi3_internal12"
4802 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4803 (compare:CC (zero_extend:SI
4804 (subreg:HI
4805 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4806 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4807 (const_int 0)))
4808 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4809 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4810 ""
4811 "@
4812 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4813 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4814 #
4815 #"
4816 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4817 (set_attr "length" "4,4,8,8")])
4819 (define_split
4820 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4821 (compare:CC (zero_extend:SI
4822 (subreg:HI
4823 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4824 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4825 (const_int 0)))
4826 (set (match_operand:SI 0 "gpc_reg_operand" "")
4827 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4828 "reload_completed"
4829 [(set (match_dup 0)
4830 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4831 (set (match_dup 3)
4832 (compare:CC (match_dup 0)
4833 (const_int 0)))]
4834 "")
4836 ;; Note that we use "sle." instead of "sl." so that we can set
4837 ;; SHIFT_COUNT_TRUNCATED.
4839 (define_expand "ashlsi3"
4840 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4841 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4842 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4843 ""
4844 "
4845 {
4846 if (TARGET_POWER)
4847 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4848 else
4849 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4850 DONE;
4851 }")
4853 (define_insn "ashlsi3_power"
4854 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4855 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4856 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4857 (clobber (match_scratch:SI 3 "=q,X"))]
4858 "TARGET_POWER"
4859 "@
4860 sle %0,%1,%2
4861 {sli|slwi} %0,%1,%h2")
4863 (define_insn "ashlsi3_no_power"
4864 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4865 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4866 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4867 "! TARGET_POWER"
4868 "@
4869 {sl|slw} %0,%1,%2
4870 {sli|slwi} %0,%1,%h2"
4871 [(set_attr "type" "var_shift_rotate,shift")])
4873 (define_insn "*ashlsi3_64"
4874 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4875 (zero_extend:DI
4876 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4877 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4878 "TARGET_POWERPC64"
4879 "@
4880 {sl|slw} %0,%1,%2
4881 {sli|slwi} %0,%1,%h2"
4882 [(set_attr "type" "var_shift_rotate,shift")])
4884 (define_insn ""
4885 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4886 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4887 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4888 (const_int 0)))
4889 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4890 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4891 "TARGET_POWER"
4892 "@
4893 sle. %3,%1,%2
4894 {sli.|slwi.} %3,%1,%h2
4895 #
4896 #"
4897 [(set_attr "type" "delayed_compare")
4898 (set_attr "length" "4,4,8,8")])
4900 (define_split
4901 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4902 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4903 (match_operand:SI 2 "reg_or_cint_operand" ""))
4904 (const_int 0)))
4905 (clobber (match_scratch:SI 3 ""))
4906 (clobber (match_scratch:SI 4 ""))]
4907 "TARGET_POWER && reload_completed"
4908 [(parallel [(set (match_dup 3)
4909 (ashift:SI (match_dup 1) (match_dup 2)))
4910 (clobber (match_dup 4))])
4911 (set (match_dup 0)
4912 (compare:CC (match_dup 3)
4913 (const_int 0)))]
4914 "")
4916 (define_insn ""
4917 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4918 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4919 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4920 (const_int 0)))
4921 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4922 "! TARGET_POWER && TARGET_32BIT"
4923 "@
4924 {sl.|slw.} %3,%1,%2
4925 {sli.|slwi.} %3,%1,%h2
4926 #
4927 #"
4928 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4929 (set_attr "length" "4,4,8,8")])
4931 (define_split
4932 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4933 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4934 (match_operand:SI 2 "reg_or_cint_operand" ""))
4935 (const_int 0)))
4936 (clobber (match_scratch:SI 3 ""))]
4937 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4938 [(set (match_dup 3)
4939 (ashift:SI (match_dup 1) (match_dup 2)))
4940 (set (match_dup 0)
4941 (compare:CC (match_dup 3)
4942 (const_int 0)))]
4943 "")
4945 (define_insn ""
4946 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4947 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4948 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4949 (const_int 0)))
4950 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4951 (ashift:SI (match_dup 1) (match_dup 2)))
4952 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4953 "TARGET_POWER"
4954 "@
4955 sle. %0,%1,%2
4956 {sli.|slwi.} %0,%1,%h2
4957 #
4958 #"
4959 [(set_attr "type" "delayed_compare")
4960 (set_attr "length" "4,4,8,8")])
4962 (define_split
4963 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4964 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4965 (match_operand:SI 2 "reg_or_cint_operand" ""))
4966 (const_int 0)))
4967 (set (match_operand:SI 0 "gpc_reg_operand" "")
4968 (ashift:SI (match_dup 1) (match_dup 2)))
4969 (clobber (match_scratch:SI 4 ""))]
4970 "TARGET_POWER && reload_completed"
4971 [(parallel [(set (match_dup 0)
4972 (ashift:SI (match_dup 1) (match_dup 2)))
4973 (clobber (match_dup 4))])
4974 (set (match_dup 3)
4975 (compare:CC (match_dup 0)
4976 (const_int 0)))]
4977 "")
4979 (define_insn ""
4980 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4981 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4982 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4983 (const_int 0)))
4984 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4985 (ashift:SI (match_dup 1) (match_dup 2)))]
4986 "! TARGET_POWER && TARGET_32BIT"
4987 "@
4988 {sl.|slw.} %0,%1,%2
4989 {sli.|slwi.} %0,%1,%h2
4990 #
4991 #"
4992 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4993 (set_attr "length" "4,4,8,8")])
4995 (define_split
4996 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4997 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4998 (match_operand:SI 2 "reg_or_cint_operand" ""))
4999 (const_int 0)))
5000 (set (match_operand:SI 0 "gpc_reg_operand" "")
5001 (ashift:SI (match_dup 1) (match_dup 2)))]
5002 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5003 [(set (match_dup 0)
5004 (ashift:SI (match_dup 1) (match_dup 2)))
5005 (set (match_dup 3)
5006 (compare:CC (match_dup 0)
5007 (const_int 0)))]
5008 "")
5010 (define_insn "rlwinm"
5011 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5012 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5013 (match_operand:SI 2 "const_int_operand" "i"))
5014 (match_operand:SI 3 "mask_operand" "n")))]
5015 "includes_lshift_p (operands[2], operands[3])"
5016 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
5018 (define_insn ""
5019 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5020 (compare:CC
5021 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5022 (match_operand:SI 2 "const_int_operand" "i,i"))
5023 (match_operand:SI 3 "mask_operand" "n,n"))
5024 (const_int 0)))
5025 (clobber (match_scratch:SI 4 "=r,r"))]
5026 "includes_lshift_p (operands[2], operands[3])"
5027 "@
5028 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
5029 #"
5030 [(set_attr "type" "delayed_compare")
5031 (set_attr "length" "4,8")])
5033 (define_split
5034 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5035 (compare:CC
5036 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
5037 (match_operand:SI 2 "const_int_operand" ""))
5038 (match_operand:SI 3 "mask_operand" ""))
5039 (const_int 0)))
5040 (clobber (match_scratch:SI 4 ""))]
5041 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
5042 [(set (match_dup 4)
5043 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
5044 (match_dup 3)))
5045 (set (match_dup 0)
5046 (compare:CC (match_dup 4)
5047 (const_int 0)))]
5048 "")
5050 (define_insn ""
5051 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
5052 (compare:CC
5053 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5054 (match_operand:SI 2 "const_int_operand" "i,i"))
5055 (match_operand:SI 3 "mask_operand" "n,n"))
5056 (const_int 0)))
5057 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5058 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5059 "includes_lshift_p (operands[2], operands[3])"
5060 "@
5061 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
5062 #"
5063 [(set_attr "type" "delayed_compare")
5064 (set_attr "length" "4,8")])
5066 (define_split
5067 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
5068 (compare:CC
5069 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
5070 (match_operand:SI 2 "const_int_operand" ""))
5071 (match_operand:SI 3 "mask_operand" ""))
5072 (const_int 0)))
5073 (set (match_operand:SI 0 "gpc_reg_operand" "")
5074 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5075 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
5076 [(set (match_dup 0)
5077 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5078 (set (match_dup 4)
5079 (compare:CC (match_dup 0)
5080 (const_int 0)))]
5081 "")
5083 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
5084 ;; "sli x,x,0".
5085 (define_expand "lshrsi3"
5086 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
5087 (use (match_operand:SI 1 "gpc_reg_operand" ""))
5088 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
5089 ""
5090 "
5091 {
5092 if (TARGET_POWER)
5093 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
5094 else
5095 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
5096 DONE;
5097 }")
5099 (define_insn "lshrsi3_power"
5100 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
5101 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
5102 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
5103 (clobber (match_scratch:SI 3 "=q,X,X"))]
5104 "TARGET_POWER"
5105 "@
5106 sre %0,%1,%2
5107 mr %0,%1
5108 {s%A2i|s%A2wi} %0,%1,%h2")
5110 (define_insn "lshrsi3_no_power"
5111 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
5112 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
5113 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
5114 "! TARGET_POWER"
5115 "@
5116 mr %0,%1
5117 {sr|srw} %0,%1,%2
5118 {sri|srwi} %0,%1,%h2"
5119 [(set_attr "type" "integer,var_shift_rotate,shift")])
5121 (define_insn "*lshrsi3_64"
5122 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5123 (zero_extend:DI
5124 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5125 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5126 "TARGET_POWERPC64"
5127 "@
5128 {sr|srw} %0,%1,%2
5129 {sri|srwi} %0,%1,%h2"
5130 [(set_attr "type" "var_shift_rotate,shift")])
5132 (define_insn ""
5133 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5134 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5135 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
5136 (const_int 0)))
5137 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
5138 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
5139 "TARGET_POWER"
5140 "@
5141 sre. %3,%1,%2
5142 mr. %1,%1
5143 {s%A2i.|s%A2wi.} %3,%1,%h2
5144 #
5145 #
5146 #"
5147 [(set_attr "type" "delayed_compare")
5148 (set_attr "length" "4,4,4,8,8,8")])
5150 (define_split
5151 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5152 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5153 (match_operand:SI 2 "reg_or_cint_operand" ""))
5154 (const_int 0)))
5155 (clobber (match_scratch:SI 3 ""))
5156 (clobber (match_scratch:SI 4 ""))]
5157 "TARGET_POWER && reload_completed"
5158 [(parallel [(set (match_dup 3)
5159 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5160 (clobber (match_dup 4))])
5161 (set (match_dup 0)
5162 (compare:CC (match_dup 3)
5163 (const_int 0)))]
5164 "")
5166 (define_insn ""
5167 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5168 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5169 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5170 (const_int 0)))
5171 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
5172 "! TARGET_POWER && TARGET_32BIT"
5173 "@
5174 mr. %1,%1
5175 {sr.|srw.} %3,%1,%2
5176 {sri.|srwi.} %3,%1,%h2
5177 #
5178 #
5179 #"
5180 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5181 (set_attr "length" "4,4,4,8,8,8")])
5183 (define_split
5184 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5185 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5186 (match_operand:SI 2 "reg_or_cint_operand" ""))
5187 (const_int 0)))
5188 (clobber (match_scratch:SI 3 ""))]
5189 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5190 [(set (match_dup 3)
5191 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5192 (set (match_dup 0)
5193 (compare:CC (match_dup 3)
5194 (const_int 0)))]
5195 "")
5197 (define_insn ""
5198 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5199 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5200 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
5201 (const_int 0)))
5202 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5203 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5204 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
5205 "TARGET_POWER"
5206 "@
5207 sre. %0,%1,%2
5208 mr. %0,%1
5209 {s%A2i.|s%A2wi.} %0,%1,%h2
5210 #
5211 #
5212 #"
5213 [(set_attr "type" "delayed_compare")
5214 (set_attr "length" "4,4,4,8,8,8")])
5216 (define_split
5217 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5218 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5219 (match_operand:SI 2 "reg_or_cint_operand" ""))
5220 (const_int 0)))
5221 (set (match_operand:SI 0 "gpc_reg_operand" "")
5222 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5223 (clobber (match_scratch:SI 4 ""))]
5224 "TARGET_POWER && reload_completed"
5225 [(parallel [(set (match_dup 0)
5226 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5227 (clobber (match_dup 4))])
5228 (set (match_dup 3)
5229 (compare:CC (match_dup 0)
5230 (const_int 0)))]
5231 "")
5233 (define_insn ""
5234 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5235 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5236 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5237 (const_int 0)))
5238 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5239 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5240 "! TARGET_POWER && TARGET_32BIT"
5241 "@
5242 mr. %0,%1
5243 {sr.|srw.} %0,%1,%2
5244 {sri.|srwi.} %0,%1,%h2
5245 #
5246 #
5247 #"
5248 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5249 (set_attr "length" "4,4,4,8,8,8")])
5251 (define_split
5252 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5253 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5254 (match_operand:SI 2 "reg_or_cint_operand" ""))
5255 (const_int 0)))
5256 (set (match_operand:SI 0 "gpc_reg_operand" "")
5257 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5258 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5259 [(set (match_dup 0)
5260 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5261 (set (match_dup 3)
5262 (compare:CC (match_dup 0)
5263 (const_int 0)))]
5264 "")
5266 (define_insn ""
5267 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5268 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5269 (match_operand:SI 2 "const_int_operand" "i"))
5270 (match_operand:SI 3 "mask_operand" "n")))]
5271 "includes_rshift_p (operands[2], operands[3])"
5272 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
5274 (define_insn ""
5275 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5276 (compare:CC
5277 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5278 (match_operand:SI 2 "const_int_operand" "i,i"))
5279 (match_operand:SI 3 "mask_operand" "n,n"))
5280 (const_int 0)))
5281 (clobber (match_scratch:SI 4 "=r,r"))]
5282 "includes_rshift_p (operands[2], operands[3])"
5283 "@
5284 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
5285 #"
5286 [(set_attr "type" "delayed_compare")
5287 (set_attr "length" "4,8")])
5289 (define_split
5290 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5291 (compare:CC
5292 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5293 (match_operand:SI 2 "const_int_operand" ""))
5294 (match_operand:SI 3 "mask_operand" ""))
5295 (const_int 0)))
5296 (clobber (match_scratch:SI 4 ""))]
5297 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5298 [(set (match_dup 4)
5299 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
5300 (match_dup 3)))
5301 (set (match_dup 0)
5302 (compare:CC (match_dup 4)
5303 (const_int 0)))]
5304 "")
5306 (define_insn ""
5307 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
5308 (compare:CC
5309 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5310 (match_operand:SI 2 "const_int_operand" "i,i"))
5311 (match_operand:SI 3 "mask_operand" "n,n"))
5312 (const_int 0)))
5313 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5314 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5315 "includes_rshift_p (operands[2], operands[3])"
5316 "@
5317 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
5318 #"
5319 [(set_attr "type" "delayed_compare")
5320 (set_attr "length" "4,8")])
5322 (define_split
5323 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
5324 (compare:CC
5325 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5326 (match_operand:SI 2 "const_int_operand" ""))
5327 (match_operand:SI 3 "mask_operand" ""))
5328 (const_int 0)))
5329 (set (match_operand:SI 0 "gpc_reg_operand" "")
5330 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5331 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5332 [(set (match_dup 0)
5333 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5334 (set (match_dup 4)
5335 (compare:CC (match_dup 0)
5336 (const_int 0)))]
5337 "")
5339 (define_insn ""
5340 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5341 (zero_extend:SI
5342 (subreg:QI
5343 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5344 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5345 "includes_rshift_p (operands[2], GEN_INT (255))"
5346 "{rlinm|rlwinm} %0,%1,%s2,0xff")
5348 (define_insn ""
5349 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5350 (compare:CC
5351 (zero_extend:SI
5352 (subreg:QI
5353 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5354 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5355 (const_int 0)))
5356 (clobber (match_scratch:SI 3 "=r,r"))]
5357 "includes_rshift_p (operands[2], GEN_INT (255))"
5358 "@
5359 {rlinm.|rlwinm.} %3,%1,%s2,0xff
5360 #"
5361 [(set_attr "type" "delayed_compare")
5362 (set_attr "length" "4,8")])
5364 (define_split
5365 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5366 (compare:CC
5367 (zero_extend:SI
5368 (subreg:QI
5369 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5370 (match_operand:SI 2 "const_int_operand" "")) 0))
5371 (const_int 0)))
5372 (clobber (match_scratch:SI 3 ""))]
5373 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5374 [(set (match_dup 3)
5375 (zero_extend:SI (subreg:QI
5376 (lshiftrt:SI (match_dup 1)
5377 (match_dup 2)) 0)))
5378 (set (match_dup 0)
5379 (compare:CC (match_dup 3)
5380 (const_int 0)))]
5381 "")
5383 (define_insn ""
5384 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5385 (compare:CC
5386 (zero_extend:SI
5387 (subreg:QI
5388 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5389 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5390 (const_int 0)))
5391 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5392 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5393 "includes_rshift_p (operands[2], GEN_INT (255))"
5394 "@
5395 {rlinm.|rlwinm.} %0,%1,%s2,0xff
5396 #"
5397 [(set_attr "type" "delayed_compare")
5398 (set_attr "length" "4,8")])
5400 (define_split
5401 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5402 (compare:CC
5403 (zero_extend:SI
5404 (subreg:QI
5405 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5406 (match_operand:SI 2 "const_int_operand" "")) 0))
5407 (const_int 0)))
5408 (set (match_operand:SI 0 "gpc_reg_operand" "")
5409 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5410 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5411 [(set (match_dup 0)
5412 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5413 (set (match_dup 3)
5414 (compare:CC (match_dup 0)
5415 (const_int 0)))]
5416 "")
5418 (define_insn ""
5419 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5420 (zero_extend:SI
5421 (subreg:HI
5422 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5423 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5424 "includes_rshift_p (operands[2], GEN_INT (65535))"
5425 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
5427 (define_insn ""
5428 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5429 (compare:CC
5430 (zero_extend:SI
5431 (subreg:HI
5432 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5433 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5434 (const_int 0)))
5435 (clobber (match_scratch:SI 3 "=r,r"))]
5436 "includes_rshift_p (operands[2], GEN_INT (65535))"
5437 "@
5438 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
5439 #"
5440 [(set_attr "type" "delayed_compare")
5441 (set_attr "length" "4,8")])
5443 (define_split
5444 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5445 (compare:CC
5446 (zero_extend:SI
5447 (subreg:HI
5448 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5449 (match_operand:SI 2 "const_int_operand" "")) 0))
5450 (const_int 0)))
5451 (clobber (match_scratch:SI 3 ""))]
5452 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5453 [(set (match_dup 3)
5454 (zero_extend:SI (subreg:HI
5455 (lshiftrt:SI (match_dup 1)
5456 (match_dup 2)) 0)))
5457 (set (match_dup 0)
5458 (compare:CC (match_dup 3)
5459 (const_int 0)))]
5460 "")
5462 (define_insn ""
5463 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5464 (compare:CC
5465 (zero_extend:SI
5466 (subreg:HI
5467 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5468 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5469 (const_int 0)))
5470 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5471 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5472 "includes_rshift_p (operands[2], GEN_INT (65535))"
5473 "@
5474 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
5475 #"
5476 [(set_attr "type" "delayed_compare")
5477 (set_attr "length" "4,8")])
5479 (define_split
5480 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5481 (compare:CC
5482 (zero_extend:SI
5483 (subreg:HI
5484 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5485 (match_operand:SI 2 "const_int_operand" "")) 0))
5486 (const_int 0)))
5487 (set (match_operand:SI 0 "gpc_reg_operand" "")
5488 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5489 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5490 [(set (match_dup 0)
5491 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5492 (set (match_dup 3)
5493 (compare:CC (match_dup 0)
5494 (const_int 0)))]
5495 "")
5497 (define_insn ""
5498 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5499 (const_int 1)
5500 (match_operand:SI 1 "gpc_reg_operand" "r"))
5501 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5502 (const_int 31)))]
5503 "TARGET_POWER"
5504 "rrib %0,%1,%2")
5506 (define_insn ""
5507 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5508 (const_int 1)
5509 (match_operand:SI 1 "gpc_reg_operand" "r"))
5510 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5511 (const_int 31)))]
5512 "TARGET_POWER"
5513 "rrib %0,%1,%2")
5515 (define_insn ""
5516 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5517 (const_int 1)
5518 (match_operand:SI 1 "gpc_reg_operand" "r"))
5519 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5520 (const_int 1)
5521 (const_int 0)))]
5522 "TARGET_POWER"
5523 "rrib %0,%1,%2")
5525 (define_expand "ashrsi3"
5526 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5527 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5528 (match_operand:SI 2 "reg_or_cint_operand" "")))]
5529 ""
5530 "
5531 {
5532 if (TARGET_POWER)
5533 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
5534 else
5535 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
5536 DONE;
5537 }")
5539 (define_insn "ashrsi3_power"
5540 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5541 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5542 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
5543 (clobber (match_scratch:SI 3 "=q,X"))]
5544 "TARGET_POWER"
5545 "@
5546 srea %0,%1,%2
5547 {srai|srawi} %0,%1,%h2"
5548 [(set_attr "type" "shift")])
5550 (define_insn "ashrsi3_no_power"
5551 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5552 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5553 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
5554 "! TARGET_POWER"
5555 "@
5556 {sra|sraw} %0,%1,%2
5557 {srai|srawi} %0,%1,%h2"
5558 [(set_attr "type" "var_shift_rotate,shift")])
5560 (define_insn "*ashrsi3_64"
5561 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5562 (sign_extend:DI
5563 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5564 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5565 "TARGET_POWERPC64"
5566 "@
5567 {sra|sraw} %0,%1,%2
5568 {srai|srawi} %0,%1,%h2"
5569 [(set_attr "type" "var_shift_rotate,shift")])
5571 (define_insn ""
5572 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5573 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5574 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5575 (const_int 0)))
5576 (clobber (match_scratch:SI 3 "=r,r,r,r"))
5577 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5578 "TARGET_POWER"
5579 "@
5580 srea. %3,%1,%2
5581 {srai.|srawi.} %3,%1,%h2
5582 #
5583 #"
5584 [(set_attr "type" "delayed_compare")
5585 (set_attr "length" "4,4,8,8")])
5587 (define_split
5588 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5589 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5590 (match_operand:SI 2 "reg_or_cint_operand" ""))
5591 (const_int 0)))
5592 (clobber (match_scratch:SI 3 ""))
5593 (clobber (match_scratch:SI 4 ""))]
5594 "TARGET_POWER && reload_completed"
5595 [(parallel [(set (match_dup 3)
5596 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5597 (clobber (match_dup 4))])
5598 (set (match_dup 0)
5599 (compare:CC (match_dup 3)
5600 (const_int 0)))]
5601 "")
5603 (define_insn ""
5604 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5605 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5606 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5607 (const_int 0)))
5608 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
5609 "! TARGET_POWER"
5610 "@
5611 {sra.|sraw.} %3,%1,%2
5612 {srai.|srawi.} %3,%1,%h2
5613 #
5614 #"
5615 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5616 (set_attr "length" "4,4,8,8")])
5618 (define_split
5619 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5620 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5621 (match_operand:SI 2 "reg_or_cint_operand" ""))
5622 (const_int 0)))
5623 (clobber (match_scratch:SI 3 ""))]
5624 "! TARGET_POWER && reload_completed"
5625 [(set (match_dup 3)
5626 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5627 (set (match_dup 0)
5628 (compare:CC (match_dup 3)
5629 (const_int 0)))]
5630 "")
5632 (define_insn ""
5633 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5634 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5635 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5636 (const_int 0)))
5637 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5638 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5639 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5640 "TARGET_POWER"
5641 "@
5642 srea. %0,%1,%2
5643 {srai.|srawi.} %0,%1,%h2
5644 #
5645 #"
5646 [(set_attr "type" "delayed_compare")
5647 (set_attr "length" "4,4,8,8")])
5649 (define_split
5650 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5651 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5652 (match_operand:SI 2 "reg_or_cint_operand" ""))
5653 (const_int 0)))
5654 (set (match_operand:SI 0 "gpc_reg_operand" "")
5655 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5656 (clobber (match_scratch:SI 4 ""))]
5657 "TARGET_POWER && reload_completed"
5658 [(parallel [(set (match_dup 0)
5659 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5660 (clobber (match_dup 4))])
5661 (set (match_dup 3)
5662 (compare:CC (match_dup 0)
5663 (const_int 0)))]
5664 "")
5666 (define_insn ""
5667 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5668 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5669 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5670 (const_int 0)))
5671 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5672 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5673 "! TARGET_POWER"
5674 "@
5675 {sra.|sraw.} %0,%1,%2
5676 {srai.|srawi.} %0,%1,%h2
5677 #
5678 #"
5679 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5680 (set_attr "length" "4,4,8,8")])
5681 \f
5682 ;; Builtins to replace a division to generate FRE reciprocal estimate
5683 ;; instructions and the necessary fixup instructions
5684 (define_expand "recip<mode>3"
5685 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5686 (match_operand:RECIPF 1 "gpc_reg_operand" "")
5687 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
5688 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
5689 {
5690 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
5691 DONE;
5692 })
5694 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
5695 ;; hardware division. This is only done before register allocation and with
5696 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
5697 (define_split
5698 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
5699 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
5700 (match_operand 2 "gpc_reg_operand" "")))]
5701 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
5702 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
5703 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
5704 [(const_int 0)]
5705 {
5706 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
5707 DONE;
5708 })
5710 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
5711 ;; appropriate fixup.
5712 (define_expand "rsqrt<mode>2"
5713 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5714 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
5715 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
5716 {
5717 rs6000_emit_swrsqrt (operands[0], operands[1]);
5718 DONE;
5719 })
5720 \f
5721 (define_split
5722 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5723 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5724 (match_operand:SI 2 "reg_or_cint_operand" ""))
5725 (const_int 0)))
5726 (set (match_operand:SI 0 "gpc_reg_operand" "")
5727 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5728 "! TARGET_POWER && reload_completed"
5729 [(set (match_dup 0)
5730 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5731 (set (match_dup 3)
5732 (compare:CC (match_dup 0)
5733 (const_int 0)))]
5734 "")
5736 ;; Floating-point insns, excluding normal data motion.
5737 ;;
5738 ;; PowerPC has a full set of single-precision floating point instructions.
5739 ;;
5740 ;; For the POWER architecture, we pretend that we have both SFmode and
5741 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5742 ;; The only conversions we will do will be when storing to memory. In that
5743 ;; case, we will use the "frsp" instruction before storing.
5744 ;;
5745 ;; Note that when we store into a single-precision memory location, we need to
5746 ;; use the frsp insn first. If the register being stored isn't dead, we
5747 ;; need a scratch register for the frsp. But this is difficult when the store
5748 ;; is done by reload. It is not incorrect to do the frsp on the register in
5749 ;; this case, we just lose precision that we would have otherwise gotten but
5750 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5752 (define_expand "extendsfdf2"
5753 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5754 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5755 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5756 "")
5758 (define_insn_and_split "*extendsfdf2_fpr"
5759 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
5760 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5761 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5762 "@
5763 #
5764 fmr %0,%1
5765 lfs%U1%X1 %0,%1"
5766 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5767 [(const_int 0)]
5768 {
5769 emit_note (NOTE_INSN_DELETED);
5770 DONE;
5771 }
5772 [(set_attr "type" "fp,fp,fpload")])
5774 (define_expand "truncdfsf2"
5775 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5776 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5777 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5778 "")
5780 (define_insn "*truncdfsf2_fpr"
5781 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5782 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5783 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5784 "frsp %0,%1"
5785 [(set_attr "type" "fp")])
5787 (define_insn "aux_truncdfsf2"
5788 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5789 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5790 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5791 "frsp %0,%1"
5792 [(set_attr "type" "fp")])
5794 (define_expand "negsf2"
5795 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5796 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5797 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5798 "")
5800 (define_insn "*negsf2"
5801 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5802 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5803 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5804 "fneg %0,%1"
5805 [(set_attr "type" "fp")])
5807 (define_expand "abssf2"
5808 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5809 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5810 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5811 "")
5813 (define_insn "*abssf2"
5814 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5815 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5816 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5817 "fabs %0,%1"
5818 [(set_attr "type" "fp")])
5820 (define_insn ""
5821 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5822 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5823 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5824 "fnabs %0,%1"
5825 [(set_attr "type" "fp")])
5827 (define_expand "addsf3"
5828 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5829 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5830 (match_operand:SF 2 "gpc_reg_operand" "")))]
5831 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5832 "")
5834 (define_insn ""
5835 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5836 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5837 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5838 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5839 "fadds %0,%1,%2"
5840 [(set_attr "type" "fp")
5841 (set_attr "fp_type" "fp_addsub_s")])
5843 (define_insn ""
5844 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5845 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5846 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5847 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5848 "{fa|fadd} %0,%1,%2"
5849 [(set_attr "type" "fp")])
5851 (define_expand "subsf3"
5852 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5853 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5854 (match_operand:SF 2 "gpc_reg_operand" "")))]
5855 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5856 "")
5858 (define_insn ""
5859 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5860 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5861 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5862 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5863 "fsubs %0,%1,%2"
5864 [(set_attr "type" "fp")
5865 (set_attr "fp_type" "fp_addsub_s")])
5867 (define_insn ""
5868 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5869 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5870 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5871 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5872 "{fs|fsub} %0,%1,%2"
5873 [(set_attr "type" "fp")])
5875 (define_expand "mulsf3"
5876 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5877 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5878 (match_operand:SF 2 "gpc_reg_operand" "")))]
5879 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5880 "")
5882 (define_insn ""
5883 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5884 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5885 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5886 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5887 "fmuls %0,%1,%2"
5888 [(set_attr "type" "fp")
5889 (set_attr "fp_type" "fp_mul_s")])
5891 (define_insn ""
5892 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5893 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5894 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5895 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5896 "{fm|fmul} %0,%1,%2"
5897 [(set_attr "type" "dmul")])
5899 (define_expand "divsf3"
5900 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5901 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5902 (match_operand:SF 2 "gpc_reg_operand" "")))]
5903 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5904 "")
5906 (define_insn ""
5907 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5908 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5909 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5910 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5911 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5912 "fdivs %0,%1,%2"
5913 [(set_attr "type" "sdiv")])
5915 (define_insn ""
5916 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5917 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5918 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5919 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5920 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5921 "{fd|fdiv} %0,%1,%2"
5922 [(set_attr "type" "ddiv")])
5924 (define_insn "fres"
5925 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5926 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5927 "TARGET_FRES"
5928 "fres %0,%1"
5929 [(set_attr "type" "fp")])
5931 ; builtin fmaf support
5932 (define_insn "*fmasf4_fpr"
5933 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5934 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5935 (match_operand:SF 2 "gpc_reg_operand" "f")
5936 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5937 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5938 {
5939 return (TARGET_POWERPC
5940 ? "fmadds %0,%1,%2,%3"
5941 : "{fma|fmadd} %0,%1,%2,%3");
5942 }
5943 [(set_attr "type" "fp")
5944 (set_attr "fp_type" "fp_maddsub_s")])
5946 (define_insn "*fmssf4_fpr"
5947 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5948 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5949 (match_operand:SF 2 "gpc_reg_operand" "f")
5950 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5951 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5952 {
5953 return (TARGET_POWERPC
5954 ? "fmsubs %0,%1,%2,%3"
5955 : "{fms|fmsub} %0,%1,%2,%3");
5956 }
5957 [(set_attr "type" "fp")
5958 (set_attr "fp_type" "fp_maddsub_s")])
5960 (define_insn "*nfmasf4_fpr"
5961 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5962 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5963 (match_operand:SF 2 "gpc_reg_operand" "f")
5964 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5965 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5966 {
5967 return (TARGET_POWERPC
5968 ? "fnmadds %0,%1,%2,%3"
5969 : "{fnma|fnmadd} %0,%1,%2,%3");
5970 }
5971 [(set_attr "type" "fp")
5972 (set_attr "fp_type" "fp_maddsub_s")])
5974 (define_insn "*nfmssf4_fpr"
5975 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5976 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5977 (match_operand:SF 2 "gpc_reg_operand" "f")
5978 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f")))))]
5979 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5980 {
5981 return (TARGET_POWERPC
5982 ? "fnmsubs %0,%1,%2,%3"
5983 : "{fnms|fnmsub} %0,%1,%2,%3");
5984 }
5985 [(set_attr "type" "fp")
5986 (set_attr "fp_type" "fp_maddsub_s")])
5988 (define_expand "sqrtsf2"
5989 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5990 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5991 "(TARGET_PPC_GPOPT || TARGET_POWER2 || TARGET_XILINX_FPU)
5992 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5993 && !TARGET_SIMPLE_FPU"
5994 "")
5996 (define_insn ""
5997 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5998 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5999 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
6000 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
6001 "fsqrts %0,%1"
6002 [(set_attr "type" "ssqrt")])
6004 (define_insn ""
6005 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6006 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
6007 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS
6008 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
6009 "fsqrt %0,%1"
6010 [(set_attr "type" "dsqrt")])
6012 (define_insn "*rsqrtsf_internal1"
6013 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6014 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
6015 UNSPEC_RSQRT))]
6016 "TARGET_FRSQRTES"
6017 "frsqrtes %0,%1"
6018 [(set_attr "type" "fp")])
6020 (define_expand "copysign<mode>3"
6021 [(set (match_dup 3)
6022 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
6023 (set (match_dup 4)
6024 (neg:SFDF (abs:SFDF (match_dup 1))))
6025 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
6026 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
6027 (match_dup 5))
6028 (match_dup 3)
6029 (match_dup 4)))]
6030 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
6031 && ((TARGET_PPC_GFXOPT
6032 && !HONOR_NANS (<MODE>mode)
6033 && !HONOR_SIGNED_ZEROS (<MODE>mode))
6034 || TARGET_CMPB
6035 || VECTOR_UNIT_VSX_P (<MODE>mode))"
6036 {
6037 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
6038 {
6039 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
6040 operands[2]));
6041 DONE;
6042 }
6044 operands[3] = gen_reg_rtx (<MODE>mode);
6045 operands[4] = gen_reg_rtx (<MODE>mode);
6046 operands[5] = CONST0_RTX (<MODE>mode);
6047 })
6049 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
6050 ;; compiler from optimizing -0.0
6051 (define_insn "copysign<mode>3_fcpsgn"
6052 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6053 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")
6054 (match_operand:SFDF 2 "gpc_reg_operand" "<rreg2>")]
6055 UNSPEC_COPYSIGN))]
6056 "TARGET_CMPB && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6057 "fcpsgn %0,%2,%1"
6058 [(set_attr "type" "fp")])
6060 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
6061 ;; fsel instruction and some auxiliary computations. Then we just have a
6062 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
6063 ;; combine.
6064 (define_expand "smaxsf3"
6065 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6066 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
6067 (match_operand:SF 2 "gpc_reg_operand" ""))
6068 (match_dup 1)
6069 (match_dup 2)))]
6070 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6071 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6072 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
6074 (define_expand "sminsf3"
6075 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6076 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
6077 (match_operand:SF 2 "gpc_reg_operand" ""))
6078 (match_dup 2)
6079 (match_dup 1)))]
6080 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6081 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6082 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
6084 (define_split
6085 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6086 (match_operator:SF 3 "min_max_operator"
6087 [(match_operand:SF 1 "gpc_reg_operand" "")
6088 (match_operand:SF 2 "gpc_reg_operand" "")]))]
6089 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6090 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6091 [(const_int 0)]
6092 "
6093 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6094 operands[1], operands[2]);
6095 DONE;
6096 }")
6098 (define_expand "mov<mode>cc"
6099 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
6100 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6101 (match_operand:GPR 2 "gpc_reg_operand" "")
6102 (match_operand:GPR 3 "gpc_reg_operand" "")))]
6103 "TARGET_ISEL<sel>"
6104 "
6105 {
6106 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6107 DONE;
6108 else
6109 FAIL;
6110 }")
6112 ;; We use the BASE_REGS for the isel input operands because, if rA is
6113 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
6114 ;; because we may switch the operands and rB may end up being rA.
6115 ;;
6116 ;; We need 2 patterns: an unsigned and a signed pattern. We could
6117 ;; leave out the mode in operand 4 and use one pattern, but reload can
6118 ;; change the mode underneath our feet and then gets confused trying
6119 ;; to reload the value.
6120 (define_insn "isel_signed_<mode>"
6121 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
6122 (if_then_else:GPR
6123 (match_operator 1 "scc_comparison_operator"
6124 [(match_operand:CC 4 "cc_reg_operand" "y,y")
6125 (const_int 0)])
6126 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
6127 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
6128 "TARGET_ISEL<sel>"
6129 "*
6130 { return output_isel (operands); }"
6131 [(set_attr "type" "isel")
6132 (set_attr "length" "4")])
6134 (define_insn "isel_unsigned_<mode>"
6135 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
6136 (if_then_else:GPR
6137 (match_operator 1 "scc_comparison_operator"
6138 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
6139 (const_int 0)])
6140 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
6141 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
6142 "TARGET_ISEL<sel>"
6143 "*
6144 { return output_isel (operands); }"
6145 [(set_attr "type" "isel")
6146 (set_attr "length" "4")])
6148 ;; These patterns can be useful for combine; they let combine know that
6149 ;; isel can handle reversed comparisons so long as the operands are
6150 ;; registers.
6152 (define_insn "*isel_reversed_signed_<mode>"
6153 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
6154 (if_then_else:GPR
6155 (match_operator 1 "scc_rev_comparison_operator"
6156 [(match_operand:CC 4 "cc_reg_operand" "y")
6157 (const_int 0)])
6158 (match_operand:GPR 2 "gpc_reg_operand" "b")
6159 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
6160 "TARGET_ISEL<sel>"
6161 "*
6162 { return output_isel (operands); }"
6163 [(set_attr "type" "isel")
6164 (set_attr "length" "4")])
6166 (define_insn "*isel_reversed_unsigned_<mode>"
6167 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
6168 (if_then_else:GPR
6169 (match_operator 1 "scc_rev_comparison_operator"
6170 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
6171 (const_int 0)])
6172 (match_operand:GPR 2 "gpc_reg_operand" "b")
6173 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
6174 "TARGET_ISEL<sel>"
6175 "*
6176 { return output_isel (operands); }"
6177 [(set_attr "type" "isel")
6178 (set_attr "length" "4")])
6180 (define_expand "movsfcc"
6181 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6182 (if_then_else:SF (match_operand 1 "comparison_operator" "")
6183 (match_operand:SF 2 "gpc_reg_operand" "")
6184 (match_operand:SF 3 "gpc_reg_operand" "")))]
6185 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6186 "
6187 {
6188 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6189 DONE;
6190 else
6191 FAIL;
6192 }")
6194 (define_insn "*fselsfsf4"
6195 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6196 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6197 (match_operand:SF 4 "zero_fp_constant" "F"))
6198 (match_operand:SF 2 "gpc_reg_operand" "f")
6199 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6200 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6201 "fsel %0,%1,%2,%3"
6202 [(set_attr "type" "fp")])
6204 (define_insn "*fseldfsf4"
6205 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6206 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6207 (match_operand:DF 4 "zero_fp_constant" "F"))
6208 (match_operand:SF 2 "gpc_reg_operand" "f")
6209 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6210 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6211 "fsel %0,%1,%2,%3"
6212 [(set_attr "type" "fp")])
6214 (define_expand "negdf2"
6215 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6216 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6217 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6218 "")
6220 (define_insn "*negdf2_fpr"
6221 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6222 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6223 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6224 && !VECTOR_UNIT_VSX_P (DFmode)"
6225 "fneg %0,%1"
6226 [(set_attr "type" "fp")])
6228 (define_expand "absdf2"
6229 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6230 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6231 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6232 "")
6234 (define_insn "*absdf2_fpr"
6235 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6236 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6237 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6238 && !VECTOR_UNIT_VSX_P (DFmode)"
6239 "fabs %0,%1"
6240 [(set_attr "type" "fp")])
6242 (define_insn "*nabsdf2_fpr"
6243 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6244 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6245 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6246 && !VECTOR_UNIT_VSX_P (DFmode)"
6247 "fnabs %0,%1"
6248 [(set_attr "type" "fp")])
6250 (define_expand "adddf3"
6251 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6252 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6253 (match_operand:DF 2 "gpc_reg_operand" "")))]
6254 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6255 "")
6257 (define_insn "*adddf3_fpr"
6258 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6259 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6260 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6261 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6262 && !VECTOR_UNIT_VSX_P (DFmode)"
6263 "{fa|fadd} %0,%1,%2"
6264 [(set_attr "type" "fp")
6265 (set_attr "fp_type" "fp_addsub_d")])
6267 (define_expand "subdf3"
6268 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6269 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6270 (match_operand:DF 2 "gpc_reg_operand" "")))]
6271 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6272 "")
6274 (define_insn "*subdf3_fpr"
6275 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6276 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6277 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6278 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6279 && !VECTOR_UNIT_VSX_P (DFmode)"
6280 "{fs|fsub} %0,%1,%2"
6281 [(set_attr "type" "fp")
6282 (set_attr "fp_type" "fp_addsub_d")])
6284 (define_expand "muldf3"
6285 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6286 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
6287 (match_operand:DF 2 "gpc_reg_operand" "")))]
6288 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6289 "")
6291 (define_insn "*muldf3_fpr"
6292 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6293 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6294 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6295 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6296 && !VECTOR_UNIT_VSX_P (DFmode)"
6297 "{fm|fmul} %0,%1,%2"
6298 [(set_attr "type" "dmul")
6299 (set_attr "fp_type" "fp_mul_d")])
6301 (define_expand "divdf3"
6302 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6303 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
6304 (match_operand:DF 2 "gpc_reg_operand" "")))]
6305 "TARGET_HARD_FLOAT
6306 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
6307 && !TARGET_SIMPLE_FPU"
6308 "")
6310 (define_insn "*divdf3_fpr"
6311 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6312 (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6313 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6314 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU
6315 && !VECTOR_UNIT_VSX_P (DFmode)"
6316 "{fd|fdiv} %0,%1,%2"
6317 [(set_attr "type" "ddiv")])
6319 (define_insn "*fred_fpr"
6320 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6321 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
6322 "TARGET_FRE && !VECTOR_UNIT_VSX_P (DFmode)"
6323 "fre %0,%1"
6324 [(set_attr "type" "fp")])
6326 (define_insn "*rsqrtdf_internal1"
6327 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6328 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]
6329 UNSPEC_RSQRT))]
6330 "TARGET_FRSQRTE && !VECTOR_UNIT_VSX_P (DFmode)"
6331 "frsqrte %0,%1"
6332 [(set_attr "type" "fp")])
6334 ; builtin fma support
6335 (define_insn "*fmadf4_fpr"
6336 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6337 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
6338 (match_operand:DF 2 "gpc_reg_operand" "f")
6339 (match_operand:DF 3 "gpc_reg_operand" "f")))]
6340 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6341 && VECTOR_UNIT_NONE_P (DFmode)"
6342 "{fma|fmadd} %0,%1,%2,%3"
6343 [(set_attr "type" "fp")
6344 (set_attr "fp_type" "fp_maddsub_d")])
6346 (define_insn "*fmsdf4_fpr"
6347 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6348 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
6349 (match_operand:DF 2 "gpc_reg_operand" "f")
6350 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f"))))]
6351 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6352 && VECTOR_UNIT_NONE_P (DFmode)"
6353 "{fms|fmsub} %0,%1,%2,%3"
6354 [(set_attr "type" "fp")
6355 (set_attr "fp_type" "fp_maddsub_d")])
6357 (define_insn "*nfmadf4_fpr"
6358 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6359 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
6360 (match_operand:DF 2 "gpc_reg_operand" "f")
6361 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
6362 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6363 && VECTOR_UNIT_NONE_P (DFmode)"
6364 "{fnma|fnmadd} %0,%1,%2,%3"
6365 [(set_attr "type" "fp")
6366 (set_attr "fp_type" "fp_maddsub_d")])
6368 (define_insn "*nfmsdf4_fpr"
6369 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6370 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
6371 (match_operand:DF 2 "gpc_reg_operand" "f")
6372 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f")))))]
6373 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6374 && VECTOR_UNIT_NONE_P (DFmode)"
6375 "{fnms|fnmsub} %0,%1,%2,%3"
6376 [(set_attr "type" "fp")
6377 (set_attr "fp_type" "fp_maddsub_d")])
6379 (define_expand "sqrtdf2"
6380 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6381 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6382 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
6383 && TARGET_DOUBLE_FLOAT"
6384 "")
6386 (define_insn "*sqrtdf2_fpr"
6387 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6388 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6389 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
6390 && TARGET_DOUBLE_FLOAT
6391 && !VECTOR_UNIT_VSX_P (DFmode)"
6392 "fsqrt %0,%1"
6393 [(set_attr "type" "dsqrt")])
6395 ;; The conditional move instructions allow us to perform max and min
6396 ;; operations even when
6398 (define_expand "smaxdf3"
6399 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6400 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6401 (match_operand:DF 2 "gpc_reg_operand" ""))
6402 (match_dup 1)
6403 (match_dup 2)))]
6404 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6405 && !flag_trapping_math"
6406 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
6408 (define_expand "smindf3"
6409 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6410 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6411 (match_operand:DF 2 "gpc_reg_operand" ""))
6412 (match_dup 2)
6413 (match_dup 1)))]
6414 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6415 && !flag_trapping_math"
6416 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
6418 (define_split
6419 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6420 (match_operator:DF 3 "min_max_operator"
6421 [(match_operand:DF 1 "gpc_reg_operand" "")
6422 (match_operand:DF 2 "gpc_reg_operand" "")]))]
6423 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6424 && !flag_trapping_math"
6425 [(const_int 0)]
6426 "
6427 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6428 operands[1], operands[2]);
6429 DONE;
6430 }")
6432 (define_expand "movdfcc"
6433 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6434 (if_then_else:DF (match_operand 1 "comparison_operator" "")
6435 (match_operand:DF 2 "gpc_reg_operand" "")
6436 (match_operand:DF 3 "gpc_reg_operand" "")))]
6437 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6438 "
6439 {
6440 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6441 DONE;
6442 else
6443 FAIL;
6444 }")
6446 (define_insn "*fseldfdf4"
6447 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6448 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6449 (match_operand:DF 4 "zero_fp_constant" "F"))
6450 (match_operand:DF 2 "gpc_reg_operand" "d")
6451 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6452 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6453 "fsel %0,%1,%2,%3"
6454 [(set_attr "type" "fp")])
6456 (define_insn "*fselsfdf4"
6457 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6458 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6459 (match_operand:SF 4 "zero_fp_constant" "F"))
6460 (match_operand:DF 2 "gpc_reg_operand" "d")
6461 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6462 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6463 "fsel %0,%1,%2,%3"
6464 [(set_attr "type" "fp")])
6465 \f
6466 ;; Conversions to and from floating-point.
6468 ; We don't define lfiwax/lfiwzx with the normal definition, because we
6469 ; don't want to support putting SImode in FPR registers.
6470 (define_insn "lfiwax"
6471 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6472 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
6473 UNSPEC_LFIWAX))]
6474 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
6475 "lfiwax %0,%y1"
6476 [(set_attr "type" "fpload")])
6478 ; This split must be run before register allocation because it allocates the
6479 ; memory slot that is needed to move values to/from the FPR. We don't allocate
6480 ; it earlier to allow for the combiner to merge insns together where it might
6481 ; not be needed and also in case the insns are deleted as dead code.
6483 (define_insn_and_split "floatsi<mode>2_lfiwax"
6484 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6485 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
6486 (clobber (match_scratch:DI 2 "=d"))]
6487 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
6488 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
6489 "#"
6490 ""
6491 [(pc)]
6492 "
6493 {
6494 rtx dest = operands[0];
6495 rtx src = operands[1];
6496 rtx tmp;
6498 if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
6499 tmp = convert_to_mode (DImode, src, false);
6500 else
6501 {
6502 tmp = operands[2];
6503 if (GET_CODE (tmp) == SCRATCH)
6504 tmp = gen_reg_rtx (DImode);
6505 if (MEM_P (src))
6506 {
6507 src = rs6000_address_for_fpconvert (src);
6508 emit_insn (gen_lfiwax (tmp, src));
6509 }
6510 else
6511 {
6512 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6513 emit_move_insn (stack, src);
6514 emit_insn (gen_lfiwax (tmp, stack));
6515 }
6516 }
6517 emit_insn (gen_floatdi<mode>2 (dest, tmp));
6518 DONE;
6519 }"
6520 [(set_attr "length" "12")
6521 (set_attr "type" "fpload")])
6523 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
6524 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
6525 (float:SFDF
6526 (sign_extend:DI
6527 (match_operand:SI 1 "memory_operand" "Z,Z"))))
6528 (clobber (match_scratch:DI 2 "=0,d"))]
6529 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
6530 && <SI_CONVERT_FP>"
6531 "#"
6532 ""
6533 [(pc)]
6534 "
6535 {
6536 operands[1] = rs6000_address_for_fpconvert (operands[1]);
6537 if (GET_CODE (operands[2]) == SCRATCH)
6538 operands[2] = gen_reg_rtx (DImode);
6539 emit_insn (gen_lfiwax (operands[2], operands[1]));
6540 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
6541 DONE;
6542 }"
6543 [(set_attr "length" "8")
6544 (set_attr "type" "fpload")])
6546 (define_insn "lfiwzx"
6547 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6548 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
6549 UNSPEC_LFIWZX))]
6550 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
6551 "lfiwzx %0,%y1"
6552 [(set_attr "type" "fpload")])
6554 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
6555 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6556 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
6557 (clobber (match_scratch:DI 2 "=d"))]
6558 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
6559 && <SI_CONVERT_FP>"
6560 "#"
6561 ""
6562 [(pc)]
6563 "
6564 {
6565 rtx dest = operands[0];
6566 rtx src = operands[1];
6567 rtx tmp;
6569 if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
6570 tmp = convert_to_mode (DImode, src, true);
6571 else
6572 {
6573 tmp = operands[2];
6574 if (GET_CODE (tmp) == SCRATCH)
6575 tmp = gen_reg_rtx (DImode);
6576 if (MEM_P (src))
6577 {
6578 src = rs6000_address_for_fpconvert (src);
6579 emit_insn (gen_lfiwzx (tmp, src));
6580 }
6581 else
6582 {
6583 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6584 emit_move_insn (stack, src);
6585 emit_insn (gen_lfiwzx (tmp, stack));
6586 }
6587 }
6588 emit_insn (gen_floatdi<mode>2 (dest, tmp));
6589 DONE;
6590 }"
6591 [(set_attr "length" "12")
6592 (set_attr "type" "fpload")])
6594 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
6595 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
6596 (unsigned_float:SFDF
6597 (zero_extend:DI
6598 (match_operand:SI 1 "memory_operand" "Z,Z"))))
6599 (clobber (match_scratch:DI 2 "=0,d"))]
6600 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
6601 && <SI_CONVERT_FP>"
6602 "#"
6603 ""
6604 [(pc)]
6605 "
6606 {
6607 operands[1] = rs6000_address_for_fpconvert (operands[1]);
6608 if (GET_CODE (operands[2]) == SCRATCH)
6609 operands[2] = gen_reg_rtx (DImode);
6610 emit_insn (gen_lfiwzx (operands[2], operands[1]));
6611 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
6612 DONE;
6613 }"
6614 [(set_attr "length" "8")
6615 (set_attr "type" "fpload")])
6617 ; For each of these conversions, there is a define_expand, a define_insn
6618 ; with a '#' template, and a define_split (with C code). The idea is
6619 ; to allow constant folding with the template of the define_insn,
6620 ; then to have the insns split later (between sched1 and final).
6622 (define_expand "floatsidf2"
6623 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6624 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
6625 (use (match_dup 2))
6626 (use (match_dup 3))
6627 (clobber (match_dup 4))
6628 (clobber (match_dup 5))
6629 (clobber (match_dup 6))])]
6630 "TARGET_HARD_FLOAT
6631 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6632 "
6633 {
6634 if (TARGET_E500_DOUBLE)
6635 {
6636 if (!REG_P (operands[1]))
6637 operands[1] = force_reg (SImode, operands[1]);
6638 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
6639 DONE;
6640 }
6641 else if (TARGET_LFIWAX && TARGET_FCFID)
6642 {
6643 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
6644 DONE;
6645 }
6646 else if (TARGET_FCFID)
6647 {
6648 rtx dreg = operands[1];
6649 if (!REG_P (dreg))
6650 dreg = force_reg (SImode, dreg);
6651 dreg = convert_to_mode (DImode, dreg, false);
6652 emit_insn (gen_floatdidf2 (operands[0], dreg));
6653 DONE;
6654 }
6656 if (!REG_P (operands[1]))
6657 operands[1] = force_reg (SImode, operands[1]);
6658 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6659 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
6660 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
6661 operands[5] = gen_reg_rtx (DFmode);
6662 operands[6] = gen_reg_rtx (SImode);
6663 }")
6665 (define_insn_and_split "*floatsidf2_internal"
6666 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6667 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6668 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6669 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6670 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6671 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
6672 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
6673 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6674 "#"
6675 ""
6676 [(pc)]
6677 "
6678 {
6679 rtx lowword, highword;
6680 gcc_assert (MEM_P (operands[4]));
6681 highword = adjust_address (operands[4], SImode, 0);
6682 lowword = adjust_address (operands[4], SImode, 4);
6683 if (! WORDS_BIG_ENDIAN)
6684 {
6685 rtx tmp;
6686 tmp = highword; highword = lowword; lowword = tmp;
6687 }
6689 emit_insn (gen_xorsi3 (operands[6], operands[1],
6690 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
6691 emit_move_insn (lowword, operands[6]);
6692 emit_move_insn (highword, operands[2]);
6693 emit_move_insn (operands[5], operands[4]);
6694 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6695 DONE;
6696 }"
6697 [(set_attr "length" "24")
6698 (set_attr "type" "fp")])
6700 ;; If we don't have a direct conversion to single precision, don't enable this
6701 ;; conversion for 32-bit without fast math, because we don't have the insn to
6702 ;; generate the fixup swizzle to avoid double rounding problems.
6703 (define_expand "floatunssisf2"
6704 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6705 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
6706 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
6707 && (!TARGET_FPRS
6708 || (TARGET_FPRS
6709 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
6710 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
6711 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
6712 "
6713 {
6714 if (!TARGET_FPRS)
6715 {
6716 if (!REG_P (operands[1]))
6717 operands[1] = force_reg (SImode, operands[1]);
6718 }
6719 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
6720 {
6721 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
6722 DONE;
6723 }
6724 else
6725 {
6726 rtx dreg = operands[1];
6727 if (!REG_P (dreg))
6728 dreg = force_reg (SImode, dreg);
6729 dreg = convert_to_mode (DImode, dreg, true);
6730 emit_insn (gen_floatdisf2 (operands[0], dreg));
6731 DONE;
6732 }
6733 }")
6735 (define_expand "floatunssidf2"
6736 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6737 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
6738 (use (match_dup 2))
6739 (use (match_dup 3))
6740 (clobber (match_dup 4))
6741 (clobber (match_dup 5))])]
6742 "TARGET_HARD_FLOAT
6743 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6744 "
6745 {
6746 if (TARGET_E500_DOUBLE)
6747 {
6748 if (!REG_P (operands[1]))
6749 operands[1] = force_reg (SImode, operands[1]);
6750 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
6751 DONE;
6752 }
6753 else if (TARGET_LFIWZX && TARGET_FCFID)
6754 {
6755 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
6756 DONE;
6757 }
6758 else if (TARGET_FCFID)
6759 {
6760 rtx dreg = operands[1];
6761 if (!REG_P (dreg))
6762 dreg = force_reg (SImode, dreg);
6763 dreg = convert_to_mode (DImode, dreg, true);
6764 emit_insn (gen_floatdidf2 (operands[0], dreg));
6765 DONE;
6766 }
6768 if (!REG_P (operands[1]))
6769 operands[1] = force_reg (SImode, operands[1]);
6770 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6771 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
6772 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
6773 operands[5] = gen_reg_rtx (DFmode);
6774 }")
6776 (define_insn_and_split "*floatunssidf2_internal"
6777 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6778 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6779 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6780 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6781 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6782 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
6783 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6784 && !(TARGET_FCFID && TARGET_POWERPC64)"
6785 "#"
6786 ""
6787 [(pc)]
6788 "
6789 {
6790 rtx lowword, highword;
6791 gcc_assert (MEM_P (operands[4]));
6792 highword = adjust_address (operands[4], SImode, 0);
6793 lowword = adjust_address (operands[4], SImode, 4);
6794 if (! WORDS_BIG_ENDIAN)
6795 {
6796 rtx tmp;
6797 tmp = highword; highword = lowword; lowword = tmp;
6798 }
6800 emit_move_insn (lowword, operands[1]);
6801 emit_move_insn (highword, operands[2]);
6802 emit_move_insn (operands[5], operands[4]);
6803 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6804 DONE;
6805 }"
6806 [(set_attr "length" "20")
6807 (set_attr "type" "fp")])
6809 (define_expand "fix_trunc<mode>si2"
6810 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6811 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6812 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT
6813 && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
6814 "
6815 {
6816 if (!<E500_CONVERT>)
6817 {
6818 rtx tmp, stack;
6820 if (TARGET_STFIWX)
6821 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
6822 else
6823 {
6824 tmp = gen_reg_rtx (DImode);
6825 stack = rs6000_allocate_stack_temp (DImode, true, false);
6826 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
6827 tmp, stack));
6828 }
6829 DONE;
6830 }
6831 }")
6833 ; Like the convert to float patterns, this insn must be split before
6834 ; register allocation so that it can allocate the memory slot if it
6835 ; needed
6836 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
6837 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
6838 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
6839 (clobber (match_scratch:DI 2 "=d"))]
6840 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6841 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
6842 && TARGET_STFIWX && can_create_pseudo_p ()"
6843 "#"
6844 ""
6845 [(pc)]
6846 {
6847 rtx dest = operands[0];
6848 rtx src = operands[1];
6849 rtx tmp = operands[2];
6851 if (GET_CODE (tmp) == SCRATCH)
6852 tmp = gen_reg_rtx (DImode);
6854 emit_insn (gen_fctiwz_<mode> (tmp, src));
6855 if (MEM_P (dest))
6856 {
6857 dest = rs6000_address_for_fpconvert (dest);
6858 emit_insn (gen_stfiwx (dest, tmp));
6859 DONE;
6860 }
6861 else if (TARGET_MFPGPR && TARGET_POWERPC64)
6862 {
6863 dest = gen_lowpart (DImode, dest);
6864 emit_move_insn (dest, tmp);
6865 DONE;
6866 }
6867 else
6868 {
6869 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6870 emit_insn (gen_stfiwx (stack, tmp));
6871 emit_move_insn (dest, stack);
6872 DONE;
6873 }
6874 }
6875 [(set_attr "length" "12")
6876 (set_attr "type" "fp")])
6878 (define_insn_and_split "fix_trunc<mode>si2_internal"
6879 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
6880 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
6881 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
6882 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
6883 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6884 && TARGET_DOUBLE_FLOAT"
6885 "#"
6886 ""
6887 [(pc)]
6888 "
6889 {
6890 rtx lowword;
6891 gcc_assert (MEM_P (operands[3]));
6892 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6894 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
6895 emit_move_insn (operands[3], operands[2]);
6896 emit_move_insn (operands[0], lowword);
6897 DONE;
6898 }"
6899 [(set_attr "length" "16")
6900 (set_attr "type" "fp")])
6902 (define_expand "fix_trunc<mode>di2"
6903 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6904 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6905 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6906 && TARGET_FCFID"
6907 "")
6909 (define_insn "*fix_trunc<mode>di2_fctidz"
6910 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6911 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6912 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6913 && TARGET_FCFID && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6914 "fctidz %0,%1"
6915 [(set_attr "type" "fp")])
6917 (define_expand "fixuns_trunc<mode>si2"
6918 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6919 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6920 "TARGET_HARD_FLOAT
6921 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
6922 || <E500_CONVERT>)"
6923 "
6924 {
6925 if (!<E500_CONVERT>)
6926 {
6927 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
6928 DONE;
6929 }
6930 }")
6932 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
6933 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
6934 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
6935 (clobber (match_scratch:DI 2 "=d"))]
6936 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
6937 && TARGET_STFIWX && can_create_pseudo_p ()"
6938 "#"
6939 ""
6940 [(pc)]
6941 {
6942 rtx dest = operands[0];
6943 rtx src = operands[1];
6944 rtx tmp = operands[2];
6946 if (GET_CODE (tmp) == SCRATCH)
6947 tmp = gen_reg_rtx (DImode);
6949 emit_insn (gen_fctiwuz_<mode> (tmp, src));
6950 if (MEM_P (dest))
6951 {
6952 dest = rs6000_address_for_fpconvert (dest);
6953 emit_insn (gen_stfiwx (dest, tmp));
6954 DONE;
6955 }
6956 else if (TARGET_MFPGPR && TARGET_POWERPC64)
6957 {
6958 dest = gen_lowpart (DImode, dest);
6959 emit_move_insn (dest, tmp);
6960 DONE;
6961 }
6962 else
6963 {
6964 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6965 emit_insn (gen_stfiwx (stack, tmp));
6966 emit_move_insn (dest, stack);
6967 DONE;
6968 }
6969 }
6970 [(set_attr "length" "12")
6971 (set_attr "type" "fp")])
6973 (define_expand "fixuns_trunc<mode>di2"
6974 [(set (match_operand:DI 0 "register_operand" "")
6975 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
6976 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
6977 "")
6979 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
6980 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6981 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6982 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6983 && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6984 "fctiduz %0,%1"
6985 [(set_attr "type" "fp")])
6987 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6988 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6989 ; because the first makes it clear that operand 0 is not live
6990 ; before the instruction.
6991 (define_insn "fctiwz_<mode>"
6992 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6993 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
6994 UNSPEC_FCTIWZ))]
6995 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6996 && TARGET_DOUBLE_FLOAT"
6997 "{fcirz|fctiwz} %0,%1"
6998 [(set_attr "type" "fp")])
7000 (define_insn "fctiwuz_<mode>"
7001 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
7002 (unspec:DI [(unsigned_fix:SI
7003 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>"))]
7004 UNSPEC_FCTIWUZ))]
7005 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
7006 "fctiwuz %0,%1"
7007 [(set_attr "type" "fp")])
7009 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
7010 ;; since the friz instruction does not truncate the value if the floating
7011 ;; point value is < LONG_MIN or > LONG_MAX.
7012 (define_insn "*friz"
7013 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7014 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))]
7015 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
7016 && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations
7017 && !flag_trapping_math && TARGET_FRIZ"
7018 "friz %0,%1"
7019 [(set_attr "type" "fp")])
7021 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
7022 ;; load to properly sign extend the value, but at least doing a store, load
7023 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
7024 ;; if we have 32-bit memory ops
7025 (define_insn_and_split "*round32<mode>2_fprs"
7026 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
7027 (float:SFDF
7028 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
7029 (clobber (match_scratch:DI 2 "=d"))
7030 (clobber (match_scratch:DI 3 "=d"))]
7031 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
7032 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
7033 && can_create_pseudo_p ()"
7034 "#"
7035 ""
7036 [(pc)]
7037 {
7038 rtx dest = operands[0];
7039 rtx src = operands[1];
7040 rtx tmp1 = operands[2];
7041 rtx tmp2 = operands[3];
7042 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
7044 if (GET_CODE (tmp1) == SCRATCH)
7045 tmp1 = gen_reg_rtx (DImode);
7046 if (GET_CODE (tmp2) == SCRATCH)
7047 tmp2 = gen_reg_rtx (DImode);
7049 emit_insn (gen_fctiwz_<mode> (tmp1, src));
7050 emit_insn (gen_stfiwx (stack, tmp1));
7051 emit_insn (gen_lfiwax (tmp2, stack));
7052 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
7053 DONE;
7054 }
7055 [(set_attr "type" "fpload")
7056 (set_attr "length" "16")])
7058 (define_insn_and_split "*roundu32<mode>2_fprs"
7059 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
7060 (unsigned_float:SFDF
7061 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
7062 (clobber (match_scratch:DI 2 "=d"))
7063 (clobber (match_scratch:DI 3 "=d"))]
7064 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
7065 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
7066 && can_create_pseudo_p ()"
7067 "#"
7068 ""
7069 [(pc)]
7070 {
7071 rtx dest = operands[0];
7072 rtx src = operands[1];
7073 rtx tmp1 = operands[2];
7074 rtx tmp2 = operands[3];
7075 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
7077 if (GET_CODE (tmp1) == SCRATCH)
7078 tmp1 = gen_reg_rtx (DImode);
7079 if (GET_CODE (tmp2) == SCRATCH)
7080 tmp2 = gen_reg_rtx (DImode);
7082 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
7083 emit_insn (gen_stfiwx (stack, tmp1));
7084 emit_insn (gen_lfiwzx (tmp2, stack));
7085 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
7086 DONE;
7087 }
7088 [(set_attr "type" "fpload")
7089 (set_attr "length" "16")])
7091 ;; No VSX equivalent to fctid
7092 (define_insn "lrint<mode>di2"
7093 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
7094 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7095 UNSPEC_FCTID))]
7096 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7097 "fctid %0,%1"
7098 [(set_attr "type" "fp")])
7100 (define_expand "btrunc<mode>2"
7101 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
7102 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
7103 UNSPEC_FRIZ))]
7104 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7105 "")
7107 (define_insn "*btrunc<mode>2_fpr"
7108 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
7109 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7110 UNSPEC_FRIZ))]
7111 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
7112 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
7113 "friz %0,%1"
7114 [(set_attr "type" "fp")])
7116 (define_expand "ceil<mode>2"
7117 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
7118 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
7119 UNSPEC_FRIP))]
7120 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7121 "")
7123 (define_insn "*ceil<mode>2_fpr"
7124 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
7125 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7126 UNSPEC_FRIP))]
7127 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
7128 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
7129 "frip %0,%1"
7130 [(set_attr "type" "fp")])
7132 (define_expand "floor<mode>2"
7133 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
7134 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
7135 UNSPEC_FRIM))]
7136 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7137 "")
7139 (define_insn "*floor<mode>2_fpr"
7140 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
7141 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7142 UNSPEC_FRIM))]
7143 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
7144 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
7145 "frim %0,%1"
7146 [(set_attr "type" "fp")])
7148 ;; No VSX equivalent to frin
7149 (define_insn "round<mode>2"
7150 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
7151 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
7152 UNSPEC_FRIN))]
7153 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
7154 "frin %0,%1"
7155 [(set_attr "type" "fp")])
7157 ; An UNSPEC is used so we don't have to support SImode in FP registers.
7158 (define_insn "stfiwx"
7159 [(set (match_operand:SI 0 "memory_operand" "=Z")
7160 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
7161 UNSPEC_STFIWX))]
7162 "TARGET_PPC_GFXOPT"
7163 "stfiwx %1,%y0"
7164 [(set_attr "type" "fpstore")])
7166 ;; If we don't have a direct conversion to single precision, don't enable this
7167 ;; conversion for 32-bit without fast math, because we don't have the insn to
7168 ;; generate the fixup swizzle to avoid double rounding problems.
7169 (define_expand "floatsisf2"
7170 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7171 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
7172 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
7173 && (!TARGET_FPRS
7174 || (TARGET_FPRS
7175 && ((TARGET_FCFIDS && TARGET_LFIWAX)
7176 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
7177 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
7178 "
7179 {
7180 if (!TARGET_FPRS)
7181 {
7182 if (!REG_P (operands[1]))
7183 operands[1] = force_reg (SImode, operands[1]);
7184 }
7185 else if (TARGET_FCFIDS && TARGET_LFIWAX)
7186 {
7187 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
7188 DONE;
7189 }
7190 else if (TARGET_FCFID && TARGET_LFIWAX)
7191 {
7192 rtx dfreg = gen_reg_rtx (DFmode);
7193 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
7194 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
7195 DONE;
7196 }
7197 else
7198 {
7199 rtx dreg = operands[1];
7200 if (!REG_P (dreg))
7201 dreg = force_reg (SImode, dreg);
7202 dreg = convert_to_mode (DImode, dreg, false);
7203 emit_insn (gen_floatdisf2 (operands[0], dreg));
7204 DONE;
7205 }
7206 }")
7208 (define_expand "floatdidf2"
7209 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7210 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
7211 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
7212 "")
7214 (define_insn "*floatdidf2_fpr"
7215 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7216 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
7217 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
7218 && !VECTOR_UNIT_VSX_P (DFmode)"
7219 "fcfid %0,%1"
7220 [(set_attr "type" "fp")])
7222 ; Allow the combiner to merge source memory operands to the conversion so that
7223 ; the optimizer/register allocator doesn't try to load the value too early in a
7224 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
7225 ; hit. We will split after reload to avoid the trip through the GPRs
7227 (define_insn_and_split "*floatdidf2_mem"
7228 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7229 (float:DF (match_operand:DI 1 "memory_operand" "m")))
7230 (clobber (match_scratch:DI 2 "=d"))]
7231 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
7232 "#"
7233 "&& reload_completed"
7234 [(set (match_dup 2) (match_dup 1))
7235 (set (match_dup 0) (float:DF (match_dup 2)))]
7236 ""
7237 [(set_attr "length" "8")
7238 (set_attr "type" "fpload")])
7240 (define_expand "floatunsdidf2"
7241 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7242 (unsigned_float:DF
7243 (match_operand:DI 1 "gpc_reg_operand" "")))]
7244 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
7245 "")
7247 (define_insn "*floatunsdidf2_fcfidu"
7248 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7249 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
7250 "TARGET_HARD_FLOAT && TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
7251 "fcfidu %0,%1"
7252 [(set_attr "type" "fp")
7253 (set_attr "length" "4")])
7255 (define_insn_and_split "*floatunsdidf2_mem"
7256 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7257 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
7258 (clobber (match_scratch:DI 2 "=d"))]
7259 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
7260 "#"
7261 "&& reload_completed"
7262 [(set (match_dup 2) (match_dup 1))
7263 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
7264 ""
7265 [(set_attr "length" "8")
7266 (set_attr "type" "fpload")])
7268 (define_expand "floatdisf2"
7269 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7270 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
7271 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7272 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
7273 "
7274 {
7275 if (!TARGET_FCFIDS)
7276 {
7277 rtx val = operands[1];
7278 if (!flag_unsafe_math_optimizations)
7279 {
7280 rtx label = gen_label_rtx ();
7281 val = gen_reg_rtx (DImode);
7282 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
7283 emit_label (label);
7284 }
7285 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
7286 DONE;
7287 }
7288 }")
7290 (define_insn "floatdisf2_fcfids"
7291 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7292 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
7293 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7294 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
7295 "fcfids %0,%1"
7296 [(set_attr "type" "fp")])
7298 (define_insn_and_split "*floatdisf2_mem"
7299 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7300 (float:SF (match_operand:DI 1 "memory_operand" "m")))
7301 (clobber (match_scratch:DI 2 "=f"))]
7302 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7303 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
7304 "#"
7305 "&& reload_completed"
7306 [(pc)]
7307 "
7308 {
7309 emit_move_insn (operands[2], operands[1]);
7310 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
7311 DONE;
7312 }"
7313 [(set_attr "length" "8")])
7315 ;; This is not IEEE compliant if rounding mode is "round to nearest".
7316 ;; If the DI->DF conversion is inexact, then it's possible to suffer
7317 ;; from double rounding.
7318 ;; Instead of creating a new cpu type for two FP operations, just use fp
7319 (define_insn_and_split "floatdisf2_internal1"
7320 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7321 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
7322 (clobber (match_scratch:DF 2 "=d"))]
7323 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
7324 "#"
7325 "&& reload_completed"
7326 [(set (match_dup 2)
7327 (float:DF (match_dup 1)))
7328 (set (match_dup 0)
7329 (float_truncate:SF (match_dup 2)))]
7330 ""
7331 [(set_attr "length" "8")
7332 (set_attr "type" "fp")])
7334 ;; Twiddles bits to avoid double rounding.
7335 ;; Bits that might be truncated when converting to DFmode are replaced
7336 ;; by a bit that won't be lost at that stage, but is below the SFmode
7337 ;; rounding position.
7338 (define_expand "floatdisf2_internal2"
7339 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
7340 (const_int 53)))
7341 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
7342 (const_int 2047)))
7343 (clobber (scratch:CC))])
7344 (set (match_dup 3) (plus:DI (match_dup 3)
7345 (const_int 1)))
7346 (set (match_dup 0) (plus:DI (match_dup 0)
7347 (const_int 2047)))
7348 (set (match_dup 4) (compare:CCUNS (match_dup 3)
7349 (const_int 2)))
7350 (set (match_dup 0) (ior:DI (match_dup 0)
7351 (match_dup 1)))
7352 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
7353 (const_int -2048)))
7354 (clobber (scratch:CC))])
7355 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
7356 (label_ref (match_operand:DI 2 "" ""))
7357 (pc)))
7358 (set (match_dup 0) (match_dup 1))]
7359 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
7360 "
7361 {
7362 operands[3] = gen_reg_rtx (DImode);
7363 operands[4] = gen_reg_rtx (CCUNSmode);
7364 }")
7366 (define_expand "floatunsdisf2"
7367 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7368 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
7369 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7370 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
7371 "")
7373 (define_insn "floatunsdisf2_fcfidus"
7374 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7375 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
7376 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7377 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
7378 "fcfidus %0,%1"
7379 [(set_attr "type" "fp")])
7381 (define_insn_and_split "*floatunsdisf2_mem"
7382 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7383 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m")))
7384 (clobber (match_scratch:DI 2 "=f"))]
7385 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7386 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
7387 "#"
7388 "&& reload_completed"
7389 [(pc)]
7390 "
7391 {
7392 emit_move_insn (operands[2], operands[1]);
7393 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
7394 DONE;
7395 }"
7396 [(set_attr "length" "8")
7397 (set_attr "type" "fpload")])
7398 \f
7399 ;; Define the DImode operations that can be done in a small number
7400 ;; of instructions. The & constraints are to prevent the register
7401 ;; allocator from allocating registers that overlap with the inputs
7402 ;; (for example, having an input in 7,8 and an output in 6,7). We
7403 ;; also allow for the output being the same as one of the inputs.
7405 (define_insn "*adddi3_noppc64"
7406 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
7407 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
7408 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
7409 "! TARGET_POWERPC64"
7410 "*
7411 {
7412 if (WORDS_BIG_ENDIAN)
7413 return (GET_CODE (operands[2])) != CONST_INT
7414 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
7415 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
7416 else
7417 return (GET_CODE (operands[2])) != CONST_INT
7418 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
7419 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
7420 }"
7421 [(set_attr "type" "two")
7422 (set_attr "length" "8")])
7424 (define_insn "*subdi3_noppc64"
7425 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
7426 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
7427 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
7428 "! TARGET_POWERPC64"
7429 "*
7430 {
7431 if (WORDS_BIG_ENDIAN)
7432 return (GET_CODE (operands[1]) != CONST_INT)
7433 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
7434 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
7435 else
7436 return (GET_CODE (operands[1]) != CONST_INT)
7437 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
7438 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
7439 }"
7440 [(set_attr "type" "two")
7441 (set_attr "length" "8")])
7443 (define_insn "*negdi2_noppc64"
7444 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7445 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
7446 "! TARGET_POWERPC64"
7447 "*
7448 {
7449 return (WORDS_BIG_ENDIAN)
7450 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
7451 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
7452 }"
7453 [(set_attr "type" "two")
7454 (set_attr "length" "8")])
7456 (define_expand "mulsidi3"
7457 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7458 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7459 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7460 "! TARGET_POWERPC64"
7461 "
7462 {
7463 if (! TARGET_POWER && ! TARGET_POWERPC)
7464 {
7465 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
7466 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
7467 emit_insn (gen_mull_call ());
7468 if (WORDS_BIG_ENDIAN)
7469 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
7470 else
7471 {
7472 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
7473 gen_rtx_REG (SImode, 3));
7474 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
7475 gen_rtx_REG (SImode, 4));
7476 }
7477 DONE;
7478 }
7479 else if (TARGET_POWER)
7480 {
7481 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
7482 DONE;
7483 }
7484 }")
7486 (define_insn "mulsidi3_mq"
7487 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7488 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7489 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
7490 (clobber (match_scratch:SI 3 "=q"))]
7491 "TARGET_POWER"
7492 "mul %0,%1,%2\;mfmq %L0"
7493 [(set_attr "type" "imul")
7494 (set_attr "length" "8")])
7496 (define_insn "*mulsidi3_no_mq"
7497 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7498 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7499 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
7500 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
7501 "*
7502 {
7503 return (WORDS_BIG_ENDIAN)
7504 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
7505 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
7506 }"
7507 [(set_attr "type" "imul")
7508 (set_attr "length" "8")])
7510 (define_split
7511 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7512 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7513 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7514 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
7515 [(set (match_dup 3)
7516 (truncate:SI
7517 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
7518 (sign_extend:DI (match_dup 2)))
7519 (const_int 32))))
7520 (set (match_dup 4)
7521 (mult:SI (match_dup 1)
7522 (match_dup 2)))]
7523 "
7524 {
7525 int endian = (WORDS_BIG_ENDIAN == 0);
7526 operands[3] = operand_subword (operands[0], endian, 0, DImode);
7527 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
7528 }")
7530 (define_expand "umulsidi3"
7531 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7532 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7533 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7534 "TARGET_POWERPC && ! TARGET_POWERPC64"
7535 "
7536 {
7537 if (TARGET_POWER)
7538 {
7539 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
7540 DONE;
7541 }
7542 }")
7544 (define_insn "umulsidi3_mq"
7545 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7546 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7547 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
7548 (clobber (match_scratch:SI 3 "=q"))]
7549 "TARGET_POWERPC && TARGET_POWER"
7550 "*
7551 {
7552 return (WORDS_BIG_ENDIAN)
7553 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
7554 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
7555 }"
7556 [(set_attr "type" "imul")
7557 (set_attr "length" "8")])
7559 (define_insn "*umulsidi3_no_mq"
7560 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7561 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7562 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
7563 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
7564 "*
7565 {
7566 return (WORDS_BIG_ENDIAN)
7567 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
7568 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
7569 }"
7570 [(set_attr "type" "imul")
7571 (set_attr "length" "8")])
7573 (define_split
7574 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7575 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7576 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7577 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
7578 [(set (match_dup 3)
7579 (truncate:SI
7580 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
7581 (zero_extend:DI (match_dup 2)))
7582 (const_int 32))))
7583 (set (match_dup 4)
7584 (mult:SI (match_dup 1)
7585 (match_dup 2)))]
7586 "
7587 {
7588 int endian = (WORDS_BIG_ENDIAN == 0);
7589 operands[3] = operand_subword (operands[0], endian, 0, DImode);
7590 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
7591 }")
7593 (define_expand "smulsi3_highpart"
7594 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7595 (truncate:SI
7596 (lshiftrt:DI (mult:DI (sign_extend:DI
7597 (match_operand:SI 1 "gpc_reg_operand" ""))
7598 (sign_extend:DI
7599 (match_operand:SI 2 "gpc_reg_operand" "")))
7600 (const_int 32))))]
7601 ""
7602 "
7603 {
7604 if (! TARGET_POWER && ! TARGET_POWERPC)
7605 {
7606 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
7607 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
7608 emit_insn (gen_mulh_call ());
7609 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
7610 DONE;
7611 }
7612 else if (TARGET_POWER)
7613 {
7614 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7615 DONE;
7616 }
7617 }")
7619 (define_insn "smulsi3_highpart_mq"
7620 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7621 (truncate:SI
7622 (lshiftrt:DI (mult:DI (sign_extend:DI
7623 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7624 (sign_extend:DI
7625 (match_operand:SI 2 "gpc_reg_operand" "r")))
7626 (const_int 32))))
7627 (clobber (match_scratch:SI 3 "=q"))]
7628 "TARGET_POWER"
7629 "mul %0,%1,%2"
7630 [(set_attr "type" "imul")])
7632 (define_insn "*smulsi3_highpart_no_mq"
7633 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7634 (truncate:SI
7635 (lshiftrt:DI (mult:DI (sign_extend:DI
7636 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7637 (sign_extend:DI
7638 (match_operand:SI 2 "gpc_reg_operand" "r")))
7639 (const_int 32))))]
7640 "TARGET_POWERPC && ! TARGET_POWER"
7641 "mulhw %0,%1,%2"
7642 [(set_attr "type" "imul")])
7644 (define_expand "umulsi3_highpart"
7645 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7646 (truncate:SI
7647 (lshiftrt:DI (mult:DI (zero_extend:DI
7648 (match_operand:SI 1 "gpc_reg_operand" ""))
7649 (zero_extend:DI
7650 (match_operand:SI 2 "gpc_reg_operand" "")))
7651 (const_int 32))))]
7652 "TARGET_POWERPC"
7653 "
7654 {
7655 if (TARGET_POWER)
7656 {
7657 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7658 DONE;
7659 }
7660 }")
7662 (define_insn "umulsi3_highpart_mq"
7663 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7664 (truncate:SI
7665 (lshiftrt:DI (mult:DI (zero_extend:DI
7666 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7667 (zero_extend:DI
7668 (match_operand:SI 2 "gpc_reg_operand" "r")))
7669 (const_int 32))))
7670 (clobber (match_scratch:SI 3 "=q"))]
7671 "TARGET_POWERPC && TARGET_POWER"
7672 "mulhwu %0,%1,%2"
7673 [(set_attr "type" "imul")])
7675 (define_insn "*umulsi3_highpart_no_mq"
7676 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7677 (truncate:SI
7678 (lshiftrt:DI (mult:DI (zero_extend:DI
7679 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7680 (zero_extend:DI
7681 (match_operand:SI 2 "gpc_reg_operand" "r")))
7682 (const_int 32))))]
7683 "TARGET_POWERPC && ! TARGET_POWER"
7684 "mulhwu %0,%1,%2"
7685 [(set_attr "type" "imul")])
7687 ;; If operands 0 and 2 are in the same register, we have a problem. But
7688 ;; operands 0 and 1 (the usual case) can be in the same register. That's
7689 ;; why we have the strange constraints below.
7690 (define_insn "ashldi3_power"
7691 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7692 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7693 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7694 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7695 "TARGET_POWER"
7696 "@
7697 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
7698 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7699 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7700 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
7701 [(set_attr "length" "8")])
7703 (define_insn "lshrdi3_power"
7704 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7705 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7706 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7707 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7708 "TARGET_POWER"
7709 "@
7710 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
7711 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7712 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7713 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
7714 [(set_attr "length" "8")])
7716 ;; Shift by a variable amount is too complex to be worth open-coding. We
7717 ;; just handle shifts by constants.
7718 (define_insn "ashrdi3_power"
7719 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7720 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7721 (match_operand:SI 2 "const_int_operand" "M,i")))
7722 (clobber (match_scratch:SI 3 "=X,q"))]
7723 "TARGET_POWER"
7724 "@
7725 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7726 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
7727 [(set_attr "type" "shift")
7728 (set_attr "length" "8")])
7730 (define_insn "ashrdi3_no_power"
7731 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
7732 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7733 (match_operand:SI 2 "const_int_operand" "M,i")))]
7734 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
7735 "@
7736 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7737 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
7738 [(set_attr "type" "two,three")
7739 (set_attr "length" "8,12")])
7741 (define_insn "*ashrdisi3_noppc64"
7742 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7743 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7744 (const_int 32)) 4))]
7745 "TARGET_32BIT && !TARGET_POWERPC64"
7746 "*
7747 {
7748 if (REGNO (operands[0]) == REGNO (operands[1]))
7749 return \"\";
7750 else
7751 return \"mr %0,%1\";
7752 }"
7753 [(set_attr "length" "4")])
7755 \f
7756 ;; PowerPC64 DImode operations.
7758 (define_expand "absdi2"
7759 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7760 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
7761 "TARGET_POWERPC64"
7762 "
7763 {
7764 if (TARGET_ISEL)
7765 emit_insn (gen_absdi2_isel (operands[0], operands[1]));
7766 else
7767 emit_insn (gen_absdi2_internal (operands[0], operands[1]));
7768 DONE;
7769 }")
7771 (define_insn_and_split "absdi2_internal"
7772 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7773 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
7774 (clobber (match_scratch:DI 2 "=&r,&r"))]
7775 "TARGET_POWERPC64 && !TARGET_ISEL"
7776 "#"
7777 "&& reload_completed"
7778 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7779 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7780 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
7781 "")
7783 (define_insn_and_split "*nabsdi2"
7784 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7785 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
7786 (clobber (match_scratch:DI 2 "=&r,&r"))]
7787 "TARGET_POWERPC64 && !TARGET_ISEL"
7788 "#"
7789 "&& reload_completed"
7790 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7791 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7792 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
7793 "")
7795 (define_insn "muldi3"
7796 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7797 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7798 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
7799 "TARGET_POWERPC64"
7800 "@
7801 mulld %0,%1,%2
7802 mulli %0,%1,%2"
7803 [(set (attr "type")
7804 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
7805 (const_string "imul3")
7806 (match_operand:SI 2 "short_cint_operand" "")
7807 (const_string "imul2")]
7808 (const_string "lmul")))])
7810 (define_insn "*muldi3_internal1"
7811 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7812 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7813 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7814 (const_int 0)))
7815 (clobber (match_scratch:DI 3 "=r,r"))]
7816 "TARGET_POWERPC64"
7817 "@
7818 mulld. %3,%1,%2
7819 #"
7820 [(set_attr "type" "lmul_compare")
7821 (set_attr "length" "4,8")])
7823 (define_split
7824 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7825 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7826 (match_operand:DI 2 "gpc_reg_operand" ""))
7827 (const_int 0)))
7828 (clobber (match_scratch:DI 3 ""))]
7829 "TARGET_POWERPC64 && reload_completed"
7830 [(set (match_dup 3)
7831 (mult:DI (match_dup 1) (match_dup 2)))
7832 (set (match_dup 0)
7833 (compare:CC (match_dup 3)
7834 (const_int 0)))]
7835 "")
7837 (define_insn "*muldi3_internal2"
7838 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7839 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7840 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7841 (const_int 0)))
7842 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7843 (mult:DI (match_dup 1) (match_dup 2)))]
7844 "TARGET_POWERPC64"
7845 "@
7846 mulld. %0,%1,%2
7847 #"
7848 [(set_attr "type" "lmul_compare")
7849 (set_attr "length" "4,8")])
7851 (define_split
7852 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7853 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7854 (match_operand:DI 2 "gpc_reg_operand" ""))
7855 (const_int 0)))
7856 (set (match_operand:DI 0 "gpc_reg_operand" "")
7857 (mult:DI (match_dup 1) (match_dup 2)))]
7858 "TARGET_POWERPC64 && reload_completed"
7859 [(set (match_dup 0)
7860 (mult:DI (match_dup 1) (match_dup 2)))
7861 (set (match_dup 3)
7862 (compare:CC (match_dup 0)
7863 (const_int 0)))]
7864 "")
7866 (define_insn "smuldi3_highpart"
7867 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7868 (truncate:DI
7869 (lshiftrt:TI (mult:TI (sign_extend:TI
7870 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7871 (sign_extend:TI
7872 (match_operand:DI 2 "gpc_reg_operand" "r")))
7873 (const_int 64))))]
7874 "TARGET_POWERPC64"
7875 "mulhd %0,%1,%2"
7876 [(set_attr "type" "lmul")])
7878 (define_insn "umuldi3_highpart"
7879 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7880 (truncate:DI
7881 (lshiftrt:TI (mult:TI (zero_extend:TI
7882 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7883 (zero_extend:TI
7884 (match_operand:DI 2 "gpc_reg_operand" "r")))
7885 (const_int 64))))]
7886 "TARGET_POWERPC64"
7887 "mulhdu %0,%1,%2"
7888 [(set_attr "type" "lmul")])
7890 (define_insn "rotldi3"
7891 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7892 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7893 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
7894 "TARGET_POWERPC64"
7895 "@
7896 rldcl %0,%1,%2,0
7897 rldicl %0,%1,%H2,0"
7898 [(set_attr "type" "var_shift_rotate,integer")])
7900 (define_insn "*rotldi3_internal2"
7901 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7902 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7903 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7904 (const_int 0)))
7905 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7906 "TARGET_64BIT"
7907 "@
7908 rldcl. %3,%1,%2,0
7909 rldicl. %3,%1,%H2,0
7910 #
7911 #"
7912 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7913 (set_attr "length" "4,4,8,8")])
7915 (define_split
7916 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7917 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7918 (match_operand:DI 2 "reg_or_cint_operand" ""))
7919 (const_int 0)))
7920 (clobber (match_scratch:DI 3 ""))]
7921 "TARGET_POWERPC64 && reload_completed"
7922 [(set (match_dup 3)
7923 (rotate:DI (match_dup 1) (match_dup 2)))
7924 (set (match_dup 0)
7925 (compare:CC (match_dup 3)
7926 (const_int 0)))]
7927 "")
7929 (define_insn "*rotldi3_internal3"
7930 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7931 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7932 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7933 (const_int 0)))
7934 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7935 (rotate:DI (match_dup 1) (match_dup 2)))]
7936 "TARGET_64BIT"
7937 "@
7938 rldcl. %0,%1,%2,0
7939 rldicl. %0,%1,%H2,0
7940 #
7941 #"
7942 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7943 (set_attr "length" "4,4,8,8")])
7945 (define_split
7946 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7947 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7948 (match_operand:DI 2 "reg_or_cint_operand" ""))
7949 (const_int 0)))
7950 (set (match_operand:DI 0 "gpc_reg_operand" "")
7951 (rotate:DI (match_dup 1) (match_dup 2)))]
7952 "TARGET_POWERPC64 && reload_completed"
7953 [(set (match_dup 0)
7954 (rotate:DI (match_dup 1) (match_dup 2)))
7955 (set (match_dup 3)
7956 (compare:CC (match_dup 0)
7957 (const_int 0)))]
7958 "")
7960 (define_insn "*rotldi3_internal4"
7961 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7962 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7963 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
7964 (match_operand:DI 3 "mask64_operand" "n,n")))]
7965 "TARGET_POWERPC64"
7966 "@
7967 rldc%B3 %0,%1,%2,%S3
7968 rldic%B3 %0,%1,%H2,%S3"
7969 [(set_attr "type" "var_shift_rotate,integer")])
7971 (define_insn "*rotldi3_internal5"
7972 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7973 (compare:CC (and:DI
7974 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7975 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7976 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7977 (const_int 0)))
7978 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
7979 "TARGET_64BIT"
7980 "@
7981 rldc%B3. %4,%1,%2,%S3
7982 rldic%B3. %4,%1,%H2,%S3
7983 #
7984 #"
7985 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7986 (set_attr "length" "4,4,8,8")])
7988 (define_split
7989 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7990 (compare:CC (and:DI
7991 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7992 (match_operand:DI 2 "reg_or_cint_operand" ""))
7993 (match_operand:DI 3 "mask64_operand" ""))
7994 (const_int 0)))
7995 (clobber (match_scratch:DI 4 ""))]
7996 "TARGET_POWERPC64 && reload_completed"
7997 [(set (match_dup 4)
7998 (and:DI (rotate:DI (match_dup 1)
7999 (match_dup 2))
8000 (match_dup 3)))
8001 (set (match_dup 0)
8002 (compare:CC (match_dup 4)
8003 (const_int 0)))]
8004 "")
8006 (define_insn "*rotldi3_internal6"
8007 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
8008 (compare:CC (and:DI
8009 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8010 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
8011 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
8012 (const_int 0)))
8013 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8014 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8015 "TARGET_64BIT"
8016 "@
8017 rldc%B3. %0,%1,%2,%S3
8018 rldic%B3. %0,%1,%H2,%S3
8019 #
8020 #"
8021 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8022 (set_attr "length" "4,4,8,8")])
8024 (define_split
8025 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
8026 (compare:CC (and:DI
8027 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8028 (match_operand:DI 2 "reg_or_cint_operand" ""))
8029 (match_operand:DI 3 "mask64_operand" ""))
8030 (const_int 0)))
8031 (set (match_operand:DI 0 "gpc_reg_operand" "")
8032 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8033 "TARGET_POWERPC64 && reload_completed"
8034 [(set (match_dup 0)
8035 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
8036 (set (match_dup 4)
8037 (compare:CC (match_dup 0)
8038 (const_int 0)))]
8039 "")
8041 (define_insn "*rotldi3_internal7"
8042 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8043 (zero_extend:DI
8044 (subreg:QI
8045 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8046 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
8047 "TARGET_POWERPC64"
8048 "@
8049 rldcl %0,%1,%2,56
8050 rldicl %0,%1,%H2,56"
8051 [(set_attr "type" "var_shift_rotate,integer")])
8053 (define_insn "*rotldi3_internal8"
8054 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8055 (compare:CC (zero_extend:DI
8056 (subreg:QI
8057 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8058 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8059 (const_int 0)))
8060 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8061 "TARGET_64BIT"
8062 "@
8063 rldcl. %3,%1,%2,56
8064 rldicl. %3,%1,%H2,56
8065 #
8066 #"
8067 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8068 (set_attr "length" "4,4,8,8")])
8070 (define_split
8071 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8072 (compare:CC (zero_extend:DI
8073 (subreg:QI
8074 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8075 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8076 (const_int 0)))
8077 (clobber (match_scratch:DI 3 ""))]
8078 "TARGET_POWERPC64 && reload_completed"
8079 [(set (match_dup 3)
8080 (zero_extend:DI (subreg:QI
8081 (rotate:DI (match_dup 1)
8082 (match_dup 2)) 0)))
8083 (set (match_dup 0)
8084 (compare:CC (match_dup 3)
8085 (const_int 0)))]
8086 "")
8088 (define_insn "*rotldi3_internal9"
8089 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8090 (compare:CC (zero_extend:DI
8091 (subreg:QI
8092 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8093 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8094 (const_int 0)))
8095 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8096 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8097 "TARGET_64BIT"
8098 "@
8099 rldcl. %0,%1,%2,56
8100 rldicl. %0,%1,%H2,56
8101 #
8102 #"
8103 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8104 (set_attr "length" "4,4,8,8")])
8106 (define_split
8107 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8108 (compare:CC (zero_extend:DI
8109 (subreg:QI
8110 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8111 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8112 (const_int 0)))
8113 (set (match_operand:DI 0 "gpc_reg_operand" "")
8114 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8115 "TARGET_POWERPC64 && reload_completed"
8116 [(set (match_dup 0)
8117 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
8118 (set (match_dup 3)
8119 (compare:CC (match_dup 0)
8120 (const_int 0)))]
8121 "")
8123 (define_insn "*rotldi3_internal10"
8124 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8125 (zero_extend:DI
8126 (subreg:HI
8127 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8128 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
8129 "TARGET_POWERPC64"
8130 "@
8131 rldcl %0,%1,%2,48
8132 rldicl %0,%1,%H2,48"
8133 [(set_attr "type" "var_shift_rotate,integer")])
8135 (define_insn "*rotldi3_internal11"
8136 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8137 (compare:CC (zero_extend:DI
8138 (subreg:HI
8139 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8140 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8141 (const_int 0)))
8142 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8143 "TARGET_64BIT"
8144 "@
8145 rldcl. %3,%1,%2,48
8146 rldicl. %3,%1,%H2,48
8147 #
8148 #"
8149 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8150 (set_attr "length" "4,4,8,8")])
8152 (define_split
8153 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8154 (compare:CC (zero_extend:DI
8155 (subreg:HI
8156 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8157 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8158 (const_int 0)))
8159 (clobber (match_scratch:DI 3 ""))]
8160 "TARGET_POWERPC64 && reload_completed"
8161 [(set (match_dup 3)
8162 (zero_extend:DI (subreg:HI
8163 (rotate:DI (match_dup 1)
8164 (match_dup 2)) 0)))
8165 (set (match_dup 0)
8166 (compare:CC (match_dup 3)
8167 (const_int 0)))]
8168 "")
8170 (define_insn "*rotldi3_internal12"
8171 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8172 (compare:CC (zero_extend:DI
8173 (subreg:HI
8174 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8175 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8176 (const_int 0)))
8177 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8178 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8179 "TARGET_64BIT"
8180 "@
8181 rldcl. %0,%1,%2,48
8182 rldicl. %0,%1,%H2,48
8183 #
8184 #"
8185 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8186 (set_attr "length" "4,4,8,8")])
8188 (define_split
8189 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8190 (compare:CC (zero_extend:DI
8191 (subreg:HI
8192 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8193 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8194 (const_int 0)))
8195 (set (match_operand:DI 0 "gpc_reg_operand" "")
8196 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8197 "TARGET_POWERPC64 && reload_completed"
8198 [(set (match_dup 0)
8199 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
8200 (set (match_dup 3)
8201 (compare:CC (match_dup 0)
8202 (const_int 0)))]
8203 "")
8205 (define_insn "*rotldi3_internal13"
8206 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8207 (zero_extend:DI
8208 (subreg:SI
8209 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8210 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
8211 "TARGET_POWERPC64"
8212 "@
8213 rldcl %0,%1,%2,32
8214 rldicl %0,%1,%H2,32"
8215 [(set_attr "type" "var_shift_rotate,integer")])
8217 (define_insn "*rotldi3_internal14"
8218 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8219 (compare:CC (zero_extend:DI
8220 (subreg:SI
8221 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8222 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8223 (const_int 0)))
8224 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8225 "TARGET_64BIT"
8226 "@
8227 rldcl. %3,%1,%2,32
8228 rldicl. %3,%1,%H2,32
8229 #
8230 #"
8231 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8232 (set_attr "length" "4,4,8,8")])
8234 (define_split
8235 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8236 (compare:CC (zero_extend:DI
8237 (subreg:SI
8238 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8239 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8240 (const_int 0)))
8241 (clobber (match_scratch:DI 3 ""))]
8242 "TARGET_POWERPC64 && reload_completed"
8243 [(set (match_dup 3)
8244 (zero_extend:DI (subreg:SI
8245 (rotate:DI (match_dup 1)
8246 (match_dup 2)) 0)))
8247 (set (match_dup 0)
8248 (compare:CC (match_dup 3)
8249 (const_int 0)))]
8250 "")
8252 (define_insn "*rotldi3_internal15"
8253 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8254 (compare:CC (zero_extend:DI
8255 (subreg:SI
8256 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8257 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
8258 (const_int 0)))
8259 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8260 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8261 "TARGET_64BIT"
8262 "@
8263 rldcl. %0,%1,%2,32
8264 rldicl. %0,%1,%H2,32
8265 #
8266 #"
8267 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8268 (set_attr "length" "4,4,8,8")])
8270 (define_split
8271 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8272 (compare:CC (zero_extend:DI
8273 (subreg:SI
8274 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
8275 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
8276 (const_int 0)))
8277 (set (match_operand:DI 0 "gpc_reg_operand" "")
8278 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
8279 "TARGET_POWERPC64 && reload_completed"
8280 [(set (match_dup 0)
8281 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
8282 (set (match_dup 3)
8283 (compare:CC (match_dup 0)
8284 (const_int 0)))]
8285 "")
8287 (define_expand "ashldi3"
8288 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8289 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8290 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8291 "TARGET_POWERPC64 || TARGET_POWER"
8292 "
8293 {
8294 if (TARGET_POWERPC64)
8295 ;
8296 else if (TARGET_POWER)
8297 {
8298 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
8299 DONE;
8300 }
8301 else
8302 FAIL;
8303 }")
8305 (define_insn "*ashldi3_internal1"
8306 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8307 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8308 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8309 "TARGET_POWERPC64"
8310 "@
8311 sld %0,%1,%2
8312 sldi %0,%1,%H2"
8313 [(set_attr "type" "var_shift_rotate,shift")])
8315 (define_insn "*ashldi3_internal2"
8316 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8317 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8318 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8319 (const_int 0)))
8320 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8321 "TARGET_64BIT"
8322 "@
8323 sld. %3,%1,%2
8324 sldi. %3,%1,%H2
8325 #
8326 #"
8327 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8328 (set_attr "length" "4,4,8,8")])
8330 (define_split
8331 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
8332 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8333 (match_operand:SI 2 "reg_or_cint_operand" ""))
8334 (const_int 0)))
8335 (clobber (match_scratch:DI 3 ""))]
8336 "TARGET_POWERPC64 && reload_completed"
8337 [(set (match_dup 3)
8338 (ashift:DI (match_dup 1) (match_dup 2)))
8339 (set (match_dup 0)
8340 (compare:CC (match_dup 3)
8341 (const_int 0)))]
8342 "")
8344 (define_insn "*ashldi3_internal3"
8345 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8346 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8347 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8348 (const_int 0)))
8349 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8350 (ashift:DI (match_dup 1) (match_dup 2)))]
8351 "TARGET_64BIT"
8352 "@
8353 sld. %0,%1,%2
8354 sldi. %0,%1,%H2
8355 #
8356 #"
8357 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8358 (set_attr "length" "4,4,8,8")])
8360 (define_split
8361 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
8362 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8363 (match_operand:SI 2 "reg_or_cint_operand" ""))
8364 (const_int 0)))
8365 (set (match_operand:DI 0 "gpc_reg_operand" "")
8366 (ashift:DI (match_dup 1) (match_dup 2)))]
8367 "TARGET_POWERPC64 && reload_completed"
8368 [(set (match_dup 0)
8369 (ashift:DI (match_dup 1) (match_dup 2)))
8370 (set (match_dup 3)
8371 (compare:CC (match_dup 0)
8372 (const_int 0)))]
8373 "")
8375 (define_insn "*ashldi3_internal4"
8376 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8377 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
8378 (match_operand:SI 2 "const_int_operand" "i"))
8379 (match_operand:DI 3 "const_int_operand" "n")))]
8380 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
8381 "rldic %0,%1,%H2,%W3")
8383 (define_insn "ashldi3_internal5"
8384 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8385 (compare:CC
8386 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8387 (match_operand:SI 2 "const_int_operand" "i,i"))
8388 (match_operand:DI 3 "const_int_operand" "n,n"))
8389 (const_int 0)))
8390 (clobber (match_scratch:DI 4 "=r,r"))]
8391 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
8392 "@
8393 rldic. %4,%1,%H2,%W3
8394 #"
8395 [(set_attr "type" "compare")
8396 (set_attr "length" "4,8")])
8398 (define_split
8399 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8400 (compare:CC
8401 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8402 (match_operand:SI 2 "const_int_operand" ""))
8403 (match_operand:DI 3 "const_int_operand" ""))
8404 (const_int 0)))
8405 (clobber (match_scratch:DI 4 ""))]
8406 "TARGET_POWERPC64 && reload_completed
8407 && includes_rldic_lshift_p (operands[2], operands[3])"
8408 [(set (match_dup 4)
8409 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8410 (match_dup 3)))
8411 (set (match_dup 0)
8412 (compare:CC (match_dup 4)
8413 (const_int 0)))]
8414 "")
8416 (define_insn "*ashldi3_internal6"
8417 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
8418 (compare:CC
8419 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8420 (match_operand:SI 2 "const_int_operand" "i,i"))
8421 (match_operand:DI 3 "const_int_operand" "n,n"))
8422 (const_int 0)))
8423 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8424 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8425 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
8426 "@
8427 rldic. %0,%1,%H2,%W3
8428 #"
8429 [(set_attr "type" "compare")
8430 (set_attr "length" "4,8")])
8432 (define_split
8433 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
8434 (compare:CC
8435 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8436 (match_operand:SI 2 "const_int_operand" ""))
8437 (match_operand:DI 3 "const_int_operand" ""))
8438 (const_int 0)))
8439 (set (match_operand:DI 0 "gpc_reg_operand" "")
8440 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8441 "TARGET_POWERPC64 && reload_completed
8442 && includes_rldic_lshift_p (operands[2], operands[3])"
8443 [(set (match_dup 0)
8444 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8445 (match_dup 3)))
8446 (set (match_dup 4)
8447 (compare:CC (match_dup 0)
8448 (const_int 0)))]
8449 "")
8451 (define_insn "*ashldi3_internal7"
8452 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8453 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
8454 (match_operand:SI 2 "const_int_operand" "i"))
8455 (match_operand:DI 3 "mask64_operand" "n")))]
8456 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
8457 "rldicr %0,%1,%H2,%S3")
8459 (define_insn "ashldi3_internal8"
8460 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8461 (compare:CC
8462 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8463 (match_operand:SI 2 "const_int_operand" "i,i"))
8464 (match_operand:DI 3 "mask64_operand" "n,n"))
8465 (const_int 0)))
8466 (clobber (match_scratch:DI 4 "=r,r"))]
8467 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
8468 "@
8469 rldicr. %4,%1,%H2,%S3
8470 #"
8471 [(set_attr "type" "compare")
8472 (set_attr "length" "4,8")])
8474 (define_split
8475 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8476 (compare:CC
8477 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8478 (match_operand:SI 2 "const_int_operand" ""))
8479 (match_operand:DI 3 "mask64_operand" ""))
8480 (const_int 0)))
8481 (clobber (match_scratch:DI 4 ""))]
8482 "TARGET_POWERPC64 && reload_completed
8483 && includes_rldicr_lshift_p (operands[2], operands[3])"
8484 [(set (match_dup 4)
8485 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8486 (match_dup 3)))
8487 (set (match_dup 0)
8488 (compare:CC (match_dup 4)
8489 (const_int 0)))]
8490 "")
8492 (define_insn "*ashldi3_internal9"
8493 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
8494 (compare:CC
8495 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8496 (match_operand:SI 2 "const_int_operand" "i,i"))
8497 (match_operand:DI 3 "mask64_operand" "n,n"))
8498 (const_int 0)))
8499 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8500 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8501 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
8502 "@
8503 rldicr. %0,%1,%H2,%S3
8504 #"
8505 [(set_attr "type" "compare")
8506 (set_attr "length" "4,8")])
8508 (define_split
8509 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
8510 (compare:CC
8511 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
8512 (match_operand:SI 2 "const_int_operand" ""))
8513 (match_operand:DI 3 "mask64_operand" ""))
8514 (const_int 0)))
8515 (set (match_operand:DI 0 "gpc_reg_operand" "")
8516 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
8517 "TARGET_POWERPC64 && reload_completed
8518 && includes_rldicr_lshift_p (operands[2], operands[3])"
8519 [(set (match_dup 0)
8520 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
8521 (match_dup 3)))
8522 (set (match_dup 4)
8523 (compare:CC (match_dup 0)
8524 (const_int 0)))]
8525 "")
8527 (define_expand "lshrdi3"
8528 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8529 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8530 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8531 "TARGET_POWERPC64 || TARGET_POWER"
8532 "
8533 {
8534 if (TARGET_POWERPC64)
8535 ;
8536 else if (TARGET_POWER)
8537 {
8538 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
8539 DONE;
8540 }
8541 else
8542 FAIL;
8543 }")
8545 (define_insn "*lshrdi3_internal1"
8546 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8547 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8548 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8549 "TARGET_POWERPC64"
8550 "@
8551 srd %0,%1,%2
8552 srdi %0,%1,%H2"
8553 [(set_attr "type" "var_shift_rotate,shift")])
8555 (define_insn "*lshrdi3_internal2"
8556 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8557 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8558 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8559 (const_int 0)))
8560 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8561 "TARGET_64BIT "
8562 "@
8563 srd. %3,%1,%2
8564 srdi. %3,%1,%H2
8565 #
8566 #"
8567 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8568 (set_attr "length" "4,4,8,8")])
8570 (define_split
8571 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8572 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8573 (match_operand:SI 2 "reg_or_cint_operand" ""))
8574 (const_int 0)))
8575 (clobber (match_scratch:DI 3 ""))]
8576 "TARGET_POWERPC64 && reload_completed"
8577 [(set (match_dup 3)
8578 (lshiftrt:DI (match_dup 1) (match_dup 2)))
8579 (set (match_dup 0)
8580 (compare:CC (match_dup 3)
8581 (const_int 0)))]
8582 "")
8584 (define_insn "*lshrdi3_internal3"
8585 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8586 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8587 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8588 (const_int 0)))
8589 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8590 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8591 "TARGET_64BIT"
8592 "@
8593 srd. %0,%1,%2
8594 srdi. %0,%1,%H2
8595 #
8596 #"
8597 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8598 (set_attr "length" "4,4,8,8")])
8600 (define_split
8601 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8602 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8603 (match_operand:SI 2 "reg_or_cint_operand" ""))
8604 (const_int 0)))
8605 (set (match_operand:DI 0 "gpc_reg_operand" "")
8606 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8607 "TARGET_POWERPC64 && reload_completed"
8608 [(set (match_dup 0)
8609 (lshiftrt:DI (match_dup 1) (match_dup 2)))
8610 (set (match_dup 3)
8611 (compare:CC (match_dup 0)
8612 (const_int 0)))]
8613 "")
8615 (define_expand "ashrdi3"
8616 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8617 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8618 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8619 "WORDS_BIG_ENDIAN"
8620 "
8621 {
8622 if (TARGET_POWERPC64)
8623 ;
8624 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
8625 {
8626 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
8627 DONE;
8628 }
8629 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
8630 && WORDS_BIG_ENDIAN)
8631 {
8632 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
8633 DONE;
8634 }
8635 else
8636 FAIL;
8637 }")
8639 (define_insn "*ashrdi3_internal1"
8640 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8641 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8642 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8643 "TARGET_POWERPC64"
8644 "@
8645 srad %0,%1,%2
8646 sradi %0,%1,%H2"
8647 [(set_attr "type" "var_shift_rotate,shift")])
8649 (define_insn "*ashrdi3_internal2"
8650 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8651 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8652 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8653 (const_int 0)))
8654 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8655 "TARGET_64BIT"
8656 "@
8657 srad. %3,%1,%2
8658 sradi. %3,%1,%H2
8659 #
8660 #"
8661 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8662 (set_attr "length" "4,4,8,8")])
8664 (define_split
8665 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
8666 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8667 (match_operand:SI 2 "reg_or_cint_operand" ""))
8668 (const_int 0)))
8669 (clobber (match_scratch:DI 3 ""))]
8670 "TARGET_POWERPC64 && reload_completed"
8671 [(set (match_dup 3)
8672 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8673 (set (match_dup 0)
8674 (compare:CC (match_dup 3)
8675 (const_int 0)))]
8676 "")
8678 (define_insn "*ashrdi3_internal3"
8679 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8680 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8681 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8682 (const_int 0)))
8683 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8684 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8685 "TARGET_64BIT"
8686 "@
8687 srad. %0,%1,%2
8688 sradi. %0,%1,%H2
8689 #
8690 #"
8691 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8692 (set_attr "length" "4,4,8,8")])
8694 (define_split
8695 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
8696 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8697 (match_operand:SI 2 "reg_or_cint_operand" ""))
8698 (const_int 0)))
8699 (set (match_operand:DI 0 "gpc_reg_operand" "")
8700 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8701 "TARGET_POWERPC64 && reload_completed"
8702 [(set (match_dup 0)
8703 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8704 (set (match_dup 3)
8705 (compare:CC (match_dup 0)
8706 (const_int 0)))]
8707 "")
8709 (define_expand "anddi3"
8710 [(parallel
8711 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8712 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8713 (match_operand:DI 2 "and64_2_operand" "")))
8714 (clobber (match_scratch:CC 3 ""))])]
8715 "TARGET_POWERPC64"
8716 "")
8718 (define_insn "anddi3_mc"
8719 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
8720 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
8721 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
8722 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
8723 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
8724 "@
8725 and %0,%1,%2
8726 rldic%B2 %0,%1,0,%S2
8727 rlwinm %0,%1,0,%m2,%M2
8728 andi. %0,%1,%b2
8729 andis. %0,%1,%u2
8730 #"
8731 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
8732 (set_attr "length" "4,4,4,4,4,8")])
8734 (define_insn "anddi3_nomc"
8735 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8736 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
8737 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
8738 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
8739 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
8740 "@
8741 and %0,%1,%2
8742 rldic%B2 %0,%1,0,%S2
8743 rlwinm %0,%1,0,%m2,%M2
8744 #"
8745 [(set_attr "length" "4,4,4,8")])
8747 (define_split
8748 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8749 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8750 (match_operand:DI 2 "mask64_2_operand" "")))
8751 (clobber (match_scratch:CC 3 ""))]
8752 "TARGET_POWERPC64
8753 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8754 && !mask_operand (operands[2], DImode)
8755 && !mask64_operand (operands[2], DImode)"
8756 [(set (match_dup 0)
8757 (and:DI (rotate:DI (match_dup 1)
8758 (match_dup 4))
8759 (match_dup 5)))
8760 (set (match_dup 0)
8761 (and:DI (rotate:DI (match_dup 0)
8762 (match_dup 6))
8763 (match_dup 7)))]
8764 {
8765 build_mask64_2_operands (operands[2], &operands[4]);
8766 })
8768 (define_insn "*anddi3_internal2_mc"
8769 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8770 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8771 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8772 (const_int 0)))
8773 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
8774 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8775 "TARGET_64BIT && rs6000_gen_cell_microcode"
8776 "@
8777 and. %3,%1,%2
8778 rldic%B2. %3,%1,0,%S2
8779 rlwinm. %3,%1,0,%m2,%M2
8780 andi. %3,%1,%b2
8781 andis. %3,%1,%u2
8782 #
8783 #
8784 #
8785 #
8786 #
8787 #
8788 #"
8789 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8790 fast_compare,compare,compare,compare,compare,compare,\
8791 compare,compare")
8792 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8794 (define_split
8795 [(set (match_operand:CC 0 "cc_reg_operand" "")
8796 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8797 (match_operand:DI 2 "mask64_2_operand" ""))
8798 (const_int 0)))
8799 (clobber (match_scratch:DI 3 ""))
8800 (clobber (match_scratch:CC 4 ""))]
8801 "TARGET_64BIT && reload_completed
8802 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8803 && !mask_operand (operands[2], DImode)
8804 && !mask64_operand (operands[2], DImode)"
8805 [(set (match_dup 3)
8806 (and:DI (rotate:DI (match_dup 1)
8807 (match_dup 5))
8808 (match_dup 6)))
8809 (parallel [(set (match_dup 0)
8810 (compare:CC (and:DI (rotate:DI (match_dup 3)
8811 (match_dup 7))
8812 (match_dup 8))
8813 (const_int 0)))
8814 (clobber (match_dup 3))])]
8815 "
8816 {
8817 build_mask64_2_operands (operands[2], &operands[5]);
8818 }")
8820 (define_insn "*anddi3_internal3_mc"
8821 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8822 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8823 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8824 (const_int 0)))
8825 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
8826 (and:DI (match_dup 1) (match_dup 2)))
8827 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8828 "TARGET_64BIT && rs6000_gen_cell_microcode"
8829 "@
8830 and. %0,%1,%2
8831 rldic%B2. %0,%1,0,%S2
8832 rlwinm. %0,%1,0,%m2,%M2
8833 andi. %0,%1,%b2
8834 andis. %0,%1,%u2
8835 #
8836 #
8837 #
8838 #
8839 #
8840 #
8841 #"
8842 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8843 fast_compare,compare,compare,compare,compare,compare,\
8844 compare,compare")
8845 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8847 (define_split
8848 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8849 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8850 (match_operand:DI 2 "and64_2_operand" ""))
8851 (const_int 0)))
8852 (set (match_operand:DI 0 "gpc_reg_operand" "")
8853 (and:DI (match_dup 1) (match_dup 2)))
8854 (clobber (match_scratch:CC 4 ""))]
8855 "TARGET_64BIT && reload_completed"
8856 [(parallel [(set (match_dup 0)
8857 (and:DI (match_dup 1) (match_dup 2)))
8858 (clobber (match_dup 4))])
8859 (set (match_dup 3)
8860 (compare:CC (match_dup 0)
8861 (const_int 0)))]
8862 "")
8864 (define_split
8865 [(set (match_operand:CC 3 "cc_reg_operand" "")
8866 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8867 (match_operand:DI 2 "mask64_2_operand" ""))
8868 (const_int 0)))
8869 (set (match_operand:DI 0 "gpc_reg_operand" "")
8870 (and:DI (match_dup 1) (match_dup 2)))
8871 (clobber (match_scratch:CC 4 ""))]
8872 "TARGET_64BIT && reload_completed
8873 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8874 && !mask_operand (operands[2], DImode)
8875 && !mask64_operand (operands[2], DImode)"
8876 [(set (match_dup 0)
8877 (and:DI (rotate:DI (match_dup 1)
8878 (match_dup 5))
8879 (match_dup 6)))
8880 (parallel [(set (match_dup 3)
8881 (compare:CC (and:DI (rotate:DI (match_dup 0)
8882 (match_dup 7))
8883 (match_dup 8))
8884 (const_int 0)))
8885 (set (match_dup 0)
8886 (and:DI (rotate:DI (match_dup 0)
8887 (match_dup 7))
8888 (match_dup 8)))])]
8889 "
8890 {
8891 build_mask64_2_operands (operands[2], &operands[5]);
8892 }")
8894 (define_expand "iordi3"
8895 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8896 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
8897 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8898 "TARGET_POWERPC64"
8899 "
8900 {
8901 if (non_logical_cint_operand (operands[2], DImode))
8902 {
8903 HOST_WIDE_INT value;
8904 rtx tmp = ((!can_create_pseudo_p ()
8905 || rtx_equal_p (operands[0], operands[1]))
8906 ? operands[0] : gen_reg_rtx (DImode));
8908 if (GET_CODE (operands[2]) == CONST_INT)
8909 {
8910 value = INTVAL (operands[2]);
8911 emit_insn (gen_iordi3 (tmp, operands[1],
8912 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8913 }
8914 else
8915 {
8916 value = CONST_DOUBLE_LOW (operands[2]);
8917 emit_insn (gen_iordi3 (tmp, operands[1],
8918 immed_double_const (value
8919 & (~ (HOST_WIDE_INT) 0xffff),
8920 0, DImode)));
8921 }
8923 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8924 DONE;
8925 }
8926 }")
8928 (define_expand "xordi3"
8929 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8930 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
8931 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8932 "TARGET_POWERPC64"
8933 "
8934 {
8935 if (non_logical_cint_operand (operands[2], DImode))
8936 {
8937 HOST_WIDE_INT value;
8938 rtx tmp = ((!can_create_pseudo_p ()
8939 || rtx_equal_p (operands[0], operands[1]))
8940 ? operands[0] : gen_reg_rtx (DImode));
8942 if (GET_CODE (operands[2]) == CONST_INT)
8943 {
8944 value = INTVAL (operands[2]);
8945 emit_insn (gen_xordi3 (tmp, operands[1],
8946 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8947 }
8948 else
8949 {
8950 value = CONST_DOUBLE_LOW (operands[2]);
8951 emit_insn (gen_xordi3 (tmp, operands[1],
8952 immed_double_const (value
8953 & (~ (HOST_WIDE_INT) 0xffff),
8954 0, DImode)));
8955 }
8957 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8958 DONE;
8959 }
8960 }")
8962 (define_insn "*booldi3_internal1"
8963 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
8964 (match_operator:DI 3 "boolean_or_operator"
8965 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
8966 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
8967 "TARGET_POWERPC64"
8968 "@
8969 %q3 %0,%1,%2
8970 %q3i %0,%1,%b2
8971 %q3is %0,%1,%u2")
8973 (define_insn "*booldi3_internal2"
8974 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8975 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8976 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8977 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8978 (const_int 0)))
8979 (clobber (match_scratch:DI 3 "=r,r"))]
8980 "TARGET_64BIT"
8981 "@
8982 %q4. %3,%1,%2
8983 #"
8984 [(set_attr "type" "fast_compare,compare")
8985 (set_attr "length" "4,8")])
8987 (define_split
8988 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8989 (compare:CC (match_operator:DI 4 "boolean_operator"
8990 [(match_operand:DI 1 "gpc_reg_operand" "")
8991 (match_operand:DI 2 "gpc_reg_operand" "")])
8992 (const_int 0)))
8993 (clobber (match_scratch:DI 3 ""))]
8994 "TARGET_POWERPC64 && reload_completed"
8995 [(set (match_dup 3) (match_dup 4))
8996 (set (match_dup 0)
8997 (compare:CC (match_dup 3)
8998 (const_int 0)))]
8999 "")
9001 (define_insn "*booldi3_internal3"
9002 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
9003 (compare:CC (match_operator:DI 4 "boolean_or_operator"
9004 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
9005 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
9006 (const_int 0)))
9007 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
9008 (match_dup 4))]
9009 "TARGET_64BIT"
9010 "@
9011 %q4. %0,%1,%2
9012 #"
9013 [(set_attr "type" "fast_compare,compare")
9014 (set_attr "length" "4,8")])
9016 (define_split
9017 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9018 (compare:CC (match_operator:DI 4 "boolean_operator"
9019 [(match_operand:DI 1 "gpc_reg_operand" "")
9020 (match_operand:DI 2 "gpc_reg_operand" "")])
9021 (const_int 0)))
9022 (set (match_operand:DI 0 "gpc_reg_operand" "")
9023 (match_dup 4))]
9024 "TARGET_POWERPC64 && reload_completed"
9025 [(set (match_dup 0) (match_dup 4))
9026 (set (match_dup 3)
9027 (compare:CC (match_dup 0)
9028 (const_int 0)))]
9029 "")
9031 ;; Split a logical operation that we can't do in one insn into two insns,
9032 ;; each of which does one 16-bit part. This is used by combine.
9034 (define_split
9035 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9036 (match_operator:DI 3 "boolean_or_operator"
9037 [(match_operand:DI 1 "gpc_reg_operand" "")
9038 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
9039 "TARGET_POWERPC64"
9040 [(set (match_dup 0) (match_dup 4))
9041 (set (match_dup 0) (match_dup 5))]
9042 "
9043 {
9044 rtx i3,i4;
9046 if (GET_CODE (operands[2]) == CONST_DOUBLE)
9047 {
9048 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
9049 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
9050 0, DImode);
9051 i4 = GEN_INT (value & 0xffff);
9052 }
9053 else
9054 {
9055 i3 = GEN_INT (INTVAL (operands[2])
9056 & (~ (HOST_WIDE_INT) 0xffff));
9057 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
9058 }
9059 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
9060 operands[1], i3);
9061 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
9062 operands[0], i4);
9063 }")
9065 (define_insn "*boolcdi3_internal1"
9066 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9067 (match_operator:DI 3 "boolean_operator"
9068 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
9069 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
9070 "TARGET_POWERPC64"
9071 "%q3 %0,%2,%1")
9073 (define_insn "*boolcdi3_internal2"
9074 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
9075 (compare:CC (match_operator:DI 4 "boolean_operator"
9076 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
9077 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
9078 (const_int 0)))
9079 (clobber (match_scratch:DI 3 "=r,r"))]
9080 "TARGET_64BIT"
9081 "@
9082 %q4. %3,%2,%1
9083 #"
9084 [(set_attr "type" "fast_compare,compare")
9085 (set_attr "length" "4,8")])
9087 (define_split
9088 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9089 (compare:CC (match_operator:DI 4 "boolean_operator"
9090 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
9091 (match_operand:DI 2 "gpc_reg_operand" "")])
9092 (const_int 0)))
9093 (clobber (match_scratch:DI 3 ""))]
9094 "TARGET_POWERPC64 && reload_completed"
9095 [(set (match_dup 3) (match_dup 4))
9096 (set (match_dup 0)
9097 (compare:CC (match_dup 3)
9098 (const_int 0)))]
9099 "")
9101 (define_insn "*boolcdi3_internal3"
9102 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
9103 (compare:CC (match_operator:DI 4 "boolean_operator"
9104 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
9105 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
9106 (const_int 0)))
9107 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
9108 (match_dup 4))]
9109 "TARGET_64BIT"
9110 "@
9111 %q4. %0,%2,%1
9112 #"
9113 [(set_attr "type" "fast_compare,compare")
9114 (set_attr "length" "4,8")])
9116 (define_split
9117 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9118 (compare:CC (match_operator:DI 4 "boolean_operator"
9119 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
9120 (match_operand:DI 2 "gpc_reg_operand" "")])
9121 (const_int 0)))
9122 (set (match_operand:DI 0 "gpc_reg_operand" "")
9123 (match_dup 4))]
9124 "TARGET_POWERPC64 && reload_completed"
9125 [(set (match_dup 0) (match_dup 4))
9126 (set (match_dup 3)
9127 (compare:CC (match_dup 0)
9128 (const_int 0)))]
9129 "")
9131 (define_insn "*boolccdi3_internal1"
9132 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9133 (match_operator:DI 3 "boolean_operator"
9134 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
9135 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
9136 "TARGET_POWERPC64"
9137 "%q3 %0,%1,%2")
9139 (define_insn "*boolccdi3_internal2"
9140 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
9141 (compare:CC (match_operator:DI 4 "boolean_operator"
9142 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
9143 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
9144 (const_int 0)))
9145 (clobber (match_scratch:DI 3 "=r,r"))]
9146 "TARGET_64BIT"
9147 "@
9148 %q4. %3,%1,%2
9149 #"
9150 [(set_attr "type" "fast_compare,compare")
9151 (set_attr "length" "4,8")])
9153 (define_split
9154 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9155 (compare:CC (match_operator:DI 4 "boolean_operator"
9156 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
9157 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
9158 (const_int 0)))
9159 (clobber (match_scratch:DI 3 ""))]
9160 "TARGET_POWERPC64 && reload_completed"
9161 [(set (match_dup 3) (match_dup 4))
9162 (set (match_dup 0)
9163 (compare:CC (match_dup 3)
9164 (const_int 0)))]
9165 "")
9167 (define_insn "*boolccdi3_internal3"
9168 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
9169 (compare:CC (match_operator:DI 4 "boolean_operator"
9170 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
9171 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
9172 (const_int 0)))
9173 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
9174 (match_dup 4))]
9175 "TARGET_64BIT"
9176 "@
9177 %q4. %0,%1,%2
9178 #"
9179 [(set_attr "type" "fast_compare,compare")
9180 (set_attr "length" "4,8")])
9182 (define_split
9183 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9184 (compare:CC (match_operator:DI 4 "boolean_operator"
9185 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
9186 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
9187 (const_int 0)))
9188 (set (match_operand:DI 0 "gpc_reg_operand" "")
9189 (match_dup 4))]
9190 "TARGET_POWERPC64 && reload_completed"
9191 [(set (match_dup 0) (match_dup 4))
9192 (set (match_dup 3)
9193 (compare:CC (match_dup 0)
9194 (const_int 0)))]
9195 "")
9197 (define_expand "smindi3"
9198 [(match_operand:DI 0 "gpc_reg_operand" "")
9199 (match_operand:DI 1 "gpc_reg_operand" "")
9200 (match_operand:DI 2 "gpc_reg_operand" "")]
9201 "TARGET_ISEL64"
9202 "
9203 {
9204 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
9205 DONE;
9206 }")
9208 (define_expand "smaxdi3"
9209 [(match_operand:DI 0 "gpc_reg_operand" "")
9210 (match_operand:DI 1 "gpc_reg_operand" "")
9211 (match_operand:DI 2 "gpc_reg_operand" "")]
9212 "TARGET_ISEL64"
9213 "
9214 {
9215 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
9216 DONE;
9217 }")
9219 (define_expand "umindi3"
9220 [(match_operand:DI 0 "gpc_reg_operand" "")
9221 (match_operand:DI 1 "gpc_reg_operand" "")
9222 (match_operand:DI 2 "gpc_reg_operand" "")]
9223 "TARGET_ISEL64"
9224 "
9225 {
9226 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
9227 DONE;
9228 }")
9230 (define_expand "umaxdi3"
9231 [(match_operand:DI 0 "gpc_reg_operand" "")
9232 (match_operand:DI 1 "gpc_reg_operand" "")
9233 (match_operand:DI 2 "gpc_reg_operand" "")]
9234 "TARGET_ISEL64"
9235 "
9236 {
9237 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
9238 DONE;
9239 }")
9241 \f
9242 ;; Now define ways of moving data around.
9244 ;; Set up a register with a value from the GOT table
9246 (define_expand "movsi_got"
9247 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9248 (unspec:SI [(match_operand:SI 1 "got_operand" "")
9249 (match_dup 2)] UNSPEC_MOVSI_GOT))]
9250 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
9251 "
9252 {
9253 if (GET_CODE (operands[1]) == CONST)
9254 {
9255 rtx offset = const0_rtx;
9256 HOST_WIDE_INT value;
9258 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
9259 value = INTVAL (offset);
9260 if (value != 0)
9261 {
9262 rtx tmp = (!can_create_pseudo_p ()
9263 ? operands[0]
9264 : gen_reg_rtx (Pmode));
9265 emit_insn (gen_movsi_got (tmp, operands[1]));
9266 emit_insn (gen_addsi3 (operands[0], tmp, offset));
9267 DONE;
9268 }
9269 }
9271 operands[2] = rs6000_got_register (operands[1]);
9272 }")
9274 (define_insn "*movsi_got_internal"
9275 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9276 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
9277 (match_operand:SI 2 "gpc_reg_operand" "b")]
9278 UNSPEC_MOVSI_GOT))]
9279 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
9280 "{l|lwz} %0,%a1@got(%2)"
9281 [(set_attr "type" "load")])
9283 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
9284 ;; didn't get allocated to a hard register.
9285 (define_split
9286 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9287 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
9288 (match_operand:SI 2 "memory_operand" "")]
9289 UNSPEC_MOVSI_GOT))]
9290 "DEFAULT_ABI == ABI_V4
9291 && flag_pic == 1
9292 && (reload_in_progress || reload_completed)"
9293 [(set (match_dup 0) (match_dup 2))
9294 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
9295 UNSPEC_MOVSI_GOT))]
9296 "")
9298 ;; For SI, we special-case integers that can't be loaded in one insn. We
9299 ;; do the load 16-bits at a time. We could do this by loading from memory,
9300 ;; and this is even supposed to be faster, but it is simpler not to get
9301 ;; integers in the TOC.
9302 (define_insn "movsi_low"
9303 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9304 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9305 (match_operand 2 "" ""))))]
9306 "TARGET_MACHO && ! TARGET_64BIT"
9307 "{l|lwz} %0,lo16(%2)(%1)"
9308 [(set_attr "type" "load")
9309 (set_attr "length" "4")])
9311 (define_insn "*movsi_internal1"
9312 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*q,*c*l,*h,*h")
9313 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,r,0"))]
9314 "!TARGET_SINGLE_FPU &&
9315 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
9316 "@
9317 mr %0,%1
9318 {cal|la} %0,%a1
9319 {l%U1%X1|lwz%U1%X1} %0,%1
9320 {st%U0%X0|stw%U0%X0} %1,%0
9321 {lil|li} %0,%1
9322 {liu|lis} %0,%v1
9323 #
9324 mf%1 %0
9325 mt%0 %1
9326 mt%0 %1
9327 mt%0 %1
9328 {cror 0,0,0|nop}"
9329 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,*,mtjmpr,*,*")
9330 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4")])
9332 (define_insn "*movsi_internal1_single"
9333 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*q,*c*l,*h,*h,m,*f")
9334 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,r,0,f,m"))]
9335 "TARGET_SINGLE_FPU &&
9336 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
9337 "@
9338 mr %0,%1
9339 {cal|la} %0,%a1
9340 {l%U1%X1|lwz%U1%X1} %0,%1
9341 {st%U0%X0|stw%U0%X0} %1,%0
9342 {lil|li} %0,%1
9343 {liu|lis} %0,%v1
9344 #
9345 mf%1 %0
9346 mt%0 %1
9347 mt%0 %1
9348 mt%0 %1
9349 {cror 0,0,0|nop}
9350 stfs%U0%X0 %1, %0
9351 lfs%U1%X1 %0, %1"
9352 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,*,mtjmpr,*,*,*,*")
9353 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4,4")])
9355 ;; Split a load of a large constant into the appropriate two-insn
9356 ;; sequence.
9358 (define_split
9359 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9360 (match_operand:SI 1 "const_int_operand" ""))]
9361 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
9362 && (INTVAL (operands[1]) & 0xffff) != 0"
9363 [(set (match_dup 0)
9364 (match_dup 2))
9365 (set (match_dup 0)
9366 (ior:SI (match_dup 0)
9367 (match_dup 3)))]
9368 "
9369 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
9371 if (tem == operands[0])
9372 DONE;
9373 else
9374 FAIL;
9375 }")
9377 (define_insn "*mov<mode>_internal2"
9378 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
9379 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
9380 (const_int 0)))
9381 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
9382 ""
9383 "@
9384 {cmpi|cmp<wd>i} %2,%0,0
9385 mr. %0,%1
9386 #"
9387 [(set_attr "type" "cmp,compare,cmp")
9388 (set_attr "length" "4,4,8")])
9390 (define_split
9391 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
9392 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
9393 (const_int 0)))
9394 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
9395 "reload_completed"
9396 [(set (match_dup 0) (match_dup 1))
9397 (set (match_dup 2)
9398 (compare:CC (match_dup 0)
9399 (const_int 0)))]
9400 "")
9401 \f
9402 (define_insn "*movhi_internal"
9403 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
9404 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
9405 "gpc_reg_operand (operands[0], HImode)
9406 || gpc_reg_operand (operands[1], HImode)"
9407 "@
9408 mr %0,%1
9409 lhz%U1%X1 %0,%1
9410 sth%U0%X0 %1,%0
9411 {lil|li} %0,%w1
9412 mf%1 %0
9413 mt%0 %1
9414 mt%0 %1
9415 {cror 0,0,0|nop}"
9416 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
9418 (define_expand "mov<mode>"
9419 [(set (match_operand:INT 0 "general_operand" "")
9420 (match_operand:INT 1 "any_operand" ""))]
9421 ""
9422 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
9424 (define_insn "*movqi_internal"
9425 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
9426 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
9427 "gpc_reg_operand (operands[0], QImode)
9428 || gpc_reg_operand (operands[1], QImode)"
9429 "@
9430 mr %0,%1
9431 lbz%U1%X1 %0,%1
9432 stb%U0%X0 %1,%0
9433 {lil|li} %0,%1
9434 mf%1 %0
9435 mt%0 %1
9436 mt%0 %1
9437 {cror 0,0,0|nop}"
9438 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
9439 \f
9440 ;; Here is how to move condition codes around. When we store CC data in
9441 ;; an integer register or memory, we store just the high-order 4 bits.
9442 ;; This lets us not shift in the most common case of CR0.
9443 (define_expand "movcc"
9444 [(set (match_operand:CC 0 "nonimmediate_operand" "")
9445 (match_operand:CC 1 "nonimmediate_operand" ""))]
9446 ""
9447 "")
9449 (define_insn "*movcc_internal1"
9450 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
9451 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
9452 "register_operand (operands[0], CCmode)
9453 || register_operand (operands[1], CCmode)"
9454 "@
9455 mcrf %0,%1
9456 mtcrf 128,%1
9457 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
9458 crxor %0,%0,%0
9459 mfcr %0%Q1
9460 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
9461 mr %0,%1
9462 {lil|li} %0,%1
9463 mf%1 %0
9464 mt%0 %1
9465 mt%0 %1
9466 {l%U1%X1|lwz%U1%X1} %0,%1
9467 {st%U0%U1|stw%U0%U1} %1,%0"
9468 [(set (attr "type")
9469 (cond [(eq_attr "alternative" "0,3")
9470 (const_string "cr_logical")
9471 (eq_attr "alternative" "1,2")
9472 (const_string "mtcr")
9473 (eq_attr "alternative" "6,7,9")
9474 (const_string "integer")
9475 (eq_attr "alternative" "8")
9476 (const_string "mfjmpr")
9477 (eq_attr "alternative" "10")
9478 (const_string "mtjmpr")
9479 (eq_attr "alternative" "11")
9480 (const_string "load")
9481 (eq_attr "alternative" "12")
9482 (const_string "store")
9483 (match_test "TARGET_MFCRF")
9484 (const_string "mfcrf")
9485 ]
9486 (const_string "mfcr")))
9487 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
9488 \f
9489 ;; For floating-point, we normally deal with the floating-point registers
9490 ;; unless -msoft-float is used. The sole exception is that parameter passing
9491 ;; can produce floating-point values in fixed-point registers. Unless the
9492 ;; value is a simple constant or already in memory, we deal with this by
9493 ;; allocating memory and copying the value explicitly via that memory location.
9494 (define_expand "movsf"
9495 [(set (match_operand:SF 0 "nonimmediate_operand" "")
9496 (match_operand:SF 1 "any_operand" ""))]
9497 ""
9498 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
9500 (define_split
9501 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9502 (match_operand:SF 1 "const_double_operand" ""))]
9503 "reload_completed
9504 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9505 || (GET_CODE (operands[0]) == SUBREG
9506 && GET_CODE (SUBREG_REG (operands[0])) == REG
9507 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9508 [(set (match_dup 2) (match_dup 3))]
9509 "
9510 {
9511 long l;
9512 REAL_VALUE_TYPE rv;
9514 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9515 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
9517 if (! TARGET_POWERPC64)
9518 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
9519 else
9520 operands[2] = gen_lowpart (SImode, operands[0]);
9522 operands[3] = gen_int_mode (l, SImode);
9523 }")
9525 (define_insn "*movsf_hardfloat"
9526 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
9527 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
9528 "(gpc_reg_operand (operands[0], SFmode)
9529 || gpc_reg_operand (operands[1], SFmode))
9530 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
9531 "@
9532 mr %0,%1
9533 {l%U1%X1|lwz%U1%X1} %0,%1
9534 {st%U0%X0|stw%U0%X0} %1,%0
9535 fmr %0,%1
9536 lfs%U1%X1 %0,%1
9537 stfs%U0%X0 %1,%0
9538 mt%0 %1
9539 mt%0 %1
9540 mf%1 %0
9541 {cror 0,0,0|nop}
9542 #
9543 #"
9544 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
9545 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
9547 (define_insn "*movsf_softfloat"
9548 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,*h")
9549 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,G,Fn,0"))]
9550 "(gpc_reg_operand (operands[0], SFmode)
9551 || gpc_reg_operand (operands[1], SFmode))
9552 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
9553 "@
9554 mr %0,%1
9555 mt%0 %1
9556 mt%0 %1
9557 mf%1 %0
9558 {l%U1%X1|lwz%U1%X1} %0,%1
9559 {st%U0%X0|stw%U0%X0} %1,%0
9560 {lil|li} %0,%1
9561 {liu|lis} %0,%v1
9562 #
9563 #
9564 {cror 0,0,0|nop}"
9565 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*")
9566 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,4")])
9568 \f
9569 (define_expand "movdf"
9570 [(set (match_operand:DF 0 "nonimmediate_operand" "")
9571 (match_operand:DF 1 "any_operand" ""))]
9572 ""
9573 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
9575 (define_split
9576 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9577 (match_operand:DF 1 "const_int_operand" ""))]
9578 "! TARGET_POWERPC64 && reload_completed
9579 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9580 || (GET_CODE (operands[0]) == SUBREG
9581 && GET_CODE (SUBREG_REG (operands[0])) == REG
9582 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9583 [(set (match_dup 2) (match_dup 4))
9584 (set (match_dup 3) (match_dup 1))]
9585 "
9586 {
9587 int endian = (WORDS_BIG_ENDIAN == 0);
9588 HOST_WIDE_INT value = INTVAL (operands[1]);
9590 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9591 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9592 #if HOST_BITS_PER_WIDE_INT == 32
9593 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9594 #else
9595 operands[4] = GEN_INT (value >> 32);
9596 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9597 #endif
9598 }")
9600 (define_split
9601 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9602 (match_operand:DF 1 "const_double_operand" ""))]
9603 "! TARGET_POWERPC64 && reload_completed
9604 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9605 || (GET_CODE (operands[0]) == SUBREG
9606 && GET_CODE (SUBREG_REG (operands[0])) == REG
9607 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9608 [(set (match_dup 2) (match_dup 4))
9609 (set (match_dup 3) (match_dup 5))]
9610 "
9611 {
9612 int endian = (WORDS_BIG_ENDIAN == 0);
9613 long l[2];
9614 REAL_VALUE_TYPE rv;
9616 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9617 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9619 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9620 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9621 operands[4] = gen_int_mode (l[endian], SImode);
9622 operands[5] = gen_int_mode (l[1 - endian], SImode);
9623 }")
9625 (define_split
9626 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9627 (match_operand:DF 1 "const_double_operand" ""))]
9628 "TARGET_POWERPC64 && reload_completed
9629 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9630 || (GET_CODE (operands[0]) == SUBREG
9631 && GET_CODE (SUBREG_REG (operands[0])) == REG
9632 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9633 [(set (match_dup 2) (match_dup 3))]
9634 "
9635 {
9636 int endian = (WORDS_BIG_ENDIAN == 0);
9637 long l[2];
9638 REAL_VALUE_TYPE rv;
9639 #if HOST_BITS_PER_WIDE_INT >= 64
9640 HOST_WIDE_INT val;
9641 #endif
9643 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9644 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9646 operands[2] = gen_lowpart (DImode, operands[0]);
9647 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
9648 #if HOST_BITS_PER_WIDE_INT >= 64
9649 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
9650 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
9652 operands[3] = gen_int_mode (val, DImode);
9653 #else
9654 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
9655 #endif
9656 }")
9658 ;; Don't have reload use general registers to load a constant. It is
9659 ;; less efficient than loading the constant into an FP register, since
9660 ;; it will probably be used there.
9661 (define_insn "*movdf_hardfloat32"
9662 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,m,d,d,wa,!r,!r,!r")
9663 (match_operand:DF 1 "input_operand" "r,Y,r,ws,wa,Z,Z,ws,wa,d,m,d,j,G,H,F"))]
9664 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9665 && (gpc_reg_operand (operands[0], DFmode)
9666 || gpc_reg_operand (operands[1], DFmode))"
9667 "*
9668 {
9669 switch (which_alternative)
9670 {
9671 default:
9672 gcc_unreachable ();
9673 case 0:
9674 case 1:
9675 case 2:
9676 return \"#\";
9677 case 3:
9678 case 4:
9679 return \"xxlor %x0,%x1,%x1\";
9680 case 5:
9681 case 6:
9682 return \"lxsd%U1x %x0,%y1\";
9683 case 7:
9684 case 8:
9685 return \"stxsd%U0x %x1,%y0\";
9686 case 9:
9687 return \"stfd%U0%X0 %1,%0\";
9688 case 10:
9689 return \"lfd%U1%X1 %0,%1\";
9690 case 11:
9691 return \"fmr %0,%1\";
9692 case 12:
9693 return \"xxlxor %x0,%x0,%x0\";
9694 case 13:
9695 case 14:
9696 case 15:
9697 return \"#\";
9698 }
9699 }"
9700 [(set_attr "type" "store,load,two,fp,fp,fpload,fpload,fpstore,fpstore,fpstore,fpload,fp,vecsimple,*,*,*")
9701 (set_attr "length" "8,8,8,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9703 (define_insn "*movdf_softfloat32"
9704 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
9705 (match_operand:DF 1 "input_operand" "r,Y,r,G,H,F"))]
9706 "! TARGET_POWERPC64
9707 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
9708 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
9709 && (gpc_reg_operand (operands[0], DFmode)
9710 || gpc_reg_operand (operands[1], DFmode))"
9711 "#"
9712 [(set_attr "type" "store,load,two,*,*,*")
9713 (set_attr "length" "8,8,8,8,12,16")])
9715 ;; Reload patterns to support gpr load/store with misaligned mem.
9716 ;; and multiple gpr load/store at offset >= 0xfffc
9717 (define_expand "reload_<mode>_store"
9718 [(parallel [(match_operand 0 "memory_operand" "=m")
9719 (match_operand 1 "gpc_reg_operand" "r")
9720 (match_operand:GPR 2 "register_operand" "=&b")])]
9721 ""
9722 {
9723 rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
9724 DONE;
9725 })
9727 (define_expand "reload_<mode>_load"
9728 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
9729 (match_operand 1 "memory_operand" "m")
9730 (match_operand:GPR 2 "register_operand" "=b")])]
9731 ""
9732 {
9733 rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
9734 DONE;
9735 })
9737 ; ld/std require word-aligned displacements -> 'Y' constraint.
9738 ; List Y->r and r->Y before r->r for reload.
9739 (define_insn "*movdf_hardfloat64_mfpgpr"
9740 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,m,d,d,wa,*c*l,!r,*h,!r,!r,!r,r,d")
9741 (match_operand:DF 1 "input_operand" "r,Y,r,ws,?wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F,d,r"))]
9742 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9743 && TARGET_DOUBLE_FLOAT
9744 && (gpc_reg_operand (operands[0], DFmode)
9745 || gpc_reg_operand (operands[1], DFmode))"
9746 "@
9747 std%U0%X0 %1,%0
9748 ld%U1%X1 %0,%1
9749 mr %0,%1
9750 xxlor %x0,%x1,%x1
9751 xxlor %x0,%x1,%x1
9752 lxsd%U1x %x0,%y1
9753 lxsd%U1x %x0,%y1
9754 stxsd%U0x %x1,%y0
9755 stxsd%U0x %x1,%y0
9756 stfd%U0%X0 %1,%0
9757 lfd%U1%X1 %0,%1
9758 fmr %0,%1
9759 xxlxor %x0,%x0,%x0
9760 mt%0 %1
9761 mf%1 %0
9762 {cror 0,0,0|nop}
9763 #
9764 #
9765 #
9766 mftgpr %0,%1
9767 mffgpr %0,%1"
9768 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fpstore,fpload,fp,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
9769 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
9771 ; ld/std require word-aligned displacements -> 'Y' constraint.
9772 ; List Y->r and r->Y before r->r for reload.
9773 (define_insn "*movdf_hardfloat64"
9774 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,m,d,d,wa,*c*l,!r,*h,!r,!r,!r")
9775 (match_operand:DF 1 "input_operand" "r,Y,r,ws,wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F"))]
9776 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9777 && TARGET_DOUBLE_FLOAT
9778 && (gpc_reg_operand (operands[0], DFmode)
9779 || gpc_reg_operand (operands[1], DFmode))"
9780 "@
9781 std%U0%X0 %1,%0
9782 ld%U1%X1 %0,%1
9783 mr %0,%1
9784 xxlor %x0,%x1,%x1
9785 xxlor %x0,%x1,%x1
9786 lxsd%U1x %x0,%y1
9787 lxsd%U1x %x0,%y1
9788 stxsd%U0x %x1,%y0
9789 stxsd%U0x %x1,%y0
9790 stfd%U0%X0 %1,%0
9791 lfd%U1%X1 %0,%1
9792 fmr %0,%1
9793 xxlxor %x0,%x0,%x0
9794 mt%0 %1
9795 mf%1 %0
9796 {cror 0,0,0|nop}
9797 #
9798 #
9799 #"
9800 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fpstore,fpload,fp,vecsimple,mtjmpr,mfjmpr,*,*,*,*")
9801 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9803 (define_insn "*movdf_softfloat64"
9804 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
9805 (match_operand:DF 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
9806 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
9807 && (gpc_reg_operand (operands[0], DFmode)
9808 || gpc_reg_operand (operands[1], DFmode))"
9809 "@
9810 std%U0%X0 %1,%0
9811 ld%U1%X1 %0,%1
9812 mr %0,%1
9813 mt%0 %1
9814 mf%1 %0
9815 #
9816 #
9817 #
9818 {cror 0,0,0|nop}"
9819 [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*")
9820 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
9821 \f
9822 (define_expand "movtf"
9823 [(set (match_operand:TF 0 "general_operand" "")
9824 (match_operand:TF 1 "any_operand" ""))]
9825 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
9826 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
9828 ;; It's important to list Y->r and r->Y before r->r because otherwise
9829 ;; reload, given m->r, will try to pick r->r and reload it, which
9830 ;; doesn't make progress.
9831 (define_insn_and_split "*movtf_internal"
9832 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
9833 (match_operand:TF 1 "input_operand" "d,m,d,r,YGHF,r"))]
9834 "!TARGET_IEEEQUAD
9835 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
9836 && (gpc_reg_operand (operands[0], TFmode)
9837 || gpc_reg_operand (operands[1], TFmode))"
9838 "#"
9839 "&& reload_completed"
9840 [(pc)]
9841 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9842 [(set_attr "length" "8,8,8,20,20,16")])
9844 (define_insn_and_split "*movtf_softfloat"
9845 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=Y,r,r")
9846 (match_operand:TF 1 "input_operand" "r,YGHF,r"))]
9847 "!TARGET_IEEEQUAD
9848 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
9849 && (gpc_reg_operand (operands[0], TFmode)
9850 || gpc_reg_operand (operands[1], TFmode))"
9851 "#"
9852 "&& reload_completed"
9853 [(pc)]
9854 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9855 [(set_attr "length" "20,20,16")])
9857 (define_expand "extenddftf2"
9858 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9859 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
9860 "!TARGET_IEEEQUAD
9861 && TARGET_HARD_FLOAT
9862 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9863 && TARGET_LONG_DOUBLE_128"
9864 {
9865 if (TARGET_E500_DOUBLE)
9866 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
9867 else
9868 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
9869 DONE;
9870 })
9872 (define_expand "extenddftf2_fprs"
9873 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9874 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
9875 (use (match_dup 2))])]
9876 "!TARGET_IEEEQUAD
9877 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9878 && TARGET_LONG_DOUBLE_128"
9879 {
9880 operands[2] = CONST0_RTX (DFmode);
9881 /* Generate GOT reference early for SVR4 PIC. */
9882 if (DEFAULT_ABI == ABI_V4 && flag_pic)
9883 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
9884 })
9886 (define_insn_and_split "*extenddftf2_internal"
9887 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
9888 (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
9889 (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
9890 "!TARGET_IEEEQUAD
9891 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9892 && TARGET_LONG_DOUBLE_128"
9893 "#"
9894 "&& reload_completed"
9895 [(pc)]
9896 {
9897 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9898 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9899 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
9900 operands[1]);
9901 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
9902 operands[2]);
9903 DONE;
9904 })
9906 (define_expand "extendsftf2"
9907 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9908 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
9909 "!TARGET_IEEEQUAD
9910 && TARGET_HARD_FLOAT
9911 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9912 && TARGET_LONG_DOUBLE_128"
9913 {
9914 rtx tmp = gen_reg_rtx (DFmode);
9915 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
9916 emit_insn (gen_extenddftf2 (operands[0], tmp));
9917 DONE;
9918 })
9920 (define_expand "trunctfdf2"
9921 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9922 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
9923 "!TARGET_IEEEQUAD
9924 && TARGET_HARD_FLOAT
9925 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9926 && TARGET_LONG_DOUBLE_128"
9927 "")
9929 (define_insn_and_split "trunctfdf2_internal1"
9930 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
9931 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
9932 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
9933 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9934 "@
9935 #
9936 fmr %0,%1"
9937 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
9938 [(const_int 0)]
9939 {
9940 emit_note (NOTE_INSN_DELETED);
9941 DONE;
9942 }
9943 [(set_attr "type" "fp")])
9945 (define_insn "trunctfdf2_internal2"
9946 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9947 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9948 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
9949 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9950 && TARGET_LONG_DOUBLE_128"
9951 "fadd %0,%1,%L1"
9952 [(set_attr "type" "fp")
9953 (set_attr "fp_type" "fp_addsub_d")])
9955 (define_expand "trunctfsf2"
9956 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9957 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
9958 "!TARGET_IEEEQUAD
9959 && TARGET_HARD_FLOAT
9960 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9961 && TARGET_LONG_DOUBLE_128"
9962 {
9963 if (TARGET_E500_DOUBLE)
9964 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
9965 else
9966 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
9967 DONE;
9968 })
9970 (define_insn_and_split "trunctfsf2_fprs"
9971 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9972 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
9973 (clobber (match_scratch:DF 2 "=d"))]
9974 "!TARGET_IEEEQUAD
9975 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
9976 && TARGET_LONG_DOUBLE_128"
9977 "#"
9978 "&& reload_completed"
9979 [(set (match_dup 2)
9980 (float_truncate:DF (match_dup 1)))
9981 (set (match_dup 0)
9982 (float_truncate:SF (match_dup 2)))]
9983 "")
9985 (define_expand "floatsitf2"
9986 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9987 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
9988 "!TARGET_IEEEQUAD
9989 && TARGET_HARD_FLOAT
9990 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9991 && TARGET_LONG_DOUBLE_128"
9992 {
9993 rtx tmp = gen_reg_rtx (DFmode);
9994 expand_float (tmp, operands[1], false);
9995 emit_insn (gen_extenddftf2 (operands[0], tmp));
9996 DONE;
9997 })
9999 ; fadd, but rounding towards zero.
10000 ; This is probably not the optimal code sequence.
10001 (define_insn "fix_trunc_helper"
10002 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
10003 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
10004 UNSPEC_FIX_TRUNC_TF))
10005 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
10006 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
10007 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
10008 [(set_attr "type" "fp")
10009 (set_attr "length" "20")])
10011 (define_expand "fix_trunctfsi2"
10012 [(set (match_operand:SI 0 "gpc_reg_operand" "")
10013 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
10014 "!TARGET_IEEEQUAD
10015 && (TARGET_POWER2 || TARGET_POWERPC)
10016 && TARGET_HARD_FLOAT
10017 && (TARGET_FPRS || TARGET_E500_DOUBLE)
10018 && TARGET_LONG_DOUBLE_128"
10019 {
10020 if (TARGET_E500_DOUBLE)
10021 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
10022 else
10023 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
10024 DONE;
10025 })
10027 (define_expand "fix_trunctfsi2_fprs"
10028 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
10029 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
10030 (clobber (match_dup 2))
10031 (clobber (match_dup 3))
10032 (clobber (match_dup 4))
10033 (clobber (match_dup 5))])]
10034 "!TARGET_IEEEQUAD
10035 && (TARGET_POWER2 || TARGET_POWERPC)
10036 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10037 {
10038 operands[2] = gen_reg_rtx (DFmode);
10039 operands[3] = gen_reg_rtx (DFmode);
10040 operands[4] = gen_reg_rtx (DImode);
10041 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
10042 })
10044 (define_insn_and_split "*fix_trunctfsi2_internal"
10045 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10046 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
10047 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
10048 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
10049 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
10050 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
10051 "!TARGET_IEEEQUAD
10052 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10053 "#"
10054 ""
10055 [(pc)]
10056 {
10057 rtx lowword;
10058 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
10060 gcc_assert (MEM_P (operands[5]));
10061 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
10063 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
10064 emit_move_insn (operands[5], operands[4]);
10065 emit_move_insn (operands[0], lowword);
10066 DONE;
10067 })
10069 (define_expand "negtf2"
10070 [(set (match_operand:TF 0 "gpc_reg_operand" "")
10071 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
10072 "!TARGET_IEEEQUAD
10073 && TARGET_HARD_FLOAT
10074 && (TARGET_FPRS || TARGET_E500_DOUBLE)
10075 && TARGET_LONG_DOUBLE_128"
10076 "")
10078 (define_insn "negtf2_internal"
10079 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
10080 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
10081 "!TARGET_IEEEQUAD
10082 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10083 "*
10084 {
10085 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
10086 return \"fneg %L0,%L1\;fneg %0,%1\";
10087 else
10088 return \"fneg %0,%1\;fneg %L0,%L1\";
10089 }"
10090 [(set_attr "type" "fp")
10091 (set_attr "length" "8")])
10093 (define_expand "abstf2"
10094 [(set (match_operand:TF 0 "gpc_reg_operand" "")
10095 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
10096 "!TARGET_IEEEQUAD
10097 && TARGET_HARD_FLOAT
10098 && (TARGET_FPRS || TARGET_E500_DOUBLE)
10099 && TARGET_LONG_DOUBLE_128"
10100 "
10101 {
10102 rtx label = gen_label_rtx ();
10103 if (TARGET_E500_DOUBLE)
10104 {
10105 if (flag_finite_math_only && !flag_trapping_math)
10106 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
10107 else
10108 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
10109 }
10110 else
10111 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
10112 emit_label (label);
10113 DONE;
10114 }")
10116 (define_expand "abstf2_internal"
10117 [(set (match_operand:TF 0 "gpc_reg_operand" "")
10118 (match_operand:TF 1 "gpc_reg_operand" ""))
10119 (set (match_dup 3) (match_dup 5))
10120 (set (match_dup 5) (abs:DF (match_dup 5)))
10121 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
10122 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
10123 (label_ref (match_operand 2 "" ""))
10124 (pc)))
10125 (set (match_dup 6) (neg:DF (match_dup 6)))]
10126 "!TARGET_IEEEQUAD
10127 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10128 && TARGET_LONG_DOUBLE_128"
10129 "
10130 {
10131 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
10132 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
10133 operands[3] = gen_reg_rtx (DFmode);
10134 operands[4] = gen_reg_rtx (CCFPmode);
10135 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
10136 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
10137 }")
10138 \f
10139 ;; Next come the multi-word integer load and store and the load and store
10140 ;; multiple insns.
10142 ;; List r->r after r->Y, otherwise reload will try to reload a
10143 ;; non-offsettable address by using r->r which won't make progress.
10144 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
10145 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
10146 (define_insn "*movdi_internal32"
10147 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r,?wa")
10148 (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF,O"))]
10149 "! TARGET_POWERPC64
10150 && (gpc_reg_operand (operands[0], DImode)
10151 || gpc_reg_operand (operands[1], DImode))"
10152 "@
10153 #
10154 #
10155 #
10156 stfd%U0%X0 %1,%0
10157 lfd%U1%X1 %0,%1
10158 fmr %0,%1
10159 #
10160 xxlxor %x0,%x0,%x0"
10161 [(set_attr "type" "store,load,*,fpstore,fpload,fp,*,vecsimple")])
10163 (define_split
10164 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10165 (match_operand:DI 1 "const_int_operand" ""))]
10166 "! TARGET_POWERPC64 && reload_completed
10167 && gpr_or_gpr_p (operands[0], operands[1])"
10168 [(set (match_dup 2) (match_dup 4))
10169 (set (match_dup 3) (match_dup 1))]
10170 "
10171 {
10172 HOST_WIDE_INT value = INTVAL (operands[1]);
10173 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
10174 DImode);
10175 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
10176 DImode);
10177 #if HOST_BITS_PER_WIDE_INT == 32
10178 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
10179 #else
10180 operands[4] = GEN_INT (value >> 32);
10181 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
10182 #endif
10183 }")
10185 (define_split
10186 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
10187 (match_operand:DIFD 1 "input_operand" ""))]
10188 "reload_completed && !TARGET_POWERPC64
10189 && gpr_or_gpr_p (operands[0], operands[1])"
10190 [(pc)]
10191 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
10193 (define_insn "*movdi_mfpgpr"
10194 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*d")
10195 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*d,r"))]
10196 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
10197 && (gpc_reg_operand (operands[0], DImode)
10198 || gpc_reg_operand (operands[1], DImode))"
10199 "@
10200 std%U0%X0 %1,%0
10201 ld%U1%X1 %0,%1
10202 mr %0,%1
10203 li %0,%1
10204 lis %0,%v1
10205 #
10206 stfd%U0%X0 %1,%0
10207 lfd%U1%X1 %0,%1
10208 fmr %0,%1
10209 mf%1 %0
10210 mt%0 %1
10211 {cror 0,0,0|nop}
10212 mftgpr %0,%1
10213 mffgpr %0,%1"
10214 [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
10215 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4")])
10217 (define_insn "*movdi_internal64"
10218 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,?wa")
10219 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,O"))]
10220 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
10221 && (gpc_reg_operand (operands[0], DImode)
10222 || gpc_reg_operand (operands[1], DImode))"
10223 "@
10224 std%U0%X0 %1,%0
10225 ld%U1%X1 %0,%1
10226 mr %0,%1
10227 li %0,%1
10228 lis %0,%v1
10229 #
10230 stfd%U0%X0 %1,%0
10231 lfd%U1%X1 %0,%1
10232 fmr %0,%1
10233 mf%1 %0
10234 mt%0 %1
10235 {cror 0,0,0|nop}
10236 xxlxor %x0,%x0,%x0"
10237 [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,vecsimple")
10238 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
10240 ;; immediate value valid for a single instruction hiding in a const_double
10241 (define_insn ""
10242 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10243 (match_operand:DI 1 "const_double_operand" "F"))]
10244 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
10245 && GET_CODE (operands[1]) == CONST_DOUBLE
10246 && num_insns_constant (operands[1], DImode) == 1"
10247 "*
10248 {
10249 return ((unsigned HOST_WIDE_INT)
10250 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
10251 ? \"li %0,%1\" : \"lis %0,%v1\";
10252 }")
10254 ;; Generate all one-bits and clear left or right.
10255 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
10256 (define_split
10257 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10258 (match_operand:DI 1 "mask64_operand" ""))]
10259 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10260 [(set (match_dup 0) (const_int -1))
10261 (set (match_dup 0)
10262 (and:DI (rotate:DI (match_dup 0)
10263 (const_int 0))
10264 (match_dup 1)))]
10265 "")
10267 ;; Split a load of a large constant into the appropriate five-instruction
10268 ;; sequence. Handle anything in a constant number of insns.
10269 ;; When non-easy constants can go in the TOC, this should use
10270 ;; easy_fp_constant predicate.
10271 (define_split
10272 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10273 (match_operand:DI 1 "const_int_operand" ""))]
10274 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10275 [(set (match_dup 0) (match_dup 2))
10276 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
10277 "
10278 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
10280 if (tem == operands[0])
10281 DONE;
10282 else
10283 FAIL;
10284 }")
10286 (define_split
10287 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10288 (match_operand:DI 1 "const_double_operand" ""))]
10289 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10290 [(set (match_dup 0) (match_dup 2))
10291 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
10292 "
10293 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
10295 if (tem == operands[0])
10296 DONE;
10297 else
10298 FAIL;
10299 }")
10300 \f
10301 ;; TImode is similar, except that we usually want to compute the address into
10302 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
10303 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
10305 ;; We say that MQ is clobbered in the last alternative because the first
10306 ;; alternative would never get used otherwise since it would need a reload
10307 ;; while the 2nd alternative would not. We put memory cases first so they
10308 ;; are preferred. Otherwise, we'd try to reload the output instead of
10309 ;; giving the SCRATCH mq.
10311 (define_insn "*movti_power"
10312 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
10313 (match_operand:TI 1 "input_operand" "r,r,Q,Y,r,n"))
10314 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
10315 "TARGET_POWER && ! TARGET_POWERPC64
10316 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
10317 "*
10318 {
10319 switch (which_alternative)
10320 {
10321 default:
10322 gcc_unreachable ();
10324 case 0:
10325 if (TARGET_STRING)
10326 return \"{stsi|stswi} %1,%P0,16\";
10327 case 1:
10328 return \"#\";
10329 case 2:
10330 /* If the address is not used in the output, we can use lsi. Otherwise,
10331 fall through to generating four loads. */
10332 if (TARGET_STRING
10333 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
10334 return \"{lsi|lswi} %0,%P1,16\";
10335 /* ... fall through ... */
10336 case 3:
10337 case 4:
10338 case 5:
10339 return \"#\";
10340 }
10341 }"
10342 [(set_attr "type" "store,store,load,load,*,*")])
10344 (define_insn "*movti_string"
10345 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
10346 (match_operand:TI 1 "input_operand" "r,r,Q,Y,r,n"))]
10347 "! TARGET_POWER && ! TARGET_POWERPC64
10348 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
10349 "*
10350 {
10351 switch (which_alternative)
10352 {
10353 default:
10354 gcc_unreachable ();
10355 case 0:
10356 if (TARGET_STRING)
10357 return \"{stsi|stswi} %1,%P0,16\";
10358 case 1:
10359 return \"#\";
10360 case 2:
10361 /* If the address is not used in the output, we can use lsi. Otherwise,
10362 fall through to generating four loads. */
10363 if (TARGET_STRING
10364 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
10365 return \"{lsi|lswi} %0,%P1,16\";
10366 /* ... fall through ... */
10367 case 3:
10368 case 4:
10369 case 5:
10370 return \"#\";
10371 }
10372 }"
10373 [(set_attr "type" "store_ux,store_ux,load_ux,load_ux,*,*")
10374 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
10375 (const_string "always")
10376 (const_string "conditional")))])
10378 (define_insn "*movti_ppc64"
10379 [(set (match_operand:TI 0 "nonimmediate_operand" "=Y,r,r")
10380 (match_operand:TI 1 "input_operand" "r,Y,r"))]
10381 "(TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
10382 || gpc_reg_operand (operands[1], TImode)))
10383 && VECTOR_MEM_NONE_P (TImode)"
10384 "#"
10385 [(set_attr "type" "store,load,*")])
10387 (define_split
10388 [(set (match_operand:TI 0 "gpc_reg_operand" "")
10389 (match_operand:TI 1 "const_double_operand" ""))]
10390 "TARGET_POWERPC64 && VECTOR_MEM_NONE_P (TImode)"
10391 [(set (match_dup 2) (match_dup 4))
10392 (set (match_dup 3) (match_dup 5))]
10393 "
10394 {
10395 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
10396 TImode);
10397 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
10398 TImode);
10399 if (GET_CODE (operands[1]) == CONST_DOUBLE)
10400 {
10401 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
10402 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
10403 }
10404 else if (GET_CODE (operands[1]) == CONST_INT)
10405 {
10406 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
10407 operands[5] = operands[1];
10408 }
10409 else
10410 FAIL;
10411 }")
10413 (define_split
10414 [(set (match_operand:TI 0 "nonimmediate_operand" "")
10415 (match_operand:TI 1 "input_operand" ""))]
10416 "reload_completed && VECTOR_MEM_NONE_P (TImode)
10417 && gpr_or_gpr_p (operands[0], operands[1])"
10418 [(pc)]
10419 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
10420 \f
10421 (define_expand "load_multiple"
10422 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10423 (match_operand:SI 1 "" ""))
10424 (use (match_operand:SI 2 "" ""))])]
10425 "TARGET_STRING && !TARGET_POWERPC64"
10426 "
10427 {
10428 int regno;
10429 int count;
10430 rtx op1;
10431 int i;
10433 /* Support only loading a constant number of fixed-point registers from
10434 memory and only bother with this if more than two; the machine
10435 doesn't support more than eight. */
10436 if (GET_CODE (operands[2]) != CONST_INT
10437 || INTVAL (operands[2]) <= 2
10438 || INTVAL (operands[2]) > 8
10439 || GET_CODE (operands[1]) != MEM
10440 || GET_CODE (operands[0]) != REG
10441 || REGNO (operands[0]) >= 32)
10442 FAIL;
10444 count = INTVAL (operands[2]);
10445 regno = REGNO (operands[0]);
10447 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
10448 op1 = replace_equiv_address (operands[1],
10449 force_reg (SImode, XEXP (operands[1], 0)));
10451 for (i = 0; i < count; i++)
10452 XVECEXP (operands[3], 0, i)
10453 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
10454 adjust_address_nv (op1, SImode, i * 4));
10455 }")
10457 (define_insn "*ldmsi8"
10458 [(match_parallel 0 "load_multiple_operation"
10459 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10460 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10461 (set (match_operand:SI 3 "gpc_reg_operand" "")
10462 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10463 (set (match_operand:SI 4 "gpc_reg_operand" "")
10464 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10465 (set (match_operand:SI 5 "gpc_reg_operand" "")
10466 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10467 (set (match_operand:SI 6 "gpc_reg_operand" "")
10468 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10469 (set (match_operand:SI 7 "gpc_reg_operand" "")
10470 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
10471 (set (match_operand:SI 8 "gpc_reg_operand" "")
10472 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
10473 (set (match_operand:SI 9 "gpc_reg_operand" "")
10474 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
10475 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
10476 "*
10477 { return rs6000_output_load_multiple (operands); }"
10478 [(set_attr "type" "load_ux")
10479 (set_attr "length" "32")])
10481 (define_insn "*ldmsi7"
10482 [(match_parallel 0 "load_multiple_operation"
10483 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10484 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10485 (set (match_operand:SI 3 "gpc_reg_operand" "")
10486 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10487 (set (match_operand:SI 4 "gpc_reg_operand" "")
10488 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10489 (set (match_operand:SI 5 "gpc_reg_operand" "")
10490 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10491 (set (match_operand:SI 6 "gpc_reg_operand" "")
10492 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10493 (set (match_operand:SI 7 "gpc_reg_operand" "")
10494 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
10495 (set (match_operand:SI 8 "gpc_reg_operand" "")
10496 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
10497 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
10498 "*
10499 { return rs6000_output_load_multiple (operands); }"
10500 [(set_attr "type" "load_ux")
10501 (set_attr "length" "32")])
10503 (define_insn "*ldmsi6"
10504 [(match_parallel 0 "load_multiple_operation"
10505 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10506 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10507 (set (match_operand:SI 3 "gpc_reg_operand" "")
10508 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10509 (set (match_operand:SI 4 "gpc_reg_operand" "")
10510 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10511 (set (match_operand:SI 5 "gpc_reg_operand" "")
10512 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10513 (set (match_operand:SI 6 "gpc_reg_operand" "")
10514 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10515 (set (match_operand:SI 7 "gpc_reg_operand" "")
10516 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
10517 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
10518 "*
10519 { return rs6000_output_load_multiple (operands); }"
10520 [(set_attr "type" "load_ux")
10521 (set_attr "length" "32")])
10523 (define_insn "*ldmsi5"
10524 [(match_parallel 0 "load_multiple_operation"
10525 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10526 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10527 (set (match_operand:SI 3 "gpc_reg_operand" "")
10528 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10529 (set (match_operand:SI 4 "gpc_reg_operand" "")
10530 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10531 (set (match_operand:SI 5 "gpc_reg_operand" "")
10532 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10533 (set (match_operand:SI 6 "gpc_reg_operand" "")
10534 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
10535 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
10536 "*
10537 { return rs6000_output_load_multiple (operands); }"
10538 [(set_attr "type" "load_ux")
10539 (set_attr "length" "32")])
10541 (define_insn "*ldmsi4"
10542 [(match_parallel 0 "load_multiple_operation"
10543 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10544 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10545 (set (match_operand:SI 3 "gpc_reg_operand" "")
10546 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10547 (set (match_operand:SI 4 "gpc_reg_operand" "")
10548 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10549 (set (match_operand:SI 5 "gpc_reg_operand" "")
10550 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
10551 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
10552 "*
10553 { return rs6000_output_load_multiple (operands); }"
10554 [(set_attr "type" "load_ux")
10555 (set_attr "length" "32")])
10557 (define_insn "*ldmsi3"
10558 [(match_parallel 0 "load_multiple_operation"
10559 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10560 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10561 (set (match_operand:SI 3 "gpc_reg_operand" "")
10562 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10563 (set (match_operand:SI 4 "gpc_reg_operand" "")
10564 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
10565 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
10566 "*
10567 { return rs6000_output_load_multiple (operands); }"
10568 [(set_attr "type" "load_ux")
10569 (set_attr "length" "32")])
10571 (define_expand "store_multiple"
10572 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10573 (match_operand:SI 1 "" ""))
10574 (clobber (scratch:SI))
10575 (use (match_operand:SI 2 "" ""))])]
10576 "TARGET_STRING && !TARGET_POWERPC64"
10577 "
10578 {
10579 int regno;
10580 int count;
10581 rtx to;
10582 rtx op0;
10583 int i;
10585 /* Support only storing a constant number of fixed-point registers to
10586 memory and only bother with this if more than two; the machine
10587 doesn't support more than eight. */
10588 if (GET_CODE (operands[2]) != CONST_INT
10589 || INTVAL (operands[2]) <= 2
10590 || INTVAL (operands[2]) > 8
10591 || GET_CODE (operands[0]) != MEM
10592 || GET_CODE (operands[1]) != REG
10593 || REGNO (operands[1]) >= 32)
10594 FAIL;
10596 count = INTVAL (operands[2]);
10597 regno = REGNO (operands[1]);
10599 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
10600 to = force_reg (SImode, XEXP (operands[0], 0));
10601 op0 = replace_equiv_address (operands[0], to);
10603 XVECEXP (operands[3], 0, 0)
10604 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
10605 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
10606 gen_rtx_SCRATCH (SImode));
10608 for (i = 1; i < count; i++)
10609 XVECEXP (operands[3], 0, i + 1)
10610 = gen_rtx_SET (VOIDmode,
10611 adjust_address_nv (op0, SImode, i * 4),
10612 gen_rtx_REG (SImode, regno + i));
10613 }")
10615 (define_insn "*stmsi8"
10616 [(match_parallel 0 "store_multiple_operation"
10617 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10618 (match_operand:SI 2 "gpc_reg_operand" "r"))
10619 (clobber (match_scratch:SI 3 "=X"))
10620 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10621 (match_operand:SI 4 "gpc_reg_operand" "r"))
10622 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10623 (match_operand:SI 5 "gpc_reg_operand" "r"))
10624 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10625 (match_operand:SI 6 "gpc_reg_operand" "r"))
10626 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10627 (match_operand:SI 7 "gpc_reg_operand" "r"))
10628 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10629 (match_operand:SI 8 "gpc_reg_operand" "r"))
10630 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10631 (match_operand:SI 9 "gpc_reg_operand" "r"))
10632 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10633 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10634 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10635 "{stsi|stswi} %2,%1,%O0"
10636 [(set_attr "type" "store_ux")
10637 (set_attr "cell_micro" "always")])
10639 (define_insn "*stmsi7"
10640 [(match_parallel 0 "store_multiple_operation"
10641 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10642 (match_operand:SI 2 "gpc_reg_operand" "r"))
10643 (clobber (match_scratch:SI 3 "=X"))
10644 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10645 (match_operand:SI 4 "gpc_reg_operand" "r"))
10646 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10647 (match_operand:SI 5 "gpc_reg_operand" "r"))
10648 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10649 (match_operand:SI 6 "gpc_reg_operand" "r"))
10650 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10651 (match_operand:SI 7 "gpc_reg_operand" "r"))
10652 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10653 (match_operand:SI 8 "gpc_reg_operand" "r"))
10654 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10655 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10656 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10657 "{stsi|stswi} %2,%1,%O0"
10658 [(set_attr "type" "store_ux")
10659 (set_attr "cell_micro" "always")])
10661 (define_insn "*stmsi6"
10662 [(match_parallel 0 "store_multiple_operation"
10663 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10664 (match_operand:SI 2 "gpc_reg_operand" "r"))
10665 (clobber (match_scratch:SI 3 "=X"))
10666 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10667 (match_operand:SI 4 "gpc_reg_operand" "r"))
10668 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10669 (match_operand:SI 5 "gpc_reg_operand" "r"))
10670 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10671 (match_operand:SI 6 "gpc_reg_operand" "r"))
10672 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10673 (match_operand:SI 7 "gpc_reg_operand" "r"))
10674 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10675 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10676 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10677 "{stsi|stswi} %2,%1,%O0"
10678 [(set_attr "type" "store_ux")
10679 (set_attr "cell_micro" "always")])
10681 (define_insn "*stmsi5"
10682 [(match_parallel 0 "store_multiple_operation"
10683 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10684 (match_operand:SI 2 "gpc_reg_operand" "r"))
10685 (clobber (match_scratch:SI 3 "=X"))
10686 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10687 (match_operand:SI 4 "gpc_reg_operand" "r"))
10688 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10689 (match_operand:SI 5 "gpc_reg_operand" "r"))
10690 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10691 (match_operand:SI 6 "gpc_reg_operand" "r"))
10692 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10693 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10694 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10695 "{stsi|stswi} %2,%1,%O0"
10696 [(set_attr "type" "store_ux")
10697 (set_attr "cell_micro" "always")])
10699 (define_insn "*stmsi4"
10700 [(match_parallel 0 "store_multiple_operation"
10701 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10702 (match_operand:SI 2 "gpc_reg_operand" "r"))
10703 (clobber (match_scratch:SI 3 "=X"))
10704 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10705 (match_operand:SI 4 "gpc_reg_operand" "r"))
10706 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10707 (match_operand:SI 5 "gpc_reg_operand" "r"))
10708 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10709 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10710 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10711 "{stsi|stswi} %2,%1,%O0"
10712 [(set_attr "type" "store_ux")
10713 (set_attr "cell_micro" "always")])
10715 (define_insn "*stmsi3"
10716 [(match_parallel 0 "store_multiple_operation"
10717 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10718 (match_operand:SI 2 "gpc_reg_operand" "r"))
10719 (clobber (match_scratch:SI 3 "=X"))
10720 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10721 (match_operand:SI 4 "gpc_reg_operand" "r"))
10722 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10723 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10724 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10725 "{stsi|stswi} %2,%1,%O0"
10726 [(set_attr "type" "store_ux")
10727 (set_attr "cell_micro" "always")])
10729 (define_insn "*stmsi8_power"
10730 [(match_parallel 0 "store_multiple_operation"
10731 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10732 (match_operand:SI 2 "gpc_reg_operand" "r"))
10733 (clobber (match_scratch:SI 3 "=q"))
10734 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10735 (match_operand:SI 4 "gpc_reg_operand" "r"))
10736 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10737 (match_operand:SI 5 "gpc_reg_operand" "r"))
10738 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10739 (match_operand:SI 6 "gpc_reg_operand" "r"))
10740 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10741 (match_operand:SI 7 "gpc_reg_operand" "r"))
10742 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10743 (match_operand:SI 8 "gpc_reg_operand" "r"))
10744 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10745 (match_operand:SI 9 "gpc_reg_operand" "r"))
10746 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10747 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10748 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10749 "{stsi|stswi} %2,%1,%O0"
10750 [(set_attr "type" "store_ux")
10751 (set_attr "cell_micro" "always")])
10753 (define_insn "*stmsi7_power"
10754 [(match_parallel 0 "store_multiple_operation"
10755 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10756 (match_operand:SI 2 "gpc_reg_operand" "r"))
10757 (clobber (match_scratch:SI 3 "=q"))
10758 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10759 (match_operand:SI 4 "gpc_reg_operand" "r"))
10760 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10761 (match_operand:SI 5 "gpc_reg_operand" "r"))
10762 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10763 (match_operand:SI 6 "gpc_reg_operand" "r"))
10764 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10765 (match_operand:SI 7 "gpc_reg_operand" "r"))
10766 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10767 (match_operand:SI 8 "gpc_reg_operand" "r"))
10768 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10769 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10770 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10771 "{stsi|stswi} %2,%1,%O0"
10772 [(set_attr "type" "store_ux")
10773 (set_attr "cell_micro" "always")])
10775 (define_insn "*stmsi6_power"
10776 [(match_parallel 0 "store_multiple_operation"
10777 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10778 (match_operand:SI 2 "gpc_reg_operand" "r"))
10779 (clobber (match_scratch:SI 3 "=q"))
10780 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10781 (match_operand:SI 4 "gpc_reg_operand" "r"))
10782 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10783 (match_operand:SI 5 "gpc_reg_operand" "r"))
10784 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10785 (match_operand:SI 6 "gpc_reg_operand" "r"))
10786 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10787 (match_operand:SI 7 "gpc_reg_operand" "r"))
10788 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10789 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10790 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10791 "{stsi|stswi} %2,%1,%O0"
10792 [(set_attr "type" "store_ux")
10793 (set_attr "cell_micro" "always")])
10795 (define_insn "*stmsi5_power"
10796 [(match_parallel 0 "store_multiple_operation"
10797 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10798 (match_operand:SI 2 "gpc_reg_operand" "r"))
10799 (clobber (match_scratch:SI 3 "=q"))
10800 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10801 (match_operand:SI 4 "gpc_reg_operand" "r"))
10802 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10803 (match_operand:SI 5 "gpc_reg_operand" "r"))
10804 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10805 (match_operand:SI 6 "gpc_reg_operand" "r"))
10806 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10807 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10808 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10809 "{stsi|stswi} %2,%1,%O0"
10810 [(set_attr "type" "store_ux")
10811 (set_attr "cell_micro" "always")])
10813 (define_insn "*stmsi4_power"
10814 [(match_parallel 0 "store_multiple_operation"
10815 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10816 (match_operand:SI 2 "gpc_reg_operand" "r"))
10817 (clobber (match_scratch:SI 3 "=q"))
10818 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10819 (match_operand:SI 4 "gpc_reg_operand" "r"))
10820 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10821 (match_operand:SI 5 "gpc_reg_operand" "r"))
10822 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10823 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10824 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10825 "{stsi|stswi} %2,%1,%O0"
10826 [(set_attr "type" "store_ux")
10827 (set_attr "cell_micro" "always")])
10829 (define_insn "*stmsi3_power"
10830 [(match_parallel 0 "store_multiple_operation"
10831 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10832 (match_operand:SI 2 "gpc_reg_operand" "r"))
10833 (clobber (match_scratch:SI 3 "=q"))
10834 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10835 (match_operand:SI 4 "gpc_reg_operand" "r"))
10836 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10837 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10838 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10839 "{stsi|stswi} %2,%1,%O0"
10840 [(set_attr "type" "store_ux")
10841 (set_attr "cell_micro" "always")])
10842 \f
10843 (define_expand "setmemsi"
10844 [(parallel [(set (match_operand:BLK 0 "" "")
10845 (match_operand 2 "const_int_operand" ""))
10846 (use (match_operand:SI 1 "" ""))
10847 (use (match_operand:SI 3 "" ""))])]
10848 ""
10849 "
10850 {
10851 /* If value to set is not zero, use the library routine. */
10852 if (operands[2] != const0_rtx)
10853 FAIL;
10855 if (expand_block_clear (operands))
10856 DONE;
10857 else
10858 FAIL;
10859 }")
10861 ;; String/block move insn.
10862 ;; Argument 0 is the destination
10863 ;; Argument 1 is the source
10864 ;; Argument 2 is the length
10865 ;; Argument 3 is the alignment
10867 (define_expand "movmemsi"
10868 [(parallel [(set (match_operand:BLK 0 "" "")
10869 (match_operand:BLK 1 "" ""))
10870 (use (match_operand:SI 2 "" ""))
10871 (use (match_operand:SI 3 "" ""))])]
10872 ""
10873 "
10874 {
10875 if (expand_block_move (operands))
10876 DONE;
10877 else
10878 FAIL;
10879 }")
10881 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
10882 ;; register allocator doesn't have a clue about allocating 8 word registers.
10883 ;; rD/rS = r5 is preferred, efficient form.
10884 (define_expand "movmemsi_8reg"
10885 [(parallel [(set (match_operand 0 "" "")
10886 (match_operand 1 "" ""))
10887 (use (match_operand 2 "" ""))
10888 (use (match_operand 3 "" ""))
10889 (clobber (reg:SI 5))
10890 (clobber (reg:SI 6))
10891 (clobber (reg:SI 7))
10892 (clobber (reg:SI 8))
10893 (clobber (reg:SI 9))
10894 (clobber (reg:SI 10))
10895 (clobber (reg:SI 11))
10896 (clobber (reg:SI 12))
10897 (clobber (match_scratch:SI 4 ""))])]
10898 "TARGET_STRING"
10899 "")
10901 (define_insn ""
10902 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10903 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10904 (use (match_operand:SI 2 "immediate_operand" "i"))
10905 (use (match_operand:SI 3 "immediate_operand" "i"))
10906 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10907 (clobber (reg:SI 6))
10908 (clobber (reg:SI 7))
10909 (clobber (reg:SI 8))
10910 (clobber (reg:SI 9))
10911 (clobber (reg:SI 10))
10912 (clobber (reg:SI 11))
10913 (clobber (reg:SI 12))
10914 (clobber (match_scratch:SI 5 "=q"))]
10915 "TARGET_STRING && TARGET_POWER
10916 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10917 || INTVAL (operands[2]) == 0)
10918 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10919 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10920 && REGNO (operands[4]) == 5"
10921 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10922 [(set_attr "type" "store_ux")
10923 (set_attr "cell_micro" "always")
10924 (set_attr "length" "8")])
10926 (define_insn ""
10927 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10928 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10929 (use (match_operand:SI 2 "immediate_operand" "i"))
10930 (use (match_operand:SI 3 "immediate_operand" "i"))
10931 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10932 (clobber (reg:SI 6))
10933 (clobber (reg:SI 7))
10934 (clobber (reg:SI 8))
10935 (clobber (reg:SI 9))
10936 (clobber (reg:SI 10))
10937 (clobber (reg:SI 11))
10938 (clobber (reg:SI 12))
10939 (clobber (match_scratch:SI 5 "=X"))]
10940 "TARGET_STRING && ! TARGET_POWER
10941 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10942 || INTVAL (operands[2]) == 0)
10943 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10944 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10945 && REGNO (operands[4]) == 5"
10946 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10947 [(set_attr "type" "store_ux")
10948 (set_attr "cell_micro" "always")
10949 (set_attr "length" "8")])
10951 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
10952 ;; register allocator doesn't have a clue about allocating 6 word registers.
10953 ;; rD/rS = r5 is preferred, efficient form.
10954 (define_expand "movmemsi_6reg"
10955 [(parallel [(set (match_operand 0 "" "")
10956 (match_operand 1 "" ""))
10957 (use (match_operand 2 "" ""))
10958 (use (match_operand 3 "" ""))
10959 (clobber (reg:SI 5))
10960 (clobber (reg:SI 6))
10961 (clobber (reg:SI 7))
10962 (clobber (reg:SI 8))
10963 (clobber (reg:SI 9))
10964 (clobber (reg:SI 10))
10965 (clobber (match_scratch:SI 4 ""))])]
10966 "TARGET_STRING"
10967 "")
10969 (define_insn ""
10970 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10971 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10972 (use (match_operand:SI 2 "immediate_operand" "i"))
10973 (use (match_operand:SI 3 "immediate_operand" "i"))
10974 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10975 (clobber (reg:SI 6))
10976 (clobber (reg:SI 7))
10977 (clobber (reg:SI 8))
10978 (clobber (reg:SI 9))
10979 (clobber (reg:SI 10))
10980 (clobber (match_scratch:SI 5 "=q"))]
10981 "TARGET_STRING && TARGET_POWER
10982 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
10983 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10984 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10985 && REGNO (operands[4]) == 5"
10986 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10987 [(set_attr "type" "store_ux")
10988 (set_attr "cell_micro" "always")
10989 (set_attr "length" "8")])
10991 (define_insn ""
10992 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10993 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10994 (use (match_operand:SI 2 "immediate_operand" "i"))
10995 (use (match_operand:SI 3 "immediate_operand" "i"))
10996 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10997 (clobber (reg:SI 6))
10998 (clobber (reg:SI 7))
10999 (clobber (reg:SI 8))
11000 (clobber (reg:SI 9))
11001 (clobber (reg:SI 10))
11002 (clobber (match_scratch:SI 5 "=X"))]
11003 "TARGET_STRING && ! TARGET_POWER
11004 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
11005 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
11006 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
11007 && REGNO (operands[4]) == 5"
11008 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11009 [(set_attr "type" "store_ux")
11010 (set_attr "cell_micro" "always")
11011 (set_attr "length" "8")])
11013 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
11014 ;; problems with TImode.
11015 ;; rD/rS = r5 is preferred, efficient form.
11016 (define_expand "movmemsi_4reg"
11017 [(parallel [(set (match_operand 0 "" "")
11018 (match_operand 1 "" ""))
11019 (use (match_operand 2 "" ""))
11020 (use (match_operand 3 "" ""))
11021 (clobber (reg:SI 5))
11022 (clobber (reg:SI 6))
11023 (clobber (reg:SI 7))
11024 (clobber (reg:SI 8))
11025 (clobber (match_scratch:SI 4 ""))])]
11026 "TARGET_STRING"
11027 "")
11029 (define_insn ""
11030 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
11031 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
11032 (use (match_operand:SI 2 "immediate_operand" "i"))
11033 (use (match_operand:SI 3 "immediate_operand" "i"))
11034 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
11035 (clobber (reg:SI 6))
11036 (clobber (reg:SI 7))
11037 (clobber (reg:SI 8))
11038 (clobber (match_scratch:SI 5 "=q"))]
11039 "TARGET_STRING && TARGET_POWER
11040 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
11041 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
11042 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
11043 && REGNO (operands[4]) == 5"
11044 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11045 [(set_attr "type" "store_ux")
11046 (set_attr "cell_micro" "always")
11047 (set_attr "length" "8")])
11049 (define_insn ""
11050 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
11051 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
11052 (use (match_operand:SI 2 "immediate_operand" "i"))
11053 (use (match_operand:SI 3 "immediate_operand" "i"))
11054 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
11055 (clobber (reg:SI 6))
11056 (clobber (reg:SI 7))
11057 (clobber (reg:SI 8))
11058 (clobber (match_scratch:SI 5 "=X"))]
11059 "TARGET_STRING && ! TARGET_POWER
11060 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
11061 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
11062 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
11063 && REGNO (operands[4]) == 5"
11064 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11065 [(set_attr "type" "store_ux")
11066 (set_attr "cell_micro" "always")
11067 (set_attr "length" "8")])
11069 ;; Move up to 8 bytes at a time.
11070 (define_expand "movmemsi_2reg"
11071 [(parallel [(set (match_operand 0 "" "")
11072 (match_operand 1 "" ""))
11073 (use (match_operand 2 "" ""))
11074 (use (match_operand 3 "" ""))
11075 (clobber (match_scratch:DI 4 ""))
11076 (clobber (match_scratch:SI 5 ""))])]
11077 "TARGET_STRING && ! TARGET_POWERPC64"
11078 "")
11080 (define_insn ""
11081 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
11082 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
11083 (use (match_operand:SI 2 "immediate_operand" "i"))
11084 (use (match_operand:SI 3 "immediate_operand" "i"))
11085 (clobber (match_scratch:DI 4 "=&r"))
11086 (clobber (match_scratch:SI 5 "=q"))]
11087 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
11088 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
11089 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11090 [(set_attr "type" "store_ux")
11091 (set_attr "cell_micro" "always")
11092 (set_attr "length" "8")])
11094 (define_insn ""
11095 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
11096 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
11097 (use (match_operand:SI 2 "immediate_operand" "i"))
11098 (use (match_operand:SI 3 "immediate_operand" "i"))
11099 (clobber (match_scratch:DI 4 "=&r"))
11100 (clobber (match_scratch:SI 5 "=X"))]
11101 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
11102 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
11103 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11104 [(set_attr "type" "store_ux")
11105 (set_attr "cell_micro" "always")
11106 (set_attr "length" "8")])
11108 ;; Move up to 4 bytes at a time.
11109 (define_expand "movmemsi_1reg"
11110 [(parallel [(set (match_operand 0 "" "")
11111 (match_operand 1 "" ""))
11112 (use (match_operand 2 "" ""))
11113 (use (match_operand 3 "" ""))
11114 (clobber (match_scratch:SI 4 ""))
11115 (clobber (match_scratch:SI 5 ""))])]
11116 "TARGET_STRING"
11117 "")
11119 (define_insn ""
11120 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
11121 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
11122 (use (match_operand:SI 2 "immediate_operand" "i"))
11123 (use (match_operand:SI 3 "immediate_operand" "i"))
11124 (clobber (match_scratch:SI 4 "=&r"))
11125 (clobber (match_scratch:SI 5 "=q"))]
11126 "TARGET_STRING && TARGET_POWER
11127 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
11128 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11129 [(set_attr "type" "store_ux")
11130 (set_attr "cell_micro" "always")
11131 (set_attr "length" "8")])
11133 (define_insn ""
11134 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
11135 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
11136 (use (match_operand:SI 2 "immediate_operand" "i"))
11137 (use (match_operand:SI 3 "immediate_operand" "i"))
11138 (clobber (match_scratch:SI 4 "=&r"))
11139 (clobber (match_scratch:SI 5 "=X"))]
11140 "TARGET_STRING && ! TARGET_POWER
11141 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
11142 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
11143 [(set_attr "type" "store_ux")
11144 (set_attr "cell_micro" "always")
11145 (set_attr "length" "8")])
11146 \f
11147 ;; Define insns that do load or store with update. Some of these we can
11148 ;; get by using pre-decrement or pre-increment, but the hardware can also
11149 ;; do cases where the increment is not the size of the object.
11150 ;;
11151 ;; In all these cases, we use operands 0 and 1 for the register being
11152 ;; incremented because those are the operands that local-alloc will
11153 ;; tie and these are the pair most likely to be tieable (and the ones
11154 ;; that will benefit the most).
11156 (define_insn "*movdi_update1"
11157 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
11158 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
11159 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
11160 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
11161 (plus:DI (match_dup 1) (match_dup 2)))]
11162 "TARGET_POWERPC64 && TARGET_UPDATE
11163 && (!avoiding_indexed_address_p (DImode)
11164 || !gpc_reg_operand (operands[2], DImode))"
11165 "@
11166 ldux %3,%0,%2
11167 ldu %3,%2(%0)"
11168 [(set_attr "type" "load_ux,load_u")])
11170 (define_insn "movdi_<mode>_update"
11171 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
11172 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
11173 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
11174 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
11175 (plus:P (match_dup 1) (match_dup 2)))]
11176 "TARGET_POWERPC64 && TARGET_UPDATE
11177 && (!avoiding_indexed_address_p (Pmode)
11178 || !gpc_reg_operand (operands[2], Pmode)
11179 || (REG_P (operands[0])
11180 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
11181 "@
11182 stdux %3,%0,%2
11183 stdu %3,%2(%0)"
11184 [(set_attr "type" "store_ux,store_u")])
11186 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
11187 ;; needed for stack allocation, even if the user passes -mno-update.
11188 (define_insn "movdi_<mode>_update_stack"
11189 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
11190 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
11191 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
11192 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
11193 (plus:P (match_dup 1) (match_dup 2)))]
11194 "TARGET_POWERPC64"
11195 "@
11196 stdux %3,%0,%2
11197 stdu %3,%2(%0)"
11198 [(set_attr "type" "store_ux,store_u")])
11200 (define_insn "*movsi_update1"
11201 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11202 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11203 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11204 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11205 (plus:SI (match_dup 1) (match_dup 2)))]
11206 "TARGET_UPDATE
11207 && (!avoiding_indexed_address_p (SImode)
11208 || !gpc_reg_operand (operands[2], SImode))"
11209 "@
11210 {lux|lwzux} %3,%0,%2
11211 {lu|lwzu} %3,%2(%0)"
11212 [(set_attr "type" "load_ux,load_u")])
11214 (define_insn "*movsi_update2"
11215 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
11216 (sign_extend:DI
11217 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
11218 (match_operand:DI 2 "gpc_reg_operand" "r")))))
11219 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
11220 (plus:DI (match_dup 1) (match_dup 2)))]
11221 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
11222 && !avoiding_indexed_address_p (DImode)"
11223 "lwaux %3,%0,%2"
11224 [(set_attr "type" "load_ext_ux")])
11226 (define_insn "movsi_update"
11227 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11228 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11229 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11230 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11231 (plus:SI (match_dup 1) (match_dup 2)))]
11232 "TARGET_UPDATE
11233 && (!avoiding_indexed_address_p (SImode)
11234 || !gpc_reg_operand (operands[2], SImode)
11235 || (REG_P (operands[0])
11236 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
11237 "@
11238 {stux|stwux} %3,%0,%2
11239 {stu|stwu} %3,%2(%0)"
11240 [(set_attr "type" "store_ux,store_u")])
11242 ;; This is an unconditional pattern; needed for stack allocation, even
11243 ;; if the user passes -mno-update.
11244 (define_insn "movsi_update_stack"
11245 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11246 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11247 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11248 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11249 (plus:SI (match_dup 1) (match_dup 2)))]
11250 ""
11251 "@
11252 {stux|stwux} %3,%0,%2
11253 {stu|stwu} %3,%2(%0)"
11254 [(set_attr "type" "store_ux,store_u")])
11256 (define_insn "*movhi_update1"
11257 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
11258 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11259 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11260 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11261 (plus:SI (match_dup 1) (match_dup 2)))]
11262 "TARGET_UPDATE
11263 && (!avoiding_indexed_address_p (SImode)
11264 || !gpc_reg_operand (operands[2], SImode))"
11265 "@
11266 lhzux %3,%0,%2
11267 lhzu %3,%2(%0)"
11268 [(set_attr "type" "load_ux,load_u")])
11270 (define_insn "*movhi_update2"
11271 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11272 (zero_extend:SI
11273 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11274 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
11275 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11276 (plus:SI (match_dup 1) (match_dup 2)))]
11277 "TARGET_UPDATE
11278 && (!avoiding_indexed_address_p (SImode)
11279 || !gpc_reg_operand (operands[2], SImode))"
11280 "@
11281 lhzux %3,%0,%2
11282 lhzu %3,%2(%0)"
11283 [(set_attr "type" "load_ux,load_u")])
11285 (define_insn "*movhi_update3"
11286 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11287 (sign_extend:SI
11288 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11289 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
11290 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11291 (plus:SI (match_dup 1) (match_dup 2)))]
11292 "TARGET_UPDATE && rs6000_gen_cell_microcode
11293 && (!avoiding_indexed_address_p (SImode)
11294 || !gpc_reg_operand (operands[2], SImode))"
11295 "@
11296 lhaux %3,%0,%2
11297 lhau %3,%2(%0)"
11298 [(set_attr "type" "load_ext_ux,load_ext_u")])
11300 (define_insn "*movhi_update4"
11301 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11302 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11303 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
11304 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11305 (plus:SI (match_dup 1) (match_dup 2)))]
11306 "TARGET_UPDATE
11307 && (!avoiding_indexed_address_p (SImode)
11308 || !gpc_reg_operand (operands[2], SImode))"
11309 "@
11310 sthux %3,%0,%2
11311 sthu %3,%2(%0)"
11312 [(set_attr "type" "store_ux,store_u")])
11314 (define_insn "*movqi_update1"
11315 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
11316 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11317 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11318 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11319 (plus:SI (match_dup 1) (match_dup 2)))]
11320 "TARGET_UPDATE
11321 && (!avoiding_indexed_address_p (SImode)
11322 || !gpc_reg_operand (operands[2], SImode))"
11323 "@
11324 lbzux %3,%0,%2
11325 lbzu %3,%2(%0)"
11326 [(set_attr "type" "load_ux,load_u")])
11328 (define_insn "*movqi_update2"
11329 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11330 (zero_extend:SI
11331 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11332 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
11333 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11334 (plus:SI (match_dup 1) (match_dup 2)))]
11335 "TARGET_UPDATE
11336 && (!avoiding_indexed_address_p (SImode)
11337 || !gpc_reg_operand (operands[2], SImode))"
11338 "@
11339 lbzux %3,%0,%2
11340 lbzu %3,%2(%0)"
11341 [(set_attr "type" "load_ux,load_u")])
11343 (define_insn "*movqi_update3"
11344 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11345 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11346 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
11347 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11348 (plus:SI (match_dup 1) (match_dup 2)))]
11349 "TARGET_UPDATE
11350 && (!avoiding_indexed_address_p (SImode)
11351 || !gpc_reg_operand (operands[2], SImode))"
11352 "@
11353 stbux %3,%0,%2
11354 stbu %3,%2(%0)"
11355 [(set_attr "type" "store_ux,store_u")])
11357 (define_insn "*movsf_update1"
11358 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
11359 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11360 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11361 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11362 (plus:SI (match_dup 1) (match_dup 2)))]
11363 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
11364 && (!avoiding_indexed_address_p (SImode)
11365 || !gpc_reg_operand (operands[2], SImode))"
11366 "@
11367 lfsux %3,%0,%2
11368 lfsu %3,%2(%0)"
11369 [(set_attr "type" "fpload_ux,fpload_u")])
11371 (define_insn "*movsf_update2"
11372 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11373 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11374 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
11375 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11376 (plus:SI (match_dup 1) (match_dup 2)))]
11377 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
11378 && (!avoiding_indexed_address_p (SImode)
11379 || !gpc_reg_operand (operands[2], SImode))"
11380 "@
11381 stfsux %3,%0,%2
11382 stfsu %3,%2(%0)"
11383 [(set_attr "type" "fpstore_ux,fpstore_u")])
11385 (define_insn "*movsf_update3"
11386 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
11387 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11388 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11389 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11390 (plus:SI (match_dup 1) (match_dup 2)))]
11391 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
11392 && (!avoiding_indexed_address_p (SImode)
11393 || !gpc_reg_operand (operands[2], SImode))"
11394 "@
11395 {lux|lwzux} %3,%0,%2
11396 {lu|lwzu} %3,%2(%0)"
11397 [(set_attr "type" "load_ux,load_u")])
11399 (define_insn "*movsf_update4"
11400 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11401 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11402 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
11403 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11404 (plus:SI (match_dup 1) (match_dup 2)))]
11405 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
11406 && (!avoiding_indexed_address_p (SImode)
11407 || !gpc_reg_operand (operands[2], SImode))"
11408 "@
11409 {stux|stwux} %3,%0,%2
11410 {stu|stwu} %3,%2(%0)"
11411 [(set_attr "type" "store_ux,store_u")])
11413 (define_insn "*movdf_update1"
11414 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
11415 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11416 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11417 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11418 (plus:SI (match_dup 1) (match_dup 2)))]
11419 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
11420 && (!avoiding_indexed_address_p (SImode)
11421 || !gpc_reg_operand (operands[2], SImode))"
11422 "@
11423 lfdux %3,%0,%2
11424 lfdu %3,%2(%0)"
11425 [(set_attr "type" "fpload_ux,fpload_u")])
11427 (define_insn "*movdf_update2"
11428 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11429 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11430 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
11431 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11432 (plus:SI (match_dup 1) (match_dup 2)))]
11433 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
11434 && (!avoiding_indexed_address_p (SImode)
11435 || !gpc_reg_operand (operands[2], SImode))"
11436 "@
11437 stfdux %3,%0,%2
11438 stfdu %3,%2(%0)"
11439 [(set_attr "type" "fpstore_ux,fpstore_u")])
11441 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
11443 (define_insn "*lfq_power2"
11444 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
11445 (match_operand:V2DF 1 "memory_operand" ""))]
11446 "TARGET_POWER2
11447 && TARGET_HARD_FLOAT && TARGET_FPRS"
11448 "lfq%U1%X1 %0,%1")
11450 (define_peephole2
11451 [(set (match_operand:DF 0 "gpc_reg_operand" "")
11452 (match_operand:DF 1 "memory_operand" ""))
11453 (set (match_operand:DF 2 "gpc_reg_operand" "")
11454 (match_operand:DF 3 "memory_operand" ""))]
11455 "TARGET_POWER2
11456 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
11457 && registers_ok_for_quad_peep (operands[0], operands[2])
11458 && mems_ok_for_quad_peep (operands[1], operands[3])"
11459 [(set (match_dup 0)
11460 (match_dup 1))]
11461 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
11462 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
11464 (define_insn "*stfq_power2"
11465 [(set (match_operand:V2DF 0 "memory_operand" "")
11466 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
11467 "TARGET_POWER2
11468 && TARGET_HARD_FLOAT && TARGET_FPRS"
11469 "stfq%U0%X0 %1,%0")
11472 (define_peephole2
11473 [(set (match_operand:DF 0 "memory_operand" "")
11474 (match_operand:DF 1 "gpc_reg_operand" ""))
11475 (set (match_operand:DF 2 "memory_operand" "")
11476 (match_operand:DF 3 "gpc_reg_operand" ""))]
11477 "TARGET_POWER2
11478 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
11479 && registers_ok_for_quad_peep (operands[1], operands[3])
11480 && mems_ok_for_quad_peep (operands[0], operands[2])"
11481 [(set (match_dup 0)
11482 (match_dup 1))]
11483 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
11484 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
11486 ;; After inserting conditional returns we can sometimes have
11487 ;; unnecessary register moves. Unfortunately we cannot have a
11488 ;; modeless peephole here, because some single SImode sets have early
11489 ;; clobber outputs. Although those sets expand to multi-ppc-insn
11490 ;; sequences, using get_attr_length here will smash the operands
11491 ;; array. Neither is there an early_cobbler_p predicate.
11492 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
11493 (define_peephole2
11494 [(set (match_operand:DF 0 "gpc_reg_operand" "")
11495 (match_operand:DF 1 "any_operand" ""))
11496 (set (match_operand:DF 2 "gpc_reg_operand" "")
11497 (match_dup 0))]
11498 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
11499 && peep2_reg_dead_p (2, operands[0])"
11500 [(set (match_dup 2) (match_dup 1))])
11502 (define_peephole2
11503 [(set (match_operand:SF 0 "gpc_reg_operand" "")
11504 (match_operand:SF 1 "any_operand" ""))
11505 (set (match_operand:SF 2 "gpc_reg_operand" "")
11506 (match_dup 0))]
11507 "peep2_reg_dead_p (2, operands[0])"
11508 [(set (match_dup 2) (match_dup 1))])
11510 \f
11511 ;; TLS support.
11513 ;; Mode attributes for different ABIs.
11514 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
11515 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
11516 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
11517 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
11519 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
11520 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11521 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11522 (match_operand 4 "" "g")))
11523 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11524 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11525 UNSPEC_TLSGD)
11526 (clobber (reg:SI LR_REGNO))]
11527 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11528 {
11529 if (TARGET_CMODEL != CMODEL_SMALL)
11530 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;bl %z3\;%.";
11531 else
11532 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;%.";
11533 }
11534 "&& TARGET_TLS_MARKERS"
11535 [(set (match_dup 0)
11536 (unspec:TLSmode [(match_dup 1)
11537 (match_dup 2)]
11538 UNSPEC_TLSGD))
11539 (parallel [(set (match_dup 0)
11540 (call (mem:TLSmode (match_dup 3))
11541 (match_dup 4)))
11542 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11543 (clobber (reg:SI LR_REGNO))])]
11544 ""
11545 [(set_attr "type" "two")
11546 (set (attr "length")
11547 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11548 (const_int 16)
11549 (const_int 12)))])
11551 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
11552 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11553 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11554 (match_operand 4 "" "g")))
11555 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11556 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11557 UNSPEC_TLSGD)
11558 (clobber (reg:SI LR_REGNO))]
11559 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11560 {
11561 if (flag_pic)
11562 {
11563 if (TARGET_SECURE_PLT && flag_pic == 2)
11564 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
11565 else
11566 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
11567 }
11568 else
11569 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
11570 }
11571 "&& TARGET_TLS_MARKERS"
11572 [(set (match_dup 0)
11573 (unspec:TLSmode [(match_dup 1)
11574 (match_dup 2)]
11575 UNSPEC_TLSGD))
11576 (parallel [(set (match_dup 0)
11577 (call (mem:TLSmode (match_dup 3))
11578 (match_dup 4)))
11579 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11580 (clobber (reg:SI LR_REGNO))])]
11581 ""
11582 [(set_attr "type" "two")
11583 (set_attr "length" "8")])
11585 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
11586 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11587 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11588 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11589 UNSPEC_TLSGD))]
11590 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11591 "addi %0,%1,%2@got@tlsgd"
11592 "&& TARGET_CMODEL != CMODEL_SMALL"
11593 [(set (match_dup 3)
11594 (high:TLSmode
11595 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
11596 (set (match_dup 0)
11597 (lo_sum:TLSmode (match_dup 3)
11598 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)))]
11599 "
11600 {
11601 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11602 }"
11603 [(set (attr "length")
11604 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11605 (const_int 8)
11606 (const_int 4)))])
11608 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
11609 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11610 (high:TLSmode
11611 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11612 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11613 UNSPEC_TLSGD)))]
11614 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11615 "addis %0,%1,%2@got@tlsgd@ha"
11616 [(set_attr "length" "4")])
11618 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
11619 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11620 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11621 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11622 UNSPEC_TLSGD)))]
11623 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11624 "addi %0,%1,%2@got@tlsgd@l"
11625 [(set_attr "length" "4")])
11627 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
11628 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11629 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11630 (match_operand 2 "" "g")))
11631 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11632 UNSPEC_TLSGD)
11633 (clobber (reg:SI LR_REGNO))]
11634 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11635 "bl %z1(%3@tlsgd)\;%."
11636 [(set_attr "type" "branch")
11637 (set_attr "length" "8")])
11639 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
11640 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11641 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11642 (match_operand 2 "" "g")))
11643 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11644 UNSPEC_TLSGD)
11645 (clobber (reg:SI LR_REGNO))]
11646 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11647 {
11648 if (flag_pic)
11649 {
11650 if (TARGET_SECURE_PLT && flag_pic == 2)
11651 return "bl %z1+32768(%3@tlsgd)@plt";
11652 return "bl %z1(%3@tlsgd)@plt";
11653 }
11654 return "bl %z1(%3@tlsgd)";
11655 }
11656 [(set_attr "type" "branch")
11657 (set_attr "length" "4")])
11659 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
11660 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11661 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11662 (match_operand 3 "" "g")))
11663 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11664 UNSPEC_TLSLD)
11665 (clobber (reg:SI LR_REGNO))]
11666 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11667 {
11668 if (TARGET_CMODEL != CMODEL_SMALL)
11669 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;bl %z2\;%.";
11670 else
11671 return "addi %0,%1,%&@got@tlsld\;bl %z2\;%.";
11672 }
11673 "&& TARGET_TLS_MARKERS"
11674 [(set (match_dup 0)
11675 (unspec:TLSmode [(match_dup 1)]
11676 UNSPEC_TLSLD))
11677 (parallel [(set (match_dup 0)
11678 (call (mem:TLSmode (match_dup 2))
11679 (match_dup 3)))
11680 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11681 (clobber (reg:SI LR_REGNO))])]
11682 ""
11683 [(set_attr "type" "two")
11684 (set (attr "length")
11685 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11686 (const_int 16)
11687 (const_int 12)))])
11689 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
11690 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11691 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11692 (match_operand 3 "" "g")))
11693 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11694 UNSPEC_TLSLD)
11695 (clobber (reg:SI LR_REGNO))]
11696 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11697 {
11698 if (flag_pic)
11699 {
11700 if (TARGET_SECURE_PLT && flag_pic == 2)
11701 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
11702 else
11703 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
11704 }
11705 else
11706 return "addi %0,%1,%&@got@tlsld\;bl %z2";
11707 }
11708 "&& TARGET_TLS_MARKERS"
11709 [(set (match_dup 0)
11710 (unspec:TLSmode [(match_dup 1)]
11711 UNSPEC_TLSLD))
11712 (parallel [(set (match_dup 0)
11713 (call (mem:TLSmode (match_dup 2))
11714 (match_dup 3)))
11715 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11716 (clobber (reg:SI LR_REGNO))])]
11717 ""
11718 [(set_attr "length" "8")])
11720 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
11721 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11722 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11723 UNSPEC_TLSLD))]
11724 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11725 "addi %0,%1,%&@got@tlsld"
11726 "&& TARGET_CMODEL != CMODEL_SMALL"
11727 [(set (match_dup 2)
11728 (high:TLSmode
11729 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
11730 (set (match_dup 0)
11731 (lo_sum:TLSmode (match_dup 2)
11732 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
11733 "
11734 {
11735 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11736 }"
11737 [(set (attr "length")
11738 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11739 (const_int 8)
11740 (const_int 4)))])
11742 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
11743 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11744 (high:TLSmode
11745 (unspec:TLSmode [(const_int 0)
11746 (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11747 UNSPEC_TLSLD)))]
11748 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11749 "addis %0,%1,%&@got@tlsld@ha"
11750 [(set_attr "length" "4")])
11752 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
11753 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11754 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11755 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
11756 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11757 "addi %0,%1,%&@got@tlsld@l"
11758 [(set_attr "length" "4")])
11760 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
11761 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11762 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11763 (match_operand 2 "" "g")))
11764 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11765 (clobber (reg:SI LR_REGNO))]
11766 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11767 "bl %z1(%&@tlsld)\;%."
11768 [(set_attr "type" "branch")
11769 (set_attr "length" "8")])
11771 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
11772 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11773 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11774 (match_operand 2 "" "g")))
11775 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11776 (clobber (reg:SI LR_REGNO))]
11777 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11778 {
11779 if (flag_pic)
11780 {
11781 if (TARGET_SECURE_PLT && flag_pic == 2)
11782 return "bl %z1+32768(%&@tlsld)@plt";
11783 return "bl %z1(%&@tlsld)@plt";
11784 }
11785 return "bl %z1(%&@tlsld)";
11786 }
11787 [(set_attr "type" "branch")
11788 (set_attr "length" "4")])
11790 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
11791 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11792 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11793 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11794 UNSPEC_TLSDTPREL))]
11795 "HAVE_AS_TLS"
11796 "addi %0,%1,%2@dtprel")
11798 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
11799 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11800 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11801 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11802 UNSPEC_TLSDTPRELHA))]
11803 "HAVE_AS_TLS"
11804 "addis %0,%1,%2@dtprel@ha")
11806 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
11807 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11808 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11809 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11810 UNSPEC_TLSDTPRELLO))]
11811 "HAVE_AS_TLS"
11812 "addi %0,%1,%2@dtprel@l")
11814 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
11815 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11816 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11817 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11818 UNSPEC_TLSGOTDTPREL))]
11819 "HAVE_AS_TLS"
11820 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
11821 "&& TARGET_CMODEL != CMODEL_SMALL"
11822 [(set (match_dup 3)
11823 (high:TLSmode
11824 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
11825 (set (match_dup 0)
11826 (lo_sum:TLSmode (match_dup 3)
11827 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
11828 "
11829 {
11830 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11831 }"
11832 [(set (attr "length")
11833 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11834 (const_int 8)
11835 (const_int 4)))])
11837 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
11838 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11839 (high:TLSmode
11840 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11841 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11842 UNSPEC_TLSGOTDTPREL)))]
11843 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11844 "addis %0,%1,%2@got@dtprel@ha"
11845 [(set_attr "length" "4")])
11847 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
11848 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11849 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11850 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11851 UNSPEC_TLSGOTDTPREL)))]
11852 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11853 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
11854 [(set_attr "length" "4")])
11856 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
11857 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11858 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11859 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11860 UNSPEC_TLSTPREL))]
11861 "HAVE_AS_TLS"
11862 "addi %0,%1,%2@tprel")
11864 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
11865 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11866 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11867 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11868 UNSPEC_TLSTPRELHA))]
11869 "HAVE_AS_TLS"
11870 "addis %0,%1,%2@tprel@ha")
11872 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
11873 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11874 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11875 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11876 UNSPEC_TLSTPRELLO))]
11877 "HAVE_AS_TLS"
11878 "addi %0,%1,%2@tprel@l")
11880 ;; "b" output constraint here and on tls_tls input to support linker tls
11881 ;; optimization. The linker may edit the instructions emitted by a
11882 ;; tls_got_tprel/tls_tls pair to addis,addi.
11883 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
11884 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11885 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11886 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11887 UNSPEC_TLSGOTTPREL))]
11888 "HAVE_AS_TLS"
11889 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
11890 "&& TARGET_CMODEL != CMODEL_SMALL"
11891 [(set (match_dup 3)
11892 (high:TLSmode
11893 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
11894 (set (match_dup 0)
11895 (lo_sum:TLSmode (match_dup 3)
11896 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL)))]
11897 "
11898 {
11899 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11900 }"
11901 [(set (attr "length")
11902 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11903 (const_int 8)
11904 (const_int 4)))])
11906 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
11907 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11908 (high:TLSmode
11909 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11910 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11911 UNSPEC_TLSGOTTPREL)))]
11912 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11913 "addis %0,%1,%2@got@tprel@ha"
11914 [(set_attr "length" "4")])
11916 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
11917 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11918 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11919 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11920 UNSPEC_TLSGOTTPREL)))]
11921 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11922 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
11923 [(set_attr "length" "4")])
11925 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
11926 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11927 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11928 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11929 UNSPEC_TLSTLS))]
11930 "HAVE_AS_TLS"
11931 "add %0,%1,%2@tls")
11932 \f
11933 ;; Next come insns related to the calling sequence.
11934 ;;
11935 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
11936 ;; We move the back-chain and decrement the stack pointer.
11938 (define_expand "allocate_stack"
11939 [(set (match_operand 0 "gpc_reg_operand" "")
11940 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
11941 (set (reg 1)
11942 (minus (reg 1) (match_dup 1)))]
11943 ""
11944 "
11945 { rtx chain = gen_reg_rtx (Pmode);
11946 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
11947 rtx neg_op0;
11948 rtx insn, par, set, mem;
11950 emit_move_insn (chain, stack_bot);
11952 /* Check stack bounds if necessary. */
11953 if (crtl->limit_stack)
11954 {
11955 rtx available;
11956 available = expand_binop (Pmode, sub_optab,
11957 stack_pointer_rtx, stack_limit_rtx,
11958 NULL_RTX, 1, OPTAB_WIDEN);
11959 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
11960 }
11962 if (GET_CODE (operands[1]) != CONST_INT
11963 || INTVAL (operands[1]) < -32767
11964 || INTVAL (operands[1]) > 32768)
11965 {
11966 neg_op0 = gen_reg_rtx (Pmode);
11967 if (TARGET_32BIT)
11968 emit_insn (gen_negsi2 (neg_op0, operands[1]));
11969 else
11970 emit_insn (gen_negdi2 (neg_op0, operands[1]));
11971 }
11972 else
11973 neg_op0 = GEN_INT (- INTVAL (operands[1]));
11975 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
11976 : gen_movdi_di_update_stack))
11977 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
11978 chain));
11979 /* Since we didn't use gen_frame_mem to generate the MEM, grab
11980 it now and set the alias set/attributes. The above gen_*_update
11981 calls will generate a PARALLEL with the MEM set being the first
11982 operation. */
11983 par = PATTERN (insn);
11984 gcc_assert (GET_CODE (par) == PARALLEL);
11985 set = XVECEXP (par, 0, 0);
11986 gcc_assert (GET_CODE (set) == SET);
11987 mem = SET_DEST (set);
11988 gcc_assert (MEM_P (mem));
11989 MEM_NOTRAP_P (mem) = 1;
11990 set_mem_alias_set (mem, get_frame_alias_set ());
11992 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
11993 DONE;
11994 }")
11996 ;; These patterns say how to save and restore the stack pointer. We need not
11997 ;; save the stack pointer at function level since we are careful to
11998 ;; preserve the backchain. At block level, we have to restore the backchain
11999 ;; when we restore the stack pointer.
12000 ;;
12001 ;; For nonlocal gotos, we must save both the stack pointer and its
12002 ;; backchain and restore both. Note that in the nonlocal case, the
12003 ;; save area is a memory location.
12005 (define_expand "save_stack_function"
12006 [(match_operand 0 "any_operand" "")
12007 (match_operand 1 "any_operand" "")]
12008 ""
12009 "DONE;")
12011 (define_expand "restore_stack_function"
12012 [(match_operand 0 "any_operand" "")
12013 (match_operand 1 "any_operand" "")]
12014 ""
12015 "DONE;")
12017 ;; Adjust stack pointer (op0) to a new value (op1).
12018 ;; First copy old stack backchain to new location, and ensure that the
12019 ;; scheduler won't reorder the sp assignment before the backchain write.
12020 (define_expand "restore_stack_block"
12021 [(set (match_dup 2) (match_dup 3))
12022 (set (match_dup 4) (match_dup 2))
12023 (match_dup 5)
12024 (set (match_operand 0 "register_operand" "")
12025 (match_operand 1 "register_operand" ""))]
12026 ""
12027 "
12028 {
12029 rtvec p;
12031 operands[1] = force_reg (Pmode, operands[1]);
12032 operands[2] = gen_reg_rtx (Pmode);
12033 operands[3] = gen_frame_mem (Pmode, operands[0]);
12034 operands[4] = gen_frame_mem (Pmode, operands[1]);
12035 p = rtvec_alloc (1);
12036 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
12037 gen_frame_mem (BLKmode, operands[0]),
12038 const0_rtx);
12039 operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
12040 }")
12042 (define_expand "save_stack_nonlocal"
12043 [(set (match_dup 3) (match_dup 4))
12044 (set (match_operand 0 "memory_operand" "") (match_dup 3))
12045 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
12046 ""
12047 "
12048 {
12049 int units_per_word = (TARGET_32BIT) ? 4 : 8;
12051 /* Copy the backchain to the first word, sp to the second. */
12052 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
12053 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
12054 operands[3] = gen_reg_rtx (Pmode);
12055 operands[4] = gen_frame_mem (Pmode, operands[1]);
12056 }")
12058 (define_expand "restore_stack_nonlocal"
12059 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
12060 (set (match_dup 3) (match_dup 4))
12061 (set (match_dup 5) (match_dup 2))
12062 (match_dup 6)
12063 (set (match_operand 0 "register_operand" "") (match_dup 3))]
12064 ""
12065 "
12066 {
12067 int units_per_word = (TARGET_32BIT) ? 4 : 8;
12068 rtvec p;
12070 /* Restore the backchain from the first word, sp from the second. */
12071 operands[2] = gen_reg_rtx (Pmode);
12072 operands[3] = gen_reg_rtx (Pmode);
12073 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
12074 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
12075 operands[5] = gen_frame_mem (Pmode, operands[3]);
12076 p = rtvec_alloc (1);
12077 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
12078 gen_frame_mem (BLKmode, operands[0]),
12079 const0_rtx);
12080 operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
12081 }")
12082 \f
12083 ;; TOC register handling.
12085 ;; Code to initialize the TOC register...
12087 (define_insn "load_toc_aix_si"
12088 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12089 (unspec:SI [(const_int 0)] UNSPEC_TOC))
12090 (use (reg:SI 2))])]
12091 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
12092 "*
12093 {
12094 char buf[30];
12095 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
12096 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12097 operands[2] = gen_rtx_REG (Pmode, 2);
12098 return \"{l|lwz} %0,%1(%2)\";
12099 }"
12100 [(set_attr "type" "load")])
12102 (define_insn "load_toc_aix_di"
12103 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12104 (unspec:DI [(const_int 0)] UNSPEC_TOC))
12105 (use (reg:DI 2))])]
12106 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
12107 "*
12108 {
12109 char buf[30];
12110 #ifdef TARGET_RELOCATABLE
12111 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
12112 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
12113 #else
12114 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
12115 #endif
12116 if (TARGET_ELF)
12117 strcat (buf, \"@toc\");
12118 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12119 operands[2] = gen_rtx_REG (Pmode, 2);
12120 return \"ld %0,%1(%2)\";
12121 }"
12122 [(set_attr "type" "load")])
12124 (define_insn "load_toc_v4_pic_si"
12125 [(set (reg:SI LR_REGNO)
12126 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
12127 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
12128 "bl _GLOBAL_OFFSET_TABLE_@local-4"
12129 [(set_attr "type" "branch")
12130 (set_attr "length" "4")])
12132 (define_expand "load_toc_v4_PIC_1"
12133 [(parallel [(set (reg:SI LR_REGNO)
12134 (match_operand:SI 0 "immediate_operand" "s"))
12135 (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
12136 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
12137 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
12138 "")
12140 (define_insn "load_toc_v4_PIC_1_normal"
12141 [(set (reg:SI LR_REGNO)
12142 (match_operand:SI 0 "immediate_operand" "s"))
12143 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
12144 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX
12145 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
12146 "bcl 20,31,%0\\n%0:"
12147 [(set_attr "type" "branch")
12148 (set_attr "length" "4")])
12150 (define_insn "load_toc_v4_PIC_1_476"
12151 [(set (reg:SI LR_REGNO)
12152 (match_operand:SI 0 "immediate_operand" "s"))
12153 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
12154 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX
12155 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
12156 "*
12157 {
12158 char name[32];
12159 static char templ[32];
12161 get_ppc476_thunk_name (name);
12162 sprintf (templ, \"bl %s\\n%%0:\", name);
12163 return templ;
12164 }"
12165 [(set_attr "type" "branch")
12166 (set_attr "length" "4")])
12168 (define_expand "load_toc_v4_PIC_1b"
12169 [(parallel [(set (reg:SI LR_REGNO)
12170 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
12171 (label_ref (match_operand 1 "" ""))]
12172 UNSPEC_TOCPTR))
12173 (match_dup 1)])]
12174 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
12175 "")
12177 (define_insn "load_toc_v4_PIC_1b_normal"
12178 [(set (reg:SI LR_REGNO)
12179 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
12180 (label_ref (match_operand 1 "" ""))]
12181 UNSPEC_TOCPTR))
12182 (match_dup 1)]
12183 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
12184 "bcl 20,31,$+8\;.long %0-$"
12185 [(set_attr "type" "branch")
12186 (set_attr "length" "8")])
12188 (define_insn "load_toc_v4_PIC_1b_476"
12189 [(set (reg:SI LR_REGNO)
12190 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
12191 (label_ref (match_operand 1 "" ""))]
12192 UNSPEC_TOCPTR))
12193 (match_dup 1)]
12194 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
12195 "*
12196 {
12197 char name[32];
12198 static char templ[32];
12200 get_ppc476_thunk_name (name);
12201 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
12202 return templ;
12203 }"
12204 [(set_attr "type" "branch")
12205 (set_attr "length" "16")])
12207 (define_insn "load_toc_v4_PIC_2"
12208 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12209 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
12210 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
12211 (match_operand:SI 3 "immediate_operand" "s")))))]
12212 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
12213 "{l|lwz} %0,%2-%3(%1)"
12214 [(set_attr "type" "load")])
12216 (define_insn "load_toc_v4_PIC_3b"
12217 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12218 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
12219 (high:SI
12220 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
12221 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
12222 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
12223 "{cau|addis} %0,%1,%2-%3@ha")
12225 (define_insn "load_toc_v4_PIC_3c"
12226 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12227 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
12228 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
12229 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
12230 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
12231 "{cal %0,%2-%3@l(%1)|addi %0,%1,%2-%3@l}")
12233 ;; If the TOC is shared over a translation unit, as happens with all
12234 ;; the kinds of PIC that we support, we need to restore the TOC
12235 ;; pointer only when jumping over units of translation.
12236 ;; On Darwin, we need to reload the picbase.
12238 (define_expand "builtin_setjmp_receiver"
12239 [(use (label_ref (match_operand 0 "" "")))]
12240 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
12241 || (TARGET_TOC && TARGET_MINIMAL_TOC)
12242 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
12243 "
12244 {
12245 #if TARGET_MACHO
12246 if (DEFAULT_ABI == ABI_DARWIN)
12247 {
12248 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
12249 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
12250 rtx tmplabrtx;
12251 char tmplab[20];
12253 crtl->uses_pic_offset_table = 1;
12254 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
12255 CODE_LABEL_NUMBER (operands[0]));
12256 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
12258 emit_insn (gen_load_macho_picbase (tmplabrtx));
12259 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
12260 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
12261 }
12262 else
12263 #endif
12264 rs6000_emit_load_toc_table (FALSE);
12265 DONE;
12266 }")
12268 ;; Largetoc support
12269 (define_insn "*largetoc_high"
12270 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
12271 (high:DI
12272 (unspec [(match_operand:DI 1 "" "")
12273 (match_operand:DI 2 "gpc_reg_operand" "b")]
12274 UNSPEC_TOCREL)))]
12275 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
12276 "{cau|addis} %0,%2,%1@toc@ha")
12278 (define_insn "*largetoc_high_plus"
12279 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
12280 (high:DI
12281 (plus:DI
12282 (unspec [(match_operand:DI 1 "" "")
12283 (match_operand:DI 2 "gpc_reg_operand" "b")]
12284 UNSPEC_TOCREL)
12285 (match_operand 3 "const_int_operand" "n"))))]
12286 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
12287 "{cau|addis} %0,%2,%1+%3@toc@ha")
12289 (define_insn "*largetoc_low"
12290 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12291 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
12292 (match_operand:DI 2 "" "")))]
12293 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
12294 "@
12295 {cal %0,%2@l(%1)|addi %0,%1,%2@l}
12296 {ai|addic} %0,%1,%2@l")
12298 (define_insn_and_split "*tocref<mode>"
12299 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
12300 (match_operand:P 1 "small_toc_ref" "R"))]
12301 "TARGET_TOC"
12302 "{cal|la} %0,%a1"
12303 "&& TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL && reload_completed"
12304 [(set (match_dup 0) (high:P (match_dup 1)))
12305 (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))])
12307 ;; Elf specific ways of loading addresses for non-PIC code.
12308 ;; The output of this could be r0, but we make a very strong
12309 ;; preference for a base register because it will usually
12310 ;; be needed there.
12311 (define_insn "elf_high"
12312 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
12313 (high:SI (match_operand 1 "" "")))]
12314 "TARGET_ELF && ! TARGET_64BIT"
12315 "{liu|lis} %0,%1@ha")
12317 (define_insn "elf_low"
12318 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12319 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
12320 (match_operand 2 "" "")))]
12321 "TARGET_ELF && ! TARGET_64BIT"
12322 "@
12323 {cal|la} %0,%2@l(%1)
12324 {ai|addic} %0,%1,%K2")
12325 \f
12326 ;; Call and call_value insns
12327 (define_expand "call"
12328 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12329 (match_operand 1 "" ""))
12330 (use (match_operand 2 "" ""))
12331 (clobber (reg:SI LR_REGNO))])]
12332 ""
12333 "
12334 {
12335 #if TARGET_MACHO
12336 if (MACHOPIC_INDIRECT)
12337 operands[0] = machopic_indirect_call_target (operands[0]);
12338 #endif
12340 gcc_assert (GET_CODE (operands[0]) == MEM);
12341 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12343 operands[0] = XEXP (operands[0], 0);
12345 if (GET_CODE (operands[0]) != SYMBOL_REF
12346 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
12347 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
12348 {
12349 if (INTVAL (operands[2]) & CALL_LONG)
12350 operands[0] = rs6000_longcall_ref (operands[0]);
12352 switch (DEFAULT_ABI)
12353 {
12354 case ABI_V4:
12355 case ABI_DARWIN:
12356 operands[0] = force_reg (Pmode, operands[0]);
12357 break;
12359 case ABI_AIX:
12360 /* AIX function pointers are really pointers to a three word
12361 area. */
12362 rs6000_call_indirect_aix (NULL_RTX, operands[0], operands[1]);
12363 DONE;
12365 default:
12366 gcc_unreachable ();
12367 }
12368 }
12369 }")
12371 (define_expand "call_value"
12372 [(parallel [(set (match_operand 0 "" "")
12373 (call (mem:SI (match_operand 1 "address_operand" ""))
12374 (match_operand 2 "" "")))
12375 (use (match_operand 3 "" ""))
12376 (clobber (reg:SI LR_REGNO))])]
12377 ""
12378 "
12379 {
12380 #if TARGET_MACHO
12381 if (MACHOPIC_INDIRECT)
12382 operands[1] = machopic_indirect_call_target (operands[1]);
12383 #endif
12385 gcc_assert (GET_CODE (operands[1]) == MEM);
12386 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12388 operands[1] = XEXP (operands[1], 0);
12390 if (GET_CODE (operands[1]) != SYMBOL_REF
12391 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
12392 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
12393 {
12394 if (INTVAL (operands[3]) & CALL_LONG)
12395 operands[1] = rs6000_longcall_ref (operands[1]);
12397 switch (DEFAULT_ABI)
12398 {
12399 case ABI_V4:
12400 case ABI_DARWIN:
12401 operands[1] = force_reg (Pmode, operands[1]);
12402 break;
12404 case ABI_AIX:
12405 /* AIX function pointers are really pointers to a three word
12406 area. */
12407 rs6000_call_indirect_aix (operands[0], operands[1], operands[2]);
12408 DONE;
12410 default:
12411 gcc_unreachable ();
12412 }
12413 }
12414 }")
12416 ;; Call to function in current module. No TOC pointer reload needed.
12417 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
12418 ;; either the function was not prototyped, or it was prototyped as a
12419 ;; variable argument function. It is > 0 if FP registers were passed
12420 ;; and < 0 if they were not.
12422 (define_insn "*call_local32"
12423 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12424 (match_operand 1 "" "g,g"))
12425 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12426 (clobber (reg:SI LR_REGNO))]
12427 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12428 "*
12429 {
12430 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12431 output_asm_insn (\"crxor 6,6,6\", operands);
12433 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12434 output_asm_insn (\"creqv 6,6,6\", operands);
12436 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
12437 }"
12438 [(set_attr "type" "branch")
12439 (set_attr "length" "4,8")])
12441 (define_insn "*call_local64"
12442 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12443 (match_operand 1 "" "g,g"))
12444 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12445 (clobber (reg:SI LR_REGNO))]
12446 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12447 "*
12448 {
12449 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12450 output_asm_insn (\"crxor 6,6,6\", operands);
12452 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12453 output_asm_insn (\"creqv 6,6,6\", operands);
12455 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
12456 }"
12457 [(set_attr "type" "branch")
12458 (set_attr "length" "4,8")])
12460 (define_insn "*call_value_local32"
12461 [(set (match_operand 0 "" "")
12462 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12463 (match_operand 2 "" "g,g")))
12464 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12465 (clobber (reg:SI LR_REGNO))]
12466 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12467 "*
12468 {
12469 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12470 output_asm_insn (\"crxor 6,6,6\", operands);
12472 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12473 output_asm_insn (\"creqv 6,6,6\", operands);
12475 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
12476 }"
12477 [(set_attr "type" "branch")
12478 (set_attr "length" "4,8")])
12481 (define_insn "*call_value_local64"
12482 [(set (match_operand 0 "" "")
12483 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12484 (match_operand 2 "" "g,g")))
12485 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12486 (clobber (reg:SI LR_REGNO))]
12487 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12488 "*
12489 {
12490 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12491 output_asm_insn (\"crxor 6,6,6\", operands);
12493 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12494 output_asm_insn (\"creqv 6,6,6\", operands);
12496 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
12497 }"
12498 [(set_attr "type" "branch")
12499 (set_attr "length" "4,8")])
12501 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
12502 ;; Operand0 is the addresss of the function to call
12503 ;; Operand1 is the flag for System V.4 for unprototyped or FP registers
12504 ;; Operand2 is the location in the function descriptor to load r2 from
12505 ;; Operand3 is the stack location to hold the current TOC pointer
12507 (define_insn "call_indirect_aix<ptrsize>"
12508 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
12509 (match_operand 1 "" "g,g"))
12510 (use (match_operand:P 2 "memory_operand" "m,m"))
12511 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "m,m"))
12512 (use (reg:P STATIC_CHAIN_REGNUM))
12513 (clobber (reg:P LR_REGNO))]
12514 "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
12515 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
12516 [(set_attr "type" "jmpreg")
12517 (set_attr "length" "12")])
12519 ;; Like call_indirect_aix<ptrsize>, but no use of the static chain
12520 ;; Operand0 is the addresss of the function to call
12521 ;; Operand1 is the flag for System V.4 for unprototyped or FP registers
12522 ;; Operand2 is the location in the function descriptor to load r2 from
12523 ;; Operand3 is the stack location to hold the current TOC pointer
12525 (define_insn "call_indirect_aix<ptrsize>_nor11"
12526 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
12527 (match_operand 1 "" "g,g"))
12528 (use (match_operand:P 2 "memory_operand" "m,m"))
12529 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "m,m"))
12530 (clobber (reg:P LR_REGNO))]
12531 "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
12532 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
12533 [(set_attr "type" "jmpreg")
12534 (set_attr "length" "12")])
12536 ;; Operand0 is the return result of the function
12537 ;; Operand1 is the addresss of the function to call
12538 ;; Operand2 is the flag for System V.4 for unprototyped or FP registers
12539 ;; Operand3 is the location in the function descriptor to load r2 from
12540 ;; Operand4 is the stack location to hold the current TOC pointer
12542 (define_insn "call_value_indirect_aix<ptrsize>"
12543 [(set (match_operand 0 "" "")
12544 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
12545 (match_operand 2 "" "g,g")))
12546 (use (match_operand:P 3 "memory_operand" "m,m"))
12547 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "m,m"))
12548 (use (reg:P STATIC_CHAIN_REGNUM))
12549 (clobber (reg:P LR_REGNO))]
12550 "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
12551 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
12552 [(set_attr "type" "jmpreg")
12553 (set_attr "length" "12")])
12555 ;; Like call_value_indirect_aix<ptrsize>, but no use of the static chain
12556 ;; Operand0 is the return result of the function
12557 ;; Operand1 is the addresss of the function to call
12558 ;; Operand2 is the flag for System V.4 for unprototyped or FP registers
12559 ;; Operand3 is the location in the function descriptor to load r2 from
12560 ;; Operand4 is the stack location to hold the current TOC pointer
12562 (define_insn "call_value_indirect_aix<ptrsize>_nor11"
12563 [(set (match_operand 0 "" "")
12564 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
12565 (match_operand 2 "" "g,g")))
12566 (use (match_operand:P 3 "memory_operand" "m,m"))
12567 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "m,m"))
12568 (clobber (reg:P LR_REGNO))]
12569 "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
12570 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
12571 [(set_attr "type" "jmpreg")
12572 (set_attr "length" "12")])
12574 ;; Call to function which may be in another module. Restore the TOC
12575 ;; pointer (r2) after the call unless this is System V.
12576 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
12577 ;; either the function was not prototyped, or it was prototyped as a
12578 ;; variable argument function. It is > 0 if FP registers were passed
12579 ;; and < 0 if they were not.
12581 (define_insn "*call_nonlocal_aix32"
12582 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
12583 (match_operand 1 "" "g"))
12584 (use (match_operand:SI 2 "immediate_operand" "O"))
12585 (clobber (reg:SI LR_REGNO))]
12586 "TARGET_32BIT
12587 && DEFAULT_ABI == ABI_AIX
12588 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12589 "bl %z0\;%."
12590 [(set_attr "type" "branch")
12591 (set_attr "length" "8")])
12593 (define_insn "*call_nonlocal_aix64"
12594 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
12595 (match_operand 1 "" "g"))
12596 (use (match_operand:SI 2 "immediate_operand" "O"))
12597 (clobber (reg:SI LR_REGNO))]
12598 "TARGET_64BIT
12599 && DEFAULT_ABI == ABI_AIX
12600 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12601 "bl %z0\;%."
12602 [(set_attr "type" "branch")
12603 (set_attr "length" "8")])
12605 (define_insn "*call_value_nonlocal_aix32"
12606 [(set (match_operand 0 "" "")
12607 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
12608 (match_operand 2 "" "g")))
12609 (use (match_operand:SI 3 "immediate_operand" "O"))
12610 (clobber (reg:SI LR_REGNO))]
12611 "TARGET_32BIT
12612 && DEFAULT_ABI == ABI_AIX
12613 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12614 "bl %z1\;%."
12615 [(set_attr "type" "branch")
12616 (set_attr "length" "8")])
12618 (define_insn "*call_value_nonlocal_aix64"
12619 [(set (match_operand 0 "" "")
12620 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
12621 (match_operand 2 "" "g")))
12622 (use (match_operand:SI 3 "immediate_operand" "O"))
12623 (clobber (reg:SI LR_REGNO))]
12624 "TARGET_64BIT
12625 && DEFAULT_ABI == ABI_AIX
12626 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12627 "bl %z1\;%."
12628 [(set_attr "type" "branch")
12629 (set_attr "length" "8")])
12631 ;; A function pointer under System V is just a normal pointer
12632 ;; operands[0] is the function pointer
12633 ;; operands[1] is the stack size to clean up
12634 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
12635 ;; which indicates how to set cr1
12637 (define_insn "*call_indirect_nonlocal_sysv<mode>"
12638 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
12639 (match_operand 1 "" "g,g,g,g"))
12640 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
12641 (clobber (reg:SI LR_REGNO))]
12642 "DEFAULT_ABI == ABI_V4
12643 || DEFAULT_ABI == ABI_DARWIN"
12644 {
12645 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12646 output_asm_insn ("crxor 6,6,6", operands);
12648 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12649 output_asm_insn ("creqv 6,6,6", operands);
12651 return "b%T0l";
12652 }
12653 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12654 (set_attr "length" "4,4,8,8")])
12656 (define_insn_and_split "*call_nonlocal_sysv<mode>"
12657 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12658 (match_operand 1 "" "g,g"))
12659 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12660 (clobber (reg:SI LR_REGNO))]
12661 "(DEFAULT_ABI == ABI_DARWIN
12662 || (DEFAULT_ABI == ABI_V4
12663 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
12664 {
12665 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12666 output_asm_insn ("crxor 6,6,6", operands);
12668 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12669 output_asm_insn ("creqv 6,6,6", operands);
12671 #if TARGET_MACHO
12672 return output_call(insn, operands, 0, 2);
12673 #else
12674 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12675 {
12676 gcc_assert (!TARGET_SECURE_PLT);
12677 return "bl %z0@plt";
12678 }
12679 else
12680 return "bl %z0";
12681 #endif
12682 }
12683 "DEFAULT_ABI == ABI_V4
12684 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12685 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12686 [(parallel [(call (mem:SI (match_dup 0))
12687 (match_dup 1))
12688 (use (match_dup 2))
12689 (use (match_dup 3))
12690 (clobber (reg:SI LR_REGNO))])]
12691 {
12692 operands[3] = pic_offset_table_rtx;
12693 }
12694 [(set_attr "type" "branch,branch")
12695 (set_attr "length" "4,8")])
12697 (define_insn "*call_nonlocal_sysv_secure<mode>"
12698 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12699 (match_operand 1 "" "g,g"))
12700 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12701 (use (match_operand:SI 3 "register_operand" "r,r"))
12702 (clobber (reg:SI LR_REGNO))]
12703 "(DEFAULT_ABI == ABI_V4
12704 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12705 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
12706 {
12707 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12708 output_asm_insn ("crxor 6,6,6", operands);
12710 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12711 output_asm_insn ("creqv 6,6,6", operands);
12713 if (flag_pic == 2)
12714 /* The magic 32768 offset here and in the other sysv call insns
12715 corresponds to the offset of r30 in .got2, as given by LCTOC1.
12716 See sysv4.h:toc_section. */
12717 return "bl %z0+32768@plt";
12718 else
12719 return "bl %z0@plt";
12720 }
12721 [(set_attr "type" "branch,branch")
12722 (set_attr "length" "4,8")])
12724 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
12725 [(set (match_operand 0 "" "")
12726 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
12727 (match_operand 2 "" "g,g,g,g")))
12728 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
12729 (clobber (reg:SI LR_REGNO))]
12730 "DEFAULT_ABI == ABI_V4
12731 || DEFAULT_ABI == ABI_DARWIN"
12732 {
12733 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12734 output_asm_insn ("crxor 6,6,6", operands);
12736 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12737 output_asm_insn ("creqv 6,6,6", operands);
12739 return "b%T1l";
12740 }
12741 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12742 (set_attr "length" "4,4,8,8")])
12744 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
12745 [(set (match_operand 0 "" "")
12746 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12747 (match_operand 2 "" "g,g")))
12748 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12749 (clobber (reg:SI LR_REGNO))]
12750 "(DEFAULT_ABI == ABI_DARWIN
12751 || (DEFAULT_ABI == ABI_V4
12752 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
12753 {
12754 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12755 output_asm_insn ("crxor 6,6,6", operands);
12757 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12758 output_asm_insn ("creqv 6,6,6", operands);
12760 #if TARGET_MACHO
12761 return output_call(insn, operands, 1, 3);
12762 #else
12763 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12764 {
12765 gcc_assert (!TARGET_SECURE_PLT);
12766 return "bl %z1@plt";
12767 }
12768 else
12769 return "bl %z1";
12770 #endif
12771 }
12772 "DEFAULT_ABI == ABI_V4
12773 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12774 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12775 [(parallel [(set (match_dup 0)
12776 (call (mem:SI (match_dup 1))
12777 (match_dup 2)))
12778 (use (match_dup 3))
12779 (use (match_dup 4))
12780 (clobber (reg:SI LR_REGNO))])]
12781 {
12782 operands[4] = pic_offset_table_rtx;
12783 }
12784 [(set_attr "type" "branch,branch")
12785 (set_attr "length" "4,8")])
12787 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
12788 [(set (match_operand 0 "" "")
12789 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12790 (match_operand 2 "" "g,g")))
12791 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12792 (use (match_operand:SI 4 "register_operand" "r,r"))
12793 (clobber (reg:SI LR_REGNO))]
12794 "(DEFAULT_ABI == ABI_V4
12795 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12796 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
12797 {
12798 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12799 output_asm_insn ("crxor 6,6,6", operands);
12801 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12802 output_asm_insn ("creqv 6,6,6", operands);
12804 if (flag_pic == 2)
12805 return "bl %z1+32768@plt";
12806 else
12807 return "bl %z1@plt";
12808 }
12809 [(set_attr "type" "branch,branch")
12810 (set_attr "length" "4,8")])
12812 ;; Call subroutine returning any type.
12813 (define_expand "untyped_call"
12814 [(parallel [(call (match_operand 0 "" "")
12815 (const_int 0))
12816 (match_operand 1 "" "")
12817 (match_operand 2 "" "")])]
12818 ""
12819 "
12820 {
12821 int i;
12823 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
12825 for (i = 0; i < XVECLEN (operands[2], 0); i++)
12826 {
12827 rtx set = XVECEXP (operands[2], 0, i);
12828 emit_move_insn (SET_DEST (set), SET_SRC (set));
12829 }
12831 /* The optimizer does not know that the call sets the function value
12832 registers we stored in the result block. We avoid problems by
12833 claiming that all hard registers are used and clobbered at this
12834 point. */
12835 emit_insn (gen_blockage ());
12837 DONE;
12838 }")
12840 ;; sibling call patterns
12841 (define_expand "sibcall"
12842 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12843 (match_operand 1 "" ""))
12844 (use (match_operand 2 "" ""))
12845 (use (reg:SI LR_REGNO))
12846 (simple_return)])]
12847 ""
12848 "
12849 {
12850 #if TARGET_MACHO
12851 if (MACHOPIC_INDIRECT)
12852 operands[0] = machopic_indirect_call_target (operands[0]);
12853 #endif
12855 gcc_assert (GET_CODE (operands[0]) == MEM);
12856 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12858 operands[0] = XEXP (operands[0], 0);
12859 }")
12861 ;; this and similar patterns must be marked as using LR, otherwise
12862 ;; dataflow will try to delete the store into it. This is true
12863 ;; even when the actual reg to jump to is in CTR, when LR was
12864 ;; saved and restored around the PIC-setting BCL.
12865 (define_insn "*sibcall_local32"
12866 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12867 (match_operand 1 "" "g,g"))
12868 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12869 (use (reg:SI LR_REGNO))
12870 (simple_return)]
12871 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12872 "*
12873 {
12874 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12875 output_asm_insn (\"crxor 6,6,6\", operands);
12877 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12878 output_asm_insn (\"creqv 6,6,6\", operands);
12880 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12881 }"
12882 [(set_attr "type" "branch")
12883 (set_attr "length" "4,8")])
12885 (define_insn "*sibcall_local64"
12886 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12887 (match_operand 1 "" "g,g"))
12888 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12889 (use (reg:SI LR_REGNO))
12890 (simple_return)]
12891 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12892 "*
12893 {
12894 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12895 output_asm_insn (\"crxor 6,6,6\", operands);
12897 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12898 output_asm_insn (\"creqv 6,6,6\", operands);
12900 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12901 }"
12902 [(set_attr "type" "branch")
12903 (set_attr "length" "4,8")])
12905 (define_insn "*sibcall_value_local32"
12906 [(set (match_operand 0 "" "")
12907 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12908 (match_operand 2 "" "g,g")))
12909 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12910 (use (reg:SI LR_REGNO))
12911 (simple_return)]
12912 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12913 "*
12914 {
12915 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12916 output_asm_insn (\"crxor 6,6,6\", operands);
12918 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12919 output_asm_insn (\"creqv 6,6,6\", operands);
12921 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12922 }"
12923 [(set_attr "type" "branch")
12924 (set_attr "length" "4,8")])
12927 (define_insn "*sibcall_value_local64"
12928 [(set (match_operand 0 "" "")
12929 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12930 (match_operand 2 "" "g,g")))
12931 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12932 (use (reg:SI LR_REGNO))
12933 (simple_return)]
12934 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12935 "*
12936 {
12937 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12938 output_asm_insn (\"crxor 6,6,6\", operands);
12940 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12941 output_asm_insn (\"creqv 6,6,6\", operands);
12943 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12944 }"
12945 [(set_attr "type" "branch")
12946 (set_attr "length" "4,8")])
12948 (define_insn "*sibcall_nonlocal_aix<mode>"
12949 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
12950 (match_operand 1 "" "g,g"))
12951 (use (match_operand:SI 2 "immediate_operand" "O,O"))
12952 (use (reg:SI LR_REGNO))
12953 (simple_return)]
12954 "DEFAULT_ABI == ABI_AIX
12955 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12956 "@
12957 b %z0
12958 b%T0"
12959 [(set_attr "type" "branch")
12960 (set_attr "length" "4")])
12962 (define_insn "*sibcall_value_nonlocal_aix<mode>"
12963 [(set (match_operand 0 "" "")
12964 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
12965 (match_operand 2 "" "g,g")))
12966 (use (match_operand:SI 3 "immediate_operand" "O,O"))
12967 (use (reg:SI LR_REGNO))
12968 (simple_return)]
12969 "DEFAULT_ABI == ABI_AIX
12970 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12971 "@
12972 b %z1
12973 b%T1"
12974 [(set_attr "type" "branch")
12975 (set_attr "length" "4")])
12977 (define_insn "*sibcall_nonlocal_sysv<mode>"
12978 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
12979 (match_operand 1 "" ""))
12980 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
12981 (use (reg:SI LR_REGNO))
12982 (simple_return)]
12983 "(DEFAULT_ABI == ABI_DARWIN
12984 || DEFAULT_ABI == ABI_V4)
12985 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12986 "*
12987 {
12988 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12989 output_asm_insn (\"crxor 6,6,6\", operands);
12991 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12992 output_asm_insn (\"creqv 6,6,6\", operands);
12994 if (which_alternative >= 2)
12995 return \"b%T0\";
12996 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
12997 {
12998 gcc_assert (!TARGET_SECURE_PLT);
12999 return \"b %z0@plt\";
13000 }
13001 else
13002 return \"b %z0\";
13003 }"
13004 [(set_attr "type" "branch")
13005 (set_attr "length" "4,8,4,8")])
13007 (define_expand "sibcall_value"
13008 [(parallel [(set (match_operand 0 "register_operand" "")
13009 (call (mem:SI (match_operand 1 "address_operand" ""))
13010 (match_operand 2 "" "")))
13011 (use (match_operand 3 "" ""))
13012 (use (reg:SI LR_REGNO))
13013 (simple_return)])]
13014 ""
13015 "
13016 {
13017 #if TARGET_MACHO
13018 if (MACHOPIC_INDIRECT)
13019 operands[1] = machopic_indirect_call_target (operands[1]);
13020 #endif
13022 gcc_assert (GET_CODE (operands[1]) == MEM);
13023 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
13025 operands[1] = XEXP (operands[1], 0);
13026 }")
13028 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
13029 [(set (match_operand 0 "" "")
13030 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
13031 (match_operand 2 "" "")))
13032 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
13033 (use (reg:SI LR_REGNO))
13034 (simple_return)]
13035 "(DEFAULT_ABI == ABI_DARWIN
13036 || DEFAULT_ABI == ABI_V4)
13037 && (INTVAL (operands[3]) & CALL_LONG) == 0"
13038 "*
13039 {
13040 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
13041 output_asm_insn (\"crxor 6,6,6\", operands);
13043 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
13044 output_asm_insn (\"creqv 6,6,6\", operands);
13046 if (which_alternative >= 2)
13047 return \"b%T1\";
13048 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
13049 {
13050 gcc_assert (!TARGET_SECURE_PLT);
13051 return \"b %z1@plt\";
13052 }
13053 else
13054 return \"b %z1\";
13055 }"
13056 [(set_attr "type" "branch")
13057 (set_attr "length" "4,8,4,8")])
13059 (define_expand "sibcall_epilogue"
13060 [(use (const_int 0))]
13061 ""
13062 {
13063 if (!TARGET_SCHED_PROLOG)
13064 emit_insn (gen_blockage ());
13065 rs6000_emit_epilogue (TRUE);
13066 DONE;
13067 })
13069 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
13070 ;; all of memory. This blocks insns from being moved across this point.
13072 (define_insn "blockage"
13073 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
13074 ""
13075 "")
13077 (define_insn "probe_stack"
13078 [(set (match_operand 0 "memory_operand" "=m")
13079 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
13080 ""
13081 "*
13082 {
13083 operands[1] = gen_rtx_REG (Pmode, 0);
13084 return \"{st%U0%X0|stw%U0%X0} %1,%0\";
13085 }"
13086 [(set_attr "type" "store")
13087 (set_attr "length" "4")])
13089 (define_insn "probe_stack_range<P:mode>"
13090 [(set (match_operand:P 0 "register_operand" "=r")
13091 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
13092 (match_operand:P 2 "register_operand" "r")]
13093 UNSPECV_PROBE_STACK_RANGE))]
13094 ""
13095 "* return output_probe_stack_range (operands[0], operands[2]);"
13096 [(set_attr "type" "three")])
13097 \f
13098 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
13099 ;; signed & unsigned, and one type of branch.
13100 ;;
13101 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
13102 ;; insns, and branches.
13104 (define_expand "cbranch<mode>4"
13105 [(use (match_operator 0 "rs6000_cbranch_operator"
13106 [(match_operand:GPR 1 "gpc_reg_operand" "")
13107 (match_operand:GPR 2 "reg_or_short_operand" "")]))
13108 (use (match_operand 3 ""))]
13109 ""
13110 "
13111 {
13112 /* Take care of the possibility that operands[2] might be negative but
13113 this might be a logical operation. That insn doesn't exist. */
13114 if (GET_CODE (operands[2]) == CONST_INT
13115 && INTVAL (operands[2]) < 0)
13116 {
13117 operands[2] = force_reg (<MODE>mode, operands[2]);
13118 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
13119 GET_MODE (operands[0]),
13120 operands[1], operands[2]);
13121 }
13123 rs6000_emit_cbranch (<MODE>mode, operands);
13124 DONE;
13125 }")
13127 (define_expand "cbranch<mode>4"
13128 [(use (match_operator 0 "rs6000_cbranch_operator"
13129 [(match_operand:FP 1 "gpc_reg_operand" "")
13130 (match_operand:FP 2 "gpc_reg_operand" "")]))
13131 (use (match_operand 3 ""))]
13132 ""
13133 "
13134 {
13135 rs6000_emit_cbranch (<MODE>mode, operands);
13136 DONE;
13137 }")
13139 (define_expand "cstore<mode>4"
13140 [(use (match_operator 1 "rs6000_cbranch_operator"
13141 [(match_operand:GPR 2 "gpc_reg_operand" "")
13142 (match_operand:GPR 3 "reg_or_short_operand" "")]))
13143 (clobber (match_operand:SI 0 "register_operand"))]
13144 ""
13145 "
13146 {
13147 /* Take care of the possibility that operands[3] might be negative but
13148 this might be a logical operation. That insn doesn't exist. */
13149 if (GET_CODE (operands[3]) == CONST_INT
13150 && INTVAL (operands[3]) < 0)
13151 {
13152 operands[3] = force_reg (<MODE>mode, operands[3]);
13153 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
13154 GET_MODE (operands[1]),
13155 operands[2], operands[3]);
13156 }
13158 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
13159 For SEQ, likewise, except that comparisons with zero should be done
13160 with an scc insns. However, due to the order that combine see the
13161 resulting insns, we must, in fact, allow SEQ for integers. Fail in
13162 the cases we don't want to handle or are best handled by portable
13163 code. */
13164 if (GET_CODE (operands[1]) == NE)
13165 FAIL;
13166 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
13167 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
13168 && operands[3] == const0_rtx)
13169 FAIL;
13170 rs6000_emit_sCOND (<MODE>mode, operands);
13171 DONE;
13172 }")
13174 (define_expand "cstore<mode>4"
13175 [(use (match_operator 1 "rs6000_cbranch_operator"
13176 [(match_operand:FP 2 "gpc_reg_operand" "")
13177 (match_operand:FP 3 "gpc_reg_operand" "")]))
13178 (clobber (match_operand:SI 0 "register_operand"))]
13179 ""
13180 "
13181 {
13182 rs6000_emit_sCOND (<MODE>mode, operands);
13183 DONE;
13184 }")
13187 (define_expand "stack_protect_set"
13188 [(match_operand 0 "memory_operand" "")
13189 (match_operand 1 "memory_operand" "")]
13190 ""
13191 {
13192 #ifdef TARGET_THREAD_SSP_OFFSET
13193 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
13194 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
13195 operands[1] = gen_rtx_MEM (Pmode, addr);
13196 #endif
13197 if (TARGET_64BIT)
13198 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
13199 else
13200 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
13201 DONE;
13202 })
13204 (define_insn "stack_protect_setsi"
13205 [(set (match_operand:SI 0 "memory_operand" "=m")
13206 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
13207 (set (match_scratch:SI 2 "=&r") (const_int 0))]
13208 "TARGET_32BIT"
13209 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
13210 [(set_attr "type" "three")
13211 (set_attr "length" "12")])
13213 (define_insn "stack_protect_setdi"
13214 [(set (match_operand:DI 0 "memory_operand" "=Y")
13215 (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
13216 (set (match_scratch:DI 2 "=&r") (const_int 0))]
13217 "TARGET_64BIT"
13218 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
13219 [(set_attr "type" "three")
13220 (set_attr "length" "12")])
13222 (define_expand "stack_protect_test"
13223 [(match_operand 0 "memory_operand" "")
13224 (match_operand 1 "memory_operand" "")
13225 (match_operand 2 "" "")]
13226 ""
13227 {
13228 rtx test, op0, op1;
13229 #ifdef TARGET_THREAD_SSP_OFFSET
13230 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
13231 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
13232 operands[1] = gen_rtx_MEM (Pmode, addr);
13233 #endif
13234 op0 = operands[0];
13235 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
13236 test = gen_rtx_EQ (VOIDmode, op0, op1);
13237 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
13238 DONE;
13239 })
13241 (define_insn "stack_protect_testsi"
13242 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
13243 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
13244 (match_operand:SI 2 "memory_operand" "m,m")]
13245 UNSPEC_SP_TEST))
13246 (set (match_scratch:SI 4 "=r,r") (const_int 0))
13247 (clobber (match_scratch:SI 3 "=&r,&r"))]
13248 "TARGET_32BIT"
13249 "@
13250 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
13251 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
13252 [(set_attr "length" "16,20")])
13254 (define_insn "stack_protect_testdi"
13255 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
13256 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
13257 (match_operand:DI 2 "memory_operand" "Y,Y")]
13258 UNSPEC_SP_TEST))
13259 (set (match_scratch:DI 4 "=r,r") (const_int 0))
13260 (clobber (match_scratch:DI 3 "=&r,&r"))]
13261 "TARGET_64BIT"
13262 "@
13263 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
13264 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
13265 [(set_attr "length" "16,20")])
13267 \f
13268 ;; Here are the actual compare insns.
13269 (define_insn "*cmp<mode>_internal1"
13270 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13271 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
13272 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
13273 ""
13274 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
13275 [(set_attr "type" "cmp")])
13277 ;; If we are comparing a register for equality with a large constant,
13278 ;; we can do this with an XOR followed by a compare. But this is profitable
13279 ;; only if the large constant is only used for the comparison (and in this
13280 ;; case we already have a register to reuse as scratch).
13281 ;;
13282 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
13283 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
13285 (define_peephole2
13286 [(set (match_operand:SI 0 "register_operand")
13287 (match_operand:SI 1 "logical_const_operand" ""))
13288 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
13289 [(match_dup 0)
13290 (match_operand:SI 2 "logical_const_operand" "")]))
13291 (set (match_operand:CC 4 "cc_reg_operand" "")
13292 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
13293 (match_dup 0)))
13294 (set (pc)
13295 (if_then_else (match_operator 6 "equality_operator"
13296 [(match_dup 4) (const_int 0)])
13297 (match_operand 7 "" "")
13298 (match_operand 8 "" "")))]
13299 "peep2_reg_dead_p (3, operands[0])
13300 && peep2_reg_dead_p (4, operands[4])"
13301 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
13302 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
13303 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
13305 {
13306 /* Get the constant we are comparing against, and see what it looks like
13307 when sign-extended from 16 to 32 bits. Then see what constant we could
13308 XOR with SEXTC to get the sign-extended value. */
13309 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
13310 SImode,
13311 operands[1], operands[2]);
13312 HOST_WIDE_INT c = INTVAL (cnst);
13313 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
13314 HOST_WIDE_INT xorv = c ^ sextc;
13316 operands[9] = GEN_INT (xorv);
13317 operands[10] = GEN_INT (sextc);
13318 })
13320 (define_insn "*cmpsi_internal2"
13321 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
13322 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
13323 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
13324 ""
13325 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
13326 [(set_attr "type" "cmp")])
13328 (define_insn "*cmpdi_internal2"
13329 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
13330 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
13331 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
13332 ""
13333 "cmpld%I2 %0,%1,%b2"
13334 [(set_attr "type" "cmp")])
13336 ;; The following two insns don't exist as single insns, but if we provide
13337 ;; them, we can swap an add and compare, which will enable us to overlap more
13338 ;; of the required delay between a compare and branch. We generate code for
13339 ;; them by splitting.
13341 (define_insn ""
13342 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13343 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
13344 (match_operand:SI 2 "short_cint_operand" "i")))
13345 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
13346 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
13347 ""
13348 "#"
13349 [(set_attr "length" "8")])
13351 (define_insn ""
13352 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
13353 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
13354 (match_operand:SI 2 "u_short_cint_operand" "i")))
13355 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
13356 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
13357 ""
13358 "#"
13359 [(set_attr "length" "8")])
13361 (define_split
13362 [(set (match_operand:CC 3 "cc_reg_operand" "")
13363 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
13364 (match_operand:SI 2 "short_cint_operand" "")))
13365 (set (match_operand:SI 0 "gpc_reg_operand" "")
13366 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
13367 ""
13368 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
13369 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
13371 (define_split
13372 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
13373 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
13374 (match_operand:SI 2 "u_short_cint_operand" "")))
13375 (set (match_operand:SI 0 "gpc_reg_operand" "")
13376 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
13377 ""
13378 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
13379 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
13381 (define_insn "*cmpsf_internal1"
13382 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13383 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
13384 (match_operand:SF 2 "gpc_reg_operand" "f")))]
13385 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
13386 "fcmpu %0,%1,%2"
13387 [(set_attr "type" "fpcompare")])
13389 (define_insn "*cmpdf_internal1"
13390 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13391 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
13392 (match_operand:DF 2 "gpc_reg_operand" "d")))]
13393 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
13394 && !VECTOR_UNIT_VSX_P (DFmode)"
13395 "fcmpu %0,%1,%2"
13396 [(set_attr "type" "fpcompare")])
13398 ;; Only need to compare second words if first words equal
13399 (define_insn "*cmptf_internal1"
13400 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13401 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
13402 (match_operand:TF 2 "gpc_reg_operand" "d")))]
13403 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
13404 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
13405 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
13406 [(set_attr "type" "fpcompare")
13407 (set_attr "length" "12")])
13409 (define_insn_and_split "*cmptf_internal2"
13410 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13411 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
13412 (match_operand:TF 2 "gpc_reg_operand" "d")))
13413 (clobber (match_scratch:DF 3 "=d"))
13414 (clobber (match_scratch:DF 4 "=d"))
13415 (clobber (match_scratch:DF 5 "=d"))
13416 (clobber (match_scratch:DF 6 "=d"))
13417 (clobber (match_scratch:DF 7 "=d"))
13418 (clobber (match_scratch:DF 8 "=d"))
13419 (clobber (match_scratch:DF 9 "=d"))
13420 (clobber (match_scratch:DF 10 "=d"))
13421 (clobber (match_scratch:GPR 11 "=b"))]
13422 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
13423 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
13424 "#"
13425 "&& reload_completed"
13426 [(set (match_dup 3) (match_dup 14))
13427 (set (match_dup 4) (match_dup 15))
13428 (set (match_dup 9) (abs:DF (match_dup 5)))
13429 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
13430 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
13431 (label_ref (match_dup 12))
13432 (pc)))
13433 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
13434 (set (pc) (label_ref (match_dup 13)))
13435 (match_dup 12)
13436 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
13437 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
13438 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
13439 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
13440 (match_dup 13)]
13441 {
13442 REAL_VALUE_TYPE rv;
13443 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
13444 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
13446 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
13447 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
13448 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
13449 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
13450 operands[12] = gen_label_rtx ();
13451 operands[13] = gen_label_rtx ();
13452 real_inf (&rv);
13453 operands[14] = force_const_mem (DFmode,
13454 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
13455 operands[15] = force_const_mem (DFmode,
13456 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
13457 DFmode));
13458 if (TARGET_TOC)
13459 {
13460 rtx tocref;
13461 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
13462 operands[14] = gen_const_mem (DFmode, tocref);
13463 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
13464 operands[15] = gen_const_mem (DFmode, tocref);
13465 set_mem_alias_set (operands[14], get_TOC_alias_set ());
13466 set_mem_alias_set (operands[15], get_TOC_alias_set ());
13467 }
13468 })
13469 \f
13470 ;; Now we have the scc insns. We can do some combinations because of the
13471 ;; way the machine works.
13472 ;;
13473 ;; Note that this is probably faster if we can put an insn between the
13474 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
13475 ;; cases the insns below which don't use an intermediate CR field will
13476 ;; be used instead.
13477 (define_insn ""
13478 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13479 (match_operator:SI 1 "scc_comparison_operator"
13480 [(match_operand 2 "cc_reg_operand" "y")
13481 (const_int 0)]))]
13482 ""
13483 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
13484 [(set (attr "type")
13485 (cond [(match_test "TARGET_MFCRF")
13486 (const_string "mfcrf")
13487 ]
13488 (const_string "mfcr")))
13489 (set_attr "length" "8")])
13491 ;; Same as above, but get the GT bit.
13492 (define_insn "move_from_CR_gt_bit"
13493 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13494 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
13495 "TARGET_HARD_FLOAT && !TARGET_FPRS"
13496 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
13497 [(set_attr "type" "mfcr")
13498 (set_attr "length" "8")])
13500 ;; Same as above, but get the OV/ORDERED bit.
13501 (define_insn "move_from_CR_ov_bit"
13502 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13503 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
13504 "TARGET_ISEL"
13505 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
13506 [(set_attr "type" "mfcr")
13507 (set_attr "length" "8")])
13509 (define_insn ""
13510 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13511 (match_operator:DI 1 "scc_comparison_operator"
13512 [(match_operand 2 "cc_reg_operand" "y")
13513 (const_int 0)]))]
13514 "TARGET_POWERPC64"
13515 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
13516 [(set (attr "type")
13517 (cond [(match_test "TARGET_MFCRF")
13518 (const_string "mfcrf")
13519 ]
13520 (const_string "mfcr")))
13521 (set_attr "length" "8")])
13523 (define_insn ""
13524 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13525 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
13526 [(match_operand 2 "cc_reg_operand" "y,y")
13527 (const_int 0)])
13528 (const_int 0)))
13529 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
13530 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
13531 "TARGET_32BIT"
13532 "@
13533 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
13534 #"
13535 [(set_attr "type" "delayed_compare")
13536 (set_attr "length" "8,16")])
13538 (define_split
13539 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13540 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
13541 [(match_operand 2 "cc_reg_operand" "")
13542 (const_int 0)])
13543 (const_int 0)))
13544 (set (match_operand:SI 3 "gpc_reg_operand" "")
13545 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
13546 "TARGET_32BIT && reload_completed"
13547 [(set (match_dup 3)
13548 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
13549 (set (match_dup 0)
13550 (compare:CC (match_dup 3)
13551 (const_int 0)))]
13552 "")
13554 (define_insn ""
13555 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13556 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13557 [(match_operand 2 "cc_reg_operand" "y")
13558 (const_int 0)])
13559 (match_operand:SI 3 "const_int_operand" "n")))]
13560 ""
13561 "*
13562 {
13563 int is_bit = ccr_bit (operands[1], 1);
13564 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13565 int count;
13567 if (is_bit >= put_bit)
13568 count = is_bit - put_bit;
13569 else
13570 count = 32 - (put_bit - is_bit);
13572 operands[4] = GEN_INT (count);
13573 operands[5] = GEN_INT (put_bit);
13575 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
13576 }"
13577 [(set (attr "type")
13578 (cond [(match_test "TARGET_MFCRF")
13579 (const_string "mfcrf")
13580 ]
13581 (const_string "mfcr")))
13582 (set_attr "length" "8")])
13584 (define_insn ""
13585 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13586 (compare:CC
13587 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13588 [(match_operand 2 "cc_reg_operand" "y,y")
13589 (const_int 0)])
13590 (match_operand:SI 3 "const_int_operand" "n,n"))
13591 (const_int 0)))
13592 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
13593 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13594 (match_dup 3)))]
13595 ""
13596 "*
13597 {
13598 int is_bit = ccr_bit (operands[1], 1);
13599 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13600 int count;
13602 /* Force split for non-cc0 compare. */
13603 if (which_alternative == 1)
13604 return \"#\";
13606 if (is_bit >= put_bit)
13607 count = is_bit - put_bit;
13608 else
13609 count = 32 - (put_bit - is_bit);
13611 operands[5] = GEN_INT (count);
13612 operands[6] = GEN_INT (put_bit);
13614 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
13615 }"
13616 [(set_attr "type" "delayed_compare")
13617 (set_attr "length" "8,16")])
13619 (define_split
13620 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13621 (compare:CC
13622 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13623 [(match_operand 2 "cc_reg_operand" "")
13624 (const_int 0)])
13625 (match_operand:SI 3 "const_int_operand" ""))
13626 (const_int 0)))
13627 (set (match_operand:SI 4 "gpc_reg_operand" "")
13628 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13629 (match_dup 3)))]
13630 "reload_completed"
13631 [(set (match_dup 4)
13632 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13633 (match_dup 3)))
13634 (set (match_dup 0)
13635 (compare:CC (match_dup 4)
13636 (const_int 0)))]
13637 "")
13639 ;; There is a 3 cycle delay between consecutive mfcr instructions
13640 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
13642 (define_peephole
13643 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13644 (match_operator:SI 1 "scc_comparison_operator"
13645 [(match_operand 2 "cc_reg_operand" "y")
13646 (const_int 0)]))
13647 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
13648 (match_operator:SI 4 "scc_comparison_operator"
13649 [(match_operand 5 "cc_reg_operand" "y")
13650 (const_int 0)]))]
13651 "REGNO (operands[2]) != REGNO (operands[5])"
13652 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13653 [(set_attr "type" "mfcr")
13654 (set_attr "length" "12")])
13656 (define_peephole
13657 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13658 (match_operator:DI 1 "scc_comparison_operator"
13659 [(match_operand 2 "cc_reg_operand" "y")
13660 (const_int 0)]))
13661 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
13662 (match_operator:DI 4 "scc_comparison_operator"
13663 [(match_operand 5 "cc_reg_operand" "y")
13664 (const_int 0)]))]
13665 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
13666 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13667 [(set_attr "type" "mfcr")
13668 (set_attr "length" "12")])
13670 ;; There are some scc insns that can be done directly, without a compare.
13671 ;; These are faster because they don't involve the communications between
13672 ;; the FXU and branch units. In fact, we will be replacing all of the
13673 ;; integer scc insns here or in the portable methods in emit_store_flag.
13674 ;;
13675 ;; Also support (neg (scc ..)) since that construct is used to replace
13676 ;; branches, (plus (scc ..) ..) since that construct is common and
13677 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
13678 ;; cases where it is no more expensive than (neg (scc ..)).
13680 ;; Have reload force a constant into a register for the simple insns that
13681 ;; otherwise won't accept constants. We do this because it is faster than
13682 ;; the cmp/mfcr sequence we would otherwise generate.
13684 (define_mode_attr scc_eq_op2 [(SI "rKLI")
13685 (DI "rKJI")])
13687 (define_insn_and_split "*eq<mode>"
13688 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
13689 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
13690 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
13691 "!TARGET_POWER"
13692 "#"
13693 "!TARGET_POWER"
13694 [(set (match_dup 0)
13695 (clz:GPR (match_dup 3)))
13696 (set (match_dup 0)
13697 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
13698 {
13699 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13700 {
13701 /* Use output operand as intermediate. */
13702 operands[3] = operands[0];
13704 if (logical_operand (operands[2], <MODE>mode))
13705 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13706 gen_rtx_XOR (<MODE>mode,
13707 operands[1], operands[2])));
13708 else
13709 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13710 gen_rtx_PLUS (<MODE>mode, operands[1],
13711 negate_rtx (<MODE>mode,
13712 operands[2]))));
13713 }
13714 else
13715 operands[3] = operands[1];
13717 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13718 })
13720 (define_insn_and_split "*eq<mode>_compare"
13721 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13722 (compare:CC
13723 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
13724 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
13725 (const_int 0)))
13726 (set (match_operand:P 0 "gpc_reg_operand" "=r")
13727 (eq:P (match_dup 1) (match_dup 2)))]
13728 "!TARGET_POWER && optimize_size"
13729 "#"
13730 "!TARGET_POWER && optimize_size"
13731 [(set (match_dup 0)
13732 (clz:P (match_dup 4)))
13733 (parallel [(set (match_dup 3)
13734 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
13735 (const_int 0)))
13736 (set (match_dup 0)
13737 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
13738 {
13739 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13740 {
13741 /* Use output operand as intermediate. */
13742 operands[4] = operands[0];
13744 if (logical_operand (operands[2], <MODE>mode))
13745 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13746 gen_rtx_XOR (<MODE>mode,
13747 operands[1], operands[2])));
13748 else
13749 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13750 gen_rtx_PLUS (<MODE>mode, operands[1],
13751 negate_rtx (<MODE>mode,
13752 operands[2]))));
13753 }
13754 else
13755 operands[4] = operands[1];
13757 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13758 })
13760 (define_insn "*eqsi_power"
13761 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
13762 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13763 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
13764 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
13765 "TARGET_POWER"
13766 "@
13767 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13768 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
13769 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13770 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13771 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
13772 [(set_attr "type" "three,two,three,three,three")
13773 (set_attr "length" "12,8,12,12,12")])
13775 ;; We have insns of the form shown by the first define_insn below. If
13776 ;; there is something inside the comparison operation, we must split it.
13777 (define_split
13778 [(set (match_operand:SI 0 "gpc_reg_operand" "")
13779 (plus:SI (match_operator 1 "comparison_operator"
13780 [(match_operand:SI 2 "" "")
13781 (match_operand:SI 3
13782 "reg_or_cint_operand" "")])
13783 (match_operand:SI 4 "gpc_reg_operand" "")))
13784 (clobber (match_operand:SI 5 "register_operand" ""))]
13785 "! gpc_reg_operand (operands[2], SImode)"
13786 [(set (match_dup 5) (match_dup 2))
13787 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
13788 (match_dup 4)))])
13790 (define_insn "*plus_eqsi"
13791 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
13792 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13793 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
13794 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
13795 "TARGET_32BIT"
13796 "@
13797 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13798 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
13799 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13800 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13801 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13802 [(set_attr "type" "three,two,three,three,three")
13803 (set_attr "length" "12,8,12,12,12")])
13805 (define_insn "*compare_plus_eqsi"
13806 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13807 (compare:CC
13808 (plus:SI
13809 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13810 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13811 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13812 (const_int 0)))
13813 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
13814 "TARGET_32BIT && optimize_size"
13815 "@
13816 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13817 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
13818 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13819 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13820 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13821 #
13822 #
13823 #
13824 #
13825 #"
13826 [(set_attr "type" "compare")
13827 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13829 (define_split
13830 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13831 (compare:CC
13832 (plus:SI
13833 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13834 (match_operand:SI 2 "scc_eq_operand" ""))
13835 (match_operand:SI 3 "gpc_reg_operand" ""))
13836 (const_int 0)))
13837 (clobber (match_scratch:SI 4 ""))]
13838 "TARGET_32BIT && optimize_size && reload_completed"
13839 [(set (match_dup 4)
13840 (plus:SI (eq:SI (match_dup 1)
13841 (match_dup 2))
13842 (match_dup 3)))
13843 (set (match_dup 0)
13844 (compare:CC (match_dup 4)
13845 (const_int 0)))]
13846 "")
13848 (define_insn "*plus_eqsi_compare"
13849 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13850 (compare:CC
13851 (plus:SI
13852 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13853 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13854 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13855 (const_int 0)))
13856 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
13857 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13858 "TARGET_32BIT && optimize_size"
13859 "@
13860 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13861 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
13862 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13863 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13864 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13865 #
13866 #
13867 #
13868 #
13869 #"
13870 [(set_attr "type" "compare")
13871 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13873 (define_split
13874 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13875 (compare:CC
13876 (plus:SI
13877 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13878 (match_operand:SI 2 "scc_eq_operand" ""))
13879 (match_operand:SI 3 "gpc_reg_operand" ""))
13880 (const_int 0)))
13881 (set (match_operand:SI 0 "gpc_reg_operand" "")
13882 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13883 "TARGET_32BIT && optimize_size && reload_completed"
13884 [(set (match_dup 0)
13885 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13886 (set (match_dup 4)
13887 (compare:CC (match_dup 0)
13888 (const_int 0)))]
13889 "")
13891 (define_insn "*neg_eq0<mode>"
13892 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13893 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
13894 (const_int 0))))]
13895 ""
13896 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
13897 [(set_attr "type" "two")
13898 (set_attr "length" "8")])
13900 (define_insn_and_split "*neg_eq<mode>"
13901 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13902 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
13903 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
13904 ""
13905 "#"
13906 ""
13907 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
13908 {
13909 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13910 {
13911 /* Use output operand as intermediate. */
13912 operands[3] = operands[0];
13914 if (logical_operand (operands[2], <MODE>mode))
13915 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13916 gen_rtx_XOR (<MODE>mode,
13917 operands[1], operands[2])));
13918 else
13919 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13920 gen_rtx_PLUS (<MODE>mode, operands[1],
13921 negate_rtx (<MODE>mode,
13922 operands[2]))));
13923 }
13924 else
13925 operands[3] = operands[1];
13926 })
13928 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
13929 ;; since it nabs/sr is just as fast.
13930 (define_insn "*ne0si"
13931 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13932 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13933 (const_int 31)))
13934 (clobber (match_scratch:SI 2 "=&r"))]
13935 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
13936 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
13937 [(set_attr "type" "two")
13938 (set_attr "length" "8")])
13940 (define_insn "*ne0di"
13941 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13942 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13943 (const_int 63)))
13944 (clobber (match_scratch:DI 2 "=&r"))]
13945 "TARGET_64BIT"
13946 "addic %2,%1,-1\;subfe %0,%2,%1"
13947 [(set_attr "type" "two")
13948 (set_attr "length" "8")])
13950 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
13951 (define_insn "*plus_ne0si"
13952 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13953 (plus:SI (lshiftrt:SI
13954 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13955 (const_int 31))
13956 (match_operand:SI 2 "gpc_reg_operand" "r")))
13957 (clobber (match_scratch:SI 3 "=&r"))]
13958 "TARGET_32BIT"
13959 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
13960 [(set_attr "type" "two")
13961 (set_attr "length" "8")])
13963 (define_insn "*plus_ne0di"
13964 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13965 (plus:DI (lshiftrt:DI
13966 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13967 (const_int 63))
13968 (match_operand:DI 2 "gpc_reg_operand" "r")))
13969 (clobber (match_scratch:DI 3 "=&r"))]
13970 "TARGET_64BIT"
13971 "addic %3,%1,-1\;addze %0,%2"
13972 [(set_attr "type" "two")
13973 (set_attr "length" "8")])
13975 (define_insn "*compare_plus_ne0si"
13976 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13977 (compare:CC
13978 (plus:SI (lshiftrt:SI
13979 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
13980 (const_int 31))
13981 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13982 (const_int 0)))
13983 (clobber (match_scratch:SI 3 "=&r,&r"))
13984 (clobber (match_scratch:SI 4 "=X,&r"))]
13985 "TARGET_32BIT"
13986 "@
13987 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
13988 #"
13989 [(set_attr "type" "compare")
13990 (set_attr "length" "8,12")])
13992 (define_split
13993 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13994 (compare:CC
13995 (plus:SI (lshiftrt:SI
13996 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
13997 (const_int 31))
13998 (match_operand:SI 2 "gpc_reg_operand" ""))
13999 (const_int 0)))
14000 (clobber (match_scratch:SI 3 ""))
14001 (clobber (match_scratch:SI 4 ""))]
14002 "TARGET_32BIT && reload_completed"
14003 [(parallel [(set (match_dup 3)
14004 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
14005 (const_int 31))
14006 (match_dup 2)))
14007 (clobber (match_dup 4))])
14008 (set (match_dup 0)
14009 (compare:CC (match_dup 3)
14010 (const_int 0)))]
14011 "")
14013 (define_insn "*compare_plus_ne0di"
14014 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14015 (compare:CC
14016 (plus:DI (lshiftrt:DI
14017 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
14018 (const_int 63))
14019 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14020 (const_int 0)))
14021 (clobber (match_scratch:DI 3 "=&r,&r"))]
14022 "TARGET_64BIT"
14023 "@
14024 addic %3,%1,-1\;addze. %3,%2
14025 #"
14026 [(set_attr "type" "compare")
14027 (set_attr "length" "8,12")])
14029 (define_split
14030 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
14031 (compare:CC
14032 (plus:DI (lshiftrt:DI
14033 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
14034 (const_int 63))
14035 (match_operand:DI 2 "gpc_reg_operand" ""))
14036 (const_int 0)))
14037 (clobber (match_scratch:DI 3 ""))]
14038 "TARGET_64BIT && reload_completed"
14039 [(set (match_dup 3)
14040 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
14041 (const_int 63))
14042 (match_dup 2)))
14043 (set (match_dup 0)
14044 (compare:CC (match_dup 3)
14045 (const_int 0)))]
14046 "")
14048 (define_insn "*plus_ne0si_compare"
14049 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14050 (compare:CC
14051 (plus:SI (lshiftrt:SI
14052 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
14053 (const_int 31))
14054 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14055 (const_int 0)))
14056 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14057 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
14058 (match_dup 2)))
14059 (clobber (match_scratch:SI 3 "=&r,&r"))]
14060 "TARGET_32BIT"
14061 "@
14062 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
14063 #"
14064 [(set_attr "type" "compare")
14065 (set_attr "length" "8,12")])
14067 (define_split
14068 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14069 (compare:CC
14070 (plus:SI (lshiftrt:SI
14071 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
14072 (const_int 31))
14073 (match_operand:SI 2 "gpc_reg_operand" ""))
14074 (const_int 0)))
14075 (set (match_operand:SI 0 "gpc_reg_operand" "")
14076 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
14077 (match_dup 2)))
14078 (clobber (match_scratch:SI 3 ""))]
14079 "TARGET_32BIT && reload_completed"
14080 [(parallel [(set (match_dup 0)
14081 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
14082 (match_dup 2)))
14083 (clobber (match_dup 3))])
14084 (set (match_dup 4)
14085 (compare:CC (match_dup 0)
14086 (const_int 0)))]
14087 "")
14089 (define_insn "*plus_ne0di_compare"
14090 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14091 (compare:CC
14092 (plus:DI (lshiftrt:DI
14093 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
14094 (const_int 63))
14095 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14096 (const_int 0)))
14097 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
14098 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
14099 (match_dup 2)))
14100 (clobber (match_scratch:DI 3 "=&r,&r"))]
14101 "TARGET_64BIT"
14102 "@
14103 addic %3,%1,-1\;addze. %0,%2
14104 #"
14105 [(set_attr "type" "compare")
14106 (set_attr "length" "8,12")])
14108 (define_split
14109 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
14110 (compare:CC
14111 (plus:DI (lshiftrt:DI
14112 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
14113 (const_int 63))
14114 (match_operand:DI 2 "gpc_reg_operand" ""))
14115 (const_int 0)))
14116 (set (match_operand:DI 0 "gpc_reg_operand" "")
14117 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
14118 (match_dup 2)))
14119 (clobber (match_scratch:DI 3 ""))]
14120 "TARGET_64BIT && reload_completed"
14121 [(parallel [(set (match_dup 0)
14122 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
14123 (match_dup 2)))
14124 (clobber (match_dup 3))])
14125 (set (match_dup 4)
14126 (compare:CC (match_dup 0)
14127 (const_int 0)))]
14128 "")
14130 (define_insn ""
14131 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14132 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14133 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
14134 (clobber (match_scratch:SI 3 "=r,X"))]
14135 "TARGET_POWER"
14136 "@
14137 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
14138 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
14139 [(set_attr "length" "12")])
14141 (define_insn ""
14142 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14143 (compare:CC
14144 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14145 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
14146 (const_int 0)))
14147 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
14148 (le:SI (match_dup 1) (match_dup 2)))
14149 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
14150 "TARGET_POWER"
14151 "@
14152 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
14153 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
14154 #
14155 #"
14156 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
14157 (set_attr "length" "12,12,16,16")])
14159 (define_split
14160 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14161 (compare:CC
14162 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
14163 (match_operand:SI 2 "reg_or_short_operand" ""))
14164 (const_int 0)))
14165 (set (match_operand:SI 0 "gpc_reg_operand" "")
14166 (le:SI (match_dup 1) (match_dup 2)))
14167 (clobber (match_scratch:SI 3 ""))]
14168 "TARGET_POWER && reload_completed"
14169 [(parallel [(set (match_dup 0)
14170 (le:SI (match_dup 1) (match_dup 2)))
14171 (clobber (match_dup 3))])
14172 (set (match_dup 4)
14173 (compare:CC (match_dup 0)
14174 (const_int 0)))]
14175 "")
14177 (define_insn ""
14178 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14179 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14180 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
14181 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
14182 "TARGET_POWER"
14183 "@
14184 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
14185 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
14186 [(set_attr "length" "12")])
14188 (define_insn ""
14189 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14190 (compare:CC
14191 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14192 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
14193 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14194 (const_int 0)))
14195 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14196 "TARGET_POWER"
14197 "@
14198 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
14199 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
14200 #
14201 #"
14202 [(set_attr "type" "compare")
14203 (set_attr "length" "12,12,16,16")])
14205 (define_split
14206 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14207 (compare:CC
14208 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
14209 (match_operand:SI 2 "reg_or_short_operand" ""))
14210 (match_operand:SI 3 "gpc_reg_operand" ""))
14211 (const_int 0)))
14212 (clobber (match_scratch:SI 4 ""))]
14213 "TARGET_POWER && reload_completed"
14214 [(set (match_dup 4)
14215 (plus:SI (le:SI (match_dup 1) (match_dup 2))
14216 (match_dup 3)))
14217 (set (match_dup 0)
14218 (compare:CC (match_dup 4)
14219 (const_int 0)))]
14220 "")
14222 (define_insn ""
14223 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14224 (compare:CC
14225 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14226 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
14227 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14228 (const_int 0)))
14229 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14230 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14231 "TARGET_POWER"
14232 "@
14233 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
14234 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
14235 #
14236 #"
14237 [(set_attr "type" "compare")
14238 (set_attr "length" "12,12,16,16")])
14240 (define_split
14241 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14242 (compare:CC
14243 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
14244 (match_operand:SI 2 "reg_or_short_operand" ""))
14245 (match_operand:SI 3 "gpc_reg_operand" ""))
14246 (const_int 0)))
14247 (set (match_operand:SI 0 "gpc_reg_operand" "")
14248 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14249 "TARGET_POWER && reload_completed"
14250 [(set (match_dup 0)
14251 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14252 (set (match_dup 4)
14253 (compare:CC (match_dup 0)
14254 (const_int 0)))]
14255 "")
14257 (define_insn ""
14258 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14259 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14260 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
14261 "TARGET_POWER"
14262 "@
14263 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
14264 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
14265 [(set_attr "length" "12")])
14267 (define_insn "*leu<mode>"
14268 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14269 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14270 (match_operand:P 2 "reg_or_short_operand" "rI")))]
14271 ""
14272 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
14273 [(set_attr "type" "three")
14274 (set_attr "length" "12")])
14276 (define_insn "*leu<mode>_compare"
14277 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14278 (compare:CC
14279 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14280 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
14281 (const_int 0)))
14282 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14283 (leu:P (match_dup 1) (match_dup 2)))]
14284 ""
14285 "@
14286 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14287 #"
14288 [(set_attr "type" "compare")
14289 (set_attr "length" "12,16")])
14291 (define_split
14292 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14293 (compare:CC
14294 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
14295 (match_operand:P 2 "reg_or_short_operand" ""))
14296 (const_int 0)))
14297 (set (match_operand:P 0 "gpc_reg_operand" "")
14298 (leu:P (match_dup 1) (match_dup 2)))]
14299 "reload_completed"
14300 [(set (match_dup 0)
14301 (leu:P (match_dup 1) (match_dup 2)))
14302 (set (match_dup 3)
14303 (compare:CC (match_dup 0)
14304 (const_int 0)))]
14305 "")
14307 (define_insn "*plus_leu<mode>"
14308 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14309 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14310 (match_operand:P 2 "reg_or_short_operand" "rI"))
14311 (match_operand:P 3 "gpc_reg_operand" "r")))]
14312 ""
14313 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
14314 [(set_attr "type" "two")
14315 (set_attr "length" "8")])
14317 (define_insn ""
14318 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14319 (compare:CC
14320 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14321 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14322 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14323 (const_int 0)))
14324 (clobber (match_scratch:SI 4 "=&r,&r"))]
14325 "TARGET_32BIT"
14326 "@
14327 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
14328 #"
14329 [(set_attr "type" "compare")
14330 (set_attr "length" "8,12")])
14332 (define_split
14333 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14334 (compare:CC
14335 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14336 (match_operand:SI 2 "reg_or_short_operand" ""))
14337 (match_operand:SI 3 "gpc_reg_operand" ""))
14338 (const_int 0)))
14339 (clobber (match_scratch:SI 4 ""))]
14340 "TARGET_32BIT && reload_completed"
14341 [(set (match_dup 4)
14342 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
14343 (match_dup 3)))
14344 (set (match_dup 0)
14345 (compare:CC (match_dup 4)
14346 (const_int 0)))]
14347 "")
14349 (define_insn ""
14350 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14351 (compare:CC
14352 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14353 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14354 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14355 (const_int 0)))
14356 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14357 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14358 "TARGET_32BIT"
14359 "@
14360 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
14361 #"
14362 [(set_attr "type" "compare")
14363 (set_attr "length" "8,12")])
14365 (define_split
14366 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14367 (compare:CC
14368 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14369 (match_operand:SI 2 "reg_or_short_operand" ""))
14370 (match_operand:SI 3 "gpc_reg_operand" ""))
14371 (const_int 0)))
14372 (set (match_operand:SI 0 "gpc_reg_operand" "")
14373 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14374 "TARGET_32BIT && reload_completed"
14375 [(set (match_dup 0)
14376 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14377 (set (match_dup 4)
14378 (compare:CC (match_dup 0)
14379 (const_int 0)))]
14380 "")
14382 (define_insn "*neg_leu<mode>"
14383 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14384 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14385 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14386 ""
14387 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
14388 [(set_attr "type" "three")
14389 (set_attr "length" "12")])
14391 (define_insn "*and_neg_leu<mode>"
14392 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14393 (and:P (neg:P
14394 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
14395 (match_operand:P 2 "reg_or_short_operand" "rI")))
14396 (match_operand:P 3 "gpc_reg_operand" "r")))]
14397 ""
14398 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
14399 [(set_attr "type" "three")
14400 (set_attr "length" "12")])
14402 (define_insn ""
14403 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14404 (compare:CC
14405 (and:SI (neg:SI
14406 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14407 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
14408 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14409 (const_int 0)))
14410 (clobber (match_scratch:SI 4 "=&r,&r"))]
14411 "TARGET_32BIT"
14412 "@
14413 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14414 #"
14415 [(set_attr "type" "compare")
14416 (set_attr "length" "12,16")])
14418 (define_split
14419 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14420 (compare:CC
14421 (and:SI (neg:SI
14422 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14423 (match_operand:SI 2 "reg_or_short_operand" "")))
14424 (match_operand:SI 3 "gpc_reg_operand" ""))
14425 (const_int 0)))
14426 (clobber (match_scratch:SI 4 ""))]
14427 "TARGET_32BIT && reload_completed"
14428 [(set (match_dup 4)
14429 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
14430 (match_dup 3)))
14431 (set (match_dup 0)
14432 (compare:CC (match_dup 4)
14433 (const_int 0)))]
14434 "")
14436 (define_insn ""
14437 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14438 (compare:CC
14439 (and:SI (neg:SI
14440 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14441 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
14442 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14443 (const_int 0)))
14444 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14445 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14446 "TARGET_32BIT"
14447 "@
14448 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14449 #"
14450 [(set_attr "type" "compare")
14451 (set_attr "length" "12,16")])
14453 (define_split
14454 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14455 (compare:CC
14456 (and:SI (neg:SI
14457 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14458 (match_operand:SI 2 "reg_or_short_operand" "")))
14459 (match_operand:SI 3 "gpc_reg_operand" ""))
14460 (const_int 0)))
14461 (set (match_operand:SI 0 "gpc_reg_operand" "")
14462 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14463 "TARGET_32BIT && reload_completed"
14464 [(set (match_dup 0)
14465 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
14466 (match_dup 3)))
14467 (set (match_dup 4)
14468 (compare:CC (match_dup 0)
14469 (const_int 0)))]
14470 "")
14472 (define_insn ""
14473 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14474 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14475 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
14476 "TARGET_POWER"
14477 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
14478 [(set_attr "length" "12")])
14480 (define_insn ""
14481 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14482 (compare:CC
14483 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14484 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14485 (const_int 0)))
14486 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14487 (lt:SI (match_dup 1) (match_dup 2)))]
14488 "TARGET_POWER"
14489 "@
14490 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
14491 #"
14492 [(set_attr "type" "delayed_compare")
14493 (set_attr "length" "12,16")])
14495 (define_split
14496 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14497 (compare:CC
14498 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14499 (match_operand:SI 2 "reg_or_short_operand" ""))
14500 (const_int 0)))
14501 (set (match_operand:SI 0 "gpc_reg_operand" "")
14502 (lt:SI (match_dup 1) (match_dup 2)))]
14503 "TARGET_POWER && reload_completed"
14504 [(set (match_dup 0)
14505 (lt:SI (match_dup 1) (match_dup 2)))
14506 (set (match_dup 3)
14507 (compare:CC (match_dup 0)
14508 (const_int 0)))]
14509 "")
14511 (define_insn ""
14512 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14513 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14514 (match_operand:SI 2 "reg_or_short_operand" "rI"))
14515 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14516 "TARGET_POWER"
14517 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
14518 [(set_attr "length" "12")])
14520 (define_insn ""
14521 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14522 (compare:CC
14523 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14524 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14525 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14526 (const_int 0)))
14527 (clobber (match_scratch:SI 4 "=&r,&r"))]
14528 "TARGET_POWER"
14529 "@
14530 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
14531 #"
14532 [(set_attr "type" "compare")
14533 (set_attr "length" "12,16")])
14535 (define_split
14536 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14537 (compare:CC
14538 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14539 (match_operand:SI 2 "reg_or_short_operand" ""))
14540 (match_operand:SI 3 "gpc_reg_operand" ""))
14541 (const_int 0)))
14542 (clobber (match_scratch:SI 4 ""))]
14543 "TARGET_POWER && reload_completed"
14544 [(set (match_dup 4)
14545 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
14546 (match_dup 3)))
14547 (set (match_dup 0)
14548 (compare:CC (match_dup 4)
14549 (const_int 0)))]
14550 "")
14552 (define_insn ""
14553 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14554 (compare:CC
14555 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14556 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14557 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14558 (const_int 0)))
14559 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14560 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14561 "TARGET_POWER"
14562 "@
14563 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
14564 #"
14565 [(set_attr "type" "compare")
14566 (set_attr "length" "12,16")])
14568 (define_split
14569 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14570 (compare:CC
14571 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14572 (match_operand:SI 2 "reg_or_short_operand" ""))
14573 (match_operand:SI 3 "gpc_reg_operand" ""))
14574 (const_int 0)))
14575 (set (match_operand:SI 0 "gpc_reg_operand" "")
14576 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14577 "TARGET_POWER && reload_completed"
14578 [(set (match_dup 0)
14579 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14580 (set (match_dup 4)
14581 (compare:CC (match_dup 0)
14582 (const_int 0)))]
14583 "")
14585 (define_insn ""
14586 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14587 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14588 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
14589 "TARGET_POWER"
14590 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
14591 [(set_attr "length" "12")])
14593 (define_insn_and_split "*ltu<mode>"
14594 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14595 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14596 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14597 ""
14598 "#"
14599 ""
14600 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14601 (set (match_dup 0) (neg:P (match_dup 0)))]
14602 "")
14604 (define_insn_and_split "*ltu<mode>_compare"
14605 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14606 (compare:CC
14607 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14608 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14609 (const_int 0)))
14610 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14611 (ltu:P (match_dup 1) (match_dup 2)))]
14612 ""
14613 "#"
14614 ""
14615 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14616 (parallel [(set (match_dup 3)
14617 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14618 (set (match_dup 0) (neg:P (match_dup 0)))])]
14619 "")
14621 (define_insn_and_split "*plus_ltu<mode>"
14622 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
14623 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14624 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14625 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
14626 ""
14627 "#"
14628 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14629 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14630 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14631 "")
14633 (define_insn_and_split "*plus_ltu<mode>_compare"
14634 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14635 (compare:CC
14636 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14637 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14638 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14639 (const_int 0)))
14640 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14641 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14642 ""
14643 "#"
14644 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14645 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14646 (parallel [(set (match_dup 4)
14647 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14648 (const_int 0)))
14649 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14650 "")
14652 (define_insn "*neg_ltu<mode>"
14653 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14654 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14655 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
14656 ""
14657 "@
14658 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
14659 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
14660 [(set_attr "type" "two")
14661 (set_attr "length" "8")])
14663 (define_insn ""
14664 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14665 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14666 (match_operand:SI 2 "reg_or_short_operand" "rI")))
14667 (clobber (match_scratch:SI 3 "=r"))]
14668 "TARGET_POWER"
14669 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
14670 [(set_attr "length" "12")])
14672 (define_insn ""
14673 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14674 (compare:CC
14675 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14676 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14677 (const_int 0)))
14678 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14679 (ge:SI (match_dup 1) (match_dup 2)))
14680 (clobber (match_scratch:SI 3 "=r,r"))]
14681 "TARGET_POWER"
14682 "@
14683 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
14684 #"
14685 [(set_attr "type" "compare")
14686 (set_attr "length" "12,16")])
14688 (define_split
14689 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14690 (compare:CC
14691 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14692 (match_operand:SI 2 "reg_or_short_operand" ""))
14693 (const_int 0)))
14694 (set (match_operand:SI 0 "gpc_reg_operand" "")
14695 (ge:SI (match_dup 1) (match_dup 2)))
14696 (clobber (match_scratch:SI 3 ""))]
14697 "TARGET_POWER && reload_completed"
14698 [(parallel [(set (match_dup 0)
14699 (ge:SI (match_dup 1) (match_dup 2)))
14700 (clobber (match_dup 3))])
14701 (set (match_dup 4)
14702 (compare:CC (match_dup 0)
14703 (const_int 0)))]
14704 "")
14706 (define_insn ""
14707 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14708 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14709 (match_operand:SI 2 "reg_or_short_operand" "rI"))
14710 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14711 "TARGET_POWER"
14712 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
14713 [(set_attr "length" "12")])
14715 (define_insn ""
14716 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14717 (compare:CC
14718 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14719 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14720 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14721 (const_int 0)))
14722 (clobber (match_scratch:SI 4 "=&r,&r"))]
14723 "TARGET_POWER"
14724 "@
14725 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
14726 #"
14727 [(set_attr "type" "compare")
14728 (set_attr "length" "12,16")])
14730 (define_split
14731 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14732 (compare:CC
14733 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14734 (match_operand:SI 2 "reg_or_short_operand" ""))
14735 (match_operand:SI 3 "gpc_reg_operand" ""))
14736 (const_int 0)))
14737 (clobber (match_scratch:SI 4 ""))]
14738 "TARGET_POWER && reload_completed"
14739 [(set (match_dup 4)
14740 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
14741 (match_dup 3)))
14742 (set (match_dup 0)
14743 (compare:CC (match_dup 4)
14744 (const_int 0)))]
14745 "")
14747 (define_insn ""
14748 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14749 (compare:CC
14750 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14751 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14752 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14753 (const_int 0)))
14754 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14755 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14756 "TARGET_POWER"
14757 "@
14758 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
14759 #"
14760 [(set_attr "type" "compare")
14761 (set_attr "length" "12,16")])
14763 (define_split
14764 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14765 (compare:CC
14766 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14767 (match_operand:SI 2 "reg_or_short_operand" ""))
14768 (match_operand:SI 3 "gpc_reg_operand" ""))
14769 (const_int 0)))
14770 (set (match_operand:SI 0 "gpc_reg_operand" "")
14771 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14772 "TARGET_POWER && reload_completed"
14773 [(set (match_dup 0)
14774 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14775 (set (match_dup 4)
14776 (compare:CC (match_dup 0)
14777 (const_int 0)))]
14778 "")
14780 (define_insn ""
14781 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14782 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14783 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
14784 "TARGET_POWER"
14785 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
14786 [(set_attr "length" "12")])
14788 (define_insn "*geu<mode>"
14789 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14790 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14791 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14792 ""
14793 "@
14794 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
14795 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
14796 [(set_attr "type" "three")
14797 (set_attr "length" "12")])
14799 (define_insn "*geu<mode>_compare"
14800 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14801 (compare:CC
14802 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14803 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14804 (const_int 0)))
14805 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14806 (geu:P (match_dup 1) (match_dup 2)))]
14807 ""
14808 "@
14809 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14810 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14811 #
14812 #"
14813 [(set_attr "type" "compare")
14814 (set_attr "length" "12,12,16,16")])
14816 (define_split
14817 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14818 (compare:CC
14819 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
14820 (match_operand:P 2 "reg_or_neg_short_operand" ""))
14821 (const_int 0)))
14822 (set (match_operand:P 0 "gpc_reg_operand" "")
14823 (geu:P (match_dup 1) (match_dup 2)))]
14824 "reload_completed"
14825 [(set (match_dup 0)
14826 (geu:P (match_dup 1) (match_dup 2)))
14827 (set (match_dup 3)
14828 (compare:CC (match_dup 0)
14829 (const_int 0)))]
14830 "")
14832 (define_insn "*plus_geu<mode>"
14833 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14834 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14835 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14836 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14837 ""
14838 "@
14839 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
14840 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
14841 [(set_attr "type" "two")
14842 (set_attr "length" "8")])
14844 (define_insn ""
14845 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14846 (compare:CC
14847 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14848 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14849 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14850 (const_int 0)))
14851 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14852 "TARGET_32BIT"
14853 "@
14854 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
14855 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
14856 #
14857 #"
14858 [(set_attr "type" "compare")
14859 (set_attr "length" "8,8,12,12")])
14861 (define_split
14862 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14863 (compare:CC
14864 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14865 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14866 (match_operand:SI 3 "gpc_reg_operand" ""))
14867 (const_int 0)))
14868 (clobber (match_scratch:SI 4 ""))]
14869 "TARGET_32BIT && reload_completed"
14870 [(set (match_dup 4)
14871 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
14872 (match_dup 3)))
14873 (set (match_dup 0)
14874 (compare:CC (match_dup 4)
14875 (const_int 0)))]
14876 "")
14878 (define_insn ""
14879 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14880 (compare:CC
14881 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14882 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14883 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14884 (const_int 0)))
14885 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14886 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14887 "TARGET_32BIT"
14888 "@
14889 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
14890 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
14891 #
14892 #"
14893 [(set_attr "type" "compare")
14894 (set_attr "length" "8,8,12,12")])
14896 (define_split
14897 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14898 (compare:CC
14899 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14900 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14901 (match_operand:SI 3 "gpc_reg_operand" ""))
14902 (const_int 0)))
14903 (set (match_operand:SI 0 "gpc_reg_operand" "")
14904 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14905 "TARGET_32BIT && reload_completed"
14906 [(set (match_dup 0)
14907 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14908 (set (match_dup 4)
14909 (compare:CC (match_dup 0)
14910 (const_int 0)))]
14911 "")
14913 (define_insn "*neg_geu<mode>"
14914 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14915 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14916 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
14917 ""
14918 "@
14919 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
14920 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
14921 [(set_attr "type" "three")
14922 (set_attr "length" "12")])
14924 (define_insn "*and_neg_geu<mode>"
14925 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14926 (and:P (neg:P
14927 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14928 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
14929 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14930 ""
14931 "@
14932 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
14933 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
14934 [(set_attr "type" "three")
14935 (set_attr "length" "12")])
14937 (define_insn ""
14938 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14939 (compare:CC
14940 (and:SI (neg:SI
14941 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14942 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14943 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14944 (const_int 0)))
14945 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14946 "TARGET_32BIT"
14947 "@
14948 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14949 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14950 #
14951 #"
14952 [(set_attr "type" "compare")
14953 (set_attr "length" "12,12,16,16")])
14955 (define_split
14956 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14957 (compare:CC
14958 (and:SI (neg:SI
14959 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14960 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14961 (match_operand:SI 3 "gpc_reg_operand" ""))
14962 (const_int 0)))
14963 (clobber (match_scratch:SI 4 ""))]
14964 "TARGET_32BIT && reload_completed"
14965 [(set (match_dup 4)
14966 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
14967 (match_dup 3)))
14968 (set (match_dup 0)
14969 (compare:CC (match_dup 4)
14970 (const_int 0)))]
14971 "")
14973 (define_insn ""
14974 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14975 (compare:CC
14976 (and:SI (neg:SI
14977 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14978 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14979 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14980 (const_int 0)))
14981 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14982 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14983 "TARGET_32BIT"
14984 "@
14985 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14986 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14987 #
14988 #"
14989 [(set_attr "type" "compare")
14990 (set_attr "length" "12,12,16,16")])
14992 (define_split
14993 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14994 (compare:CC
14995 (and:SI (neg:SI
14996 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14997 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14998 (match_operand:SI 3 "gpc_reg_operand" ""))
14999 (const_int 0)))
15000 (set (match_operand:SI 0 "gpc_reg_operand" "")
15001 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
15002 "TARGET_32BIT && reload_completed"
15003 [(set (match_dup 0)
15004 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
15005 (set (match_dup 4)
15006 (compare:CC (match_dup 0)
15007 (const_int 0)))]
15008 "")
15010 (define_insn ""
15011 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
15012 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
15013 (match_operand:SI 2 "reg_or_short_operand" "r")))]
15014 "TARGET_POWER"
15015 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
15016 [(set_attr "length" "12")])
15018 (define_insn ""
15019 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
15020 (compare:CC
15021 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15022 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
15023 (const_int 0)))
15024 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
15025 (gt:SI (match_dup 1) (match_dup 2)))]
15026 "TARGET_POWER"
15027 "@
15028 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
15029 #"
15030 [(set_attr "type" "delayed_compare")
15031 (set_attr "length" "12,16")])
15033 (define_split
15034 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
15035 (compare:CC
15036 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15037 (match_operand:SI 2 "reg_or_short_operand" ""))
15038 (const_int 0)))
15039 (set (match_operand:SI 0 "gpc_reg_operand" "")
15040 (gt:SI (match_dup 1) (match_dup 2)))]
15041 "TARGET_POWER && reload_completed"
15042 [(set (match_dup 0)
15043 (gt:SI (match_dup 1) (match_dup 2)))
15044 (set (match_dup 3)
15045 (compare:CC (match_dup 0)
15046 (const_int 0)))]
15047 "")
15049 (define_insn "*plus_gt0<mode>"
15050 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
15051 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
15052 (const_int 0))
15053 (match_operand:P 2 "gpc_reg_operand" "r")))]
15054 ""
15055 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
15056 [(set_attr "type" "three")
15057 (set_attr "length" "12")])
15059 (define_insn ""
15060 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
15061 (compare:CC
15062 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15063 (const_int 0))
15064 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
15065 (const_int 0)))
15066 (clobber (match_scratch:SI 3 "=&r,&r"))]
15067 "TARGET_32BIT"
15068 "@
15069 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
15070 #"
15071 [(set_attr "type" "compare")
15072 (set_attr "length" "12,16")])
15074 (define_split
15075 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
15076 (compare:CC
15077 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15078 (const_int 0))
15079 (match_operand:SI 2 "gpc_reg_operand" ""))
15080 (const_int 0)))
15081 (clobber (match_scratch:SI 3 ""))]
15082 "TARGET_32BIT && reload_completed"
15083 [(set (match_dup 3)
15084 (plus:SI (gt:SI (match_dup 1) (const_int 0))
15085 (match_dup 2)))
15086 (set (match_dup 0)
15087 (compare:CC (match_dup 3)
15088 (const_int 0)))]
15089 "")
15091 (define_insn ""
15092 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
15093 (compare:CC
15094 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
15095 (const_int 0))
15096 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
15097 (const_int 0)))
15098 (clobber (match_scratch:DI 3 "=&r,&r"))]
15099 "TARGET_64BIT"
15100 "@
15101 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
15102 #"
15103 [(set_attr "type" "compare")
15104 (set_attr "length" "12,16")])
15106 (define_split
15107 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
15108 (compare:CC
15109 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
15110 (const_int 0))
15111 (match_operand:DI 2 "gpc_reg_operand" ""))
15112 (const_int 0)))
15113 (clobber (match_scratch:DI 3 ""))]
15114 "TARGET_64BIT && reload_completed"
15115 [(set (match_dup 3)
15116 (plus:DI (gt:DI (match_dup 1) (const_int 0))
15117 (match_dup 2)))
15118 (set (match_dup 0)
15119 (compare:CC (match_dup 3)
15120 (const_int 0)))]
15121 "")
15123 (define_insn ""
15124 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
15125 (compare:CC
15126 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15127 (const_int 0))
15128 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
15129 (const_int 0)))
15130 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
15131 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
15132 "TARGET_32BIT"
15133 "@
15134 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
15135 #"
15136 [(set_attr "type" "compare")
15137 (set_attr "length" "12,16")])
15139 (define_split
15140 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
15141 (compare:CC
15142 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15143 (const_int 0))
15144 (match_operand:SI 2 "gpc_reg_operand" ""))
15145 (const_int 0)))
15146 (set (match_operand:SI 0 "gpc_reg_operand" "")
15147 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
15148 "TARGET_32BIT && reload_completed"
15149 [(set (match_dup 0)
15150 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
15151 (set (match_dup 3)
15152 (compare:CC (match_dup 0)
15153 (const_int 0)))]
15154 "")
15156 (define_insn ""
15157 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
15158 (compare:CC
15159 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
15160 (const_int 0))
15161 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
15162 (const_int 0)))
15163 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
15164 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
15165 "TARGET_64BIT"
15166 "@
15167 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
15168 #"
15169 [(set_attr "type" "compare")
15170 (set_attr "length" "12,16")])
15172 (define_split
15173 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
15174 (compare:CC
15175 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
15176 (const_int 0))
15177 (match_operand:DI 2 "gpc_reg_operand" ""))
15178 (const_int 0)))
15179 (set (match_operand:DI 0 "gpc_reg_operand" "")
15180 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
15181 "TARGET_64BIT && reload_completed"
15182 [(set (match_dup 0)
15183 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
15184 (set (match_dup 3)
15185 (compare:CC (match_dup 0)
15186 (const_int 0)))]
15187 "")
15189 (define_insn ""
15190 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
15191 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
15192 (match_operand:SI 2 "reg_or_short_operand" "r"))
15193 (match_operand:SI 3 "gpc_reg_operand" "r")))]
15194 "TARGET_POWER"
15195 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
15196 [(set_attr "length" "12")])
15198 (define_insn ""
15199 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
15200 (compare:CC
15201 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15202 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
15203 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
15204 (const_int 0)))
15205 (clobber (match_scratch:SI 4 "=&r,&r"))]
15206 "TARGET_POWER"
15207 "@
15208 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
15209 #"
15210 [(set_attr "type" "compare")
15211 (set_attr "length" "12,16")])
15213 (define_split
15214 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
15215 (compare:CC
15216 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15217 (match_operand:SI 2 "reg_or_short_operand" ""))
15218 (match_operand:SI 3 "gpc_reg_operand" ""))
15219 (const_int 0)))
15220 (clobber (match_scratch:SI 4 ""))]
15221 "TARGET_POWER && reload_completed"
15222 [(set (match_dup 4)
15223 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
15224 (set (match_dup 0)
15225 (compare:CC (match_dup 4)
15226 (const_int 0)))]
15227 "")
15229 (define_insn ""
15230 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
15231 (compare:CC
15232 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
15233 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
15234 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
15235 (const_int 0)))
15236 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
15237 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
15238 "TARGET_POWER"
15239 "@
15240 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
15241 #"
15242 [(set_attr "type" "compare")
15243 (set_attr "length" "12,16")])
15245 (define_split
15246 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
15247 (compare:CC
15248 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
15249 (match_operand:SI 2 "reg_or_short_operand" ""))
15250 (match_operand:SI 3 "gpc_reg_operand" ""))
15251 (const_int 0)))
15252 (set (match_operand:SI 0 "gpc_reg_operand" "")
15253 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
15254 "TARGET_POWER && reload_completed"
15255 [(set (match_dup 0)
15256 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
15257 (set (match_dup 4)
15258 (compare:CC (match_dup 0)
15259 (const_int 0)))]
15260 "")
15262 (define_insn ""
15263 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
15264 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
15265 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
15266 "TARGET_POWER"
15267 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
15268 [(set_attr "length" "12")])
15270 (define_insn_and_split "*gtu<mode>"
15271 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15272 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
15273 (match_operand:P 2 "reg_or_short_operand" "rI")))]
15274 ""
15275 "#"
15276 ""
15277 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
15278 (set (match_dup 0) (neg:P (match_dup 0)))]
15279 "")
15281 (define_insn_and_split "*gtu<mode>_compare"
15282 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
15283 (compare:CC
15284 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
15285 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
15286 (const_int 0)))
15287 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
15288 (gtu:P (match_dup 1) (match_dup 2)))]
15289 ""
15290 "#"
15291 ""
15292 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
15293 (parallel [(set (match_dup 3)
15294 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
15295 (set (match_dup 0) (neg:P (match_dup 0)))])]
15296 "")
15298 (define_insn_and_split "*plus_gtu<mode>"
15299 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
15300 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
15301 (match_operand:P 2 "reg_or_short_operand" "rI"))
15302 (match_operand:P 3 "reg_or_short_operand" "rI")))]
15303 ""
15304 "#"
15305 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
15306 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
15307 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
15308 "")
15310 (define_insn_and_split "*plus_gtu<mode>_compare"
15311 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
15312 (compare:CC
15313 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
15314 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
15315 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
15316 (const_int 0)))
15317 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
15318 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
15319 ""
15320 "#"
15321 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
15322 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
15323 (parallel [(set (match_dup 4)
15324 (compare:CC (minus:P (match_dup 3) (match_dup 0))
15325 (const_int 0)))
15326 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
15327 "")
15329 (define_insn "*neg_gtu<mode>"
15330 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15331 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
15332 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
15333 ""
15334 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
15335 [(set_attr "type" "two")
15336 (set_attr "length" "8")])
15338 \f
15339 ;; Define both directions of branch and return. If we need a reload
15340 ;; register, we'd rather use CR0 since it is much easier to copy a
15341 ;; register CC value to there.
15343 (define_insn ""
15344 [(set (pc)
15345 (if_then_else (match_operator 1 "branch_comparison_operator"
15346 [(match_operand 2
15347 "cc_reg_operand" "y")
15348 (const_int 0)])
15349 (label_ref (match_operand 0 "" ""))
15350 (pc)))]
15351 ""
15352 "*
15353 {
15354 return output_cbranch (operands[1], \"%l0\", 0, insn);
15355 }"
15356 [(set_attr "type" "branch")])
15358 (define_insn ""
15359 [(set (pc)
15360 (if_then_else (match_operator 0 "branch_comparison_operator"
15361 [(match_operand 1
15362 "cc_reg_operand" "y")
15363 (const_int 0)])
15364 (any_return)
15365 (pc)))]
15366 "<return_pred>"
15367 "*
15368 {
15369 return output_cbranch (operands[0], NULL, 0, insn);
15370 }"
15371 [(set_attr "type" "jmpreg")
15372 (set_attr "length" "4")])
15374 (define_insn ""
15375 [(set (pc)
15376 (if_then_else (match_operator 1 "branch_comparison_operator"
15377 [(match_operand 2
15378 "cc_reg_operand" "y")
15379 (const_int 0)])
15380 (pc)
15381 (label_ref (match_operand 0 "" ""))))]
15382 ""
15383 "*
15384 {
15385 return output_cbranch (operands[1], \"%l0\", 1, insn);
15386 }"
15387 [(set_attr "type" "branch")])
15389 (define_insn ""
15390 [(set (pc)
15391 (if_then_else (match_operator 0 "branch_comparison_operator"
15392 [(match_operand 1
15393 "cc_reg_operand" "y")
15394 (const_int 0)])
15395 (pc)
15396 (any_return)))]
15397 "<return_pred>"
15398 "*
15399 {
15400 return output_cbranch (operands[0], NULL, 1, insn);
15401 }"
15402 [(set_attr "type" "jmpreg")
15403 (set_attr "length" "4")])
15405 ;; Logic on condition register values.
15407 ; This pattern matches things like
15408 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
15409 ; (eq:SI (reg:CCFP 68) (const_int 0)))
15410 ; (const_int 1)))
15411 ; which are generated by the branch logic.
15412 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
15414 (define_insn "*cceq_ior_compare"
15415 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
15416 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
15417 [(match_operator:SI 2
15418 "branch_positive_comparison_operator"
15419 [(match_operand 3
15420 "cc_reg_operand" "y,y")
15421 (const_int 0)])
15422 (match_operator:SI 4
15423 "branch_positive_comparison_operator"
15424 [(match_operand 5
15425 "cc_reg_operand" "0,y")
15426 (const_int 0)])])
15427 (const_int 1)))]
15428 ""
15429 "cr%q1 %E0,%j2,%j4"
15430 [(set_attr "type" "cr_logical,delayed_cr")])
15432 ; Why is the constant -1 here, but 1 in the previous pattern?
15433 ; Because ~1 has all but the low bit set.
15434 (define_insn ""
15435 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
15436 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
15437 [(not:SI (match_operator:SI 2
15438 "branch_positive_comparison_operator"
15439 [(match_operand 3
15440 "cc_reg_operand" "y,y")
15441 (const_int 0)]))
15442 (match_operator:SI 4
15443 "branch_positive_comparison_operator"
15444 [(match_operand 5
15445 "cc_reg_operand" "0,y")
15446 (const_int 0)])])
15447 (const_int -1)))]
15448 ""
15449 "cr%q1 %E0,%j2,%j4"
15450 [(set_attr "type" "cr_logical,delayed_cr")])
15452 (define_insn "*cceq_rev_compare"
15453 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
15454 (compare:CCEQ (match_operator:SI 1
15455 "branch_positive_comparison_operator"
15456 [(match_operand 2
15457 "cc_reg_operand" "0,y")
15458 (const_int 0)])
15459 (const_int 0)))]
15460 ""
15461 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
15462 [(set_attr "type" "cr_logical,delayed_cr")])
15464 ;; If we are comparing the result of two comparisons, this can be done
15465 ;; using creqv or crxor.
15467 (define_insn_and_split ""
15468 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
15469 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
15470 [(match_operand 2 "cc_reg_operand" "y")
15471 (const_int 0)])
15472 (match_operator 3 "branch_comparison_operator"
15473 [(match_operand 4 "cc_reg_operand" "y")
15474 (const_int 0)])))]
15475 ""
15476 "#"
15477 ""
15478 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
15479 (match_dup 5)))]
15480 "
15481 {
15482 int positive_1, positive_2;
15484 positive_1 = branch_positive_comparison_operator (operands[1],
15485 GET_MODE (operands[1]));
15486 positive_2 = branch_positive_comparison_operator (operands[3],
15487 GET_MODE (operands[3]));
15489 if (! positive_1)
15490 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
15491 GET_CODE (operands[1])),
15492 SImode,
15493 operands[2], const0_rtx);
15494 else if (GET_MODE (operands[1]) != SImode)
15495 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
15496 operands[2], const0_rtx);
15498 if (! positive_2)
15499 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
15500 GET_CODE (operands[3])),
15501 SImode,
15502 operands[4], const0_rtx);
15503 else if (GET_MODE (operands[3]) != SImode)
15504 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
15505 operands[4], const0_rtx);
15507 if (positive_1 == positive_2)
15508 {
15509 operands[1] = gen_rtx_NOT (SImode, operands[1]);
15510 operands[5] = constm1_rtx;
15511 }
15512 else
15513 {
15514 operands[5] = const1_rtx;
15515 }
15516 }")
15518 ;; Unconditional branch and return.
15520 (define_insn "jump"
15521 [(set (pc)
15522 (label_ref (match_operand 0 "" "")))]
15523 ""
15524 "b %l0"
15525 [(set_attr "type" "branch")])
15527 (define_insn "<return_str>return"
15528 [(any_return)]
15529 "<return_pred>"
15530 "{br|blr}"
15531 [(set_attr "type" "jmpreg")])
15533 (define_expand "indirect_jump"
15534 [(set (pc) (match_operand 0 "register_operand" ""))])
15536 (define_insn "*indirect_jump<mode>"
15537 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
15538 ""
15539 "@
15540 bctr
15541 {br|blr}"
15542 [(set_attr "type" "jmpreg")])
15544 ;; Table jump for switch statements:
15545 (define_expand "tablejump"
15546 [(use (match_operand 0 "" ""))
15547 (use (label_ref (match_operand 1 "" "")))]
15548 ""
15549 "
15550 {
15551 if (TARGET_32BIT)
15552 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
15553 else
15554 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
15555 DONE;
15556 }")
15558 (define_expand "tablejumpsi"
15559 [(set (match_dup 3)
15560 (plus:SI (match_operand:SI 0 "" "")
15561 (match_dup 2)))
15562 (parallel [(set (pc) (match_dup 3))
15563 (use (label_ref (match_operand 1 "" "")))])]
15564 "TARGET_32BIT"
15565 "
15566 { operands[0] = force_reg (SImode, operands[0]);
15567 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
15568 operands[3] = gen_reg_rtx (SImode);
15569 }")
15571 (define_expand "tablejumpdi"
15572 [(set (match_dup 4)
15573 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
15574 (set (match_dup 3)
15575 (plus:DI (match_dup 4)
15576 (match_dup 2)))
15577 (parallel [(set (pc) (match_dup 3))
15578 (use (label_ref (match_operand 1 "" "")))])]
15579 "TARGET_64BIT"
15580 "
15581 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
15582 operands[3] = gen_reg_rtx (DImode);
15583 operands[4] = gen_reg_rtx (DImode);
15584 }")
15586 (define_insn "*tablejump<mode>_internal1"
15587 [(set (pc)
15588 (match_operand:P 0 "register_operand" "c,*l"))
15589 (use (label_ref (match_operand 1 "" "")))]
15590 ""
15591 "@
15592 bctr
15593 {br|blr}"
15594 [(set_attr "type" "jmpreg")])
15596 (define_insn "nop"
15597 [(const_int 0)]
15598 ""
15599 "{cror 0,0,0|nop}")
15601 (define_insn "group_ending_nop"
15602 [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)]
15603 ""
15604 "*
15605 {
15606 if (rs6000_cpu_attr == CPU_POWER6)
15607 return \"ori 1,1,0\";
15608 return \"ori 2,2,0\";
15609 }")
15610 \f
15611 ;; Define the subtract-one-and-jump insns, starting with the template
15612 ;; so loop.c knows what to generate.
15614 (define_expand "doloop_end"
15615 [(use (match_operand 0 "" "")) ; loop pseudo
15616 (use (match_operand 1 "" "")) ; iterations; zero if unknown
15617 (use (match_operand 2 "" "")) ; max iterations
15618 (use (match_operand 3 "" "")) ; loop level
15619 (use (match_operand 4 "" ""))] ; label
15620 ""
15621 "
15622 {
15623 /* Only use this on innermost loops. */
15624 if (INTVAL (operands[3]) > 1)
15625 FAIL;
15626 if (TARGET_64BIT)
15627 {
15628 if (GET_MODE (operands[0]) != DImode)
15629 FAIL;
15630 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
15631 }
15632 else
15633 {
15634 if (GET_MODE (operands[0]) != SImode)
15635 FAIL;
15636 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
15637 }
15638 DONE;
15639 }")
15641 (define_expand "ctr<mode>"
15642 [(parallel [(set (pc)
15643 (if_then_else (ne (match_operand:P 0 "register_operand" "")
15644 (const_int 1))
15645 (label_ref (match_operand 1 "" ""))
15646 (pc)))
15647 (set (match_dup 0)
15648 (plus:P (match_dup 0)
15649 (const_int -1)))
15650 (clobber (match_scratch:CC 2 ""))
15651 (clobber (match_scratch:P 3 ""))])]
15652 ""
15653 "")
15655 ;; We need to be able to do this for any operand, including MEM, or we
15656 ;; will cause reload to blow up since we don't allow output reloads on
15657 ;; JUMP_INSNs.
15658 ;; For the length attribute to be calculated correctly, the
15659 ;; label MUST be operand 0.
15661 (define_insn "*ctr<mode>_internal1"
15662 [(set (pc)
15663 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15664 (const_int 1))
15665 (label_ref (match_operand 0 "" ""))
15666 (pc)))
15667 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15668 (plus:P (match_dup 1)
15669 (const_int -1)))
15670 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15671 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15672 ""
15673 "*
15674 {
15675 if (which_alternative != 0)
15676 return \"#\";
15677 else if (get_attr_length (insn) == 4)
15678 return \"{bdn|bdnz} %l0\";
15679 else
15680 return \"bdz $+8\;b %l0\";
15681 }"
15682 [(set_attr "type" "branch")
15683 (set_attr "length" "*,12,16,16")])
15685 (define_insn "*ctr<mode>_internal2"
15686 [(set (pc)
15687 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15688 (const_int 1))
15689 (pc)
15690 (label_ref (match_operand 0 "" ""))))
15691 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15692 (plus:P (match_dup 1)
15693 (const_int -1)))
15694 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15695 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15696 ""
15697 "*
15698 {
15699 if (which_alternative != 0)
15700 return \"#\";
15701 else if (get_attr_length (insn) == 4)
15702 return \"bdz %l0\";
15703 else
15704 return \"{bdn|bdnz} $+8\;b %l0\";
15705 }"
15706 [(set_attr "type" "branch")
15707 (set_attr "length" "*,12,16,16")])
15709 ;; Similar but use EQ
15711 (define_insn "*ctr<mode>_internal5"
15712 [(set (pc)
15713 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15714 (const_int 1))
15715 (label_ref (match_operand 0 "" ""))
15716 (pc)))
15717 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15718 (plus:P (match_dup 1)
15719 (const_int -1)))
15720 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15721 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15722 ""
15723 "*
15724 {
15725 if (which_alternative != 0)
15726 return \"#\";
15727 else if (get_attr_length (insn) == 4)
15728 return \"bdz %l0\";
15729 else
15730 return \"{bdn|bdnz} $+8\;b %l0\";
15731 }"
15732 [(set_attr "type" "branch")
15733 (set_attr "length" "*,12,16,16")])
15735 (define_insn "*ctr<mode>_internal6"
15736 [(set (pc)
15737 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15738 (const_int 1))
15739 (pc)
15740 (label_ref (match_operand 0 "" ""))))
15741 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15742 (plus:P (match_dup 1)
15743 (const_int -1)))
15744 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15745 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15746 ""
15747 "*
15748 {
15749 if (which_alternative != 0)
15750 return \"#\";
15751 else if (get_attr_length (insn) == 4)
15752 return \"{bdn|bdnz} %l0\";
15753 else
15754 return \"bdz $+8\;b %l0\";
15755 }"
15756 [(set_attr "type" "branch")
15757 (set_attr "length" "*,12,16,16")])
15759 ;; Now the splitters if we could not allocate the CTR register
15761 (define_split
15762 [(set (pc)
15763 (if_then_else (match_operator 2 "comparison_operator"
15764 [(match_operand:P 1 "gpc_reg_operand" "")
15765 (const_int 1)])
15766 (match_operand 5 "" "")
15767 (match_operand 6 "" "")))
15768 (set (match_operand:P 0 "gpc_reg_operand" "")
15769 (plus:P (match_dup 1) (const_int -1)))
15770 (clobber (match_scratch:CC 3 ""))
15771 (clobber (match_scratch:P 4 ""))]
15772 "reload_completed"
15773 [(parallel [(set (match_dup 3)
15774 (compare:CC (plus:P (match_dup 1)
15775 (const_int -1))
15776 (const_int 0)))
15777 (set (match_dup 0)
15778 (plus:P (match_dup 1)
15779 (const_int -1)))])
15780 (set (pc) (if_then_else (match_dup 7)
15781 (match_dup 5)
15782 (match_dup 6)))]
15783 "
15784 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15785 operands[3], const0_rtx); }")
15787 (define_split
15788 [(set (pc)
15789 (if_then_else (match_operator 2 "comparison_operator"
15790 [(match_operand:P 1 "gpc_reg_operand" "")
15791 (const_int 1)])
15792 (match_operand 5 "" "")
15793 (match_operand 6 "" "")))
15794 (set (match_operand:P 0 "nonimmediate_operand" "")
15795 (plus:P (match_dup 1) (const_int -1)))
15796 (clobber (match_scratch:CC 3 ""))
15797 (clobber (match_scratch:P 4 ""))]
15798 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
15799 [(parallel [(set (match_dup 3)
15800 (compare:CC (plus:P (match_dup 1)
15801 (const_int -1))
15802 (const_int 0)))
15803 (set (match_dup 4)
15804 (plus:P (match_dup 1)
15805 (const_int -1)))])
15806 (set (match_dup 0)
15807 (match_dup 4))
15808 (set (pc) (if_then_else (match_dup 7)
15809 (match_dup 5)
15810 (match_dup 6)))]
15811 "
15812 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15813 operands[3], const0_rtx); }")
15814 \f
15815 (define_insn "trap"
15816 [(trap_if (const_int 1) (const_int 0))]
15817 ""
15818 "{t 31,0,0|trap}"
15819 [(set_attr "type" "trap")])
15821 (define_expand "ctrap<mode>4"
15822 [(trap_if (match_operator 0 "ordered_comparison_operator"
15823 [(match_operand:GPR 1 "register_operand")
15824 (match_operand:GPR 2 "reg_or_short_operand")])
15825 (match_operand 3 "zero_constant" ""))]
15826 ""
15827 "")
15829 (define_insn ""
15830 [(trap_if (match_operator 0 "ordered_comparison_operator"
15831 [(match_operand:GPR 1 "register_operand" "r")
15832 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
15833 (const_int 0))]
15834 ""
15835 "{t|t<wd>}%V0%I2 %1,%2"
15836 [(set_attr "type" "trap")])
15837 \f
15838 ;; Insns related to generating the function prologue and epilogue.
15840 (define_expand "prologue"
15841 [(use (const_int 0))]
15842 ""
15843 {
15844 rs6000_emit_prologue ();
15845 if (!TARGET_SCHED_PROLOG)
15846 emit_insn (gen_blockage ());
15847 DONE;
15848 })
15850 (define_insn "*movesi_from_cr_one"
15851 [(match_parallel 0 "mfcr_operation"
15852 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15853 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
15854 (match_operand 3 "immediate_operand" "n")]
15855 UNSPEC_MOVESI_FROM_CR))])]
15856 "TARGET_MFCRF"
15857 "*
15858 {
15859 int mask = 0;
15860 int i;
15861 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15862 {
15863 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15864 operands[4] = GEN_INT (mask);
15865 output_asm_insn (\"mfcr %1,%4\", operands);
15866 }
15867 return \"\";
15868 }"
15869 [(set_attr "type" "mfcrf")])
15871 (define_insn "movesi_from_cr"
15872 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
15873 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
15874 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
15875 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
15876 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
15877 UNSPEC_MOVESI_FROM_CR))]
15878 ""
15879 "mfcr %0"
15880 [(set_attr "type" "mfcr")])
15882 (define_insn "*stmw"
15883 [(match_parallel 0 "stmw_operation"
15884 [(set (match_operand:SI 1 "memory_operand" "=m")
15885 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
15886 "TARGET_MULTIPLE"
15887 "{stm|stmw} %2,%1"
15888 [(set_attr "type" "store_ux")])
15890 ; The following comment applies to:
15891 ; save_gpregs_*
15892 ; save_fpregs_*
15893 ; restore_gpregs*
15894 ; return_and_restore_gpregs*
15895 ; return_and_restore_fpregs*
15896 ; return_and_restore_fpregs_aix*
15897 ;
15898 ; The out-of-line save / restore functions expects one input argument.
15899 ; Since those are not standard call_insn's, we must avoid using
15900 ; MATCH_OPERAND for that argument. That way the register rename
15901 ; optimization will not try to rename this register.
15902 ; Each pattern is repeated for each possible register number used in
15903 ; various ABIs (r11, r1, and for some functions r12)
15905 (define_insn "*save_gpregs_<mode>_r11"
15906 [(match_parallel 0 "any_parallel_operand"
15907 [(clobber (reg:P 65))
15908 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15909 (use (reg:P 11))
15910 (set (match_operand:P 2 "memory_operand" "=m")
15911 (match_operand:P 3 "gpc_reg_operand" "r"))])]
15912 ""
15913 "bl %1"
15914 [(set_attr "type" "branch")
15915 (set_attr "length" "4")])
15917 (define_insn "*save_gpregs_<mode>_r12"
15918 [(match_parallel 0 "any_parallel_operand"
15919 [(clobber (reg:P 65))
15920 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15921 (use (reg:P 12))
15922 (set (match_operand:P 2 "memory_operand" "=m")
15923 (match_operand:P 3 "gpc_reg_operand" "r"))])]
15924 ""
15925 "bl %1"
15926 [(set_attr "type" "branch")
15927 (set_attr "length" "4")])
15929 (define_insn "*save_gpregs_<mode>_r1"
15930 [(match_parallel 0 "any_parallel_operand"
15931 [(clobber (reg:P 65))
15932 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15933 (use (reg:P 1))
15934 (set (match_operand:P 2 "memory_operand" "=m")
15935 (match_operand:P 3 "gpc_reg_operand" "r"))])]
15936 ""
15937 "bl %1"
15938 [(set_attr "type" "branch")
15939 (set_attr "length" "4")])
15941 (define_insn "*save_fpregs_<mode>_r11"
15942 [(match_parallel 0 "any_parallel_operand"
15943 [(clobber (reg:P 65))
15944 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15945 (use (reg:P 11))
15946 (set (match_operand:DF 2 "memory_operand" "=m")
15947 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
15948 ""
15949 "bl %1"
15950 [(set_attr "type" "branch")
15951 (set_attr "length" "4")])
15953 (define_insn "*save_fpregs_<mode>_r12"
15954 [(match_parallel 0 "any_parallel_operand"
15955 [(clobber (reg:P 65))
15956 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15957 (use (reg:P 12))
15958 (set (match_operand:DF 2 "memory_operand" "=m")
15959 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
15960 ""
15961 "bl %1"
15962 [(set_attr "type" "branch")
15963 (set_attr "length" "4")])
15965 (define_insn "*save_fpregs_<mode>_r1"
15966 [(match_parallel 0 "any_parallel_operand"
15967 [(clobber (reg:P 65))
15968 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15969 (use (reg:P 1))
15970 (set (match_operand:DF 2 "memory_operand" "=m")
15971 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
15972 ""
15973 "bl %1"
15974 [(set_attr "type" "branch")
15975 (set_attr "length" "4")])
15977 ; This is to explain that changes to the stack pointer should
15978 ; not be moved over loads from or stores to stack memory.
15979 (define_insn "stack_tie"
15980 [(match_parallel 0 "tie_operand"
15981 [(set (mem:BLK (reg 1)) (const_int 0))])]
15982 ""
15983 ""
15984 [(set_attr "length" "0")])
15986 (define_expand "epilogue"
15987 [(use (const_int 0))]
15988 ""
15989 {
15990 if (!TARGET_SCHED_PROLOG)
15991 emit_insn (gen_blockage ());
15992 rs6000_emit_epilogue (FALSE);
15993 DONE;
15994 })
15996 ; On some processors, doing the mtcrf one CC register at a time is
15997 ; faster (like on the 604e). On others, doing them all at once is
15998 ; faster; for instance, on the 601 and 750.
16000 (define_expand "movsi_to_cr_one"
16001 [(set (match_operand:CC 0 "cc_reg_operand" "")
16002 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
16003 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
16004 ""
16005 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
16007 (define_insn "*movsi_to_cr"
16008 [(match_parallel 0 "mtcrf_operation"
16009 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
16010 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
16011 (match_operand 3 "immediate_operand" "n")]
16012 UNSPEC_MOVESI_TO_CR))])]
16013 ""
16014 "*
16015 {
16016 int mask = 0;
16017 int i;
16018 for (i = 0; i < XVECLEN (operands[0], 0); i++)
16019 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
16020 operands[4] = GEN_INT (mask);
16021 return \"mtcrf %4,%2\";
16022 }"
16023 [(set_attr "type" "mtcr")])
16025 (define_insn "*mtcrfsi"
16026 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
16027 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
16028 (match_operand 2 "immediate_operand" "n")]
16029 UNSPEC_MOVESI_TO_CR))]
16030 "GET_CODE (operands[0]) == REG
16031 && CR_REGNO_P (REGNO (operands[0]))
16032 && GET_CODE (operands[2]) == CONST_INT
16033 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
16034 "mtcrf %R0,%1"
16035 [(set_attr "type" "mtcr")])
16037 ; The load-multiple instructions have similar properties.
16038 ; Note that "load_multiple" is a name known to the machine-independent
16039 ; code that actually corresponds to the PowerPC load-string.
16041 (define_insn "*lmw"
16042 [(match_parallel 0 "lmw_operation"
16043 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
16044 (match_operand:SI 2 "memory_operand" "m"))])]
16045 "TARGET_MULTIPLE"
16046 "{lm|lmw} %1,%2"
16047 [(set_attr "type" "load_ux")
16048 (set_attr "cell_micro" "always")])
16050 (define_insn "*return_internal_<mode>"
16051 [(simple_return)
16052 (use (match_operand:P 0 "register_operand" "lc"))]
16053 ""
16054 "b%T0"
16055 [(set_attr "type" "jmpreg")])
16057 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
16058 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
16060 ; The following comment applies to:
16061 ; save_gpregs_*
16062 ; save_fpregs_*
16063 ; restore_gpregs*
16064 ; return_and_restore_gpregs*
16065 ; return_and_restore_fpregs*
16066 ; return_and_restore_fpregs_aix*
16067 ;
16068 ; The out-of-line save / restore functions expects one input argument.
16069 ; Since those are not standard call_insn's, we must avoid using
16070 ; MATCH_OPERAND for that argument. That way the register rename
16071 ; optimization will not try to rename this register.
16072 ; Each pattern is repeated for each possible register number used in
16073 ; various ABIs (r11, r1, and for some functions r12)
16075 (define_insn "*restore_gpregs_<mode>_r11"
16076 [(match_parallel 0 "any_parallel_operand"
16077 [(clobber (match_operand:P 1 "register_operand" "=l"))
16078 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16079 (use (reg:P 11))
16080 (set (match_operand:P 3 "gpc_reg_operand" "=r")
16081 (match_operand:P 4 "memory_operand" "m"))])]
16082 ""
16083 "bl %2"
16084 [(set_attr "type" "branch")
16085 (set_attr "length" "4")])
16087 (define_insn "*restore_gpregs_<mode>_r12"
16088 [(match_parallel 0 "any_parallel_operand"
16089 [(clobber (match_operand:P 1 "register_operand" "=l"))
16090 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16091 (use (reg:P 12))
16092 (set (match_operand:P 3 "gpc_reg_operand" "=r")
16093 (match_operand:P 4 "memory_operand" "m"))])]
16094 ""
16095 "bl %2"
16096 [(set_attr "type" "branch")
16097 (set_attr "length" "4")])
16099 (define_insn "*restore_gpregs_<mode>_r1"
16100 [(match_parallel 0 "any_parallel_operand"
16101 [(clobber (match_operand:P 1 "register_operand" "=l"))
16102 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16103 (use (reg:P 1))
16104 (set (match_operand:P 3 "gpc_reg_operand" "=r")
16105 (match_operand:P 4 "memory_operand" "m"))])]
16106 ""
16107 "bl %2"
16108 [(set_attr "type" "branch")
16109 (set_attr "length" "4")])
16111 (define_insn "*return_and_restore_gpregs_<mode>_r11"
16112 [(match_parallel 0 "any_parallel_operand"
16113 [(return)
16114 (clobber (match_operand:P 1 "register_operand" "=l"))
16115 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16116 (use (reg:P 11))
16117 (set (match_operand:P 3 "gpc_reg_operand" "=r")
16118 (match_operand:P 4 "memory_operand" "m"))])]
16119 ""
16120 "b %2"
16121 [(set_attr "type" "branch")
16122 (set_attr "length" "4")])
16124 (define_insn "*return_and_restore_gpregs_<mode>_r12"
16125 [(match_parallel 0 "any_parallel_operand"
16126 [(return)
16127 (clobber (match_operand:P 1 "register_operand" "=l"))
16128 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16129 (use (reg:P 12))
16130 (set (match_operand:P 3 "gpc_reg_operand" "=r")
16131 (match_operand:P 4 "memory_operand" "m"))])]
16132 ""
16133 "b %2"
16134 [(set_attr "type" "branch")
16135 (set_attr "length" "4")])
16137 (define_insn "*return_and_restore_gpregs_<mode>_r1"
16138 [(match_parallel 0 "any_parallel_operand"
16139 [(return)
16140 (clobber (match_operand:P 1 "register_operand" "=l"))
16141 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16142 (use (reg:P 1))
16143 (set (match_operand:P 3 "gpc_reg_operand" "=r")
16144 (match_operand:P 4 "memory_operand" "m"))])]
16145 ""
16146 "b %2"
16147 [(set_attr "type" "branch")
16148 (set_attr "length" "4")])
16150 (define_insn "*return_and_restore_fpregs_<mode>_r11"
16151 [(match_parallel 0 "any_parallel_operand"
16152 [(return)
16153 (clobber (match_operand:P 1 "register_operand" "=l"))
16154 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16155 (use (reg:P 11))
16156 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
16157 (match_operand:DF 4 "memory_operand" "m"))])]
16158 ""
16159 "b %2"
16160 [(set_attr "type" "branch")
16161 (set_attr "length" "4")])
16163 (define_insn "*return_and_restore_fpregs_<mode>_r12"
16164 [(match_parallel 0 "any_parallel_operand"
16165 [(return)
16166 (clobber (match_operand:P 1 "register_operand" "=l"))
16167 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16168 (use (reg:P 12))
16169 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
16170 (match_operand:DF 4 "memory_operand" "m"))])]
16171 ""
16172 "b %2"
16173 [(set_attr "type" "branch")
16174 (set_attr "length" "4")])
16176 (define_insn "*return_and_restore_fpregs_<mode>_r1"
16177 [(match_parallel 0 "any_parallel_operand"
16178 [(return)
16179 (clobber (match_operand:P 1 "register_operand" "=l"))
16180 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16181 (use (reg:P 1))
16182 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
16183 (match_operand:DF 4 "memory_operand" "m"))])]
16184 ""
16185 "b %2"
16186 [(set_attr "type" "branch")
16187 (set_attr "length" "4")])
16189 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
16190 [(match_parallel 0 "any_parallel_operand"
16191 [(return)
16192 (use (match_operand:P 1 "register_operand" "l"))
16193 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16194 (use (reg:P 11))
16195 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
16196 (match_operand:DF 4 "memory_operand" "m"))])]
16197 ""
16198 "b %2"
16199 [(set_attr "type" "branch")
16200 (set_attr "length" "4")])
16202 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
16203 [(match_parallel 0 "any_parallel_operand"
16204 [(return)
16205 (use (match_operand:P 1 "register_operand" "l"))
16206 (use (match_operand:P 2 "symbol_ref_operand" "s"))
16207 (use (reg:P 1))
16208 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
16209 (match_operand:DF 4 "memory_operand" "m"))])]
16210 ""
16211 "b %2"
16212 [(set_attr "type" "branch")
16213 (set_attr "length" "4")])
16215 ; This is used in compiling the unwind routines.
16216 (define_expand "eh_return"
16217 [(use (match_operand 0 "general_operand" ""))]
16218 ""
16219 "
16220 {
16221 if (TARGET_32BIT)
16222 emit_insn (gen_eh_set_lr_si (operands[0]));
16223 else
16224 emit_insn (gen_eh_set_lr_di (operands[0]));
16225 DONE;
16226 }")
16228 ; We can't expand this before we know where the link register is stored.
16229 (define_insn "eh_set_lr_<mode>"
16230 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
16231 UNSPECV_EH_RR)
16232 (clobber (match_scratch:P 1 "=&b"))]
16233 ""
16234 "#")
16236 (define_split
16237 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
16238 (clobber (match_scratch 1 ""))]
16239 "reload_completed"
16240 [(const_int 0)]
16241 "
16242 {
16243 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
16244 DONE;
16245 }")
16247 (define_insn "prefetch"
16248 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
16249 (match_operand:SI 1 "const_int_operand" "n")
16250 (match_operand:SI 2 "const_int_operand" "n"))]
16251 "TARGET_POWERPC"
16252 "*
16253 {
16254 if (GET_CODE (operands[0]) == REG)
16255 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
16256 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
16257 }"
16258 [(set_attr "type" "load")])
16259 \f
16260 (define_insn "bpermd_<mode>"
16261 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
16262 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
16263 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
16264 "TARGET_POPCNTD"
16265 "bpermd %0,%1,%2"
16266 [(set_attr "type" "integer")])
16268 \f
16269 ;; Builtin fma support. Handle
16270 ;; Note that the conditions for expansion are in the FMA_F iterator.
16272 (define_expand "fma<mode>4"
16273 [(set (match_operand:FMA_F 0 "register_operand" "")
16274 (fma:FMA_F
16275 (match_operand:FMA_F 1 "register_operand" "")
16276 (match_operand:FMA_F 2 "register_operand" "")
16277 (match_operand:FMA_F 3 "register_operand" "")))]
16278 ""
16279 "")
16281 ; Altivec only has fma and nfms.
16282 (define_expand "fms<mode>4"
16283 [(set (match_operand:FMA_F 0 "register_operand" "")
16284 (fma:FMA_F
16285 (match_operand:FMA_F 1 "register_operand" "")
16286 (match_operand:FMA_F 2 "register_operand" "")
16287 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
16288 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
16289 "")
16291 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
16292 (define_expand "fnma<mode>4"
16293 [(set (match_operand:FMA_F 0 "register_operand" "")
16294 (neg:FMA_F
16295 (fma:FMA_F
16296 (match_operand:FMA_F 1 "register_operand" "")
16297 (match_operand:FMA_F 2 "register_operand" "")
16298 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
16299 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
16300 "")
16302 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
16303 (define_expand "fnms<mode>4"
16304 [(set (match_operand:FMA_F 0 "register_operand" "")
16305 (neg:FMA_F
16306 (fma:FMA_F
16307 (match_operand:FMA_F 1 "register_operand" "")
16308 (match_operand:FMA_F 2 "register_operand" "")
16309 (match_operand:FMA_F 3 "register_operand" ""))))]
16310 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
16311 "")
16313 ; Not an official optab name, but used from builtins.
16314 (define_expand "nfma<mode>4"
16315 [(set (match_operand:FMA_F 0 "register_operand" "")
16316 (neg:FMA_F
16317 (fma:FMA_F
16318 (match_operand:FMA_F 1 "register_operand" "")
16319 (match_operand:FMA_F 2 "register_operand" "")
16320 (match_operand:FMA_F 3 "register_operand" ""))))]
16321 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
16322 "")
16324 ; Not an official optab name, but used from builtins.
16325 (define_expand "nfms<mode>4"
16326 [(set (match_operand:FMA_F 0 "register_operand" "")
16327 (neg:FMA_F
16328 (fma:FMA_F
16329 (match_operand:FMA_F 1 "register_operand" "")
16330 (match_operand:FMA_F 2 "register_operand" "")
16331 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
16332 ""
16333 "")
16335 \f
16337 (include "sync.md")
16338 (include "vector.md")
16339 (include "vsx.md")
16340 (include "altivec.md")
16341 (include "spe.md")
16342 (include "dfp.md")
16343 (include "paired.md")