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1 ;; Copyright (C) 2005-2015 Free Software Foundation, Inc.
2 ;;
3 ;; This file is part of GCC.
4 ;;
5 ;; GCC is free software; you can redistribute it and/or modify
6 ;; it under the terms of the GNU General Public License as published by
7 ;; the Free Software Foundation; either version 3, or (at your option)
8 ;; any later version.
9 ;;
10 ;; GCC is distributed in the hope that it will be useful,
11 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ;; GNU General Public License for more details.
14 ;;
15 ;; You should have received a copy of the GNU General Public License
16 ;; along with GCC; see the file COPYING3. If not see
17 ;; <http://www.gnu.org/licenses/>.
19 ;; MIPS DSP ASE Revision 0.98 3/24/2005
20 (define_c_enum "unspec" [
21 UNSPEC_ADDQ
22 UNSPEC_ADDQ_S
23 UNSPEC_SUBQ
24 UNSPEC_SUBQ_S
25 UNSPEC_ADDSC
26 UNSPEC_ADDWC
27 UNSPEC_MODSUB
28 UNSPEC_RADDU_W_QB
29 UNSPEC_ABSQ_S
30 UNSPEC_PRECRQ_QB_PH
31 UNSPEC_PRECRQ_PH_W
32 UNSPEC_PRECRQ_RS_PH_W
33 UNSPEC_PRECRQU_S_QB_PH
34 UNSPEC_PRECEQ_W_PHL
35 UNSPEC_PRECEQ_W_PHR
36 UNSPEC_PRECEQU_PH_QBL
37 UNSPEC_PRECEQU_PH_QBR
38 UNSPEC_PRECEQU_PH_QBLA
39 UNSPEC_PRECEQU_PH_QBRA
40 UNSPEC_PRECEU_PH_QBL
41 UNSPEC_PRECEU_PH_QBR
42 UNSPEC_PRECEU_PH_QBLA
43 UNSPEC_PRECEU_PH_QBRA
44 UNSPEC_SHLL
45 UNSPEC_SHLL_S
46 UNSPEC_SHRL_QB
47 UNSPEC_SHRA_PH
48 UNSPEC_SHRA_R
49 UNSPEC_MULEU_S_PH_QBL
50 UNSPEC_MULEU_S_PH_QBR
51 UNSPEC_MULQ_RS_PH
52 UNSPEC_MULEQ_S_W_PHL
53 UNSPEC_MULEQ_S_W_PHR
54 UNSPEC_DPAU_H_QBL
55 UNSPEC_DPAU_H_QBR
56 UNSPEC_DPSU_H_QBL
57 UNSPEC_DPSU_H_QBR
58 UNSPEC_DPAQ_S_W_PH
59 UNSPEC_DPSQ_S_W_PH
60 UNSPEC_MULSAQ_S_W_PH
61 UNSPEC_DPAQ_SA_L_W
62 UNSPEC_DPSQ_SA_L_W
63 UNSPEC_MAQ_S_W_PHL
64 UNSPEC_MAQ_S_W_PHR
65 UNSPEC_MAQ_SA_W_PHL
66 UNSPEC_MAQ_SA_W_PHR
67 UNSPEC_BITREV
68 UNSPEC_INSV
69 UNSPEC_REPL_QB
70 UNSPEC_REPL_PH
71 UNSPEC_CMP_EQ
72 UNSPEC_CMP_LT
73 UNSPEC_CMP_LE
74 UNSPEC_CMPGU_EQ_QB
75 UNSPEC_CMPGU_LT_QB
76 UNSPEC_CMPGU_LE_QB
77 UNSPEC_PICK
78 UNSPEC_PACKRL_PH
79 UNSPEC_EXTR_W
80 UNSPEC_EXTR_R_W
81 UNSPEC_EXTR_RS_W
82 UNSPEC_EXTR_S_H
83 UNSPEC_EXTP
84 UNSPEC_EXTPDP
85 UNSPEC_SHILO
86 UNSPEC_MTHLIP
87 UNSPEC_WRDSP
88 UNSPEC_RDDSP
89 ])
91 (define_constants
92 [(CCDSP_PO_REGNUM 182)
93 (CCDSP_SC_REGNUM 183)
94 (CCDSP_CA_REGNUM 184)
95 (CCDSP_OU_REGNUM 185)
96 (CCDSP_CC_REGNUM 186)
97 (CCDSP_EF_REGNUM 187)])
99 ;; This mode iterator allows si, v2hi, v4qi for all possible modes in DSP ASE.
100 (define_mode_iterator DSP [(SI "ISA_HAS_DSP")
101 (V2HI "ISA_HAS_DSP")
102 (V4QI "ISA_HAS_DSP")])
104 ;; This mode iterator allows v2hi, v4qi for vector/SIMD data.
105 (define_mode_iterator DSPV [(V2HI "ISA_HAS_DSP")
106 (V4QI "ISA_HAS_DSP")])
108 ;; This mode iterator allows si, v2hi for Q31 and V2Q15 fixed-point data.
109 (define_mode_iterator DSPQ [(SI "ISA_HAS_DSP")
110 (V2HI "ISA_HAS_DSP")])
112 ;; DSP instructions use q for fixed-point data, and u for integer in the infix.
113 (define_mode_attr dspfmt1 [(SI "q") (V2HI "q") (V4QI "u")])
115 ;; DSP instructions use nothing for fixed-point data, and u for integer in
116 ;; the infix.
117 (define_mode_attr dspfmt1_1 [(SI "") (V2HI "") (V4QI "u")])
119 ;; DSP instructions use w, ph, qb in the postfix.
120 (define_mode_attr dspfmt2 [(SI "w") (V2HI "ph") (V4QI "qb")])
122 ;; DSP shift masks for SI, V2HI, V4QI.
123 (define_mode_attr dspshift_mask [(SI "0x1f") (V2HI "0xf") (V4QI "0x7")])
125 ;; MIPS DSP ASE Revision 0.98 3/24/2005
126 ;; Table 2-1. MIPS DSP ASE Instructions: Arithmetic
127 ;; ADDQ*
128 (define_insn "add<DSPV:mode>3"
129 [(set (match_operand:DSPV 0 "register_operand" "=d")
130 (plus:DSPV (match_operand:DSPV 1 "register_operand" "d")
131 (match_operand:DSPV 2 "register_operand" "d")))
132 (set (reg:CCDSP CCDSP_OU_REGNUM)
133 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ))]
134 "ISA_HAS_DSP"
135 "add<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2"
136 [(set_attr "type" "dspalu")
137 (set_attr "mode" "SI")])
139 (define_insn "mips_add<DSP:dspfmt1>_s_<DSP:dspfmt2>"
140 [(set (match_operand:DSP 0 "register_operand" "=d")
141 (unspec:DSP [(match_operand:DSP 1 "register_operand" "d")
142 (match_operand:DSP 2 "register_operand" "d")]
143 UNSPEC_ADDQ_S))
144 (set (reg:CCDSP CCDSP_OU_REGNUM)
145 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))]
146 "ISA_HAS_DSP"
147 "add<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2"
148 [(set_attr "type" "dspalusat")
149 (set_attr "mode" "SI")])
151 ;; SUBQ*
152 (define_insn "sub<DSPV:mode>3"
153 [(set (match_operand:DSPV 0 "register_operand" "=d")
154 (minus:DSPV (match_operand:DSPV 1 "register_operand" "d")
155 (match_operand:DSPV 2 "register_operand" "d")))
156 (set (reg:CCDSP CCDSP_OU_REGNUM)
157 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ))]
158 "ISA_HAS_DSP"
159 "sub<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2"
160 [(set_attr "type" "dspalu")
161 (set_attr "mode" "SI")])
163 (define_insn "mips_sub<DSP:dspfmt1>_s_<DSP:dspfmt2>"
164 [(set (match_operand:DSP 0 "register_operand" "=d")
165 (unspec:DSP [(match_operand:DSP 1 "register_operand" "d")
166 (match_operand:DSP 2 "register_operand" "d")]
167 UNSPEC_SUBQ_S))
168 (set (reg:CCDSP CCDSP_OU_REGNUM)
169 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))]
170 "ISA_HAS_DSP"
171 "sub<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2"
172 [(set_attr "type" "dspalusat")
173 (set_attr "mode" "SI")])
175 ;; ADDSC
176 (define_insn "mips_addsc"
177 [(set (match_operand:SI 0 "register_operand" "=d")
178 (unspec:SI [(match_operand:SI 1 "register_operand" "d")
179 (match_operand:SI 2 "register_operand" "d")]
180 UNSPEC_ADDSC))
181 (set (reg:CCDSP CCDSP_CA_REGNUM)
182 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDSC))]
183 "ISA_HAS_DSP"
184 "addsc\t%0,%1,%2"
185 [(set_attr "type" "dspalu")
186 (set_attr "mode" "SI")])
188 ;; ADDWC
189 (define_insn "mips_addwc"
190 [(set (match_operand:SI 0 "register_operand" "=d")
191 (unspec:SI [(match_operand:SI 1 "register_operand" "d")
192 (match_operand:SI 2 "register_operand" "d")
193 (reg:CCDSP CCDSP_CA_REGNUM)]
194 UNSPEC_ADDWC))
195 (set (reg:CCDSP CCDSP_OU_REGNUM)
196 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDWC))]
197 "ISA_HAS_DSP"
198 "addwc\t%0,%1,%2"
199 [(set_attr "type" "dspalu")
200 (set_attr "mode" "SI")])
202 ;; MODSUB
203 (define_insn "mips_modsub"
204 [(set (match_operand:SI 0 "register_operand" "=d")
205 (unspec:SI [(match_operand:SI 1 "register_operand" "d")
206 (match_operand:SI 2 "register_operand" "d")]
207 UNSPEC_MODSUB))]
208 "ISA_HAS_DSP"
209 "modsub\t%0,%1,%2"
210 [(set_attr "type" "dspalu")
211 (set_attr "mode" "SI")])
213 ;; RADDU*
214 (define_insn "mips_raddu_w_qb"
215 [(set (match_operand:SI 0 "register_operand" "=d")
216 (unspec:SI [(match_operand:V4QI 1 "register_operand" "d")]
217 UNSPEC_RADDU_W_QB))]
218 "ISA_HAS_DSP"
219 "raddu.w.qb\t%0,%1"
220 [(set_attr "type" "dspalu")
221 (set_attr "mode" "SI")])
223 ;; ABSQ*
224 (define_insn "mips_absq_s_<DSPQ:dspfmt2>"
225 [(set (match_operand:DSPQ 0 "register_operand" "=d")
226 (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d")]
227 UNSPEC_ABSQ_S))
228 (set (reg:CCDSP CCDSP_OU_REGNUM)
229 (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S))]
230 "ISA_HAS_DSP"
231 "absq_s.<DSPQ:dspfmt2>\t%0,%1"
232 [(set_attr "type" "dspalusat")
233 (set_attr "mode" "SI")])
235 ;; PRECRQ*
236 (define_insn "mips_precrq_qb_ph"
237 [(set (match_operand:V4QI 0 "register_operand" "=d")
238 (unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d")
239 (match_operand:V2HI 2 "register_operand" "d")]
240 UNSPEC_PRECRQ_QB_PH))]
241 "ISA_HAS_DSP"
242 "precrq.qb.ph\t%0,%1,%2"
243 [(set_attr "type" "dspalu")
244 (set_attr "mode" "SI")])
246 (define_insn "mips_precrq_ph_w"
247 [(set (match_operand:V2HI 0 "register_operand" "=d")
248 (unspec:V2HI [(match_operand:SI 1 "register_operand" "d")
249 (match_operand:SI 2 "register_operand" "d")]
250 UNSPEC_PRECRQ_PH_W))]
251 "ISA_HAS_DSP"
252 "precrq.ph.w\t%0,%1,%2"
253 [(set_attr "type" "dspalu")
254 (set_attr "mode" "SI")])
256 (define_insn "mips_precrq_rs_ph_w"
257 [(set (match_operand:V2HI 0 "register_operand" "=d")
258 (unspec:V2HI [(match_operand:SI 1 "register_operand" "d")
259 (match_operand:SI 2 "register_operand" "d")]
260 UNSPEC_PRECRQ_RS_PH_W))
261 (set (reg:CCDSP CCDSP_OU_REGNUM)
262 (unspec:CCDSP [(match_dup 1) (match_dup 2)]
263 UNSPEC_PRECRQ_RS_PH_W))]
264 "ISA_HAS_DSP"
265 "precrq_rs.ph.w\t%0,%1,%2"
266 [(set_attr "type" "dspalu")
267 (set_attr "mode" "SI")])
269 ;; PRECRQU*
270 (define_insn "mips_precrqu_s_qb_ph"
271 [(set (match_operand:V4QI 0 "register_operand" "=d")
272 (unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d")
273 (match_operand:V2HI 2 "register_operand" "d")]
274 UNSPEC_PRECRQU_S_QB_PH))
275 (set (reg:CCDSP CCDSP_OU_REGNUM)
276 (unspec:CCDSP [(match_dup 1) (match_dup 2)]
277 UNSPEC_PRECRQU_S_QB_PH))]
278 "ISA_HAS_DSP"
279 "precrqu_s.qb.ph\t%0,%1,%2"
280 [(set_attr "type" "dspalusat")
281 (set_attr "mode" "SI")])
283 ;; PRECEQ*
284 (define_insn "mips_preceq_w_phl"
285 [(set (match_operand:SI 0 "register_operand" "=d")
286 (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")]
287 UNSPEC_PRECEQ_W_PHL))]
288 "ISA_HAS_DSP"
289 "preceq.w.phl\t%0,%1"
290 [(set_attr "type" "dspalu")
291 (set_attr "mode" "SI")])
293 (define_insn "mips_preceq_w_phr"
294 [(set (match_operand:SI 0 "register_operand" "=d")
295 (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")]
296 UNSPEC_PRECEQ_W_PHR))]
297 "ISA_HAS_DSP"
298 "preceq.w.phr\t%0,%1"
299 [(set_attr "type" "dspalu")
300 (set_attr "mode" "SI")])
302 ;; PRECEQU*
303 (define_insn "mips_precequ_ph_qbl"
304 [(set (match_operand:V2HI 0 "register_operand" "=d")
305 (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
306 UNSPEC_PRECEQU_PH_QBL))]
307 "ISA_HAS_DSP"
308 "precequ.ph.qbl\t%0,%1"
309 [(set_attr "type" "dspalu")
310 (set_attr "mode" "SI")])
312 (define_insn "mips_precequ_ph_qbr"
313 [(set (match_operand:V2HI 0 "register_operand" "=d")
314 (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
315 UNSPEC_PRECEQU_PH_QBR))]
316 "ISA_HAS_DSP"
317 "precequ.ph.qbr\t%0,%1"
318 [(set_attr "type" "dspalu")
319 (set_attr "mode" "SI")])
321 (define_insn "mips_precequ_ph_qbla"
322 [(set (match_operand:V2HI 0 "register_operand" "=d")
323 (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
324 UNSPEC_PRECEQU_PH_QBLA))]
325 "ISA_HAS_DSP"
326 "precequ.ph.qbla\t%0,%1"
327 [(set_attr "type" "dspalu")
328 (set_attr "mode" "SI")])
330 (define_insn "mips_precequ_ph_qbra"
331 [(set (match_operand:V2HI 0 "register_operand" "=d")
332 (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
333 UNSPEC_PRECEQU_PH_QBRA))]
334 "ISA_HAS_DSP"
335 "precequ.ph.qbra\t%0,%1"
336 [(set_attr "type" "dspalu")
337 (set_attr "mode" "SI")])
339 ;; PRECEU*
340 (define_insn "mips_preceu_ph_qbl"
341 [(set (match_operand:V2HI 0 "register_operand" "=d")
342 (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
343 UNSPEC_PRECEU_PH_QBL))]
344 "ISA_HAS_DSP"
345 "preceu.ph.qbl\t%0,%1"
346 [(set_attr "type" "dspalu")
347 (set_attr "mode" "SI")])
349 (define_insn "mips_preceu_ph_qbr"
350 [(set (match_operand:V2HI 0 "register_operand" "=d")
351 (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
352 UNSPEC_PRECEU_PH_QBR))]
353 "ISA_HAS_DSP"
354 "preceu.ph.qbr\t%0,%1"
355 [(set_attr "type" "dspalu")
356 (set_attr "mode" "SI")])
358 (define_insn "mips_preceu_ph_qbla"
359 [(set (match_operand:V2HI 0 "register_operand" "=d")
360 (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
361 UNSPEC_PRECEU_PH_QBLA))]
362 "ISA_HAS_DSP"
363 "preceu.ph.qbla\t%0,%1"
364 [(set_attr "type" "dspalu")
365 (set_attr "mode" "SI")])
367 (define_insn "mips_preceu_ph_qbra"
368 [(set (match_operand:V2HI 0 "register_operand" "=d")
369 (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
370 UNSPEC_PRECEU_PH_QBRA))]
371 "ISA_HAS_DSP"
372 "preceu.ph.qbra\t%0,%1"
373 [(set_attr "type" "dspalu")
374 (set_attr "mode" "SI")])
376 ;; Table 2-2. MIPS DSP ASE Instructions: Shift
377 ;; SHLL*
378 (define_insn "mips_shll_<DSPV:dspfmt2>"
379 [(set (match_operand:DSPV 0 "register_operand" "=d,d")
380 (unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d,d")
381 (match_operand:SI 2 "arith_operand" "I,d")]
382 UNSPEC_SHLL))
383 (set (reg:CCDSP CCDSP_OU_REGNUM)
384 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL))]
385 "ISA_HAS_DSP"
386 {
387 if (which_alternative == 0)
388 {
389 if (INTVAL (operands[2])
390 & ~(unsigned HOST_WIDE_INT) <DSPV:dspshift_mask>)
391 operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPV:dspshift_mask>);
392 return "shll.<DSPV:dspfmt2>\t%0,%1,%2";
393 }
394 return "shllv.<DSPV:dspfmt2>\t%0,%1,%2";
395 }
396 [(set_attr "type" "dspalu")
397 (set_attr "mode" "SI")])
399 (define_insn "mips_shll_s_<DSPQ:dspfmt2>"
400 [(set (match_operand:DSPQ 0 "register_operand" "=d,d")
401 (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d")
402 (match_operand:SI 2 "arith_operand" "I,d")]
403 UNSPEC_SHLL_S))
404 (set (reg:CCDSP CCDSP_OU_REGNUM)
405 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL_S))]
406 "ISA_HAS_DSP"
407 {
408 if (which_alternative == 0)
409 {
410 if (INTVAL (operands[2])
411 & ~(unsigned HOST_WIDE_INT) <DSPQ:dspshift_mask>)
412 operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPQ:dspshift_mask>);
413 return "shll_s.<DSPQ:dspfmt2>\t%0,%1,%2";
414 }
415 return "shllv_s.<DSPQ:dspfmt2>\t%0,%1,%2";
416 }
417 [(set_attr "type" "dspalusat")
418 (set_attr "mode" "SI")])
420 ;; SHRL*
421 (define_insn "mips_shrl_qb"
422 [(set (match_operand:V4QI 0 "register_operand" "=d,d")
423 (unspec:V4QI [(match_operand:V4QI 1 "register_operand" "d,d")
424 (match_operand:SI 2 "arith_operand" "I,d")]
425 UNSPEC_SHRL_QB))]
426 "ISA_HAS_DSP"
427 {
428 if (which_alternative == 0)
429 {
430 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x7)
431 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x7);
432 return "shrl.qb\t%0,%1,%2";
433 }
434 return "shrlv.qb\t%0,%1,%2";
435 }
436 [(set_attr "type" "dspalu")
437 (set_attr "mode" "SI")])
439 ;; SHRA*
440 (define_insn "mips_shra_ph"
441 [(set (match_operand:V2HI 0 "register_operand" "=d,d")
442 (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d,d")
443 (match_operand:SI 2 "arith_operand" "I,d")]
444 UNSPEC_SHRA_PH))]
445 "ISA_HAS_DSP"
446 {
447 if (which_alternative == 0)
448 {
449 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0xf)
450 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xf);
451 return "shra.ph\t%0,%1,%2";
452 }
453 return "shrav.ph\t%0,%1,%2";
454 }
455 [(set_attr "type" "dspalu")
456 (set_attr "mode" "SI")])
458 (define_insn "mips_shra_r_<DSPQ:dspfmt2>"
459 [(set (match_operand:DSPQ 0 "register_operand" "=d,d")
460 (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d")
461 (match_operand:SI 2 "arith_operand" "I,d")]
462 UNSPEC_SHRA_R))]
463 "ISA_HAS_DSP"
464 {
465 if (which_alternative == 0)
466 {
467 if (INTVAL (operands[2])
468 & ~(unsigned HOST_WIDE_INT) <DSPQ:dspshift_mask>)
469 operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPQ:dspshift_mask>);
470 return "shra_r.<DSPQ:dspfmt2>\t%0,%1,%2";
471 }
472 return "shrav_r.<DSPQ:dspfmt2>\t%0,%1,%2";
473 }
474 [(set_attr "type" "dspalu")
475 (set_attr "mode" "SI")])
477 ;; Table 2-3. MIPS DSP ASE Instructions: Multiply
478 ;; MULEU*
479 (define_insn "mips_muleu_s_ph_qbl"
480 [(set (match_operand:V2HI 0 "register_operand" "=d")
481 (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")
482 (match_operand:V2HI 2 "register_operand" "d")]
483 UNSPEC_MULEU_S_PH_QBL))
484 (set (reg:CCDSP CCDSP_OU_REGNUM)
485 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBL))
486 (clobber (match_scratch:DI 3 "=x"))]
487 "ISA_HAS_DSP"
488 "muleu_s.ph.qbl\t%0,%1,%2"
489 [(set_attr "type" "imul3")
490 (set_attr "mode" "SI")])
492 (define_insn "mips_muleu_s_ph_qbr"
493 [(set (match_operand:V2HI 0 "register_operand" "=d")
494 (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")
495 (match_operand:V2HI 2 "register_operand" "d")]
496 UNSPEC_MULEU_S_PH_QBR))
497 (set (reg:CCDSP CCDSP_OU_REGNUM)
498 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBR))
499 (clobber (match_scratch:DI 3 "=x"))]
500 "ISA_HAS_DSP"
501 "muleu_s.ph.qbr\t%0,%1,%2"
502 [(set_attr "type" "imul3")
503 (set_attr "mode" "SI")])
505 ;; MULQ*
506 (define_insn "mips_mulq_rs_ph"
507 [(set (match_operand:V2HI 0 "register_operand" "=d")
508 (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d")
509 (match_operand:V2HI 2 "register_operand" "d")]
510 UNSPEC_MULQ_RS_PH))
511 (set (reg:CCDSP CCDSP_OU_REGNUM)
512 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH))
513 (clobber (match_scratch:DI 3 "=x"))]
514 "ISA_HAS_DSP"
515 "mulq_rs.ph\t%0,%1,%2"
516 [(set_attr "type" "imul3")
517 (set_attr "mode" "SI")])
519 ;; MULEQ*
520 (define_insn "mips_muleq_s_w_phl"
521 [(set (match_operand:SI 0 "register_operand" "=d")
522 (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")
523 (match_operand:V2HI 2 "register_operand" "d")]
524 UNSPEC_MULEQ_S_W_PHL))
525 (set (reg:CCDSP CCDSP_OU_REGNUM)
526 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHL))
527 (clobber (match_scratch:DI 3 "=x"))]
528 "ISA_HAS_DSP"
529 "muleq_s.w.phl\t%0,%1,%2"
530 [(set_attr "type" "imul3")
531 (set_attr "mode" "SI")])
533 (define_insn "mips_muleq_s_w_phr"
534 [(set (match_operand:SI 0 "register_operand" "=d")
535 (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")
536 (match_operand:V2HI 2 "register_operand" "d")]
537 UNSPEC_MULEQ_S_W_PHR))
538 (set (reg:CCDSP CCDSP_OU_REGNUM)
539 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHR))
540 (clobber (match_scratch:DI 3 "=x"))]
541 "ISA_HAS_DSP"
542 "muleq_s.w.phr\t%0,%1,%2"
543 [(set_attr "type" "imul3")
544 (set_attr "mode" "SI")])
546 ;; DPAU*
547 (define_insn "mips_dpau_h_qbl"
548 [(set (match_operand:DI 0 "register_operand" "=a")
549 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
550 (match_operand:V4QI 2 "register_operand" "d")
551 (match_operand:V4QI 3 "register_operand" "d")]
552 UNSPEC_DPAU_H_QBL))]
553 "ISA_HAS_DSP && !TARGET_64BIT"
554 "dpau.h.qbl\t%q0,%2,%3"
555 [(set_attr "type" "dspmac")
556 (set_attr "accum_in" "1")
557 (set_attr "mode" "SI")])
559 (define_insn "mips_dpau_h_qbr"
560 [(set (match_operand:DI 0 "register_operand" "=a")
561 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
562 (match_operand:V4QI 2 "register_operand" "d")
563 (match_operand:V4QI 3 "register_operand" "d")]
564 UNSPEC_DPAU_H_QBR))]
565 "ISA_HAS_DSP && !TARGET_64BIT"
566 "dpau.h.qbr\t%q0,%2,%3"
567 [(set_attr "type" "dspmac")
568 (set_attr "accum_in" "1")
569 (set_attr "mode" "SI")])
571 ;; DPSU*
572 (define_insn "mips_dpsu_h_qbl"
573 [(set (match_operand:DI 0 "register_operand" "=a")
574 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
575 (match_operand:V4QI 2 "register_operand" "d")
576 (match_operand:V4QI 3 "register_operand" "d")]
577 UNSPEC_DPSU_H_QBL))]
578 "ISA_HAS_DSP && !TARGET_64BIT"
579 "dpsu.h.qbl\t%q0,%2,%3"
580 [(set_attr "type" "dspmac")
581 (set_attr "accum_in" "1")
582 (set_attr "mode" "SI")])
584 (define_insn "mips_dpsu_h_qbr"
585 [(set (match_operand:DI 0 "register_operand" "=a")
586 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
587 (match_operand:V4QI 2 "register_operand" "d")
588 (match_operand:V4QI 3 "register_operand" "d")]
589 UNSPEC_DPSU_H_QBR))]
590 "ISA_HAS_DSP && !TARGET_64BIT"
591 "dpsu.h.qbr\t%q0,%2,%3"
592 [(set_attr "type" "dspmac")
593 (set_attr "accum_in" "1")
594 (set_attr "mode" "SI")])
596 ;; DPAQ*
597 (define_insn "mips_dpaq_s_w_ph"
598 [(set (match_operand:DI 0 "register_operand" "=a")
599 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
600 (match_operand:V2HI 2 "register_operand" "d")
601 (match_operand:V2HI 3 "register_operand" "d")]
602 UNSPEC_DPAQ_S_W_PH))
603 (set (reg:CCDSP CCDSP_OU_REGNUM)
604 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
605 UNSPEC_DPAQ_S_W_PH))]
606 "ISA_HAS_DSP && !TARGET_64BIT"
607 "dpaq_s.w.ph\t%q0,%2,%3"
608 [(set_attr "type" "dspmac")
609 (set_attr "accum_in" "1")
610 (set_attr "mode" "SI")])
612 ;; DPSQ*
613 (define_insn "mips_dpsq_s_w_ph"
614 [(set (match_operand:DI 0 "register_operand" "=a")
615 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
616 (match_operand:V2HI 2 "register_operand" "d")
617 (match_operand:V2HI 3 "register_operand" "d")]
618 UNSPEC_DPSQ_S_W_PH))
619 (set (reg:CCDSP CCDSP_OU_REGNUM)
620 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
621 UNSPEC_DPSQ_S_W_PH))]
622 "ISA_HAS_DSP && !TARGET_64BIT"
623 "dpsq_s.w.ph\t%q0,%2,%3"
624 [(set_attr "type" "dspmac")
625 (set_attr "accum_in" "1")
626 (set_attr "mode" "SI")])
628 ;; MULSAQ*
629 (define_insn "mips_mulsaq_s_w_ph"
630 [(set (match_operand:DI 0 "register_operand" "=a")
631 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
632 (match_operand:V2HI 2 "register_operand" "d")
633 (match_operand:V2HI 3 "register_operand" "d")]
634 UNSPEC_MULSAQ_S_W_PH))
635 (set (reg:CCDSP CCDSP_OU_REGNUM)
636 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
637 UNSPEC_MULSAQ_S_W_PH))]
638 "ISA_HAS_DSP && !TARGET_64BIT"
639 "mulsaq_s.w.ph\t%q0,%2,%3"
640 [(set_attr "type" "dspmac")
641 (set_attr "accum_in" "1")
642 (set_attr "mode" "SI")])
644 ;; DPAQ*
645 (define_insn "mips_dpaq_sa_l_w"
646 [(set (match_operand:DI 0 "register_operand" "=a")
647 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
648 (match_operand:SI 2 "register_operand" "d")
649 (match_operand:SI 3 "register_operand" "d")]
650 UNSPEC_DPAQ_SA_L_W))
651 (set (reg:CCDSP CCDSP_OU_REGNUM)
652 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
653 UNSPEC_DPAQ_SA_L_W))]
654 "ISA_HAS_DSP && !TARGET_64BIT"
655 "dpaq_sa.l.w\t%q0,%2,%3"
656 [(set_attr "type" "dspmacsat")
657 (set_attr "accum_in" "1")
658 (set_attr "mode" "SI")])
660 ;; DPSQ*
661 (define_insn "mips_dpsq_sa_l_w"
662 [(set (match_operand:DI 0 "register_operand" "=a")
663 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
664 (match_operand:SI 2 "register_operand" "d")
665 (match_operand:SI 3 "register_operand" "d")]
666 UNSPEC_DPSQ_SA_L_W))
667 (set (reg:CCDSP CCDSP_OU_REGNUM)
668 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
669 UNSPEC_DPSQ_SA_L_W))]
670 "ISA_HAS_DSP && !TARGET_64BIT"
671 "dpsq_sa.l.w\t%q0,%2,%3"
672 [(set_attr "type" "dspmacsat")
673 (set_attr "accum_in" "1")
674 (set_attr "mode" "SI")])
676 ;; MAQ*
677 (define_insn "mips_maq_s_w_phl"
678 [(set (match_operand:DI 0 "register_operand" "=a")
679 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
680 (match_operand:V2HI 2 "register_operand" "d")
681 (match_operand:V2HI 3 "register_operand" "d")]
682 UNSPEC_MAQ_S_W_PHL))
683 (set (reg:CCDSP CCDSP_OU_REGNUM)
684 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
685 UNSPEC_MAQ_S_W_PHL))]
686 "ISA_HAS_DSP && !TARGET_64BIT"
687 "maq_s.w.phl\t%q0,%2,%3"
688 [(set_attr "type" "dspmac")
689 (set_attr "accum_in" "1")
690 (set_attr "mode" "SI")])
692 (define_insn "mips_maq_s_w_phr"
693 [(set (match_operand:DI 0 "register_operand" "=a")
694 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
695 (match_operand:V2HI 2 "register_operand" "d")
696 (match_operand:V2HI 3 "register_operand" "d")]
697 UNSPEC_MAQ_S_W_PHR))
698 (set (reg:CCDSP CCDSP_OU_REGNUM)
699 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
700 UNSPEC_MAQ_S_W_PHR))]
701 "ISA_HAS_DSP && !TARGET_64BIT"
702 "maq_s.w.phr\t%q0,%2,%3"
703 [(set_attr "type" "dspmac")
704 (set_attr "accum_in" "1")
705 (set_attr "mode" "SI")])
707 ;; MAQ_SA*
708 (define_insn "mips_maq_sa_w_phl"
709 [(set (match_operand:DI 0 "register_operand" "=a")
710 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
711 (match_operand:V2HI 2 "register_operand" "d")
712 (match_operand:V2HI 3 "register_operand" "d")]
713 UNSPEC_MAQ_SA_W_PHL))
714 (set (reg:CCDSP CCDSP_OU_REGNUM)
715 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
716 UNSPEC_MAQ_SA_W_PHL))]
717 "ISA_HAS_DSP && !TARGET_64BIT"
718 "maq_sa.w.phl\t%q0,%2,%3"
719 [(set_attr "type" "dspmacsat")
720 (set_attr "accum_in" "1")
721 (set_attr "mode" "SI")])
723 (define_insn "mips_maq_sa_w_phr"
724 [(set (match_operand:DI 0 "register_operand" "=a")
725 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
726 (match_operand:V2HI 2 "register_operand" "d")
727 (match_operand:V2HI 3 "register_operand" "d")]
728 UNSPEC_MAQ_SA_W_PHR))
729 (set (reg:CCDSP CCDSP_OU_REGNUM)
730 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
731 UNSPEC_MAQ_SA_W_PHR))]
732 "ISA_HAS_DSP && !TARGET_64BIT"
733 "maq_sa.w.phr\t%q0,%2,%3"
734 [(set_attr "type" "dspmacsat")
735 (set_attr "accum_in" "1")
736 (set_attr "mode" "SI")])
738 ;; Table 2-4. MIPS DSP ASE Instructions: General Bit/Manipulation
739 ;; BITREV
740 (define_insn "mips_bitrev"
741 [(set (match_operand:SI 0 "register_operand" "=d")
742 (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
743 UNSPEC_BITREV))]
744 "ISA_HAS_DSP"
745 "bitrev\t%0,%1"
746 [(set_attr "type" "dspalu")
747 (set_attr "mode" "SI")])
749 ;; INSV
750 (define_insn "mips_insv"
751 [(set (match_operand:SI 0 "register_operand" "=d")
752 (unspec:SI [(match_operand:SI 1 "register_operand" "0")
753 (match_operand:SI 2 "register_operand" "d")
754 (reg:CCDSP CCDSP_SC_REGNUM)
755 (reg:CCDSP CCDSP_PO_REGNUM)]
756 UNSPEC_INSV))]
757 "ISA_HAS_DSP"
758 "insv\t%0,%2"
759 [(set_attr "type" "dspalu")
760 (set_attr "mode" "SI")])
762 ;; REPL*
763 (define_insn "mips_repl_qb"
764 [(set (match_operand:V4QI 0 "register_operand" "=d,d")
765 (unspec:V4QI [(match_operand:SI 1 "arith_operand" "I,d")]
766 UNSPEC_REPL_QB))]
767 "ISA_HAS_DSP"
768 {
769 if (which_alternative == 0)
770 {
771 if (INTVAL (operands[1]) & ~(unsigned HOST_WIDE_INT) 0xff)
772 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
773 return "repl.qb\t%0,%1";
774 }
775 return "replv.qb\t%0,%1";
776 }
777 [(set_attr "type" "dspalu")
778 (set_attr "mode" "SI")])
780 (define_insn "mips_repl_ph"
781 [(set (match_operand:V2HI 0 "register_operand" "=d,d")
782 (unspec:V2HI [(match_operand:SI 1 "reg_imm10_operand" "YB,d")]
783 UNSPEC_REPL_PH))]
784 "ISA_HAS_DSP"
785 "@
786 repl.ph\t%0,%1
787 replv.ph\t%0,%1"
788 [(set_attr "type" "dspalu")
789 (set_attr "mode" "SI")])
791 ;; Table 2-5. MIPS DSP ASE Instructions: Compare-Pick
792 ;; CMPU.* CMP.*
793 (define_insn "mips_cmp<DSPV:dspfmt1_1>_eq_<DSPV:dspfmt2>"
794 [(set (reg:CCDSP CCDSP_CC_REGNUM)
795 (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d")
796 (match_operand:DSPV 1 "register_operand" "d")
797 (reg:CCDSP CCDSP_CC_REGNUM)]
798 UNSPEC_CMP_EQ))]
799 "ISA_HAS_DSP"
800 "cmp<DSPV:dspfmt1_1>.eq.<DSPV:dspfmt2>\t%0,%1"
801 [(set_attr "type" "dspalu")
802 (set_attr "mode" "SI")])
804 (define_insn "mips_cmp<DSPV:dspfmt1_1>_lt_<DSPV:dspfmt2>"
805 [(set (reg:CCDSP CCDSP_CC_REGNUM)
806 (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d")
807 (match_operand:DSPV 1 "register_operand" "d")
808 (reg:CCDSP CCDSP_CC_REGNUM)]
809 UNSPEC_CMP_LT))]
810 "ISA_HAS_DSP"
811 "cmp<DSPV:dspfmt1_1>.lt.<DSPV:dspfmt2>\t%0,%1"
812 [(set_attr "type" "dspalu")
813 (set_attr "mode" "SI")])
815 (define_insn "mips_cmp<DSPV:dspfmt1_1>_le_<DSPV:dspfmt2>"
816 [(set (reg:CCDSP CCDSP_CC_REGNUM)
817 (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d")
818 (match_operand:DSPV 1 "register_operand" "d")
819 (reg:CCDSP CCDSP_CC_REGNUM)]
820 UNSPEC_CMP_LE))]
821 "ISA_HAS_DSP"
822 "cmp<DSPV:dspfmt1_1>.le.<DSPV:dspfmt2>\t%0,%1"
823 [(set_attr "type" "dspalu")
824 (set_attr "mode" "SI")])
826 (define_insn "mips_cmpgu_eq_qb"
827 [(set (match_operand:SI 0 "register_operand" "=d")
828 (unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
829 (match_operand:V4QI 2 "register_operand" "d")]
830 UNSPEC_CMPGU_EQ_QB))]
831 "ISA_HAS_DSP"
832 "cmpgu.eq.qb\t%0,%1,%2"
833 [(set_attr "type" "dspalu")
834 (set_attr "mode" "SI")])
836 (define_insn "mips_cmpgu_lt_qb"
837 [(set (match_operand:SI 0 "register_operand" "=d")
838 (unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
839 (match_operand:V4QI 2 "register_operand" "d")]
840 UNSPEC_CMPGU_LT_QB))]
841 "ISA_HAS_DSP"
842 "cmpgu.lt.qb\t%0,%1,%2"
843 [(set_attr "type" "dspalu")
844 (set_attr "mode" "SI")])
846 (define_insn "mips_cmpgu_le_qb"
847 [(set (match_operand:SI 0 "register_operand" "=d")
848 (unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
849 (match_operand:V4QI 2 "register_operand" "d")]
850 UNSPEC_CMPGU_LE_QB))]
851 "ISA_HAS_DSP"
852 "cmpgu.le.qb\t%0,%1,%2"
853 [(set_attr "type" "dspalu")
854 (set_attr "mode" "SI")])
856 ;; PICK*
857 (define_insn "mips_pick_<DSPV:dspfmt2>"
858 [(set (match_operand:DSPV 0 "register_operand" "=d")
859 (unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d")
860 (match_operand:DSPV 2 "register_operand" "d")
861 (reg:CCDSP CCDSP_CC_REGNUM)]
862 UNSPEC_PICK))]
863 "ISA_HAS_DSP"
864 "pick.<DSPV:dspfmt2>\t%0,%1,%2"
865 [(set_attr "type" "dspalu")
866 (set_attr "mode" "SI")])
868 ;; PACKRL*
869 (define_insn "mips_packrl_ph"
870 [(set (match_operand:V2HI 0 "register_operand" "=d")
871 (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d")
872 (match_operand:V2HI 2 "register_operand" "d")]
873 UNSPEC_PACKRL_PH))]
874 "ISA_HAS_DSP"
875 "packrl.ph\t%0,%1,%2"
876 [(set_attr "type" "dspalu")
877 (set_attr "mode" "SI")])
879 ;; Table 2-6. MIPS DSP ASE Instructions: Accumulator and DSPControl Access
880 ;; EXTR*
881 (define_insn "mips_extr_w"
882 [(set (match_operand:SI 0 "register_operand" "=d,d")
883 (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
884 (match_operand:SI 2 "arith_operand" "I,d")]
885 UNSPEC_EXTR_W))
886 (set (reg:CCDSP CCDSP_OU_REGNUM)
887 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_W))]
888 "ISA_HAS_DSP && !TARGET_64BIT"
889 {
890 if (which_alternative == 0)
891 {
892 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
893 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
894 return "extr.w\t%0,%q1,%2";
895 }
896 return "extrv.w\t%0,%q1,%2";
897 }
898 [(set_attr "type" "accext")
899 (set_attr "mode" "SI")])
901 (define_insn "mips_extr_r_w"
902 [(set (match_operand:SI 0 "register_operand" "=d,d")
903 (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
904 (match_operand:SI 2 "arith_operand" "I,d")]
905 UNSPEC_EXTR_R_W))
906 (set (reg:CCDSP CCDSP_OU_REGNUM)
907 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_R_W))]
908 "ISA_HAS_DSP && !TARGET_64BIT"
909 {
910 if (which_alternative == 0)
911 {
912 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
913 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
914 return "extr_r.w\t%0,%q1,%2";
915 }
916 return "extrv_r.w\t%0,%q1,%2";
917 }
918 [(set_attr "type" "accext")
919 (set_attr "mode" "SI")])
921 (define_insn "mips_extr_rs_w"
922 [(set (match_operand:SI 0 "register_operand" "=d,d")
923 (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
924 (match_operand:SI 2 "arith_operand" "I,d")]
925 UNSPEC_EXTR_RS_W))
926 (set (reg:CCDSP CCDSP_OU_REGNUM)
927 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_RS_W))]
928 "ISA_HAS_DSP && !TARGET_64BIT"
929 {
930 if (which_alternative == 0)
931 {
932 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
933 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
934 return "extr_rs.w\t%0,%q1,%2";
935 }
936 return "extrv_rs.w\t%0,%q1,%2";
937 }
938 [(set_attr "type" "accext")
939 (set_attr "mode" "SI")])
941 ;; EXTR*_S.H
942 (define_insn "mips_extr_s_h"
943 [(set (match_operand:SI 0 "register_operand" "=d,d")
944 (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
945 (match_operand:SI 2 "arith_operand" "I,d")]
946 UNSPEC_EXTR_S_H))
947 (set (reg:CCDSP CCDSP_OU_REGNUM)
948 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_S_H))]
949 "ISA_HAS_DSP && !TARGET_64BIT"
950 {
951 if (which_alternative == 0)
952 {
953 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
954 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
955 return "extr_s.h\t%0,%q1,%2";
956 }
957 return "extrv_s.h\t%0,%q1,%2";
958 }
959 [(set_attr "type" "accext")
960 (set_attr "mode" "SI")])
962 ;; EXTP*
963 (define_insn "mips_extp"
964 [(set (match_operand:SI 0 "register_operand" "=d,d")
965 (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
966 (match_operand:SI 2 "arith_operand" "I,d")
967 (reg:CCDSP CCDSP_PO_REGNUM)]
968 UNSPEC_EXTP))
969 (set (reg:CCDSP CCDSP_EF_REGNUM)
970 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTP))]
971 "ISA_HAS_DSP && !TARGET_64BIT"
972 {
973 if (which_alternative == 0)
974 {
975 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
976 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
977 return "extp\t%0,%q1,%2";
978 }
979 return "extpv\t%0,%q1,%2";
980 }
981 [(set_attr "type" "accext")
982 (set_attr "mode" "SI")])
984 (define_insn "mips_extpdp"
985 [(set (match_operand:SI 0 "register_operand" "=d,d")
986 (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
987 (match_operand:SI 2 "arith_operand" "I,d")
988 (reg:CCDSP CCDSP_PO_REGNUM)]
989 UNSPEC_EXTPDP))
990 (set (reg:CCDSP CCDSP_PO_REGNUM)
991 (unspec:CCDSP [(match_dup 1) (match_dup 2)
992 (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_EXTPDP))
993 (set (reg:CCDSP CCDSP_EF_REGNUM)
994 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTPDP))]
995 "ISA_HAS_DSP && !TARGET_64BIT"
996 {
997 if (which_alternative == 0)
998 {
999 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
1000 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
1001 return "extpdp\t%0,%q1,%2";
1002 }
1003 return "extpdpv\t%0,%q1,%2";
1004 }
1005 [(set_attr "type" "accext")
1006 (set_attr "mode" "SI")])
1008 ;; SHILO*
1009 (define_insn "mips_shilo"
1010 [(set (match_operand:DI 0 "register_operand" "=a,a")
1011 (unspec:DI [(match_operand:DI 1 "register_operand" "0,0")
1012 (match_operand:SI 2 "arith_operand" "I,d")]
1013 UNSPEC_SHILO))]
1014 "ISA_HAS_DSP && !TARGET_64BIT"
1015 {
1016 if (which_alternative == 0)
1017 {
1018 if (INTVAL (operands[2]) < -32 || INTVAL (operands[2]) > 31)
1019 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
1020 return "shilo\t%q0,%2";
1021 }
1022 return "shilov\t%q0,%2";
1023 }
1024 [(set_attr "type" "accmod")
1025 (set_attr "mode" "SI")])
1027 ;; MTHLIP*
1028 (define_insn "mips_mthlip"
1029 [(set (match_operand:DI 0 "register_operand" "=a")
1030 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
1031 (match_operand:SI 2 "register_operand" "d")
1032 (reg:CCDSP CCDSP_PO_REGNUM)]
1033 UNSPEC_MTHLIP))
1034 (set (reg:CCDSP CCDSP_PO_REGNUM)
1035 (unspec:CCDSP [(match_dup 1) (match_dup 2)
1036 (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_MTHLIP))]
1037 "ISA_HAS_DSP && !TARGET_64BIT"
1038 "mthlip\t%2,%q0"
1039 [(set_attr "type" "accmod")
1040 (set_attr "mode" "SI")])
1042 ;; WRDSP
1043 (define_insn "mips_wrdsp"
1044 [(set (reg:CCDSP CCDSP_PO_REGNUM)
1045 (unspec:CCDSP [(match_operand:SI 0 "register_operand" "d")
1046 (match_operand:SI 1 "const_uimm6_operand" "YA")]
1047 UNSPEC_WRDSP))
1048 (set (reg:CCDSP CCDSP_SC_REGNUM)
1049 (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
1050 (set (reg:CCDSP CCDSP_CA_REGNUM)
1051 (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
1052 (set (reg:CCDSP CCDSP_OU_REGNUM)
1053 (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
1054 (set (reg:CCDSP CCDSP_CC_REGNUM)
1055 (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
1056 (set (reg:CCDSP CCDSP_EF_REGNUM)
1057 (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))]
1058 "ISA_HAS_DSP"
1059 "wrdsp\t%0,%1"
1060 [(set_attr "type" "dspalu")
1061 (set_attr "mode" "SI")])
1063 ;; RDDSP
1064 (define_insn "mips_rddsp"
1065 [(set (match_operand:SI 0 "register_operand" "=d")
1066 (unspec:SI [(match_operand:SI 1 "const_uimm6_operand" "YA")
1067 (reg:CCDSP CCDSP_PO_REGNUM)
1068 (reg:CCDSP CCDSP_SC_REGNUM)
1069 (reg:CCDSP CCDSP_CA_REGNUM)
1070 (reg:CCDSP CCDSP_OU_REGNUM)
1071 (reg:CCDSP CCDSP_CC_REGNUM)
1072 (reg:CCDSP CCDSP_EF_REGNUM)]
1073 UNSPEC_RDDSP))]
1074 "ISA_HAS_DSP"
1075 "rddsp\t%0,%1"
1076 [(set_attr "type" "dspalu")
1077 (set_attr "mode" "SI")])
1079 ;; Table 2-7. MIPS DSP ASE Instructions: Indexed-Load
1080 ;; L*X
1081 (define_expand "mips_lbux"
1082 [(match_operand:SI 0 "register_operand")
1083 (match_operand 1 "pmode_register_operand")
1084 (match_operand:SI 2 "register_operand")]
1085 "ISA_HAS_DSP"
1086 {
1087 operands[2] = convert_to_mode (Pmode, operands[2], false);
1088 emit_insn (PMODE_INSN (gen_mips_lbux_extsi,
1089 (operands[0], operands[1], operands[2])));
1090 DONE;
1091 })
1093 (define_insn "mips_l<SHORT:size><u>x_ext<GPR:mode>_<P:mode>"
1094 [(set (match_operand:GPR 0 "register_operand" "=d")
1095 (any_extend:GPR
1096 (mem:SHORT (plus:P (match_operand:P 1 "register_operand" "d")
1097 (match_operand:P 2 "register_operand" "d")))))]
1098 "ISA_HAS_L<SHORT:SIZE><U>X"
1099 "l<SHORT:size><u>x\t%0,%2(%1)"
1100 [(set_attr "type" "load")
1101 (set_attr "mode" "<GPR:MODE>")])
1103 (define_expand "mips_lhx"
1104 [(match_operand:SI 0 "register_operand")
1105 (match_operand 1 "pmode_register_operand")
1106 (match_operand:SI 2 "register_operand")]
1107 "ISA_HAS_DSP"
1108 {
1109 operands[2] = convert_to_mode (Pmode, operands[2], false);
1110 emit_insn (PMODE_INSN (gen_mips_lhx_extsi,
1111 (operands[0], operands[1], operands[2])));
1112 DONE;
1113 })
1115 (define_expand "mips_l<size>x"
1116 [(match_operand:GPR 0 "register_operand")
1117 (match_operand 1 "pmode_register_operand")
1118 (match_operand:SI 2 "register_operand")]
1119 "ISA_HAS_DSP"
1120 {
1121 operands[2] = convert_to_mode (Pmode, operands[2], false);
1122 emit_insn (PMODE_INSN (gen_mips_l<size>x,
1123 (operands[0], operands[1], operands[2])));
1124 DONE;
1125 })
1127 (define_insn "mips_l<GPR:size>x_<P:mode>"
1128 [(set (match_operand:GPR 0 "register_operand" "=d")
1129 (mem:GPR (plus:P (match_operand:P 1 "register_operand" "d")
1130 (match_operand:P 2 "register_operand" "d"))))]
1131 "ISA_HAS_L<GPR:SIZE>X"
1132 "l<GPR:size>x\t%0,%2(%1)"
1133 [(set_attr "type" "load")
1134 (set_attr "mode" "<GPR:MODE>")])
1136 (define_insn "*mips_lw<u>x_<P:mode>_ext"
1137 [(set (match_operand:DI 0 "register_operand" "=d")
1138 (any_extend:DI
1139 (mem:SI (plus:P (match_operand:P 1 "register_operand" "d")
1140 (match_operand:P 2 "register_operand" "d")))))]
1141 "ISA_HAS_LW<U>X && TARGET_64BIT"
1142 "lw<u>x\t%0,%2(%1)"
1143 [(set_attr "type" "load")
1144 (set_attr "mode" "DI")])
1146 ;; Table 2-8. MIPS DSP ASE Instructions: Branch
1147 ;; BPOSGE32
1148 (define_insn "mips_bposge"
1149 [(set (pc)
1150 (if_then_else (ge (reg:CCDSP CCDSP_PO_REGNUM)
1151 (match_operand:SI 1 "immediate_operand" "I"))
1152 (label_ref (match_operand 0 "" ""))
1153 (pc)))]
1154 "ISA_HAS_DSP"
1155 "%*bposge%1\t%0%/"
1156 [(set_attr "type" "branch")])
1158 (define_expand "mips_madd<u>"
1159 [(set (match_operand:DI 0 "register_operand")
1160 (plus:DI
1161 (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
1162 (any_extend:DI (match_operand:SI 3 "register_operand")))
1163 (match_operand:DI 1 "register_operand")))]
1164 "ISA_HAS_DSP && !TARGET_64BIT")
1166 (define_expand "mips_msub<u>"
1167 [(set (match_operand:DI 0 "register_operand")
1168 (minus:DI
1169 (match_operand:DI 1 "register_operand")
1170 (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
1171 (any_extend:DI (match_operand:SI 3 "register_operand")))))]
1172 "ISA_HAS_DSP && !TARGET_64BIT")