1 /* LRA (local register allocator) driver and LRA utilities.
2 Copyright (C) 2010-2013 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* The Local Register Allocator (LRA) is a replacement of former
23 reload pass. It is focused to simplify code solving the reload
24 pass tasks, to make the code maintenance easier, and to implement new
25 perspective optimizations.
27 The major LRA design solutions are:
28 o division small manageable, separated sub-tasks
29 o reflection of all transformations and decisions in RTL as more
31 o insn constraints as a primary source of the info (minimizing
32 number of target-depended macros/hooks)
34 In brief LRA works by iterative insn process with the final goal is
35 to satisfy all insn and address constraints:
36 o New reload insns (in brief reloads) and reload pseudos might be
38 o Some pseudos might be spilled to assign hard registers to
40 o Changing spilled pseudos to stack memory or their equivalences;
41 o Allocation stack memory changes the address displacement and
42 new iteration is needed.
44 Here is block diagram of LRA passes:
46 ------------------------
47 --------------- | Undo inheritance for | ---------------
48 | Memory-memory | | spilled pseudos, | | New (and old) |
49 | move coalesce |<---| splits for pseudos got |<-- | pseudos |
50 --------------- | the same hard regs, | | assignment |
51 Start | | and optional reloads | ---------------
52 | | ------------------------ ^
53 V | ---------------- |
54 ----------- V | Update virtual | |
55 | Remove |----> ------------>| register | |
56 | scratches | ^ | displacements | |
57 ----------- | ---------------- |
60 ---------------- No ------------ pseudos -------------------
61 | Spilled pseudo | change |Constraints:| or insns | Inheritance/split |
62 | to memory |<-------| RTL |--------->| transformations |
63 | substitution | | transfor- | | in EBB scope |
64 ---------------- | mations | -------------------
67 -------------------------
68 | Hard regs substitution, |
69 | devirtalization, and |------> Finish
70 | restoring scratches got |
72 -------------------------
74 To speed up the process:
75 o We process only insns affected by changes on previous
77 o We don't use DFA-infrastructure because it results in much slower
78 compiler speed than a special IR described below does;
79 o We use a special insn representation for quick access to insn
80 info which is always *synchronized* with the current RTL;
81 o Insn IR is minimized by memory. It is divided on three parts:
82 o one specific for each insn in RTL (only operand locations);
83 o one common for all insns in RTL with the same insn code
84 (different operand attributes from machine descriptions);
85 o one oriented for maintenance of live info (list of pseudos).
87 o all insns where the pseudo is referenced;
88 o live info (conflicting hard regs, live ranges, # of
90 o data used for assigning (preferred hard regs, costs etc).
92 This file contains LRA driver, LRA utility functions and data, and
93 code for dealing with scratches. */
97 #include "coretypes.h"
99 #include "hard-reg-set.h"
103 #include "insn-config.h"
104 #include "insn-codes.h"
107 #include "addresses.h"
109 #include "function.h"
111 #include "basic-block.h"
113 #include "tree-pass.h"
121 /* Hard registers currently not available for allocation. It can
122 changed after some hard registers become not eliminable. */
123 HARD_REG_SET lra_no_alloc_regs
;
125 static int get_new_reg_value (void);
126 static void expand_reg_info (void);
127 static void invalidate_insn_recog_data (int);
128 static int get_insn_freq (rtx
);
129 static void invalidate_insn_data_regno_info (lra_insn_recog_data_t
, rtx
, int);
131 /* Expand all regno related info needed for LRA. */
133 expand_reg_data (int old
)
137 ira_expand_reg_equiv ();
138 for (int i
= (int) max_reg_num () - 1; i
>= old
; i
--)
139 lra_change_class (i
, ALL_REGS
, " Set", true);
142 /* Create and return a new reg of ORIGINAL mode. If ORIGINAL is NULL
143 or of VOIDmode, use MD_MODE for the new reg. Initialize its
144 register class to RCLASS. Print message about assigning class
145 RCLASS containing new register name TITLE unless it is NULL. Use
146 attributes of ORIGINAL if it is a register. The created register
147 will have unique held value. */
149 lra_create_new_reg_with_unique_value (enum machine_mode md_mode
, rtx original
,
150 enum reg_class rclass
, const char *title
)
152 enum machine_mode mode
;
155 if (original
== NULL_RTX
|| (mode
= GET_MODE (original
)) == VOIDmode
)
157 lra_assert (mode
!= VOIDmode
);
158 new_reg
= gen_reg_rtx (mode
);
159 if (original
== NULL_RTX
|| ! REG_P (original
))
161 if (lra_dump_file
!= NULL
)
162 fprintf (lra_dump_file
, " Creating newreg=%i", REGNO (new_reg
));
166 if (ORIGINAL_REGNO (original
) >= FIRST_PSEUDO_REGISTER
)
167 ORIGINAL_REGNO (new_reg
) = ORIGINAL_REGNO (original
);
168 REG_USERVAR_P (new_reg
) = REG_USERVAR_P (original
);
169 REG_POINTER (new_reg
) = REG_POINTER (original
);
170 REG_ATTRS (new_reg
) = REG_ATTRS (original
);
171 if (lra_dump_file
!= NULL
)
172 fprintf (lra_dump_file
, " Creating newreg=%i from oldreg=%i",
173 REGNO (new_reg
), REGNO (original
));
175 if (lra_dump_file
!= NULL
)
178 fprintf (lra_dump_file
, ", assigning class %s to%s%s r%d",
179 reg_class_names
[rclass
], *title
== '\0' ? "" : " ",
180 title
, REGNO (new_reg
));
181 fprintf (lra_dump_file
, "\n");
183 expand_reg_data (max_reg_num ());
184 setup_reg_classes (REGNO (new_reg
), rclass
, NO_REGS
, rclass
);
188 /* Analogous to the previous function but also inherits value of
191 lra_create_new_reg (enum machine_mode md_mode
, rtx original
,
192 enum reg_class rclass
, const char *title
)
197 = lra_create_new_reg_with_unique_value (md_mode
, original
, rclass
, title
);
198 if (original
!= NULL_RTX
&& REG_P (original
))
199 lra_assign_reg_val (REGNO (original
), REGNO (new_reg
));
203 /* Set up for REGNO unique hold value. */
205 lra_set_regno_unique_value (int regno
)
207 lra_reg_info
[regno
].val
= get_new_reg_value ();
210 /* Invalidate INSN related info used by LRA. */
212 lra_invalidate_insn_data (rtx insn
)
214 lra_invalidate_insn_regno_info (insn
);
215 invalidate_insn_recog_data (INSN_UID (insn
));
218 /* Mark INSN deleted and invalidate the insn related info used by
221 lra_set_insn_deleted (rtx insn
)
223 lra_invalidate_insn_data (insn
);
224 SET_INSN_DELETED (insn
);
227 /* Delete an unneeded INSN and any previous insns who sole purpose is
228 loading data that is dead in INSN. */
230 lra_delete_dead_insn (rtx insn
)
232 rtx prev
= prev_real_insn (insn
);
235 /* If the previous insn sets a register that dies in our insn,
237 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
238 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
239 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
240 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
241 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
242 lra_delete_dead_insn (prev
);
244 lra_set_insn_deleted (insn
);
247 /* Emit insn x = y + z. Return NULL if we failed to do it.
248 Otherwise, return the insn. We don't use gen_add3_insn as it might
251 emit_add3_insn (rtx x
, rtx y
, rtx z
)
255 last
= get_last_insn ();
256 insn
= emit_insn (gen_rtx_SET (VOIDmode
, x
,
257 gen_rtx_PLUS (GET_MODE (y
), y
, z
)));
258 if (recog_memoized (insn
) < 0)
260 delete_insns_since (last
);
266 /* Emit insn x = x + y. Return the insn. We use gen_add2_insn as the
269 emit_add2_insn (rtx x
, rtx y
)
273 insn
= emit_add3_insn (x
, x
, y
);
274 if (insn
== NULL_RTX
)
276 insn
= gen_add2_insn (x
, y
);
277 if (insn
!= NULL_RTX
)
283 /* Target checks operands through operand predicates to recognize an
284 insn. We should have a special precaution to generate add insns
285 which are frequent results of elimination.
287 Emit insns for x = y + z. X can be used to store intermediate
288 values and should be not in Y and Z when we use X to store an
289 intermediate value. Y + Z should form [base] [+ index[ * scale]] [
290 + disp] where base and index are registers, disp and scale are
291 constants. Y should contain base if it is present, Z should
292 contain disp if any. index[*scale] can be part of Y or Z. */
294 lra_emit_add (rtx x
, rtx y
, rtx z
)
298 rtx a1
, a2
, base
, index
, disp
, scale
, index_scale
;
301 insn
= emit_add3_insn (x
, y
, z
);
302 old
= max_reg_num ();
303 if (insn
!= NULL_RTX
)
307 disp
= a2
= NULL_RTX
;
308 if (GET_CODE (y
) == PLUS
)
322 index_scale
= scale
= NULL_RTX
;
323 if (GET_CODE (a1
) == MULT
)
326 index
= XEXP (a1
, 0);
327 scale
= XEXP (a1
, 1);
330 else if (a2
!= NULL_RTX
&& GET_CODE (a2
) == MULT
)
333 index
= XEXP (a2
, 0);
334 scale
= XEXP (a2
, 1);
343 || (index
!= NULL_RTX
&& ! REG_P (index
))
344 || (disp
!= NULL_RTX
&& ! CONSTANT_P (disp
))
345 || (scale
!= NULL_RTX
&& ! CONSTANT_P (scale
)))
347 /* Probably we have no 3 op add. Last chance is to use 2-op
348 add insn. To succeed, don't move Z to X as an address
349 segment always comes in Y. Otherwise, we might fail when
350 adding the address segment to register. */
351 lra_assert (x
!= y
&& x
!= z
);
352 emit_move_insn (x
, y
);
353 insn
= emit_add2_insn (x
, z
);
354 lra_assert (insn
!= NULL_RTX
);
358 if (index_scale
== NULL_RTX
)
360 if (disp
== NULL_RTX
)
362 /* Generate x = index_scale; x = x + base. */
363 lra_assert (index_scale
!= NULL_RTX
&& base
!= NULL_RTX
);
364 emit_move_insn (x
, index_scale
);
365 insn
= emit_add2_insn (x
, base
);
366 lra_assert (insn
!= NULL_RTX
);
368 else if (scale
== NULL_RTX
)
370 /* Try x = base + disp. */
371 lra_assert (base
!= NULL_RTX
);
372 last
= get_last_insn ();
373 insn
= emit_move_insn (x
, gen_rtx_PLUS (GET_MODE (base
),
375 if (recog_memoized (insn
) < 0)
377 delete_insns_since (last
);
378 /* Generate x = disp; x = x + base. */
379 emit_move_insn (x
, disp
);
380 insn
= emit_add2_insn (x
, base
);
381 lra_assert (insn
!= NULL_RTX
);
383 /* Generate x = x + index. */
384 if (index
!= NULL_RTX
)
386 insn
= emit_add2_insn (x
, index
);
387 lra_assert (insn
!= NULL_RTX
);
392 /* Try x = index_scale; x = x + disp; x = x + base. */
393 last
= get_last_insn ();
394 insn
= emit_move_insn (x
, index_scale
);
396 if (recog_memoized (insn
) >= 0)
398 insn
= emit_add2_insn (x
, disp
);
399 if (insn
!= NULL_RTX
)
401 insn
= emit_add2_insn (x
, disp
);
402 if (insn
!= NULL_RTX
)
408 delete_insns_since (last
);
409 /* Generate x = disp; x = x + base; x = x + index_scale. */
410 emit_move_insn (x
, disp
);
411 insn
= emit_add2_insn (x
, base
);
412 lra_assert (insn
!= NULL_RTX
);
413 insn
= emit_add2_insn (x
, index_scale
);
414 lra_assert (insn
!= NULL_RTX
);
419 /* Functions emit_... can create pseudos -- so expand the pseudo
421 if (old
!= max_reg_num ())
422 expand_reg_data (old
);
425 /* The number of emitted reload insns so far. */
426 int lra_curr_reload_num
;
428 /* Emit x := y, processing special case when y = u + v or y = u + v *
429 scale + w through emit_add (Y can be an address which is base +
430 index reg * scale + displacement in general case). X may be used
431 as intermediate result therefore it should be not in Y. */
433 lra_emit_move (rtx x
, rtx y
)
437 if (GET_CODE (y
) != PLUS
)
439 if (rtx_equal_p (x
, y
))
441 old
= max_reg_num ();
442 emit_move_insn (x
, y
);
444 lra_reg_info
[ORIGINAL_REGNO (x
)].last_reload
= ++lra_curr_reload_num
;
445 /* Function emit_move can create pseudos -- so expand the pseudo
447 if (old
!= max_reg_num ())
448 expand_reg_data (old
);
451 lra_emit_add (x
, XEXP (y
, 0), XEXP (y
, 1));
454 /* Update insn operands which are duplication of operands whose
455 numbers are in array of NOPS (with end marker -1). The insn is
456 represented by its LRA internal representation ID. */
458 lra_update_dups (lra_insn_recog_data_t id
, signed char *nops
)
461 struct lra_static_insn_data
*static_id
= id
->insn_static_data
;
463 for (i
= 0; i
< static_id
->n_dups
; i
++)
464 for (j
= 0; (nop
= nops
[j
]) >= 0; j
++)
465 if (static_id
->dup_num
[i
] == nop
)
466 *id
->dup_loc
[i
] = *id
->operand_loc
[nop
];
471 /* This page contains code dealing with info about registers in the
474 /* Pools for insn reg info. */
475 static alloc_pool insn_reg_pool
;
477 /* Initiate pool for insn reg info. */
479 init_insn_regs (void)
482 = create_alloc_pool ("insn regs", sizeof (struct lra_insn_reg
), 100);
485 /* Create LRA insn related info about a reference to REGNO in INSN with
486 TYPE (in/out/inout), biggest reference mode MODE, flag that it is
487 reference through subreg (SUBREG_P), flag that is early clobbered
488 in the insn (EARLY_CLOBBER), and reference to the next insn reg
490 static struct lra_insn_reg
*
491 new_insn_reg (rtx insn
, int regno
, enum op_type type
, enum machine_mode mode
,
492 bool subreg_p
, bool early_clobber
, struct lra_insn_reg
*next
)
494 struct lra_insn_reg
*ir
;
496 ir
= (struct lra_insn_reg
*) pool_alloc (insn_reg_pool
);
498 ir
->biggest_mode
= mode
;
499 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (lra_reg_info
[regno
].biggest_mode
)
500 && NONDEBUG_INSN_P (insn
))
501 lra_reg_info
[regno
].biggest_mode
= mode
;
502 ir
->subreg_p
= subreg_p
;
503 ir
->early_clobber
= early_clobber
;
509 /* Free insn reg info IR. */
511 free_insn_reg (struct lra_insn_reg
*ir
)
513 pool_free (insn_reg_pool
, ir
);
516 /* Free insn reg info list IR. */
518 free_insn_regs (struct lra_insn_reg
*ir
)
520 struct lra_insn_reg
*next_ir
;
522 for (; ir
!= NULL
; ir
= next_ir
)
529 /* Finish pool for insn reg info. */
531 finish_insn_regs (void)
533 free_alloc_pool (insn_reg_pool
);
538 /* This page contains code dealing LRA insn info (or in other words
539 LRA internal insn representation). */
541 struct target_lra_int default_target_lra_int
;
542 #if SWITCHABLE_TARGET
543 struct target_lra_int
*this_target_lra_int
= &default_target_lra_int
;
546 /* Map INSN_CODE -> the static insn data. This info is valid during
547 all translation unit. */
548 struct lra_static_insn_data
*insn_code_data
[LAST_INSN_CODE
];
550 /* Debug insns are represented as a special insn with one input
551 operand which is RTL expression in var_location. */
553 /* The following data are used as static insn operand data for all
554 debug insns. If structure lra_operand_data is changed, the
555 initializer should be changed too. */
556 static struct lra_operand_data debug_operand_data
=
558 NULL
, /* alternative */
559 VOIDmode
, /* We are not interesting in the operand mode. */
564 /* The following data are used as static insn data for all debug
565 insns. If structure lra_static_insn_data is changed, the
566 initializer should be changed too. */
567 static struct lra_static_insn_data debug_insn_static_data
=
570 0, /* Duplication operands #. */
571 -1, /* Commutative operand #. */
572 1, /* Operands #. There is only one operand which is debug RTL
574 0, /* Duplications #. */
575 0, /* Alternatives #. We are not interesting in alternatives
576 because we does not proceed debug_insns for reloads. */
577 NULL
, /* Hard registers referenced in machine description. */
578 NULL
/* Descriptions of operands in alternatives. */
581 /* Called once per compiler work to initialize some LRA data related
584 init_insn_code_data_once (void)
586 memset (insn_code_data
, 0, sizeof (insn_code_data
));
587 memset (op_alt_data
, 0, sizeof (op_alt_data
));
590 /* Called once per compiler work to finalize some LRA data related to
593 finish_insn_code_data_once (void)
597 for (i
= 0; i
< LAST_INSN_CODE
; i
++)
599 if (insn_code_data
[i
] != NULL
)
600 free (insn_code_data
[i
]);
601 if (op_alt_data
[i
] != NULL
)
602 free (op_alt_data
[i
]);
606 /* Initialize LRA info about operands in insn alternatives. */
608 init_op_alt_data (void)
612 for (i
= 0; i
< LAST_INSN_CODE
; i
++)
613 if (op_alt_data
[i
] != NULL
)
615 free (op_alt_data
[i
]);
616 op_alt_data
[i
] = NULL
;
620 /* Return static insn data, allocate and setup if necessary. Although
621 dup_num is static data (it depends only on icode), to set it up we
622 need to extract insn first. So recog_data should be valid for
623 normal insn (ICODE >= 0) before the call. */
624 static struct lra_static_insn_data
*
625 get_static_insn_data (int icode
, int nop
, int ndup
, int nalt
)
627 struct lra_static_insn_data
*data
;
630 lra_assert (icode
< LAST_INSN_CODE
);
631 if (icode
>= 0 && (data
= insn_code_data
[icode
]) != NULL
)
633 lra_assert (nop
>= 0 && ndup
>= 0 && nalt
>= 0);
634 n_bytes
= sizeof (struct lra_static_insn_data
)
635 + sizeof (struct lra_operand_data
) * nop
636 + sizeof (int) * ndup
;
637 data
= XNEWVAR (struct lra_static_insn_data
, n_bytes
);
638 data
->n_operands
= nop
;
640 data
->n_alternatives
= nalt
;
641 data
->operand
= ((struct lra_operand_data
*)
642 ((char *) data
+ sizeof (struct lra_static_insn_data
)));
643 data
->dup_num
= ((int *) ((char *) data
->operand
644 + sizeof (struct lra_operand_data
) * nop
));
649 insn_code_data
[icode
] = data
;
650 for (i
= 0; i
< nop
; i
++)
652 data
->operand
[i
].constraint
653 = insn_data
[icode
].operand
[i
].constraint
;
654 data
->operand
[i
].mode
= insn_data
[icode
].operand
[i
].mode
;
655 data
->operand
[i
].strict_low
= insn_data
[icode
].operand
[i
].strict_low
;
656 data
->operand
[i
].is_operator
657 = insn_data
[icode
].operand
[i
].is_operator
;
658 data
->operand
[i
].type
659 = (data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
660 : data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
662 data
->operand
[i
].is_address
= false;
664 for (i
= 0; i
< ndup
; i
++)
665 data
->dup_num
[i
] = recog_data
.dup_num
[i
];
670 /* The current length of the following array. */
671 int lra_insn_recog_data_len
;
673 /* Map INSN_UID -> the insn recog data (NULL if unknown). */
674 lra_insn_recog_data_t
*lra_insn_recog_data
;
676 /* Initialize LRA data about insns. */
678 init_insn_recog_data (void)
680 lra_insn_recog_data_len
= 0;
681 lra_insn_recog_data
= NULL
;
685 /* Expand, if necessary, LRA data about insns. */
687 check_and_expand_insn_recog_data (int index
)
691 if (lra_insn_recog_data_len
> index
)
693 old
= lra_insn_recog_data_len
;
694 lra_insn_recog_data_len
= index
* 3 / 2 + 1;
695 lra_insn_recog_data
= XRESIZEVEC (lra_insn_recog_data_t
,
697 lra_insn_recog_data_len
);
698 for (i
= old
; i
< lra_insn_recog_data_len
; i
++)
699 lra_insn_recog_data
[i
] = NULL
;
702 /* Finish LRA DATA about insn. */
704 free_insn_recog_data (lra_insn_recog_data_t data
)
706 if (data
->operand_loc
!= NULL
)
707 free (data
->operand_loc
);
708 if (data
->dup_loc
!= NULL
)
709 free (data
->dup_loc
);
710 if (data
->arg_hard_regs
!= NULL
)
711 free (data
->arg_hard_regs
);
712 if (HAVE_ATTR_enabled
&& data
->alternative_enabled_p
!= NULL
)
713 free (data
->alternative_enabled_p
);
714 if (data
->icode
< 0 && NONDEBUG_INSN_P (data
->insn
))
716 if (data
->insn_static_data
->operand_alternative
!= NULL
)
717 free (data
->insn_static_data
->operand_alternative
);
718 free_insn_regs (data
->insn_static_data
->hard_regs
);
719 free (data
->insn_static_data
);
721 free_insn_regs (data
->regs
);
726 /* Finish LRA data about all insns. */
728 finish_insn_recog_data (void)
731 lra_insn_recog_data_t data
;
733 for (i
= 0; i
< lra_insn_recog_data_len
; i
++)
734 if ((data
= lra_insn_recog_data
[i
]) != NULL
)
735 free_insn_recog_data (data
);
737 free (lra_insn_recog_data
);
740 /* Setup info about operands in alternatives of LRA DATA of insn. */
742 setup_operand_alternative (lra_insn_recog_data_t data
)
745 int icode
= data
->icode
;
746 struct lra_static_insn_data
*static_data
= data
->insn_static_data
;
749 && (static_data
->operand_alternative
= op_alt_data
[icode
]) != NULL
)
751 static_data
->commutative
= -1;
752 nop
= static_data
->n_operands
;
755 static_data
->operand_alternative
= NULL
;
758 nalt
= static_data
->n_alternatives
;
759 static_data
->operand_alternative
= XNEWVEC (struct operand_alternative
,
761 memset (static_data
->operand_alternative
, 0,
762 nalt
* nop
* sizeof (struct operand_alternative
));
764 op_alt_data
[icode
] = static_data
->operand_alternative
;
765 for (i
= 0; i
< nop
; i
++)
768 struct operand_alternative
*op_alt_start
, *op_alt
;
769 const char *p
= static_data
->operand
[i
].constraint
;
771 static_data
->operand
[i
].early_clobber
= 0;
772 op_alt_start
= &static_data
->operand_alternative
[i
];
774 for (j
= 0; j
< nalt
; j
++)
776 op_alt
= op_alt_start
+ j
* nop
;
777 op_alt
->cl
= NO_REGS
;
778 op_alt
->constraint
= p
;
779 op_alt
->matches
= -1;
780 op_alt
->matched
= -1;
782 if (*p
== '\0' || *p
== ',')
784 op_alt
->anything_ok
= 1;
794 while (c
!= ',' && c
!= '\0');
795 if (c
== ',' || c
== '\0')
803 case '=': case '+': case '*':
804 case 'E': case 'F': case 'G': case 'H':
805 case 's': case 'i': case 'n':
806 case 'I': case 'J': case 'K': case 'L':
807 case 'M': case 'N': case 'O': case 'P':
808 /* These don't say anything we care about. */
812 /* We currently only support one commutative pair of
814 if (static_data
->commutative
< 0)
815 static_data
->commutative
= i
;
817 lra_assert (data
->icode
< 0); /* Asm */
819 /* The last operand should not be marked
821 lra_assert (i
!= nop
- 1);
825 op_alt
->reject
+= LRA_LOSER_COST_FACTOR
;
828 op_alt
->reject
+= LRA_MAX_REJECT
;
831 op_alt
->earlyclobber
= 1;
832 static_data
->operand
[i
].early_clobber
= 1;
835 case '0': case '1': case '2': case '3': case '4':
836 case '5': case '6': case '7': case '8': case '9':
839 op_alt
->matches
= strtoul (p
, &end
, 10);
840 static_data
->operand_alternative
841 [j
* nop
+ op_alt
->matches
].matched
= i
;
846 case TARGET_MEM_CONSTRAINT
:
847 op_alt
->memory_ok
= 1;
850 op_alt
->decmem_ok
= 1;
853 op_alt
->incmem_ok
= 1;
856 op_alt
->nonoffmem_ok
= 1;
859 op_alt
->offmem_ok
= 1;
862 op_alt
->anything_ok
= 1;
866 static_data
->operand
[i
].is_address
= true;
867 op_alt
->is_address
= 1;
868 op_alt
->cl
= (reg_class_subunion
[(int) op_alt
->cl
]
869 [(int) base_reg_class (VOIDmode
,
877 reg_class_subunion
[(int) op_alt
->cl
][(int) GENERAL_REGS
];
881 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
883 op_alt
->memory_ok
= 1;
886 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
888 static_data
->operand
[i
].is_address
= true;
889 op_alt
->is_address
= 1;
891 = (reg_class_subunion
893 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
899 = (reg_class_subunion
902 REG_CLASS_FROM_CONSTRAINT ((unsigned char) c
, p
)]);
905 p
+= CONSTRAINT_LEN (c
, p
);
911 /* Recursively process X and collect info about registers, which are
912 not the insn operands, in X with TYPE (in/out/inout) and flag that
913 it is early clobbered in the insn (EARLY_CLOBBER) and add the info
914 to LIST. X is a part of insn given by DATA. Return the result
916 static struct lra_insn_reg
*
917 collect_non_operand_hard_regs (rtx
*x
, lra_insn_recog_data_t data
,
918 struct lra_insn_reg
*list
,
919 enum op_type type
, bool early_clobber
)
921 int i
, j
, regno
, last
;
923 enum machine_mode mode
;
924 struct lra_insn_reg
*curr
;
926 enum rtx_code code
= GET_CODE (op
);
927 const char *fmt
= GET_RTX_FORMAT (code
);
929 for (i
= 0; i
< data
->insn_static_data
->n_operands
; i
++)
930 if (x
== data
->operand_loc
[i
])
931 /* It is an operand loc. Stop here. */
933 for (i
= 0; i
< data
->insn_static_data
->n_dups
; i
++)
934 if (x
== data
->dup_loc
[i
])
935 /* It is a dup loc. Stop here. */
937 mode
= GET_MODE (op
);
941 op
= SUBREG_REG (op
);
942 code
= GET_CODE (op
);
943 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (op
)))
945 mode
= GET_MODE (op
);
946 if (GET_MODE_SIZE (mode
) > REGMODE_NATURAL_SIZE (mode
))
952 if ((regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
)
954 for (last
= regno
+ hard_regno_nregs
[regno
][mode
];
957 if (! TEST_HARD_REG_BIT (lra_no_alloc_regs
, regno
)
958 || TEST_HARD_REG_BIT (eliminable_regset
, regno
))
960 for (curr
= list
; curr
!= NULL
; curr
= curr
->next
)
961 if (curr
->regno
== regno
&& curr
->subreg_p
== subreg_p
962 && curr
->biggest_mode
== mode
)
964 if (curr
->type
!= type
)
965 curr
->type
= OP_INOUT
;
966 if (curr
->early_clobber
!= early_clobber
)
967 curr
->early_clobber
= true;
972 /* This is a new hard regno or the info can not be
973 integrated into the found structure. */
977 /* This clobber is to inform popping floating
979 && ! (FIRST_STACK_REG
<= regno
980 && regno
<= LAST_STACK_REG
));
982 list
= new_insn_reg (data
->insn
, regno
, type
, mode
, subreg_p
,
983 early_clobber
, list
);
991 list
= collect_non_operand_hard_regs (&SET_DEST (op
), data
,
992 list
, OP_OUT
, false);
993 list
= collect_non_operand_hard_regs (&SET_SRC (op
), data
,
997 /* We treat clobber of non-operand hard registers as early
998 clobber (the behavior is expected from asm). */
999 list
= collect_non_operand_hard_regs (&XEXP (op
, 0), data
,
1000 list
, OP_OUT
, true);
1002 case PRE_INC
: case PRE_DEC
: case POST_INC
: case POST_DEC
:
1003 list
= collect_non_operand_hard_regs (&XEXP (op
, 0), data
,
1004 list
, OP_INOUT
, false);
1006 case PRE_MODIFY
: case POST_MODIFY
:
1007 list
= collect_non_operand_hard_regs (&XEXP (op
, 0), data
,
1008 list
, OP_INOUT
, false);
1009 list
= collect_non_operand_hard_regs (&XEXP (op
, 1), data
,
1010 list
, OP_IN
, false);
1013 fmt
= GET_RTX_FORMAT (code
);
1014 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1017 list
= collect_non_operand_hard_regs (&XEXP (op
, i
), data
,
1018 list
, OP_IN
, false);
1019 else if (fmt
[i
] == 'E')
1020 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
1021 list
= collect_non_operand_hard_regs (&XVECEXP (op
, i
, j
), data
,
1022 list
, OP_IN
, false);
1028 /* Set up and return info about INSN. Set up the info if it is not set up
1030 lra_insn_recog_data_t
1031 lra_set_insn_recog_data (rtx insn
)
1033 lra_insn_recog_data_t data
;
1036 unsigned int uid
= INSN_UID (insn
);
1037 struct lra_static_insn_data
*insn_static_data
;
1039 check_and_expand_insn_recog_data (uid
);
1040 if (DEBUG_INSN_P (insn
))
1044 icode
= INSN_CODE (insn
);
1046 /* It might be a new simple insn which is not recognized yet. */
1047 INSN_CODE (insn
) = icode
= recog_memoized (insn
);
1049 data
= XNEW (struct lra_insn_recog_data
);
1050 lra_insn_recog_data
[uid
] = data
;
1052 data
->used_insn_alternative
= -1;
1053 data
->icode
= icode
;
1055 if (DEBUG_INSN_P (insn
))
1057 data
->insn_static_data
= &debug_insn_static_data
;
1058 data
->dup_loc
= NULL
;
1059 data
->arg_hard_regs
= NULL
;
1060 data
->alternative_enabled_p
= NULL
;
1061 data
->operand_loc
= XNEWVEC (rtx
*, 1);
1062 data
->operand_loc
[0] = &INSN_VAR_LOCATION_LOC (insn
);
1068 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1069 const char *constraints
[MAX_RECOG_OPERANDS
];
1071 nop
= asm_noperands (PATTERN (insn
));
1072 data
->operand_loc
= data
->dup_loc
= NULL
;
1074 /* Its is a special insn like USE or CLOBBER. */
1075 data
->insn_static_data
= insn_static_data
1076 = get_static_insn_data (-1, 0, 0, 1);
1079 /* expand_asm_operands makes sure there aren't too many
1081 lra_assert (nop
<= MAX_RECOG_OPERANDS
);
1083 data
->operand_loc
= XNEWVEC (rtx
*, nop
);
1084 /* Now get the operand values and constraints out of the
1086 decode_asm_operands (PATTERN (insn
), NULL
,
1088 constraints
, operand_mode
, NULL
);
1092 const char *p
= recog_data
.constraints
[0];
1094 for (p
= constraints
[0]; *p
; p
++)
1097 data
->insn_static_data
= insn_static_data
1098 = get_static_insn_data (-1, nop
, 0, n
);
1099 for (i
= 0; i
< nop
; i
++)
1101 insn_static_data
->operand
[i
].mode
= operand_mode
[i
];
1102 insn_static_data
->operand
[i
].constraint
= constraints
[i
];
1103 insn_static_data
->operand
[i
].strict_low
= false;
1104 insn_static_data
->operand
[i
].is_operator
= false;
1105 insn_static_data
->operand
[i
].is_address
= false;
1108 for (i
= 0; i
< insn_static_data
->n_operands
; i
++)
1109 insn_static_data
->operand
[i
].type
1110 = (insn_static_data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
1111 : insn_static_data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
1113 data
->alternative_enabled_p
= NULL
;
1117 insn_extract (insn
);
1118 data
->insn_static_data
= insn_static_data
1119 = get_static_insn_data (icode
, insn_data
[icode
].n_operands
,
1120 insn_data
[icode
].n_dups
,
1121 insn_data
[icode
].n_alternatives
);
1122 n
= insn_static_data
->n_operands
;
1127 locs
= XNEWVEC (rtx
*, n
);
1128 memcpy (locs
, recog_data
.operand_loc
, n
* sizeof (rtx
*));
1130 data
->operand_loc
= locs
;
1131 n
= insn_static_data
->n_dups
;
1136 locs
= XNEWVEC (rtx
*, n
);
1137 memcpy (locs
, recog_data
.dup_loc
, n
* sizeof (rtx
*));
1139 data
->dup_loc
= locs
;
1140 if (HAVE_ATTR_enabled
)
1144 n
= insn_static_data
->n_alternatives
;
1145 lra_assert (n
>= 0);
1146 data
->alternative_enabled_p
= bp
= XNEWVEC (bool, n
);
1147 /* Cache the insn because we don't want to call extract_insn
1148 from get_attr_enabled as extract_insn modifies
1149 which_alternative. The attribute enabled should not depend
1150 on insn operands, operand modes, operand types, and operand
1151 constraints. It should depend on the architecture. If it
1152 is not true, we should rewrite this file code to use
1153 extract_insn instead of less expensive insn_extract. */
1154 recog_data
.insn
= insn
;
1155 for (i
= 0; i
< n
; i
++)
1157 which_alternative
= i
;
1158 bp
[i
] = get_attr_enabled (insn
);
1162 if (GET_CODE (PATTERN (insn
)) == CLOBBER
|| GET_CODE (PATTERN (insn
)) == USE
)
1163 insn_static_data
->hard_regs
= NULL
;
1165 insn_static_data
->hard_regs
1166 = collect_non_operand_hard_regs (&PATTERN (insn
), data
,
1167 NULL
, OP_IN
, false);
1168 setup_operand_alternative (data
);
1169 data
->arg_hard_regs
= NULL
;
1173 int n_hard_regs
, regno
, arg_hard_regs
[FIRST_PSEUDO_REGISTER
];
1176 /* Finding implicit hard register usage. We believe it will be
1177 not changed whatever transformations are used. Call insns
1178 are such example. */
1179 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
1181 link
= XEXP (link
, 1))
1182 if (GET_CODE (XEXP (link
, 0)) == USE
1183 && REG_P (XEXP (XEXP (link
, 0), 0)))
1185 regno
= REGNO (XEXP (XEXP (link
, 0), 0));
1186 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
1187 /* It is an argument register. */
1188 for (i
= (hard_regno_nregs
1189 [regno
][GET_MODE (XEXP (XEXP (link
, 0), 0))]) - 1;
1192 arg_hard_regs
[n_hard_regs
++] = regno
+ i
;
1194 if (n_hard_regs
!= 0)
1196 arg_hard_regs
[n_hard_regs
++] = -1;
1197 data
->arg_hard_regs
= XNEWVEC (int, n_hard_regs
);
1198 memcpy (data
->arg_hard_regs
, arg_hard_regs
,
1199 sizeof (int) * n_hard_regs
);
1202 /* Some output operand can be recognized only from the context not
1203 from the constraints which are empty in this case. Call insn may
1204 contain a hard register in set destination with empty constraint
1205 and extract_insn treats them as an input. */
1206 for (i
= 0; i
< insn_static_data
->n_operands
; i
++)
1210 struct lra_operand_data
*operand
= &insn_static_data
->operand
[i
];
1212 /* ??? Should we treat 'X' the same way. It looks to me that
1213 'X' means anything and empty constraint means we do not
1215 if (operand
->type
!= OP_IN
|| *operand
->constraint
!= '\0'
1216 || operand
->is_operator
)
1218 pat
= PATTERN (insn
);
1219 if (GET_CODE (pat
) == SET
)
1221 if (data
->operand_loc
[i
] != &SET_DEST (pat
))
1224 else if (GET_CODE (pat
) == PARALLEL
)
1226 for (j
= XVECLEN (pat
, 0) - 1; j
>= 0; j
--)
1228 set
= XVECEXP (PATTERN (insn
), 0, j
);
1229 if (GET_CODE (set
) == SET
1230 && &SET_DEST (set
) == data
->operand_loc
[i
])
1238 operand
->type
= OP_OUT
;
1243 /* Return info about insn give by UID. The info should be already set
1245 static lra_insn_recog_data_t
1246 get_insn_recog_data_by_uid (int uid
)
1248 lra_insn_recog_data_t data
;
1250 data
= lra_insn_recog_data
[uid
];
1251 lra_assert (data
!= NULL
);
1255 /* Invalidate all info about insn given by its UID. */
1257 invalidate_insn_recog_data (int uid
)
1259 lra_insn_recog_data_t data
;
1261 data
= lra_insn_recog_data
[uid
];
1262 lra_assert (data
!= NULL
);
1263 free_insn_recog_data (data
);
1264 lra_insn_recog_data
[uid
] = NULL
;
1267 /* Update all the insn info about INSN. It is usually called when
1268 something in the insn was changed. Return the updated info. */
1269 lra_insn_recog_data_t
1270 lra_update_insn_recog_data (rtx insn
)
1272 lra_insn_recog_data_t data
;
1274 unsigned int uid
= INSN_UID (insn
);
1275 struct lra_static_insn_data
*insn_static_data
;
1277 check_and_expand_insn_recog_data (uid
);
1278 if ((data
= lra_insn_recog_data
[uid
]) != NULL
1279 && data
->icode
!= INSN_CODE (insn
))
1281 invalidate_insn_data_regno_info (data
, insn
, get_insn_freq (insn
));
1282 invalidate_insn_recog_data (uid
);
1286 return lra_get_insn_recog_data (insn
);
1287 insn_static_data
= data
->insn_static_data
;
1288 data
->used_insn_alternative
= -1;
1289 if (DEBUG_INSN_P (insn
))
1291 if (data
->icode
< 0)
1294 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1295 const char *constraints
[MAX_RECOG_OPERANDS
];
1297 nop
= asm_noperands (PATTERN (insn
));
1300 lra_assert (nop
== data
->insn_static_data
->n_operands
);
1301 /* Now get the operand values and constraints out of the
1303 decode_asm_operands (PATTERN (insn
), NULL
,
1305 constraints
, operand_mode
, NULL
);
1306 #ifdef ENABLE_CHECKING
1310 for (i
= 0; i
< nop
; i
++)
1312 (insn_static_data
->operand
[i
].mode
== operand_mode
[i
]
1313 && insn_static_data
->operand
[i
].constraint
== constraints
[i
]
1314 && ! insn_static_data
->operand
[i
].is_operator
);
1318 #ifdef ENABLE_CHECKING
1322 for (i
= 0; i
< insn_static_data
->n_operands
; i
++)
1324 (insn_static_data
->operand
[i
].type
1325 == (insn_static_data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
1326 : insn_static_data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
1333 insn_extract (insn
);
1334 n
= insn_static_data
->n_operands
;
1336 memcpy (data
->operand_loc
, recog_data
.operand_loc
, n
* sizeof (rtx
*));
1337 n
= insn_static_data
->n_dups
;
1339 memcpy (data
->dup_loc
, recog_data
.dup_loc
, n
* sizeof (rtx
*));
1340 #if HAVE_ATTR_enabled
1341 #ifdef ENABLE_CHECKING
1346 n
= insn_static_data
->n_alternatives
;
1347 bp
= data
->alternative_enabled_p
;
1348 lra_assert (n
>= 0 && bp
!= NULL
);
1349 /* Cache the insn to prevent extract_insn call from
1350 get_attr_enabled. */
1351 recog_data
.insn
= insn
;
1352 for (i
= 0; i
< n
; i
++)
1354 which_alternative
= i
;
1355 lra_assert (bp
[i
] == get_attr_enabled (insn
));
1364 /* Set up that INSN is using alternative ALT now. */
1366 lra_set_used_insn_alternative (rtx insn
, int alt
)
1368 lra_insn_recog_data_t data
;
1370 data
= lra_get_insn_recog_data (insn
);
1371 data
->used_insn_alternative
= alt
;
1374 /* Set up that insn with UID is using alternative ALT now. The insn
1375 info should be already set up. */
1377 lra_set_used_insn_alternative_by_uid (int uid
, int alt
)
1379 lra_insn_recog_data_t data
;
1381 check_and_expand_insn_recog_data (uid
);
1382 data
= lra_insn_recog_data
[uid
];
1383 lra_assert (data
!= NULL
);
1384 data
->used_insn_alternative
= alt
;
1389 /* This page contains code dealing with common register info and
1392 /* The size of the following array. */
1393 static int reg_info_size
;
1394 /* Common info about each register. */
1395 struct lra_reg
*lra_reg_info
;
1397 /* Last register value. */
1398 static int last_reg_value
;
1400 /* Return new register value. */
1402 get_new_reg_value (void)
1404 return ++last_reg_value
;
1407 /* Pools for copies. */
1408 static alloc_pool copy_pool
;
1410 /* Vec referring to pseudo copies. */
1411 static vec
<lra_copy_t
> copy_vec
;
1413 /* Initialize I-th element of lra_reg_info. */
1415 initialize_lra_reg_info_element (int i
)
1417 bitmap_initialize (&lra_reg_info
[i
].insn_bitmap
, ®_obstack
);
1419 lra_reg_info
[i
].no_stack_p
= false;
1421 CLEAR_HARD_REG_SET (lra_reg_info
[i
].conflict_hard_regs
);
1422 lra_reg_info
[i
].preferred_hard_regno1
= -1;
1423 lra_reg_info
[i
].preferred_hard_regno2
= -1;
1424 lra_reg_info
[i
].preferred_hard_regno_profit1
= 0;
1425 lra_reg_info
[i
].preferred_hard_regno_profit2
= 0;
1426 lra_reg_info
[i
].biggest_mode
= VOIDmode
;
1427 lra_reg_info
[i
].live_ranges
= NULL
;
1428 lra_reg_info
[i
].nrefs
= lra_reg_info
[i
].freq
= 0;
1429 lra_reg_info
[i
].last_reload
= 0;
1430 lra_reg_info
[i
].restore_regno
= -1;
1431 lra_reg_info
[i
].val
= get_new_reg_value ();
1432 lra_reg_info
[i
].offset
= 0;
1433 lra_reg_info
[i
].copies
= NULL
;
1436 /* Initialize common reg info and copies. */
1438 init_reg_info (void)
1443 reg_info_size
= max_reg_num () * 3 / 2 + 1;
1444 lra_reg_info
= XNEWVEC (struct lra_reg
, reg_info_size
);
1445 for (i
= 0; i
< reg_info_size
; i
++)
1446 initialize_lra_reg_info_element (i
);
1448 = create_alloc_pool ("lra copies", sizeof (struct lra_copy
), 100);
1449 copy_vec
.create (100);
1453 /* Finish common reg info and copies. */
1455 finish_reg_info (void)
1459 for (i
= 0; i
< reg_info_size
; i
++)
1460 bitmap_clear (&lra_reg_info
[i
].insn_bitmap
);
1461 free (lra_reg_info
);
1463 free_alloc_pool (copy_pool
);
1464 copy_vec
.release ();
1467 /* Expand common reg info if it is necessary. */
1469 expand_reg_info (void)
1471 int i
, old
= reg_info_size
;
1473 if (reg_info_size
> max_reg_num ())
1475 reg_info_size
= max_reg_num () * 3 / 2 + 1;
1476 lra_reg_info
= XRESIZEVEC (struct lra_reg
, lra_reg_info
, reg_info_size
);
1477 for (i
= old
; i
< reg_info_size
; i
++)
1478 initialize_lra_reg_info_element (i
);
1481 /* Free all copies. */
1483 lra_free_copies (void)
1487 while (copy_vec
.length () != 0)
1489 cp
= copy_vec
.pop ();
1490 lra_reg_info
[cp
->regno1
].copies
= lra_reg_info
[cp
->regno2
].copies
= NULL
;
1491 pool_free (copy_pool
, cp
);
1495 /* Create copy of two pseudos REGNO1 and REGNO2. The copy execution
1496 frequency is FREQ. */
1498 lra_create_copy (int regno1
, int regno2
, int freq
)
1503 lra_assert (regno1
!= regno2
);
1504 regno1_dest_p
= true;
1505 if (regno1
> regno2
)
1509 regno1_dest_p
= false;
1513 cp
= (lra_copy_t
) pool_alloc (copy_pool
);
1514 copy_vec
.safe_push (cp
);
1515 cp
->regno1_dest_p
= regno1_dest_p
;
1517 cp
->regno1
= regno1
;
1518 cp
->regno2
= regno2
;
1519 cp
->regno1_next
= lra_reg_info
[regno1
].copies
;
1520 lra_reg_info
[regno1
].copies
= cp
;
1521 cp
->regno2_next
= lra_reg_info
[regno2
].copies
;
1522 lra_reg_info
[regno2
].copies
= cp
;
1523 if (lra_dump_file
!= NULL
)
1524 fprintf (lra_dump_file
, " Creating copy r%d%sr%d@%d\n",
1525 regno1
, regno1_dest_p
? "<-" : "->", regno2
, freq
);
1528 /* Return N-th (0, 1, ...) copy. If there is no copy, return
1531 lra_get_copy (int n
)
1533 if (n
>= (int) copy_vec
.length ())
1540 /* This page contains code dealing with info about registers in
1543 /* Process X of insn UID recursively and add info (operand type is
1544 given by TYPE, flag of that it is early clobber is EARLY_CLOBBER)
1545 about registers in X to the insn DATA. */
1547 add_regs_to_insn_regno_info (lra_insn_recog_data_t data
, rtx x
, int uid
,
1548 enum op_type type
, bool early_clobber
)
1552 enum machine_mode mode
;
1555 struct lra_insn_reg
*curr
;
1557 code
= GET_CODE (x
);
1558 mode
= GET_MODE (x
);
1560 if (GET_CODE (x
) == SUBREG
)
1563 code
= GET_CODE (x
);
1564 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
)))
1566 mode
= GET_MODE (x
);
1567 if (GET_MODE_SIZE (mode
) > REGMODE_NATURAL_SIZE (mode
))
1574 if (regno
< FIRST_PSEUDO_REGISTER
1575 && TEST_HARD_REG_BIT (lra_no_alloc_regs
, regno
)
1576 && ! TEST_HARD_REG_BIT (eliminable_regset
, regno
))
1579 if (bitmap_set_bit (&lra_reg_info
[regno
].insn_bitmap
, uid
))
1581 data
->regs
= new_insn_reg (data
->insn
, regno
, type
, mode
, subreg_p
,
1582 early_clobber
, data
->regs
);
1587 for (curr
= data
->regs
; curr
!= NULL
; curr
= curr
->next
)
1588 if (curr
->regno
== regno
)
1590 if (curr
->subreg_p
!= subreg_p
|| curr
->biggest_mode
!= mode
)
1591 /* The info can not be integrated into the found
1593 data
->regs
= new_insn_reg (data
->insn
, regno
, type
, mode
,
1594 subreg_p
, early_clobber
,
1598 if (curr
->type
!= type
)
1599 curr
->type
= OP_INOUT
;
1600 if (curr
->early_clobber
!= early_clobber
)
1601 curr
->early_clobber
= true;
1612 add_regs_to_insn_regno_info (data
, SET_DEST (x
), uid
, OP_OUT
, false);
1613 add_regs_to_insn_regno_info (data
, SET_SRC (x
), uid
, OP_IN
, false);
1616 /* We treat clobber of non-operand hard registers as early
1617 clobber (the behavior is expected from asm). */
1618 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), uid
, OP_OUT
, true);
1620 case PRE_INC
: case PRE_DEC
: case POST_INC
: case POST_DEC
:
1621 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), uid
, OP_INOUT
, false);
1623 case PRE_MODIFY
: case POST_MODIFY
:
1624 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), uid
, OP_INOUT
, false);
1625 add_regs_to_insn_regno_info (data
, XEXP (x
, 1), uid
, OP_IN
, false);
1628 if ((code
!= PARALLEL
&& code
!= EXPR_LIST
) || type
!= OP_OUT
)
1629 /* Some targets place small structures in registers for return
1630 values of functions, and those registers are wrapped in
1631 PARALLEL that we may see as the destination of a SET. Here
1634 (call_insn 13 12 14 2 (set (parallel:BLK [
1635 (expr_list:REG_DEP_TRUE (reg:DI 0 ax)
1637 (expr_list:REG_DEP_TRUE (reg:DI 1 dx)
1638 (const_int 8 [0x8]))
1640 (call (mem:QI (symbol_ref:DI (... */
1642 fmt
= GET_RTX_FORMAT (code
);
1643 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1646 add_regs_to_insn_regno_info (data
, XEXP (x
, i
), uid
, type
, false);
1647 else if (fmt
[i
] == 'E')
1649 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1650 add_regs_to_insn_regno_info (data
, XVECEXP (x
, i
, j
), uid
,
1657 /* Return execution frequency of INSN. */
1659 get_insn_freq (rtx insn
)
1661 basic_block bb
= BLOCK_FOR_INSN (insn
);
1663 gcc_checking_assert (bb
!= NULL
);
1664 return REG_FREQ_FROM_BB (bb
);
1667 /* Invalidate all reg info of INSN with DATA and execution frequency
1668 FREQ. Update common info about the invalidated registers. */
1670 invalidate_insn_data_regno_info (lra_insn_recog_data_t data
, rtx insn
,
1676 struct lra_insn_reg
*ir
, *next_ir
;
1678 uid
= INSN_UID (insn
);
1679 debug_p
= DEBUG_INSN_P (insn
);
1680 for (ir
= data
->regs
; ir
!= NULL
; ir
= next_ir
)
1685 bitmap_clear_bit (&lra_reg_info
[i
].insn_bitmap
, uid
);
1686 if (i
>= FIRST_PSEUDO_REGISTER
&& ! debug_p
)
1688 lra_reg_info
[i
].nrefs
--;
1689 lra_reg_info
[i
].freq
-= freq
;
1690 lra_assert (lra_reg_info
[i
].nrefs
>= 0 && lra_reg_info
[i
].freq
>= 0);
1696 /* Invalidate all reg info of INSN. Update common info about the
1697 invalidated registers. */
1699 lra_invalidate_insn_regno_info (rtx insn
)
1701 invalidate_insn_data_regno_info (lra_get_insn_recog_data (insn
), insn
,
1702 get_insn_freq (insn
));
1705 /* Update common reg info from reg info of insn given by its DATA and
1706 execution frequency FREQ. */
1708 setup_insn_reg_info (lra_insn_recog_data_t data
, int freq
)
1711 struct lra_insn_reg
*ir
;
1713 for (ir
= data
->regs
; ir
!= NULL
; ir
= ir
->next
)
1714 if ((i
= ir
->regno
) >= FIRST_PSEUDO_REGISTER
)
1716 lra_reg_info
[i
].nrefs
++;
1717 lra_reg_info
[i
].freq
+= freq
;
1721 /* Set up insn reg info of INSN. Update common reg info from reg info
1724 lra_update_insn_regno_info (rtx insn
)
1727 lra_insn_recog_data_t data
;
1728 struct lra_static_insn_data
*static_data
;
1731 if (! INSN_P (insn
))
1733 data
= lra_get_insn_recog_data (insn
);
1734 static_data
= data
->insn_static_data
;
1735 freq
= get_insn_freq (insn
);
1736 invalidate_insn_data_regno_info (data
, insn
, freq
);
1737 uid
= INSN_UID (insn
);
1738 for (i
= static_data
->n_operands
- 1; i
>= 0; i
--)
1739 add_regs_to_insn_regno_info (data
, *data
->operand_loc
[i
], uid
,
1740 static_data
->operand
[i
].type
,
1741 static_data
->operand
[i
].early_clobber
);
1742 if ((code
= GET_CODE (PATTERN (insn
))) == CLOBBER
|| code
== USE
)
1743 add_regs_to_insn_regno_info (data
, XEXP (PATTERN (insn
), 0), uid
,
1744 code
== USE
? OP_IN
: OP_OUT
, false);
1745 if (NONDEBUG_INSN_P (insn
))
1746 setup_insn_reg_info (data
, freq
);
1749 /* Return reg info of insn given by it UID. */
1750 struct lra_insn_reg
*
1751 lra_get_insn_regs (int uid
)
1753 lra_insn_recog_data_t data
;
1755 data
= get_insn_recog_data_by_uid (uid
);
1761 /* This page contains code dealing with stack of the insns which
1762 should be processed by the next constraint pass. */
1764 /* Bitmap used to put an insn on the stack only in one exemplar. */
1765 static sbitmap lra_constraint_insn_stack_bitmap
;
1767 /* The stack itself. */
1768 vec
<rtx
> lra_constraint_insn_stack
;
1770 /* Put INSN on the stack. If ALWAYS_UPDATE is true, always update the reg
1771 info for INSN, otherwise only update it if INSN is not already on the
1774 lra_push_insn_1 (rtx insn
, bool always_update
)
1776 unsigned int uid
= INSN_UID (insn
);
1778 lra_update_insn_regno_info (insn
);
1779 if (uid
>= SBITMAP_SIZE (lra_constraint_insn_stack_bitmap
))
1780 lra_constraint_insn_stack_bitmap
=
1781 sbitmap_resize (lra_constraint_insn_stack_bitmap
, 3 * uid
/ 2, 0);
1782 if (bitmap_bit_p (lra_constraint_insn_stack_bitmap
, uid
))
1784 bitmap_set_bit (lra_constraint_insn_stack_bitmap
, uid
);
1785 if (! always_update
)
1786 lra_update_insn_regno_info (insn
);
1787 lra_constraint_insn_stack
.safe_push (insn
);
1790 /* Put INSN on the stack. */
1792 lra_push_insn (rtx insn
)
1794 lra_push_insn_1 (insn
, false);
1797 /* Put INSN on the stack and update its reg info. */
1799 lra_push_insn_and_update_insn_regno_info (rtx insn
)
1801 lra_push_insn_1 (insn
, true);
1804 /* Put insn with UID on the stack. */
1806 lra_push_insn_by_uid (unsigned int uid
)
1808 lra_push_insn (lra_insn_recog_data
[uid
]->insn
);
1811 /* Take the last-inserted insns off the stack and return it. */
1815 rtx insn
= lra_constraint_insn_stack
.pop ();
1816 bitmap_clear_bit (lra_constraint_insn_stack_bitmap
, INSN_UID (insn
));
1820 /* Return the current size of the insn stack. */
1822 lra_insn_stack_length (void)
1824 return lra_constraint_insn_stack
.length ();
1827 /* Push insns FROM to TO (excluding it) going in reverse order. */
1829 push_insns (rtx from
, rtx to
)
1833 if (from
== NULL_RTX
)
1835 for (insn
= from
; insn
!= to
; insn
= PREV_INSN (insn
))
1837 lra_push_insn (insn
);
1840 /* Emit insns BEFORE before INSN and insns AFTER after INSN. Put the
1841 insns onto the stack. Print about emitting the insns with
1844 lra_process_new_insns (rtx insn
, rtx before
, rtx after
, const char *title
)
1848 if (lra_dump_file
!= NULL
&& (before
!= NULL_RTX
|| after
!= NULL_RTX
))
1850 dump_insn_slim (lra_dump_file
, insn
);
1851 if (before
!= NULL_RTX
)
1853 fprintf (lra_dump_file
," %s before:\n", title
);
1854 dump_rtl_slim (lra_dump_file
, before
, NULL_RTX
, -1, 0);
1856 if (after
!= NULL_RTX
)
1858 fprintf (lra_dump_file
, " %s after:\n", title
);
1859 dump_rtl_slim (lra_dump_file
, after
, NULL_RTX
, -1, 0);
1861 fprintf (lra_dump_file
, "\n");
1863 if (before
!= NULL_RTX
)
1865 emit_insn_before (before
, insn
);
1866 push_insns (PREV_INSN (insn
), PREV_INSN (before
));
1868 if (after
!= NULL_RTX
)
1870 for (last
= after
; NEXT_INSN (last
) != NULL_RTX
; last
= NEXT_INSN (last
))
1872 emit_insn_after (after
, insn
);
1873 push_insns (last
, insn
);
1879 /* This page contains code dealing with scratches (changing them onto
1880 pseudos and restoring them from the pseudos).
1882 We change scratches into pseudos at the beginning of LRA to
1883 simplify dealing with them (conflicts, hard register assignments).
1885 If the pseudo denoting scratch was spilled it means that we do need
1886 a hard register for it. Such pseudos are transformed back to
1887 scratches at the end of LRA. */
1889 /* Description of location of a former scratch operand. */
1892 rtx insn
; /* Insn where the scratch was. */
1893 int nop
; /* Number of the operand which was a scratch. */
1896 typedef struct sloc
*sloc_t
;
1898 /* Locations of the former scratches. */
1899 static vec
<sloc_t
> scratches
;
1901 /* Bitmap of scratch regnos. */
1902 static bitmap_head scratch_bitmap
;
1904 /* Bitmap of scratch operands. */
1905 static bitmap_head scratch_operand_bitmap
;
1907 /* Return true if pseudo REGNO is made of SCRATCH. */
1909 lra_former_scratch_p (int regno
)
1911 return bitmap_bit_p (&scratch_bitmap
, regno
);
1914 /* Return true if the operand NOP of INSN is a former scratch. */
1916 lra_former_scratch_operand_p (rtx insn
, int nop
)
1918 return bitmap_bit_p (&scratch_operand_bitmap
,
1919 INSN_UID (insn
) * MAX_RECOG_OPERANDS
+ nop
) != 0;
1922 /* Change scratches onto pseudos and save their location. */
1924 remove_scratches (void)
1927 bool insn_changed_p
;
1931 lra_insn_recog_data_t id
;
1932 struct lra_static_insn_data
*static_id
;
1934 scratches
.create (get_max_uid ());
1935 bitmap_initialize (&scratch_bitmap
, ®_obstack
);
1936 bitmap_initialize (&scratch_operand_bitmap
, ®_obstack
);
1938 FOR_BB_INSNS (bb
, insn
)
1941 id
= lra_get_insn_recog_data (insn
);
1942 static_id
= id
->insn_static_data
;
1943 insn_changed_p
= false;
1944 for (i
= 0; i
< static_id
->n_operands
; i
++)
1945 if (GET_CODE (*id
->operand_loc
[i
]) == SCRATCH
1946 && GET_MODE (*id
->operand_loc
[i
]) != VOIDmode
)
1948 insn_changed_p
= true;
1949 *id
->operand_loc
[i
] = reg
1950 = lra_create_new_reg (static_id
->operand
[i
].mode
,
1951 *id
->operand_loc
[i
], ALL_REGS
, NULL
);
1952 add_reg_note (insn
, REG_UNUSED
, reg
);
1953 lra_update_dup (id
, i
);
1954 loc
= XNEW (struct sloc
);
1957 scratches
.safe_push (loc
);
1958 bitmap_set_bit (&scratch_bitmap
, REGNO (*id
->operand_loc
[i
]));
1959 bitmap_set_bit (&scratch_operand_bitmap
,
1960 INSN_UID (insn
) * MAX_RECOG_OPERANDS
+ i
);
1961 if (lra_dump_file
!= NULL
)
1962 fprintf (lra_dump_file
,
1963 "Removing SCRATCH in insn #%u (nop %d)\n",
1964 INSN_UID (insn
), i
);
1967 /* Because we might use DF right after caller-saves sub-pass
1968 we need to keep DF info up to date. */
1969 df_insn_rescan (insn
);
1973 /* Changes pseudos created by function remove_scratches onto scratches. */
1975 restore_scratches (void)
1980 rtx last
= NULL_RTX
;
1981 lra_insn_recog_data_t id
= NULL
;
1983 for (i
= 0; scratches
.iterate (i
, &loc
); i
++)
1985 if (last
!= loc
->insn
)
1988 id
= lra_get_insn_recog_data (last
);
1990 if (REG_P (*id
->operand_loc
[loc
->nop
])
1991 && ((regno
= REGNO (*id
->operand_loc
[loc
->nop
]))
1992 >= FIRST_PSEUDO_REGISTER
)
1993 && lra_get_regno_hard_regno (regno
) < 0)
1995 /* It should be only case when scratch register with chosen
1996 constraint 'X' did not get memory or hard register. */
1997 lra_assert (lra_former_scratch_p (regno
));
1998 *id
->operand_loc
[loc
->nop
]
1999 = gen_rtx_SCRATCH (GET_MODE (*id
->operand_loc
[loc
->nop
]));
2000 lra_update_dup (id
, loc
->nop
);
2001 if (lra_dump_file
!= NULL
)
2002 fprintf (lra_dump_file
, "Restoring SCRATCH in insn #%u(nop %d)\n",
2003 INSN_UID (loc
->insn
), loc
->nop
);
2006 for (i
= 0; scratches
.iterate (i
, &loc
); i
++)
2008 scratches
.release ();
2009 bitmap_clear (&scratch_bitmap
);
2010 bitmap_clear (&scratch_operand_bitmap
);
2015 #ifdef ENABLE_CHECKING
2017 /* Function checks RTL for correctness. If FINAL_P is true, it is
2018 done at the end of LRA and the check is more rigorous. */
2020 check_rtl (bool final_p
)
2025 lra_assert (! final_p
|| reload_completed
);
2027 FOR_BB_INSNS (bb
, insn
)
2028 if (NONDEBUG_INSN_P (insn
)
2029 && GET_CODE (PATTERN (insn
)) != USE
2030 && GET_CODE (PATTERN (insn
)) != CLOBBER
2031 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
)
2035 extract_insn (insn
);
2036 lra_assert (constrain_operands (1));
2039 /* LRA code is based on assumption that all addresses can be
2040 correctly decomposed. LRA can generate reloads for
2041 decomposable addresses. The decomposition code checks the
2042 correctness of the addresses. So we don't need to check
2043 the addresses here. */
2044 if (insn_invalid_p (insn
, false))
2045 fatal_insn_not_found (insn
);
2048 #endif /* #ifdef ENABLE_CHECKING */
2050 /* Determine if the current function has an exception receiver block
2051 that reaches the exit block via non-exceptional edges */
2053 has_nonexceptional_receiver (void)
2057 basic_block
*tos
, *worklist
, bb
;
2059 /* If we're not optimizing, then just err on the safe side. */
2063 /* First determine which blocks can reach exit via normal paths. */
2064 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks_for_fn (cfun
) + 1);
2067 bb
->flags
&= ~BB_REACHABLE
;
2069 /* Place the exit block on our worklist. */
2070 EXIT_BLOCK_PTR_FOR_FN (cfun
)->flags
|= BB_REACHABLE
;
2071 *tos
++ = EXIT_BLOCK_PTR_FOR_FN (cfun
);
2073 /* Iterate: find everything reachable from what we've already seen. */
2074 while (tos
!= worklist
)
2078 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
2079 if (e
->flags
& EDGE_ABNORMAL
)
2086 basic_block src
= e
->src
;
2088 if (!(src
->flags
& BB_REACHABLE
))
2090 src
->flags
|= BB_REACHABLE
;
2096 /* No exceptional block reached exit unexceptionally. */
2102 /* Process recursively X of INSN and add REG_INC notes if necessary. */
2104 add_auto_inc_notes (rtx insn
, rtx x
)
2106 enum rtx_code code
= GET_CODE (x
);
2110 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
2112 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
2116 /* Scan all X sub-expressions. */
2117 fmt
= GET_RTX_FORMAT (code
);
2118 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2121 add_auto_inc_notes (insn
, XEXP (x
, i
));
2122 else if (fmt
[i
] == 'E')
2123 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2124 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));
2130 /* Remove all REG_DEAD and REG_UNUSED notes and regenerate REG_INC.
2131 We change pseudos by hard registers without notification of DF and
2132 that can make the notes obsolete. DF-infrastructure does not deal
2133 with REG_INC notes -- so we should regenerate them here. */
2135 update_inc_notes (void)
2142 FOR_BB_INSNS (bb
, insn
)
2143 if (NONDEBUG_INSN_P (insn
))
2145 pnote
= ®_NOTES (insn
);
2148 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
2149 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
2150 || REG_NOTE_KIND (*pnote
) == REG_INC
)
2151 *pnote
= XEXP (*pnote
, 1);
2153 pnote
= &XEXP (*pnote
, 1);
2156 add_auto_inc_notes (insn
, PATTERN (insn
));
2161 /* Set to 1 while in lra. */
2162 int lra_in_progress
;
2164 /* Start of pseudo regnos before the LRA. */
2165 int lra_new_regno_start
;
2167 /* Start of reload pseudo regnos before the new spill pass. */
2168 int lra_constraint_new_regno_start
;
2170 /* Inheritance pseudo regnos before the new spill pass. */
2171 bitmap_head lra_inheritance_pseudos
;
2173 /* Split regnos before the new spill pass. */
2174 bitmap_head lra_split_regs
;
2176 /* Reload pseudo regnos before the new assignmnet pass which still can
2177 be spilled after the assinment pass as memory is also accepted in
2178 insns for the reload pseudos. */
2179 bitmap_head lra_optional_reload_pseudos
;
2181 /* Pseudo regnos used for subreg reloads before the new assignment
2182 pass. Such pseudos still can be spilled after the assinment
2184 bitmap_head lra_subreg_reload_pseudos
;
2186 /* First UID of insns generated before a new spill pass. */
2187 int lra_constraint_new_insn_uid_start
;
2189 /* File used for output of LRA debug information. */
2190 FILE *lra_dump_file
;
2192 /* True if we should try spill into registers of different classes
2193 instead of memory. */
2194 bool lra_reg_spill_p
;
2196 /* Set up value LRA_REG_SPILL_P. */
2198 setup_reg_spill_flag (void)
2202 if (targetm
.spill_class
!= NULL
)
2203 for (cl
= 0; cl
< (int) LIM_REG_CLASSES
; cl
++)
2204 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
2205 if (targetm
.spill_class ((enum reg_class
) cl
,
2206 (enum machine_mode
) mode
) != NO_REGS
)
2208 lra_reg_spill_p
= true;
2211 lra_reg_spill_p
= false;
2214 /* True if the current function is too big to use regular algorithms
2215 in LRA. In other words, we should use simpler and faster algorithms
2216 in LRA. It also means we should not worry about generation code
2217 for caller saves. The value is set up in IRA. */
2220 /* Major LRA entry function. F is a file should be used to dump LRA
2226 bool live_p
, scratch_p
, inserted_p
;
2230 timevar_push (TV_LRA
);
2232 /* Make sure that the last insn is a note. Some subsequent passes
2234 emit_note (NOTE_INSN_DELETED
);
2236 COPY_HARD_REG_SET (lra_no_alloc_regs
, ira_no_alloc_regs
);
2241 init_insn_recog_data ();
2243 /* We can not set up reload_in_progress because it prevents new
2245 lra_in_progress
= 1;
2247 #ifdef ENABLE_CHECKING
2251 lra_live_range_iter
= lra_coalesce_iter
= 0;
2252 lra_constraint_iter
= lra_constraint_iter_after_spill
= 0;
2253 lra_inheritance_iter
= lra_undo_inheritance_iter
= 0;
2255 setup_reg_spill_flag ();
2257 /* Function remove_scratches can creates new pseudos for clobbers --
2258 so set up lra_constraint_new_regno_start before its call to
2259 permit changing reg classes for pseudos created by this
2261 lra_constraint_new_regno_start
= lra_new_regno_start
= max_reg_num ();
2262 remove_scratches ();
2263 scratch_p
= lra_constraint_new_regno_start
!= max_reg_num ();
2265 /* A function that has a non-local label that can reach the exit
2266 block via non-exceptional paths must save all call-saved
2268 if (cfun
->has_nonlocal_label
&& has_nonexceptional_receiver ())
2269 crtl
->saves_all_registers
= 1;
2271 if (crtl
->saves_all_registers
)
2272 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2273 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
2274 df_set_regs_ever_live (i
, true);
2276 /* We don't DF from now and avoid its using because it is to
2277 expensive when a lot of RTL changes are made. */
2278 df_set_flags (DF_NO_INSN_RESCAN
);
2279 lra_constraint_insn_stack
.create (get_max_uid ());
2280 lra_constraint_insn_stack_bitmap
= sbitmap_alloc (get_max_uid ());
2281 bitmap_clear (lra_constraint_insn_stack_bitmap
);
2282 lra_live_ranges_init ();
2283 lra_constraints_init ();
2284 lra_curr_reload_num
= 0;
2285 push_insns (get_last_insn (), NULL_RTX
);
2286 /* It is needed for the 1st coalescing. */
2287 lra_constraint_new_insn_uid_start
= get_max_uid ();
2288 bitmap_initialize (&lra_inheritance_pseudos
, ®_obstack
);
2289 bitmap_initialize (&lra_split_regs
, ®_obstack
);
2290 bitmap_initialize (&lra_optional_reload_pseudos
, ®_obstack
);
2291 bitmap_initialize (&lra_subreg_reload_pseudos
, ®_obstack
);
2293 if (get_frame_size () != 0 && crtl
->stack_alignment_needed
)
2294 /* If we have a stack frame, we must align it now. The stack size
2295 may be a part of the offset computation for register
2297 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
2302 /* We should try to assign hard registers to scratches even
2303 if there were no RTL transformations in
2305 if (! lra_constraints (lra_constraint_iter
== 0)
2306 && (lra_constraint_iter
> 1
2307 || (! scratch_p
&& ! caller_save_needed
)))
2309 /* Constraint transformations may result in that eliminable
2310 hard regs become uneliminable and pseudos which use them
2311 should be spilled. It is better to do it before pseudo
2314 For example, rs6000 can make
2315 RS6000_PIC_OFFSET_TABLE_REGNUM uneliminable if we started
2316 to use a constant pool. */
2317 lra_eliminate (false);
2318 /* Do inheritance only for regular algorithms. */
2322 lra_clear_live_ranges ();
2323 /* We need live ranges for lra_assign -- so build them. */
2324 lra_create_live_ranges (true);
2326 /* If we don't spill non-reload and non-inheritance pseudos,
2327 there is no sense to run memory-memory move coalescing.
2328 If inheritance pseudos were spilled, the memory-memory
2329 moves involving them will be removed by pass undoing
2335 bool spill_p
= !lra_assign ();
2337 if (lra_undo_inheritance ())
2343 lra_create_live_ranges (true);
2346 if (lra_coalesce ())
2350 lra_clear_live_ranges ();
2353 /* Don't clear optional reloads bitmap until all constraints are
2354 satisfied as we need to differ them from regular reloads. */
2355 bitmap_clear (&lra_optional_reload_pseudos
);
2356 bitmap_clear (&lra_subreg_reload_pseudos
);
2357 bitmap_clear (&lra_inheritance_pseudos
);
2358 bitmap_clear (&lra_split_regs
);
2359 if (! lra_need_for_spills_p ())
2363 /* We need full live info for spilling pseudos into
2364 registers instead of memory. */
2365 lra_create_live_ranges (lra_reg_spill_p
);
2369 /* Assignment of stack slots changes elimination offsets for
2370 some eliminations. So update the offsets here. */
2371 lra_eliminate (false);
2372 lra_constraint_new_regno_start
= max_reg_num ();
2373 lra_constraint_new_insn_uid_start
= get_max_uid ();
2374 lra_constraint_iter_after_spill
= 0;
2376 restore_scratches ();
2377 lra_eliminate (true);
2378 lra_final_code_change ();
2379 lra_in_progress
= 0;
2381 lra_clear_live_ranges ();
2382 lra_live_ranges_finish ();
2383 lra_constraints_finish ();
2385 sbitmap_free (lra_constraint_insn_stack_bitmap
);
2386 lra_constraint_insn_stack
.release ();
2387 finish_insn_recog_data ();
2388 regstat_free_n_sets_and_refs ();
2390 reload_completed
= 1;
2391 update_inc_notes ();
2393 inserted_p
= fixup_abnormal_edges ();
2395 /* We've possibly turned single trapping insn into multiple ones. */
2396 if (cfun
->can_throw_non_call_exceptions
)
2399 blocks
= sbitmap_alloc (last_basic_block
);
2400 bitmap_ones (blocks
);
2401 find_many_sub_basic_blocks (blocks
);
2402 sbitmap_free (blocks
);
2406 commit_edge_insertions ();
2408 /* Replacing pseudos with their memory equivalents might have
2409 created shared rtx. Subsequent passes would get confused
2410 by this, so unshare everything here. */
2411 unshare_all_rtl_again (get_insns ());
2413 #ifdef ENABLE_CHECKING
2417 timevar_pop (TV_LRA
);
2420 /* Called once per compiler to initialize LRA data once. */
2422 lra_init_once (void)
2424 init_insn_code_data_once ();
2427 /* Initialize LRA whenever register-related information is changed. */
2431 init_op_alt_data ();
2434 /* Called once per compiler to finish LRA data which are initialize
2437 lra_finish_once (void)
2439 finish_insn_code_data_once ();