1 @c Copyright (C) 1988-2013 Free Software Foundation, Inc.
2 @c This is part of the GCC manual.
3 @c For copying conditions, see the file gcc.texi.
7 @chapter Machine Descriptions
8 @cindex machine descriptions
10 A machine description has two parts: a file of instruction patterns
11 (@file{.md} file) and a C header file of macro definitions.
13 The @file{.md} file for a target machine contains a pattern for each
14 instruction that the target machine supports (or at least each instruction
15 that is worth telling the compiler about). It may also contain comments.
16 A semicolon causes the rest of the line to be a comment, unless the semicolon
17 is inside a quoted string.
19 See the next chapter for information on the C header file.
22 * Overview:: How the machine description is used.
23 * Patterns:: How to write instruction patterns.
24 * Example:: An explained example of a @code{define_insn} pattern.
25 * RTL Template:: The RTL template defines what insns match a pattern.
26 * Output Template:: The output template says how to make assembler code
28 * Output Statement:: For more generality, write C code to output
30 * Predicates:: Controlling what kinds of operands can be used
32 * Constraints:: Fine-tuning operand selection.
33 * Standard Names:: Names mark patterns to use for code generation.
34 * Pattern Ordering:: When the order of patterns makes a difference.
35 * Dependent Patterns:: Having one pattern may make you need another.
36 * Jump Patterns:: Special considerations for patterns for jump insns.
37 * Looping Patterns:: How to define patterns for special looping insns.
38 * Insn Canonicalizations::Canonicalization of Instructions
39 * Expander Definitions::Generating a sequence of several RTL insns
40 for a standard operation.
41 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
42 * Including Patterns:: Including Patterns in Machine Descriptions.
43 * Peephole Definitions::Defining machine-specific peephole optimizations.
44 * Insn Attributes:: Specifying the value of attributes for generated insns.
45 * Conditional Execution::Generating @code{define_insn} patterns for
47 * Define Subst:: Generating @code{define_insn} and @code{define_expand}
48 patterns from other patterns.
49 * Constant Definitions::Defining symbolic constants that can be used in the
51 * Iterators:: Using iterators to generate patterns from a template.
55 @section Overview of How the Machine Description is Used
57 There are three main conversions that happen in the compiler:
62 The front end reads the source code and builds a parse tree.
65 The parse tree is used to generate an RTL insn list based on named
69 The insn list is matched against the RTL templates to produce assembler
74 For the generate pass, only the names of the insns matter, from either a
75 named @code{define_insn} or a @code{define_expand}. The compiler will
76 choose the pattern with the right name and apply the operands according
77 to the documentation later in this chapter, without regard for the RTL
78 template or operand constraints. Note that the names the compiler looks
79 for are hard-coded in the compiler---it will ignore unnamed patterns and
80 patterns with names it doesn't know about, but if you don't provide a
81 named pattern it needs, it will abort.
83 If a @code{define_insn} is used, the template given is inserted into the
84 insn list. If a @code{define_expand} is used, one of three things
85 happens, based on the condition logic. The condition logic may manually
86 create new insns for the insn list, say via @code{emit_insn()}, and
87 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
88 compiler to use an alternate way of performing that task. If it invokes
89 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
90 is inserted, as if the @code{define_expand} were a @code{define_insn}.
92 Once the insn list is generated, various optimization passes convert,
93 replace, and rearrange the insns in the insn list. This is where the
94 @code{define_split} and @code{define_peephole} patterns get used, for
97 Finally, the insn list's RTL is matched up with the RTL templates in the
98 @code{define_insn} patterns, and those patterns are used to emit the
99 final assembly code. For this purpose, each named @code{define_insn}
100 acts like it's unnamed, since the names are ignored.
103 @section Everything about Instruction Patterns
105 @cindex instruction patterns
108 Each instruction pattern contains an incomplete RTL expression, with pieces
109 to be filled in later, operand constraints that restrict how the pieces can
110 be filled in, and an output pattern or C code to generate the assembler
111 output, all wrapped up in a @code{define_insn} expression.
113 A @code{define_insn} is an RTL expression containing four or five operands:
117 An optional name. The presence of a name indicate that this instruction
118 pattern can perform a certain standard job for the RTL-generation
119 pass of the compiler. This pass knows certain names and will use
120 the instruction patterns with those names, if the names are defined
121 in the machine description.
123 The absence of a name is indicated by writing an empty string
124 where the name should go. Nameless instruction patterns are never
125 used for generating RTL code, but they may permit several simpler insns
126 to be combined later on.
128 Names that are not thus known and used in RTL-generation have no
129 effect; they are equivalent to no name at all.
131 For the purpose of debugging the compiler, you may also specify a
132 name beginning with the @samp{*} character. Such a name is used only
133 for identifying the instruction in RTL dumps; it is entirely equivalent
134 to having a nameless pattern for all other purposes.
137 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
138 RTL expressions which show what the instruction should look like. It is
139 incomplete because it may contain @code{match_operand},
140 @code{match_operator}, and @code{match_dup} expressions that stand for
141 operands of the instruction.
143 If the vector has only one element, that element is the template for the
144 instruction pattern. If the vector has multiple elements, then the
145 instruction pattern is a @code{parallel} expression containing the
149 @cindex pattern conditions
150 @cindex conditions, in patterns
151 A condition. This is a string which contains a C expression that is
152 the final test to decide whether an insn body matches this pattern.
154 @cindex named patterns and conditions
155 For a named pattern, the condition (if present) may not depend on
156 the data in the insn being matched, but only the target-machine-type
157 flags. The compiler needs to test these conditions during
158 initialization in order to learn exactly which named instructions are
159 available in a particular run.
162 For nameless patterns, the condition is applied only when matching an
163 individual insn, and only after the insn has matched the pattern's
164 recognition template. The insn's operands may be found in the vector
165 @code{operands}. For an insn where the condition has once matched, it
166 can't be used to control register allocation, for example by excluding
167 certain hard registers or hard register combinations.
170 The @dfn{output template}: a string that says how to output matching
171 insns as assembler code. @samp{%} in this string specifies where
172 to substitute the value of an operand. @xref{Output Template}.
174 When simple substitution isn't general enough, you can specify a piece
175 of C code to compute the output. @xref{Output Statement}.
178 Optionally, a vector containing the values of attributes for insns matching
179 this pattern. @xref{Insn Attributes}.
183 @section Example of @code{define_insn}
184 @cindex @code{define_insn} example
186 Here is an actual example of an instruction pattern, for the 68000/68020.
191 (match_operand:SI 0 "general_operand" "rm"))]
195 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
197 return \"cmpl #0,%0\";
202 This can also be written using braced strings:
207 (match_operand:SI 0 "general_operand" "rm"))]
210 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
216 This is an instruction that sets the condition codes based on the value of
217 a general operand. It has no condition, so any insn whose RTL description
218 has the form shown may be handled according to this pattern. The name
219 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
220 pass that, when it is necessary to test such a value, an insn to do so
221 can be constructed using this pattern.
223 The output control string is a piece of C code which chooses which
224 output template to return based on the kind of operand and the specific
225 type of CPU for which code is being generated.
227 @samp{"rm"} is an operand constraint. Its meaning is explained below.
230 @section RTL Template
231 @cindex RTL insn template
232 @cindex generating insns
233 @cindex insns, generating
234 @cindex recognizing insns
235 @cindex insns, recognizing
237 The RTL template is used to define which insns match the particular pattern
238 and how to find their operands. For named patterns, the RTL template also
239 says how to construct an insn from specified operands.
241 Construction involves substituting specified operands into a copy of the
242 template. Matching involves determining the values that serve as the
243 operands in the insn being matched. Both of these activities are
244 controlled by special expression types that direct matching and
245 substitution of the operands.
248 @findex match_operand
249 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
250 This expression is a placeholder for operand number @var{n} of
251 the insn. When constructing an insn, operand number @var{n}
252 will be substituted at this point. When matching an insn, whatever
253 appears at this position in the insn will be taken as operand
254 number @var{n}; but it must satisfy @var{predicate} or this instruction
255 pattern will not match at all.
257 Operand numbers must be chosen consecutively counting from zero in
258 each instruction pattern. There may be only one @code{match_operand}
259 expression in the pattern for each operand number. Usually operands
260 are numbered in the order of appearance in @code{match_operand}
261 expressions. In the case of a @code{define_expand}, any operand numbers
262 used only in @code{match_dup} expressions have higher values than all
263 other operand numbers.
265 @var{predicate} is a string that is the name of a function that
266 accepts two arguments, an expression and a machine mode.
267 @xref{Predicates}. During matching, the function will be called with
268 the putative operand as the expression and @var{m} as the mode
269 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
270 which normally causes @var{predicate} to accept any mode). If it
271 returns zero, this instruction pattern fails to match.
272 @var{predicate} may be an empty string; then it means no test is to be
273 done on the operand, so anything which occurs in this position is
276 Most of the time, @var{predicate} will reject modes other than @var{m}---but
277 not always. For example, the predicate @code{address_operand} uses
278 @var{m} as the mode of memory ref that the address should be valid for.
279 Many predicates accept @code{const_int} nodes even though their mode is
282 @var{constraint} controls reloading and the choice of the best register
283 class to use for a value, as explained later (@pxref{Constraints}).
284 If the constraint would be an empty string, it can be omitted.
286 People are often unclear on the difference between the constraint and the
287 predicate. The predicate helps decide whether a given insn matches the
288 pattern. The constraint plays no role in this decision; instead, it
289 controls various decisions in the case of an insn which does match.
291 @findex match_scratch
292 @item (match_scratch:@var{m} @var{n} @var{constraint})
293 This expression is also a placeholder for operand number @var{n}
294 and indicates that operand must be a @code{scratch} or @code{reg}
297 When matching patterns, this is equivalent to
300 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
303 but, when generating RTL, it produces a (@code{scratch}:@var{m})
306 If the last few expressions in a @code{parallel} are @code{clobber}
307 expressions whose operands are either a hard register or
308 @code{match_scratch}, the combiner can add or delete them when
309 necessary. @xref{Side Effects}.
312 @item (match_dup @var{n})
313 This expression is also a placeholder for operand number @var{n}.
314 It is used when the operand needs to appear more than once in the
317 In construction, @code{match_dup} acts just like @code{match_operand}:
318 the operand is substituted into the insn being constructed. But in
319 matching, @code{match_dup} behaves differently. It assumes that operand
320 number @var{n} has already been determined by a @code{match_operand}
321 appearing earlier in the recognition template, and it matches only an
322 identical-looking expression.
324 Note that @code{match_dup} should not be used to tell the compiler that
325 a particular register is being used for two operands (example:
326 @code{add} that adds one register to another; the second register is
327 both an input operand and the output operand). Use a matching
328 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
329 operand is used in two places in the template, such as an instruction
330 that computes both a quotient and a remainder, where the opcode takes
331 two input operands but the RTL template has to refer to each of those
332 twice; once for the quotient pattern and once for the remainder pattern.
334 @findex match_operator
335 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
336 This pattern is a kind of placeholder for a variable RTL expression
339 When constructing an insn, it stands for an RTL expression whose
340 expression code is taken from that of operand @var{n}, and whose
341 operands are constructed from the patterns @var{operands}.
343 When matching an expression, it matches an expression if the function
344 @var{predicate} returns nonzero on that expression @emph{and} the
345 patterns @var{operands} match the operands of the expression.
347 Suppose that the function @code{commutative_operator} is defined as
348 follows, to match any expression whose operator is one of the
349 commutative arithmetic operators of RTL and whose mode is @var{mode}:
353 commutative_integer_operator (x, mode)
355 enum machine_mode mode;
357 enum rtx_code code = GET_CODE (x);
358 if (GET_MODE (x) != mode)
360 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
361 || code == EQ || code == NE);
365 Then the following pattern will match any RTL expression consisting
366 of a commutative operator applied to two general operands:
369 (match_operator:SI 3 "commutative_operator"
370 [(match_operand:SI 1 "general_operand" "g")
371 (match_operand:SI 2 "general_operand" "g")])
374 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
375 because the expressions to be matched all contain two operands.
377 When this pattern does match, the two operands of the commutative
378 operator are recorded as operands 1 and 2 of the insn. (This is done
379 by the two instances of @code{match_operand}.) Operand 3 of the insn
380 will be the entire commutative expression: use @code{GET_CODE
381 (operands[3])} to see which commutative operator was used.
383 The machine mode @var{m} of @code{match_operator} works like that of
384 @code{match_operand}: it is passed as the second argument to the
385 predicate function, and that function is solely responsible for
386 deciding whether the expression to be matched ``has'' that mode.
388 When constructing an insn, argument 3 of the gen-function will specify
389 the operation (i.e.@: the expression code) for the expression to be
390 made. It should be an RTL expression, whose expression code is copied
391 into a new expression whose operands are arguments 1 and 2 of the
392 gen-function. The subexpressions of argument 3 are not used;
393 only its expression code matters.
395 When @code{match_operator} is used in a pattern for matching an insn,
396 it usually best if the operand number of the @code{match_operator}
397 is higher than that of the actual operands of the insn. This improves
398 register allocation because the register allocator often looks at
399 operands 1 and 2 of insns to see if it can do register tying.
401 There is no way to specify constraints in @code{match_operator}. The
402 operand of the insn which corresponds to the @code{match_operator}
403 never has any constraints because it is never reloaded as a whole.
404 However, if parts of its @var{operands} are matched by
405 @code{match_operand} patterns, those parts may have constraints of
409 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
410 Like @code{match_dup}, except that it applies to operators instead of
411 operands. When constructing an insn, operand number @var{n} will be
412 substituted at this point. But in matching, @code{match_op_dup} behaves
413 differently. It assumes that operand number @var{n} has already been
414 determined by a @code{match_operator} appearing earlier in the
415 recognition template, and it matches only an identical-looking
418 @findex match_parallel
419 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
420 This pattern is a placeholder for an insn that consists of a
421 @code{parallel} expression with a variable number of elements. This
422 expression should only appear at the top level of an insn pattern.
424 When constructing an insn, operand number @var{n} will be substituted at
425 this point. When matching an insn, it matches if the body of the insn
426 is a @code{parallel} expression with at least as many elements as the
427 vector of @var{subpat} expressions in the @code{match_parallel}, if each
428 @var{subpat} matches the corresponding element of the @code{parallel},
429 @emph{and} the function @var{predicate} returns nonzero on the
430 @code{parallel} that is the body of the insn. It is the responsibility
431 of the predicate to validate elements of the @code{parallel} beyond
432 those listed in the @code{match_parallel}.
434 A typical use of @code{match_parallel} is to match load and store
435 multiple expressions, which can contain a variable number of elements
436 in a @code{parallel}. For example,
440 [(match_parallel 0 "load_multiple_operation"
441 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
442 (match_operand:SI 2 "memory_operand" "m"))
444 (clobber (reg:SI 179))])]
449 This example comes from @file{a29k.md}. The function
450 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
451 that subsequent elements in the @code{parallel} are the same as the
452 @code{set} in the pattern, except that they are referencing subsequent
453 registers and memory locations.
455 An insn that matches this pattern might look like:
459 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
461 (clobber (reg:SI 179))
463 (mem:SI (plus:SI (reg:SI 100)
466 (mem:SI (plus:SI (reg:SI 100)
470 @findex match_par_dup
471 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
472 Like @code{match_op_dup}, but for @code{match_parallel} instead of
473 @code{match_operator}.
477 @node Output Template
478 @section Output Templates and Operand Substitution
479 @cindex output templates
480 @cindex operand substitution
482 @cindex @samp{%} in template
484 The @dfn{output template} is a string which specifies how to output the
485 assembler code for an instruction pattern. Most of the template is a
486 fixed string which is output literally. The character @samp{%} is used
487 to specify where to substitute an operand; it can also be used to
488 identify places where different variants of the assembler require
491 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
492 operand @var{n} at that point in the string.
494 @samp{%} followed by a letter and a digit says to output an operand in an
495 alternate fashion. Four letters have standard, built-in meanings described
496 below. The machine description macro @code{PRINT_OPERAND} can define
497 additional letters with nonstandard meanings.
499 @samp{%c@var{digit}} can be used to substitute an operand that is a
500 constant value without the syntax that normally indicates an immediate
503 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
504 the constant is negated before printing.
506 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
507 memory reference, with the actual operand treated as the address. This may
508 be useful when outputting a ``load address'' instruction, because often the
509 assembler syntax for such an instruction requires you to write the operand
510 as if it were a memory reference.
512 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
515 @samp{%=} outputs a number which is unique to each instruction in the
516 entire compilation. This is useful for making local labels to be
517 referred to more than once in a single template that generates multiple
518 assembler instructions.
520 @samp{%} followed by a punctuation character specifies a substitution that
521 does not use an operand. Only one case is standard: @samp{%%} outputs a
522 @samp{%} into the assembler code. Other nonstandard cases can be
523 defined in the @code{PRINT_OPERAND} macro. You must also define
524 which punctuation characters are valid with the
525 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
529 The template may generate multiple assembler instructions. Write the text
530 for the instructions, with @samp{\;} between them.
532 @cindex matching operands
533 When the RTL contains two operands which are required by constraint to match
534 each other, the output template must refer only to the lower-numbered operand.
535 Matching operands are not always identical, and the rest of the compiler
536 arranges to put the proper RTL expression for printing into the lower-numbered
539 One use of nonstandard letters or punctuation following @samp{%} is to
540 distinguish between different assembler languages for the same machine; for
541 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
542 requires periods in most opcode names, while MIT syntax does not. For
543 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
544 syntax. The same file of patterns is used for both kinds of output syntax,
545 but the character sequence @samp{%.} is used in each place where Motorola
546 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
547 defines the sequence to output a period; the macro for MIT syntax defines
550 @cindex @code{#} in template
551 As a special case, a template consisting of the single character @code{#}
552 instructs the compiler to first split the insn, and then output the
553 resulting instructions separately. This helps eliminate redundancy in the
554 output templates. If you have a @code{define_insn} that needs to emit
555 multiple assembler instructions, and there is a matching @code{define_split}
556 already defined, then you can simply use @code{#} as the output template
557 instead of writing an output template that emits the multiple assembler
560 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
561 of the form @samp{@{option0|option1|option2@}} in the templates. These
562 describe multiple variants of assembler language syntax.
563 @xref{Instruction Output}.
565 @node Output Statement
566 @section C Statements for Assembler Output
567 @cindex output statements
568 @cindex C statements for assembler output
569 @cindex generating assembler output
571 Often a single fixed template string cannot produce correct and efficient
572 assembler code for all the cases that are recognized by a single
573 instruction pattern. For example, the opcodes may depend on the kinds of
574 operands; or some unfortunate combinations of operands may require extra
575 machine instructions.
577 If the output control string starts with a @samp{@@}, then it is actually
578 a series of templates, each on a separate line. (Blank lines and
579 leading spaces and tabs are ignored.) The templates correspond to the
580 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
581 if a target machine has a two-address add instruction @samp{addr} to add
582 into a register and another @samp{addm} to add a register to memory, you
583 might write this pattern:
586 (define_insn "addsi3"
587 [(set (match_operand:SI 0 "general_operand" "=r,m")
588 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
589 (match_operand:SI 2 "general_operand" "g,r")))]
596 @cindex @code{*} in template
597 @cindex asterisk in template
598 If the output control string starts with a @samp{*}, then it is not an
599 output template but rather a piece of C program that should compute a
600 template. It should execute a @code{return} statement to return the
601 template-string you want. Most such templates use C string literals, which
602 require doublequote characters to delimit them. To include these
603 doublequote characters in the string, prefix each one with @samp{\}.
605 If the output control string is written as a brace block instead of a
606 double-quoted string, it is automatically assumed to be C code. In that
607 case, it is not necessary to put in a leading asterisk, or to escape the
608 doublequotes surrounding C string literals.
610 The operands may be found in the array @code{operands}, whose C data type
613 It is very common to select different ways of generating assembler code
614 based on whether an immediate operand is within a certain range. Be
615 careful when doing this, because the result of @code{INTVAL} is an
616 integer on the host machine. If the host machine has more bits in an
617 @code{int} than the target machine has in the mode in which the constant
618 will be used, then some of the bits you get from @code{INTVAL} will be
619 superfluous. For proper results, you must carefully disregard the
620 values of those bits.
622 @findex output_asm_insn
623 It is possible to output an assembler instruction and then go on to output
624 or compute more of them, using the subroutine @code{output_asm_insn}. This
625 receives two arguments: a template-string and a vector of operands. The
626 vector may be @code{operands}, or it may be another array of @code{rtx}
627 that you declare locally and initialize yourself.
629 @findex which_alternative
630 When an insn pattern has multiple alternatives in its constraints, often
631 the appearance of the assembler code is determined mostly by which alternative
632 was matched. When this is so, the C code can test the variable
633 @code{which_alternative}, which is the ordinal number of the alternative
634 that was actually satisfied (0 for the first, 1 for the second alternative,
637 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
638 for registers and @samp{clrmem} for memory locations. Here is how
639 a pattern could use @code{which_alternative} to choose between them:
643 [(set (match_operand:SI 0 "general_operand" "=r,m")
647 return (which_alternative == 0
648 ? "clrreg %0" : "clrmem %0");
652 The example above, where the assembler code to generate was
653 @emph{solely} determined by the alternative, could also have been specified
654 as follows, having the output control string start with a @samp{@@}:
659 [(set (match_operand:SI 0 "general_operand" "=r,m")
668 If you just need a little bit of C code in one (or a few) alternatives,
669 you can use @samp{*} inside of a @samp{@@} multi-alternative template:
674 [(set (match_operand:SI 0 "general_operand" "=r,<,m")
679 * return stack_mem_p (operands[0]) ? \"push 0\" : \"clrmem %0\";
687 @cindex operand predicates
688 @cindex operator predicates
690 A predicate determines whether a @code{match_operand} or
691 @code{match_operator} expression matches, and therefore whether the
692 surrounding instruction pattern will be used for that combination of
693 operands. GCC has a number of machine-independent predicates, and you
694 can define machine-specific predicates as needed. By convention,
695 predicates used with @code{match_operand} have names that end in
696 @samp{_operand}, and those used with @code{match_operator} have names
697 that end in @samp{_operator}.
699 All predicates are Boolean functions (in the mathematical sense) of
700 two arguments: the RTL expression that is being considered at that
701 position in the instruction pattern, and the machine mode that the
702 @code{match_operand} or @code{match_operator} specifies. In this
703 section, the first argument is called @var{op} and the second argument
704 @var{mode}. Predicates can be called from C as ordinary two-argument
705 functions; this can be useful in output templates or other
706 machine-specific code.
708 Operand predicates can allow operands that are not actually acceptable
709 to the hardware, as long as the constraints give reload the ability to
710 fix them up (@pxref{Constraints}). However, GCC will usually generate
711 better code if the predicates specify the requirements of the machine
712 instructions as closely as possible. Reload cannot fix up operands
713 that must be constants (``immediate operands''); you must use a
714 predicate that allows only constants, or else enforce the requirement
715 in the extra condition.
717 @cindex predicates and machine modes
718 @cindex normal predicates
719 @cindex special predicates
720 Most predicates handle their @var{mode} argument in a uniform manner.
721 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
722 any mode. If @var{mode} is anything else, then @var{op} must have the
723 same mode, unless @var{op} is a @code{CONST_INT} or integer
724 @code{CONST_DOUBLE}. These RTL expressions always have
725 @code{VOIDmode}, so it would be counterproductive to check that their
726 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
727 integer @code{CONST_DOUBLE} check that the value stored in the
728 constant will fit in the requested mode.
730 Predicates with this behavior are called @dfn{normal}.
731 @command{genrecog} can optimize the instruction recognizer based on
732 knowledge of how normal predicates treat modes. It can also diagnose
733 certain kinds of common errors in the use of normal predicates; for
734 instance, it is almost always an error to use a normal predicate
735 without specifying a mode.
737 Predicates that do something different with their @var{mode} argument
738 are called @dfn{special}. The generic predicates
739 @code{address_operand} and @code{pmode_register_operand} are special
740 predicates. @command{genrecog} does not do any optimizations or
741 diagnosis when special predicates are used.
744 * Machine-Independent Predicates:: Predicates available to all back ends.
745 * Defining Predicates:: How to write machine-specific predicate
749 @node Machine-Independent Predicates
750 @subsection Machine-Independent Predicates
751 @cindex machine-independent predicates
752 @cindex generic predicates
754 These are the generic predicates available to all back ends. They are
755 defined in @file{recog.c}. The first category of predicates allow
756 only constant, or @dfn{immediate}, operands.
758 @defun immediate_operand
759 This predicate allows any sort of constant that fits in @var{mode}.
760 It is an appropriate choice for instructions that take operands that
764 @defun const_int_operand
765 This predicate allows any @code{CONST_INT} expression that fits in
766 @var{mode}. It is an appropriate choice for an immediate operand that
767 does not allow a symbol or label.
770 @defun const_double_operand
771 This predicate accepts any @code{CONST_DOUBLE} expression that has
772 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
773 accept @code{CONST_INT}. It is intended for immediate floating point
778 The second category of predicates allow only some kind of machine
781 @defun register_operand
782 This predicate allows any @code{REG} or @code{SUBREG} expression that
783 is valid for @var{mode}. It is often suitable for arithmetic
784 instruction operands on a RISC machine.
787 @defun pmode_register_operand
788 This is a slight variant on @code{register_operand} which works around
789 a limitation in the machine-description reader.
792 (match_operand @var{n} "pmode_register_operand" @var{constraint})
799 (match_operand:P @var{n} "register_operand" @var{constraint})
803 would mean, if the machine-description reader accepted @samp{:P}
804 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
805 alias for some other mode, and might vary with machine-specific
806 options. @xref{Misc}.
809 @defun scratch_operand
810 This predicate allows hard registers and @code{SCRATCH} expressions,
811 but not pseudo-registers. It is used internally by @code{match_scratch};
812 it should not be used directly.
816 The third category of predicates allow only some kind of memory reference.
818 @defun memory_operand
819 This predicate allows any valid reference to a quantity of mode
820 @var{mode} in memory, as determined by the weak form of
821 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
824 @defun address_operand
825 This predicate is a little unusual; it allows any operand that is a
826 valid expression for the @emph{address} of a quantity of mode
827 @var{mode}, again determined by the weak form of
828 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
829 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
830 @code{memory_operand}, then @var{exp} is acceptable to
831 @code{address_operand}. Note that @var{exp} does not necessarily have
835 @defun indirect_operand
836 This is a stricter form of @code{memory_operand} which allows only
837 memory references with a @code{general_operand} as the address
838 expression. New uses of this predicate are discouraged, because
839 @code{general_operand} is very permissive, so it's hard to tell what
840 an @code{indirect_operand} does or does not allow. If a target has
841 different requirements for memory operands for different instructions,
842 it is better to define target-specific predicates which enforce the
843 hardware's requirements explicitly.
847 This predicate allows a memory reference suitable for pushing a value
848 onto the stack. This will be a @code{MEM} which refers to
849 @code{stack_pointer_rtx}, with a side-effect in its address expression
850 (@pxref{Incdec}); which one is determined by the
851 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
855 This predicate allows a memory reference suitable for popping a value
856 off the stack. Again, this will be a @code{MEM} referring to
857 @code{stack_pointer_rtx}, with a side-effect in its address
858 expression. However, this time @code{STACK_POP_CODE} is expected.
862 The fourth category of predicates allow some combination of the above
865 @defun nonmemory_operand
866 This predicate allows any immediate or register operand valid for @var{mode}.
869 @defun nonimmediate_operand
870 This predicate allows any register or memory operand valid for @var{mode}.
873 @defun general_operand
874 This predicate allows any immediate, register, or memory operand
875 valid for @var{mode}.
879 Finally, there are two generic operator predicates.
881 @defun comparison_operator
882 This predicate matches any expression which performs an arithmetic
883 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
887 @defun ordered_comparison_operator
888 This predicate matches any expression which performs an arithmetic
889 comparison in @var{mode} and whose expression code is valid for integer
890 modes; that is, the expression code will be one of @code{eq}, @code{ne},
891 @code{lt}, @code{ltu}, @code{le}, @code{leu}, @code{gt}, @code{gtu},
892 @code{ge}, @code{geu}.
895 @node Defining Predicates
896 @subsection Defining Machine-Specific Predicates
897 @cindex defining predicates
898 @findex define_predicate
899 @findex define_special_predicate
901 Many machines have requirements for their operands that cannot be
902 expressed precisely using the generic predicates. You can define
903 additional predicates using @code{define_predicate} and
904 @code{define_special_predicate} expressions. These expressions have
909 The name of the predicate, as it will be referred to in
910 @code{match_operand} or @code{match_operator} expressions.
913 An RTL expression which evaluates to true if the predicate allows the
914 operand @var{op}, false if it does not. This expression can only use
915 the following RTL codes:
919 When written inside a predicate expression, a @code{MATCH_OPERAND}
920 expression evaluates to true if the predicate it names would allow
921 @var{op}. The operand number and constraint are ignored. Due to
922 limitations in @command{genrecog}, you can only refer to generic
923 predicates and predicates that have already been defined.
926 This expression evaluates to true if @var{op} or a specified
927 subexpression of @var{op} has one of a given list of RTX codes.
929 The first operand of this expression is a string constant containing a
930 comma-separated list of RTX code names (in lower case). These are the
931 codes for which the @code{MATCH_CODE} will be true.
933 The second operand is a string constant which indicates what
934 subexpression of @var{op} to examine. If it is absent or the empty
935 string, @var{op} itself is examined. Otherwise, the string constant
936 must be a sequence of digits and/or lowercase letters. Each character
937 indicates a subexpression to extract from the current expression; for
938 the first character this is @var{op}, for the second and subsequent
939 characters it is the result of the previous character. A digit
940 @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l}
941 extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the
942 alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
943 @code{MATCH_CODE} then examines the RTX code of the subexpression
944 extracted by the complete string. It is not possible to extract
945 components of an @code{rtvec} that is not at position 0 within its RTX
949 This expression has one operand, a string constant containing a C
950 expression. The predicate's arguments, @var{op} and @var{mode}, are
951 available with those names in the C expression. The @code{MATCH_TEST}
952 evaluates to true if the C expression evaluates to a nonzero value.
953 @code{MATCH_TEST} expressions must not have side effects.
959 The basic @samp{MATCH_} expressions can be combined using these
960 logical operators, which have the semantics of the C operators
961 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
962 in Common Lisp, you may give an @code{AND} or @code{IOR} expression an
963 arbitrary number of arguments; this has exactly the same effect as
964 writing a chain of two-argument @code{AND} or @code{IOR} expressions.
968 An optional block of C code, which should execute
969 @samp{@w{return true}} if the predicate is found to match and
970 @samp{@w{return false}} if it does not. It must not have any side
971 effects. The predicate arguments, @var{op} and @var{mode}, are
972 available with those names.
974 If a code block is present in a predicate definition, then the RTL
975 expression must evaluate to true @emph{and} the code block must
976 execute @samp{@w{return true}} for the predicate to allow the operand.
977 The RTL expression is evaluated first; do not re-check anything in the
978 code block that was checked in the RTL expression.
981 The program @command{genrecog} scans @code{define_predicate} and
982 @code{define_special_predicate} expressions to determine which RTX
983 codes are possibly allowed. You should always make this explicit in
984 the RTL predicate expression, using @code{MATCH_OPERAND} and
987 Here is an example of a simple predicate definition, from the IA64
992 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
993 (define_predicate "small_addr_symbolic_operand"
994 (and (match_code "symbol_ref")
995 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
1000 And here is another, showing the use of the C block.
1004 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
1005 (define_predicate "gr_register_operand"
1006 (match_operand 0 "register_operand")
1009 if (GET_CODE (op) == SUBREG)
1010 op = SUBREG_REG (op);
1013 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
1018 Predicates written with @code{define_predicate} automatically include
1019 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
1020 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
1021 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
1022 integer @code{CONST_DOUBLE}, nor do they test that the value of either
1023 kind of constant fits in the requested mode. This is because
1024 target-specific predicates that take constants usually have to do more
1025 stringent value checks anyway. If you need the exact same treatment
1026 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
1027 provide, use a @code{MATCH_OPERAND} subexpression to call
1028 @code{const_int_operand}, @code{const_double_operand}, or
1029 @code{immediate_operand}.
1031 Predicates written with @code{define_special_predicate} do not get any
1032 automatic mode checks, and are treated as having special mode handling
1033 by @command{genrecog}.
1035 The program @command{genpreds} is responsible for generating code to
1036 test predicates. It also writes a header file containing function
1037 declarations for all machine-specific predicates. It is not necessary
1038 to declare these predicates in @file{@var{cpu}-protos.h}.
1041 @c Most of this node appears by itself (in a different place) even
1042 @c when the INTERNALS flag is clear. Passages that require the internals
1043 @c manual's context are conditionalized to appear only in the internals manual.
1046 @section Operand Constraints
1047 @cindex operand constraints
1050 Each @code{match_operand} in an instruction pattern can specify
1051 constraints for the operands allowed. The constraints allow you to
1052 fine-tune matching within the set of operands allowed by the
1058 @section Constraints for @code{asm} Operands
1059 @cindex operand constraints, @code{asm}
1060 @cindex constraints, @code{asm}
1061 @cindex @code{asm} constraints
1063 Here are specific details on what constraint letters you can use with
1064 @code{asm} operands.
1066 Constraints can say whether
1067 an operand may be in a register, and which kinds of register; whether the
1068 operand can be a memory reference, and which kinds of address; whether the
1069 operand may be an immediate constant, and which possible values it may
1070 have. Constraints can also require two operands to match.
1071 Side-effects aren't allowed in operands of inline @code{asm}, unless
1072 @samp{<} or @samp{>} constraints are used, because there is no guarantee
1073 that the side-effects will happen exactly once in an instruction that can update
1074 the addressing register.
1078 * Simple Constraints:: Basic use of constraints.
1079 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1080 * Class Preferences:: Constraints guide which hard register to put things in.
1081 * Modifiers:: More precise control over effects of constraints.
1082 * Machine Constraints:: Existing constraints for some particular machines.
1083 * Disable Insn Alternatives:: Disable insn alternatives using the @code{enabled} attribute.
1084 * Define Constraints:: How to define machine-specific constraints.
1085 * C Constraint Interface:: How to test constraints from C code.
1091 * Simple Constraints:: Basic use of constraints.
1092 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1093 * Modifiers:: More precise control over effects of constraints.
1094 * Machine Constraints:: Special constraints for some particular machines.
1098 @node Simple Constraints
1099 @subsection Simple Constraints
1100 @cindex simple constraints
1102 The simplest kind of constraint is a string full of letters, each of
1103 which describes one kind of operand that is permitted. Here are
1104 the letters that are allowed:
1108 Whitespace characters are ignored and can be inserted at any position
1109 except the first. This enables each alternative for different operands to
1110 be visually aligned in the machine description even if they have different
1111 number of constraints and modifiers.
1113 @cindex @samp{m} in constraint
1114 @cindex memory references in constraints
1116 A memory operand is allowed, with any kind of address that the machine
1117 supports in general.
1118 Note that the letter used for the general memory constraint can be
1119 re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro.
1121 @cindex offsettable address
1122 @cindex @samp{o} in constraint
1124 A memory operand is allowed, but only if the address is
1125 @dfn{offsettable}. This means that adding a small integer (actually,
1126 the width in bytes of the operand, as determined by its machine mode)
1127 may be added to the address and the result is also a valid memory
1130 @cindex autoincrement/decrement addressing
1131 For example, an address which is constant is offsettable; so is an
1132 address that is the sum of a register and a constant (as long as a
1133 slightly larger constant is also within the range of address-offsets
1134 supported by the machine); but an autoincrement or autodecrement
1135 address is not offsettable. More complicated indirect/indexed
1136 addresses may or may not be offsettable depending on the other
1137 addressing modes that the machine supports.
1139 Note that in an output operand which can be matched by another
1140 operand, the constraint letter @samp{o} is valid only when accompanied
1141 by both @samp{<} (if the target machine has predecrement addressing)
1142 and @samp{>} (if the target machine has preincrement addressing).
1144 @cindex @samp{V} in constraint
1146 A memory operand that is not offsettable. In other words, anything that
1147 would fit the @samp{m} constraint but not the @samp{o} constraint.
1149 @cindex @samp{<} in constraint
1151 A memory operand with autodecrement addressing (either predecrement or
1152 postdecrement) is allowed. In inline @code{asm} this constraint is only
1153 allowed if the operand is used exactly once in an instruction that can
1154 handle the side-effects. Not using an operand with @samp{<} in constraint
1155 string in the inline @code{asm} pattern at all or using it in multiple
1156 instructions isn't valid, because the side-effects wouldn't be performed
1157 or would be performed more than once. Furthermore, on some targets
1158 the operand with @samp{<} in constraint string must be accompanied by
1159 special instruction suffixes like @code{%U0} instruction suffix on PowerPC
1160 or @code{%P0} on IA-64.
1162 @cindex @samp{>} in constraint
1164 A memory operand with autoincrement addressing (either preincrement or
1165 postincrement) is allowed. In inline @code{asm} the same restrictions
1166 as for @samp{<} apply.
1168 @cindex @samp{r} in constraint
1169 @cindex registers in constraints
1171 A register operand is allowed provided that it is in a general
1174 @cindex constants in constraints
1175 @cindex @samp{i} in constraint
1177 An immediate integer operand (one with constant value) is allowed.
1178 This includes symbolic constants whose values will be known only at
1179 assembly time or later.
1181 @cindex @samp{n} in constraint
1183 An immediate integer operand with a known numeric value is allowed.
1184 Many systems cannot support assembly-time constants for operands less
1185 than a word wide. Constraints for these operands should use @samp{n}
1186 rather than @samp{i}.
1188 @cindex @samp{I} in constraint
1189 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1190 Other letters in the range @samp{I} through @samp{P} may be defined in
1191 a machine-dependent fashion to permit immediate integer operands with
1192 explicit integer values in specified ranges. For example, on the
1193 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1194 This is the range permitted as a shift count in the shift
1197 @cindex @samp{E} in constraint
1199 An immediate floating operand (expression code @code{const_double}) is
1200 allowed, but only if the target floating point format is the same as
1201 that of the host machine (on which the compiler is running).
1203 @cindex @samp{F} in constraint
1205 An immediate floating operand (expression code @code{const_double} or
1206 @code{const_vector}) is allowed.
1208 @cindex @samp{G} in constraint
1209 @cindex @samp{H} in constraint
1210 @item @samp{G}, @samp{H}
1211 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1212 permit immediate floating operands in particular ranges of values.
1214 @cindex @samp{s} in constraint
1216 An immediate integer operand whose value is not an explicit integer is
1219 This might appear strange; if an insn allows a constant operand with a
1220 value not known at compile time, it certainly must allow any known
1221 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1222 better code to be generated.
1224 For example, on the 68000 in a fullword instruction it is possible to
1225 use an immediate operand; but if the immediate value is between @minus{}128
1226 and 127, better code results from loading the value into a register and
1227 using the register. This is because the load into the register can be
1228 done with a @samp{moveq} instruction. We arrange for this to happen
1229 by defining the letter @samp{K} to mean ``any integer outside the
1230 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1233 @cindex @samp{g} in constraint
1235 Any register, memory or immediate integer operand is allowed, except for
1236 registers that are not general registers.
1238 @cindex @samp{X} in constraint
1241 Any operand whatsoever is allowed, even if it does not satisfy
1242 @code{general_operand}. This is normally used in the constraint of
1243 a @code{match_scratch} when certain alternatives will not actually
1244 require a scratch register.
1247 Any operand whatsoever is allowed.
1250 @cindex @samp{0} in constraint
1251 @cindex digits in constraint
1252 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1253 An operand that matches the specified operand number is allowed. If a
1254 digit is used together with letters within the same alternative, the
1255 digit should come last.
1257 This number is allowed to be more than a single digit. If multiple
1258 digits are encountered consecutively, they are interpreted as a single
1259 decimal integer. There is scant chance for ambiguity, since to-date
1260 it has never been desirable that @samp{10} be interpreted as matching
1261 either operand 1 @emph{or} operand 0. Should this be desired, one
1262 can use multiple alternatives instead.
1264 @cindex matching constraint
1265 @cindex constraint, matching
1266 This is called a @dfn{matching constraint} and what it really means is
1267 that the assembler has only a single operand that fills two roles
1269 considered separate in the RTL insn. For example, an add insn has two
1270 input operands and one output operand in the RTL, but on most CISC
1273 which @code{asm} distinguishes. For example, an add instruction uses
1274 two input operands and an output operand, but on most CISC
1276 machines an add instruction really has only two operands, one of them an
1277 input-output operand:
1283 Matching constraints are used in these circumstances.
1284 More precisely, the two operands that match must include one input-only
1285 operand and one output-only operand. Moreover, the digit must be a
1286 smaller number than the number of the operand that uses it in the
1290 For operands to match in a particular case usually means that they
1291 are identical-looking RTL expressions. But in a few special cases
1292 specific kinds of dissimilarity are allowed. For example, @code{*x}
1293 as an input operand will match @code{*x++} as an output operand.
1294 For proper results in such cases, the output template should always
1295 use the output-operand's number when printing the operand.
1298 @cindex load address instruction
1299 @cindex push address instruction
1300 @cindex address constraints
1301 @cindex @samp{p} in constraint
1303 An operand that is a valid memory address is allowed. This is
1304 for ``load address'' and ``push address'' instructions.
1306 @findex address_operand
1307 @samp{p} in the constraint must be accompanied by @code{address_operand}
1308 as the predicate in the @code{match_operand}. This predicate interprets
1309 the mode specified in the @code{match_operand} as the mode of the memory
1310 reference for which the address would be valid.
1312 @cindex other register constraints
1313 @cindex extensible constraints
1314 @item @var{other-letters}
1315 Other letters can be defined in machine-dependent fashion to stand for
1316 particular classes of registers or other arbitrary operand types.
1317 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1318 for data, address and floating point registers.
1322 In order to have valid assembler code, each operand must satisfy
1323 its constraint. But a failure to do so does not prevent the pattern
1324 from applying to an insn. Instead, it directs the compiler to modify
1325 the code so that the constraint will be satisfied. Usually this is
1326 done by copying an operand into a register.
1328 Contrast, therefore, the two instruction patterns that follow:
1332 [(set (match_operand:SI 0 "general_operand" "=r")
1333 (plus:SI (match_dup 0)
1334 (match_operand:SI 1 "general_operand" "r")))]
1340 which has two operands, one of which must appear in two places, and
1344 [(set (match_operand:SI 0 "general_operand" "=r")
1345 (plus:SI (match_operand:SI 1 "general_operand" "0")
1346 (match_operand:SI 2 "general_operand" "r")))]
1352 which has three operands, two of which are required by a constraint to be
1353 identical. If we are considering an insn of the form
1356 (insn @var{n} @var{prev} @var{next}
1358 (plus:SI (reg:SI 6) (reg:SI 109)))
1363 the first pattern would not apply at all, because this insn does not
1364 contain two identical subexpressions in the right place. The pattern would
1365 say, ``That does not look like an add instruction; try other patterns''.
1366 The second pattern would say, ``Yes, that's an add instruction, but there
1367 is something wrong with it''. It would direct the reload pass of the
1368 compiler to generate additional insns to make the constraint true. The
1369 results might look like this:
1372 (insn @var{n2} @var{prev} @var{n}
1373 (set (reg:SI 3) (reg:SI 6))
1376 (insn @var{n} @var{n2} @var{next}
1378 (plus:SI (reg:SI 3) (reg:SI 109)))
1382 It is up to you to make sure that each operand, in each pattern, has
1383 constraints that can handle any RTL expression that could be present for
1384 that operand. (When multiple alternatives are in use, each pattern must,
1385 for each possible combination of operand expressions, have at least one
1386 alternative which can handle that combination of operands.) The
1387 constraints don't need to @emph{allow} any possible operand---when this is
1388 the case, they do not constrain---but they must at least point the way to
1389 reloading any possible operand so that it will fit.
1393 If the constraint accepts whatever operands the predicate permits,
1394 there is no problem: reloading is never necessary for this operand.
1396 For example, an operand whose constraints permit everything except
1397 registers is safe provided its predicate rejects registers.
1399 An operand whose predicate accepts only constant values is safe
1400 provided its constraints include the letter @samp{i}. If any possible
1401 constant value is accepted, then nothing less than @samp{i} will do;
1402 if the predicate is more selective, then the constraints may also be
1406 Any operand expression can be reloaded by copying it into a register.
1407 So if an operand's constraints allow some kind of register, it is
1408 certain to be safe. It need not permit all classes of registers; the
1409 compiler knows how to copy a register into another register of the
1410 proper class in order to make an instruction valid.
1412 @cindex nonoffsettable memory reference
1413 @cindex memory reference, nonoffsettable
1415 A nonoffsettable memory reference can be reloaded by copying the
1416 address into a register. So if the constraint uses the letter
1417 @samp{o}, all memory references are taken care of.
1420 A constant operand can be reloaded by allocating space in memory to
1421 hold it as preinitialized data. Then the memory reference can be used
1422 in place of the constant. So if the constraint uses the letters
1423 @samp{o} or @samp{m}, constant operands are not a problem.
1426 If the constraint permits a constant and a pseudo register used in an insn
1427 was not allocated to a hard register and is equivalent to a constant,
1428 the register will be replaced with the constant. If the predicate does
1429 not permit a constant and the insn is re-recognized for some reason, the
1430 compiler will crash. Thus the predicate must always recognize any
1431 objects allowed by the constraint.
1434 If the operand's predicate can recognize registers, but the constraint does
1435 not permit them, it can make the compiler crash. When this operand happens
1436 to be a register, the reload pass will be stymied, because it does not know
1437 how to copy a register temporarily into memory.
1439 If the predicate accepts a unary operator, the constraint applies to the
1440 operand. For example, the MIPS processor at ISA level 3 supports an
1441 instruction which adds two registers in @code{SImode} to produce a
1442 @code{DImode} result, but only if the registers are correctly sign
1443 extended. This predicate for the input operands accepts a
1444 @code{sign_extend} of an @code{SImode} register. Write the constraint
1445 to indicate the type of register that is required for the operand of the
1449 @node Multi-Alternative
1450 @subsection Multiple Alternative Constraints
1451 @cindex multiple alternative constraints
1453 Sometimes a single instruction has multiple alternative sets of possible
1454 operands. For example, on the 68000, a logical-or instruction can combine
1455 register or an immediate value into memory, or it can combine any kind of
1456 operand into a register; but it cannot combine one memory location into
1459 These constraints are represented as multiple alternatives. An alternative
1460 can be described by a series of letters for each operand. The overall
1461 constraint for an operand is made from the letters for this operand
1462 from the first alternative, a comma, the letters for this operand from
1463 the second alternative, a comma, and so on until the last alternative.
1465 Here is how it is done for fullword logical-or on the 68000:
1468 (define_insn "iorsi3"
1469 [(set (match_operand:SI 0 "general_operand" "=m,d")
1470 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1471 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1475 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1476 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1477 2. The second alternative has @samp{d} (data register) for operand 0,
1478 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1479 @samp{%} in the constraints apply to all the alternatives; their
1480 meaning is explained in the next section (@pxref{Class Preferences}).
1483 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1484 If all the operands fit any one alternative, the instruction is valid.
1485 Otherwise, for each alternative, the compiler counts how many instructions
1486 must be added to copy the operands so that that alternative applies.
1487 The alternative requiring the least copying is chosen. If two alternatives
1488 need the same amount of copying, the one that comes first is chosen.
1489 These choices can be altered with the @samp{?} and @samp{!} characters:
1492 @cindex @samp{?} in constraint
1493 @cindex question mark
1495 Disparage slightly the alternative that the @samp{?} appears in,
1496 as a choice when no alternative applies exactly. The compiler regards
1497 this alternative as one unit more costly for each @samp{?} that appears
1500 @cindex @samp{!} in constraint
1501 @cindex exclamation point
1503 Disparage severely the alternative that the @samp{!} appears in.
1504 This alternative can still be used if it fits without reloading,
1505 but if reloading is needed, some other alternative will be used.
1509 When an insn pattern has multiple alternatives in its constraints, often
1510 the appearance of the assembler code is determined mostly by which
1511 alternative was matched. When this is so, the C code for writing the
1512 assembler code can use the variable @code{which_alternative}, which is
1513 the ordinal number of the alternative that was actually satisfied (0 for
1514 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1518 @node Class Preferences
1519 @subsection Register Class Preferences
1520 @cindex class preference constraints
1521 @cindex register class preference constraints
1523 @cindex voting between constraint alternatives
1524 The operand constraints have another function: they enable the compiler
1525 to decide which kind of hardware register a pseudo register is best
1526 allocated to. The compiler examines the constraints that apply to the
1527 insns that use the pseudo register, looking for the machine-dependent
1528 letters such as @samp{d} and @samp{a} that specify classes of registers.
1529 The pseudo register is put in whichever class gets the most ``votes''.
1530 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1531 favor of a general register. The machine description says which registers
1532 are considered general.
1534 Of course, on some machines all registers are equivalent, and no register
1535 classes are defined. Then none of this complexity is relevant.
1539 @subsection Constraint Modifier Characters
1540 @cindex modifiers in constraints
1541 @cindex constraint modifier characters
1543 @c prevent bad page break with this line
1544 Here are constraint modifier characters.
1547 @cindex @samp{=} in constraint
1549 Means that this operand is write-only for this instruction: the previous
1550 value is discarded and replaced by output data.
1552 @cindex @samp{+} in constraint
1554 Means that this operand is both read and written by the instruction.
1556 When the compiler fixes up the operands to satisfy the constraints,
1557 it needs to know which operands are inputs to the instruction and
1558 which are outputs from it. @samp{=} identifies an output; @samp{+}
1559 identifies an operand that is both input and output; all other operands
1560 are assumed to be input only.
1562 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1563 first character of the constraint string.
1565 @cindex @samp{&} in constraint
1566 @cindex earlyclobber operand
1568 Means (in a particular alternative) that this operand is an
1569 @dfn{earlyclobber} operand, which is modified before the instruction is
1570 finished using the input operands. Therefore, this operand may not lie
1571 in a register that is used as an input operand or as part of any memory
1574 @samp{&} applies only to the alternative in which it is written. In
1575 constraints with multiple alternatives, sometimes one alternative
1576 requires @samp{&} while others do not. See, for example, the
1577 @samp{movdf} insn of the 68000.
1579 An input operand can be tied to an earlyclobber operand if its only
1580 use as an input occurs before the early result is written. Adding
1581 alternatives of this form often allows GCC to produce better code
1582 when only some of the inputs can be affected by the earlyclobber.
1583 See, for example, the @samp{mulsi3} insn of the ARM@.
1585 @samp{&} does not obviate the need to write @samp{=}.
1587 @cindex @samp{%} in constraint
1589 Declares the instruction to be commutative for this operand and the
1590 following operand. This means that the compiler may interchange the
1591 two operands if that is the cheapest way to make all operands fit the
1594 This is often used in patterns for addition instructions
1595 that really have only two operands: the result must go in one of the
1596 arguments. Here for example, is how the 68000 halfword-add
1597 instruction is defined:
1600 (define_insn "addhi3"
1601 [(set (match_operand:HI 0 "general_operand" "=m,r")
1602 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1603 (match_operand:HI 2 "general_operand" "di,g")))]
1607 GCC can only handle one commutative pair in an asm; if you use more,
1608 the compiler may fail. Note that you need not use the modifier if
1609 the two alternatives are strictly identical; this would only waste
1610 time in the reload pass. The modifier is not operational after
1611 register allocation, so the result of @code{define_peephole2}
1612 and @code{define_split}s performed after reload cannot rely on
1613 @samp{%} to make the intended insn match.
1615 @cindex @samp{#} in constraint
1617 Says that all following characters, up to the next comma, are to be
1618 ignored as a constraint. They are significant only for choosing
1619 register preferences.
1621 @cindex @samp{*} in constraint
1623 Says that the following character should be ignored when choosing
1624 register preferences. @samp{*} has no effect on the meaning of the
1625 constraint as a constraint, and no effect on reloading. For LRA
1626 @samp{*} additionally disparages slightly the alternative if the
1627 following character matches the operand.
1630 Here is an example: the 68000 has an instruction to sign-extend a
1631 halfword in a data register, and can also sign-extend a value by
1632 copying it into an address register. While either kind of register is
1633 acceptable, the constraints on an address-register destination are
1634 less strict, so it is best if register allocation makes an address
1635 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1636 constraint letter (for data register) is ignored when computing
1637 register preferences.
1640 (define_insn "extendhisi2"
1641 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1643 (match_operand:HI 1 "general_operand" "0,g")))]
1649 @node Machine Constraints
1650 @subsection Constraints for Particular Machines
1651 @cindex machine specific constraints
1652 @cindex constraints, machine specific
1654 Whenever possible, you should use the general-purpose constraint letters
1655 in @code{asm} arguments, since they will convey meaning more readily to
1656 people reading your code. Failing that, use the constraint letters
1657 that usually have very similar meanings across architectures. The most
1658 commonly used constraints are @samp{m} and @samp{r} (for memory and
1659 general-purpose registers respectively; @pxref{Simple Constraints}), and
1660 @samp{I}, usually the letter indicating the most common
1661 immediate-constant format.
1663 Each architecture defines additional constraints. These constraints
1664 are used by the compiler itself for instruction generation, as well as
1665 for @code{asm} statements; therefore, some of the constraints are not
1666 particularly useful for @code{asm}. Here is a summary of some of the
1667 machine-dependent constraints available on some particular machines;
1668 it includes both constraints that are useful for @code{asm} and
1669 constraints that aren't. The compiler source file mentioned in the
1670 table heading for each architecture is the definitive reference for
1671 the meanings of that architecture's constraints.
1674 @item AArch64 family---@file{config/aarch64/constraints.md}
1677 The stack pointer register (@code{SP})
1680 Floating point or SIMD vector register
1683 Integer constant that is valid as an immediate operand in an @code{ADD}
1687 Integer constant that is valid as an immediate operand in a @code{SUB}
1688 instruction (once negated)
1691 Integer constant that can be used with a 32-bit logical instruction
1694 Integer constant that can be used with a 64-bit logical instruction
1697 Integer constant that is valid as an immediate operand in a 32-bit @code{MOV}
1698 pseudo instruction. The @code{MOV} may be assembled to one of several different
1699 machine instructions depending on the value
1702 Integer constant that is valid as an immediate operand in a 64-bit @code{MOV}
1706 An absolute symbolic address or a label reference
1709 Floating point constant zero
1712 Integer constant zero
1715 The high part (bits 12 and upwards) of the pc-relative address of a symbol
1716 within 4GB of the instruction
1719 A memory address which uses a single base register with no offset
1722 A memory address suitable for a load/store pair instruction in SI, DI, SF and
1728 @item ARC ---@file{config/arc/constraints.md}
1731 Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
1732 @code{r12}-@code{r15}. This constraint can only match when the @option{-mq}
1733 option is in effect.
1736 Registers usable as base-regs of memory addresses in ARCompact 16-bit memory
1737 instructions: @code{r0}-@code{r3}, @code{r12}-@code{r15}, @code{sp}.
1738 This constraint can only match when the @option{-mq}
1739 option is in effect.
1741 ARC FPX (dpfp) 64-bit registers. @code{D0}, @code{D1}.
1744 A signed 12-bit integer constant.
1747 constant for arithmetic/logical operations. This might be any constant
1748 that can be put into a long immediate by the assmbler or linker without
1749 involving a PIC relocation.
1752 A 3-bit unsigned integer constant.
1755 A 6-bit unsigned integer constant.
1758 One's complement of a 6-bit unsigned integer constant.
1761 Two's complement of a 6-bit unsigned integer constant.
1764 A 5-bit unsigned integer constant.
1767 A 7-bit unsigned integer constant.
1770 A 8-bit unsigned integer constant.
1773 Any const_double value.
1776 @item ARM family---@file{config/arm/constraints.md}
1779 VFP floating-point register
1782 The floating-point constant 0.0
1785 Integer that is valid as an immediate operand in a data processing
1786 instruction. That is, an integer in the range 0 to 255 rotated by a
1790 Integer in the range @minus{}4095 to 4095
1793 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1796 Integer that satisfies constraint @samp{I} when negated (twos complement)
1799 Integer in the range 0 to 32
1802 A memory reference where the exact address is in a single register
1803 (`@samp{m}' is preferable for @code{asm} statements)
1806 An item in the constant pool
1809 A symbol in the text segment of the current file
1812 A memory reference suitable for VFP load/store insns (reg+constant offset)
1815 A memory reference suitable for iWMMXt load/store instructions.
1818 A memory reference suitable for the ARMv4 ldrsb instruction.
1821 @item AVR family---@file{config/avr/constraints.md}
1824 Registers from r0 to r15
1827 Registers from r16 to r23
1830 Registers from r16 to r31
1833 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1836 Pointer register (r26--r31)
1839 Base pointer register (r28--r31)
1842 Stack pointer register (SPH:SPL)
1845 Temporary register r0
1848 Register pair X (r27:r26)
1851 Register pair Y (r29:r28)
1854 Register pair Z (r31:r30)
1857 Constant greater than @minus{}1, less than 64
1860 Constant greater than @minus{}64, less than 1
1869 Constant that fits in 8 bits
1872 Constant integer @minus{}1
1875 Constant integer 8, 16, or 24
1881 A floating point constant 0.0
1884 A memory address based on Y or Z pointer with displacement.
1887 @item Epiphany---@file{config/epiphany/constraints.md}
1890 An unsigned 16-bit constant.
1893 An unsigned 5-bit constant.
1896 A signed 11-bit constant.
1899 A signed 11-bit constant added to @minus{}1.
1900 Can only match when the @option{-m1reg-@var{reg}} option is active.
1903 Left-shift of @minus{}1, i.e., a bit mask with a block of leading ones, the rest
1904 being a block of trailing zeroes.
1905 Can only match when the @option{-m1reg-@var{reg}} option is active.
1908 Right-shift of @minus{}1, i.e., a bit mask with a trailing block of ones, the
1909 rest being zeroes. Or to put it another way, one less than a power of two.
1910 Can only match when the @option{-m1reg-@var{reg}} option is active.
1913 Constant for arithmetic/logical operations.
1914 This is like @code{i}, except that for position independent code,
1915 no symbols / expressions needing relocations are allowed.
1918 Symbolic constant for call/jump instruction.
1921 The register class usable in short insns. This is a register class
1922 constraint, and can thus drive register allocation.
1923 This constraint won't match unless @option{-mprefer-short-insn-regs} is
1927 The the register class of registers that can be used to hold a
1928 sibcall call address. I.e., a caller-saved register.
1931 Core control register class.
1934 The register group usable in short insns.
1935 This constraint does not use a register class, so that it only
1936 passively matches suitable registers, and doesn't drive register allocation.
1940 Constant suitable for the addsi3_r pattern. This is a valid offset
1941 For byte, halfword, or word addressing.
1945 Matches the return address if it can be replaced with the link register.
1948 Matches the integer condition code register.
1951 Matches the return address if it is in a stack slot.
1954 Matches control register values to switch fp mode, which are encapsulated in
1955 @code{UNSPEC_FP_MODE}.
1958 @item CR16 Architecture---@file{config/cr16/cr16.h}
1962 Registers from r0 to r14 (registers without stack pointer)
1965 Register from r0 to r11 (all 16-bit registers)
1968 Register from r12 to r15 (all 32-bit registers)
1971 Signed constant that fits in 4 bits
1974 Signed constant that fits in 5 bits
1977 Signed constant that fits in 6 bits
1980 Unsigned constant that fits in 4 bits
1983 Signed constant that fits in 32 bits
1986 Check for 64 bits wide constants for add/sub instructions
1989 Floating point constant that is legal for store immediate
1992 @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
1998 Floating point register
2001 Shift amount register
2004 Floating point register (deprecated)
2007 Upper floating point register (32-bit), floating point register (64-bit)
2013 Signed 11-bit integer constant
2016 Signed 14-bit integer constant
2019 Integer constant that can be deposited with a @code{zdepi} instruction
2022 Signed 5-bit integer constant
2028 Integer constant that can be loaded with a @code{ldil} instruction
2031 Integer constant whose value plus one is a power of 2
2034 Integer constant that can be used for @code{and} operations in @code{depi}
2035 and @code{extru} instructions
2044 Floating-point constant 0.0
2047 A @code{lo_sum} data-linkage-table memory operand
2050 A memory operand that can be used as the destination operand of an
2051 integer store instruction
2054 A scaled or unscaled indexed memory operand
2057 A memory operand for floating-point loads and stores
2060 A register indirect memory operand
2063 @item picoChip family---@file{picochip.h}
2069 Pointer register. A register which can be used to access memory without
2070 supplying an offset. Any other register can be used to access memory,
2071 but will need a constant offset. In the case of the offset being zero,
2072 it is more efficient to use a pointer register, since this reduces code
2076 A twin register. A register which may be paired with an adjacent
2077 register to create a 32-bit register.
2080 Any absolute memory address (e.g., symbolic constant, symbolic
2084 4-bit signed integer.
2087 4-bit unsigned integer.
2090 8-bit signed integer.
2093 Any constant whose absolute value is no greater than 4-bits.
2096 10-bit signed integer
2099 16-bit signed integer.
2103 @item PowerPC and IBM RS6000---@file{config/rs6000/constraints.md}
2106 Address base register
2109 Floating point register (containing 64-bit value)
2112 Floating point register (containing 32-bit value)
2115 Altivec vector register
2118 Any VSX register if the -mvsx option was used or NO_REGS.
2121 VSX vector register to hold vector double data or NO_REGS.
2124 VSX vector register to hold vector float data or NO_REGS.
2127 If @option{-mmfpgpr} was used, a floating point register or NO_REGS.
2130 Floating point register if the LFIWAX instruction is enabled or NO_REGS.
2133 VSX register if direct move instructions are enabled, or NO_REGS.
2136 No register (NO_REGS).
2139 General purpose register if 64-bit instructions are enabled or NO_REGS.
2142 VSX vector register to hold scalar double values or NO_REGS.
2145 VSX vector register to hold 128 bit integer or NO_REGS.
2148 Altivec register to use for float/32-bit int loads/stores or NO_REGS.
2151 Altivec register to use for double loads/stores or NO_REGS.
2154 FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS.
2157 Floating point register if the STFIWX instruction is enabled or NO_REGS.
2160 VSX vector register to hold scalar float values or NO_REGS.
2163 Floating point register if the LFIWZX instruction is enabled or NO_REGS.
2166 A memory address that will work with the @code{lq} and @code{stq}
2170 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
2179 @samp{LINK} register
2182 @samp{CR} register (condition register) number 0
2185 @samp{CR} register (condition register)
2188 @samp{XER[CA]} carry bit (part of the XER register)
2191 Signed 16-bit constant
2194 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
2195 @code{SImode} constants)
2198 Unsigned 16-bit constant
2201 Signed 16-bit constant shifted left 16 bits
2204 Constant larger than 31
2213 Constant whose negation is a signed 16-bit constant
2216 Floating point constant that can be loaded into a register with one
2217 instruction per word
2220 Integer/Floating point constant that can be loaded into a register using
2225 Normally, @code{m} does not allow addresses that update the base register.
2226 If @samp{<} or @samp{>} constraint is also used, they are allowed and
2227 therefore on PowerPC targets in that case it is only safe
2228 to use @samp{m<>} in an @code{asm} statement if that @code{asm} statement
2229 accesses the operand exactly once. The @code{asm} statement must also
2230 use @samp{%U@var{<opno>}} as a placeholder for the ``update'' flag in the
2231 corresponding load or store instruction. For example:
2234 asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val));
2240 asm ("st %1,%0" : "=m<>" (mem) : "r" (val));
2246 A ``stable'' memory operand; that is, one which does not include any
2247 automodification of the base register. This used to be useful when
2248 @samp{m} allowed automodification of the base register, but as those are now only
2249 allowed when @samp{<} or @samp{>} is used, @samp{es} is basically the same
2250 as @samp{m} without @samp{<} and @samp{>}.
2253 Memory operand that is an offset from a register (it is usually better
2254 to use @samp{m} or @samp{es} in @code{asm} statements)
2257 Memory operand that is an indexed or indirect from a register (it is
2258 usually better to use @samp{m} or @samp{es} in @code{asm} statements)
2264 Address operand that is an indexed or indirect from a register (@samp{p} is
2265 preferable for @code{asm} statements)
2268 Constant suitable as a 64-bit mask operand
2271 Constant suitable as a 32-bit mask operand
2274 System V Release 4 small data area reference
2277 AND masks that can be performed by two rldic@{l, r@} instructions
2280 Vector constant that does not require memory
2283 Vector constant that is all zeros.
2287 @item Intel 386---@file{config/i386/constraints.md}
2290 Legacy register---the eight integer registers available on all
2291 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
2292 @code{si}, @code{di}, @code{bp}, @code{sp}).
2295 Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
2296 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
2299 Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
2300 @code{c}, and @code{d}.
2304 Any register that can be used as the index in a base+index memory
2305 access: that is, any general register except the stack pointer.
2309 The @code{a} register.
2312 The @code{b} register.
2315 The @code{c} register.
2318 The @code{d} register.
2321 The @code{si} register.
2324 The @code{di} register.
2327 The @code{a} and @code{d} registers. This class is used for instructions
2328 that return double word results in the @code{ax:dx} register pair. Single
2329 word values will be allocated either in @code{ax} or @code{dx}.
2330 For example on i386 the following implements @code{rdtsc}:
2333 unsigned long long rdtsc (void)
2335 unsigned long long tick;
2336 __asm__ __volatile__("rdtsc":"=A"(tick));
2341 This is not correct on x86_64 as it would allocate tick in either @code{ax}
2342 or @code{dx}. You have to use the following variant instead:
2345 unsigned long long rdtsc (void)
2347 unsigned int tickl, tickh;
2348 __asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh));
2349 return ((unsigned long long)tickh << 32)|tickl;
2355 Any 80387 floating-point (stack) register.
2358 Top of 80387 floating-point stack (@code{%st(0)}).
2361 Second from top of 80387 floating-point stack (@code{%st(1)}).
2370 First SSE register (@code{%xmm0}).
2374 Any SSE register, when SSE2 is enabled.
2377 Any SSE register, when SSE2 and inter-unit moves are enabled.
2380 Any MMX register, when inter-unit moves are enabled.
2384 Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
2387 Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
2390 Signed 8-bit integer constant.
2393 @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
2396 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
2399 Unsigned 8-bit integer constant (for @code{in} and @code{out}
2404 Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
2408 Standard 80387 floating point constant.
2411 Standard SSE floating point constant.
2414 32-bit signed integer constant, or a symbolic reference known
2415 to fit that range (for immediate operands in sign-extending x86-64
2419 32-bit unsigned integer constant, or a symbolic reference known
2420 to fit that range (for immediate operands in zero-extending x86-64
2425 @item Intel IA-64---@file{config/ia64/ia64.h}
2428 General register @code{r0} to @code{r3} for @code{addl} instruction
2434 Predicate register (@samp{c} as in ``conditional'')
2437 Application register residing in M-unit
2440 Application register residing in I-unit
2443 Floating-point register
2446 Memory operand. If used together with @samp{<} or @samp{>},
2447 the operand can have postincrement and postdecrement which
2448 require printing with @samp{%Pn} on IA-64.
2451 Floating-point constant 0.0 or 1.0
2454 14-bit signed integer constant
2457 22-bit signed integer constant
2460 8-bit signed integer constant for logical instructions
2463 8-bit adjusted signed integer constant for compare pseudo-ops
2466 6-bit unsigned integer constant for shift counts
2469 9-bit signed integer constant for load and store postincrements
2475 0 or @minus{}1 for @code{dep} instruction
2478 Non-volatile memory for floating-point loads and stores
2481 Integer constant in the range 1 to 4 for @code{shladd} instruction
2484 Memory operand except postincrement and postdecrement. This is
2485 now roughly the same as @samp{m} when not used together with @samp{<}
2489 @item FRV---@file{config/frv/frv.h}
2492 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2495 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2498 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
2499 @code{icc0} to @code{icc3}).
2502 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2505 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2506 Odd registers are excluded not in the class but through the use of a machine
2507 mode larger than 4 bytes.
2510 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2513 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2514 Odd registers are excluded not in the class but through the use of a machine
2515 mode larger than 4 bytes.
2518 Register in the class @code{LR_REG} (the @code{lr} register).
2521 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2522 Register numbers not divisible by 4 are excluded not in the class but through
2523 the use of a machine mode larger than 8 bytes.
2526 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2529 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2532 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2535 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2538 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2539 Register numbers not divisible by 4 are excluded not in the class but through
2540 the use of a machine mode larger than 8 bytes.
2543 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2546 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2549 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2552 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2555 Floating point constant zero
2558 6-bit signed integer constant
2561 10-bit signed integer constant
2564 16-bit signed integer constant
2567 16-bit unsigned integer constant
2570 12-bit signed integer constant that is negative---i.e.@: in the
2571 range of @minus{}2048 to @minus{}1
2577 12-bit signed integer constant that is greater than zero---i.e.@: in the
2582 @item Blackfin family---@file{config/bfin/constraints.md}
2591 A call clobbered P register.
2594 A single register. If @var{n} is in the range 0 to 7, the corresponding D
2595 register. If it is @code{A}, then the register P0.
2598 Even-numbered D register
2601 Odd-numbered D register
2604 Accumulator register.
2607 Even-numbered accumulator register.
2610 Odd-numbered accumulator register.
2622 Registers used for circular buffering, i.e. I, B, or L registers.
2637 Any D, P, B, M, I or L register.
2640 Additional registers typically used only in prologues and epilogues: RETS,
2641 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
2644 Any register except accumulators or CC.
2647 Signed 16 bit integer (in the range @minus{}32768 to 32767)
2650 Unsigned 16 bit integer (in the range 0 to 65535)
2653 Signed 7 bit integer (in the range @minus{}64 to 63)
2656 Unsigned 7 bit integer (in the range 0 to 127)
2659 Unsigned 5 bit integer (in the range 0 to 31)
2662 Signed 4 bit integer (in the range @minus{}8 to 7)
2665 Signed 3 bit integer (in the range @minus{}3 to 4)
2668 Unsigned 3 bit integer (in the range 0 to 7)
2671 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2674 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2675 use with either accumulator.
2678 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2679 use only with accumulator A1.
2688 An integer constant with exactly a single bit set.
2691 An integer constant with all bits set except exactly one.
2699 @item M32C---@file{config/m32c/m32c.c}
2704 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2707 Any control register, when they're 16 bits wide (nothing if control
2708 registers are 24 bits wide)
2711 Any control register, when they're 24 bits wide.
2720 $r0 or $r2, or $r2r0 for 32 bit values.
2723 $r1 or $r3, or $r3r1 for 32 bit values.
2726 A register that can hold a 64 bit value.
2729 $r0 or $r1 (registers with addressable high/low bytes)
2738 Address registers when they're 16 bits wide.
2741 Address registers when they're 24 bits wide.
2744 Registers that can hold QI values.
2747 Registers that can be used with displacements ($a0, $a1, $sb).
2750 Registers that can hold 32 bit values.
2753 Registers that can hold 16 bit values.
2756 Registers chat can hold 16 bit values, including all control
2760 $r0 through R1, plus $a0 and $a1.
2766 The memory-based pseudo-registers $mem0 through $mem15.
2769 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2770 bit registers for m32cm, m32c).
2773 Matches multiple registers in a PARALLEL to form a larger register.
2774 Used to match function return values.
2780 @minus{}128 @dots{} 127
2783 @minus{}32768 @dots{} 32767
2789 @minus{}8 @dots{} @minus{}1 or 1 @dots{} 8
2792 @minus{}16 @dots{} @minus{}1 or 1 @dots{} 16
2795 @minus{}32 @dots{} @minus{}1 or 1 @dots{} 32
2798 @minus{}65536 @dots{} @minus{}1
2801 An 8 bit value with exactly one bit set.
2804 A 16 bit value with exactly one bit set.
2807 The common src/dest memory addressing modes.
2810 Memory addressed using $a0 or $a1.
2813 Memory addressed with immediate addresses.
2816 Memory addressed using the stack pointer ($sp).
2819 Memory addressed using the frame base register ($fb).
2822 Memory addressed using the small base register ($sb).
2828 @item MeP---@file{config/mep/constraints.md}
2838 Any control register.
2841 Either the $hi or the $lo register.
2844 Coprocessor registers that can be directly loaded ($c0-$c15).
2847 Coprocessor registers that can be moved to each other.
2850 Coprocessor registers that can be moved to core registers.
2862 Registers which can be used in $tp-relative addressing.
2868 The coprocessor registers.
2871 The coprocessor control registers.
2877 User-defined register set A.
2880 User-defined register set B.
2883 User-defined register set C.
2886 User-defined register set D.
2889 Offsets for $gp-rel addressing.
2892 Constants that can be used directly with boolean insns.
2895 Constants that can be moved directly to registers.
2898 Small constants that can be added to registers.
2904 Small constants that can be compared to registers.
2907 Constants that can be loaded into the top half of registers.
2910 Signed 8-bit immediates.
2913 Symbols encoded for $tp-rel or $gp-rel addressing.
2916 Non-constant addresses for loading/saving coprocessor registers.
2919 The top half of a symbol's value.
2922 A register indirect address without offset.
2925 Symbolic references to the control bus.
2929 @item MicroBlaze---@file{config/microblaze/constraints.md}
2932 A general register (@code{r0} to @code{r31}).
2935 A status register (@code{rmsr}, @code{$fcc1} to @code{$fcc7}).
2939 @item MIPS---@file{config/mips/constraints.md}
2942 An address register. This is equivalent to @code{r} unless
2943 generating MIPS16 code.
2946 A floating-point register (if available).
2949 Formerly the @code{hi} register. This constraint is no longer supported.
2952 The @code{lo} register. Use this register to store values that are
2953 no bigger than a word.
2956 The concatenated @code{hi} and @code{lo} registers. Use this register
2957 to store doubleword values.
2960 A register suitable for use in an indirect jump. This will always be
2961 @code{$25} for @option{-mabicalls}.
2964 Register @code{$3}. Do not use this constraint in new code;
2965 it is retained only for compatibility with glibc.
2968 Equivalent to @code{r}; retained for backwards compatibility.
2971 A floating-point condition code register.
2974 A signed 16-bit constant (for arithmetic instructions).
2980 An unsigned 16-bit constant (for logic instructions).
2983 A signed 32-bit constant in which the lower 16 bits are zero.
2984 Such constants can be loaded using @code{lui}.
2987 A constant that cannot be loaded using @code{lui}, @code{addiu}
2991 A constant in the range @minus{}65535 to @minus{}1 (inclusive).
2994 A signed 15-bit constant.
2997 A constant in the range 1 to 65535 (inclusive).
3000 Floating-point zero.
3003 An address that can be used in a non-macro load or store.
3006 When compiling microMIPS code, this constraint matches a memory operand
3007 whose address is formed from a base register and a 12-bit offset. These
3008 operands can be used for microMIPS instructions such as @code{ll} and
3009 @code{sc}. When not compiling for microMIPS code, @code{ZC} is
3010 equivalent to @code{R}.
3013 When compiling microMIPS code, this constraint matches an address operand
3014 that is formed from a base register and a 12-bit offset. These operands
3015 can be used for microMIPS instructions such as @code{prefetch}. When
3016 not compiling for microMIPS code, @code{ZD} is equivalent to @code{p}.
3019 @item Motorola 680x0---@file{config/m68k/constraints.md}
3028 68881 floating-point register, if available
3031 Integer in the range 1 to 8
3034 16-bit signed number
3037 Signed number whose magnitude is greater than 0x80
3040 Integer in the range @minus{}8 to @minus{}1
3043 Signed number whose magnitude is greater than 0x100
3046 Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
3049 16 (for rotate using swap)
3052 Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
3055 Numbers that mov3q can handle
3058 Floating point constant that is not a 68881 constant
3061 Operands that satisfy 'm' when -mpcrel is in effect
3064 Operands that satisfy 's' when -mpcrel is not in effect
3067 Address register indirect addressing mode
3070 Register offset addressing
3085 Range of signed numbers that don't fit in 16 bits
3088 Integers valid for mvq
3091 Integers valid for a moveq followed by a swap
3094 Integers valid for mvz
3097 Integers valid for mvs
3103 Non-register operands allowed in clr
3107 @item Moxie---@file{config/moxie/constraints.md}
3116 A register indirect memory operand
3119 A constant in the range of 0 to 255.
3122 A constant in the range of 0 to @minus{}255.
3126 @item MSP430--@file{config/msp430/constraints.md}
3139 Integer constant -1^20..1^19.
3142 Integer constant 1-4.
3145 Memory references which do not require an extended MOVX instruction.
3148 Memory reference, labels only.
3151 Memory reference, stack only.
3155 @item PDP-11---@file{config/pdp11/constraints.md}
3158 Floating point registers AC0 through AC3. These can be loaded from/to
3159 memory with a single instruction.
3162 Odd numbered general registers (R1, R3, R5). These are used for
3163 16-bit multiply operations.
3166 Any of the floating point registers (AC0 through AC5).
3169 Floating point constant 0.
3172 An integer constant that fits in 16 bits.
3175 An integer constant whose low order 16 bits are zero.
3178 An integer constant that does not meet the constraints for codes
3179 @samp{I} or @samp{J}.
3182 The integer constant 1.
3185 The integer constant @minus{}1.
3188 The integer constant 0.
3191 Integer constants @minus{}4 through @minus{}1 and 1 through 4; shifts by these
3192 amounts are handled as multiple single-bit shifts rather than a single
3193 variable-length shift.
3196 A memory reference which requires an additional word (address or
3197 offset) after the opcode.
3200 A memory reference that is encoded within the opcode.
3204 @item RL78---@file{config/rl78/constraints.md}
3208 An integer constant in the range 1 @dots{} 7.
3210 An integer constant in the range 0 @dots{} 255.
3212 An integer constant in the range @minus{}255 @dots{} 0
3214 The integer constant 1.
3216 The integer constant -1.
3218 The integer constant 0.
3220 The integer constant 2.
3222 The integer constant -2.
3224 An integer constant in the range 1 @dots{} 15.
3226 The built-in compare types--eq, ne, gtu, ltu, geu, and leu.
3228 The synthetic compare types--gt, lt, ge, and le.
3230 A memory reference with an absolute address.
3232 A memory reference using @code{BC} as a base register, with an optional offset.
3234 A memory reference using @code{AX}, @code{BC}, @code{DE}, or @code{HL} for the address, for calls.
3236 A memory reference using any 16-bit register pair for the address, for calls.
3238 A memory reference using @code{DE} as a base register, with an optional offset.
3240 A memory reference using @code{DE} as a base register, without any offset.
3242 Any memory reference to an address in the far address space.
3244 A memory reference using @code{HL} as a base register, with an optional one-byte offset.
3246 A memory reference using @code{HL} as a base register, with @code{B} or @code{C} as the index register.
3248 A memory reference using @code{HL} as a base register, without any offset.
3250 A memory reference using @code{SP} as a base register, with an optional one-byte offset.
3252 Any memory reference to an address in the near address space.
3254 The @code{AX} register.
3256 The @code{BC} register.
3258 The @code{DE} register.
3260 @code{A} through @code{L} registers.
3262 The @code{SP} register.
3264 The @code{HL} register.
3266 The 16-bit @code{R8} register.
3268 The 16-bit @code{R10} register.
3270 The registers reserved for interrupts (@code{R24} to @code{R31}).
3272 The @code{A} register.
3274 The @code{B} register.
3276 The @code{C} register.
3278 The @code{D} register.
3280 The @code{E} register.
3282 The @code{H} register.
3284 The @code{L} register.
3286 The virtual registers.
3288 The @code{PSW} register.
3290 The @code{X} register.
3294 @item RX---@file{config/rx/constraints.md}
3297 An address which does not involve register indirect addressing or
3298 pre/post increment/decrement addressing.
3304 A constant in the range @minus{}256 to 255, inclusive.
3307 A constant in the range @minus{}128 to 127, inclusive.
3310 A constant in the range @minus{}32768 to 32767, inclusive.
3313 A constant in the range @minus{}8388608 to 8388607, inclusive.
3316 A constant in the range 0 to 15, inclusive.
3321 @item SPARC---@file{config/sparc/sparc.h}
3324 Floating-point register on the SPARC-V8 architecture and
3325 lower floating-point register on the SPARC-V9 architecture.
3328 Floating-point register. It is equivalent to @samp{f} on the
3329 SPARC-V8 architecture and contains both lower and upper
3330 floating-point registers on the SPARC-V9 architecture.
3333 Floating-point condition code register.
3336 Lower floating-point register. It is only valid on the SPARC-V9
3337 architecture when the Visual Instruction Set is available.
3340 Floating-point register. It is only valid on the SPARC-V9 architecture
3341 when the Visual Instruction Set is available.
3344 64-bit global or out register for the SPARC-V8+ architecture.
3347 The constant all-ones, for floating-point.
3350 Signed 5-bit constant
3356 Signed 13-bit constant
3362 32-bit constant with the low 12 bits clear (a constant that can be
3363 loaded with the @code{sethi} instruction)
3366 A constant in the range supported by @code{movcc} instructions (11-bit
3370 A constant in the range supported by @code{movrcc} instructions (10-bit
3374 Same as @samp{K}, except that it verifies that bits that are not in the
3375 lower 32-bit range are all zero. Must be used instead of @samp{K} for
3376 modes wider than @code{SImode}
3385 Signed 13-bit constant, sign-extended to 32 or 64 bits
3391 Floating-point constant whose integral representation can
3392 be moved into an integer register using a single sethi
3396 Floating-point constant whose integral representation can
3397 be moved into an integer register using a single mov
3401 Floating-point constant whose integral representation can
3402 be moved into an integer register using a high/lo_sum
3403 instruction sequence
3406 Memory address aligned to an 8-byte boundary
3412 Memory address for @samp{e} constraint registers
3415 Memory address with only a base register
3422 @item SPU---@file{config/spu/spu.h}
3425 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
3428 An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
3431 An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
3434 An immediate which can be loaded with @code{fsmbi}.
3437 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
3440 An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
3443 An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
3446 An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
3449 A constant in the range [@minus{}64, 63] for shift/rotate instructions.
3452 An unsigned 7-bit constant for conversion/nop/channel instructions.
3455 A signed 10-bit constant for most arithmetic instructions.
3458 A signed 16 bit immediate for @code{stop}.
3461 An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
3464 An unsigned 7-bit constant whose 3 least significant bits are 0.
3467 An unsigned 3-bit constant for 16-byte rotates and shifts
3470 Call operand, reg, for indirect calls
3473 Call operand, symbol, for relative calls.
3476 Call operand, const_int, for absolute calls.
3479 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
3482 An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
3485 An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
3488 An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
3492 @item S/390 and zSeries---@file{config/s390/s390.h}
3495 Address register (general purpose register except r0)
3498 Condition code register
3501 Data register (arbitrary general purpose register)
3504 Floating-point register
3507 Unsigned 8-bit constant (0--255)
3510 Unsigned 12-bit constant (0--4095)
3513 Signed 16-bit constant (@minus{}32768--32767)
3516 Value appropriate as displacement.
3519 for short displacement
3520 @item (@minus{}524288..524287)
3521 for long displacement
3525 Constant integer with a value of 0x7fffffff.
3528 Multiple letter constraint followed by 4 parameter letters.
3531 number of the part counting from most to least significant
3535 mode of the containing operand
3537 value of the other parts (F---all bits set)
3539 The constraint matches if the specified part of a constant
3540 has a value different from its other parts.
3543 Memory reference without index register and with short displacement.
3546 Memory reference with index register and short displacement.
3549 Memory reference without index register but with long displacement.
3552 Memory reference with index register and long displacement.
3555 Pointer with short displacement.
3558 Pointer with long displacement.
3561 Shift count operand.
3565 @item Score family---@file{config/score/score.h}
3568 Registers from r0 to r32.
3571 Registers from r0 to r16.
3574 r8---r11 or r22---r27 registers.
3595 cnt + lcb + scb register.
3598 cr0---cr15 register.
3610 cp1 + cp2 + cp3 registers.
3613 High 16-bit constant (32-bit constant with 16 LSBs zero).
3616 Unsigned 5 bit integer (in the range 0 to 31).
3619 Unsigned 16 bit integer (in the range 0 to 65535).
3622 Signed 16 bit integer (in the range @minus{}32768 to 32767).
3625 Unsigned 14 bit integer (in the range 0 to 16383).
3628 Signed 14 bit integer (in the range @minus{}8192 to 8191).
3634 @item Xstormy16---@file{config/stormy16/stormy16.h}
3649 Registers r0 through r7.
3652 Registers r0 and r1.
3658 Registers r8 and r9.
3661 A constant between 0 and 3 inclusive.
3664 A constant that has exactly one bit set.
3667 A constant that has exactly one bit clear.
3670 A constant between 0 and 255 inclusive.
3673 A constant between @minus{}255 and 0 inclusive.
3676 A constant between @minus{}3 and 0 inclusive.
3679 A constant between 1 and 4 inclusive.
3682 A constant between @minus{}4 and @minus{}1 inclusive.
3685 A memory reference that is a stack push.
3688 A memory reference that is a stack pop.
3691 A memory reference that refers to a constant address of known value.
3694 The register indicated by Rx (not implemented yet).
3697 A constant that is not between 2 and 15 inclusive.
3704 @item TI C6X family---@file{config/c6x/constraints.md}
3707 Register file A (A0--A31).
3710 Register file B (B0--B31).
3713 Predicate registers in register file A (A0--A2 on C64X and
3714 higher, A1 and A2 otherwise).
3717 Predicate registers in register file B (B0--B2).
3720 A call-used register in register file B (B0--B9, B16--B31).
3723 Register file A, excluding predicate registers (A3--A31,
3724 plus A0 if not C64X or higher).
3727 Register file B, excluding predicate registers (B3--B31).
3730 Integer constant in the range 0 @dots{} 15.
3733 Integer constant in the range 0 @dots{} 31.
3736 Integer constant in the range @minus{}31 @dots{} 0.
3739 Integer constant in the range @minus{}16 @dots{} 15.
3742 Integer constant that can be the operand of an ADDA or a SUBA insn.
3745 Integer constant in the range 0 @dots{} 65535.
3748 Integer constant in the range @minus{}32768 @dots{} 32767.
3751 Integer constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}.
3754 Integer constant that is a valid mask for the clr instruction.
3757 Integer constant that is a valid mask for the set instruction.
3760 Memory location with A base register.
3763 Memory location with B base register.
3767 On C64x+ targets, a GP-relative small data reference.
3770 Any kind of @code{SYMBOL_REF}, for use in a call address.
3773 Any kind of immediate operand, unless it matches the S0 constraint.
3776 Memory location with B base register, but not using a long offset.
3779 A memory operand with an address that can't be used in an unaligned access.
3783 Register B14 (aka DP).
3787 @item TILE-Gx---@file{config/tilegx/constraints.md}
3800 Each of these represents a register constraint for an individual
3801 register, from r0 to r10.
3804 Signed 8-bit integer constant.
3807 Signed 16-bit integer constant.
3810 Unsigned 16-bit integer constant.
3813 Integer constant that fits in one signed byte when incremented by one
3814 (@minus{}129 @dots{} 126).
3817 Memory operand. If used together with @samp{<} or @samp{>}, the
3818 operand can have postincrement which requires printing with @samp{%In}
3819 and @samp{%in} on TILE-Gx. For example:
3822 asm ("st_add %I0,%1,%i0" : "=m<>" (*mem) : "r" (val));
3826 A bit mask suitable for the BFINS instruction.
3829 Integer constant that is a byte tiled out eight times.
3832 The integer zero constant.
3835 Integer constant that is a sign-extended byte tiled out as four shorts.
3838 Integer constant that fits in one signed byte when incremented
3839 (@minus{}129 @dots{} 126), but excluding -1.
3842 Integer constant that has all 1 bits consecutive and starting at bit 0.
3845 A 16-bit fragment of a got, tls, or pc-relative reference.
3848 Memory operand except postincrement. This is roughly the same as
3849 @samp{m} when not used together with @samp{<} or @samp{>}.
3852 An 8-element vector constant with identical elements.
3855 A 4-element vector constant with identical elements.
3858 The integer constant 0xffffffff.
3861 The integer constant 0xffffffff00000000.
3865 @item TILEPro---@file{config/tilepro/constraints.md}
3878 Each of these represents a register constraint for an individual
3879 register, from r0 to r10.
3882 Signed 8-bit integer constant.
3885 Signed 16-bit integer constant.
3888 Nonzero integer constant with low 16 bits zero.
3891 Integer constant that fits in one signed byte when incremented by one
3892 (@minus{}129 @dots{} 126).
3895 Memory operand. If used together with @samp{<} or @samp{>}, the
3896 operand can have postincrement which requires printing with @samp{%In}
3897 and @samp{%in} on TILEPro. For example:
3900 asm ("swadd %I0,%1,%i0" : "=m<>" (mem) : "r" (val));
3904 A bit mask suitable for the MM instruction.
3907 Integer constant that is a byte tiled out four times.
3910 The integer zero constant.
3913 Integer constant that is a sign-extended byte tiled out as two shorts.
3916 Integer constant that fits in one signed byte when incremented
3917 (@minus{}129 @dots{} 126), but excluding -1.
3920 A symbolic operand, or a 16-bit fragment of a got, tls, or pc-relative
3924 Memory operand except postincrement. This is roughly the same as
3925 @samp{m} when not used together with @samp{<} or @samp{>}.
3928 A 4-element vector constant with identical elements.
3931 A 2-element vector constant with identical elements.
3935 @item Xtensa---@file{config/xtensa/constraints.md}
3938 General-purpose 32-bit register
3941 One-bit boolean register
3944 MAC16 40-bit accumulator register
3947 Signed 12-bit integer constant, for use in MOVI instructions
3950 Signed 8-bit integer constant, for use in ADDI instructions
3953 Integer constant valid for BccI instructions
3956 Unsigned constant valid for BccUI instructions
3963 @node Disable Insn Alternatives
3964 @subsection Disable insn alternatives using the @code{enabled} attribute
3967 The @code{enabled} insn attribute may be used to disable certain insn
3968 alternatives for machine-specific reasons. This is useful when adding
3969 new instructions to an existing pattern which are only available for
3970 certain cpu architecture levels as specified with the @code{-march=}
3973 If an insn alternative is disabled, then it will never be used. The
3974 compiler treats the constraints for the disabled alternative as
3977 In order to make use of the @code{enabled} attribute a back end has to add
3978 in the machine description files:
3982 A definition of the @code{enabled} insn attribute. The attribute is
3983 defined as usual using the @code{define_attr} command. This
3984 definition should be based on other insn attributes and/or target flags.
3985 The @code{enabled} attribute is a numeric attribute and should evaluate to
3986 @code{(const_int 1)} for an enabled alternative and to
3987 @code{(const_int 0)} otherwise.
3989 A definition of another insn attribute used to describe for what
3990 reason an insn alternative might be available or
3991 not. E.g. @code{cpu_facility} as in the example below.
3993 An assignment for the second attribute to each insn definition
3994 combining instructions which are not all available under the same
3995 circumstances. (Note: It obviously only makes sense for definitions
3996 with more than one alternative. Otherwise the insn pattern should be
3997 disabled or enabled using the insn condition.)
4000 E.g. the following two patterns could easily be merged using the @code{enabled}
4005 (define_insn "*movdi_old"
4006 [(set (match_operand:DI 0 "register_operand" "=d")
4007 (match_operand:DI 1 "register_operand" " d"))]
4011 (define_insn "*movdi_new"
4012 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4013 (match_operand:DI 1 "register_operand" " d,d,f"))]
4026 (define_insn "*movdi_combined"
4027 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4028 (match_operand:DI 1 "register_operand" " d,d,f"))]
4034 [(set_attr "cpu_facility" "*,new,new")])
4038 with the @code{enabled} attribute defined like this:
4042 (define_attr "cpu_facility" "standard,new" (const_string "standard"))
4044 (define_attr "enabled" ""
4045 (cond [(eq_attr "cpu_facility" "standard") (const_int 1)
4046 (and (eq_attr "cpu_facility" "new")
4047 (ne (symbol_ref "TARGET_NEW") (const_int 0)))
4056 @node Define Constraints
4057 @subsection Defining Machine-Specific Constraints
4058 @cindex defining constraints
4059 @cindex constraints, defining
4061 Machine-specific constraints fall into two categories: register and
4062 non-register constraints. Within the latter category, constraints
4063 which allow subsets of all possible memory or address operands should
4064 be specially marked, to give @code{reload} more information.
4066 Machine-specific constraints can be given names of arbitrary length,
4067 but they must be entirely composed of letters, digits, underscores
4068 (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
4069 must begin with a letter or underscore.
4071 In order to avoid ambiguity in operand constraint strings, no
4072 constraint can have a name that begins with any other constraint's
4073 name. For example, if @code{x} is defined as a constraint name,
4074 @code{xy} may not be, and vice versa. As a consequence of this rule,
4075 no constraint may begin with one of the generic constraint letters:
4076 @samp{E F V X g i m n o p r s}.
4078 Register constraints correspond directly to register classes.
4079 @xref{Register Classes}. There is thus not much flexibility in their
4082 @deffn {MD Expression} define_register_constraint name regclass docstring
4083 All three arguments are string constants.
4084 @var{name} is the name of the constraint, as it will appear in
4085 @code{match_operand} expressions. If @var{name} is a multi-letter
4086 constraint its length shall be the same for all constraints starting
4087 with the same letter. @var{regclass} can be either the
4088 name of the corresponding register class (@pxref{Register Classes}),
4089 or a C expression which evaluates to the appropriate register class.
4090 If it is an expression, it must have no side effects, and it cannot
4091 look at the operand. The usual use of expressions is to map some
4092 register constraints to @code{NO_REGS} when the register class
4093 is not available on a given subarchitecture.
4095 @var{docstring} is a sentence documenting the meaning of the
4096 constraint. Docstrings are explained further below.
4099 Non-register constraints are more like predicates: the constraint
4100 definition gives a Boolean expression which indicates whether the
4103 @deffn {MD Expression} define_constraint name docstring exp
4104 The @var{name} and @var{docstring} arguments are the same as for
4105 @code{define_register_constraint}, but note that the docstring comes
4106 immediately after the name for these expressions. @var{exp} is an RTL
4107 expression, obeying the same rules as the RTL expressions in predicate
4108 definitions. @xref{Defining Predicates}, for details. If it
4109 evaluates true, the constraint matches; if it evaluates false, it
4110 doesn't. Constraint expressions should indicate which RTL codes they
4111 might match, just like predicate expressions.
4113 @code{match_test} C expressions have access to the
4114 following variables:
4118 The RTL object defining the operand.
4120 The machine mode of @var{op}.
4122 @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
4124 @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer
4125 @code{const_double}.
4127 @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer
4128 @code{const_double}.
4130 @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point
4131 @code{const_double}.
4134 The @var{*val} variables should only be used once another piece of the
4135 expression has verified that @var{op} is the appropriate kind of RTL
4139 Most non-register constraints should be defined with
4140 @code{define_constraint}. The remaining two definition expressions
4141 are only appropriate for constraints that should be handled specially
4142 by @code{reload} if they fail to match.
4144 @deffn {MD Expression} define_memory_constraint name docstring exp
4145 Use this expression for constraints that match a subset of all memory
4146 operands: that is, @code{reload} can make them match by converting the
4147 operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a
4148 base register (from the register class specified by
4149 @code{BASE_REG_CLASS}, @pxref{Register Classes}).
4151 For example, on the S/390, some instructions do not accept arbitrary
4152 memory references, but only those that do not make use of an index
4153 register. The constraint letter @samp{Q} is defined to represent a
4154 memory address of this type. If @samp{Q} is defined with
4155 @code{define_memory_constraint}, a @samp{Q} constraint can handle any
4156 memory operand, because @code{reload} knows it can simply copy the
4157 memory address into a base register if required. This is analogous to
4158 the way an @samp{o} constraint can handle any memory operand.
4160 The syntax and semantics are otherwise identical to
4161 @code{define_constraint}.
4164 @deffn {MD Expression} define_address_constraint name docstring exp
4165 Use this expression for constraints that match a subset of all address
4166 operands: that is, @code{reload} can make the constraint match by
4167 converting the operand to the form @samp{@w{(reg @var{X})}}, again
4168 with @var{X} a base register.
4170 Constraints defined with @code{define_address_constraint} can only be
4171 used with the @code{address_operand} predicate, or machine-specific
4172 predicates that work the same way. They are treated analogously to
4173 the generic @samp{p} constraint.
4175 The syntax and semantics are otherwise identical to
4176 @code{define_constraint}.
4179 For historical reasons, names beginning with the letters @samp{G H}
4180 are reserved for constraints that match only @code{const_double}s, and
4181 names beginning with the letters @samp{I J K L M N O P} are reserved
4182 for constraints that match only @code{const_int}s. This may change in
4183 the future. For the time being, constraints with these names must be
4184 written in a stylized form, so that @code{genpreds} can tell you did
4189 (define_constraint "[@var{GHIJKLMNOP}]@dots{}"
4191 (and (match_code "const_int") ; @r{@code{const_double} for G/H}
4192 @var{condition}@dots{})) ; @r{usually a @code{match_test}}
4195 @c the semicolons line up in the formatted manual
4197 It is fine to use names beginning with other letters for constraints
4198 that match @code{const_double}s or @code{const_int}s.
4200 Each docstring in a constraint definition should be one or more complete
4201 sentences, marked up in Texinfo format. @emph{They are currently unused.}
4202 In the future they will be copied into the GCC manual, in @ref{Machine
4203 Constraints}, replacing the hand-maintained tables currently found in
4204 that section. Also, in the future the compiler may use this to give
4205 more helpful diagnostics when poor choice of @code{asm} constraints
4206 causes a reload failure.
4208 If you put the pseudo-Texinfo directive @samp{@@internal} at the
4209 beginning of a docstring, then (in the future) it will appear only in
4210 the internals manual's version of the machine-specific constraint tables.
4211 Use this for constraints that should not appear in @code{asm} statements.
4213 @node C Constraint Interface
4214 @subsection Testing constraints from C
4215 @cindex testing constraints
4216 @cindex constraints, testing
4218 It is occasionally useful to test a constraint from C code rather than
4219 implicitly via the constraint string in a @code{match_operand}. The
4220 generated file @file{tm_p.h} declares a few interfaces for working
4221 with machine-specific constraints. None of these interfaces work with
4222 the generic constraints described in @ref{Simple Constraints}. This
4223 may change in the future.
4225 @strong{Warning:} @file{tm_p.h} may declare other functions that
4226 operate on constraints, besides the ones documented here. Do not use
4227 those functions from machine-dependent code. They exist to implement
4228 the old constraint interface that machine-independent components of
4229 the compiler still expect. They will change or disappear in the
4232 Some valid constraint names are not valid C identifiers, so there is a
4233 mangling scheme for referring to them from C@. Constraint names that
4234 do not contain angle brackets or underscores are left unchanged.
4235 Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and
4236 each @samp{>} with @samp{_g}. Here are some examples:
4238 @c the @c's prevent double blank lines in the printed manual.
4240 @multitable {Original} {Mangled}
4241 @item @strong{Original} @tab @strong{Mangled} @c
4242 @item @code{x} @tab @code{x} @c
4243 @item @code{P42x} @tab @code{P42x} @c
4244 @item @code{P4_x} @tab @code{P4__x} @c
4245 @item @code{P4>x} @tab @code{P4_gx} @c
4246 @item @code{P4>>} @tab @code{P4_g_g} @c
4247 @item @code{P4_g>} @tab @code{P4__g_g} @c
4251 Throughout this section, the variable @var{c} is either a constraint
4252 in the abstract sense, or a constant from @code{enum constraint_num};
4253 the variable @var{m} is a mangled constraint name (usually as part of
4254 a larger identifier).
4256 @deftp Enum constraint_num
4257 For each machine-specific constraint, there is a corresponding
4258 enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the
4259 constraint. Functions that take an @code{enum constraint_num} as an
4260 argument expect one of these constants.
4262 Machine-independent constraints do not have associated constants.
4263 This may change in the future.
4266 @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp})
4267 For each machine-specific, non-register constraint @var{m}, there is
4268 one of these functions; it returns @code{true} if @var{exp} satisfies the
4269 constraint. These functions are only visible if @file{rtl.h} was included
4270 before @file{tm_p.h}.
4273 @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c})
4274 Like the @code{satisfies_constraint_@var{m}} functions, but the
4275 constraint to test is given as an argument, @var{c}. If @var{c}
4276 specifies a register constraint, this function will always return
4280 @deftypefun {enum reg_class} regclass_for_constraint (enum constraint_num @var{c})
4281 Returns the register class associated with @var{c}. If @var{c} is not
4282 a register constraint, or those registers are not available for the
4283 currently selected subtarget, returns @code{NO_REGS}.
4286 Here is an example use of @code{satisfies_constraint_@var{m}}. In
4287 peephole optimizations (@pxref{Peephole Definitions}), operand
4288 constraint strings are ignored, so if there are relevant constraints,
4289 they must be tested in the C condition. In the example, the
4290 optimization is applied if operand 2 does @emph{not} satisfy the
4291 @samp{K} constraint. (This is a simplified version of a peephole
4292 definition from the i386 machine description.)
4296 [(match_scratch:SI 3 "r")
4297 (set (match_operand:SI 0 "register_operand" "")
4298 (mult:SI (match_operand:SI 1 "memory_operand" "")
4299 (match_operand:SI 2 "immediate_operand" "")))]
4301 "!satisfies_constraint_K (operands[2])"
4303 [(set (match_dup 3) (match_dup 1))
4304 (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))]
4309 @node Standard Names
4310 @section Standard Pattern Names For Generation
4311 @cindex standard pattern names
4312 @cindex pattern names
4313 @cindex names, pattern
4315 Here is a table of the instruction names that are meaningful in the RTL
4316 generation pass of the compiler. Giving one of these names to an
4317 instruction pattern tells the RTL generation pass that it can use the
4318 pattern to accomplish a certain task.
4321 @cindex @code{mov@var{m}} instruction pattern
4322 @item @samp{mov@var{m}}
4323 Here @var{m} stands for a two-letter machine mode name, in lowercase.
4324 This instruction pattern moves data with that machine mode from operand
4325 1 to operand 0. For example, @samp{movsi} moves full-word data.
4327 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
4328 own mode is wider than @var{m}, the effect of this instruction is
4329 to store the specified value in the part of the register that corresponds
4330 to mode @var{m}. Bits outside of @var{m}, but which are within the
4331 same target word as the @code{subreg} are undefined. Bits which are
4332 outside the target word are left unchanged.
4334 This class of patterns is special in several ways. First of all, each
4335 of these names up to and including full word size @emph{must} be defined,
4336 because there is no other way to copy a datum from one place to another.
4337 If there are patterns accepting operands in larger modes,
4338 @samp{mov@var{m}} must be defined for integer modes of those sizes.
4340 Second, these patterns are not used solely in the RTL generation pass.
4341 Even the reload pass can generate move insns to copy values from stack
4342 slots into temporary registers. When it does so, one of the operands is
4343 a hard register and the other is an operand that can need to be reloaded
4347 Therefore, when given such a pair of operands, the pattern must generate
4348 RTL which needs no reloading and needs no temporary registers---no
4349 registers other than the operands. For example, if you support the
4350 pattern with a @code{define_expand}, then in such a case the
4351 @code{define_expand} mustn't call @code{force_reg} or any other such
4352 function which might generate new pseudo registers.
4354 This requirement exists even for subword modes on a RISC machine where
4355 fetching those modes from memory normally requires several insns and
4356 some temporary registers.
4358 @findex change_address
4359 During reload a memory reference with an invalid address may be passed
4360 as an operand. Such an address will be replaced with a valid address
4361 later in the reload pass. In this case, nothing may be done with the
4362 address except to use it as it stands. If it is copied, it will not be
4363 replaced with a valid address. No attempt should be made to make such
4364 an address into a valid address and no routine (such as
4365 @code{change_address}) that will do so may be called. Note that
4366 @code{general_operand} will fail when applied to such an address.
4368 @findex reload_in_progress
4369 The global variable @code{reload_in_progress} (which must be explicitly
4370 declared if required) can be used to determine whether such special
4371 handling is required.
4373 The variety of operands that have reloads depends on the rest of the
4374 machine description, but typically on a RISC machine these can only be
4375 pseudo registers that did not get hard registers, while on other
4376 machines explicit memory references will get optional reloads.
4378 If a scratch register is required to move an object to or from memory,
4379 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
4381 If there are cases which need scratch registers during or after reload,
4382 you must provide an appropriate secondary_reload target hook.
4384 @findex can_create_pseudo_p
4385 The macro @code{can_create_pseudo_p} can be used to determine if it
4386 is unsafe to create new pseudo registers. If this variable is nonzero, then
4387 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
4389 The constraints on a @samp{mov@var{m}} must permit moving any hard
4390 register to any other hard register provided that
4391 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
4392 @code{TARGET_REGISTER_MOVE_COST} applied to their classes returns a value
4395 It is obligatory to support floating point @samp{mov@var{m}}
4396 instructions into and out of any registers that can hold fixed point
4397 values, because unions and structures (which have modes @code{SImode} or
4398 @code{DImode}) can be in those registers and they may have floating
4401 There may also be a need to support fixed point @samp{mov@var{m}}
4402 instructions in and out of floating point registers. Unfortunately, I
4403 have forgotten why this was so, and I don't know whether it is still
4404 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
4405 floating point registers, then the constraints of the fixed point
4406 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
4407 reload into a floating point register.
4409 @cindex @code{reload_in} instruction pattern
4410 @cindex @code{reload_out} instruction pattern
4411 @item @samp{reload_in@var{m}}
4412 @itemx @samp{reload_out@var{m}}
4413 These named patterns have been obsoleted by the target hook
4414 @code{secondary_reload}.
4416 Like @samp{mov@var{m}}, but used when a scratch register is required to
4417 move between operand 0 and operand 1. Operand 2 describes the scratch
4418 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
4419 macro in @pxref{Register Classes}.
4421 There are special restrictions on the form of the @code{match_operand}s
4422 used in these patterns. First, only the predicate for the reload
4423 operand is examined, i.e., @code{reload_in} examines operand 1, but not
4424 the predicates for operand 0 or 2. Second, there may be only one
4425 alternative in the constraints. Third, only a single register class
4426 letter may be used for the constraint; subsequent constraint letters
4427 are ignored. As a special exception, an empty constraint string
4428 matches the @code{ALL_REGS} register class. This may relieve ports
4429 of the burden of defining an @code{ALL_REGS} constraint letter just
4432 @cindex @code{movstrict@var{m}} instruction pattern
4433 @item @samp{movstrict@var{m}}
4434 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
4435 with mode @var{m} of a register whose natural mode is wider,
4436 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
4437 any of the register except the part which belongs to mode @var{m}.
4439 @cindex @code{movmisalign@var{m}} instruction pattern
4440 @item @samp{movmisalign@var{m}}
4441 This variant of a move pattern is designed to load or store a value
4442 from a memory address that is not naturally aligned for its mode.
4443 For a store, the memory will be in operand 0; for a load, the memory
4444 will be in operand 1. The other operand is guaranteed not to be a
4445 memory, so that it's easy to tell whether this is a load or store.
4447 This pattern is used by the autovectorizer, and when expanding a
4448 @code{MISALIGNED_INDIRECT_REF} expression.
4450 @cindex @code{load_multiple} instruction pattern
4451 @item @samp{load_multiple}
4452 Load several consecutive memory locations into consecutive registers.
4453 Operand 0 is the first of the consecutive registers, operand 1
4454 is the first memory location, and operand 2 is a constant: the
4455 number of consecutive registers.
4457 Define this only if the target machine really has such an instruction;
4458 do not define this if the most efficient way of loading consecutive
4459 registers from memory is to do them one at a time.
4461 On some machines, there are restrictions as to which consecutive
4462 registers can be stored into memory, such as particular starting or
4463 ending register numbers or only a range of valid counts. For those
4464 machines, use a @code{define_expand} (@pxref{Expander Definitions})
4465 and make the pattern fail if the restrictions are not met.
4467 Write the generated insn as a @code{parallel} with elements being a
4468 @code{set} of one register from the appropriate memory location (you may
4469 also need @code{use} or @code{clobber} elements). Use a
4470 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
4471 @file{rs6000.md} for examples of the use of this insn pattern.
4473 @cindex @samp{store_multiple} instruction pattern
4474 @item @samp{store_multiple}
4475 Similar to @samp{load_multiple}, but store several consecutive registers
4476 into consecutive memory locations. Operand 0 is the first of the
4477 consecutive memory locations, operand 1 is the first register, and
4478 operand 2 is a constant: the number of consecutive registers.
4480 @cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern
4481 @item @samp{vec_load_lanes@var{m}@var{n}}
4482 Perform an interleaved load of several vectors from memory operand 1
4483 into register operand 0. Both operands have mode @var{m}. The register
4484 operand is viewed as holding consecutive vectors of mode @var{n},
4485 while the memory operand is a flat array that contains the same number
4486 of elements. The operation is equivalent to:
4489 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4490 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4491 for (i = 0; i < c; i++)
4492 operand0[i][j] = operand1[j * c + i];
4495 For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values
4496 from memory into a register of mode @samp{TI}@. The register
4497 contains two consecutive vectors of mode @samp{V4HI}@.
4499 This pattern can only be used if:
4501 TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c})
4503 is true. GCC assumes that, if a target supports this kind of
4504 instruction for some mode @var{n}, it also supports unaligned
4505 loads for vectors of mode @var{n}.
4507 @cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern
4508 @item @samp{vec_store_lanes@var{m}@var{n}}
4509 Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory
4510 and register operands reversed. That is, the instruction is
4514 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4515 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4516 for (i = 0; i < c; i++)
4517 operand0[j * c + i] = operand1[i][j];
4520 for a memory operand 0 and register operand 1.
4522 @cindex @code{vec_set@var{m}} instruction pattern
4523 @item @samp{vec_set@var{m}}
4524 Set given field in the vector value. Operand 0 is the vector to modify,
4525 operand 1 is new value of field and operand 2 specify the field index.
4527 @cindex @code{vec_extract@var{m}} instruction pattern
4528 @item @samp{vec_extract@var{m}}
4529 Extract given field from the vector value. Operand 1 is the vector, operand 2
4530 specify field index and operand 0 place to store value into.
4532 @cindex @code{vec_init@var{m}} instruction pattern
4533 @item @samp{vec_init@var{m}}
4534 Initialize the vector to given values. Operand 0 is the vector to initialize
4535 and operand 1 is parallel containing values for individual fields.
4537 @cindex @code{vcond@var{m}@var{n}} instruction pattern
4538 @item @samp{vcond@var{m}@var{n}}
4539 Output a conditional vector move. Operand 0 is the destination to
4540 receive a combination of operand 1 and operand 2, which are of mode @var{m},
4541 dependent on the outcome of the predicate in operand 3 which is a
4542 vector comparison with operands of mode @var{n} in operands 4 and 5. The
4543 modes @var{m} and @var{n} should have the same size. Operand 0
4544 will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk}
4545 where @var{msk} is computed by element-wise evaluation of the vector
4546 comparison with a truth value of all-ones and a false value of all-zeros.
4548 @cindex @code{vec_perm@var{m}} instruction pattern
4549 @item @samp{vec_perm@var{m}}
4550 Output a (variable) vector permutation. Operand 0 is the destination
4551 to receive elements from operand 1 and operand 2, which are of mode
4552 @var{m}. Operand 3 is the @dfn{selector}. It is an integral mode
4553 vector of the same width and number of elements as mode @var{m}.
4555 The input elements are numbered from 0 in operand 1 through
4556 @math{2*@var{N}-1} in operand 2. The elements of the selector must
4557 be computed modulo @math{2*@var{N}}. Note that if
4558 @code{rtx_equal_p(operand1, operand2)}, this can be implemented
4559 with just operand 1 and selector elements modulo @var{N}.
4561 In order to make things easy for a number of targets, if there is no
4562 @samp{vec_perm} pattern for mode @var{m}, but there is for mode @var{q}
4563 where @var{q} is a vector of @code{QImode} of the same width as @var{m},
4564 the middle-end will lower the mode @var{m} @code{VEC_PERM_EXPR} to
4567 @cindex @code{vec_perm_const@var{m}} instruction pattern
4568 @item @samp{vec_perm_const@var{m}}
4569 Like @samp{vec_perm} except that the permutation is a compile-time
4570 constant. That is, operand 3, the @dfn{selector}, is a @code{CONST_VECTOR}.
4572 Some targets cannot perform a permutation with a variable selector,
4573 but can efficiently perform a constant permutation. Further, the
4574 target hook @code{vec_perm_ok} is queried to determine if the
4575 specific constant permutation is available efficiently; the named
4576 pattern is never expanded without @code{vec_perm_ok} returning true.
4578 There is no need for a target to supply both @samp{vec_perm@var{m}}
4579 and @samp{vec_perm_const@var{m}} if the former can trivially implement
4580 the operation with, say, the vector constant loaded into a register.
4582 @cindex @code{push@var{m}1} instruction pattern
4583 @item @samp{push@var{m}1}
4584 Output a push instruction. Operand 0 is value to push. Used only when
4585 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
4586 missing and in such case an @code{mov} expander is used instead, with a
4587 @code{MEM} expression forming the push operation. The @code{mov} expander
4588 method is deprecated.
4590 @cindex @code{add@var{m}3} instruction pattern
4591 @item @samp{add@var{m}3}
4592 Add operand 2 and operand 1, storing the result in operand 0. All operands
4593 must have mode @var{m}. This can be used even on two-address machines, by
4594 means of constraints requiring operands 1 and 0 to be the same location.
4596 @cindex @code{ssadd@var{m}3} instruction pattern
4597 @cindex @code{usadd@var{m}3} instruction pattern
4598 @cindex @code{sub@var{m}3} instruction pattern
4599 @cindex @code{sssub@var{m}3} instruction pattern
4600 @cindex @code{ussub@var{m}3} instruction pattern
4601 @cindex @code{mul@var{m}3} instruction pattern
4602 @cindex @code{ssmul@var{m}3} instruction pattern
4603 @cindex @code{usmul@var{m}3} instruction pattern
4604 @cindex @code{div@var{m}3} instruction pattern
4605 @cindex @code{ssdiv@var{m}3} instruction pattern
4606 @cindex @code{udiv@var{m}3} instruction pattern
4607 @cindex @code{usdiv@var{m}3} instruction pattern
4608 @cindex @code{mod@var{m}3} instruction pattern
4609 @cindex @code{umod@var{m}3} instruction pattern
4610 @cindex @code{umin@var{m}3} instruction pattern
4611 @cindex @code{umax@var{m}3} instruction pattern
4612 @cindex @code{and@var{m}3} instruction pattern
4613 @cindex @code{ior@var{m}3} instruction pattern
4614 @cindex @code{xor@var{m}3} instruction pattern
4615 @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
4616 @itemx @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
4617 @itemx @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
4618 @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
4619 @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
4620 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
4621 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
4622 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
4623 Similar, for other arithmetic operations.
4625 @cindex @code{fma@var{m}4} instruction pattern
4626 @item @samp{fma@var{m}4}
4627 Multiply operand 2 and operand 1, then add operand 3, storing the
4628 result in operand 0 without doing an intermediate rounding step. All
4629 operands must have mode @var{m}. This pattern is used to implement
4630 the @code{fma}, @code{fmaf}, and @code{fmal} builtin functions from
4631 the ISO C99 standard.
4633 @cindex @code{fms@var{m}4} instruction pattern
4634 @item @samp{fms@var{m}4}
4635 Like @code{fma@var{m}4}, except operand 3 subtracted from the
4636 product instead of added to the product. This is represented
4640 (fma:@var{m} @var{op1} @var{op2} (neg:@var{m} @var{op3}))
4643 @cindex @code{fnma@var{m}4} instruction pattern
4644 @item @samp{fnma@var{m}4}
4645 Like @code{fma@var{m}4} except that the intermediate product
4646 is negated before being added to operand 3. This is represented
4650 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} @var{op3})
4653 @cindex @code{fnms@var{m}4} instruction pattern
4654 @item @samp{fnms@var{m}4}
4655 Like @code{fms@var{m}4} except that the intermediate product
4656 is negated before subtracting operand 3. This is represented
4660 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} (neg:@var{m} @var{op3}))
4663 @cindex @code{min@var{m}3} instruction pattern
4664 @cindex @code{max@var{m}3} instruction pattern
4665 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
4666 Signed minimum and maximum operations. When used with floating point,
4667 if both operands are zeros, or if either operand is @code{NaN}, then
4668 it is unspecified which of the two operands is returned as the result.
4670 @cindex @code{reduc_smin_@var{m}} instruction pattern
4671 @cindex @code{reduc_smax_@var{m}} instruction pattern
4672 @item @samp{reduc_smin_@var{m}}, @samp{reduc_smax_@var{m}}
4673 Find the signed minimum/maximum of the elements of a vector. The vector is
4674 operand 1, and the scalar result is stored in the least significant bits of
4675 operand 0 (also a vector). The output and input vector should have the same
4678 @cindex @code{reduc_umin_@var{m}} instruction pattern
4679 @cindex @code{reduc_umax_@var{m}} instruction pattern
4680 @item @samp{reduc_umin_@var{m}}, @samp{reduc_umax_@var{m}}
4681 Find the unsigned minimum/maximum of the elements of a vector. The vector is
4682 operand 1, and the scalar result is stored in the least significant bits of
4683 operand 0 (also a vector). The output and input vector should have the same
4686 @cindex @code{reduc_splus_@var{m}} instruction pattern
4687 @item @samp{reduc_splus_@var{m}}
4688 Compute the sum of the signed elements of a vector. The vector is operand 1,
4689 and the scalar result is stored in the least significant bits of operand 0
4690 (also a vector). The output and input vector should have the same modes.
4692 @cindex @code{reduc_uplus_@var{m}} instruction pattern
4693 @item @samp{reduc_uplus_@var{m}}
4694 Compute the sum of the unsigned elements of a vector. The vector is operand 1,
4695 and the scalar result is stored in the least significant bits of operand 0
4696 (also a vector). The output and input vector should have the same modes.
4698 @cindex @code{sdot_prod@var{m}} instruction pattern
4699 @item @samp{sdot_prod@var{m}}
4700 @cindex @code{udot_prod@var{m}} instruction pattern
4701 @item @samp{udot_prod@var{m}}
4702 Compute the sum of the products of two signed/unsigned elements.
4703 Operand 1 and operand 2 are of the same mode. Their product, which is of a
4704 wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
4705 wider than the mode of the product. The result is placed in operand 0, which
4706 is of the same mode as operand 3.
4708 @cindex @code{ssum_widen@var{m3}} instruction pattern
4709 @item @samp{ssum_widen@var{m3}}
4710 @cindex @code{usum_widen@var{m3}} instruction pattern
4711 @item @samp{usum_widen@var{m3}}
4712 Operands 0 and 2 are of the same mode, which is wider than the mode of
4713 operand 1. Add operand 1 to operand 2 and place the widened result in
4714 operand 0. (This is used express accumulation of elements into an accumulator
4717 @cindex @code{vec_shl_@var{m}} instruction pattern
4718 @cindex @code{vec_shr_@var{m}} instruction pattern
4719 @item @samp{vec_shl_@var{m}}, @samp{vec_shr_@var{m}}
4720 Whole vector left/right shift in bits.
4721 Operand 1 is a vector to be shifted.
4722 Operand 2 is an integer shift amount in bits.
4723 Operand 0 is where the resulting shifted vector is stored.
4724 The output and input vectors should have the same modes.
4726 @cindex @code{vec_pack_trunc_@var{m}} instruction pattern
4727 @item @samp{vec_pack_trunc_@var{m}}
4728 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
4729 are vectors of the same mode having N integral or floating point elements
4730 of size S@. Operand 0 is the resulting vector in which 2*N elements of
4731 size N/2 are concatenated after narrowing them down using truncation.
4733 @cindex @code{vec_pack_ssat_@var{m}} instruction pattern
4734 @cindex @code{vec_pack_usat_@var{m}} instruction pattern
4735 @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}}
4736 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
4737 are vectors of the same mode having N integral elements of size S.
4738 Operand 0 is the resulting vector in which the elements of the two input
4739 vectors are concatenated after narrowing them down using signed/unsigned
4740 saturating arithmetic.
4742 @cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern
4743 @cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern
4744 @item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}}
4745 Narrow, convert to signed/unsigned integral type and merge the elements
4746 of two vectors. Operands 1 and 2 are vectors of the same mode having N
4747 floating point elements of size S@. Operand 0 is the resulting vector
4748 in which 2*N elements of size N/2 are concatenated.
4750 @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern
4751 @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern
4752 @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}}
4753 Extract and widen (promote) the high/low part of a vector of signed
4754 integral or floating point elements. The input vector (operand 1) has N
4755 elements of size S@. Widen (promote) the high/low elements of the vector
4756 using signed or floating point extension and place the resulting N/2
4757 values of size 2*S in the output vector (operand 0).
4759 @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern
4760 @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern
4761 @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}}
4762 Extract and widen (promote) the high/low part of a vector of unsigned
4763 integral elements. The input vector (operand 1) has N elements of size S.
4764 Widen (promote) the high/low elements of the vector using zero extension and
4765 place the resulting N/2 values of size 2*S in the output vector (operand 0).
4767 @cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern
4768 @cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern
4769 @cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern
4770 @cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern
4771 @item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}}
4772 @itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}}
4773 Extract, convert to floating point type and widen the high/low part of a
4774 vector of signed/unsigned integral elements. The input vector (operand 1)
4775 has N elements of size S@. Convert the high/low elements of the vector using
4776 floating point conversion and place the resulting N/2 values of size 2*S in
4777 the output vector (operand 0).
4779 @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern
4780 @cindex @code{vec_widen_umult_lo_@var{m}} instruction pattern
4781 @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern
4782 @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern
4783 @cindex @code{vec_widen_umult_even_@var{m}} instruction pattern
4784 @cindex @code{vec_widen_umult_odd_@var{m}} instruction pattern
4785 @cindex @code{vec_widen_smult_even_@var{m}} instruction pattern
4786 @cindex @code{vec_widen_smult_odd_@var{m}} instruction pattern
4787 @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}}
4788 @itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}}
4789 @itemx @samp{vec_widen_umult_even_@var{m}}, @samp{vec_widen_umult_odd_@var{m}}
4790 @itemx @samp{vec_widen_smult_even_@var{m}}, @samp{vec_widen_smult_odd_@var{m}}
4791 Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
4792 are vectors with N signed/unsigned elements of size S@. Multiply the high/low
4793 or even/odd elements of the two vectors, and put the N/2 products of size 2*S
4794 in the output vector (operand 0).
4796 @cindex @code{vec_widen_ushiftl_hi_@var{m}} instruction pattern
4797 @cindex @code{vec_widen_ushiftl_lo_@var{m}} instruction pattern
4798 @cindex @code{vec_widen_sshiftl_hi_@var{m}} instruction pattern
4799 @cindex @code{vec_widen_sshiftl_lo_@var{m}} instruction pattern
4800 @item @samp{vec_widen_ushiftl_hi_@var{m}}, @samp{vec_widen_ushiftl_lo_@var{m}}
4801 @itemx @samp{vec_widen_sshiftl_hi_@var{m}}, @samp{vec_widen_sshiftl_lo_@var{m}}
4802 Signed/Unsigned widening shift left. The first input (operand 1) is a vector
4803 with N signed/unsigned elements of size S@. Operand 2 is a constant. Shift
4804 the high/low elements of operand 1, and put the N/2 results of size 2*S in the
4805 output vector (operand 0).
4807 @cindex @code{mulhisi3} instruction pattern
4808 @item @samp{mulhisi3}
4809 Multiply operands 1 and 2, which have mode @code{HImode}, and store
4810 a @code{SImode} product in operand 0.
4812 @cindex @code{mulqihi3} instruction pattern
4813 @cindex @code{mulsidi3} instruction pattern
4814 @item @samp{mulqihi3}, @samp{mulsidi3}
4815 Similar widening-multiplication instructions of other widths.
4817 @cindex @code{umulqihi3} instruction pattern
4818 @cindex @code{umulhisi3} instruction pattern
4819 @cindex @code{umulsidi3} instruction pattern
4820 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
4821 Similar widening-multiplication instructions that do unsigned
4824 @cindex @code{usmulqihi3} instruction pattern
4825 @cindex @code{usmulhisi3} instruction pattern
4826 @cindex @code{usmulsidi3} instruction pattern
4827 @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3}
4828 Similar widening-multiplication instructions that interpret the first
4829 operand as unsigned and the second operand as signed, then do a signed
4832 @cindex @code{smul@var{m}3_highpart} instruction pattern
4833 @item @samp{smul@var{m}3_highpart}
4834 Perform a signed multiplication of operands 1 and 2, which have mode
4835 @var{m}, and store the most significant half of the product in operand 0.
4836 The least significant half of the product is discarded.
4838 @cindex @code{umul@var{m}3_highpart} instruction pattern
4839 @item @samp{umul@var{m}3_highpart}
4840 Similar, but the multiplication is unsigned.
4842 @cindex @code{madd@var{m}@var{n}4} instruction pattern
4843 @item @samp{madd@var{m}@var{n}4}
4844 Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
4845 operand 3, and store the result in operand 0. Operands 1 and 2
4846 have mode @var{m} and operands 0 and 3 have mode @var{n}.
4847 Both modes must be integer or fixed-point modes and @var{n} must be twice
4848 the size of @var{m}.
4850 In other words, @code{madd@var{m}@var{n}4} is like
4851 @code{mul@var{m}@var{n}3} except that it also adds operand 3.
4853 These instructions are not allowed to @code{FAIL}.
4855 @cindex @code{umadd@var{m}@var{n}4} instruction pattern
4856 @item @samp{umadd@var{m}@var{n}4}
4857 Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
4858 operands instead of sign-extending them.
4860 @cindex @code{ssmadd@var{m}@var{n}4} instruction pattern
4861 @item @samp{ssmadd@var{m}@var{n}4}
4862 Like @code{madd@var{m}@var{n}4}, but all involved operations must be
4865 @cindex @code{usmadd@var{m}@var{n}4} instruction pattern
4866 @item @samp{usmadd@var{m}@var{n}4}
4867 Like @code{umadd@var{m}@var{n}4}, but all involved operations must be
4868 unsigned-saturating.
4870 @cindex @code{msub@var{m}@var{n}4} instruction pattern
4871 @item @samp{msub@var{m}@var{n}4}
4872 Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the
4873 result from operand 3, and store the result in operand 0. Operands 1 and 2
4874 have mode @var{m} and operands 0 and 3 have mode @var{n}.
4875 Both modes must be integer or fixed-point modes and @var{n} must be twice
4876 the size of @var{m}.
4878 In other words, @code{msub@var{m}@var{n}4} is like
4879 @code{mul@var{m}@var{n}3} except that it also subtracts the result
4882 These instructions are not allowed to @code{FAIL}.
4884 @cindex @code{umsub@var{m}@var{n}4} instruction pattern
4885 @item @samp{umsub@var{m}@var{n}4}
4886 Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication
4887 operands instead of sign-extending them.
4889 @cindex @code{ssmsub@var{m}@var{n}4} instruction pattern
4890 @item @samp{ssmsub@var{m}@var{n}4}
4891 Like @code{msub@var{m}@var{n}4}, but all involved operations must be
4894 @cindex @code{usmsub@var{m}@var{n}4} instruction pattern
4895 @item @samp{usmsub@var{m}@var{n}4}
4896 Like @code{umsub@var{m}@var{n}4}, but all involved operations must be
4897 unsigned-saturating.
4899 @cindex @code{divmod@var{m}4} instruction pattern
4900 @item @samp{divmod@var{m}4}
4901 Signed division that produces both a quotient and a remainder.
4902 Operand 1 is divided by operand 2 to produce a quotient stored
4903 in operand 0 and a remainder stored in operand 3.
4905 For machines with an instruction that produces both a quotient and a
4906 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
4907 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
4908 allows optimization in the relatively common case when both the quotient
4909 and remainder are computed.
4911 If an instruction that just produces a quotient or just a remainder
4912 exists and is more efficient than the instruction that produces both,
4913 write the output routine of @samp{divmod@var{m}4} to call
4914 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
4915 quotient or remainder and generate the appropriate instruction.
4917 @cindex @code{udivmod@var{m}4} instruction pattern
4918 @item @samp{udivmod@var{m}4}
4919 Similar, but does unsigned division.
4921 @anchor{shift patterns}
4922 @cindex @code{ashl@var{m}3} instruction pattern
4923 @cindex @code{ssashl@var{m}3} instruction pattern
4924 @cindex @code{usashl@var{m}3} instruction pattern
4925 @item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3}
4926 Arithmetic-shift operand 1 left by a number of bits specified by operand
4927 2, and store the result in operand 0. Here @var{m} is the mode of
4928 operand 0 and operand 1; operand 2's mode is specified by the
4929 instruction pattern, and the compiler will convert the operand to that
4930 mode before generating the instruction. The meaning of out-of-range shift
4931 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
4932 @xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type.
4934 @cindex @code{ashr@var{m}3} instruction pattern
4935 @cindex @code{lshr@var{m}3} instruction pattern
4936 @cindex @code{rotl@var{m}3} instruction pattern
4937 @cindex @code{rotr@var{m}3} instruction pattern
4938 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
4939 Other shift and rotate instructions, analogous to the
4940 @code{ashl@var{m}3} instructions. Operand 2 is always a scalar type.
4942 @cindex @code{vashl@var{m}3} instruction pattern
4943 @cindex @code{vashr@var{m}3} instruction pattern
4944 @cindex @code{vlshr@var{m}3} instruction pattern
4945 @cindex @code{vrotl@var{m}3} instruction pattern
4946 @cindex @code{vrotr@var{m}3} instruction pattern
4947 @item @samp{vashl@var{m}3}, @samp{vashr@var{m}3}, @samp{vlshr@var{m}3}, @samp{vrotl@var{m}3}, @samp{vrotr@var{m}3}
4948 Vector shift and rotate instructions that take vectors as operand 2
4949 instead of a scalar type.
4951 @cindex @code{bswap@var{m}2} instruction pattern
4952 @item @samp{bswap@var{m}2}
4953 Reverse the order of bytes of operand 1 and store the result in operand 0.
4955 @cindex @code{neg@var{m}2} instruction pattern
4956 @cindex @code{ssneg@var{m}2} instruction pattern
4957 @cindex @code{usneg@var{m}2} instruction pattern
4958 @item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2}
4959 Negate operand 1 and store the result in operand 0.
4961 @cindex @code{abs@var{m}2} instruction pattern
4962 @item @samp{abs@var{m}2}
4963 Store the absolute value of operand 1 into operand 0.
4965 @cindex @code{sqrt@var{m}2} instruction pattern
4966 @item @samp{sqrt@var{m}2}
4967 Store the square root of operand 1 into operand 0.
4969 The @code{sqrt} built-in function of C always uses the mode which
4970 corresponds to the C data type @code{double} and the @code{sqrtf}
4971 built-in function uses the mode which corresponds to the C data
4974 @cindex @code{fmod@var{m}3} instruction pattern
4975 @item @samp{fmod@var{m}3}
4976 Store the remainder of dividing operand 1 by operand 2 into
4977 operand 0, rounded towards zero to an integer.
4979 The @code{fmod} built-in function of C always uses the mode which
4980 corresponds to the C data type @code{double} and the @code{fmodf}
4981 built-in function uses the mode which corresponds to the C data
4984 @cindex @code{remainder@var{m}3} instruction pattern
4985 @item @samp{remainder@var{m}3}
4986 Store the remainder of dividing operand 1 by operand 2 into
4987 operand 0, rounded to the nearest integer.
4989 The @code{remainder} built-in function of C always uses the mode
4990 which corresponds to the C data type @code{double} and the
4991 @code{remainderf} built-in function uses the mode which corresponds
4992 to the C data type @code{float}.
4994 @cindex @code{cos@var{m}2} instruction pattern
4995 @item @samp{cos@var{m}2}
4996 Store the cosine of operand 1 into operand 0.
4998 The @code{cos} built-in function of C always uses the mode which
4999 corresponds to the C data type @code{double} and the @code{cosf}
5000 built-in function uses the mode which corresponds to the C data
5003 @cindex @code{sin@var{m}2} instruction pattern
5004 @item @samp{sin@var{m}2}
5005 Store the sine of operand 1 into operand 0.
5007 The @code{sin} built-in function of C always uses the mode which
5008 corresponds to the C data type @code{double} and the @code{sinf}
5009 built-in function uses the mode which corresponds to the C data
5012 @cindex @code{sincos@var{m}3} instruction pattern
5013 @item @samp{sincos@var{m}3}
5014 Store the cosine of operand 2 into operand 0 and the sine of
5015 operand 2 into operand 1.
5017 The @code{sin} and @code{cos} built-in functions of C always use the
5018 mode which corresponds to the C data type @code{double} and the
5019 @code{sinf} and @code{cosf} built-in function use the mode which
5020 corresponds to the C data type @code{float}.
5021 Targets that can calculate the sine and cosine simultaneously can
5022 implement this pattern as opposed to implementing individual
5023 @code{sin@var{m}2} and @code{cos@var{m}2} patterns. The @code{sin}
5024 and @code{cos} built-in functions will then be expanded to the
5025 @code{sincos@var{m}3} pattern, with one of the output values
5028 @cindex @code{exp@var{m}2} instruction pattern
5029 @item @samp{exp@var{m}2}
5030 Store the exponential of operand 1 into operand 0.
5032 The @code{exp} built-in function of C always uses the mode which
5033 corresponds to the C data type @code{double} and the @code{expf}
5034 built-in function uses the mode which corresponds to the C data
5037 @cindex @code{log@var{m}2} instruction pattern
5038 @item @samp{log@var{m}2}
5039 Store the natural logarithm of operand 1 into operand 0.
5041 The @code{log} built-in function of C always uses the mode which
5042 corresponds to the C data type @code{double} and the @code{logf}
5043 built-in function uses the mode which corresponds to the C data
5046 @cindex @code{pow@var{m}3} instruction pattern
5047 @item @samp{pow@var{m}3}
5048 Store the value of operand 1 raised to the exponent operand 2
5051 The @code{pow} built-in function of C always uses the mode which
5052 corresponds to the C data type @code{double} and the @code{powf}
5053 built-in function uses the mode which corresponds to the C data
5056 @cindex @code{atan2@var{m}3} instruction pattern
5057 @item @samp{atan2@var{m}3}
5058 Store the arc tangent (inverse tangent) of operand 1 divided by
5059 operand 2 into operand 0, using the signs of both arguments to
5060 determine the quadrant of the result.
5062 The @code{atan2} built-in function of C always uses the mode which
5063 corresponds to the C data type @code{double} and the @code{atan2f}
5064 built-in function uses the mode which corresponds to the C data
5067 @cindex @code{floor@var{m}2} instruction pattern
5068 @item @samp{floor@var{m}2}
5069 Store the largest integral value not greater than argument.
5071 The @code{floor} built-in function of C always uses the mode which
5072 corresponds to the C data type @code{double} and the @code{floorf}
5073 built-in function uses the mode which corresponds to the C data
5076 @cindex @code{btrunc@var{m}2} instruction pattern
5077 @item @samp{btrunc@var{m}2}
5078 Store the argument rounded to integer towards zero.
5080 The @code{trunc} built-in function of C always uses the mode which
5081 corresponds to the C data type @code{double} and the @code{truncf}
5082 built-in function uses the mode which corresponds to the C data
5085 @cindex @code{round@var{m}2} instruction pattern
5086 @item @samp{round@var{m}2}
5087 Store the argument rounded to integer away from zero.
5089 The @code{round} built-in function of C always uses the mode which
5090 corresponds to the C data type @code{double} and the @code{roundf}
5091 built-in function uses the mode which corresponds to the C data
5094 @cindex @code{ceil@var{m}2} instruction pattern
5095 @item @samp{ceil@var{m}2}
5096 Store the argument rounded to integer away from zero.
5098 The @code{ceil} built-in function of C always uses the mode which
5099 corresponds to the C data type @code{double} and the @code{ceilf}
5100 built-in function uses the mode which corresponds to the C data
5103 @cindex @code{nearbyint@var{m}2} instruction pattern
5104 @item @samp{nearbyint@var{m}2}
5105 Store the argument rounded according to the default rounding mode
5107 The @code{nearbyint} built-in function of C always uses the mode which
5108 corresponds to the C data type @code{double} and the @code{nearbyintf}
5109 built-in function uses the mode which corresponds to the C data
5112 @cindex @code{rint@var{m}2} instruction pattern
5113 @item @samp{rint@var{m}2}
5114 Store the argument rounded according to the default rounding mode and
5115 raise the inexact exception when the result differs in value from
5118 The @code{rint} built-in function of C always uses the mode which
5119 corresponds to the C data type @code{double} and the @code{rintf}
5120 built-in function uses the mode which corresponds to the C data
5123 @cindex @code{lrint@var{m}@var{n}2}
5124 @item @samp{lrint@var{m}@var{n}2}
5125 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5126 point mode @var{n} as a signed number according to the current
5127 rounding mode and store in operand 0 (which has mode @var{n}).
5129 @cindex @code{lround@var{m}@var{n}2}
5130 @item @samp{lround@var{m}@var{n}2}
5131 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5132 point mode @var{n} as a signed number rounding to nearest and away
5133 from zero and store in operand 0 (which has mode @var{n}).
5135 @cindex @code{lfloor@var{m}@var{n}2}
5136 @item @samp{lfloor@var{m}@var{n}2}
5137 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5138 point mode @var{n} as a signed number rounding down and store in
5139 operand 0 (which has mode @var{n}).
5141 @cindex @code{lceil@var{m}@var{n}2}
5142 @item @samp{lceil@var{m}@var{n}2}
5143 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5144 point mode @var{n} as a signed number rounding up and store in
5145 operand 0 (which has mode @var{n}).
5147 @cindex @code{copysign@var{m}3} instruction pattern
5148 @item @samp{copysign@var{m}3}
5149 Store a value with the magnitude of operand 1 and the sign of operand
5152 The @code{copysign} built-in function of C always uses the mode which
5153 corresponds to the C data type @code{double} and the @code{copysignf}
5154 built-in function uses the mode which corresponds to the C data
5157 @cindex @code{ffs@var{m}2} instruction pattern
5158 @item @samp{ffs@var{m}2}
5159 Store into operand 0 one plus the index of the least significant 1-bit
5160 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
5161 of operand 0; operand 1's mode is specified by the instruction
5162 pattern, and the compiler will convert the operand to that mode before
5163 generating the instruction.
5165 The @code{ffs} built-in function of C always uses the mode which
5166 corresponds to the C data type @code{int}.
5168 @cindex @code{clz@var{m}2} instruction pattern
5169 @item @samp{clz@var{m}2}
5170 Store into operand 0 the number of leading 0-bits in @var{x}, starting
5171 at the most significant bit position. If @var{x} is 0, the
5172 @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
5173 the result is undefined or has a useful value.
5174 @var{m} is the mode of operand 0; operand 1's mode is
5175 specified by the instruction pattern, and the compiler will convert the
5176 operand to that mode before generating the instruction.
5178 @cindex @code{ctz@var{m}2} instruction pattern
5179 @item @samp{ctz@var{m}2}
5180 Store into operand 0 the number of trailing 0-bits in @var{x}, starting
5181 at the least significant bit position. If @var{x} is 0, the
5182 @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
5183 the result is undefined or has a useful value.
5184 @var{m} is the mode of operand 0; operand 1's mode is
5185 specified by the instruction pattern, and the compiler will convert the
5186 operand to that mode before generating the instruction.
5188 @cindex @code{popcount@var{m}2} instruction pattern
5189 @item @samp{popcount@var{m}2}
5190 Store into operand 0 the number of 1-bits in @var{x}. @var{m} is the
5191 mode of operand 0; operand 1's mode is specified by the instruction
5192 pattern, and the compiler will convert the operand to that mode before
5193 generating the instruction.
5195 @cindex @code{parity@var{m}2} instruction pattern
5196 @item @samp{parity@var{m}2}
5197 Store into operand 0 the parity of @var{x}, i.e.@: the number of 1-bits
5198 in @var{x} modulo 2. @var{m} is the mode of operand 0; operand 1's mode
5199 is specified by the instruction pattern, and the compiler will convert
5200 the operand to that mode before generating the instruction.
5202 @cindex @code{one_cmpl@var{m}2} instruction pattern
5203 @item @samp{one_cmpl@var{m}2}
5204 Store the bitwise-complement of operand 1 into operand 0.
5206 @cindex @code{movmem@var{m}} instruction pattern
5207 @item @samp{movmem@var{m}}
5208 Block move instruction. The destination and source blocks of memory
5209 are the first two operands, and both are @code{mem:BLK}s with an
5210 address in mode @code{Pmode}.
5212 The number of bytes to move is the third operand, in mode @var{m}.
5213 Usually, you specify @code{word_mode} for @var{m}. However, if you can
5214 generate better code knowing the range of valid lengths is smaller than
5215 those representable in a full word, you should provide a pattern with a
5216 mode corresponding to the range of values you can handle efficiently
5217 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
5218 that appear negative) and also a pattern with @code{word_mode}.
5220 The fourth operand is the known shared alignment of the source and
5221 destination, in the form of a @code{const_int} rtx. Thus, if the
5222 compiler knows that both source and destination are word-aligned,
5223 it may provide the value 4 for this operand.
5225 Optional operands 5 and 6 specify expected alignment and size of block
5226 respectively. The expected alignment differs from alignment in operand 4
5227 in a way that the blocks are not required to be aligned according to it in
5228 all cases. This expected alignment is also in bytes, just like operand 4.
5229 Expected size, when unknown, is set to @code{(const_int -1)}.
5231 Descriptions of multiple @code{movmem@var{m}} patterns can only be
5232 beneficial if the patterns for smaller modes have fewer restrictions
5233 on their first, second and fourth operands. Note that the mode @var{m}
5234 in @code{movmem@var{m}} does not impose any restriction on the mode of
5235 individually moved data units in the block.
5237 These patterns need not give special consideration to the possibility
5238 that the source and destination strings might overlap.
5240 @cindex @code{movstr} instruction pattern
5242 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
5243 an output operand in mode @code{Pmode}. The addresses of the
5244 destination and source strings are operands 1 and 2, and both are
5245 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
5246 the expansion of this pattern should store in operand 0 the address in
5247 which the @code{NUL} terminator was stored in the destination string.
5249 @cindex @code{setmem@var{m}} instruction pattern
5250 @item @samp{setmem@var{m}}
5251 Block set instruction. The destination string is the first operand,
5252 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
5253 number of bytes to set is the second operand, in mode @var{m}. The value to
5254 initialize the memory with is the third operand. Targets that only support the
5255 clearing of memory should reject any value that is not the constant 0. See
5256 @samp{movmem@var{m}} for a discussion of the choice of mode.
5258 The fourth operand is the known alignment of the destination, in the form
5259 of a @code{const_int} rtx. Thus, if the compiler knows that the
5260 destination is word-aligned, it may provide the value 4 for this
5263 Optional operands 5 and 6 specify expected alignment and size of block
5264 respectively. The expected alignment differs from alignment in operand 4
5265 in a way that the blocks are not required to be aligned according to it in
5266 all cases. This expected alignment is also in bytes, just like operand 4.
5267 Expected size, when unknown, is set to @code{(const_int -1)}.
5269 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
5271 @cindex @code{cmpstrn@var{m}} instruction pattern
5272 @item @samp{cmpstrn@var{m}}
5273 String compare instruction, with five operands. Operand 0 is the output;
5274 it has mode @var{m}. The remaining four operands are like the operands
5275 of @samp{movmem@var{m}}. The two memory blocks specified are compared
5276 byte by byte in lexicographic order starting at the beginning of each
5277 string. The instruction is not allowed to prefetch more than one byte
5278 at a time since either string may end in the first byte and reading past
5279 that may access an invalid page or segment and cause a fault. The
5280 comparison terminates early if the fetched bytes are different or if
5281 they are equal to zero. The effect of the instruction is to store a
5282 value in operand 0 whose sign indicates the result of the comparison.
5284 @cindex @code{cmpstr@var{m}} instruction pattern
5285 @item @samp{cmpstr@var{m}}
5286 String compare instruction, without known maximum length. Operand 0 is the
5287 output; it has mode @var{m}. The second and third operand are the blocks of
5288 memory to be compared; both are @code{mem:BLK} with an address in mode
5291 The fourth operand is the known shared alignment of the source and
5292 destination, in the form of a @code{const_int} rtx. Thus, if the
5293 compiler knows that both source and destination are word-aligned,
5294 it may provide the value 4 for this operand.
5296 The two memory blocks specified are compared byte by byte in lexicographic
5297 order starting at the beginning of each string. The instruction is not allowed
5298 to prefetch more than one byte at a time since either string may end in the
5299 first byte and reading past that may access an invalid page or segment and
5300 cause a fault. The comparison will terminate when the fetched bytes
5301 are different or if they are equal to zero. The effect of the
5302 instruction is to store a value in operand 0 whose sign indicates the
5303 result of the comparison.
5305 @cindex @code{cmpmem@var{m}} instruction pattern
5306 @item @samp{cmpmem@var{m}}
5307 Block compare instruction, with five operands like the operands
5308 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
5309 byte by byte in lexicographic order starting at the beginning of each
5310 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
5311 any bytes in the two memory blocks. Also unlike @samp{cmpstr@var{m}}
5312 the comparison will not stop if both bytes are zero. The effect of
5313 the instruction is to store a value in operand 0 whose sign indicates
5314 the result of the comparison.
5316 @cindex @code{strlen@var{m}} instruction pattern
5317 @item @samp{strlen@var{m}}
5318 Compute the length of a string, with three operands.
5319 Operand 0 is the result (of mode @var{m}), operand 1 is
5320 a @code{mem} referring to the first character of the string,
5321 operand 2 is the character to search for (normally zero),
5322 and operand 3 is a constant describing the known alignment
5323 of the beginning of the string.
5325 @cindex @code{float@var{m}@var{n}2} instruction pattern
5326 @item @samp{float@var{m}@var{n}2}
5327 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
5328 floating point mode @var{n} and store in operand 0 (which has mode
5331 @cindex @code{floatuns@var{m}@var{n}2} instruction pattern
5332 @item @samp{floatuns@var{m}@var{n}2}
5333 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
5334 to floating point mode @var{n} and store in operand 0 (which has mode
5337 @cindex @code{fix@var{m}@var{n}2} instruction pattern
5338 @item @samp{fix@var{m}@var{n}2}
5339 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5340 point mode @var{n} as a signed number and store in operand 0 (which
5341 has mode @var{n}). This instruction's result is defined only when
5342 the value of operand 1 is an integer.
5344 If the machine description defines this pattern, it also needs to
5345 define the @code{ftrunc} pattern.
5347 @cindex @code{fixuns@var{m}@var{n}2} instruction pattern
5348 @item @samp{fixuns@var{m}@var{n}2}
5349 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5350 point mode @var{n} as an unsigned number and store in operand 0 (which
5351 has mode @var{n}). This instruction's result is defined only when the
5352 value of operand 1 is an integer.
5354 @cindex @code{ftrunc@var{m}2} instruction pattern
5355 @item @samp{ftrunc@var{m}2}
5356 Convert operand 1 (valid for floating point mode @var{m}) to an
5357 integer value, still represented in floating point mode @var{m}, and
5358 store it in operand 0 (valid for floating point mode @var{m}).
5360 @cindex @code{fix_trunc@var{m}@var{n}2} instruction pattern
5361 @item @samp{fix_trunc@var{m}@var{n}2}
5362 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
5363 of mode @var{m} by converting the value to an integer.
5365 @cindex @code{fixuns_trunc@var{m}@var{n}2} instruction pattern
5366 @item @samp{fixuns_trunc@var{m}@var{n}2}
5367 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
5368 value of mode @var{m} by converting the value to an integer.
5370 @cindex @code{trunc@var{m}@var{n}2} instruction pattern
5371 @item @samp{trunc@var{m}@var{n}2}
5372 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
5373 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5374 point or both floating point.
5376 @cindex @code{extend@var{m}@var{n}2} instruction pattern
5377 @item @samp{extend@var{m}@var{n}2}
5378 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
5379 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5380 point or both floating point.
5382 @cindex @code{zero_extend@var{m}@var{n}2} instruction pattern
5383 @item @samp{zero_extend@var{m}@var{n}2}
5384 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
5385 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5388 @cindex @code{fract@var{m}@var{n}2} instruction pattern
5389 @item @samp{fract@var{m}@var{n}2}
5390 Convert operand 1 of mode @var{m} to mode @var{n} and store in
5391 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5392 could be fixed-point to fixed-point, signed integer to fixed-point,
5393 fixed-point to signed integer, floating-point to fixed-point,
5394 or fixed-point to floating-point.
5395 When overflows or underflows happen, the results are undefined.
5397 @cindex @code{satfract@var{m}@var{n}2} instruction pattern
5398 @item @samp{satfract@var{m}@var{n}2}
5399 Convert operand 1 of mode @var{m} to mode @var{n} and store in
5400 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5401 could be fixed-point to fixed-point, signed integer to fixed-point,
5402 or floating-point to fixed-point.
5403 When overflows or underflows happen, the instruction saturates the
5404 results to the maximum or the minimum.
5406 @cindex @code{fractuns@var{m}@var{n}2} instruction pattern
5407 @item @samp{fractuns@var{m}@var{n}2}
5408 Convert operand 1 of mode @var{m} to mode @var{n} and store in
5409 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5410 could be unsigned integer to fixed-point, or
5411 fixed-point to unsigned integer.
5412 When overflows or underflows happen, the results are undefined.
5414 @cindex @code{satfractuns@var{m}@var{n}2} instruction pattern
5415 @item @samp{satfractuns@var{m}@var{n}2}
5416 Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode
5417 @var{n} and store in operand 0 (which has mode @var{n}).
5418 When overflows or underflows happen, the instruction saturates the
5419 results to the maximum or the minimum.
5421 @cindex @code{extv@var{m}} instruction pattern
5422 @item @samp{extv@var{m}}
5423 Extract a bit-field from register operand 1, sign-extend it, and store
5424 it in operand 0. Operand 2 specifies the width of the field in bits
5425 and operand 3 the starting bit, which counts from the most significant
5426 bit if @samp{BITS_BIG_ENDIAN} is true and from the least significant bit
5429 Operands 0 and 1 both have mode @var{m}. Operands 2 and 3 have a
5430 target-specific mode.
5432 @cindex @code{extvmisalign@var{m}} instruction pattern
5433 @item @samp{extvmisalign@var{m}}
5434 Extract a bit-field from memory operand 1, sign extend it, and store
5435 it in operand 0. Operand 2 specifies the width in bits and operand 3
5436 the starting bit. The starting bit is always somewhere in the first byte of
5437 operand 1; it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
5438 is true and from the least significant bit otherwise.
5440 Operand 0 has mode @var{m} while operand 1 has @code{BLK} mode.
5441 Operands 2 and 3 have a target-specific mode.
5443 The instruction must not read beyond the last byte of the bit-field.
5445 @cindex @code{extzv@var{m}} instruction pattern
5446 @item @samp{extzv@var{m}}
5447 Like @samp{extv@var{m}} except that the bit-field value is zero-extended.
5449 @cindex @code{extzvmisalign@var{m}} instruction pattern
5450 @item @samp{extzvmisalign@var{m}}
5451 Like @samp{extvmisalign@var{m}} except that the bit-field value is
5454 @cindex @code{insv@var{m}} instruction pattern
5455 @item @samp{insv@var{m}}
5456 Insert operand 3 into a bit-field of register operand 0. Operand 1
5457 specifies the width of the field in bits and operand 2 the starting bit,
5458 which counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
5459 is true and from the least significant bit otherwise.
5461 Operands 0 and 3 both have mode @var{m}. Operands 1 and 2 have a
5462 target-specific mode.
5464 @cindex @code{insvmisalign@var{m}} instruction pattern
5465 @item @samp{insvmisalign@var{m}}
5466 Insert operand 3 into a bit-field of memory operand 0. Operand 1
5467 specifies the width of the field in bits and operand 2 the starting bit.
5468 The starting bit is always somewhere in the first byte of operand 0;
5469 it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
5470 is true and from the least significant bit otherwise.
5472 Operand 3 has mode @var{m} while operand 0 has @code{BLK} mode.
5473 Operands 1 and 2 have a target-specific mode.
5475 The instruction must not read or write beyond the last byte of the bit-field.
5477 @cindex @code{extv} instruction pattern
5479 Extract a bit-field from operand 1 (a register or memory operand), where
5480 operand 2 specifies the width in bits and operand 3 the starting bit,
5481 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
5482 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
5483 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
5484 be valid for @code{word_mode}.
5486 The RTL generation pass generates this instruction only with constants
5487 for operands 2 and 3 and the constant is never zero for operand 2.
5489 The bit-field value is sign-extended to a full word integer
5490 before it is stored in operand 0.
5492 This pattern is deprecated; please use @samp{extv@var{m}} and
5493 @code{extvmisalign@var{m}} instead.
5495 @cindex @code{extzv} instruction pattern
5497 Like @samp{extv} except that the bit-field value is zero-extended.
5499 This pattern is deprecated; please use @samp{extzv@var{m}} and
5500 @code{extzvmisalign@var{m}} instead.
5502 @cindex @code{insv} instruction pattern
5504 Store operand 3 (which must be valid for @code{word_mode}) into a
5505 bit-field in operand 0, where operand 1 specifies the width in bits and
5506 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
5507 @code{word_mode}; often @code{word_mode} is allowed only for registers.
5508 Operands 1 and 2 must be valid for @code{word_mode}.
5510 The RTL generation pass generates this instruction only with constants
5511 for operands 1 and 2 and the constant is never zero for operand 1.
5513 This pattern is deprecated; please use @samp{insv@var{m}} and
5514 @code{insvmisalign@var{m}} instead.
5516 @cindex @code{mov@var{mode}cc} instruction pattern
5517 @item @samp{mov@var{mode}cc}
5518 Conditionally move operand 2 or operand 3 into operand 0 according to the
5519 comparison in operand 1. If the comparison is true, operand 2 is moved
5520 into operand 0, otherwise operand 3 is moved.
5522 The mode of the operands being compared need not be the same as the operands
5523 being moved. Some machines, sparc64 for example, have instructions that
5524 conditionally move an integer value based on the floating point condition
5525 codes and vice versa.
5527 If the machine does not have conditional move instructions, do not
5528 define these patterns.
5530 @cindex @code{add@var{mode}cc} instruction pattern
5531 @item @samp{add@var{mode}cc}
5532 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
5533 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
5534 comparison in operand 1. If the comparison is false, operand 2 is moved into
5535 operand 0, otherwise (operand 2 + operand 3) is moved.
5537 @cindex @code{cstore@var{mode}4} instruction pattern
5538 @item @samp{cstore@var{mode}4}
5539 Store zero or nonzero in operand 0 according to whether a comparison
5540 is true. Operand 1 is a comparison operator. Operand 2 and operand 3
5541 are the first and second operand of the comparison, respectively.
5542 You specify the mode that operand 0 must have when you write the
5543 @code{match_operand} expression. The compiler automatically sees which
5544 mode you have used and supplies an operand of that mode.
5546 The value stored for a true condition must have 1 as its low bit, or
5547 else must be negative. Otherwise the instruction is not suitable and
5548 you should omit it from the machine description. You describe to the
5549 compiler exactly which value is stored by defining the macro
5550 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
5551 found that can be used for all the possible comparison operators, you
5552 should pick one and use a @code{define_expand} to map all results
5553 onto the one you chose.
5555 These operations may @code{FAIL}, but should do so only in relatively
5556 uncommon cases; if they would @code{FAIL} for common cases involving
5557 integer comparisons, it is best to restrict the predicates to not
5558 allow these operands. Likewise if a given comparison operator will
5559 always fail, independent of the operands (for floating-point modes, the
5560 @code{ordered_comparison_operator} predicate is often useful in this case).
5562 If this pattern is omitted, the compiler will generate a conditional
5563 branch---for example, it may copy a constant one to the target and branching
5564 around an assignment of zero to the target---or a libcall. If the predicate
5565 for operand 1 only rejects some operators, it will also try reordering the
5566 operands and/or inverting the result value (e.g.@: by an exclusive OR).
5567 These possibilities could be cheaper or equivalent to the instructions
5568 used for the @samp{cstore@var{mode}4} pattern followed by those required
5569 to convert a positive result from @code{STORE_FLAG_VALUE} to 1; in this
5570 case, you can and should make operand 1's predicate reject some operators
5571 in the @samp{cstore@var{mode}4} pattern, or remove the pattern altogether
5572 from the machine description.
5574 @cindex @code{cbranch@var{mode}4} instruction pattern
5575 @item @samp{cbranch@var{mode}4}
5576 Conditional branch instruction combined with a compare instruction.
5577 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
5578 first and second operands of the comparison, respectively. Operand 3
5579 is a @code{label_ref} that refers to the label to jump to.
5581 @cindex @code{jump} instruction pattern
5583 A jump inside a function; an unconditional branch. Operand 0 is the
5584 @code{label_ref} of the label to jump to. This pattern name is mandatory
5587 @cindex @code{call} instruction pattern
5589 Subroutine call instruction returning no value. Operand 0 is the
5590 function to call; operand 1 is the number of bytes of arguments pushed
5591 as a @code{const_int}; operand 2 is the number of registers used as
5594 On most machines, operand 2 is not actually stored into the RTL
5595 pattern. It is supplied for the sake of some RISC machines which need
5596 to put this information into the assembler code; they can put it in
5597 the RTL instead of operand 1.
5599 Operand 0 should be a @code{mem} RTX whose address is the address of the
5600 function. Note, however, that this address can be a @code{symbol_ref}
5601 expression even if it would not be a legitimate memory address on the
5602 target machine. If it is also not a valid argument for a call
5603 instruction, the pattern for this operation should be a
5604 @code{define_expand} (@pxref{Expander Definitions}) that places the
5605 address into a register and uses that register in the call instruction.
5607 @cindex @code{call_value} instruction pattern
5608 @item @samp{call_value}
5609 Subroutine call instruction returning a value. Operand 0 is the hard
5610 register in which the value is returned. There are three more
5611 operands, the same as the three operands of the @samp{call}
5612 instruction (but with numbers increased by one).
5614 Subroutines that return @code{BLKmode} objects use the @samp{call}
5617 @cindex @code{call_pop} instruction pattern
5618 @cindex @code{call_value_pop} instruction pattern
5619 @item @samp{call_pop}, @samp{call_value_pop}
5620 Similar to @samp{call} and @samp{call_value}, except used if defined and
5621 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
5622 that contains both the function call and a @code{set} to indicate the
5623 adjustment made to the frame pointer.
5625 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
5626 patterns increases the number of functions for which the frame pointer
5627 can be eliminated, if desired.
5629 @cindex @code{untyped_call} instruction pattern
5630 @item @samp{untyped_call}
5631 Subroutine call instruction returning a value of any type. Operand 0 is
5632 the function to call; operand 1 is a memory location where the result of
5633 calling the function is to be stored; operand 2 is a @code{parallel}
5634 expression where each element is a @code{set} expression that indicates
5635 the saving of a function return value into the result block.
5637 This instruction pattern should be defined to support
5638 @code{__builtin_apply} on machines where special instructions are needed
5639 to call a subroutine with arbitrary arguments or to save the value
5640 returned. This instruction pattern is required on machines that have
5641 multiple registers that can hold a return value
5642 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
5644 @cindex @code{return} instruction pattern
5646 Subroutine return instruction. This instruction pattern name should be
5647 defined only if a single instruction can do all the work of returning
5650 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
5651 RTL generation phase. In this case it is to support machines where
5652 multiple instructions are usually needed to return from a function, but
5653 some class of functions only requires one instruction to implement a
5654 return. Normally, the applicable functions are those which do not need
5655 to save any registers or allocate stack space.
5657 It is valid for this pattern to expand to an instruction using
5658 @code{simple_return} if no epilogue is required.
5660 @cindex @code{simple_return} instruction pattern
5661 @item @samp{simple_return}
5662 Subroutine return instruction. This instruction pattern name should be
5663 defined only if a single instruction can do all the work of returning
5664 from a function on a path where no epilogue is required. This pattern
5665 is very similar to the @code{return} instruction pattern, but it is emitted
5666 only by the shrink-wrapping optimization on paths where the function
5667 prologue has not been executed, and a function return should occur without
5668 any of the effects of the epilogue. Additional uses may be introduced on
5669 paths where both the prologue and the epilogue have executed.
5671 @findex reload_completed
5672 @findex leaf_function_p
5673 For such machines, the condition specified in this pattern should only
5674 be true when @code{reload_completed} is nonzero and the function's
5675 epilogue would only be a single instruction. For machines with register
5676 windows, the routine @code{leaf_function_p} may be used to determine if
5677 a register window push is required.
5679 Machines that have conditional return instructions should define patterns
5685 (if_then_else (match_operator
5686 0 "comparison_operator"
5687 [(cc0) (const_int 0)])
5694 where @var{condition} would normally be the same condition specified on the
5695 named @samp{return} pattern.
5697 @cindex @code{untyped_return} instruction pattern
5698 @item @samp{untyped_return}
5699 Untyped subroutine return instruction. This instruction pattern should
5700 be defined to support @code{__builtin_return} on machines where special
5701 instructions are needed to return a value of any type.
5703 Operand 0 is a memory location where the result of calling a function
5704 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
5705 expression where each element is a @code{set} expression that indicates
5706 the restoring of a function return value from the result block.
5708 @cindex @code{nop} instruction pattern
5710 No-op instruction. This instruction pattern name should always be defined
5711 to output a no-op in assembler code. @code{(const_int 0)} will do as an
5714 @cindex @code{indirect_jump} instruction pattern
5715 @item @samp{indirect_jump}
5716 An instruction to jump to an address which is operand zero.
5717 This pattern name is mandatory on all machines.
5719 @cindex @code{casesi} instruction pattern
5721 Instruction to jump through a dispatch table, including bounds checking.
5722 This instruction takes five operands:
5726 The index to dispatch on, which has mode @code{SImode}.
5729 The lower bound for indices in the table, an integer constant.
5732 The total range of indices in the table---the largest index
5733 minus the smallest one (both inclusive).
5736 A label that precedes the table itself.
5739 A label to jump to if the index has a value outside the bounds.
5742 The table is an @code{addr_vec} or @code{addr_diff_vec} inside of a
5743 @code{jump_table_data}. The number of elements in the table is one plus the
5744 difference between the upper bound and the lower bound.
5746 @cindex @code{tablejump} instruction pattern
5747 @item @samp{tablejump}
5748 Instruction to jump to a variable address. This is a low-level
5749 capability which can be used to implement a dispatch table when there
5750 is no @samp{casesi} pattern.
5752 This pattern requires two operands: the address or offset, and a label
5753 which should immediately precede the jump table. If the macro
5754 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
5755 operand is an offset which counts from the address of the table; otherwise,
5756 it is an absolute address to jump to. In either case, the first operand has
5759 The @samp{tablejump} insn is always the last insn before the jump
5760 table it uses. Its assembler code normally has no need to use the
5761 second operand, but you should incorporate it in the RTL pattern so
5762 that the jump optimizer will not delete the table as unreachable code.
5765 @cindex @code{decrement_and_branch_until_zero} instruction pattern
5766 @item @samp{decrement_and_branch_until_zero}
5767 Conditional branch instruction that decrements a register and
5768 jumps if the register is nonzero. Operand 0 is the register to
5769 decrement and test; operand 1 is the label to jump to if the
5770 register is nonzero. @xref{Looping Patterns}.
5772 This optional instruction pattern is only used by the combiner,
5773 typically for loops reversed by the loop optimizer when strength
5774 reduction is enabled.
5776 @cindex @code{doloop_end} instruction pattern
5777 @item @samp{doloop_end}
5778 Conditional branch instruction that decrements a register and jumps if
5779 the register is nonzero. This instruction takes five operands: Operand
5780 0 is the register to decrement and test; operand 1 is the number of loop
5781 iterations as a @code{const_int} or @code{const0_rtx} if this cannot be
5782 determined until run-time; operand 2 is the actual or estimated maximum
5783 number of iterations as a @code{const_int}; operand 3 is the number of
5784 enclosed loops as a @code{const_int} (an innermost loop has a value of
5785 1); operand 4 is the label to jump to if the register is nonzero;
5786 operand 5 is const1_rtx if the loop in entered at its top, const0_rtx
5788 @xref{Looping Patterns}.
5790 This optional instruction pattern should be defined for machines with
5791 low-overhead looping instructions as the loop optimizer will try to
5792 modify suitable loops to utilize it. If nested low-overhead looping is
5793 not supported, use a @code{define_expand} (@pxref{Expander Definitions})
5794 and make the pattern fail if operand 3 is not @code{const1_rtx}.
5795 Similarly, if the actual or estimated maximum number of iterations is
5796 too large for this instruction, make it fail.
5798 @cindex @code{doloop_begin} instruction pattern
5799 @item @samp{doloop_begin}
5800 Companion instruction to @code{doloop_end} required for machines that
5801 need to perform some initialization, such as loading special registers
5802 used by a low-overhead looping instruction. If initialization insns do
5803 not always need to be emitted, use a @code{define_expand}
5804 (@pxref{Expander Definitions}) and make it fail.
5807 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
5808 @item @samp{canonicalize_funcptr_for_compare}
5809 Canonicalize the function pointer in operand 1 and store the result
5812 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
5813 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
5814 and also has mode @code{Pmode}.
5816 Canonicalization of a function pointer usually involves computing
5817 the address of the function which would be called if the function
5818 pointer were used in an indirect call.
5820 Only define this pattern if function pointers on the target machine
5821 can have different values but still call the same function when
5822 used in an indirect call.
5824 @cindex @code{save_stack_block} instruction pattern
5825 @cindex @code{save_stack_function} instruction pattern
5826 @cindex @code{save_stack_nonlocal} instruction pattern
5827 @cindex @code{restore_stack_block} instruction pattern
5828 @cindex @code{restore_stack_function} instruction pattern
5829 @cindex @code{restore_stack_nonlocal} instruction pattern
5830 @item @samp{save_stack_block}
5831 @itemx @samp{save_stack_function}
5832 @itemx @samp{save_stack_nonlocal}
5833 @itemx @samp{restore_stack_block}
5834 @itemx @samp{restore_stack_function}
5835 @itemx @samp{restore_stack_nonlocal}
5836 Most machines save and restore the stack pointer by copying it to or
5837 from an object of mode @code{Pmode}. Do not define these patterns on
5840 Some machines require special handling for stack pointer saves and
5841 restores. On those machines, define the patterns corresponding to the
5842 non-standard cases by using a @code{define_expand} (@pxref{Expander
5843 Definitions}) that produces the required insns. The three types of
5844 saves and restores are:
5848 @samp{save_stack_block} saves the stack pointer at the start of a block
5849 that allocates a variable-sized object, and @samp{restore_stack_block}
5850 restores the stack pointer when the block is exited.
5853 @samp{save_stack_function} and @samp{restore_stack_function} do a
5854 similar job for the outermost block of a function and are used when the
5855 function allocates variable-sized objects or calls @code{alloca}. Only
5856 the epilogue uses the restored stack pointer, allowing a simpler save or
5857 restore sequence on some machines.
5860 @samp{save_stack_nonlocal} is used in functions that contain labels
5861 branched to by nested functions. It saves the stack pointer in such a
5862 way that the inner function can use @samp{restore_stack_nonlocal} to
5863 restore the stack pointer. The compiler generates code to restore the
5864 frame and argument pointer registers, but some machines require saving
5865 and restoring additional data such as register window information or
5866 stack backchains. Place insns in these patterns to save and restore any
5870 When saving the stack pointer, operand 0 is the save area and operand 1
5871 is the stack pointer. The mode used to allocate the save area defaults
5872 to @code{Pmode} but you can override that choice by defining the
5873 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
5874 specify an integral mode, or @code{VOIDmode} if no save area is needed
5875 for a particular type of save (either because no save is needed or
5876 because a machine-specific save area can be used). Operand 0 is the
5877 stack pointer and operand 1 is the save area for restore operations. If
5878 @samp{save_stack_block} is defined, operand 0 must not be
5879 @code{VOIDmode} since these saves can be arbitrarily nested.
5881 A save area is a @code{mem} that is at a constant offset from
5882 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
5883 nonlocal gotos and a @code{reg} in the other two cases.
5885 @cindex @code{allocate_stack} instruction pattern
5886 @item @samp{allocate_stack}
5887 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
5888 the stack pointer to create space for dynamically allocated data.
5890 Store the resultant pointer to this space into operand 0. If you
5891 are allocating space from the main stack, do this by emitting a
5892 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
5893 If you are allocating the space elsewhere, generate code to copy the
5894 location of the space to operand 0. In the latter case, you must
5895 ensure this space gets freed when the corresponding space on the main
5898 Do not define this pattern if all that must be done is the subtraction.
5899 Some machines require other operations such as stack probes or
5900 maintaining the back chain. Define this pattern to emit those
5901 operations in addition to updating the stack pointer.
5903 @cindex @code{check_stack} instruction pattern
5904 @item @samp{check_stack}
5905 If stack checking (@pxref{Stack Checking}) cannot be done on your system by
5906 probing the stack, define this pattern to perform the needed check and signal
5907 an error if the stack has overflowed. The single operand is the address in
5908 the stack farthest from the current stack pointer that you need to validate.
5909 Normally, on platforms where this pattern is needed, you would obtain the
5910 stack limit from a global or thread-specific variable or register.
5912 @cindex @code{probe_stack_address} instruction pattern
5913 @item @samp{probe_stack_address}
5914 If stack checking (@pxref{Stack Checking}) can be done on your system by
5915 probing the stack but without the need to actually access it, define this
5916 pattern and signal an error if the stack has overflowed. The single operand
5917 is the memory address in the stack that needs to be probed.
5919 @cindex @code{probe_stack} instruction pattern
5920 @item @samp{probe_stack}
5921 If stack checking (@pxref{Stack Checking}) can be done on your system by
5922 probing the stack but doing it with a ``store zero'' instruction is not valid
5923 or optimal, define this pattern to do the probing differently and signal an
5924 error if the stack has overflowed. The single operand is the memory reference
5925 in the stack that needs to be probed.
5927 @cindex @code{nonlocal_goto} instruction pattern
5928 @item @samp{nonlocal_goto}
5929 Emit code to generate a non-local goto, e.g., a jump from one function
5930 to a label in an outer function. This pattern has four arguments,
5931 each representing a value to be used in the jump. The first
5932 argument is to be loaded into the frame pointer, the second is
5933 the address to branch to (code to dispatch to the actual label),
5934 the third is the address of a location where the stack is saved,
5935 and the last is the address of the label, to be placed in the
5936 location for the incoming static chain.
5938 On most machines you need not define this pattern, since GCC will
5939 already generate the correct code, which is to load the frame pointer
5940 and static chain, restore the stack (using the
5941 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
5942 to the dispatcher. You need only define this pattern if this code will
5943 not work on your machine.
5945 @cindex @code{nonlocal_goto_receiver} instruction pattern
5946 @item @samp{nonlocal_goto_receiver}
5947 This pattern, if defined, contains code needed at the target of a
5948 nonlocal goto after the code already generated by GCC@. You will not
5949 normally need to define this pattern. A typical reason why you might
5950 need this pattern is if some value, such as a pointer to a global table,
5951 must be restored when the frame pointer is restored. Note that a nonlocal
5952 goto only occurs within a unit-of-translation, so a global table pointer
5953 that is shared by all functions of a given module need not be restored.
5954 There are no arguments.
5956 @cindex @code{exception_receiver} instruction pattern
5957 @item @samp{exception_receiver}
5958 This pattern, if defined, contains code needed at the site of an
5959 exception handler that isn't needed at the site of a nonlocal goto. You
5960 will not normally need to define this pattern. A typical reason why you
5961 might need this pattern is if some value, such as a pointer to a global
5962 table, must be restored after control flow is branched to the handler of
5963 an exception. There are no arguments.
5965 @cindex @code{builtin_setjmp_setup} instruction pattern
5966 @item @samp{builtin_setjmp_setup}
5967 This pattern, if defined, contains additional code needed to initialize
5968 the @code{jmp_buf}. You will not normally need to define this pattern.
5969 A typical reason why you might need this pattern is if some value, such
5970 as a pointer to a global table, must be restored. Though it is
5971 preferred that the pointer value be recalculated if possible (given the
5972 address of a label for instance). The single argument is a pointer to
5973 the @code{jmp_buf}. Note that the buffer is five words long and that
5974 the first three are normally used by the generic mechanism.
5976 @cindex @code{builtin_setjmp_receiver} instruction pattern
5977 @item @samp{builtin_setjmp_receiver}
5978 This pattern, if defined, contains code needed at the site of a
5979 built-in setjmp that isn't needed at the site of a nonlocal goto. You
5980 will not normally need to define this pattern. A typical reason why you
5981 might need this pattern is if some value, such as a pointer to a global
5982 table, must be restored. It takes one argument, which is the label
5983 to which builtin_longjmp transferred control; this pattern may be emitted
5984 at a small offset from that label.
5986 @cindex @code{builtin_longjmp} instruction pattern
5987 @item @samp{builtin_longjmp}
5988 This pattern, if defined, performs the entire action of the longjmp.
5989 You will not normally need to define this pattern unless you also define
5990 @code{builtin_setjmp_setup}. The single argument is a pointer to the
5993 @cindex @code{eh_return} instruction pattern
5994 @item @samp{eh_return}
5995 This pattern, if defined, affects the way @code{__builtin_eh_return},
5996 and thence the call frame exception handling library routines, are
5997 built. It is intended to handle non-trivial actions needed along
5998 the abnormal return path.
6000 The address of the exception handler to which the function should return
6001 is passed as operand to this pattern. It will normally need to copied by
6002 the pattern to some special register or memory location.
6003 If the pattern needs to determine the location of the target call
6004 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
6005 if defined; it will have already been assigned.
6007 If this pattern is not defined, the default action will be to simply
6008 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
6009 that macro or this pattern needs to be defined if call frame exception
6010 handling is to be used.
6012 @cindex @code{prologue} instruction pattern
6013 @anchor{prologue instruction pattern}
6014 @item @samp{prologue}
6015 This pattern, if defined, emits RTL for entry to a function. The function
6016 entry is responsible for setting up the stack frame, initializing the frame
6017 pointer register, saving callee saved registers, etc.
6019 Using a prologue pattern is generally preferred over defining
6020 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
6022 The @code{prologue} pattern is particularly useful for targets which perform
6023 instruction scheduling.
6025 @cindex @code{window_save} instruction pattern
6026 @anchor{window_save instruction pattern}
6027 @item @samp{window_save}
6028 This pattern, if defined, emits RTL for a register window save. It should
6029 be defined if the target machine has register windows but the window events
6030 are decoupled from calls to subroutines. The canonical example is the SPARC
6033 @cindex @code{epilogue} instruction pattern
6034 @anchor{epilogue instruction pattern}
6035 @item @samp{epilogue}
6036 This pattern emits RTL for exit from a function. The function
6037 exit is responsible for deallocating the stack frame, restoring callee saved
6038 registers and emitting the return instruction.
6040 Using an epilogue pattern is generally preferred over defining
6041 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
6043 The @code{epilogue} pattern is particularly useful for targets which perform
6044 instruction scheduling or which have delay slots for their return instruction.
6046 @cindex @code{sibcall_epilogue} instruction pattern
6047 @item @samp{sibcall_epilogue}
6048 This pattern, if defined, emits RTL for exit from a function without the final
6049 branch back to the calling function. This pattern will be emitted before any
6050 sibling call (aka tail call) sites.
6052 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
6053 parameter passing or any stack slots for arguments passed to the current
6056 @cindex @code{trap} instruction pattern
6058 This pattern, if defined, signals an error, typically by causing some
6059 kind of signal to be raised. Among other places, it is used by the Java
6060 front end to signal `invalid array index' exceptions.
6062 @cindex @code{ctrap@var{MM}4} instruction pattern
6063 @item @samp{ctrap@var{MM}4}
6064 Conditional trap instruction. Operand 0 is a piece of RTL which
6065 performs a comparison, and operands 1 and 2 are the arms of the
6066 comparison. Operand 3 is the trap code, an integer.
6068 A typical @code{ctrap} pattern looks like
6071 (define_insn "ctrapsi4"
6072 [(trap_if (match_operator 0 "trap_operator"
6073 [(match_operand 1 "register_operand")
6074 (match_operand 2 "immediate_operand")])
6075 (match_operand 3 "const_int_operand" "i"))]
6080 @cindex @code{prefetch} instruction pattern
6081 @item @samp{prefetch}
6083 This pattern, if defined, emits code for a non-faulting data prefetch
6084 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
6085 is a constant 1 if the prefetch is preparing for a write to the memory
6086 address, or a constant 0 otherwise. Operand 2 is the expected degree of
6087 temporal locality of the data and is a value between 0 and 3, inclusive; 0
6088 means that the data has no temporal locality, so it need not be left in the
6089 cache after the access; 3 means that the data has a high degree of temporal
6090 locality and should be left in all levels of cache possible; 1 and 2 mean,
6091 respectively, a low or moderate degree of temporal locality.
6093 Targets that do not support write prefetches or locality hints can ignore
6094 the values of operands 1 and 2.
6096 @cindex @code{blockage} instruction pattern
6097 @item @samp{blockage}
6099 This pattern defines a pseudo insn that prevents the instruction
6100 scheduler and other passes from moving instructions and using register
6101 equivalences across the boundary defined by the blockage insn.
6102 This needs to be an UNSPEC_VOLATILE pattern or a volatile ASM.
6104 @cindex @code{memory_barrier} instruction pattern
6105 @item @samp{memory_barrier}
6107 If the target memory model is not fully synchronous, then this pattern
6108 should be defined to an instruction that orders both loads and stores
6109 before the instruction with respect to loads and stores after the instruction.
6110 This pattern has no operands.
6112 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
6113 @item @samp{sync_compare_and_swap@var{mode}}
6115 This pattern, if defined, emits code for an atomic compare-and-swap
6116 operation. Operand 1 is the memory on which the atomic operation is
6117 performed. Operand 2 is the ``old'' value to be compared against the
6118 current contents of the memory location. Operand 3 is the ``new'' value
6119 to store in the memory if the compare succeeds. Operand 0 is the result
6120 of the operation; it should contain the contents of the memory
6121 before the operation. If the compare succeeds, this should obviously be
6122 a copy of operand 2.
6124 This pattern must show that both operand 0 and operand 1 are modified.
6126 This pattern must issue any memory barrier instructions such that all
6127 memory operations before the atomic operation occur before the atomic
6128 operation and all memory operations after the atomic operation occur
6129 after the atomic operation.
6131 For targets where the success or failure of the compare-and-swap
6132 operation is available via the status flags, it is possible to
6133 avoid a separate compare operation and issue the subsequent
6134 branch or store-flag operation immediately after the compare-and-swap.
6135 To this end, GCC will look for a @code{MODE_CC} set in the
6136 output of @code{sync_compare_and_swap@var{mode}}; if the machine
6137 description includes such a set, the target should also define special
6138 @code{cbranchcc4} and/or @code{cstorecc4} instructions. GCC will then
6139 be able to take the destination of the @code{MODE_CC} set and pass it
6140 to the @code{cbranchcc4} or @code{cstorecc4} pattern as the first
6141 operand of the comparison (the second will be @code{(const_int 0)}).
6143 For targets where the operating system may provide support for this
6144 operation via library calls, the @code{sync_compare_and_swap_optab}
6145 may be initialized to a function with the same interface as the
6146 @code{__sync_val_compare_and_swap_@var{n}} built-in. If the entire
6147 set of @var{__sync} builtins are supported via library calls, the
6148 target can initialize all of the optabs at once with
6149 @code{init_sync_libfuncs}.
6150 For the purposes of C++11 @code{std::atomic::is_lock_free}, it is
6151 assumed that these library calls do @emph{not} use any kind of
6152 interruptable locking.
6154 @cindex @code{sync_add@var{mode}} instruction pattern
6155 @cindex @code{sync_sub@var{mode}} instruction pattern
6156 @cindex @code{sync_ior@var{mode}} instruction pattern
6157 @cindex @code{sync_and@var{mode}} instruction pattern
6158 @cindex @code{sync_xor@var{mode}} instruction pattern
6159 @cindex @code{sync_nand@var{mode}} instruction pattern
6160 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
6161 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
6162 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
6164 These patterns emit code for an atomic operation on memory.
6165 Operand 0 is the memory on which the atomic operation is performed.
6166 Operand 1 is the second operand to the binary operator.
6168 This pattern must issue any memory barrier instructions such that all
6169 memory operations before the atomic operation occur before the atomic
6170 operation and all memory operations after the atomic operation occur
6171 after the atomic operation.
6173 If these patterns are not defined, the operation will be constructed
6174 from a compare-and-swap operation, if defined.
6176 @cindex @code{sync_old_add@var{mode}} instruction pattern
6177 @cindex @code{sync_old_sub@var{mode}} instruction pattern
6178 @cindex @code{sync_old_ior@var{mode}} instruction pattern
6179 @cindex @code{sync_old_and@var{mode}} instruction pattern
6180 @cindex @code{sync_old_xor@var{mode}} instruction pattern
6181 @cindex @code{sync_old_nand@var{mode}} instruction pattern
6182 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
6183 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
6184 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
6186 These patterns emit code for an atomic operation on memory,
6187 and return the value that the memory contained before the operation.
6188 Operand 0 is the result value, operand 1 is the memory on which the
6189 atomic operation is performed, and operand 2 is the second operand
6190 to the binary operator.
6192 This pattern must issue any memory barrier instructions such that all
6193 memory operations before the atomic operation occur before the atomic
6194 operation and all memory operations after the atomic operation occur
6195 after the atomic operation.
6197 If these patterns are not defined, the operation will be constructed
6198 from a compare-and-swap operation, if defined.
6200 @cindex @code{sync_new_add@var{mode}} instruction pattern
6201 @cindex @code{sync_new_sub@var{mode}} instruction pattern
6202 @cindex @code{sync_new_ior@var{mode}} instruction pattern
6203 @cindex @code{sync_new_and@var{mode}} instruction pattern
6204 @cindex @code{sync_new_xor@var{mode}} instruction pattern
6205 @cindex @code{sync_new_nand@var{mode}} instruction pattern
6206 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
6207 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
6208 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
6210 These patterns are like their @code{sync_old_@var{op}} counterparts,
6211 except that they return the value that exists in the memory location
6212 after the operation, rather than before the operation.
6214 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
6215 @item @samp{sync_lock_test_and_set@var{mode}}
6217 This pattern takes two forms, based on the capabilities of the target.
6218 In either case, operand 0 is the result of the operand, operand 1 is
6219 the memory on which the atomic operation is performed, and operand 2
6220 is the value to set in the lock.
6222 In the ideal case, this operation is an atomic exchange operation, in
6223 which the previous value in memory operand is copied into the result
6224 operand, and the value operand is stored in the memory operand.
6226 For less capable targets, any value operand that is not the constant 1
6227 should be rejected with @code{FAIL}. In this case the target may use
6228 an atomic test-and-set bit operation. The result operand should contain
6229 1 if the bit was previously set and 0 if the bit was previously clear.
6230 The true contents of the memory operand are implementation defined.
6232 This pattern must issue any memory barrier instructions such that the
6233 pattern as a whole acts as an acquire barrier, that is all memory
6234 operations after the pattern do not occur until the lock is acquired.
6236 If this pattern is not defined, the operation will be constructed from
6237 a compare-and-swap operation, if defined.
6239 @cindex @code{sync_lock_release@var{mode}} instruction pattern
6240 @item @samp{sync_lock_release@var{mode}}
6242 This pattern, if defined, releases a lock set by
6243 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
6244 that contains the lock; operand 1 is the value to store in the lock.
6246 If the target doesn't implement full semantics for
6247 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
6248 the constant 0 should be rejected with @code{FAIL}, and the true contents
6249 of the memory operand are implementation defined.
6251 This pattern must issue any memory barrier instructions such that the
6252 pattern as a whole acts as a release barrier, that is the lock is
6253 released only after all previous memory operations have completed.
6255 If this pattern is not defined, then a @code{memory_barrier} pattern
6256 will be emitted, followed by a store of the value to the memory operand.
6258 @cindex @code{atomic_compare_and_swap@var{mode}} instruction pattern
6259 @item @samp{atomic_compare_and_swap@var{mode}}
6260 This pattern, if defined, emits code for an atomic compare-and-swap
6261 operation with memory model semantics. Operand 2 is the memory on which
6262 the atomic operation is performed. Operand 0 is an output operand which
6263 is set to true or false based on whether the operation succeeded. Operand
6264 1 is an output operand which is set to the contents of the memory before
6265 the operation was attempted. Operand 3 is the value that is expected to
6266 be in memory. Operand 4 is the value to put in memory if the expected
6267 value is found there. Operand 5 is set to 1 if this compare and swap is to
6268 be treated as a weak operation. Operand 6 is the memory model to be used
6269 if the operation is a success. Operand 7 is the memory model to be used
6270 if the operation fails.
6272 If memory referred to in operand 2 contains the value in operand 3, then
6273 operand 4 is stored in memory pointed to by operand 2 and fencing based on
6274 the memory model in operand 6 is issued.
6276 If memory referred to in operand 2 does not contain the value in operand 3,
6277 then fencing based on the memory model in operand 7 is issued.
6279 If a target does not support weak compare-and-swap operations, or the port
6280 elects not to implement weak operations, the argument in operand 5 can be
6281 ignored. Note a strong implementation must be provided.
6283 If this pattern is not provided, the @code{__atomic_compare_exchange}
6284 built-in functions will utilize the legacy @code{sync_compare_and_swap}
6285 pattern with an @code{__ATOMIC_SEQ_CST} memory model.
6287 @cindex @code{atomic_load@var{mode}} instruction pattern
6288 @item @samp{atomic_load@var{mode}}
6289 This pattern implements an atomic load operation with memory model
6290 semantics. Operand 1 is the memory address being loaded from. Operand 0
6291 is the result of the load. Operand 2 is the memory model to be used for
6294 If not present, the @code{__atomic_load} built-in function will either
6295 resort to a normal load with memory barriers, or a compare-and-swap
6296 operation if a normal load would not be atomic.
6298 @cindex @code{atomic_store@var{mode}} instruction pattern
6299 @item @samp{atomic_store@var{mode}}
6300 This pattern implements an atomic store operation with memory model
6301 semantics. Operand 0 is the memory address being stored to. Operand 1
6302 is the value to be written. Operand 2 is the memory model to be used for
6305 If not present, the @code{__atomic_store} built-in function will attempt to
6306 perform a normal store and surround it with any required memory fences. If
6307 the store would not be atomic, then an @code{__atomic_exchange} is
6308 attempted with the result being ignored.
6310 @cindex @code{atomic_exchange@var{mode}} instruction pattern
6311 @item @samp{atomic_exchange@var{mode}}
6312 This pattern implements an atomic exchange operation with memory model
6313 semantics. Operand 1 is the memory location the operation is performed on.
6314 Operand 0 is an output operand which is set to the original value contained
6315 in the memory pointed to by operand 1. Operand 2 is the value to be
6316 stored. Operand 3 is the memory model to be used.
6318 If this pattern is not present, the built-in function
6319 @code{__atomic_exchange} will attempt to preform the operation with a
6320 compare and swap loop.
6322 @cindex @code{atomic_add@var{mode}} instruction pattern
6323 @cindex @code{atomic_sub@var{mode}} instruction pattern
6324 @cindex @code{atomic_or@var{mode}} instruction pattern
6325 @cindex @code{atomic_and@var{mode}} instruction pattern
6326 @cindex @code{atomic_xor@var{mode}} instruction pattern
6327 @cindex @code{atomic_nand@var{mode}} instruction pattern
6328 @item @samp{atomic_add@var{mode}}, @samp{atomic_sub@var{mode}}
6329 @itemx @samp{atomic_or@var{mode}}, @samp{atomic_and@var{mode}}
6330 @itemx @samp{atomic_xor@var{mode}}, @samp{atomic_nand@var{mode}}
6332 These patterns emit code for an atomic operation on memory with memory
6333 model semantics. Operand 0 is the memory on which the atomic operation is
6334 performed. Operand 1 is the second operand to the binary operator.
6335 Operand 2 is the memory model to be used by the operation.
6337 If these patterns are not defined, attempts will be made to use legacy
6338 @code{sync} patterns, or equivalent patterns which return a result. If
6339 none of these are available a compare-and-swap loop will be used.
6341 @cindex @code{atomic_fetch_add@var{mode}} instruction pattern
6342 @cindex @code{atomic_fetch_sub@var{mode}} instruction pattern
6343 @cindex @code{atomic_fetch_or@var{mode}} instruction pattern
6344 @cindex @code{atomic_fetch_and@var{mode}} instruction pattern
6345 @cindex @code{atomic_fetch_xor@var{mode}} instruction pattern
6346 @cindex @code{atomic_fetch_nand@var{mode}} instruction pattern
6347 @item @samp{atomic_fetch_add@var{mode}}, @samp{atomic_fetch_sub@var{mode}}
6348 @itemx @samp{atomic_fetch_or@var{mode}}, @samp{atomic_fetch_and@var{mode}}
6349 @itemx @samp{atomic_fetch_xor@var{mode}}, @samp{atomic_fetch_nand@var{mode}}
6351 These patterns emit code for an atomic operation on memory with memory
6352 model semantics, and return the original value. Operand 0 is an output
6353 operand which contains the value of the memory location before the
6354 operation was performed. Operand 1 is the memory on which the atomic
6355 operation is performed. Operand 2 is the second operand to the binary
6356 operator. Operand 3 is the memory model to be used by the operation.
6358 If these patterns are not defined, attempts will be made to use legacy
6359 @code{sync} patterns. If none of these are available a compare-and-swap
6362 @cindex @code{atomic_add_fetch@var{mode}} instruction pattern
6363 @cindex @code{atomic_sub_fetch@var{mode}} instruction pattern
6364 @cindex @code{atomic_or_fetch@var{mode}} instruction pattern
6365 @cindex @code{atomic_and_fetch@var{mode}} instruction pattern
6366 @cindex @code{atomic_xor_fetch@var{mode}} instruction pattern
6367 @cindex @code{atomic_nand_fetch@var{mode}} instruction pattern
6368 @item @samp{atomic_add_fetch@var{mode}}, @samp{atomic_sub_fetch@var{mode}}
6369 @itemx @samp{atomic_or_fetch@var{mode}}, @samp{atomic_and_fetch@var{mode}}
6370 @itemx @samp{atomic_xor_fetch@var{mode}}, @samp{atomic_nand_fetch@var{mode}}
6372 These patterns emit code for an atomic operation on memory with memory
6373 model semantics and return the result after the operation is performed.
6374 Operand 0 is an output operand which contains the value after the
6375 operation. Operand 1 is the memory on which the atomic operation is
6376 performed. Operand 2 is the second operand to the binary operator.
6377 Operand 3 is the memory model to be used by the operation.
6379 If these patterns are not defined, attempts will be made to use legacy
6380 @code{sync} patterns, or equivalent patterns which return the result before
6381 the operation followed by the arithmetic operation required to produce the
6382 result. If none of these are available a compare-and-swap loop will be
6385 @cindex @code{atomic_test_and_set} instruction pattern
6386 @item @samp{atomic_test_and_set}
6388 This pattern emits code for @code{__builtin_atomic_test_and_set}.
6389 Operand 0 is an output operand which is set to true if the previous
6390 previous contents of the byte was "set", and false otherwise. Operand 1
6391 is the @code{QImode} memory to be modified. Operand 2 is the memory
6394 The specific value that defines "set" is implementation defined, and
6395 is normally based on what is performed by the native atomic test and set
6398 @cindex @code{mem_thread_fence@var{mode}} instruction pattern
6399 @item @samp{mem_thread_fence@var{mode}}
6400 This pattern emits code required to implement a thread fence with
6401 memory model semantics. Operand 0 is the memory model to be used.
6403 If this pattern is not specified, all memory models except
6404 @code{__ATOMIC_RELAXED} will result in issuing a @code{sync_synchronize}
6407 @cindex @code{mem_signal_fence@var{mode}} instruction pattern
6408 @item @samp{mem_signal_fence@var{mode}}
6409 This pattern emits code required to implement a signal fence with
6410 memory model semantics. Operand 0 is the memory model to be used.
6412 This pattern should impact the compiler optimizers the same way that
6413 mem_signal_fence does, but it does not need to issue any barrier
6416 If this pattern is not specified, all memory models except
6417 @code{__ATOMIC_RELAXED} will result in issuing a @code{sync_synchronize}
6420 @cindex @code{get_thread_pointer@var{mode}} instruction pattern
6421 @cindex @code{set_thread_pointer@var{mode}} instruction pattern
6422 @item @samp{get_thread_pointer@var{mode}}
6423 @itemx @samp{set_thread_pointer@var{mode}}
6424 These patterns emit code that reads/sets the TLS thread pointer. Currently,
6425 these are only needed if the target needs to support the
6426 @code{__builtin_thread_pointer} and @code{__builtin_set_thread_pointer}
6429 The get/set patterns have a single output/input operand respectively,
6430 with @var{mode} intended to be @code{Pmode}.
6432 @cindex @code{stack_protect_set} instruction pattern
6433 @item @samp{stack_protect_set}
6435 This pattern, if defined, moves a @code{ptr_mode} value from the memory
6436 in operand 1 to the memory in operand 0 without leaving the value in
6437 a register afterward. This is to avoid leaking the value some place
6438 that an attacker might use to rewrite the stack guard slot after
6439 having clobbered it.
6441 If this pattern is not defined, then a plain move pattern is generated.
6443 @cindex @code{stack_protect_test} instruction pattern
6444 @item @samp{stack_protect_test}
6446 This pattern, if defined, compares a @code{ptr_mode} value from the
6447 memory in operand 1 with the memory in operand 0 without leaving the
6448 value in a register afterward and branches to operand 2 if the values
6451 If this pattern is not defined, then a plain compare pattern and
6452 conditional branch pattern is used.
6454 @cindex @code{clear_cache} instruction pattern
6455 @item @samp{clear_cache}
6457 This pattern, if defined, flushes the instruction cache for a region of
6458 memory. The region is bounded to by the Pmode pointers in operand 0
6459 inclusive and operand 1 exclusive.
6461 If this pattern is not defined, a call to the library function
6462 @code{__clear_cache} is used.
6467 @c Each of the following nodes are wrapped in separate
6468 @c "@ifset INTERNALS" to work around memory limits for the default
6469 @c configuration in older tetex distributions. Known to not work:
6470 @c tetex-1.0.7, known to work: tetex-2.0.2.
6472 @node Pattern Ordering
6473 @section When the Order of Patterns Matters
6474 @cindex Pattern Ordering
6475 @cindex Ordering of Patterns
6477 Sometimes an insn can match more than one instruction pattern. Then the
6478 pattern that appears first in the machine description is the one used.
6479 Therefore, more specific patterns (patterns that will match fewer things)
6480 and faster instructions (those that will produce better code when they
6481 do match) should usually go first in the description.
6483 In some cases the effect of ordering the patterns can be used to hide
6484 a pattern when it is not valid. For example, the 68000 has an
6485 instruction for converting a fullword to floating point and another
6486 for converting a byte to floating point. An instruction converting
6487 an integer to floating point could match either one. We put the
6488 pattern to convert the fullword first to make sure that one will
6489 be used rather than the other. (Otherwise a large integer might
6490 be generated as a single-byte immediate quantity, which would not work.)
6491 Instead of using this pattern ordering it would be possible to make the
6492 pattern for convert-a-byte smart enough to deal properly with any
6497 @node Dependent Patterns
6498 @section Interdependence of Patterns
6499 @cindex Dependent Patterns
6500 @cindex Interdependence of Patterns
6502 In some cases machines support instructions identical except for the
6503 machine mode of one or more operands. For example, there may be
6504 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
6508 (set (match_operand:SI 0 @dots{})
6509 (extend:SI (match_operand:HI 1 @dots{})))
6511 (set (match_operand:SI 0 @dots{})
6512 (extend:SI (match_operand:QI 1 @dots{})))
6516 Constant integers do not specify a machine mode, so an instruction to
6517 extend a constant value could match either pattern. The pattern it
6518 actually will match is the one that appears first in the file. For correct
6519 results, this must be the one for the widest possible mode (@code{HImode},
6520 here). If the pattern matches the @code{QImode} instruction, the results
6521 will be incorrect if the constant value does not actually fit that mode.
6523 Such instructions to extend constants are rarely generated because they are
6524 optimized away, but they do occasionally happen in nonoptimized
6527 If a constraint in a pattern allows a constant, the reload pass may
6528 replace a register with a constant permitted by the constraint in some
6529 cases. Similarly for memory references. Because of this substitution,
6530 you should not provide separate patterns for increment and decrement
6531 instructions. Instead, they should be generated from the same pattern
6532 that supports register-register add insns by examining the operands and
6533 generating the appropriate machine instruction.
6538 @section Defining Jump Instruction Patterns
6539 @cindex jump instruction patterns
6540 @cindex defining jump instruction patterns
6542 GCC does not assume anything about how the machine realizes jumps.
6543 The machine description should define a single pattern, usually
6544 a @code{define_expand}, which expands to all the required insns.
6546 Usually, this would be a comparison insn to set the condition code
6547 and a separate branch insn testing the condition code and branching
6548 or not according to its value. For many machines, however,
6549 separating compares and branches is limiting, which is why the
6550 more flexible approach with one @code{define_expand} is used in GCC.
6551 The machine description becomes clearer for architectures that
6552 have compare-and-branch instructions but no condition code. It also
6553 works better when different sets of comparison operators are supported
6554 by different kinds of conditional branches (e.g. integer vs. floating-point),
6555 or by conditional branches with respect to conditional stores.
6557 Two separate insns are always used if the machine description represents
6558 a condition code register using the legacy RTL expression @code{(cc0)},
6559 and on most machines that use a separate condition code register
6560 (@pxref{Condition Code}). For machines that use @code{(cc0)}, in
6561 fact, the set and use of the condition code must be separate and
6562 adjacent@footnote{@code{note} insns can separate them, though.}, thus
6563 allowing flags in @code{cc_status} to be used (@pxref{Condition Code}) and
6564 so that the comparison and branch insns could be located from each other
6565 by using the functions @code{prev_cc0_setter} and @code{next_cc0_user}.
6567 Even in this case having a single entry point for conditional branches
6568 is advantageous, because it handles equally well the case where a single
6569 comparison instruction records the results of both signed and unsigned
6570 comparison of the given operands (with the branch insns coming in distinct
6571 signed and unsigned flavors) as in the x86 or SPARC, and the case where
6572 there are distinct signed and unsigned compare instructions and only
6573 one set of conditional branch instructions as in the PowerPC.
6577 @node Looping Patterns
6578 @section Defining Looping Instruction Patterns
6579 @cindex looping instruction patterns
6580 @cindex defining looping instruction patterns
6582 Some machines have special jump instructions that can be utilized to
6583 make loops more efficient. A common example is the 68000 @samp{dbra}
6584 instruction which performs a decrement of a register and a branch if the
6585 result was greater than zero. Other machines, in particular digital
6586 signal processors (DSPs), have special block repeat instructions to
6587 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
6588 DSPs have a block repeat instruction that loads special registers to
6589 mark the top and end of a loop and to count the number of loop
6590 iterations. This avoids the need for fetching and executing a
6591 @samp{dbra}-like instruction and avoids pipeline stalls associated with
6594 GCC has three special named patterns to support low overhead looping.
6595 They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
6596 and @samp{doloop_end}. The first pattern,
6597 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
6598 generation but may be emitted during the instruction combination phase.
6599 This requires the assistance of the loop optimizer, using information
6600 collected during strength reduction, to reverse a loop to count down to
6601 zero. Some targets also require the loop optimizer to add a
6602 @code{REG_NONNEG} note to indicate that the iteration count is always
6603 positive. This is needed if the target performs a signed loop
6604 termination test. For example, the 68000 uses a pattern similar to the
6605 following for its @code{dbra} instruction:
6609 (define_insn "decrement_and_branch_until_zero"
6612 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6615 (label_ref (match_operand 1 "" ""))
6618 (plus:SI (match_dup 0)
6620 "find_reg_note (insn, REG_NONNEG, 0)"
6625 Note that since the insn is both a jump insn and has an output, it must
6626 deal with its own reloads, hence the `m' constraints. Also note that
6627 since this insn is generated by the instruction combination phase
6628 combining two sequential insns together into an implicit parallel insn,
6629 the iteration counter needs to be biased by the same amount as the
6630 decrement operation, in this case @minus{}1. Note that the following similar
6631 pattern will not be matched by the combiner.
6635 (define_insn "decrement_and_branch_until_zero"
6638 (ge (match_operand:SI 0 "general_operand" "+d*am")
6640 (label_ref (match_operand 1 "" ""))
6643 (plus:SI (match_dup 0)
6645 "find_reg_note (insn, REG_NONNEG, 0)"
6650 The other two special looping patterns, @samp{doloop_begin} and
6651 @samp{doloop_end}, are emitted by the loop optimizer for certain
6652 well-behaved loops with a finite number of loop iterations using
6653 information collected during strength reduction.
6655 The @samp{doloop_end} pattern describes the actual looping instruction
6656 (or the implicit looping operation) and the @samp{doloop_begin} pattern
6657 is an optional companion pattern that can be used for initialization
6658 needed for some low-overhead looping instructions.
6660 Note that some machines require the actual looping instruction to be
6661 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
6662 the true RTL for a looping instruction at the top of the loop can cause
6663 problems with flow analysis. So instead, a dummy @code{doloop} insn is
6664 emitted at the end of the loop. The machine dependent reorg pass checks
6665 for the presence of this @code{doloop} insn and then searches back to
6666 the top of the loop, where it inserts the true looping insn (provided
6667 there are no instructions in the loop which would cause problems). Any
6668 additional labels can be emitted at this point. In addition, if the
6669 desired special iteration counter register was not allocated, this
6670 machine dependent reorg pass could emit a traditional compare and jump
6673 The essential difference between the
6674 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
6675 patterns is that the loop optimizer allocates an additional pseudo
6676 register for the latter as an iteration counter. This pseudo register
6677 cannot be used within the loop (i.e., general induction variables cannot
6678 be derived from it), however, in many cases the loop induction variable
6679 may become redundant and removed by the flow pass.
6684 @node Insn Canonicalizations
6685 @section Canonicalization of Instructions
6686 @cindex canonicalization of instructions
6687 @cindex insn canonicalization
6689 There are often cases where multiple RTL expressions could represent an
6690 operation performed by a single machine instruction. This situation is
6691 most commonly encountered with logical, branch, and multiply-accumulate
6692 instructions. In such cases, the compiler attempts to convert these
6693 multiple RTL expressions into a single canonical form to reduce the
6694 number of insn patterns required.
6696 In addition to algebraic simplifications, following canonicalizations
6701 For commutative and comparison operators, a constant is always made the
6702 second operand. If a machine only supports a constant as the second
6703 operand, only patterns that match a constant in the second operand need
6707 For associative operators, a sequence of operators will always chain
6708 to the left; for instance, only the left operand of an integer @code{plus}
6709 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
6710 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
6711 @code{umax} are associative when applied to integers, and sometimes to
6715 @cindex @code{neg}, canonicalization of
6716 @cindex @code{not}, canonicalization of
6717 @cindex @code{mult}, canonicalization of
6718 @cindex @code{plus}, canonicalization of
6719 @cindex @code{minus}, canonicalization of
6720 For these operators, if only one operand is a @code{neg}, @code{not},
6721 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
6725 In combinations of @code{neg}, @code{mult}, @code{plus}, and
6726 @code{minus}, the @code{neg} operations (if any) will be moved inside
6727 the operations as far as possible. For instance,
6728 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
6729 @code{(plus (mult (neg B) C) A)} is canonicalized as
6730 @code{(minus A (mult B C))}.
6732 @cindex @code{compare}, canonicalization of
6734 For the @code{compare} operator, a constant is always the second operand
6735 if the first argument is a condition code register or @code{(cc0)}.
6738 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
6739 @code{minus} is made the first operand under the same conditions as
6743 @code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to
6744 @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead
6748 @code{(minus @var{x} (const_int @var{n}))} is converted to
6749 @code{(plus @var{x} (const_int @var{-n}))}.
6752 Within address computations (i.e., inside @code{mem}), a left shift is
6753 converted into the appropriate multiplication by a power of two.
6755 @cindex @code{ior}, canonicalization of
6756 @cindex @code{and}, canonicalization of
6757 @cindex De Morgan's law
6759 De Morgan's Law is used to move bitwise negation inside a bitwise
6760 logical-and or logical-or operation. If this results in only one
6761 operand being a @code{not} expression, it will be the first one.
6763 A machine that has an instruction that performs a bitwise logical-and of one
6764 operand with the bitwise negation of the other should specify the pattern
6765 for that instruction as
6769 [(set (match_operand:@var{m} 0 @dots{})
6770 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
6771 (match_operand:@var{m} 2 @dots{})))]
6777 Similarly, a pattern for a ``NAND'' instruction should be written
6781 [(set (match_operand:@var{m} 0 @dots{})
6782 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
6783 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
6788 In both cases, it is not necessary to include patterns for the many
6789 logically equivalent RTL expressions.
6791 @cindex @code{xor}, canonicalization of
6793 The only possible RTL expressions involving both bitwise exclusive-or
6794 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
6795 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
6798 The sum of three items, one of which is a constant, will only appear in
6802 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
6805 @cindex @code{zero_extract}, canonicalization of
6806 @cindex @code{sign_extract}, canonicalization of
6808 Equality comparisons of a group of bits (usually a single bit) with zero
6809 will be written using @code{zero_extract} rather than the equivalent
6810 @code{and} or @code{sign_extract} operations.
6812 @cindex @code{mult}, canonicalization of
6814 @code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x})
6815 (sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1}
6816 (sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and likewise
6817 for @code{zero_extend}.
6820 @code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2}
6821 @var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted
6822 to @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2}
6823 @var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for
6824 patterns using @code{zero_extend} and @code{lshiftrt}. If the second
6825 operand of @code{mult} is also a shift, then that is extended also.
6826 This transformation is only applied when it can be proven that the
6827 original operation had sufficient precision to prevent overflow.
6831 Further canonicalization rules are defined in the function
6832 @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
6836 @node Expander Definitions
6837 @section Defining RTL Sequences for Code Generation
6838 @cindex expander definitions
6839 @cindex code generation RTL sequences
6840 @cindex defining RTL sequences for code generation
6842 On some target machines, some standard pattern names for RTL generation
6843 cannot be handled with single insn, but a sequence of RTL insns can
6844 represent them. For these target machines, you can write a
6845 @code{define_expand} to specify how to generate the sequence of RTL@.
6847 @findex define_expand
6848 A @code{define_expand} is an RTL expression that looks almost like a
6849 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
6850 only for RTL generation and it can produce more than one RTL insn.
6852 A @code{define_expand} RTX has four operands:
6856 The name. Each @code{define_expand} must have a name, since the only
6857 use for it is to refer to it by name.
6860 The RTL template. This is a vector of RTL expressions representing
6861 a sequence of separate instructions. Unlike @code{define_insn}, there
6862 is no implicit surrounding @code{PARALLEL}.
6865 The condition, a string containing a C expression. This expression is
6866 used to express how the availability of this pattern depends on
6867 subclasses of target machine, selected by command-line options when GCC
6868 is run. This is just like the condition of a @code{define_insn} that
6869 has a standard name. Therefore, the condition (if present) may not
6870 depend on the data in the insn being matched, but only the
6871 target-machine-type flags. The compiler needs to test these conditions
6872 during initialization in order to learn exactly which named instructions
6873 are available in a particular run.
6876 The preparation statements, a string containing zero or more C
6877 statements which are to be executed before RTL code is generated from
6880 Usually these statements prepare temporary registers for use as
6881 internal operands in the RTL template, but they can also generate RTL
6882 insns directly by calling routines such as @code{emit_insn}, etc.
6883 Any such insns precede the ones that come from the RTL template.
6886 Optionally, a vector containing the values of attributes. @xref{Insn
6890 Every RTL insn emitted by a @code{define_expand} must match some
6891 @code{define_insn} in the machine description. Otherwise, the compiler
6892 will crash when trying to generate code for the insn or trying to optimize
6895 The RTL template, in addition to controlling generation of RTL insns,
6896 also describes the operands that need to be specified when this pattern
6897 is used. In particular, it gives a predicate for each operand.
6899 A true operand, which needs to be specified in order to generate RTL from
6900 the pattern, should be described with a @code{match_operand} in its first
6901 occurrence in the RTL template. This enters information on the operand's
6902 predicate into the tables that record such things. GCC uses the
6903 information to preload the operand into a register if that is required for
6904 valid RTL code. If the operand is referred to more than once, subsequent
6905 references should use @code{match_dup}.
6907 The RTL template may also refer to internal ``operands'' which are
6908 temporary registers or labels used only within the sequence made by the
6909 @code{define_expand}. Internal operands are substituted into the RTL
6910 template with @code{match_dup}, never with @code{match_operand}. The
6911 values of the internal operands are not passed in as arguments by the
6912 compiler when it requests use of this pattern. Instead, they are computed
6913 within the pattern, in the preparation statements. These statements
6914 compute the values and store them into the appropriate elements of
6915 @code{operands} so that @code{match_dup} can find them.
6917 There are two special macros defined for use in the preparation statements:
6918 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
6925 Use the @code{DONE} macro to end RTL generation for the pattern. The
6926 only RTL insns resulting from the pattern on this occasion will be
6927 those already emitted by explicit calls to @code{emit_insn} within the
6928 preparation statements; the RTL template will not be generated.
6932 Make the pattern fail on this occasion. When a pattern fails, it means
6933 that the pattern was not truly available. The calling routines in the
6934 compiler will try other strategies for code generation using other patterns.
6936 Failure is currently supported only for binary (addition, multiplication,
6937 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
6941 If the preparation falls through (invokes neither @code{DONE} nor
6942 @code{FAIL}), then the @code{define_expand} acts like a
6943 @code{define_insn} in that the RTL template is used to generate the
6946 The RTL template is not used for matching, only for generating the
6947 initial insn list. If the preparation statement always invokes
6948 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
6949 list of operands, such as this example:
6953 (define_expand "addsi3"
6954 [(match_operand:SI 0 "register_operand" "")
6955 (match_operand:SI 1 "register_operand" "")
6956 (match_operand:SI 2 "register_operand" "")]
6962 handle_add (operands[0], operands[1], operands[2]);
6968 Here is an example, the definition of left-shift for the SPUR chip:
6972 (define_expand "ashlsi3"
6973 [(set (match_operand:SI 0 "register_operand" "")
6977 (match_operand:SI 1 "register_operand" "")
6978 (match_operand:SI 2 "nonmemory_operand" "")))]
6987 if (GET_CODE (operands[2]) != CONST_INT
6988 || (unsigned) INTVAL (operands[2]) > 3)
6995 This example uses @code{define_expand} so that it can generate an RTL insn
6996 for shifting when the shift-count is in the supported range of 0 to 3 but
6997 fail in other cases where machine insns aren't available. When it fails,
6998 the compiler tries another strategy using different patterns (such as, a
7001 If the compiler were able to handle nontrivial condition-strings in
7002 patterns with names, then it would be possible to use a
7003 @code{define_insn} in that case. Here is another case (zero-extension
7004 on the 68000) which makes more use of the power of @code{define_expand}:
7007 (define_expand "zero_extendhisi2"
7008 [(set (match_operand:SI 0 "general_operand" "")
7010 (set (strict_low_part
7014 (match_operand:HI 1 "general_operand" ""))]
7016 "operands[1] = make_safe_from (operands[1], operands[0]);")
7020 @findex make_safe_from
7021 Here two RTL insns are generated, one to clear the entire output operand
7022 and the other to copy the input operand into its low half. This sequence
7023 is incorrect if the input operand refers to [the old value of] the output
7024 operand, so the preparation statement makes sure this isn't so. The
7025 function @code{make_safe_from} copies the @code{operands[1]} into a
7026 temporary register if it refers to @code{operands[0]}. It does this
7027 by emitting another RTL insn.
7029 Finally, a third example shows the use of an internal operand.
7030 Zero-extension on the SPUR chip is done by @code{and}-ing the result
7031 against a halfword mask. But this mask cannot be represented by a
7032 @code{const_int} because the constant value is too large to be legitimate
7033 on this machine. So it must be copied into a register with
7034 @code{force_reg} and then the register used in the @code{and}.
7037 (define_expand "zero_extendhisi2"
7038 [(set (match_operand:SI 0 "register_operand" "")
7040 (match_operand:HI 1 "register_operand" "")
7045 = force_reg (SImode, GEN_INT (65535)); ")
7048 @emph{Note:} If the @code{define_expand} is used to serve a
7049 standard binary or unary arithmetic operation or a bit-field operation,
7050 then the last insn it generates must not be a @code{code_label},
7051 @code{barrier} or @code{note}. It must be an @code{insn},
7052 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
7053 at the end, emit an insn to copy the result of the operation into
7054 itself. Such an insn will generate no code, but it can avoid problems
7059 @node Insn Splitting
7060 @section Defining How to Split Instructions
7061 @cindex insn splitting
7062 @cindex instruction splitting
7063 @cindex splitting instructions
7065 There are two cases where you should specify how to split a pattern
7066 into multiple insns. On machines that have instructions requiring
7067 delay slots (@pxref{Delay Slots}) or that have instructions whose
7068 output is not available for multiple cycles (@pxref{Processor pipeline
7069 description}), the compiler phases that optimize these cases need to
7070 be able to move insns into one-instruction delay slots. However, some
7071 insns may generate more than one machine instruction. These insns
7072 cannot be placed into a delay slot.
7074 Often you can rewrite the single insn as a list of individual insns,
7075 each corresponding to one machine instruction. The disadvantage of
7076 doing so is that it will cause the compilation to be slower and require
7077 more space. If the resulting insns are too complex, it may also
7078 suppress some optimizations. The compiler splits the insn if there is a
7079 reason to believe that it might improve instruction or delay slot
7082 The insn combiner phase also splits putative insns. If three insns are
7083 merged into one insn with a complex expression that cannot be matched by
7084 some @code{define_insn} pattern, the combiner phase attempts to split
7085 the complex pattern into two insns that are recognized. Usually it can
7086 break the complex pattern into two patterns by splitting out some
7087 subexpression. However, in some other cases, such as performing an
7088 addition of a large constant in two insns on a RISC machine, the way to
7089 split the addition into two insns is machine-dependent.
7091 @findex define_split
7092 The @code{define_split} definition tells the compiler how to split a
7093 complex insn into several simpler insns. It looks like this:
7097 [@var{insn-pattern}]
7099 [@var{new-insn-pattern-1}
7100 @var{new-insn-pattern-2}
7102 "@var{preparation-statements}")
7105 @var{insn-pattern} is a pattern that needs to be split and
7106 @var{condition} is the final condition to be tested, as in a
7107 @code{define_insn}. When an insn matching @var{insn-pattern} and
7108 satisfying @var{condition} is found, it is replaced in the insn list
7109 with the insns given by @var{new-insn-pattern-1},
7110 @var{new-insn-pattern-2}, etc.
7112 The @var{preparation-statements} are similar to those statements that
7113 are specified for @code{define_expand} (@pxref{Expander Definitions})
7114 and are executed before the new RTL is generated to prepare for the
7115 generated code or emit some insns whose pattern is not fixed. Unlike
7116 those in @code{define_expand}, however, these statements must not
7117 generate any new pseudo-registers. Once reload has completed, they also
7118 must not allocate any space in the stack frame.
7120 Patterns are matched against @var{insn-pattern} in two different
7121 circumstances. If an insn needs to be split for delay slot scheduling
7122 or insn scheduling, the insn is already known to be valid, which means
7123 that it must have been matched by some @code{define_insn} and, if
7124 @code{reload_completed} is nonzero, is known to satisfy the constraints
7125 of that @code{define_insn}. In that case, the new insn patterns must
7126 also be insns that are matched by some @code{define_insn} and, if
7127 @code{reload_completed} is nonzero, must also satisfy the constraints
7128 of those definitions.
7130 As an example of this usage of @code{define_split}, consider the following
7131 example from @file{a29k.md}, which splits a @code{sign_extend} from
7132 @code{HImode} to @code{SImode} into a pair of shift insns:
7136 [(set (match_operand:SI 0 "gen_reg_operand" "")
7137 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
7140 (ashift:SI (match_dup 1)
7143 (ashiftrt:SI (match_dup 0)
7146 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
7149 When the combiner phase tries to split an insn pattern, it is always the
7150 case that the pattern is @emph{not} matched by any @code{define_insn}.
7151 The combiner pass first tries to split a single @code{set} expression
7152 and then the same @code{set} expression inside a @code{parallel}, but
7153 followed by a @code{clobber} of a pseudo-reg to use as a scratch
7154 register. In these cases, the combiner expects exactly two new insn
7155 patterns to be generated. It will verify that these patterns match some
7156 @code{define_insn} definitions, so you need not do this test in the
7157 @code{define_split} (of course, there is no point in writing a
7158 @code{define_split} that will never produce insns that match).
7160 Here is an example of this use of @code{define_split}, taken from
7165 [(set (match_operand:SI 0 "gen_reg_operand" "")
7166 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
7167 (match_operand:SI 2 "non_add_cint_operand" "")))]
7169 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
7170 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
7173 int low = INTVAL (operands[2]) & 0xffff;
7174 int high = (unsigned) INTVAL (operands[2]) >> 16;
7177 high++, low |= 0xffff0000;
7179 operands[3] = GEN_INT (high << 16);
7180 operands[4] = GEN_INT (low);
7184 Here the predicate @code{non_add_cint_operand} matches any
7185 @code{const_int} that is @emph{not} a valid operand of a single add
7186 insn. The add with the smaller displacement is written so that it
7187 can be substituted into the address of a subsequent operation.
7189 An example that uses a scratch register, from the same file, generates
7190 an equality comparison of a register and a large constant:
7194 [(set (match_operand:CC 0 "cc_reg_operand" "")
7195 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
7196 (match_operand:SI 2 "non_short_cint_operand" "")))
7197 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
7198 "find_single_use (operands[0], insn, 0)
7199 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
7200 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
7201 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
7202 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
7205 /* @r{Get the constant we are comparing against, C, and see what it
7206 looks like sign-extended to 16 bits. Then see what constant
7207 could be XOR'ed with C to get the sign-extended value.} */
7209 int c = INTVAL (operands[2]);
7210 int sextc = (c << 16) >> 16;
7211 int xorv = c ^ sextc;
7213 operands[4] = GEN_INT (xorv);
7214 operands[5] = GEN_INT (sextc);
7218 To avoid confusion, don't write a single @code{define_split} that
7219 accepts some insns that match some @code{define_insn} as well as some
7220 insns that don't. Instead, write two separate @code{define_split}
7221 definitions, one for the insns that are valid and one for the insns that
7224 The splitter is allowed to split jump instructions into sequence of
7225 jumps or create new jumps in while splitting non-jump instructions. As
7226 the central flowgraph and branch prediction information needs to be updated,
7227 several restriction apply.
7229 Splitting of jump instruction into sequence that over by another jump
7230 instruction is always valid, as compiler expect identical behavior of new
7231 jump. When new sequence contains multiple jump instructions or new labels,
7232 more assistance is needed. Splitter is required to create only unconditional
7233 jumps, or simple conditional jump instructions. Additionally it must attach a
7234 @code{REG_BR_PROB} note to each conditional jump. A global variable
7235 @code{split_branch_probability} holds the probability of the original branch in case
7236 it was a simple conditional jump, @minus{}1 otherwise. To simplify
7237 recomputing of edge frequencies, the new sequence is required to have only
7238 forward jumps to the newly created labels.
7240 @findex define_insn_and_split
7241 For the common case where the pattern of a define_split exactly matches the
7242 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
7246 (define_insn_and_split
7247 [@var{insn-pattern}]
7249 "@var{output-template}"
7250 "@var{split-condition}"
7251 [@var{new-insn-pattern-1}
7252 @var{new-insn-pattern-2}
7254 "@var{preparation-statements}"
7255 [@var{insn-attributes}])
7259 @var{insn-pattern}, @var{condition}, @var{output-template}, and
7260 @var{insn-attributes} are used as in @code{define_insn}. The
7261 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
7262 in a @code{define_split}. The @var{split-condition} is also used as in
7263 @code{define_split}, with the additional behavior that if the condition starts
7264 with @samp{&&}, the condition used for the split will be the constructed as a
7265 logical ``and'' of the split condition with the insn condition. For example,
7269 (define_insn_and_split "zero_extendhisi2_and"
7270 [(set (match_operand:SI 0 "register_operand" "=r")
7271 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
7272 (clobber (reg:CC 17))]
7273 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
7275 "&& reload_completed"
7276 [(parallel [(set (match_dup 0)
7277 (and:SI (match_dup 0) (const_int 65535)))
7278 (clobber (reg:CC 17))])]
7280 [(set_attr "type" "alu1")])
7284 In this case, the actual split condition will be
7285 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
7287 The @code{define_insn_and_split} construction provides exactly the same
7288 functionality as two separate @code{define_insn} and @code{define_split}
7289 patterns. It exists for compactness, and as a maintenance tool to prevent
7290 having to ensure the two patterns' templates match.
7294 @node Including Patterns
7295 @section Including Patterns in Machine Descriptions.
7296 @cindex insn includes
7299 The @code{include} pattern tells the compiler tools where to
7300 look for patterns that are in files other than in the file
7301 @file{.md}. This is used only at build time and there is no preprocessing allowed.
7315 (include "filestuff")
7319 Where @var{pathname} is a string that specifies the location of the file,
7320 specifies the include file to be in @file{gcc/config/target/filestuff}. The
7321 directory @file{gcc/config/target} is regarded as the default directory.
7324 Machine descriptions may be split up into smaller more manageable subsections
7325 and placed into subdirectories.
7331 (include "BOGUS/filestuff")
7335 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
7337 Specifying an absolute path for the include file such as;
7340 (include "/u2/BOGUS/filestuff")
7343 is permitted but is not encouraged.
7345 @subsection RTL Generation Tool Options for Directory Search
7346 @cindex directory options .md
7347 @cindex options, directory search
7348 @cindex search options
7350 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
7355 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
7360 Add the directory @var{dir} to the head of the list of directories to be
7361 searched for header files. This can be used to override a system machine definition
7362 file, substituting your own version, since these directories are
7363 searched before the default machine description file directories. If you use more than
7364 one @option{-I} option, the directories are scanned in left-to-right
7365 order; the standard default directory come after.
7370 @node Peephole Definitions
7371 @section Machine-Specific Peephole Optimizers
7372 @cindex peephole optimizer definitions
7373 @cindex defining peephole optimizers
7375 In addition to instruction patterns the @file{md} file may contain
7376 definitions of machine-specific peephole optimizations.
7378 The combiner does not notice certain peephole optimizations when the data
7379 flow in the program does not suggest that it should try them. For example,
7380 sometimes two consecutive insns related in purpose can be combined even
7381 though the second one does not appear to use a register computed in the
7382 first one. A machine-specific peephole optimizer can detect such
7385 There are two forms of peephole definitions that may be used. The
7386 original @code{define_peephole} is run at assembly output time to
7387 match insns and substitute assembly text. Use of @code{define_peephole}
7390 A newer @code{define_peephole2} matches insns and substitutes new
7391 insns. The @code{peephole2} pass is run after register allocation
7392 but before scheduling, which may result in much better code for
7393 targets that do scheduling.
7396 * define_peephole:: RTL to Text Peephole Optimizers
7397 * define_peephole2:: RTL to RTL Peephole Optimizers
7402 @node define_peephole
7403 @subsection RTL to Text Peephole Optimizers
7404 @findex define_peephole
7407 A definition looks like this:
7411 [@var{insn-pattern-1}
7412 @var{insn-pattern-2}
7416 "@var{optional-insn-attributes}")
7420 The last string operand may be omitted if you are not using any
7421 machine-specific information in this machine description. If present,
7422 it must obey the same rules as in a @code{define_insn}.
7424 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
7425 consecutive insns. The optimization applies to a sequence of insns when
7426 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
7427 the next, and so on.
7429 Each of the insns matched by a peephole must also match a
7430 @code{define_insn}. Peepholes are checked only at the last stage just
7431 before code generation, and only optionally. Therefore, any insn which
7432 would match a peephole but no @code{define_insn} will cause a crash in code
7433 generation in an unoptimized compilation, or at various optimization
7436 The operands of the insns are matched with @code{match_operands},
7437 @code{match_operator}, and @code{match_dup}, as usual. What is not
7438 usual is that the operand numbers apply to all the insn patterns in the
7439 definition. So, you can check for identical operands in two insns by
7440 using @code{match_operand} in one insn and @code{match_dup} in the
7443 The operand constraints used in @code{match_operand} patterns do not have
7444 any direct effect on the applicability of the peephole, but they will
7445 be validated afterward, so make sure your constraints are general enough
7446 to apply whenever the peephole matches. If the peephole matches
7447 but the constraints are not satisfied, the compiler will crash.
7449 It is safe to omit constraints in all the operands of the peephole; or
7450 you can write constraints which serve as a double-check on the criteria
7453 Once a sequence of insns matches the patterns, the @var{condition} is
7454 checked. This is a C expression which makes the final decision whether to
7455 perform the optimization (we do so if the expression is nonzero). If
7456 @var{condition} is omitted (in other words, the string is empty) then the
7457 optimization is applied to every sequence of insns that matches the
7460 The defined peephole optimizations are applied after register allocation
7461 is complete. Therefore, the peephole definition can check which
7462 operands have ended up in which kinds of registers, just by looking at
7465 @findex prev_active_insn
7466 The way to refer to the operands in @var{condition} is to write
7467 @code{operands[@var{i}]} for operand number @var{i} (as matched by
7468 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
7469 to refer to the last of the insns being matched; use
7470 @code{prev_active_insn} to find the preceding insns.
7472 @findex dead_or_set_p
7473 When optimizing computations with intermediate results, you can use
7474 @var{condition} to match only when the intermediate results are not used
7475 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
7476 @var{op})}, where @var{insn} is the insn in which you expect the value
7477 to be used for the last time (from the value of @code{insn}, together
7478 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
7479 value (from @code{operands[@var{i}]}).
7481 Applying the optimization means replacing the sequence of insns with one
7482 new insn. The @var{template} controls ultimate output of assembler code
7483 for this combined insn. It works exactly like the template of a
7484 @code{define_insn}. Operand numbers in this template are the same ones
7485 used in matching the original sequence of insns.
7487 The result of a defined peephole optimizer does not need to match any of
7488 the insn patterns in the machine description; it does not even have an
7489 opportunity to match them. The peephole optimizer definition itself serves
7490 as the insn pattern to control how the insn is output.
7492 Defined peephole optimizers are run as assembler code is being output,
7493 so the insns they produce are never combined or rearranged in any way.
7495 Here is an example, taken from the 68000 machine description:
7499 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
7500 (set (match_operand:DF 0 "register_operand" "=f")
7501 (match_operand:DF 1 "register_operand" "ad"))]
7502 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
7505 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7507 output_asm_insn ("move.l %1,(sp)", xoperands);
7508 output_asm_insn ("move.l %1,-(sp)", operands);
7509 return "fmove.d (sp)+,%0";
7511 output_asm_insn ("movel %1,sp@@", xoperands);
7512 output_asm_insn ("movel %1,sp@@-", operands);
7513 return "fmoved sp@@+,%0";
7519 The effect of this optimization is to change
7545 If a peephole matches a sequence including one or more jump insns, you must
7546 take account of the flags such as @code{CC_REVERSED} which specify that the
7547 condition codes are represented in an unusual manner. The compiler
7548 automatically alters any ordinary conditional jumps which occur in such
7549 situations, but the compiler cannot alter jumps which have been replaced by
7550 peephole optimizations. So it is up to you to alter the assembler code
7551 that the peephole produces. Supply C code to write the assembler output,
7552 and in this C code check the condition code status flags and change the
7553 assembler code as appropriate.
7556 @var{insn-pattern-1} and so on look @emph{almost} like the second
7557 operand of @code{define_insn}. There is one important difference: the
7558 second operand of @code{define_insn} consists of one or more RTX's
7559 enclosed in square brackets. Usually, there is only one: then the same
7560 action can be written as an element of a @code{define_peephole}. But
7561 when there are multiple actions in a @code{define_insn}, they are
7562 implicitly enclosed in a @code{parallel}. Then you must explicitly
7563 write the @code{parallel}, and the square brackets within it, in the
7564 @code{define_peephole}. Thus, if an insn pattern looks like this,
7567 (define_insn "divmodsi4"
7568 [(set (match_operand:SI 0 "general_operand" "=d")
7569 (div:SI (match_operand:SI 1 "general_operand" "0")
7570 (match_operand:SI 2 "general_operand" "dmsK")))
7571 (set (match_operand:SI 3 "general_operand" "=d")
7572 (mod:SI (match_dup 1) (match_dup 2)))]
7574 "divsl%.l %2,%3:%0")
7578 then the way to mention this insn in a peephole is as follows:
7584 [(set (match_operand:SI 0 "general_operand" "=d")
7585 (div:SI (match_operand:SI 1 "general_operand" "0")
7586 (match_operand:SI 2 "general_operand" "dmsK")))
7587 (set (match_operand:SI 3 "general_operand" "=d")
7588 (mod:SI (match_dup 1) (match_dup 2)))])
7595 @node define_peephole2
7596 @subsection RTL to RTL Peephole Optimizers
7597 @findex define_peephole2
7599 The @code{define_peephole2} definition tells the compiler how to
7600 substitute one sequence of instructions for another sequence,
7601 what additional scratch registers may be needed and what their
7606 [@var{insn-pattern-1}
7607 @var{insn-pattern-2}
7610 [@var{new-insn-pattern-1}
7611 @var{new-insn-pattern-2}
7613 "@var{preparation-statements}")
7616 The definition is almost identical to @code{define_split}
7617 (@pxref{Insn Splitting}) except that the pattern to match is not a
7618 single instruction, but a sequence of instructions.
7620 It is possible to request additional scratch registers for use in the
7621 output template. If appropriate registers are not free, the pattern
7622 will simply not match.
7624 @findex match_scratch
7626 Scratch registers are requested with a @code{match_scratch} pattern at
7627 the top level of the input pattern. The allocated register (initially) will
7628 be dead at the point requested within the original sequence. If the scratch
7629 is used at more than a single point, a @code{match_dup} pattern at the
7630 top level of the input pattern marks the last position in the input sequence
7631 at which the register must be available.
7633 Here is an example from the IA-32 machine description:
7637 [(match_scratch:SI 2 "r")
7638 (parallel [(set (match_operand:SI 0 "register_operand" "")
7639 (match_operator:SI 3 "arith_or_logical_operator"
7641 (match_operand:SI 1 "memory_operand" "")]))
7642 (clobber (reg:CC 17))])]
7643 "! optimize_size && ! TARGET_READ_MODIFY"
7644 [(set (match_dup 2) (match_dup 1))
7645 (parallel [(set (match_dup 0)
7646 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
7647 (clobber (reg:CC 17))])]
7652 This pattern tries to split a load from its use in the hopes that we'll be
7653 able to schedule around the memory load latency. It allocates a single
7654 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
7655 to be live only at the point just before the arithmetic.
7657 A real example requiring extended scratch lifetimes is harder to come by,
7658 so here's a silly made-up example:
7662 [(match_scratch:SI 4 "r")
7663 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
7664 (set (match_operand:SI 2 "" "") (match_dup 1))
7666 (set (match_operand:SI 3 "" "") (match_dup 1))]
7667 "/* @r{determine 1 does not overlap 0 and 2} */"
7668 [(set (match_dup 4) (match_dup 1))
7669 (set (match_dup 0) (match_dup 4))
7670 (set (match_dup 2) (match_dup 4))
7671 (set (match_dup 3) (match_dup 4))]
7676 If we had not added the @code{(match_dup 4)} in the middle of the input
7677 sequence, it might have been the case that the register we chose at the
7678 beginning of the sequence is killed by the first or second @code{set}.
7682 @node Insn Attributes
7683 @section Instruction Attributes
7684 @cindex insn attributes
7685 @cindex instruction attributes
7687 In addition to describing the instruction supported by the target machine,
7688 the @file{md} file also defines a group of @dfn{attributes} and a set of
7689 values for each. Every generated insn is assigned a value for each attribute.
7690 One possible attribute would be the effect that the insn has on the machine's
7691 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
7692 to track the condition codes.
7695 * Defining Attributes:: Specifying attributes and their values.
7696 * Expressions:: Valid expressions for attribute values.
7697 * Tagging Insns:: Assigning attribute values to insns.
7698 * Attr Example:: An example of assigning attributes.
7699 * Insn Lengths:: Computing the length of insns.
7700 * Constant Attributes:: Defining attributes that are constant.
7701 * Delay Slots:: Defining delay slots required for a machine.
7702 * Processor pipeline description:: Specifying information for insn scheduling.
7707 @node Defining Attributes
7708 @subsection Defining Attributes and their Values
7709 @cindex defining attributes and their values
7710 @cindex attributes, defining
7713 The @code{define_attr} expression is used to define each attribute required
7714 by the target machine. It looks like:
7717 (define_attr @var{name} @var{list-of-values} @var{default})
7720 @var{name} is a string specifying the name of the attribute being defined.
7721 Some attributes are used in a special way by the rest of the compiler. The
7722 @code{enabled} attribute can be used to conditionally enable or disable
7723 insn alternatives (@pxref{Disable Insn Alternatives}). The @code{predicable}
7724 attribute, together with a suitable @code{define_cond_exec}
7725 (@pxref{Conditional Execution}), can be used to automatically generate
7726 conditional variants of instruction patterns. The compiler internally uses
7727 the names @code{ce_enabled} and @code{nonce_enabled}, so they should not be
7728 used elsewhere as alternative names.
7730 @var{list-of-values} is either a string that specifies a comma-separated
7731 list of values that can be assigned to the attribute, or a null string to
7732 indicate that the attribute takes numeric values.
7734 @var{default} is an attribute expression that gives the value of this
7735 attribute for insns that match patterns whose definition does not include
7736 an explicit value for this attribute. @xref{Attr Example}, for more
7737 information on the handling of defaults. @xref{Constant Attributes},
7738 for information on attributes that do not depend on any particular insn.
7741 For each defined attribute, a number of definitions are written to the
7742 @file{insn-attr.h} file. For cases where an explicit set of values is
7743 specified for an attribute, the following are defined:
7747 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
7750 An enumerated class is defined for @samp{attr_@var{name}} with
7751 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
7752 the attribute name and value are first converted to uppercase.
7755 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
7756 returns the attribute value for that insn.
7759 For example, if the following is present in the @file{md} file:
7762 (define_attr "type" "branch,fp,load,store,arith" @dots{})
7766 the following lines will be written to the file @file{insn-attr.h}.
7769 #define HAVE_ATTR_type 1
7770 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
7771 TYPE_STORE, TYPE_ARITH@};
7772 extern enum attr_type get_attr_type ();
7775 If the attribute takes numeric values, no @code{enum} type will be
7776 defined and the function to obtain the attribute's value will return
7779 There are attributes which are tied to a specific meaning. These
7780 attributes are not free to use for other purposes:
7784 The @code{length} attribute is used to calculate the length of emitted
7785 code chunks. This is especially important when verifying branch
7786 distances. @xref{Insn Lengths}.
7789 The @code{enabled} attribute can be defined to prevent certain
7790 alternatives of an insn definition from being used during code
7791 generation. @xref{Disable Insn Alternatives}.
7794 For each of these special attributes, the corresponding
7795 @samp{HAVE_ATTR_@var{name}} @samp{#define} is also written when the
7796 attribute is not defined; in that case, it is defined as @samp{0}.
7798 @findex define_enum_attr
7799 @anchor{define_enum_attr}
7800 Another way of defining an attribute is to use:
7803 (define_enum_attr "@var{attr}" "@var{enum}" @var{default})
7806 This works in just the same way as @code{define_attr}, except that
7807 the list of values is taken from a separate enumeration called
7808 @var{enum} (@pxref{define_enum}). This form allows you to use
7809 the same list of values for several attributes without having to
7810 repeat the list each time. For example:
7813 (define_enum "processor" [
7818 (define_enum_attr "arch" "processor"
7819 (const (symbol_ref "target_arch")))
7820 (define_enum_attr "tune" "processor"
7821 (const (symbol_ref "target_tune")))
7824 defines the same attributes as:
7827 (define_attr "arch" "model_a,model_b,@dots{}"
7828 (const (symbol_ref "target_arch")))
7829 (define_attr "tune" "model_a,model_b,@dots{}"
7830 (const (symbol_ref "target_tune")))
7833 but without duplicating the processor list. The second example defines two
7834 separate C enums (@code{attr_arch} and @code{attr_tune}) whereas the first
7835 defines a single C enum (@code{processor}).
7839 @subsection Attribute Expressions
7840 @cindex attribute expressions
7842 RTL expressions used to define attributes use the codes described above
7843 plus a few specific to attribute definitions, to be discussed below.
7844 Attribute value expressions must have one of the following forms:
7847 @cindex @code{const_int} and attributes
7848 @item (const_int @var{i})
7849 The integer @var{i} specifies the value of a numeric attribute. @var{i}
7850 must be non-negative.
7852 The value of a numeric attribute can be specified either with a
7853 @code{const_int}, or as an integer represented as a string in
7854 @code{const_string}, @code{eq_attr} (see below), @code{attr},
7855 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
7856 overrides on specific instructions (@pxref{Tagging Insns}).
7858 @cindex @code{const_string} and attributes
7859 @item (const_string @var{value})
7860 The string @var{value} specifies a constant attribute value.
7861 If @var{value} is specified as @samp{"*"}, it means that the default value of
7862 the attribute is to be used for the insn containing this expression.
7863 @samp{"*"} obviously cannot be used in the @var{default} expression
7864 of a @code{define_attr}.
7866 If the attribute whose value is being specified is numeric, @var{value}
7867 must be a string containing a non-negative integer (normally
7868 @code{const_int} would be used in this case). Otherwise, it must
7869 contain one of the valid values for the attribute.
7871 @cindex @code{if_then_else} and attributes
7872 @item (if_then_else @var{test} @var{true-value} @var{false-value})
7873 @var{test} specifies an attribute test, whose format is defined below.
7874 The value of this expression is @var{true-value} if @var{test} is true,
7875 otherwise it is @var{false-value}.
7877 @cindex @code{cond} and attributes
7878 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
7879 The first operand of this expression is a vector containing an even
7880 number of expressions and consisting of pairs of @var{test} and @var{value}
7881 expressions. The value of the @code{cond} expression is that of the
7882 @var{value} corresponding to the first true @var{test} expression. If
7883 none of the @var{test} expressions are true, the value of the @code{cond}
7884 expression is that of the @var{default} expression.
7887 @var{test} expressions can have one of the following forms:
7890 @cindex @code{const_int} and attribute tests
7891 @item (const_int @var{i})
7892 This test is true if @var{i} is nonzero and false otherwise.
7894 @cindex @code{not} and attributes
7895 @cindex @code{ior} and attributes
7896 @cindex @code{and} and attributes
7897 @item (not @var{test})
7898 @itemx (ior @var{test1} @var{test2})
7899 @itemx (and @var{test1} @var{test2})
7900 These tests are true if the indicated logical function is true.
7902 @cindex @code{match_operand} and attributes
7903 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
7904 This test is true if operand @var{n} of the insn whose attribute value
7905 is being determined has mode @var{m} (this part of the test is ignored
7906 if @var{m} is @code{VOIDmode}) and the function specified by the string
7907 @var{pred} returns a nonzero value when passed operand @var{n} and mode
7908 @var{m} (this part of the test is ignored if @var{pred} is the null
7911 The @var{constraints} operand is ignored and should be the null string.
7913 @cindex @code{match_test} and attributes
7914 @item (match_test @var{c-expr})
7915 The test is true if C expression @var{c-expr} is true. In non-constant
7916 attributes, @var{c-expr} has access to the following variables:
7920 The rtl instruction under test.
7921 @item which_alternative
7922 The @code{define_insn} alternative that @var{insn} matches.
7923 @xref{Output Statement}.
7925 An array of @var{insn}'s rtl operands.
7928 @var{c-expr} behaves like the condition in a C @code{if} statement,
7929 so there is no need to explicitly convert the expression into a boolean
7930 0 or 1 value. For example, the following two tests are equivalent:
7933 (match_test "x & 2")
7934 (match_test "(x & 2) != 0")
7937 @cindex @code{le} and attributes
7938 @cindex @code{leu} and attributes
7939 @cindex @code{lt} and attributes
7940 @cindex @code{gt} and attributes
7941 @cindex @code{gtu} and attributes
7942 @cindex @code{ge} and attributes
7943 @cindex @code{geu} and attributes
7944 @cindex @code{ne} and attributes
7945 @cindex @code{eq} and attributes
7946 @cindex @code{plus} and attributes
7947 @cindex @code{minus} and attributes
7948 @cindex @code{mult} and attributes
7949 @cindex @code{div} and attributes
7950 @cindex @code{mod} and attributes
7951 @cindex @code{abs} and attributes
7952 @cindex @code{neg} and attributes
7953 @cindex @code{ashift} and attributes
7954 @cindex @code{lshiftrt} and attributes
7955 @cindex @code{ashiftrt} and attributes
7956 @item (le @var{arith1} @var{arith2})
7957 @itemx (leu @var{arith1} @var{arith2})
7958 @itemx (lt @var{arith1} @var{arith2})
7959 @itemx (ltu @var{arith1} @var{arith2})
7960 @itemx (gt @var{arith1} @var{arith2})
7961 @itemx (gtu @var{arith1} @var{arith2})
7962 @itemx (ge @var{arith1} @var{arith2})
7963 @itemx (geu @var{arith1} @var{arith2})
7964 @itemx (ne @var{arith1} @var{arith2})
7965 @itemx (eq @var{arith1} @var{arith2})
7966 These tests are true if the indicated comparison of the two arithmetic
7967 expressions is true. Arithmetic expressions are formed with
7968 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
7969 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
7970 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
7973 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
7974 Lengths},for additional forms). @code{symbol_ref} is a string
7975 denoting a C expression that yields an @code{int} when evaluated by the
7976 @samp{get_attr_@dots{}} routine. It should normally be a global
7980 @item (eq_attr @var{name} @var{value})
7981 @var{name} is a string specifying the name of an attribute.
7983 @var{value} is a string that is either a valid value for attribute
7984 @var{name}, a comma-separated list of values, or @samp{!} followed by a
7985 value or list. If @var{value} does not begin with a @samp{!}, this
7986 test is true if the value of the @var{name} attribute of the current
7987 insn is in the list specified by @var{value}. If @var{value} begins
7988 with a @samp{!}, this test is true if the attribute's value is
7989 @emph{not} in the specified list.
7994 (eq_attr "type" "load,store")
8001 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
8004 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
8005 value of the compiler variable @code{which_alternative}
8006 (@pxref{Output Statement}) and the values must be small integers. For
8010 (eq_attr "alternative" "2,3")
8017 (ior (eq (symbol_ref "which_alternative") (const_int 2))
8018 (eq (symbol_ref "which_alternative") (const_int 3)))
8021 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
8022 where the value of the attribute being tested is known for all insns matching
8023 a particular pattern. This is by far the most common case.
8026 @item (attr_flag @var{name})
8027 The value of an @code{attr_flag} expression is true if the flag
8028 specified by @var{name} is true for the @code{insn} currently being
8031 @var{name} is a string specifying one of a fixed set of flags to test.
8032 Test the flags @code{forward} and @code{backward} to determine the
8033 direction of a conditional branch.
8035 This example describes a conditional branch delay slot which
8036 can be nullified for forward branches that are taken (annul-true) or
8037 for backward branches which are not taken (annul-false).
8040 (define_delay (eq_attr "type" "cbranch")
8041 [(eq_attr "in_branch_delay" "true")
8042 (and (eq_attr "in_branch_delay" "true")
8043 (attr_flag "forward"))
8044 (and (eq_attr "in_branch_delay" "true")
8045 (attr_flag "backward"))])
8048 The @code{forward} and @code{backward} flags are false if the current
8049 @code{insn} being scheduled is not a conditional branch.
8051 @code{attr_flag} is only used during delay slot scheduling and has no
8052 meaning to other passes of the compiler.
8055 @item (attr @var{name})
8056 The value of another attribute is returned. This is most useful
8057 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
8058 produce more efficient code for non-numeric attributes.
8064 @subsection Assigning Attribute Values to Insns
8065 @cindex tagging insns
8066 @cindex assigning attribute values to insns
8068 The value assigned to an attribute of an insn is primarily determined by
8069 which pattern is matched by that insn (or which @code{define_peephole}
8070 generated it). Every @code{define_insn} and @code{define_peephole} can
8071 have an optional last argument to specify the values of attributes for
8072 matching insns. The value of any attribute not specified in a particular
8073 insn is set to the default value for that attribute, as specified in its
8074 @code{define_attr}. Extensive use of default values for attributes
8075 permits the specification of the values for only one or two attributes
8076 in the definition of most insn patterns, as seen in the example in the
8079 The optional last argument of @code{define_insn} and
8080 @code{define_peephole} is a vector of expressions, each of which defines
8081 the value for a single attribute. The most general way of assigning an
8082 attribute's value is to use a @code{set} expression whose first operand is an
8083 @code{attr} expression giving the name of the attribute being set. The
8084 second operand of the @code{set} is an attribute expression
8085 (@pxref{Expressions}) giving the value of the attribute.
8087 When the attribute value depends on the @samp{alternative} attribute
8088 (i.e., which is the applicable alternative in the constraint of the
8089 insn), the @code{set_attr_alternative} expression can be used. It
8090 allows the specification of a vector of attribute expressions, one for
8094 When the generality of arbitrary attribute expressions is not required,
8095 the simpler @code{set_attr} expression can be used, which allows
8096 specifying a string giving either a single attribute value or a list
8097 of attribute values, one for each alternative.
8099 The form of each of the above specifications is shown below. In each case,
8100 @var{name} is a string specifying the attribute to be set.
8103 @item (set_attr @var{name} @var{value-string})
8104 @var{value-string} is either a string giving the desired attribute value,
8105 or a string containing a comma-separated list giving the values for
8106 succeeding alternatives. The number of elements must match the number
8107 of alternatives in the constraint of the insn pattern.
8109 Note that it may be useful to specify @samp{*} for some alternative, in
8110 which case the attribute will assume its default value for insns matching
8113 @findex set_attr_alternative
8114 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
8115 Depending on the alternative of the insn, the value will be one of the
8116 specified values. This is a shorthand for using a @code{cond} with
8117 tests on the @samp{alternative} attribute.
8120 @item (set (attr @var{name}) @var{value})
8121 The first operand of this @code{set} must be the special RTL expression
8122 @code{attr}, whose sole operand is a string giving the name of the
8123 attribute being set. @var{value} is the value of the attribute.
8126 The following shows three different ways of representing the same
8127 attribute value specification:
8130 (set_attr "type" "load,store,arith")
8132 (set_attr_alternative "type"
8133 [(const_string "load") (const_string "store")
8134 (const_string "arith")])
8137 (cond [(eq_attr "alternative" "1") (const_string "load")
8138 (eq_attr "alternative" "2") (const_string "store")]
8139 (const_string "arith")))
8143 @findex define_asm_attributes
8144 The @code{define_asm_attributes} expression provides a mechanism to
8145 specify the attributes assigned to insns produced from an @code{asm}
8146 statement. It has the form:
8149 (define_asm_attributes [@var{attr-sets}])
8153 where @var{attr-sets} is specified the same as for both the
8154 @code{define_insn} and the @code{define_peephole} expressions.
8156 These values will typically be the ``worst case'' attribute values. For
8157 example, they might indicate that the condition code will be clobbered.
8159 A specification for a @code{length} attribute is handled specially. The
8160 way to compute the length of an @code{asm} insn is to multiply the
8161 length specified in the expression @code{define_asm_attributes} by the
8162 number of machine instructions specified in the @code{asm} statement,
8163 determined by counting the number of semicolons and newlines in the
8164 string. Therefore, the value of the @code{length} attribute specified
8165 in a @code{define_asm_attributes} should be the maximum possible length
8166 of a single machine instruction.
8171 @subsection Example of Attribute Specifications
8172 @cindex attribute specifications example
8173 @cindex attribute specifications
8175 The judicious use of defaulting is important in the efficient use of
8176 insn attributes. Typically, insns are divided into @dfn{types} and an
8177 attribute, customarily called @code{type}, is used to represent this
8178 value. This attribute is normally used only to define the default value
8179 for other attributes. An example will clarify this usage.
8181 Assume we have a RISC machine with a condition code and in which only
8182 full-word operations are performed in registers. Let us assume that we
8183 can divide all insns into loads, stores, (integer) arithmetic
8184 operations, floating point operations, and branches.
8186 Here we will concern ourselves with determining the effect of an insn on
8187 the condition code and will limit ourselves to the following possible
8188 effects: The condition code can be set unpredictably (clobbered), not
8189 be changed, be set to agree with the results of the operation, or only
8190 changed if the item previously set into the condition code has been
8193 Here is part of a sample @file{md} file for such a machine:
8196 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
8198 (define_attr "cc" "clobber,unchanged,set,change0"
8199 (cond [(eq_attr "type" "load")
8200 (const_string "change0")
8201 (eq_attr "type" "store,branch")
8202 (const_string "unchanged")
8203 (eq_attr "type" "arith")
8204 (if_then_else (match_operand:SI 0 "" "")
8205 (const_string "set")
8206 (const_string "clobber"))]
8207 (const_string "clobber")))
8210 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
8211 (match_operand:SI 1 "general_operand" "r,m,r"))]
8217 [(set_attr "type" "arith,load,store")])
8220 Note that we assume in the above example that arithmetic operations
8221 performed on quantities smaller than a machine word clobber the condition
8222 code since they will set the condition code to a value corresponding to the
8228 @subsection Computing the Length of an Insn
8229 @cindex insn lengths, computing
8230 @cindex computing the length of an insn
8232 For many machines, multiple types of branch instructions are provided, each
8233 for different length branch displacements. In most cases, the assembler
8234 will choose the correct instruction to use. However, when the assembler
8235 cannot do so, GCC can when a special attribute, the @code{length}
8236 attribute, is defined. This attribute must be defined to have numeric
8237 values by specifying a null string in its @code{define_attr}.
8239 In the case of the @code{length} attribute, two additional forms of
8240 arithmetic terms are allowed in test expressions:
8243 @cindex @code{match_dup} and attributes
8244 @item (match_dup @var{n})
8245 This refers to the address of operand @var{n} of the current insn, which
8246 must be a @code{label_ref}.
8248 @cindex @code{pc} and attributes
8250 This refers to the address of the @emph{current} insn. It might have
8251 been more consistent with other usage to make this the address of the
8252 @emph{next} insn but this would be confusing because the length of the
8253 current insn is to be computed.
8256 @cindex @code{addr_vec}, length of
8257 @cindex @code{addr_diff_vec}, length of
8258 For normal insns, the length will be determined by value of the
8259 @code{length} attribute. In the case of @code{addr_vec} and
8260 @code{addr_diff_vec} insn patterns, the length is computed as
8261 the number of vectors multiplied by the size of each vector.
8263 Lengths are measured in addressable storage units (bytes).
8265 The following macros can be used to refine the length computation:
8268 @findex ADJUST_INSN_LENGTH
8269 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
8270 If defined, modifies the length assigned to instruction @var{insn} as a
8271 function of the context in which it is used. @var{length} is an lvalue
8272 that contains the initially computed length of the insn and should be
8273 updated with the correct length of the insn.
8275 This macro will normally not be required. A case in which it is
8276 required is the ROMP@. On this machine, the size of an @code{addr_vec}
8277 insn must be increased by two to compensate for the fact that alignment
8281 @findex get_attr_length
8282 The routine that returns @code{get_attr_length} (the value of the
8283 @code{length} attribute) can be used by the output routine to
8284 determine the form of the branch instruction to be written, as the
8285 example below illustrates.
8287 As an example of the specification of variable-length branches, consider
8288 the IBM 360. If we adopt the convention that a register will be set to
8289 the starting address of a function, we can jump to labels within 4k of
8290 the start using a four-byte instruction. Otherwise, we need a six-byte
8291 sequence to load the address from memory and then branch to it.
8293 On such a machine, a pattern for a branch instruction might be specified
8299 (label_ref (match_operand 0 "" "")))]
8302 return (get_attr_length (insn) == 4
8303 ? "b %l0" : "l r15,=a(%l0); br r15");
8305 [(set (attr "length")
8306 (if_then_else (lt (match_dup 0) (const_int 4096))
8313 @node Constant Attributes
8314 @subsection Constant Attributes
8315 @cindex constant attributes
8317 A special form of @code{define_attr}, where the expression for the
8318 default value is a @code{const} expression, indicates an attribute that
8319 is constant for a given run of the compiler. Constant attributes may be
8320 used to specify which variety of processor is used. For example,
8323 (define_attr "cpu" "m88100,m88110,m88000"
8325 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
8326 (symbol_ref "TARGET_88110") (const_string "m88110")]
8327 (const_string "m88000"))))
8329 (define_attr "memory" "fast,slow"
8331 (if_then_else (symbol_ref "TARGET_FAST_MEM")
8332 (const_string "fast")
8333 (const_string "slow"))))
8336 The routine generated for constant attributes has no parameters as it
8337 does not depend on any particular insn. RTL expressions used to define
8338 the value of a constant attribute may use the @code{symbol_ref} form,
8339 but may not use either the @code{match_operand} form or @code{eq_attr}
8340 forms involving insn attributes.
8345 @subsection Delay Slot Scheduling
8346 @cindex delay slots, defining
8348 The insn attribute mechanism can be used to specify the requirements for
8349 delay slots, if any, on a target machine. An instruction is said to
8350 require a @dfn{delay slot} if some instructions that are physically
8351 after the instruction are executed as if they were located before it.
8352 Classic examples are branch and call instructions, which often execute
8353 the following instruction before the branch or call is performed.
8355 On some machines, conditional branch instructions can optionally
8356 @dfn{annul} instructions in the delay slot. This means that the
8357 instruction will not be executed for certain branch outcomes. Both
8358 instructions that annul if the branch is true and instructions that
8359 annul if the branch is false are supported.
8361 Delay slot scheduling differs from instruction scheduling in that
8362 determining whether an instruction needs a delay slot is dependent only
8363 on the type of instruction being generated, not on data flow between the
8364 instructions. See the next section for a discussion of data-dependent
8365 instruction scheduling.
8367 @findex define_delay
8368 The requirement of an insn needing one or more delay slots is indicated
8369 via the @code{define_delay} expression. It has the following form:
8372 (define_delay @var{test}
8373 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
8374 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
8378 @var{test} is an attribute test that indicates whether this
8379 @code{define_delay} applies to a particular insn. If so, the number of
8380 required delay slots is determined by the length of the vector specified
8381 as the second argument. An insn placed in delay slot @var{n} must
8382 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
8383 attribute test that specifies which insns may be annulled if the branch
8384 is true. Similarly, @var{annul-false-n} specifies which insns in the
8385 delay slot may be annulled if the branch is false. If annulling is not
8386 supported for that delay slot, @code{(nil)} should be coded.
8388 For example, in the common case where branch and call insns require
8389 a single delay slot, which may contain any insn other than a branch or
8390 call, the following would be placed in the @file{md} file:
8393 (define_delay (eq_attr "type" "branch,call")
8394 [(eq_attr "type" "!branch,call") (nil) (nil)])
8397 Multiple @code{define_delay} expressions may be specified. In this
8398 case, each such expression specifies different delay slot requirements
8399 and there must be no insn for which tests in two @code{define_delay}
8400 expressions are both true.
8402 For example, if we have a machine that requires one delay slot for branches
8403 but two for calls, no delay slot can contain a branch or call insn,
8404 and any valid insn in the delay slot for the branch can be annulled if the
8405 branch is true, we might represent this as follows:
8408 (define_delay (eq_attr "type" "branch")
8409 [(eq_attr "type" "!branch,call")
8410 (eq_attr "type" "!branch,call")
8413 (define_delay (eq_attr "type" "call")
8414 [(eq_attr "type" "!branch,call") (nil) (nil)
8415 (eq_attr "type" "!branch,call") (nil) (nil)])
8417 @c the above is *still* too long. --mew 4feb93
8421 @node Processor pipeline description
8422 @subsection Specifying processor pipeline description
8423 @cindex processor pipeline description
8424 @cindex processor functional units
8425 @cindex instruction latency time
8426 @cindex interlock delays
8427 @cindex data dependence delays
8428 @cindex reservation delays
8429 @cindex pipeline hazard recognizer
8430 @cindex automaton based pipeline description
8431 @cindex regular expressions
8432 @cindex deterministic finite state automaton
8433 @cindex automaton based scheduler
8437 To achieve better performance, most modern processors
8438 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
8439 processors) have many @dfn{functional units} on which several
8440 instructions can be executed simultaneously. An instruction starts
8441 execution if its issue conditions are satisfied. If not, the
8442 instruction is stalled until its conditions are satisfied. Such
8443 @dfn{interlock (pipeline) delay} causes interruption of the fetching
8444 of successor instructions (or demands nop instructions, e.g.@: for some
8447 There are two major kinds of interlock delays in modern processors.
8448 The first one is a data dependence delay determining @dfn{instruction
8449 latency time}. The instruction execution is not started until all
8450 source data have been evaluated by prior instructions (there are more
8451 complex cases when the instruction execution starts even when the data
8452 are not available but will be ready in given time after the
8453 instruction execution start). Taking the data dependence delays into
8454 account is simple. The data dependence (true, output, and
8455 anti-dependence) delay between two instructions is given by a
8456 constant. In most cases this approach is adequate. The second kind
8457 of interlock delays is a reservation delay. The reservation delay
8458 means that two instructions under execution will be in need of shared
8459 processors resources, i.e.@: buses, internal registers, and/or
8460 functional units, which are reserved for some time. Taking this kind
8461 of delay into account is complex especially for modern @acronym{RISC}
8464 The task of exploiting more processor parallelism is solved by an
8465 instruction scheduler. For a better solution to this problem, the
8466 instruction scheduler has to have an adequate description of the
8467 processor parallelism (or @dfn{pipeline description}). GCC
8468 machine descriptions describe processor parallelism and functional
8469 unit reservations for groups of instructions with the aid of
8470 @dfn{regular expressions}.
8472 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
8473 figure out the possibility of the instruction issue by the processor
8474 on a given simulated processor cycle. The pipeline hazard recognizer is
8475 automatically generated from the processor pipeline description. The
8476 pipeline hazard recognizer generated from the machine description
8477 is based on a deterministic finite state automaton (@acronym{DFA}):
8478 the instruction issue is possible if there is a transition from one
8479 automaton state to another one. This algorithm is very fast, and
8480 furthermore, its speed is not dependent on processor
8481 complexity@footnote{However, the size of the automaton depends on
8482 processor complexity. To limit this effect, machine descriptions
8483 can split orthogonal parts of the machine description among several
8484 automata: but then, since each of these must be stepped independently,
8485 this does cause a small decrease in the algorithm's performance.}.
8487 @cindex automaton based pipeline description
8488 The rest of this section describes the directives that constitute
8489 an automaton-based processor pipeline description. The order of
8490 these constructions within the machine description file is not
8493 @findex define_automaton
8494 @cindex pipeline hazard recognizer
8495 The following optional construction describes names of automata
8496 generated and used for the pipeline hazards recognition. Sometimes
8497 the generated finite state automaton used by the pipeline hazard
8498 recognizer is large. If we use more than one automaton and bind functional
8499 units to the automata, the total size of the automata is usually
8500 less than the size of the single automaton. If there is no one such
8501 construction, only one finite state automaton is generated.
8504 (define_automaton @var{automata-names})
8507 @var{automata-names} is a string giving names of the automata. The
8508 names are separated by commas. All the automata should have unique names.
8509 The automaton name is used in the constructions @code{define_cpu_unit} and
8510 @code{define_query_cpu_unit}.
8512 @findex define_cpu_unit
8513 @cindex processor functional units
8514 Each processor functional unit used in the description of instruction
8515 reservations should be described by the following construction.
8518 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
8521 @var{unit-names} is a string giving the names of the functional units
8522 separated by commas. Don't use name @samp{nothing}, it is reserved
8525 @var{automaton-name} is a string giving the name of the automaton with
8526 which the unit is bound. The automaton should be described in
8527 construction @code{define_automaton}. You should give
8528 @dfn{automaton-name}, if there is a defined automaton.
8530 The assignment of units to automata are constrained by the uses of the
8531 units in insn reservations. The most important constraint is: if a
8532 unit reservation is present on a particular cycle of an alternative
8533 for an insn reservation, then some unit from the same automaton must
8534 be present on the same cycle for the other alternatives of the insn
8535 reservation. The rest of the constraints are mentioned in the
8536 description of the subsequent constructions.
8538 @findex define_query_cpu_unit
8539 @cindex querying function unit reservations
8540 The following construction describes CPU functional units analogously
8541 to @code{define_cpu_unit}. The reservation of such units can be
8542 queried for an automaton state. The instruction scheduler never
8543 queries reservation of functional units for given automaton state. So
8544 as a rule, you don't need this construction. This construction could
8545 be used for future code generation goals (e.g.@: to generate
8546 @acronym{VLIW} insn templates).
8549 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
8552 @var{unit-names} is a string giving names of the functional units
8553 separated by commas.
8555 @var{automaton-name} is a string giving the name of the automaton with
8556 which the unit is bound.
8558 @findex define_insn_reservation
8559 @cindex instruction latency time
8560 @cindex regular expressions
8562 The following construction is the major one to describe pipeline
8563 characteristics of an instruction.
8566 (define_insn_reservation @var{insn-name} @var{default_latency}
8567 @var{condition} @var{regexp})
8570 @var{default_latency} is a number giving latency time of the
8571 instruction. There is an important difference between the old
8572 description and the automaton based pipeline description. The latency
8573 time is used for all dependencies when we use the old description. In
8574 the automaton based pipeline description, the given latency time is only
8575 used for true dependencies. The cost of anti-dependencies is always
8576 zero and the cost of output dependencies is the difference between
8577 latency times of the producing and consuming insns (if the difference
8578 is negative, the cost is considered to be zero). You can always
8579 change the default costs for any description by using the target hook
8580 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
8582 @var{insn-name} is a string giving the internal name of the insn. The
8583 internal names are used in constructions @code{define_bypass} and in
8584 the automaton description file generated for debugging. The internal
8585 name has nothing in common with the names in @code{define_insn}. It is a
8586 good practice to use insn classes described in the processor manual.
8588 @var{condition} defines what RTL insns are described by this
8589 construction. You should remember that you will be in trouble if
8590 @var{condition} for two or more different
8591 @code{define_insn_reservation} constructions is TRUE for an insn. In
8592 this case what reservation will be used for the insn is not defined.
8593 Such cases are not checked during generation of the pipeline hazards
8594 recognizer because in general recognizing that two conditions may have
8595 the same value is quite difficult (especially if the conditions
8596 contain @code{symbol_ref}). It is also not checked during the
8597 pipeline hazard recognizer work because it would slow down the
8598 recognizer considerably.
8600 @var{regexp} is a string describing the reservation of the cpu's functional
8601 units by the instruction. The reservations are described by a regular
8602 expression according to the following syntax:
8605 regexp = regexp "," oneof
8608 oneof = oneof "|" allof
8611 allof = allof "+" repeat
8614 repeat = element "*" number
8617 element = cpu_function_unit_name
8626 @samp{,} is used for describing the start of the next cycle in
8630 @samp{|} is used for describing a reservation described by the first
8631 regular expression @strong{or} a reservation described by the second
8632 regular expression @strong{or} etc.
8635 @samp{+} is used for describing a reservation described by the first
8636 regular expression @strong{and} a reservation described by the
8637 second regular expression @strong{and} etc.
8640 @samp{*} is used for convenience and simply means a sequence in which
8641 the regular expression are repeated @var{number} times with cycle
8642 advancing (see @samp{,}).
8645 @samp{cpu_function_unit_name} denotes reservation of the named
8649 @samp{reservation_name} --- see description of construction
8650 @samp{define_reservation}.
8653 @samp{nothing} denotes no unit reservations.
8656 @findex define_reservation
8657 Sometimes unit reservations for different insns contain common parts.
8658 In such case, you can simplify the pipeline description by describing
8659 the common part by the following construction
8662 (define_reservation @var{reservation-name} @var{regexp})
8665 @var{reservation-name} is a string giving name of @var{regexp}.
8666 Functional unit names and reservation names are in the same name
8667 space. So the reservation names should be different from the
8668 functional unit names and can not be the reserved name @samp{nothing}.
8670 @findex define_bypass
8671 @cindex instruction latency time
8673 The following construction is used to describe exceptions in the
8674 latency time for given instruction pair. This is so called bypasses.
8677 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
8681 @var{number} defines when the result generated by the instructions
8682 given in string @var{out_insn_names} will be ready for the
8683 instructions given in string @var{in_insn_names}. Each of these
8684 strings is a comma-separated list of filename-style globs and
8685 they refer to the names of @code{define_insn_reservation}s.
8688 (define_bypass 1 "cpu1_load_*, cpu1_store_*" "cpu1_load_*")
8690 defines a bypass between instructions that start with
8691 @samp{cpu1_load_} or @samp{cpu1_store_} and those that start with
8694 @var{guard} is an optional string giving the name of a C function which
8695 defines an additional guard for the bypass. The function will get the
8696 two insns as parameters. If the function returns zero the bypass will
8697 be ignored for this case. The additional guard is necessary to
8698 recognize complicated bypasses, e.g.@: when the consumer is only an address
8699 of insn @samp{store} (not a stored value).
8701 If there are more one bypass with the same output and input insns, the
8702 chosen bypass is the first bypass with a guard in description whose
8703 guard function returns nonzero. If there is no such bypass, then
8704 bypass without the guard function is chosen.
8706 @findex exclusion_set
8707 @findex presence_set
8708 @findex final_presence_set
8710 @findex final_absence_set
8713 The following five constructions are usually used to describe
8714 @acronym{VLIW} processors, or more precisely, to describe a placement
8715 of small instructions into @acronym{VLIW} instruction slots. They
8716 can be used for @acronym{RISC} processors, too.
8719 (exclusion_set @var{unit-names} @var{unit-names})
8720 (presence_set @var{unit-names} @var{patterns})
8721 (final_presence_set @var{unit-names} @var{patterns})
8722 (absence_set @var{unit-names} @var{patterns})
8723 (final_absence_set @var{unit-names} @var{patterns})
8726 @var{unit-names} is a string giving names of functional units
8727 separated by commas.
8729 @var{patterns} is a string giving patterns of functional units
8730 separated by comma. Currently pattern is one unit or units
8731 separated by white-spaces.
8733 The first construction (@samp{exclusion_set}) means that each
8734 functional unit in the first string can not be reserved simultaneously
8735 with a unit whose name is in the second string and vice versa. For
8736 example, the construction is useful for describing processors
8737 (e.g.@: some SPARC processors) with a fully pipelined floating point
8738 functional unit which can execute simultaneously only single floating
8739 point insns or only double floating point insns.
8741 The second construction (@samp{presence_set}) means that each
8742 functional unit in the first string can not be reserved unless at
8743 least one of pattern of units whose names are in the second string is
8744 reserved. This is an asymmetric relation. For example, it is useful
8745 for description that @acronym{VLIW} @samp{slot1} is reserved after
8746 @samp{slot0} reservation. We could describe it by the following
8750 (presence_set "slot1" "slot0")
8753 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
8754 reservation. In this case we could write
8757 (presence_set "slot1" "slot0 b0")
8760 The third construction (@samp{final_presence_set}) is analogous to
8761 @samp{presence_set}. The difference between them is when checking is
8762 done. When an instruction is issued in given automaton state
8763 reflecting all current and planned unit reservations, the automaton
8764 state is changed. The first state is a source state, the second one
8765 is a result state. Checking for @samp{presence_set} is done on the
8766 source state reservation, checking for @samp{final_presence_set} is
8767 done on the result reservation. This construction is useful to
8768 describe a reservation which is actually two subsequent reservations.
8769 For example, if we use
8772 (presence_set "slot1" "slot0")
8775 the following insn will be never issued (because @samp{slot1} requires
8776 @samp{slot0} which is absent in the source state).
8779 (define_reservation "insn_and_nop" "slot0 + slot1")
8782 but it can be issued if we use analogous @samp{final_presence_set}.
8784 The forth construction (@samp{absence_set}) means that each functional
8785 unit in the first string can be reserved only if each pattern of units
8786 whose names are in the second string is not reserved. This is an
8787 asymmetric relation (actually @samp{exclusion_set} is analogous to
8788 this one but it is symmetric). For example it might be useful in a
8789 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
8790 after either @samp{slot1} or @samp{slot2} have been reserved. This
8791 can be described as:
8794 (absence_set "slot0" "slot1, slot2")
8797 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
8798 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
8799 this case we could write
8802 (absence_set "slot2" "slot0 b0, slot1 b1")
8805 All functional units mentioned in a set should belong to the same
8808 The last construction (@samp{final_absence_set}) is analogous to
8809 @samp{absence_set} but checking is done on the result (state)
8810 reservation. See comments for @samp{final_presence_set}.
8812 @findex automata_option
8813 @cindex deterministic finite state automaton
8814 @cindex nondeterministic finite state automaton
8815 @cindex finite state automaton minimization
8816 You can control the generator of the pipeline hazard recognizer with
8817 the following construction.
8820 (automata_option @var{options})
8823 @var{options} is a string giving options which affect the generated
8824 code. Currently there are the following options:
8828 @dfn{no-minimization} makes no minimization of the automaton. This is
8829 only worth to do when we are debugging the description and need to
8830 look more accurately at reservations of states.
8833 @dfn{time} means printing time statistics about the generation of
8837 @dfn{stats} means printing statistics about the generated automata
8838 such as the number of DFA states, NDFA states and arcs.
8841 @dfn{v} means a generation of the file describing the result automata.
8842 The file has suffix @samp{.dfa} and can be used for the description
8843 verification and debugging.
8846 @dfn{w} means a generation of warning instead of error for
8847 non-critical errors.
8850 @dfn{no-comb-vect} prevents the automaton generator from generating
8851 two data structures and comparing them for space efficiency. Using
8852 a comb vector to represent transitions may be better, but it can be
8853 very expensive to construct. This option is useful if the build
8854 process spends an unacceptably long time in genautomata.
8857 @dfn{ndfa} makes nondeterministic finite state automata. This affects
8858 the treatment of operator @samp{|} in the regular expressions. The
8859 usual treatment of the operator is to try the first alternative and,
8860 if the reservation is not possible, the second alternative. The
8861 nondeterministic treatment means trying all alternatives, some of them
8862 may be rejected by reservations in the subsequent insns.
8865 @dfn{collapse-ndfa} modifies the behaviour of the generator when
8866 producing an automaton. An additional state transition to collapse a
8867 nondeterministic @acronym{NDFA} state to a deterministic @acronym{DFA}
8868 state is generated. It can be triggered by passing @code{const0_rtx} to
8869 state_transition. In such an automaton, cycle advance transitions are
8870 available only for these collapsed states. This option is useful for
8871 ports that want to use the @code{ndfa} option, but also want to use
8872 @code{define_query_cpu_unit} to assign units to insns issued in a cycle.
8875 @dfn{progress} means output of a progress bar showing how many states
8876 were generated so far for automaton being processed. This is useful
8877 during debugging a @acronym{DFA} description. If you see too many
8878 generated states, you could interrupt the generator of the pipeline
8879 hazard recognizer and try to figure out a reason for generation of the
8883 As an example, consider a superscalar @acronym{RISC} machine which can
8884 issue three insns (two integer insns and one floating point insn) on
8885 the cycle but can finish only two insns. To describe this, we define
8886 the following functional units.
8889 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
8890 (define_cpu_unit "port0, port1")
8893 All simple integer insns can be executed in any integer pipeline and
8894 their result is ready in two cycles. The simple integer insns are
8895 issued into the first pipeline unless it is reserved, otherwise they
8896 are issued into the second pipeline. Integer division and
8897 multiplication insns can be executed only in the second integer
8898 pipeline and their results are ready correspondingly in 8 and 4
8899 cycles. The integer division is not pipelined, i.e.@: the subsequent
8900 integer division insn can not be issued until the current division
8901 insn finished. Floating point insns are fully pipelined and their
8902 results are ready in 3 cycles. Where the result of a floating point
8903 insn is used by an integer insn, an additional delay of one cycle is
8904 incurred. To describe all of this we could specify
8907 (define_cpu_unit "div")
8909 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
8910 "(i0_pipeline | i1_pipeline), (port0 | port1)")
8912 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
8913 "i1_pipeline, nothing*2, (port0 | port1)")
8915 (define_insn_reservation "div" 8 (eq_attr "type" "div")
8916 "i1_pipeline, div*7, div + (port0 | port1)")
8918 (define_insn_reservation "float" 3 (eq_attr "type" "float")
8919 "f_pipeline, nothing, (port0 | port1))
8921 (define_bypass 4 "float" "simple,mult,div")
8924 To simplify the description we could describe the following reservation
8927 (define_reservation "finish" "port0|port1")
8930 and use it in all @code{define_insn_reservation} as in the following
8934 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
8935 "(i0_pipeline | i1_pipeline), finish")
8941 @node Conditional Execution
8942 @section Conditional Execution
8943 @cindex conditional execution
8946 A number of architectures provide for some form of conditional
8947 execution, or predication. The hallmark of this feature is the
8948 ability to nullify most of the instructions in the instruction set.
8949 When the instruction set is large and not entirely symmetric, it
8950 can be quite tedious to describe these forms directly in the
8951 @file{.md} file. An alternative is the @code{define_cond_exec} template.
8953 @findex define_cond_exec
8956 [@var{predicate-pattern}]
8958 "@var{output-template}"
8959 "@var{optional-insn-attribues}")
8962 @var{predicate-pattern} is the condition that must be true for the
8963 insn to be executed at runtime and should match a relational operator.
8964 One can use @code{match_operator} to match several relational operators
8965 at once. Any @code{match_operand} operands must have no more than one
8968 @var{condition} is a C expression that must be true for the generated
8971 @findex current_insn_predicate
8972 @var{output-template} is a string similar to the @code{define_insn}
8973 output template (@pxref{Output Template}), except that the @samp{*}
8974 and @samp{@@} special cases do not apply. This is only useful if the
8975 assembly text for the predicate is a simple prefix to the main insn.
8976 In order to handle the general case, there is a global variable
8977 @code{current_insn_predicate} that will contain the entire predicate
8978 if the current insn is predicated, and will otherwise be @code{NULL}.
8980 @var{optional-insn-attributes} is an optional vector of attributes that gets
8981 appended to the insn attributes of the produced cond_exec rtx. It can
8982 be used to add some distinguishing attribute to cond_exec rtxs produced
8983 that way. An example usage would be to use this attribute in conjunction
8984 with attributes on the main pattern to disable particular alternatives under
8987 When @code{define_cond_exec} is used, an implicit reference to
8988 the @code{predicable} instruction attribute is made.
8989 @xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have
8990 exactly two elements in its @var{list-of-values}), with the possible
8991 values being @code{no} and @code{yes}. The default and all uses in
8992 the insns must be a simple constant, not a complex expressions. It
8993 may, however, depend on the alternative, by using a comma-separated
8994 list of values. If that is the case, the port should also define an
8995 @code{enabled} attribute (@pxref{Disable Insn Alternatives}), which
8996 should also allow only @code{no} and @code{yes} as its values.
8998 For each @code{define_insn} for which the @code{predicable}
8999 attribute is true, a new @code{define_insn} pattern will be
9000 generated that matches a predicated version of the instruction.
9004 (define_insn "addsi"
9005 [(set (match_operand:SI 0 "register_operand" "r")
9006 (plus:SI (match_operand:SI 1 "register_operand" "r")
9007 (match_operand:SI 2 "register_operand" "r")))]
9012 [(ne (match_operand:CC 0 "register_operand" "c")
9019 generates a new pattern
9024 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
9025 (set (match_operand:SI 0 "register_operand" "r")
9026 (plus:SI (match_operand:SI 1 "register_operand" "r")
9027 (match_operand:SI 2 "register_operand" "r"))))]
9028 "(@var{test2}) && (@var{test1})"
9029 "(%3) add %2,%1,%0")
9035 @section RTL Templates Transformations
9036 @cindex define_subst
9038 For some hardware architectures there are common cases when the RTL
9039 templates for the instructions can be derived from the other RTL
9040 templates using simple transformations. E.g., @file{i386.md} contains
9041 an RTL template for the ordinary @code{sub} instruction---
9042 @code{*subsi_1}, and for the @code{sub} instruction with subsequent
9043 zero-extension---@code{*subsi_1_zext}. Such cases can be easily
9044 implemented by a single meta-template capable of generating a modified
9045 case based on the initial one:
9047 @findex define_subst
9049 (define_subst "@var{name}"
9050 [@var{input-template}]
9052 [@var{output-template}])
9054 @var{input-template} is a pattern describing the source RTL template,
9055 which will be transformed.
9057 @var{condition} is a C expression that is conjunct with the condition
9058 from the input-template to generate a condition to be used in the
9061 @var{output-template} is a pattern that will be used in the resulting
9064 @code{define_subst} mechanism is tightly coupled with the notion of the
9065 subst attribute (@pxref{Subst Iterators}). The use of
9066 @code{define_subst} is triggered by a reference to a subst attribute in
9067 the transforming RTL template. This reference initiates duplication of
9068 the source RTL template and substitution of the attributes with their
9069 values. The source RTL template is left unchanged, while the copy is
9070 transformed by @code{define_subst}. This transformation can fail in the
9071 case when the source RTL template is not matched against the
9072 input-template of the @code{define_subst}. In such case the copy is
9075 @code{define_subst} can be used only in @code{define_insn} and
9076 @code{define_expand}, it cannot be used in other expressions (e.g. in
9077 @code{define_insn_and_split}).
9080 * Define Subst Example:: Example of @code{define_subst} work.
9081 * Define Subst Pattern Matching:: Process of template comparison.
9082 * Define Subst Output Template:: Generation of output template.
9085 @node Define Subst Example
9086 @subsection @code{define_subst} Example
9087 @cindex define_subst
9089 To illustrate how @code{define_subst} works, let us examine a simple
9090 template transformation.
9092 Suppose there are two kinds of instructions: one that touches flags and
9093 the other that does not. The instructions of the second type could be
9094 generated with the following @code{define_subst}:
9097 (define_subst "add_clobber_subst"
9098 [(set (match_operand:SI 0 "" "")
9099 (match_operand:SI 1 "" ""))]
9103 (clobber (reg:CC FLAGS_REG))]
9106 This @code{define_subst} can be applied to any RTL pattern containing
9107 @code{set} of mode SI and generates a copy with clobber when it is
9110 Assume there is an RTL template for a @code{max} instruction to be used
9111 in @code{define_subst} mentioned above:
9114 (define_insn "maxsi"
9115 [(set (match_operand:SI 0 "register_operand" "=r")
9117 (match_operand:SI 1 "register_operand" "r")
9118 (match_operand:SI 2 "register_operand" "r")))]
9120 "max\t@{%2, %1, %0|%0, %1, %2@}"
9124 To mark the RTL template for @code{define_subst} application,
9125 subst-attributes are used. They should be declared in advance:
9128 (define_subst_attr "add_clobber_name" "add_clobber_subst" "_noclobber" "_clobber")
9131 Here @samp{add_clobber_name} is the attribute name,
9132 @samp{add_clobber_subst} is the name of the corresponding
9133 @code{define_subst}, the third argument (@samp{_noclobber}) is the
9134 attribute value that would be substituted into the unchanged version of
9135 the source RTL template, and the last argument (@samp{_clobber}) is the
9136 value that would be substituted into the second, transformed,
9137 version of the RTL template.
9139 Once the subst-attribute has been defined, it should be used in RTL
9140 templates which need to be processed by the @code{define_subst}. So,
9141 the original RTL template should be changed:
9144 (define_insn "maxsi<add_clobber_name>"
9145 [(set (match_operand:SI 0 "register_operand" "=r")
9147 (match_operand:SI 1 "register_operand" "r")
9148 (match_operand:SI 2 "register_operand" "r")))]
9150 "max\t@{%2, %1, %0|%0, %1, %2@}"
9154 The result of the @code{define_subst} usage would look like the following:
9157 (define_insn "maxsi_noclobber"
9158 [(set (match_operand:SI 0 "register_operand" "=r")
9160 (match_operand:SI 1 "register_operand" "r")
9161 (match_operand:SI 2 "register_operand" "r")))]
9163 "max\t@{%2, %1, %0|%0, %1, %2@}"
9165 (define_insn "maxsi_clobber"
9166 [(set (match_operand:SI 0 "register_operand" "=r")
9168 (match_operand:SI 1 "register_operand" "r")
9169 (match_operand:SI 2 "register_operand" "r")))
9170 (clobber (reg:CC FLAGS_REG))]
9172 "max\t@{%2, %1, %0|%0, %1, %2@}"
9176 @node Define Subst Pattern Matching
9177 @subsection Pattern Matching in @code{define_subst}
9178 @cindex define_subst
9180 All expressions, allowed in @code{define_insn} or @code{define_expand},
9181 are allowed in the input-template of @code{define_subst}, except
9182 @code{match_par_dup}, @code{match_scratch}, @code{match_parallel}. The
9183 meanings of expressions in the input-template were changed:
9185 @code{match_operand} matches any expression (possibly, a subtree in
9186 RTL-template), if modes of the @code{match_operand} and this expression
9187 are the same, or mode of the @code{match_operand} is @code{VOIDmode}, or
9188 this expression is @code{match_dup}, @code{match_op_dup}. If the
9189 expression is @code{match_operand} too, and predicate of
9190 @code{match_operand} from the input pattern is not empty, then the
9191 predicates are compared. That can be used for more accurate filtering
9192 of accepted RTL-templates.
9194 @code{match_operator} matches common operators (like @code{plus},
9195 @code{minus}), @code{unspec}, @code{unspec_volatile} operators and
9196 @code{match_operator}s from the original pattern if the modes match and
9197 @code{match_operator} from the input pattern has the same number of
9198 operands as the operator from the original pattern.
9200 @node Define Subst Output Template
9201 @subsection Generation of output template in @code{define_subst}
9202 @cindex define_subst
9204 If all necessary checks for @code{define_subst} application pass, a new
9205 RTL-pattern, based on the output-template, is created to replace the old
9206 template. Like in input-patterns, meanings of some RTL expressions are
9207 changed when they are used in output-patterns of a @code{define_subst}.
9208 Thus, @code{match_dup} is used for copying the whole expression from the
9209 original pattern, which matched corresponding @code{match_operand} from
9212 @code{match_dup N} is used in the output template to be replaced with
9213 the expression from the original pattern, which matched
9214 @code{match_operand N} from the input pattern. As a consequence,
9215 @code{match_dup} cannot be used to point to @code{match_operand}s from
9216 the output pattern, it should always refer to a @code{match_operand}
9217 from the input pattern.
9219 In the output template one can refer to the expressions from the
9220 original pattern and create new ones. For instance, some operands could
9221 be added by means of standard @code{match_operand}.
9223 After replacing @code{match_dup} with some RTL-subtree from the original
9224 pattern, it could happen that several @code{match_operand}s in the
9225 output pattern have the same indexes. It is unknown, how many and what
9226 indexes would be used in the expression which would replace
9227 @code{match_dup}, so such conflicts in indexes are inevitable. To
9228 overcome this issue, @code{match_operands} and @code{match_operators},
9229 which were introduced into the output pattern, are renumerated when all
9230 @code{match_dup}s are replaced.
9232 Number of alternatives in @code{match_operand}s introduced into the
9233 output template @code{M} could differ from the number of alternatives in
9234 the original pattern @code{N}, so in the resultant pattern there would
9235 be @code{N*M} alternatives. Thus, constraints from the original pattern
9236 would be duplicated @code{N} times, constraints from the output pattern
9237 would be duplicated @code{M} times, producing all possible combinations.
9241 @node Constant Definitions
9242 @section Constant Definitions
9243 @cindex constant definitions
9244 @findex define_constants
9246 Using literal constants inside instruction patterns reduces legibility and
9247 can be a maintenance problem.
9249 To overcome this problem, you may use the @code{define_constants}
9250 expression. It contains a vector of name-value pairs. From that
9251 point on, wherever any of the names appears in the MD file, it is as
9252 if the corresponding value had been written instead. You may use
9253 @code{define_constants} multiple times; each appearance adds more
9254 constants to the table. It is an error to redefine a constant with
9257 To come back to the a29k load multiple example, instead of
9261 [(match_parallel 0 "load_multiple_operation"
9262 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
9263 (match_operand:SI 2 "memory_operand" "m"))
9265 (clobber (reg:SI 179))])]
9281 [(match_parallel 0 "load_multiple_operation"
9282 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
9283 (match_operand:SI 2 "memory_operand" "m"))
9285 (clobber (reg:SI R_CR))])]
9290 The constants that are defined with a define_constant are also output
9291 in the insn-codes.h header file as #defines.
9293 @cindex enumerations
9294 @findex define_c_enum
9295 You can also use the machine description file to define enumerations.
9296 Like the constants defined by @code{define_constant}, these enumerations
9297 are visible to both the machine description file and the main C code.
9299 The syntax is as follows:
9302 (define_c_enum "@var{name}" [
9310 This definition causes the equivalent of the following C code to appear
9311 in @file{insn-constants.h}:
9318 @var{valuen} = @var{n}
9320 #define NUM_@var{cname}_VALUES (@var{n} + 1)
9323 where @var{cname} is the capitalized form of @var{name}.
9324 It also makes each @var{valuei} available in the machine description
9325 file, just as if it had been declared with:
9328 (define_constants [(@var{valuei} @var{i})])
9331 Each @var{valuei} is usually an upper-case identifier and usually
9332 begins with @var{cname}.
9334 You can split the enumeration definition into as many statements as
9335 you like. The above example is directly equivalent to:
9338 (define_c_enum "@var{name}" [@var{value0}])
9339 (define_c_enum "@var{name}" [@var{value1}])
9341 (define_c_enum "@var{name}" [@var{valuen}])
9344 Splitting the enumeration helps to improve the modularity of each
9345 individual @code{.md} file. For example, if a port defines its
9346 synchronization instructions in a separate @file{sync.md} file,
9347 it is convenient to define all synchronization-specific enumeration
9348 values in @file{sync.md} rather than in the main @file{.md} file.
9350 Some enumeration names have special significance to GCC:
9354 @findex unspec_volatile
9355 If an enumeration called @code{unspecv} is defined, GCC will use it
9356 when printing out @code{unspec_volatile} expressions. For example:
9359 (define_c_enum "unspecv" [
9364 causes GCC to print @samp{(unspec_volatile @dots{} 0)} as:
9367 (unspec_volatile ... UNSPECV_BLOCKAGE)
9372 If an enumeration called @code{unspec} is defined, GCC will use
9373 it when printing out @code{unspec} expressions. GCC will also use
9374 it when printing out @code{unspec_volatile} expressions unless an
9375 @code{unspecv} enumeration is also defined. You can therefore
9376 decide whether to keep separate enumerations for volatile and
9377 non-volatile expressions or whether to use the same enumeration
9382 @anchor{define_enum}
9383 Another way of defining an enumeration is to use @code{define_enum}:
9386 (define_enum "@var{name}" [
9394 This directive implies:
9397 (define_c_enum "@var{name}" [
9398 @var{cname}_@var{cvalue0}
9399 @var{cname}_@var{cvalue1}
9401 @var{cname}_@var{cvaluen}
9405 @findex define_enum_attr
9406 where @var{cvaluei} is the capitalized form of @var{valuei}.
9407 However, unlike @code{define_c_enum}, the enumerations defined
9408 by @code{define_enum} can be used in attribute specifications
9409 (@pxref{define_enum_attr}).
9414 @cindex iterators in @file{.md} files
9416 Ports often need to define similar patterns for more than one machine
9417 mode or for more than one rtx code. GCC provides some simple iterator
9418 facilities to make this process easier.
9421 * Mode Iterators:: Generating variations of patterns for different modes.
9422 * Code Iterators:: Doing the same for codes.
9423 * Int Iterators:: Doing the same for integers.
9424 * Subst Iterators:: Generating variations of patterns for define_subst.
9427 @node Mode Iterators
9428 @subsection Mode Iterators
9429 @cindex mode iterators in @file{.md} files
9431 Ports often need to define similar patterns for two or more different modes.
9436 If a processor has hardware support for both single and double
9437 floating-point arithmetic, the @code{SFmode} patterns tend to be
9438 very similar to the @code{DFmode} ones.
9441 If a port uses @code{SImode} pointers in one configuration and
9442 @code{DImode} pointers in another, it will usually have very similar
9443 @code{SImode} and @code{DImode} patterns for manipulating pointers.
9446 Mode iterators allow several patterns to be instantiated from one
9447 @file{.md} file template. They can be used with any type of
9448 rtx-based construct, such as a @code{define_insn},
9449 @code{define_split}, or @code{define_peephole2}.
9452 * Defining Mode Iterators:: Defining a new mode iterator.
9453 * Substitutions:: Combining mode iterators with substitutions
9454 * Examples:: Examples
9457 @node Defining Mode Iterators
9458 @subsubsection Defining Mode Iterators
9459 @findex define_mode_iterator
9461 The syntax for defining a mode iterator is:
9464 (define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") @dots{} (@var{moden} "@var{condn}")])
9467 This allows subsequent @file{.md} file constructs to use the mode suffix
9468 @code{:@var{name}}. Every construct that does so will be expanded
9469 @var{n} times, once with every use of @code{:@var{name}} replaced by
9470 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
9471 and so on. In the expansion for a particular @var{modei}, every
9472 C condition will also require that @var{condi} be true.
9477 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
9480 defines a new mode suffix @code{:P}. Every construct that uses
9481 @code{:P} will be expanded twice, once with every @code{:P} replaced
9482 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
9483 The @code{:SI} version will only apply if @code{Pmode == SImode} and
9484 the @code{:DI} version will only apply if @code{Pmode == DImode}.
9486 As with other @file{.md} conditions, an empty string is treated
9487 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
9488 to @code{@var{mode}}. For example:
9491 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
9494 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
9495 but that the @code{:SI} expansion has no such constraint.
9497 Iterators are applied in the order they are defined. This can be
9498 significant if two iterators are used in a construct that requires
9499 substitutions. @xref{Substitutions}.
9502 @subsubsection Substitution in Mode Iterators
9503 @findex define_mode_attr
9505 If an @file{.md} file construct uses mode iterators, each version of the
9506 construct will often need slightly different strings or modes. For
9511 When a @code{define_expand} defines several @code{add@var{m}3} patterns
9512 (@pxref{Standard Names}), each expander will need to use the
9513 appropriate mode name for @var{m}.
9516 When a @code{define_insn} defines several instruction patterns,
9517 each instruction will often use a different assembler mnemonic.
9520 When a @code{define_insn} requires operands with different modes,
9521 using an iterator for one of the operand modes usually requires a specific
9522 mode for the other operand(s).
9525 GCC supports such variations through a system of ``mode attributes''.
9526 There are two standard attributes: @code{mode}, which is the name of
9527 the mode in lower case, and @code{MODE}, which is the same thing in
9528 upper case. You can define other attributes using:
9531 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") @dots{} (@var{moden} "@var{valuen}")])
9534 where @var{name} is the name of the attribute and @var{valuei}
9535 is the value associated with @var{modei}.
9537 When GCC replaces some @var{:iterator} with @var{:mode}, it will scan
9538 each string and mode in the pattern for sequences of the form
9539 @code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a
9540 mode attribute. If the attribute is defined for @var{mode}, the whole
9541 @code{<@dots{}>} sequence will be replaced by the appropriate attribute
9544 For example, suppose an @file{.md} file has:
9547 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
9548 (define_mode_attr load [(SI "lw") (DI "ld")])
9551 If one of the patterns that uses @code{:P} contains the string
9552 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
9553 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
9556 Here is an example of using an attribute for a mode:
9559 (define_mode_iterator LONG [SI DI])
9560 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
9561 (define_insn @dots{}
9562 (sign_extend:LONG (match_operand:<LONG:SHORT> @dots{})) @dots{})
9565 The @code{@var{iterator}:} prefix may be omitted, in which case the
9566 substitution will be attempted for every iterator expansion.
9569 @subsubsection Mode Iterator Examples
9571 Here is an example from the MIPS port. It defines the following
9572 modes and attributes (among others):
9575 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
9576 (define_mode_attr d [(SI "") (DI "d")])
9579 and uses the following template to define both @code{subsi3}
9583 (define_insn "sub<mode>3"
9584 [(set (match_operand:GPR 0 "register_operand" "=d")
9585 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
9586 (match_operand:GPR 2 "register_operand" "d")))]
9589 [(set_attr "type" "arith")
9590 (set_attr "mode" "<MODE>")])
9593 This is exactly equivalent to:
9596 (define_insn "subsi3"
9597 [(set (match_operand:SI 0 "register_operand" "=d")
9598 (minus:SI (match_operand:SI 1 "register_operand" "d")
9599 (match_operand:SI 2 "register_operand" "d")))]
9602 [(set_attr "type" "arith")
9603 (set_attr "mode" "SI")])
9605 (define_insn "subdi3"
9606 [(set (match_operand:DI 0 "register_operand" "=d")
9607 (minus:DI (match_operand:DI 1 "register_operand" "d")
9608 (match_operand:DI 2 "register_operand" "d")))]
9611 [(set_attr "type" "arith")
9612 (set_attr "mode" "DI")])
9615 @node Code Iterators
9616 @subsection Code Iterators
9617 @cindex code iterators in @file{.md} files
9618 @findex define_code_iterator
9619 @findex define_code_attr
9621 Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}.
9626 (define_code_iterator @var{name} [(@var{code1} "@var{cond1}") @dots{} (@var{coden} "@var{condn}")])
9629 defines a pseudo rtx code @var{name} that can be instantiated as
9630 @var{codei} if condition @var{condi} is true. Each @var{codei}
9631 must have the same rtx format. @xref{RTL Classes}.
9633 As with mode iterators, each pattern that uses @var{name} will be
9634 expanded @var{n} times, once with all uses of @var{name} replaced by
9635 @var{code1}, once with all uses replaced by @var{code2}, and so on.
9636 @xref{Defining Mode Iterators}.
9638 It is possible to define attributes for codes as well as for modes.
9639 There are two standard code attributes: @code{code}, the name of the
9640 code in lower case, and @code{CODE}, the name of the code in upper case.
9641 Other attributes are defined using:
9644 (define_code_attr @var{name} [(@var{code1} "@var{value1}") @dots{} (@var{coden} "@var{valuen}")])
9647 Here's an example of code iterators in action, taken from the MIPS port:
9650 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
9651 eq ne gt ge lt le gtu geu ltu leu])
9653 (define_expand "b<code>"
9655 (if_then_else (any_cond:CC (cc0)
9657 (label_ref (match_operand 0 ""))
9661 gen_conditional_branch (operands, <CODE>);
9666 This is equivalent to:
9669 (define_expand "bunordered"
9671 (if_then_else (unordered:CC (cc0)
9673 (label_ref (match_operand 0 ""))
9677 gen_conditional_branch (operands, UNORDERED);
9681 (define_expand "bordered"
9683 (if_then_else (ordered:CC (cc0)
9685 (label_ref (match_operand 0 ""))
9689 gen_conditional_branch (operands, ORDERED);
9697 @subsection Int Iterators
9698 @cindex int iterators in @file{.md} files
9699 @findex define_int_iterator
9700 @findex define_int_attr
9702 Int iterators operate in a similar way to code iterators. @xref{Code Iterators}.
9707 (define_int_iterator @var{name} [(@var{int1} "@var{cond1}") @dots{} (@var{intn} "@var{condn}")])
9710 defines a pseudo integer constant @var{name} that can be instantiated as
9711 @var{inti} if condition @var{condi} is true. Each @var{int}
9712 must have the same rtx format. @xref{RTL Classes}. Int iterators can appear
9713 in only those rtx fields that have 'i' as the specifier. This means that
9714 each @var{int} has to be a constant defined using define_constant or
9717 As with mode and code iterators, each pattern that uses @var{name} will be
9718 expanded @var{n} times, once with all uses of @var{name} replaced by
9719 @var{int1}, once with all uses replaced by @var{int2}, and so on.
9720 @xref{Defining Mode Iterators}.
9722 It is possible to define attributes for ints as well as for codes and modes.
9723 Attributes are defined using:
9726 (define_int_attr @var{name} [(@var{int1} "@var{value1}") @dots{} (@var{intn} "@var{valuen}")])
9729 Here's an example of int iterators in action, taken from the ARM port:
9732 (define_int_iterator QABSNEG [UNSPEC_VQABS UNSPEC_VQNEG])
9734 (define_int_attr absneg [(UNSPEC_VQABS "abs") (UNSPEC_VQNEG "neg")])
9736 (define_insn "neon_vq<absneg><mode>"
9737 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
9738 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
9739 (match_operand:SI 2 "immediate_operand" "i")]
9742 "vq<absneg>.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
9743 [(set_attr "type" "neon_vqneg_vqabs")]
9748 This is equivalent to:
9751 (define_insn "neon_vqabs<mode>"
9752 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
9753 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
9754 (match_operand:SI 2 "immediate_operand" "i")]
9757 "vqabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
9758 [(set_attr "type" "neon_vqneg_vqabs")]
9761 (define_insn "neon_vqneg<mode>"
9762 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
9763 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
9764 (match_operand:SI 2 "immediate_operand" "i")]
9767 "vqneg.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
9768 [(set_attr "type" "neon_vqneg_vqabs")]
9773 @node Subst Iterators
9774 @subsection Subst Iterators
9775 @cindex subst iterators in @file{.md} files
9776 @findex define_subst
9777 @findex define_subst_attr
9779 Subst iterators are special type of iterators with the following
9780 restrictions: they could not be declared explicitly, they always have
9781 only two values, and they do not have explicit dedicated name.
9782 Subst-iterators are triggered only when corresponding subst-attribute is
9783 used in RTL-pattern.
9785 Subst iterators transform templates in the following way: the templates
9786 are duplicated, the subst-attributes in these templates are replaced
9787 with the corresponding values, and a new attribute is implicitly added
9788 to the given @code{define_insn}/@code{define_expand}. The name of the
9789 added attribute matches the name of @code{define_subst}. Such
9790 attributes are declared implicitly, and it is not allowed to have a
9791 @code{define_attr} named as a @code{define_subst}.
9793 Each subst iterator is linked to a @code{define_subst}. It is declared
9794 implicitly by the first appearance of the corresponding
9795 @code{define_subst_attr}, and it is not allowed to define it explicitly.
9797 Declarations of subst-attributes have the following syntax:
9799 @findex define_subst_attr
9801 (define_subst_attr "@var{name}"
9803 "@var{no-subst-value}"
9804 "@var{subst-applied-value}")
9807 @var{name} is a string with which the given subst-attribute could be
9810 @var{subst-name} shows which @code{define_subst} should be applied to an
9811 RTL-template if the given subst-attribute is present in the
9814 @var{no-subst-value} is a value with which subst-attribute would be
9815 replaced in the first copy of the original RTL-template.
9817 @var{subst-applied-value} is a value with which subst-attribute would be
9818 replaced in the second copy of the original RTL-template.