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PR sanitizer/82595
[official-gcc.git] / gcc / config / bfin / bfin.h
blob787600f3308d3294215e0e9311274d7ee7924252
1 /* Definitions for the Blackfin port.
2 Copyright (C) 2005-2017 Free Software Foundation, Inc.
3 Contributed by Analog Devices.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21 #ifndef _BFIN_CONFIG
22 #define _BFIN_CONFIG
23
24 #ifndef BFIN_OPTS_H
25 #include "config/bfin/bfin-opts.h"
26 #endif
27
28 #define OBJECT_FORMAT_ELF
29
30 #define BRT 1
31 #define BRF 0
32
33 /* Predefinition in the preprocessor for this target machine */
34 #ifndef TARGET_CPU_CPP_BUILTINS
35 #define TARGET_CPU_CPP_BUILTINS() \
36 do \
37 { \
38 builtin_define_std ("bfin"); \
39 builtin_define_std ("BFIN"); \
40 builtin_define ("__ADSPBLACKFIN__"); \
41 builtin_define ("__ADSPLPBLACKFIN__"); \
42 \
43 switch (bfin_cpu_type) \
44 { \
45 case BFIN_CPU_UNKNOWN: \
46 break; \
47 case BFIN_CPU_BF512: \
48 builtin_define ("__ADSPBF512__"); \
49 builtin_define ("__ADSPBF51x__"); \
50 break; \
51 case BFIN_CPU_BF514: \
52 builtin_define ("__ADSPBF514__"); \
53 builtin_define ("__ADSPBF51x__"); \
54 break; \
55 case BFIN_CPU_BF516: \
56 builtin_define ("__ADSPBF516__"); \
57 builtin_define ("__ADSPBF51x__"); \
58 break; \
59 case BFIN_CPU_BF518: \
60 builtin_define ("__ADSPBF518__"); \
61 builtin_define ("__ADSPBF51x__"); \
62 break; \
63 case BFIN_CPU_BF522: \
64 builtin_define ("__ADSPBF522__"); \
65 builtin_define ("__ADSPBF52x__"); \
66 break; \
67 case BFIN_CPU_BF523: \
68 builtin_define ("__ADSPBF523__"); \
69 builtin_define ("__ADSPBF52x__"); \
70 break; \
71 case BFIN_CPU_BF524: \
72 builtin_define ("__ADSPBF524__"); \
73 builtin_define ("__ADSPBF52x__"); \
74 break; \
75 case BFIN_CPU_BF525: \
76 builtin_define ("__ADSPBF525__"); \
77 builtin_define ("__ADSPBF52x__"); \
78 break; \
79 case BFIN_CPU_BF526: \
80 builtin_define ("__ADSPBF526__"); \
81 builtin_define ("__ADSPBF52x__"); \
82 break; \
83 case BFIN_CPU_BF527: \
84 builtin_define ("__ADSPBF527__"); \
85 builtin_define ("__ADSPBF52x__"); \
86 break; \
87 case BFIN_CPU_BF531: \
88 builtin_define ("__ADSPBF531__"); \
89 break; \
90 case BFIN_CPU_BF532: \
91 builtin_define ("__ADSPBF532__"); \
92 break; \
93 case BFIN_CPU_BF533: \
94 builtin_define ("__ADSPBF533__"); \
95 break; \
96 case BFIN_CPU_BF534: \
97 builtin_define ("__ADSPBF534__"); \
98 break; \
99 case BFIN_CPU_BF536: \
100 builtin_define ("__ADSPBF536__"); \
101 break; \
102 case BFIN_CPU_BF537: \
103 builtin_define ("__ADSPBF537__"); \
104 break; \
105 case BFIN_CPU_BF538: \
106 builtin_define ("__ADSPBF538__"); \
107 break; \
108 case BFIN_CPU_BF539: \
109 builtin_define ("__ADSPBF539__"); \
110 break; \
111 case BFIN_CPU_BF542M: \
112 builtin_define ("__ADSPBF542M__"); \
113 /* FALLTHRU */ \
114 case BFIN_CPU_BF542: \
115 builtin_define ("__ADSPBF542__"); \
116 builtin_define ("__ADSPBF54x__"); \
117 break; \
118 case BFIN_CPU_BF544M: \
119 builtin_define ("__ADSPBF544M__"); \
120 /* FALLTHRU */ \
121 case BFIN_CPU_BF544: \
122 builtin_define ("__ADSPBF544__"); \
123 builtin_define ("__ADSPBF54x__"); \
124 break; \
125 case BFIN_CPU_BF547M: \
126 builtin_define ("__ADSPBF547M__"); \
127 /* FALLTHRU */ \
128 case BFIN_CPU_BF547: \
129 builtin_define ("__ADSPBF547__"); \
130 builtin_define ("__ADSPBF54x__"); \
131 break; \
132 case BFIN_CPU_BF548M: \
133 builtin_define ("__ADSPBF548M__"); \
134 /* FALLTHRU */ \
135 case BFIN_CPU_BF548: \
136 builtin_define ("__ADSPBF548__"); \
137 builtin_define ("__ADSPBF54x__"); \
138 break; \
139 case BFIN_CPU_BF549M: \
140 builtin_define ("__ADSPBF549M__"); \
141 /* FALLTHRU */ \
142 case BFIN_CPU_BF549: \
143 builtin_define ("__ADSPBF549__"); \
144 builtin_define ("__ADSPBF54x__"); \
145 break; \
146 case BFIN_CPU_BF561: \
147 builtin_define ("__ADSPBF561__"); \
148 break; \
149 case BFIN_CPU_BF592: \
150 builtin_define ("__ADSPBF592__"); \
151 builtin_define ("__ADSPBF59x__"); \
152 break; \
153 } \
154 \
155 if (bfin_si_revision != -1) \
156 { \
157 /* space of 0xnnnn and a NUL */ \
158 char *buf = XALLOCAVEC (char, 7); \
159 \
160 sprintf (buf, "0x%04x", bfin_si_revision); \
161 builtin_define_with_value ("__SILICON_REVISION__", buf, 0); \
162 } \
163 \
164 if (bfin_workarounds) \
165 builtin_define ("__WORKAROUNDS_ENABLED"); \
166 if (ENABLE_WA_SPECULATIVE_LOADS) \
167 builtin_define ("__WORKAROUND_SPECULATIVE_LOADS"); \
168 if (ENABLE_WA_SPECULATIVE_SYNCS) \
169 builtin_define ("__WORKAROUND_SPECULATIVE_SYNCS"); \
170 if (ENABLE_WA_INDIRECT_CALLS) \
171 builtin_define ("__WORKAROUND_INDIRECT_CALLS"); \
172 if (ENABLE_WA_RETS) \
173 builtin_define ("__WORKAROUND_RETS"); \
174 \
175 if (TARGET_FDPIC) \
176 { \
177 builtin_define ("__BFIN_FDPIC__"); \
178 builtin_define ("__FDPIC__"); \
179 } \
180 if (TARGET_ID_SHARED_LIBRARY \
181 && !TARGET_SEP_DATA) \
182 builtin_define ("__ID_SHARED_LIB__"); \
183 if (flag_no_builtin) \
184 builtin_define ("__NO_BUILTIN"); \
185 if (TARGET_MULTICORE) \
186 builtin_define ("__BFIN_MULTICORE"); \
187 if (TARGET_COREA) \
188 builtin_define ("__BFIN_COREA"); \
189 if (TARGET_COREB) \
190 builtin_define ("__BFIN_COREB"); \
191 if (TARGET_SDRAM) \
192 builtin_define ("__BFIN_SDRAM"); \
193 } \
194 while (0)
195 #endif
196
197 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\
198 %{mleaf-id-shared-library:%{!mid-shared-library:-mid-shared-library}} \
199 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\
200 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \
201 "
202 #ifndef SUBTARGET_DRIVER_SELF_SPECS
203 # define SUBTARGET_DRIVER_SELF_SPECS
204 #endif
205
206 #define LINK_GCC_C_SEQUENCE_SPEC "\
207 %{mfast-fp:-lbffastfp} %G %L %{mfast-fp:-lbffastfp} %G \
208 "
209
210 #undef ASM_SPEC
211 #define ASM_SPEC "\
212 %{mno-fdpic:-mnopic} %{mfdpic}"
213
214 #define LINK_SPEC "\
215 %{h*} %{v:-V} \
216 %{mfdpic:-melf32bfinfd -z text} \
217 %{static:-dn -Bstatic} \
218 %{shared:-G -Bdynamic} \
219 %{symbolic:-Bsymbolic} \
220 -init __init -fini __fini "
221
222 /* Generate DSP instructions, like DSP halfword loads */
223 #define TARGET_DSP (1)
224
225 #define TARGET_DEFAULT 0
226
227 /* Maximum number of library ids we permit */
228 #define MAX_LIBRARY_ID 255
229
230 extern const char *bfin_library_id_string;
231
232 #define FUNCTION_MODE SImode
233 #define Pmode SImode
234
235 /* store-condition-codes instructions store 0 for false
236 This is the value stored for true. */
237 #define STORE_FLAG_VALUE 1
238
239 /* Define this if pushing a word on the stack
240 makes the stack pointer a smaller address. */
241 #define STACK_GROWS_DOWNWARD 1
242
243 #define STACK_PUSH_CODE PRE_DEC
244
245 /* Define this to nonzero if the nominal address of the stack frame
246 is at the high-address end of the local variables;
247 that is, each additional local variable allocated
248 goes at a more negative offset in the frame. */
249 #define FRAME_GROWS_DOWNWARD 1
250
251 /* We define a dummy ARGP register; the parameters start at offset 0 from
252 it. */
253 #define FIRST_PARM_OFFSET(DECL) 0
254
255 /* Offset within stack frame to start allocating local variables at.
256 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
257 first local allocated. Otherwise, it is the offset to the BEGINNING
258 of the first local allocated. */
259 #define STARTING_FRAME_OFFSET 0
260
261 /* Register to use for pushing function arguments. */
262 #define STACK_POINTER_REGNUM REG_P6
263
264 /* Base register for access to local variables of the function. */
265 #define FRAME_POINTER_REGNUM REG_P7
266
267 /* A dummy register that will be eliminated to either FP or SP. */
268 #define ARG_POINTER_REGNUM REG_ARGP
269
270 /* `PIC_OFFSET_TABLE_REGNUM'
271 The register number of the register used to address a table of
272 static data addresses in memory. In some cases this register is
273 defined by a processor's "application binary interface" (ABI).
274 When this macro is defined, RTL is generated for this register
275 once, as with the stack pointer and frame pointer registers. If
276 this macro is not defined, it is up to the machine-dependent files
277 to allocate such a register (if necessary). */
278 #define PIC_OFFSET_TABLE_REGNUM (REG_P5)
279
280 #define FDPIC_FPTR_REGNO REG_P1
281 #define FDPIC_REGNO REG_P3
282 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO)
283
284 /* A static chain register for nested functions. We need to use a
285 call-clobbered register for this. */
286 #define STATIC_CHAIN_REGNUM REG_P2
287
288 /* Define this if functions should assume that stack space has been
289 allocated for arguments even when their values are passed in
290 registers.
291
292 The value of this macro is the size, in bytes, of the area reserved for
293 arguments passed in registers.
294
295 This space can either be allocated by the caller or be a part of the
296 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
297 says which. */
298 #define FIXED_STACK_AREA 12
299 #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA
300
301 /* Define this if the above stack space is to be considered part of the
302 * space allocated by the caller. */
303 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
304
305 /* Define this if the maximum size of all the outgoing args is to be
306 accumulated and pushed during the prologue. The amount can be
307 found in the variable crtl->outgoing_args_size. */
308 #define ACCUMULATE_OUTGOING_ARGS 1
309
310 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */
311
312 /* If defined, a C expression to compute the alignment for a local
313 variable. TYPE is the data type, and ALIGN is the alignment that
314 the object would ordinarily have. The value of this macro is used
315 instead of that alignment to align the object.
316
317 If this macro is not defined, then ALIGN is used.
318
319 One use of this macro is to increase alignment of medium-size
320 data to make it all fit in fewer cache lines. */
321
322 #define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN))
323
324 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18)
325 \f
326 /* Definitions for register eliminations.
327
328 This is an array of structures. Each structure initializes one pair
329 of eliminable registers. The "from" register number is given first,
330 followed by "to". Eliminations of the same "from" register are listed
331 in order of preference.
332
333 There are two registers that can always be eliminated on the i386.
334 The frame pointer and the arg pointer can be replaced by either the
335 hard frame pointer or to the stack pointer, depending upon the
336 circumstances. The hard frame pointer is not used before reload and
337 so it is not eligible for elimination. */
338
339 #define ELIMINABLE_REGS \
340 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
341 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
342 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \
343
344 /* Define the offset between two registers, one to be eliminated, and the other
345 its replacement, at the start of a routine. */
346
347 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
348 ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO)))
349 \f
350 /* This processor has
351 8 data register for doing arithmetic
352 8 pointer register for doing addressing, including
353 1 stack pointer P6
354 1 frame pointer P7
355 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3)
356 1 condition code flag register CC
357 5 return address registers RETS/I/X/N/E
358 1 arithmetic status register (ASTAT). */
359
360 #define FIRST_PSEUDO_REGISTER 50
361
362 #define D_REGNO_P(X) ((X) <= REG_R7)
363 #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7)
364 #define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3)
365 #define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X))
366 #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3)
367 #define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X)))
368 #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X)))
369 #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X)))
370 #define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X)))
371
372 #define REGISTER_NAMES { \
373 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \
374 "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \
375 "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \
376 "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \
377 "A0", "A1", \
378 "CC", \
379 "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \
380 "ARGP", \
381 "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \
382 }
383
384 #define SHORT_REGISTER_NAMES { \
385 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \
386 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \
387 "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \
388 "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", }
389
390 #define HIGH_REGISTER_NAMES { \
391 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \
392 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \
393 "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \
394 "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", }
395
396 #define DREGS_PAIR_NAMES { \
397 "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, }
398
399 #define BYTE_REGISTER_NAMES { \
400 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", }
401
402
403 /* 1 for registers that have pervasive standard uses
404 and are not available for the register allocator. */
405
406 #define FIXED_REGISTERS \
407 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
408 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
409 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
410 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \
411 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
412 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
413 /*lb0/1 */ \
414 1, 1 \
415 }
416
417 /* 1 for registers not available across function calls.
418 These must include the FIXED_REGISTERS and also any
419 registers that can be used without being saved.
420 The latter must include the registers where values are returned
421 and the register where structure-value addresses are passed.
422 Aside from that, you can include as many other registers as you like. */
423
424 #define CALL_USED_REGISTERS \
425 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
426 { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \
427 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
428 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
429 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
430 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
431 /*lb0/1 */ \
432 1, 1 \
433 }
434
435 /* Order in which to allocate registers. Each register must be
436 listed once, even those in FIXED_REGISTERS. List frame pointer
437 late and fixed registers last. Note that, in general, we prefer
438 registers listed in CALL_USED_REGISTERS, keeping the others
439 available for storage of persistent values. */
440
441 #define REG_ALLOC_ORDER \
442 { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \
443 REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \
444 REG_A0, REG_A1, \
445 REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \
446 REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \
447 REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \
448 REG_ASTAT, REG_SEQSTAT, REG_USP, \
449 REG_CC, REG_ARGP, \
450 REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \
451 }
452
453 /* Define the classes of registers for register constraints in the
454 machine description. Also define ranges of constants.
455
456 One of the classes must always be named ALL_REGS and include all hard regs.
457 If there is more than one class, another class must be named NO_REGS
458 and contain no registers.
459
460 The name GENERAL_REGS must be the name of a class (or an alias for
461 another name such as ALL_REGS). This is the class of registers
462 that is allowed by "g" or "r" in a register constraint.
463 Also, registers outside this class are allocated only when
464 instructions express preferences for them.
465
466 The classes must be numbered in nondecreasing order; that is,
467 a larger-numbered class must never be contained completely
468 in a smaller-numbered class.
469
470 For any two classes, it is very desirable that there be another
471 class that represents their union. */
472
473
474 enum reg_class
475 {
476 NO_REGS,
477 IREGS,
478 BREGS,
479 LREGS,
480 MREGS,
481 CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */
482 DAGREGS,
483 EVEN_AREGS,
484 ODD_AREGS,
485 AREGS,
486 CCREGS,
487 EVEN_DREGS,
488 ODD_DREGS,
489 D0REGS,
490 D1REGS,
491 D2REGS,
492 D3REGS,
493 D4REGS,
494 D5REGS,
495 D6REGS,
496 D7REGS,
497 DREGS,
498 P0REGS,
499 FDPIC_REGS,
500 FDPIC_FPTR_REGS,
501 PREGS_CLOBBERED,
502 PREGS,
503 IPREGS,
504 DPREGS,
505 MOST_REGS,
506 LT_REGS,
507 LC_REGS,
508 LB_REGS,
509 PROLOGUE_REGS,
510 NON_A_CC_REGS,
511 ALL_REGS, LIM_REG_CLASSES
512 };
513
514 #define N_REG_CLASSES ((int)LIM_REG_CLASSES)
515
516 #define GENERAL_REGS DPREGS
517
518 /* Give names of register classes as strings for dump file. */
519
520 #define REG_CLASS_NAMES \
521 { "NO_REGS", \
522 "IREGS", \
523 "BREGS", \
524 "LREGS", \
525 "MREGS", \
526 "CIRCREGS", \
527 "DAGREGS", \
528 "EVEN_AREGS", \
529 "ODD_AREGS", \
530 "AREGS", \
531 "CCREGS", \
532 "EVEN_DREGS", \
533 "ODD_DREGS", \
534 "D0REGS", \
535 "D1REGS", \
536 "D2REGS", \
537 "D3REGS", \
538 "D4REGS", \
539 "D5REGS", \
540 "D6REGS", \
541 "D7REGS", \
542 "DREGS", \
543 "P0REGS", \
544 "FDPIC_REGS", \
545 "FDPIC_FPTR_REGS", \
546 "PREGS_CLOBBERED", \
547 "PREGS", \
548 "IPREGS", \
549 "DPREGS", \
550 "MOST_REGS", \
551 "LT_REGS", \
552 "LC_REGS", \
553 "LB_REGS", \
554 "PROLOGUE_REGS", \
555 "NON_A_CC_REGS", \
556 "ALL_REGS" }
557
558 /* An initializer containing the contents of the register classes, as integers
559 which are bit masks. The Nth integer specifies the contents of class N.
560 The way the integer MASK is interpreted is that register R is in the class
561 if `MASK & (1 << R)' is 1.
562
563 When the machine has more than 32 registers, an integer does not suffice.
564 Then the integers are replaced by sub-initializers, braced groupings
565 containing several integers. Each sub-initializer must be suitable as an
566 initializer for the type `HARD_REG_SET' which is defined in
567 `hard-reg-set.h'. */
568
569 /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use
570 MOST_REGS as the union of DPREGS and DAGREGS. */
571
572 #define REG_CLASS_CONTENTS \
573 /* 31 - 0 63-32 */ \
574 { { 0x00000000, 0 }, /* NO_REGS */ \
575 { 0x000f0000, 0 }, /* IREGS */ \
576 { 0x00f00000, 0 }, /* BREGS */ \
577 { 0x0f000000, 0 }, /* LREGS */ \
578 { 0xf0000000, 0 }, /* MREGS */ \
579 { 0x0fff0000, 0 }, /* CIRCREGS */ \
580 { 0xffff0000, 0 }, /* DAGREGS */ \
581 { 0x00000000, 0x1 }, /* EVEN_AREGS */ \
582 { 0x00000000, 0x2 }, /* ODD_AREGS */ \
583 { 0x00000000, 0x3 }, /* AREGS */ \
584 { 0x00000000, 0x4 }, /* CCREGS */ \
585 { 0x00000055, 0 }, /* EVEN_DREGS */ \
586 { 0x000000aa, 0 }, /* ODD_DREGS */ \
587 { 0x00000001, 0 }, /* D0REGS */ \
588 { 0x00000002, 0 }, /* D1REGS */ \
589 { 0x00000004, 0 }, /* D2REGS */ \
590 { 0x00000008, 0 }, /* D3REGS */ \
591 { 0x00000010, 0 }, /* D4REGS */ \
592 { 0x00000020, 0 }, /* D5REGS */ \
593 { 0x00000040, 0 }, /* D6REGS */ \
594 { 0x00000080, 0 }, /* D7REGS */ \
595 { 0x000000ff, 0 }, /* DREGS */ \
596 { 0x00000100, 0x000 }, /* P0REGS */ \
597 { 0x00000800, 0x000 }, /* FDPIC_REGS */ \
598 { 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \
599 { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \
600 { 0x0000ff00, 0x800 }, /* PREGS */ \
601 { 0x000fff00, 0x800 }, /* IPREGS */ \
602 { 0x0000ffff, 0x800 }, /* DPREGS */ \
603 { 0xffffffff, 0x800 }, /* MOST_REGS */\
604 { 0x00000000, 0x3000 }, /* LT_REGS */\
605 { 0x00000000, 0xc000 }, /* LC_REGS */\
606 { 0x00000000, 0x30000 }, /* LB_REGS */\
607 { 0x00000000, 0x3f7f8 }, /* PROLOGUE_REGS */\
608 { 0xffffffff, 0x3fff8 }, /* NON_A_CC_REGS */\
609 { 0xffffffff, 0x3ffff }} /* ALL_REGS */
610
611 #define IREG_POSSIBLE_P(OUTER) \
612 ((OUTER) == POST_INC || (OUTER) == PRE_INC \
613 || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \
614 || (OUTER) == MEM || (OUTER) == ADDRESS)
615
616 #define MODE_CODE_BASE_REG_CLASS(MODE, AS, OUTER, INDEX) \
617 ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS)
618
619 #define INDEX_REG_CLASS PREGS
620
621 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \
622 (P_REGNO_P (X) || (X) == REG_ARGP \
623 || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \
624 && I_REGNO_P (X)))
625
626 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \
627 ((X) >= FIRST_PSEUDO_REGISTER \
628 || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX))
629
630 #ifdef REG_OK_STRICT
631 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, AS, OUTER, INDEX) \
632 REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)
633 #else
634 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, AS, OUTER, INDEX) \
635 REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX)
636 #endif
637
638 #define REGNO_OK_FOR_INDEX_P(X) 0
639
640 /* The same information, inverted:
641 Return the class number of the smallest class containing
642 reg number REGNO. This could be a conditional expression
643 or could index an array. */
644
645 #define REGNO_REG_CLASS(REGNO) \
646 ((REGNO) == REG_R0 ? D0REGS \
647 : (REGNO) == REG_R1 ? D1REGS \
648 : (REGNO) == REG_R2 ? D2REGS \
649 : (REGNO) == REG_R3 ? D3REGS \
650 : (REGNO) == REG_R4 ? D4REGS \
651 : (REGNO) == REG_R5 ? D5REGS \
652 : (REGNO) == REG_R6 ? D6REGS \
653 : (REGNO) == REG_R7 ? D7REGS \
654 : (REGNO) == REG_P0 ? P0REGS \
655 : (REGNO) < REG_I0 ? PREGS \
656 : (REGNO) == REG_ARGP ? PREGS \
657 : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \
658 : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \
659 : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \
660 : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \
661 : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \
662 : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \
663 : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \
664 : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \
665 : (REGNO) == REG_CC ? CCREGS \
666 : (REGNO) >= REG_RETS ? PROLOGUE_REGS \
667 : NO_REGS)
668
669 /* When this hook returns true for MODE, the compiler allows
670 registers explicitly used in the rtl to be used as spill registers
671 but prevents the compiler from extending the lifetime of these
672 registers. */
673 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
674
675 /* Return the maximum number of consecutive registers
676 needed to represent mode MODE in a register of class CLASS. */
677 #define CLASS_MAX_NREGS(CLASS, MODE) \
678 ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \
679 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
680
681 /* A C expression that is nonzero if hard register TO can be
682 considered for use as a rename register for FROM register */
683 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO)
684
685 /* `PREFERRED_RELOAD_CLASS (X, CLASS)'
686 A C expression that places additional restrictions on the register
687 class to use when it is necessary to copy value X into a register
688 in class CLASS. The value is a register class; perhaps CLASS, or
689 perhaps another, smaller class. */
690 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
691 (GET_CODE (X) == POST_INC \
692 || GET_CODE (X) == POST_DEC \
693 || GET_CODE (X) == PRE_DEC ? PREGS : (CLASS))
694
695 /* Function Calling Conventions. */
696
697 /* The type of the current function; normal functions are of type
698 SUBROUTINE. */
699 typedef enum {
700 SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER
701 } e_funkind;
702 #define FUNCTION_RETURN_REGISTERS { REG_RETS, REG_RETI, REG_RETX, REG_RETN }
703
704 #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 }
705
706 /* Flags for the call/call_value rtl operations set up by function_arg */
707 #define CALL_NORMAL 0x00000000 /* no special processing */
708 #define CALL_LONG 0x00000001 /* always call indirect */
709 #define CALL_SHORT 0x00000002 /* always call by symbol */
710
711 typedef struct {
712 int words; /* # words passed so far */
713 int nregs; /* # registers available for passing */
714 int *arg_regs; /* array of register -1 terminated */
715 int call_cookie; /* Do special things for this call */
716 } CUMULATIVE_ARGS;
717
718 #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO)
719
720
721 /* Initialize a variable CUM of type CUMULATIVE_ARGS
722 for a call to a function whose data type is FNTYPE.
723 For a library call, FNTYPE is 0. */
724 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \
725 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
726
727 /* Define how to find the value returned by a function.
728 VALTYPE is the data type of the value (as a tree).
729 If the precise function being called is known, FUNC is its FUNCTION_DECL;
730 otherwise, FUNC is 0.
731 */
732
733 #define VALUE_REGNO(MODE) (REG_R0)
734
735 #define FUNCTION_VALUE(VALTYPE, FUNC) \
736 gen_rtx_REG (TYPE_MODE (VALTYPE), \
737 VALUE_REGNO(TYPE_MODE(VALTYPE)))
738
739 /* Define how to find the value returned by a library function
740 assuming the value has mode MODE. */
741
742 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE))
743
744 #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0)
745
746 #define DEFAULT_PCC_STRUCT_RETURN 0
747
748 /* Before the prologue, the return address is in the RETS register. */
749 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS)
750
751 #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT)
752
753 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS)
754
755 /* Call instructions don't modify the stack pointer on the Blackfin. */
756 #define INCOMING_FRAME_SP_OFFSET 0
757
758 /* Describe how we implement __builtin_eh_return. */
759 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
760 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2)
761 #define EH_RETURN_HANDLER_RTX \
762 gen_frame_mem (Pmode, plus_constant (Pmode, frame_pointer_rtx, \
763 UNITS_PER_WORD))
764
765 /* Addressing Modes */
766
767 /* A number, the maximum number of registers that can appear in a
768 valid memory address. Note that it is up to you to specify a
769 value equal to the maximum number that `TARGET_LEGITIMATE_ADDRESS_P'
770 would ever accept. */
771 #define MAX_REGS_PER_ADDRESS 1
772
773 #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \
774 (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode)
775
776 #define HAVE_POST_INCREMENT 1
777 #define HAVE_POST_DECREMENT 1
778 #define HAVE_PRE_DECREMENT 1
779
780 /* `LEGITIMATE_PIC_OPERAND_P (X)'
781 A C expression that is nonzero if X is a legitimate immediate
782 operand on the target machine when generating position independent
783 code. You can assume that X satisfies `CONSTANT_P', so you need
784 not check this. You can also assume FLAG_PIC is true, so you need
785 not check it either. You need not define this macro if all
786 constants (including `SYMBOL_REF') can be immediate operands when
787 generating position independent code. */
788 #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X)
789
790 #define SYMBOLIC_CONST(X) \
791 (GET_CODE (X) == SYMBOL_REF \
792 || GET_CODE (X) == LABEL_REF \
793 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
794
795 #define NOTICE_UPDATE_CC(EXPR, INSN) 0
796
797 /* Max number of bytes we can move from memory to memory
798 in one reasonably fast instruction. */
799 #define MOVE_MAX UNITS_PER_WORD
800
801 /* If a memory-to-memory move would take MOVE_RATIO or more simple
802 move-instruction pairs, we will do a movmem or libcall instead. */
803
804 #define MOVE_RATIO(speed) 5
805
806 /* STORAGE LAYOUT: target machine storage layout
807 Define this macro as a C expression which is nonzero if accessing
808 less than a word of memory (i.e. a `char' or a `short') is no
809 faster than accessing a word of memory, i.e., if such access
810 require more than one instruction or if there is no difference in
811 cost between byte and (aligned) word loads.
812
813 When this macro is not defined, the compiler will access a field by
814 finding the smallest containing object; when it is defined, a
815 fullword load will be used if alignment permits. Unless bytes
816 accesses are faster than word accesses, using word accesses is
817 preferable since it may eliminate subsequent memory access if
818 subsequent accesses occur to other fields in the same word of the
819 structure, but to different bytes. */
820 #define SLOW_BYTE_ACCESS 0
821 #define SLOW_SHORT_ACCESS 0
822
823 /* Define this if most significant bit is lowest numbered
824 in instructions that operate on numbered bit-fields. */
825 #define BITS_BIG_ENDIAN 0
826
827 /* Define this if most significant byte of a word is the lowest numbered.
828 We can't access bytes but if we could we would in the Big Endian order. */
829 #define BYTES_BIG_ENDIAN 0
830
831 /* Define this if most significant word of a multiword number is numbered. */
832 #define WORDS_BIG_ENDIAN 0
833
834 /* Width in bits of a "word", which is the contents of a machine register.
835 Note that this is not necessarily the width of data type `int';
836 if using 16-bit ints on a 68000, this would still be 32.
837 But on a machine with 16-bit registers, this would be 16. */
838 #define BITS_PER_WORD 32
839
840 /* Width of a word, in units (bytes). */
841 #define UNITS_PER_WORD 4
842
843 /* Width in bits of a pointer.
844 See also the macro `Pmode1' defined below. */
845 #define POINTER_SIZE 32
846
847 /* Allocation boundary (in *bits*) for storing pointers in memory. */
848 #define POINTER_BOUNDARY 32
849
850 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
851 #define PARM_BOUNDARY 32
852
853 /* Boundary (in *bits*) on which stack pointer should be aligned. */
854 #define STACK_BOUNDARY 32
855
856 /* Allocation boundary (in *bits*) for the code of a function. */
857 #define FUNCTION_BOUNDARY 32
858
859 /* Alignment of field after `int : 0' in a structure. */
860 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
861
862 /* No data type wants to be aligned rounder than this. */
863 #define BIGGEST_ALIGNMENT 32
864
865 /* Define this if move instructions will actually fail to work
866 when given unaligned data. */
867 #define STRICT_ALIGNMENT 1
868
869 /* (shell-command "rm c-decl.o stor-layout.o")
870 * never define PCC_BITFIELD_TYPE_MATTERS
871 * really cause some alignment problem
872 */
873
874 #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \
875 BITS_PER_UNIT)
876
877 #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \
878 BITS_PER_UNIT)
879
880
881 /* what is the 'type' of size_t */
882 #define SIZE_TYPE "long unsigned int"
883
884 /* Define this as 1 if `char' should by default be signed; else as 0. */
885 #define DEFAULT_SIGNED_CHAR 1
886 #define FLOAT_TYPE_SIZE BITS_PER_WORD
887 #define SHORT_TYPE_SIZE 16
888 #define CHAR_TYPE_SIZE 8
889 #define INT_TYPE_SIZE 32
890 #define LONG_TYPE_SIZE 32
891 #define LONG_LONG_TYPE_SIZE 64
892
893 /* Note: Fix this to depend on target switch. -- lev */
894
895 /* Note: Try to implement double and force long double. -- tonyko
896 * #define __DOUBLES_ARE_FLOATS__
897 * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE
898 * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
899 * #define DOUBLES_ARE_FLOATS 1
900 */
901
902 #define DOUBLE_TYPE_SIZE 64
903 #define LONG_DOUBLE_TYPE_SIZE 64
904
905 /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)'
906 A macro to update M and UNSIGNEDP when an object whose type is
907 TYPE and which has the specified mode and signedness is to be
908 stored in a register. This macro is only called when TYPE is a
909 scalar type.
910
911 On most RISC machines, which only have operations that operate on
912 a full register, define this macro to set M to `word_mode' if M is
913 an integer mode narrower than `BITS_PER_WORD'. In most cases,
914 only integer modes should be widened because wider-precision
915 floating-point operations are usually more expensive than their
916 narrower counterparts.
917
918 For most machines, the macro definition does not change UNSIGNEDP.
919 However, some machines, have instructions that preferentially
920 handle either signed or unsigned quantities of certain modes. For
921 example, on the DEC Alpha, 32-bit loads from memory and 32-bit add
922 instructions sign-extend the result to 64 bits. On such machines,
923 set UNSIGNEDP according to which kind of extension is more
924 efficient.
925
926 Do not define this macro if it would never modify M.*/
927
928 #define BFIN_PROMOTE_MODE_P(MODE) \
929 (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \
930 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)
931
932 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
933 if (BFIN_PROMOTE_MODE_P(MODE)) \
934 { \
935 if (MODE == QImode) \
936 UNSIGNEDP = 1; \
937 else if (MODE == HImode) \
938 UNSIGNEDP = 0; \
939 (MODE) = SImode; \
940 }
941
942 /* Describing Relative Costs of Operations */
943
944 /* Do not put function addr into constant pool */
945 #define NO_FUNCTION_CSE 1
946
947 /* Specify the machine mode that this machine uses
948 for the index in the tablejump instruction. */
949 #define CASE_VECTOR_MODE SImode
950
951 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic
952
953 /* Define if operations between registers always perform the operation
954 on the full register even if a narrower mode is specified.
955 #define WORD_REGISTER_OPERATIONS 1
956 */
957
958 /* Evaluates to true if A and B are mac flags that can be used
959 together in a single multiply insn. That is the case if they are
960 both the same flag not involving M, or if one is a combination of
961 the other with M. */
962 #define MACFLAGS_MATCH_P(A, B) \
963 ((A) == (B) \
964 || ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \
965 || ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \
966 || ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \
967 || ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS))
968
969 /* Switch into a generic section. */
970 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
971
972 #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE)
973 #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX)
974
975 typedef enum sections {
976 CODE_DIR,
977 DATA_DIR,
978 LAST_SECT_NM
979 } SECT_ENUM_T;
980
981 typedef enum directives {
982 LONG_CONST_DIR,
983 SHORT_CONST_DIR,
984 BYTE_CONST_DIR,
985 SPACE_DIR,
986 INIT_DIR,
987 LAST_DIR_NM
988 } DIR_ENUM_T;
989
990 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) \
991 ((C) == ';' \
992 || ((C) == '|' && (STR)[1] == '|'))
993
994 #define TEXT_SECTION_ASM_OP ".text;"
995 #define DATA_SECTION_ASM_OP ".data;"
996
997 #define ASM_APP_ON ""
998 #define ASM_APP_OFF ""
999
1000 #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \
1001 do { fputs (".global ", FILE); \
1002 assemble_name (FILE, NAME); \
1003 fputc (';',FILE); \
1004 fputc ('\n',FILE); \
1005 } while (0)
1006
1007 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1008 do { \
1009 fputs (".type ", FILE); \
1010 assemble_name (FILE, NAME); \
1011 fputs (", STT_FUNC", FILE); \
1012 fputc (';',FILE); \
1013 fputc ('\n',FILE); \
1014 ASM_OUTPUT_LABEL(FILE, NAME); \
1015 } while (0)
1016
1017 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1018 do { assemble_name (FILE, NAME); \
1019 fputs (":\n",FILE); \
1020 } while (0)
1021
1022 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1023 do { fprintf (FILE, "_%s", NAME); \
1024 } while (0)
1025
1026 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1027 do { char __buf[256]; \
1028 fprintf (FILE, "\t.dd\t"); \
1029 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1030 assemble_name (FILE, __buf); \
1031 fputc (';', FILE); \
1032 fputc ('\n', FILE); \
1033 } while (0)
1034
1035 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1036 MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL)
1037
1038 #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1039 do { \
1040 char __buf[256]; \
1041 fprintf (FILE, "\t.dd\t"); \
1042 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1043 assemble_name (FILE, __buf); \
1044 fputs (" - ", FILE); \
1045 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \
1046 assemble_name (FILE, __buf); \
1047 fputc (';', FILE); \
1048 fputc ('\n', FILE); \
1049 } while (0)
1050
1051 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1052 do { \
1053 if ((LOG) != 0) \
1054 fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \
1055 } while (0)
1056
1057 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1058 do { \
1059 asm_output_skip (FILE, SIZE); \
1060 } while (0)
1061
1062 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1063 do { \
1064 switch_to_section (data_section); \
1065 if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \
1066 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \
1067 ASM_OUTPUT_LABEL (FILE, NAME); \
1068 fprintf (FILE, "%s %ld;\n", ASM_SPACE, \
1069 (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \
1070 } while (0)
1071
1072 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1073 do { \
1074 ASM_GLOBALIZE_LABEL1(FILE,NAME); \
1075 ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0)
1076
1077 #define ASM_COMMENT_START "//"
1078
1079 #define PROFILE_BEFORE_PROLOGUE
1080 #define FUNCTION_PROFILER(FILE, LABELNO) \
1081 do { \
1082 fprintf (FILE, "\t[--SP] = RETS;\n"); \
1083 if (TARGET_LONG_CALLS) \
1084 { \
1085 fprintf (FILE, "\tP2.h = __mcount;\n"); \
1086 fprintf (FILE, "\tP2.l = __mcount;\n"); \
1087 fprintf (FILE, "\tCALL (P2);\n"); \
1088 } \
1089 else \
1090 fprintf (FILE, "\tCALL __mcount;\n"); \
1091 fprintf (FILE, "\tRETS = [SP++];\n"); \
1092 } while(0)
1093
1094 #undef NO_PROFILE_COUNTERS
1095 #define NO_PROFILE_COUNTERS 1
1096
1097 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "\t[--SP] = %s;\n", reg_names[REGNO])
1098 #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "\t%s = [SP++];\n", reg_names[REGNO])
1099
1100 extern rtx bfin_cc_rtx, bfin_rets_rtx;
1101
1102 /* This works for GAS and some other assemblers. */
1103 #define SET_ASM_OP ".set "
1104
1105 /* DBX register number for a given compiler register number */
1106 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1107
1108 #define SIZE_ASM_OP "\t.size\t"
1109
1110 extern int splitting_for_sched, splitting_loops;
1111
1112 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) ((CHAR) == '!')
1113
1114 #ifndef TARGET_SUPPORTS_SYNC_CALLS
1115 #define TARGET_SUPPORTS_SYNC_CALLS 0
1116 #endif
1117
1118 struct bfin_cpu
1119 {
1120 const char *name;
1121 bfin_cpu_t type;
1122 int si_revision;
1123 unsigned int workarounds;
1124 };
1125
1126 extern const struct bfin_cpu bfin_cpus[];
1127
1128 #endif /* _BFIN_CONFIG */
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