| blob | 4bdef2d0af7711428d3cbc5298006dd0b29492ae |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
61 /* Not really meaningful values, but at least something. */
62 #ifndef SIMULTANEOUS_PREFETCHES
63 #define SIMULTANEOUS_PREFETCHES 3
64 #endif
65 #ifndef PREFETCH_BLOCK
66 #define PREFETCH_BLOCK 32
67 #endif
68 #ifndef HAVE_prefetch
69 #define HAVE_prefetch 0
70 #define CODE_FOR_prefetch 0
71 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
72 #endif
74 /* Give up the prefetch optimizations once we exceed a given threshhold.
75 It is unlikely that we would be able to optimize something in a loop
76 with so many detected prefetches. */
77 #define MAX_PREFETCHES 100
78 /* The number of prefetch blocks that are beneficial to fetch at once before
79 a loop with a known (and low) iteration count. */
80 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
81 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
82 since it is likely that the data are already in the cache. */
83 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
85 /* Parameterize some prefetch heuristics so they can be turned on and off
86 easily for performance testing on new architectures. These can be
87 defined in target-dependent files. */
89 /* Prefetch is worthwhile only when loads/stores are dense. */
90 #ifndef PREFETCH_ONLY_DENSE_MEM
91 #define PREFETCH_ONLY_DENSE_MEM 1
92 #endif
94 /* Define what we mean by "dense" loads and stores; This value divided by 256
95 is the minimum percentage of memory references that worth prefetching. */
96 #ifndef PREFETCH_DENSE_MEM
97 #define PREFETCH_DENSE_MEM 220
98 #endif
100 /* Do not prefetch for a loop whose iteration count is known to be low. */
101 #ifndef PREFETCH_NO_LOW_LOOPCNT
102 #define PREFETCH_NO_LOW_LOOPCNT 1
103 #endif
105 /* Define what we mean by a "low" iteration count. */
106 #ifndef PREFETCH_LOW_LOOPCNT
107 #define PREFETCH_LOW_LOOPCNT 32
108 #endif
110 /* Do not prefetch for a loop that contains a function call; such a loop is
111 probably not an internal loop. */
112 #ifndef PREFETCH_NO_CALL
113 #define PREFETCH_NO_CALL 1
114 #endif
116 /* Do not prefetch accesses with an extreme stride. */
117 #ifndef PREFETCH_NO_EXTREME_STRIDE
118 #define PREFETCH_NO_EXTREME_STRIDE 1
119 #endif
121 /* Define what we mean by an "extreme" stride. */
122 #ifndef PREFETCH_EXTREME_STRIDE
123 #define PREFETCH_EXTREME_STRIDE 4096
124 #endif
126 /* Define a limit to how far apart indices can be and still be merged
127 into a single prefetch. */
128 #ifndef PREFETCH_EXTREME_DIFFERENCE
129 #define PREFETCH_EXTREME_DIFFERENCE 4096
130 #endif
132 /* Issue prefetch instructions before the loop to fetch data to be used
133 in the first few loop iterations. */
134 #ifndef PREFETCH_BEFORE_LOOP
135 #define PREFETCH_BEFORE_LOOP 1
136 #endif
138 /* Do not handle reversed order prefetches (negative stride). */
139 #ifndef PREFETCH_NO_REVERSE_ORDER
140 #define PREFETCH_NO_REVERSE_ORDER 1
141 #endif
143 /* Prefetch even if the GIV is in conditional code. */
144 #ifndef PREFETCH_CONDITIONAL
145 #define PREFETCH_CONDITIONAL 1
146 #endif
148 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
149 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
151 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
152 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
153 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
155 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
156 ((REGNO) < FIRST_PSEUDO_REGISTER \
157 ? (int) HARD_REGNO_NREGS ((REGNO), GET_MODE (SET_DEST)) : 1)
160 /* Vector mapping INSN_UIDs to luids.
161 The luids are like uids but increase monotonically always.
162 We use them to see whether a jump comes from outside a given loop. */
166 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
167 number the insn is contained in. */
171 /* 1 + largest uid of any insn. */
175 /* Number of loops detected in current function. Used as index to the
176 next few tables. */
180 /* Bound on pseudo register number before loop optimization.
181 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
184 /* The value to pass to the next call of reg_scan_update. */
186 \f
187 /* During the analysis of a loop, a chain of `struct movable's
188 is made to record all the movable insns found.
189 Then the entire chain can be scanned to decide which to move. */
191 struct movable
192 {
197 of any registers used within the LIBCALL. */
199 that must be moved with this one. */
202 may be adjusted when matching movables
203 that load the same value are found. */
205 including other movables that force this
206 or match this one. */
210 /* If PARTIAL is 1, GLOBAL means something different:
211 that the reg is live outside the range from where it is set
212 to the following label. */
216 In particular, moving it does not make it
217 invariant. */
219 load SRC, rather than copying INSN. */
221 first insn of a consecutive sets group. */
224 that we should avoid changing when clearing
225 the rest of the reg. */
229 };
234 /* Forward declarations. */
249 #if 0
251 #endif
281 rtx *));
364 {
365 rtx r1;
366 rtx r2;
370 {
371 rtx match;
372 rtx replacement;
373 rtx insn;
376 /* Nonzero iff INSN is between START and END, inclusive. */
377 #define INSN_IN_RANGE_P(INSN, START, END) \
378 (INSN_UID (INSN) < max_uid_for_loop \
379 && INSN_LUID (INSN) >= INSN_LUID (START) \
380 && INSN_LUID (INSN) <= INSN_LUID (END))
382 /* Indirect_jump_in_function is computed once per function. */
390 rtx));
391 \f
392 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
393 copy the value of the strength reduced giv to its original register. */
396 /* Cost of using a register, to normalize the benefits of a giv. */
399 void
401 {
407 }
408 \f
409 /* Compute the mapping from uids to luids.
410 LUIDs are numbers assigned to insns, like uids,
411 except that luids increase monotonically through the code.
412 Start at insn START and stop just before END. Assign LUIDs
413 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
414 static int
418 {
420 rtx insn;
423 {
426 /* Don't assign luids to line-number NOTEs, so that the distance in
427 luids between two insns is not affected by -g. */
431 else
432 /* Give a line number note the same luid as preceding insn. */
434 }
436 }
437 \f
438 /* Entry point of this file. Perform loop optimization
439 on the current function. F is the first insn of the function
440 and DUMPFILE is a stream for output of a trace of actions taken
441 (or 0 if none should be output). */
443 void
445 /* f is the first instruction of a chain of insns for one function */
446 rtx f;
449 {
450 rtx insn;
465 /* Count the number of loops. */
469 {
472 max_loop_num++;
473 }
475 /* Don't waste time if no loops. */
481 /* Get size to use for tables indexed by uids.
482 Leave some space for labels allocated by find_and_verify_loops. */
489 /* Allocate storage for array of loops. */
493 /* Find and process each loop.
494 First, find them, and record them in order of their beginnings. */
497 /* Allocate and initialize auxiliary loop information. */
502 /* Now find all register lifetimes. This must be done after
503 find_and_verify_loops, because it might reorder the insns in the
504 function. */
507 /* This must occur after reg_scan so that registers created by gcse
508 will have entries in the register tables.
510 We could have added a call to reg_scan after gcse_main in toplev.c,
511 but moving this call to init_alias_analysis is more efficient. */
514 /* See if we went too far. Note that get_max_uid already returns
515 one more that the maximum uid of all insn. */
518 /* Now reset it to the actual size we need. See above. */
521 /* find_and_verify_loops has already called compute_luids, but it
522 might have rearranged code afterwards, so we need to recompute
523 the luids now. */
526 /* Don't leave gaps in uid_luid for insns that have been
527 deleted. It is possible that the first or last insn
528 using some register has been deleted by cross-jumping.
529 Make sure that uid_luid for that former insn's uid
530 points to the general area where that insn used to be. */
532 {
536 }
541 /* Determine if the function has indirect jump. On some systems
542 this prevents low overhead loop instructions from being used. */
545 /* Now scan the loops, last ones first, since this means inner ones are done
546 before outer ones. */
548 {
553 }
557 /* Clean up. */
562 }
563 \f
564 /* Returns the next insn, in execution order, after INSN. START and
565 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
566 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
567 insn-stream; it is used with loops that are entered near the
568 bottom. */
570 static rtx
573 rtx insn;
574 {
578 {
580 /* Go to the top of the loop, and continue there. */
582 else
583 /* We're done. */
585 }
588 /* We're done. */
592 }
594 /* Optimize one loop described by LOOP. */
596 /* ??? Could also move memory writes out of loops if the destination address
597 is invariant, the source is invariant, the memory write is not volatile,
598 and if we can prove that no read inside the loop can read this address
599 before the write occurs. If there is a read of this address after the
600 write, then we can also mark the memory read as invariant. */
602 static void
606 {
612 rtx p;
613 /* 1 if we are scanning insns that could be executed zero times. */
615 /* 1 if we are scanning insns that might never be executed
616 due to a subroutine call which might exit before they are reached. */
618 /* Number of insns in the loop. */
622 /* The SET from an insn, if it is the only SET in the insn. */
624 /* Chain describing insns movable in current loop. */
626 /* Ratio of extra register life span we can justify
627 for saving an instruction. More if loop doesn't call subroutines
628 since in that case saving an insn makes more difference
629 and more registers are available. */
631 /* Nonzero if we are scanning instructions in a sub-loop. */
640 /* Determine whether this loop starts with a jump down to a test at
641 the end. This will occur for a small number of loops with a test
642 that is too complex to duplicate in front of the loop.
644 We search for the first insn or label in the loop, skipping NOTEs.
645 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
646 (because we might have a loop executed only once that contains a
647 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
648 (in case we have a degenerate loop).
650 Note that if we mistakenly think that a loop is entered at the top
651 when, in fact, it is entered at the exit test, the only effect will be
652 slightly poorer optimization. Making the opposite error can generate
653 incorrect code. Since very few loops now start with a jump to the
654 exit test, the code here to detect that case is very conservative. */
657 p != loop_end
663 ;
667 /* If loop end is the end of the current function, then emit a
668 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
669 note insn. This is the position we use when sinking insns out of
670 the loop. */
673 else
676 /* Set up variables describing this loop. */
680 /* If loop has a jump before the first label,
681 the true entry is the target of that jump.
682 Start scan from there.
683 But record in LOOP->TOP the place where the end-test jumps
684 back to so we can scan that after the end of the loop. */
686 /* Loop entry must be unconditional jump (and not a RETURN) */
689 /* Check to see whether the jump actually
690 jumps out of the loop (meaning it's no loop).
691 This case can happen for things like
692 do {..} while (0). If this label was generated previously
693 by loop, we can't tell anything about it and have to reject
694 the loop. */
696 {
699 }
701 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
702 as required by loop_reg_used_before_p. So skip such loops. (This
703 test may never be true, but it's best to play it safe.)
705 Also, skip loops where we do not start scanning at a label. This
706 test also rejects loops starting with a JUMP_INSN that failed the
707 test above. */
711 {
716 }
718 /* Allocate extra space for REGs that might be created by load_mems.
719 We allocate a little extra slop as well, in the hopes that we
720 won't have to reallocate the regs array. */
725 {
731 }
733 /* Scan through the loop finding insns that are safe to move.
734 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
735 this reg will be considered invariant for subsequent insns.
736 We consider whether subsequent insns use the reg
737 in deciding whether it is worth actually moving.
739 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
740 and therefore it is possible that the insns we are scanning
741 would never be executed. At such times, we must make sure
742 that it is safe to execute the insn once instead of zero times.
743 When MAYBE_NEVER is 0, all insns will be executed at least once
744 so that is not a problem. */
749 {
751 in_libcall--;
753 {
756 in_libcall++;
760 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
762 #endif
764 {
771 /* Figure out what to use as a source of this insn. If a
772 REG_EQUIV note is given or if a REG_EQUAL note with a
773 constant operand is specified, use it as the source and
774 mark that we should move this insn by calling
775 emit_move_insn rather that duplicating the insn.
777 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL
778 note is present. */
782 else
783 {
788 {
790 /* A libcall block can use regs that don't appear in
791 the equivalent expression. To move the libcall,
792 we must move those regs too. */
794 }
795 }
797 /* For parallels, add any possible uses to the dependencies, as
798 we can't move the insn without resolving them first. */
800 {
802 {
805 dependencies
807 dependencies);
808 }
809 }
811 /* Don't try to optimize a register that was made
812 by loop-optimization for an inner loop.
813 We don't know its life-span, so we can't compute
814 the benefit. */
816 ;
818 than the one where it is set (meaning that
819 something after this point in the loop might
820 depend on its value before the set). */
822 /* And the set is not guaranteed to be executed once
823 the loop starts, or the value before the set is
824 needed before the set occurs...
826 ??? Note we have quadratic behavior here, mitigated
827 by the fact that the previous test will often fail for
828 large loops. Rather than re-scanning the entire loop
829 each time for register usage, we should build tables
830 of the register usage and use them here instead. */
831 && (maybe_never
833 /* It is unsafe to move the set.
835 This code used to consider it OK to move a set of a variable
836 which was not created by the user and not used in an exit
837 test.
838 That behavior is incorrect and was removed. */
839 ;
842 || (tem2
845 || (tem1
846 = consec_sets_invariant_p
849 p)))
850 /* If the insn can cause a trap (such as divide by zero),
851 can't move it unless it's guaranteed to be executed
852 once loop is entered. Even a function call might
853 prevent the trap insn from being reached
854 (since it might exit!) */
857 {
861 /* A potential lossage is where we have a case where two insns
862 can be combined as long as they are both in the loop, but
863 we move one of them outside the loop. For large loops,
864 this can lose. The most common case of this is the address
865 of a function being called.
867 Therefore, if this register is marked as being used
868 exactly once if we are in a loop with calls
869 (a "large loop"), see if we can replace the usage of
870 this register with the source of this SET. If we can,
871 delete this insn.
873 Don't do this if P has a REG_RETVAL note or if we have
874 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
886 && (! SMALL_REGISTER_CLASSES
890 /* This test is not redundant; SET_SRC (set) might be
891 a call-clobbered register and the life of REGNO
892 might span a call. */
899 {
900 /* Replace any usage in a REG_EQUAL note. Must copy
901 the new source, so that we don't get rtx sharing
902 between the SET_SOURCE and REG_NOTES of insn p. */
904 = (replace_rtx
910 i++)
913 }
922 m->consec
932 /* Set M->cond if either loop_invariant_p
933 or consec_sets_invariant_p returned 2
934 (only conditionally invariant). */
944 /* Add M to the end of the chain MOVABLES. */
948 {
949 /* It is possible for the first instruction to have a
950 REG_EQUAL note but a non-invariant SET_SRC, so we must
951 remember the status of the first instruction in case
952 the last instruction doesn't have a REG_EQUAL note. */
955 /* Skip this insn, not checking REG_LIBCALL notes. */
957 /* Skip the consecutive insns, if there are any. */
959 /* Back up to the last insn of the consecutive group. */
962 /* We must now reset m->move_insn, m->is_equiv, and
963 possibly m->set_src to correspond to the effects of
964 all the insns. */
968 else
969 {
973 else
976 }
977 m->is_equiv
979 }
980 }
981 /* If this register is always set within a STRICT_LOW_PART
982 or set to zero, then its high bytes are constant.
983 So clear them outside the loop and within the loop
984 just load the low bytes.
985 We must check that the machine has an instruction to do so.
986 Also, if the value loaded into the register
987 depends on the same register, this cannot be done. */
997 {
1000 {
1014 /* If the insn may not be executed on some cycles,
1015 we can't clear the whole reg; clear just high part.
1016 Not even if the reg is used only within this loop.
1017 Consider this:
1018 while (1)
1019 while (s != t) {
1020 if (foo ()) x = *s;
1021 use (x);
1022 }
1023 Clearing x before the inner loop could clobber a value
1024 being saved from the last time around the outer loop.
1025 However, if the reg is not used outside this loop
1026 and all uses of the register are in the same
1027 basic block as the store, there is no problem.
1029 If this insn was made by loop, we don't know its
1030 INSN_LUID and hence must make a conservative
1031 assumption. */
1034 || (labels_in_range_p
1038 else
1047 i++)
1049 /* Add M to the end of the chain MOVABLES. */
1051 }
1052 }
1053 }
1054 }
1055 /* Past a call insn, we get to insns which might not be executed
1056 because the call might exit. This matters for insns that trap.
1057 Constant and pure call insns always return, so they don't count. */
1060 /* Past a label or a jump, we get to insns for which we
1061 can't count on whether or how many times they will be
1062 executed during each iteration. Therefore, we can
1063 only move out sets of trivial variables
1064 (those not used after the loop). */
1065 /* Similar code appears twice in strength_reduce. */
1067 /* If we enter the loop in the middle, and scan around to the
1068 beginning, don't set maybe_never for that. This must be an
1069 unconditional jump, otherwise the code at the top of the
1070 loop might never be executed. Unconditional jumps are
1071 followed by a barrier then the loop_end. */
1077 {
1078 /* At the virtual top of a converted loop, insns are again known to
1079 be executed: logically, the loop begins here even though the exit
1080 code has been duplicated. */
1084 loop_depth++;
1086 loop_depth--;
1087 }
1088 }
1090 /* If one movable subsumes another, ignore that other. */
1094 /* For each movable insn, see if the reg that it loads
1095 leads when it dies right into another conditionally movable insn.
1096 If so, record that the second insn "forces" the first one,
1097 since the second can be moved only if the first is. */
1101 /* See if there are multiple movable insns that load the same value.
1102 If there are, make all but the first point at the first one
1103 through the `match' field, and add the priorities of them
1104 all together as the priority of the first. */
1108 /* Now consider each movable insn to decide whether it is worth moving.
1109 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1111 For machines with few registers this increases code size, so do not
1112 move moveables when optimizing for code size on such machines.
1113 (The 18 below is the value for i386.) */
1117 {
1120 /* Recalculate regs->array if move_movables has created new
1121 registers. */
1123 {
1129 ;
1134 }
1135 }
1137 /* Now candidates that still are negative are those not moved.
1138 Change regs->array[I].set_in_loop to indicate that those are not actually
1139 invariant. */
1144 /* Now that we've moved some things out of the loop, we might be able to
1145 hoist even more memory references. */
1148 /* Recalculate regs->array if load_mems has created new registers. */
1156 ;
1163 {
1165 /* Ensure our label doesn't go away. */
1176 }
1179 /* The movable information is required for strength reduction. */
1185 }
1186 \f
1187 /* Add elements to *OUTPUT to record all the pseudo-regs
1188 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1190 void
1194 {
1202 {
1220 }
1224 {
1228 {
1237 }
1238 }
1239 }
1240 \f
1241 /* Check what regs are referred to in the libcall block ending with INSN,
1242 aside from those mentioned in the equivalent value.
1243 If there are none, return 0.
1244 If there are one or more, return an EXPR_LIST containing all of them. */
1246 rtx
1249 {
1254 /* First, find all the regs used in the libcall block
1255 that are not mentioned as inputs to the result. */
1258 {
1263 }
1266 }
1267 \f
1268 /* Return 1 if all uses of REG
1269 are between INSN and the end of the basic block. */
1271 static int
1274 {
1276 rtx p;
1281 /* Search this basic block for the already recorded last use of the reg. */
1283 {
1285 {
1291 /* Ordinary insn: if this is the last use, we win. */
1297 /* Jump insn: if this is the last use, we win. */
1300 /* Otherwise, it's the end of the basic block, so we lose. */
1305 /* It's the end of the basic block, so we lose. */
1310 }
1311 }
1313 /* The "last use" that was recorded can't be found after the first
1314 use. This can happen when the last use was deleted while
1315 processing an inner loop, this inner loop was then completely
1316 unrolled, and the outer loop is always exited after the inner loop,
1317 so that everything after the first use becomes a single basic block. */
1319 }
1320 \f
1321 /* Compute the benefit of eliminating the insns in the block whose
1322 last insn is LAST. This may be a group of insns used to compute a
1323 value directly or can contain a library call. */
1325 static int
1327 rtx last;
1328 {
1329 rtx insn;
1334 {
1337 routine. */
1341 benefit++;
1342 }
1345 }
1346 \f
1347 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1349 static rtx
1351 rtx insn;
1353 {
1355 {
1356 rtx temp;
1358 /* If first insn of libcall sequence, skip to end. */
1359 /* Do this at start of loop, since INSN is guaranteed to
1360 be an insn here. */
1365 do
1368 }
1371 }
1373 /* Ignore any movable whose insn falls within a libcall
1374 which is part of another movable.
1375 We make use of the fact that the movable for the libcall value
1376 was made later and so appears later on the chain. */
1378 static void
1381 {
1385 {
1386 /* Is this a movable for the value of a libcall? */
1389 {
1390 rtx insn;
1391 /* Check for earlier movables inside that range,
1392 and mark them invalid. We cannot use LUIDs here because
1393 insns created by loop.c for prior loops don't have LUIDs.
1394 Rather than reject all such insns from movables, we just
1395 explicitly check each insn in the libcall (since invariant
1396 libcalls aren't that common). */
1401 }
1402 }
1403 }
1405 /* For each movable insn, see if the reg that it loads
1406 leads when it dies right into another conditionally movable insn.
1407 If so, record that the second insn "forces" the first one,
1408 since the second can be moved only if the first is. */
1410 static void
1413 {
1417 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1419 {
1422 /* ??? Could this be a bug? What if CSE caused the
1423 register of M1 to be used after this insn?
1424 Since CSE does not update regno_last_uid,
1425 this insn M->insn might not be where it dies.
1426 But very likely this doesn't matter; what matters is
1427 that M's reg is computed from M1's reg. */
1432 /* If m->consec, m->set_src isn't valid. */
1436 /* Increase the priority of the moving the first insn
1437 since it permits the second to be moved as well. */
1439 {
1443 }
1444 }
1445 }
1446 \f
1447 /* Find invariant expressions that are equal and can be combined into
1448 one register. */
1450 static void
1454 {
1459 /* Regs that are set more than once are not allowed to match
1460 or be matched. I'm no longer sure why not. */
1461 /* Only pseudo registers are allowed to match or be matched,
1462 since move_movables does not validate the change. */
1463 /* Perhaps testing m->consec_sets would be more appropriate here? */
1469 {
1476 /* We want later insns to match the first one. Don't make the first
1477 one match any later ones. So start this loop at m->next. */
1482 /* A reg used outside the loop mustn't be eliminated. */
1484 /* A reg used for zero-extending mustn't be eliminated. */
1487 ||
1488 (
1489 /* Can combine regs with different modes loaded from the
1490 same constant only if the modes are the same or
1491 if both are integer modes with M wider or the same
1492 width as M1. The check for integer is redundant, but
1493 safe, since the only case of differing destination
1494 modes with equal sources is when both sources are
1495 VOIDmode, i.e., CONST_INT. */
1501 /* See if the source of M1 says it matches M. */
1508 {
1514 }
1515 }
1517 /* Now combine the regs used for zero-extension.
1518 This can be done for those not marked `global'
1519 provided their lives don't overlap. */
1523 {
1526 /* Combine all the registers for extension from mode MODE.
1527 Don't combine any that are used outside this loop. */
1531 {
1538 {
1539 /* First one: don't check for overlap, just record it. */
1542 }
1544 /* Make sure they extend to the same mode.
1545 (Almost always true.) */
1549 /* We already have one: check for overlap with those
1550 already combined together. */
1557 /* No overlap: we can combine this with the others. */
1563 overlap:
1564 ;
1565 }
1566 }
1568 /* Clean up. */
1570 }
1572 /* Returns the number of movable instructions in LOOP that were not
1573 moved outside the loop. */
1575 static int
1578 {
1587 }
1589 \f
1590 /* Return 1 if regs X and Y will become the same if moved. */
1592 static int
1596 {
1613 }
1615 /* Return 1 if X and Y are identical-looking rtx's.
1616 This is the Lisp function EQUAL for rtx arguments.
1618 If two registers are matching movables or a movable register and an
1619 equivalent constant, consider them equal. */
1621 static int
1626 {
1640 /* If we have a register and a constant, they may sometimes be
1641 equal. */
1644 {
1649 }
1652 {
1657 }
1659 /* Otherwise, rtx's of different codes cannot be equal. */
1663 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1664 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1669 /* These three types of rtx's can be compared nonrecursively. */
1678 /* Compare the elements. If any pair of corresponding elements
1679 fail to match, return 0 for the whole things. */
1683 {
1685 {
1697 /* Two vectors must have the same length. */
1701 /* And the corresponding elements must match. */
1720 /* These are just backpointers, so they don't matter. */
1726 /* It is believed that rtx's at this level will never
1727 contain anything but integers and other rtx's,
1728 except for within LABEL_REFs and SYMBOL_REFs. */
1731 }
1732 }
1734 }
1735 \f
1736 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1737 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1738 references is incremented once for each added note. */
1740 static void
1742 rtx x;
1743 rtx insns;
1744 {
1748 rtx insn;
1751 {
1752 /* This code used to ignore labels that referred to dispatch tables to
1753 avoid flow generating (slighly) worse code.
1755 We no longer ignore such label references (see LABEL_REF handling in
1756 mark_jump_label for additional information). */
1759 {
1764 }
1765 }
1769 {
1775 }
1776 }
1777 \f
1778 /* Scan MOVABLES, and move the insns that deserve to be moved.
1779 If two matching movables are combined, replace one reg with the
1780 other throughout. */
1782 static void
1788 {
1793 rtx p;
1796 /* Map of pseudo-register replacements to handle combining
1797 when we move several insns that load the same value
1798 into different pseudo-registers. */
1803 {
1804 /* Describe this movable insn. */
1807 {
1828 }
1830 /* Ignore the insn if it's already done (it matched something else).
1831 Otherwise, see if it is now safe to move. */
1843 {
1845 rtx p;
1848 /* We have an insn that is safe to move.
1849 Compute its desirability. */
1860 /* An insn MUST be moved if we already moved something else
1861 which is safe only if this one is moved too: that is,
1862 if already_moved[REGNO] is nonzero. */
1864 /* An insn is desirable to move if the new lifetime of the
1865 register is no more than THRESHOLD times the old lifetime.
1866 If it's not desirable, it means the loop is so big
1867 that moving won't speed things up much,
1868 and it is liable to make register usage worse. */
1870 /* It is also desirable to move if it can be moved at no
1871 extra cost because something else was already moved. */
1874 || flag_move_all_movables
1879 {
1884 /* Now move the insns that set the reg. */
1887 {
1890 /* Find the end of this chain of matching regs.
1891 Thus, we load each reg in the chain from that one reg.
1892 And that reg is loaded with 0 directly,
1893 since it has ->match == 0. */
1899 /* Mark the moved, invariant reg as being allowed to
1900 share a hard reg with the other matching invariant. */
1904 regs_may_share
1907 regs_may_share));
1915 }
1916 /* If we are to re-generate the item being moved with a
1917 new move insn, first delete what we have and then emit
1918 the move insn before the loop. */
1920 {
1924 {
1925 /* If this is the first insn of a library call sequence,
1926 something is very wrong. */
1931 /* If this is the last insn of a libcall sequence, then
1932 delete every insn in the sequence except the last.
1933 The last insn is handled in the normal manner. */
1936 {
1940 }
1945 /* simplify_giv_expr expects that it can walk the insns
1946 at m->insn forwards and see this old sequence we are
1947 tossing here. delete_insn does preserve the next
1948 pointers, but when we skip over a NOTE we must fix
1949 it up. Otherwise that code walks into the non-deleted
1950 insn stream. */
1953 }
1971 /* The more regs we move, the less we like moving them. */
1973 }
1974 else
1975 {
1977 {
1980 /* If first insn of libcall sequence, skip to end. */
1981 /* Do this at start of loop, since p is guaranteed to
1982 be an insn here. */
1987 /* If last insn of libcall sequence, move all
1988 insns except the last before the loop. The last
1989 insn is handled in the normal manner. */
1992 {
2000 {
2001 rtx body;
2002 rtx n;
2003 rtx next;
2010 /* Find the next insn after TEMP,
2011 not counting USE or NOTE insns. */
2019 /* If that is the call, this may be the insn
2020 that loads the function address.
2022 Extract the function address from the insn
2023 that loads it into a register.
2024 If this insn was cse'd, we get incorrect code.
2026 So emit a new move insn that copies the
2027 function address into the register that the
2028 call insn will use. flow.c will delete any
2029 redundant stores that we have created. */
2034 NULL_RTX)))
2035 {
2041 }
2042 /* We have the call insn.
2043 If it uses the register we suspect it might,
2044 load it with the correct address directly. */
2049 gen_move_insn
2053 {
2055 /* Because the USAGE information potentially
2056 contains objects other than hard registers
2057 we need to copy it. */
2061 }
2062 else
2071 }
2074 }
2076 {
2077 /* P sets REG to zero; but we should clear only
2078 the bits that are not covered by the mode
2079 m->savemode. */
2081 rtx sequence;
2082 rtx tem;
2085 tem = expand_simple_binop
2098 }
2100 {
2102 /* Because the USAGE information potentially
2103 contains objects other than hard registers
2104 we need to copy it. */
2108 }
2110 {
2111 rtx seq;
2112 /* The SET_SRC might not be invariant, so we must
2113 use the REG_EQUAL note. */
2125 }
2126 else
2130 {
2134 /* If there is a REG_EQUAL note present whose value
2135 is not loop invariant, then delete it, since it
2136 may cause problems with later optimization passes.
2137 It is possible for cse to create such notes
2138 like this as a result of record_jump_cond. */
2143 }
2152 /* If library call, now fix the REG_NOTES that contain
2153 insn pointers, namely REG_LIBCALL on FIRST
2154 and REG_RETVAL on I1. */
2156 {
2160 }
2166 /* simplify_giv_expr expects that it can walk the insns
2167 at m->insn forwards and see this old sequence we are
2168 tossing here. delete_insn does preserve the next
2169 pointers, but when we skip over a NOTE we must fix
2170 it up. Otherwise that code walks into the non-deleted
2171 insn stream. */
2174 }
2176 /* The more regs we move, the less we like moving them. */
2178 }
2180 /* Any other movable that loads the same register
2181 MUST be moved. */
2184 /* This reg has been moved out of one loop. */
2187 /* The reg set here is now invariant. */
2189 {
2193 }
2197 /* Change the length-of-life info for the register
2198 to say it lives at least the full length of this loop.
2199 This will help guide optimizations in outer loops. */
2202 /* This is the old insn before all the moved insns.
2203 We can't use the moved insn because it is out of range
2204 in uid_luid. Only the old insns have luids. */
2209 /* Combine with this moved insn any other matching movables. */
2214 {
2215 rtx temp;
2217 /* Schedule the reg loaded by M1
2218 for replacement so that shares the reg of M.
2219 If the modes differ (only possible in restricted
2220 circumstances, make a SUBREG.
2222 Note this assumes that the target dependent files
2223 treat REG and SUBREG equally, including within
2224 GO_IF_LEGITIMATE_ADDRESS and in all the
2225 predicates since we never verify that replacing the
2226 original register with a SUBREG results in a
2227 recognizable insn. */
2230 else
2235 /* Get rid of the matching insn
2236 and prevent further processing of it. */
2239 /* if library call, delete all insns. */
2241 NULL_RTX)))
2243 else
2246 /* Any other movable that loads the same register
2247 MUST be moved. */
2250 /* The reg merged here is now invariant,
2251 if the reg it matches is invariant. */
2253 {
2257 i++)
2259 }
2260 }
2261 }
2264 }
2270 }
2275 /* Go through all the instructions in the loop, making
2276 all the register substitutions scheduled in REG_MAP. */
2280 {
2284 }
2286 /* Clean up. */
2289 }
2292 static void
2296 {
2299 else
2302 }
2305 static void
2308 {
2313 {
2316 }
2317 }
2318 \f
2319 #if 0
2320 /* Scan X and replace the address of any MEM in it with ADDR.
2321 REG is the address that MEM should have before the replacement. */
2323 static void
2326 {
2335 {
2347 /* Short cut for very common case. */
2352 /* Short cut for very common case. */
2357 /* If this MEM uses a reg other than the one we expected,
2358 something is wrong. */
2366 }
2370 {
2374 {
2378 }
2379 }
2380 }
2381 #endif
2382 \f
2383 /* Return the number of memory refs to addresses that vary
2384 in the rtx X. */
2386 static int
2389 rtx x;
2390 {
2401 {
2418 }
2423 {
2427 {
2431 }
2432 }
2434 }
2435 \f
2436 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2437 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2438 `unknown_address_altered', `unknown_constant_address_altered', and
2439 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2440 list `store_mems' in LOOP. */
2442 static void
2445 {
2447 rtx insn;
2451 /* The label after END. Jumping here is just like falling off the
2452 end of the loop. We use next_nonnote_insn instead of next_label
2453 as a hedge against the (pathological) case where some actual insn
2454 might end up between the two. */
2473 /* If loop opts run twice, this was set on 1st pass for 2nd. */
2478 {
2480 {
2483 }
2484 }
2488 {
2490 {
2493 {
2495 /* Count number of loops contained in this one. */
2497 }
2504 {
2507 }
2517 {
2521 {
2526 {
2529 }
2530 else
2531 {
2534 }
2536 do
2537 {
2539 {
2541 {
2542 /* Something tricky. */
2545 }
2548 {
2549 /* A jump outside the current loop. */
2552 }
2553 }
2557 }
2559 }
2560 else
2561 {
2562 /* A return, or something tricky. */
2564 }
2565 }
2566 /* FALLTHRU */
2587 }
2588 }
2590 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2592 anywhere. */
2594 /* We don't want loads for MEMs moved to a location before the
2595 one at which their stack memory becomes allocated. (Note
2596 that this is not a problem for malloc, etc., since those
2597 require actual function calls. */
2598 && ! current_function_calls_alloca
2599 /* There are ways to leave the loop other than falling off the
2600 end. */
2606 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2607 that loop_invariant_p and load_mems can use true_dependence
2608 to determine what is really clobbered. */
2610 {
2613 loop_info->store_mems
2615 }
2617 {
2621 loop_info->store_mems
2623 }
2624 }
2625 \f
2626 /* Invalidate all loops containing LABEL. */
2628 static void
2630 rtx label;
2631 {
2635 }
2637 /* Scan the function looking for loops. Record the start and end of each loop.
2638 Also mark as invalid loops any loops that contain a setjmp or are branched
2639 to from outside the loop. */
2641 static void
2643 rtx f;
2645 {
2646 rtx insn;
2647 rtx label;
2657 /* If there are jumps to undefined labels,
2658 treat them as jumps out of any/all loops.
2659 This also avoids writing past end of tables when there are no loops. */
2662 /* Find boundaries of loops, mark which loops are contained within
2663 loops, and invalidate loops that have setjmp. */
2668 {
2671 {
2675 num_loops++;
2699 }
2703 {
2704 /* In this case, we must invalidate our current loop and any
2705 enclosing loop. */
2707 {
2713 }
2714 }
2716 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2717 enclosing loop, but this doesn't matter. */
2719 }
2721 /* Any loop containing a label used in an initializer must be invalidated,
2722 because it can be jumped into from anywhere. */
2726 /* Any loop containing a label used for an exception handler must be
2727 invalidated, because it can be jumped into from anywhere. */
2730 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2731 loop that it is not contained within, that loop is marked invalid.
2732 If any INSN or CALL_INSN uses a label's address, then the loop containing
2733 that label is marked invalid, because it could be jumped into from
2734 anywhere.
2736 Also look for blocks of code ending in an unconditional branch that
2737 exits the loop. If such a block is surrounded by a conditional
2738 branch around the block, move the block elsewhere (see below) and
2739 invert the jump to point to the code block. This may eliminate a
2740 label in our loop and will simplify processing by both us and a
2741 possible second cse pass. */
2745 {
2749 {
2753 }
2760 /* See if this is an unconditional branch outside the loop. */
2768 {
2769 rtx p;
2775 /* Go backwards until we reach the start of the loop, a label,
2776 or a JUMP_INSN. */
2783 ;
2785 /* Check for the case where we have a jump to an inner nested
2786 loop, and do not perform the optimization in that case. */
2789 {
2792 {
2797 }
2798 }
2800 /* Make sure that the target of P is within the current loop. */
2806 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2807 we have a block of code to try to move.
2809 We look backward and then forward from the target of INSN
2810 to find a BARRIER at the same loop depth as the target.
2811 If we find such a BARRIER, we make a new label for the start
2812 of the block, invert the jump in P and point it to that label,
2813 and move the block of code to the spot we found. */
2818 /* Just ignore jumps to labels that were never emitted.
2819 These always indicate compilation errors. */
2823 /* If it's not safe to move the sequence, then we
2824 mustn't try. */
2827 {
2828 rtx target
2832 rtx tmp;
2834 /* Search for possible garbage past the conditional jumps
2835 and look for the last barrier. */
2843 /* Don't move things inside a tablejump. */
2856 /* Don't move things inside a tablejump. */
2867 {
2871 /* Ensure our label doesn't go away. */
2874 /* Verify that uid_loop is large enough and that
2875 we can invert P. */
2877 {
2880 /* If no suitable BARRIER was found, create a suitable
2881 one before TARGET. Since TARGET is a fall through
2882 path, we'll need to insert a jump around our block
2883 and add a BARRIER before TARGET.
2885 This creates an extra unconditional jump outside
2886 the loop. However, the benefits of removing rarely
2887 executed instructions from inside the loop usually
2888 outweighs the cost of the extra unconditional jump
2889 outside the loop. */
2891 {
2892 rtx temp;
2899 }
2901 /* Include the BARRIER after INSN and copy the
2902 block after LOC. */
2907 /* All those insns are now in TARGET_LOOP. */
2913 /* The label jumped to by INSN is no longer a loop
2914 exit. Unless INSN does not have a label (e.g.,
2915 it is a RETURN insn), search loop->exit_labels
2916 to find its label_ref, and remove it. Also turn
2917 off LABEL_OUTSIDE_LOOP_P bit. */
2919 {
2921 r;
2924 {
2928 else
2931 }
2937 /* If we didn't find it, then something is
2938 wrong. */
2941 }
2943 /* P is now a jump outside the loop, so it must be put
2944 in loop->exit_labels, and marked as such.
2945 The easiest way to do this is to just call
2946 mark_loop_jump again for P. */
2949 /* If INSN now jumps to the insn after it,
2950 delete INSN. */
2955 }
2957 /* Continue the loop after where the conditional
2958 branch used to jump, since the only branch insn
2959 in the block (if it still remains) is an inter-loop
2960 branch and hence needs no processing. */
2966 /* This loop will be continued with NEXT_INSN (insn). */
2968 }
2969 }
2970 }
2971 }
2972 }
2974 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2975 loops it is contained in, mark the target loop invalid.
2977 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2979 static void
2981 rtx x;
2983 {
2989 {
3001 /* There could be a label reference in here. */
3013 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3025 /* Link together all labels that branch outside the loop. This
3026 is used by final_[bg]iv_value and the loop unrolling code. Also
3027 mark this LABEL_REF so we know that this branch should predict
3028 false. */
3030 /* A check to make sure the label is not in an inner nested loop,
3031 since this does not count as a loop exit. */
3033 {
3038 }
3039 else
3043 {
3052 }
3054 /* If this is inside a loop, but not in the current loop or one enclosed
3055 by it, it invalidates at least one loop. */
3060 /* We must invalidate every nested loop containing the target of this
3061 label, except those that also contain the jump insn. */
3064 {
3065 /* Stop when we reach a loop that also contains the jump insn. */
3070 /* If we get here, we know we need to invalidate a loop. */
3077 }
3081 /* If this is not setting pc, ignore. */
3103 /* Strictly speaking this is not a jump into the loop, only a possible
3104 jump out of the loop. However, we have no way to link the destination
3105 of this jump onto the list of exit labels. To be safe we mark this
3106 loop and any containing loops as invalid. */
3108 {
3110 {
3116 }
3117 }
3119 }
3120 }
3121 \f
3122 /* Return nonzero if there is a label in the range from
3123 insn INSN to and including the insn whose luid is END
3124 INSN must have an assigned luid (i.e., it must not have
3125 been previously created by loop.c). */
3127 static int
3129 rtx insn;
3131 {
3133 {
3137 }
3140 }
3142 /* Record that a memory reference X is being set. */
3144 static void
3146 rtx x;
3147 rtx y ATTRIBUTE_UNUSED;
3149 {
3155 /* Count number of memory writes.
3156 This affects heuristics in strength_reduce. */
3159 /* BLKmode MEM means all memory is clobbered. */
3161 {
3164 else
3168 }
3172 }
3174 /* X is a value modified by an INSN that references a biv inside a loop
3175 exit test (ie, X is somehow related to the value of the biv). If X
3176 is a pseudo that is used more than once, then the biv is (effectively)
3177 used more than once. DATA is a pointer to a loop_regs structure. */
3179 static void
3181 rtx x;
3182 rtx y ATTRIBUTE_UNUSED;
3184 {
3199 /* If we do not have usage information, or if we know the register
3200 is used more than once, note that fact for check_dbra_loop. */
3205 }
3206 \f
3207 /* Return nonzero if the rtx X is invariant over the current loop.
3209 The value is 2 if we refer to something only conditionally invariant.
3211 A memory ref is invariant if it is not volatile and does not conflict
3212 with anything stored in `loop_info->store_mems'. */
3214 int
3217 rtx x;
3218 {
3225 rtx mem_list_entry;
3231 {
3239 /* A LABEL_REF is normally invariant, however, if we are unrolling
3240 loops, and this label is inside the loop, then it isn't invariant.
3241 This is because each unrolled copy of the loop body will have
3242 a copy of this label. If this was invariant, then an insn loading
3243 the address of this label into a register might get moved outside
3244 the loop, and then each loop body would end up using the same label.
3246 We don't know the loop bounds here though, so just fail for all
3247 labels. */
3250 else
3259 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3260 since the reg might be set by initialization within the loop. */
3271 /* Out-of-range regs can occur when we are called from unrolling.
3272 These have always been created by the unroller and are set in
3273 the loop, hence are never invariant. */
3284 /* Volatile memory references must be rejected. Do this before
3285 checking for read-only items, so that volatile read-only items
3286 will be rejected also. */
3290 /* See if there is any dependence between a store and this load. */
3293 {
3299 }
3301 /* It's not invalidated by a store in memory
3302 but we must still verify the address is invariant. */
3306 /* Don't mess with insns declared volatile. */
3313 }
3317 {
3319 {
3325 }
3327 {
3330 {
3336 }
3338 }
3339 }
3342 }
3343 \f
3344 /* Return nonzero if all the insns in the loop that set REG
3345 are INSN and the immediately following insns,
3346 and if each of those insns sets REG in an invariant way
3347 (not counting uses of REG in them).
3349 The value is 2 if some of these insns are only conditionally invariant.
3351 We assume that INSN itself is the first set of REG
3352 and that its source is invariant. */
3354 static int
3359 {
3363 rtx temp;
3364 /* Number of sets we have to insist on finding after INSN. */
3370 /* If N_SETS hit the limit, we can't rely on its value. */
3377 {
3379 rtx set;
3384 /* If library call, skip to end of it. */
3393 {
3398 {
3399 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3400 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3401 notes are OK. */
3407 }
3408 }
3410 count--;
3412 {
3415 }
3416 }
3419 /* If loop_invariant_p ever returned 2, we return 2. */
3421 }
3423 #if 0
3424 /* I don't think this condition is sufficient to allow INSN
3425 to be moved, so we no longer test it. */
3427 /* Return 1 if all insns in the basic block of INSN and following INSN
3428 that set REG are invariant according to TABLE. */
3430 static int
3434 {
3439 {
3448 {
3451 }
3452 }
3453 }
3455 \f
3456 /* Look at all uses (not sets) of registers in X. For each, if it is
3457 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3458 a different insn, set USAGE[REGNO] to const0_rtx. */
3460 static void
3463 rtx insn;
3464 rtx x;
3465 {
3477 {
3478 /* Don't count SET_DEST if it is a REG; otherwise count things
3479 in SET_DEST because if a register is partially modified, it won't
3480 show up as a potential movable so we don't care how USAGE is set
3481 for it. */
3485 }
3486 else
3488 {
3494 }
3495 }
3496 \f
3497 /* Count and record any set in X which is contained in INSN. Update
3498 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3499 in X. */
3501 static void
3506 {
3508 /* Don't move a reg that has an explicit clobber.
3509 It's not worth the pain to try to do it correctly. */
3513 {
3521 {
3525 {
3526 /* If this is the first setting of this reg
3527 in current basic block, and it was set before,
3528 it must be set in two basic blocks, so it cannot
3529 be moved out of the loop. */
3533 /* If this is not first setting in current basic block,
3534 see if reg was used in between previous one and this.
3535 If so, neither one can be moved. */
3542 }
3543 }
3544 }
3545 }
3546 \f
3547 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3548 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3549 contained in insn INSN is used by any insn that precedes INSN in
3550 cyclic order starting from the loop entry point.
3552 We don't want to use INSN_LUID here because if we restrict INSN to those
3553 that have a valid INSN_LUID, it means we cannot move an invariant out
3554 from an inner loop past two loops. */
3556 static int
3560 {
3562 rtx p;
3564 /* Scan forward checking for register usage. If we hit INSN, we
3565 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3567 {
3573 }
3576 }
3577 \f
3579 /* Information we collect about arrays that we might want to prefetch. */
3580 struct prefetch_info
3581 {
3585 index. */
3586 HOST_WIDE_INT index;
3588 iteration. */
3590 prefetch area in one iteration. */
3592 This is set only for loops with known
3593 iteration counts and is 0xffffffff
3594 otherwise. */
3598 };
3600 /* Data used by check_store function. */
3601 struct check_store_data
3602 {
3603 rtx mem_address;
3605 };
3611 /* Set mem_write when mem_address is found. Used as callback to
3612 note_stores. */
3613 static void
3617 {
3622 }
3623 \f
3624 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3625 important to get some addresses combined. Later more sophisticated
3626 transformations can be added when necessary.
3628 ??? Same trick with swapping operand is done at several other places.
3629 It can be nice to develop some common way to handle this. */
3631 static int
3634 {
3648 {
3653 }
3654 /* Compare the elements. If any pair of corresponding elements fails to
3655 match, return 0 for the whole thing. */
3659 {
3661 {
3673 /* Two vectors must have the same length. */
3677 /* And the corresponding elements must match. */
3695 /* These are just backpointers, so they don't matter. */
3701 /* It is believed that rtx's at this level will never
3702 contain anything but integers and other rtx's,
3703 except for within LABEL_REFs and SYMBOL_REFs. */
3706 }
3707 }
3709 }
3710 \f
3711 /* Remove constant addition value from the expression X (when present)
3712 and return it. */
3714 static HOST_WIDE_INT
3717 {
3721 /* Avoid clobbering a shared CONST expression. */
3723 {
3727 {
3730 }
3732 }
3735 {
3738 }
3740 /* For plus expression recurse on ourself. */
3742 {
3746 /* In case our parameter was constant, remove extra zero from the
3747 expression. */
3752 }
3755 }
3757 /* Attempt to identify accesses to arrays that are most likely to cause cache
3758 misses, and emit prefetch instructions a few prefetch blocks forward.
3760 To detect the arrays we use the GIV information that was collected by the
3761 strength reduction pass.
3763 The prefetch instructions are generated after the GIV information is done
3764 and before the strength reduction process. The new GIVs are injected into
3765 the strength reduction tables, so the prefetch addresses are optimized as
3766 well.
3768 GIVs are split into base address, stride, and constant addition values.
3769 GIVs with the same address, stride and close addition values are combined
3770 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3771 for write instructions can be used for the block we write to, on machines
3772 that support write prefetches.
3774 Several heuristics are used to determine when to prefetch. They are
3775 controlled by defined symbols that can be overridden for each target. */
3777 static void
3780 {
3796 /* Consider only loops w/o calls. When a call is done, the loop is probably
3797 slow enough to read the memory. */
3799 {
3804 }
3806 /* Don't prefetch in loops known to have few iterations. */
3810 {
3815 }
3817 /* Search all induction variables and pick those interesting for the prefetch
3818 machinery. */
3820 {
3826 /* Expect all BIVs to be executed in each iteration. This makes our
3827 analysis more conservative. */
3829 {
3830 /* Discard non-constant additions that we can't handle well yet, and
3831 BIVs that are executed multiple times; such BIVs ought to be
3832 handled in the nested loop. We accept not_every_iteration BIVs,
3833 since these only result in larger strides and make our
3834 heuristics more conservative. */
3836 {
3838 {
3844 }
3846 }
3849 {
3851 {
3857 }
3859 }
3863 }
3869 {
3870 rtx address;
3871 rtx temp;
3880 /* See whether an induction variable is interesting to us and if
3881 not, report the reason. */
3885 /* We are interested only in constant stride memory references
3886 in order to be able to compute density easily. */
3890 else
3891 {
3894 {
3897 }
3899 /* On some targets, reversed order prefetches are not
3900 worthwhile. */
3904 /* Prefetch of accesses with an extreme stride might not be
3905 worthwhile, either. */
3910 /* Ignore GIVs with varying add values; we can't predict the
3911 value for the next iteration. */
3915 /* Ignore GIVs in the nested loops; they ought to have been
3916 handled already. */
3919 }
3922 {
3928 }
3930 /* Determine the pointer to the basic array we are examining. It is
3931 the sum of the BIV's initial value and the GIV's add_val. */
3941 /* When the GIV is not always executed, we might be better off by
3942 not dirtying the cache pages. */
3945 else
3946 {
3951 }
3953 /* Attempt to find another prefetch to the same array and see if we
3954 can merge this one. */
3958 {
3959 /* In case both access same array (same location
3960 just with small difference in constant indexes), merge
3961 the prefetches. Just do the later and the earlier will
3962 get prefetched from previous iteration.
3963 The artificial threshold should not be too small,
3964 but also not bigger than small portion of memory usually
3965 traversed by single loop. */
3968 {
3977 }
3981 {
3986 }
3987 }
3989 /* Merging failed. */
3991 {
3999 num_prefetches++;
4001 {
4006 }
4007 }
4008 }
4009 }
4012 {
4015 /* Attempt to calculate the total number of bytes fetched by all
4016 iterations of the loop. Avoid overflow. */
4021 else
4026 /* Prefetch might be worthwhile only when the loads/stores are dense. */
4031 {
4036 }
4037 else
4038 {
4044 }
4045 else
4048 /* Find how many prefetch instructions we'll use within the loop. */
4050 {
4056 }
4057 }
4059 /* Determine how many iterations ahead to prefetch within the loop, based
4060 on how many prefetches we currently expect to do within the loop. */
4062 {
4064 {
4070 }
4071 }
4072 /* We'll also use AHEAD to determine how many prefetch instructions to
4073 emit before a loop, so don't leave it zero. */
4078 {
4079 /* Update if we've decided not to prefetch anything within the loop. */
4083 /* Find how many prefetch instructions we'll use before the loop. */
4085 {
4093 }
4096 {
4118 }
4119 }
4122 {
4123 /* Record that this loop uses prefetch instructions. */
4127 {
4132 }
4133 }
4136 {
4140 {
4142 rtx insn;
4146 rtx seq;
4148 /* We can save some effort by offsetting the address on
4149 architectures with offsettable memory references. */
4152 else
4153 {
4159 }
4162 /* Make sure the address operand is valid for prefetch. */
4172 /* Check all insns emitted and record the new GIV
4173 information. */
4176 {
4181 }
4182 }
4185 {
4186 /* Emit insns before the loop to fetch the first cache lines or,
4187 if we're not prefetching within the loop, everything we expect
4188 to need. */
4190 {
4198 /* Functions called by LOOP_IV_ADD_EMIT_BEFORE expect a
4199 non-constant INIT_VAL to have the same mode as REG, which
4200 in this case we know to be Pmode. */
4202 {
4203 rtx seq;
4210 }
4216 loop_start);
4217 }
4218 }
4219 }
4222 }
4223 \f
4224 /* A "basic induction variable" or biv is a pseudo reg that is set
4225 (within this loop) only by incrementing or decrementing it. */
4226 /* A "general induction variable" or giv is a pseudo reg whose
4227 value is a linear function of a biv. */
4229 /* Bivs are recognized by `basic_induction_var';
4230 Givs by `general_induction_var'. */
4232 /* Communication with routines called via `note_stores'. */
4236 /* Dummy register to have nonzero DEST_REG for DEST_ADDR type givs. */
4240 /* ??? Unfinished optimizations, and possible future optimizations,
4241 for the strength reduction code. */
4243 /* ??? The interaction of biv elimination, and recognition of 'constant'
4244 bivs, may cause problems. */
4246 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4247 performance problems.
4249 Perhaps don't eliminate things that can be combined with an addressing
4250 mode. Find all givs that have the same biv, mult_val, and add_val;
4251 then for each giv, check to see if its only use dies in a following
4252 memory address. If so, generate a new memory address and check to see
4253 if it is valid. If it is valid, then store the modified memory address,
4254 otherwise, mark the giv as not done so that it will get its own iv. */
4256 /* ??? Could try to optimize branches when it is known that a biv is always
4257 positive. */
4259 /* ??? When replace a biv in a compare insn, we should replace with closest
4260 giv so that an optimized branch can still be recognized by the combiner,
4261 e.g. the VAX acb insn. */
4263 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4264 was rerun in loop_optimize whenever a register was added or moved.
4265 Also, some of the optimizations could be a little less conservative. */
4266 \f
4267 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4268 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4269 callback.
4271 NOT_EVERY_ITERATION is 1 if current insn is not known to be executed at
4272 least once for every loop iteration except for the last one.
4274 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4275 loop iteration.
4276 */
4277 void
4280 loop_insn_callback fncall;
4281 {
4286 rtx p;
4288 /* If loop_scan_start points to the loop exit test, we have to be wary of
4289 subversive use of gotos inside expression statements. */
4293 /* Scan through loop and update NOT_EVERY_ITERATION and MAYBE_MULTIPLE. */
4297 {
4300 /* Past CODE_LABEL, we get to insns that may be executed multiple
4301 times. The only way we can be sure that they can't is if every
4302 jump insn between here and the end of the loop either
4303 returns, exits the loop, is a jump to a location that is still
4304 behind the label, or is a jump to the loop start. */
4307 {
4313 {
4318 {
4321 else
4325 }
4333 {
4336 }
4337 }
4338 }
4340 /* Past a jump, we get to insns for which we can't count
4341 on whether they will be executed during each iteration. */
4342 /* This code appears twice in strength_reduce. There is also similar
4343 code in scan_loop. */
4345 /* If we enter the loop in the middle, and scan around to the
4346 beginning, don't set not_every_iteration for that.
4347 This can be any kind of jump, since we want to know if insns
4348 will be executed if the loop is executed. */
4353 {
4356 /* If this is a jump outside the loop, then it also doesn't
4357 matter. Check to see if the target of this branch is on the
4358 loop->exits_labels list. */
4366 }
4369 {
4370 /* At the virtual top of a converted loop, insns are again known to
4371 be executed each iteration: logically, the loop begins here
4372 even though the exit code has been duplicated.
4374 Insns are also again known to be executed each iteration at
4375 the LOOP_CONT note. */
4381 loop_depth++;
4383 loop_depth--;
4384 }
4386 /* Note if we pass a loop latch. If we do, then we can not clear
4387 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4388 a loop since a jump before the last CODE_LABEL may have started
4389 a new loop iteration.
4391 Note that LOOP_TOP is only set for rotated loops and we need
4392 this check for all loops, so compare against the CODE_LABEL
4393 which immediately follows LOOP_START. */
4398 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4399 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4400 or not an insn is known to be executed each iteration of the
4401 loop, whether or not any iterations are known to occur.
4403 Therefore, if we have just passed a label and have no more labels
4404 between here and the test insn of the loop, and we have not passed
4405 a jump to the top of the loop, then we know these insns will be
4406 executed each iteration. */
4409 && !past_loop_latch
4414 }
4415 }
4416 \f
4417 static void
4420 {
4423 /* Temporary list pointers for traversing ivs->list. */
4430 /* Scan ivs->list to remove all regs that proved not to be bivs.
4431 Make a sanity check against regs->n_times_set. */
4433 {
4435 /* Above happens if register modified by subreg, etc. */
4436 /* Make sure it is not recognized as a basic induction var: */
4438 /* If never incremented, it is invariant that we decided not to
4439 move. So leave it alone. */
4441 {
4452 }
4453 else
4454 {
4459 }
4460 }
4461 }
4464 /* Determine how BIVS are initialized by looking through pre-header
4465 extended basic block. */
4466 static void
4469 {
4471 /* Temporary list pointers for traversing ivs->list. */
4474 rtx p;
4476 /* Find initial value for each biv by searching backwards from loop_start,
4477 halting at first label. Also record any test condition. */
4481 {
4482 rtx test;
4492 /* Record any test of a biv that branches around the loop if no store
4493 between it and the start of loop. We only care about tests with
4494 constants and registers and only certain of those. */
4504 {
4505 /* If an NE test, we have an initial value! */
4507 {
4511 }
4512 else
4514 }
4515 }
4516 }
4519 /* Look at the each biv and see if we can say anything better about its
4520 initial value from any initializing insns set up above. (This is done
4521 in two passes to avoid missing SETs in a PARALLEL.) */
4522 static void
4525 {
4527 /* Temporary list pointers for traversing ivs->list. */
4532 {
4533 rtx src;
4534 rtx note;
4539 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4540 is a constant, use the value of that. */
4546 else
4559 {
4563 {
4566 }
4567 }
4568 /* If we can't make it a giv,
4569 let biv keep initial value of "itself". */
4572 }
4573 }
4576 /* Search the loop for general induction variables. */
4578 static void
4581 {
4583 }
4586 /* For each giv for which we still don't know whether or not it is
4587 replaceable, check to see if it is replaceable because its final value
4588 can be calculated. */
4590 static void
4593 {
4598 {
4604 }
4605 }
4608 /* Return nonzero if it is possible to eliminate the biv BL provided
4609 all givs are reduced. This is possible if either the reg is not
4610 used outside the loop, or we can compute what its final value will
4611 be. */
4613 static int
4619 {
4620 /* For architectures with a decrement_and_branch_until_zero insn,
4621 don't do this if we put a REG_NONNEG note on the endtest for this
4622 biv. */
4624 #ifdef HAVE_decrement_and_branch_until_zero
4626 {
4631 }
4632 #endif
4634 /* Check that biv is used outside loop or if it has a final value.
4635 Compare against bl->init_insn rather than loop->start. We aren't
4636 concerned with any uses of the biv between init_insn and
4637 loop->start since these won't be affected by the value of the biv
4638 elsewhere in the function, so long as init_insn doesn't use the
4639 biv itself. */
4650 {
4658 }
4660 }
4663 /* Reduce each giv of BL that we have decided to reduce. */
4665 static void
4669 {
4673 {
4676 {
4679 /* If the code for derived givs immediately below has already
4680 allocated a new_reg, we must keep it. */
4684 #ifdef AUTO_INC_DEC
4685 /* If the target has auto-increment addressing modes, and
4686 this is an address giv, then try to put the increment
4687 immediately after its use, so that flow can create an
4688 auto-increment addressing mode. */
4691 /* We don't handle reversed biv's because bl->biv->insn
4692 does not have a valid INSN_LUID. */
4696 {
4697 /* If other giv's have been combined with this one, then
4698 this will work only if all uses of the other giv's occur
4699 before this giv's insn. This is difficult to check.
4701 We simplify this by looking for the common case where
4702 there is one DEST_REG giv, and this giv's insn is the
4703 last use of the dest_reg of that DEST_REG giv. If the
4704 increment occurs after the address giv, then we can
4705 perform the optimization. (Otherwise, the increment
4706 would have to go before other_giv, and we would not be
4707 able to combine it with the address giv to get an
4708 auto-inc address.) */
4710 {
4715 {
4718 else
4720 }
4727 }
4728 /* Check for case where increment is before the address
4729 giv. Do this test in "loop order". */
4738 else
4741 #ifdef HAVE_cc0
4742 {
4743 rtx prev;
4745 /* We can't put an insn immediately after one setting
4746 cc0, or immediately before one using cc0. */
4753 }
4754 #endif
4758 }
4759 #endif
4761 /* For each place where the biv is incremented, add an insn
4762 to increment the new, reduced reg for the giv. */
4764 {
4765 rtx insert_before;
4771 else
4779 /* A multiply is acceptable here
4780 since this is presumed to be seldom executed. */
4784 }
4786 /* Add code at loop start to initialize giv's reduced reg. */
4791 }
4792 }
4793 }
4796 /* Check for givs whose first use is their definition and whose
4797 last use is the definition of another giv. If so, it is likely
4798 dead and should not be used to derive another giv nor to
4799 eliminate a biv. */
4801 static void
4805 {
4809 {
4816 {
4822 }
4823 }
4824 }
4827 static void
4832 {
4836 {
4843 /* Update expression if this was combined, in case other giv was
4844 replaced. */
4849 /* See if this register is known to be a pointer to something. If
4850 so, see if we can find the alignment. First see if there is a
4851 destination register that is a pointer. If so, this shares the
4852 alignment too. Next see if we can deduce anything from the
4853 computational information. If not, and this is a DEST_ADDR
4854 giv, at least we know that it's a pointer, though we don't know
4855 the alignment. */
4863 {
4872 }
4876 {
4884 }
4889 /* Store reduced reg as the address in the memref where we found
4890 this giv. */
4893 {
4895 }
4896 else
4897 {
4899 rtx note;
4901 /* Not replaceable; emit an insn to set the original giv reg from
4902 the reduced giv, same as above. */
4907 /* The original insn may have a REG_EQUAL note. This note is
4908 now incorrect and may result in invalid substitutions later.
4909 The original insn is dead, but may be part of a libcall
4910 sequence, which doesn't seem worth the bother of handling. */
4914 }
4916 /* When a loop is reversed, givs which depend on the reversed
4917 biv, and which are live outside the loop, must be set to their
4918 correct final value. This insn is only needed if the giv is
4919 not replaceable. The correct final value is the same as the
4920 value that the giv starts the reversed loop with. */
4931 {
4936 }
4937 }
4938 }
4941 static int
4946 rtx test_reg;
4947 {
4956 /* Reduce benefit if not replaceable, since we will insert a
4957 move-insn to replace the insn that calculates this giv. Don't do
4958 this unless the giv is a user variable, since it will often be
4959 marked non-replaceable because of the duplication of the exit
4960 code outside the loop. In such a case, the copies we insert are
4961 dead and will be deleted. So they don't have a cost. Similar
4962 situations exist. */
4963 /* ??? The new final_[bg]iv_value code does a much better job of
4964 finding replaceable giv's, and hence this code may no longer be
4965 necessary. */
4970 /* Decrease the benefit to count the add-insns that we will insert
4971 to increment the reduced reg for the giv. ??? This can
4972 overestimate the run-time cost of the additional insns, e.g. if
4973 there are multiple basic blocks that increment the biv, but only
4974 one of these blocks is executed during each iteration. There is
4975 no good way to detect cases like this with the current structure
4976 of the loop optimizer. This code is more accurate for
4977 determining code size than run-time benefits. */
4980 /* Decide whether to strength-reduce this giv or to leave the code
4981 unchanged (recompute it from the biv each time it is used). This
4982 decision can be made independently for each giv. */
4984 #ifdef AUTO_INC_DEC
4985 /* Attempt to guess whether autoincrement will handle some of the
4986 new add insns; if so, increase BENEFIT (undo the subtraction of
4987 add_cost that was done above). */
4989 /* Increasing the benefit is risky, since this is only a guess.
4990 Avoid increasing register pressure in cases where there would
4991 be no other benefit from reducing this giv. */
4994 {
5009 }
5010 #endif
5013 }
5016 /* Free IV structures for LOOP. */
5018 static void
5021 {
5028 {
5034 {
5037 }
5039 {
5042 }
5046 }
5047 }
5050 /* Perform strength reduction and induction variable elimination.
5052 Pseudo registers created during this function will be beyond the
5053 last valid index in several tables including
5054 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
5055 problem here, because the added registers cannot be givs outside of
5056 their loop, and hence will never be reconsidered. But scan_loop
5057 must check regnos to make sure they are in bounds. */
5059 static void
5063 {
5067 rtx p;
5068 /* Temporary list pointer for traversing ivs->list. */
5070 /* Ratio of extra register life span we can justify
5071 for saving an instruction. More if loop doesn't call subroutines
5072 since in that case saving an insn makes more difference
5073 and more registers are available. */
5074 /* ??? could set this to last value of threshold in move_movables */
5076 /* Map of pseudo-register replacements. */
5088 /* Find all BIVs in loop. */
5091 /* Exit if there are no bivs. */
5093 {
5094 /* Can still unroll the loop anyways, but indicate that there is no
5095 strength reduction info available. */
5101 }
5103 /* Determine how BIVS are initialized by looking through pre-header
5104 extended basic block. */
5107 /* Look at the each biv and see if we can say anything better about its
5108 initial value from any initializing insns set up above. */
5111 /* Search the loop for general induction variables. */
5114 /* Try to calculate and save the number of loop iterations. This is
5115 set to zero if the actual number can not be calculated. This must
5116 be called after all giv's have been identified, since otherwise it may
5117 fail if the iteration variable is a giv. */
5120 #ifdef HAVE_prefetch
5123 #endif
5125 /* Now for each giv for which we still don't know whether or not it is
5126 replaceable, check to see if it is replaceable because its final value
5127 can be calculated. This must be done after loop_iterations is called,
5128 so that final_giv_value will work correctly. */
5131 /* Try to prove that the loop counter variable (if any) is always
5132 nonnegative; if so, record that fact with a REG_NONNEG note
5133 so that "decrement and branch until zero" insn can be used. */
5136 /* Create reg_map to hold substitutions for replaceable giv regs.
5137 Some givs might have been made from biv increments, so look at
5138 ivs->reg_iv_type for a suitable size. */
5142 /* Examine each iv class for feasibility of strength reduction/induction
5143 variable elimination. */
5146 {
5150 /* Test whether it will be possible to eliminate this biv
5151 provided all givs are reduced. */
5154 /* This will be true at the end, if all givs which depend on this
5155 biv have been strength reduced.
5156 We can't (currently) eliminate the biv unless this is so. */
5159 /* Check each extension dependent giv in this class to see if its
5160 root biv is safe from wrapping in the interior mode. */
5163 /* Combine all giv's for this iv_class. */
5167 {
5175 /* If an insn is not to be strength reduced, then set its ignore
5176 flag, and clear bl->all_reduced. */
5178 /* A giv that depends on a reversed biv must be reduced if it is
5179 used after the loop exit, otherwise, it would have the wrong
5180 value after the loop exit. To make it simple, just reduce all
5181 of such giv's whether or not we know they are used after the loop
5182 exit. */
5187 {
5195 }
5196 else
5197 {
5198 /* Check that we can increment the reduced giv without a
5199 multiply insn. If not, reject it. */
5204 {
5212 }
5213 }
5214 }
5216 /* Check for givs whose first use is their definition and whose
5217 last use is the definition of another giv. If so, it is likely
5218 dead and should not be used to derive another giv nor to
5219 eliminate a biv. */
5222 /* Reduce each giv that we decided to reduce. */
5225 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5226 as not reduced.
5228 For each giv register that can be reduced now: if replaceable,
5229 substitute reduced reg wherever the old giv occurs;
5230 else add new move insn "giv_reg = reduced_reg". */
5233 /* All the givs based on the biv bl have been reduced if they
5234 merit it. */
5236 /* For each giv not marked as maybe dead that has been combined with a
5237 second giv, clear any "maybe dead" mark on that second giv.
5238 v->new_reg will either be or refer to the register of the giv it
5239 combined with.
5241 Doing this clearing avoids problems in biv elimination where
5242 a giv's new_reg is a complex value that can't be put in the
5243 insn but the giv combined with (with a reg as new_reg) is
5244 marked maybe_dead. Since the register will be used in either
5245 case, we'd prefer it be used from the simpler giv. */
5251 /* Try to eliminate the biv, if it is a candidate.
5252 This won't work if ! bl->all_reduced,
5253 since the givs we planned to use might not have been reduced.
5255 We have to be careful that we didn't initially think we could
5256 eliminate this biv because of a giv that we now think may be
5257 dead and shouldn't be used as a biv replacement.
5259 Also, there is the possibility that we may have a giv that looks
5260 like it can be used to eliminate a biv, but the resulting insn
5261 isn't valid. This can happen, for example, on the 88k, where a
5262 JUMP_INSN can compare a register only with zero. Attempts to
5263 replace it with a compare with a constant will fail.
5265 Note that in cases where this call fails, we may have replaced some
5266 of the occurrences of the biv with a giv, but no harm was done in
5267 doing so in the rare cases where it can occur. */
5271 {
5272 /* ?? If we created a new test to bypass the loop entirely,
5273 or otherwise drop straight in, based on this test, then
5274 we might want to rewrite it also. This way some later
5275 pass has more hope of removing the initialization of this
5276 biv entirely. */
5278 /* If final_value != 0, then the biv may be used after loop end
5279 and we must emit an insn to set it just in case.
5281 Reversed bivs already have an insn after the loop setting their
5282 value, so we don't need another one. We can't calculate the
5283 proper final value for such a biv here anyways. */
5292 }
5293 /* See above note wrt final_value. But since we couldn't eliminate
5294 the biv, we must set the value after the loop instead of before. */
5298 }
5300 /* Go through all the instructions in the loop, making all the
5301 register substitutions scheduled in REG_MAP. */
5306 {
5310 }
5313 {
5314 /* When we completely unroll a loop we will likely not need the increment
5315 of the loop BIV and we will not need the conditional branch at the
5316 end of the loop. */
5319 #ifdef HAVE_cc0
5320 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5321 need the comparison before the conditional branch at the end of the
5322 loop. */
5324 #endif
5326 /* We'll need one copy for each loop iteration. */
5329 /* A little slop to account for the ability to remove initialization
5330 code, better CSE, and other secondary benefits of completely
5331 unrolling some loops. */
5334 /* Clamp the value. */
5337 }
5339 /* Unroll loops from within strength reduction so that we can use the
5340 induction variable information that strength_reduce has already
5341 collected. Always unroll loops that would be as small or smaller
5342 unrolled than when rolled. */
5349 #ifdef HAVE_doloop_end
5354 /* In case number of iterations is known, drop branch prediction note
5355 in the branch. Do that only in second loop pass, as loop unrolling
5356 may change the number of iterations performed. */
5358 {
5359 unsigned HOST_WIDE_INT n
5364 }
5372 }
5373 \f
5374 /*Record all basic induction variables calculated in the insn. */
5375 static rtx
5378 rtx p;
5381 {
5383 rtx set;
5384 rtx dest_reg;
5385 rtx inc_val;
5386 rtx mult_val;
5392 {
5397 {
5402 {
5403 /* It is a possible basic induction variable.
5404 Create and initialize an induction structure for it. */
5412 }
5415 }
5416 }
5418 }
5419 \f
5420 /* Record all givs calculated in the insn.
5421 A register is a giv if: it is only set once, it is a function of a
5422 biv and a constant (or invariant), and it is not a biv. */
5423 static rtx
5426 rtx p;
5429 {
5432 rtx set;
5433 /* Look for a general induction variable in a register. */
5438 {
5439 rtx src_reg;
5440 rtx dest_reg;
5441 rtx add_val;
5442 rtx mult_val;
5443 rtx ext_val;
5446 rtx last_consec_insn;
5455 /* Equivalent expression is a giv. */
5460 /* Don't try to handle any regs made by loop optimization.
5461 We have nothing on them in regno_first_uid, etc. */
5463 /* Don't recognize a BASIC_INDUCT_VAR here. */
5465 /* This must be the only place where the register is set. */
5467 /* or all sets must be consecutive and make a giv. */
5472 {
5476 /* If this is a library call, increase benefit. */
5480 /* Skip the consecutive insns, if there are any. */
5488 }
5489 }
5491 #ifndef DONT_REDUCE_ADDR
5492 /* Look for givs which are memory addresses. */
5493 /* This resulted in worse code on a VAX 8600. I wonder if it
5494 still does. */
5497 maybe_multiple);
5498 #endif
5500 /* Update the status of whether giv can derive other givs. This can
5501 change when we pass a label or an insn that updates a biv. */
5506 }
5507 \f
5508 /* Return 1 if X is a valid source for an initial value (or as value being
5509 compared against in an initial test).
5511 X must be either a register or constant and must not be clobbered between
5512 the current insn and the start of the loop.
5514 INSN is the insn containing X. */
5516 static int
5518 rtx x;
5519 rtx insn;
5521 rtx loop_start;
5522 {
5526 /* Only consider pseudos we know about initialized in insns whose luids
5527 we know. */
5532 /* Don't use call-clobbered registers across a call which clobbers it. On
5533 some machines, don't use any hard registers at all. */
5535 && (SMALL_REGISTER_CLASSES
5539 /* Don't use registers that have been clobbered before the start of the
5540 loop. */
5545 }
5546 \f
5547 /* Scan X for memory refs and check each memory address
5548 as a possible giv. INSN is the insn whose pattern X comes from.
5549 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5550 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5551 more than once in each loop iteration. */
5553 static void
5556 rtx x;
5557 rtx insn;
5559 {
5569 {
5585 {
5586 rtx src_reg;
5587 rtx add_val;
5588 rtx mult_val;
5589 rtx ext_val;
5592 /* This code used to disable creating GIVs with mult_val == 1 and
5593 add_val == 0. However, this leads to lost optimizations when
5594 it comes time to combine a set of related DEST_ADDR GIVs, since
5595 this one would not be seen. */
5600 {
5601 /* Found one; record it. */
5610 }
5611 }
5616 }
5618 /* Recursively scan the subexpressions for other mem refs. */
5624 maybe_multiple);
5628 maybe_multiple);
5629 }
5630 \f
5631 /* Fill in the data about one biv update.
5632 V is the `struct induction' in which we record the biv. (It is
5633 allocated by the caller, with alloca.)
5634 INSN is the insn that sets it.
5635 DEST_REG is the biv's reg.
5637 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5638 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5639 being set to INC_VAL.
5641 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5642 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5643 can be executed more than once per iteration. If MAYBE_MULTIPLE
5644 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5645 executed exactly once per iteration. */
5647 static void
5652 rtx insn;
5653 rtx dest_reg;
5654 rtx inc_val;
5655 rtx mult_val;
5659 {
5675 /* Add this to the reg's iv_class, creating a class
5676 if this is the first incrementation of the reg. */
5680 {
5681 /* Create and initialize new iv_class. */
5691 /* Set initial value to the reg itself. */
5694 /* We haven't seen the initializing insn yet */
5704 /* Add this class to ivs->list. */
5708 /* Put it in the array of biv register classes. */
5710 }
5712 /* Update IV_CLASS entry for this biv. */
5721 }
5722 \f
5723 /* Fill in the data about one giv.
5724 V is the `struct induction' in which we record the giv. (It is
5725 allocated by the caller, with alloca.)
5726 INSN is the insn that sets it.
5727 BENEFIT estimates the savings from deleting this insn.
5728 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5729 into a register or is used as a memory address.
5731 SRC_REG is the biv reg which the giv is computed from.
5732 DEST_REG is the giv's reg (if the giv is stored in a reg).
5733 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5734 LOCATION points to the place where this giv's value appears in INSN. */
5736 static void
5741 rtx insn;
5742 rtx src_reg;
5743 rtx dest_reg;
5749 {
5754 rtx temp;
5756 /* Attempt to prove constantness of the values. Don't let simplify_rtx
5757 undo the MULT canonicalization that we performed earlier. */
5787 /* The v->always_computable field is used in update_giv_derive, to
5788 determine whether a giv can be used to derive another giv. For a
5789 DEST_REG giv, INSN computes a new value for the giv, so its value
5790 isn't computable if INSN insn't executed every iteration.
5791 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5792 it does not compute a new value. Hence the value is always computable
5793 regardless of whether INSN is executed each iteration. */
5797 else
5803 {
5806 }
5808 {
5813 /* If the lifetime is zero, it means that this register is
5814 really a dead store. So mark this as a giv that can be
5815 ignored. This will not prevent the biv from being eliminated. */
5821 }
5823 /* Add the giv to the class of givs computed from one biv. */
5827 {
5830 /* Don't count DEST_ADDR. This is supposed to count the number of
5831 insns that calculate givs. */
5835 }
5836 else
5837 /* Fatal error, biv missing for this giv? */
5841 {
5844 }
5845 else
5846 {
5847 /* The giv can be replaced outright by the reduced register only if all
5848 of the following conditions are true:
5849 - the insn that sets the giv is always executed on any iteration
5850 on which the giv is used at all
5851 (there are two ways to deduce this:
5852 either the insn is executed on every iteration,
5853 or all uses follow that insn in the same basic block),
5854 - the giv is not used outside the loop
5855 - no assignments to the biv occur during the giv's lifetime. */
5858 /* Previous line always fails if INSN was moved by loop opt. */
5861 && (! not_every_iteration
5863 {
5864 /* Now check that there are no assignments to the biv within the
5865 giv's lifetime. This requires two separate checks. */
5867 /* Check each biv update, and fail if any are between the first
5868 and last use of the giv.
5870 If this loop contains an inner loop that was unrolled, then
5871 the insn modifying the biv may have been emitted by the loop
5872 unrolling code, and hence does not have a valid luid. Just
5873 mark the biv as not replaceable in this case. It is not very
5874 useful as a biv, because it is used in two different loops.
5875 It is very unlikely that we would be able to optimize the giv
5876 using this biv anyways. */
5881 {
5887 {
5891 }
5892 }
5894 /* If there are any backwards branches that go from after the
5895 biv update to before it, then this giv is not replaceable. */
5899 {
5903 }
5904 }
5905 else
5906 {
5907 /* May still be replaceable, we don't have enough info here to
5908 decide. */
5911 }
5912 }
5914 /* Record whether the add_val contains a const_int, for later use by
5915 combine_givs. */
5916 {
5921 ;
5925 {
5927 {
5932 else
5934 }
5937 }
5938 }
5942 }
5944 /* All this does is determine whether a giv can be made replaceable because
5945 its final value can be calculated. This code can not be part of record_giv
5946 above, because final_giv_value requires that the number of loop iterations
5947 be known, and that can not be accurately calculated until after all givs
5948 have been identified. */
5950 static void
5954 {
5957 /* DEST_ADDR givs will never reach here, because they are always marked
5958 replaceable above in record_giv. */
5960 /* The giv can be replaced outright by the reduced register only if all
5961 of the following conditions are true:
5962 - the insn that sets the giv is always executed on any iteration
5963 on which the giv is used at all
5964 (there are two ways to deduce this:
5965 either the insn is executed on every iteration,
5966 or all uses follow that insn in the same basic block),
5967 - its final value can be calculated (this condition is different
5968 than the one above in record_giv)
5969 - it's not used before the it's set
5970 - no assignments to the biv occur during the giv's lifetime. */
5972 #if 0
5973 /* This is only called now when replaceable is known to be false. */
5974 /* Clear replaceable, so that it won't confuse final_giv_value. */
5976 #endif
5981 {
5984 rtx last_giv_use;
5989 /* When trying to determine whether or not a biv increment occurs
5990 during the lifetime of the giv, we can ignore uses of the variable
5991 outside the loop because final_value is true. Hence we can not
5992 use regno_last_uid and regno_first_uid as above in record_giv. */
5994 /* Search the loop to determine whether any assignments to the
5995 biv occur during the giv's lifetime. Start with the insn
5996 that sets the giv, and search around the loop until we come
5997 back to that insn again.
5999 Also fail if there is a jump within the giv's lifetime that jumps
6000 to somewhere outside the lifetime but still within the loop. This
6001 catches spaghetti code where the execution order is not linear, and
6002 hence the above test fails. Here we assume that the giv lifetime
6003 does not extend from one iteration of the loop to the next, so as
6004 to make the test easier. Since the lifetime isn't known yet,
6005 this requires two loops. See also record_giv above. */
6010 {
6013 {
6016 }
6022 {
6023 /* It is possible for the BIV increment to use the GIV if we
6024 have a cycle. Thus we must be sure to check each insn for
6025 both BIV and GIV uses, and we must check for BIV uses
6026 first. */
6033 {
6035 {
6039 }
6041 }
6042 }
6043 }
6045 /* Now that the lifetime of the giv is known, check for branches
6046 from within the lifetime to outside the lifetime if it is still
6047 replaceable. */
6050 {
6053 {
6066 {
6075 }
6076 }
6077 }
6079 /* If it is replaceable, then save the final value. */
6082 }
6087 }
6088 \f
6089 /* Update the status of whether a giv can derive other givs.
6091 We need to do something special if there is or may be an update to the biv
6092 between the time the giv is defined and the time it is used to derive
6093 another giv.
6095 In addition, a giv that is only conditionally set is not allowed to
6096 derive another giv once a label has been passed.
6098 The cases we look at are when a label or an update to a biv is passed. */
6100 static void
6103 rtx p;
6104 {
6108 rtx tem;
6111 /* Search all IV classes, then all bivs, and finally all givs.
6113 There are three cases we are concerned with. First we have the situation
6114 of a giv that is only updated conditionally. In that case, it may not
6115 derive any givs after a label is passed.
6117 The second case is when a biv update occurs, or may occur, after the
6118 definition of a giv. For certain biv updates (see below) that are
6119 known to occur between the giv definition and use, we can adjust the
6120 giv definition. For others, or when the biv update is conditional,
6121 we must prevent the giv from deriving any other givs. There are two
6122 sub-cases within this case.
6124 If this is a label, we are concerned with any biv update that is done
6125 conditionally, since it may be done after the giv is defined followed by
6126 a branch here (actually, we need to pass both a jump and a label, but
6127 this extra tracking doesn't seem worth it).
6129 If this is a jump, we are concerned about any biv update that may be
6130 executed multiple times. We are actually only concerned about
6131 backward jumps, but it is probably not worth performing the test
6132 on the jump again here.
6134 If this is a biv update, we must adjust the giv status to show that a
6135 subsequent biv update was performed. If this adjustment cannot be done,
6136 the giv cannot derive further givs. */
6142 {
6144 {
6145 /* If cant_derive is already true, there is no point in
6146 checking all of these conditions again. */
6150 /* If this giv is conditionally set and we have passed a label,
6151 it cannot derive anything. */
6155 /* Skip givs that have mult_val == 0, since
6156 they are really invariants. Also skip those that are
6157 replaceable, since we know their lifetime doesn't contain
6158 any biv update. */
6162 /* The only way we can allow this giv to derive another
6163 is if this is a biv increment and we can form the product
6164 of biv->add_val and giv->mult_val. In this case, we will
6165 be able to compute a compensation. */
6167 {
6168 rtx ext_val_dummy;
6179 tem = simplify_giv_expr
6186 else
6188 }
6192 }
6193 }
6194 }
6195 \f
6196 /* Check whether an insn is an increment legitimate for a basic induction var.
6197 X is the source of insn P, or a part of it.
6198 MODE is the mode in which X should be interpreted.
6200 DEST_REG is the putative biv, also the destination of the insn.
6201 We accept patterns of these forms:
6202 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6203 REG = INVARIANT + REG
6205 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6206 store the additive term into *INC_VAL, and store the place where
6207 we found the additive term into *LOCATION.
6209 If X is an assignment of an invariant into DEST_REG, we set
6210 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6212 We also want to detect a BIV when it corresponds to a variable
6213 whose mode was promoted via PROMOTED_MODE. In that case, an increment
6214 of the variable may be a PLUS that adds a SUBREG of that variable to
6215 an invariant and then sign- or zero-extends the result of the PLUS
6216 into the variable.
6218 Most GIVs in such cases will be in the promoted mode, since that is the
6219 probably the natural computation mode (and almost certainly the mode
6220 used for addresses) on the machine. So we view the pseudo-reg containing
6221 the variable as the BIV, as if it were simply incremented.
6223 Note that treating the entire pseudo as a BIV will result in making
6224 simple increments to any GIVs based on it. However, if the variable
6225 overflows in its declared mode but not its promoted mode, the result will
6226 be incorrect. This is acceptable if the variable is signed, since
6227 overflows in such cases are undefined, but not if it is unsigned, since
6228 those overflows are defined. So we only check for SIGN_EXTEND and
6229 not ZERO_EXTEND.
6231 If we cannot find a biv, we return 0. */
6233 static int
6236 rtx x;
6238 rtx dest_reg;
6239 rtx p;
6243 {
6251 {
6257 {
6259 }
6264 {
6266 }
6267 else
6280 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6281 handle addition of promoted variables.
6282 ??? The comment at the start of this function is wrong: promoted
6283 variable increments don't look like it says they do. */
6289 /* If this register is assigned in a previous insn, look at its
6290 source, but don't go outside the loop or past a label. */
6292 /* If this sets a register to itself, we would repeat any previous
6293 biv increment if we applied this strategy blindly. */
6299 {
6300 rtx dest;
6301 do
6302 {
6304 }
6333 }
6334 /* Fall through. */
6336 /* Can accept constant setting of biv only when inside inner most loop.
6337 Otherwise, a biv of an inner loop may be incorrectly recognized
6338 as a biv of the outer loop,
6339 causing code to be moved INTO the inner loop. */
6346 /* convert_modes aborts if we try to convert to or from CCmode, so just
6347 exclude that case. It is very unlikely that a condition code value
6348 would be a useful iterator anyways. convert_modes aborts if we try to
6349 convert a float mode to non-float or vice versa too. */
6353 {
6354 /* Possible bug here? Perhaps we don't know the mode of X. */
6358 }
6359 else
6367 /* Similar, since this can be a sign extension. */
6372 ;
6386 location);
6391 }
6392 }
6393 \f
6394 /* A general induction variable (giv) is any quantity that is a linear
6395 function of a basic induction variable,
6396 i.e. giv = biv * mult_val + add_val.
6397 The coefficients can be any loop invariant quantity.
6398 A giv need not be computed directly from the biv;
6399 it can be computed by way of other givs. */
6401 /* Determine whether X computes a giv.
6402 If it does, return a nonzero value
6403 which is the benefit from eliminating the computation of X;
6404 set *SRC_REG to the register of the biv that it is computed from;
6405 set *ADD_VAL and *MULT_VAL to the coefficients,
6406 such that the value of X is biv * mult + add; */
6408 static int
6412 rtx x;
6420 {
6424 /* If this is an invariant, forget it, it isn't a giv. */
6435 {
6438 /* Since this is now an invariant and wasn't before, it must be a giv
6439 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6440 with. */
6447 /* This is equivalent to a BIV. */
6454 /* Either (plus (biv) (invar)) or
6455 (plus (mult (biv) (invar_1)) (invar_2)). */
6457 {
6460 }
6461 else
6462 {
6465 }
6470 /* ADD_VAL is zero. */
6478 }
6480 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6481 unless they are CONST_INT). */
6489 else
6492 /* Always return true if this is a giv so it will be detected as such,
6493 even if the benefit is zero or negative. This allows elimination
6494 of bivs that might otherwise not be eliminated. */
6496 }
6497 \f
6498 /* Given an expression, X, try to form it as a linear function of a biv.
6499 We will canonicalize it to be of the form
6500 (plus (mult (BIV) (invar_1))
6501 (invar_2))
6502 with possible degeneracies.
6504 The invariant expressions must each be of a form that can be used as a
6505 machine operand. We surround then with a USE rtx (a hack, but localized
6506 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6507 routine; it is the caller's responsibility to strip them.
6509 If no such canonicalization is possible (i.e., two biv's are used or an
6510 expression that is neither invariant nor a biv or giv), this routine
6511 returns 0.
6513 For a nonzero return, the result will have a code of CONST_INT, USE,
6514 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6516 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6521 static rtx
6524 rtx x;
6527 {
6532 rtx tem;
6534 /* If this is not an integer mode, or if we cannot do arithmetic in this
6535 mode, this can't be a giv. */
6542 {
6549 /* Put constant last, CONST_INT last if both constant. */
6557 /* Handle addition of zero, then addition of an invariant. */
6562 {
6565 /* Adding two invariants must result in an invariant, so enclose
6566 addition operation inside a USE and return it. */
6576 else
6585 /* biv + invar or mult + invar. Return sum. */
6589 /* (a + invar_1) + invar_2. Associate. */
6590 return
6596 arg1)),
6601 }
6603 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6604 MULT to reduce cases. */
6610 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6611 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6612 Recurse to associate the second PLUS. */
6617 return
6625 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6641 /* Handle "a - b" as "a + b * (-1)". */
6647 constm1_rtx)),
6656 /* Put constant last, CONST_INT last if both constant. */
6661 /* If second argument is not now constant, not giv. */
6665 /* Handle multiply by 0 or 1. */
6673 {
6675 /* biv * invar. Done. */
6679 /* Product of two constants. */
6683 /* invar * invar is a giv, but attempt to simplify it somehow. */
6689 {
6690 /* (invar_0 * invar_1) * invar_2. Associate. */
6697 arg1)),
6699 }
6700 /* Propagate the MULT expressions to the intermost nodes. */
6702 {
6703 /* (invar_0 + invar_1) * invar_2. Distribute. */
6709 arg1),
6713 arg1)),
6715 }
6719 /* (a * invar_1) * invar_2. Associate. */
6725 arg1)),
6729 /* (a + invar_1) * invar_2. Distribute. */
6734 arg1),
6737 arg1)),
6742 }
6745 /* Shift by constant is multiply by power of two. */
6749 return
6758 /* "-a" is "a * (-1)" */
6764 /* "~a" is "-a - 1". Silly, but easy. */
6768 const1_rtx),
6772 /* Already in proper form for invariant. */
6778 /* Conditionally recognize extensions of simple IVs. After we've
6779 computed loop traversal counts and verified the range of the
6780 source IV, we'll reevaluate this as a GIV. */
6782 {
6785 {
6788 }
6789 }
6793 /* If this is a new register, we can't deal with it. */
6797 /* Check for biv or giv. */
6799 {
6803 {
6806 /* Form expression from giv and add benefit. Ensure this giv
6807 can derive another and subtract any needed adjustment if so. */
6809 /* Increasing the benefit here is risky. The only case in which it
6810 is arguably correct is if this is the only use of V. In other
6811 cases, this will artificially inflate the benefit of the current
6812 giv, and lead to suboptimal code. Thus, it is disabled, since
6813 potentially not reducing an only marginally beneficial giv is
6814 less harmful than reducing many givs that are not really
6815 beneficial. */
6816 {
6820 }
6833 {
6836 }
6837 else
6838 {
6841 }
6843 }
6846 do_default:
6847 /* If it isn't an induction variable, and it is invariant, we
6848 may be able to simplify things further by looking through
6849 the bits we just moved outside the loop. */
6851 {
6857 {
6858 /* Ok, we found a match. Substitute and simplify. */
6860 /* If we match another movable, we must use that, as
6861 this one is going away. */
6866 /* If consec is nonzero, this is a member of a group of
6867 instructions that were moved together. We handle this
6868 case only to the point of seeking to the last insn and
6869 looking for a REG_EQUAL. Fail if we don't find one. */
6871 {
6874 do
6875 {
6877 }
6883 }
6884 else
6885 {
6889 }
6892 {
6893 /* What we are most interested in is pointer
6894 arithmetic on invariants -- only take
6895 patterns we may be able to do something with. */
6901 {
6903 benefit);
6906 }
6911 {
6916 }
6917 }
6919 }
6920 }
6922 }
6924 /* Fall through to general case. */
6926 /* If invariant, return as USE (unless CONST_INT).
6927 Otherwise, not giv. */
6932 {
6941 }
6942 else
6944 }
6945 }
6947 /* This routine folds invariants such that there is only ever one
6948 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6950 static rtx
6953 {
6959 {
6962 }
6965 {
6968 }
6969 else
6970 {
6973 }
6974 }
6976 static rtx
6980 {
6982 {
6986 else
6989 }
6992 else
6995 }
6996 \f
6997 /* Help detect a giv that is calculated by several consecutive insns;
6998 for example,
6999 giv = biv * M
7000 giv = giv + A
7001 The caller has already identified the first insn P as having a giv as dest;
7002 we check that all other insns that set the same register follow
7003 immediately after P, that they alter nothing else,
7004 and that the result of the last is still a giv.
7006 The value is 0 if the reg set in P is not really a giv.
7007 Otherwise, the value is the amount gained by eliminating
7008 all the consecutive insns that compute the value.
7010 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
7011 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
7013 The coefficients of the ultimate giv value are stored in
7014 *MULT_VAL and *ADD_VAL. */
7016 static int
7021 rtx p;
7022 rtx src_reg;
7023 rtx dest_reg;
7028 {
7034 rtx temp;
7035 rtx set;
7037 /* Indicate that this is a giv so that we can update the value produced in
7038 each insn of the multi-insn sequence.
7040 This induction structure will be used only by the call to
7041 general_induction_var below, so we can allocate it on our stack.
7042 If this is a giv, our caller will replace the induct var entry with
7043 a new induction structure. */
7064 {
7068 /* If libcall, skip to end of call sequence. */
7079 /* Giv created by equivalent expression. */
7085 {
7089 count--;
7093 }
7095 {
7096 /* Allow insns that set something other than this giv to a
7097 constant. Such insns are needed on machines which cannot
7098 include long constants and should not disqualify a giv. */
7107 }
7108 }
7113 }
7114 \f
7115 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7116 represented by G1. If no such expression can be found, or it is clear that
7117 it cannot possibly be a valid address, 0 is returned.
7119 To perform the computation, we note that
7120 G1 = x * v + a and
7121 G2 = y * v + b
7122 where `v' is the biv.
7124 So G2 = (y/b) * G1 + (b - a*y/x).
7126 Note that MULT = y/x.
7128 Update: A and B are now allowed to be additive expressions such that
7129 B contains all variables in A. That is, computing B-A will not require
7130 subtracting variables. */
7132 static rtx
7135 {
7136 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7141 /* If MULT is not 1, we cannot handle A with non-constants, since we
7142 would then be required to subtract multiples of the registers in A.
7143 This is theoretically possible, and may even apply to some Fortran
7144 constructs, but it is a lot of work and we do not attempt it here. */
7149 /* In general these structures are sorted top to bottom (down the PLUS
7150 chain), but not left to right across the PLUS. If B is a higher
7151 order giv than A, we can strip one level and recurse. If A is higher
7152 order, we'll eventually bail out, but won't know that until the end.
7153 If they are the same, we'll strip one level around this loop. */
7156 {
7168 /* We matched: remove one reg completely. */
7171 /* An alternate match. */
7174 /* An alternate match. */
7176 else
7177 {
7178 /* Indicates an extra register in B. Strip one level from B and
7179 recurse, hoping B was the higher order expression. */
7184 }
7185 }
7187 /* Here we are at the last level of A, go through the cases hoping to
7188 get rid of everything but a constant. */
7191 {
7204 }
7206 {
7208 }
7210 {
7215 }
7217 {
7222 else
7224 }
7229 }
7231 rtx
7234 {
7237 /* The value that G1 will be multiplied by must be a constant integer. Also,
7238 the only chance we have of getting a valid address is if b*c/a (see above
7239 for notation) is also an integer. */
7242 {
7247 }
7250 else
7251 {
7252 /* ??? Find out if the one is a multiple of the other? */
7254 }
7258 {
7259 /* Failed. If we've got a multiplication factor between G1 and G2,
7260 scale G1's addend and try again. */
7262 {
7266 {
7267 HOST_WIDE_INT m;
7271 }
7272 else
7273 {
7275 mult);
7276 }
7279 }
7280 }
7284 /* Form simplified final result. */
7289 else
7294 else
7295 {
7298 {
7302 }
7305 }
7306 }
7307 \f
7308 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7309 represented by G1. This indicates that G2 should be combined with G1 and
7310 that G2 can use (either directly or via an address expression) a register
7311 used to represent G1. */
7313 static rtx
7316 {
7319 /* With the introduction of ext dependent givs, we must care for modes.
7320 G2 must not use a wider mode than G1. */
7330 /* If these givs are identical, they can be combined. We use the results
7331 of express_from because the addends are not in a canonical form, so
7332 rtx_equal_p is a weaker test. */
7333 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7334 combination to be the other way round. */
7337 {
7339 }
7341 /* If G2 can be expressed as a function of G1 and that function is valid
7342 as an address and no more expensive than using a register for G2,
7343 the expression of G2 in terms of G1 can be used. */
7350 }
7351 \f
7352 /* Check each extension dependent giv in this class to see if its
7353 root biv is safe from wrapping in the interior mode, which would
7354 make the giv illegal. */
7356 static void
7360 {
7363 HOST_WIDE_INT start_val;
7369 /* Make sure the iteration data is available. We must have
7370 constants in order to be certain of no overflow. */
7371 /* ??? An unknown iteration count with an increment of +-1
7372 combined with friendly exit tests of against an invariant
7373 value is also amenable to optimization. Not implemented. */
7379 /* Make sure the host can represent the arithmetic. */
7381 {
7383 HOST_WIDE_INT s_end_val;
7395 /* Check for host arithmetic overflow. */
7397 {
7399 HOST_WIDE_INT s_max;
7406 /* Check zero extension of biv ok. */
7408 /* Check for host arithmetic overflow. */
7409 && (neg_incr
7412 /* Check for target arithmetic overflow. */
7413 && (neg_incr
7416 {
7418 }
7420 /* Check sign extension of biv ok. */
7421 /* ??? While it is true that overflow with signed and pointer
7422 arithmetic is undefined, I fear too many programmers don't
7423 keep this fact in mind -- myself included on occasion.
7424 So leave alone with the signed overflow optimizations. */
7426 /* Check for host arithmetic overflow. */
7427 && (neg_incr
7430 /* Check for target arithmetic overflow. */
7431 && (neg_incr
7434 {
7436 }
7437 }
7438 }
7440 /* Invalidate givs that fail the tests. */
7443 {
7448 {
7457 /* We don't know whether this value is being used as either
7458 signed or unsigned, so to safely truncate we must satisfy
7459 both. The initial check here verifies the BIV itself;
7460 once that is successful we may check its range wrt the
7461 derived GIV. */
7463 {
7467 /* We know from the above that both endpoints are nonnegative,
7468 and that there is no wrapping. Verify that both endpoints
7469 are within the (signed) range of the outer mode. */
7472 }
7477 }
7480 {
7482 {
7486 }
7487 }
7488 else
7489 {
7491 {
7496 else
7497 {
7502 else
7504 }
7509 }
7512 }
7513 }
7514 }
7516 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7518 rtx
7521 rtx value;
7522 {
7528 /* Recall that check_ext_dependent_givs verified that the known bounds
7529 of a biv did not overflow or wrap with respect to the extension for
7530 the giv. Therefore, constants need no additional adjustment. */
7534 /* Otherwise, we must adjust the value to compensate for the
7535 differing modes of the biv and the giv. */
7537 }
7538 \f
7539 struct combine_givs_stats
7540 {
7543 };
7545 static int
7549 {
7556 /* Stabilize the sort. */
7560 }
7562 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7563 any other. If so, point SAME to the giv combined with and set NEW_REG to
7564 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7565 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7567 static void
7571 {
7572 /* Additional benefit to add for being combined multiple times. */
7580 /* Count givs, because bl->giv_count is incorrect here. */
7584 giv_count++;
7586 giv_array
7597 {
7599 rtx single_use;
7604 /* If a DEST_REG GIV is used only once, do not allow it to combine
7605 with anything, for in doing so we will gain nothing that cannot
7606 be had by simply letting the GIV with which we would have combined
7607 to be reduced on its own. The losage shows up in particular with
7608 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7609 be seen elsewhere as well. */
7616 /* Add an additional weight for zero addends. */
7621 {
7622 rtx this_combine;
7627 {
7630 }
7631 }
7633 }
7635 /* Iterate, combining until we can't. */
7636 restart:
7640 {
7643 {
7649 }
7651 }
7654 {
7660 /* If it has already been combined, skip. */
7665 {
7668 /* If it has already been combined, skip. */
7670 {
7675 /* For destination, we now may replace by mem expression instead
7676 of register. This changes the costs considerably, so add the
7677 compensation. */
7687 /* ??? The new final_[bg]iv_value code does a much better job
7688 of finding replaceable giv's, and hence this code may no
7689 longer be necessary. */
7693 /* To help optimize the next set of combinations, remove
7694 this giv from the benefits of other potential mates. */
7696 {
7700 }
7707 }
7708 }
7710 /* To help optimize the next set of combinations, remove
7711 this giv from the benefits of other potential mates. */
7713 {
7715 {
7719 }
7723 /* We've finished with this giv, and everything it touched.
7724 Restart the combination so that proper weights for the
7725 rest of the givs are properly taken into account. */
7726 /* ??? Ideally we would compact the arrays at this point, so
7727 as to not cover old ground. But sanely compacting
7728 can_combine is tricky. */
7730 }
7731 }
7733 /* Clean up. */
7736 }
7737 \f
7738 /* Generate sequence for REG = B * M + A. */
7740 static rtx
7746 {
7747 rtx seq;
7748 rtx result;
7751 /* Use unsigned arithmetic. */
7759 }
7762 /* Update registers created in insn sequence SEQ. */
7764 static void
7767 rtx seq;
7768 {
7769 rtx insn;
7771 /* Update register info for alias analysis. */
7777 {
7780 {
7787 }
7788 }
7792 }
7795 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. */
7797 void
7804 basic_block before_bb;
7805 rtx before_insn;
7806 {
7807 rtx seq;
7810 {
7813 }
7815 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7818 /* Increase the lifetime of any invariants moved further in code. */
7825 /* It is possible that the expansion created lots of new registers.
7826 Iterate over the sequence we just created and record them all. */
7828 }
7831 /* Emit insns in loop pre-header to set REG = B * M + A. */
7833 void
7840 {
7841 rtx seq;
7843 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7846 /* Increase the lifetime of any invariants moved further in code.
7847 ???? Is this really necessary? */
7854 /* It is possible that the expansion created lots of new registers.
7855 Iterate over the sequence we just created and record them all. */
7857 }
7860 /* Emit insns after loop to set REG = B * M + A. */
7862 void
7869 {
7870 rtx seq;
7872 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7877 /* It is possible that the expansion created lots of new registers.
7878 Iterate over the sequence we just created and record them all. */
7880 }
7884 /* Similar to gen_add_mult, but compute cost rather than generating
7885 sequence. */
7887 static int
7893 {
7903 {
7908 }
7911 }
7912 \f
7913 /* Test whether A * B can be computed without
7914 an actual multiply insn. Value is 1 if so.
7916 ??? This function stinks because it generates a ton of wasted RTL
7917 ??? and as a result fragments GC memory to no end. There are other
7918 ??? places in the compiler which are invoked a lot and do the same
7919 ??? thing, generate wasted RTL just to see if something is possible. */
7921 static int
7923 rtx a;
7924 rtx b;
7925 {
7926 rtx tmp;
7929 /* If only one is constant, make it B. */
7933 /* If first constant, both constant, so don't need multiply. */
7937 /* If second not constant, neither is constant, so would need multiply. */
7941 /* One operand is constant, so might not need multiply insn. Generate the
7942 code for the multiply and see if a call or multiply, or long sequence
7943 of insns is generated. */
7952 {
7955 {
7965 {
7968 }
7971 }
7972 }
7982 }
7983 \f
7984 /* Check to see if loop can be terminated by a "decrement and branch until
7985 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7986 Also try reversing an increment loop to a decrement loop
7987 to see if the optimization can be performed.
7988 Value is nonzero if optimization was performed. */
7990 /* This is useful even if the architecture doesn't have such an insn,
7991 because it might change a loops which increments from 0 to n to a loop
7992 which decrements from n to 0. A loop that decrements to zero is usually
7993 faster than one that increments from zero. */
7995 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7996 such as approx_final_value, biv_total_increment, loop_iterations, and
7997 final_[bg]iv_value. */
7999 static int
8003 {
8008 rtx reg;
8009 rtx jump_label;
8010 rtx final_value;
8011 rtx start_value;
8012 rtx new_add_val;
8013 rtx comparison;
8014 rtx before_comparison;
8015 rtx p;
8016 rtx jump;
8017 rtx first_compare;
8022 /* If last insn is a conditional branch, and the insn before tests a
8023 register value, try to optimize it. Otherwise, we can't do anything. */
8032 /* Try to compute whether the compare/branch at the loop end is one or
8033 two instructions. */
8039 else
8042 {
8043 /* If more than one condition is present to control the loop, then
8044 do not proceed, as this function does not know how to rewrite
8045 loop tests with more than one condition.
8047 Look backwards from the first insn in the last comparison
8048 sequence and see if we've got another comparison sequence. */
8050 rtx jump1;
8054 }
8056 /* Check all of the bivs to see if the compare uses one of them.
8057 Skip biv's set more than once because we can't guarantee that
8058 it will be zero on the last iteration. Also skip if the biv is
8059 used between its update and the test insn. */
8062 {
8067 first_compare))
8069 }
8074 /* Look for the case where the basic induction variable is always
8075 nonnegative, and equals zero on the last iteration.
8076 In this case, add a reg_note REG_NONNEG, which allows the
8077 m68k DBRA instruction to be used. */
8085 {
8086 /* Initial value must be greater than 0,
8087 init_val % -dec_value == 0 to ensure that it equals zero on
8088 the last iteration */
8094 {
8095 /* register always nonnegative, add REG_NOTE to branch */
8103 }
8105 /* If the decrement is 1 and the value was tested as >= 0 before
8106 the loop, then we can safely optimize. */
8108 {
8121 {
8129 }
8130 }
8131 }
8134 {
8135 /* Try to change inc to dec, so can apply above optimization. */
8136 /* Can do this if:
8137 all registers modified are induction variables or invariant,
8138 all memory references have non-overlapping addresses
8139 (obviously true if only one write)
8140 allow 2 insns for the compare/jump at the end of the loop. */
8141 /* Also, we must avoid any instructions which use both the reversed
8142 biv and another biv. Such instructions will fail if the loop is
8143 reversed. We meet this condition by requiring that either
8144 no_use_except_counting is true, or else that there is only
8145 one biv. */
8147 /* 1 if the iteration var is used only to count iterations. */
8149 /* 1 if the loop has no memory store, or it has a single memory store
8150 which is reversible. */
8156 {
8160 /* If there are no givs for this biv, and the only exit is the
8161 fall through at the end of the loop, then
8162 see if perhaps there are no uses except to count. */
8166 {
8171 /* An insn that sets the biv is okay. */
8172 ;
8176 {
8177 /* If either of these insns uses the biv and sets a pseudo
8178 that has more than one usage, then the biv has uses
8179 other than counting since it's used to derive a value
8180 that is used more than one time. */
8182 regs);
8184 {
8187 }
8188 }
8190 {
8193 }
8194 }
8196 /* A biv has uses besides counting if it is used to set
8197 another biv. */
8201 {
8204 }
8205 }
8208 /* No need to worry about MEMs. */
8209 ;
8211 {
8216 /* If the loop has a single store, and the destination address is
8217 invariant, then we can't reverse the loop, because this address
8218 might then have the wrong value at loop exit.
8219 This would work if the source was invariant also, however, in that
8220 case, the insn should have been moved out of the loop. */
8223 {
8226 /* If we could prove that each of the memory locations
8227 written to was different, then we could reverse the
8228 store -- but we don't presently have any way of
8229 knowing that. */
8232 /* If the store depends on a register that is set after the
8233 store, it depends on the initial value, and is thus not
8234 reversible. */
8236 {
8243 }
8244 }
8245 }
8246 else
8249 /* This code only acts for innermost loops. Also it simplifies
8250 the memory address check by only reversing loops with
8251 zero or one memory access.
8252 Two memory accesses could involve parts of the same array,
8253 and that can't be reversed.
8254 If the biv is used only for counting, than we don't need to worry
8255 about all these things. */
8261 && reversible_mem_store
8266 {
8267 rtx tem;
8269 /* Loop can be reversed. */
8273 /* Now check other conditions:
8275 The increment must be a constant, as must the initial value,
8276 and the comparison code must be LT.
8278 This test can probably be improved since +/- 1 in the constant
8279 can be obtained by changing LT to LE and vice versa; this is
8280 confusing. */
8283 /* for constants, LE gets turned into LT */
8287 {
8298 comparison_const_width
8300 else
8301 comparison_const_width
8305 comparison_sign_mask
8308 /* If the comparison value is not a loop invariant, then we
8309 can not reverse this loop.
8311 ??? If the insns which initialize the comparison value as
8312 a whole compute an invariant result, then we could move
8313 them out of the loop and proceed with loop reversal. */
8321 /* Normalize the initial value if it is an integer and
8322 has no other use except as a counter. This will allow
8323 a few more loops to be reversed. */
8327 {
8329 /* The code below requires comparison_val to be a multiple
8330 of add_val in order to do the loop reversal, so
8331 round up comparison_val to a multiple of add_val.
8332 Since comparison_value is constant, we know that the
8333 current comparison code is LT. */
8335 comparison_val
8337 /* We postpone overflow checks for COMPARISON_VAL here;
8338 even if there is an overflow, we might still be able to
8339 reverse the loop, if converting the loop exit test to
8340 NE is possible. */
8342 }
8344 /* First check if we can do a vanilla loop reversal. */
8346 /* If we have a decrement_and_branch_on_count,
8347 prefer the NE test, since this will allow that
8348 instruction to be generated. Note that we must
8349 use a vanilla loop reversal if the biv is used to
8350 calculate a giv or has a non-counting use. */
8351 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8352 && defined (HAVE_decrement_and_branch_on_count)
8356 #endif
8358 /* Now do postponed overflow checks on COMPARISON_VAL. */
8361 {
8362 /* Register will always be nonnegative, with value
8363 0 on last iteration */
8367 }
8371 {
8374 }
8375 else
8381 /* If the initial value is not zero, or if the comparison
8382 value is not an exact multiple of the increment, then we
8383 can not reverse this loop. */
8386 {
8389 }
8390 else
8391 {
8394 }
8398 /* Reset these in case we normalized the initial value
8399 and comparison value above. */
8402 {
8404 final_value
8406 }
8409 /* Save some info needed to produce the new insns. */
8414 /* Set start_value; if this is not a CONST_INT, we need
8415 to generate a SUB.
8416 Initialize biv to start_value before loop start.
8417 The old initializing insn will be deleted as a
8418 dead store by flow.c. */
8421 {
8424 }
8426 {
8434 start_value
8440 }
8442 {
8445 initial_value);
8449 start_value
8452 }
8453 else
8454 /* We could handle the other cases too, but it'll be
8455 better to have a testcase first. */
8458 /* We may not have a single insn which can increment a reg, so
8459 create a sequence to hold all the insns from expand_inc. */
8468 /* Update biv info to reflect its new status. */
8473 /* Update loop info. */
8482 /* Inc LABEL_NUSES so that delete_insn will
8483 not delete the label. */
8486 /* Emit an insn after the end of the loop to set the biv's
8487 proper exit value if it is used anywhere outside the loop. */
8493 /* Delete compare/branch at end of loop. */
8498 /* Add new compare/branch insn at end of loop. */
8510 ;
8516 {
8518 {
8519 /* Increment of LABEL_NUSES done above. */
8520 /* Register is now always nonnegative,
8521 so add REG_NONNEG note to the branch. */
8524 }
8526 }
8528 /* No insn may reference both the reversed and another biv or it
8529 will fail (see comment near the top of the loop reversal
8530 code).
8531 Earlier on, we have verified that the biv has no use except
8532 counting, or it is the only biv in this function.
8533 However, the code that computes no_use_except_counting does
8534 not verify reg notes. It's possible to have an insn that
8535 references another biv, and has a REG_EQUAL note with an
8536 expression based on the reversed biv. To avoid this case,
8537 remove all REG_EQUAL notes based on the reversed biv
8538 here. */
8541 {
8544 /* If this is a set of a GIV based on the reversed biv, any
8545 REG_EQUAL notes should still be correct. */
8552 {
8557 else
8559 }
8560 }
8562 /* Mark that this biv has been reversed. Each giv which depends
8563 on this biv, and which is also live past the end of the loop
8564 will have to be fixed up. */
8569 {
8573 else
8575 }
8578 }
8579 }
8580 }
8583 }
8584 \f
8585 /* Verify whether the biv BL appears to be eliminable,
8586 based on the insns in the loop that refer to it.
8588 If ELIMINATE_P is nonzero, actually do the elimination.
8590 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8591 determine whether invariant insns should be placed inside or at the
8592 start of the loop. */
8594 static int
8600 {
8603 rtx p;
8605 /* Scan all insns in the loop, stopping if we find one that uses the
8606 biv in a way that we cannot eliminate. */
8609 {
8613 rtx note;
8615 /* If this is a libcall that sets a giv, skip ahead to its end. */
8617 {
8621 {
8626 {
8633 }
8634 }
8635 }
8637 /* Closely examine the insn if the biv is mentioned. */
8642 {
8648 }
8650 /* If we are eliminating, kill REG_EQUAL notes mentioning the biv. */
8655 }
8658 {
8663 }
8666 }
8667 \f
8668 /* INSN and REFERENCE are instructions in the same insn chain.
8669 Return nonzero if INSN is first. */
8671 int
8674 {
8678 {
8679 /* Start with test for not first so that INSN == REFERENCE yields not
8680 first. */
8686 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8687 previous insn, hence the <= comparison below does not work if
8688 P is a note. */
8699 }
8700 }
8702 /* We are trying to eliminate BIV in INSN using GIV. Return nonzero if
8703 the offset that we have to take into account due to auto-increment /
8704 div derivation is zero. */
8705 static int
8708 rtx insn;
8709 {
8710 /* If the giv V had the auto-inc address optimization applied
8711 to it, and INSN occurs between the giv insn and the biv
8712 insn, then we'd have to adjust the value used here.
8713 This is rare, so we don't bother to make this possible. */
8722 }
8724 /* If BL appears in X (part of the pattern of INSN), see if we can
8725 eliminate its use. If so, return 1. If not, return 0.
8727 If BIV does not appear in X, return 1.
8729 If ELIMINATE_P is nonzero, actually do the elimination.
8730 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8731 Depending on how many items have been moved out of the loop, it
8732 will either be before INSN (when WHERE_INSN is nonzero) or at the
8733 start of the loop (when WHERE_INSN is zero). */
8735 static int
8741 basic_block where_bb;
8742 rtx where_insn;
8743 {
8749 #ifdef HAVE_cc0
8751 #endif
8757 {
8759 /* If we haven't already been able to do something with this BIV,
8760 we can't eliminate it. */
8766 /* If this sets the BIV, it is not a problem. */
8770 /* If this is an insn that defines a giv, it is also ok because
8771 it will go away when the giv is reduced. */
8776 #ifdef HAVE_cc0
8778 {
8779 /* Can replace with any giv that was reduced and
8780 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8781 Require a constant for MULT_VAL, so we know it's nonzero.
8782 ??? We disable this optimization to avoid potential
8783 overflows. */
8791 {
8798 /* If the giv has the opposite direction of change,
8799 then reverse the comparison. */
8803 else
8806 /* We can probably test that giv's reduced reg. */
8809 }
8811 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8812 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8813 Require a constant for MULT_VAL, so we know it's nonzero.
8814 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8815 overflow problem. */
8827 {
8834 /* If the giv has the opposite direction of change,
8835 then reverse the comparison. */
8839 else
8843 /* Replace biv with the giv's reduced register. */
8848 /* Insn doesn't support that constant or invariant. Copy it
8849 into a register (it will be a loop invariant.) */
8856 /* Substitute the new register for its invariant value in
8857 the compare expression. */
8861 }
8862 }
8863 #endif
8870 /* See if either argument is the biv. */
8875 else
8879 {
8880 /* First try to replace with any giv that has constant positive
8881 mult_val and constant add_val. We might be able to support
8882 negative mult_val, but it seems complex to do it in general. */
8894 {
8898 /* Don't eliminate if the linear combination that makes up
8899 the giv overflows when it is applied to ARG. */
8901 {
8902 rtx add_val;
8906 else
8912 }
8917 /* Replace biv with the giv's reduced reg. */
8920 /* If all constants are actually constant integers and
8921 the derived constant can be directly placed in the COMPARE,
8922 do so. */
8925 {
8928 }
8929 else
8930 {
8931 /* Otherwise, load it into a register. */
8936 }
8942 }
8944 /* Look for giv with positive constant mult_val and nonconst add_val.
8945 Insert insns to calculate new compare value.
8946 ??? Turn this off due to possible overflow. */
8954 {
8955 rtx tem;
8965 /* Replace biv with giv's reduced register. */
8969 /* Compute value to compare against. */
8973 /* Use it in this insn. */
8977 }
8978 }
8980 {
8982 {
8983 /* Look for giv with constant positive mult_val and nonconst
8984 add_val. Insert insns to compute new compare value.
8985 ??? Turn this off due to possible overflow. */
8992 {
8993 rtx tem;
9003 /* Replace biv with giv's reduced register. */
9007 /* Compute value to compare against. */
9014 }
9015 }
9017 /* This code has problems. Basically, you can't know when
9018 seeing if we will eliminate BL, whether a particular giv
9019 of ARG will be reduced. If it isn't going to be reduced,
9020 we can't eliminate BL. We can try forcing it to be reduced,
9021 but that can generate poor code.
9023 The problem is that the benefit of reducing TV, below should
9024 be increased if BL can actually be eliminated, but this means
9025 we might have to do a topological sort of the order in which
9026 we try to process biv. It doesn't seem worthwhile to do
9027 this sort of thing now. */
9029 #if 0
9030 /* Otherwise the reg compared with had better be a biv. */
9035 /* Look for a pair of givs, one for each biv,
9036 with identical coefficients. */
9038 {
9050 {
9057 /* Replace biv with its giv's reduced reg. */
9059 /* Replace other operand with the other giv's
9060 reduced reg. */
9063 }
9064 }
9065 #endif
9066 }
9068 /* If we get here, the biv can't be eliminated. */
9072 /* If this address is a DEST_ADDR giv, it doesn't matter if the
9073 biv is used in it, since it will be replaced. */
9081 }
9083 /* See if any subexpression fails elimination. */
9086 {
9088 {
9101 }
9102 }
9105 }
9106 \f
9107 /* Return nonzero if the last use of REG
9108 is in an insn following INSN in the same basic block. */
9110 static int
9112 rtx reg;
9113 rtx insn;
9114 {
9115 rtx n;
9119 {
9122 }
9124 }
9125 \f
9126 /* Called via `note_stores' to record the initial value of a biv. Here we
9127 just record the location of the set and process it later. */
9129 static void
9131 rtx dest;
9132 rtx set;
9134 {
9145 /* If this is the first set found, record it. */
9147 {
9150 }
9151 }
9152 \f
9153 /* If any of the registers in X are "old" and currently have a last use earlier
9154 than INSN, update them to have a last use of INSN. Their actual last use
9155 will be the previous insn but it will not have a valid uid_luid so we can't
9156 use it. X must be a source expression only. */
9158 static void
9160 rtx x;
9161 rtx insn;
9162 {
9163 /* Check for the case where INSN does not have a valid luid. In this case,
9164 there is no need to modify the regno_last_uid, as this can only happen
9165 when code is inserted after the loop_end to set a pseudo's final value,
9166 and hence this insn will never be the last use of x.
9167 ???? This comment is not correct. See for example loop_givs_reduce.
9168 This may insert an insn before another new insn. */
9172 {
9174 }
9175 else
9176 {
9180 {
9186 }
9187 }
9188 }
9189 \f
9190 /* Given an insn INSN and condition COND, return the condition in a
9191 canonical form to simplify testing by callers. Specifically:
9193 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9194 (2) Both operands will be machine operands; (cc0) will have been replaced.
9195 (3) If an operand is a constant, it will be the second operand.
9196 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9197 for GE, GEU, and LEU.
9199 If the condition cannot be understood, or is an inequality floating-point
9200 comparison which needs to be reversed, 0 will be returned.
9202 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
9204 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9205 insn used in locating the condition was found. If a replacement test
9206 of the condition is desired, it should be placed in front of that
9207 insn and we will be sure that the inputs are still valid.
9209 If WANT_REG is nonzero, we wish the condition to be relative to that
9210 register, if possible. Therefore, do not canonicalize the condition
9211 further. */
9213 rtx
9215 rtx insn;
9216 rtx cond;
9219 rtx want_reg;
9220 {
9223 rtx set;
9224 rtx tem;
9242 /* If we are comparing a register with zero, see if the register is set
9243 in the previous insn to a COMPARE or a comparison operation. Perform
9244 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9245 in cse.c */
9250 {
9251 /* Set nonzero when we find something of interest. */
9254 #ifdef HAVE_cc0
9255 /* If comparison with cc0, import actual comparison from compare
9256 insn. */
9258 {
9269 }
9270 #endif
9272 /* If this is a COMPARE, pick up the two things being compared. */
9274 {
9278 }
9282 /* Go back to the previous insn. Stop if it is not an INSN. We also
9283 stop if it isn't a single set or if it has a REG_INC note because
9284 we don't want to bother dealing with it. */
9298 /* If this is setting OP0, get what it sets it to if it looks
9299 relevant. */
9301 {
9303 #ifdef FLOAT_STORE_FLAG_VALUE
9304 REAL_VALUE_TYPE fsfv;
9305 #endif
9307 /* ??? We may not combine comparisons done in a CCmode with
9308 comparisons not done in a CCmode. This is to aid targets
9309 like Alpha that have an IEEE compliant EQ instruction, and
9310 a non-IEEE compliant BEQ instruction. The use of CCmode is
9311 actually artificial, simply to prevent the combination, but
9312 should not affect other platforms.
9314 However, we must allow VOIDmode comparisons to match either
9315 CCmode or non-CCmode comparison, because some ports have
9316 modeless comparisons inside branch patterns.
9318 ??? This mode check should perhaps look more like the mode check
9319 in simplify_comparison in combine. */
9327 && (STORE_FLAG_VALUE
9330 #ifdef FLOAT_STORE_FLAG_VALUE
9335 #endif
9336 ))
9347 && (STORE_FLAG_VALUE
9350 #ifdef FLOAT_STORE_FLAG_VALUE
9355 #endif
9356 ))
9362 {
9365 }
9366 else
9368 }
9371 /* If this sets OP0, but not directly, we have to give up. */
9375 {
9379 {
9384 }
9389 }
9390 }
9392 /* If constant is first, put it last. */
9396 /* If OP0 is the result of a comparison, we weren't able to find what
9397 was really being compared, so fail. */
9401 /* Canonicalize any ordered comparison with integers involving equality
9402 if we can do computations in the relevant mode and we do not
9403 overflow. */
9408 {
9411 unsigned HOST_WIDE_INT max_val
9415 {
9421 /* When cross-compiling, const_val might be sign-extended from
9422 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9442 }
9443 }
9445 #ifdef HAVE_cc0
9446 /* Never return CC0; return zero instead. */
9449 #endif
9452 }
9454 /* Given a jump insn JUMP, return the condition that will cause it to branch
9455 to its JUMP_LABEL. If the condition cannot be understood, or is an
9456 inequality floating-point comparison which needs to be reversed, 0 will
9457 be returned.
9459 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9460 insn used in locating the condition was found. If a replacement test
9461 of the condition is desired, it should be placed in front of that
9462 insn and we will be sure that the inputs are still valid. */
9464 rtx
9466 rtx jump;
9468 {
9469 rtx cond;
9471 rtx set;
9473 /* If this is not a standard conditional jump, we can't parse it. */
9481 /* If this branches to JUMP_LABEL when the condition is false, reverse
9482 the condition. */
9483 reverse
9488 }
9490 /* Similar to above routine, except that we also put an invariant last
9491 unless both operands are invariants. */
9493 rtx
9496 rtx x;
9497 {
9507 }
9509 /* Scan the function and determine whether it has indirect (computed) jumps.
9511 This is taken mostly from flow.c; similar code exists elsewhere
9512 in the compiler. It may be useful to put this into rtlanal.c. */
9513 static int
9515 rtx start;
9516 {
9517 rtx insn;
9524 }
9526 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9527 documentation for LOOP_MEMS for the definition of `appropriate'.
9528 This function is called from prescan_loop via for_each_rtx. */
9530 static int
9534 {
9543 {
9548 /* We're not interested in MEMs that are only clobbered. */
9552 /* We're not interested in the MEM associated with a
9553 CONST_DOUBLE, so there's no need to traverse into this. */
9557 /* We're not interested in any MEMs that only appear in notes. */
9561 /* This is not a MEM. */
9563 }
9565 /* See if we've already seen this MEM. */
9568 {
9570 /* The modes of the two memory accesses are different. If
9571 this happens, something tricky is going on, and we just
9572 don't optimize accesses to this MEM. */
9576 }
9578 /* Resize the array, if necessary. */
9580 {
9583 else
9589 }
9591 /* Actually insert the MEM. */
9593 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9594 because we can't put it in a register. We still store it in the
9595 table, though, so that if we see the same address later, but in a
9596 non-BLK mode, we'll not think we can optimize it at that point. */
9602 }
9605 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9607 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9608 register that is modified by an insn between FROM and TO. If the
9609 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9610 more, stop incrementing it, to avoid overflow.
9612 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9613 register I is used, if it is only used once. Otherwise, it is set
9614 to 0 (for no uses) or const0_rtx for more than one use. This
9615 parameter may be zero, in which case this processing is not done.
9617 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9618 optimize register I. */
9620 static void
9624 {
9627 /* last_set[n] is nonzero iff reg n has been set in the current
9628 basic block. In that case, it is the insn that last set reg n. */
9630 rtx insn;
9636 /* Grow the regs array if not allocated or too small. */
9638 {
9644 /* Zero the new elements. */
9647 }
9649 /* Clear previously scanned fields but do not clear n_times_set. */
9651 {
9655 }
9659 /* Scan the loop, recording register usage. */
9662 {
9664 {
9665 /* Record registers that have exactly one use. */
9668 /* Include uses in REG_EQUAL notes. */
9676 {
9680 last_set);
9681 }
9682 }
9687 /* Invalidate all registers used for function argument passing.
9688 We check rtx_varies_p for the same reason as below, to allow
9689 optimizing PIC calculations. */
9691 {
9692 rtx link;
9694 link;
9696 {
9703 }
9704 }
9705 }
9707 /* Invalidate all hard registers clobbered by calls. With one exception:
9708 a call-clobbered PIC register is still function-invariant for our
9709 purposes, since we can hoist any PIC calculations out of the loop.
9710 Thus the call to rtx_varies_p. */
9715 {
9718 }
9720 #ifdef AVOID_CCMODE_COPIES
9721 /* Don't try to move insns which set CC registers if we should not
9722 create CCmode register copies. */
9726 #endif
9728 /* Set regs->array[I].n_times_set for the new registers. */
9733 }
9735 /* Returns the number of real INSNs in the LOOP. */
9737 static int
9740 {
9742 rtx insn;
9750 }
9752 /* Move MEMs into registers for the duration of the loop. */
9754 static void
9757 {
9764 rtx end_label;
9765 /* Nonzero if the next instruction may never be executed. */
9772 /* We cannot use next_label here because it skips over normal insns. */
9777 /* Check to see if it's possible that some instructions in the loop are
9778 never executed. Also check if there is a goto out of the loop other
9779 than right after the end of the loop. */
9783 {
9787 /* If we enter the loop in the middle, and scan
9788 around to the beginning, don't set maybe_never
9789 for that. This must be an unconditional jump,
9790 otherwise the code at the top of the loop might
9791 never be executed. Unconditional jumps are
9792 followed a by barrier then loop end. */
9797 {
9798 /* If this is a jump outside of the loop but not right
9799 after the end of the loop, we would have to emit new fixup
9800 sequences for each such label. */
9802 JUMP_INSN is executed, we must be conservative. */
9811 /* Something complicated. */
9813 else
9814 /* If there are any more instructions in the loop, they
9815 might not be reached. */
9817 }
9820 }
9822 /* Find start of the extended basic block that enters the loop. */
9826 ;
9831 /* Build table of mems that get set to constant values before the
9832 loop. */
9836 /* Actually move the MEMs. */
9838 {
9839 regset_head load_copies;
9840 regset_head store_copies;
9842 rtx reg;
9844 rtx mem_list_entry;
9848 /* There's no telling whether or not MEM is modified. */
9851 /* Go through the MEMs written to in the loop to see if this
9852 one is aliased by one of them. */
9855 {
9860 {
9861 /* MEM is indeed aliased by this store. */
9864 }
9866 }
9872 /* If this MEM is written to, we must be sure that there
9873 are no reads from another MEM that aliases this one. */
9875 {
9879 {
9883 VOIDmode,
9885 rtx_varies_p))
9886 {
9887 /* It's not safe to hoist loop_info->mems[i] out of
9888 the loop because writes to it might not be
9889 seen by reads from loop_info->mems[j]. */
9892 }
9893 }
9894 }
9897 /* We can't access the MEM outside the loop; it might
9898 cause a trap that wouldn't have happened otherwise. */
9902 /* We thought we were going to lift this MEM out of the
9903 loop, but later discovered that we could not. */
9909 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9910 order to keep scan_loop from moving stores to this MEM
9911 out of the loop just because this REG is neither a
9912 user-variable nor used in the loop test. */
9917 /* Now, replace all references to the MEM with the
9918 corresponding pseudos. */
9923 {
9925 {
9926 rtx set;
9930 /* See if this copies the mem into a register that isn't
9931 modified afterwards. We'll try to do copy propagation
9932 a little further on. */
9934 /* @@@ This test is _way_ too conservative. */
9935 && ! maybe_never
9943 /* See if this copies the mem from a register that isn't
9944 modified afterwards. We'll try to remove the
9945 redundant copy later on by doing a little register
9946 renaming and copy propagation. This will help
9947 to untangle things for the BIV detection code. */
9949 && ! maybe_never
9957 /* If this is a call which uses / clobbers this memory
9958 location, we must not change the interface here. */
9962 {
9966 }
9967 else
9968 /* Replace the memory reference with the shadow register. */
9971 }
9976 }
9981 /* We couldn't replace all occurrences of the MEM. */
9983 else
9984 {
9985 /* Load the memory immediately before LOOP->START, which is
9986 the NOTE_LOOP_BEG. */
9988 rtx set;
9994 {
9998 {
10002 /* Extending hard register lifetimes causes crash
10003 on SRC targets. Doing so on non-SRC is
10004 probably also not good idea, since we most
10005 probably have pseudoregister equivalence as
10006 well. */
10009 }
10010 /* Use the constant equivalence if that is cheap enough. */
10016 {
10019 }
10021 /* If best_equiv is nonzero, we know that MEM is set to a
10022 constant or register before the loop. We will use this
10023 knowledge to initialize the shadow register with that
10024 constant or reg rather than by loading from MEM. */
10027 }
10032 {
10035 {
10038 }
10039 }
10045 {
10047 {
10050 }
10052 /* Store the memory immediately after END, which is
10053 the NOTE_LOOP_END. */
10056 }
10059 {
10064 }
10066 /* Attempt a bit of copy propagation. This helps untangle the
10067 data flow, and enables {basic,general}_induction_var to find
10068 more bivs/givs. */
10069 EXECUTE_IF_SET_IN_REG_SET
10071 {
10073 });
10076 EXECUTE_IF_SET_IN_REG_SET
10078 {
10080 });
10082 }
10083 }
10086 {
10087 /* Now, we need to replace all references to the previous exit
10088 label with the new one. */
10089 rtx_pair rr;
10094 {
10097 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
10098 field. This is not handled by for_each_rtx because it doesn't
10099 handle unprinted ('0') fields. We need to update JUMP_LABEL
10100 because the immediately following unroll pass will use it.
10101 replace_label would not work anyways, because that only handles
10102 LABEL_REFs. */
10105 }
10106 }
10109 }
10111 /* For communication between note_reg_stored and its caller. */
10112 struct note_reg_stored_arg
10113 {
10115 rtx reg;
10116 };
10118 /* Called via note_stores, record in SET_SEEN whether X, which is written,
10119 is equal to ARG. */
10120 static void
10124 {
10128 }
10130 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
10131 There must be exactly one insn that sets this pseudo; it will be
10132 deleted if all replacements succeed and we can prove that the register
10133 is not used after the loop. */
10135 static void
10138 rtx replacement;
10140 {
10141 /* This is the reg that we are copying from. */
10144 rtx insn;
10145 /* These help keep track of whether we replaced all uses of the reg. */
10152 {
10153 rtx set;
10155 /* Only substitute within one extended basic block from the initializing
10156 insn. */
10163 /* Is this the initializing insn? */
10168 {
10175 }
10177 /* Only substitute after seeing the initializing insn. */
10179 {
10186 /* Stop replacing when REPLACEMENT is modified. */
10191 {
10194 /* It is possible that we've turned previously valid REG_EQUAL to
10195 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10196 REPLACEMENT is modified, we get different meaning. */
10200 }
10201 }
10202 }
10206 {
10210 {
10211 rtx first;
10212 rtx retval_note;
10214 /* Assume we're just deleting INIT_INSN. */
10216 /* Look for REG_RETVAL note. If we're deleting the end of
10217 the libcall sequence, the whole sequence can go. */
10219 /* If we found a REG_RETVAL note, find the first instruction
10220 in the sequence. */
10224 /* Delete the instructions. */
10226 }
10229 }
10230 }
10232 /* Replace all the instructions from FIRST up to and including LAST
10233 with NOTE_INSN_DELETED notes. */
10235 static void
10237 rtx first;
10238 rtx last;
10239 {
10241 {
10247 /* If this was the LAST instructions we're supposed to delete,
10248 we're done. */
10253 }
10254 }
10256 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10257 loop LOOP if the order of the sets of these registers can be
10258 swapped. There must be exactly one insn within the loop that sets
10259 this pseudo followed immediately by a move insn that sets
10260 REPLACEMENT with REGNO. */
10261 static void
10264 rtx replacement;
10266 {
10267 rtx insn;
10276 {
10277 /* Search for the insn that copies REGNO to NEW_REGNO? */
10285 }
10288 {
10289 rtx prev_insn;
10290 rtx prev_set;
10292 /* Some DEF-USE info would come in handy here to make this
10293 function more general. For now, just check the previous insn
10294 which is the most likely candidate for setting REGNO. */
10302 {
10303 /* We have:
10304 (set (reg regno) (expr))
10305 (set (reg new_regno) (reg regno))
10307 so try converting this to:
10308 (set (reg new_regno) (expr))
10309 (set (reg regno) (reg new_regno))
10311 The former construct is often generated when a global
10312 variable used for an induction variable is shadowed by a
10313 register (NEW_REGNO). The latter construct improves the
10314 chances of GIV replacement and BIV elimination. */
10324 {
10331 /* Update first use of REGNO. */
10335 /* Now perform copy propagation to hopefully
10336 remove all uses of REGNO within the loop. */
10338 }
10339 }
10340 }
10341 }
10343 /* Replace MEM with its associated pseudo register. This function is
10344 called from load_mems via for_each_rtx. DATA is actually a pointer
10345 to a structure describing the instruction currently being scanned
10346 and the MEM we are currently replacing. */
10348 static int
10352 {
10360 {
10365 /* We're not interested in the MEM associated with a
10366 CONST_DOUBLE, so there's no need to traverse into one. */
10370 /* This is not a MEM. */
10372 }
10375 /* This is not the MEM we are currently replacing. */
10378 /* Actually replace the MEM. */
10382 }
10384 static void
10386 rtx insn;
10387 rtx mem;
10388 rtx reg;
10389 {
10390 loop_replace_args args;
10397 }
10399 /* Replace one register with another. Called through for_each_rtx; PX points
10400 to the rtx being scanned. DATA is actually a pointer to
10401 a structure of arguments. */
10403 static int
10407 {
10418 }
10420 static void
10422 rtx insn;
10423 rtx reg;
10424 rtx replacement;
10425 {
10426 loop_replace_args args;
10433 }
10435 /* Replace occurrences of the old exit label for the loop with the new
10436 one. DATA is an rtx_pair containing the old and new labels,
10437 respectively. */
10439 static int
10443 {
10462 }
10463 \f
10464 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10465 (ignored in the interim). */
10467 static rtx
10470 basic_block where_bb ATTRIBUTE_UNUSED;
10471 rtx where_insn;
10472 rtx pattern;
10473 {
10475 }
10478 /* If WHERE_INSN is nonzero emit insn for PATTERN before WHERE_INSN
10479 in basic block WHERE_BB (ignored in the interim) within the loop
10480 otherwise hoist PATTERN into the loop pre-header. */
10482 rtx
10485 basic_block where_bb ATTRIBUTE_UNUSED;
10486 rtx where_insn;
10487 rtx pattern;
10488 {
10492 }
10495 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10496 WHERE_BB (ignored in the interim) within the loop. */
10498 static rtx
10501 basic_block where_bb ATTRIBUTE_UNUSED;
10502 rtx where_insn;
10503 rtx pattern;
10504 {
10506 }
10509 /* Hoist insn for PATTERN into the loop pre-header. */
10511 rtx
10514 rtx pattern;
10515 {
10517 }
10520 /* Hoist call insn for PATTERN into the loop pre-header. */
10522 static rtx
10525 rtx pattern;
10526 {
10528 }
10531 /* Sink insn for PATTERN after the loop end. */
10533 rtx
10536 rtx pattern;
10537 {
10539 }
10541 /* bl->final_value can be eighter general_operand or PLUS of general_operand
10542 and constant. Emit sequence of instructions to load it into REG. */
10543 static rtx
10546 {
10547 rtx seq;
10555 }
10557 /* If the loop has multiple exits, emit insn for PATTERN before the
10558 loop to ensure that it will always be executed no matter how the
10559 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10560 since this is slightly more efficient. */
10562 static rtx
10565 rtx pattern;
10566 {
10569 else
10571 }
10572 \f
10573 static void
10578 {
10586 iv_num++;
10591 {
10594 }
10595 }
10598 static void
10603 {
10605 rtx incr;
10616 {
10619 }
10621 {
10624 }
10628 {
10632 }
10635 {
10639 }
10641 /* List the increments. */
10643 {
10647 }
10649 /* List the givs. */
10651 {
10656 else
10659 }
10660 }
10663 static void
10668 {
10679 {
10683 }
10686 }
10689 static void
10694 {
10701 else
10717 {
10719 {
10731 }
10732 }
10743 {
10747 }
10750 }
10753 void
10756 {
10758 }
10761 void
10764 {
10766 }
10769 void
10772 {
10774 }
10777 void
10780 {
10782 }
10785 #define LOOP_BLOCK_NUM_1(INSN) \
10786 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10788 /* The notes do not have an assigned block, so look at the next insn. */
10789 #define LOOP_BLOCK_NUM(INSN) \
10790 ((INSN) ? (GET_CODE (INSN) == NOTE \
10791 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10792 : LOOP_BLOCK_NUM_1 (INSN)) \
10793 : -1)
10795 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10797 static void
10802 {
10803 rtx label;
10808 /* Print diagnostics to compare our concept of a loop with
10809 what the loop notes say. */
10824 {
10844 {
10847 {
10850 }
10851 }
10854 /* This can happen when a marked loop appears as two nested loops,
10855 say from while (a || b) {}. The inner loop won't match
10856 the loop markers but the outer one will. */
10859 }
10860 }
10862 /* Call this function from the debugger to dump LOOP. */
10864 void
10867 {
10869 }
10871 /* Call this function from the debugger to dump LOOPS. */
10873 void
10876 {
10878 }