gcc/reload1.c

   1 /* Reload pseudo regs into hard regs for insns that require hard regs.
   2    Copyright (C) 1987-2015 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify it under
   7 the terms of the GNU General Public License as published by the Free
   8 Software Foundation; either version 3, or (at your option) any later
   9 version.
  10
  11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14 for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 #include "config.h"
  21 #include "system.h"
  22 #include "coretypes.h"
  23 #include "tm.h"
  24
  25 #include "machmode.h"
  26 #include "hard-reg-set.h"
  27 #include "rtl-error.h"
  28 #include "tm_p.h"
  29 #include "obstack.h"
  30 #include "insn-config.h"
  31 #include "ggc.h"
  32 #include "flags.h"
  33 #include "hashtab.h"
  34 #include "hash-set.h"
  35 #include "vec.h"
  36 #include "input.h"
  37 #include "function.h"
  38 #include "symtab.h"
  39 #include "rtl.h"
  40 #include "statistics.h"
  41 #include "double-int.h"
  42 #include "real.h"
  43 #include "fixed-value.h"
  44 #include "alias.h"
  45 #include "wide-int.h"
  46 #include "inchash.h"
  47 #include "tree.h"
  48 #include "expmed.h"
  49 #include "dojump.h"
  50 #include "explow.h"
  51 #include "calls.h"
  52 #include "emit-rtl.h"
  53 #include "varasm.h"
  54 #include "stmt.h"
  55 #include "expr.h"
  56 #include "insn-codes.h"
  57 #include "optabs.h"
  58 #include "regs.h"
  59 #include "addresses.h"
  60 #include "predict.h"
  61 #include "dominance.h"
  62 #include "cfg.h"
  63 #include "cfgrtl.h"
  64 #include "cfgbuild.h"
  65 #include "basic-block.h"
  66 #include "df.h"
  67 #include "reload.h"
  68 #include "recog.h"
  69 #include "except.h"
  70 #include "ira.h"
  71 #include "target.h"
  72 #include "dumpfile.h"
  73 #include "rtl-iter.h"
  74
  75 /* This file contains the reload pass of the compiler, which is
  76    run after register allocation has been done.  It checks that
  77    each insn is valid (operands required to be in registers really
  78    are in registers of the proper class) and fixes up invalid ones
  79    by copying values temporarily into registers for the insns
  80    that need them.
  81
  82    The results of register allocation are described by the vector
  83    reg_renumber; the insns still contain pseudo regs, but reg_renumber
  84    can be used to find which hard reg, if any, a pseudo reg is in.
  85
  86    The technique we always use is to free up a few hard regs that are
  87    called ``reload regs'', and for each place where a pseudo reg
  88    must be in a hard reg, copy it temporarily into one of the reload regs.
  89
  90    Reload regs are allocated locally for every instruction that needs
  91    reloads.  When there are pseudos which are allocated to a register that
  92    has been chosen as a reload reg, such pseudos must be ``spilled''.
  93    This means that they go to other hard regs, or to stack slots if no other
  94    available hard regs can be found.  Spilling can invalidate more
  95    insns, requiring additional need for reloads, so we must keep checking
  96    until the process stabilizes.
  97
  98    For machines with different classes of registers, we must keep track
  99    of the register class needed for each reload, and make sure that
 100    we allocate enough reload registers of each class.
 101
 102    The file reload.c contains the code that checks one insn for
 103    validity and reports the reloads that it needs.  This file
 104    is in charge of scanning the entire rtl code, accumulating the
 105    reload needs, spilling, assigning reload registers to use for
 106    fixing up each insn, and generating the new insns to copy values
 107    into the reload registers.  */
 108 \f
 109 struct target_reload default_target_reload;
 110 #if SWITCHABLE_TARGET
 111 struct target_reload *this_target_reload = &default_target_reload;
 112 #endif
 113
 114 #define spill_indirect_levels                   \
 115   (this_target_reload->x_spill_indirect_levels)
 116
 117 /* During reload_as_needed, element N contains a REG rtx for the hard reg
 118    into which reg N has been reloaded (perhaps for a previous insn).  */
 119 static rtx *reg_last_reload_reg;
 120
 121 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
 122    for an output reload that stores into reg N.  */
 123 static regset_head reg_has_output_reload;
 124
 125 /* Indicates which hard regs are reload-registers for an output reload
 126    in the current insn.  */
 127 static HARD_REG_SET reg_is_output_reload;
 128
 129 /* Widest width in which each pseudo reg is referred to (via subreg).  */
 130 static unsigned int *reg_max_ref_width;
 131
 132 /* Vector to remember old contents of reg_renumber before spilling.  */
 133 static short *reg_old_renumber;
 134
 135 /* During reload_as_needed, element N contains the last pseudo regno reloaded
 136    into hard register N.  If that pseudo reg occupied more than one register,
 137    reg_reloaded_contents points to that pseudo for each spill register in
 138    use; all of these must remain set for an inheritance to occur.  */
 139 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
 140
 141 /* During reload_as_needed, element N contains the insn for which
 142    hard register N was last used.   Its contents are significant only
 143    when reg_reloaded_valid is set for this register.  */
 144 static rtx_insn *reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
 145
 146 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid.  */
 147 static HARD_REG_SET reg_reloaded_valid;
 148 /* Indicate if the register was dead at the end of the reload.
 149    This is only valid if reg_reloaded_contents is set and valid.  */
 150 static HARD_REG_SET reg_reloaded_dead;
 151
 152 /* Indicate whether the register's current value is one that is not
 153    safe to retain across a call, even for registers that are normally
 154    call-saved.  This is only meaningful for members of reg_reloaded_valid.  */
 155 static HARD_REG_SET reg_reloaded_call_part_clobbered;
 156
 157 /* Number of spill-regs so far; number of valid elements of spill_regs.  */
 158 static int n_spills;
 159
 160 /* In parallel with spill_regs, contains REG rtx's for those regs.
 161    Holds the last rtx used for any given reg, or 0 if it has never
 162    been used for spilling yet.  This rtx is reused, provided it has
 163    the proper mode.  */
 164 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
 165
 166 /* In parallel with spill_regs, contains nonzero for a spill reg
 167    that was stored after the last time it was used.
 168    The precise value is the insn generated to do the store.  */
 169 static rtx_insn *spill_reg_store[FIRST_PSEUDO_REGISTER];
 170
 171 /* This is the register that was stored with spill_reg_store.  This is a
 172    copy of reload_out / reload_out_reg when the value was stored; if
 173    reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg.  */
 174 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
 175
 176 /* This table is the inverse mapping of spill_regs:
 177    indexed by hard reg number,
 178    it contains the position of that reg in spill_regs,
 179    or -1 for something that is not in spill_regs.
 180
 181    ?!?  This is no longer accurate.  */
 182 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
 183
 184 /* This reg set indicates registers that can't be used as spill registers for
 185    the currently processed insn.  These are the hard registers which are live
 186    during the insn, but not allocated to pseudos, as well as fixed
 187    registers.  */
 188 static HARD_REG_SET bad_spill_regs;
 189
 190 /* These are the hard registers that can't be used as spill register for any
 191    insn.  This includes registers used for user variables and registers that
 192    we can't eliminate.  A register that appears in this set also can't be used
 193    to retry register allocation.  */
 194 static HARD_REG_SET bad_spill_regs_global;
 195
 196 /* Describes order of use of registers for reloading
 197    of spilled pseudo-registers.  `n_spills' is the number of
 198    elements that are actually valid; new ones are added at the end.
 199
 200    Both spill_regs and spill_reg_order are used on two occasions:
 201    once during find_reload_regs, where they keep track of the spill registers
 202    for a single insn, but also during reload_as_needed where they show all
 203    the registers ever used by reload.  For the latter case, the information
 204    is calculated during finish_spills.  */
 205 static short spill_regs[FIRST_PSEUDO_REGISTER];
 206
 207 /* This vector of reg sets indicates, for each pseudo, which hard registers
 208    may not be used for retrying global allocation because the register was
 209    formerly spilled from one of them.  If we allowed reallocating a pseudo to
 210    a register that it was already allocated to, reload might not
 211    terminate.  */
 212 static HARD_REG_SET *pseudo_previous_regs;
 213
 214 /* This vector of reg sets indicates, for each pseudo, which hard
 215    registers may not be used for retrying global allocation because they
 216    are used as spill registers during one of the insns in which the
 217    pseudo is live.  */
 218 static HARD_REG_SET *pseudo_forbidden_regs;
 219
 220 /* All hard regs that have been used as spill registers for any insn are
 221    marked in this set.  */
 222 static HARD_REG_SET used_spill_regs;
 223
 224 /* Index of last register assigned as a spill register.  We allocate in
 225    a round-robin fashion.  */
 226 static int last_spill_reg;
 227
 228 /* Record the stack slot for each spilled hard register.  */
 229 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
 230
 231 /* Width allocated so far for that stack slot.  */
 232 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
 233
 234 /* Record which pseudos needed to be spilled.  */
 235 static regset_head spilled_pseudos;
 236
 237 /* Record which pseudos changed their allocation in finish_spills.  */
 238 static regset_head changed_allocation_pseudos;
 239
 240 /* Used for communication between order_regs_for_reload and count_pseudo.
 241    Used to avoid counting one pseudo twice.  */
 242 static regset_head pseudos_counted;
 243
 244 /* First uid used by insns created by reload in this function.
 245    Used in find_equiv_reg.  */
 246 int reload_first_uid;
 247
 248 /* Flag set by local-alloc or global-alloc if anything is live in
 249    a call-clobbered reg across calls.  */
 250 int caller_save_needed;
 251
 252 /* Set to 1 while reload_as_needed is operating.
 253    Required by some machines to handle any generated moves differently.  */
 254 int reload_in_progress = 0;
 255
 256 /* This obstack is used for allocation of rtl during register elimination.
 257    The allocated storage can be freed once find_reloads has processed the
 258    insn.  */
 259 static struct obstack reload_obstack;
 260
 261 /* Points to the beginning of the reload_obstack.  All insn_chain structures
 262    are allocated first.  */
 263 static char *reload_startobj;
 264
 265 /* The point after all insn_chain structures.  Used to quickly deallocate
 266    memory allocated in copy_reloads during calculate_needs_all_insns.  */
 267 static char *reload_firstobj;
 268
 269 /* This points before all local rtl generated by register elimination.
 270    Used to quickly free all memory after processing one insn.  */
 271 static char *reload_insn_firstobj;
 272
 273 /* List of insn_chain instructions, one for every insn that reload needs to
 274    examine.  */
 275 struct insn_chain *reload_insn_chain;
 276
 277 /* TRUE if we potentially left dead insns in the insn stream and want to
 278    run DCE immediately after reload, FALSE otherwise.  */
 279 static bool need_dce;
 280
 281 /* List of all insns needing reloads.  */
 282 static struct insn_chain *insns_need_reload;
 283 \f
 284 /* This structure is used to record information about register eliminations.
 285    Each array entry describes one possible way of eliminating a register
 286    in favor of another.   If there is more than one way of eliminating a
 287    particular register, the most preferred should be specified first.  */
 288
 289 struct elim_table
 290 {
 291   int from;                     /* Register number to be eliminated.  */
 292   int to;                       /* Register number used as replacement.  */
 293   HOST_WIDE_INT initial_offset; /* Initial difference between values.  */
 294   int can_eliminate;            /* Nonzero if this elimination can be done.  */
 295   int can_eliminate_previous;   /* Value returned by TARGET_CAN_ELIMINATE
 296                                    target hook in previous scan over insns
 297                                    made by reload.  */
 298   HOST_WIDE_INT offset;         /* Current offset between the two regs.  */
 299   HOST_WIDE_INT previous_offset;/* Offset at end of previous insn.  */
 300   int ref_outside_mem;          /* "to" has been referenced outside a MEM.  */
 301   rtx from_rtx;                 /* REG rtx for the register to be eliminated.
 302                                    We cannot simply compare the number since
 303                                    we might then spuriously replace a hard
 304                                    register corresponding to a pseudo
 305                                    assigned to the reg to be eliminated.  */
 306   rtx to_rtx;                   /* REG rtx for the replacement.  */
 307 };
 308
 309 static struct elim_table *reg_eliminate = 0;
 310
 311 /* This is an intermediate structure to initialize the table.  It has
 312    exactly the members provided by ELIMINABLE_REGS.  */
 313 static const struct elim_table_1
 314 {
 315   const int from;
 316   const int to;
 317 } reg_eliminate_1[] =
 318
 319 /* If a set of eliminable registers was specified, define the table from it.
 320    Otherwise, default to the normal case of the frame pointer being
 321    replaced by the stack pointer.  */
 322
 323 #ifdef ELIMINABLE_REGS
 324   ELIMINABLE_REGS;
 325 #else
 326   {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
 327 #endif
 328
 329 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
 330
 331 /* Record the number of pending eliminations that have an offset not equal
 332    to their initial offset.  If nonzero, we use a new copy of each
 333    replacement result in any insns encountered.  */
 334 int num_not_at_initial_offset;
 335
 336 /* Count the number of registers that we may be able to eliminate.  */
 337 static int num_eliminable;
 338 /* And the number of registers that are equivalent to a constant that
 339    can be eliminated to frame_pointer / arg_pointer + constant.  */
 340 static int num_eliminable_invariants;
 341
 342 /* For each label, we record the offset of each elimination.  If we reach
 343    a label by more than one path and an offset differs, we cannot do the
 344    elimination.  This information is indexed by the difference of the
 345    number of the label and the first label number.  We can't offset the
 346    pointer itself as this can cause problems on machines with segmented
 347    memory.  The first table is an array of flags that records whether we
 348    have yet encountered a label and the second table is an array of arrays,
 349    one entry in the latter array for each elimination.  */
 350
 351 static int first_label_num;
 352 static char *offsets_known_at;
 353 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
 354
 355 vec<reg_equivs_t, va_gc> *reg_equivs;
 356
 357 /* Stack of addresses where an rtx has been changed.  We can undo the
 358    changes by popping items off the stack and restoring the original
 359    value at each location.
 360
 361    We use this simplistic undo capability rather than copy_rtx as copy_rtx
 362    will not make a deep copy of a normally sharable rtx, such as
 363    (const (plus (symbol_ref) (const_int))).  If such an expression appears
 364    as R1 in gen_reload_chain_without_interm_reg_p, then a shared
 365    rtx expression would be changed.  See PR 42431.  */
 366
 367 typedef rtx *rtx_p;
 368 static vec<rtx_p> substitute_stack;
 369
 370 /* Number of labels in the current function.  */
 371
 372 static int num_labels;
 373 \f
 374 static void replace_pseudos_in (rtx *, machine_mode, rtx);
 375 static void maybe_fix_stack_asms (void);
 376 static void copy_reloads (struct insn_chain *);
 377 static void calculate_needs_all_insns (int);
 378 static int find_reg (struct insn_chain *, int);
 379 static void find_reload_regs (struct insn_chain *);
 380 static void select_reload_regs (void);
 381 static void delete_caller_save_insns (void);
 382
 383 static void spill_failure (rtx_insn *, enum reg_class);
 384 static void count_spilled_pseudo (int, int, int);
 385 static void delete_dead_insn (rtx_insn *);
 386 static void alter_reg (int, int, bool);
 387 static void set_label_offsets (rtx, rtx_insn *, int);
 388 static void check_eliminable_occurrences (rtx);
 389 static void elimination_effects (rtx, machine_mode);
 390 static rtx eliminate_regs_1 (rtx, machine_mode, rtx, bool, bool);
 391 static int eliminate_regs_in_insn (rtx_insn *, int);
 392 static void update_eliminable_offsets (void);
 393 static void mark_not_eliminable (rtx, const_rtx, void *);
 394 static void set_initial_elim_offsets (void);
 395 static bool verify_initial_elim_offsets (void);
 396 static void set_initial_label_offsets (void);
 397 static void set_offsets_for_label (rtx_insn *);
 398 static void init_eliminable_invariants (rtx_insn *, bool);
 399 static void init_elim_table (void);
 400 static void free_reg_equiv (void);
 401 static void update_eliminables (HARD_REG_SET *);
 402 static bool update_eliminables_and_spill (void);
 403 static void elimination_costs_in_insn (rtx_insn *);
 404 static void spill_hard_reg (unsigned int, int);
 405 static int finish_spills (int);
 406 static void scan_paradoxical_subregs (rtx);
 407 static void count_pseudo (int);
 408 static void order_regs_for_reload (struct insn_chain *);
 409 static void reload_as_needed (int);
 410 static void forget_old_reloads_1 (rtx, const_rtx, void *);
 411 static void forget_marked_reloads (regset);
 412 static int reload_reg_class_lower (const void *, const void *);
 413 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
 414                                     machine_mode);
 415 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
 416                                      machine_mode);
 417 static int reload_reg_free_p (unsigned int, int, enum reload_type);
 418 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
 419                                         rtx, rtx, int, int);
 420 static int free_for_value_p (int, machine_mode, int, enum reload_type,
 421                              rtx, rtx, int, int);
 422 static int allocate_reload_reg (struct insn_chain *, int, int);
 423 static int conflicts_with_override (rtx);
 424 static void failed_reload (rtx_insn *, int);
 425 static int set_reload_reg (int, int);
 426 static void choose_reload_regs_init (struct insn_chain *, rtx *);
 427 static void choose_reload_regs (struct insn_chain *);
 428 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
 429                                      rtx, int);
 430 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
 431                                       int);
 432 static void do_input_reload (struct insn_chain *, struct reload *, int);
 433 static void do_output_reload (struct insn_chain *, struct reload *, int);
 434 static void emit_reload_insns (struct insn_chain *);
 435 static void delete_output_reload (rtx_insn *, int, int, rtx);
 436 static void delete_address_reloads (rtx_insn *, rtx_insn *);
 437 static void delete_address_reloads_1 (rtx_insn *, rtx, rtx_insn *);
 438 static void inc_for_reload (rtx, rtx, rtx, int);
 439 #ifdef AUTO_INC_DEC
 440 static void add_auto_inc_notes (rtx_insn *, rtx);
 441 #endif
 442 static void substitute (rtx *, const_rtx, rtx);
 443 static bool gen_reload_chain_without_interm_reg_p (int, int);
 444 static int reloads_conflict (int, int);
 445 static rtx_insn *gen_reload (rtx, rtx, int, enum reload_type);
 446 static rtx_insn *emit_insn_if_valid_for_reload (rtx);
 447 \f
 448 /* Initialize the reload pass.  This is called at the beginning of compilation
 449    and may be called again if the target is reinitialized.  */
 450
 451 void
 452 init_reload (void)
 453 {
 454   int i;
 455
 456   /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
 457      Set spill_indirect_levels to the number of levels such addressing is
 458      permitted, zero if it is not permitted at all.  */
 459
 460   rtx tem
 461     = gen_rtx_MEM (Pmode,
 462                    gen_rtx_PLUS (Pmode,
 463                                  gen_rtx_REG (Pmode,
 464                                               LAST_VIRTUAL_REGISTER + 1),
 465                                  gen_int_mode (4, Pmode)));
 466   spill_indirect_levels = 0;
 467
 468   while (memory_address_p (QImode, tem))
 469     {
 470       spill_indirect_levels++;
 471       tem = gen_rtx_MEM (Pmode, tem);
 472     }
 473
 474   /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)).  */
 475
 476   tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
 477   indirect_symref_ok = memory_address_p (QImode, tem);
 478
 479   /* See if reg+reg is a valid (and offsettable) address.  */
 480
 481   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
 482     {
 483       tem = gen_rtx_PLUS (Pmode,
 484                           gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
 485                           gen_rtx_REG (Pmode, i));
 486
 487       /* This way, we make sure that reg+reg is an offsettable address.  */
 488       tem = plus_constant (Pmode, tem, 4);
 489
 490       if (memory_address_p (QImode, tem))
 491         {
 492           double_reg_address_ok = 1;
 493           break;
 494         }
 495     }
 496
 497   /* Initialize obstack for our rtl allocation.  */
 498   if (reload_startobj == NULL)
 499     {
 500       gcc_obstack_init (&reload_obstack);
 501       reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
 502     }
 503
 504   INIT_REG_SET (&spilled_pseudos);
 505   INIT_REG_SET (&changed_allocation_pseudos);
 506   INIT_REG_SET (&pseudos_counted);
 507 }
 508
 509 /* List of insn chains that are currently unused.  */
 510 static struct insn_chain *unused_insn_chains = 0;
 511
 512 /* Allocate an empty insn_chain structure.  */
 513 struct insn_chain *
 514 new_insn_chain (void)
 515 {
 516   struct insn_chain *c;
 517
 518   if (unused_insn_chains == 0)
 519     {
 520       c = XOBNEW (&reload_obstack, struct insn_chain);
 521       INIT_REG_SET (&c->live_throughout);
 522       INIT_REG_SET (&c->dead_or_set);
 523     }
 524   else
 525     {
 526       c = unused_insn_chains;
 527       unused_insn_chains = c->next;
 528     }
 529   c->is_caller_save_insn = 0;
 530   c->need_operand_change = 0;
 531   c->need_reload = 0;
 532   c->need_elim = 0;
 533   return c;
 534 }
 535
 536 /* Small utility function to set all regs in hard reg set TO which are
 537    allocated to pseudos in regset FROM.  */
 538
 539 void
 540 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
 541 {
 542   unsigned int regno;
 543   reg_set_iterator rsi;
 544
 545   EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
 546     {
 547       int r = reg_renumber[regno];
 548
 549       if (r < 0)
 550         {
 551           /* reload_combine uses the information from DF_LIVE_IN,
 552              which might still contain registers that have not
 553              actually been allocated since they have an
 554              equivalence.  */
 555           gcc_assert (ira_conflicts_p || reload_completed);
 556         }
 557       else
 558         add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
 559     }
 560 }
 561
 562 /* Replace all pseudos found in LOC with their corresponding
 563    equivalences.  */
 564
 565 static void
 566 replace_pseudos_in (rtx *loc, machine_mode mem_mode, rtx usage)
 567 {
 568   rtx x = *loc;
 569   enum rtx_code code;
 570   const char *fmt;
 571   int i, j;
 572
 573   if (! x)
 574     return;
 575
 576   code = GET_CODE (x);
 577   if (code == REG)
 578     {
 579       unsigned int regno = REGNO (x);
 580
 581       if (regno < FIRST_PSEUDO_REGISTER)
 582         return;
 583
 584       x = eliminate_regs_1 (x, mem_mode, usage, true, false);
 585       if (x != *loc)
 586         {
 587           *loc = x;
 588           replace_pseudos_in (loc, mem_mode, usage);
 589           return;
 590         }
 591
 592       if (reg_equiv_constant (regno))
 593         *loc = reg_equiv_constant (regno);
 594       else if (reg_equiv_invariant (regno))
 595         *loc = reg_equiv_invariant (regno);
 596       else if (reg_equiv_mem (regno))
 597         *loc = reg_equiv_mem (regno);
 598       else if (reg_equiv_address (regno))
 599         *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address (regno));
 600       else
 601         {
 602           gcc_assert (!REG_P (regno_reg_rtx[regno])
 603                       || REGNO (regno_reg_rtx[regno]) != regno);
 604           *loc = regno_reg_rtx[regno];
 605         }
 606
 607       return;
 608     }
 609   else if (code == MEM)
 610     {
 611       replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
 612       return;
 613     }
 614
 615   /* Process each of our operands recursively.  */
 616   fmt = GET_RTX_FORMAT (code);
 617   for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
 618     if (*fmt == 'e')
 619       replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
 620     else if (*fmt == 'E')
 621       for (j = 0; j < XVECLEN (x, i); j++)
 622         replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
 623 }
 624
 625 /* Determine if the current function has an exception receiver block
 626    that reaches the exit block via non-exceptional edges  */
 627
 628 static bool
 629 has_nonexceptional_receiver (void)
 630 {
 631   edge e;
 632   edge_iterator ei;
 633   basic_block *tos, *worklist, bb;
 634
 635   /* If we're not optimizing, then just err on the safe side.  */
 636   if (!optimize)
 637     return true;
 638
 639   /* First determine which blocks can reach exit via normal paths.  */
 640   tos = worklist = XNEWVEC (basic_block, n_basic_blocks_for_fn (cfun) + 1);
 641
 642   FOR_EACH_BB_FN (bb, cfun)
 643     bb->flags &= ~BB_REACHABLE;
 644
 645   /* Place the exit block on our worklist.  */
 646   EXIT_BLOCK_PTR_FOR_FN (cfun)->flags |= BB_REACHABLE;
 647   *tos++ = EXIT_BLOCK_PTR_FOR_FN (cfun);
 648
 649   /* Iterate: find everything reachable from what we've already seen.  */
 650   while (tos != worklist)
 651     {
 652       bb = *--tos;
 653
 654       FOR_EACH_EDGE (e, ei, bb->preds)
 655         if (!(e->flags & EDGE_ABNORMAL))
 656           {
 657             basic_block src = e->src;
 658
 659             if (!(src->flags & BB_REACHABLE))
 660               {
 661                 src->flags |= BB_REACHABLE;
 662                 *tos++ = src;
 663               }
 664           }
 665     }
 666   free (worklist);
 667
 668   /* Now see if there's a reachable block with an exceptional incoming
 669      edge.  */
 670   FOR_EACH_BB_FN (bb, cfun)
 671     if (bb->flags & BB_REACHABLE && bb_has_abnormal_pred (bb))
 672       return true;
 673
 674   /* No exceptional block reached exit unexceptionally.  */
 675   return false;
 676 }
 677
 678 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
 679    zero elements) to MAX_REG_NUM elements.
 680
 681    Initialize all new fields to NULL and update REG_EQUIVS_SIZE.  */
 682 void
 683 grow_reg_equivs (void)
 684 {
 685   int old_size = vec_safe_length (reg_equivs);
 686   int max_regno = max_reg_num ();
 687   int i;
 688   reg_equivs_t ze;
 689
 690   memset (&ze, 0, sizeof (reg_equivs_t));
 691   vec_safe_reserve (reg_equivs, max_regno);
 692   for (i = old_size; i < max_regno; i++)
 693     reg_equivs->quick_insert (i, ze);
 694 }
 695
 696 \f
 697 /* Global variables used by reload and its subroutines.  */
 698
 699 /* The current basic block while in calculate_elim_costs_all_insns.  */
 700 static basic_block elim_bb;
 701
 702 /* Set during calculate_needs if an insn needs register elimination.  */
 703 static int something_needs_elimination;
 704 /* Set during calculate_needs if an insn needs an operand changed.  */
 705 static int something_needs_operands_changed;
 706 /* Set by alter_regs if we spilled a register to the stack.  */
 707 static bool something_was_spilled;
 708
 709 /* Nonzero means we couldn't get enough spill regs.  */
 710 static int failure;
 711
 712 /* Temporary array of pseudo-register number.  */
 713 static int *temp_pseudo_reg_arr;
 714
 715 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
 716    If that insn didn't set the register (i.e., it copied the register to
 717    memory), just delete that insn instead of the equivalencing insn plus
 718    anything now dead.  If we call delete_dead_insn on that insn, we may
 719    delete the insn that actually sets the register if the register dies
 720    there and that is incorrect.  */
 721 static void
 722 remove_init_insns ()
 723 {
 724   for (int i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
 725     {
 726       if (reg_renumber[i] < 0 && reg_equiv_init (i) != 0)
 727         {
 728           rtx list;
 729           for (list = reg_equiv_init (i); list; list = XEXP (list, 1))
 730             {
 731               rtx_insn *equiv_insn = as_a <rtx_insn *> (XEXP (list, 0));
 732
 733               /* If we already deleted the insn or if it may trap, we can't
 734                  delete it.  The latter case shouldn't happen, but can
 735                  if an insn has a variable address, gets a REG_EH_REGION
 736                  note added to it, and then gets converted into a load
 737                  from a constant address.  */
 738               if (NOTE_P (equiv_insn)
 739                   || can_throw_internal (equiv_insn))
 740                 ;
 741               else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
 742                 delete_dead_insn (equiv_insn);
 743               else
 744                 SET_INSN_DELETED (equiv_insn);
 745             }
 746         }
 747     }
 748 }
 749
 750 /* Return true if remove_init_insns will delete INSN.  */
 751 static bool
 752 will_delete_init_insn_p (rtx_insn *insn)
 753 {
 754   rtx set = single_set (insn);
 755   if (!set || !REG_P (SET_DEST (set)))
 756     return false;
 757   unsigned regno = REGNO (SET_DEST (set));
 758
 759   if (can_throw_internal (insn))
 760     return false;
 761
 762   if (regno < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0)
 763     return false;
 764
 765   for (rtx list = reg_equiv_init (regno); list; list = XEXP (list, 1))
 766     {
 767       rtx equiv_insn = XEXP (list, 0);
 768       if (equiv_insn == insn)
 769         return true;
 770     }
 771   return false;
 772 }
 773
 774 /* Main entry point for the reload pass.
 775
 776    FIRST is the first insn of the function being compiled.
 777
 778    GLOBAL nonzero means we were called from global_alloc
 779    and should attempt to reallocate any pseudoregs that we
 780    displace from hard regs we will use for reloads.
 781    If GLOBAL is zero, we do not have enough information to do that,
 782    so any pseudo reg that is spilled must go to the stack.
 783
 784    Return value is TRUE if reload likely left dead insns in the
 785    stream and a DCE pass should be run to elimiante them.  Else the
 786    return value is FALSE.  */
 787
 788 bool
 789 reload (rtx_insn *first, int global)
 790 {
 791   int i, n;
 792   rtx_insn *insn;
 793   struct elim_table *ep;
 794   basic_block bb;
 795   bool inserted;
 796
 797   /* Make sure even insns with volatile mem refs are recognizable.  */
 798   init_recog ();
 799
 800   failure = 0;
 801
 802   reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
 803
 804   /* Make sure that the last insn in the chain
 805      is not something that needs reloading.  */
 806   emit_note (NOTE_INSN_DELETED);
 807
 808   /* Enable find_equiv_reg to distinguish insns made by reload.  */
 809   reload_first_uid = get_max_uid ();
 810
 811 #ifdef SECONDARY_MEMORY_NEEDED
 812   /* Initialize the secondary memory table.  */
 813   clear_secondary_mem ();
 814 #endif
 815
 816   /* We don't have a stack slot for any spill reg yet.  */
 817   memset (spill_stack_slot, 0, sizeof spill_stack_slot);
 818   memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
 819
 820   /* Initialize the save area information for caller-save, in case some
 821      are needed.  */
 822   init_save_areas ();
 823
 824   /* Compute which hard registers are now in use
 825      as homes for pseudo registers.
 826      This is done here rather than (eg) in global_alloc
 827      because this point is reached even if not optimizing.  */
 828   for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
 829     mark_home_live (i);
 830
 831   /* A function that has a nonlocal label that can reach the exit
 832      block via non-exceptional paths must save all call-saved
 833      registers.  */
 834   if (cfun->has_nonlocal_label
 835       && has_nonexceptional_receiver ())
 836     crtl->saves_all_registers = 1;
 837
 838   if (crtl->saves_all_registers)
 839     for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
 840       if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
 841         df_set_regs_ever_live (i, true);
 842
 843   /* Find all the pseudo registers that didn't get hard regs
 844      but do have known equivalent constants or memory slots.
 845      These include parameters (known equivalent to parameter slots)
 846      and cse'd or loop-moved constant memory addresses.
 847
 848      Record constant equivalents in reg_equiv_constant
 849      so they will be substituted by find_reloads.
 850      Record memory equivalents in reg_mem_equiv so they can
 851      be substituted eventually by altering the REG-rtx's.  */
 852
 853   grow_reg_equivs ();
 854   reg_old_renumber = XCNEWVEC (short, max_regno);
 855   memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
 856   pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
 857   pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
 858
 859   CLEAR_HARD_REG_SET (bad_spill_regs_global);
 860
 861   init_eliminable_invariants (first, true);
 862   init_elim_table ();
 863
 864   /* Alter each pseudo-reg rtx to contain its hard reg number.  Assign
 865      stack slots to the pseudos that lack hard regs or equivalents.
 866      Do not touch virtual registers.  */
 867
 868   temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
 869   for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
 870     temp_pseudo_reg_arr[n++] = i;
 871
 872   if (ira_conflicts_p)
 873     /* Ask IRA to order pseudo-registers for better stack slot
 874        sharing.  */
 875     ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
 876
 877   for (i = 0; i < n; i++)
 878     alter_reg (temp_pseudo_reg_arr[i], -1, false);
 879
 880   /* If we have some registers we think can be eliminated, scan all insns to
 881      see if there is an insn that sets one of these registers to something
 882      other than itself plus a constant.  If so, the register cannot be
 883      eliminated.  Doing this scan here eliminates an extra pass through the
 884      main reload loop in the most common case where register elimination
 885      cannot be done.  */
 886   for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
 887     if (INSN_P (insn))
 888       note_stores (PATTERN (insn), mark_not_eliminable, NULL);
 889
 890   maybe_fix_stack_asms ();
 891
 892   insns_need_reload = 0;
 893   something_needs_elimination = 0;
 894
 895   /* Initialize to -1, which means take the first spill register.  */
 896   last_spill_reg = -1;
 897
 898   /* Spill any hard regs that we know we can't eliminate.  */
 899   CLEAR_HARD_REG_SET (used_spill_regs);
 900   /* There can be multiple ways to eliminate a register;
 901      they should be listed adjacently.
 902      Elimination for any register fails only if all possible ways fail.  */
 903   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; )
 904     {
 905       int from = ep->from;
 906       int can_eliminate = 0;
 907       do
 908         {
 909           can_eliminate |= ep->can_eliminate;
 910           ep++;
 911         }
 912       while (ep < &reg_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
 913       if (! can_eliminate)
 914         spill_hard_reg (from, 1);
 915     }
 916
 917   if (!HARD_FRAME_POINTER_IS_FRAME_POINTER && frame_pointer_needed)
 918     spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
 919
 920   finish_spills (global);
 921
 922   /* From now on, we may need to generate moves differently.  We may also
 923      allow modifications of insns which cause them to not be recognized.
 924      Any such modifications will be cleaned up during reload itself.  */
 925   reload_in_progress = 1;
 926
 927   /* This loop scans the entire function each go-round
 928      and repeats until one repetition spills no additional hard regs.  */
 929   for (;;)
 930     {
 931       int something_changed;
 932       int did_spill;
 933       HOST_WIDE_INT starting_frame_size;
 934
 935       starting_frame_size = get_frame_size ();
 936       something_was_spilled = false;
 937
 938       set_initial_elim_offsets ();
 939       set_initial_label_offsets ();
 940
 941       /* For each pseudo register that has an equivalent location defined,
 942          try to eliminate any eliminable registers (such as the frame pointer)
 943          assuming initial offsets for the replacement register, which
 944          is the normal case.
 945
 946          If the resulting location is directly addressable, substitute
 947          the MEM we just got directly for the old REG.
 948
 949          If it is not addressable but is a constant or the sum of a hard reg
 950          and constant, it is probably not addressable because the constant is
 951          out of range, in that case record the address; we will generate
 952          hairy code to compute the address in a register each time it is
 953          needed.  Similarly if it is a hard register, but one that is not
 954          valid as an address register.
 955
 956          If the location is not addressable, but does not have one of the
 957          above forms, assign a stack slot.  We have to do this to avoid the
 958          potential of producing lots of reloads if, e.g., a location involves
 959          a pseudo that didn't get a hard register and has an equivalent memory
 960          location that also involves a pseudo that didn't get a hard register.
 961
 962          Perhaps at some point we will improve reload_when_needed handling
 963          so this problem goes away.  But that's very hairy.  */
 964
 965       for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
 966         if (reg_renumber[i] < 0 && reg_equiv_memory_loc (i))
 967           {
 968             rtx x = eliminate_regs (reg_equiv_memory_loc (i), VOIDmode,
 969                                     NULL_RTX);
 970
 971             if (strict_memory_address_addr_space_p
 972                   (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
 973                    MEM_ADDR_SPACE (x)))
 974               reg_equiv_mem (i) = x, reg_equiv_address (i) = 0;
 975             else if (CONSTANT_P (XEXP (x, 0))
 976                      || (REG_P (XEXP (x, 0))
 977                          && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
 978                      || (GET_CODE (XEXP (x, 0)) == PLUS
 979                          && REG_P (XEXP (XEXP (x, 0), 0))
 980                          && (REGNO (XEXP (XEXP (x, 0), 0))
 981                              < FIRST_PSEUDO_REGISTER)
 982                          && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
 983               reg_equiv_address (i) = XEXP (x, 0), reg_equiv_mem (i) = 0;
 984             else
 985               {
 986                 /* Make a new stack slot.  Then indicate that something
 987                    changed so we go back and recompute offsets for
 988                    eliminable registers because the allocation of memory
 989                    below might change some offset.  reg_equiv_{mem,address}
 990                    will be set up for this pseudo on the next pass around
 991                    the loop.  */
 992                 reg_equiv_memory_loc (i) = 0;
 993                 reg_equiv_init (i) = 0;
 994                 alter_reg (i, -1, true);
 995               }
 996           }
 997
 998       if (caller_save_needed)
 999         setup_save_areas ();
1000
1001       if (starting_frame_size && crtl->stack_alignment_needed)
1002         {
1003           /* If we have a stack frame, we must align it now.  The
1004              stack size may be a part of the offset computation for
1005              register elimination.  So if this changes the stack size,
1006              then repeat the elimination bookkeeping.  We don't
1007              realign when there is no stack, as that will cause a
1008              stack frame when none is needed should
1009              STARTING_FRAME_OFFSET not be already aligned to
1010              STACK_BOUNDARY.  */
1011           assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
1012         }
1013       /* If we allocated another stack slot, redo elimination bookkeeping.  */
1014       if (something_was_spilled || starting_frame_size != get_frame_size ())
1015         {
1016           update_eliminables_and_spill ();
1017           continue;
1018         }
1019
1020       if (caller_save_needed)
1021         {
1022           save_call_clobbered_regs ();
1023           /* That might have allocated new insn_chain structures.  */
1024           reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1025         }
1026
1027       calculate_needs_all_insns (global);
1028
1029       if (! ira_conflicts_p)
1030         /* Don't do it for IRA.  We need this info because we don't
1031            change live_throughout and dead_or_set for chains when IRA
1032            is used.  */
1033         CLEAR_REG_SET (&spilled_pseudos);
1034
1035       did_spill = 0;
1036
1037       something_changed = 0;
1038
1039       /* If we allocated any new memory locations, make another pass
1040          since it might have changed elimination offsets.  */
1041       if (something_was_spilled || starting_frame_size != get_frame_size ())
1042         something_changed = 1;
1043
1044       /* Even if the frame size remained the same, we might still have
1045          changed elimination offsets, e.g. if find_reloads called
1046          force_const_mem requiring the back end to allocate a constant
1047          pool base register that needs to be saved on the stack.  */
1048       else if (!verify_initial_elim_offsets ())
1049         something_changed = 1;
1050
1051       if (update_eliminables_and_spill ())
1052         {
1053           did_spill = 1;
1054           something_changed = 1;
1055         }
1056
1057       select_reload_regs ();
1058       if (failure)
1059         goto failed;
1060
1061       if (insns_need_reload != 0 || did_spill)
1062         something_changed |= finish_spills (global);
1063
1064       if (! something_changed)
1065         break;
1066
1067       if (caller_save_needed)
1068         delete_caller_save_insns ();
1069
1070       obstack_free (&reload_obstack, reload_firstobj);
1071     }
1072
1073   /* If global-alloc was run, notify it of any register eliminations we have
1074      done.  */
1075   if (global)
1076     for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1077       if (ep->can_eliminate)
1078         mark_elimination (ep->from, ep->to);
1079
1080   remove_init_insns ();
1081
1082   /* Use the reload registers where necessary
1083      by generating move instructions to move the must-be-register
1084      values into or out of the reload registers.  */
1085
1086   if (insns_need_reload != 0 || something_needs_elimination
1087       || something_needs_operands_changed)
1088     {
1089       HOST_WIDE_INT old_frame_size = get_frame_size ();
1090
1091       reload_as_needed (global);
1092
1093       gcc_assert (old_frame_size == get_frame_size ());
1094
1095       gcc_assert (verify_initial_elim_offsets ());
1096     }
1097
1098   /* If we were able to eliminate the frame pointer, show that it is no
1099      longer live at the start of any basic block.  If it ls live by
1100      virtue of being in a pseudo, that pseudo will be marked live
1101      and hence the frame pointer will be known to be live via that
1102      pseudo.  */
1103
1104   if (! frame_pointer_needed)
1105     FOR_EACH_BB_FN (bb, cfun)
1106       bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1107
1108   /* Come here (with failure set nonzero) if we can't get enough spill
1109      regs.  */
1110  failed:
1111
1112   CLEAR_REG_SET (&changed_allocation_pseudos);
1113   CLEAR_REG_SET (&spilled_pseudos);
1114   reload_in_progress = 0;
1115
1116   /* Now eliminate all pseudo regs by modifying them into
1117      their equivalent memory references.
1118      The REG-rtx's for the pseudos are modified in place,
1119      so all insns that used to refer to them now refer to memory.
1120
1121      For a reg that has a reg_equiv_address, all those insns
1122      were changed by reloading so that no insns refer to it any longer;
1123      but the DECL_RTL of a variable decl may refer to it,
1124      and if so this causes the debugging info to mention the variable.  */
1125
1126   for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1127     {
1128       rtx addr = 0;
1129
1130       if (reg_equiv_mem (i))
1131         addr = XEXP (reg_equiv_mem (i), 0);
1132
1133       if (reg_equiv_address (i))
1134         addr = reg_equiv_address (i);
1135
1136       if (addr)
1137         {
1138           if (reg_renumber[i] < 0)
1139             {
1140               rtx reg = regno_reg_rtx[i];
1141
1142               REG_USERVAR_P (reg) = 0;
1143               PUT_CODE (reg, MEM);
1144               XEXP (reg, 0) = addr;
1145               if (reg_equiv_memory_loc (i))
1146                 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc (i));
1147               else
1148                 MEM_ATTRS (reg) = 0;
1149               MEM_NOTRAP_P (reg) = 1;
1150             }
1151           else if (reg_equiv_mem (i))
1152             XEXP (reg_equiv_mem (i), 0) = addr;
1153         }
1154
1155       /* We don't want complex addressing modes in debug insns
1156          if simpler ones will do, so delegitimize equivalences
1157          in debug insns.  */
1158       if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
1159         {
1160           rtx reg = regno_reg_rtx[i];
1161           rtx equiv = 0;
1162           df_ref use, next;
1163
1164           if (reg_equiv_constant (i))
1165             equiv = reg_equiv_constant (i);
1166           else if (reg_equiv_invariant (i))
1167             equiv = reg_equiv_invariant (i);
1168           else if (reg && MEM_P (reg))
1169             equiv = targetm.delegitimize_address (reg);
1170           else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1171             equiv = reg;
1172
1173           if (equiv == reg)
1174             continue;
1175
1176           for (use = DF_REG_USE_CHAIN (i); use; use = next)
1177             {
1178               insn = DF_REF_INSN (use);
1179
1180               /* Make sure the next ref is for a different instruction,
1181                  so that we're not affected by the rescan.  */
1182               next = DF_REF_NEXT_REG (use);
1183               while (next && DF_REF_INSN (next) == insn)
1184                 next = DF_REF_NEXT_REG (next);
1185
1186               if (DEBUG_INSN_P (insn))
1187                 {
1188                   if (!equiv)
1189                     {
1190                       INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1191                       df_insn_rescan_debug_internal (insn);
1192                     }
1193                   else
1194                     INSN_VAR_LOCATION_LOC (insn)
1195                       = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1196                                               reg, equiv);
1197                 }
1198             }
1199         }
1200     }
1201
1202   /* We must set reload_completed now since the cleanup_subreg_operands call
1203      below will re-recognize each insn and reload may have generated insns
1204      which are only valid during and after reload.  */
1205   reload_completed = 1;
1206
1207   /* Make a pass over all the insns and delete all USEs which we inserted
1208      only to tag a REG_EQUAL note on them.  Remove all REG_DEAD and REG_UNUSED
1209      notes.  Delete all CLOBBER insns, except those that refer to the return
1210      value and the special mem:BLK CLOBBERs added to prevent the scheduler
1211      from misarranging variable-array code, and simplify (subreg (reg))
1212      operands.  Strip and regenerate REG_INC notes that may have been moved
1213      around.  */
1214
1215   for (insn = first; insn; insn = NEXT_INSN (insn))
1216     if (INSN_P (insn))
1217       {
1218         rtx *pnote;
1219
1220         if (CALL_P (insn))
1221           replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1222                               VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1223
1224         if ((GET_CODE (PATTERN (insn)) == USE
1225              /* We mark with QImode USEs introduced by reload itself.  */
1226              && (GET_MODE (insn) == QImode
1227                  || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1228             || (GET_CODE (PATTERN (insn)) == CLOBBER
1229                 && (!MEM_P (XEXP (PATTERN (insn), 0))
1230                     || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1231                     || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1232                         && XEXP (XEXP (PATTERN (insn), 0), 0)
1233                                 != stack_pointer_rtx))
1234                 && (!REG_P (XEXP (PATTERN (insn), 0))
1235                     || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1236           {
1237             delete_insn (insn);
1238             continue;
1239           }
1240
1241         /* Some CLOBBERs may survive until here and still reference unassigned
1242            pseudos with const equivalent, which may in turn cause ICE in later
1243            passes if the reference remains in place.  */
1244         if (GET_CODE (PATTERN (insn)) == CLOBBER)
1245           replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1246                               VOIDmode, PATTERN (insn));
1247
1248         /* Discard obvious no-ops, even without -O.  This optimization
1249            is fast and doesn't interfere with debugging.  */
1250         if (NONJUMP_INSN_P (insn)
1251             && GET_CODE (PATTERN (insn)) == SET
1252             && REG_P (SET_SRC (PATTERN (insn)))
1253             && REG_P (SET_DEST (PATTERN (insn)))
1254             && (REGNO (SET_SRC (PATTERN (insn)))
1255                 == REGNO (SET_DEST (PATTERN (insn)))))
1256           {
1257             delete_insn (insn);
1258             continue;
1259           }
1260
1261         pnote = &REG_NOTES (insn);
1262         while (*pnote != 0)
1263           {
1264             if (REG_NOTE_KIND (*pnote) == REG_DEAD
1265                 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1266                 || REG_NOTE_KIND (*pnote) == REG_INC)
1267               *pnote = XEXP (*pnote, 1);
1268             else
1269               pnote = &XEXP (*pnote, 1);
1270           }
1271
1272 #ifdef AUTO_INC_DEC
1273         add_auto_inc_notes (insn, PATTERN (insn));
1274 #endif
1275
1276         /* Simplify (subreg (reg)) if it appears as an operand.  */
1277         cleanup_subreg_operands (insn);
1278
1279         /* Clean up invalid ASMs so that they don't confuse later passes.
1280            See PR 21299.  */
1281         if (asm_noperands (PATTERN (insn)) >= 0)
1282           {
1283             extract_insn (insn);
1284             if (!constrain_operands (1, get_enabled_alternatives (insn)))
1285               {
1286                 error_for_asm (insn,
1287                                "%<asm%> operand has impossible constraints");
1288                 delete_insn (insn);
1289                 continue;
1290               }
1291           }
1292       }
1293
1294   /* If we are doing generic stack checking, give a warning if this
1295      function's frame size is larger than we expect.  */
1296   if (flag_stack_check == GENERIC_STACK_CHECK)
1297     {
1298       HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1299       static int verbose_warned = 0;
1300
1301       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1302         if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1303           size += UNITS_PER_WORD;
1304
1305       if (size > STACK_CHECK_MAX_FRAME_SIZE)
1306         {
1307           warning (0, "frame size too large for reliable stack checking");
1308           if (! verbose_warned)
1309             {
1310               warning (0, "try reducing the number of local variables");
1311               verbose_warned = 1;
1312             }
1313         }
1314     }
1315
1316   free (temp_pseudo_reg_arr);
1317
1318   /* Indicate that we no longer have known memory locations or constants.  */
1319   free_reg_equiv ();
1320
1321   free (reg_max_ref_width);
1322   free (reg_old_renumber);
1323   free (pseudo_previous_regs);
1324   free (pseudo_forbidden_regs);
1325
1326   CLEAR_HARD_REG_SET (used_spill_regs);
1327   for (i = 0; i < n_spills; i++)
1328     SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1329
1330   /* Free all the insn_chain structures at once.  */
1331   obstack_free (&reload_obstack, reload_startobj);
1332   unused_insn_chains = 0;
1333
1334   inserted = fixup_abnormal_edges ();
1335
1336   /* We've possibly turned single trapping insn into multiple ones.  */
1337   if (cfun->can_throw_non_call_exceptions)
1338     {
1339       sbitmap blocks;
1340       blocks = sbitmap_alloc (last_basic_block_for_fn (cfun));
1341       bitmap_ones (blocks);
1342       find_many_sub_basic_blocks (blocks);
1343       sbitmap_free (blocks);
1344     }
1345
1346   if (inserted)
1347     commit_edge_insertions ();
1348
1349   /* Replacing pseudos with their memory equivalents might have
1350      created shared rtx.  Subsequent passes would get confused
1351      by this, so unshare everything here.  */
1352   unshare_all_rtl_again (first);
1353
1354 #ifdef STACK_BOUNDARY
1355   /* init_emit has set the alignment of the hard frame pointer
1356      to STACK_BOUNDARY.  It is very likely no longer valid if
1357      the hard frame pointer was used for register allocation.  */
1358   if (!frame_pointer_needed)
1359     REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1360 #endif
1361
1362   substitute_stack.release ();
1363
1364   gcc_assert (bitmap_empty_p (&spilled_pseudos));
1365
1366   reload_completed = !failure;
1367
1368   return need_dce;
1369 }
1370
1371 /* Yet another special case.  Unfortunately, reg-stack forces people to
1372    write incorrect clobbers in asm statements.  These clobbers must not
1373    cause the register to appear in bad_spill_regs, otherwise we'll call
1374    fatal_insn later.  We clear the corresponding regnos in the live
1375    register sets to avoid this.
1376    The whole thing is rather sick, I'm afraid.  */
1377
1378 static void
1379 maybe_fix_stack_asms (void)
1380 {
1381 #ifdef STACK_REGS
1382   const char *constraints[MAX_RECOG_OPERANDS];
1383   machine_mode operand_mode[MAX_RECOG_OPERANDS];
1384   struct insn_chain *chain;
1385
1386   for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1387     {
1388       int i, noperands;
1389       HARD_REG_SET clobbered, allowed;
1390       rtx pat;
1391
1392       if (! INSN_P (chain->insn)
1393           || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1394         continue;
1395       pat = PATTERN (chain->insn);
1396       if (GET_CODE (pat) != PARALLEL)
1397         continue;
1398
1399       CLEAR_HARD_REG_SET (clobbered);
1400       CLEAR_HARD_REG_SET (allowed);
1401
1402       /* First, make a mask of all stack regs that are clobbered.  */
1403       for (i = 0; i < XVECLEN (pat, 0); i++)
1404         {
1405           rtx t = XVECEXP (pat, 0, i);
1406           if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1407             SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1408         }
1409
1410       /* Get the operand values and constraints out of the insn.  */
1411       decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1412                            constraints, operand_mode, NULL);
1413
1414       /* For every operand, see what registers are allowed.  */
1415       for (i = 0; i < noperands; i++)
1416         {
1417           const char *p = constraints[i];
1418           /* For every alternative, we compute the class of registers allowed
1419              for reloading in CLS, and merge its contents into the reg set
1420              ALLOWED.  */
1421           int cls = (int) NO_REGS;
1422
1423           for (;;)
1424             {
1425               char c = *p;
1426
1427               if (c == '\0' || c == ',' || c == '#')
1428                 {
1429                   /* End of one alternative - mark the regs in the current
1430                      class, and reset the class.  */
1431                   IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1432                   cls = NO_REGS;
1433                   p++;
1434                   if (c == '#')
1435                     do {
1436                       c = *p++;
1437                     } while (c != '\0' && c != ',');
1438                   if (c == '\0')
1439                     break;
1440                   continue;
1441                 }
1442
1443               switch (c)
1444                 {
1445                 case 'g':
1446                   cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1447                   break;
1448
1449                 default:
1450                   enum constraint_num cn = lookup_constraint (p);
1451                   if (insn_extra_address_constraint (cn))
1452                     cls = (int) reg_class_subunion[cls]
1453                       [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1454                                              ADDRESS, SCRATCH)];
1455                   else
1456                     cls = (int) reg_class_subunion[cls]
1457                       [reg_class_for_constraint (cn)];
1458                   break;
1459                 }
1460               p += CONSTRAINT_LEN (c, p);
1461             }
1462         }
1463       /* Those of the registers which are clobbered, but allowed by the
1464          constraints, must be usable as reload registers.  So clear them
1465          out of the life information.  */
1466       AND_HARD_REG_SET (allowed, clobbered);
1467       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1468         if (TEST_HARD_REG_BIT (allowed, i))
1469           {
1470             CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1471             CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1472           }
1473     }
1474
1475 #endif
1476 }
1477 \f
1478 /* Copy the global variables n_reloads and rld into the corresponding elts
1479    of CHAIN.  */
1480 static void
1481 copy_reloads (struct insn_chain *chain)
1482 {
1483   chain->n_reloads = n_reloads;
1484   chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1485   memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1486   reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1487 }
1488
1489 /* Walk the chain of insns, and determine for each whether it needs reloads
1490    and/or eliminations.  Build the corresponding insns_need_reload list, and
1491    set something_needs_elimination as appropriate.  */
1492 static void
1493 calculate_needs_all_insns (int global)
1494 {
1495   struct insn_chain **pprev_reload = &insns_need_reload;
1496   struct insn_chain *chain, *next = 0;
1497
1498   something_needs_elimination = 0;
1499
1500   reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1501   for (chain = reload_insn_chain; chain != 0; chain = next)
1502     {
1503       rtx_insn *insn = chain->insn;
1504
1505       next = chain->next;
1506
1507       /* Clear out the shortcuts.  */
1508       chain->n_reloads = 0;
1509       chain->need_elim = 0;
1510       chain->need_reload = 0;
1511       chain->need_operand_change = 0;
1512
1513       /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1514          include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1515          what effects this has on the known offsets at labels.  */
1516
1517       if (LABEL_P (insn) || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
1518           || (INSN_P (insn) && REG_NOTES (insn) != 0))
1519         set_label_offsets (insn, insn, 0);
1520
1521       if (INSN_P (insn))
1522         {
1523           rtx old_body = PATTERN (insn);
1524           int old_code = INSN_CODE (insn);
1525           rtx old_notes = REG_NOTES (insn);
1526           int did_elimination = 0;
1527           int operands_changed = 0;
1528
1529           /* Skip insns that only set an equivalence.  */
1530           if (will_delete_init_insn_p (insn))
1531             continue;
1532
1533           /* If needed, eliminate any eliminable registers.  */
1534           if (num_eliminable || num_eliminable_invariants)
1535             did_elimination = eliminate_regs_in_insn (insn, 0);
1536
1537           /* Analyze the instruction.  */
1538           operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1539                                            global, spill_reg_order);
1540
1541           /* If a no-op set needs more than one reload, this is likely
1542              to be something that needs input address reloads.  We
1543              can't get rid of this cleanly later, and it is of no use
1544              anyway, so discard it now.
1545              We only do this when expensive_optimizations is enabled,
1546              since this complements reload inheritance / output
1547              reload deletion, and it can make debugging harder.  */
1548           if (flag_expensive_optimizations && n_reloads > 1)
1549             {
1550               rtx set = single_set (insn);
1551               if (set
1552                   &&
1553                   ((SET_SRC (set) == SET_DEST (set)
1554                     && REG_P (SET_SRC (set))
1555                     && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1556                    || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1557                        && reg_renumber[REGNO (SET_SRC (set))] < 0
1558                        && reg_renumber[REGNO (SET_DEST (set))] < 0
1559                        && reg_equiv_memory_loc (REGNO (SET_SRC (set))) != NULL
1560                        && reg_equiv_memory_loc (REGNO (SET_DEST (set))) != NULL
1561                        && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set))),
1562                                        reg_equiv_memory_loc (REGNO (SET_DEST (set)))))))
1563                 {
1564                   if (ira_conflicts_p)
1565                     /* Inform IRA about the insn deletion.  */
1566                     ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1567                                                    REGNO (SET_SRC (set)));
1568                   delete_insn (insn);
1569                   /* Delete it from the reload chain.  */
1570                   if (chain->prev)
1571                     chain->prev->next = next;
1572                   else
1573                     reload_insn_chain = next;
1574                   if (next)
1575                     next->prev = chain->prev;
1576                   chain->next = unused_insn_chains;
1577                   unused_insn_chains = chain;
1578                   continue;
1579                 }
1580             }
1581           if (num_eliminable)
1582             update_eliminable_offsets ();
1583
1584           /* Remember for later shortcuts which insns had any reloads or
1585              register eliminations.  */
1586           chain->need_elim = did_elimination;
1587           chain->need_reload = n_reloads > 0;
1588           chain->need_operand_change = operands_changed;
1589
1590           /* Discard any register replacements done.  */
1591           if (did_elimination)
1592             {
1593               obstack_free (&reload_obstack, reload_insn_firstobj);
1594               PATTERN (insn) = old_body;
1595               INSN_CODE (insn) = old_code;
1596               REG_NOTES (insn) = old_notes;
1597               something_needs_elimination = 1;
1598             }
1599
1600           something_needs_operands_changed |= operands_changed;
1601
1602           if (n_reloads != 0)
1603             {
1604               copy_reloads (chain);
1605               *pprev_reload = chain;
1606               pprev_reload = &chain->next_need_reload;
1607             }
1608         }
1609     }
1610   *pprev_reload = 0;
1611 }
1612 \f
1613 /* This function is called from the register allocator to set up estimates
1614    for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1615    an invariant.  The structure is similar to calculate_needs_all_insns.  */
1616
1617 void
1618 calculate_elim_costs_all_insns (void)
1619 {
1620   int *reg_equiv_init_cost;
1621   basic_block bb;
1622   int i;
1623
1624   reg_equiv_init_cost = XCNEWVEC (int, max_regno);
1625   init_elim_table ();
1626   init_eliminable_invariants (get_insns (), false);
1627
1628   set_initial_elim_offsets ();
1629   set_initial_label_offsets ();
1630
1631   FOR_EACH_BB_FN (bb, cfun)
1632     {
1633       rtx_insn *insn;
1634       elim_bb = bb;
1635
1636       FOR_BB_INSNS (bb, insn)
1637         {
1638           /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1639              include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1640              what effects this has on the known offsets at labels.  */
1641
1642           if (LABEL_P (insn) || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
1643               || (INSN_P (insn) && REG_NOTES (insn) != 0))
1644             set_label_offsets (insn, insn, 0);
1645
1646           if (INSN_P (insn))
1647             {
1648               rtx set = single_set (insn);
1649
1650               /* Skip insns that only set an equivalence.  */
1651               if (set && REG_P (SET_DEST (set))
1652                   && reg_renumber[REGNO (SET_DEST (set))] < 0
1653                   && (reg_equiv_constant (REGNO (SET_DEST (set)))
1654                       || reg_equiv_invariant (REGNO (SET_DEST (set)))))
1655                 {
1656                   unsigned regno = REGNO (SET_DEST (set));
1657                   rtx init = reg_equiv_init (regno);
1658                   if (init)
1659                     {
1660                       rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn,
1661                                                 false, true);
1662                       int cost = set_src_cost (t, optimize_bb_for_speed_p (bb));
1663                       int freq = REG_FREQ_FROM_BB (bb);
1664
1665                       reg_equiv_init_cost[regno] = cost * freq;
1666                       continue;
1667                     }
1668                 }
1669               /* If needed, eliminate any eliminable registers.  */
1670               if (num_eliminable || num_eliminable_invariants)
1671                 elimination_costs_in_insn (insn);
1672
1673               if (num_eliminable)
1674                 update_eliminable_offsets ();
1675             }
1676         }
1677     }
1678   for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1679     {
1680       if (reg_equiv_invariant (i))
1681         {
1682           if (reg_equiv_init (i))
1683             {
1684               int cost = reg_equiv_init_cost[i];
1685               if (dump_file)
1686                 fprintf (dump_file,
1687                          "Reg %d has equivalence, initial gains %d\n", i, cost);
1688               if (cost != 0)
1689                 ira_adjust_equiv_reg_cost (i, cost);
1690             }
1691           else
1692             {
1693               if (dump_file)
1694                 fprintf (dump_file,
1695                          "Reg %d had equivalence, but can't be eliminated\n",
1696                          i);
1697               ira_adjust_equiv_reg_cost (i, 0);
1698             }
1699         }
1700     }
1701
1702   free (reg_equiv_init_cost);
1703   free (offsets_known_at);
1704   free (offsets_at);
1705   offsets_at = NULL;
1706   offsets_known_at = NULL;
1707 }
1708 \f
1709 /* Comparison function for qsort to decide which of two reloads
1710    should be handled first.  *P1 and *P2 are the reload numbers.  */
1711
1712 static int
1713 reload_reg_class_lower (const void *r1p, const void *r2p)
1714 {
1715   int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1716   int t;
1717
1718   /* Consider required reloads before optional ones.  */
1719   t = rld[r1].optional - rld[r2].optional;
1720   if (t != 0)
1721     return t;
1722
1723   /* Count all solitary classes before non-solitary ones.  */
1724   t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1725        - (reg_class_size[(int) rld[r1].rclass] == 1));
1726   if (t != 0)
1727     return t;
1728
1729   /* Aside from solitaires, consider all multi-reg groups first.  */
1730   t = rld[r2].nregs - rld[r1].nregs;
1731   if (t != 0)
1732     return t;
1733
1734   /* Consider reloads in order of increasing reg-class number.  */
1735   t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1736   if (t != 0)
1737     return t;
1738
1739   /* If reloads are equally urgent, sort by reload number,
1740      so that the results of qsort leave nothing to chance.  */
1741   return r1 - r2;
1742 }
1743 \f
1744 /* The cost of spilling each hard reg.  */
1745 static int spill_cost[FIRST_PSEUDO_REGISTER];
1746
1747 /* When spilling multiple hard registers, we use SPILL_COST for the first
1748    spilled hard reg and SPILL_ADD_COST for subsequent regs.  SPILL_ADD_COST
1749    only the first hard reg for a multi-reg pseudo.  */
1750 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1751
1752 /* Map of hard regno to pseudo regno currently occupying the hard
1753    reg.  */
1754 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1755
1756 /* Update the spill cost arrays, considering that pseudo REG is live.  */
1757
1758 static void
1759 count_pseudo (int reg)
1760 {
1761   int freq = REG_FREQ (reg);
1762   int r = reg_renumber[reg];
1763   int nregs;
1764
1765   /* Ignore spilled pseudo-registers which can be here only if IRA is used.  */
1766   if (ira_conflicts_p && r < 0)
1767     return;
1768
1769   if (REGNO_REG_SET_P (&pseudos_counted, reg)
1770       || REGNO_REG_SET_P (&spilled_pseudos, reg))
1771     return;
1772
1773   SET_REGNO_REG_SET (&pseudos_counted, reg);
1774
1775   gcc_assert (r >= 0);
1776
1777   spill_add_cost[r] += freq;
1778   nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1779   while (nregs-- > 0)
1780     {
1781       hard_regno_to_pseudo_regno[r + nregs] = reg;
1782       spill_cost[r + nregs] += freq;
1783     }
1784 }
1785
1786 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1787    contents of BAD_SPILL_REGS for the insn described by CHAIN.  */
1788
1789 static void
1790 order_regs_for_reload (struct insn_chain *chain)
1791 {
1792   unsigned i;
1793   HARD_REG_SET used_by_pseudos;
1794   HARD_REG_SET used_by_pseudos2;
1795   reg_set_iterator rsi;
1796
1797   COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1798
1799   memset (spill_cost, 0, sizeof spill_cost);
1800   memset (spill_add_cost, 0, sizeof spill_add_cost);
1801   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1802     hard_regno_to_pseudo_regno[i] = -1;
1803
1804   /* Count number of uses of each hard reg by pseudo regs allocated to it
1805      and then order them by decreasing use.  First exclude hard registers
1806      that are live in or across this insn.  */
1807
1808   REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1809   REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1810   IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1811   IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1812
1813   /* Now find out which pseudos are allocated to it, and update
1814      hard_reg_n_uses.  */
1815   CLEAR_REG_SET (&pseudos_counted);
1816
1817   EXECUTE_IF_SET_IN_REG_SET
1818     (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1819     {
1820       count_pseudo (i);
1821     }
1822   EXECUTE_IF_SET_IN_REG_SET
1823     (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1824     {
1825       count_pseudo (i);
1826     }
1827   CLEAR_REG_SET (&pseudos_counted);
1828 }
1829 \f
1830 /* Vector of reload-numbers showing the order in which the reloads should
1831    be processed.  */
1832 static short reload_order[MAX_RELOADS];
1833
1834 /* This is used to keep track of the spill regs used in one insn.  */
1835 static HARD_REG_SET used_spill_regs_local;
1836
1837 /* We decided to spill hard register SPILLED, which has a size of
1838    SPILLED_NREGS.  Determine how pseudo REG, which is live during the insn,
1839    is affected.  We will add it to SPILLED_PSEUDOS if necessary, and we will
1840    update SPILL_COST/SPILL_ADD_COST.  */
1841
1842 static void
1843 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1844 {
1845   int freq = REG_FREQ (reg);
1846   int r = reg_renumber[reg];
1847   int nregs;
1848
1849   /* Ignore spilled pseudo-registers which can be here only if IRA is used.  */
1850   if (ira_conflicts_p && r < 0)
1851     return;
1852
1853   gcc_assert (r >= 0);
1854
1855   nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1856
1857   if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1858       || spilled + spilled_nregs <= r || r + nregs <= spilled)
1859     return;
1860
1861   SET_REGNO_REG_SET (&spilled_pseudos, reg);
1862
1863   spill_add_cost[r] -= freq;
1864   while (nregs-- > 0)
1865     {
1866       hard_regno_to_pseudo_regno[r + nregs] = -1;
1867       spill_cost[r + nregs] -= freq;
1868     }
1869 }
1870
1871 /* Find reload register to use for reload number ORDER.  */
1872
1873 static int
1874 find_reg (struct insn_chain *chain, int order)
1875 {
1876   int rnum = reload_order[order];
1877   struct reload *rl = rld + rnum;
1878   int best_cost = INT_MAX;
1879   int best_reg = -1;
1880   unsigned int i, j, n;
1881   int k;
1882   HARD_REG_SET not_usable;
1883   HARD_REG_SET used_by_other_reload;
1884   reg_set_iterator rsi;
1885   static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1886   static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1887
1888   COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1889   IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1890   IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1891
1892   CLEAR_HARD_REG_SET (used_by_other_reload);
1893   for (k = 0; k < order; k++)
1894     {
1895       int other = reload_order[k];
1896
1897       if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1898         for (j = 0; j < rld[other].nregs; j++)
1899           SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1900     }
1901
1902   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1903     {
1904 #ifdef REG_ALLOC_ORDER
1905       unsigned int regno = reg_alloc_order[i];
1906 #else
1907       unsigned int regno = i;
1908 #endif
1909
1910       if (! TEST_HARD_REG_BIT (not_usable, regno)
1911           && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1912           && HARD_REGNO_MODE_OK (regno, rl->mode))
1913         {
1914           int this_cost = spill_cost[regno];
1915           int ok = 1;
1916           unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1917
1918           for (j = 1; j < this_nregs; j++)
1919             {
1920               this_cost += spill_add_cost[regno + j];
1921               if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1922                   || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1923                 ok = 0;
1924             }
1925           if (! ok)
1926             continue;
1927
1928           if (ira_conflicts_p)
1929             {
1930               /* Ask IRA to find a better pseudo-register for
1931                  spilling.  */
1932               for (n = j = 0; j < this_nregs; j++)
1933                 {
1934                   int r = hard_regno_to_pseudo_regno[regno + j];
1935
1936                   if (r < 0)
1937                     continue;
1938                   if (n == 0 || regno_pseudo_regs[n - 1] != r)
1939                     regno_pseudo_regs[n++] = r;
1940                 }
1941               regno_pseudo_regs[n++] = -1;
1942               if (best_reg < 0
1943                   || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1944                                                       best_regno_pseudo_regs,
1945                                                       rl->in, rl->out,
1946                                                       chain->insn))
1947                 {
1948                   best_reg = regno;
1949                   for (j = 0;; j++)
1950                     {
1951                       best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1952                       if (regno_pseudo_regs[j] < 0)
1953                         break;
1954                     }
1955                 }
1956               continue;
1957             }
1958
1959           if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1960             this_cost--;
1961           if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1962             this_cost--;
1963           if (this_cost < best_cost
1964               /* Among registers with equal cost, prefer caller-saved ones, or
1965                  use REG_ALLOC_ORDER if it is defined.  */
1966               || (this_cost == best_cost
1967 #ifdef REG_ALLOC_ORDER
1968                   && (inv_reg_alloc_order[regno]
1969                       < inv_reg_alloc_order[best_reg])
1970 #else
1971                   && call_used_regs[regno]
1972                   && ! call_used_regs[best_reg]
1973 #endif
1974                   ))
1975             {
1976               best_reg = regno;
1977               best_cost = this_cost;
1978             }
1979         }
1980     }
1981   if (best_reg == -1)
1982     return 0;
1983
1984   if (dump_file)
1985     fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1986
1987   rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1988   rl->regno = best_reg;
1989
1990   EXECUTE_IF_SET_IN_REG_SET
1991     (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1992     {
1993       count_spilled_pseudo (best_reg, rl->nregs, j);
1994     }
1995
1996   EXECUTE_IF_SET_IN_REG_SET
1997     (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1998     {
1999       count_spilled_pseudo (best_reg, rl->nregs, j);
2000     }
2001
2002   for (i = 0; i < rl->nregs; i++)
2003     {
2004       gcc_assert (spill_cost[best_reg + i] == 0);
2005       gcc_assert (spill_add_cost[best_reg + i] == 0);
2006       gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
2007       SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
2008     }
2009   return 1;
2010 }
2011
2012 /* Find more reload regs to satisfy the remaining need of an insn, which
2013    is given by CHAIN.
2014    Do it by ascending class number, since otherwise a reg
2015    might be spilled for a big class and might fail to count
2016    for a smaller class even though it belongs to that class.  */
2017
2018 static void
2019 find_reload_regs (struct insn_chain *chain)
2020 {
2021   int i;
2022
2023   /* In order to be certain of getting the registers we need,
2024      we must sort the reloads into order of increasing register class.
2025      Then our grabbing of reload registers will parallel the process
2026      that provided the reload registers.  */
2027   for (i = 0; i < chain->n_reloads; i++)
2028     {
2029       /* Show whether this reload already has a hard reg.  */
2030       if (chain->rld[i].reg_rtx)
2031         {
2032           int regno = REGNO (chain->rld[i].reg_rtx);
2033           chain->rld[i].regno = regno;
2034           chain->rld[i].nregs
2035             = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
2036         }
2037       else
2038         chain->rld[i].regno = -1;
2039       reload_order[i] = i;
2040     }
2041
2042   n_reloads = chain->n_reloads;
2043   memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
2044
2045   CLEAR_HARD_REG_SET (used_spill_regs_local);
2046
2047   if (dump_file)
2048     fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2049
2050   qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2051
2052   /* Compute the order of preference for hard registers to spill.  */
2053
2054   order_regs_for_reload (chain);
2055
2056   for (i = 0; i < n_reloads; i++)
2057     {
2058       int r = reload_order[i];
2059
2060       /* Ignore reloads that got marked inoperative.  */
2061       if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2062           && ! rld[r].optional
2063           && rld[r].regno == -1)
2064         if (! find_reg (chain, i))
2065           {
2066             if (dump_file)
2067               fprintf (dump_file, "reload failure for reload %d\n", r);
2068             spill_failure (chain->insn, rld[r].rclass);
2069             failure = 1;
2070             return;
2071           }
2072     }
2073
2074   COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2075   IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2076
2077   memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2078 }
2079
2080 static void
2081 select_reload_regs (void)
2082 {
2083   struct insn_chain *chain;
2084
2085   /* Try to satisfy the needs for each insn.  */
2086   for (chain = insns_need_reload; chain != 0;
2087        chain = chain->next_need_reload)
2088     find_reload_regs (chain);
2089 }
2090 \f
2091 /* Delete all insns that were inserted by emit_caller_save_insns during
2092    this iteration.  */
2093 static void
2094 delete_caller_save_insns (void)
2095 {
2096   struct insn_chain *c = reload_insn_chain;
2097
2098   while (c != 0)
2099     {
2100       while (c != 0 && c->is_caller_save_insn)
2101         {
2102           struct insn_chain *next = c->next;
2103           rtx_insn *insn = c->insn;
2104
2105           if (c == reload_insn_chain)
2106             reload_insn_chain = next;
2107           delete_insn (insn);
2108
2109           if (next)
2110             next->prev = c->prev;
2111           if (c->prev)
2112             c->prev->next = next;
2113           c->next = unused_insn_chains;
2114           unused_insn_chains = c;
2115           c = next;
2116         }
2117       if (c != 0)
2118         c = c->next;
2119     }
2120 }
2121 \f
2122 /* Handle the failure to find a register to spill.
2123    INSN should be one of the insns which needed this particular spill reg.  */
2124
2125 static void
2126 spill_failure (rtx_insn *insn, enum reg_class rclass)
2127 {
2128   if (asm_noperands (PATTERN (insn)) >= 0)
2129     error_for_asm (insn, "can%'t find a register in class %qs while "
2130                    "reloading %<asm%>",
2131                    reg_class_names[rclass]);
2132   else
2133     {
2134       error ("unable to find a register to spill in class %qs",
2135              reg_class_names[rclass]);
2136
2137       if (dump_file)
2138         {
2139           fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2140           debug_reload_to_stream (dump_file);
2141         }
2142       fatal_insn ("this is the insn:", insn);
2143     }
2144 }
2145 \f
2146 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2147    data that is dead in INSN.  */
2148
2149 static void
2150 delete_dead_insn (rtx_insn *insn)
2151 {
2152   rtx_insn *prev = prev_active_insn (insn);
2153   rtx prev_dest;
2154
2155   /* If the previous insn sets a register that dies in our insn make
2156      a note that we want to run DCE immediately after reload.
2157
2158      We used to delete the previous insn & recurse, but that's wrong for
2159      block local equivalences.  Instead of trying to figure out the exact
2160      circumstances where we can delete the potentially dead insns, just
2161      let DCE do the job.  */
2162   if (prev && BLOCK_FOR_INSN (prev) == BLOCK_FOR_INSN (insn)
2163       && GET_CODE (PATTERN (prev)) == SET
2164       && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2165       && reg_mentioned_p (prev_dest, PATTERN (insn))
2166       && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2167       && ! side_effects_p (SET_SRC (PATTERN (prev))))
2168     need_dce = 1;
2169
2170   SET_INSN_DELETED (insn);
2171 }
2172
2173 /* Modify the home of pseudo-reg I.
2174    The new home is present in reg_renumber[I].
2175
2176    FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2177    or it may be -1, meaning there is none or it is not relevant.
2178    This is used so that all pseudos spilled from a given hard reg
2179    can share one stack slot.  */
2180
2181 static void
2182 alter_reg (int i, int from_reg, bool dont_share_p)
2183 {
2184   /* When outputting an inline function, this can happen
2185      for a reg that isn't actually used.  */
2186   if (regno_reg_rtx[i] == 0)
2187     return;
2188
2189   /* If the reg got changed to a MEM at rtl-generation time,
2190      ignore it.  */
2191   if (!REG_P (regno_reg_rtx[i]))
2192     return;
2193
2194   /* Modify the reg-rtx to contain the new hard reg
2195      number or else to contain its pseudo reg number.  */
2196   SET_REGNO (regno_reg_rtx[i],
2197              reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2198
2199   /* If we have a pseudo that is needed but has no hard reg or equivalent,
2200      allocate a stack slot for it.  */
2201
2202   if (reg_renumber[i] < 0
2203       && REG_N_REFS (i) > 0
2204       && reg_equiv_constant (i) == 0
2205       && (reg_equiv_invariant (i) == 0
2206           || reg_equiv_init (i) == 0)
2207       && reg_equiv_memory_loc (i) == 0)
2208     {
2209       rtx x = NULL_RTX;
2210       machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2211       unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2212       unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2213       unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2214       unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2215       int adjust = 0;
2216
2217       something_was_spilled = true;
2218
2219       if (ira_conflicts_p)
2220         {
2221           /* Mark the spill for IRA.  */
2222           SET_REGNO_REG_SET (&spilled_pseudos, i);
2223           if (!dont_share_p)
2224             x = ira_reuse_stack_slot (i, inherent_size, total_size);
2225         }
2226
2227       if (x)
2228         ;
2229
2230       /* Each pseudo reg has an inherent size which comes from its own mode,
2231          and a total size which provides room for paradoxical subregs
2232          which refer to the pseudo reg in wider modes.
2233
2234          We can use a slot already allocated if it provides both
2235          enough inherent space and enough total space.
2236          Otherwise, we allocate a new slot, making sure that it has no less
2237          inherent space, and no less total space, then the previous slot.  */
2238       else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2239         {
2240           rtx stack_slot;
2241
2242           /* No known place to spill from => no slot to reuse.  */
2243           x = assign_stack_local (mode, total_size,
2244                                   min_align > inherent_align
2245                                   || total_size > inherent_size ? -1 : 0);
2246
2247           stack_slot = x;
2248
2249           /* Cancel the big-endian correction done in assign_stack_local.
2250              Get the address of the beginning of the slot.  This is so we
2251              can do a big-endian correction unconditionally below.  */
2252           if (BYTES_BIG_ENDIAN)
2253             {
2254               adjust = inherent_size - total_size;
2255               if (adjust)
2256                 stack_slot
2257                   = adjust_address_nv (x, mode_for_size (total_size
2258                                                          * BITS_PER_UNIT,
2259                                                          MODE_INT, 1),
2260                                        adjust);
2261             }
2262
2263           if (! dont_share_p && ira_conflicts_p)
2264             /* Inform IRA about allocation a new stack slot.  */
2265             ira_mark_new_stack_slot (stack_slot, i, total_size);
2266         }
2267
2268       /* Reuse a stack slot if possible.  */
2269       else if (spill_stack_slot[from_reg] != 0
2270                && spill_stack_slot_width[from_reg] >= total_size
2271                && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2272                    >= inherent_size)
2273                && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2274         x = spill_stack_slot[from_reg];
2275
2276       /* Allocate a bigger slot.  */
2277       else
2278         {
2279           /* Compute maximum size needed, both for inherent size
2280              and for total size.  */
2281           rtx stack_slot;
2282
2283           if (spill_stack_slot[from_reg])
2284             {
2285               if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2286                   > inherent_size)
2287                 mode = GET_MODE (spill_stack_slot[from_reg]);
2288               if (spill_stack_slot_width[from_reg] > total_size)
2289                 total_size = spill_stack_slot_width[from_reg];
2290               if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2291                 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2292             }
2293
2294           /* Make a slot with that size.  */
2295           x = assign_stack_local (mode, total_size,
2296                                   min_align > inherent_align
2297                                   || total_size > inherent_size ? -1 : 0);
2298           stack_slot = x;
2299
2300           /* Cancel the  big-endian correction done in assign_stack_local.
2301              Get the address of the beginning of the slot.  This is so we
2302              can do a big-endian correction unconditionally below.  */
2303           if (BYTES_BIG_ENDIAN)
2304             {
2305               adjust = GET_MODE_SIZE (mode) - total_size;
2306               if (adjust)
2307                 stack_slot
2308                   = adjust_address_nv (x, mode_for_size (total_size
2309                                                          * BITS_PER_UNIT,
2310                                                          MODE_INT, 1),
2311                                        adjust);
2312             }
2313
2314           spill_stack_slot[from_reg] = stack_slot;
2315           spill_stack_slot_width[from_reg] = total_size;
2316         }
2317
2318       /* On a big endian machine, the "address" of the slot
2319          is the address of the low part that fits its inherent mode.  */
2320       if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2321         adjust += (total_size - inherent_size);
2322
2323       /* If we have any adjustment to make, or if the stack slot is the
2324          wrong mode, make a new stack slot.  */
2325       x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2326
2327       /* Set all of the memory attributes as appropriate for a spill.  */
2328       set_mem_attrs_for_spill (x);
2329
2330       /* Save the stack slot for later.  */
2331       reg_equiv_memory_loc (i) = x;
2332     }
2333 }
2334
2335 /* Mark the slots in regs_ever_live for the hard regs used by
2336    pseudo-reg number REGNO, accessed in MODE.  */
2337
2338 static void
2339 mark_home_live_1 (int regno, machine_mode mode)
2340 {
2341   int i, lim;
2342
2343   i = reg_renumber[regno];
2344   if (i < 0)
2345     return;
2346   lim = end_hard_regno (mode, i);
2347   while (i < lim)
2348     df_set_regs_ever_live (i++, true);
2349 }
2350
2351 /* Mark the slots in regs_ever_live for the hard regs
2352    used by pseudo-reg number REGNO.  */
2353
2354 void
2355 mark_home_live (int regno)
2356 {
2357   if (reg_renumber[regno] >= 0)
2358     mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2359 }
2360 \f
2361 /* This function handles the tracking of elimination offsets around branches.
2362
2363    X is a piece of RTL being scanned.
2364
2365    INSN is the insn that it came from, if any.
2366
2367    INITIAL_P is nonzero if we are to set the offset to be the initial
2368    offset and zero if we are setting the offset of the label to be the
2369    current offset.  */
2370
2371 static void
2372 set_label_offsets (rtx x, rtx_insn *insn, int initial_p)
2373 {
2374   enum rtx_code code = GET_CODE (x);
2375   rtx tem;
2376   unsigned int i;
2377   struct elim_table *p;
2378
2379   switch (code)
2380     {
2381     case LABEL_REF:
2382       if (LABEL_REF_NONLOCAL_P (x))
2383         return;
2384
2385       x = LABEL_REF_LABEL (x);
2386
2387       /* ... fall through ...  */
2388
2389     case CODE_LABEL:
2390       /* If we know nothing about this label, set the desired offsets.  Note
2391          that this sets the offset at a label to be the offset before a label
2392          if we don't know anything about the label.  This is not correct for
2393          the label after a BARRIER, but is the best guess we can make.  If
2394          we guessed wrong, we will suppress an elimination that might have
2395          been possible had we been able to guess correctly.  */
2396
2397       if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2398         {
2399           for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2400             offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2401               = (initial_p ? reg_eliminate[i].initial_offset
2402                  : reg_eliminate[i].offset);
2403           offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2404         }
2405
2406       /* Otherwise, if this is the definition of a label and it is
2407          preceded by a BARRIER, set our offsets to the known offset of
2408          that label.  */
2409
2410       else if (x == insn
2411                && (tem = prev_nonnote_insn (insn)) != 0
2412                && BARRIER_P (tem))
2413         set_offsets_for_label (insn);
2414       else
2415         /* If neither of the above cases is true, compare each offset
2416            with those previously recorded and suppress any eliminations
2417            where the offsets disagree.  */
2418
2419         for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2420           if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2421               != (initial_p ? reg_eliminate[i].initial_offset
2422                   : reg_eliminate[i].offset))
2423             reg_eliminate[i].can_eliminate = 0;
2424
2425       return;
2426
2427     case JUMP_TABLE_DATA:
2428       set_label_offsets (PATTERN (insn), insn, initial_p);
2429       return;
2430
2431     case JUMP_INSN:
2432       set_label_offsets (PATTERN (insn), insn, initial_p);
2433
2434       /* ... fall through ...  */
2435
2436     case INSN:
2437     case CALL_INSN:
2438       /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2439          to indirectly and hence must have all eliminations at their
2440          initial offsets.  */
2441       for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2442         if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2443           set_label_offsets (XEXP (tem, 0), insn, 1);
2444       return;
2445
2446     case PARALLEL:
2447     case ADDR_VEC:
2448     case ADDR_DIFF_VEC:
2449       /* Each of the labels in the parallel or address vector must be
2450          at their initial offsets.  We want the first field for PARALLEL
2451          and ADDR_VEC and the second field for ADDR_DIFF_VEC.  */
2452
2453       for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2454         set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2455                            insn, initial_p);
2456       return;
2457
2458     case SET:
2459       /* We only care about setting PC.  If the source is not RETURN,
2460          IF_THEN_ELSE, or a label, disable any eliminations not at
2461          their initial offsets.  Similarly if any arm of the IF_THEN_ELSE
2462          isn't one of those possibilities.  For branches to a label,
2463          call ourselves recursively.
2464
2465          Note that this can disable elimination unnecessarily when we have
2466          a non-local goto since it will look like a non-constant jump to
2467          someplace in the current function.  This isn't a significant
2468          problem since such jumps will normally be when all elimination
2469          pairs are back to their initial offsets.  */
2470
2471       if (SET_DEST (x) != pc_rtx)
2472         return;
2473
2474       switch (GET_CODE (SET_SRC (x)))
2475         {
2476         case PC:
2477         case RETURN:
2478           return;
2479
2480         case LABEL_REF:
2481           set_label_offsets (SET_SRC (x), insn, initial_p);
2482           return;
2483
2484         case IF_THEN_ELSE:
2485           tem = XEXP (SET_SRC (x), 1);
2486           if (GET_CODE (tem) == LABEL_REF)
2487             set_label_offsets (LABEL_REF_LABEL (tem), insn, initial_p);
2488           else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2489             break;
2490
2491           tem = XEXP (SET_SRC (x), 2);
2492           if (GET_CODE (tem) == LABEL_REF)
2493             set_label_offsets (LABEL_REF_LABEL (tem), insn, initial_p);
2494           else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2495             break;
2496           return;
2497
2498         default:
2499           break;
2500         }
2501
2502       /* If we reach here, all eliminations must be at their initial
2503          offset because we are doing a jump to a variable address.  */
2504       for (p = reg_eliminate; p < &reg_eliminate[NUM_ELIMINABLE_REGS]; p++)
2505         if (p->offset != p->initial_offset)
2506           p->can_eliminate = 0;
2507       break;
2508
2509     default:
2510       break;
2511     }
2512 }
2513 \f
2514 /* This function examines every reg that occurs in X and adjusts the
2515    costs for its elimination which are gathered by IRA.  INSN is the
2516    insn in which X occurs.  We do not recurse into MEM expressions.  */
2517
2518 static void
2519 note_reg_elim_costly (const_rtx x, rtx insn)
2520 {
2521   subrtx_iterator::array_type array;
2522   FOR_EACH_SUBRTX (iter, array, x, NONCONST)
2523     {
2524       const_rtx x = *iter;
2525       if (MEM_P (x))
2526         iter.skip_subrtxes ();
2527       else if (REG_P (x)
2528                && REGNO (x) >= FIRST_PSEUDO_REGISTER
2529                && reg_equiv_init (REGNO (x))
2530                && reg_equiv_invariant (REGNO (x)))
2531         {
2532           rtx t = reg_equiv_invariant (REGNO (x));
2533           rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true);
2534           int cost = set_src_cost (new_rtx, optimize_bb_for_speed_p (elim_bb));
2535           int freq = REG_FREQ_FROM_BB (elim_bb);
2536
2537           if (cost != 0)
2538             ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq);
2539         }
2540     }
2541 }
2542
2543 /* Scan X and replace any eliminable registers (such as fp) with a
2544    replacement (such as sp), plus an offset.
2545
2546    MEM_MODE is the mode of an enclosing MEM.  We need this to know how
2547    much to adjust a register for, e.g., PRE_DEC.  Also, if we are inside a
2548    MEM, we are allowed to replace a sum of a register and the constant zero
2549    with the register, which we cannot do outside a MEM.  In addition, we need
2550    to record the fact that a register is referenced outside a MEM.
2551
2552    If INSN is an insn, it is the insn containing X.  If we replace a REG
2553    in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2554    CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2555    the REG is being modified.
2556
2557    Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2558    That's used when we eliminate in expressions stored in notes.
2559    This means, do not set ref_outside_mem even if the reference
2560    is outside of MEMs.
2561
2562    If FOR_COSTS is true, we are being called before reload in order to
2563    estimate the costs of keeping registers with an equivalence unallocated.
2564
2565    REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2566    replacements done assuming all offsets are at their initial values.  If
2567    they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2568    encounter, return the actual location so that find_reloads will do
2569    the proper thing.  */
2570
2571 static rtx
2572 eliminate_regs_1 (rtx x, machine_mode mem_mode, rtx insn,
2573                   bool may_use_invariant, bool for_costs)
2574 {
2575   enum rtx_code code = GET_CODE (x);
2576   struct elim_table *ep;
2577   int regno;
2578   rtx new_rtx;
2579   int i, j;
2580   const char *fmt;
2581   int copied = 0;
2582
2583   if (! current_function_decl)
2584     return x;
2585
2586   switch (code)
2587     {
2588     CASE_CONST_ANY:
2589     case CONST:
2590     case SYMBOL_REF:
2591     case CODE_LABEL:
2592     case PC:
2593     case CC0:
2594     case ASM_INPUT:
2595     case ADDR_VEC:
2596     case ADDR_DIFF_VEC:
2597     case RETURN:
2598       return x;
2599
2600     case REG:
2601       regno = REGNO (x);
2602
2603       /* First handle the case where we encounter a bare register that
2604          is eliminable.  Replace it with a PLUS.  */
2605       if (regno < FIRST_PSEUDO_REGISTER)
2606         {
2607           for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
2608                ep++)
2609             if (ep->from_rtx == x && ep->can_eliminate)
2610               return plus_constant (Pmode, ep->to_rtx, ep->previous_offset);
2611
2612         }
2613       else if (reg_renumber && reg_renumber[regno] < 0
2614                && reg_equivs
2615                && reg_equiv_invariant (regno))
2616         {
2617           if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2618             return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno)),
2619                                      mem_mode, insn, true, for_costs);
2620           /* There exists at least one use of REGNO that cannot be
2621              eliminated.  Prevent the defining insn from being deleted.  */
2622           reg_equiv_init (regno) = NULL;
2623           if (!for_costs)
2624             alter_reg (regno, -1, true);
2625         }
2626       return x;
2627
2628     /* You might think handling MINUS in a manner similar to PLUS is a
2629        good idea.  It is not.  It has been tried multiple times and every
2630        time the change has had to have been reverted.
2631
2632        Other parts of reload know a PLUS is special (gen_reload for example)
2633        and require special code to handle code a reloaded PLUS operand.
2634
2635        Also consider backends where the flags register is clobbered by a
2636        MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2637        lea instruction comes to mind).  If we try to reload a MINUS, we
2638        may kill the flags register that was holding a useful value.
2639
2640        So, please before trying to handle MINUS, consider reload as a
2641        whole instead of this little section as well as the backend issues.  */
2642     case PLUS:
2643       /* If this is the sum of an eliminable register and a constant, rework
2644          the sum.  */
2645       if (REG_P (XEXP (x, 0))
2646           && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2647           && CONSTANT_P (XEXP (x, 1)))
2648         {
2649           for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
2650                ep++)
2651             if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2652               {
2653                 /* The only time we want to replace a PLUS with a REG (this
2654                    occurs when the constant operand of the PLUS is the negative
2655                    of the offset) is when we are inside a MEM.  We won't want
2656                    to do so at other times because that would change the
2657                    structure of the insn in a way that reload can't handle.
2658                    We special-case the commonest situation in
2659                    eliminate_regs_in_insn, so just replace a PLUS with a
2660                    PLUS here, unless inside a MEM.  */
2661                 if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2662                     && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2663                   return ep->to_rtx;
2664                 else
2665                   return gen_rtx_PLUS (Pmode, ep->to_rtx,
2666                                        plus_constant (Pmode, XEXP (x, 1),
2667                                                       ep->previous_offset));
2668               }
2669
2670           /* If the register is not eliminable, we are done since the other
2671              operand is a constant.  */
2672           return x;
2673         }
2674
2675       /* If this is part of an address, we want to bring any constant to the
2676          outermost PLUS.  We will do this by doing register replacement in
2677          our operands and seeing if a constant shows up in one of them.
2678
2679          Note that there is no risk of modifying the structure of the insn,
2680          since we only get called for its operands, thus we are either
2681          modifying the address inside a MEM, or something like an address
2682          operand of a load-address insn.  */
2683
2684       {
2685         rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2686                                      for_costs);
2687         rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2688                                      for_costs);
2689
2690         if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2691           {
2692             /* If one side is a PLUS and the other side is a pseudo that
2693                didn't get a hard register but has a reg_equiv_constant,
2694                we must replace the constant here since it may no longer
2695                be in the position of any operand.  */
2696             if (GET_CODE (new0) == PLUS && REG_P (new1)
2697                 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2698                 && reg_renumber[REGNO (new1)] < 0
2699                 && reg_equivs
2700                 && reg_equiv_constant (REGNO (new1)) != 0)
2701               new1 = reg_equiv_constant (REGNO (new1));
2702             else if (GET_CODE (new1) == PLUS && REG_P (new0)
2703                      && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2704                      && reg_renumber[REGNO (new0)] < 0
2705                      && reg_equiv_constant (REGNO (new0)) != 0)
2706               new0 = reg_equiv_constant (REGNO (new0));
2707
2708             new_rtx = form_sum (GET_MODE (x), new0, new1);
2709
2710             /* As above, if we are not inside a MEM we do not want to
2711                turn a PLUS into something else.  We might try to do so here
2712                for an addition of 0 if we aren't optimizing.  */
2713             if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2714               return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2715             else
2716               return new_rtx;
2717           }
2718       }
2719       return x;
2720
2721     case MULT:
2722       /* If this is the product of an eliminable register and a
2723          constant, apply the distribute law and move the constant out
2724          so that we have (plus (mult ..) ..).  This is needed in order
2725          to keep load-address insns valid.   This case is pathological.
2726          We ignore the possibility of overflow here.  */
2727       if (REG_P (XEXP (x, 0))
2728           && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2729           && CONST_INT_P (XEXP (x, 1)))
2730         for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
2731              ep++)
2732           if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2733             {
2734               if (! mem_mode
2735                   /* Refs inside notes or in DEBUG_INSNs don't count for
2736                      this purpose.  */
2737                   && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2738                                       || GET_CODE (insn) == INSN_LIST
2739                                       || DEBUG_INSN_P (insn))))
2740                 ep->ref_outside_mem = 1;
2741
2742               return
2743                 plus_constant (Pmode,
2744                                gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2745                                ep->previous_offset * INTVAL (XEXP (x, 1)));
2746             }
2747
2748       /* ... fall through ...  */
2749
2750     case CALL:
2751     case COMPARE:
2752     /* See comments before PLUS about handling MINUS.  */
2753     case MINUS:
2754     case DIV:      case UDIV:
2755     case MOD:      case UMOD:
2756     case AND:      case IOR:      case XOR:
2757     case ROTATERT: case ROTATE:
2758     case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2759     case NE:       case EQ:
2760     case GE:       case GT:       case GEU:    case GTU:
2761     case LE:       case LT:       case LEU:    case LTU:
2762       {
2763         rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2764                                      for_costs);
2765         rtx new1 = XEXP (x, 1)
2766           ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false,
2767                               for_costs) : 0;
2768
2769         if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2770           return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2771       }
2772       return x;
2773
2774     case EXPR_LIST:
2775       /* If we have something in XEXP (x, 0), the usual case, eliminate it.  */
2776       if (XEXP (x, 0))
2777         {
2778           new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2779                                       for_costs);
2780           if (new_rtx != XEXP (x, 0))
2781             {
2782               /* If this is a REG_DEAD note, it is not valid anymore.
2783                  Using the eliminated version could result in creating a
2784                  REG_DEAD note for the stack or frame pointer.  */
2785               if (REG_NOTE_KIND (x) == REG_DEAD)
2786                 return (XEXP (x, 1)
2787                         ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2788                                             for_costs)
2789                         : NULL_RTX);
2790
2791               x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2792             }
2793         }
2794
2795       /* ... fall through ...  */
2796
2797     case INSN_LIST:
2798     case INT_LIST:
2799       /* Now do eliminations in the rest of the chain.  If this was
2800          an EXPR_LIST, this might result in allocating more memory than is
2801          strictly needed, but it simplifies the code.  */
2802       if (XEXP (x, 1))
2803         {
2804           new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2805                                       for_costs);
2806           if (new_rtx != XEXP (x, 1))
2807             return
2808               gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2809         }
2810       return x;
2811
2812     case PRE_INC:
2813     case POST_INC:
2814     case PRE_DEC:
2815     case POST_DEC:
2816       /* We do not support elimination of a register that is modified.
2817          elimination_effects has already make sure that this does not
2818          happen.  */
2819       return x;
2820
2821     case PRE_MODIFY:
2822     case POST_MODIFY:
2823       /* We do not support elimination of a register that is modified.
2824          elimination_effects has already make sure that this does not
2825          happen.  The only remaining case we need to consider here is
2826          that the increment value may be an eliminable register.  */
2827       if (GET_CODE (XEXP (x, 1)) == PLUS
2828           && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2829         {
2830           rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2831                                           insn, true, for_costs);
2832
2833           if (new_rtx != XEXP (XEXP (x, 1), 1))
2834             return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2835                                    gen_rtx_PLUS (GET_MODE (x),
2836                                                  XEXP (x, 0), new_rtx));
2837         }
2838       return x;
2839
2840     case STRICT_LOW_PART:
2841     case NEG:          case NOT:
2842     case SIGN_EXTEND:  case ZERO_EXTEND:
2843     case TRUNCATE:     case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2844     case FLOAT:        case FIX:
2845     case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2846     case ABS:
2847     case SQRT:
2848     case FFS:
2849     case CLZ:
2850     case CTZ:
2851     case POPCOUNT:
2852     case PARITY:
2853     case BSWAP:
2854       new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2855                                   for_costs);
2856       if (new_rtx != XEXP (x, 0))
2857         return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2858       return x;
2859
2860     case SUBREG:
2861       /* Similar to above processing, but preserve SUBREG_BYTE.
2862          Convert (subreg (mem)) to (mem) if not paradoxical.
2863          Also, if we have a non-paradoxical (subreg (pseudo)) and the
2864          pseudo didn't get a hard reg, we must replace this with the
2865          eliminated version of the memory location because push_reload
2866          may do the replacement in certain circumstances.  */
2867       if (REG_P (SUBREG_REG (x))
2868           && !paradoxical_subreg_p (x)
2869           && reg_equivs
2870           && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
2871         {
2872           new_rtx = SUBREG_REG (x);
2873         }
2874       else
2875         new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false, for_costs);
2876
2877       if (new_rtx != SUBREG_REG (x))
2878         {
2879           int x_size = GET_MODE_SIZE (GET_MODE (x));
2880           int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2881
2882           if (MEM_P (new_rtx)
2883               && ((x_size < new_size
2884 #ifdef WORD_REGISTER_OPERATIONS
2885                    /* On these machines, combine can create rtl of the form
2886                       (set (subreg:m1 (reg:m2 R) 0) ...)
2887                       where m1 < m2, and expects something interesting to
2888                       happen to the entire word.  Moreover, it will use the
2889                       (reg:m2 R) later, expecting all bits to be preserved.
2890                       So if the number of words is the same, preserve the
2891                       subreg so that push_reload can see it.  */
2892                    && ! ((x_size - 1) / UNITS_PER_WORD
2893                          == (new_size -1 ) / UNITS_PER_WORD)
2894 #endif
2895                    )
2896                   || x_size == new_size)
2897               )
2898             return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2899           else
2900             return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2901         }
2902
2903       return x;
2904
2905     case MEM:
2906       /* Our only special processing is to pass the mode of the MEM to our
2907          recursive call and copy the flags.  While we are here, handle this
2908          case more efficiently.  */
2909
2910       new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true,
2911                                   for_costs);
2912       if (for_costs
2913           && memory_address_p (GET_MODE (x), XEXP (x, 0))
2914           && !memory_address_p (GET_MODE (x), new_rtx))
2915         note_reg_elim_costly (XEXP (x, 0), insn);
2916
2917       return replace_equiv_address_nv (x, new_rtx);
2918
2919     case USE:
2920       /* Handle insn_list USE that a call to a pure function may generate.  */
2921       new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false,
2922                                   for_costs);
2923       if (new_rtx != XEXP (x, 0))
2924         return gen_rtx_USE (GET_MODE (x), new_rtx);
2925       return x;
2926
2927     case CLOBBER:
2928     case ASM_OPERANDS:
2929       gcc_assert (insn && DEBUG_INSN_P (insn));
2930       break;
2931
2932     case SET:
2933       gcc_unreachable ();
2934
2935     default:
2936       break;
2937     }
2938
2939   /* Process each of our operands recursively.  If any have changed, make a
2940      copy of the rtx.  */
2941   fmt = GET_RTX_FORMAT (code);
2942   for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2943     {
2944       if (*fmt == 'e')
2945         {
2946           new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false,
2947                                       for_costs);
2948           if (new_rtx != XEXP (x, i) && ! copied)
2949             {
2950               x = shallow_copy_rtx (x);
2951               copied = 1;
2952             }
2953           XEXP (x, i) = new_rtx;
2954         }
2955       else if (*fmt == 'E')
2956         {
2957           int copied_vec = 0;
2958           for (j = 0; j < XVECLEN (x, i); j++)
2959             {
2960               new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false,
2961                                           for_costs);
2962               if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2963                 {
2964                   rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2965                                              XVEC (x, i)->elem);
2966                   if (! copied)
2967                     {
2968                       x = shallow_copy_rtx (x);
2969                       copied = 1;
2970                     }
2971                   XVEC (x, i) = new_v;
2972                   copied_vec = 1;
2973                 }
2974               XVECEXP (x, i, j) = new_rtx;
2975             }
2976         }
2977     }
2978
2979   return x;
2980 }
2981
2982 rtx
2983 eliminate_regs (rtx x, machine_mode mem_mode, rtx insn)
2984 {
2985   if (reg_eliminate == NULL)
2986     {
2987       gcc_assert (targetm.no_register_allocation);
2988       return x;
2989     }
2990   return eliminate_regs_1 (x, mem_mode, insn, false, false);
2991 }
2992
2993 /* Scan rtx X for modifications of elimination target registers.  Update
2994    the table of eliminables to reflect the changed state.  MEM_MODE is
2995    the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM.  */
2996
2997 static void
2998 elimination_effects (rtx x, machine_mode mem_mode)
2999 {
3000   enum rtx_code code = GET_CODE (x);
3001   struct elim_table *ep;
3002   int regno;
3003   int i, j;
3004   const char *fmt;
3005
3006   switch (code)
3007     {
3008     CASE_CONST_ANY:
3009     case CONST:
3010     case SYMBOL_REF:
3011     case CODE_LABEL:
3012     case PC:
3013     case CC0:
3014     case ASM_INPUT:
3015     case ADDR_VEC:
3016     case ADDR_DIFF_VEC:
3017     case RETURN:
3018       return;
3019
3020     case REG:
3021       regno = REGNO (x);
3022
3023       /* First handle the case where we encounter a bare register that
3024          is eliminable.  Replace it with a PLUS.  */
3025       if (regno < FIRST_PSEUDO_REGISTER)
3026         {
3027           for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
3028                ep++)
3029             if (ep->from_rtx == x && ep->can_eliminate)
3030               {
3031                 if (! mem_mode)
3032                   ep->ref_outside_mem = 1;
3033                 return;
3034               }
3035
3036         }
3037       else if (reg_renumber[regno] < 0
3038                && reg_equivs
3039                && reg_equiv_constant (regno)
3040                && ! function_invariant_p (reg_equiv_constant (regno)))
3041         elimination_effects (reg_equiv_constant (regno), mem_mode);
3042       return;
3043
3044     case PRE_INC:
3045     case POST_INC:
3046     case PRE_DEC:
3047     case POST_DEC:
3048     case POST_MODIFY:
3049     case PRE_MODIFY:
3050       /* If we modify the source of an elimination rule, disable it.  */
3051       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3052         if (ep->from_rtx == XEXP (x, 0))
3053           ep->can_eliminate = 0;
3054
3055       /* If we modify the target of an elimination rule by adding a constant,
3056          update its offset.  If we modify the target in any other way, we'll
3057          have to disable the rule as well.  */
3058       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3059         if (ep->to_rtx == XEXP (x, 0))
3060           {
3061             int size = GET_MODE_SIZE (mem_mode);
3062
3063             /* If more bytes than MEM_MODE are pushed, account for them.  */
3064 #ifdef PUSH_ROUNDING
3065             if (ep->to_rtx == stack_pointer_rtx)
3066               size = PUSH_ROUNDING (size);
3067 #endif
3068             if (code == PRE_DEC || code == POST_DEC)
3069               ep->offset += size;
3070             else if (code == PRE_INC || code == POST_INC)
3071               ep->offset -= size;
3072             else if (code == PRE_MODIFY || code == POST_MODIFY)
3073               {
3074                 if (GET_CODE (XEXP (x, 1)) == PLUS
3075                     && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3076                     && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3077                   ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3078                 else
3079                   ep->can_eliminate = 0;
3080               }
3081           }
3082
3083       /* These two aren't unary operators.  */
3084       if (code == POST_MODIFY || code == PRE_MODIFY)
3085         break;
3086
3087       /* Fall through to generic unary operation case.  */
3088     case STRICT_LOW_PART:
3089     case NEG:          case NOT:
3090     case SIGN_EXTEND:  case ZERO_EXTEND:
3091     case TRUNCATE:     case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3092     case FLOAT:        case FIX:
3093     case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3094     case ABS:
3095     case SQRT:
3096     case FFS:
3097     case CLZ:
3098     case CTZ:
3099     case POPCOUNT:
3100     case PARITY:
3101     case BSWAP:
3102       elimination_effects (XEXP (x, 0), mem_mode);
3103       return;
3104
3105     case SUBREG:
3106       if (REG_P (SUBREG_REG (x))
3107           && (GET_MODE_SIZE (GET_MODE (x))
3108               <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3109           && reg_equivs
3110           && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
3111         return;
3112
3113       elimination_effects (SUBREG_REG (x), mem_mode);
3114       return;
3115
3116     case USE:
3117       /* If using a register that is the source of an eliminate we still
3118          think can be performed, note it cannot be performed since we don't
3119          know how this register is used.  */
3120       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3121         if (ep->from_rtx == XEXP (x, 0))
3122           ep->can_eliminate = 0;
3123
3124       elimination_effects (XEXP (x, 0), mem_mode);
3125       return;
3126
3127     case CLOBBER:
3128       /* If clobbering a register that is the replacement register for an
3129          elimination we still think can be performed, note that it cannot
3130          be performed.  Otherwise, we need not be concerned about it.  */
3131       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3132         if (ep->to_rtx == XEXP (x, 0))
3133           ep->can_eliminate = 0;
3134
3135       elimination_effects (XEXP (x, 0), mem_mode);
3136       return;
3137
3138     case SET:
3139       /* Check for setting a register that we know about.  */
3140       if (REG_P (SET_DEST (x)))
3141         {
3142           /* See if this is setting the replacement register for an
3143              elimination.
3144
3145              If DEST is the hard frame pointer, we do nothing because we
3146              assume that all assignments to the frame pointer are for
3147              non-local gotos and are being done at a time when they are valid
3148              and do not disturb anything else.  Some machines want to
3149              eliminate a fake argument pointer (or even a fake frame pointer)
3150              with either the real frame or the stack pointer.  Assignments to
3151              the hard frame pointer must not prevent this elimination.  */
3152
3153           for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
3154                ep++)
3155             if (ep->to_rtx == SET_DEST (x)
3156                 && SET_DEST (x) != hard_frame_pointer_rtx)
3157               {
3158                 /* If it is being incremented, adjust the offset.  Otherwise,
3159                    this elimination can't be done.  */
3160                 rtx src = SET_SRC (x);
3161
3162                 if (GET_CODE (src) == PLUS
3163                     && XEXP (src, 0) == SET_DEST (x)
3164                     && CONST_INT_P (XEXP (src, 1)))
3165                   ep->offset -= INTVAL (XEXP (src, 1));
3166                 else
3167                   ep->can_eliminate = 0;
3168               }
3169         }
3170
3171       elimination_effects (SET_DEST (x), VOIDmode);
3172       elimination_effects (SET_SRC (x), VOIDmode);
3173       return;
3174
3175     case MEM:
3176       /* Our only special processing is to pass the mode of the MEM to our
3177          recursive call.  */
3178       elimination_effects (XEXP (x, 0), GET_MODE (x));
3179       return;
3180
3181     default:
3182       break;
3183     }
3184
3185   fmt = GET_RTX_FORMAT (code);
3186   for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3187     {
3188       if (*fmt == 'e')
3189         elimination_effects (XEXP (x, i), mem_mode);
3190       else if (*fmt == 'E')
3191         for (j = 0; j < XVECLEN (x, i); j++)
3192           elimination_effects (XVECEXP (x, i, j), mem_mode);
3193     }
3194 }
3195
3196 /* Descend through rtx X and verify that no references to eliminable registers
3197    remain.  If any do remain, mark the involved register as not
3198    eliminable.  */
3199
3200 static void
3201 check_eliminable_occurrences (rtx x)
3202 {
3203   const char *fmt;
3204   int i;
3205   enum rtx_code code;
3206
3207   if (x == 0)
3208     return;
3209
3210   code = GET_CODE (x);
3211
3212   if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3213     {
3214       struct elim_table *ep;
3215
3216       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3217         if (ep->from_rtx == x)
3218           ep->can_eliminate = 0;
3219       return;
3220     }
3221
3222   fmt = GET_RTX_FORMAT (code);
3223   for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3224     {
3225       if (*fmt == 'e')
3226         check_eliminable_occurrences (XEXP (x, i));
3227       else if (*fmt == 'E')
3228         {
3229           int j;
3230           for (j = 0; j < XVECLEN (x, i); j++)
3231             check_eliminable_occurrences (XVECEXP (x, i, j));
3232         }
3233     }
3234 }
3235 \f
3236 /* Scan INSN and eliminate all eliminable registers in it.
3237
3238    If REPLACE is nonzero, do the replacement destructively.  Also
3239    delete the insn as dead it if it is setting an eliminable register.
3240
3241    If REPLACE is zero, do all our allocations in reload_obstack.
3242
3243    If no eliminations were done and this insn doesn't require any elimination
3244    processing (these are not identical conditions: it might be updating sp,
3245    but not referencing fp; this needs to be seen during reload_as_needed so
3246    that the offset between fp and sp can be taken into consideration), zero
3247    is returned.  Otherwise, 1 is returned.  */
3248
3249 static int
3250 eliminate_regs_in_insn (rtx_insn *insn, int replace)
3251 {
3252   int icode = recog_memoized (insn);
3253   rtx old_body = PATTERN (insn);
3254   int insn_is_asm = asm_noperands (old_body) >= 0;
3255   rtx old_set = single_set (insn);
3256   rtx new_body;
3257   int val = 0;
3258   int i;
3259   rtx substed_operand[MAX_RECOG_OPERANDS];
3260   rtx orig_operand[MAX_RECOG_OPERANDS];
3261   struct elim_table *ep;
3262   rtx plus_src, plus_cst_src;
3263
3264   if (! insn_is_asm && icode < 0)
3265     {
3266       gcc_assert (DEBUG_INSN_P (insn)
3267                   || GET_CODE (PATTERN (insn)) == USE
3268                   || GET_CODE (PATTERN (insn)) == CLOBBER
3269                   || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3270       if (DEBUG_INSN_P (insn))
3271         INSN_VAR_LOCATION_LOC (insn)
3272           = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
3273       return 0;
3274     }
3275
3276   if (old_set != 0 && REG_P (SET_DEST (old_set))
3277       && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3278     {
3279       /* Check for setting an eliminable register.  */
3280       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3281         if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3282           {
3283             /* If this is setting the frame pointer register to the
3284                hardware frame pointer register and this is an elimination
3285                that will be done (tested above), this insn is really
3286                adjusting the frame pointer downward to compensate for
3287                the adjustment done before a nonlocal goto.  */
3288             if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
3289                 && ep->from == FRAME_POINTER_REGNUM
3290                 && ep->to == HARD_FRAME_POINTER_REGNUM)
3291               {
3292                 rtx base = SET_SRC (old_set);
3293                 rtx_insn *base_insn = insn;
3294                 HOST_WIDE_INT offset = 0;
3295
3296                 while (base != ep->to_rtx)
3297                   {
3298                     rtx_insn *prev_insn;
3299                     rtx prev_set;
3300
3301                     if (GET_CODE (base) == PLUS
3302                         && CONST_INT_P (XEXP (base, 1)))
3303                       {
3304                         offset += INTVAL (XEXP (base, 1));
3305                         base = XEXP (base, 0);
3306                       }
3307                     else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3308                              && (prev_set = single_set (prev_insn)) != 0
3309                              && rtx_equal_p (SET_DEST (prev_set), base))
3310                       {
3311                         base = SET_SRC (prev_set);
3312                         base_insn = prev_insn;
3313                       }
3314                     else
3315                       break;
3316                   }
3317
3318                 if (base == ep->to_rtx)
3319                   {
3320                     rtx src = plus_constant (Pmode, ep->to_rtx,
3321                                              offset - ep->offset);
3322
3323                     new_body = old_body;
3324                     if (! replace)
3325                       {
3326                         new_body = copy_insn (old_body);
3327                         if (REG_NOTES (insn))
3328                           REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3329                       }
3330                     PATTERN (insn) = new_body;
3331                     old_set = single_set (insn);
3332
3333                     /* First see if this insn remains valid when we
3334                        make the change.  If not, keep the INSN_CODE
3335                        the same and let reload fit it up.  */
3336                     validate_change (insn, &SET_SRC (old_set), src, 1);
3337                     validate_change (insn, &SET_DEST (old_set),
3338                                      ep->to_rtx, 1);
3339                     if (! apply_change_group ())
3340                       {
3341                         SET_SRC (old_set) = src;
3342                         SET_DEST (old_set) = ep->to_rtx;
3343                       }
3344
3345                     val = 1;
3346                     goto done;
3347                   }
3348               }
3349
3350             /* In this case this insn isn't serving a useful purpose.  We
3351                will delete it in reload_as_needed once we know that this
3352                elimination is, in fact, being done.
3353
3354                If REPLACE isn't set, we can't delete this insn, but needn't
3355                process it since it won't be used unless something changes.  */
3356             if (replace)
3357               {
3358                 delete_dead_insn (insn);
3359                 return 1;
3360               }
3361             val = 1;
3362             goto done;
3363           }
3364     }
3365
3366   /* We allow one special case which happens to work on all machines we
3367      currently support: a single set with the source or a REG_EQUAL
3368      note being a PLUS of an eliminable register and a constant.  */
3369   plus_src = plus_cst_src = 0;
3370   if (old_set && REG_P (SET_DEST (old_set)))
3371     {
3372       if (GET_CODE (SET_SRC (old_set)) == PLUS)
3373         plus_src = SET_SRC (old_set);
3374       /* First see if the source is of the form (plus (...) CST).  */
3375       if (plus_src
3376           && CONST_INT_P (XEXP (plus_src, 1)))
3377         plus_cst_src = plus_src;
3378       else if (REG_P (SET_SRC (old_set))
3379                || plus_src)
3380         {
3381           /* Otherwise, see if we have a REG_EQUAL note of the form
3382              (plus (...) CST).  */
3383           rtx links;
3384           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3385             {
3386               if ((REG_NOTE_KIND (links) == REG_EQUAL
3387                    || REG_NOTE_KIND (links) == REG_EQUIV)
3388                   && GET_CODE (XEXP (links, 0)) == PLUS
3389                   && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3390                 {
3391                   plus_cst_src = XEXP (links, 0);
3392                   break;
3393                 }
3394             }
3395         }
3396
3397       /* Check that the first operand of the PLUS is a hard reg or
3398          the lowpart subreg of one.  */
3399       if (plus_cst_src)
3400         {
3401           rtx reg = XEXP (plus_cst_src, 0);
3402           if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3403             reg = SUBREG_REG (reg);
3404
3405           if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3406             plus_cst_src = 0;
3407         }
3408     }
3409   if (plus_cst_src)
3410     {
3411       rtx reg = XEXP (plus_cst_src, 0);
3412       HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3413
3414       if (GET_CODE (reg) == SUBREG)
3415         reg = SUBREG_REG (reg);
3416
3417       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3418         if (ep->from_rtx == reg && ep->can_eliminate)
3419           {
3420             rtx to_rtx = ep->to_rtx;
3421             offset += ep->offset;
3422             offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3423
3424             if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3425               to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3426                                     to_rtx);
3427             /* If we have a nonzero offset, and the source is already
3428                a simple REG, the following transformation would
3429                increase the cost of the insn by replacing a simple REG
3430                with (plus (reg sp) CST).  So try only when we already
3431                had a PLUS before.  */
3432             if (offset == 0 || plus_src)
3433               {
3434                 rtx new_src = plus_constant (GET_MODE (to_rtx),
3435                                              to_rtx, offset);
3436
3437                 new_body = old_body;
3438                 if (! replace)
3439                   {
3440                     new_body = copy_insn (old_body);
3441                     if (REG_NOTES (insn))
3442                       REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3443                   }
3444                 PATTERN (insn) = new_body;
3445                 old_set = single_set (insn);
3446
3447                 /* First see if this insn remains valid when we make the
3448                    change.  If not, try to replace the whole pattern with
3449                    a simple set (this may help if the original insn was a
3450                    PARALLEL that was only recognized as single_set due to
3451                    REG_UNUSED notes).  If this isn't valid either, keep
3452                    the INSN_CODE the same and let reload fix it up.  */
3453                 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3454                   {
3455                     rtx new_pat = gen_rtx_SET (SET_DEST (old_set), new_src);
3456
3457                     if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3458                       SET_SRC (old_set) = new_src;
3459                   }
3460               }
3461             else
3462               break;
3463
3464             val = 1;
3465             /* This can't have an effect on elimination offsets, so skip right
3466                to the end.  */
3467             goto done;
3468           }
3469     }
3470
3471   /* Determine the effects of this insn on elimination offsets.  */
3472   elimination_effects (old_body, VOIDmode);
3473
3474   /* Eliminate all eliminable registers occurring in operands that
3475      can be handled by reload.  */
3476   extract_insn (insn);
3477   for (i = 0; i < recog_data.n_operands; i++)
3478     {
3479       orig_operand[i] = recog_data.operand[i];
3480       substed_operand[i] = recog_data.operand[i];
3481
3482       /* For an asm statement, every operand is eliminable.  */
3483       if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3484         {
3485           bool is_set_src, in_plus;
3486
3487           /* Check for setting a register that we know about.  */
3488           if (recog_data.operand_type[i] != OP_IN
3489               && REG_P (orig_operand[i]))
3490             {
3491               /* If we are assigning to a register that can be eliminated, it
3492                  must be as part of a PARALLEL, since the code above handles
3493                  single SETs.  We must indicate that we can no longer
3494                  eliminate this reg.  */
3495               for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
3496                    ep++)
3497                 if (ep->from_rtx == orig_operand[i])
3498                   ep->can_eliminate = 0;
3499             }
3500
3501           /* Companion to the above plus substitution, we can allow
3502              invariants as the source of a plain move.  */
3503           is_set_src = false;
3504           if (old_set
3505               && recog_data.operand_loc[i] == &SET_SRC (old_set))
3506             is_set_src = true;
3507           in_plus = false;
3508           if (plus_src
3509               && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3510                   || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3511             in_plus = true;
3512
3513           substed_operand[i]
3514             = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3515                                 replace ? insn : NULL_RTX,
3516                                 is_set_src || in_plus, false);
3517           if (substed_operand[i] != orig_operand[i])
3518             val = 1;
3519           /* Terminate the search in check_eliminable_occurrences at
3520              this point.  */
3521           *recog_data.operand_loc[i] = 0;
3522
3523           /* If an output operand changed from a REG to a MEM and INSN is an
3524              insn, write a CLOBBER insn.  */
3525           if (recog_data.operand_type[i] != OP_IN
3526               && REG_P (orig_operand[i])
3527               && MEM_P (substed_operand[i])
3528               && replace)
3529             emit_insn_after (gen_clobber (orig_operand[i]), insn);
3530         }
3531     }
3532
3533   for (i = 0; i < recog_data.n_dups; i++)
3534     *recog_data.dup_loc[i]
3535       = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3536
3537   /* If any eliminable remain, they aren't eliminable anymore.  */
3538   check_eliminable_occurrences (old_body);
3539
3540   /* Substitute the operands; the new values are in the substed_operand
3541      array.  */
3542   for (i = 0; i < recog_data.n_operands; i++)
3543     *recog_data.operand_loc[i] = substed_operand[i];
3544   for (i = 0; i < recog_data.n_dups; i++)
3545     *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3546
3547   /* If we are replacing a body that was a (set X (plus Y Z)), try to
3548      re-recognize the insn.  We do this in case we had a simple addition
3549      but now can do this as a load-address.  This saves an insn in this
3550      common case.
3551      If re-recognition fails, the old insn code number will still be used,
3552      and some register operands may have changed into PLUS expressions.
3553      These will be handled by find_reloads by loading them into a register
3554      again.  */
3555
3556   if (val)
3557     {
3558       /* If we aren't replacing things permanently and we changed something,
3559          make another copy to ensure that all the RTL is new.  Otherwise
3560          things can go wrong if find_reload swaps commutative operands
3561          and one is inside RTL that has been copied while the other is not.  */
3562       new_body = old_body;
3563       if (! replace)
3564         {
3565           new_body = copy_insn (old_body);
3566           if (REG_NOTES (insn))
3567             REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3568         }
3569       PATTERN (insn) = new_body;
3570
3571       /* If we had a move insn but now we don't, rerecognize it.  This will
3572          cause spurious re-recognition if the old move had a PARALLEL since
3573          the new one still will, but we can't call single_set without
3574          having put NEW_BODY into the insn and the re-recognition won't
3575          hurt in this rare case.  */
3576       /* ??? Why this huge if statement - why don't we just rerecognize the
3577          thing always?  */
3578       if (! insn_is_asm
3579           && old_set != 0
3580           && ((REG_P (SET_SRC (old_set))
3581                && (GET_CODE (new_body) != SET
3582                    || !REG_P (SET_SRC (new_body))))
3583               /* If this was a load from or store to memory, compare
3584                  the MEM in recog_data.operand to the one in the insn.
3585                  If they are not equal, then rerecognize the insn.  */
3586               || (old_set != 0
3587                   && ((MEM_P (SET_SRC (old_set))
3588                        && SET_SRC (old_set) != recog_data.operand[1])
3589                       || (MEM_P (SET_DEST (old_set))
3590                           && SET_DEST (old_set) != recog_data.operand[0])))
3591               /* If this was an add insn before, rerecognize.  */
3592               || GET_CODE (SET_SRC (old_set)) == PLUS))
3593         {
3594           int new_icode = recog (PATTERN (insn), insn, 0);
3595           if (new_icode >= 0)
3596             INSN_CODE (insn) = new_icode;
3597         }
3598     }
3599
3600   /* Restore the old body.  If there were any changes to it, we made a copy
3601      of it while the changes were still in place, so we'll correctly return
3602      a modified insn below.  */
3603   if (! replace)
3604     {
3605       /* Restore the old body.  */
3606       for (i = 0; i < recog_data.n_operands; i++)
3607         /* Restoring a top-level match_parallel would clobber the new_body
3608            we installed in the insn.  */
3609         if (recog_data.operand_loc[i] != &PATTERN (insn))
3610           *recog_data.operand_loc[i] = orig_operand[i];
3611       for (i = 0; i < recog_data.n_dups; i++)
3612         *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3613     }
3614
3615   /* Update all elimination pairs to reflect the status after the current
3616      insn.  The changes we make were determined by the earlier call to
3617      elimination_effects.
3618
3619      We also detect cases where register elimination cannot be done,
3620      namely, if a register would be both changed and referenced outside a MEM
3621      in the resulting insn since such an insn is often undefined and, even if
3622      not, we cannot know what meaning will be given to it.  Note that it is
3623      valid to have a register used in an address in an insn that changes it
3624      (presumably with a pre- or post-increment or decrement).
3625
3626      If anything changes, return nonzero.  */
3627
3628   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3629     {
3630       if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3631         ep->can_eliminate = 0;
3632
3633       ep->ref_outside_mem = 0;
3634
3635       if (ep->previous_offset != ep->offset)
3636         val = 1;
3637     }
3638
3639  done:
3640   /* If we changed something, perform elimination in REG_NOTES.  This is
3641      needed even when REPLACE is zero because a REG_DEAD note might refer
3642      to a register that we eliminate and could cause a different number
3643      of spill registers to be needed in the final reload pass than in
3644      the pre-passes.  */
3645   if (val && REG_NOTES (insn) != 0)
3646     REG_NOTES (insn)
3647       = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true,
3648                           false);
3649
3650   return val;
3651 }
3652
3653 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3654    register allocator.  INSN is the instruction we need to examine, we perform
3655    eliminations in its operands and record cases where eliminating a reg with
3656    an invariant equivalence would add extra cost.  */
3657
3658 static void
3659 elimination_costs_in_insn (rtx_insn *insn)
3660 {
3661   int icode = recog_memoized (insn);
3662   rtx old_body = PATTERN (insn);
3663   int insn_is_asm = asm_noperands (old_body) >= 0;
3664   rtx old_set = single_set (insn);
3665   int i;
3666   rtx orig_operand[MAX_RECOG_OPERANDS];
3667   rtx orig_dup[MAX_RECOG_OPERANDS];
3668   struct elim_table *ep;
3669   rtx plus_src, plus_cst_src;
3670   bool sets_reg_p;
3671
3672   if (! insn_is_asm && icode < 0)
3673     {
3674       gcc_assert (DEBUG_INSN_P (insn)
3675                   || GET_CODE (PATTERN (insn)) == USE
3676                   || GET_CODE (PATTERN (insn)) == CLOBBER
3677                   || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3678       return;
3679     }
3680
3681   if (old_set != 0 && REG_P (SET_DEST (old_set))
3682       && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3683     {
3684       /* Check for setting an eliminable register.  */
3685       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3686         if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3687           return;
3688     }
3689
3690   /* We allow one special case which happens to work on all machines we
3691      currently support: a single set with the source or a REG_EQUAL
3692      note being a PLUS of an eliminable register and a constant.  */
3693   plus_src = plus_cst_src = 0;
3694   sets_reg_p = false;
3695   if (old_set && REG_P (SET_DEST (old_set)))
3696     {
3697       sets_reg_p = true;
3698       if (GET_CODE (SET_SRC (old_set)) == PLUS)
3699         plus_src = SET_SRC (old_set);
3700       /* First see if the source is of the form (plus (...) CST).  */
3701       if (plus_src
3702           && CONST_INT_P (XEXP (plus_src, 1)))
3703         plus_cst_src = plus_src;
3704       else if (REG_P (SET_SRC (old_set))
3705                || plus_src)
3706         {
3707           /* Otherwise, see if we have a REG_EQUAL note of the form
3708              (plus (...) CST).  */
3709           rtx links;
3710           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3711             {
3712               if ((REG_NOTE_KIND (links) == REG_EQUAL
3713                    || REG_NOTE_KIND (links) == REG_EQUIV)
3714                   && GET_CODE (XEXP (links, 0)) == PLUS
3715                   && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3716                 {
3717                   plus_cst_src = XEXP (links, 0);
3718                   break;
3719                 }
3720             }
3721         }
3722     }
3723
3724   /* Determine the effects of this insn on elimination offsets.  */
3725   elimination_effects (old_body, VOIDmode);
3726
3727   /* Eliminate all eliminable registers occurring in operands that
3728      can be handled by reload.  */
3729   extract_insn (insn);
3730   for (i = 0; i < recog_data.n_dups; i++)
3731     orig_dup[i] = *recog_data.dup_loc[i];
3732
3733   for (i = 0; i < recog_data.n_operands; i++)
3734     {
3735       orig_operand[i] = recog_data.operand[i];
3736
3737       /* For an asm statement, every operand is eliminable.  */
3738       if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3739         {
3740           bool is_set_src, in_plus;
3741
3742           /* Check for setting a register that we know about.  */
3743           if (recog_data.operand_type[i] != OP_IN
3744               && REG_P (orig_operand[i]))
3745             {
3746               /* If we are assigning to a register that can be eliminated, it
3747                  must be as part of a PARALLEL, since the code above handles
3748                  single SETs.  We must indicate that we can no longer
3749                  eliminate this reg.  */
3750               for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
3751                    ep++)
3752                 if (ep->from_rtx == orig_operand[i])
3753                   ep->can_eliminate = 0;
3754             }
3755
3756           /* Companion to the above plus substitution, we can allow
3757              invariants as the source of a plain move.  */
3758           is_set_src = false;
3759           if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3760             is_set_src = true;
3761           if (is_set_src && !sets_reg_p)
3762             note_reg_elim_costly (SET_SRC (old_set), insn);
3763           in_plus = false;
3764           if (plus_src && sets_reg_p
3765               && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3766                   || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3767             in_plus = true;
3768
3769           eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3770                             NULL_RTX,
3771                             is_set_src || in_plus, true);
3772           /* Terminate the search in check_eliminable_occurrences at
3773              this point.  */
3774           *recog_data.operand_loc[i] = 0;
3775         }
3776     }
3777
3778   for (i = 0; i < recog_data.n_dups; i++)
3779     *recog_data.dup_loc[i]
3780       = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3781
3782   /* If any eliminable remain, they aren't eliminable anymore.  */
3783   check_eliminable_occurrences (old_body);
3784
3785   /* Restore the old body.  */
3786   for (i = 0; i < recog_data.n_operands; i++)
3787     *recog_data.operand_loc[i] = orig_operand[i];
3788   for (i = 0; i < recog_data.n_dups; i++)
3789     *recog_data.dup_loc[i] = orig_dup[i];
3790
3791   /* Update all elimination pairs to reflect the status after the current
3792      insn.  The changes we make were determined by the earlier call to
3793      elimination_effects.  */
3794
3795   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3796     {
3797       if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3798         ep->can_eliminate = 0;
3799
3800       ep->ref_outside_mem = 0;
3801     }
3802
3803   return;
3804 }
3805
3806 /* Loop through all elimination pairs.
3807    Recalculate the number not at initial offset.
3808
3809    Compute the maximum offset (minimum offset if the stack does not
3810    grow downward) for each elimination pair.  */
3811
3812 static void
3813 update_eliminable_offsets (void)
3814 {
3815   struct elim_table *ep;
3816
3817   num_not_at_initial_offset = 0;
3818   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3819     {
3820       ep->previous_offset = ep->offset;
3821       if (ep->can_eliminate && ep->offset != ep->initial_offset)
3822         num_not_at_initial_offset++;
3823     }
3824 }
3825
3826 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3827    replacement we currently believe is valid, mark it as not eliminable if X
3828    modifies DEST in any way other than by adding a constant integer to it.
3829
3830    If DEST is the frame pointer, we do nothing because we assume that
3831    all assignments to the hard frame pointer are nonlocal gotos and are being
3832    done at a time when they are valid and do not disturb anything else.
3833    Some machines want to eliminate a fake argument pointer with either the
3834    frame or stack pointer.  Assignments to the hard frame pointer must not
3835    prevent this elimination.
3836
3837    Called via note_stores from reload before starting its passes to scan
3838    the insns of the function.  */
3839
3840 static void
3841 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3842 {
3843   unsigned int i;
3844
3845   /* A SUBREG of a hard register here is just changing its mode.  We should
3846      not see a SUBREG of an eliminable hard register, but check just in
3847      case.  */
3848   if (GET_CODE (dest) == SUBREG)
3849     dest = SUBREG_REG (dest);
3850
3851   if (dest == hard_frame_pointer_rtx)
3852     return;
3853
3854   for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3855     if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3856         && (GET_CODE (x) != SET
3857             || GET_CODE (SET_SRC (x)) != PLUS
3858             || XEXP (SET_SRC (x), 0) != dest
3859             || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3860       {
3861         reg_eliminate[i].can_eliminate_previous
3862           = reg_eliminate[i].can_eliminate = 0;
3863         num_eliminable--;
3864       }
3865 }
3866
3867 /* Verify that the initial elimination offsets did not change since the
3868    last call to set_initial_elim_offsets.  This is used to catch cases
3869    where something illegal happened during reload_as_needed that could
3870    cause incorrect code to be generated if we did not check for it.  */
3871
3872 static bool
3873 verify_initial_elim_offsets (void)
3874 {
3875   HOST_WIDE_INT t;
3876
3877   if (!num_eliminable)
3878     return true;
3879
3880 #ifdef ELIMINABLE_REGS
3881   {
3882    struct elim_table *ep;
3883
3884    for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3885      {
3886        INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3887        if (t != ep->initial_offset)
3888          return false;
3889      }
3890   }
3891 #else
3892   INITIAL_FRAME_POINTER_OFFSET (t);
3893   if (t != reg_eliminate[0].initial_offset)
3894     return false;
3895 #endif
3896
3897   return true;
3898 }
3899
3900 /* Reset all offsets on eliminable registers to their initial values.  */
3901
3902 static void
3903 set_initial_elim_offsets (void)
3904 {
3905   struct elim_table *ep = reg_eliminate;
3906
3907 #ifdef ELIMINABLE_REGS
3908   for (; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3909     {
3910       INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3911       ep->previous_offset = ep->offset = ep->initial_offset;
3912     }
3913 #else
3914   INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3915   ep->previous_offset = ep->offset = ep->initial_offset;
3916 #endif
3917
3918   num_not_at_initial_offset = 0;
3919 }
3920
3921 /* Subroutine of set_initial_label_offsets called via for_each_eh_label.  */
3922
3923 static void
3924 set_initial_eh_label_offset (rtx label)
3925 {
3926   set_label_offsets (label, NULL, 1);
3927 }
3928
3929 /* Initialize the known label offsets.
3930    Set a known offset for each forced label to be at the initial offset
3931    of each elimination.  We do this because we assume that all
3932    computed jumps occur from a location where each elimination is
3933    at its initial offset.
3934    For all other labels, show that we don't know the offsets.  */
3935
3936 static void
3937 set_initial_label_offsets (void)
3938 {
3939   memset (offsets_known_at, 0, num_labels);
3940
3941   for (rtx_insn_list *x = forced_labels; x; x = x->next ())
3942     if (x->insn ())
3943       set_label_offsets (x->insn (), NULL, 1);
3944
3945   for (rtx_insn_list *x = nonlocal_goto_handler_labels; x; x = x->next ())
3946     if (x->insn ())
3947       set_label_offsets (x->insn (), NULL, 1);
3948
3949   for_each_eh_label (set_initial_eh_label_offset);
3950 }
3951
3952 /* Set all elimination offsets to the known values for the code label given
3953    by INSN.  */
3954
3955 static void
3956 set_offsets_for_label (rtx_insn *insn)
3957 {
3958   unsigned int i;
3959   int label_nr = CODE_LABEL_NUMBER (insn);
3960   struct elim_table *ep;
3961
3962   num_not_at_initial_offset = 0;
3963   for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3964     {
3965       ep->offset = ep->previous_offset
3966                  = offsets_at[label_nr - first_label_num][i];
3967       if (ep->can_eliminate && ep->offset != ep->initial_offset)
3968         num_not_at_initial_offset++;
3969     }
3970 }
3971
3972 /* See if anything that happened changes which eliminations are valid.
3973    For example, on the SPARC, whether or not the frame pointer can
3974    be eliminated can depend on what registers have been used.  We need
3975    not check some conditions again (such as flag_omit_frame_pointer)
3976    since they can't have changed.  */
3977
3978 static void
3979 update_eliminables (HARD_REG_SET *pset)
3980 {
3981   int previous_frame_pointer_needed = frame_pointer_needed;
3982   struct elim_table *ep;
3983
3984   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3985     if ((ep->from == HARD_FRAME_POINTER_REGNUM
3986          && targetm.frame_pointer_required ())
3987 #ifdef ELIMINABLE_REGS
3988         || ! targetm.can_eliminate (ep->from, ep->to)
3989 #endif
3990         )
3991       ep->can_eliminate = 0;
3992
3993   /* Look for the case where we have discovered that we can't replace
3994      register A with register B and that means that we will now be
3995      trying to replace register A with register C.  This means we can
3996      no longer replace register C with register B and we need to disable
3997      such an elimination, if it exists.  This occurs often with A == ap,
3998      B == sp, and C == fp.  */
3999
4000   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4001     {
4002       struct elim_table *op;
4003       int new_to = -1;
4004
4005       if (! ep->can_eliminate && ep->can_eliminate_previous)
4006         {
4007           /* Find the current elimination for ep->from, if there is a
4008              new one.  */
4009           for (op = reg_eliminate;
4010                op < &reg_eliminate[NUM_ELIMINABLE_REGS]; op++)
4011             if (op->from == ep->from && op->can_eliminate)
4012               {
4013                 new_to = op->to;
4014                 break;
4015               }
4016
4017           /* See if there is an elimination of NEW_TO -> EP->TO.  If so,
4018              disable it.  */
4019           for (op = reg_eliminate;
4020                op < &reg_eliminate[NUM_ELIMINABLE_REGS]; op++)
4021             if (op->from == new_to && op->to == ep->to)
4022               op->can_eliminate = 0;
4023         }
4024     }
4025
4026   /* See if any registers that we thought we could eliminate the previous
4027      time are no longer eliminable.  If so, something has changed and we
4028      must spill the register.  Also, recompute the number of eliminable
4029      registers and see if the frame pointer is needed; it is if there is
4030      no elimination of the frame pointer that we can perform.  */
4031
4032   frame_pointer_needed = 1;
4033   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4034     {
4035       if (ep->can_eliminate
4036           && ep->from == FRAME_POINTER_REGNUM
4037           && ep->to != HARD_FRAME_POINTER_REGNUM
4038           && (! SUPPORTS_STACK_ALIGNMENT
4039               || ! crtl->stack_realign_needed))
4040         frame_pointer_needed = 0;
4041
4042       if (! ep->can_eliminate && ep->can_eliminate_previous)
4043         {
4044           ep->can_eliminate_previous = 0;
4045           SET_HARD_REG_BIT (*pset, ep->from);
4046           num_eliminable--;
4047         }
4048     }
4049
4050   /* If we didn't need a frame pointer last time, but we do now, spill
4051      the hard frame pointer.  */
4052   if (frame_pointer_needed && ! previous_frame_pointer_needed)
4053     SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
4054 }
4055
4056 /* Call update_eliminables an spill any registers we can't eliminate anymore.
4057    Return true iff a register was spilled.  */
4058
4059 static bool
4060 update_eliminables_and_spill (void)
4061 {
4062   int i;
4063   bool did_spill = false;
4064   HARD_REG_SET to_spill;
4065   CLEAR_HARD_REG_SET (to_spill);
4066   update_eliminables (&to_spill);
4067   AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
4068
4069   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4070     if (TEST_HARD_REG_BIT (to_spill, i))
4071       {
4072         spill_hard_reg (i, 1);
4073         did_spill = true;
4074
4075         /* Regardless of the state of spills, if we previously had
4076            a register that we thought we could eliminate, but now can
4077            not eliminate, we must run another pass.
4078
4079            Consider pseudos which have an entry in reg_equiv_* which
4080            reference an eliminable register.  We must make another pass
4081            to update reg_equiv_* so that we do not substitute in the
4082            old value from when we thought the elimination could be
4083            performed.  */
4084       }
4085   return did_spill;
4086 }
4087
4088 /* Return true if X is used as the target register of an elimination.  */
4089
4090 bool
4091 elimination_target_reg_p (rtx x)
4092 {
4093   struct elim_table *ep;
4094
4095   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4096     if (ep->to_rtx == x && ep->can_eliminate)
4097       return true;
4098
4099   return false;
4100 }
4101
4102 /* Initialize the table of registers to eliminate.
4103    Pre-condition: global flag frame_pointer_needed has been set before
4104    calling this function.  */
4105
4106 static void
4107 init_elim_table (void)
4108 {
4109   struct elim_table *ep;
4110 #ifdef ELIMINABLE_REGS
4111   const struct elim_table_1 *ep1;
4112 #endif
4113
4114   if (!reg_eliminate)
4115     reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
4116
4117   num_eliminable = 0;
4118
4119 #ifdef ELIMINABLE_REGS
4120   for (ep = reg_eliminate, ep1 = reg_eliminate_1;
4121        ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
4122     {
4123       ep->from = ep1->from;
4124       ep->to = ep1->to;
4125       ep->can_eliminate = ep->can_eliminate_previous
4126         = (targetm.can_eliminate (ep->from, ep->to)
4127            && ! (ep->to == STACK_POINTER_REGNUM
4128                  && frame_pointer_needed
4129                  && (! SUPPORTS_STACK_ALIGNMENT
4130                      || ! stack_realign_fp)));
4131     }
4132 #else
4133   reg_eliminate[0].from = reg_eliminate_1[0].from;
4134   reg_eliminate[0].to = reg_eliminate_1[0].to;
4135   reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
4136     = ! frame_pointer_needed;
4137 #endif
4138
4139   /* Count the number of eliminable registers and build the FROM and TO
4140      REG rtx's.  Note that code in gen_rtx_REG will cause, e.g.,
4141      gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4142      We depend on this.  */
4143   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4144     {
4145       num_eliminable += ep->can_eliminate;
4146       ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
4147       ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
4148     }
4149 }
4150
4151 /* Find all the pseudo registers that didn't get hard regs
4152    but do have known equivalent constants or memory slots.
4153    These include parameters (known equivalent to parameter slots)
4154    and cse'd or loop-moved constant memory addresses.
4155
4156    Record constant equivalents in reg_equiv_constant
4157    so they will be substituted by find_reloads.
4158    Record memory equivalents in reg_mem_equiv so they can
4159    be substituted eventually by altering the REG-rtx's.  */
4160
4161 static void
4162 init_eliminable_invariants (rtx_insn *first, bool do_subregs)
4163 {
4164   int i;
4165   rtx_insn *insn;
4166
4167   grow_reg_equivs ();
4168   if (do_subregs)
4169     reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
4170   else
4171     reg_max_ref_width = NULL;
4172
4173   num_eliminable_invariants = 0;
4174
4175   first_label_num = get_first_label_num ();
4176   num_labels = max_label_num () - first_label_num;
4177
4178   /* Allocate the tables used to store offset information at labels.  */
4179   offsets_known_at = XNEWVEC (char, num_labels);
4180   offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
4181
4182 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4183    to.  If DO_SUBREGS is true, also find all paradoxical subregs and
4184    find largest such for each pseudo.  FIRST is the head of the insn
4185    list.  */
4186
4187   for (insn = first; insn; insn = NEXT_INSN (insn))
4188     {
4189       rtx set = single_set (insn);
4190
4191       /* We may introduce USEs that we want to remove at the end, so
4192          we'll mark them with QImode.  Make sure there are no
4193          previously-marked insns left by say regmove.  */
4194       if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
4195           && GET_MODE (insn) != VOIDmode)
4196         PUT_MODE (insn, VOIDmode);
4197
4198       if (do_subregs && NONDEBUG_INSN_P (insn))
4199         scan_paradoxical_subregs (PATTERN (insn));
4200
4201       if (set != 0 && REG_P (SET_DEST (set)))
4202         {
4203           rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
4204           rtx x;
4205
4206           if (! note)
4207             continue;
4208
4209           i = REGNO (SET_DEST (set));
4210           x = XEXP (note, 0);
4211
4212           if (i <= LAST_VIRTUAL_REGISTER)
4213             continue;
4214
4215           /* If flag_pic and we have constant, verify it's legitimate.  */
4216           if (!CONSTANT_P (x)
4217               || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
4218             {
4219               /* It can happen that a REG_EQUIV note contains a MEM
4220                  that is not a legitimate memory operand.  As later
4221                  stages of reload assume that all addresses found
4222                  in the reg_equiv_* arrays were originally legitimate,
4223                  we ignore such REG_EQUIV notes.  */
4224               if (memory_operand (x, VOIDmode))
4225                 {
4226                   /* Always unshare the equivalence, so we can
4227                      substitute into this insn without touching the
4228                        equivalence.  */
4229                   reg_equiv_memory_loc (i) = copy_rtx (x);
4230                 }
4231               else if (function_invariant_p (x))
4232                 {
4233                   machine_mode mode;
4234
4235                   mode = GET_MODE (SET_DEST (set));
4236                   if (GET_CODE (x) == PLUS)
4237                     {
4238                       /* This is PLUS of frame pointer and a constant,
4239                          and might be shared.  Unshare it.  */
4240                       reg_equiv_invariant (i) = copy_rtx (x);
4241                       num_eliminable_invariants++;
4242                     }
4243                   else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4244                     {
4245                       reg_equiv_invariant (i) = x;
4246                       num_eliminable_invariants++;
4247                     }
4248                   else if (targetm.legitimate_constant_p (mode, x))
4249                     reg_equiv_constant (i) = x;
4250                   else
4251                     {
4252                       reg_equiv_memory_loc (i) = force_const_mem (mode, x);
4253                       if (! reg_equiv_memory_loc (i))
4254                         reg_equiv_init (i) = NULL;
4255                     }
4256                 }
4257               else
4258                 {
4259                   reg_equiv_init (i) = NULL;
4260                   continue;
4261                 }
4262             }
4263           else
4264             reg_equiv_init (i) = NULL;
4265         }
4266     }
4267
4268   if (dump_file)
4269     for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4270       if (reg_equiv_init (i))
4271         {
4272           fprintf (dump_file, "init_insns for %u: ", i);
4273           print_inline_rtx (dump_file, reg_equiv_init (i), 20);
4274           fprintf (dump_file, "\n");
4275         }
4276 }
4277
4278 /* Indicate that we no longer have known memory locations or constants.
4279    Free all data involved in tracking these.  */
4280
4281 static void
4282 free_reg_equiv (void)
4283 {
4284   int i;
4285
4286   free (offsets_known_at);
4287   free (offsets_at);
4288   offsets_at = 0;
4289   offsets_known_at = 0;
4290
4291   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4292     if (reg_equiv_alt_mem_list (i))
4293       free_EXPR_LIST_list (&reg_equiv_alt_mem_list (i));
4294   vec_free (reg_equivs);
4295 }
4296 \f
4297 /* Kick all pseudos out of hard register REGNO.
4298
4299    If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4300    because we found we can't eliminate some register.  In the case, no pseudos
4301    are allowed to be in the register, even if they are only in a block that
4302    doesn't require spill registers, unlike the case when we are spilling this
4303    hard reg to produce another spill register.
4304
4305    Return nonzero if any pseudos needed to be kicked out.  */
4306
4307 static void
4308 spill_hard_reg (unsigned int regno, int cant_eliminate)
4309 {
4310   int i;
4311
4312   if (cant_eliminate)
4313     {
4314       SET_HARD_REG_BIT (bad_spill_regs_global, regno);
4315       df_set_regs_ever_live (regno, true);
4316     }
4317
4318   /* Spill every pseudo reg that was allocated to this reg
4319      or to something that overlaps this reg.  */
4320
4321   for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4322     if (reg_renumber[i] >= 0
4323         && (unsigned int) reg_renumber[i] <= regno
4324         && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
4325       SET_REGNO_REG_SET (&spilled_pseudos, i);
4326 }
4327
4328 /* After find_reload_regs has been run for all insn that need reloads,
4329    and/or spill_hard_regs was called, this function is used to actually
4330    spill pseudo registers and try to reallocate them.  It also sets up the
4331    spill_regs array for use by choose_reload_regs.  */
4332
4333 static int
4334 finish_spills (int global)
4335 {
4336   struct insn_chain *chain;
4337   int something_changed = 0;
4338   unsigned i;
4339   reg_set_iterator rsi;
4340
4341   /* Build the spill_regs array for the function.  */
4342   /* If there are some registers still to eliminate and one of the spill regs
4343      wasn't ever used before, additional stack space may have to be
4344      allocated to store this register.  Thus, we may have changed the offset
4345      between the stack and frame pointers, so mark that something has changed.
4346
4347      One might think that we need only set VAL to 1 if this is a call-used
4348      register.  However, the set of registers that must be saved by the
4349      prologue is not identical to the call-used set.  For example, the
4350      register used by the call insn for the return PC is a call-used register,
4351      but must be saved by the prologue.  */
4352
4353   n_spills = 0;
4354   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4355     if (TEST_HARD_REG_BIT (used_spill_regs, i))
4356       {
4357         spill_reg_order[i] = n_spills;
4358         spill_regs[n_spills++] = i;
4359         if (num_eliminable && ! df_regs_ever_live_p (i))
4360           something_changed = 1;
4361         df_set_regs_ever_live (i, true);
4362       }
4363     else
4364       spill_reg_order[i] = -1;
4365
4366   EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
4367     if (! ira_conflicts_p || reg_renumber[i] >= 0)
4368       {
4369         /* Record the current hard register the pseudo is allocated to
4370            in pseudo_previous_regs so we avoid reallocating it to the
4371            same hard reg in a later pass.  */
4372         gcc_assert (reg_renumber[i] >= 0);
4373
4374         SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
4375         /* Mark it as no longer having a hard register home.  */
4376         reg_renumber[i] = -1;
4377         if (ira_conflicts_p)
4378           /* Inform IRA about the change.  */
4379           ira_mark_allocation_change (i);
4380         /* We will need to scan everything again.  */
4381         something_changed = 1;
4382       }
4383
4384   /* Retry global register allocation if possible.  */
4385   if (global && ira_conflicts_p)
4386     {
4387       unsigned int n;
4388
4389       memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
4390       /* For every insn that needs reloads, set the registers used as spill
4391          regs in pseudo_forbidden_regs for every pseudo live across the
4392          insn.  */
4393       for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4394         {
4395           EXECUTE_IF_SET_IN_REG_SET
4396             (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
4397             {
4398               IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4399                                 chain->used_spill_regs);
4400             }
4401           EXECUTE_IF_SET_IN_REG_SET
4402             (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4403             {
4404               IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4405                                 chain->used_spill_regs);
4406             }
4407         }
4408
4409       /* Retry allocating the pseudos spilled in IRA and the
4410          reload.  For each reg, merge the various reg sets that
4411          indicate which hard regs can't be used, and call
4412          ira_reassign_pseudos.  */
4413       for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4414         if (reg_old_renumber[i] != reg_renumber[i])
4415           {
4416             if (reg_renumber[i] < 0)
4417               temp_pseudo_reg_arr[n++] = i;
4418             else
4419               CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4420           }
4421       if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4422                                 bad_spill_regs_global,
4423                                 pseudo_forbidden_regs, pseudo_previous_regs,
4424                                 &spilled_pseudos))
4425         something_changed = 1;
4426     }
4427   /* Fix up the register information in the insn chain.
4428      This involves deleting those of the spilled pseudos which did not get
4429      a new hard register home from the live_{before,after} sets.  */
4430   for (chain = reload_insn_chain; chain; chain = chain->next)
4431     {
4432       HARD_REG_SET used_by_pseudos;
4433       HARD_REG_SET used_by_pseudos2;
4434
4435       if (! ira_conflicts_p)
4436         {
4437           /* Don't do it for IRA because IRA and the reload still can
4438              assign hard registers to the spilled pseudos on next
4439              reload iterations.  */
4440           AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4441           AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4442         }
4443       /* Mark any unallocated hard regs as available for spills.  That
4444          makes inheritance work somewhat better.  */
4445       if (chain->need_reload)
4446         {
4447           REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4448           REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4449           IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4450
4451           compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4452           compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4453           /* Value of chain->used_spill_regs from previous iteration
4454              may be not included in the value calculated here because
4455              of possible removing caller-saves insns (see function
4456              delete_caller_save_insns.  */
4457           COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4458           AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4459         }
4460     }
4461
4462   CLEAR_REG_SET (&changed_allocation_pseudos);
4463   /* Let alter_reg modify the reg rtx's for the modified pseudos.  */
4464   for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4465     {
4466       int regno = reg_renumber[i];
4467       if (reg_old_renumber[i] == regno)
4468         continue;
4469
4470       SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4471
4472       alter_reg (i, reg_old_renumber[i], false);
4473       reg_old_renumber[i] = regno;
4474       if (dump_file)
4475         {
4476           if (regno == -1)
4477             fprintf (dump_file, " Register %d now on stack.\n\n", i);
4478           else
4479             fprintf (dump_file, " Register %d now in %d.\n\n",
4480                      i, reg_renumber[i]);
4481         }
4482     }
4483
4484   return something_changed;
4485 }
4486 \f
4487 /* Find all paradoxical subregs within X and update reg_max_ref_width.  */
4488
4489 static void
4490 scan_paradoxical_subregs (rtx x)
4491 {
4492   int i;
4493   const char *fmt;
4494   enum rtx_code code = GET_CODE (x);
4495
4496   switch (code)
4497     {
4498     case REG:
4499     case CONST:
4500     case SYMBOL_REF:
4501     case LABEL_REF:
4502     CASE_CONST_ANY:
4503     case CC0:
4504     case PC:
4505     case USE:
4506     case CLOBBER:
4507       return;
4508
4509     case SUBREG:
4510       if (REG_P (SUBREG_REG (x))
4511           && (GET_MODE_SIZE (GET_MODE (x))
4512               > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4513         {
4514           reg_max_ref_width[REGNO (SUBREG_REG (x))]
4515             = GET_MODE_SIZE (GET_MODE (x));
4516           mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4517         }
4518       return;
4519
4520     default:
4521       break;
4522     }
4523
4524   fmt = GET_RTX_FORMAT (code);
4525   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4526     {
4527       if (fmt[i] == 'e')
4528         scan_paradoxical_subregs (XEXP (x, i));
4529       else if (fmt[i] == 'E')
4530         {
4531           int j;
4532           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4533             scan_paradoxical_subregs (XVECEXP (x, i, j));
4534         }
4535     }
4536 }
4537
4538 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4539    If *OP_PTR is a paradoxical subreg, try to remove that subreg
4540    and apply the corresponding narrowing subreg to *OTHER_PTR.
4541    Return true if the operands were changed, false otherwise.  */
4542
4543 static bool
4544 strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
4545 {
4546   rtx op, inner, other, tem;
4547
4548   op = *op_ptr;
4549   if (!paradoxical_subreg_p (op))
4550     return false;
4551   inner = SUBREG_REG (op);
4552
4553   other = *other_ptr;
4554   tem = gen_lowpart_common (GET_MODE (inner), other);
4555   if (!tem)
4556     return false;
4557
4558   /* If the lowpart operation turned a hard register into a subreg,
4559      rather than simplifying it to another hard register, then the
4560      mode change cannot be properly represented.  For example, OTHER
4561      might be valid in its current mode, but not in the new one.  */
4562   if (GET_CODE (tem) == SUBREG
4563       && REG_P (other)
4564       && HARD_REGISTER_P (other))
4565     return false;
4566
4567   *op_ptr = inner;
4568   *other_ptr = tem;
4569   return true;
4570 }
4571 \f
4572 /* A subroutine of reload_as_needed.  If INSN has a REG_EH_REGION note,
4573    examine all of the reload insns between PREV and NEXT exclusive, and
4574    annotate all that may trap.  */
4575
4576 static void
4577 fixup_eh_region_note (rtx_insn *insn, rtx_insn *prev, rtx_insn *next)
4578 {
4579   rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4580   if (note == NULL)
4581     return;
4582   if (!insn_could_throw_p (insn))
4583     remove_note (insn, note);
4584   copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4585 }
4586
4587 /* Reload pseudo-registers into hard regs around each insn as needed.
4588    Additional register load insns are output before the insn that needs it
4589    and perhaps store insns after insns that modify the reloaded pseudo reg.
4590
4591    reg_last_reload_reg and reg_reloaded_contents keep track of
4592    which registers are already available in reload registers.
4593    We update these for the reloads that we perform,
4594    as the insns are scanned.  */
4595
4596 static void
4597 reload_as_needed (int live_known)
4598 {
4599   struct insn_chain *chain;
4600 #if defined (AUTO_INC_DEC)
4601   int i;
4602 #endif
4603   rtx_note *marker;
4604
4605   memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4606   memset (spill_reg_store, 0, sizeof spill_reg_store);
4607   reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4608   INIT_REG_SET (&reg_has_output_reload);
4609   CLEAR_HARD_REG_SET (reg_reloaded_valid);
4610   CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4611
4612   set_initial_elim_offsets ();
4613
4614   /* Generate a marker insn that we will move around.  */
4615   marker = emit_note (NOTE_INSN_DELETED);
4616   unlink_insn_chain (marker, marker);
4617
4618   for (chain = reload_insn_chain; chain; chain = chain->next)
4619     {
4620       rtx_insn *prev = 0;
4621       rtx_insn *insn = chain->insn;
4622       rtx_insn *old_next = NEXT_INSN (insn);
4623 #ifdef AUTO_INC_DEC
4624       rtx_insn *old_prev = PREV_INSN (insn);
4625 #endif
4626
4627       if (will_delete_init_insn_p (insn))
4628         continue;
4629
4630       /* If we pass a label, copy the offsets from the label information
4631          into the current offsets of each elimination.  */
4632       if (LABEL_P (insn))
4633         set_offsets_for_label (insn);
4634
4635       else if (INSN_P (insn))
4636         {
4637           regset_head regs_to_forget;
4638           INIT_REG_SET (&regs_to_forget);
4639           note_stores (PATTERN (insn), forget_old_reloads_1, &regs_to_forget);
4640
4641           /* If this is a USE and CLOBBER of a MEM, ensure that any
4642              references to eliminable registers have been removed.  */
4643
4644           if ((GET_CODE (PATTERN (insn)) == USE
4645                || GET_CODE (PATTERN (insn)) == CLOBBER)
4646               && MEM_P (XEXP (PATTERN (insn), 0)))
4647             XEXP (XEXP (PATTERN (insn), 0), 0)
4648               = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4649                                 GET_MODE (XEXP (PATTERN (insn), 0)),
4650                                 NULL_RTX);
4651
4652           /* If we need to do register elimination processing, do so.
4653              This might delete the insn, in which case we are done.  */
4654           if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4655             {
4656               eliminate_regs_in_insn (insn, 1);
4657               if (NOTE_P (insn))
4658                 {
4659                   update_eliminable_offsets ();
4660                   CLEAR_REG_SET (&regs_to_forget);
4661                   continue;
4662                 }
4663             }
4664
4665           /* If need_elim is nonzero but need_reload is zero, one might think
4666              that we could simply set n_reloads to 0.  However, find_reloads
4667              could have done some manipulation of the insn (such as swapping
4668              commutative operands), and these manipulations are lost during
4669              the first pass for every insn that needs register elimination.
4670              So the actions of find_reloads must be redone here.  */
4671
4672           if (! chain->need_elim && ! chain->need_reload
4673               && ! chain->need_operand_change)
4674             n_reloads = 0;
4675           /* First find the pseudo regs that must be reloaded for this insn.
4676              This info is returned in the tables reload_... (see reload.h).
4677              Also modify the body of INSN by substituting RELOAD
4678              rtx's for those pseudo regs.  */
4679           else
4680             {
4681               CLEAR_REG_SET (&reg_has_output_reload);
4682               CLEAR_HARD_REG_SET (reg_is_output_reload);
4683
4684               find_reloads (insn, 1, spill_indirect_levels, live_known,
4685                             spill_reg_order);
4686             }
4687
4688           if (n_reloads > 0)
4689             {
4690               rtx_insn *next = NEXT_INSN (insn);
4691
4692               /* ??? PREV can get deleted by reload inheritance.
4693                  Work around this by emitting a marker note.  */
4694               prev = PREV_INSN (insn);
4695               reorder_insns_nobb (marker, marker, prev);
4696
4697               /* Now compute which reload regs to reload them into.  Perhaps
4698                  reusing reload regs from previous insns, or else output
4699                  load insns to reload them.  Maybe output store insns too.
4700                  Record the choices of reload reg in reload_reg_rtx.  */
4701               choose_reload_regs (chain);
4702
4703               /* Generate the insns to reload operands into or out of
4704                  their reload regs.  */
4705               emit_reload_insns (chain);
4706
4707               /* Substitute the chosen reload regs from reload_reg_rtx
4708                  into the insn's body (or perhaps into the bodies of other
4709                  load and store insn that we just made for reloading
4710                  and that we moved the structure into).  */
4711               subst_reloads (insn);
4712
4713               prev = PREV_INSN (marker);
4714               unlink_insn_chain (marker, marker);
4715
4716               /* Adjust the exception region notes for loads and stores.  */
4717               if (cfun->can_throw_non_call_exceptions && !CALL_P (insn))
4718                 fixup_eh_region_note (insn, prev, next);
4719
4720               /* Adjust the location of REG_ARGS_SIZE.  */
4721               rtx p = find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX);
4722               if (p)
4723                 {
4724                   remove_note (insn, p);
4725                   fixup_args_size_notes (prev, PREV_INSN (next),
4726                                          INTVAL (XEXP (p, 0)));
4727                 }
4728
4729               /* If this was an ASM, make sure that all the reload insns
4730                  we have generated are valid.  If not, give an error
4731                  and delete them.  */
4732               if (asm_noperands (PATTERN (insn)) >= 0)
4733                 for (rtx_insn *p = NEXT_INSN (prev);
4734                      p != next;
4735                      p = NEXT_INSN (p))
4736                   if (p != insn && INSN_P (p)
4737                       && GET_CODE (PATTERN (p)) != USE
4738                       && (recog_memoized (p) < 0
4739                           || (extract_insn (p),
4740                               !(constrain_operands (1,
4741                                   get_enabled_alternatives (p))))))
4742                     {
4743                       error_for_asm (insn,
4744                                      "%<asm%> operand requires "
4745                                      "impossible reload");
4746                       delete_insn (p);
4747                     }
4748             }
4749
4750           if (num_eliminable && chain->need_elim)
4751             update_eliminable_offsets ();
4752
4753           /* Any previously reloaded spilled pseudo reg, stored in this insn,
4754              is no longer validly lying around to save a future reload.
4755              Note that this does not detect pseudos that were reloaded
4756              for this insn in order to be stored in
4757              (obeying register constraints).  That is correct; such reload
4758              registers ARE still valid.  */
4759           forget_marked_reloads (&regs_to_forget);
4760           CLEAR_REG_SET (&regs_to_forget);
4761
4762           /* There may have been CLOBBER insns placed after INSN.  So scan
4763              between INSN and NEXT and use them to forget old reloads.  */
4764           for (rtx_insn *x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4765             if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4766               note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4767
4768 #ifdef AUTO_INC_DEC
4769           /* Likewise for regs altered by auto-increment in this insn.
4770              REG_INC notes have been changed by reloading:
4771              find_reloads_address_1 records substitutions for them,
4772              which have been performed by subst_reloads above.  */
4773           for (i = n_reloads - 1; i >= 0; i--)
4774             {
4775               rtx in_reg = rld[i].in_reg;
4776               if (in_reg)
4777                 {
4778                   enum rtx_code code = GET_CODE (in_reg);
4779                   /* PRE_INC / PRE_DEC will have the reload register ending up
4780                      with the same value as the stack slot, but that doesn't
4781                      hold true for POST_INC / POST_DEC.  Either we have to
4782                      convert the memory access to a true POST_INC / POST_DEC,
4783                      or we can't use the reload register for inheritance.  */
4784                   if ((code == POST_INC || code == POST_DEC)
4785                       && TEST_HARD_REG_BIT (reg_reloaded_valid,
4786                                             REGNO (rld[i].reg_rtx))
4787                       /* Make sure it is the inc/dec pseudo, and not
4788                          some other (e.g. output operand) pseudo.  */
4789                       && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4790                           == REGNO (XEXP (in_reg, 0))))
4791
4792                     {
4793                       rtx reload_reg = rld[i].reg_rtx;
4794                       machine_mode mode = GET_MODE (reload_reg);
4795                       int n = 0;
4796                       rtx_insn *p;
4797
4798                       for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4799                         {
4800                           /* We really want to ignore REG_INC notes here, so
4801                              use PATTERN (p) as argument to reg_set_p .  */
4802                           if (reg_set_p (reload_reg, PATTERN (p)))
4803                             break;
4804                           n = count_occurrences (PATTERN (p), reload_reg, 0);
4805                           if (! n)
4806                             continue;
4807                           if (n == 1)
4808                             {
4809                               rtx replace_reg
4810                                 = gen_rtx_fmt_e (code, mode, reload_reg);
4811
4812                               validate_replace_rtx_group (reload_reg,
4813                                                           replace_reg, p);
4814                               n = verify_changes (0);
4815
4816                               /* We must also verify that the constraints
4817                                  are met after the replacement.  Make sure
4818                                  extract_insn is only called for an insn
4819                                  where the replacements were found to be
4820                                  valid so far. */
4821                               if (n)
4822                                 {
4823                                   extract_insn (p);
4824                                   n = constrain_operands (1,
4825                                     get_enabled_alternatives (p));
4826                                 }
4827
4828                               /* If the constraints were not met, then
4829                                  undo the replacement, else confirm it.  */
4830                               if (!n)
4831                                 cancel_changes (0);
4832                               else
4833                                 confirm_change_group ();
4834                             }
4835                           break;
4836                         }
4837                       if (n == 1)
4838                         {
4839                           add_reg_note (p, REG_INC, reload_reg);
4840                           /* Mark this as having an output reload so that the
4841                              REG_INC processing code below won't invalidate
4842                              the reload for inheritance.  */
4843                           SET_HARD_REG_BIT (reg_is_output_reload,
4844                                             REGNO (reload_reg));
4845                           SET_REGNO_REG_SET (&reg_has_output_reload,
4846                                              REGNO (XEXP (in_reg, 0)));
4847                         }
4848                       else
4849                         forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4850                                               NULL);
4851                     }
4852                   else if ((code == PRE_INC || code == PRE_DEC)
4853                            && TEST_HARD_REG_BIT (reg_reloaded_valid,
4854                                                  REGNO (rld[i].reg_rtx))
4855                            /* Make sure it is the inc/dec pseudo, and not
4856                               some other (e.g. output operand) pseudo.  */
4857                            && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4858                                == REGNO (XEXP (in_reg, 0))))
4859                     {
4860                       SET_HARD_REG_BIT (reg_is_output_reload,
4861                                         REGNO (rld[i].reg_rtx));
4862                       SET_REGNO_REG_SET (&reg_has_output_reload,
4863                                          REGNO (XEXP (in_reg, 0)));
4864                     }
4865                   else if (code == PRE_INC || code == PRE_DEC
4866                            || code == POST_INC || code == POST_DEC)
4867                     {
4868                       int in_regno = REGNO (XEXP (in_reg, 0));
4869
4870                       if (reg_last_reload_reg[in_regno] != NULL_RTX)
4871                         {
4872                           int in_hard_regno;
4873                           bool forget_p = true;
4874
4875                           in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4876                           if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4877                                                  in_hard_regno))
4878                             {
4879                               for (rtx_insn *x = (old_prev ?
4880                                                   NEXT_INSN (old_prev) : insn);
4881                                    x != old_next;
4882                                    x = NEXT_INSN (x))
4883                                 if (x == reg_reloaded_insn[in_hard_regno])
4884                                   {
4885                                     forget_p = false;
4886                                     break;
4887                                   }
4888                             }
4889                           /* If for some reasons, we didn't set up
4890                              reg_last_reload_reg in this insn,
4891                              invalidate inheritance from previous
4892                              insns for the incremented/decremented
4893                              register.  Such registers will be not in
4894                              reg_has_output_reload.  Invalidate it
4895                              also if the corresponding element in
4896                              reg_reloaded_insn is also
4897                              invalidated.  */
4898                           if (forget_p)
4899                             forget_old_reloads_1 (XEXP (in_reg, 0),
4900                                                   NULL_RTX, NULL);
4901                         }
4902                     }
4903                 }
4904             }
4905           /* If a pseudo that got a hard register is auto-incremented,
4906              we must purge records of copying it into pseudos without
4907              hard registers.  */
4908           for (rtx x = REG_NOTES (insn); x; x = XEXP (x, 1))
4909             if (REG_NOTE_KIND (x) == REG_INC)
4910               {
4911                 /* See if this pseudo reg was reloaded in this insn.
4912                    If so, its last-reload info is still valid
4913                    because it is based on this insn's reload.  */
4914                 for (i = 0; i < n_reloads; i++)
4915                   if (rld[i].out == XEXP (x, 0))
4916                     break;
4917
4918                 if (i == n_reloads)
4919                   forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4920               }
4921 #endif
4922         }
4923       /* A reload reg's contents are unknown after a label.  */
4924       if (LABEL_P (insn))
4925         CLEAR_HARD_REG_SET (reg_reloaded_valid);
4926
4927       /* Don't assume a reload reg is still good after a call insn
4928          if it is a call-used reg, or if it contains a value that will
4929          be partially clobbered by the call.  */
4930       else if (CALL_P (insn))
4931         {
4932           AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4933           AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4934
4935           /* If this is a call to a setjmp-type function, we must not
4936              reuse any reload reg contents across the call; that will
4937              just be clobbered by other uses of the register in later
4938              code, before the longjmp.  */
4939           if (find_reg_note (insn, REG_SETJMP, NULL_RTX))
4940             CLEAR_HARD_REG_SET (reg_reloaded_valid);
4941         }
4942     }
4943
4944   /* Clean up.  */
4945   free (reg_last_reload_reg);
4946   CLEAR_REG_SET (&reg_has_output_reload);
4947 }
4948
4949 /* Discard all record of any value reloaded from X,
4950    or reloaded in X from someplace else;
4951    unless X is an output reload reg of the current insn.
4952
4953    X may be a hard reg (the reload reg)
4954    or it may be a pseudo reg that was reloaded from.
4955
4956    When DATA is non-NULL just mark the registers in regset
4957    to be forgotten later.  */
4958
4959 static void
4960 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4961                       void *data)
4962 {
4963   unsigned int regno;
4964   unsigned int nr;
4965   regset regs = (regset) data;
4966
4967   /* note_stores does give us subregs of hard regs,
4968      subreg_regno_offset requires a hard reg.  */
4969   while (GET_CODE (x) == SUBREG)
4970     {
4971       /* We ignore the subreg offset when calculating the regno,
4972          because we are using the entire underlying hard register
4973          below.  */
4974       x = SUBREG_REG (x);
4975     }
4976
4977   if (!REG_P (x))
4978     return;
4979
4980   regno = REGNO (x);
4981
4982   if (regno >= FIRST_PSEUDO_REGISTER)
4983     nr = 1;
4984   else
4985     {
4986       unsigned int i;
4987
4988       nr = hard_regno_nregs[regno][GET_MODE (x)];
4989       /* Storing into a spilled-reg invalidates its contents.
4990          This can happen if a block-local pseudo is allocated to that reg
4991          and it wasn't spilled because this block's total need is 0.
4992          Then some insn might have an optional reload and use this reg.  */
4993       if (!regs)
4994         for (i = 0; i < nr; i++)
4995           /* But don't do this if the reg actually serves as an output
4996              reload reg in the current instruction.  */
4997           if (n_reloads == 0
4998               || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4999             {
5000               CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
5001               spill_reg_store[regno + i] = 0;
5002             }
5003     }
5004
5005   if (regs)
5006     while (nr-- > 0)
5007       SET_REGNO_REG_SET (regs, regno + nr);
5008   else
5009     {
5010       /* Since value of X has changed,
5011          forget any value previously copied from it.  */
5012
5013       while (nr-- > 0)
5014         /* But don't forget a copy if this is the output reload
5015            that establishes the copy's validity.  */
5016         if (n_reloads == 0
5017             || !REGNO_REG_SET_P (&reg_has_output_reload, regno + nr))
5018           reg_last_reload_reg[regno + nr] = 0;
5019      }
5020 }
5021
5022 /* Forget the reloads marked in regset by previous function.  */
5023 static void
5024 forget_marked_reloads (regset regs)
5025 {
5026   unsigned int reg;
5027   reg_set_iterator rsi;
5028   EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
5029     {
5030       if (reg < FIRST_PSEUDO_REGISTER
5031           /* But don't do this if the reg actually serves as an output
5032              reload reg in the current instruction.  */
5033           && (n_reloads == 0
5034               || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
5035           {
5036             CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
5037             spill_reg_store[reg] = 0;
5038           }
5039       if (n_reloads == 0
5040           || !REGNO_REG_SET_P (&reg_has_output_reload, reg))
5041         reg_last_reload_reg[reg] = 0;
5042     }
5043 }
5044 \f
5045 /* The following HARD_REG_SETs indicate when each hard register is
5046    used for a reload of various parts of the current insn.  */
5047
5048 /* If reg is unavailable for all reloads.  */
5049 static HARD_REG_SET reload_reg_unavailable;
5050 /* If reg is in use as a reload reg for a RELOAD_OTHER reload.  */
5051 static HARD_REG_SET reload_reg_used;
5052 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I.  */
5053 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
5054 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I.  */
5055 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
5056 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I.  */
5057 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5058 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I.  */
5059 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5060 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I.  */
5061 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5062 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I.  */
5063 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5064 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload.  */
5065 static HARD_REG_SET reload_reg_used_in_op_addr;
5066 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload.  */
5067 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
5068 /* If reg is in use for a RELOAD_FOR_INSN reload.  */
5069 static HARD_REG_SET reload_reg_used_in_insn;
5070 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload.  */
5071 static HARD_REG_SET reload_reg_used_in_other_addr;
5072
5073 /* If reg is in use as a reload reg for any sort of reload.  */
5074 static HARD_REG_SET reload_reg_used_at_all;
5075
5076 /* If reg is use as an inherited reload.  We just mark the first register
5077    in the group.  */
5078 static HARD_REG_SET reload_reg_used_for_inherit;
5079
5080 /* Records which hard regs are used in any way, either as explicit use or
5081    by being allocated to a pseudo during any point of the current insn.  */
5082 static HARD_REG_SET reg_used_in_insn;
5083
5084 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5085    TYPE. MODE is used to indicate how many consecutive regs are
5086    actually used.  */
5087
5088 static void
5089 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
5090                         machine_mode mode)
5091 {
5092   switch (type)
5093     {
5094     case RELOAD_OTHER:
5095       add_to_hard_reg_set (&reload_reg_used, mode, regno);
5096       break;
5097
5098     case RELOAD_FOR_INPUT_ADDRESS:
5099       add_to_hard_reg_set (&reload_reg_used_in_input_addr[opnum], mode, regno);
5100       break;
5101
5102     case RELOAD_FOR_INPADDR_ADDRESS:
5103       add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr[opnum], mode, regno);
5104       break;
5105
5106     case RELOAD_FOR_OUTPUT_ADDRESS:
5107       add_to_hard_reg_set (&reload_reg_used_in_output_addr[opnum], mode, regno);
5108       break;
5109
5110     case RELOAD_FOR_OUTADDR_ADDRESS:
5111       add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr[opnum], mode, regno);
5112       break;
5113
5114     case RELOAD_FOR_OPERAND_ADDRESS:
5115       add_to_hard_reg_set (&reload_reg_used_in_op_addr, mode, regno);
5116       break;
5117
5118     case RELOAD_FOR_OPADDR_ADDR:
5119       add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload, mode, regno);
5120       break;
5121
5122     case RELOAD_FOR_OTHER_ADDRESS:
5123       add_to_hard_reg_set (&reload_reg_used_in_other_addr, mode, regno);
5124       break;
5125
5126     case RELOAD_FOR_INPUT:
5127       add_to_hard_reg_set (&reload_reg_used_in_input[opnum], mode, regno);
5128       break;
5129
5130     case RELOAD_FOR_OUTPUT:
5131       add_to_hard_reg_set (&reload_reg_used_in_output[opnum], mode, regno);
5132       break;
5133
5134     case RELOAD_FOR_INSN:
5135       add_to_hard_reg_set (&reload_reg_used_in_insn,  mode, regno);
5136       break;
5137     }
5138
5139   add_to_hard_reg_set (&reload_reg_used_at_all, mode, regno);
5140 }
5141
5142 /* Similarly, but show REGNO is no longer in use for a reload.  */
5143
5144 static void
5145 clear_reload_reg_in_use (unsigned int regno, int opnum,
5146                          enum reload_type type, machine_mode mode)
5147 {
5148   unsigned int nregs = hard_regno_nregs[regno][mode];
5149   unsigned int start_regno, end_regno, r;
5150   int i;
5151   /* A complication is that for some reload types, inheritance might
5152      allow multiple reloads of the same types to share a reload register.
5153      We set check_opnum if we have to check only reloads with the same
5154      operand number, and check_any if we have to check all reloads.  */
5155   int check_opnum = 0;
5156   int check_any = 0;
5157   HARD_REG_SET *used_in_set;
5158
5159   switch (type)
5160     {
5161     case RELOAD_OTHER:
5162       used_in_set = &reload_reg_used;
5163       break;
5164
5165     case RELOAD_FOR_INPUT_ADDRESS:
5166       used_in_set = &reload_reg_used_in_input_addr[opnum];
5167       break;
5168
5169     case RELOAD_FOR_INPADDR_ADDRESS:
5170       check_opnum = 1;
5171       used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
5172       break;
5173
5174     case RELOAD_FOR_OUTPUT_ADDRESS:
5175       used_in_set = &reload_reg_used_in_output_addr[opnum];
5176       break;
5177
5178     case RELOAD_FOR_OUTADDR_ADDRESS:
5179       check_opnum = 1;
5180       used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
5181       break;
5182
5183     case RELOAD_FOR_OPERAND_ADDRESS:
5184       used_in_set = &reload_reg_used_in_op_addr;
5185       break;
5186
5187     case RELOAD_FOR_OPADDR_ADDR:
5188       check_any = 1;
5189       used_in_set = &reload_reg_used_in_op_addr_reload;
5190       break;
5191
5192     case RELOAD_FOR_OTHER_ADDRESS:
5193       used_in_set = &reload_reg_used_in_other_addr;
5194       check_any = 1;
5195       break;
5196
5197     case RELOAD_FOR_INPUT:
5198       used_in_set = &reload_reg_used_in_input[opnum];
5199       break;
5200
5201     case RELOAD_FOR_OUTPUT:
5202       used_in_set = &reload_reg_used_in_output[opnum];
5203       break;
5204
5205     case RELOAD_FOR_INSN:
5206       used_in_set = &reload_reg_used_in_insn;
5207       break;
5208     default:
5209       gcc_unreachable ();
5210     }
5211   /* We resolve conflicts with remaining reloads of the same type by
5212      excluding the intervals of reload registers by them from the
5213      interval of freed reload registers.  Since we only keep track of
5214      one set of interval bounds, we might have to exclude somewhat
5215      more than what would be necessary if we used a HARD_REG_SET here.
5216      But this should only happen very infrequently, so there should
5217      be no reason to worry about it.  */
5218
5219   start_regno = regno;
5220   end_regno = regno + nregs;
5221   if (check_opnum || check_any)
5222     {
5223       for (i = n_reloads - 1; i >= 0; i--)
5224         {
5225           if (rld[i].when_needed == type
5226               && (check_any || rld[i].opnum == opnum)
5227               && rld[i].reg_rtx)
5228             {
5229               unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
5230               unsigned int conflict_end
5231                 = end_hard_regno (rld[i].mode, conflict_start);
5232
5233               /* If there is an overlap with the first to-be-freed register,
5234                  adjust the interval start.  */
5235               if (conflict_start <= start_regno && conflict_end > start_regno)
5236                 start_regno = conflict_end;
5237               /* Otherwise, if there is a conflict with one of the other
5238                  to-be-freed registers, adjust the interval end.  */
5239               if (conflict_start > start_regno && conflict_start < end_regno)
5240                 end_regno = conflict_start;
5241             }
5242         }
5243     }
5244
5245   for (r = start_regno; r < end_regno; r++)
5246     CLEAR_HARD_REG_BIT (*used_in_set, r);
5247 }
5248
5249 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5250    specified by OPNUM and TYPE.  */
5251
5252 static int
5253 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
5254 {
5255   int i;
5256
5257   /* In use for a RELOAD_OTHER means it's not available for anything.  */
5258   if (TEST_HARD_REG_BIT (reload_reg_used, regno)
5259       || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5260     return 0;
5261
5262   switch (type)
5263     {
5264     case RELOAD_OTHER:
5265       /* In use for anything means we can't use it for RELOAD_OTHER.  */
5266       if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
5267           || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5268           || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5269           || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5270         return 0;
5271
5272       for (i = 0; i < reload_n_operands; i++)
5273         if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5274             || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5275             || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5276             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5277             || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5278             || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5279           return 0;
5280
5281       return 1;
5282
5283     case RELOAD_FOR_INPUT:
5284       if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5285           || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
5286         return 0;
5287
5288       if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5289         return 0;
5290
5291       /* If it is used for some other input, can't use it.  */
5292       for (i = 0; i < reload_n_operands; i++)
5293         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5294           return 0;
5295
5296       /* If it is used in a later operand's address, can't use it.  */
5297       for (i = opnum + 1; i < reload_n_operands; i++)
5298         if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5299             || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5300           return 0;
5301
5302       return 1;
5303
5304     case RELOAD_FOR_INPUT_ADDRESS:
5305       /* Can't use a register if it is used for an input address for this
5306          operand or used as an input in an earlier one.  */
5307       if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
5308           || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5309         return 0;
5310
5311       for (i = 0; i < opnum; i++)
5312         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5313           return 0;
5314
5315       return 1;
5316
5317     case RELOAD_FOR_INPADDR_ADDRESS:
5318       /* Can't use a register if it is used for an input address
5319          for this operand or used as an input in an earlier
5320          one.  */
5321       if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5322         return 0;
5323
5324       for (i = 0; i < opnum; i++)
5325         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5326           return 0;
5327
5328       return 1;
5329
5330     case RELOAD_FOR_OUTPUT_ADDRESS:
5331       /* Can't use a register if it is used for an output address for this
5332          operand or used as an output in this or a later operand.  Note
5333          that multiple output operands are emitted in reverse order, so
5334          the conflicting ones are those with lower indices.  */
5335       if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
5336         return 0;
5337
5338       for (i = 0; i <= opnum; i++)
5339         if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5340           return 0;
5341
5342       return 1;
5343
5344     case RELOAD_FOR_OUTADDR_ADDRESS:
5345       /* Can't use a register if it is used for an output address
5346          for this operand or used as an output in this or a
5347          later operand.  Note that multiple output operands are
5348          emitted in reverse order, so the conflicting ones are
5349          those with lower indices.  */
5350       if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5351         return 0;
5352
5353       for (i = 0; i <= opnum; i++)
5354         if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5355           return 0;
5356
5357       return 1;
5358
5359     case RELOAD_FOR_OPERAND_ADDRESS:
5360       for (i = 0; i < reload_n_operands; i++)
5361         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5362           return 0;
5363
5364       return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5365               && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5366
5367     case RELOAD_FOR_OPADDR_ADDR:
5368       for (i = 0; i < reload_n_operands; i++)
5369         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5370           return 0;
5371
5372       return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5373
5374     case RELOAD_FOR_OUTPUT:
5375       /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5376          outputs, or an operand address for this or an earlier output.
5377          Note that multiple output operands are emitted in reverse order,
5378          so the conflicting ones are those with higher indices.  */
5379       if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5380         return 0;
5381
5382       for (i = 0; i < reload_n_operands; i++)
5383         if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5384           return 0;
5385
5386       for (i = opnum; i < reload_n_operands; i++)
5387         if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5388             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5389           return 0;
5390
5391       return 1;
5392
5393     case RELOAD_FOR_INSN:
5394       for (i = 0; i < reload_n_operands; i++)
5395         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5396             || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5397           return 0;
5398
5399       return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5400               && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5401
5402     case RELOAD_FOR_OTHER_ADDRESS:
5403       return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5404
5405     default:
5406       gcc_unreachable ();
5407     }
5408 }
5409
5410 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5411    the number RELOADNUM, is still available in REGNO at the end of the insn.
5412
5413    We can assume that the reload reg was already tested for availability
5414    at the time it is needed, and we should not check this again,
5415    in case the reg has already been marked in use.  */
5416
5417 static int
5418 reload_reg_reaches_end_p (unsigned int regno, int reloadnum)
5419 {
5420   int opnum = rld[reloadnum].opnum;
5421   enum reload_type type = rld[reloadnum].when_needed;
5422   int i;
5423
5424   /* See if there is a reload with the same type for this operand, using
5425      the same register. This case is not handled by the code below.  */
5426   for (i = reloadnum + 1; i < n_reloads; i++)
5427     {
5428       rtx reg;
5429       int nregs;
5430
5431       if (rld[i].opnum != opnum || rld[i].when_needed != type)
5432         continue;
5433       reg = rld[i].reg_rtx;
5434       if (reg == NULL_RTX)
5435         continue;
5436       nregs = hard_regno_nregs[REGNO (reg)][GET_MODE (reg)];
5437       if (regno >= REGNO (reg) && regno < REGNO (reg) + nregs)
5438         return 0;
5439     }
5440
5441   switch (type)
5442     {
5443     case RELOAD_OTHER:
5444       /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5445          its value must reach the end.  */
5446       return 1;
5447
5448       /* If this use is for part of the insn,
5449          its value reaches if no subsequent part uses the same register.
5450          Just like the above function, don't try to do this with lots
5451          of fallthroughs.  */
5452
5453     case RELOAD_FOR_OTHER_ADDRESS:
5454       /* Here we check for everything else, since these don't conflict
5455          with anything else and everything comes later.  */
5456
5457       for (i = 0; i < reload_n_operands; i++)
5458         if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5459             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5460             || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5461             || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5462             || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5463             || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5464           return 0;
5465
5466       return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5467               && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5468               && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5469               && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5470
5471     case RELOAD_FOR_INPUT_ADDRESS:
5472     case RELOAD_FOR_INPADDR_ADDRESS:
5473       /* Similar, except that we check only for this and subsequent inputs
5474          and the address of only subsequent inputs and we do not need
5475          to check for RELOAD_OTHER objects since they are known not to
5476          conflict.  */
5477
5478       for (i = opnum; i < reload_n_operands; i++)
5479         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5480           return 0;
5481
5482       /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5483          could be killed if the register is also used by reload with type
5484          RELOAD_FOR_INPUT_ADDRESS, so check it.  */
5485       if (type == RELOAD_FOR_INPADDR_ADDRESS
5486           && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno))
5487         return 0;
5488
5489       for (i = opnum + 1; i < reload_n_operands; i++)
5490         if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5491             || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5492           return 0;
5493
5494       for (i = 0; i < reload_n_operands; i++)
5495         if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5496             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5497             || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5498           return 0;
5499
5500       if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5501         return 0;
5502
5503       return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5504               && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5505               && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5506
5507     case RELOAD_FOR_INPUT:
5508       /* Similar to input address, except we start at the next operand for
5509          both input and input address and we do not check for
5510          RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5511          would conflict.  */
5512
5513       for (i = opnum + 1; i < reload_n_operands; i++)
5514         if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5515             || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5516             || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5517           return 0;
5518
5519       /* ... fall through ...  */
5520
5521     case RELOAD_FOR_OPERAND_ADDRESS:
5522       /* Check outputs and their addresses.  */
5523
5524       for (i = 0; i < reload_n_operands; i++)
5525         if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5526             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5527             || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5528           return 0;
5529
5530       return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5531
5532     case RELOAD_FOR_OPADDR_ADDR:
5533       for (i = 0; i < reload_n_operands; i++)
5534         if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5535             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5536             || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5537           return 0;
5538
5539       return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5540               && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5541               && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5542
5543     case RELOAD_FOR_INSN:
5544       /* These conflict with other outputs with RELOAD_OTHER.  So
5545          we need only check for output addresses.  */
5546
5547       opnum = reload_n_operands;
5548
5549       /* ... fall through ...  */
5550
5551     case RELOAD_FOR_OUTPUT:
5552     case RELOAD_FOR_OUTPUT_ADDRESS:
5553     case RELOAD_FOR_OUTADDR_ADDRESS:
5554       /* We already know these can't conflict with a later output.  So the
5555          only thing to check are later output addresses.
5556          Note that multiple output operands are emitted in reverse order,
5557          so the conflicting ones are those with lower indices.  */
5558       for (i = 0; i < opnum; i++)
5559         if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5560             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5561           return 0;
5562
5563       /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5564          could be killed if the register is also used by reload with type
5565          RELOAD_FOR_OUTPUT_ADDRESS, so check it.  */
5566       if (type == RELOAD_FOR_OUTADDR_ADDRESS
5567           && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5568         return 0;
5569
5570       return 1;
5571
5572     default:
5573       gcc_unreachable ();
5574     }
5575 }
5576
5577 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5578    every register in REG.  */
5579
5580 static bool
5581 reload_reg_rtx_reaches_end_p (rtx reg, int reloadnum)
5582 {
5583   unsigned int i;
5584
5585   for (i = REGNO (reg); i < END_REGNO (reg); i++)
5586     if (!reload_reg_reaches_end_p (i, reloadnum))
5587       return false;
5588   return true;
5589 }
5590 \f
5591
5592 /*  Returns whether R1 and R2 are uniquely chained: the value of one
5593     is used by the other, and that value is not used by any other
5594     reload for this insn.  This is used to partially undo the decision
5595     made in find_reloads when in the case of multiple
5596     RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5597     RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5598     reloads.  This code tries to avoid the conflict created by that
5599     change.  It might be cleaner to explicitly keep track of which
5600     RELOAD_FOR_OPADDR_ADDR reload is associated with which
5601     RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5602     this after the fact. */
5603 static bool
5604 reloads_unique_chain_p (int r1, int r2)
5605 {
5606   int i;
5607
5608   /* We only check input reloads.  */
5609   if (! rld[r1].in || ! rld[r2].in)
5610     return false;
5611
5612   /* Avoid anything with output reloads.  */
5613   if (rld[r1].out || rld[r2].out)
5614     return false;
5615
5616   /* "chained" means one reload is a component of the other reload,
5617      not the same as the other reload.  */
5618   if (rld[r1].opnum != rld[r2].opnum
5619       || rtx_equal_p (rld[r1].in, rld[r2].in)
5620       || rld[r1].optional || rld[r2].optional
5621       || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5622             || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5623     return false;
5624
5625   /* The following loop assumes that r1 is the reload that feeds r2.  */
5626   if (r1 > r2)
5627     {
5628       int tmp = r2;
5629       r2 = r1;
5630       r1 = tmp;
5631     }
5632
5633   for (i = 0; i < n_reloads; i ++)
5634     /* Look for input reloads that aren't our two */
5635     if (i != r1 && i != r2 && rld[i].in)
5636       {
5637         /* If our reload is mentioned at all, it isn't a simple chain.  */
5638         if (reg_mentioned_p (rld[r1].in, rld[i].in))
5639           return false;
5640       }
5641   return true;
5642 }
5643
5644 /* The recursive function change all occurrences of WHAT in *WHERE
5645    to REPL.  */
5646 static void
5647 substitute (rtx *where, const_rtx what, rtx repl)
5648 {
5649   const char *fmt;
5650   int i;
5651   enum rtx_code code;
5652
5653   if (*where == 0)
5654     return;
5655
5656   if (*where == what || rtx_equal_p (*where, what))
5657     {
5658       /* Record the location of the changed rtx.  */
5659       substitute_stack.safe_push (where);
5660       *where = repl;
5661       return;
5662     }
5663
5664   code = GET_CODE (*where);
5665   fmt = GET_RTX_FORMAT (code);
5666   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5667     {
5668       if (fmt[i] == 'E')
5669         {
5670           int j;
5671
5672           for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5673             substitute (&XVECEXP (*where, i, j), what, repl);
5674         }
5675       else if (fmt[i] == 'e')
5676         substitute (&XEXP (*where, i), what, repl);
5677     }
5678 }
5679
5680 /* The function returns TRUE if chain of reload R1 and R2 (in any
5681    order) can be evaluated without usage of intermediate register for
5682    the reload containing another reload.  It is important to see
5683    gen_reload to understand what the function is trying to do.  As an
5684    example, let us have reload chain
5685
5686       r2: const
5687       r1: <something> + const
5688
5689    and reload R2 got reload reg HR.  The function returns true if
5690    there is a correct insn HR = HR + <something>.  Otherwise,
5691    gen_reload will use intermediate register (and this is the reload
5692    reg for R1) to reload <something>.
5693
5694    We need this function to find a conflict for chain reloads.  In our
5695    example, if HR = HR + <something> is incorrect insn, then we cannot
5696    use HR as a reload register for R2.  If we do use it then we get a
5697    wrong code:
5698
5699       HR = const
5700       HR = <something>
5701       HR = HR + HR
5702
5703 */
5704 static bool
5705 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5706 {
5707   /* Assume other cases in gen_reload are not possible for
5708      chain reloads or do need an intermediate hard registers.  */
5709   bool result = true;
5710   int regno, n, code;
5711   rtx out, in;
5712   rtx_insn *insn;
5713   rtx_insn *last = get_last_insn ();
5714
5715   /* Make r2 a component of r1.  */
5716   if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5717     {
5718       n = r1;
5719       r1 = r2;
5720       r2 = n;
5721     }
5722   gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5723   regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5724   gcc_assert (regno >= 0);
5725   out = gen_rtx_REG (rld[r1].mode, regno);
5726   in = rld[r1].in;
5727   substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5728
5729   /* If IN is a paradoxical SUBREG, remove it and try to put the
5730      opposite SUBREG on OUT.  Likewise for a paradoxical SUBREG on OUT.  */
5731   strip_paradoxical_subreg (&in, &out);
5732
5733   if (GET_CODE (in) == PLUS
5734       && (REG_P (XEXP (in, 0))
5735           || GET_CODE (XEXP (in, 0)) == SUBREG
5736           || MEM_P (XEXP (in, 0)))
5737       && (REG_P (XEXP (in, 1))
5738           || GET_CODE (XEXP (in, 1)) == SUBREG
5739           || CONSTANT_P (XEXP (in, 1))
5740           || MEM_P (XEXP (in, 1))))
5741     {
5742       insn = emit_insn (gen_rtx_SET (out, in));
5743       code = recog_memoized (insn);
5744       result = false;
5745
5746       if (code >= 0)
5747         {
5748           extract_insn (insn);
5749           /* We want constrain operands to treat this insn strictly in
5750              its validity determination, i.e., the way it would after
5751              reload has completed.  */
5752           result = constrain_operands (1, get_enabled_alternatives (insn));
5753         }
5754
5755       delete_insns_since (last);
5756     }
5757
5758   /* Restore the original value at each changed address within R1.  */
5759   while (!substitute_stack.is_empty ())
5760     {
5761       rtx *where = substitute_stack.pop ();
5762       *where = rld[r2].in;
5763     }
5764
5765   return result;
5766 }
5767
5768 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5769    Return 0 otherwise.
5770
5771    This function uses the same algorithm as reload_reg_free_p above.  */
5772
5773 static int
5774 reloads_conflict (int r1, int r2)
5775 {
5776   enum reload_type r1_type = rld[r1].when_needed;
5777   enum reload_type r2_type = rld[r2].when_needed;
5778   int r1_opnum = rld[r1].opnum;
5779   int r2_opnum = rld[r2].opnum;
5780
5781   /* RELOAD_OTHER conflicts with everything.  */
5782   if (r2_type == RELOAD_OTHER)
5783     return 1;
5784
5785   /* Otherwise, check conflicts differently for each type.  */
5786
5787   switch (r1_type)
5788     {
5789     case RELOAD_FOR_INPUT:
5790       return (r2_type == RELOAD_FOR_INSN
5791               || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5792               || r2_type == RELOAD_FOR_OPADDR_ADDR
5793               || r2_type == RELOAD_FOR_INPUT
5794               || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5795                    || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5796                   && r2_opnum > r1_opnum));
5797
5798     case RELOAD_FOR_INPUT_ADDRESS:
5799       return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5800               || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5801
5802     case RELOAD_FOR_INPADDR_ADDRESS:
5803       return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5804               || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5805
5806     case RELOAD_FOR_OUTPUT_ADDRESS:
5807       return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5808               || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5809
5810     case RELOAD_FOR_OUTADDR_ADDRESS:
5811       return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5812               || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5813
5814     case RELOAD_FOR_OPERAND_ADDRESS:
5815       return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5816               || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5817                   && (!reloads_unique_chain_p (r1, r2)
5818                       || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5819
5820     case RELOAD_FOR_OPADDR_ADDR:
5821       return (r2_type == RELOAD_FOR_INPUT
5822               || r2_type == RELOAD_FOR_OPADDR_ADDR);
5823
5824     case RELOAD_FOR_OUTPUT:
5825       return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5826               || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5827                    || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5828                   && r2_opnum >= r1_opnum));
5829
5830     case RELOAD_FOR_INSN:
5831       return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5832               || r2_type == RELOAD_FOR_INSN
5833               || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5834
5835     case RELOAD_FOR_OTHER_ADDRESS:
5836       return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5837
5838     case RELOAD_OTHER:
5839       return 1;
5840
5841     default:
5842       gcc_unreachable ();
5843     }
5844 }
5845 \f
5846 /* Indexed by reload number, 1 if incoming value
5847    inherited from previous insns.  */
5848 static char reload_inherited[MAX_RELOADS];
5849
5850 /* For an inherited reload, this is the insn the reload was inherited from,
5851    if we know it.  Otherwise, this is 0.  */
5852 static rtx_insn *reload_inheritance_insn[MAX_RELOADS];
5853
5854 /* If nonzero, this is a place to get the value of the reload,
5855    rather than using reload_in.  */
5856 static rtx reload_override_in[MAX_RELOADS];
5857
5858 /* For each reload, the hard register number of the register used,
5859    or -1 if we did not need a register for this reload.  */
5860 static int reload_spill_index[MAX_RELOADS];
5861
5862 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode.  */
5863 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5864
5865 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode.  */
5866 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5867
5868 /* Subroutine of free_for_value_p, used to check a single register.
5869    START_REGNO is the starting regno of the full reload register
5870    (possibly comprising multiple hard registers) that we are considering.  */
5871
5872 static int
5873 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5874                              enum reload_type type, rtx value, rtx out,
5875                              int reloadnum, int ignore_address_reloads)
5876 {
5877   int time1;
5878   /* Set if we see an input reload that must not share its reload register
5879      with any new earlyclobber, but might otherwise share the reload
5880      register with an output or input-output reload.  */
5881   int check_earlyclobber = 0;
5882   int i;
5883   int copy = 0;
5884
5885   if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5886     return 0;
5887
5888   if (out == const0_rtx)
5889     {
5890       copy = 1;
5891       out = NULL_RTX;
5892     }
5893
5894   /* We use some pseudo 'time' value to check if the lifetimes of the
5895      new register use would overlap with the one of a previous reload
5896      that is not read-only or uses a different value.
5897      The 'time' used doesn't have to be linear in any shape or form, just
5898      monotonic.
5899      Some reload types use different 'buckets' for each operand.
5900      So there are MAX_RECOG_OPERANDS different time values for each
5901      such reload type.
5902      We compute TIME1 as the time when the register for the prospective
5903      new reload ceases to be live, and TIME2 for each existing
5904      reload as the time when that the reload register of that reload
5905      becomes live.
5906      Where there is little to be gained by exact lifetime calculations,
5907      we just make conservative assumptions, i.e. a longer lifetime;
5908      this is done in the 'default:' cases.  */
5909   switch (type)
5910     {
5911     case RELOAD_FOR_OTHER_ADDRESS:
5912       /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads.  */
5913       time1 = copy ? 0 : 1;
5914       break;
5915     case RELOAD_OTHER:
5916       time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5917       break;
5918       /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5919          RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT.  By adding 0 / 1 / 2 ,
5920          respectively, to the time values for these, we get distinct time
5921          values.  To get distinct time values for each operand, we have to
5922          multiply opnum by at least three.  We round that up to four because
5923          multiply by four is often cheaper.  */
5924     case RELOAD_FOR_INPADDR_ADDRESS:
5925       time1 = opnum * 4 + 2;
5926       break;
5927     case RELOAD_FOR_INPUT_ADDRESS:
5928       time1 = opnum * 4 + 3;
5929       break;
5930     case RELOAD_FOR_INPUT:
5931       /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5932          executes (inclusive).  */
5933       time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5934       break;
5935     case RELOAD_FOR_OPADDR_ADDR:
5936       /* opnum * 4 + 4
5937          <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5938       time1 = MAX_RECOG_OPERANDS * 4 + 1;
5939       break;
5940     case RELOAD_FOR_OPERAND_ADDRESS:
5941       /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5942          is executed.  */
5943       time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5944       break;
5945     case RELOAD_FOR_OUTADDR_ADDRESS:
5946       time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5947       break;
5948     case RELOAD_FOR_OUTPUT_ADDRESS:
5949       time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5950       break;
5951     default:
5952       time1 = MAX_RECOG_OPERANDS * 5 + 5;
5953     }
5954
5955   for (i = 0; i < n_reloads; i++)
5956     {
5957       rtx reg = rld[i].reg_rtx;
5958       if (reg && REG_P (reg)
5959           && ((unsigned) regno - true_regnum (reg)
5960               <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5961           && i != reloadnum)
5962         {
5963           rtx other_input = rld[i].in;
5964
5965           /* If the other reload loads the same input value, that
5966              will not cause a conflict only if it's loading it into
5967              the same register.  */
5968           if (true_regnum (reg) != start_regno)
5969             other_input = NULL_RTX;
5970           if (! other_input || ! rtx_equal_p (other_input, value)
5971               || rld[i].out || out)
5972             {
5973               int time2;
5974               switch (rld[i].when_needed)
5975                 {
5976                 case RELOAD_FOR_OTHER_ADDRESS:
5977                   time2 = 0;
5978                   break;
5979                 case RELOAD_FOR_INPADDR_ADDRESS:
5980                   /* find_reloads makes sure that a
5981                      RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5982                      by at most one - the first -
5983                      RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS .  If the
5984                      address reload is inherited, the address address reload
5985                      goes away, so we can ignore this conflict.  */
5986                   if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5987                       && ignore_address_reloads
5988                       /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5989                          Then the address address is still needed to store
5990                          back the new address.  */
5991                       && ! rld[reloadnum].out)
5992                     continue;
5993                   /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5994                      RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5995                      reloads go away.  */
5996                   if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5997                       && ignore_address_reloads
5998                       /* Unless we are reloading an auto_inc expression.  */
5999                       && ! rld[reloadnum].out)
6000                     continue;
6001                   time2 = rld[i].opnum * 4 + 2;
6002                   break;
6003                 case RELOAD_FOR_INPUT_ADDRESS:
6004                   if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
6005                       && ignore_address_reloads
6006                       && ! rld[reloadnum].out)
6007                     continue;
6008                   time2 = rld[i].opnum * 4 + 3;
6009                   break;
6010                 case RELOAD_FOR_INPUT:
6011                   time2 = rld[i].opnum * 4 + 4;
6012                   check_earlyclobber = 1;
6013                   break;
6014                   /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
6015                      == MAX_RECOG_OPERAND * 4  */
6016                 case RELOAD_FOR_OPADDR_ADDR:
6017                   if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
6018                       && ignore_address_reloads
6019                       && ! rld[reloadnum].out)
6020                     continue;
6021                   time2 = MAX_RECOG_OPERANDS * 4 + 1;
6022                   break;
6023                 case RELOAD_FOR_OPERAND_ADDRESS:
6024                   time2 = MAX_RECOG_OPERANDS * 4 + 2;
6025                   check_earlyclobber = 1;
6026                   break;
6027                 case RELOAD_FOR_INSN:
6028                   time2 = MAX_RECOG_OPERANDS * 4 + 3;
6029                   break;
6030                 case RELOAD_FOR_OUTPUT:
6031                   /* All RELOAD_FOR_OUTPUT reloads become live just after the
6032                      instruction is executed.  */
6033                   time2 = MAX_RECOG_OPERANDS * 4 + 4;
6034                   break;
6035                   /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
6036                      the RELOAD_FOR_OUTPUT reloads, so assign it the same time
6037                      value.  */
6038                 case RELOAD_FOR_OUTADDR_ADDRESS:
6039                   if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
6040                       && ignore_address_reloads
6041                       && ! rld[reloadnum].out)
6042                     continue;
6043                   time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
6044                   break;
6045                 case RELOAD_FOR_OUTPUT_ADDRESS:
6046                   time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
6047                   break;
6048                 case RELOAD_OTHER:
6049                   /* If there is no conflict in the input part, handle this
6050                      like an output reload.  */
6051                   if (! rld[i].in || rtx_equal_p (other_input, value))
6052                     {
6053                       time2 = MAX_RECOG_OPERANDS * 4 + 4;
6054                       /* Earlyclobbered outputs must conflict with inputs.  */
6055                       if (earlyclobber_operand_p (rld[i].out))
6056                         time2 = MAX_RECOG_OPERANDS * 4 + 3;
6057
6058                       break;
6059                     }
6060                   time2 = 1;
6061                   /* RELOAD_OTHER might be live beyond instruction execution,
6062                      but this is not obvious when we set time2 = 1.  So check
6063                      here if there might be a problem with the new reload
6064                      clobbering the register used by the RELOAD_OTHER.  */
6065                   if (out)
6066                     return 0;
6067                   break;
6068                 default:
6069                   return 0;
6070                 }
6071               if ((time1 >= time2
6072                    && (! rld[i].in || rld[i].out
6073                        || ! rtx_equal_p (other_input, value)))
6074                   || (out && rld[reloadnum].out_reg
6075                       && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
6076                 return 0;
6077             }
6078         }
6079     }
6080
6081   /* Earlyclobbered outputs must conflict with inputs.  */
6082   if (check_earlyclobber && out && earlyclobber_operand_p (out))
6083     return 0;
6084
6085   return 1;
6086 }
6087
6088 /* Return 1 if the value in reload reg REGNO, as used by a reload
6089    needed for the part of the insn specified by OPNUM and TYPE,
6090    may be used to load VALUE into it.
6091
6092    MODE is the mode in which the register is used, this is needed to
6093    determine how many hard regs to test.
6094
6095    Other read-only reloads with the same value do not conflict
6096    unless OUT is nonzero and these other reloads have to live while
6097    output reloads live.
6098    If OUT is CONST0_RTX, this is a special case: it means that the
6099    test should not be for using register REGNO as reload register, but
6100    for copying from register REGNO into the reload register.
6101
6102    RELOADNUM is the number of the reload we want to load this value for;
6103    a reload does not conflict with itself.
6104
6105    When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
6106    reloads that load an address for the very reload we are considering.
6107
6108    The caller has to make sure that there is no conflict with the return
6109    register.  */
6110
6111 static int
6112 free_for_value_p (int regno, machine_mode mode, int opnum,
6113                   enum reload_type type, rtx value, rtx out, int reloadnum,
6114                   int ignore_address_reloads)
6115 {
6116   int nregs = hard_regno_nregs[regno][mode];
6117   while (nregs-- > 0)
6118     if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
6119                                        value, out, reloadnum,
6120                                        ignore_address_reloads))
6121       return 0;
6122   return 1;
6123 }
6124
6125 /* Return nonzero if the rtx X is invariant over the current function.  */
6126 /* ??? Actually, the places where we use this expect exactly what is
6127    tested here, and not everything that is function invariant.  In
6128    particular, the frame pointer and arg pointer are special cased;
6129    pic_offset_table_rtx is not, and we must not spill these things to
6130    memory.  */
6131
6132 int
6133 function_invariant_p (const_rtx x)
6134 {
6135   if (CONSTANT_P (x))
6136     return 1;
6137   if (x == frame_pointer_rtx || x == arg_pointer_rtx)
6138     return 1;
6139   if (GET_CODE (x) == PLUS
6140       && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
6141       && GET_CODE (XEXP (x, 1)) == CONST_INT)
6142     return 1;
6143   return 0;
6144 }
6145
6146 /* Determine whether the reload reg X overlaps any rtx'es used for
6147    overriding inheritance.  Return nonzero if so.  */
6148
6149 static int
6150 conflicts_with_override (rtx x)
6151 {
6152   int i;
6153   for (i = 0; i < n_reloads; i++)
6154     if (reload_override_in[i]
6155         && reg_overlap_mentioned_p (x, reload_override_in[i]))
6156       return 1;
6157   return 0;
6158 }
6159 \f
6160 /* Give an error message saying we failed to find a reload for INSN,
6161    and clear out reload R.  */
6162 static void
6163 failed_reload (rtx_insn *insn, int r)
6164 {
6165   if (asm_noperands (PATTERN (insn)) < 0)
6166     /* It's the compiler's fault.  */
6167     fatal_insn ("could not find a spill register", insn);
6168
6169   /* It's the user's fault; the operand's mode and constraint
6170      don't match.  Disable this reload so we don't crash in final.  */
6171   error_for_asm (insn,
6172                  "%<asm%> operand constraint incompatible with operand size");
6173   rld[r].in = 0;
6174   rld[r].out = 0;
6175   rld[r].reg_rtx = 0;
6176   rld[r].optional = 1;
6177   rld[r].secondary_p = 1;
6178 }
6179
6180 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6181    for reload R.  If it's valid, get an rtx for it.  Return nonzero if
6182    successful.  */
6183 static int
6184 set_reload_reg (int i, int r)
6185 {
6186   /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6187      parameter.  */
6188   int regno ATTRIBUTE_UNUSED;
6189   rtx reg = spill_reg_rtx[i];
6190
6191   if (reg == 0 || GET_MODE (reg) != rld[r].mode)
6192     spill_reg_rtx[i] = reg
6193       = gen_rtx_REG (rld[r].mode, spill_regs[i]);
6194
6195   regno = true_regnum (reg);
6196
6197   /* Detect when the reload reg can't hold the reload mode.
6198      This used to be one `if', but Sequent compiler can't handle that.  */
6199   if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
6200     {
6201       machine_mode test_mode = VOIDmode;
6202       if (rld[r].in)
6203         test_mode = GET_MODE (rld[r].in);
6204       /* If rld[r].in has VOIDmode, it means we will load it
6205          in whatever mode the reload reg has: to wit, rld[r].mode.
6206          We have already tested that for validity.  */
6207       /* Aside from that, we need to test that the expressions
6208          to reload from or into have modes which are valid for this
6209          reload register.  Otherwise the reload insns would be invalid.  */
6210       if (! (rld[r].in != 0 && test_mode != VOIDmode
6211              && ! HARD_REGNO_MODE_OK (regno, test_mode)))
6212         if (! (rld[r].out != 0
6213                && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
6214           {
6215             /* The reg is OK.  */
6216             last_spill_reg = i;
6217
6218             /* Mark as in use for this insn the reload regs we use
6219                for this.  */
6220             mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
6221                                     rld[r].when_needed, rld[r].mode);
6222
6223             rld[r].reg_rtx = reg;
6224             reload_spill_index[r] = spill_regs[i];
6225             return 1;
6226           }
6227     }
6228   return 0;
6229 }
6230
6231 /* Find a spill register to use as a reload register for reload R.
6232    LAST_RELOAD is nonzero if this is the last reload for the insn being
6233    processed.
6234
6235    Set rld[R].reg_rtx to the register allocated.
6236
6237    We return 1 if successful, or 0 if we couldn't find a spill reg and
6238    we didn't change anything.  */
6239
6240 static int
6241 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
6242                      int last_reload)
6243 {
6244   int i, pass, count;
6245
6246   /* If we put this reload ahead, thinking it is a group,
6247      then insist on finding a group.  Otherwise we can grab a
6248      reg that some other reload needs.
6249      (That can happen when we have a 68000 DATA_OR_FP_REG
6250      which is a group of data regs or one fp reg.)
6251      We need not be so restrictive if there are no more reloads
6252      for this insn.
6253
6254      ??? Really it would be nicer to have smarter handling
6255      for that kind of reg class, where a problem like this is normal.
6256      Perhaps those classes should be avoided for reloading
6257      by use of more alternatives.  */
6258
6259   int force_group = rld[r].nregs > 1 && ! last_reload;
6260
6261   /* If we want a single register and haven't yet found one,
6262      take any reg in the right class and not in use.
6263      If we want a consecutive group, here is where we look for it.
6264
6265      We use three passes so we can first look for reload regs to
6266      reuse, which are already in use for other reloads in this insn,
6267      and only then use additional registers which are not "bad", then
6268      finally any register.
6269
6270      I think that maximizing reuse is needed to make sure we don't
6271      run out of reload regs.  Suppose we have three reloads, and
6272      reloads A and B can share regs.  These need two regs.
6273      Suppose A and B are given different regs.
6274      That leaves none for C.  */
6275   for (pass = 0; pass < 3; pass++)
6276     {
6277       /* I is the index in spill_regs.
6278          We advance it round-robin between insns to use all spill regs
6279          equally, so that inherited reloads have a chance
6280          of leapfrogging each other.  */
6281
6282       i = last_spill_reg;
6283
6284       for (count = 0; count < n_spills; count++)
6285         {
6286           int rclass = (int) rld[r].rclass;
6287           int regnum;
6288
6289           i++;
6290           if (i >= n_spills)
6291             i -= n_spills;
6292           regnum = spill_regs[i];
6293
6294           if ((reload_reg_free_p (regnum, rld[r].opnum,
6295                                   rld[r].when_needed)
6296                || (rld[r].in
6297                    /* We check reload_reg_used to make sure we
6298                       don't clobber the return register.  */
6299                    && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
6300                    && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
6301                                         rld[r].when_needed, rld[r].in,
6302                                         rld[r].out, r, 1)))
6303               && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
6304               && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
6305               /* Look first for regs to share, then for unshared.  But
6306                  don't share regs used for inherited reloads; they are
6307                  the ones we want to preserve.  */
6308               && (pass
6309                   || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
6310                                          regnum)
6311                       && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
6312                                               regnum))))
6313             {
6314               int nr = hard_regno_nregs[regnum][rld[r].mode];
6315
6316               /* During the second pass we want to avoid reload registers
6317                  which are "bad" for this reload.  */
6318               if (pass == 1
6319                   && ira_bad_reload_regno (regnum, rld[r].in, rld[r].out))
6320                 continue;
6321
6322               /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6323                  (on 68000) got us two FP regs.  If NR is 1,
6324                  we would reject both of them.  */
6325               if (force_group)
6326                 nr = rld[r].nregs;
6327               /* If we need only one reg, we have already won.  */
6328               if (nr == 1)
6329                 {
6330                   /* But reject a single reg if we demand a group.  */
6331                   if (force_group)
6332                     continue;
6333                   break;
6334                 }
6335               /* Otherwise check that as many consecutive regs as we need
6336                  are available here.  */
6337               while (nr > 1)
6338                 {
6339                   int regno = regnum + nr - 1;
6340                   if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
6341                         && spill_reg_order[regno] >= 0
6342                         && reload_reg_free_p (regno, rld[r].opnum,
6343                                               rld[r].when_needed)))
6344                     break;
6345                   nr--;
6346                 }
6347               if (nr == 1)
6348                 break;
6349             }
6350         }
6351
6352       /* If we found something on the current pass, omit later passes.  */
6353       if (count < n_spills)
6354         break;
6355     }
6356
6357   /* We should have found a spill register by now.  */
6358   if (count >= n_spills)
6359     return 0;
6360
6361   /* I is the index in SPILL_REG_RTX of the reload register we are to
6362      allocate.  Get an rtx for it and find its register number.  */
6363
6364   return set_reload_reg (i, r);
6365 }
6366 \f
6367 /* Initialize all the tables needed to allocate reload registers.
6368    CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6369    is the array we use to restore the reg_rtx field for every reload.  */
6370
6371 static void
6372 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
6373 {
6374   int i;
6375
6376   for (i = 0; i < n_reloads; i++)
6377     rld[i].reg_rtx = save_reload_reg_rtx[i];
6378
6379   memset (reload_inherited, 0, MAX_RELOADS);
6380   memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
6381   memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
6382
6383   CLEAR_HARD_REG_SET (reload_reg_used);
6384   CLEAR_HARD_REG_SET (reload_reg_used_at_all);
6385   CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
6386   CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
6387   CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
6388   CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
6389
6390   CLEAR_HARD_REG_SET (reg_used_in_insn);
6391   {
6392     HARD_REG_SET tmp;
6393     REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
6394     IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6395     REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
6396     IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6397     compute_use_by_pseudos (&reg_used_in_insn, &chain->live_throughout);
6398     compute_use_by_pseudos (&reg_used_in_insn, &chain->dead_or_set);
6399   }
6400
6401   for (i = 0; i < reload_n_operands; i++)
6402     {
6403       CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
6404       CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
6405       CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
6406       CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
6407       CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
6408       CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
6409     }
6410
6411   COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
6412
6413   CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
6414
6415   for (i = 0; i < n_reloads; i++)
6416     /* If we have already decided to use a certain register,
6417        don't use it in another way.  */
6418     if (rld[i].reg_rtx)
6419       mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
6420                               rld[i].when_needed, rld[i].mode);
6421 }
6422
6423 #ifdef SECONDARY_MEMORY_NEEDED
6424 /* If X is not a subreg, return it unmodified.  If it is a subreg,
6425    look up whether we made a replacement for the SUBREG_REG.  Return
6426    either the replacement or the SUBREG_REG.  */
6427
6428 static rtx
6429 replaced_subreg (rtx x)
6430 {
6431   if (GET_CODE (x) == SUBREG)
6432     return find_replacement (&SUBREG_REG (x));
6433   return x;
6434 }
6435 #endif
6436
6437 /* Compute the offset to pass to subreg_regno_offset, for a pseudo of
6438    mode OUTERMODE that is available in a hard reg of mode INNERMODE.
6439    SUBREG is non-NULL if the pseudo is a subreg whose reg is a pseudo,
6440    otherwise it is NULL.  */
6441
6442 static int
6443 compute_reload_subreg_offset (machine_mode outermode,
6444                               rtx subreg,
6445                               machine_mode innermode)
6446 {
6447   int outer_offset;
6448   machine_mode middlemode;
6449
6450   if (!subreg)
6451     return subreg_lowpart_offset (outermode, innermode);
6452
6453   outer_offset = SUBREG_BYTE (subreg);
6454   middlemode = GET_MODE (SUBREG_REG (subreg));
6455
6456   /* If SUBREG is paradoxical then return the normal lowpart offset
6457      for OUTERMODE and INNERMODE.  Our caller has already checked
6458      that OUTERMODE fits in INNERMODE.  */
6459   if (outer_offset == 0
6460       && GET_MODE_SIZE (outermode) > GET_MODE_SIZE (middlemode))
6461     return subreg_lowpart_offset (outermode, innermode);
6462
6463   /* SUBREG is normal, but may not be lowpart; return OUTER_OFFSET
6464      plus the normal lowpart offset for MIDDLEMODE and INNERMODE.  */
6465   return outer_offset + subreg_lowpart_offset (middlemode, innermode);
6466 }
6467
6468 /* Assign hard reg targets for the pseudo-registers we must reload
6469    into hard regs for this insn.
6470    Also output the instructions to copy them in and out of the hard regs.
6471
6472    For machines with register classes, we are responsible for
6473    finding a reload reg in the proper class.  */
6474
6475 static void
6476 choose_reload_regs (struct insn_chain *chain)
6477 {
6478   rtx_insn *insn = chain->insn;
6479   int i, j;
6480   unsigned int max_group_size = 1;
6481   enum reg_class group_class = NO_REGS;
6482   int pass, win, inheritance;
6483
6484   rtx save_reload_reg_rtx[MAX_RELOADS];
6485
6486   /* In order to be certain of getting the registers we need,
6487      we must sort the reloads into order of increasing register class.
6488      Then our grabbing of reload registers will parallel the process
6489      that provided the reload registers.
6490
6491      Also note whether any of the reloads wants a consecutive group of regs.
6492      If so, record the maximum size of the group desired and what
6493      register class contains all the groups needed by this insn.  */
6494
6495   for (j = 0; j < n_reloads; j++)
6496     {
6497       reload_order[j] = j;
6498       if (rld[j].reg_rtx != NULL_RTX)
6499         {
6500           gcc_assert (REG_P (rld[j].reg_rtx)
6501                       && HARD_REGISTER_P (rld[j].reg_rtx));
6502           reload_spill_index[j] = REGNO (rld[j].reg_rtx);
6503         }
6504       else
6505         reload_spill_index[j] = -1;
6506
6507       if (rld[j].nregs > 1)
6508         {
6509           max_group_size = MAX (rld[j].nregs, max_group_size);
6510           group_class
6511             = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
6512         }
6513
6514       save_reload_reg_rtx[j] = rld[j].reg_rtx;
6515     }
6516
6517   if (n_reloads > 1)
6518     qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
6519
6520   /* If -O, try first with inheritance, then turning it off.
6521      If not -O, don't do inheritance.
6522      Using inheritance when not optimizing leads to paradoxes
6523      with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6524      because one side of the comparison might be inherited.  */
6525   win = 0;
6526   for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
6527     {
6528       choose_reload_regs_init (chain, save_reload_reg_rtx);
6529
6530       /* Process the reloads in order of preference just found.
6531          Beyond this point, subregs can be found in reload_reg_rtx.
6532
6533          This used to look for an existing reloaded home for all of the
6534          reloads, and only then perform any new reloads.  But that could lose
6535          if the reloads were done out of reg-class order because a later
6536          reload with a looser constraint might have an old home in a register
6537          needed by an earlier reload with a tighter constraint.
6538
6539          To solve this, we make two passes over the reloads, in the order
6540          described above.  In the first pass we try to inherit a reload
6541          from a previous insn.  If there is a later reload that needs a
6542          class that is a proper subset of the class being processed, we must
6543          also allocate a spill register during the first pass.
6544
6545          Then make a second pass over the reloads to allocate any reloads
6546          that haven't been given registers yet.  */
6547
6548       for (j = 0; j < n_reloads; j++)
6549         {
6550           int r = reload_order[j];
6551           rtx search_equiv = NULL_RTX;
6552
6553           /* Ignore reloads that got marked inoperative.  */
6554           if (rld[r].out == 0 && rld[r].in == 0
6555               && ! rld[r].secondary_p)
6556             continue;
6557
6558           /* If find_reloads chose to use reload_in or reload_out as a reload
6559              register, we don't need to chose one.  Otherwise, try even if it
6560              found one since we might save an insn if we find the value lying
6561              around.
6562              Try also when reload_in is a pseudo without a hard reg.  */
6563           if (rld[r].in != 0 && rld[r].reg_rtx != 0
6564               && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6565                   || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6566                       && !MEM_P (rld[r].in)
6567                       && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6568             continue;
6569
6570 #if 0 /* No longer needed for correct operation.
6571          It might give better code, or might not; worth an experiment?  */
6572           /* If this is an optional reload, we can't inherit from earlier insns
6573              until we are sure that any non-optional reloads have been allocated.
6574              The following code takes advantage of the fact that optional reloads
6575              are at the end of reload_order.  */
6576           if (rld[r].optional != 0)
6577             for (i = 0; i < j; i++)
6578               if ((rld[reload_order[i]].out != 0
6579                    || rld[reload_order[i]].in != 0
6580                    || rld[reload_order[i]].secondary_p)
6581                   && ! rld[reload_order[i]].optional
6582                   && rld[reload_order[i]].reg_rtx == 0)
6583                 allocate_reload_reg (chain, reload_order[i], 0);
6584 #endif
6585
6586           /* First see if this pseudo is already available as reloaded
6587              for a previous insn.  We cannot try to inherit for reloads
6588              that are smaller than the maximum number of registers needed
6589              for groups unless the register we would allocate cannot be used
6590              for the groups.
6591
6592              We could check here to see if this is a secondary reload for
6593              an object that is already in a register of the desired class.
6594              This would avoid the need for the secondary reload register.
6595              But this is complex because we can't easily determine what
6596              objects might want to be loaded via this reload.  So let a
6597              register be allocated here.  In `emit_reload_insns' we suppress
6598              one of the loads in the case described above.  */
6599
6600           if (inheritance)
6601             {
6602               int byte = 0;
6603               int regno = -1;
6604               machine_mode mode = VOIDmode;
6605               rtx subreg = NULL_RTX;
6606
6607               if (rld[r].in == 0)
6608                 ;
6609               else if (REG_P (rld[r].in))
6610                 {
6611                   regno = REGNO (rld[r].in);
6612                   mode = GET_MODE (rld[r].in);
6613                 }
6614               else if (REG_P (rld[r].in_reg))
6615                 {
6616                   regno = REGNO (rld[r].in_reg);
6617                   mode = GET_MODE (rld[r].in_reg);
6618                 }
6619               else if (GET_CODE (rld[r].in_reg) == SUBREG
6620                        && REG_P (SUBREG_REG (rld[r].in_reg)))
6621                 {
6622                   regno = REGNO (SUBREG_REG (rld[r].in_reg));
6623                   if (regno < FIRST_PSEUDO_REGISTER)
6624                     regno = subreg_regno (rld[r].in_reg);
6625                   else
6626                     {
6627                       subreg = rld[r].in_reg;
6628                       byte = SUBREG_BYTE (subreg);
6629                     }
6630                   mode = GET_MODE (rld[r].in_reg);
6631                 }
6632 #ifdef AUTO_INC_DEC
6633               else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6634                        && REG_P (XEXP (rld[r].in_reg, 0)))
6635                 {
6636                   regno = REGNO (XEXP (rld[r].in_reg, 0));
6637                   mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6638                   rld[r].out = rld[r].in;
6639                 }
6640 #endif
6641 #if 0
6642               /* This won't work, since REGNO can be a pseudo reg number.
6643                  Also, it takes much more hair to keep track of all the things
6644                  that can invalidate an inherited reload of part of a pseudoreg.  */
6645               else if (GET_CODE (rld[r].in) == SUBREG
6646                        && REG_P (SUBREG_REG (rld[r].in)))
6647                 regno = subreg_regno (rld[r].in);
6648 #endif
6649
6650               if (regno >= 0
6651                   && reg_last_reload_reg[regno] != 0
6652                   && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
6653                       >= GET_MODE_SIZE (mode) + byte)
6654 #ifdef CANNOT_CHANGE_MODE_CLASS
6655                   /* Verify that the register it's in can be used in
6656                      mode MODE.  */
6657                   && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6658                                                 GET_MODE (reg_last_reload_reg[regno]),
6659                                                 mode)
6660 #endif
6661                   )
6662                 {
6663                   enum reg_class rclass = rld[r].rclass, last_class;
6664                   rtx last_reg = reg_last_reload_reg[regno];
6665
6666                   i = REGNO (last_reg);
6667                   byte = compute_reload_subreg_offset (mode,
6668                                                        subreg,
6669                                                        GET_MODE (last_reg));
6670                   i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6671                   last_class = REGNO_REG_CLASS (i);
6672
6673                   if (reg_reloaded_contents[i] == regno
6674                       && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6675                       && HARD_REGNO_MODE_OK (i, rld[r].mode)
6676                       && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6677                           /* Even if we can't use this register as a reload
6678                              register, we might use it for reload_override_in,
6679                              if copying it to the desired class is cheap
6680                              enough.  */
6681                           || ((register_move_cost (mode, last_class, rclass)
6682                                < memory_move_cost (mode, rclass, true))
6683                               && (secondary_reload_class (1, rclass, mode,
6684                                                           last_reg)
6685                                   == NO_REGS)
6686 #ifdef SECONDARY_MEMORY_NEEDED
6687                               && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6688                                                             mode)
6689 #endif
6690                               ))
6691
6692                       && (rld[r].nregs == max_group_size
6693                           || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6694                                                   i))
6695                       && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6696                                            rld[r].when_needed, rld[r].in,
6697                                            const0_rtx, r, 1))
6698                     {
6699                       /* If a group is needed, verify that all the subsequent
6700                          registers still have their values intact.  */
6701                       int nr = hard_regno_nregs[i][rld[r].mode];
6702                       int k;
6703
6704                       for (k = 1; k < nr; k++)
6705                         if (reg_reloaded_contents[i + k] != regno
6706                             || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6707                           break;
6708
6709                       if (k == nr)
6710                         {
6711                           int i1;
6712                           int bad_for_class;
6713
6714                           last_reg = (GET_MODE (last_reg) == mode
6715                                       ? last_reg : gen_rtx_REG (mode, i));
6716
6717                           bad_for_class = 0;
6718                           for (k = 0; k < nr; k++)
6719                             bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6720                                                                   i+k);
6721
6722                           /* We found a register that contains the
6723                              value we need.  If this register is the
6724                              same as an `earlyclobber' operand of the
6725                              current insn, just mark it as a place to
6726                              reload from since we can't use it as the
6727                              reload register itself.  */
6728
6729                           for (i1 = 0; i1 < n_earlyclobbers; i1++)
6730                             if (reg_overlap_mentioned_for_reload_p
6731                                 (reg_last_reload_reg[regno],
6732                                  reload_earlyclobbers[i1]))
6733                               break;
6734
6735                           if (i1 != n_earlyclobbers
6736                               || ! (free_for_value_p (i, rld[r].mode,
6737                                                       rld[r].opnum,
6738                                                       rld[r].when_needed, rld[r].in,
6739                                                       rld[r].out, r, 1))
6740                               /* Don't use it if we'd clobber a pseudo reg.  */
6741                               || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6742                                   && rld[r].out
6743                                   && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6744                               /* Don't clobber the frame pointer.  */
6745                               || (i == HARD_FRAME_POINTER_REGNUM
6746                                   && frame_pointer_needed
6747                                   && rld[r].out)
6748                               /* Don't really use the inherited spill reg
6749                                  if we need it wider than we've got it.  */
6750                               || (GET_MODE_SIZE (rld[r].mode)
6751                                   > GET_MODE_SIZE (mode))
6752                               || bad_for_class
6753
6754                               /* If find_reloads chose reload_out as reload
6755                                  register, stay with it - that leaves the
6756                                  inherited register for subsequent reloads.  */
6757                               || (rld[r].out && rld[r].reg_rtx
6758                                   && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6759                             {
6760                               if (! rld[r].optional)
6761                                 {
6762                                   reload_override_in[r] = last_reg;
6763                                   reload_inheritance_insn[r]
6764                                     = reg_reloaded_insn[i];
6765                                 }
6766                             }
6767                           else
6768                             {
6769                               int k;
6770                               /* We can use this as a reload reg.  */
6771                               /* Mark the register as in use for this part of
6772                                  the insn.  */
6773                               mark_reload_reg_in_use (i,
6774                                                       rld[r].opnum,
6775                                                       rld[r].when_needed,
6776                                                       rld[r].mode);
6777                               rld[r].reg_rtx = last_reg;
6778                               reload_inherited[r] = 1;
6779                               reload_inheritance_insn[r]
6780                                 = reg_reloaded_insn[i];
6781                               reload_spill_index[r] = i;
6782                               for (k = 0; k < nr; k++)
6783                                 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6784                                                   i + k);
6785                             }
6786                         }
6787                     }
6788                 }
6789             }
6790
6791           /* Here's another way to see if the value is already lying around.  */
6792           if (inheritance
6793               && rld[r].in != 0
6794               && ! reload_inherited[r]
6795               && rld[r].out == 0
6796               && (CONSTANT_P (rld[r].in)
6797                   || GET_CODE (rld[r].in) == PLUS
6798                   || REG_P (rld[r].in)
6799                   || MEM_P (rld[r].in))
6800               && (rld[r].nregs == max_group_size
6801                   || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6802             search_equiv = rld[r].in;
6803
6804           if (search_equiv)
6805             {
6806               rtx equiv
6807                 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6808                                   -1, NULL, 0, rld[r].mode);
6809               int regno = 0;
6810
6811               if (equiv != 0)
6812                 {
6813                   if (REG_P (equiv))
6814                     regno = REGNO (equiv);
6815                   else
6816                     {
6817                       /* This must be a SUBREG of a hard register.
6818                          Make a new REG since this might be used in an
6819                          address and not all machines support SUBREGs
6820                          there.  */
6821                       gcc_assert (GET_CODE (equiv) == SUBREG);
6822                       regno = subreg_regno (equiv);
6823                       equiv = gen_rtx_REG (rld[r].mode, regno);
6824                       /* If we choose EQUIV as the reload register, but the
6825                          loop below decides to cancel the inheritance, we'll
6826                          end up reloading EQUIV in rld[r].mode, not the mode
6827                          it had originally.  That isn't safe when EQUIV isn't
6828                          available as a spill register since its value might
6829                          still be live at this point.  */
6830                       for (i = regno; i < regno + (int) rld[r].nregs; i++)
6831                         if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6832                           equiv = 0;
6833                     }
6834                 }
6835
6836               /* If we found a spill reg, reject it unless it is free
6837                  and of the desired class.  */
6838               if (equiv != 0)
6839                 {
6840                   int regs_used = 0;
6841                   int bad_for_class = 0;
6842                   int max_regno = regno + rld[r].nregs;
6843
6844                   for (i = regno; i < max_regno; i++)
6845                     {
6846                       regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6847                                                       i);
6848                       bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6849                                                            i);
6850                     }
6851
6852                   if ((regs_used
6853                        && ! free_for_value_p (regno, rld[r].mode,
6854                                               rld[r].opnum, rld[r].when_needed,
6855                                               rld[r].in, rld[r].out, r, 1))
6856                       || bad_for_class)
6857                     equiv = 0;
6858                 }
6859
6860               if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6861                 equiv = 0;
6862
6863               /* We found a register that contains the value we need.
6864                  If this register is the same as an `earlyclobber' operand
6865                  of the current insn, just mark it as a place to reload from
6866                  since we can't use it as the reload register itself.  */
6867
6868               if (equiv != 0)
6869                 for (i = 0; i < n_earlyclobbers; i++)
6870                   if (reg_overlap_mentioned_for_reload_p (equiv,
6871                                                           reload_earlyclobbers[i]))
6872                     {
6873                       if (! rld[r].optional)
6874                         reload_override_in[r] = equiv;
6875                       equiv = 0;
6876                       break;
6877                     }
6878
6879               /* If the equiv register we have found is explicitly clobbered
6880                  in the current insn, it depends on the reload type if we
6881                  can use it, use it for reload_override_in, or not at all.
6882                  In particular, we then can't use EQUIV for a
6883                  RELOAD_FOR_OUTPUT_ADDRESS reload.  */
6884
6885               if (equiv != 0)
6886                 {
6887                   if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6888                     switch (rld[r].when_needed)
6889                       {
6890                       case RELOAD_FOR_OTHER_ADDRESS:
6891                       case RELOAD_FOR_INPADDR_ADDRESS:
6892                       case RELOAD_FOR_INPUT_ADDRESS:
6893                       case RELOAD_FOR_OPADDR_ADDR:
6894                         break;
6895                       case RELOAD_OTHER:
6896                       case RELOAD_FOR_INPUT:
6897                       case RELOAD_FOR_OPERAND_ADDRESS:
6898                         if (! rld[r].optional)
6899                           reload_override_in[r] = equiv;
6900                         /* Fall through.  */
6901                       default:
6902                         equiv = 0;
6903                         break;
6904                       }
6905                   else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6906                     switch (rld[r].when_needed)
6907                       {
6908                       case RELOAD_FOR_OTHER_ADDRESS:
6909                       case RELOAD_FOR_INPADDR_ADDRESS:
6910                       case RELOAD_FOR_INPUT_ADDRESS:
6911                       case RELOAD_FOR_OPADDR_ADDR:
6912                       case RELOAD_FOR_OPERAND_ADDRESS:
6913                       case RELOAD_FOR_INPUT:
6914                         break;
6915                       case RELOAD_OTHER:
6916                         if (! rld[r].optional)
6917                           reload_override_in[r] = equiv;
6918                         /* Fall through.  */
6919                       default:
6920                         equiv = 0;
6921                         break;
6922                       }
6923                 }
6924
6925               /* If we found an equivalent reg, say no code need be generated
6926                  to load it, and use it as our reload reg.  */
6927               if (equiv != 0
6928                   && (regno != HARD_FRAME_POINTER_REGNUM
6929                       || !frame_pointer_needed))
6930                 {
6931                   int nr = hard_regno_nregs[regno][rld[r].mode];
6932                   int k;
6933                   rld[r].reg_rtx = equiv;
6934                   reload_spill_index[r] = regno;
6935                   reload_inherited[r] = 1;
6936
6937                   /* If reg_reloaded_valid is not set for this register,
6938                      there might be a stale spill_reg_store lying around.
6939                      We must clear it, since otherwise emit_reload_insns
6940                      might delete the store.  */
6941                   if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6942                     spill_reg_store[regno] = NULL;
6943                   /* If any of the hard registers in EQUIV are spill
6944                      registers, mark them as in use for this insn.  */
6945                   for (k = 0; k < nr; k++)
6946                     {
6947                       i = spill_reg_order[regno + k];
6948                       if (i >= 0)
6949                         {
6950                           mark_reload_reg_in_use (regno, rld[r].opnum,
6951                                                   rld[r].when_needed,
6952                                                   rld[r].mode);
6953                           SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6954                                             regno + k);
6955                         }
6956                     }
6957                 }
6958             }
6959
6960           /* If we found a register to use already, or if this is an optional
6961              reload, we are done.  */
6962           if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6963             continue;
6964
6965 #if 0
6966           /* No longer needed for correct operation.  Might or might
6967              not give better code on the average.  Want to experiment?  */
6968
6969           /* See if there is a later reload that has a class different from our
6970              class that intersects our class or that requires less register
6971              than our reload.  If so, we must allocate a register to this
6972              reload now, since that reload might inherit a previous reload
6973              and take the only available register in our class.  Don't do this
6974              for optional reloads since they will force all previous reloads
6975              to be allocated.  Also don't do this for reloads that have been
6976              turned off.  */
6977
6978           for (i = j + 1; i < n_reloads; i++)
6979             {
6980               int s = reload_order[i];
6981
6982               if ((rld[s].in == 0 && rld[s].out == 0
6983                    && ! rld[s].secondary_p)
6984                   || rld[s].optional)
6985                 continue;
6986
6987               if ((rld[s].rclass != rld[r].rclass
6988                    && reg_classes_intersect_p (rld[r].rclass,
6989                                                rld[s].rclass))
6990                   || rld[s].nregs < rld[r].nregs)
6991                 break;
6992             }
6993
6994           if (i == n_reloads)
6995             continue;
6996
6997           allocate_reload_reg (chain, r, j == n_reloads - 1);
6998 #endif
6999         }
7000
7001       /* Now allocate reload registers for anything non-optional that
7002          didn't get one yet.  */
7003       for (j = 0; j < n_reloads; j++)
7004         {
7005           int r = reload_order[j];
7006
7007           /* Ignore reloads that got marked inoperative.  */
7008           if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
7009             continue;
7010
7011           /* Skip reloads that already have a register allocated or are
7012              optional.  */
7013           if (rld[r].reg_rtx != 0 || rld[r].optional)
7014             continue;
7015
7016           if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
7017             break;
7018         }
7019
7020       /* If that loop got all the way, we have won.  */
7021       if (j == n_reloads)
7022         {
7023           win = 1;
7024           break;
7025         }
7026
7027       /* Loop around and try without any inheritance.  */
7028     }
7029
7030   if (! win)
7031     {
7032       /* First undo everything done by the failed attempt
7033          to allocate with inheritance.  */
7034       choose_reload_regs_init (chain, save_reload_reg_rtx);
7035
7036       /* Some sanity tests to verify that the reloads found in the first
7037          pass are identical to the ones we have now.  */
7038       gcc_assert (chain->n_reloads == n_reloads);
7039
7040       for (i = 0; i < n_reloads; i++)
7041         {
7042           if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
7043             continue;
7044           gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
7045           for (j = 0; j < n_spills; j++)
7046             if (spill_regs[j] == chain->rld[i].regno)
7047               if (! set_reload_reg (j, i))
7048                 failed_reload (chain->insn, i);
7049         }
7050     }
7051
7052   /* If we thought we could inherit a reload, because it seemed that
7053      nothing else wanted the same reload register earlier in the insn,
7054      verify that assumption, now that all reloads have been assigned.
7055      Likewise for reloads where reload_override_in has been set.  */
7056
7057   /* If doing expensive optimizations, do one preliminary pass that doesn't
7058      cancel any inheritance, but removes reloads that have been needed only
7059      for reloads that we know can be inherited.  */
7060   for (pass = flag_expensive_optimizations; pass >= 0; pass--)
7061     {
7062       for (j = 0; j < n_reloads; j++)
7063         {
7064           int r = reload_order[j];
7065           rtx check_reg;
7066 #ifdef SECONDARY_MEMORY_NEEDED
7067           rtx tem;
7068 #endif
7069           if (reload_inherited[r] && rld[r].reg_rtx)
7070             check_reg = rld[r].reg_rtx;
7071           else if (reload_override_in[r]
7072                    && (REG_P (reload_override_in[r])
7073                        || GET_CODE (reload_override_in[r]) == SUBREG))
7074             check_reg = reload_override_in[r];
7075           else
7076             continue;
7077           if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
7078                                   rld[r].opnum, rld[r].when_needed, rld[r].in,
7079                                   (reload_inherited[r]
7080                                    ? rld[r].out : const0_rtx),
7081                                   r, 1))
7082             {
7083               if (pass)
7084                 continue;
7085               reload_inherited[r] = 0;
7086               reload_override_in[r] = 0;
7087             }
7088           /* If we can inherit a RELOAD_FOR_INPUT, or can use a
7089              reload_override_in, then we do not need its related
7090              RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
7091              likewise for other reload types.
7092              We handle this by removing a reload when its only replacement
7093              is mentioned in reload_in of the reload we are going to inherit.
7094              A special case are auto_inc expressions; even if the input is
7095              inherited, we still need the address for the output.  We can
7096              recognize them because they have RELOAD_OUT set to RELOAD_IN.
7097              If we succeeded removing some reload and we are doing a preliminary
7098              pass just to remove such reloads, make another pass, since the
7099              removal of one reload might allow us to inherit another one.  */
7100           else if (rld[r].in
7101                    && rld[r].out != rld[r].in
7102                    && remove_address_replacements (rld[r].in))
7103             {
7104               if (pass)
7105                 pass = 2;
7106             }
7107 #ifdef SECONDARY_MEMORY_NEEDED
7108           /* If we needed a memory location for the reload, we also have to
7109              remove its related reloads.  */
7110           else if (rld[r].in
7111                    && rld[r].out != rld[r].in
7112                    && (tem = replaced_subreg (rld[r].in), REG_P (tem))
7113                    && REGNO (tem) < FIRST_PSEUDO_REGISTER
7114                    && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem)),
7115                                                rld[r].rclass, rld[r].inmode)
7116                    && remove_address_replacements
7117                       (get_secondary_mem (tem, rld[r].inmode, rld[r].opnum,
7118                                           rld[r].when_needed)))
7119             {
7120               if (pass)
7121                 pass = 2;
7122             }
7123 #endif
7124         }
7125     }
7126
7127   /* Now that reload_override_in is known valid,
7128      actually override reload_in.  */
7129   for (j = 0; j < n_reloads; j++)
7130     if (reload_override_in[j])
7131       rld[j].in = reload_override_in[j];
7132
7133   /* If this reload won't be done because it has been canceled or is
7134      optional and not inherited, clear reload_reg_rtx so other
7135      routines (such as subst_reloads) don't get confused.  */
7136   for (j = 0; j < n_reloads; j++)
7137     if (rld[j].reg_rtx != 0
7138         && ((rld[j].optional && ! reload_inherited[j])
7139             || (rld[j].in == 0 && rld[j].out == 0
7140                 && ! rld[j].secondary_p)))
7141       {
7142         int regno = true_regnum (rld[j].reg_rtx);
7143
7144         if (spill_reg_order[regno] >= 0)
7145           clear_reload_reg_in_use (regno, rld[j].opnum,
7146                                    rld[j].when_needed, rld[j].mode);
7147         rld[j].reg_rtx = 0;
7148         reload_spill_index[j] = -1;
7149       }
7150
7151   /* Record which pseudos and which spill regs have output reloads.  */
7152   for (j = 0; j < n_reloads; j++)
7153     {
7154       int r = reload_order[j];
7155
7156       i = reload_spill_index[r];
7157
7158       /* I is nonneg if this reload uses a register.
7159          If rld[r].reg_rtx is 0, this is an optional reload
7160          that we opted to ignore.  */
7161       if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
7162           && rld[r].reg_rtx != 0)
7163         {
7164           int nregno = REGNO (rld[r].out_reg);
7165           int nr = 1;
7166
7167           if (nregno < FIRST_PSEUDO_REGISTER)
7168             nr = hard_regno_nregs[nregno][rld[r].mode];
7169
7170           while (--nr >= 0)
7171             SET_REGNO_REG_SET (&reg_has_output_reload,
7172                                nregno + nr);
7173
7174           if (i >= 0)
7175             add_to_hard_reg_set (&reg_is_output_reload, rld[r].mode, i);
7176
7177           gcc_assert (rld[r].when_needed == RELOAD_OTHER
7178                       || rld[r].when_needed == RELOAD_FOR_OUTPUT
7179                       || rld[r].when_needed == RELOAD_FOR_INSN);
7180         }
7181     }
7182 }
7183
7184 /* Deallocate the reload register for reload R.  This is called from
7185    remove_address_replacements.  */
7186
7187 void
7188 deallocate_reload_reg (int r)
7189 {
7190   int regno;
7191
7192   if (! rld[r].reg_rtx)
7193     return;
7194   regno = true_regnum (rld[r].reg_rtx);
7195   rld[r].reg_rtx = 0;
7196   if (spill_reg_order[regno] >= 0)
7197     clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
7198                              rld[r].mode);
7199   reload_spill_index[r] = -1;
7200 }
7201 \f
7202 /* These arrays are filled by emit_reload_insns and its subroutines.  */
7203 static rtx_insn *input_reload_insns[MAX_RECOG_OPERANDS];
7204 static rtx_insn *other_input_address_reload_insns = 0;
7205 static rtx_insn *other_input_reload_insns = 0;
7206 static rtx_insn *input_address_reload_insns[MAX_RECOG_OPERANDS];
7207 static rtx_insn *inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7208 static rtx_insn *output_reload_insns[MAX_RECOG_OPERANDS];
7209 static rtx_insn *output_address_reload_insns[MAX_RECOG_OPERANDS];
7210 static rtx_insn *outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7211 static rtx_insn *operand_reload_insns = 0;
7212 static rtx_insn *other_operand_reload_insns = 0;
7213 static rtx_insn *other_output_reload_insns[MAX_RECOG_OPERANDS];
7214
7215 /* Values to be put in spill_reg_store are put here first.  Instructions
7216    must only be placed here if the associated reload register reaches
7217    the end of the instruction's reload sequence.  */
7218 static rtx_insn *new_spill_reg_store[FIRST_PSEUDO_REGISTER];
7219 static HARD_REG_SET reg_reloaded_died;
7220
7221 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7222    of class NEW_CLASS with mode NEW_MODE.  Or alternatively, if alt_reload_reg
7223    is nonzero, if that is suitable.  On success, change *RELOAD_REG to the
7224    adjusted register, and return true.  Otherwise, return false.  */
7225 static bool
7226 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
7227                             enum reg_class new_class,
7228                             machine_mode new_mode)
7229
7230 {
7231   rtx reg;
7232
7233   for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
7234     {
7235       unsigned regno = REGNO (reg);
7236
7237       if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
7238         continue;
7239       if (GET_MODE (reg) != new_mode)
7240         {
7241           if (!HARD_REGNO_MODE_OK (regno, new_mode))
7242             continue;
7243           if (hard_regno_nregs[regno][new_mode]
7244               > hard_regno_nregs[regno][GET_MODE (reg)])
7245             continue;
7246           reg = reload_adjust_reg_for_mode (reg, new_mode);
7247         }
7248       *reload_reg = reg;
7249       return true;
7250     }
7251   return false;
7252 }
7253
7254 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7255    pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7256    nonzero, if that is suitable.  On success, change *RELOAD_REG to the
7257    adjusted register, and return true.  Otherwise, return false.  */
7258 static bool
7259 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
7260                              enum insn_code icode)
7261
7262 {
7263   enum reg_class new_class = scratch_reload_class (icode);
7264   machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
7265
7266   return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
7267                                      new_class, new_mode);
7268 }
7269
7270 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7271    has the number J.  OLD contains the value to be used as input.  */
7272
7273 static void
7274 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
7275                          rtx old, int j)
7276 {
7277   rtx_insn *insn = chain->insn;
7278   rtx reloadreg;
7279   rtx oldequiv_reg = 0;
7280   rtx oldequiv = 0;
7281   int special = 0;
7282   machine_mode mode;
7283   rtx_insn **where;
7284
7285   /* delete_output_reload is only invoked properly if old contains
7286      the original pseudo register.  Since this is replaced with a
7287      hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7288      find the pseudo in RELOAD_IN_REG.  This is also used to
7289      determine whether a secondary reload is needed.  */
7290   if (reload_override_in[j]
7291       && (REG_P (rl->in_reg)
7292           || (GET_CODE (rl->in_reg) == SUBREG
7293               && REG_P (SUBREG_REG (rl->in_reg)))))
7294     {
7295       oldequiv = old;
7296       old = rl->in_reg;
7297     }
7298   if (oldequiv == 0)
7299     oldequiv = old;
7300   else if (REG_P (oldequiv))
7301     oldequiv_reg = oldequiv;
7302   else if (GET_CODE (oldequiv) == SUBREG)
7303     oldequiv_reg = SUBREG_REG (oldequiv);
7304
7305   reloadreg = reload_reg_rtx_for_input[j];
7306   mode = GET_MODE (reloadreg);
7307
7308   /* If we are reloading from a register that was recently stored in
7309      with an output-reload, see if we can prove there was
7310      actually no need to store the old value in it.  */
7311
7312   if (optimize && REG_P (oldequiv)
7313       && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
7314       && spill_reg_store[REGNO (oldequiv)]
7315       && REG_P (old)
7316       && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
7317           || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7318                           rl->out_reg)))
7319     delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7320
7321   /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7322      OLDEQUIV.  */
7323
7324   while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
7325     oldequiv = SUBREG_REG (oldequiv);
7326   if (GET_MODE (oldequiv) != VOIDmode
7327       && mode != GET_MODE (oldequiv))
7328     oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
7329
7330   /* Switch to the right place to emit the reload insns.  */
7331   switch (rl->when_needed)
7332     {
7333     case RELOAD_OTHER:
7334       where = &other_input_reload_insns;
7335       break;
7336     case RELOAD_FOR_INPUT:
7337       where = &input_reload_insns[rl->opnum];
7338       break;
7339     case RELOAD_FOR_INPUT_ADDRESS:
7340       where = &input_address_reload_insns[rl->opnum];
7341       break;
7342     case RELOAD_FOR_INPADDR_ADDRESS:
7343       where = &inpaddr_address_reload_insns[rl->opnum];
7344       break;
7345     case RELOAD_FOR_OUTPUT_ADDRESS:
7346       where = &output_address_reload_insns[rl->opnum];
7347       break;
7348     case RELOAD_FOR_OUTADDR_ADDRESS:
7349       where = &outaddr_address_reload_insns[rl->opnum];
7350       break;
7351     case RELOAD_FOR_OPERAND_ADDRESS:
7352       where = &operand_reload_insns;
7353       break;
7354     case RELOAD_FOR_OPADDR_ADDR:
7355       where = &other_operand_reload_insns;
7356       break;
7357     case RELOAD_FOR_OTHER_ADDRESS:
7358       where = &other_input_address_reload_insns;
7359       break;
7360     default:
7361       gcc_unreachable ();
7362     }
7363
7364   push_to_sequence (*where);
7365
7366   /* Auto-increment addresses must be reloaded in a special way.  */
7367   if (rl->out && ! rl->out_reg)
7368     {
7369       /* We are not going to bother supporting the case where a
7370          incremented register can't be copied directly from
7371          OLDEQUIV since this seems highly unlikely.  */
7372       gcc_assert (rl->secondary_in_reload < 0);
7373
7374       if (reload_inherited[j])
7375         oldequiv = reloadreg;
7376
7377       old = XEXP (rl->in_reg, 0);
7378
7379       /* Prevent normal processing of this reload.  */
7380       special = 1;
7381       /* Output a special code sequence for this case.  */
7382       inc_for_reload (reloadreg, oldequiv, rl->out, rl->inc);
7383     }
7384
7385   /* If we are reloading a pseudo-register that was set by the previous
7386      insn, see if we can get rid of that pseudo-register entirely
7387      by redirecting the previous insn into our reload register.  */
7388
7389   else if (optimize && REG_P (old)
7390            && REGNO (old) >= FIRST_PSEUDO_REGISTER
7391            && dead_or_set_p (insn, old)
7392            /* This is unsafe if some other reload
7393               uses the same reg first.  */
7394            && ! conflicts_with_override (reloadreg)
7395            && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
7396                                 rl->when_needed, old, rl->out, j, 0))
7397     {
7398       rtx_insn *temp = PREV_INSN (insn);
7399       while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
7400         temp = PREV_INSN (temp);
7401       if (temp
7402           && NONJUMP_INSN_P (temp)
7403           && GET_CODE (PATTERN (temp)) == SET
7404           && SET_DEST (PATTERN (temp)) == old
7405           /* Make sure we can access insn_operand_constraint.  */
7406           && asm_noperands (PATTERN (temp)) < 0
7407           /* This is unsafe if operand occurs more than once in current
7408              insn.  Perhaps some occurrences aren't reloaded.  */
7409           && count_occurrences (PATTERN (insn), old, 0) == 1)
7410         {
7411           rtx old = SET_DEST (PATTERN (temp));
7412           /* Store into the reload register instead of the pseudo.  */
7413           SET_DEST (PATTERN (temp)) = reloadreg;
7414
7415           /* Verify that resulting insn is valid.
7416
7417              Note that we have replaced the destination of TEMP with
7418              RELOADREG.  If TEMP references RELOADREG within an
7419              autoincrement addressing mode, then the resulting insn
7420              is ill-formed and we must reject this optimization.  */
7421           extract_insn (temp);
7422           if (constrain_operands (1, get_enabled_alternatives (temp))
7423 #ifdef AUTO_INC_DEC
7424               && ! find_reg_note (temp, REG_INC, reloadreg)
7425 #endif
7426               )
7427             {
7428               /* If the previous insn is an output reload, the source is
7429                  a reload register, and its spill_reg_store entry will
7430                  contain the previous destination.  This is now
7431                  invalid.  */
7432               if (REG_P (SET_SRC (PATTERN (temp)))
7433                   && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7434                 {
7435                   spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7436                   spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7437                 }
7438
7439               /* If these are the only uses of the pseudo reg,
7440                  pretend for GDB it lives in the reload reg we used.  */
7441               if (REG_N_DEATHS (REGNO (old)) == 1
7442                   && REG_N_SETS (REGNO (old)) == 1)
7443                 {
7444                   reg_renumber[REGNO (old)] = REGNO (reloadreg);
7445                   if (ira_conflicts_p)
7446                     /* Inform IRA about the change.  */
7447                     ira_mark_allocation_change (REGNO (old));
7448                   alter_reg (REGNO (old), -1, false);
7449                 }
7450               special = 1;
7451
7452               /* Adjust any debug insns between temp and insn.  */
7453               while ((temp = NEXT_INSN (temp)) != insn)
7454                 if (DEBUG_INSN_P (temp))
7455                   replace_rtx (PATTERN (temp), old, reloadreg);
7456                 else
7457                   gcc_assert (NOTE_P (temp));
7458             }
7459           else
7460             {
7461               SET_DEST (PATTERN (temp)) = old;
7462             }
7463         }
7464     }
7465
7466   /* We can't do that, so output an insn to load RELOADREG.  */
7467
7468   /* If we have a secondary reload, pick up the secondary register
7469      and icode, if any.  If OLDEQUIV and OLD are different or
7470      if this is an in-out reload, recompute whether or not we
7471      still need a secondary register and what the icode should
7472      be.  If we still need a secondary register and the class or
7473      icode is different, go back to reloading from OLD if using
7474      OLDEQUIV means that we got the wrong type of register.  We
7475      cannot have different class or icode due to an in-out reload
7476      because we don't make such reloads when both the input and
7477      output need secondary reload registers.  */
7478
7479   if (! special && rl->secondary_in_reload >= 0)
7480     {
7481       rtx second_reload_reg = 0;
7482       rtx third_reload_reg = 0;
7483       int secondary_reload = rl->secondary_in_reload;
7484       rtx real_oldequiv = oldequiv;
7485       rtx real_old = old;
7486       rtx tmp;
7487       enum insn_code icode;
7488       enum insn_code tertiary_icode = CODE_FOR_nothing;
7489
7490       /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7491          and similarly for OLD.
7492          See comments in get_secondary_reload in reload.c.  */
7493       /* If it is a pseudo that cannot be replaced with its
7494          equivalent MEM, we must fall back to reload_in, which
7495          will have all the necessary substitutions registered.
7496          Likewise for a pseudo that can't be replaced with its
7497          equivalent constant.
7498
7499          Take extra care for subregs of such pseudos.  Note that
7500          we cannot use reg_equiv_mem in this case because it is
7501          not in the right mode.  */
7502
7503       tmp = oldequiv;
7504       if (GET_CODE (tmp) == SUBREG)
7505         tmp = SUBREG_REG (tmp);
7506       if (REG_P (tmp)
7507           && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7508           && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7509               || reg_equiv_constant (REGNO (tmp)) != 0))
7510         {
7511           if (! reg_equiv_mem (REGNO (tmp))
7512               || num_not_at_initial_offset
7513               || GET_CODE (oldequiv) == SUBREG)
7514             real_oldequiv = rl->in;
7515           else
7516             real_oldequiv = reg_equiv_mem (REGNO (tmp));
7517         }
7518
7519       tmp = old;
7520       if (GET_CODE (tmp) == SUBREG)
7521         tmp = SUBREG_REG (tmp);
7522       if (REG_P (tmp)
7523           && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7524           && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7525               || reg_equiv_constant (REGNO (tmp)) != 0))
7526         {
7527           if (! reg_equiv_mem (REGNO (tmp))
7528               || num_not_at_initial_offset
7529               || GET_CODE (old) == SUBREG)
7530             real_old = rl->in;
7531           else
7532             real_old = reg_equiv_mem (REGNO (tmp));
7533         }
7534
7535       second_reload_reg = rld[secondary_reload].reg_rtx;
7536       if (rld[secondary_reload].secondary_in_reload >= 0)
7537         {
7538           int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7539
7540           third_reload_reg = rld[tertiary_reload].reg_rtx;
7541           tertiary_icode = rld[secondary_reload].secondary_in_icode;
7542           /* We'd have to add more code for quartary reloads.  */
7543           gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7544         }
7545       icode = rl->secondary_in_icode;
7546
7547       if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7548           || (rl->in != 0 && rl->out != 0))
7549         {
7550           secondary_reload_info sri, sri2;
7551           enum reg_class new_class, new_t_class;
7552
7553           sri.icode = CODE_FOR_nothing;
7554           sri.prev_sri = NULL;
7555           new_class
7556             = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7557                                                          rl->rclass, mode,
7558                                                          &sri);
7559
7560           if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7561             second_reload_reg = 0;
7562           else if (new_class == NO_REGS)
7563             {
7564               if (reload_adjust_reg_for_icode (&second_reload_reg,
7565                                                third_reload_reg,
7566                                                (enum insn_code) sri.icode))
7567                 {
7568                   icode = (enum insn_code) sri.icode;
7569                   third_reload_reg = 0;
7570                 }
7571               else
7572                 {
7573                   oldequiv = old;
7574                   real_oldequiv = real_old;
7575                 }
7576             }
7577           else if (sri.icode != CODE_FOR_nothing)
7578             /* We currently lack a way to express this in reloads.  */
7579             gcc_unreachable ();
7580           else
7581             {
7582               sri2.icode = CODE_FOR_nothing;
7583               sri2.prev_sri = &sri;
7584               new_t_class
7585                 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7586                                                              new_class, mode,
7587                                                              &sri);
7588               if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7589                 {
7590                   if (reload_adjust_reg_for_temp (&second_reload_reg,
7591                                                   third_reload_reg,
7592                                                   new_class, mode))
7593                     {
7594                       third_reload_reg = 0;
7595                       tertiary_icode = (enum insn_code) sri2.icode;
7596                     }
7597                   else
7598                     {
7599                       oldequiv = old;
7600                       real_oldequiv = real_old;
7601                     }
7602                 }
7603               else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7604                 {
7605                   rtx intermediate = second_reload_reg;
7606
7607                   if (reload_adjust_reg_for_temp (&intermediate, NULL,
7608                                                   new_class, mode)
7609                       && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7610                                                       ((enum insn_code)
7611                                                        sri2.icode)))
7612                     {
7613                       second_reload_reg = intermediate;
7614                       tertiary_icode = (enum insn_code) sri2.icode;
7615                     }
7616                   else
7617                     {
7618                       oldequiv = old;
7619                       real_oldequiv = real_old;
7620                     }
7621                 }
7622               else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7623                 {
7624                   rtx intermediate = second_reload_reg;
7625
7626                   if (reload_adjust_reg_for_temp (&intermediate, NULL,
7627                                                   new_class, mode)
7628                       && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7629                                                       new_t_class, mode))
7630                     {
7631                       second_reload_reg = intermediate;
7632                       tertiary_icode = (enum insn_code) sri2.icode;
7633                     }
7634                   else
7635                     {
7636                       oldequiv = old;
7637                       real_oldequiv = real_old;
7638                     }
7639                 }
7640               else
7641                 {
7642                   /* This could be handled more intelligently too.  */
7643                   oldequiv = old;
7644                   real_oldequiv = real_old;
7645                 }
7646             }
7647         }
7648
7649       /* If we still need a secondary reload register, check
7650          to see if it is being used as a scratch or intermediate
7651          register and generate code appropriately.  If we need
7652          a scratch register, use REAL_OLDEQUIV since the form of
7653          the insn may depend on the actual address if it is
7654          a MEM.  */
7655
7656       if (second_reload_reg)
7657         {
7658           if (icode != CODE_FOR_nothing)
7659             {
7660               /* We'd have to add extra code to handle this case.  */
7661               gcc_assert (!third_reload_reg);
7662
7663               emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7664                                           second_reload_reg));
7665               special = 1;
7666             }
7667           else
7668             {
7669               /* See if we need a scratch register to load the
7670                  intermediate register (a tertiary reload).  */
7671               if (tertiary_icode != CODE_FOR_nothing)
7672                 {
7673                   emit_insn ((GEN_FCN (tertiary_icode)
7674                               (second_reload_reg, real_oldequiv,
7675                                third_reload_reg)));
7676                 }
7677               else if (third_reload_reg)
7678                 {
7679                   gen_reload (third_reload_reg, real_oldequiv,
7680                               rl->opnum,
7681                               rl->when_needed);
7682                   gen_reload (second_reload_reg, third_reload_reg,
7683                               rl->opnum,
7684                               rl->when_needed);
7685                 }
7686               else
7687                 gen_reload (second_reload_reg, real_oldequiv,
7688                             rl->opnum,
7689                             rl->when_needed);
7690
7691               oldequiv = second_reload_reg;
7692             }
7693         }
7694     }
7695
7696   if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7697     {
7698       rtx real_oldequiv = oldequiv;
7699
7700       if ((REG_P (oldequiv)
7701            && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7702            && (reg_equiv_memory_loc (REGNO (oldequiv)) != 0
7703                || reg_equiv_constant (REGNO (oldequiv)) != 0))
7704           || (GET_CODE (oldequiv) == SUBREG
7705               && REG_P (SUBREG_REG (oldequiv))
7706               && (REGNO (SUBREG_REG (oldequiv))
7707                   >= FIRST_PSEUDO_REGISTER)
7708               && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv))) != 0)
7709                   || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv))) != 0)))
7710           || (CONSTANT_P (oldequiv)
7711               && (targetm.preferred_reload_class (oldequiv,
7712                                                   REGNO_REG_CLASS (REGNO (reloadreg)))
7713                   == NO_REGS)))
7714         real_oldequiv = rl->in;
7715       gen_reload (reloadreg, real_oldequiv, rl->opnum,
7716                   rl->when_needed);
7717     }
7718
7719   if (cfun->can_throw_non_call_exceptions)
7720     copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7721
7722   /* End this sequence.  */
7723   *where = get_insns ();
7724   end_sequence ();
7725
7726   /* Update reload_override_in so that delete_address_reloads_1
7727      can see the actual register usage.  */
7728   if (oldequiv_reg)
7729     reload_override_in[j] = oldequiv;
7730 }
7731
7732 /* Generate insns to for the output reload RL, which is for the insn described
7733    by CHAIN and has the number J.  */
7734 static void
7735 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7736                           int j)
7737 {
7738   rtx reloadreg;
7739   rtx_insn *insn = chain->insn;
7740   int special = 0;
7741   rtx old = rl->out;
7742   machine_mode mode;
7743   rtx_insn *p;
7744   rtx rl_reg_rtx;
7745
7746   if (rl->when_needed == RELOAD_OTHER)
7747     start_sequence ();
7748   else
7749     push_to_sequence (output_reload_insns[rl->opnum]);
7750
7751   rl_reg_rtx = reload_reg_rtx_for_output[j];
7752   mode = GET_MODE (rl_reg_rtx);
7753
7754   reloadreg = rl_reg_rtx;
7755
7756   /* If we need two reload regs, set RELOADREG to the intermediate
7757      one, since it will be stored into OLD.  We might need a secondary
7758      register only for an input reload, so check again here.  */
7759
7760   if (rl->secondary_out_reload >= 0)
7761     {
7762       rtx real_old = old;
7763       int secondary_reload = rl->secondary_out_reload;
7764       int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7765
7766       if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7767           && reg_equiv_mem (REGNO (old)) != 0)
7768         real_old = reg_equiv_mem (REGNO (old));
7769
7770       if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7771         {
7772           rtx second_reloadreg = reloadreg;
7773           reloadreg = rld[secondary_reload].reg_rtx;
7774
7775           /* See if RELOADREG is to be used as a scratch register
7776              or as an intermediate register.  */
7777           if (rl->secondary_out_icode != CODE_FOR_nothing)
7778             {
7779               /* We'd have to add extra code to handle this case.  */
7780               gcc_assert (tertiary_reload < 0);
7781
7782               emit_insn ((GEN_FCN (rl->secondary_out_icode)
7783                           (real_old, second_reloadreg, reloadreg)));
7784               special = 1;
7785             }
7786           else
7787             {
7788               /* See if we need both a scratch and intermediate reload
7789                  register.  */
7790
7791               enum insn_code tertiary_icode
7792                 = rld[secondary_reload].secondary_out_icode;
7793
7794               /* We'd have to add more code for quartary reloads.  */
7795               gcc_assert (tertiary_reload < 0
7796                           || rld[tertiary_reload].secondary_out_reload < 0);
7797
7798               if (GET_MODE (reloadreg) != mode)
7799                 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7800
7801               if (tertiary_icode != CODE_FOR_nothing)
7802                 {
7803                   rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7804
7805                   /* Copy primary reload reg to secondary reload reg.
7806                      (Note that these have been swapped above, then
7807                      secondary reload reg to OLD using our insn.)  */
7808
7809                   /* If REAL_OLD is a paradoxical SUBREG, remove it
7810                      and try to put the opposite SUBREG on
7811                      RELOADREG.  */
7812                   strip_paradoxical_subreg (&real_old, &reloadreg);
7813
7814                   gen_reload (reloadreg, second_reloadreg,
7815                               rl->opnum, rl->when_needed);
7816                   emit_insn ((GEN_FCN (tertiary_icode)
7817                               (real_old, reloadreg, third_reloadreg)));
7818                   special = 1;
7819                 }
7820
7821               else
7822                 {
7823                   /* Copy between the reload regs here and then to
7824                      OUT later.  */
7825
7826                   gen_reload (reloadreg, second_reloadreg,
7827                               rl->opnum, rl->when_needed);
7828                   if (tertiary_reload >= 0)
7829                     {
7830                       rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7831
7832                       gen_reload (third_reloadreg, reloadreg,
7833                                   rl->opnum, rl->when_needed);
7834                       reloadreg = third_reloadreg;
7835                     }
7836                 }
7837             }
7838         }
7839     }
7840
7841   /* Output the last reload insn.  */
7842   if (! special)
7843     {
7844       rtx set;
7845
7846       /* Don't output the last reload if OLD is not the dest of
7847          INSN and is in the src and is clobbered by INSN.  */
7848       if (! flag_expensive_optimizations
7849           || !REG_P (old)
7850           || !(set = single_set (insn))
7851           || rtx_equal_p (old, SET_DEST (set))
7852           || !reg_mentioned_p (old, SET_SRC (set))
7853           || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7854                && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7855         gen_reload (old, reloadreg, rl->opnum,
7856                     rl->when_needed);
7857     }
7858
7859   /* Look at all insns we emitted, just to be safe.  */
7860   for (p = get_insns (); p; p = NEXT_INSN (p))
7861     if (INSN_P (p))
7862       {
7863         rtx pat = PATTERN (p);
7864
7865         /* If this output reload doesn't come from a spill reg,
7866            clear any memory of reloaded copies of the pseudo reg.
7867            If this output reload comes from a spill reg,
7868            reg_has_output_reload will make this do nothing.  */
7869         note_stores (pat, forget_old_reloads_1, NULL);
7870
7871         if (reg_mentioned_p (rl_reg_rtx, pat))
7872           {
7873             rtx set = single_set (insn);
7874             if (reload_spill_index[j] < 0
7875                 && set
7876                 && SET_SRC (set) == rl_reg_rtx)
7877               {
7878                 int src = REGNO (SET_SRC (set));
7879
7880                 reload_spill_index[j] = src;
7881                 SET_HARD_REG_BIT (reg_is_output_reload, src);
7882                 if (find_regno_note (insn, REG_DEAD, src))
7883                   SET_HARD_REG_BIT (reg_reloaded_died, src);
7884               }
7885             if (HARD_REGISTER_P (rl_reg_rtx))
7886               {
7887                 int s = rl->secondary_out_reload;
7888                 set = single_set (p);
7889                 /* If this reload copies only to the secondary reload
7890                    register, the secondary reload does the actual
7891                    store.  */
7892                 if (s >= 0 && set == NULL_RTX)
7893                   /* We can't tell what function the secondary reload
7894                      has and where the actual store to the pseudo is
7895                      made; leave new_spill_reg_store alone.  */
7896                   ;
7897                 else if (s >= 0
7898                          && SET_SRC (set) == rl_reg_rtx
7899                          && SET_DEST (set) == rld[s].reg_rtx)
7900                   {
7901                     /* Usually the next instruction will be the
7902                        secondary reload insn;  if we can confirm
7903                        that it is, setting new_spill_reg_store to
7904                        that insn will allow an extra optimization.  */
7905                     rtx s_reg = rld[s].reg_rtx;
7906                     rtx_insn *next = NEXT_INSN (p);
7907                     rld[s].out = rl->out;
7908                     rld[s].out_reg = rl->out_reg;
7909                     set = single_set (next);
7910                     if (set && SET_SRC (set) == s_reg
7911                         && reload_reg_rtx_reaches_end_p (s_reg, s))
7912                       {
7913                         SET_HARD_REG_BIT (reg_is_output_reload,
7914                                           REGNO (s_reg));
7915                         new_spill_reg_store[REGNO (s_reg)] = next;
7916                       }
7917                   }
7918                 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx, j))
7919                   new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7920               }
7921           }
7922       }
7923
7924   if (rl->when_needed == RELOAD_OTHER)
7925     {
7926       emit_insn (other_output_reload_insns[rl->opnum]);
7927       other_output_reload_insns[rl->opnum] = get_insns ();
7928     }
7929   else
7930     output_reload_insns[rl->opnum] = get_insns ();
7931
7932   if (cfun->can_throw_non_call_exceptions)
7933     copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7934
7935   end_sequence ();
7936 }
7937
7938 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7939    and has the number J.  */
7940 static void
7941 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7942 {
7943   rtx_insn *insn = chain->insn;
7944   rtx old = (rl->in && MEM_P (rl->in)
7945              ? rl->in_reg : rl->in);
7946   rtx reg_rtx = rl->reg_rtx;
7947
7948   if (old && reg_rtx)
7949     {
7950       machine_mode mode;
7951
7952       /* Determine the mode to reload in.
7953          This is very tricky because we have three to choose from.
7954          There is the mode the insn operand wants (rl->inmode).
7955          There is the mode of the reload register RELOADREG.
7956          There is the intrinsic mode of the operand, which we could find
7957          by stripping some SUBREGs.
7958          It turns out that RELOADREG's mode is irrelevant:
7959          we can change that arbitrarily.
7960
7961          Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7962          then the reload reg may not support QImode moves, so use SImode.
7963          If foo is in memory due to spilling a pseudo reg, this is safe,
7964          because the QImode value is in the least significant part of a
7965          slot big enough for a SImode.  If foo is some other sort of
7966          memory reference, then it is impossible to reload this case,
7967          so previous passes had better make sure this never happens.
7968
7969          Then consider a one-word union which has SImode and one of its
7970          members is a float, being fetched as (SUBREG:SF union:SI).
7971          We must fetch that as SFmode because we could be loading into
7972          a float-only register.  In this case OLD's mode is correct.
7973
7974          Consider an immediate integer: it has VOIDmode.  Here we need
7975          to get a mode from something else.
7976
7977          In some cases, there is a fourth mode, the operand's
7978          containing mode.  If the insn specifies a containing mode for
7979          this operand, it overrides all others.
7980
7981          I am not sure whether the algorithm here is always right,
7982          but it does the right things in those cases.  */
7983
7984       mode = GET_MODE (old);
7985       if (mode == VOIDmode)
7986         mode = rl->inmode;
7987
7988       /* We cannot use gen_lowpart_common since it can do the wrong thing
7989          when REG_RTX has a multi-word mode.  Note that REG_RTX must
7990          always be a REG here.  */
7991       if (GET_MODE (reg_rtx) != mode)
7992         reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7993     }
7994   reload_reg_rtx_for_input[j] = reg_rtx;
7995
7996   if (old != 0
7997       /* AUTO_INC reloads need to be handled even if inherited.  We got an
7998          AUTO_INC reload if reload_out is set but reload_out_reg isn't.  */
7999       && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
8000       && ! rtx_equal_p (reg_rtx, old)
8001       && reg_rtx != 0)
8002     emit_input_reload_insns (chain, rld + j, old, j);
8003
8004   /* When inheriting a wider reload, we have a MEM in rl->in,
8005      e.g. inheriting a SImode output reload for
8006      (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10)))  */
8007   if (optimize && reload_inherited[j] && rl->in
8008       && MEM_P (rl->in)
8009       && MEM_P (rl->in_reg)
8010       && reload_spill_index[j] >= 0
8011       && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
8012     rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
8013
8014   /* If we are reloading a register that was recently stored in with an
8015      output-reload, see if we can prove there was
8016      actually no need to store the old value in it.  */
8017
8018   if (optimize
8019       && (reload_inherited[j] || reload_override_in[j])
8020       && reg_rtx
8021       && REG_P (reg_rtx)
8022       && spill_reg_store[REGNO (reg_rtx)] != 0
8023 #if 0
8024       /* There doesn't seem to be any reason to restrict this to pseudos
8025          and doing so loses in the case where we are copying from a
8026          register of the wrong class.  */
8027       && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
8028 #endif
8029       /* The insn might have already some references to stackslots
8030          replaced by MEMs, while reload_out_reg still names the
8031          original pseudo.  */
8032       && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
8033           || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
8034     delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
8035 }
8036
8037 /* Do output reloading for reload RL, which is for the insn described by
8038    CHAIN and has the number J.
8039    ??? At some point we need to support handling output reloads of
8040    JUMP_INSNs or insns that set cc0.  */
8041 static void
8042 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
8043 {
8044   rtx note, old;
8045   rtx_insn *insn = chain->insn;
8046   /* If this is an output reload that stores something that is
8047      not loaded in this same reload, see if we can eliminate a previous
8048      store.  */
8049   rtx pseudo = rl->out_reg;
8050   rtx reg_rtx = rl->reg_rtx;
8051
8052   if (rl->out && reg_rtx)
8053     {
8054       machine_mode mode;
8055
8056       /* Determine the mode to reload in.
8057          See comments above (for input reloading).  */
8058       mode = GET_MODE (rl->out);
8059       if (mode == VOIDmode)
8060         {
8061           /* VOIDmode should never happen for an output.  */
8062           if (asm_noperands (PATTERN (insn)) < 0)
8063             /* It's the compiler's fault.  */
8064             fatal_insn ("VOIDmode on an output", insn);
8065           error_for_asm (insn, "output operand is constant in %<asm%>");
8066           /* Prevent crash--use something we know is valid.  */
8067           mode = word_mode;
8068           rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
8069         }
8070       if (GET_MODE (reg_rtx) != mode)
8071         reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
8072     }
8073   reload_reg_rtx_for_output[j] = reg_rtx;
8074
8075   if (pseudo
8076       && optimize
8077       && REG_P (pseudo)
8078       && ! rtx_equal_p (rl->in_reg, pseudo)
8079       && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
8080       && reg_last_reload_reg[REGNO (pseudo)])
8081     {
8082       int pseudo_no = REGNO (pseudo);
8083       int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
8084
8085       /* We don't need to test full validity of last_regno for
8086          inherit here; we only want to know if the store actually
8087          matches the pseudo.  */
8088       if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
8089           && reg_reloaded_contents[last_regno] == pseudo_no
8090           && spill_reg_store[last_regno]
8091           && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
8092         delete_output_reload (insn, j, last_regno, reg_rtx);
8093     }
8094
8095   old = rl->out_reg;
8096   if (old == 0
8097       || reg_rtx == 0
8098       || rtx_equal_p (old, reg_rtx))
8099     return;
8100
8101   /* An output operand that dies right away does need a reload,
8102      but need not be copied from it.  Show the new location in the
8103      REG_UNUSED note.  */
8104   if ((REG_P (old) || GET_CODE (old) == SCRATCH)
8105       && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
8106     {
8107       XEXP (note, 0) = reg_rtx;
8108       return;
8109     }
8110   /* Likewise for a SUBREG of an operand that dies.  */
8111   else if (GET_CODE (old) == SUBREG
8112            && REG_P (SUBREG_REG (old))
8113            && 0 != (note = find_reg_note (insn, REG_UNUSED,
8114                                           SUBREG_REG (old))))
8115     {
8116       XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
8117       return;
8118     }
8119   else if (GET_CODE (old) == SCRATCH)
8120     /* If we aren't optimizing, there won't be a REG_UNUSED note,
8121        but we don't want to make an output reload.  */
8122     return;
8123
8124   /* If is a JUMP_INSN, we can't support output reloads yet.  */
8125   gcc_assert (NONJUMP_INSN_P (insn));
8126
8127   emit_output_reload_insns (chain, rld + j, j);
8128 }
8129
8130 /* A reload copies values of MODE from register SRC to register DEST.
8131    Return true if it can be treated for inheritance purposes like a
8132    group of reloads, each one reloading a single hard register.  The
8133    caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
8134    occupy the same number of hard registers.  */
8135
8136 static bool
8137 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
8138                      int src ATTRIBUTE_UNUSED,
8139                      machine_mode mode ATTRIBUTE_UNUSED)
8140 {
8141 #ifdef CANNOT_CHANGE_MODE_CLASS
8142   return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
8143           && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
8144 #else
8145   return true;
8146 #endif
8147 }
8148
8149 /* Output insns to reload values in and out of the chosen reload regs.  */
8150
8151 static void
8152 emit_reload_insns (struct insn_chain *chain)
8153 {
8154   rtx_insn *insn = chain->insn;
8155
8156   int j;
8157
8158   CLEAR_HARD_REG_SET (reg_reloaded_died);
8159
8160   for (j = 0; j < reload_n_operands; j++)
8161     input_reload_insns[j] = input_address_reload_insns[j]
8162       = inpaddr_address_reload_insns[j]
8163       = output_reload_insns[j] = output_address_reload_insns[j]
8164       = outaddr_address_reload_insns[j]
8165       = other_output_reload_insns[j] = 0;
8166   other_input_address_reload_insns = 0;
8167   other_input_reload_insns = 0;
8168   operand_reload_insns = 0;
8169   other_operand_reload_insns = 0;
8170
8171   /* Dump reloads into the dump file.  */
8172   if (dump_file)
8173     {
8174       fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
8175       debug_reload_to_stream (dump_file);
8176     }
8177
8178   for (j = 0; j < n_reloads; j++)
8179     if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
8180       {
8181         unsigned int i;
8182
8183         for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
8184           new_spill_reg_store[i] = 0;
8185       }
8186
8187   /* Now output the instructions to copy the data into and out of the
8188      reload registers.  Do these in the order that the reloads were reported,
8189      since reloads of base and index registers precede reloads of operands
8190      and the operands may need the base and index registers reloaded.  */
8191
8192   for (j = 0; j < n_reloads; j++)
8193     {
8194       do_input_reload (chain, rld + j, j);
8195       do_output_reload (chain, rld + j, j);
8196     }
8197
8198   /* Now write all the insns we made for reloads in the order expected by
8199      the allocation functions.  Prior to the insn being reloaded, we write
8200      the following reloads:
8201
8202      RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8203
8204      RELOAD_OTHER reloads.
8205
8206      For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8207      by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8208      RELOAD_FOR_INPUT reload for the operand.
8209
8210      RELOAD_FOR_OPADDR_ADDRS reloads.
8211
8212      RELOAD_FOR_OPERAND_ADDRESS reloads.
8213
8214      After the insn being reloaded, we write the following:
8215
8216      For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8217      by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8218      RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8219      reloads for the operand.  The RELOAD_OTHER output reloads are
8220      output in descending order by reload number.  */
8221
8222   emit_insn_before (other_input_address_reload_insns, insn);
8223   emit_insn_before (other_input_reload_insns, insn);
8224
8225   for (j = 0; j < reload_n_operands; j++)
8226     {
8227       emit_insn_before (inpaddr_address_reload_insns[j], insn);
8228       emit_insn_before (input_address_reload_insns[j], insn);
8229       emit_insn_before (input_reload_insns[j], insn);
8230     }
8231
8232   emit_insn_before (other_operand_reload_insns, insn);
8233   emit_insn_before (operand_reload_insns, insn);
8234
8235   for (j = 0; j < reload_n_operands; j++)
8236     {
8237       rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
8238       x = emit_insn_after (output_address_reload_insns[j], x);
8239       x = emit_insn_after (output_reload_insns[j], x);
8240       emit_insn_after (other_output_reload_insns[j], x);
8241     }
8242
8243   /* For all the spill regs newly reloaded in this instruction,
8244      record what they were reloaded from, so subsequent instructions
8245      can inherit the reloads.
8246
8247      Update spill_reg_store for the reloads of this insn.
8248      Copy the elements that were updated in the loop above.  */
8249
8250   for (j = 0; j < n_reloads; j++)
8251     {
8252       int r = reload_order[j];
8253       int i = reload_spill_index[r];
8254
8255       /* If this is a non-inherited input reload from a pseudo, we must
8256          clear any memory of a previous store to the same pseudo.  Only do
8257          something if there will not be an output reload for the pseudo
8258          being reloaded.  */
8259       if (rld[r].in_reg != 0
8260           && ! (reload_inherited[r] || reload_override_in[r]))
8261         {
8262           rtx reg = rld[r].in_reg;
8263
8264           if (GET_CODE (reg) == SUBREG)
8265             reg = SUBREG_REG (reg);
8266
8267           if (REG_P (reg)
8268               && REGNO (reg) >= FIRST_PSEUDO_REGISTER
8269               && !REGNO_REG_SET_P (&reg_has_output_reload, REGNO (reg)))
8270             {
8271               int nregno = REGNO (reg);
8272
8273               if (reg_last_reload_reg[nregno])
8274                 {
8275                   int last_regno = REGNO (reg_last_reload_reg[nregno]);
8276
8277                   if (reg_reloaded_contents[last_regno] == nregno)
8278                     spill_reg_store[last_regno] = 0;
8279                 }
8280             }
8281         }
8282
8283       /* I is nonneg if this reload used a register.
8284          If rld[r].reg_rtx is 0, this is an optional reload
8285          that we opted to ignore.  */
8286
8287       if (i >= 0 && rld[r].reg_rtx != 0)
8288         {
8289           int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
8290           int k;
8291
8292           /* For a multi register reload, we need to check if all or part
8293              of the value lives to the end.  */
8294           for (k = 0; k < nr; k++)
8295             if (reload_reg_reaches_end_p (i + k, r))
8296               CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
8297
8298           /* Maybe the spill reg contains a copy of reload_out.  */
8299           if (rld[r].out != 0
8300               && (REG_P (rld[r].out)
8301                   || (rld[r].out_reg
8302                       ? REG_P (rld[r].out_reg)
8303                       /* The reload value is an auto-modification of
8304                          some kind.  For PRE_INC, POST_INC, PRE_DEC
8305                          and POST_DEC, we record an equivalence
8306                          between the reload register and the operand
8307                          on the optimistic assumption that we can make
8308                          the equivalence hold.  reload_as_needed must
8309                          then either make it hold or invalidate the
8310                          equivalence.
8311
8312                          PRE_MODIFY and POST_MODIFY addresses are reloaded
8313                          somewhat differently, and allowing them here leads
8314                          to problems.  */
8315                       : (GET_CODE (rld[r].out) != POST_MODIFY
8316                          && GET_CODE (rld[r].out) != PRE_MODIFY))))
8317             {
8318               rtx reg;
8319
8320               reg = reload_reg_rtx_for_output[r];
8321               if (reload_reg_rtx_reaches_end_p (reg, r))
8322                 {
8323                   machine_mode mode = GET_MODE (reg);
8324                   int regno = REGNO (reg);
8325                   int nregs = hard_regno_nregs[regno][mode];
8326                   rtx out = (REG_P (rld[r].out)
8327                              ? rld[r].out
8328                              : rld[r].out_reg
8329                              ? rld[r].out_reg
8330 /* AUTO_INC */               : XEXP (rld[r].in_reg, 0));
8331                   int out_regno = REGNO (out);
8332                   int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
8333                                    : hard_regno_nregs[out_regno][mode]);
8334                   bool piecemeal;
8335
8336                   spill_reg_store[regno] = new_spill_reg_store[regno];
8337                   spill_reg_stored_to[regno] = out;
8338                   reg_last_reload_reg[out_regno] = reg;
8339
8340                   piecemeal = (HARD_REGISTER_NUM_P (out_regno)
8341                                && nregs == out_nregs
8342                                && inherit_piecemeal_p (out_regno, regno, mode));
8343
8344                   /* If OUT_REGNO is a hard register, it may occupy more than
8345                      one register.  If it does, say what is in the
8346                      rest of the registers assuming that both registers
8347                      agree on how many words the object takes.  If not,
8348                      invalidate the subsequent registers.  */
8349
8350                   if (HARD_REGISTER_NUM_P (out_regno))
8351                     for (k = 1; k < out_nregs; k++)
8352                       reg_last_reload_reg[out_regno + k]
8353                         = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8354
8355                   /* Now do the inverse operation.  */
8356                   for (k = 0; k < nregs; k++)
8357                     {
8358                       CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8359                       reg_reloaded_contents[regno + k]
8360                         = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
8361                            ? out_regno
8362                            : out_regno + k);
8363                       reg_reloaded_insn[regno + k] = insn;
8364                       SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8365                       if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8366                         SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8367                                           regno + k);
8368                       else
8369                         CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8370                                             regno + k);
8371                     }
8372                 }
8373             }
8374           /* Maybe the spill reg contains a copy of reload_in.  Only do
8375              something if there will not be an output reload for
8376              the register being reloaded.  */
8377           else if (rld[r].out_reg == 0
8378                    && rld[r].in != 0
8379                    && ((REG_P (rld[r].in)
8380                         && !HARD_REGISTER_P (rld[r].in)
8381                         && !REGNO_REG_SET_P (&reg_has_output_reload,
8382                                              REGNO (rld[r].in)))
8383                        || (REG_P (rld[r].in_reg)
8384                            && !REGNO_REG_SET_P (&reg_has_output_reload,
8385                                                 REGNO (rld[r].in_reg))))
8386                    && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
8387             {
8388               rtx reg;
8389
8390               reg = reload_reg_rtx_for_input[r];
8391               if (reload_reg_rtx_reaches_end_p (reg, r))
8392                 {
8393                   machine_mode mode;
8394                   int regno;
8395                   int nregs;
8396                   int in_regno;
8397                   int in_nregs;
8398                   rtx in;
8399                   bool piecemeal;
8400
8401                   mode = GET_MODE (reg);
8402                   regno = REGNO (reg);
8403                   nregs = hard_regno_nregs[regno][mode];
8404                   if (REG_P (rld[r].in)
8405                       && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
8406                     in = rld[r].in;
8407                   else if (REG_P (rld[r].in_reg))
8408                     in = rld[r].in_reg;
8409                   else
8410                     in = XEXP (rld[r].in_reg, 0);
8411                   in_regno = REGNO (in);
8412
8413                   in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
8414                               : hard_regno_nregs[in_regno][mode]);
8415
8416                   reg_last_reload_reg[in_regno] = reg;
8417
8418                   piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8419                                && nregs == in_nregs
8420                                && inherit_piecemeal_p (regno, in_regno, mode));
8421
8422                   if (HARD_REGISTER_NUM_P (in_regno))
8423                     for (k = 1; k < in_nregs; k++)
8424                       reg_last_reload_reg[in_regno + k]
8425                         = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8426
8427                   /* Unless we inherited this reload, show we haven't
8428                      recently done a store.
8429                      Previous stores of inherited auto_inc expressions
8430                      also have to be discarded.  */
8431                   if (! reload_inherited[r]
8432                       || (rld[r].out && ! rld[r].out_reg))
8433                     spill_reg_store[regno] = 0;
8434
8435                   for (k = 0; k < nregs; k++)
8436                     {
8437                       CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8438                       reg_reloaded_contents[regno + k]
8439                         = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8440                            ? in_regno
8441                            : in_regno + k);
8442                       reg_reloaded_insn[regno + k] = insn;
8443                       SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8444                       if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8445                         SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8446                                           regno + k);
8447                       else
8448                         CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8449                                             regno + k);
8450                     }
8451                 }
8452             }
8453         }
8454
8455       /* The following if-statement was #if 0'd in 1.34 (or before...).
8456          It's reenabled in 1.35 because supposedly nothing else
8457          deals with this problem.  */
8458
8459       /* If a register gets output-reloaded from a non-spill register,
8460          that invalidates any previous reloaded copy of it.
8461          But forget_old_reloads_1 won't get to see it, because
8462          it thinks only about the original insn.  So invalidate it here.
8463          Also do the same thing for RELOAD_OTHER constraints where the
8464          output is discarded.  */
8465       if (i < 0
8466           && ((rld[r].out != 0
8467                && (REG_P (rld[r].out)
8468                    || (MEM_P (rld[r].out)
8469                        && REG_P (rld[r].out_reg))))
8470               || (rld[r].out == 0 && rld[r].out_reg
8471                   && REG_P (rld[r].out_reg))))
8472         {
8473           rtx out = ((rld[r].out && REG_P (rld[r].out))
8474                      ? rld[r].out : rld[r].out_reg);
8475           int out_regno = REGNO (out);
8476           machine_mode mode = GET_MODE (out);
8477
8478           /* REG_RTX is now set or clobbered by the main instruction.
8479              As the comment above explains, forget_old_reloads_1 only
8480              sees the original instruction, and there is no guarantee
8481              that the original instruction also clobbered REG_RTX.
8482              For example, if find_reloads sees that the input side of
8483              a matched operand pair dies in this instruction, it may
8484              use the input register as the reload register.
8485
8486              Calling forget_old_reloads_1 is a waste of effort if
8487              REG_RTX is also the output register.
8488
8489              If we know that REG_RTX holds the value of a pseudo
8490              register, the code after the call will record that fact.  */
8491           if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8492             forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8493
8494           if (!HARD_REGISTER_NUM_P (out_regno))
8495             {
8496               rtx src_reg;
8497               rtx_insn *store_insn = NULL;
8498
8499               reg_last_reload_reg[out_regno] = 0;
8500
8501               /* If we can find a hard register that is stored, record
8502                  the storing insn so that we may delete this insn with
8503                  delete_output_reload.  */
8504               src_reg = reload_reg_rtx_for_output[r];
8505
8506               if (src_reg)
8507                 {
8508                   if (reload_reg_rtx_reaches_end_p (src_reg, r))
8509                     store_insn = new_spill_reg_store[REGNO (src_reg)];
8510                   else
8511                     src_reg = NULL_RTX;
8512                 }
8513               else
8514                 {
8515                   /* If this is an optional reload, try to find the
8516                      source reg from an input reload.  */
8517                   rtx set = single_set (insn);
8518                   if (set && SET_DEST (set) == rld[r].out)
8519                     {
8520                       int k;
8521
8522                       src_reg = SET_SRC (set);
8523                       store_insn = insn;
8524                       for (k = 0; k < n_reloads; k++)
8525                         {
8526                           if (rld[k].in == src_reg)
8527                             {
8528                               src_reg = reload_reg_rtx_for_input[k];
8529                               break;
8530                             }
8531                         }
8532                     }
8533                 }
8534               if (src_reg && REG_P (src_reg)
8535                   && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8536                 {
8537                   int src_regno, src_nregs, k;
8538                   rtx note;
8539
8540                   gcc_assert (GET_MODE (src_reg) == mode);
8541                   src_regno = REGNO (src_reg);
8542                   src_nregs = hard_regno_nregs[src_regno][mode];
8543                   /* The place where to find a death note varies with
8544                      PRESERVE_DEATH_INFO_REGNO_P .  The condition is not
8545                      necessarily checked exactly in the code that moves
8546                      notes, so just check both locations.  */
8547                   note = find_regno_note (insn, REG_DEAD, src_regno);
8548                   if (! note && store_insn)
8549                     note = find_regno_note (store_insn, REG_DEAD, src_regno);
8550                   for (k = 0; k < src_nregs; k++)
8551                     {
8552                       spill_reg_store[src_regno + k] = store_insn;
8553                       spill_reg_stored_to[src_regno + k] = out;
8554                       reg_reloaded_contents[src_regno + k] = out_regno;
8555                       reg_reloaded_insn[src_regno + k] = store_insn;
8556                       CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8557                       SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8558                       if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8559                                                           mode))
8560                         SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8561                                           src_regno + k);
8562                       else
8563                         CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8564                                             src_regno + k);
8565                       SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8566                       if (note)
8567                         SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8568                       else
8569                         CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8570                     }
8571                   reg_last_reload_reg[out_regno] = src_reg;
8572                   /* We have to set reg_has_output_reload here, or else
8573                      forget_old_reloads_1 will clear reg_last_reload_reg
8574                      right away.  */
8575                   SET_REGNO_REG_SET (&reg_has_output_reload,
8576                                      out_regno);
8577                 }
8578             }
8579           else
8580             {
8581               int k, out_nregs = hard_regno_nregs[out_regno][mode];
8582
8583               for (k = 0; k < out_nregs; k++)
8584                 reg_last_reload_reg[out_regno + k] = 0;
8585             }
8586         }
8587     }
8588   IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8589 }
8590 \f
8591 /* Go through the motions to emit INSN and test if it is strictly valid.
8592    Return the emitted insn if valid, else return NULL.  */
8593
8594 static rtx_insn *
8595 emit_insn_if_valid_for_reload (rtx pat)
8596 {
8597   rtx_insn *last = get_last_insn ();
8598   int code;
8599
8600   rtx_insn *insn = emit_insn (pat);
8601   code = recog_memoized (insn);
8602
8603   if (code >= 0)
8604     {
8605       extract_insn (insn);
8606       /* We want constrain operands to treat this insn strictly in its
8607          validity determination, i.e., the way it would after reload has
8608          completed.  */
8609       if (constrain_operands (1, get_enabled_alternatives (insn)))
8610         return insn;
8611     }
8612
8613   delete_insns_since (last);
8614   return NULL;
8615 }
8616
8617 /* Emit code to perform a reload from IN (which may be a reload register) to
8618    OUT (which may also be a reload register).  IN or OUT is from operand
8619    OPNUM with reload type TYPE.
8620
8621    Returns first insn emitted.  */
8622
8623 static rtx_insn *
8624 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8625 {
8626   rtx_insn *last = get_last_insn ();
8627   rtx_insn *tem;
8628 #ifdef SECONDARY_MEMORY_NEEDED
8629   rtx tem1, tem2;
8630 #endif
8631
8632   /* If IN is a paradoxical SUBREG, remove it and try to put the
8633      opposite SUBREG on OUT.  Likewise for a paradoxical SUBREG on OUT.  */
8634   if (!strip_paradoxical_subreg (&in, &out))
8635     strip_paradoxical_subreg (&out, &in);
8636
8637   /* How to do this reload can get quite tricky.  Normally, we are being
8638      asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8639      register that didn't get a hard register.  In that case we can just
8640      call emit_move_insn.
8641
8642      We can also be asked to reload a PLUS that adds a register or a MEM to
8643      another register, constant or MEM.  This can occur during frame pointer
8644      elimination and while reloading addresses.  This case is handled by
8645      trying to emit a single insn to perform the add.  If it is not valid,
8646      we use a two insn sequence.
8647
8648      Or we can be asked to reload an unary operand that was a fragment of
8649      an addressing mode, into a register.  If it isn't recognized as-is,
8650      we try making the unop operand and the reload-register the same:
8651      (set reg:X (unop:X expr:Y))
8652      -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8653
8654      Finally, we could be called to handle an 'o' constraint by putting
8655      an address into a register.  In that case, we first try to do this
8656      with a named pattern of "reload_load_address".  If no such pattern
8657      exists, we just emit a SET insn and hope for the best (it will normally
8658      be valid on machines that use 'o').
8659
8660      This entire process is made complex because reload will never
8661      process the insns we generate here and so we must ensure that
8662      they will fit their constraints and also by the fact that parts of
8663      IN might be being reloaded separately and replaced with spill registers.
8664      Because of this, we are, in some sense, just guessing the right approach
8665      here.  The one listed above seems to work.
8666
8667      ??? At some point, this whole thing needs to be rethought.  */
8668
8669   if (GET_CODE (in) == PLUS
8670       && (REG_P (XEXP (in, 0))
8671           || GET_CODE (XEXP (in, 0)) == SUBREG
8672           || MEM_P (XEXP (in, 0)))
8673       && (REG_P (XEXP (in, 1))
8674           || GET_CODE (XEXP (in, 1)) == SUBREG
8675           || CONSTANT_P (XEXP (in, 1))
8676           || MEM_P (XEXP (in, 1))))
8677     {
8678       /* We need to compute the sum of a register or a MEM and another
8679          register, constant, or MEM, and put it into the reload
8680          register.  The best possible way of doing this is if the machine
8681          has a three-operand ADD insn that accepts the required operands.
8682
8683          The simplest approach is to try to generate such an insn and see if it
8684          is recognized and matches its constraints.  If so, it can be used.
8685
8686          It might be better not to actually emit the insn unless it is valid,
8687          but we need to pass the insn as an operand to `recog' and
8688          `extract_insn' and it is simpler to emit and then delete the insn if
8689          not valid than to dummy things up.  */
8690
8691       rtx op0, op1, tem;
8692       rtx_insn *insn;
8693       enum insn_code code;
8694
8695       op0 = find_replacement (&XEXP (in, 0));
8696       op1 = find_replacement (&XEXP (in, 1));
8697
8698       /* Since constraint checking is strict, commutativity won't be
8699          checked, so we need to do that here to avoid spurious failure
8700          if the add instruction is two-address and the second operand
8701          of the add is the same as the reload reg, which is frequently
8702          the case.  If the insn would be A = B + A, rearrange it so
8703          it will be A = A + B as constrain_operands expects.  */
8704
8705       if (REG_P (XEXP (in, 1))
8706           && REGNO (out) == REGNO (XEXP (in, 1)))
8707         tem = op0, op0 = op1, op1 = tem;
8708
8709       if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8710         in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8711
8712       insn = emit_insn_if_valid_for_reload (gen_rtx_SET (out, in));
8713       if (insn)
8714         return insn;
8715
8716       /* If that failed, we must use a conservative two-insn sequence.
8717
8718          Use a move to copy one operand into the reload register.  Prefer
8719          to reload a constant, MEM or pseudo since the move patterns can
8720          handle an arbitrary operand.  If OP1 is not a constant, MEM or
8721          pseudo and OP1 is not a valid operand for an add instruction, then
8722          reload OP1.
8723
8724          After reloading one of the operands into the reload register, add
8725          the reload register to the output register.
8726
8727          If there is another way to do this for a specific machine, a
8728          DEFINE_PEEPHOLE should be specified that recognizes the sequence
8729          we emit below.  */
8730
8731       code = optab_handler (add_optab, GET_MODE (out));
8732
8733       if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8734           || (REG_P (op1)
8735               && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8736           || (code != CODE_FOR_nothing
8737               && !insn_operand_matches (code, 2, op1)))
8738         tem = op0, op0 = op1, op1 = tem;
8739
8740       gen_reload (out, op0, opnum, type);
8741
8742       /* If OP0 and OP1 are the same, we can use OUT for OP1.
8743          This fixes a problem on the 32K where the stack pointer cannot
8744          be used as an operand of an add insn.  */
8745
8746       if (rtx_equal_p (op0, op1))
8747         op1 = out;
8748
8749       insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8750       if (insn)
8751         {
8752           /* Add a REG_EQUIV note so that find_equiv_reg can find it.  */
8753           set_dst_reg_note (insn, REG_EQUIV, in, out);
8754           return insn;
8755         }
8756
8757       /* If that failed, copy the address register to the reload register.
8758          Then add the constant to the reload register.  */
8759
8760       gcc_assert (!reg_overlap_mentioned_p (out, op0));
8761       gen_reload (out, op1, opnum, type);
8762       insn = emit_insn (gen_add2_insn (out, op0));
8763       set_dst_reg_note (insn, REG_EQUIV, in, out);
8764     }
8765
8766 #ifdef SECONDARY_MEMORY_NEEDED
8767   /* If we need a memory location to do the move, do it that way.  */
8768   else if ((tem1 = replaced_subreg (in), tem2 = replaced_subreg (out),
8769             (REG_P (tem1) && REG_P (tem2)))
8770            && REGNO (tem1) < FIRST_PSEUDO_REGISTER
8771            && REGNO (tem2) < FIRST_PSEUDO_REGISTER
8772            && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem1)),
8773                                        REGNO_REG_CLASS (REGNO (tem2)),
8774                                        GET_MODE (out)))
8775     {
8776       /* Get the memory to use and rewrite both registers to its mode.  */
8777       rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8778
8779       if (GET_MODE (loc) != GET_MODE (out))
8780         out = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (out));
8781
8782       if (GET_MODE (loc) != GET_MODE (in))
8783         in = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (in));
8784
8785       gen_reload (loc, in, opnum, type);
8786       gen_reload (out, loc, opnum, type);
8787     }
8788 #endif
8789   else if (REG_P (out) && UNARY_P (in))
8790     {
8791       rtx insn;
8792       rtx op1;
8793       rtx out_moded;
8794       rtx_insn *set;
8795
8796       op1 = find_replacement (&XEXP (in, 0));
8797       if (op1 != XEXP (in, 0))
8798         in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8799
8800       /* First, try a plain SET.  */
8801       set = emit_insn_if_valid_for_reload (gen_rtx_SET (out, in));
8802       if (set)
8803         return set;
8804
8805       /* If that failed, move the inner operand to the reload
8806          register, and try the same unop with the inner expression
8807          replaced with the reload register.  */
8808
8809       if (GET_MODE (op1) != GET_MODE (out))
8810         out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8811       else
8812         out_moded = out;
8813
8814       gen_reload (out_moded, op1, opnum, type);
8815
8816       insn = gen_rtx_SET (out, gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8817                                               out_moded));
8818       insn = emit_insn_if_valid_for_reload (insn);
8819       if (insn)
8820         {
8821           set_unique_reg_note (insn, REG_EQUIV, in);
8822           return as_a <rtx_insn *> (insn);
8823         }
8824
8825       fatal_insn ("failure trying to reload:", set);
8826     }
8827   /* If IN is a simple operand, use gen_move_insn.  */
8828   else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8829     {
8830       tem = emit_insn (gen_move_insn (out, in));
8831       /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note.  */
8832       mark_jump_label (in, tem, 0);
8833     }
8834
8835 #ifdef HAVE_reload_load_address
8836   else if (HAVE_reload_load_address)
8837     emit_insn (gen_reload_load_address (out, in));
8838 #endif
8839
8840   /* Otherwise, just write (set OUT IN) and hope for the best.  */
8841   else
8842     emit_insn (gen_rtx_SET (out, in));
8843
8844   /* Return the first insn emitted.
8845      We can not just return get_last_insn, because there may have
8846      been multiple instructions emitted.  Also note that gen_move_insn may
8847      emit more than one insn itself, so we can not assume that there is one
8848      insn emitted per emit_insn_before call.  */
8849
8850   return last ? NEXT_INSN (last) : get_insns ();
8851 }
8852 \f
8853 /* Delete a previously made output-reload whose result we now believe
8854    is not needed.  First we double-check.
8855
8856    INSN is the insn now being processed.
8857    LAST_RELOAD_REG is the hard register number for which we want to delete
8858    the last output reload.
8859    J is the reload-number that originally used REG.  The caller has made
8860    certain that reload J doesn't use REG any longer for input.
8861    NEW_RELOAD_REG is reload register that reload J is using for REG.  */
8862
8863 static void
8864 delete_output_reload (rtx_insn *insn, int j, int last_reload_reg,
8865                       rtx new_reload_reg)
8866 {
8867   rtx_insn *output_reload_insn = spill_reg_store[last_reload_reg];
8868   rtx reg = spill_reg_stored_to[last_reload_reg];
8869   int k;
8870   int n_occurrences;
8871   int n_inherited = 0;
8872   rtx substed;
8873   unsigned regno;
8874   int nregs;
8875
8876   /* It is possible that this reload has been only used to set another reload
8877      we eliminated earlier and thus deleted this instruction too.  */
8878   if (output_reload_insn->deleted ())
8879     return;
8880
8881   /* Get the raw pseudo-register referred to.  */
8882
8883   while (GET_CODE (reg) == SUBREG)
8884     reg = SUBREG_REG (reg);
8885   substed = reg_equiv_memory_loc (REGNO (reg));
8886
8887   /* This is unsafe if the operand occurs more often in the current
8888      insn than it is inherited.  */
8889   for (k = n_reloads - 1; k >= 0; k--)
8890     {
8891       rtx reg2 = rld[k].in;
8892       if (! reg2)
8893         continue;
8894       if (MEM_P (reg2) || reload_override_in[k])
8895         reg2 = rld[k].in_reg;
8896 #ifdef AUTO_INC_DEC
8897       if (rld[k].out && ! rld[k].out_reg)
8898         reg2 = XEXP (rld[k].in_reg, 0);
8899 #endif
8900       while (GET_CODE (reg2) == SUBREG)
8901         reg2 = SUBREG_REG (reg2);
8902       if (rtx_equal_p (reg2, reg))
8903         {
8904           if (reload_inherited[k] || reload_override_in[k] || k == j)
8905             n_inherited++;
8906           else
8907             return;
8908         }
8909     }
8910   n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8911   if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8912     n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8913                                         reg, 0);
8914   if (substed)
8915     n_occurrences += count_occurrences (PATTERN (insn),
8916                                         eliminate_regs (substed, VOIDmode,
8917                                                         NULL_RTX), 0);
8918   for (rtx i1 = reg_equiv_alt_mem_list (REGNO (reg)); i1; i1 = XEXP (i1, 1))
8919     {
8920       gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8921       n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8922     }
8923   if (n_occurrences > n_inherited)
8924     return;
8925
8926   regno = REGNO (reg);
8927   if (regno >= FIRST_PSEUDO_REGISTER)
8928     nregs = 1;
8929   else
8930     nregs = hard_regno_nregs[regno][GET_MODE (reg)];
8931
8932   /* If the pseudo-reg we are reloading is no longer referenced
8933      anywhere between the store into it and here,
8934      and we're within the same basic block, then the value can only
8935      pass through the reload reg and end up here.
8936      Otherwise, give up--return.  */
8937   for (rtx_insn *i1 = NEXT_INSN (output_reload_insn);
8938        i1 != insn; i1 = NEXT_INSN (i1))
8939     {
8940       if (NOTE_INSN_BASIC_BLOCK_P (i1))
8941         return;
8942       if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8943           && refers_to_regno_p (regno, regno + nregs, PATTERN (i1), NULL))
8944         {
8945           /* If this is USE in front of INSN, we only have to check that
8946              there are no more references than accounted for by inheritance.  */
8947           while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8948             {
8949               n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8950               i1 = NEXT_INSN (i1);
8951             }
8952           if (n_occurrences <= n_inherited && i1 == insn)
8953             break;
8954           return;
8955         }
8956     }
8957
8958   /* We will be deleting the insn.  Remove the spill reg information.  */
8959   for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8960     {
8961       spill_reg_store[last_reload_reg + k] = 0;
8962       spill_reg_stored_to[last_reload_reg + k] = 0;
8963     }
8964
8965   /* The caller has already checked that REG dies or is set in INSN.
8966      It has also checked that we are optimizing, and thus some
8967      inaccuracies in the debugging information are acceptable.
8968      So we could just delete output_reload_insn.  But in some cases
8969      we can improve the debugging information without sacrificing
8970      optimization - maybe even improving the code: See if the pseudo
8971      reg has been completely replaced with reload regs.  If so, delete
8972      the store insn and forget we had a stack slot for the pseudo.  */
8973   if (rld[j].out != rld[j].in
8974       && REG_N_DEATHS (REGNO (reg)) == 1
8975       && REG_N_SETS (REGNO (reg)) == 1
8976       && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8977       && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8978     {
8979       rtx_insn *i2;
8980
8981       /* We know that it was used only between here and the beginning of
8982          the current basic block.  (We also know that the last use before
8983          INSN was the output reload we are thinking of deleting, but never
8984          mind that.)  Search that range; see if any ref remains.  */
8985       for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8986         {
8987           rtx set = single_set (i2);
8988
8989           /* Uses which just store in the pseudo don't count,
8990              since if they are the only uses, they are dead.  */
8991           if (set != 0 && SET_DEST (set) == reg)
8992             continue;
8993           if (LABEL_P (i2) || JUMP_P (i2))
8994             break;
8995           if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8996               && reg_mentioned_p (reg, PATTERN (i2)))
8997             {
8998               /* Some other ref remains; just delete the output reload we
8999                  know to be dead.  */
9000               delete_address_reloads (output_reload_insn, insn);
9001               delete_insn (output_reload_insn);
9002               return;
9003             }
9004         }
9005
9006       /* Delete the now-dead stores into this pseudo.  Note that this
9007          loop also takes care of deleting output_reload_insn.  */
9008       for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
9009         {
9010           rtx set = single_set (i2);
9011
9012           if (set != 0 && SET_DEST (set) == reg)
9013             {
9014               delete_address_reloads (i2, insn);
9015               delete_insn (i2);
9016             }
9017           if (LABEL_P (i2) || JUMP_P (i2))
9018             break;
9019         }
9020
9021       /* For the debugging info, say the pseudo lives in this reload reg.  */
9022       reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
9023       if (ira_conflicts_p)
9024         /* Inform IRA about the change.  */
9025         ira_mark_allocation_change (REGNO (reg));
9026       alter_reg (REGNO (reg), -1, false);
9027     }
9028   else
9029     {
9030       delete_address_reloads (output_reload_insn, insn);
9031       delete_insn (output_reload_insn);
9032     }
9033 }
9034
9035 /* We are going to delete DEAD_INSN.  Recursively delete loads of
9036    reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
9037    CURRENT_INSN is being reloaded, so we have to check its reloads too.  */
9038 static void
9039 delete_address_reloads (rtx_insn *dead_insn, rtx_insn *current_insn)
9040 {
9041   rtx set = single_set (dead_insn);
9042   rtx set2, dst;
9043   rtx_insn *prev, *next;
9044   if (set)
9045     {
9046       rtx dst = SET_DEST (set);
9047       if (MEM_P (dst))
9048         delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
9049     }
9050   /* If we deleted the store from a reloaded post_{in,de}c expression,
9051      we can delete the matching adds.  */
9052   prev = PREV_INSN (dead_insn);
9053   next = NEXT_INSN (dead_insn);
9054   if (! prev || ! next)
9055     return;
9056   set = single_set (next);
9057   set2 = single_set (prev);
9058   if (! set || ! set2
9059       || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
9060       || !CONST_INT_P (XEXP (SET_SRC (set), 1))
9061       || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
9062     return;
9063   dst = SET_DEST (set);
9064   if (! rtx_equal_p (dst, SET_DEST (set2))
9065       || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
9066       || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
9067       || (INTVAL (XEXP (SET_SRC (set), 1))
9068           != -INTVAL (XEXP (SET_SRC (set2), 1))))
9069     return;
9070   delete_related_insns (prev);
9071   delete_related_insns (next);
9072 }
9073
9074 /* Subfunction of delete_address_reloads: process registers found in X.  */
9075 static void
9076 delete_address_reloads_1 (rtx_insn *dead_insn, rtx x, rtx_insn *current_insn)
9077 {
9078   rtx_insn *prev, *i2;
9079   rtx set, dst;
9080   int i, j;
9081   enum rtx_code code = GET_CODE (x);
9082
9083   if (code != REG)
9084     {
9085       const char *fmt = GET_RTX_FORMAT (code);
9086       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9087         {
9088           if (fmt[i] == 'e')
9089             delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
9090           else if (fmt[i] == 'E')
9091             {
9092               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9093                 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
9094                                           current_insn);
9095             }
9096         }
9097       return;
9098     }
9099
9100   if (spill_reg_order[REGNO (x)] < 0)
9101     return;
9102
9103   /* Scan backwards for the insn that sets x.  This might be a way back due
9104      to inheritance.  */
9105   for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
9106     {
9107       code = GET_CODE (prev);
9108       if (code == CODE_LABEL || code == JUMP_INSN)
9109         return;
9110       if (!INSN_P (prev))
9111         continue;
9112       if (reg_set_p (x, PATTERN (prev)))
9113         break;
9114       if (reg_referenced_p (x, PATTERN (prev)))
9115         return;
9116     }
9117   if (! prev || INSN_UID (prev) < reload_first_uid)
9118     return;
9119   /* Check that PREV only sets the reload register.  */
9120   set = single_set (prev);
9121   if (! set)
9122     return;
9123   dst = SET_DEST (set);
9124   if (!REG_P (dst)
9125       || ! rtx_equal_p (dst, x))
9126     return;
9127   if (! reg_set_p (dst, PATTERN (dead_insn)))
9128     {
9129       /* Check if DST was used in a later insn -
9130          it might have been inherited.  */
9131       for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
9132         {
9133           if (LABEL_P (i2))
9134             break;
9135           if (! INSN_P (i2))
9136             continue;
9137           if (reg_referenced_p (dst, PATTERN (i2)))
9138             {
9139               /* If there is a reference to the register in the current insn,
9140                  it might be loaded in a non-inherited reload.  If no other
9141                  reload uses it, that means the register is set before
9142                  referenced.  */
9143               if (i2 == current_insn)
9144                 {
9145                   for (j = n_reloads - 1; j >= 0; j--)
9146                     if ((rld[j].reg_rtx == dst && reload_inherited[j])
9147                         || reload_override_in[j] == dst)
9148                       return;
9149                   for (j = n_reloads - 1; j >= 0; j--)
9150                     if (rld[j].in && rld[j].reg_rtx == dst)
9151                       break;
9152                   if (j >= 0)
9153                     break;
9154                 }
9155               return;
9156             }
9157           if (JUMP_P (i2))
9158             break;
9159           /* If DST is still live at CURRENT_INSN, check if it is used for
9160              any reload.  Note that even if CURRENT_INSN sets DST, we still
9161              have to check the reloads.  */
9162           if (i2 == current_insn)
9163             {
9164               for (j = n_reloads - 1; j >= 0; j--)
9165                 if ((rld[j].reg_rtx == dst && reload_inherited[j])
9166                     || reload_override_in[j] == dst)
9167                   return;
9168               /* ??? We can't finish the loop here, because dst might be
9169                  allocated to a pseudo in this block if no reload in this
9170                  block needs any of the classes containing DST - see
9171                  spill_hard_reg.  There is no easy way to tell this, so we
9172                  have to scan till the end of the basic block.  */
9173             }
9174           if (reg_set_p (dst, PATTERN (i2)))
9175             break;
9176         }
9177     }
9178   delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
9179   reg_reloaded_contents[REGNO (dst)] = -1;
9180   delete_insn (prev);
9181 }
9182 \f
9183 /* Output reload-insns to reload VALUE into RELOADREG.
9184    VALUE is an autoincrement or autodecrement RTX whose operand
9185    is a register or memory location;
9186    so reloading involves incrementing that location.
9187    IN is either identical to VALUE, or some cheaper place to reload from.
9188
9189    INC_AMOUNT is the number to increment or decrement by (always positive).
9190    This cannot be deduced from VALUE.  */
9191
9192 static void
9193 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
9194 {
9195   /* REG or MEM to be copied and incremented.  */
9196   rtx incloc = find_replacement (&XEXP (value, 0));
9197   /* Nonzero if increment after copying.  */
9198   int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
9199               || GET_CODE (value) == POST_MODIFY);
9200   rtx_insn *last;
9201   rtx inc;
9202   rtx_insn *add_insn;
9203   int code;
9204   rtx real_in = in == value ? incloc : in;
9205
9206   /* No hard register is equivalent to this register after
9207      inc/dec operation.  If REG_LAST_RELOAD_REG were nonzero,
9208      we could inc/dec that register as well (maybe even using it for
9209      the source), but I'm not sure it's worth worrying about.  */
9210   if (REG_P (incloc))
9211     reg_last_reload_reg[REGNO (incloc)] = 0;
9212
9213   if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
9214     {
9215       gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
9216       inc = find_replacement (&XEXP (XEXP (value, 1), 1));
9217     }
9218   else
9219     {
9220       if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
9221         inc_amount = -inc_amount;
9222
9223       inc = GEN_INT (inc_amount);
9224     }
9225
9226   /* If this is post-increment, first copy the location to the reload reg.  */
9227   if (post && real_in != reloadreg)
9228     emit_insn (gen_move_insn (reloadreg, real_in));
9229
9230   if (in == value)
9231     {
9232       /* See if we can directly increment INCLOC.  Use a method similar to
9233          that in gen_reload.  */
9234
9235       last = get_last_insn ();
9236       add_insn = emit_insn (gen_rtx_SET (incloc,
9237                                          gen_rtx_PLUS (GET_MODE (incloc),
9238                                                        incloc, inc)));
9239
9240       code = recog_memoized (add_insn);
9241       if (code >= 0)
9242         {
9243           extract_insn (add_insn);
9244           if (constrain_operands (1, get_enabled_alternatives (add_insn)))
9245             {
9246               /* If this is a pre-increment and we have incremented the value
9247                  where it lives, copy the incremented value to RELOADREG to
9248                  be used as an address.  */
9249
9250               if (! post)
9251                 emit_insn (gen_move_insn (reloadreg, incloc));
9252               return;
9253             }
9254         }
9255       delete_insns_since (last);
9256     }
9257
9258   /* If couldn't do the increment directly, must increment in RELOADREG.
9259      The way we do this depends on whether this is pre- or post-increment.
9260      For pre-increment, copy INCLOC to the reload register, increment it
9261      there, then save back.  */
9262
9263   if (! post)
9264     {
9265       if (in != reloadreg)
9266         emit_insn (gen_move_insn (reloadreg, real_in));
9267       emit_insn (gen_add2_insn (reloadreg, inc));
9268       emit_insn (gen_move_insn (incloc, reloadreg));
9269     }
9270   else
9271     {
9272       /* Postincrement.
9273          Because this might be a jump insn or a compare, and because RELOADREG
9274          may not be available after the insn in an input reload, we must do
9275          the incrementation before the insn being reloaded for.
9276
9277          We have already copied IN to RELOADREG.  Increment the copy in
9278          RELOADREG, save that back, then decrement RELOADREG so it has
9279          the original value.  */
9280
9281       emit_insn (gen_add2_insn (reloadreg, inc));
9282       emit_insn (gen_move_insn (incloc, reloadreg));
9283       if (CONST_INT_P (inc))
9284         emit_insn (gen_add2_insn (reloadreg,
9285                                   gen_int_mode (-INTVAL (inc),
9286                                                 GET_MODE (reloadreg))));
9287       else
9288         emit_insn (gen_sub2_insn (reloadreg, inc));
9289     }
9290 }
9291 \f
9292 #ifdef AUTO_INC_DEC
9293 static void
9294 add_auto_inc_notes (rtx_insn *insn, rtx x)
9295 {
9296   enum rtx_code code = GET_CODE (x);
9297   const char *fmt;
9298   int i, j;
9299
9300   if (code == MEM && auto_inc_p (XEXP (x, 0)))
9301     {
9302       add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
9303       return;
9304     }
9305
9306   /* Scan all the operand sub-expressions.  */
9307   fmt = GET_RTX_FORMAT (code);
9308   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9309     {
9310       if (fmt[i] == 'e')
9311         add_auto_inc_notes (insn, XEXP (x, i));
9312       else if (fmt[i] == 'E')
9313         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9314           add_auto_inc_notes (insn, XVECEXP (x, i, j));
9315     }
9316 }
9317 #endif