1 /* Subroutines used for code generation for RISC-V.
2 Copyright (C) 2011-2018 Free Software Foundation, Inc.
3 Contributed by Andrew Waterman (andrew@sifive.com).
4 Based on MIPS target for GNU compiler.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 #define IN_TARGET_CODE 1
26 #include "coretypes.h"
30 #include "insn-config.h"
31 #include "insn-attr.h"
36 #include "stringpool.h"
39 #include "stor-layout.h"
48 #include "target-def.h"
49 #include "basic-block.h"
54 #include "diagnostic.h"
58 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
59 #define UNSPEC_ADDRESS_P(X) \
60 (GET_CODE (X) == UNSPEC \
61 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
62 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
64 /* Extract the symbol or label from UNSPEC wrapper X. */
65 #define UNSPEC_ADDRESS(X) \
68 /* Extract the symbol type from UNSPEC wrapper X. */
69 #define UNSPEC_ADDRESS_TYPE(X) \
70 ((enum riscv_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
72 /* True if bit BIT is set in VALUE. */
73 #define BITSET_P(VALUE, BIT) (((VALUE) & (1ULL << (BIT))) != 0)
75 /* Classifies an address.
78 A natural register + offset address. The register satisfies
79 riscv_valid_base_register_p and the offset is a const_arith_operand.
82 A LO_SUM rtx. The first operand is a valid base register and
83 the second operand is a symbolic address.
86 A signed 16-bit constant address.
89 A constant symbolic address. */
90 enum riscv_address_type
{
97 /* Information about a function's frame layout. */
98 struct GTY(()) riscv_frame_info
{
99 /* The size of the frame in bytes. */
100 HOST_WIDE_INT total_size
;
102 /* Bit X is set if the function saves or restores GPR X. */
105 /* Likewise FPR X. */
108 /* How much the GPR save/restore routines adjust sp (or 0 if unused). */
109 unsigned save_libcall_adjustment
;
111 /* Offsets of fixed-point and floating-point save areas from frame bottom */
112 HOST_WIDE_INT gp_sp_offset
;
113 HOST_WIDE_INT fp_sp_offset
;
115 /* Offset of virtual frame pointer from stack pointer/frame bottom */
116 HOST_WIDE_INT frame_pointer_offset
;
118 /* Offset of hard frame pointer from stack pointer/frame bottom */
119 HOST_WIDE_INT hard_frame_pointer_offset
;
121 /* The offset of arg_pointer_rtx from the bottom of the frame. */
122 HOST_WIDE_INT arg_pointer_offset
;
125 struct GTY(()) machine_function
{
126 /* The number of extra stack bytes taken up by register varargs.
127 This area is allocated by the callee at the very top of the frame. */
130 /* True if current function is a naked function. */
133 /* True if current function is an interrupt function. */
134 bool interrupt_handler_p
;
136 /* True if attributes on current function have been checked. */
137 bool attributes_checked_p
;
139 /* The current frame information, calculated by riscv_compute_frame_info. */
140 struct riscv_frame_info frame
;
143 /* Information about a single argument. */
144 struct riscv_arg_info
{
145 /* True if the argument is at least partially passed on the stack. */
148 /* The number of integer registers allocated to this argument. */
149 unsigned int num_gprs
;
151 /* The offset of the first register used, provided num_gprs is nonzero.
152 If passed entirely on the stack, the value is MAX_ARGS_IN_REGISTERS. */
153 unsigned int gpr_offset
;
155 /* The number of floating-point registers allocated to this argument. */
156 unsigned int num_fprs
;
158 /* The offset of the first register used, provided num_fprs is nonzero. */
159 unsigned int fpr_offset
;
162 /* Information about an address described by riscv_address_type.
168 REG is the base register and OFFSET is the constant offset.
171 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
172 is the type of symbol it references.
175 SYMBOL_TYPE is the type of symbol that the address references. */
176 struct riscv_address_info
{
177 enum riscv_address_type type
;
180 enum riscv_symbol_type symbol_type
;
183 /* One stage in a constant building sequence. These sequences have
187 A = A CODE[1] VALUE[1]
188 A = A CODE[2] VALUE[2]
191 where A is an accumulator, each CODE[i] is a binary rtl operation
192 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
193 struct riscv_integer_op
{
195 unsigned HOST_WIDE_INT value
;
198 /* The largest number of operations needed to load an integer constant.
199 The worst case is LUI, ADDI, SLLI, ADDI, SLLI, ADDI, SLLI, ADDI. */
200 #define RISCV_MAX_INTEGER_OPS 8
202 /* Costs of various operations on the different architectures. */
204 struct riscv_tune_info
206 unsigned short fp_add
[2];
207 unsigned short fp_mul
[2];
208 unsigned short fp_div
[2];
209 unsigned short int_mul
[2];
210 unsigned short int_div
[2];
211 unsigned short issue_rate
;
212 unsigned short branch_cost
;
213 unsigned short memory_cost
;
214 bool slow_unaligned_access
;
217 /* Information about one CPU we know about. */
218 struct riscv_cpu_info
{
219 /* This CPU's canonical name. */
222 /* Tuning parameters for this CPU. */
223 const struct riscv_tune_info
*tune_info
;
226 /* Global variables for machine-dependent things. */
228 /* Whether unaligned accesses execute very slowly. */
229 bool riscv_slow_unaligned_access_p
;
231 /* Stack alignment to assume/maintain. */
232 unsigned riscv_stack_boundary
;
234 /* Which tuning parameters to use. */
235 static const struct riscv_tune_info
*tune_info
;
237 /* Index R is the smallest register class that contains register R. */
238 const enum reg_class riscv_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
239 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
240 GR_REGS
, GR_REGS
, SIBCALL_REGS
, SIBCALL_REGS
,
241 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
242 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
243 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
244 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
245 JALR_REGS
, JALR_REGS
, JALR_REGS
, JALR_REGS
,
246 SIBCALL_REGS
, SIBCALL_REGS
, SIBCALL_REGS
, SIBCALL_REGS
,
247 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
248 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
249 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
250 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
251 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
252 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
253 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
254 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
255 FRAME_REGS
, FRAME_REGS
,
258 /* Costs to use when optimizing for rocket. */
259 static const struct riscv_tune_info rocket_tune_info
= {
260 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
261 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */
262 {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */
263 {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
264 {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
268 true, /* slow_unaligned_access */
271 /* Costs to use when optimizing for size. */
272 static const struct riscv_tune_info optimize_size_tune_info
= {
273 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_add */
274 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_mul */
275 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_div */
276 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* int_mul */
277 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* int_div */
281 false, /* slow_unaligned_access */
284 static tree
riscv_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
286 /* Defining target-specific uses of __attribute__. */
287 static const struct attribute_spec riscv_attribute_table
[] =
289 /* Syntax: { name, min_len, max_len, decl_required, type_required,
290 function_type_required, affects_type_identity, handler,
293 /* The attribute telling no prologue/epilogue. */
294 { "naked", 0, 0, true, false, false, false,
295 riscv_handle_fndecl_attribute
, NULL
},
296 /* This attribute generates prologue/epilogue for interrupt handlers. */
297 { "interrupt", 0, 0, false, true, true, false, NULL
, NULL
},
299 /* The last attribute spec is set to be NULL. */
300 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
303 /* A table describing all the processors GCC knows about. */
304 static const struct riscv_cpu_info riscv_cpu_info_table
[] = {
305 { "rocket", &rocket_tune_info
},
306 { "size", &optimize_size_tune_info
},
309 /* Return the riscv_cpu_info entry for the given name string. */
311 static const struct riscv_cpu_info
*
312 riscv_parse_cpu (const char *cpu_string
)
314 for (unsigned i
= 0; i
< ARRAY_SIZE (riscv_cpu_info_table
); i
++)
315 if (strcmp (riscv_cpu_info_table
[i
].name
, cpu_string
) == 0)
316 return riscv_cpu_info_table
+ i
;
318 error ("unknown cpu %qs for -mtune", cpu_string
);
319 return riscv_cpu_info_table
;
322 /* Helper function for riscv_build_integer; arguments are as for
323 riscv_build_integer. */
326 riscv_build_integer_1 (struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
],
327 HOST_WIDE_INT value
, machine_mode mode
)
329 HOST_WIDE_INT low_part
= CONST_LOW_PART (value
);
330 int cost
= RISCV_MAX_INTEGER_OPS
+ 1, alt_cost
;
331 struct riscv_integer_op alt_codes
[RISCV_MAX_INTEGER_OPS
];
333 if (SMALL_OPERAND (value
) || LUI_OPERAND (value
))
335 /* Simply ADDI or LUI. */
336 codes
[0].code
= UNKNOWN
;
337 codes
[0].value
= value
;
341 /* End with ADDI. When constructing HImode constants, do not generate any
342 intermediate value that is not itself a valid HImode constant. The
343 XORI case below will handle those remaining HImode constants. */
346 || value
- low_part
<= ((1 << (GET_MODE_BITSIZE (HImode
) - 1)) - 1)))
348 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, value
- low_part
, mode
);
351 alt_codes
[alt_cost
-1].code
= PLUS
;
352 alt_codes
[alt_cost
-1].value
= low_part
;
353 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
359 if (cost
> 2 && (low_part
< 0 || mode
== HImode
))
361 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, value
^ low_part
, mode
);
364 alt_codes
[alt_cost
-1].code
= XOR
;
365 alt_codes
[alt_cost
-1].value
= low_part
;
366 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
371 /* Eliminate trailing zeros and end with SLLI. */
372 if (cost
> 2 && (value
& 1) == 0)
374 int shift
= ctz_hwi (value
);
375 unsigned HOST_WIDE_INT x
= value
;
376 x
= sext_hwi (x
>> shift
, HOST_BITS_PER_WIDE_INT
- shift
);
378 /* Don't eliminate the lower 12 bits if LUI might apply. */
379 if (shift
> IMM_BITS
&& !SMALL_OPERAND (x
) && LUI_OPERAND (x
<< IMM_BITS
))
380 shift
-= IMM_BITS
, x
<<= IMM_BITS
;
382 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, x
, mode
);
385 alt_codes
[alt_cost
-1].code
= ASHIFT
;
386 alt_codes
[alt_cost
-1].value
= shift
;
387 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
392 gcc_assert (cost
<= RISCV_MAX_INTEGER_OPS
);
396 /* Fill CODES with a sequence of rtl operations to load VALUE.
397 Return the number of operations needed. */
400 riscv_build_integer (struct riscv_integer_op
*codes
, HOST_WIDE_INT value
,
403 int cost
= riscv_build_integer_1 (codes
, value
, mode
);
405 /* Eliminate leading zeros and end with SRLI. */
406 if (value
> 0 && cost
> 2)
408 struct riscv_integer_op alt_codes
[RISCV_MAX_INTEGER_OPS
];
409 int alt_cost
, shift
= clz_hwi (value
);
410 HOST_WIDE_INT shifted_val
;
412 /* Try filling trailing bits with 1s. */
413 shifted_val
= (value
<< shift
) | ((((HOST_WIDE_INT
) 1) << shift
) - 1);
414 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, shifted_val
, mode
);
417 alt_codes
[alt_cost
-1].code
= LSHIFTRT
;
418 alt_codes
[alt_cost
-1].value
= shift
;
419 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
423 /* Try filling trailing bits with 0s. */
424 shifted_val
= value
<< shift
;
425 alt_cost
= 1 + riscv_build_integer_1 (alt_codes
, shifted_val
, mode
);
428 alt_codes
[alt_cost
-1].code
= LSHIFTRT
;
429 alt_codes
[alt_cost
-1].value
= shift
;
430 memcpy (codes
, alt_codes
, sizeof (alt_codes
));
438 /* Return the cost of constructing VAL in the event that a scratch
439 register is available. */
442 riscv_split_integer_cost (HOST_WIDE_INT val
)
445 unsigned HOST_WIDE_INT loval
= sext_hwi (val
, 32);
446 unsigned HOST_WIDE_INT hival
= sext_hwi ((val
- loval
) >> 32, 32);
447 struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
];
449 cost
= 2 + riscv_build_integer (codes
, loval
, VOIDmode
);
451 cost
+= riscv_build_integer (codes
, hival
, VOIDmode
);
456 /* Return the cost of constructing the integer constant VAL. */
459 riscv_integer_cost (HOST_WIDE_INT val
)
461 struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
];
462 return MIN (riscv_build_integer (codes
, val
, VOIDmode
),
463 riscv_split_integer_cost (val
));
466 /* Try to split a 64b integer into 32b parts, then reassemble. */
469 riscv_split_integer (HOST_WIDE_INT val
, machine_mode mode
)
471 unsigned HOST_WIDE_INT loval
= sext_hwi (val
, 32);
472 unsigned HOST_WIDE_INT hival
= sext_hwi ((val
- loval
) >> 32, 32);
473 rtx hi
= gen_reg_rtx (mode
), lo
= gen_reg_rtx (mode
);
475 riscv_move_integer (hi
, hi
, hival
);
476 riscv_move_integer (lo
, lo
, loval
);
478 hi
= gen_rtx_fmt_ee (ASHIFT
, mode
, hi
, GEN_INT (32));
479 hi
= force_reg (mode
, hi
);
481 return gen_rtx_fmt_ee (PLUS
, mode
, hi
, lo
);
484 /* Return true if X is a thread-local symbol. */
487 riscv_tls_symbol_p (const_rtx x
)
489 return SYMBOL_REF_P (x
) && SYMBOL_REF_TLS_MODEL (x
) != 0;
492 /* Return true if symbol X binds locally. */
495 riscv_symbol_binds_local_p (const_rtx x
)
497 if (SYMBOL_REF_P (x
))
498 return (SYMBOL_REF_DECL (x
)
499 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
500 : SYMBOL_REF_LOCAL_P (x
));
505 /* Return the method that should be used to access SYMBOL_REF or
508 static enum riscv_symbol_type
509 riscv_classify_symbol (const_rtx x
)
511 if (riscv_tls_symbol_p (x
))
514 if (GET_CODE (x
) == SYMBOL_REF
&& flag_pic
&& !riscv_symbol_binds_local_p (x
))
515 return SYMBOL_GOT_DISP
;
517 return riscv_cmodel
== CM_MEDLOW
? SYMBOL_ABSOLUTE
: SYMBOL_PCREL
;
520 /* Classify the base of symbolic expression X. */
522 enum riscv_symbol_type
523 riscv_classify_symbolic_expression (rtx x
)
527 split_const (x
, &x
, &offset
);
528 if (UNSPEC_ADDRESS_P (x
))
529 return UNSPEC_ADDRESS_TYPE (x
);
531 return riscv_classify_symbol (x
);
534 /* Return true if X is a symbolic constant. If it is, store the type of
535 the symbol in *SYMBOL_TYPE. */
538 riscv_symbolic_constant_p (rtx x
, enum riscv_symbol_type
*symbol_type
)
542 split_const (x
, &x
, &offset
);
543 if (UNSPEC_ADDRESS_P (x
))
545 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
546 x
= UNSPEC_ADDRESS (x
);
548 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
549 *symbol_type
= riscv_classify_symbol (x
);
553 if (offset
== const0_rtx
)
556 /* Nonzero offsets are only valid for references that don't use the GOT. */
557 switch (*symbol_type
)
559 case SYMBOL_ABSOLUTE
:
562 /* GAS rejects offsets outside the range [-2^31, 2^31-1]. */
563 return sext_hwi (INTVAL (offset
), 32) == INTVAL (offset
);
570 /* Returns the number of instructions necessary to reference a symbol. */
572 static int riscv_symbol_insns (enum riscv_symbol_type type
)
576 case SYMBOL_TLS
: return 0; /* Depends on the TLS model. */
577 case SYMBOL_ABSOLUTE
: return 2; /* LUI + the reference. */
578 case SYMBOL_PCREL
: return 2; /* AUIPC + the reference. */
579 case SYMBOL_TLS_LE
: return 3; /* LUI + ADD TP + the reference. */
580 case SYMBOL_GOT_DISP
: return 3; /* AUIPC + LD GOT + the reference. */
581 default: gcc_unreachable ();
585 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
588 riscv_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
590 return riscv_const_insns (x
) > 0;
593 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
596 riscv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
598 enum riscv_symbol_type type
;
601 /* There is no assembler syntax for expressing an address-sized
603 if (GET_CODE (x
) == HIGH
)
606 split_const (x
, &base
, &offset
);
607 if (riscv_symbolic_constant_p (base
, &type
))
609 /* As an optimization, don't spill symbolic constants that are as
610 cheap to rematerialize as to access in the constant pool. */
611 if (SMALL_OPERAND (INTVAL (offset
)) && riscv_symbol_insns (type
) > 0)
614 /* As an optimization, avoid needlessly generate dynamic relocations. */
619 /* TLS symbols must be computed by riscv_legitimize_move. */
620 if (tls_referenced_p (x
))
626 /* Return true if register REGNO is a valid base register for mode MODE.
627 STRICT_P is true if REG_OK_STRICT is in effect. */
630 riscv_regno_mode_ok_for_base_p (int regno
,
631 machine_mode mode ATTRIBUTE_UNUSED
,
634 if (!HARD_REGISTER_NUM_P (regno
))
638 regno
= reg_renumber
[regno
];
641 /* These fake registers will be eliminated to either the stack or
642 hard frame pointer, both of which are usually valid base registers.
643 Reload deals with the cases where the eliminated form isn't valid. */
644 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
647 return GP_REG_P (regno
);
650 /* Return true if X is a valid base register for mode MODE.
651 STRICT_P is true if REG_OK_STRICT is in effect. */
654 riscv_valid_base_register_p (rtx x
, machine_mode mode
, bool strict_p
)
656 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
660 && riscv_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
663 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
664 can address a value of mode MODE. */
667 riscv_valid_offset_p (rtx x
, machine_mode mode
)
669 /* Check that X is a signed 12-bit number. */
670 if (!const_arith_operand (x
, Pmode
))
673 /* We may need to split multiword moves, so make sure that every word
675 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
676 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
682 /* Should a symbol of type SYMBOL_TYPE should be split in two? */
685 riscv_split_symbol_type (enum riscv_symbol_type symbol_type
)
687 if (symbol_type
== SYMBOL_TLS_LE
)
690 if (!TARGET_EXPLICIT_RELOCS
)
693 return symbol_type
== SYMBOL_ABSOLUTE
|| symbol_type
== SYMBOL_PCREL
;
696 /* Return true if a LO_SUM can address a value of mode MODE when the
697 LO_SUM symbol has type SYM_TYPE. */
700 riscv_valid_lo_sum_p (enum riscv_symbol_type sym_type
, machine_mode mode
)
702 /* Check that symbols of type SYMBOL_TYPE can be used to access values
704 if (riscv_symbol_insns (sym_type
) == 0)
707 /* Check that there is a known low-part relocation. */
708 if (!riscv_split_symbol_type (sym_type
))
711 /* We may need to split multiword moves, so make sure that each word
712 can be accessed without inducing a carry. */
713 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
714 && (!TARGET_STRICT_ALIGN
715 || GET_MODE_BITSIZE (mode
) > GET_MODE_ALIGNMENT (mode
)))
721 /* Return true if X is a valid address for machine mode MODE. If it is,
722 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
726 riscv_classify_address (struct riscv_address_info
*info
, rtx x
,
727 machine_mode mode
, bool strict_p
)
729 switch (GET_CODE (x
))
733 info
->type
= ADDRESS_REG
;
735 info
->offset
= const0_rtx
;
736 return riscv_valid_base_register_p (info
->reg
, mode
, strict_p
);
739 info
->type
= ADDRESS_REG
;
740 info
->reg
= XEXP (x
, 0);
741 info
->offset
= XEXP (x
, 1);
742 return (riscv_valid_base_register_p (info
->reg
, mode
, strict_p
)
743 && riscv_valid_offset_p (info
->offset
, mode
));
746 info
->type
= ADDRESS_LO_SUM
;
747 info
->reg
= XEXP (x
, 0);
748 info
->offset
= XEXP (x
, 1);
749 /* We have to trust the creator of the LO_SUM to do something vaguely
750 sane. Target-independent code that creates a LO_SUM should also
751 create and verify the matching HIGH. Target-independent code that
752 adds an offset to a LO_SUM must prove that the offset will not
753 induce a carry. Failure to do either of these things would be
754 a bug, and we are not required to check for it here. The RISC-V
755 backend itself should only create LO_SUMs for valid symbolic
756 constants, with the high part being either a HIGH or a copy
759 = riscv_classify_symbolic_expression (info
->offset
);
760 return (riscv_valid_base_register_p (info
->reg
, mode
, strict_p
)
761 && riscv_valid_lo_sum_p (info
->symbol_type
, mode
));
764 /* Small-integer addresses don't occur very often, but they
765 are legitimate if x0 is a valid base register. */
766 info
->type
= ADDRESS_CONST_INT
;
767 return SMALL_OPERAND (INTVAL (x
));
774 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
777 riscv_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
779 struct riscv_address_info addr
;
781 return riscv_classify_address (&addr
, x
, mode
, strict_p
);
784 /* Return the number of instructions needed to load or store a value
785 of mode MODE at address X. Return 0 if X isn't valid for MODE.
786 Assume that multiword moves may need to be split into word moves
787 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
791 riscv_address_insns (rtx x
, machine_mode mode
, bool might_split_p
)
793 struct riscv_address_info addr
;
796 if (!riscv_classify_address (&addr
, x
, mode
, false))
799 /* BLKmode is used for single unaligned loads and stores and should
800 not count as a multiword mode. */
801 if (mode
!= BLKmode
&& might_split_p
)
802 n
+= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
804 if (addr
.type
== ADDRESS_LO_SUM
)
805 n
+= riscv_symbol_insns (addr
.symbol_type
) - 1;
810 /* Return the number of instructions needed to load constant X.
811 Return 0 if X isn't a valid constant. */
814 riscv_const_insns (rtx x
)
816 enum riscv_symbol_type symbol_type
;
819 switch (GET_CODE (x
))
822 if (!riscv_symbolic_constant_p (XEXP (x
, 0), &symbol_type
)
823 || !riscv_split_symbol_type (symbol_type
))
826 /* This is simply an LUI. */
831 int cost
= riscv_integer_cost (INTVAL (x
));
832 /* Force complicated constants to memory. */
833 return cost
< 4 ? cost
: 0;
838 /* We can use x0 to load floating-point zero. */
839 return x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
842 /* See if we can refer to X directly. */
843 if (riscv_symbolic_constant_p (x
, &symbol_type
))
844 return riscv_symbol_insns (symbol_type
);
846 /* Otherwise try splitting the constant into a base and offset. */
847 split_const (x
, &x
, &offset
);
850 int n
= riscv_const_insns (x
);
852 return n
+ riscv_integer_cost (INTVAL (offset
));
858 return riscv_symbol_insns (riscv_classify_symbol (x
));
865 /* X is a doubleword constant that can be handled by splitting it into
866 two words and loading each word separately. Return the number of
867 instructions required to do this. */
870 riscv_split_const_insns (rtx x
)
872 unsigned int low
, high
;
874 low
= riscv_const_insns (riscv_subword (x
, false));
875 high
= riscv_const_insns (riscv_subword (x
, true));
876 gcc_assert (low
> 0 && high
> 0);
880 /* Return the number of instructions needed to implement INSN,
881 given that it loads from or stores to MEM. */
884 riscv_load_store_insns (rtx mem
, rtx_insn
*insn
)
890 gcc_assert (MEM_P (mem
));
891 mode
= GET_MODE (mem
);
893 /* Try to prove that INSN does not need to be split. */
894 might_split_p
= true;
895 if (GET_MODE_BITSIZE (mode
) <= 32)
896 might_split_p
= false;
897 else if (GET_MODE_BITSIZE (mode
) == 64)
899 set
= single_set (insn
);
900 if (set
&& !riscv_split_64bit_move_p (SET_DEST (set
), SET_SRC (set
)))
901 might_split_p
= false;
904 return riscv_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
907 /* Emit a move from SRC to DEST. Assume that the move expanders can
908 handle all moves if !can_create_pseudo_p (). The distinction is
909 important because, unlike emit_move_insn, the move expanders know
910 how to force Pmode objects into the constant pool even when the
911 constant pool address is not itself legitimate. */
914 riscv_emit_move (rtx dest
, rtx src
)
916 return (can_create_pseudo_p ()
917 ? emit_move_insn (dest
, src
)
918 : emit_move_insn_1 (dest
, src
));
921 /* Emit an instruction of the form (set TARGET SRC). */
924 riscv_emit_set (rtx target
, rtx src
)
926 emit_insn (gen_rtx_SET (target
, src
));
930 /* Emit an instruction of the form (set DEST (CODE X Y)). */
933 riscv_emit_binary (enum rtx_code code
, rtx dest
, rtx x
, rtx y
)
935 return riscv_emit_set (dest
, gen_rtx_fmt_ee (code
, GET_MODE (dest
), x
, y
));
938 /* Compute (CODE X Y) and store the result in a new register
939 of mode MODE. Return that new register. */
942 riscv_force_binary (machine_mode mode
, enum rtx_code code
, rtx x
, rtx y
)
944 return riscv_emit_binary (code
, gen_reg_rtx (mode
), x
, y
);
947 /* Copy VALUE to a register and return that register. If new pseudos
948 are allowed, copy it into a new register, otherwise use DEST. */
951 riscv_force_temporary (rtx dest
, rtx value
)
953 if (can_create_pseudo_p ())
954 return force_reg (Pmode
, value
);
957 riscv_emit_move (dest
, value
);
962 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
963 then add CONST_INT OFFSET to the result. */
966 riscv_unspec_address_offset (rtx base
, rtx offset
,
967 enum riscv_symbol_type symbol_type
)
969 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
970 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
971 if (offset
!= const0_rtx
)
972 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
973 return gen_rtx_CONST (Pmode
, base
);
976 /* Return an UNSPEC address with underlying address ADDRESS and symbol
980 riscv_unspec_address (rtx address
, enum riscv_symbol_type symbol_type
)
984 split_const (address
, &base
, &offset
);
985 return riscv_unspec_address_offset (base
, offset
, symbol_type
);
988 /* If OP is an UNSPEC address, return the address to which it refers,
989 otherwise return OP itself. */
992 riscv_strip_unspec_address (rtx op
)
996 split_const (op
, &base
, &offset
);
997 if (UNSPEC_ADDRESS_P (base
))
998 op
= plus_constant (Pmode
, UNSPEC_ADDRESS (base
), INTVAL (offset
));
1002 /* If riscv_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1003 high part to BASE and return the result. Just return BASE otherwise.
1004 TEMP is as for riscv_force_temporary.
1006 The returned expression can be used as the first operand to a LO_SUM. */
1009 riscv_unspec_offset_high (rtx temp
, rtx addr
, enum riscv_symbol_type symbol_type
)
1011 addr
= gen_rtx_HIGH (Pmode
, riscv_unspec_address (addr
, symbol_type
));
1012 return riscv_force_temporary (temp
, addr
);
1015 /* Load an entry from the GOT for a TLS GD access. */
1017 static rtx
riscv_got_load_tls_gd (rtx dest
, rtx sym
)
1019 if (Pmode
== DImode
)
1020 return gen_got_load_tls_gddi (dest
, sym
);
1022 return gen_got_load_tls_gdsi (dest
, sym
);
1025 /* Load an entry from the GOT for a TLS IE access. */
1027 static rtx
riscv_got_load_tls_ie (rtx dest
, rtx sym
)
1029 if (Pmode
== DImode
)
1030 return gen_got_load_tls_iedi (dest
, sym
);
1032 return gen_got_load_tls_iesi (dest
, sym
);
1035 /* Add in the thread pointer for a TLS LE access. */
1037 static rtx
riscv_tls_add_tp_le (rtx dest
, rtx base
, rtx sym
)
1039 rtx tp
= gen_rtx_REG (Pmode
, THREAD_POINTER_REGNUM
);
1040 if (Pmode
== DImode
)
1041 return gen_tls_add_tp_ledi (dest
, base
, tp
, sym
);
1043 return gen_tls_add_tp_lesi (dest
, base
, tp
, sym
);
1046 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
1047 it appears in a MEM of that mode. Return true if ADDR is a legitimate
1048 constant in that context and can be split into high and low parts.
1049 If so, and if LOW_OUT is nonnull, emit the high part and store the
1050 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
1052 TEMP is as for riscv_force_temporary and is used to load the high
1053 part into a register.
1055 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
1056 a legitimize SET_SRC for an .md pattern, otherwise the low part
1057 is guaranteed to be a legitimate address for mode MODE. */
1060 riscv_split_symbol (rtx temp
, rtx addr
, machine_mode mode
, rtx
*low_out
)
1062 enum riscv_symbol_type symbol_type
;
1064 if ((GET_CODE (addr
) == HIGH
&& mode
== MAX_MACHINE_MODE
)
1065 || !riscv_symbolic_constant_p (addr
, &symbol_type
)
1066 || riscv_symbol_insns (symbol_type
) == 0
1067 || !riscv_split_symbol_type (symbol_type
))
1071 switch (symbol_type
)
1073 case SYMBOL_ABSOLUTE
:
1075 rtx high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
1076 high
= riscv_force_temporary (temp
, high
);
1077 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
1083 static unsigned seqno
;
1087 ssize_t bytes
= snprintf (buf
, sizeof (buf
), ".LA%u", seqno
);
1088 gcc_assert ((size_t) bytes
< sizeof (buf
));
1090 label
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
1091 SYMBOL_REF_FLAGS (label
) |= SYMBOL_FLAG_LOCAL
;
1094 temp
= gen_reg_rtx (Pmode
);
1096 if (Pmode
== DImode
)
1097 emit_insn (gen_auipcdi (temp
, copy_rtx (addr
), GEN_INT (seqno
)));
1099 emit_insn (gen_auipcsi (temp
, copy_rtx (addr
), GEN_INT (seqno
)));
1101 *low_out
= gen_rtx_LO_SUM (Pmode
, temp
, label
);
1114 /* Return a legitimate address for REG + OFFSET. TEMP is as for
1115 riscv_force_temporary; it is only needed when OFFSET is not a
1119 riscv_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
1121 if (!SMALL_OPERAND (offset
))
1125 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
1126 The addition inside the macro CONST_HIGH_PART may cause an
1127 overflow, so we need to force a sign-extension check. */
1128 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
1129 offset
= CONST_LOW_PART (offset
);
1130 high
= riscv_force_temporary (temp
, high
);
1131 reg
= riscv_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
1133 return plus_constant (Pmode
, reg
, offset
);
1136 /* The __tls_get_attr symbol. */
1137 static GTY(()) rtx riscv_tls_symbol
;
1139 /* Return an instruction sequence that calls __tls_get_addr. SYM is
1140 the TLS symbol we are referencing and TYPE is the symbol type to use
1141 (either global dynamic or local dynamic). RESULT is an RTX for the
1142 return value location. */
1145 riscv_call_tls_get_addr (rtx sym
, rtx result
)
1147 rtx a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
), func
;
1150 if (!riscv_tls_symbol
)
1151 riscv_tls_symbol
= init_one_libfunc ("__tls_get_addr");
1152 func
= gen_rtx_MEM (FUNCTION_MODE
, riscv_tls_symbol
);
1156 emit_insn (riscv_got_load_tls_gd (a0
, sym
));
1157 insn
= emit_call_insn (gen_call_value (result
, func
, const0_rtx
, NULL
));
1158 RTL_CONST_CALL_P (insn
) = 1;
1159 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
1160 insn
= get_insns ();
1167 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
1168 its address. The return value will be both a valid address and a valid
1169 SET_SRC (either a REG or a LO_SUM). */
1172 riscv_legitimize_tls_address (rtx loc
)
1175 enum tls_model model
= SYMBOL_REF_TLS_MODEL (loc
);
1177 /* Since we support TLS copy relocs, non-PIC TLS accesses may all use LE. */
1179 model
= TLS_MODEL_LOCAL_EXEC
;
1183 case TLS_MODEL_LOCAL_DYNAMIC
:
1184 /* Rely on section anchors for the optimization that LDM TLS
1185 provides. The anchor's address is loaded with GD TLS. */
1186 case TLS_MODEL_GLOBAL_DYNAMIC
:
1187 tmp
= gen_rtx_REG (Pmode
, GP_RETURN
);
1188 dest
= gen_reg_rtx (Pmode
);
1189 emit_libcall_block (riscv_call_tls_get_addr (loc
, tmp
), dest
, tmp
, loc
);
1192 case TLS_MODEL_INITIAL_EXEC
:
1193 /* la.tls.ie; tp-relative add */
1194 tp
= gen_rtx_REG (Pmode
, THREAD_POINTER_REGNUM
);
1195 tmp
= gen_reg_rtx (Pmode
);
1196 emit_insn (riscv_got_load_tls_ie (tmp
, loc
));
1197 dest
= gen_reg_rtx (Pmode
);
1198 emit_insn (gen_add3_insn (dest
, tmp
, tp
));
1201 case TLS_MODEL_LOCAL_EXEC
:
1202 tmp
= riscv_unspec_offset_high (NULL
, loc
, SYMBOL_TLS_LE
);
1203 dest
= gen_reg_rtx (Pmode
);
1204 emit_insn (riscv_tls_add_tp_le (dest
, tmp
, loc
));
1205 dest
= gen_rtx_LO_SUM (Pmode
, dest
,
1206 riscv_unspec_address (loc
, SYMBOL_TLS_LE
));
1215 /* If X is not a valid address for mode MODE, force it into a register. */
1218 riscv_force_address (rtx x
, machine_mode mode
)
1220 if (!riscv_legitimate_address_p (mode
, x
, false))
1221 x
= force_reg (Pmode
, x
);
1225 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
1226 be legitimized in a way that the generic machinery might not expect,
1227 return a new address, otherwise return NULL. MODE is the mode of
1228 the memory being accessed. */
1231 riscv_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1236 if (riscv_tls_symbol_p (x
))
1237 return riscv_legitimize_tls_address (x
);
1239 /* See if the address can split into a high part and a LO_SUM. */
1240 if (riscv_split_symbol (NULL
, x
, mode
, &addr
))
1241 return riscv_force_address (addr
, mode
);
1243 /* Handle BASE + OFFSET using riscv_add_offset. */
1244 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1))
1245 && INTVAL (XEXP (x
, 1)) != 0)
1247 rtx base
= XEXP (x
, 0);
1248 HOST_WIDE_INT offset
= INTVAL (XEXP (x
, 1));
1250 if (!riscv_valid_base_register_p (base
, mode
, false))
1251 base
= copy_to_mode_reg (Pmode
, base
);
1252 addr
= riscv_add_offset (NULL
, base
, offset
);
1253 return riscv_force_address (addr
, mode
);
1259 /* Load VALUE into DEST. TEMP is as for riscv_force_temporary. */
1262 riscv_move_integer (rtx temp
, rtx dest
, HOST_WIDE_INT value
)
1264 struct riscv_integer_op codes
[RISCV_MAX_INTEGER_OPS
];
1269 mode
= GET_MODE (dest
);
1270 num_ops
= riscv_build_integer (codes
, value
, mode
);
1272 if (can_create_pseudo_p () && num_ops
> 2 /* not a simple constant */
1273 && num_ops
>= riscv_split_integer_cost (value
))
1274 x
= riscv_split_integer (value
, mode
);
1277 /* Apply each binary operation to X. */
1278 x
= GEN_INT (codes
[0].value
);
1280 for (i
= 1; i
< num_ops
; i
++)
1282 if (!can_create_pseudo_p ())
1283 x
= riscv_emit_set (temp
, x
);
1285 x
= force_reg (mode
, x
);
1287 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
1291 riscv_emit_set (dest
, x
);
1294 /* Subroutine of riscv_legitimize_move. Move constant SRC into register
1295 DEST given that SRC satisfies immediate_operand but doesn't satisfy
1299 riscv_legitimize_const_move (machine_mode mode
, rtx dest
, rtx src
)
1303 /* Split moves of big integers into smaller pieces. */
1304 if (splittable_const_int_operand (src
, mode
))
1306 riscv_move_integer (dest
, dest
, INTVAL (src
));
1310 /* Split moves of symbolic constants into high/low pairs. */
1311 if (riscv_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
1313 riscv_emit_set (dest
, src
);
1317 /* Generate the appropriate access sequences for TLS symbols. */
1318 if (riscv_tls_symbol_p (src
))
1320 riscv_emit_move (dest
, riscv_legitimize_tls_address (src
));
1324 /* If we have (const (plus symbol offset)), and that expression cannot
1325 be forced into memory, load the symbol first and add in the offset. Also
1326 prefer to do this even if the constant _can_ be forced into memory, as it
1327 usually produces better code. */
1328 split_const (src
, &base
, &offset
);
1329 if (offset
!= const0_rtx
1330 && (targetm
.cannot_force_const_mem (mode
, src
) || can_create_pseudo_p ()))
1332 base
= riscv_force_temporary (dest
, base
);
1333 riscv_emit_move (dest
, riscv_add_offset (NULL
, base
, INTVAL (offset
)));
1337 src
= force_const_mem (mode
, src
);
1339 /* When using explicit relocs, constant pool references are sometimes
1340 not legitimate addresses. */
1341 riscv_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
1342 riscv_emit_move (dest
, src
);
1345 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
1346 sequence that is valid. */
1349 riscv_legitimize_move (machine_mode mode
, rtx dest
, rtx src
)
1351 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
1353 riscv_emit_move (dest
, force_reg (mode
, src
));
1357 /* We need to deal with constants that would be legitimate
1358 immediate_operands but aren't legitimate move_operands. */
1359 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
1361 riscv_legitimize_const_move (mode
, dest
, src
);
1362 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
1366 /* RISC-V GCC may generate non-legitimate address due to we provide some
1367 pattern for optimize access PIC local symbol and it's make GCC generate
1368 unrecognizable instruction during optmizing. */
1370 if (MEM_P (dest
) && !riscv_legitimate_address_p (mode
, XEXP (dest
, 0),
1373 XEXP (dest
, 0) = riscv_force_address (XEXP (dest
, 0), mode
);
1376 if (MEM_P (src
) && !riscv_legitimate_address_p (mode
, XEXP (src
, 0),
1379 XEXP (src
, 0) = riscv_force_address (XEXP (src
, 0), mode
);
1385 /* Return true if there is an instruction that implements CODE and accepts
1386 X as an immediate operand. */
1389 riscv_immediate_operand_p (int code
, HOST_WIDE_INT x
)
1396 /* All shift counts are truncated to a valid constant. */
1405 /* These instructions take 12-bit signed immediates. */
1406 return SMALL_OPERAND (x
);
1409 /* We add 1 to the immediate and use SLT. */
1410 return SMALL_OPERAND (x
+ 1);
1413 /* Likewise SLTU, but reject the always-true case. */
1414 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
1418 /* We can emulate an immediate of 1 by using GT/GTU against x0. */
1422 /* By default assume that x0 can be used for 0. */
1427 /* Return the cost of binary operation X, given that the instruction
1428 sequence for a word-sized or smaller operation takes SIGNLE_INSNS
1429 instructions and that the sequence of a double-word operation takes
1430 DOUBLE_INSNS instructions. */
1433 riscv_binary_cost (rtx x
, int single_insns
, int double_insns
)
1435 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
1436 return COSTS_N_INSNS (double_insns
);
1437 return COSTS_N_INSNS (single_insns
);
1440 /* Return the cost of sign- or zero-extending OP. */
1443 riscv_extend_cost (rtx op
, bool unsigned_p
)
1448 if (unsigned_p
&& GET_MODE (op
) == QImode
)
1449 /* We can use ANDI. */
1450 return COSTS_N_INSNS (1);
1452 if (!unsigned_p
&& GET_MODE (op
) == SImode
)
1453 /* We can use SEXT.W. */
1454 return COSTS_N_INSNS (1);
1456 /* We need to use a shift left and a shift right. */
1457 return COSTS_N_INSNS (2);
1460 /* Implement TARGET_RTX_COSTS. */
1462 #define SINGLE_SHIFT_COST 1
1465 riscv_rtx_costs (rtx x
, machine_mode mode
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
1466 int *total
, bool speed
)
1468 bool float_mode_p
= FLOAT_MODE_P (mode
);
1471 switch (GET_CODE (x
))
1474 if (riscv_immediate_operand_p (outer_code
, INTVAL (x
)))
1485 if ((cost
= riscv_const_insns (x
)) > 0)
1487 /* If the constant is likely to be stored in a GPR, SETs of
1488 single-insn constants are as cheap as register sets; we
1489 never want to CSE them. */
1490 if (cost
== 1 && outer_code
== SET
)
1492 /* When we load a constant more than once, it usually is better
1493 to duplicate the last operation in the sequence than to CSE
1494 the constant itself. */
1495 else if (outer_code
== SET
|| GET_MODE (x
) == VOIDmode
)
1496 *total
= COSTS_N_INSNS (1);
1498 else /* The instruction will be fetched from the constant pool. */
1499 *total
= COSTS_N_INSNS (riscv_symbol_insns (SYMBOL_ABSOLUTE
));
1503 /* If the address is legitimate, return the number of
1504 instructions it needs. */
1505 if ((cost
= riscv_address_insns (XEXP (x
, 0), mode
, true)) > 0)
1507 *total
= COSTS_N_INSNS (cost
+ tune_info
->memory_cost
);
1510 /* Otherwise use the default handling. */
1514 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
1520 /* Double-word operations use two single-word operations. */
1521 *total
= riscv_binary_cost (x
, 1, 2);
1525 /* This is an SImode shift. */
1526 if (outer_code
== SET
&& (INTVAL (XEXP (x
, 2)) > 0)
1527 && (INTVAL (XEXP (x
, 1)) + INTVAL (XEXP (x
, 2)) == 32))
1529 *total
= COSTS_N_INSNS (SINGLE_SHIFT_COST
);
1537 *total
= riscv_binary_cost (x
, SINGLE_SHIFT_COST
,
1538 CONSTANT_P (XEXP (x
, 1)) ? 4 : 9);
1542 *total
= COSTS_N_INSNS (float_mode_p
? 1 : 3);
1546 *total
= set_src_cost (XEXP (x
, 0), mode
, speed
);
1550 /* This is an SImode shift. */
1551 if (outer_code
== SET
&& GET_MODE (x
) == DImode
1552 && GET_MODE (XEXP (x
, 0)) == SImode
)
1554 *total
= COSTS_N_INSNS (SINGLE_SHIFT_COST
);
1567 /* Branch comparisons have VOIDmode, so use the first operand's
1569 mode
= GET_MODE (XEXP (x
, 0));
1571 *total
= tune_info
->fp_add
[mode
== DFmode
];
1573 *total
= riscv_binary_cost (x
, 1, 3);
1578 /* (FEQ(A, A) & FEQ(B, B)) compared against 0. */
1579 mode
= GET_MODE (XEXP (x
, 0));
1580 *total
= tune_info
->fp_add
[mode
== DFmode
] + COSTS_N_INSNS (2);
1585 /* (FEQ(A, A) & FEQ(B, B)) compared against FEQ(A, B). */
1586 mode
= GET_MODE (XEXP (x
, 0));
1587 *total
= tune_info
->fp_add
[mode
== DFmode
] + COSTS_N_INSNS (3);
1594 /* FLT or FLE, but guarded by an FFLAGS read and write. */
1595 mode
= GET_MODE (XEXP (x
, 0));
1596 *total
= tune_info
->fp_add
[mode
== DFmode
] + COSTS_N_INSNS (4);
1602 *total
= tune_info
->fp_add
[mode
== DFmode
];
1604 *total
= riscv_binary_cost (x
, 1, 4);
1609 rtx op
= XEXP (x
, 0);
1610 if (GET_CODE (op
) == FMA
&& !HONOR_SIGNED_ZEROS (mode
))
1612 *total
= (tune_info
->fp_mul
[mode
== DFmode
]
1613 + set_src_cost (XEXP (op
, 0), mode
, speed
)
1614 + set_src_cost (XEXP (op
, 1), mode
, speed
)
1615 + set_src_cost (XEXP (op
, 2), mode
, speed
));
1621 *total
= tune_info
->fp_add
[mode
== DFmode
];
1623 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
1628 *total
= tune_info
->fp_mul
[mode
== DFmode
];
1629 else if (!TARGET_MUL
)
1630 /* Estimate the cost of a library call. */
1631 *total
= COSTS_N_INSNS (speed
? 32 : 6);
1632 else if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
1633 *total
= 3 * tune_info
->int_mul
[0] + COSTS_N_INSNS (2);
1635 *total
= COSTS_N_INSNS (1);
1637 *total
= tune_info
->int_mul
[mode
== DImode
];
1645 *total
= tune_info
->fp_div
[mode
== DFmode
];
1653 /* Estimate the cost of a library call. */
1654 *total
= COSTS_N_INSNS (speed
? 32 : 6);
1656 *total
= tune_info
->int_div
[mode
== DImode
];
1658 *total
= COSTS_N_INSNS (1);
1662 /* This is an SImode shift. */
1663 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
)
1665 *total
= COSTS_N_INSNS (SINGLE_SHIFT_COST
);
1670 *total
= riscv_extend_cost (XEXP (x
, 0), GET_CODE (x
) == ZERO_EXTEND
);
1674 case UNSIGNED_FLOAT
:
1677 case FLOAT_TRUNCATE
:
1678 *total
= tune_info
->fp_add
[mode
== DFmode
];
1682 *total
= (tune_info
->fp_mul
[mode
== DFmode
]
1683 + set_src_cost (XEXP (x
, 0), mode
, speed
)
1684 + set_src_cost (XEXP (x
, 1), mode
, speed
)
1685 + set_src_cost (XEXP (x
, 2), mode
, speed
));
1689 if (XINT (x
, 1) == UNSPEC_AUIPC
)
1691 /* Make AUIPC cheap to avoid spilling its result to the stack. */
1702 /* Implement TARGET_ADDRESS_COST. */
1705 riscv_address_cost (rtx addr
, machine_mode mode
,
1706 addr_space_t as ATTRIBUTE_UNUSED
,
1707 bool speed ATTRIBUTE_UNUSED
)
1709 return riscv_address_insns (addr
, mode
, false);
1712 /* Return one word of double-word value OP. HIGH_P is true to select the
1713 high part or false to select the low part. */
1716 riscv_subword (rtx op
, bool high_p
)
1718 unsigned int byte
= high_p
? UNITS_PER_WORD
: 0;
1719 machine_mode mode
= GET_MODE (op
);
1721 if (mode
== VOIDmode
)
1722 mode
= TARGET_64BIT
? TImode
: DImode
;
1725 return adjust_address (op
, word_mode
, byte
);
1728 gcc_assert (!FP_REG_RTX_P (op
));
1730 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
1733 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
1736 riscv_split_64bit_move_p (rtx dest
, rtx src
)
1741 /* Allow FPR <-> FPR and FPR <-> MEM moves, and permit the special case
1742 of zeroing an FPR with FCVT.D.W. */
1743 if (TARGET_DOUBLE_FLOAT
1744 && ((FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
1745 || (FP_REG_RTX_P (dest
) && MEM_P (src
))
1746 || (FP_REG_RTX_P (src
) && MEM_P (dest
))
1747 || (FP_REG_RTX_P (dest
) && src
== CONST0_RTX (GET_MODE (src
)))))
1753 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
1754 this function handles 64-bit moves for which riscv_split_64bit_move_p
1755 holds. For 64-bit targets, this function handles 128-bit moves. */
1758 riscv_split_doubleword_move (rtx dest
, rtx src
)
1762 /* The operation can be split into two normal moves. Decide in
1763 which order to do them. */
1764 low_dest
= riscv_subword (dest
, false);
1765 if (REG_P (low_dest
) && reg_overlap_mentioned_p (low_dest
, src
))
1767 riscv_emit_move (riscv_subword (dest
, true), riscv_subword (src
, true));
1768 riscv_emit_move (low_dest
, riscv_subword (src
, false));
1772 riscv_emit_move (low_dest
, riscv_subword (src
, false));
1773 riscv_emit_move (riscv_subword (dest
, true), riscv_subword (src
, true));
1777 /* Return the appropriate instructions to move SRC into DEST. Assume
1778 that SRC is operand 1 and DEST is operand 0. */
1781 riscv_output_move (rtx dest
, rtx src
)
1783 enum rtx_code dest_code
, src_code
;
1787 dest_code
= GET_CODE (dest
);
1788 src_code
= GET_CODE (src
);
1789 mode
= GET_MODE (dest
);
1790 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
1792 if (dbl_p
&& riscv_split_64bit_move_p (dest
, src
))
1795 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
1797 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
1798 return dbl_p
? "fmv.x.d\t%0,%1" : "fmv.x.s\t%0,%1";
1800 if (src_code
== MEM
)
1801 switch (GET_MODE_SIZE (mode
))
1803 case 1: return "lbu\t%0,%1";
1804 case 2: return "lhu\t%0,%1";
1805 case 4: return "lw\t%0,%1";
1806 case 8: return "ld\t%0,%1";
1809 if (src_code
== CONST_INT
)
1812 if (src_code
== HIGH
)
1813 return "lui\t%0,%h1";
1815 if (symbolic_operand (src
, VOIDmode
))
1816 switch (riscv_classify_symbolic_expression (src
))
1818 case SYMBOL_GOT_DISP
: return "la\t%0,%1";
1819 case SYMBOL_ABSOLUTE
: return "lla\t%0,%1";
1820 case SYMBOL_PCREL
: return "lla\t%0,%1";
1821 default: gcc_unreachable ();
1824 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
1825 || (src
== CONST0_RTX (mode
)))
1827 if (dest_code
== REG
)
1829 if (GP_REG_P (REGNO (dest
)))
1830 return "mv\t%0,%z1";
1832 if (FP_REG_P (REGNO (dest
)))
1835 return "fmv.s.x\t%0,%z1";
1837 return "fmv.d.x\t%0,%z1";
1838 /* in RV32, we can emulate fmv.d.x %0, x0 using fcvt.d.w */
1839 gcc_assert (src
== CONST0_RTX (mode
));
1840 return "fcvt.d.w\t%0,x0";
1843 if (dest_code
== MEM
)
1844 switch (GET_MODE_SIZE (mode
))
1846 case 1: return "sb\t%z1,%0";
1847 case 2: return "sh\t%z1,%0";
1848 case 4: return "sw\t%z1,%0";
1849 case 8: return "sd\t%z1,%0";
1852 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
1854 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
1855 return dbl_p
? "fmv.d\t%0,%1" : "fmv.s\t%0,%1";
1857 if (dest_code
== MEM
)
1858 return dbl_p
? "fsd\t%1,%0" : "fsw\t%1,%0";
1860 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
1862 if (src_code
== MEM
)
1863 return dbl_p
? "fld\t%0,%1" : "flw\t%0,%1";
1869 riscv_output_return ()
1871 if (cfun
->machine
->naked_p
)
1878 /* Return true if CMP1 is a suitable second operand for integer ordering
1879 test CODE. See also the *sCC patterns in riscv.md. */
1882 riscv_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
1888 return reg_or_0_operand (cmp1
, VOIDmode
);
1892 return cmp1
== const1_rtx
;
1896 return arith_operand (cmp1
, VOIDmode
);
1899 return sle_operand (cmp1
, VOIDmode
);
1902 return sleu_operand (cmp1
, VOIDmode
);
1909 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
1910 integer ordering test *CODE, or if an equivalent combination can
1911 be formed by adjusting *CODE and *CMP1. When returning true, update
1912 *CODE and *CMP1 with the chosen code and operand, otherwise leave
1916 riscv_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
1919 HOST_WIDE_INT plus_one
;
1921 if (riscv_int_order_operand_ok_p (*code
, *cmp1
))
1924 if (CONST_INT_P (*cmp1
))
1928 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
1929 if (INTVAL (*cmp1
) < plus_one
)
1932 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
1938 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
1942 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
1953 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
1954 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
1955 is nonnull, it's OK to set TARGET to the inverse of the result and
1956 flip *INVERT_PTR instead. */
1959 riscv_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
1960 rtx target
, rtx cmp0
, rtx cmp1
)
1964 /* First see if there is a RISCV instruction that can do this operation.
1965 If not, try doing the same for the inverse operation. If that also
1966 fails, force CMP1 into a register and try again. */
1967 mode
= GET_MODE (cmp0
);
1968 if (riscv_canonicalize_int_order_test (&code
, &cmp1
, mode
))
1969 riscv_emit_binary (code
, target
, cmp0
, cmp1
);
1972 enum rtx_code inv_code
= reverse_condition (code
);
1973 if (!riscv_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
1975 cmp1
= force_reg (mode
, cmp1
);
1976 riscv_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
1978 else if (invert_ptr
== 0)
1980 rtx inv_target
= riscv_force_binary (GET_MODE (target
),
1981 inv_code
, cmp0
, cmp1
);
1982 riscv_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
1986 *invert_ptr
= !*invert_ptr
;
1987 riscv_emit_binary (inv_code
, target
, cmp0
, cmp1
);
1992 /* Return a register that is zero iff CMP0 and CMP1 are equal.
1993 The register will have the same mode as CMP0. */
1996 riscv_zero_if_equal (rtx cmp0
, rtx cmp1
)
1998 if (cmp1
== const0_rtx
)
2001 return expand_binop (GET_MODE (cmp0
), sub_optab
,
2002 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
2005 /* Sign- or zero-extend OP0 and OP1 for integer comparisons. */
2008 riscv_extend_comparands (rtx_code code
, rtx
*op0
, rtx
*op1
)
2010 /* Comparisons consider all XLEN bits, so extend sub-XLEN values. */
2011 if (GET_MODE_SIZE (word_mode
) > GET_MODE_SIZE (GET_MODE (*op0
)))
2013 /* It is more profitable to zero-extend QImode values. But not if the
2014 first operand has already been sign-extended, and the second one is
2015 is a constant or has already been sign-extended also. */
2016 if (unsigned_condition (code
) == code
2017 && (GET_MODE (*op0
) == QImode
2018 && ! (GET_CODE (*op0
) == SUBREG
2019 && SUBREG_PROMOTED_VAR_P (*op0
)
2020 && SUBREG_PROMOTED_SIGNED_P (*op0
)
2021 && (CONST_INT_P (*op1
)
2022 || (GET_CODE (*op1
) == SUBREG
2023 && SUBREG_PROMOTED_VAR_P (*op1
)
2024 && SUBREG_PROMOTED_SIGNED_P (*op1
))))))
2026 *op0
= gen_rtx_ZERO_EXTEND (word_mode
, *op0
);
2027 if (CONST_INT_P (*op1
))
2028 *op1
= GEN_INT ((uint8_t) INTVAL (*op1
));
2030 *op1
= gen_rtx_ZERO_EXTEND (word_mode
, *op1
);
2034 *op0
= gen_rtx_SIGN_EXTEND (word_mode
, *op0
);
2035 if (*op1
!= const0_rtx
)
2036 *op1
= gen_rtx_SIGN_EXTEND (word_mode
, *op1
);
2041 /* Convert a comparison into something that can be used in a branch. On
2042 entry, *OP0 and *OP1 are the values being compared and *CODE is the code
2043 used to compare them. Update them to describe the final comparison. */
2046 riscv_emit_int_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
2048 if (splittable_const_int_operand (*op1
, VOIDmode
))
2050 HOST_WIDE_INT rhs
= INTVAL (*op1
);
2052 if (*code
== EQ
|| *code
== NE
)
2054 /* Convert e.g. OP0 == 2048 into OP0 - 2048 == 0. */
2055 if (SMALL_OPERAND (-rhs
))
2057 *op0
= riscv_force_binary (GET_MODE (*op0
), PLUS
, *op0
,
2064 static const enum rtx_code mag_comparisons
[][2] = {
2065 {LEU
, LTU
}, {GTU
, GEU
}, {LE
, LT
}, {GT
, GE
}
2068 /* Convert e.g. (OP0 <= 0xFFF) into (OP0 < 0x1000). */
2069 for (size_t i
= 0; i
< ARRAY_SIZE (mag_comparisons
); i
++)
2071 HOST_WIDE_INT new_rhs
;
2072 bool increment
= *code
== mag_comparisons
[i
][0];
2073 bool decrement
= *code
== mag_comparisons
[i
][1];
2074 if (!increment
&& !decrement
)
2077 new_rhs
= rhs
+ (increment
? 1 : -1);
2078 if (riscv_integer_cost (new_rhs
) < riscv_integer_cost (rhs
)
2079 && (rhs
< 0) == (new_rhs
< 0))
2081 *op1
= GEN_INT (new_rhs
);
2082 *code
= mag_comparisons
[i
][increment
];
2089 riscv_extend_comparands (*code
, op0
, op1
);
2091 *op0
= force_reg (word_mode
, *op0
);
2092 if (*op1
!= const0_rtx
)
2093 *op1
= force_reg (word_mode
, *op1
);
2096 /* Like riscv_emit_int_compare, but for floating-point comparisons. */
2099 riscv_emit_float_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
2101 rtx tmp0
, tmp1
, cmp_op0
= *op0
, cmp_op1
= *op1
;
2102 enum rtx_code fp_code
= *code
;
2112 /* a == a && b == b */
2113 tmp0
= riscv_force_binary (word_mode
, EQ
, cmp_op0
, cmp_op0
);
2114 tmp1
= riscv_force_binary (word_mode
, EQ
, cmp_op1
, cmp_op1
);
2115 *op0
= riscv_force_binary (word_mode
, AND
, tmp0
, tmp1
);
2121 /* ordered(a, b) > (a == b) */
2122 *code
= fp_code
== LTGT
? GTU
: EQ
;
2123 tmp0
= riscv_force_binary (word_mode
, EQ
, cmp_op0
, cmp_op0
);
2124 tmp1
= riscv_force_binary (word_mode
, EQ
, cmp_op1
, cmp_op1
);
2125 *op0
= riscv_force_binary (word_mode
, AND
, tmp0
, tmp1
);
2126 *op1
= riscv_force_binary (word_mode
, EQ
, cmp_op0
, cmp_op1
);
2129 #define UNORDERED_COMPARISON(CODE, CMP) \
2132 *op0 = gen_reg_rtx (word_mode); \
2133 if (GET_MODE (cmp_op0) == SFmode && TARGET_64BIT) \
2134 emit_insn (gen_f##CMP##_quietsfdi4 (*op0, cmp_op0, cmp_op1)); \
2135 else if (GET_MODE (cmp_op0) == SFmode) \
2136 emit_insn (gen_f##CMP##_quietsfsi4 (*op0, cmp_op0, cmp_op1)); \
2137 else if (GET_MODE (cmp_op0) == DFmode && TARGET_64BIT) \
2138 emit_insn (gen_f##CMP##_quietdfdi4 (*op0, cmp_op0, cmp_op1)); \
2139 else if (GET_MODE (cmp_op0) == DFmode) \
2140 emit_insn (gen_f##CMP##_quietdfsi4 (*op0, cmp_op0, cmp_op1)); \
2142 gcc_unreachable (); \
2143 *op1 = const0_rtx; \
2147 std::swap (cmp_op0
, cmp_op1
);
2150 UNORDERED_COMPARISON(UNGT
, le
)
2153 std::swap (cmp_op0
, cmp_op1
);
2156 UNORDERED_COMPARISON(UNGE
, lt
)
2157 #undef UNORDERED_COMPARISON
2169 /* We have instructions for these cases. */
2170 *op0
= riscv_force_binary (word_mode
, fp_code
, cmp_op0
, cmp_op1
);
2179 /* CODE-compare OP0 and OP1. Store the result in TARGET. */
2182 riscv_expand_int_scc (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
)
2184 riscv_extend_comparands (code
, &op0
, &op1
);
2185 op0
= force_reg (word_mode
, op0
);
2187 if (code
== EQ
|| code
== NE
)
2189 rtx zie
= riscv_zero_if_equal (op0
, op1
);
2190 riscv_emit_binary (code
, target
, zie
, const0_rtx
);
2193 riscv_emit_int_order_test (code
, 0, target
, op0
, op1
);
2196 /* Like riscv_expand_int_scc, but for floating-point comparisons. */
2199 riscv_expand_float_scc (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
)
2201 riscv_emit_float_compare (&code
, &op0
, &op1
);
2203 rtx cmp
= riscv_force_binary (word_mode
, code
, op0
, op1
);
2204 riscv_emit_set (target
, lowpart_subreg (SImode
, cmp
, word_mode
));
2207 /* Jump to LABEL if (CODE OP0 OP1) holds. */
2210 riscv_expand_conditional_branch (rtx label
, rtx_code code
, rtx op0
, rtx op1
)
2212 if (FLOAT_MODE_P (GET_MODE (op1
)))
2213 riscv_emit_float_compare (&code
, &op0
, &op1
);
2215 riscv_emit_int_compare (&code
, &op0
, &op1
);
2217 rtx condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
2218 emit_jump_insn (gen_condjump (condition
, label
));
2221 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
2222 least PARM_BOUNDARY bits of alignment, but will be given anything up
2223 to PREFERRED_STACK_BOUNDARY bits if the type requires it. */
2226 riscv_function_arg_boundary (machine_mode mode
, const_tree type
)
2228 unsigned int alignment
;
2230 /* Use natural alignment if the type is not aggregate data. */
2231 if (type
&& !AGGREGATE_TYPE_P (type
))
2232 alignment
= TYPE_ALIGN (TYPE_MAIN_VARIANT (type
));
2234 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
2236 return MIN (PREFERRED_STACK_BOUNDARY
, MAX (PARM_BOUNDARY
, alignment
));
2239 /* If MODE represents an argument that can be passed or returned in
2240 floating-point registers, return the number of registers, else 0. */
2243 riscv_pass_mode_in_fpr_p (machine_mode mode
)
2245 if (GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FP_ARG
)
2247 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2250 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
2259 HOST_WIDE_INT offset
;
2260 } riscv_aggregate_field
;
2262 /* Identify subfields of aggregates that are candidates for passing in
2263 floating-point registers. */
2266 riscv_flatten_aggregate_field (const_tree type
,
2267 riscv_aggregate_field fields
[2],
2268 int n
, HOST_WIDE_INT offset
)
2270 switch (TREE_CODE (type
))
2273 /* Can't handle incomplete types nor sizes that are not fixed. */
2274 if (!COMPLETE_TYPE_P (type
)
2275 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
2276 || !tree_fits_uhwi_p (TYPE_SIZE (type
)))
2279 for (tree f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
2280 if (TREE_CODE (f
) == FIELD_DECL
)
2282 if (!TYPE_P (TREE_TYPE (f
)))
2285 HOST_WIDE_INT pos
= offset
+ int_byte_position (f
);
2286 n
= riscv_flatten_aggregate_field (TREE_TYPE (f
), fields
, n
, pos
);
2294 HOST_WIDE_INT n_elts
;
2295 riscv_aggregate_field subfields
[2];
2296 tree index
= TYPE_DOMAIN (type
);
2297 tree elt_size
= TYPE_SIZE_UNIT (TREE_TYPE (type
));
2298 int n_subfields
= riscv_flatten_aggregate_field (TREE_TYPE (type
),
2299 subfields
, 0, offset
);
2301 /* Can't handle incomplete types nor sizes that are not fixed. */
2302 if (n_subfields
<= 0
2303 || !COMPLETE_TYPE_P (type
)
2304 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
2306 || !TYPE_MAX_VALUE (index
)
2307 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index
))
2308 || !TYPE_MIN_VALUE (index
)
2309 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index
))
2310 || !tree_fits_uhwi_p (elt_size
))
2313 n_elts
= 1 + tree_to_uhwi (TYPE_MAX_VALUE (index
))
2314 - tree_to_uhwi (TYPE_MIN_VALUE (index
));
2315 gcc_assert (n_elts
>= 0);
2317 for (HOST_WIDE_INT i
= 0; i
< n_elts
; i
++)
2318 for (int j
= 0; j
< n_subfields
; j
++)
2323 fields
[n
] = subfields
[j
];
2324 fields
[n
++].offset
+= i
* tree_to_uhwi (elt_size
);
2332 /* Complex type need consume 2 field, so n must be 0. */
2336 HOST_WIDE_INT elt_size
= GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (type
)));
2338 if (elt_size
<= UNITS_PER_FP_ARG
)
2340 fields
[0].type
= TREE_TYPE (type
);
2341 fields
[0].offset
= offset
;
2342 fields
[1].type
= TREE_TYPE (type
);
2343 fields
[1].offset
= offset
+ elt_size
;
2353 && ((SCALAR_FLOAT_TYPE_P (type
)
2354 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FP_ARG
)
2355 || (INTEGRAL_TYPE_P (type
)
2356 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_WORD
)))
2358 fields
[n
].type
= type
;
2359 fields
[n
].offset
= offset
;
2367 /* Identify candidate aggregates for passing in floating-point registers.
2368 Candidates have at most two fields after flattening. */
2371 riscv_flatten_aggregate_argument (const_tree type
,
2372 riscv_aggregate_field fields
[2])
2374 if (!type
|| TREE_CODE (type
) != RECORD_TYPE
)
2377 return riscv_flatten_aggregate_field (type
, fields
, 0, 0);
2380 /* See whether TYPE is a record whose fields should be returned in one or
2381 two floating-point registers. If so, populate FIELDS accordingly. */
2384 riscv_pass_aggregate_in_fpr_pair_p (const_tree type
,
2385 riscv_aggregate_field fields
[2])
2387 int n
= riscv_flatten_aggregate_argument (type
, fields
);
2389 for (int i
= 0; i
< n
; i
++)
2390 if (!SCALAR_FLOAT_TYPE_P (fields
[i
].type
))
2393 return n
> 0 ? n
: 0;
2396 /* See whether TYPE is a record whose fields should be returned in one or
2397 floating-point register and one integer register. If so, populate
2398 FIELDS accordingly. */
2401 riscv_pass_aggregate_in_fpr_and_gpr_p (const_tree type
,
2402 riscv_aggregate_field fields
[2])
2404 unsigned num_int
= 0, num_float
= 0;
2405 int n
= riscv_flatten_aggregate_argument (type
, fields
);
2407 for (int i
= 0; i
< n
; i
++)
2409 num_float
+= SCALAR_FLOAT_TYPE_P (fields
[i
].type
);
2410 num_int
+= INTEGRAL_TYPE_P (fields
[i
].type
);
2413 return num_int
== 1 && num_float
== 1;
2416 /* Return the representation of an argument passed or returned in an FPR
2417 when the value has mode VALUE_MODE and the type has TYPE_MODE. The
2418 two modes may be different for structures like:
2420 struct __attribute__((packed)) foo { float f; }
2422 where the SFmode value "f" is passed in REGNO but the struct itself
2423 has mode BLKmode. */
2426 riscv_pass_fpr_single (machine_mode type_mode
, unsigned regno
,
2427 machine_mode value_mode
)
2429 rtx x
= gen_rtx_REG (value_mode
, regno
);
2431 if (type_mode
!= value_mode
)
2433 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, const0_rtx
);
2434 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
2439 /* Pass or return a composite value in the FPR pair REGNO and REGNO + 1.
2440 MODE is the mode of the composite. MODE1 and OFFSET1 are the mode and
2441 byte offset for the first value, likewise MODE2 and OFFSET2 for the
2445 riscv_pass_fpr_pair (machine_mode mode
, unsigned regno1
,
2446 machine_mode mode1
, HOST_WIDE_INT offset1
,
2447 unsigned regno2
, machine_mode mode2
,
2448 HOST_WIDE_INT offset2
)
2450 return gen_rtx_PARALLEL
2453 gen_rtx_EXPR_LIST (VOIDmode
,
2454 gen_rtx_REG (mode1
, regno1
),
2456 gen_rtx_EXPR_LIST (VOIDmode
,
2457 gen_rtx_REG (mode2
, regno2
),
2458 GEN_INT (offset2
))));
2461 /* Fill INFO with information about a single argument, and return an
2462 RTL pattern to pass or return the argument. CUM is the cumulative
2463 state for earlier arguments. MODE is the mode of this argument and
2464 TYPE is its type (if known). NAMED is true if this is a named
2465 (fixed) argument rather than a variable one. RETURN_P is true if
2466 returning the argument, or false if passing the argument. */
2469 riscv_get_arg_info (struct riscv_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
2470 machine_mode mode
, const_tree type
, bool named
,
2473 unsigned num_bytes
, num_words
;
2474 unsigned fpr_base
= return_p
? FP_RETURN
: FP_ARG_FIRST
;
2475 unsigned gpr_base
= return_p
? GP_RETURN
: GP_ARG_FIRST
;
2476 unsigned alignment
= riscv_function_arg_boundary (mode
, type
);
2478 memset (info
, 0, sizeof (*info
));
2479 info
->gpr_offset
= cum
->num_gprs
;
2480 info
->fpr_offset
= cum
->num_fprs
;
2484 riscv_aggregate_field fields
[2];
2485 unsigned fregno
= fpr_base
+ info
->fpr_offset
;
2486 unsigned gregno
= gpr_base
+ info
->gpr_offset
;
2488 /* Pass one- or two-element floating-point aggregates in FPRs. */
2489 if ((info
->num_fprs
= riscv_pass_aggregate_in_fpr_pair_p (type
, fields
))
2490 && info
->fpr_offset
+ info
->num_fprs
<= MAX_ARGS_IN_REGISTERS
)
2491 switch (info
->num_fprs
)
2494 return riscv_pass_fpr_single (mode
, fregno
,
2495 TYPE_MODE (fields
[0].type
));
2498 return riscv_pass_fpr_pair (mode
, fregno
,
2499 TYPE_MODE (fields
[0].type
),
2502 TYPE_MODE (fields
[1].type
),
2509 /* Pass real and complex floating-point numbers in FPRs. */
2510 if ((info
->num_fprs
= riscv_pass_mode_in_fpr_p (mode
))
2511 && info
->fpr_offset
+ info
->num_fprs
<= MAX_ARGS_IN_REGISTERS
)
2512 switch (GET_MODE_CLASS (mode
))
2515 return gen_rtx_REG (mode
, fregno
);
2517 case MODE_COMPLEX_FLOAT
:
2518 return riscv_pass_fpr_pair (mode
, fregno
, GET_MODE_INNER (mode
), 0,
2519 fregno
+ 1, GET_MODE_INNER (mode
),
2520 GET_MODE_UNIT_SIZE (mode
));
2526 /* Pass structs with one float and one integer in an FPR and a GPR. */
2527 if (riscv_pass_aggregate_in_fpr_and_gpr_p (type
, fields
)
2528 && info
->gpr_offset
< MAX_ARGS_IN_REGISTERS
2529 && info
->fpr_offset
< MAX_ARGS_IN_REGISTERS
)
2534 if (!SCALAR_FLOAT_TYPE_P (fields
[0].type
))
2535 std::swap (fregno
, gregno
);
2537 return riscv_pass_fpr_pair (mode
, fregno
, TYPE_MODE (fields
[0].type
),
2539 gregno
, TYPE_MODE (fields
[1].type
),
2544 /* Work out the size of the argument. */
2545 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
2546 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2548 /* Doubleword-aligned varargs start on an even register boundary. */
2549 if (!named
&& num_bytes
!= 0 && alignment
> BITS_PER_WORD
)
2550 info
->gpr_offset
+= info
->gpr_offset
& 1;
2552 /* Partition the argument between registers and stack. */
2554 info
->num_gprs
= MIN (num_words
, MAX_ARGS_IN_REGISTERS
- info
->gpr_offset
);
2555 info
->stack_p
= (num_words
- info
->num_gprs
) != 0;
2557 if (info
->num_gprs
|| return_p
)
2558 return gen_rtx_REG (mode
, gpr_base
+ info
->gpr_offset
);
2563 /* Implement TARGET_FUNCTION_ARG. */
2566 riscv_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
2567 const_tree type
, bool named
)
2569 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2570 struct riscv_arg_info info
;
2572 if (mode
== VOIDmode
)
2575 return riscv_get_arg_info (&info
, cum
, mode
, type
, named
, false);
2578 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
2581 riscv_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
2582 const_tree type
, bool named
)
2584 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2585 struct riscv_arg_info info
;
2587 riscv_get_arg_info (&info
, cum
, mode
, type
, named
, false);
2589 /* Advance the register count. This has the effect of setting
2590 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
2591 argument required us to skip the final GPR and pass the whole
2592 argument on the stack. */
2593 cum
->num_fprs
= info
.fpr_offset
+ info
.num_fprs
;
2594 cum
->num_gprs
= info
.gpr_offset
+ info
.num_gprs
;
2597 /* Implement TARGET_ARG_PARTIAL_BYTES. */
2600 riscv_arg_partial_bytes (cumulative_args_t cum
,
2601 machine_mode mode
, tree type
, bool named
)
2603 struct riscv_arg_info arg
;
2605 riscv_get_arg_info (&arg
, get_cumulative_args (cum
), mode
, type
, named
, false);
2606 return arg
.stack_p
? arg
.num_gprs
* UNITS_PER_WORD
: 0;
2609 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
2610 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
2611 VALTYPE is null and MODE is the mode of the return value. */
2614 riscv_function_value (const_tree type
, const_tree func
, machine_mode mode
)
2616 struct riscv_arg_info info
;
2617 CUMULATIVE_ARGS args
;
2621 int unsigned_p
= TYPE_UNSIGNED (type
);
2623 mode
= TYPE_MODE (type
);
2625 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
2626 return values, promote the mode here too. */
2627 mode
= promote_function_mode (type
, mode
, &unsigned_p
, func
, 1);
2630 memset (&args
, 0, sizeof args
);
2631 return riscv_get_arg_info (&info
, &args
, mode
, type
, true, true);
2634 /* Implement TARGET_PASS_BY_REFERENCE. */
2637 riscv_pass_by_reference (cumulative_args_t cum_v
, machine_mode mode
,
2638 const_tree type
, bool named
)
2640 HOST_WIDE_INT size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
2641 struct riscv_arg_info info
;
2642 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2644 /* ??? std_gimplify_va_arg_expr passes NULL for cum. Fortunately, we
2645 never pass variadic arguments in floating-point registers, so we can
2646 avoid the call to riscv_get_arg_info in this case. */
2649 /* Don't pass by reference if we can use a floating-point register. */
2650 riscv_get_arg_info (&info
, cum
, mode
, type
, named
, false);
2655 /* Pass by reference if the data do not fit in two integer registers. */
2656 return !IN_RANGE (size
, 0, 2 * UNITS_PER_WORD
);
2659 /* Implement TARGET_RETURN_IN_MEMORY. */
2662 riscv_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
2664 CUMULATIVE_ARGS args
;
2665 cumulative_args_t cum
= pack_cumulative_args (&args
);
2667 /* The rules for returning in memory are the same as for passing the
2668 first named argument by reference. */
2669 memset (&args
, 0, sizeof args
);
2670 return riscv_pass_by_reference (cum
, TYPE_MODE (type
), type
, true);
2673 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
2676 riscv_setup_incoming_varargs (cumulative_args_t cum
, machine_mode mode
,
2677 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
2680 CUMULATIVE_ARGS local_cum
;
2683 /* The caller has advanced CUM up to, but not beyond, the last named
2684 argument. Advance a local copy of CUM past the last "real" named
2685 argument, to find out how many registers are left over. */
2686 local_cum
= *get_cumulative_args (cum
);
2687 riscv_function_arg_advance (pack_cumulative_args (&local_cum
), mode
, type
, 1);
2689 /* Found out how many registers we need to save. */
2690 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
2692 if (!no_rtl
&& gp_saved
> 0)
2694 rtx ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
,
2695 REG_PARM_STACK_SPACE (cfun
->decl
)
2696 - gp_saved
* UNITS_PER_WORD
);
2697 rtx mem
= gen_frame_mem (BLKmode
, ptr
);
2698 set_mem_alias_set (mem
, get_varargs_alias_set ());
2700 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
2703 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
2704 cfun
->machine
->varargs_size
= gp_saved
* UNITS_PER_WORD
;
2707 /* Handle an attribute requiring a FUNCTION_DECL;
2708 arguments as in struct attribute_spec.handler. */
2710 riscv_handle_fndecl_attribute (tree
*node
, tree name
,
2711 tree args ATTRIBUTE_UNUSED
,
2712 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2714 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2716 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
2718 *no_add_attrs
= true;
2724 /* Return true if function TYPE is an interrupt function. */
2726 riscv_interrupt_type_p (tree type
)
2728 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
2731 /* Return true if FUNC is a naked function. */
2733 riscv_naked_function_p (tree func
)
2735 tree func_decl
= func
;
2736 if (func
== NULL_TREE
)
2737 func_decl
= current_function_decl
;
2738 return NULL_TREE
!= lookup_attribute ("naked", DECL_ATTRIBUTES (func_decl
));
2741 /* Implement TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS. */
2743 riscv_allocate_stack_slots_for_args ()
2745 /* Naked functions should not allocate stack slots for arguments. */
2746 return !riscv_naked_function_p (current_function_decl
);
2749 /* Implement TARGET_WARN_FUNC_RETURN. */
2751 riscv_warn_func_return (tree decl
)
2753 /* Naked functions are implemented entirely in assembly, including the
2754 return sequence, so suppress warnings about this. */
2755 return !riscv_naked_function_p (decl
);
2758 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
2761 riscv_va_start (tree valist
, rtx nextarg
)
2763 nextarg
= plus_constant (Pmode
, nextarg
, -cfun
->machine
->varargs_size
);
2764 std_expand_builtin_va_start (valist
, nextarg
);
2767 /* Make ADDR suitable for use as a call or sibcall target. */
2770 riscv_legitimize_call_address (rtx addr
)
2772 if (!call_insn_operand (addr
, VOIDmode
))
2774 rtx reg
= RISCV_PROLOGUE_TEMP (Pmode
);
2775 riscv_emit_move (reg
, addr
);
2781 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
2782 Assume that the areas do not overlap. */
2785 riscv_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
2787 HOST_WIDE_INT offset
, delta
;
2788 unsigned HOST_WIDE_INT bits
;
2790 enum machine_mode mode
;
2793 bits
= MAX (BITS_PER_UNIT
,
2794 MIN (BITS_PER_WORD
, MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
))));
2796 mode
= mode_for_size (bits
, MODE_INT
, 0).require ();
2797 delta
= bits
/ BITS_PER_UNIT
;
2799 /* Allocate a buffer for the temporary registers. */
2800 regs
= XALLOCAVEC (rtx
, length
/ delta
);
2802 /* Load as many BITS-sized chunks as possible. Use a normal load if
2803 the source has enough alignment, otherwise use left/right pairs. */
2804 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
2806 regs
[i
] = gen_reg_rtx (mode
);
2807 riscv_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
2810 /* Copy the chunks to the destination. */
2811 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
2812 riscv_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
2814 /* Mop up any left-over bytes. */
2815 if (offset
< length
)
2817 src
= adjust_address (src
, BLKmode
, offset
);
2818 dest
= adjust_address (dest
, BLKmode
, offset
);
2819 move_by_pieces (dest
, src
, length
- offset
,
2820 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
2824 /* Helper function for doing a loop-based block operation on memory
2825 reference MEM. Each iteration of the loop will operate on LENGTH
2828 Create a new base register for use within the loop and point it to
2829 the start of MEM. Create a new memory reference that uses this
2830 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
2833 riscv_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
2834 rtx
*loop_reg
, rtx
*loop_mem
)
2836 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
2838 /* Although the new mem does not refer to a known location,
2839 it does keep up to LENGTH bytes of alignment. */
2840 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
2841 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
2844 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
2845 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
2846 the memory regions do not overlap. */
2849 riscv_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
2850 HOST_WIDE_INT bytes_per_iter
)
2852 rtx label
, src_reg
, dest_reg
, final_src
, test
;
2853 HOST_WIDE_INT leftover
;
2855 leftover
= length
% bytes_per_iter
;
2858 /* Create registers and memory references for use within the loop. */
2859 riscv_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
2860 riscv_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
2862 /* Calculate the value that SRC_REG should have after the last iteration
2864 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
2867 /* Emit the start of the loop. */
2868 label
= gen_label_rtx ();
2871 /* Emit the loop body. */
2872 riscv_block_move_straight (dest
, src
, bytes_per_iter
);
2874 /* Move on to the next block. */
2875 riscv_emit_move (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
2876 riscv_emit_move (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
2878 /* Emit the loop condition. */
2879 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
2880 if (Pmode
== DImode
)
2881 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
2883 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
2885 /* Mop up any left-over bytes. */
2887 riscv_block_move_straight (dest
, src
, leftover
);
2889 emit_insn(gen_nop ());
2892 /* Expand a movmemsi instruction, which copies LENGTH bytes from
2893 memory reference SRC to memory reference DEST. */
2896 riscv_expand_block_move (rtx dest
, rtx src
, rtx length
)
2898 if (CONST_INT_P (length
))
2900 HOST_WIDE_INT factor
, align
;
2902 align
= MIN (MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), BITS_PER_WORD
);
2903 factor
= BITS_PER_WORD
/ align
;
2905 if (optimize_function_for_size_p (cfun
)
2906 && INTVAL (length
) * factor
* UNITS_PER_WORD
> MOVE_RATIO (false))
2909 if (INTVAL (length
) <= RISCV_MAX_MOVE_BYTES_STRAIGHT
/ factor
)
2911 riscv_block_move_straight (dest
, src
, INTVAL (length
));
2914 else if (optimize
&& align
>= BITS_PER_WORD
)
2916 unsigned min_iter_words
2917 = RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER
/ UNITS_PER_WORD
;
2918 unsigned iter_words
= min_iter_words
;
2919 HOST_WIDE_INT bytes
= INTVAL (length
), words
= bytes
/ UNITS_PER_WORD
;
2921 /* Lengthen the loop body if it shortens the tail. */
2922 for (unsigned i
= min_iter_words
; i
< min_iter_words
* 2 - 1; i
++)
2924 unsigned cur_cost
= iter_words
+ words
% iter_words
;
2925 unsigned new_cost
= i
+ words
% i
;
2926 if (new_cost
<= cur_cost
)
2930 riscv_block_move_loop (dest
, src
, bytes
, iter_words
* UNITS_PER_WORD
);
2937 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
2938 in context CONTEXT. HI_RELOC indicates a high-part reloc. */
2941 riscv_print_operand_reloc (FILE *file
, rtx op
, bool hi_reloc
)
2945 switch (riscv_classify_symbolic_expression (op
))
2947 case SYMBOL_ABSOLUTE
:
2948 reloc
= hi_reloc
? "%hi" : "%lo";
2952 reloc
= hi_reloc
? "%pcrel_hi" : "%pcrel_lo";
2956 reloc
= hi_reloc
? "%tprel_hi" : "%tprel_lo";
2963 fprintf (file
, "%s(", reloc
);
2964 output_addr_const (file
, riscv_strip_unspec_address (op
));
2968 /* Return true if the .AQ suffix should be added to an AMO to implement the
2969 acquire portion of memory model MODEL. */
2972 riscv_memmodel_needs_amo_acquire (enum memmodel model
)
2976 case MEMMODEL_ACQ_REL
:
2977 case MEMMODEL_SEQ_CST
:
2978 case MEMMODEL_SYNC_SEQ_CST
:
2979 case MEMMODEL_ACQUIRE
:
2980 case MEMMODEL_CONSUME
:
2981 case MEMMODEL_SYNC_ACQUIRE
:
2984 case MEMMODEL_RELEASE
:
2985 case MEMMODEL_SYNC_RELEASE
:
2986 case MEMMODEL_RELAXED
:
2994 /* Return true if a FENCE should be emitted to before a memory access to
2995 implement the release portion of memory model MODEL. */
2998 riscv_memmodel_needs_release_fence (enum memmodel model
)
3002 case MEMMODEL_ACQ_REL
:
3003 case MEMMODEL_SEQ_CST
:
3004 case MEMMODEL_SYNC_SEQ_CST
:
3005 case MEMMODEL_RELEASE
:
3006 case MEMMODEL_SYNC_RELEASE
:
3009 case MEMMODEL_ACQUIRE
:
3010 case MEMMODEL_CONSUME
:
3011 case MEMMODEL_SYNC_ACQUIRE
:
3012 case MEMMODEL_RELAXED
:
3020 /* Implement TARGET_PRINT_OPERAND. The RISCV-specific operand codes are:
3022 'h' Print the high-part relocation associated with OP, after stripping
3024 'R' Print the low-part relocation associated with OP.
3025 'C' Print the integer branch condition for comparison OP.
3026 'A' Print the atomic operation suffix for memory model OP.
3027 'F' Print a FENCE if the memory model requires a release.
3028 'z' Print x0 if OP is zero, otherwise print OP normally.
3029 'i' Print i if the operand is not a register. */
3032 riscv_print_operand (FILE *file
, rtx op
, int letter
)
3034 machine_mode mode
= GET_MODE (op
);
3035 enum rtx_code code
= GET_CODE (op
);
3042 riscv_print_operand_reloc (file
, op
, true);
3046 riscv_print_operand_reloc (file
, op
, false);
3050 /* The RTL names match the instruction names. */
3051 fputs (GET_RTX_NAME (code
), file
);
3055 if (riscv_memmodel_needs_amo_acquire ((enum memmodel
) INTVAL (op
)))
3056 fputs (".aq", file
);
3060 if (riscv_memmodel_needs_release_fence ((enum memmodel
) INTVAL (op
)))
3061 fputs ("fence iorw,ow; ", file
);
3073 if (letter
&& letter
!= 'z')
3074 output_operand_lossage ("invalid use of '%%%c'", letter
);
3075 fprintf (file
, "%s", reg_names
[REGNO (op
)]);
3079 if (letter
&& letter
!= 'z')
3080 output_operand_lossage ("invalid use of '%%%c'", letter
);
3082 output_address (mode
, XEXP (op
, 0));
3086 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
3087 fputs (reg_names
[GP_REG_FIRST
], file
);
3088 else if (letter
&& letter
!= 'z')
3089 output_operand_lossage ("invalid use of '%%%c'", letter
);
3091 output_addr_const (file
, riscv_strip_unspec_address (op
));
3097 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
3100 riscv_print_operand_address (FILE *file
, machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
3102 struct riscv_address_info addr
;
3104 if (riscv_classify_address (&addr
, x
, word_mode
, true))
3108 riscv_print_operand (file
, addr
.offset
, 0);
3109 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
3112 case ADDRESS_LO_SUM
:
3113 riscv_print_operand_reloc (file
, addr
.offset
, false);
3114 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
3117 case ADDRESS_CONST_INT
:
3118 output_addr_const (file
, x
);
3119 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
3122 case ADDRESS_SYMBOLIC
:
3123 output_addr_const (file
, riscv_strip_unspec_address (x
));
3130 riscv_size_ok_for_small_data_p (int size
)
3132 return g_switch_value
&& IN_RANGE (size
, 1, g_switch_value
);
3135 /* Return true if EXP should be placed in the small data section. */
3138 riscv_in_small_data_p (const_tree x
)
3140 if (TREE_CODE (x
) == STRING_CST
|| TREE_CODE (x
) == FUNCTION_DECL
)
3143 if (TREE_CODE (x
) == VAR_DECL
&& DECL_SECTION_NAME (x
))
3145 const char *sec
= DECL_SECTION_NAME (x
);
3146 return strcmp (sec
, ".sdata") == 0 || strcmp (sec
, ".sbss") == 0;
3149 return riscv_size_ok_for_small_data_p (int_size_in_bytes (TREE_TYPE (x
)));
3152 /* Switch to the appropriate section for output of DECL. */
3155 riscv_select_section (tree decl
, int reloc
,
3156 unsigned HOST_WIDE_INT align
)
3158 switch (categorize_decl_for_section (decl
, reloc
))
3160 case SECCAT_SRODATA
:
3161 return get_named_section (decl
, ".srodata", reloc
);
3164 return default_elf_select_section (decl
, reloc
, align
);
3168 /* Return a section for X, handling small data. */
3171 riscv_elf_select_rtx_section (machine_mode mode
, rtx x
,
3172 unsigned HOST_WIDE_INT align
)
3174 section
*s
= default_elf_select_rtx_section (mode
, x
, align
);
3176 if (riscv_size_ok_for_small_data_p (GET_MODE_SIZE (mode
)))
3178 if (strncmp (s
->named
.name
, ".rodata.cst", strlen (".rodata.cst")) == 0)
3180 /* Rename .rodata.cst* to .srodata.cst*. */
3181 char *name
= (char *) alloca (strlen (s
->named
.name
) + 2);
3182 sprintf (name
, ".s%s", s
->named
.name
+ 1);
3183 return get_section (name
, s
->named
.common
.flags
, NULL
);
3186 if (s
== data_section
)
3187 return sdata_section
;
3193 /* Make the last instruction frame-related and note that it performs
3194 the operation described by FRAME_PATTERN. */
3197 riscv_set_frame_expr (rtx frame_pattern
)
3201 insn
= get_last_insn ();
3202 RTX_FRAME_RELATED_P (insn
) = 1;
3203 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
3208 /* Return a frame-related rtx that stores REG at MEM.
3209 REG must be a single register. */
3212 riscv_frame_set (rtx mem
, rtx reg
)
3214 rtx set
= gen_rtx_SET (mem
, reg
);
3215 RTX_FRAME_RELATED_P (set
) = 1;
3219 /* Return true if the current function must save register REGNO. */
3222 riscv_save_reg_p (unsigned int regno
)
3224 bool call_saved
= !global_regs
[regno
] && !call_used_regs
[regno
];
3225 bool might_clobber
= crtl
->saves_all_registers
3226 || df_regs_ever_live_p (regno
);
3228 if (call_saved
&& might_clobber
)
3231 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
3234 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
3237 /* If this is an interrupt handler, then must save extra registers. */
3238 if (cfun
->machine
->interrupt_handler_p
)
3240 /* zero register is always zero. */
3241 if (regno
== GP_REG_FIRST
)
3244 /* The function will return the stack pointer to its original value. */
3245 if (regno
== STACK_POINTER_REGNUM
)
3248 /* By convention, we assume that gp and tp are safe. */
3249 if (regno
== GP_REGNUM
|| regno
== THREAD_POINTER_REGNUM
)
3252 /* We must save every register used in this function. If this is not a
3253 leaf function, then we must save all temporary registers. */
3254 if (df_regs_ever_live_p (regno
)
3255 || (!crtl
->is_leaf
&& call_used_regs
[regno
]))
3262 /* Determine whether to call GPR save/restore routines. */
3264 riscv_use_save_libcall (const struct riscv_frame_info
*frame
)
3266 if (!TARGET_SAVE_RESTORE
|| crtl
->calls_eh_return
|| frame_pointer_needed
3267 || cfun
->machine
->interrupt_handler_p
)
3270 return frame
->save_libcall_adjustment
!= 0;
3273 /* Determine which GPR save/restore routine to call. */
3276 riscv_save_libcall_count (unsigned mask
)
3278 for (unsigned n
= GP_REG_LAST
; n
> GP_REG_FIRST
; n
--)
3279 if (BITSET_P (mask
, n
))
3280 return CALLEE_SAVED_REG_NUMBER (n
) + 1;
3284 /* Populate the current function's riscv_frame_info structure.
3286 RISC-V stack frames grown downward. High addresses are at the top.
3288 +-------------------------------+
3290 | incoming stack arguments |
3292 +-------------------------------+ <-- incoming stack pointer
3294 | callee-allocated save area |
3295 | for arguments that are |
3296 | split between registers and |
3299 +-------------------------------+ <-- arg_pointer_rtx
3301 | callee-allocated save area |
3302 | for register varargs |
3304 +-------------------------------+ <-- hard_frame_pointer_rtx;
3305 | | stack_pointer_rtx + gp_sp_offset
3306 | GPR save area | + UNITS_PER_WORD
3308 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
3309 | | + UNITS_PER_HWVALUE
3312 +-------------------------------+ <-- frame_pointer_rtx (virtual)
3316 P +-------------------------------+
3318 | outgoing stack arguments |
3320 +-------------------------------+ <-- stack_pointer_rtx
3322 Dynamic stack allocations such as alloca insert data at point P.
3323 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
3324 hard_frame_pointer_rtx unchanged. */
3326 static HOST_WIDE_INT
riscv_first_stack_step (struct riscv_frame_info
*frame
);
3329 riscv_compute_frame_info (void)
3331 struct riscv_frame_info
*frame
;
3332 HOST_WIDE_INT offset
;
3333 bool interrupt_save_t1
= false;
3334 unsigned int regno
, i
, num_x_saved
= 0, num_f_saved
= 0;
3336 frame
= &cfun
->machine
->frame
;
3338 /* In an interrupt function, if we have a large frame, then we need to
3339 save/restore t1. We check for this before clearing the frame struct. */
3340 if (cfun
->machine
->interrupt_handler_p
)
3342 HOST_WIDE_INT step1
= riscv_first_stack_step (frame
);
3343 if (! SMALL_OPERAND (frame
->total_size
- step1
))
3344 interrupt_save_t1
= true;
3347 memset (frame
, 0, sizeof (*frame
));
3349 if (!cfun
->machine
->naked_p
)
3351 /* Find out which GPRs we need to save. */
3352 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
3353 if (riscv_save_reg_p (regno
)
3354 || (interrupt_save_t1
&& (regno
== T1_REGNUM
)))
3355 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
), num_x_saved
++;
3357 /* If this function calls eh_return, we must also save and restore the
3358 EH data registers. */
3359 if (crtl
->calls_eh_return
)
3360 for (i
= 0; (regno
= EH_RETURN_DATA_REGNO (i
)) != INVALID_REGNUM
; i
++)
3361 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
), num_x_saved
++;
3363 /* Find out which FPRs we need to save. This loop must iterate over
3364 the same space as its companion in riscv_for_each_saved_reg. */
3365 if (TARGET_HARD_FLOAT
)
3366 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
3367 if (riscv_save_reg_p (regno
))
3368 frame
->fmask
|= 1 << (regno
- FP_REG_FIRST
), num_f_saved
++;
3371 /* At the bottom of the frame are any outgoing stack arguments. */
3372 offset
= RISCV_STACK_ALIGN (crtl
->outgoing_args_size
);
3373 /* Next are local stack variables. */
3374 offset
+= RISCV_STACK_ALIGN (get_frame_size ());
3375 /* The virtual frame pointer points above the local variables. */
3376 frame
->frame_pointer_offset
= offset
;
3377 /* Next are the callee-saved FPRs. */
3379 offset
+= RISCV_STACK_ALIGN (num_f_saved
* UNITS_PER_FP_REG
);
3380 frame
->fp_sp_offset
= offset
- UNITS_PER_FP_REG
;
3381 /* Next are the callee-saved GPRs. */
3384 unsigned x_save_size
= RISCV_STACK_ALIGN (num_x_saved
* UNITS_PER_WORD
);
3385 unsigned num_save_restore
= 1 + riscv_save_libcall_count (frame
->mask
);
3387 /* Only use save/restore routines if they don't alter the stack size. */
3388 if (RISCV_STACK_ALIGN (num_save_restore
* UNITS_PER_WORD
) == x_save_size
)
3390 /* Libcall saves/restores 3 registers at once, so we need to
3391 allocate 12 bytes for callee-saved register. */
3393 x_save_size
= 3 * UNITS_PER_WORD
;
3395 frame
->save_libcall_adjustment
= x_save_size
;
3398 offset
+= x_save_size
;
3400 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
3401 /* The hard frame pointer points above the callee-saved GPRs. */
3402 frame
->hard_frame_pointer_offset
= offset
;
3403 /* Above the hard frame pointer is the callee-allocated varags save area. */
3404 offset
+= RISCV_STACK_ALIGN (cfun
->machine
->varargs_size
);
3405 /* Next is the callee-allocated area for pretend stack arguments. */
3406 offset
+= RISCV_STACK_ALIGN (crtl
->args
.pretend_args_size
);
3407 /* Arg pointer must be below pretend args, but must be above alignment
3409 frame
->arg_pointer_offset
= offset
- crtl
->args
.pretend_args_size
;
3410 frame
->total_size
= offset
;
3411 /* Next points the incoming stack pointer and any incoming arguments. */
3413 /* Only use save/restore routines when the GPRs are atop the frame. */
3414 if (frame
->hard_frame_pointer_offset
!= frame
->total_size
)
3415 frame
->save_libcall_adjustment
= 0;
3418 /* Make sure that we're not trying to eliminate to the wrong hard frame
3422 riscv_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
3424 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
3427 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
3428 or argument pointer. TO is either the stack pointer or hard frame
3432 riscv_initial_elimination_offset (int from
, int to
)
3434 HOST_WIDE_INT src
, dest
;
3436 riscv_compute_frame_info ();
3438 if (to
== HARD_FRAME_POINTER_REGNUM
)
3439 dest
= cfun
->machine
->frame
.hard_frame_pointer_offset
;
3440 else if (to
== STACK_POINTER_REGNUM
)
3441 dest
= 0; /* The stack pointer is the base of all offsets, hence 0. */
3445 if (from
== FRAME_POINTER_REGNUM
)
3446 src
= cfun
->machine
->frame
.frame_pointer_offset
;
3447 else if (from
== ARG_POINTER_REGNUM
)
3448 src
= cfun
->machine
->frame
.arg_pointer_offset
;
3455 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
3459 riscv_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
3464 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
3467 /* Emit code to change the current function's return address to
3468 ADDRESS. SCRATCH is available as a scratch register, if needed.
3469 ADDRESS and SCRATCH are both word-mode GPRs. */
3472 riscv_set_return_address (rtx address
, rtx scratch
)
3476 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
3477 slot_address
= riscv_add_offset (scratch
, stack_pointer_rtx
,
3478 cfun
->machine
->frame
.gp_sp_offset
);
3479 riscv_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
3482 /* A function to save or store a register. The first argument is the
3483 register and the second is the stack slot. */
3484 typedef void (*riscv_save_restore_fn
) (rtx
, rtx
);
3486 /* Use FN to save or restore register REGNO. MODE is the register's
3487 mode and OFFSET is the offset of its save slot from the current
3491 riscv_save_restore_reg (machine_mode mode
, int regno
,
3492 HOST_WIDE_INT offset
, riscv_save_restore_fn fn
)
3496 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, stack_pointer_rtx
, offset
));
3497 fn (gen_rtx_REG (mode
, regno
), mem
);
3500 /* Call FN for each register that is saved by the current function.
3501 SP_OFFSET is the offset of the current stack pointer from the start
3505 riscv_for_each_saved_reg (HOST_WIDE_INT sp_offset
, riscv_save_restore_fn fn
)
3507 HOST_WIDE_INT offset
;
3509 /* Save the link register and s-registers. */
3510 offset
= cfun
->machine
->frame
.gp_sp_offset
- sp_offset
;
3511 for (int regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
3512 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
3514 riscv_save_restore_reg (word_mode
, regno
, offset
, fn
);
3515 offset
-= UNITS_PER_WORD
;
3518 /* This loop must iterate over the same space as its companion in
3519 riscv_compute_frame_info. */
3520 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
3521 for (int regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
3522 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
3524 machine_mode mode
= TARGET_DOUBLE_FLOAT
? DFmode
: SFmode
;
3526 riscv_save_restore_reg (mode
, regno
, offset
, fn
);
3527 offset
-= GET_MODE_SIZE (mode
);
3531 /* Save register REG to MEM. Make the instruction frame-related. */
3534 riscv_save_reg (rtx reg
, rtx mem
)
3536 riscv_emit_move (mem
, reg
);
3537 riscv_set_frame_expr (riscv_frame_set (mem
, reg
));
3540 /* Restore register REG from MEM. */
3543 riscv_restore_reg (rtx reg
, rtx mem
)
3545 rtx insn
= riscv_emit_move (reg
, mem
);
3546 rtx dwarf
= NULL_RTX
;
3547 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
3548 REG_NOTES (insn
) = dwarf
;
3550 RTX_FRAME_RELATED_P (insn
) = 1;
3553 /* Return the code to invoke the GPR save routine. */
3556 riscv_output_gpr_save (unsigned mask
)
3559 unsigned n
= riscv_save_libcall_count (mask
);
3561 ssize_t bytes
= snprintf (s
, sizeof (s
), "call\tt0,__riscv_save_%u", n
);
3562 gcc_assert ((size_t) bytes
< sizeof (s
));
3567 /* For stack frames that can't be allocated with a single ADDI instruction,
3568 compute the best value to initially allocate. It must at a minimum
3569 allocate enough space to spill the callee-saved registers. If TARGET_RVC,
3570 try to pick a value that will allow compression of the register saves
3571 without adding extra instructions. */
3573 static HOST_WIDE_INT
3574 riscv_first_stack_step (struct riscv_frame_info
*frame
)
3576 if (SMALL_OPERAND (frame
->total_size
))
3577 return frame
->total_size
;
3579 HOST_WIDE_INT min_first_step
=
3580 RISCV_STACK_ALIGN (frame
->total_size
- frame
->fp_sp_offset
);
3581 HOST_WIDE_INT max_first_step
= IMM_REACH
/ 2 - PREFERRED_STACK_BOUNDARY
/ 8;
3582 HOST_WIDE_INT min_second_step
= frame
->total_size
- max_first_step
;
3583 gcc_assert (min_first_step
<= max_first_step
);
3585 /* As an optimization, use the least-significant bits of the total frame
3586 size, so that the second adjustment step is just LUI + ADD. */
3587 if (!SMALL_OPERAND (min_second_step
)
3588 && frame
->total_size
% IMM_REACH
< IMM_REACH
/ 2
3589 && frame
->total_size
% IMM_REACH
>= min_first_step
)
3590 return frame
->total_size
% IMM_REACH
;
3594 /* If we need two subtracts, and one is small enough to allow compressed
3595 loads and stores, then put that one first. */
3596 if (IN_RANGE (min_second_step
, 0,
3597 (TARGET_64BIT
? SDSP_REACH
: SWSP_REACH
)))
3598 return MAX (min_second_step
, min_first_step
);
3600 /* If we need LUI + ADDI + ADD for the second adjustment step, then start
3601 with the minimum first step, so that we can get compressed loads and
3603 else if (!SMALL_OPERAND (min_second_step
))
3604 return min_first_step
;
3607 return max_first_step
;
3611 riscv_adjust_libcall_cfi_prologue ()
3613 rtx dwarf
= NULL_RTX
;
3614 rtx adjust_sp_rtx
, reg
, mem
, insn
;
3615 int saved_size
= cfun
->machine
->frame
.save_libcall_adjustment
;
3618 for (int regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
3619 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
3621 /* The save order is ra, s0, s1, s2 to s11. */
3622 if (regno
== RETURN_ADDR_REGNUM
)
3623 offset
= saved_size
- UNITS_PER_WORD
;
3624 else if (regno
== S0_REGNUM
)
3625 offset
= saved_size
- UNITS_PER_WORD
* 2;
3626 else if (regno
== S1_REGNUM
)
3627 offset
= saved_size
- UNITS_PER_WORD
* 3;
3629 offset
= saved_size
- ((regno
- S2_REGNUM
+ 4) * UNITS_PER_WORD
);
3631 reg
= gen_rtx_REG (SImode
, regno
);
3632 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
,
3636 insn
= gen_rtx_SET (mem
, reg
);
3637 dwarf
= alloc_reg_note (REG_CFA_OFFSET
, insn
, dwarf
);
3640 /* Debug info for adjust sp. */
3641 adjust_sp_rtx
= gen_add3_insn (stack_pointer_rtx
,
3642 stack_pointer_rtx
, GEN_INT (-saved_size
));
3643 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
, adjust_sp_rtx
,
3649 riscv_emit_stack_tie (void)
3651 if (Pmode
== SImode
)
3652 emit_insn (gen_stack_tiesi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
3654 emit_insn (gen_stack_tiedi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
3657 /* Expand the "prologue" pattern. */
3660 riscv_expand_prologue (void)
3662 struct riscv_frame_info
*frame
= &cfun
->machine
->frame
;
3663 HOST_WIDE_INT size
= frame
->total_size
;
3664 unsigned mask
= frame
->mask
;
3667 if (flag_stack_usage_info
)
3668 current_function_static_stack_size
= size
;
3670 if (cfun
->machine
->naked_p
)
3673 /* When optimizing for size, call a subroutine to save the registers. */
3674 if (riscv_use_save_libcall (frame
))
3676 rtx dwarf
= NULL_RTX
;
3677 dwarf
= riscv_adjust_libcall_cfi_prologue ();
3679 frame
->mask
= 0; /* Temporarily fib that we need not save GPRs. */
3680 size
-= frame
->save_libcall_adjustment
;
3681 insn
= emit_insn (gen_gpr_save (GEN_INT (mask
)));
3683 RTX_FRAME_RELATED_P (insn
) = 1;
3684 REG_NOTES (insn
) = dwarf
;
3687 /* Save the registers. */
3688 if ((frame
->mask
| frame
->fmask
) != 0)
3690 HOST_WIDE_INT step1
= MIN (size
, riscv_first_stack_step (frame
));
3692 insn
= gen_add3_insn (stack_pointer_rtx
,
3695 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
3697 riscv_for_each_saved_reg (size
, riscv_save_reg
);
3700 frame
->mask
= mask
; /* Undo the above fib. */
3702 /* Set up the frame pointer, if we're using one. */
3703 if (frame_pointer_needed
)
3705 insn
= gen_add3_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
,
3706 GEN_INT (frame
->hard_frame_pointer_offset
- size
));
3707 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
3709 riscv_emit_stack_tie ();
3712 /* Allocate the rest of the frame. */
3715 if (SMALL_OPERAND (-size
))
3717 insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
3719 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
3723 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode
), GEN_INT (-size
));
3724 emit_insn (gen_add3_insn (stack_pointer_rtx
,
3726 RISCV_PROLOGUE_TEMP (Pmode
)));
3728 /* Describe the effect of the previous instructions. */
3729 insn
= plus_constant (Pmode
, stack_pointer_rtx
, -size
);
3730 insn
= gen_rtx_SET (stack_pointer_rtx
, insn
);
3731 riscv_set_frame_expr (insn
);
3737 riscv_adjust_libcall_cfi_epilogue ()
3739 rtx dwarf
= NULL_RTX
;
3740 rtx adjust_sp_rtx
, reg
;
3741 int saved_size
= cfun
->machine
->frame
.save_libcall_adjustment
;
3743 /* Debug info for adjust sp. */
3744 adjust_sp_rtx
= gen_add3_insn (stack_pointer_rtx
,
3745 stack_pointer_rtx
, GEN_INT (saved_size
));
3746 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
, adjust_sp_rtx
,
3749 for (int regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
3750 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
3752 reg
= gen_rtx_REG (SImode
, regno
);
3753 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
3759 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
3763 riscv_expand_epilogue (bool sibcall_p
)
3765 /* Split the frame into two. STEP1 is the amount of stack we should
3766 deallocate before restoring the registers. STEP2 is the amount we
3767 should deallocate afterwards.
3769 Start off by assuming that no registers need to be restored. */
3770 struct riscv_frame_info
*frame
= &cfun
->machine
->frame
;
3771 unsigned mask
= frame
->mask
;
3772 HOST_WIDE_INT step1
= frame
->total_size
;
3773 HOST_WIDE_INT step2
= 0;
3774 bool use_restore_libcall
= !sibcall_p
&& riscv_use_save_libcall (frame
);
3775 rtx ra
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
3778 /* We need to add memory barrier to prevent read from deallocated stack. */
3779 bool need_barrier_p
= (get_frame_size ()
3780 + cfun
->machine
->frame
.arg_pointer_offset
) != 0;
3782 if (cfun
->machine
->naked_p
)
3784 gcc_assert (!sibcall_p
);
3786 emit_jump_insn (gen_return ());
3791 if (!sibcall_p
&& riscv_can_use_return_insn ())
3793 emit_jump_insn (gen_return ());
3797 /* Move past any dynamic stack allocations. */
3798 if (cfun
->calls_alloca
)
3800 /* Emit a barrier to prevent loads from a deallocated stack. */
3801 riscv_emit_stack_tie ();
3802 need_barrier_p
= false;
3804 rtx adjust
= GEN_INT (-frame
->hard_frame_pointer_offset
);
3805 if (!SMALL_OPERAND (INTVAL (adjust
)))
3807 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode
), adjust
);
3808 adjust
= RISCV_PROLOGUE_TEMP (Pmode
);
3812 gen_add3_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
,
3815 rtx dwarf
= NULL_RTX
;
3816 rtx cfa_adjust_value
= gen_rtx_PLUS (
3817 Pmode
, hard_frame_pointer_rtx
,
3818 GEN_INT (-frame
->hard_frame_pointer_offset
));
3819 rtx cfa_adjust_rtx
= gen_rtx_SET (stack_pointer_rtx
, cfa_adjust_value
);
3820 dwarf
= alloc_reg_note (REG_CFA_ADJUST_CFA
, cfa_adjust_rtx
, dwarf
);
3821 RTX_FRAME_RELATED_P (insn
) = 1;
3823 REG_NOTES (insn
) = dwarf
;
3826 /* If we need to restore registers, deallocate as much stack as
3827 possible in the second step without going out of range. */
3828 if ((frame
->mask
| frame
->fmask
) != 0)
3830 step2
= riscv_first_stack_step (frame
);
3834 /* Set TARGET to BASE + STEP1. */
3837 /* Emit a barrier to prevent loads from a deallocated stack. */
3838 riscv_emit_stack_tie ();
3839 need_barrier_p
= false;
3841 /* Get an rtx for STEP1 that we can add to BASE. */
3842 rtx adjust
= GEN_INT (step1
);
3843 if (!SMALL_OPERAND (step1
))
3845 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode
), adjust
);
3846 adjust
= RISCV_PROLOGUE_TEMP (Pmode
);
3850 gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
, adjust
));
3852 rtx dwarf
= NULL_RTX
;
3853 rtx cfa_adjust_rtx
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
3856 dwarf
= alloc_reg_note (REG_CFA_DEF_CFA
, cfa_adjust_rtx
, dwarf
);
3857 RTX_FRAME_RELATED_P (insn
) = 1;
3859 REG_NOTES (insn
) = dwarf
;
3862 if (use_restore_libcall
)
3863 frame
->mask
= 0; /* Temporarily fib that we need not save GPRs. */
3865 /* Restore the registers. */
3866 riscv_for_each_saved_reg (frame
->total_size
- step2
, riscv_restore_reg
);
3868 if (use_restore_libcall
)
3870 frame
->mask
= mask
; /* Undo the above fib. */
3871 gcc_assert (step2
>= frame
->save_libcall_adjustment
);
3872 step2
-= frame
->save_libcall_adjustment
;
3876 riscv_emit_stack_tie ();
3878 /* Deallocate the final bit of the frame. */
3881 insn
= emit_insn (gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
3884 rtx dwarf
= NULL_RTX
;
3885 rtx cfa_adjust_rtx
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
3887 dwarf
= alloc_reg_note (REG_CFA_DEF_CFA
, cfa_adjust_rtx
, dwarf
);
3888 RTX_FRAME_RELATED_P (insn
) = 1;
3890 REG_NOTES (insn
) = dwarf
;
3893 if (use_restore_libcall
)
3895 rtx dwarf
= riscv_adjust_libcall_cfi_epilogue ();
3896 insn
= emit_insn (gen_gpr_restore (GEN_INT (riscv_save_libcall_count (mask
))));
3897 RTX_FRAME_RELATED_P (insn
) = 1;
3898 REG_NOTES (insn
) = dwarf
;
3900 emit_jump_insn (gen_gpr_restore_return (ra
));
3904 /* Add in the __builtin_eh_return stack adjustment. */
3905 if (crtl
->calls_eh_return
)
3906 emit_insn (gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
3907 EH_RETURN_STACKADJ_RTX
));
3909 /* Return from interrupt. */
3910 if (cfun
->machine
->interrupt_handler_p
)
3911 emit_insn (gen_riscv_mret ());
3912 else if (!sibcall_p
)
3913 emit_jump_insn (gen_simple_return_internal (ra
));
3916 /* Implement EPILOGUE_USES. */
3919 riscv_epilogue_uses (unsigned int regno
)
3921 if (regno
== RETURN_ADDR_REGNUM
)
3924 if (epilogue_completed
&& cfun
->machine
->interrupt_handler_p
)
3926 /* An interrupt function restores temp regs, so we must indicate that
3927 they are live at function end. */
3928 if (df_regs_ever_live_p (regno
)
3929 || (!crtl
->is_leaf
&& call_used_regs
[regno
]))
3936 /* Return nonzero if this function is known to have a null epilogue.
3937 This allows the optimizer to omit jumps to jumps if no stack
3941 riscv_can_use_return_insn (void)
3943 return (reload_completed
&& cfun
->machine
->frame
.total_size
== 0
3944 && ! cfun
->machine
->interrupt_handler_p
);
3947 /* Implement TARGET_SECONDARY_MEMORY_NEEDED.
3949 When floating-point registers are wider than integer ones, moves between
3950 them must go through memory. */
3953 riscv_secondary_memory_needed (machine_mode mode
, reg_class_t class1
,
3956 return (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
3957 && (class1
== FP_REGS
) != (class2
== FP_REGS
));
3960 /* Implement TARGET_REGISTER_MOVE_COST. */
3963 riscv_register_move_cost (machine_mode mode
,
3964 reg_class_t from
, reg_class_t to
)
3966 return riscv_secondary_memory_needed (mode
, from
, to
) ? 8 : 2;
3969 /* Implement TARGET_HARD_REGNO_NREGS. */
3972 riscv_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
3974 if (FP_REG_P (regno
))
3975 return (GET_MODE_SIZE (mode
) + UNITS_PER_FP_REG
- 1) / UNITS_PER_FP_REG
;
3977 /* All other registers are word-sized. */
3978 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3981 /* Implement TARGET_HARD_REGNO_MODE_OK. */
3984 riscv_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
3986 unsigned int nregs
= riscv_hard_regno_nregs (regno
, mode
);
3988 if (GP_REG_P (regno
))
3990 if (!GP_REG_P (regno
+ nregs
- 1))
3993 else if (FP_REG_P (regno
))
3995 if (!FP_REG_P (regno
+ nregs
- 1))
3998 if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3999 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
4002 /* Only use callee-saved registers if a potential callee is guaranteed
4003 to spill the requisite width. */
4004 if (GET_MODE_UNIT_SIZE (mode
) > UNITS_PER_FP_REG
4005 || (!call_used_regs
[regno
]
4006 && GET_MODE_UNIT_SIZE (mode
) > UNITS_PER_FP_ARG
))
4012 /* Require same callee-savedness for all registers. */
4013 for (unsigned i
= 1; i
< nregs
; i
++)
4014 if (call_used_regs
[regno
] != call_used_regs
[regno
+ i
])
4020 /* Implement TARGET_MODES_TIEABLE_P.
4022 Don't allow floating-point modes to be tied, since type punning of
4023 single-precision and double-precision is implementation defined. */
4026 riscv_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
4028 return (mode1
== mode2
4029 || !(GET_MODE_CLASS (mode1
) == MODE_FLOAT
4030 && GET_MODE_CLASS (mode2
) == MODE_FLOAT
));
4033 /* Implement CLASS_MAX_NREGS. */
4035 static unsigned char
4036 riscv_class_max_nregs (reg_class_t rclass
, machine_mode mode
)
4038 if (reg_class_subset_p (FP_REGS
, rclass
))
4039 return riscv_hard_regno_nregs (FP_REG_FIRST
, mode
);
4041 if (reg_class_subset_p (GR_REGS
, rclass
))
4042 return riscv_hard_regno_nregs (GP_REG_FIRST
, mode
);
4047 /* Implement TARGET_MEMORY_MOVE_COST. */
4050 riscv_memory_move_cost (machine_mode mode
, reg_class_t rclass
, bool in
)
4052 return (tune_info
->memory_cost
4053 + memory_move_secondary_cost (mode
, rclass
, in
));
4056 /* Return the number of instructions that can be issued per cycle. */
4059 riscv_issue_rate (void)
4061 return tune_info
->issue_rate
;
4064 /* Implement TARGET_ASM_FILE_START. */
4067 riscv_file_start (void)
4069 default_file_start ();
4071 /* Instruct GAS to generate position-[in]dependent code. */
4072 fprintf (asm_out_file
, "\t.option %spic\n", (flag_pic
? "" : "no"));
4074 /* If the user specifies "-mno-relax" on the command line then disable linker
4075 relaxation in the assembler. */
4077 fprintf (asm_out_file
, "\t.option norelax\n");
4080 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
4081 in order to avoid duplicating too much logic from elsewhere. */
4084 riscv_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
4085 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
4088 rtx this_rtx
, temp1
, temp2
, fnaddr
;
4091 /* Pretend to be a post-reload pass while generating rtl. */
4092 reload_completed
= 1;
4094 /* Mark the end of the (empty) prologue. */
4095 emit_note (NOTE_INSN_PROLOGUE_END
);
4097 /* Determine if we can use a sibcall to call FUNCTION directly. */
4098 fnaddr
= gen_rtx_MEM (FUNCTION_MODE
, XEXP (DECL_RTL (function
), 0));
4100 /* We need two temporary registers in some cases. */
4101 temp1
= gen_rtx_REG (Pmode
, RISCV_PROLOGUE_TEMP_REGNUM
);
4102 temp2
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
4104 /* Find out which register contains the "this" pointer. */
4105 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
4106 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
4108 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
4110 /* Add DELTA to THIS_RTX. */
4113 rtx offset
= GEN_INT (delta
);
4114 if (!SMALL_OPERAND (delta
))
4116 riscv_emit_move (temp1
, offset
);
4119 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
4122 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
4123 if (vcall_offset
!= 0)
4127 /* Set TEMP1 to *THIS_RTX. */
4128 riscv_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
4130 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
4131 addr
= riscv_add_offset (temp2
, temp1
, vcall_offset
);
4133 /* Load the offset and add it to THIS_RTX. */
4134 riscv_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
4135 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
4138 /* Jump to the target function. */
4139 insn
= emit_call_insn (gen_sibcall (fnaddr
, const0_rtx
, NULL
, const0_rtx
));
4140 SIBLING_CALL_P (insn
) = 1;
4142 /* Run just enough of rest_of_compilation. This sequence was
4143 "borrowed" from alpha.c. */
4144 insn
= get_insns ();
4145 split_all_insns_noflow ();
4146 shorten_branches (insn
);
4147 final_start_function (insn
, file
, 1);
4148 final (insn
, file
, 1);
4149 final_end_function ();
4151 /* Clean up the vars set above. Note that final_end_function resets
4152 the global pointer for us. */
4153 reload_completed
= 0;
4156 /* Allocate a chunk of memory for per-function machine-dependent data. */
4158 static struct machine_function
*
4159 riscv_init_machine_status (void)
4161 return ggc_cleared_alloc
<machine_function
> ();
4164 /* Implement TARGET_OPTION_OVERRIDE. */
4167 riscv_option_override (void)
4169 const struct riscv_cpu_info
*cpu
;
4171 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4172 SUBTARGET_OVERRIDE_OPTIONS
;
4175 flag_pcc_struct_return
= 0;
4180 /* The presence of the M extension implies that division instructions
4181 are present, so include them unless explicitly disabled. */
4182 if (TARGET_MUL
&& (target_flags_explicit
& MASK_DIV
) == 0)
4183 target_flags
|= MASK_DIV
;
4184 else if (!TARGET_MUL
&& TARGET_DIV
)
4185 error ("-mdiv requires -march to subsume the %<M%> extension");
4187 /* Likewise floating-point division and square root. */
4188 if (TARGET_HARD_FLOAT
&& (target_flags_explicit
& MASK_FDIV
) == 0)
4189 target_flags
|= MASK_FDIV
;
4191 /* Handle -mtune. */
4192 cpu
= riscv_parse_cpu (riscv_tune_string
? riscv_tune_string
:
4193 RISCV_TUNE_STRING_DEFAULT
);
4194 tune_info
= optimize_size
? &optimize_size_tune_info
: cpu
->tune_info
;
4196 /* Use -mtune's setting for slow_unaligned_access, even when optimizing
4197 for size. For architectures that trap and emulate unaligned accesses,
4198 the performance cost is too great, even for -Os. Similarly, if
4199 -m[no-]strict-align is left unspecified, heed -mtune's advice. */
4200 riscv_slow_unaligned_access_p
= (cpu
->tune_info
->slow_unaligned_access
4201 || TARGET_STRICT_ALIGN
);
4202 if ((target_flags_explicit
& MASK_STRICT_ALIGN
) == 0
4203 && cpu
->tune_info
->slow_unaligned_access
)
4204 target_flags
|= MASK_STRICT_ALIGN
;
4206 /* If the user hasn't specified a branch cost, use the processor's
4208 if (riscv_branch_cost
== 0)
4209 riscv_branch_cost
= tune_info
->branch_cost
;
4211 /* Function to allocate machine-dependent function status. */
4212 init_machine_status
= &riscv_init_machine_status
;
4215 riscv_cmodel
= CM_PIC
;
4217 /* We get better code with explicit relocs for CM_MEDLOW, but
4218 worse code for the others (for now). Pick the best default. */
4219 if ((target_flags_explicit
& MASK_EXPLICIT_RELOCS
) == 0)
4220 if (riscv_cmodel
== CM_MEDLOW
)
4221 target_flags
|= MASK_EXPLICIT_RELOCS
;
4223 /* Require that the ISA supports the requested floating-point ABI. */
4224 if (UNITS_PER_FP_ARG
> (TARGET_HARD_FLOAT
? UNITS_PER_FP_REG
: 0))
4225 error ("requested ABI requires -march to subsume the %qc extension",
4226 UNITS_PER_FP_ARG
> 8 ? 'Q' : (UNITS_PER_FP_ARG
> 4 ? 'D' : 'F'));
4228 if (TARGET_RVE
&& riscv_abi
!= ABI_ILP32E
)
4229 error ("rv32e requires ilp32e ABI");
4231 /* We do not yet support ILP32 on RV64. */
4232 if (BITS_PER_WORD
!= POINTER_SIZE
)
4233 error ("ABI requires -march=rv%d", POINTER_SIZE
);
4235 /* Validate -mpreferred-stack-boundary= value. */
4236 riscv_stack_boundary
= ABI_STACK_BOUNDARY
;
4237 if (riscv_preferred_stack_boundary_arg
)
4239 int min
= ctz_hwi (STACK_BOUNDARY
/ 8);
4242 if (!IN_RANGE (riscv_preferred_stack_boundary_arg
, min
, max
))
4243 error ("-mpreferred-stack-boundary=%d must be between %d and %d",
4244 riscv_preferred_stack_boundary_arg
, min
, max
);
4246 riscv_stack_boundary
= 8 << riscv_preferred_stack_boundary_arg
;
4250 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
4253 riscv_conditional_register_usage (void)
4255 /* We have only x0~x15 on RV32E. */
4258 for (int r
= 16; r
<= 31; r
++)
4262 if (riscv_abi
== ABI_ILP32E
)
4264 for (int r
= 16; r
<= 31; r
++)
4265 call_used_regs
[r
] = 1;
4268 if (!TARGET_HARD_FLOAT
)
4270 for (int regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
4271 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
4274 /* In the soft-float ABI, there are no callee-saved FP registers. */
4275 if (UNITS_PER_FP_ARG
== 0)
4277 for (int regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
4278 call_used_regs
[regno
] = 1;
4282 /* Return a register priority for hard reg REGNO. */
4285 riscv_register_priority (int regno
)
4287 /* Favor x8-x15/f8-f15 to improve the odds of RVC instruction selection. */
4288 if (TARGET_RVC
&& (IN_RANGE (regno
, GP_REG_FIRST
+ 8, GP_REG_FIRST
+ 15)
4289 || IN_RANGE (regno
, FP_REG_FIRST
+ 8, FP_REG_FIRST
+ 15)))
4295 /* Implement TARGET_TRAMPOLINE_INIT. */
4298 riscv_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
4300 rtx addr
, end_addr
, mem
;
4301 uint32_t trampoline
[4];
4303 HOST_WIDE_INT static_chain_offset
, target_function_offset
;
4305 /* Work out the offsets of the pointers from the start of the
4307 gcc_assert (ARRAY_SIZE (trampoline
) * 4 == TRAMPOLINE_CODE_SIZE
);
4309 /* Get pointers to the beginning and end of the code block. */
4310 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
4311 end_addr
= riscv_force_binary (Pmode
, PLUS
, addr
,
4312 GEN_INT (TRAMPOLINE_CODE_SIZE
));
4315 if (Pmode
== SImode
)
4317 chain_value
= force_reg (Pmode
, chain_value
);
4319 rtx target_function
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
4320 /* lui t2, hi(chain)
4322 addi t2, t2, lo(chain)
4325 unsigned HOST_WIDE_INT lui_hi_chain_code
, lui_hi_func_code
;
4326 unsigned HOST_WIDE_INT lo_chain_code
, lo_func_code
;
4328 rtx uimm_mask
= force_reg (SImode
, gen_int_mode (-IMM_REACH
, SImode
));
4331 rtx imm12_mask
= gen_reg_rtx (SImode
);
4332 emit_insn (gen_one_cmplsi2 (imm12_mask
, uimm_mask
));
4334 rtx fixup_value
= force_reg (SImode
, gen_int_mode (IMM_REACH
/2, SImode
));
4336 /* Gen lui t2, hi(chain). */
4337 rtx hi_chain
= riscv_force_binary (SImode
, PLUS
, chain_value
,
4339 hi_chain
= riscv_force_binary (SImode
, AND
, hi_chain
,
4341 lui_hi_chain_code
= OPCODE_LUI
| (STATIC_CHAIN_REGNUM
<< SHIFT_RD
);
4342 rtx lui_hi_chain
= riscv_force_binary (SImode
, IOR
, hi_chain
,
4343 gen_int_mode (lui_hi_chain_code
, SImode
));
4345 mem
= adjust_address (m_tramp
, SImode
, 0);
4346 riscv_emit_move (mem
, lui_hi_chain
);
4348 /* Gen lui t1, hi(func). */
4349 rtx hi_func
= riscv_force_binary (SImode
, PLUS
, target_function
,
4351 hi_func
= riscv_force_binary (SImode
, AND
, hi_func
,
4353 lui_hi_func_code
= OPCODE_LUI
| (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RD
);
4354 rtx lui_hi_func
= riscv_force_binary (SImode
, IOR
, hi_func
,
4355 gen_int_mode (lui_hi_func_code
, SImode
));
4357 mem
= adjust_address (m_tramp
, SImode
, 1 * GET_MODE_SIZE (SImode
));
4358 riscv_emit_move (mem
, lui_hi_func
);
4360 /* Gen addi t2, t2, lo(chain). */
4361 rtx lo_chain
= riscv_force_binary (SImode
, AND
, chain_value
,
4363 lo_chain
= riscv_force_binary (SImode
, ASHIFT
, lo_chain
, GEN_INT (20));
4365 lo_chain_code
= OPCODE_ADDI
4366 | (STATIC_CHAIN_REGNUM
<< SHIFT_RD
)
4367 | (STATIC_CHAIN_REGNUM
<< SHIFT_RS1
);
4369 rtx addi_lo_chain
= riscv_force_binary (SImode
, IOR
, lo_chain
,
4370 force_reg (SImode
, GEN_INT (lo_chain_code
)));
4372 mem
= adjust_address (m_tramp
, SImode
, 2 * GET_MODE_SIZE (SImode
));
4373 riscv_emit_move (mem
, addi_lo_chain
);
4375 /* Gen jr r1, lo(func). */
4376 rtx lo_func
= riscv_force_binary (SImode
, AND
, target_function
,
4378 lo_func
= riscv_force_binary (SImode
, ASHIFT
, lo_func
, GEN_INT (20));
4380 lo_func_code
= OPCODE_JALR
| (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RS1
);
4382 rtx jr_lo_func
= riscv_force_binary (SImode
, IOR
, lo_func
,
4383 force_reg (SImode
, GEN_INT (lo_func_code
)));
4385 mem
= adjust_address (m_tramp
, SImode
, 3 * GET_MODE_SIZE (SImode
));
4386 riscv_emit_move (mem
, jr_lo_func
);
4390 static_chain_offset
= TRAMPOLINE_CODE_SIZE
;
4391 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
4394 l[wd] t1, target_function_offset(t2)
4395 l[wd] t2, static_chain_offset(t2)
4398 trampoline
[0] = OPCODE_AUIPC
| (STATIC_CHAIN_REGNUM
<< SHIFT_RD
);
4399 trampoline
[1] = (Pmode
== DImode
? OPCODE_LD
: OPCODE_LW
)
4400 | (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RD
)
4401 | (STATIC_CHAIN_REGNUM
<< SHIFT_RS1
)
4402 | (target_function_offset
<< SHIFT_IMM
);
4403 trampoline
[2] = (Pmode
== DImode
? OPCODE_LD
: OPCODE_LW
)
4404 | (STATIC_CHAIN_REGNUM
<< SHIFT_RD
)
4405 | (STATIC_CHAIN_REGNUM
<< SHIFT_RS1
)
4406 | (static_chain_offset
<< SHIFT_IMM
);
4407 trampoline
[3] = OPCODE_JALR
| (RISCV_PROLOGUE_TEMP_REGNUM
<< SHIFT_RS1
);
4409 /* Copy the trampoline code. */
4410 for (i
= 0; i
< ARRAY_SIZE (trampoline
); i
++)
4412 mem
= adjust_address (m_tramp
, SImode
, i
* GET_MODE_SIZE (SImode
));
4413 riscv_emit_move (mem
, gen_int_mode (trampoline
[i
], SImode
));
4416 /* Set up the static chain pointer field. */
4417 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
4418 riscv_emit_move (mem
, chain_value
);
4420 /* Set up the target function field. */
4421 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
4422 riscv_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
4425 /* Flush the code part of the trampoline. */
4426 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
4427 emit_insn (gen_clear_cache (addr
, end_addr
));
4430 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
4433 riscv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
4434 tree exp ATTRIBUTE_UNUSED
)
4436 /* Don't use sibcalls when use save-restore routine. */
4437 if (TARGET_SAVE_RESTORE
)
4440 /* Don't use sibcall for naked functions. */
4441 if (cfun
->machine
->naked_p
)
4444 /* Don't use sibcall for interrupt functions. */
4445 if (cfun
->machine
->interrupt_handler_p
)
4451 /* Implement `TARGET_SET_CURRENT_FUNCTION'. */
4452 /* Sanity cheching for above function attributes. */
4454 riscv_set_current_function (tree decl
)
4456 if (decl
== NULL_TREE
4457 || current_function_decl
== NULL_TREE
4458 || current_function_decl
== error_mark_node
4460 || cfun
->machine
->attributes_checked_p
)
4463 cfun
->machine
->naked_p
= riscv_naked_function_p (decl
);
4464 cfun
->machine
->interrupt_handler_p
4465 = riscv_interrupt_type_p (TREE_TYPE (decl
));
4467 if (cfun
->machine
->naked_p
&& cfun
->machine
->interrupt_handler_p
)
4468 error ("function attributes %qs and %qs are mutually exclusive",
4469 "interrupt", "naked");
4471 if (cfun
->machine
->interrupt_handler_p
)
4473 tree args
= TYPE_ARG_TYPES (TREE_TYPE (decl
));
4474 tree ret
= TREE_TYPE (TREE_TYPE (decl
));
4476 if (TREE_CODE (ret
) != VOID_TYPE
)
4477 error ("%qs function cannot return a value", "interrupt");
4479 if (args
&& TREE_CODE (TREE_VALUE (args
)) != VOID_TYPE
)
4480 error ("%qs function cannot have arguments", "interrupt");
4483 /* Don't print the above diagnostics more than once. */
4484 cfun
->machine
->attributes_checked_p
= 1;
4487 /* Implement TARGET_CANNOT_COPY_INSN_P. */
4490 riscv_cannot_copy_insn_p (rtx_insn
*insn
)
4492 return recog_memoized (insn
) >= 0 && get_attr_cannot_copy (insn
);
4495 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. */
4498 riscv_slow_unaligned_access (machine_mode
, unsigned int)
4500 return riscv_slow_unaligned_access_p
;
4503 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
4506 riscv_can_change_mode_class (machine_mode
, machine_mode
, reg_class_t rclass
)
4508 return !reg_classes_intersect_p (FP_REGS
, rclass
);
4512 /* Implement TARGET_CONSTANT_ALIGNMENT. */
4514 static HOST_WIDE_INT
4515 riscv_constant_alignment (const_tree exp
, HOST_WIDE_INT align
)
4517 if (TREE_CODE (exp
) == STRING_CST
|| TREE_CODE (exp
) == CONSTRUCTOR
)
4518 return MAX (align
, BITS_PER_WORD
);
4522 /* Initialize the GCC target structure. */
4523 #undef TARGET_ASM_ALIGNED_HI_OP
4524 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
4525 #undef TARGET_ASM_ALIGNED_SI_OP
4526 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
4527 #undef TARGET_ASM_ALIGNED_DI_OP
4528 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
4530 #undef TARGET_OPTION_OVERRIDE
4531 #define TARGET_OPTION_OVERRIDE riscv_option_override
4533 #undef TARGET_LEGITIMIZE_ADDRESS
4534 #define TARGET_LEGITIMIZE_ADDRESS riscv_legitimize_address
4536 #undef TARGET_SCHED_ISSUE_RATE
4537 #define TARGET_SCHED_ISSUE_RATE riscv_issue_rate
4539 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
4540 #define TARGET_FUNCTION_OK_FOR_SIBCALL riscv_function_ok_for_sibcall
4542 #undef TARGET_SET_CURRENT_FUNCTION
4543 #define TARGET_SET_CURRENT_FUNCTION riscv_set_current_function
4545 #undef TARGET_REGISTER_MOVE_COST
4546 #define TARGET_REGISTER_MOVE_COST riscv_register_move_cost
4547 #undef TARGET_MEMORY_MOVE_COST
4548 #define TARGET_MEMORY_MOVE_COST riscv_memory_move_cost
4549 #undef TARGET_RTX_COSTS
4550 #define TARGET_RTX_COSTS riscv_rtx_costs
4551 #undef TARGET_ADDRESS_COST
4552 #define TARGET_ADDRESS_COST riscv_address_cost
4554 #undef TARGET_ASM_FILE_START
4555 #define TARGET_ASM_FILE_START riscv_file_start
4556 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
4557 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
4559 #undef TARGET_EXPAND_BUILTIN_VA_START
4560 #define TARGET_EXPAND_BUILTIN_VA_START riscv_va_start
4562 #undef TARGET_PROMOTE_FUNCTION_MODE
4563 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
4565 #undef TARGET_RETURN_IN_MEMORY
4566 #define TARGET_RETURN_IN_MEMORY riscv_return_in_memory
4568 #undef TARGET_ASM_OUTPUT_MI_THUNK
4569 #define TARGET_ASM_OUTPUT_MI_THUNK riscv_output_mi_thunk
4570 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
4571 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
4573 #undef TARGET_PRINT_OPERAND
4574 #define TARGET_PRINT_OPERAND riscv_print_operand
4575 #undef TARGET_PRINT_OPERAND_ADDRESS
4576 #define TARGET_PRINT_OPERAND_ADDRESS riscv_print_operand_address
4578 #undef TARGET_SETUP_INCOMING_VARARGS
4579 #define TARGET_SETUP_INCOMING_VARARGS riscv_setup_incoming_varargs
4580 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
4581 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS riscv_allocate_stack_slots_for_args
4582 #undef TARGET_STRICT_ARGUMENT_NAMING
4583 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
4584 #undef TARGET_MUST_PASS_IN_STACK
4585 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
4586 #undef TARGET_PASS_BY_REFERENCE
4587 #define TARGET_PASS_BY_REFERENCE riscv_pass_by_reference
4588 #undef TARGET_ARG_PARTIAL_BYTES
4589 #define TARGET_ARG_PARTIAL_BYTES riscv_arg_partial_bytes
4590 #undef TARGET_FUNCTION_ARG
4591 #define TARGET_FUNCTION_ARG riscv_function_arg
4592 #undef TARGET_FUNCTION_ARG_ADVANCE
4593 #define TARGET_FUNCTION_ARG_ADVANCE riscv_function_arg_advance
4594 #undef TARGET_FUNCTION_ARG_BOUNDARY
4595 #define TARGET_FUNCTION_ARG_BOUNDARY riscv_function_arg_boundary
4597 /* The generic ELF target does not always have TLS support. */
4599 #undef TARGET_HAVE_TLS
4600 #define TARGET_HAVE_TLS true
4603 #undef TARGET_CANNOT_FORCE_CONST_MEM
4604 #define TARGET_CANNOT_FORCE_CONST_MEM riscv_cannot_force_const_mem
4606 #undef TARGET_LEGITIMATE_CONSTANT_P
4607 #define TARGET_LEGITIMATE_CONSTANT_P riscv_legitimate_constant_p
4609 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
4610 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
4612 #undef TARGET_LEGITIMATE_ADDRESS_P
4613 #define TARGET_LEGITIMATE_ADDRESS_P riscv_legitimate_address_p
4615 #undef TARGET_CAN_ELIMINATE
4616 #define TARGET_CAN_ELIMINATE riscv_can_eliminate
4618 #undef TARGET_CONDITIONAL_REGISTER_USAGE
4619 #define TARGET_CONDITIONAL_REGISTER_USAGE riscv_conditional_register_usage
4621 #undef TARGET_CLASS_MAX_NREGS
4622 #define TARGET_CLASS_MAX_NREGS riscv_class_max_nregs
4624 #undef TARGET_TRAMPOLINE_INIT
4625 #define TARGET_TRAMPOLINE_INIT riscv_trampoline_init
4627 #undef TARGET_IN_SMALL_DATA_P
4628 #define TARGET_IN_SMALL_DATA_P riscv_in_small_data_p
4630 #undef TARGET_HAVE_SRODATA_SECTION
4631 #define TARGET_HAVE_SRODATA_SECTION true
4633 #undef TARGET_ASM_SELECT_SECTION
4634 #define TARGET_ASM_SELECT_SECTION riscv_select_section
4636 #undef TARGET_ASM_SELECT_RTX_SECTION
4637 #define TARGET_ASM_SELECT_RTX_SECTION riscv_elf_select_rtx_section
4639 #undef TARGET_MIN_ANCHOR_OFFSET
4640 #define TARGET_MIN_ANCHOR_OFFSET (-IMM_REACH/2)
4642 #undef TARGET_MAX_ANCHOR_OFFSET
4643 #define TARGET_MAX_ANCHOR_OFFSET (IMM_REACH/2-1)
4645 #undef TARGET_REGISTER_PRIORITY
4646 #define TARGET_REGISTER_PRIORITY riscv_register_priority
4648 #undef TARGET_CANNOT_COPY_INSN_P
4649 #define TARGET_CANNOT_COPY_INSN_P riscv_cannot_copy_insn_p
4651 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
4652 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV riscv_atomic_assign_expand_fenv
4654 #undef TARGET_INIT_BUILTINS
4655 #define TARGET_INIT_BUILTINS riscv_init_builtins
4657 #undef TARGET_BUILTIN_DECL
4658 #define TARGET_BUILTIN_DECL riscv_builtin_decl
4660 #undef TARGET_EXPAND_BUILTIN
4661 #define TARGET_EXPAND_BUILTIN riscv_expand_builtin
4663 #undef TARGET_HARD_REGNO_NREGS
4664 #define TARGET_HARD_REGNO_NREGS riscv_hard_regno_nregs
4665 #undef TARGET_HARD_REGNO_MODE_OK
4666 #define TARGET_HARD_REGNO_MODE_OK riscv_hard_regno_mode_ok
4668 #undef TARGET_MODES_TIEABLE_P
4669 #define TARGET_MODES_TIEABLE_P riscv_modes_tieable_p
4671 #undef TARGET_SLOW_UNALIGNED_ACCESS
4672 #define TARGET_SLOW_UNALIGNED_ACCESS riscv_slow_unaligned_access
4674 #undef TARGET_SECONDARY_MEMORY_NEEDED
4675 #define TARGET_SECONDARY_MEMORY_NEEDED riscv_secondary_memory_needed
4677 #undef TARGET_CAN_CHANGE_MODE_CLASS
4678 #define TARGET_CAN_CHANGE_MODE_CLASS riscv_can_change_mode_class
4680 #undef TARGET_CONSTANT_ALIGNMENT
4681 #define TARGET_CONSTANT_ALIGNMENT riscv_constant_alignment
4683 #undef TARGET_ATTRIBUTE_TABLE
4684 #define TARGET_ATTRIBUTE_TABLE riscv_attribute_table
4686 #undef TARGET_WARN_FUNC_RETURN
4687 #define TARGET_WARN_FUNC_RETURN riscv_warn_func_return
4689 struct gcc_target targetm
= TARGET_INITIALIZER
;
4691 #include "gt-riscv.h"