1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
37 (UNSPEC_UMK_LOAD_CIW 9)
45 (UNSPEC_TLSGD_CALL 15)
46 (UNSPEC_TLSLDM_CALL 16)
68 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
69 (UNSPECV_LONGJMP 3) ; builtin_longjmp
71 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
73 (UNSPECV_EHR 7) ; exception_receiver
77 (UNSPECV_PLDGP2 11) ; prologue ldgp
80 (UNSPECV_SETJMPR_ER 14) ; builtin_setjmp_receiver fragment
83 ;; Where necessary, the suffixes _le and _be are used to distinguish between
84 ;; little-endian and big-endian patterns.
86 ;; Note that the Unicos/Mk assembler does not support the following
87 ;; opcodes: mov, fmov, nop, fnop, unop.
89 ;; Processor type -- this attribute must exactly match the processor_type
90 ;; enumeration in alpha.h.
92 (define_attr "cpu" "ev4,ev5,ev6"
93 (const (symbol_ref "alpha_cpu")))
95 ;; Define an insn type attribute. This is used in function unit delay
96 ;; computations, among other purposes. For the most part, we use the names
97 ;; defined in the EV4 documentation, but add a few that we have to know about
101 "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov,
102 icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
103 (const_string "iadd"))
105 ;; Describe a user's asm statement.
106 (define_asm_attributes
107 [(set_attr "type" "multi")])
109 ;; Define the operand size an insn operates on. Used primarily by mul
110 ;; and div operations that have size dependent timings.
112 (define_attr "opsize" "si,di,udi"
115 ;; The TRAP attribute marks instructions that may generate traps
116 ;; (which are imprecise and may need a trapb if software completion
119 (define_attr "trap" "no,yes"
122 ;; The ROUND_SUFFIX attribute marks which instructions require a
123 ;; rounding-mode suffix. The value NONE indicates no suffix,
124 ;; the value NORMAL indicates a suffix controlled by alpha_fprm.
126 (define_attr "round_suffix" "none,normal,c"
127 (const_string "none"))
129 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
131 ;; SU accepts only /su (cmpt et al)
132 ;; SUI accepts only /sui (cvtqt and cvtqs)
133 ;; V_SV accepts /v and /sv (cvtql only)
134 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
135 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
137 ;; The actual suffix emitted is controlled by alpha_fptm.
139 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
140 (const_string "none"))
142 ;; The length of an instruction sequence in bytes.
144 (define_attr "length" ""
147 ;; The USEGP attribute marks instructions that have relocations that use
150 (define_attr "usegp" "no,yes"
151 (cond [(eq_attr "type" "ldsym,jsr")
153 (eq_attr "type" "ild,fld,ist,fst")
154 (symbol_ref "alpha_find_lo_sum_using_gp(insn)")
156 (const_string "no")))
158 ;; The CANNOT_COPY attribute marks instructions with relocations that
159 ;; cannot easily be duplicated. This includes insns with gpdisp relocs
160 ;; since they have to stay in 1-1 correspondence with one another. This
161 ;; also includes jsr insns, since they must stay in correspondence with
162 ;; the immediately following gpdisp instructions.
164 (define_attr "cannot_copy" "false,true"
165 (const_string "false"))
167 ;; Include scheduling descriptions.
174 ;; Include predicate definitions
176 (include "predicates.md")
179 ;; First define the arithmetic insns. Note that the 32-bit forms also
182 ;; Handle 32-64 bit extension from memory to a floating point register
183 ;; specially, since this occurs frequently in int->double conversions.
185 ;; Note that while we must retain the =f case in the insn for reload's
186 ;; benefit, it should be eliminated after reload, so we should never emit
187 ;; code for that case. But we don't reject the possibility.
189 (define_expand "extendsidi2"
190 [(set (match_operand:DI 0 "register_operand" "")
191 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
195 (define_insn "*cvtlq"
196 [(set (match_operand:DI 0 "register_operand" "=f")
197 (unspec:DI [(match_operand:SF 1 "reg_or_0_operand" "fG")]
201 [(set_attr "type" "fadd")])
203 (define_insn "*extendsidi2_1"
204 [(set (match_operand:DI 0 "register_operand" "=r,r,!*f")
206 (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))]
211 lds %0,%1\;cvtlq %0,%0"
212 [(set_attr "type" "iadd,ild,fld")
213 (set_attr "length" "*,*,8")])
216 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
217 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
219 [(set (match_dup 2) (match_dup 1))
220 (set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))]
222 operands[1] = adjust_address (operands[1], SFmode, 0);
223 operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0]));
226 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
227 ;; reload when converting fp->int.
230 [(set (match_operand:SI 0 "hard_int_register_operand" "")
231 (match_operand:SI 1 "memory_operand" ""))
232 (set (match_operand:DI 2 "hard_int_register_operand" "")
233 (sign_extend:DI (match_dup 0)))]
234 "true_regnum (operands[0]) == true_regnum (operands[2])
235 || peep2_reg_dead_p (2, operands[0])"
237 (sign_extend:DI (match_dup 1)))]
240 ;; Don't say we have addsi3 if optimizing. This generates better code. We
241 ;; have the anonymous addsi3 pattern below in case combine wants to make it.
242 (define_expand "addsi3"
243 [(set (match_operand:SI 0 "register_operand" "")
244 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
245 (match_operand:SI 2 "add_operand" "")))]
249 (define_insn "*addsi_internal"
250 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
251 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
252 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
261 [(set (match_operand:SI 0 "register_operand" "")
262 (plus:SI (match_operand:SI 1 "register_operand" "")
263 (match_operand:SI 2 "const_int_operand" "")))]
264 "! add_operand (operands[2], SImode)"
265 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
266 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
268 HOST_WIDE_INT val = INTVAL (operands[2]);
269 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
270 HOST_WIDE_INT rest = val - low;
272 operands[3] = GEN_INT (rest);
273 operands[4] = GEN_INT (low);
276 (define_insn "*addsi_se"
277 [(set (match_operand:DI 0 "register_operand" "=r,r")
279 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
280 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
286 (define_insn "*addsi_se2"
287 [(set (match_operand:DI 0 "register_operand" "=r,r")
289 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
290 (match_operand:DI 2 "sext_add_operand" "rI,O"))
298 [(set (match_operand:DI 0 "register_operand" "")
300 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
301 (match_operand:SI 2 "const_int_operand" ""))))
302 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
303 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
304 && INTVAL (operands[2]) % 4 == 0"
305 [(set (match_dup 3) (match_dup 4))
306 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
310 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
316 operands[4] = GEN_INT (val);
317 operands[5] = GEN_INT (mult);
321 [(set (match_operand:DI 0 "register_operand" "")
323 (plus:SI (match_operator:SI 1 "comparison_operator"
324 [(match_operand 2 "" "")
325 (match_operand 3 "" "")])
326 (match_operand:SI 4 "add_operand" ""))))
327 (clobber (match_operand:DI 5 "register_operand" ""))]
329 [(set (match_dup 5) (match_dup 6))
330 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
332 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
333 operands[2], operands[3]);
334 operands[7] = gen_lowpart (SImode, operands[5]);
337 (define_insn "addvsi3"
338 [(set (match_operand:SI 0 "register_operand" "=r,r")
339 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
340 (match_operand:SI 2 "sext_add_operand" "rI,O")))
341 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
342 (sign_extend:DI (match_dup 2)))
343 (sign_extend:DI (plus:SI (match_dup 1)
351 (define_expand "adddi3"
352 [(set (match_operand:DI 0 "register_operand" "")
353 (plus:DI (match_operand:DI 1 "register_operand" "")
354 (match_operand:DI 2 "add_operand" "")))]
358 (define_insn "*adddi_er_lo16_dtp"
359 [(set (match_operand:DI 0 "register_operand" "=r")
360 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
361 (match_operand:DI 2 "dtp16_symbolic_operand" "")))]
363 "lda %0,%2(%1)\t\t!dtprel")
365 (define_insn "*adddi_er_hi32_dtp"
366 [(set (match_operand:DI 0 "register_operand" "=r")
367 (plus:DI (match_operand:DI 1 "register_operand" "r")
368 (high:DI (match_operand:DI 2 "dtp32_symbolic_operand" ""))))]
370 "ldah %0,%2(%1)\t\t!dtprelhi")
372 (define_insn "*adddi_er_lo32_dtp"
373 [(set (match_operand:DI 0 "register_operand" "=r")
374 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
375 (match_operand:DI 2 "dtp32_symbolic_operand" "")))]
377 "lda %0,%2(%1)\t\t!dtprello")
379 (define_insn "*adddi_er_lo16_tp"
380 [(set (match_operand:DI 0 "register_operand" "=r")
381 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
382 (match_operand:DI 2 "tp16_symbolic_operand" "")))]
384 "lda %0,%2(%1)\t\t!tprel")
386 (define_insn "*adddi_er_hi32_tp"
387 [(set (match_operand:DI 0 "register_operand" "=r")
388 (plus:DI (match_operand:DI 1 "register_operand" "r")
389 (high:DI (match_operand:DI 2 "tp32_symbolic_operand" ""))))]
391 "ldah %0,%2(%1)\t\t!tprelhi")
393 (define_insn "*adddi_er_lo32_tp"
394 [(set (match_operand:DI 0 "register_operand" "=r")
395 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
396 (match_operand:DI 2 "tp32_symbolic_operand" "")))]
398 "lda %0,%2(%1)\t\t!tprello")
400 (define_insn "*adddi_er_high_l"
401 [(set (match_operand:DI 0 "register_operand" "=r")
402 (plus:DI (match_operand:DI 1 "register_operand" "r")
403 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
404 "TARGET_EXPLICIT_RELOCS && reload_completed"
405 "ldah %0,%2(%1)\t\t!gprelhigh"
406 [(set_attr "usegp" "yes")])
409 [(set (match_operand:DI 0 "register_operand" "")
410 (high:DI (match_operand:DI 1 "local_symbolic_operand" "")))]
411 "TARGET_EXPLICIT_RELOCS && reload_completed"
413 (plus:DI (match_dup 2) (high:DI (match_dup 1))))]
414 "operands[2] = pic_offset_table_rtx;")
416 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
417 ;; With complications like
419 ;; The NT stack unwind code can't handle a subq to adjust the stack
420 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
421 ;; the exception handling code will loop if a subq is used and an
424 ;; The 19980616 change to emit prologues as RTL also confused some
425 ;; versions of GDB, which also interprets prologues. This has been
426 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
429 ;; and the fact that the three insns schedule exactly the same, it's
430 ;; just not worth the effort.
432 (define_insn "*adddi_internal"
433 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
434 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
435 (match_operand:DI 2 "add_operand" "r,K,L")))]
442 ;; ??? Allow large constants when basing off the frame pointer or some
443 ;; virtual register that may eliminate to the frame pointer. This is
444 ;; done because register elimination offsets will change the hi/lo split,
445 ;; and if we split before reload, we will require additional instructions.
447 (define_insn "*adddi_fp_hack"
448 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
449 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r,r,r")
450 (match_operand:DI 2 "const_int_operand" "K,L,n")))]
451 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
452 && INTVAL (operands[2]) >= 0
453 /* This is the largest constant an lda+ldah pair can add, minus
454 an upper bound on the displacement between SP and AP during
455 register elimination. See INITIAL_ELIMINATION_OFFSET. */
456 && INTVAL (operands[2])
458 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
459 - ALPHA_ROUND(current_function_outgoing_args_size)
460 - (ALPHA_ROUND (get_frame_size ()
461 + max_reg_num () * UNITS_PER_WORD
462 + current_function_pretend_args_size)
463 - current_function_pretend_args_size))"
469 ;; Don't do this if we are adjusting SP since we don't want to do it
470 ;; in two steps. Don't split FP sources for the reason listed above.
472 [(set (match_operand:DI 0 "register_operand" "")
473 (plus:DI (match_operand:DI 1 "register_operand" "")
474 (match_operand:DI 2 "const_int_operand" "")))]
475 "! add_operand (operands[2], DImode)
476 && operands[0] != stack_pointer_rtx
477 && operands[1] != frame_pointer_rtx
478 && operands[1] != arg_pointer_rtx"
479 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
480 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
482 HOST_WIDE_INT val = INTVAL (operands[2]);
483 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
484 HOST_WIDE_INT rest = val - low;
486 operands[4] = GEN_INT (low);
487 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
488 operands[3] = GEN_INT (rest);
489 else if (! no_new_pseudos)
491 operands[3] = gen_reg_rtx (DImode);
492 emit_move_insn (operands[3], operands[2]);
493 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
500 (define_insn "*saddl"
501 [(set (match_operand:SI 0 "register_operand" "=r,r")
502 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
503 (match_operand:SI 2 "const48_operand" "I,I"))
504 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
510 (define_insn "*saddl_se"
511 [(set (match_operand:DI 0 "register_operand" "=r,r")
513 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
514 (match_operand:SI 2 "const48_operand" "I,I"))
515 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
522 [(set (match_operand:DI 0 "register_operand" "")
524 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
525 [(match_operand 2 "" "")
526 (match_operand 3 "" "")])
527 (match_operand:SI 4 "const48_operand" ""))
528 (match_operand:SI 5 "sext_add_operand" ""))))
529 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
531 [(set (match_dup 6) (match_dup 7))
533 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
536 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
537 operands[2], operands[3]);
538 operands[8] = gen_lowpart (SImode, operands[6]);
541 (define_insn "*saddq"
542 [(set (match_operand:DI 0 "register_operand" "=r,r")
543 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
544 (match_operand:DI 2 "const48_operand" "I,I"))
545 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
551 (define_insn "addvdi3"
552 [(set (match_operand:DI 0 "register_operand" "=r,r")
553 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
554 (match_operand:DI 2 "sext_add_operand" "rI,O")))
555 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
556 (sign_extend:TI (match_dup 2)))
557 (sign_extend:TI (plus:DI (match_dup 1)
565 (define_insn "negsi2"
566 [(set (match_operand:SI 0 "register_operand" "=r")
567 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
571 (define_insn "*negsi_se"
572 [(set (match_operand:DI 0 "register_operand" "=r")
573 (sign_extend:DI (neg:SI
574 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
578 (define_insn "negvsi2"
579 [(set (match_operand:SI 0 "register_operand" "=r")
580 (neg:SI (match_operand:SI 1 "register_operand" "r")))
581 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
582 (sign_extend:DI (neg:SI (match_dup 1))))
587 (define_insn "negdi2"
588 [(set (match_operand:DI 0 "register_operand" "=r")
589 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
593 (define_insn "negvdi2"
594 [(set (match_operand:DI 0 "register_operand" "=r")
595 (neg:DI (match_operand:DI 1 "register_operand" "r")))
596 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
597 (sign_extend:TI (neg:DI (match_dup 1))))
602 (define_expand "subsi3"
603 [(set (match_operand:SI 0 "register_operand" "")
604 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
605 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
609 (define_insn "*subsi_internal"
610 [(set (match_operand:SI 0 "register_operand" "=r")
611 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
612 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
616 (define_insn "*subsi_se"
617 [(set (match_operand:DI 0 "register_operand" "=r")
618 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
619 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
623 (define_insn "*subsi_se2"
624 [(set (match_operand:DI 0 "register_operand" "=r")
626 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
627 (match_operand:DI 2 "reg_or_8bit_operand" "rI"))
632 (define_insn "subvsi3"
633 [(set (match_operand:SI 0 "register_operand" "=r")
634 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
635 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
636 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
637 (sign_extend:DI (match_dup 2)))
638 (sign_extend:DI (minus:SI (match_dup 1)
644 (define_insn "subdi3"
645 [(set (match_operand:DI 0 "register_operand" "=r")
646 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
647 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
651 (define_insn "*ssubl"
652 [(set (match_operand:SI 0 "register_operand" "=r")
653 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
654 (match_operand:SI 2 "const48_operand" "I"))
655 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
659 (define_insn "*ssubl_se"
660 [(set (match_operand:DI 0 "register_operand" "=r")
662 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
663 (match_operand:SI 2 "const48_operand" "I"))
664 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
668 (define_insn "*ssubq"
669 [(set (match_operand:DI 0 "register_operand" "=r")
670 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
671 (match_operand:DI 2 "const48_operand" "I"))
672 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
676 (define_insn "subvdi3"
677 [(set (match_operand:DI 0 "register_operand" "=r")
678 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
679 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
680 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
681 (sign_extend:TI (match_dup 2)))
682 (sign_extend:TI (minus:DI (match_dup 1)
688 ;; The Unicos/Mk assembler doesn't support mull.
690 (define_insn "mulsi3"
691 [(set (match_operand:SI 0 "register_operand" "=r")
692 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
693 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
694 "!TARGET_ABI_UNICOSMK"
696 [(set_attr "type" "imul")
697 (set_attr "opsize" "si")])
699 (define_insn "*mulsi_se"
700 [(set (match_operand:DI 0 "register_operand" "=r")
702 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
703 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
704 "!TARGET_ABI_UNICOSMK"
706 [(set_attr "type" "imul")
707 (set_attr "opsize" "si")])
709 (define_insn "mulvsi3"
710 [(set (match_operand:SI 0 "register_operand" "=r")
711 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
712 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
713 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
714 (sign_extend:DI (match_dup 2)))
715 (sign_extend:DI (mult:SI (match_dup 1)
718 "!TARGET_ABI_UNICOSMK"
720 [(set_attr "type" "imul")
721 (set_attr "opsize" "si")])
723 (define_insn "muldi3"
724 [(set (match_operand:DI 0 "register_operand" "=r")
725 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
726 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
729 [(set_attr "type" "imul")])
731 (define_insn "mulvdi3"
732 [(set (match_operand:DI 0 "register_operand" "=r")
733 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
734 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
735 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
736 (sign_extend:TI (match_dup 2)))
737 (sign_extend:TI (mult:DI (match_dup 1)
742 [(set_attr "type" "imul")])
744 (define_expand "umuldi3_highpart"
745 [(set (match_operand:DI 0 "register_operand" "")
748 (mult:TI (zero_extend:TI
749 (match_operand:DI 1 "register_operand" ""))
750 (match_operand:DI 2 "reg_or_8bit_operand" ""))
754 if (REG_P (operands[2]))
755 operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]);
758 (define_insn "*umuldi3_highpart_reg"
759 [(set (match_operand:DI 0 "register_operand" "=r")
762 (mult:TI (zero_extend:TI
763 (match_operand:DI 1 "register_operand" "r"))
765 (match_operand:DI 2 "register_operand" "r")))
769 [(set_attr "type" "imul")
770 (set_attr "opsize" "udi")])
772 (define_insn "*umuldi3_highpart_const"
773 [(set (match_operand:DI 0 "register_operand" "=r")
776 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
777 (match_operand:TI 2 "cint8_operand" "I"))
781 [(set_attr "type" "imul")
782 (set_attr "opsize" "udi")])
784 ;; The divide and remainder operations take their inputs from r24 and
785 ;; r25, put their output in r27, and clobber r23 and r28 on all
786 ;; systems except Unicos/Mk. On Unicos, the standard library provides
787 ;; subroutines which use the standard calling convention and work on
790 ;; ??? Force sign-extension here because some versions of OSF/1 and
791 ;; Interix/NT don't do the right thing if the inputs are not properly
792 ;; sign-extended. But Linux, for instance, does not have this
793 ;; problem. Is it worth the complication here to eliminate the sign
796 (define_expand "divsi3"
798 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
800 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
801 (parallel [(set (match_dup 5)
802 (sign_extend:DI (div:SI (match_dup 3) (match_dup 4))))
803 (clobber (reg:DI 23))
804 (clobber (reg:DI 28))])
805 (set (match_operand:SI 0 "nonimmediate_operand" "")
806 (subreg:SI (match_dup 5) 0))]
807 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
809 operands[3] = gen_reg_rtx (DImode);
810 operands[4] = gen_reg_rtx (DImode);
811 operands[5] = gen_reg_rtx (DImode);
814 (define_expand "udivsi3"
816 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
818 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
819 (parallel [(set (match_dup 5)
820 (sign_extend:DI (udiv:SI (match_dup 3) (match_dup 4))))
821 (clobber (reg:DI 23))
822 (clobber (reg:DI 28))])
823 (set (match_operand:SI 0 "nonimmediate_operand" "")
824 (subreg:SI (match_dup 5) 0))]
825 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
827 operands[3] = gen_reg_rtx (DImode);
828 operands[4] = gen_reg_rtx (DImode);
829 operands[5] = gen_reg_rtx (DImode);
832 (define_expand "modsi3"
834 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
836 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
837 (parallel [(set (match_dup 5)
838 (sign_extend:DI (mod:SI (match_dup 3) (match_dup 4))))
839 (clobber (reg:DI 23))
840 (clobber (reg:DI 28))])
841 (set (match_operand:SI 0 "nonimmediate_operand" "")
842 (subreg:SI (match_dup 5) 0))]
843 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
845 operands[3] = gen_reg_rtx (DImode);
846 operands[4] = gen_reg_rtx (DImode);
847 operands[5] = gen_reg_rtx (DImode);
850 (define_expand "umodsi3"
852 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
854 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
855 (parallel [(set (match_dup 5)
856 (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4))))
857 (clobber (reg:DI 23))
858 (clobber (reg:DI 28))])
859 (set (match_operand:SI 0 "nonimmediate_operand" "")
860 (subreg:SI (match_dup 5) 0))]
861 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
863 operands[3] = gen_reg_rtx (DImode);
864 operands[4] = gen_reg_rtx (DImode);
865 operands[5] = gen_reg_rtx (DImode);
868 (define_expand "divdi3"
869 [(parallel [(set (match_operand:DI 0 "register_operand" "")
870 (div:DI (match_operand:DI 1 "register_operand" "")
871 (match_operand:DI 2 "register_operand" "")))
872 (clobber (reg:DI 23))
873 (clobber (reg:DI 28))])]
874 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
877 (define_expand "udivdi3"
878 [(parallel [(set (match_operand:DI 0 "register_operand" "")
879 (udiv:DI (match_operand:DI 1 "register_operand" "")
880 (match_operand:DI 2 "register_operand" "")))
881 (clobber (reg:DI 23))
882 (clobber (reg:DI 28))])]
883 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
886 (define_expand "moddi3"
887 [(use (match_operand:DI 0 "register_operand" ""))
888 (use (match_operand:DI 1 "register_operand" ""))
889 (use (match_operand:DI 2 "register_operand" ""))]
890 "!TARGET_ABI_OPEN_VMS"
892 if (TARGET_ABI_UNICOSMK)
893 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
895 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
899 (define_expand "moddi3_dft"
900 [(parallel [(set (match_operand:DI 0 "register_operand" "")
901 (mod:DI (match_operand:DI 1 "register_operand" "")
902 (match_operand:DI 2 "register_operand" "")))
903 (clobber (reg:DI 23))
904 (clobber (reg:DI 28))])]
905 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
908 ;; On Unicos/Mk, we do as the system's C compiler does:
909 ;; compute the quotient, multiply and subtract.
911 (define_expand "moddi3_umk"
912 [(use (match_operand:DI 0 "register_operand" ""))
913 (use (match_operand:DI 1 "register_operand" ""))
914 (use (match_operand:DI 2 "register_operand" ""))]
915 "TARGET_ABI_UNICOSMK"
917 rtx div, mul = gen_reg_rtx (DImode);
919 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
920 NULL_RTX, 0, OPTAB_LIB);
921 div = force_reg (DImode, div);
922 emit_insn (gen_muldi3 (mul, operands[2], div));
923 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
927 (define_expand "umoddi3"
928 [(use (match_operand:DI 0 "register_operand" ""))
929 (use (match_operand:DI 1 "register_operand" ""))
930 (use (match_operand:DI 2 "register_operand" ""))]
931 "! TARGET_ABI_OPEN_VMS"
933 if (TARGET_ABI_UNICOSMK)
934 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
936 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
940 (define_expand "umoddi3_dft"
941 [(parallel [(set (match_operand:DI 0 "register_operand" "")
942 (umod:DI (match_operand:DI 1 "register_operand" "")
943 (match_operand:DI 2 "register_operand" "")))
944 (clobber (reg:DI 23))
945 (clobber (reg:DI 28))])]
946 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
949 (define_expand "umoddi3_umk"
950 [(use (match_operand:DI 0 "register_operand" ""))
951 (use (match_operand:DI 1 "register_operand" ""))
952 (use (match_operand:DI 2 "register_operand" ""))]
953 "TARGET_ABI_UNICOSMK"
955 rtx div, mul = gen_reg_rtx (DImode);
957 div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
958 NULL_RTX, 1, OPTAB_LIB);
959 div = force_reg (DImode, div);
960 emit_insn (gen_muldi3 (mul, operands[2], div));
961 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
965 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
966 ;; expanded by the assembler.
968 (define_insn_and_split "*divmodsi_internal_er"
969 [(set (match_operand:DI 0 "register_operand" "=c")
970 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
971 [(match_operand:DI 1 "register_operand" "a")
972 (match_operand:DI 2 "register_operand" "b")])))
973 (clobber (reg:DI 23))
974 (clobber (reg:DI 28))]
975 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
976 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
977 "&& reload_completed"
978 [(parallel [(set (match_dup 0)
979 (sign_extend:DI (match_dup 3)))
982 (clobber (reg:DI 23))
983 (clobber (reg:DI 28))])]
986 switch (GET_CODE (operands[3]))
1003 operands[4] = GEN_INT (alpha_next_sequence_number++);
1004 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1005 gen_rtx_SYMBOL_REF (DImode, str),
1008 [(set_attr "type" "jsr")
1009 (set_attr "length" "8")])
1011 (define_insn "*divmodsi_internal_er_1"
1012 [(set (match_operand:DI 0 "register_operand" "=c")
1013 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1014 [(match_operand:DI 1 "register_operand" "a")
1015 (match_operand:DI 2 "register_operand" "b")])))
1016 (use (match_operand:DI 4 "register_operand" "c"))
1017 (use (match_operand 5 "const_int_operand" ""))
1018 (clobber (reg:DI 23))
1019 (clobber (reg:DI 28))]
1020 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1021 "jsr $23,($27),__%E3%J5"
1022 [(set_attr "type" "jsr")
1023 (set_attr "length" "4")])
1025 (define_insn "*divmodsi_internal"
1026 [(set (match_operand:DI 0 "register_operand" "=c")
1027 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1028 [(match_operand:DI 1 "register_operand" "a")
1029 (match_operand:DI 2 "register_operand" "b")])))
1030 (clobber (reg:DI 23))
1031 (clobber (reg:DI 28))]
1032 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1034 [(set_attr "type" "jsr")
1035 (set_attr "length" "8")])
1037 (define_insn_and_split "*divmoddi_internal_er"
1038 [(set (match_operand:DI 0 "register_operand" "=c")
1039 (match_operator:DI 3 "divmod_operator"
1040 [(match_operand:DI 1 "register_operand" "a")
1041 (match_operand:DI 2 "register_operand" "b")]))
1042 (clobber (reg:DI 23))
1043 (clobber (reg:DI 28))]
1044 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1045 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
1046 "&& reload_completed"
1047 [(parallel [(set (match_dup 0) (match_dup 3))
1050 (clobber (reg:DI 23))
1051 (clobber (reg:DI 28))])]
1054 switch (GET_CODE (operands[3]))
1071 operands[4] = GEN_INT (alpha_next_sequence_number++);
1072 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1073 gen_rtx_SYMBOL_REF (DImode, str),
1076 [(set_attr "type" "jsr")
1077 (set_attr "length" "8")])
1079 (define_insn "*divmoddi_internal_er_1"
1080 [(set (match_operand:DI 0 "register_operand" "=c")
1081 (match_operator:DI 3 "divmod_operator"
1082 [(match_operand:DI 1 "register_operand" "a")
1083 (match_operand:DI 2 "register_operand" "b")]))
1084 (use (match_operand:DI 4 "register_operand" "c"))
1085 (use (match_operand 5 "const_int_operand" ""))
1086 (clobber (reg:DI 23))
1087 (clobber (reg:DI 28))]
1088 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1089 "jsr $23,($27),__%E3%J5"
1090 [(set_attr "type" "jsr")
1091 (set_attr "length" "4")])
1093 (define_insn "*divmoddi_internal"
1094 [(set (match_operand:DI 0 "register_operand" "=c")
1095 (match_operator:DI 3 "divmod_operator"
1096 [(match_operand:DI 1 "register_operand" "a")
1097 (match_operand:DI 2 "register_operand" "b")]))
1098 (clobber (reg:DI 23))
1099 (clobber (reg:DI 28))]
1100 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1102 [(set_attr "type" "jsr")
1103 (set_attr "length" "8")])
1105 ;; Next are the basic logical operations. These only exist in DImode.
1107 (define_insn "anddi3"
1108 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1109 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1110 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1116 [(set_attr "type" "ilog,ilog,shift")])
1118 ;; There are times when we can split an AND into two AND insns. This occurs
1119 ;; when we can first clear any bytes and then clear anything else. For
1120 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1121 ;; Only do this when running on 64-bit host since the computations are
1122 ;; too messy otherwise.
1125 [(set (match_operand:DI 0 "register_operand" "")
1126 (and:DI (match_operand:DI 1 "register_operand" "")
1127 (match_operand:DI 2 "const_int_operand" "")))]
1128 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1129 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1130 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1132 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1133 unsigned HOST_WIDE_INT mask2 = mask1;
1136 /* For each byte that isn't all zeros, make it all ones. */
1137 for (i = 0; i < 64; i += 8)
1138 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1139 mask1 |= (HOST_WIDE_INT) 0xff << i;
1141 /* Now turn on any bits we've just turned off. */
1144 operands[3] = GEN_INT (mask1);
1145 operands[4] = GEN_INT (mask2);
1148 (define_expand "zero_extendqihi2"
1149 [(set (match_operand:HI 0 "register_operand" "")
1150 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1154 operands[1] = force_reg (QImode, operands[1]);
1157 (define_insn "*zero_extendqihi2_bwx"
1158 [(set (match_operand:HI 0 "register_operand" "=r,r")
1159 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1164 [(set_attr "type" "ilog,ild")])
1166 (define_insn "*zero_extendqihi2_nobwx"
1167 [(set (match_operand:HI 0 "register_operand" "=r")
1168 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1171 [(set_attr "type" "ilog")])
1173 (define_expand "zero_extendqisi2"
1174 [(set (match_operand:SI 0 "register_operand" "")
1175 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1179 operands[1] = force_reg (QImode, operands[1]);
1182 (define_insn "*zero_extendqisi2_bwx"
1183 [(set (match_operand:SI 0 "register_operand" "=r,r")
1184 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1189 [(set_attr "type" "ilog,ild")])
1191 (define_insn "*zero_extendqisi2_nobwx"
1192 [(set (match_operand:SI 0 "register_operand" "=r")
1193 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1196 [(set_attr "type" "ilog")])
1198 (define_expand "zero_extendqidi2"
1199 [(set (match_operand:DI 0 "register_operand" "")
1200 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1204 operands[1] = force_reg (QImode, operands[1]);
1207 (define_insn "*zero_extendqidi2_bwx"
1208 [(set (match_operand:DI 0 "register_operand" "=r,r")
1209 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1214 [(set_attr "type" "ilog,ild")])
1216 (define_insn "*zero_extendqidi2_nobwx"
1217 [(set (match_operand:DI 0 "register_operand" "=r")
1218 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1221 [(set_attr "type" "ilog")])
1223 (define_expand "zero_extendhisi2"
1224 [(set (match_operand:SI 0 "register_operand" "")
1225 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1229 operands[1] = force_reg (HImode, operands[1]);
1232 (define_insn "*zero_extendhisi2_bwx"
1233 [(set (match_operand:SI 0 "register_operand" "=r,r")
1234 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1239 [(set_attr "type" "shift,ild")])
1241 (define_insn "*zero_extendhisi2_nobwx"
1242 [(set (match_operand:SI 0 "register_operand" "=r")
1243 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1246 [(set_attr "type" "shift")])
1248 (define_expand "zero_extendhidi2"
1249 [(set (match_operand:DI 0 "register_operand" "")
1250 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1254 operands[1] = force_reg (HImode, operands[1]);
1257 (define_insn "*zero_extendhidi2_bwx"
1258 [(set (match_operand:DI 0 "register_operand" "=r,r")
1259 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1264 [(set_attr "type" "shift,ild")])
1266 (define_insn "*zero_extendhidi2_nobwx"
1267 [(set (match_operand:DI 0 "register_operand" "=r")
1268 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1271 [(set_attr "type" "shift")])
1273 (define_insn "zero_extendsidi2"
1274 [(set (match_operand:DI 0 "register_operand" "=r")
1275 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1278 [(set_attr "type" "shift")])
1280 (define_insn "andnotdi3"
1281 [(set (match_operand:DI 0 "register_operand" "=r")
1282 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1283 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1286 [(set_attr "type" "ilog")])
1288 (define_insn "iordi3"
1289 [(set (match_operand:DI 0 "register_operand" "=r,r")
1290 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1291 (match_operand:DI 2 "or_operand" "rI,N")))]
1296 [(set_attr "type" "ilog")])
1298 (define_insn "one_cmpldi2"
1299 [(set (match_operand:DI 0 "register_operand" "=r")
1300 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1303 [(set_attr "type" "ilog")])
1305 (define_insn "*iornot"
1306 [(set (match_operand:DI 0 "register_operand" "=r")
1307 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1308 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1311 [(set_attr "type" "ilog")])
1313 (define_insn "xordi3"
1314 [(set (match_operand:DI 0 "register_operand" "=r,r")
1315 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1316 (match_operand:DI 2 "or_operand" "rI,N")))]
1321 [(set_attr "type" "ilog")])
1323 (define_insn "*xornot"
1324 [(set (match_operand:DI 0 "register_operand" "=r")
1325 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1326 (match_operand:DI 2 "register_operand" "rI"))))]
1329 [(set_attr "type" "ilog")])
1331 ;; Handle FFS and related insns iff we support CIX.
1333 (define_expand "ffsdi2"
1335 (unspec:DI [(match_operand:DI 1 "register_operand" "")] UNSPEC_CTTZ))
1337 (plus:DI (match_dup 2) (const_int 1)))
1338 (set (match_operand:DI 0 "register_operand" "")
1339 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1340 (const_int 0) (match_dup 3)))]
1343 operands[2] = gen_reg_rtx (DImode);
1344 operands[3] = gen_reg_rtx (DImode);
1347 (define_insn "*cttz"
1348 [(set (match_operand:DI 0 "register_operand" "=r")
1349 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_CTTZ))]
1352 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1353 ; reuse the existing type name.
1354 [(set_attr "type" "mvi")])
1356 (define_insn "clzdi2"
1357 [(set (match_operand:DI 0 "register_operand" "=r")
1358 (clz:DI (match_operand:DI 1 "register_operand" "r")))]
1361 [(set_attr "type" "mvi")])
1363 (define_insn "ctzdi2"
1364 [(set (match_operand:DI 0 "register_operand" "=r")
1365 (ctz:DI (match_operand:DI 1 "register_operand" "r")))]
1368 [(set_attr "type" "mvi")])
1370 (define_insn "popcountdi2"
1371 [(set (match_operand:DI 0 "register_operand" "=r")
1372 (popcount:DI (match_operand:DI 1 "register_operand" "r")))]
1375 [(set_attr "type" "mvi")])
1377 ;; Next come the shifts and the various extract and insert operations.
1379 (define_insn "ashldi3"
1380 [(set (match_operand:DI 0 "register_operand" "=r,r")
1381 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1382 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1385 switch (which_alternative)
1388 if (operands[2] == const1_rtx)
1389 return "addq %r1,%r1,%0";
1391 return "s%P2addq %r1,0,%0";
1393 return "sll %r1,%2,%0";
1398 [(set_attr "type" "iadd,shift")])
1400 (define_insn "*ashldi_se"
1401 [(set (match_operand:DI 0 "register_operand" "=r")
1403 (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1404 (match_operand:DI 2 "const_int_operand" "P"))
1406 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1408 if (operands[2] == const1_rtx)
1409 return "addl %r1,%r1,%0";
1411 return "s%P2addl %r1,0,%0";
1413 [(set_attr "type" "iadd")])
1415 (define_insn "lshrdi3"
1416 [(set (match_operand:DI 0 "register_operand" "=r")
1417 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1418 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1421 [(set_attr "type" "shift")])
1423 (define_insn "ashrdi3"
1424 [(set (match_operand:DI 0 "register_operand" "=r")
1425 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1426 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1429 [(set_attr "type" "shift")])
1431 (define_expand "extendqihi2"
1433 (ashift:DI (match_operand:QI 1 "some_operand" "")
1435 (set (match_operand:HI 0 "register_operand" "")
1436 (ashiftrt:DI (match_dup 2)
1442 emit_insn (gen_extendqihi2x (operands[0],
1443 force_reg (QImode, operands[1])));
1447 /* If we have an unaligned MEM, extend to DImode (which we do
1448 specially) and then copy to the result. */
1449 if (unaligned_memory_operand (operands[1], HImode))
1451 rtx temp = gen_reg_rtx (DImode);
1453 emit_insn (gen_extendqidi2 (temp, operands[1]));
1454 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1458 operands[0] = gen_lowpart (DImode, operands[0]);
1459 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1460 operands[2] = gen_reg_rtx (DImode);
1463 (define_insn "extendqidi2x"
1464 [(set (match_operand:DI 0 "register_operand" "=r")
1465 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1468 [(set_attr "type" "shift")])
1470 (define_insn "extendhidi2x"
1471 [(set (match_operand:DI 0 "register_operand" "=r")
1472 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1475 [(set_attr "type" "shift")])
1477 (define_insn "extendqisi2x"
1478 [(set (match_operand:SI 0 "register_operand" "=r")
1479 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1482 [(set_attr "type" "shift")])
1484 (define_insn "extendhisi2x"
1485 [(set (match_operand:SI 0 "register_operand" "=r")
1486 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1489 [(set_attr "type" "shift")])
1491 (define_insn "extendqihi2x"
1492 [(set (match_operand:HI 0 "register_operand" "=r")
1493 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1496 [(set_attr "type" "shift")])
1498 (define_expand "extendqisi2"
1500 (ashift:DI (match_operand:QI 1 "some_operand" "")
1502 (set (match_operand:SI 0 "register_operand" "")
1503 (ashiftrt:DI (match_dup 2)
1509 emit_insn (gen_extendqisi2x (operands[0],
1510 force_reg (QImode, operands[1])));
1514 /* If we have an unaligned MEM, extend to a DImode form of
1515 the result (which we do specially). */
1516 if (unaligned_memory_operand (operands[1], QImode))
1518 rtx temp = gen_reg_rtx (DImode);
1520 emit_insn (gen_extendqidi2 (temp, operands[1]));
1521 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1525 operands[0] = gen_lowpart (DImode, operands[0]);
1526 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1527 operands[2] = gen_reg_rtx (DImode);
1530 (define_expand "extendqidi2"
1532 (ashift:DI (match_operand:QI 1 "some_operand" "")
1534 (set (match_operand:DI 0 "register_operand" "")
1535 (ashiftrt:DI (match_dup 2)
1541 emit_insn (gen_extendqidi2x (operands[0],
1542 force_reg (QImode, operands[1])));
1546 if (unaligned_memory_operand (operands[1], QImode))
1549 = gen_unaligned_extendqidi (operands[0],
1550 get_unaligned_address (operands[1], 1));
1552 alpha_set_memflags (seq, operands[1]);
1557 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1558 operands[2] = gen_reg_rtx (DImode);
1561 (define_expand "extendhisi2"
1563 (ashift:DI (match_operand:HI 1 "some_operand" "")
1565 (set (match_operand:SI 0 "register_operand" "")
1566 (ashiftrt:DI (match_dup 2)
1572 emit_insn (gen_extendhisi2x (operands[0],
1573 force_reg (HImode, operands[1])));
1577 /* If we have an unaligned MEM, extend to a DImode form of
1578 the result (which we do specially). */
1579 if (unaligned_memory_operand (operands[1], HImode))
1581 rtx temp = gen_reg_rtx (DImode);
1583 emit_insn (gen_extendhidi2 (temp, operands[1]));
1584 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1588 operands[0] = gen_lowpart (DImode, operands[0]);
1589 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1590 operands[2] = gen_reg_rtx (DImode);
1593 (define_expand "extendhidi2"
1595 (ashift:DI (match_operand:HI 1 "some_operand" "")
1597 (set (match_operand:DI 0 "register_operand" "")
1598 (ashiftrt:DI (match_dup 2)
1604 emit_insn (gen_extendhidi2x (operands[0],
1605 force_reg (HImode, operands[1])));
1609 if (unaligned_memory_operand (operands[1], HImode))
1612 = gen_unaligned_extendhidi (operands[0],
1613 get_unaligned_address (operands[1], 2));
1615 alpha_set_memflags (seq, operands[1]);
1620 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1621 operands[2] = gen_reg_rtx (DImode);
1624 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1625 ;; as a pattern saves one instruction. The code is similar to that for
1626 ;; the unaligned loads (see below).
1628 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1629 (define_expand "unaligned_extendqidi"
1630 [(use (match_operand:QI 0 "register_operand" ""))
1631 (use (match_operand:DI 1 "address_operand" ""))]
1634 if (WORDS_BIG_ENDIAN)
1635 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
1637 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
1641 (define_expand "unaligned_extendqidi_le"
1642 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1644 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1647 (ashift:DI (match_dup 3)
1648 (minus:DI (const_int 64)
1650 (and:DI (match_dup 2) (const_int 7))
1652 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1653 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1654 "! WORDS_BIG_ENDIAN"
1656 operands[2] = gen_reg_rtx (DImode);
1657 operands[3] = gen_reg_rtx (DImode);
1658 operands[4] = gen_reg_rtx (DImode);
1661 (define_expand "unaligned_extendqidi_be"
1662 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1663 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -1)))
1665 (mem:DI (and:DI (match_dup 3)
1667 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -2)))
1669 (ashift:DI (match_dup 4)
1672 (plus:DI (match_dup 5) (const_int 1))
1675 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1676 (ashiftrt:DI (match_dup 6) (const_int 56)))]
1679 operands[2] = gen_reg_rtx (DImode);
1680 operands[3] = gen_reg_rtx (DImode);
1681 operands[4] = gen_reg_rtx (DImode);
1682 operands[5] = gen_reg_rtx (DImode);
1683 operands[6] = gen_reg_rtx (DImode);
1686 (define_expand "unaligned_extendhidi"
1687 [(use (match_operand:QI 0 "register_operand" ""))
1688 (use (match_operand:DI 1 "address_operand" ""))]
1691 operands[0] = gen_lowpart (DImode, operands[0]);
1692 emit_insn ((WORDS_BIG_ENDIAN
1693 ? gen_unaligned_extendhidi_be
1694 : gen_unaligned_extendhidi_le) (operands[0], operands[1]));
1698 (define_expand "unaligned_extendhidi_le"
1699 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1701 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1704 (ashift:DI (match_dup 3)
1705 (minus:DI (const_int 64)
1707 (and:DI (match_dup 2) (const_int 7))
1709 (set (match_operand:DI 0 "register_operand" "")
1710 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1711 "! WORDS_BIG_ENDIAN"
1713 operands[2] = gen_reg_rtx (DImode);
1714 operands[3] = gen_reg_rtx (DImode);
1715 operands[4] = gen_reg_rtx (DImode);
1718 (define_expand "unaligned_extendhidi_be"
1719 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1720 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -2)))
1722 (mem:DI (and:DI (match_dup 3)
1724 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -3)))
1726 (ashift:DI (match_dup 4)
1729 (plus:DI (match_dup 5) (const_int 1))
1732 (set (match_operand:DI 0 "register_operand" "")
1733 (ashiftrt:DI (match_dup 6) (const_int 48)))]
1736 operands[2] = gen_reg_rtx (DImode);
1737 operands[3] = gen_reg_rtx (DImode);
1738 operands[4] = gen_reg_rtx (DImode);
1739 operands[5] = gen_reg_rtx (DImode);
1740 operands[6] = gen_reg_rtx (DImode);
1743 (define_insn "*extxl_const"
1744 [(set (match_operand:DI 0 "register_operand" "=r")
1745 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1746 (match_operand:DI 2 "mode_width_operand" "n")
1747 (match_operand:DI 3 "mul8_operand" "I")))]
1749 "ext%M2l %r1,%s3,%0"
1750 [(set_attr "type" "shift")])
1752 (define_insn "extxl_le"
1753 [(set (match_operand:DI 0 "register_operand" "=r")
1754 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1755 (match_operand:DI 2 "mode_width_operand" "n")
1756 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1758 "! WORDS_BIG_ENDIAN"
1760 [(set_attr "type" "shift")])
1762 (define_insn "extxl_be"
1763 [(set (match_operand:DI 0 "register_operand" "=r")
1764 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1765 (match_operand:DI 2 "mode_width_operand" "n")
1769 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1773 [(set_attr "type" "shift")])
1775 ;; Combine has some strange notion of preserving existing undefined behavior
1776 ;; in shifts larger than a word size. So capture these patterns that it
1777 ;; should have turned into zero_extracts.
1779 (define_insn "*extxl_1_le"
1780 [(set (match_operand:DI 0 "register_operand" "=r")
1781 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1782 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1784 (match_operand:DI 3 "mode_mask_operand" "n")))]
1785 "! WORDS_BIG_ENDIAN"
1787 [(set_attr "type" "shift")])
1789 (define_insn "*extxl_1_be"
1790 [(set (match_operand:DI 0 "register_operand" "=r")
1791 (and:DI (lshiftrt:DI
1792 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1793 (minus:DI (const_int 56)
1794 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1796 (match_operand:DI 3 "mode_mask_operand" "n")))]
1799 [(set_attr "type" "shift")])
1801 (define_insn "*extql_2_le"
1802 [(set (match_operand:DI 0 "register_operand" "=r")
1803 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1804 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1806 "! WORDS_BIG_ENDIAN"
1808 [(set_attr "type" "shift")])
1810 (define_insn "*extql_2_be"
1811 [(set (match_operand:DI 0 "register_operand" "=r")
1813 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1814 (minus:DI (const_int 56)
1816 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1820 [(set_attr "type" "shift")])
1822 (define_insn "extqh_le"
1823 [(set (match_operand:DI 0 "register_operand" "=r")
1825 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1826 (minus:DI (const_int 64)
1829 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1832 "! WORDS_BIG_ENDIAN"
1834 [(set_attr "type" "shift")])
1836 (define_insn "extqh_be"
1837 [(set (match_operand:DI 0 "register_operand" "=r")
1839 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1842 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1848 [(set_attr "type" "shift")])
1850 (define_insn "extlh_le"
1851 [(set (match_operand:DI 0 "register_operand" "=r")
1853 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1854 (const_int 2147483647))
1855 (minus:DI (const_int 64)
1858 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1861 "! WORDS_BIG_ENDIAN"
1863 [(set_attr "type" "shift")])
1865 (define_insn "extlh_be"
1866 [(set (match_operand:DI 0 "register_operand" "=r")
1869 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1873 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1877 (const_int 2147483647)))]
1880 [(set_attr "type" "shift")])
1882 (define_insn "extwh_le"
1883 [(set (match_operand:DI 0 "register_operand" "=r")
1885 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1887 (minus:DI (const_int 64)
1890 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1893 "! WORDS_BIG_ENDIAN"
1895 [(set_attr "type" "shift")])
1897 (define_insn "extwh_be"
1898 [(set (match_operand:DI 0 "register_operand" "=r")
1900 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1904 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1908 (const_int 65535)))]
1911 [(set_attr "type" "shift")])
1913 ;; This converts an extXl into an extXh with an appropriate adjustment
1914 ;; to the address calculation.
1917 ;; [(set (match_operand:DI 0 "register_operand" "")
1918 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1919 ;; (match_operand:DI 2 "mode_width_operand" "")
1920 ;; (ashift:DI (match_operand:DI 3 "" "")
1922 ;; (match_operand:DI 4 "const_int_operand" "")))
1923 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1924 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1925 ;; [(set (match_dup 5) (match_dup 6))
1926 ;; (set (match_dup 0)
1927 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1928 ;; (ashift:DI (plus:DI (match_dup 5)
1934 ;; operands[6] = plus_constant (operands[3],
1935 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1936 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1939 (define_insn "*insbl_const"
1940 [(set (match_operand:DI 0 "register_operand" "=r")
1941 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1942 (match_operand:DI 2 "mul8_operand" "I")))]
1945 [(set_attr "type" "shift")])
1947 (define_insn "*inswl_const"
1948 [(set (match_operand:DI 0 "register_operand" "=r")
1949 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1950 (match_operand:DI 2 "mul8_operand" "I")))]
1953 [(set_attr "type" "shift")])
1955 (define_insn "*insll_const"
1956 [(set (match_operand:DI 0 "register_operand" "=r")
1957 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1958 (match_operand:DI 2 "mul8_operand" "I")))]
1961 [(set_attr "type" "shift")])
1963 (define_insn "insbl_le"
1964 [(set (match_operand:DI 0 "register_operand" "=r")
1965 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1966 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1968 "! WORDS_BIG_ENDIAN"
1970 [(set_attr "type" "shift")])
1972 (define_insn "insbl_be"
1973 [(set (match_operand:DI 0 "register_operand" "=r")
1974 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1975 (minus:DI (const_int 56)
1976 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1980 [(set_attr "type" "shift")])
1982 (define_insn "inswl_le"
1983 [(set (match_operand:DI 0 "register_operand" "=r")
1984 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1985 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1987 "! WORDS_BIG_ENDIAN"
1989 [(set_attr "type" "shift")])
1991 (define_insn "inswl_be"
1992 [(set (match_operand:DI 0 "register_operand" "=r")
1993 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1994 (minus:DI (const_int 56)
1995 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1999 [(set_attr "type" "shift")])
2001 (define_insn "insll_le"
2002 [(set (match_operand:DI 0 "register_operand" "=r")
2003 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2004 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2006 "! WORDS_BIG_ENDIAN"
2008 [(set_attr "type" "shift")])
2010 (define_insn "insll_be"
2011 [(set (match_operand:DI 0 "register_operand" "=r")
2012 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2013 (minus:DI (const_int 56)
2014 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2018 [(set_attr "type" "shift")])
2020 (define_insn "insql_le"
2021 [(set (match_operand:DI 0 "register_operand" "=r")
2022 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2023 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2025 "! WORDS_BIG_ENDIAN"
2027 [(set_attr "type" "shift")])
2029 (define_insn "insql_be"
2030 [(set (match_operand:DI 0 "register_operand" "=r")
2031 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2032 (minus:DI (const_int 56)
2033 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2037 [(set_attr "type" "shift")])
2039 ;; Combine has this sometimes habit of moving the and outside of the
2040 ;; shift, making life more interesting.
2042 (define_insn "*insxl"
2043 [(set (match_operand:DI 0 "register_operand" "=r")
2044 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
2045 (match_operand:DI 2 "mul8_operand" "I"))
2046 (match_operand:DI 3 "immediate_operand" "i")))]
2047 "HOST_BITS_PER_WIDE_INT == 64
2048 && GET_CODE (operands[3]) == CONST_INT
2049 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2050 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2051 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2052 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2053 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2054 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
2056 #if HOST_BITS_PER_WIDE_INT == 64
2057 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2058 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2059 return "insbl %1,%s2,%0";
2060 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2061 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2062 return "inswl %1,%s2,%0";
2063 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2064 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2065 return "insll %1,%s2,%0";
2069 [(set_attr "type" "shift")])
2071 ;; We do not include the insXh insns because they are complex to express
2072 ;; and it does not appear that we would ever want to generate them.
2074 ;; Since we need them for block moves, though, cop out and use unspec.
2076 (define_insn "insxh"
2077 [(set (match_operand:DI 0 "register_operand" "=r")
2078 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2079 (match_operand:DI 2 "mode_width_operand" "n")
2080 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2084 [(set_attr "type" "shift")])
2086 (define_insn "mskxl_le"
2087 [(set (match_operand:DI 0 "register_operand" "=r")
2088 (and:DI (not:DI (ashift:DI
2089 (match_operand:DI 2 "mode_mask_operand" "n")
2091 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2093 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2094 "! WORDS_BIG_ENDIAN"
2096 [(set_attr "type" "shift")])
2098 (define_insn "mskxl_be"
2099 [(set (match_operand:DI 0 "register_operand" "=r")
2100 (and:DI (not:DI (ashift:DI
2101 (match_operand:DI 2 "mode_mask_operand" "n")
2102 (minus:DI (const_int 56)
2104 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2106 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2109 [(set_attr "type" "shift")])
2111 ;; We do not include the mskXh insns because it does not appear we would
2112 ;; ever generate one.
2114 ;; Again, we do for block moves and we use unspec again.
2116 (define_insn "mskxh"
2117 [(set (match_operand:DI 0 "register_operand" "=r")
2118 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2119 (match_operand:DI 2 "mode_width_operand" "n")
2120 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2124 [(set_attr "type" "shift")])
2126 ;; Prefer AND + NE over LSHIFTRT + AND.
2128 (define_insn_and_split "*ze_and_ne"
2129 [(set (match_operand:DI 0 "register_operand" "=r")
2130 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2132 (match_operand 2 "const_int_operand" "I")))]
2133 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2135 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2137 (and:DI (match_dup 1) (match_dup 3)))
2139 (ne:DI (match_dup 0) (const_int 0)))]
2140 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
2142 ;; Floating-point operations. All the double-precision insns can extend
2143 ;; from single, so indicate that. The exception are the ones that simply
2144 ;; play with the sign bits; it's not clear what to do there.
2146 (define_insn "abssf2"
2147 [(set (match_operand:SF 0 "register_operand" "=f")
2148 (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2151 [(set_attr "type" "fcpys")])
2153 (define_insn "*nabssf2"
2154 [(set (match_operand:SF 0 "register_operand" "=f")
2155 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2158 [(set_attr "type" "fadd")])
2160 (define_insn "absdf2"
2161 [(set (match_operand:DF 0 "register_operand" "=f")
2162 (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2165 [(set_attr "type" "fcpys")])
2167 (define_insn "*nabsdf2"
2168 [(set (match_operand:DF 0 "register_operand" "=f")
2169 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG"))))]
2172 [(set_attr "type" "fadd")])
2174 (define_expand "abstf2"
2175 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2176 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2177 (use (match_dup 2))])]
2178 "TARGET_HAS_XFLOATING_LIBS"
2180 #if HOST_BITS_PER_WIDE_INT >= 64
2181 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2183 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2187 (define_insn_and_split "*abstf_internal"
2188 [(set (match_operand:TF 0 "register_operand" "=r")
2189 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2190 (use (match_operand:DI 2 "register_operand" "r"))]
2191 "TARGET_HAS_XFLOATING_LIBS"
2193 "&& reload_completed"
2195 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
2197 (define_insn "negsf2"
2198 [(set (match_operand:SF 0 "register_operand" "=f")
2199 (neg:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2202 [(set_attr "type" "fadd")])
2204 (define_insn "negdf2"
2205 [(set (match_operand:DF 0 "register_operand" "=f")
2206 (neg:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2209 [(set_attr "type" "fadd")])
2211 (define_expand "negtf2"
2212 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2213 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2214 (use (match_dup 2))])]
2215 "TARGET_HAS_XFLOATING_LIBS"
2217 #if HOST_BITS_PER_WIDE_INT >= 64
2218 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2220 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2224 (define_insn_and_split "*negtf_internal"
2225 [(set (match_operand:TF 0 "register_operand" "=r")
2226 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2227 (use (match_operand:DI 2 "register_operand" "r"))]
2228 "TARGET_HAS_XFLOATING_LIBS"
2230 "&& reload_completed"
2232 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2234 (define_insn "*addsf_ieee"
2235 [(set (match_operand:SF 0 "register_operand" "=&f")
2236 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2237 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2238 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2239 "add%,%/ %R1,%R2,%0"
2240 [(set_attr "type" "fadd")
2241 (set_attr "trap" "yes")
2242 (set_attr "round_suffix" "normal")
2243 (set_attr "trap_suffix" "u_su_sui")])
2245 (define_insn "addsf3"
2246 [(set (match_operand:SF 0 "register_operand" "=f")
2247 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2248 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2250 "add%,%/ %R1,%R2,%0"
2251 [(set_attr "type" "fadd")
2252 (set_attr "trap" "yes")
2253 (set_attr "round_suffix" "normal")
2254 (set_attr "trap_suffix" "u_su_sui")])
2256 (define_insn "*adddf_ieee"
2257 [(set (match_operand:DF 0 "register_operand" "=&f")
2258 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2259 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2260 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2261 "add%-%/ %R1,%R2,%0"
2262 [(set_attr "type" "fadd")
2263 (set_attr "trap" "yes")
2264 (set_attr "round_suffix" "normal")
2265 (set_attr "trap_suffix" "u_su_sui")])
2267 (define_insn "adddf3"
2268 [(set (match_operand:DF 0 "register_operand" "=f")
2269 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2270 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2272 "add%-%/ %R1,%R2,%0"
2273 [(set_attr "type" "fadd")
2274 (set_attr "trap" "yes")
2275 (set_attr "round_suffix" "normal")
2276 (set_attr "trap_suffix" "u_su_sui")])
2278 (define_insn "*adddf_ext1"
2279 [(set (match_operand:DF 0 "register_operand" "=f")
2280 (plus:DF (float_extend:DF
2281 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2282 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2283 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2284 "add%-%/ %R1,%R2,%0"
2285 [(set_attr "type" "fadd")
2286 (set_attr "trap" "yes")
2287 (set_attr "round_suffix" "normal")
2288 (set_attr "trap_suffix" "u_su_sui")])
2290 (define_insn "*adddf_ext2"
2291 [(set (match_operand:DF 0 "register_operand" "=f")
2292 (plus:DF (float_extend:DF
2293 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2295 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2296 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2297 "add%-%/ %R1,%R2,%0"
2298 [(set_attr "type" "fadd")
2299 (set_attr "trap" "yes")
2300 (set_attr "round_suffix" "normal")
2301 (set_attr "trap_suffix" "u_su_sui")])
2303 (define_expand "addtf3"
2304 [(use (match_operand 0 "register_operand" ""))
2305 (use (match_operand 1 "general_operand" ""))
2306 (use (match_operand 2 "general_operand" ""))]
2307 "TARGET_HAS_XFLOATING_LIBS"
2308 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2310 ;; Define conversion operators between DFmode and SImode, using the cvtql
2311 ;; instruction. To allow combine et al to do useful things, we keep the
2312 ;; operation as a unit until after reload, at which point we split the
2315 ;; Note that we (attempt to) only consider this optimization when the
2316 ;; ultimate destination is memory. If we will be doing further integer
2317 ;; processing, it is cheaper to do the truncation in the int regs.
2319 (define_insn "*cvtql"
2320 [(set (match_operand:SF 0 "register_operand" "=f")
2321 (unspec:SF [(match_operand:DI 1 "reg_or_0_operand" "fG")]
2325 [(set_attr "type" "fadd")
2326 (set_attr "trap" "yes")
2327 (set_attr "trap_suffix" "v_sv")])
2329 (define_insn_and_split "*fix_truncdfsi_ieee"
2330 [(set (match_operand:SI 0 "memory_operand" "=m")
2332 (match_operator:DI 4 "fix_operator"
2333 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
2334 (clobber (match_scratch:DI 2 "=&f"))
2335 (clobber (match_scratch:SF 3 "=&f"))]
2336 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2338 "&& reload_completed"
2339 [(set (match_dup 2) (match_op_dup 4 [(match_dup 1)]))
2340 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2341 (set (match_dup 5) (match_dup 3))]
2343 operands[5] = adjust_address (operands[0], SFmode, 0);
2345 [(set_attr "type" "fadd")
2346 (set_attr "trap" "yes")])
2348 (define_insn_and_split "*fix_truncdfsi_internal"
2349 [(set (match_operand:SI 0 "memory_operand" "=m")
2351 (match_operator:DI 3 "fix_operator"
2352 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
2353 (clobber (match_scratch:DI 2 "=f"))]
2354 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2356 "&& reload_completed"
2357 [(set (match_dup 2) (match_op_dup 3 [(match_dup 1)]))
2358 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2359 (set (match_dup 5) (match_dup 4))]
2361 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
2362 operands[5] = adjust_address (operands[0], SFmode, 0);
2364 [(set_attr "type" "fadd")
2365 (set_attr "trap" "yes")])
2367 (define_insn "*fix_truncdfdi_ieee"
2368 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2369 (match_operator:DI 2 "fix_operator"
2370 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
2371 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2373 [(set_attr "type" "fadd")
2374 (set_attr "trap" "yes")
2375 (set_attr "round_suffix" "c")
2376 (set_attr "trap_suffix" "v_sv_svi")])
2378 (define_insn "*fix_truncdfdi2"
2379 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2380 (match_operator:DI 2 "fix_operator"
2381 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
2384 [(set_attr "type" "fadd")
2385 (set_attr "trap" "yes")
2386 (set_attr "round_suffix" "c")
2387 (set_attr "trap_suffix" "v_sv_svi")])
2389 (define_expand "fix_truncdfdi2"
2390 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2391 (fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
2395 (define_expand "fixuns_truncdfdi2"
2396 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2397 (unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
2401 ;; Likewise between SFmode and SImode.
2403 (define_insn_and_split "*fix_truncsfsi_ieee"
2404 [(set (match_operand:SI 0 "memory_operand" "=m")
2406 (match_operator:DI 4 "fix_operator"
2408 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
2409 (clobber (match_scratch:DI 2 "=&f"))
2410 (clobber (match_scratch:SF 3 "=&f"))]
2411 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2413 "&& reload_completed"
2414 [(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))]))
2415 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2416 (set (match_dup 5) (match_dup 3))]
2418 operands[5] = adjust_address (operands[0], SFmode, 0);
2420 [(set_attr "type" "fadd")
2421 (set_attr "trap" "yes")])
2423 (define_insn_and_split "*fix_truncsfsi_internal"
2424 [(set (match_operand:SI 0 "memory_operand" "=m")
2426 (match_operator:DI 3 "fix_operator"
2428 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
2429 (clobber (match_scratch:DI 2 "=f"))]
2430 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2432 "&& reload_completed"
2433 [(set (match_dup 2) (match_op_dup 3 [(float_extend:DF (match_dup 1))]))
2434 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2435 (set (match_dup 5) (match_dup 4))]
2437 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
2438 operands[5] = adjust_address (operands[0], SFmode, 0);
2440 [(set_attr "type" "fadd")
2441 (set_attr "trap" "yes")])
2443 (define_insn "*fix_truncsfdi_ieee"
2444 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2445 (match_operator:DI 2 "fix_operator"
2446 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
2447 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2449 [(set_attr "type" "fadd")
2450 (set_attr "trap" "yes")
2451 (set_attr "round_suffix" "c")
2452 (set_attr "trap_suffix" "v_sv_svi")])
2454 (define_insn "*fix_truncsfdi2"
2455 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2456 (match_operator:DI 2 "fix_operator"
2457 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
2460 [(set_attr "type" "fadd")
2461 (set_attr "trap" "yes")
2462 (set_attr "round_suffix" "c")
2463 (set_attr "trap_suffix" "v_sv_svi")])
2465 (define_expand "fix_truncsfdi2"
2466 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2467 (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
2471 (define_expand "fixuns_truncsfdi2"
2472 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2474 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
2478 (define_expand "fix_trunctfdi2"
2479 [(use (match_operand:DI 0 "register_operand" ""))
2480 (use (match_operand:TF 1 "general_operand" ""))]
2481 "TARGET_HAS_XFLOATING_LIBS"
2482 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2484 (define_expand "fixuns_trunctfdi2"
2485 [(use (match_operand:DI 0 "register_operand" ""))
2486 (use (match_operand:TF 1 "general_operand" ""))]
2487 "TARGET_HAS_XFLOATING_LIBS"
2488 "alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;")
2490 (define_insn "*floatdisf_ieee"
2491 [(set (match_operand:SF 0 "register_operand" "=&f")
2492 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2493 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2495 [(set_attr "type" "fadd")
2496 (set_attr "trap" "yes")
2497 (set_attr "round_suffix" "normal")
2498 (set_attr "trap_suffix" "sui")])
2500 (define_insn "floatdisf2"
2501 [(set (match_operand:SF 0 "register_operand" "=f")
2502 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2505 [(set_attr "type" "fadd")
2506 (set_attr "trap" "yes")
2507 (set_attr "round_suffix" "normal")
2508 (set_attr "trap_suffix" "sui")])
2510 (define_insn_and_split "*floatsisf2_ieee"
2511 [(set (match_operand:SF 0 "register_operand" "=&f")
2512 (float:SF (match_operand:SI 1 "memory_operand" "m")))
2513 (clobber (match_scratch:DI 2 "=&f"))
2514 (clobber (match_scratch:SF 3 "=&f"))]
2515 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2517 "&& reload_completed"
2518 [(set (match_dup 3) (match_dup 1))
2519 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2520 (set (match_dup 0) (float:SF (match_dup 2)))]
2522 operands[1] = adjust_address (operands[1], SFmode, 0);
2525 (define_insn_and_split "*floatsisf2"
2526 [(set (match_operand:SF 0 "register_operand" "=f")
2527 (float:SF (match_operand:SI 1 "memory_operand" "m")))]
2530 "&& reload_completed"
2531 [(set (match_dup 0) (match_dup 1))
2532 (set (match_dup 2) (unspec:DI [(match_dup 0)] UNSPEC_CVTLQ))
2533 (set (match_dup 0) (float:SF (match_dup 2)))]
2535 operands[1] = adjust_address (operands[1], SFmode, 0);
2536 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
2539 (define_insn "*floatdidf_ieee"
2540 [(set (match_operand:DF 0 "register_operand" "=&f")
2541 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2542 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2544 [(set_attr "type" "fadd")
2545 (set_attr "trap" "yes")
2546 (set_attr "round_suffix" "normal")
2547 (set_attr "trap_suffix" "sui")])
2549 (define_insn "floatdidf2"
2550 [(set (match_operand:DF 0 "register_operand" "=f")
2551 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2554 [(set_attr "type" "fadd")
2555 (set_attr "trap" "yes")
2556 (set_attr "round_suffix" "normal")
2557 (set_attr "trap_suffix" "sui")])
2559 (define_insn_and_split "*floatsidf2_ieee"
2560 [(set (match_operand:DF 0 "register_operand" "=&f")
2561 (float:DF (match_operand:SI 1 "memory_operand" "m")))
2562 (clobber (match_scratch:DI 2 "=&f"))
2563 (clobber (match_scratch:SF 3 "=&f"))]
2564 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2566 "&& reload_completed"
2567 [(set (match_dup 3) (match_dup 1))
2568 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2569 (set (match_dup 0) (float:DF (match_dup 2)))]
2571 operands[1] = adjust_address (operands[1], SFmode, 0);
2574 (define_insn_and_split "*floatsidf2"
2575 [(set (match_operand:DF 0 "register_operand" "=f")
2576 (float:DF (match_operand:SI 1 "memory_operand" "m")))]
2579 "&& reload_completed"
2580 [(set (match_dup 3) (match_dup 1))
2581 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2582 (set (match_dup 0) (float:DF (match_dup 2)))]
2584 operands[1] = adjust_address (operands[1], SFmode, 0);
2585 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
2586 operands[3] = gen_rtx_REG (SFmode, REGNO (operands[0]));
2589 (define_expand "floatditf2"
2590 [(use (match_operand:TF 0 "register_operand" ""))
2591 (use (match_operand:DI 1 "general_operand" ""))]
2592 "TARGET_HAS_XFLOATING_LIBS"
2593 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2595 (define_expand "floatunsdisf2"
2596 [(use (match_operand:SF 0 "register_operand" ""))
2597 (use (match_operand:DI 1 "register_operand" ""))]
2599 "alpha_emit_floatuns (operands); DONE;")
2601 (define_expand "floatunsdidf2"
2602 [(use (match_operand:DF 0 "register_operand" ""))
2603 (use (match_operand:DI 1 "register_operand" ""))]
2605 "alpha_emit_floatuns (operands); DONE;")
2607 (define_expand "floatunsditf2"
2608 [(use (match_operand:TF 0 "register_operand" ""))
2609 (use (match_operand:DI 1 "general_operand" ""))]
2610 "TARGET_HAS_XFLOATING_LIBS"
2611 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2613 (define_expand "extendsfdf2"
2614 [(set (match_operand:DF 0 "register_operand" "")
2615 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2618 if (alpha_fptm >= ALPHA_FPTM_SU)
2619 operands[1] = force_reg (SFmode, operands[1]);
2622 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2623 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2625 (define_insn "*extendsfdf2_ieee"
2626 [(set (match_operand:DF 0 "register_operand" "=&f")
2627 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2628 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2630 [(set_attr "type" "fadd")
2631 (set_attr "trap" "yes")])
2633 (define_insn "*extendsfdf2_internal"
2634 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2635 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2636 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2641 [(set_attr "type" "fcpys,fld,fst")])
2643 ;; Use register_operand for operand 1 to prevent compress_float_constant
2644 ;; from doing something silly. When optimizing we'll put things back
2646 (define_expand "extendsftf2"
2647 [(use (match_operand:TF 0 "register_operand" ""))
2648 (use (match_operand:SF 1 "register_operand" ""))]
2649 "TARGET_HAS_XFLOATING_LIBS"
2651 rtx tmp = gen_reg_rtx (DFmode);
2652 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2653 emit_insn (gen_extenddftf2 (operands[0], tmp));
2657 (define_expand "extenddftf2"
2658 [(use (match_operand:TF 0 "register_operand" ""))
2659 (use (match_operand:DF 1 "register_operand" ""))]
2660 "TARGET_HAS_XFLOATING_LIBS"
2661 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2663 (define_insn "*truncdfsf2_ieee"
2664 [(set (match_operand:SF 0 "register_operand" "=&f")
2665 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2666 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2668 [(set_attr "type" "fadd")
2669 (set_attr "trap" "yes")
2670 (set_attr "round_suffix" "normal")
2671 (set_attr "trap_suffix" "u_su_sui")])
2673 (define_insn "truncdfsf2"
2674 [(set (match_operand:SF 0 "register_operand" "=f")
2675 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2678 [(set_attr "type" "fadd")
2679 (set_attr "trap" "yes")
2680 (set_attr "round_suffix" "normal")
2681 (set_attr "trap_suffix" "u_su_sui")])
2683 (define_expand "trunctfdf2"
2684 [(use (match_operand:DF 0 "register_operand" ""))
2685 (use (match_operand:TF 1 "general_operand" ""))]
2686 "TARGET_HAS_XFLOATING_LIBS"
2687 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2689 (define_expand "trunctfsf2"
2690 [(use (match_operand:SF 0 "register_operand" ""))
2691 (use (match_operand:TF 1 "general_operand" ""))]
2692 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2694 rtx tmpf, sticky, arg, lo, hi;
2696 tmpf = gen_reg_rtx (DFmode);
2697 sticky = gen_reg_rtx (DImode);
2698 arg = copy_to_mode_reg (TFmode, operands[1]);
2699 lo = gen_lowpart (DImode, arg);
2700 hi = gen_highpart (DImode, arg);
2702 /* Convert the low word of the TFmode value into a sticky rounding bit,
2703 then or it into the low bit of the high word. This leaves the sticky
2704 bit at bit 48 of the fraction, which is representable in DFmode,
2705 which prevents rounding error in the final conversion to SFmode. */
2707 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2708 gen_rtx_NE (DImode, lo, const0_rtx)));
2709 emit_insn (gen_iordi3 (hi, hi, sticky));
2710 emit_insn (gen_trunctfdf2 (tmpf, arg));
2711 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2715 (define_insn "*divsf3_ieee"
2716 [(set (match_operand:SF 0 "register_operand" "=&f")
2717 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2718 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2719 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2720 "div%,%/ %R1,%R2,%0"
2721 [(set_attr "type" "fdiv")
2722 (set_attr "opsize" "si")
2723 (set_attr "trap" "yes")
2724 (set_attr "round_suffix" "normal")
2725 (set_attr "trap_suffix" "u_su_sui")])
2727 (define_insn "divsf3"
2728 [(set (match_operand:SF 0 "register_operand" "=f")
2729 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2730 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2732 "div%,%/ %R1,%R2,%0"
2733 [(set_attr "type" "fdiv")
2734 (set_attr "opsize" "si")
2735 (set_attr "trap" "yes")
2736 (set_attr "round_suffix" "normal")
2737 (set_attr "trap_suffix" "u_su_sui")])
2739 (define_insn "*divdf3_ieee"
2740 [(set (match_operand:DF 0 "register_operand" "=&f")
2741 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2742 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2743 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2744 "div%-%/ %R1,%R2,%0"
2745 [(set_attr "type" "fdiv")
2746 (set_attr "trap" "yes")
2747 (set_attr "round_suffix" "normal")
2748 (set_attr "trap_suffix" "u_su_sui")])
2750 (define_insn "divdf3"
2751 [(set (match_operand:DF 0 "register_operand" "=f")
2752 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2753 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2755 "div%-%/ %R1,%R2,%0"
2756 [(set_attr "type" "fdiv")
2757 (set_attr "trap" "yes")
2758 (set_attr "round_suffix" "normal")
2759 (set_attr "trap_suffix" "u_su_sui")])
2761 (define_insn "*divdf_ext1"
2762 [(set (match_operand:DF 0 "register_operand" "=f")
2763 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2764 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2765 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2766 "div%-%/ %R1,%R2,%0"
2767 [(set_attr "type" "fdiv")
2768 (set_attr "trap" "yes")
2769 (set_attr "round_suffix" "normal")
2770 (set_attr "trap_suffix" "u_su_sui")])
2772 (define_insn "*divdf_ext2"
2773 [(set (match_operand:DF 0 "register_operand" "=f")
2774 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2776 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2777 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2778 "div%-%/ %R1,%R2,%0"
2779 [(set_attr "type" "fdiv")
2780 (set_attr "trap" "yes")
2781 (set_attr "round_suffix" "normal")
2782 (set_attr "trap_suffix" "u_su_sui")])
2784 (define_insn "*divdf_ext3"
2785 [(set (match_operand:DF 0 "register_operand" "=f")
2786 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2787 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2788 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2789 "div%-%/ %R1,%R2,%0"
2790 [(set_attr "type" "fdiv")
2791 (set_attr "trap" "yes")
2792 (set_attr "round_suffix" "normal")
2793 (set_attr "trap_suffix" "u_su_sui")])
2795 (define_expand "divtf3"
2796 [(use (match_operand 0 "register_operand" ""))
2797 (use (match_operand 1 "general_operand" ""))
2798 (use (match_operand 2 "general_operand" ""))]
2799 "TARGET_HAS_XFLOATING_LIBS"
2800 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2802 (define_insn "*mulsf3_ieee"
2803 [(set (match_operand:SF 0 "register_operand" "=&f")
2804 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2805 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2806 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2807 "mul%,%/ %R1,%R2,%0"
2808 [(set_attr "type" "fmul")
2809 (set_attr "trap" "yes")
2810 (set_attr "round_suffix" "normal")
2811 (set_attr "trap_suffix" "u_su_sui")])
2813 (define_insn "mulsf3"
2814 [(set (match_operand:SF 0 "register_operand" "=f")
2815 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2816 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2818 "mul%,%/ %R1,%R2,%0"
2819 [(set_attr "type" "fmul")
2820 (set_attr "trap" "yes")
2821 (set_attr "round_suffix" "normal")
2822 (set_attr "trap_suffix" "u_su_sui")])
2824 (define_insn "*muldf3_ieee"
2825 [(set (match_operand:DF 0 "register_operand" "=&f")
2826 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2827 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2828 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2829 "mul%-%/ %R1,%R2,%0"
2830 [(set_attr "type" "fmul")
2831 (set_attr "trap" "yes")
2832 (set_attr "round_suffix" "normal")
2833 (set_attr "trap_suffix" "u_su_sui")])
2835 (define_insn "muldf3"
2836 [(set (match_operand:DF 0 "register_operand" "=f")
2837 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2838 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2840 "mul%-%/ %R1,%R2,%0"
2841 [(set_attr "type" "fmul")
2842 (set_attr "trap" "yes")
2843 (set_attr "round_suffix" "normal")
2844 (set_attr "trap_suffix" "u_su_sui")])
2846 (define_insn "*muldf_ext1"
2847 [(set (match_operand:DF 0 "register_operand" "=f")
2848 (mult:DF (float_extend:DF
2849 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2850 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2851 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2852 "mul%-%/ %R1,%R2,%0"
2853 [(set_attr "type" "fmul")
2854 (set_attr "trap" "yes")
2855 (set_attr "round_suffix" "normal")
2856 (set_attr "trap_suffix" "u_su_sui")])
2858 (define_insn "*muldf_ext2"
2859 [(set (match_operand:DF 0 "register_operand" "=f")
2860 (mult:DF (float_extend:DF
2861 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2863 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2864 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2865 "mul%-%/ %R1,%R2,%0"
2866 [(set_attr "type" "fmul")
2867 (set_attr "trap" "yes")
2868 (set_attr "round_suffix" "normal")
2869 (set_attr "trap_suffix" "u_su_sui")])
2871 (define_expand "multf3"
2872 [(use (match_operand 0 "register_operand" ""))
2873 (use (match_operand 1 "general_operand" ""))
2874 (use (match_operand 2 "general_operand" ""))]
2875 "TARGET_HAS_XFLOATING_LIBS"
2876 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2878 (define_insn "*subsf3_ieee"
2879 [(set (match_operand:SF 0 "register_operand" "=&f")
2880 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2881 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2882 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2883 "sub%,%/ %R1,%R2,%0"
2884 [(set_attr "type" "fadd")
2885 (set_attr "trap" "yes")
2886 (set_attr "round_suffix" "normal")
2887 (set_attr "trap_suffix" "u_su_sui")])
2889 (define_insn "subsf3"
2890 [(set (match_operand:SF 0 "register_operand" "=f")
2891 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2892 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2894 "sub%,%/ %R1,%R2,%0"
2895 [(set_attr "type" "fadd")
2896 (set_attr "trap" "yes")
2897 (set_attr "round_suffix" "normal")
2898 (set_attr "trap_suffix" "u_su_sui")])
2900 (define_insn "*subdf3_ieee"
2901 [(set (match_operand:DF 0 "register_operand" "=&f")
2902 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2903 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2904 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2905 "sub%-%/ %R1,%R2,%0"
2906 [(set_attr "type" "fadd")
2907 (set_attr "trap" "yes")
2908 (set_attr "round_suffix" "normal")
2909 (set_attr "trap_suffix" "u_su_sui")])
2911 (define_insn "subdf3"
2912 [(set (match_operand:DF 0 "register_operand" "=f")
2913 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2914 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2916 "sub%-%/ %R1,%R2,%0"
2917 [(set_attr "type" "fadd")
2918 (set_attr "trap" "yes")
2919 (set_attr "round_suffix" "normal")
2920 (set_attr "trap_suffix" "u_su_sui")])
2922 (define_insn "*subdf_ext1"
2923 [(set (match_operand:DF 0 "register_operand" "=f")
2924 (minus:DF (float_extend:DF
2925 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2926 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2927 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2928 "sub%-%/ %R1,%R2,%0"
2929 [(set_attr "type" "fadd")
2930 (set_attr "trap" "yes")
2931 (set_attr "round_suffix" "normal")
2932 (set_attr "trap_suffix" "u_su_sui")])
2934 (define_insn "*subdf_ext2"
2935 [(set (match_operand:DF 0 "register_operand" "=f")
2936 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2938 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2939 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2940 "sub%-%/ %R1,%R2,%0"
2941 [(set_attr "type" "fadd")
2942 (set_attr "trap" "yes")
2943 (set_attr "round_suffix" "normal")
2944 (set_attr "trap_suffix" "u_su_sui")])
2946 (define_insn "*subdf_ext3"
2947 [(set (match_operand:DF 0 "register_operand" "=f")
2948 (minus:DF (float_extend:DF
2949 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2951 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2952 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2953 "sub%-%/ %R1,%R2,%0"
2954 [(set_attr "type" "fadd")
2955 (set_attr "trap" "yes")
2956 (set_attr "round_suffix" "normal")
2957 (set_attr "trap_suffix" "u_su_sui")])
2959 (define_expand "subtf3"
2960 [(use (match_operand 0 "register_operand" ""))
2961 (use (match_operand 1 "general_operand" ""))
2962 (use (match_operand 2 "general_operand" ""))]
2963 "TARGET_HAS_XFLOATING_LIBS"
2964 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
2966 (define_insn "*sqrtsf2_ieee"
2967 [(set (match_operand:SF 0 "register_operand" "=&f")
2968 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2969 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2971 [(set_attr "type" "fsqrt")
2972 (set_attr "opsize" "si")
2973 (set_attr "trap" "yes")
2974 (set_attr "round_suffix" "normal")
2975 (set_attr "trap_suffix" "u_su_sui")])
2977 (define_insn "sqrtsf2"
2978 [(set (match_operand:SF 0 "register_operand" "=f")
2979 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2980 "TARGET_FP && TARGET_FIX"
2982 [(set_attr "type" "fsqrt")
2983 (set_attr "opsize" "si")
2984 (set_attr "trap" "yes")
2985 (set_attr "round_suffix" "normal")
2986 (set_attr "trap_suffix" "u_su_sui")])
2988 (define_insn "*sqrtdf2_ieee"
2989 [(set (match_operand:DF 0 "register_operand" "=&f")
2990 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2991 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2993 [(set_attr "type" "fsqrt")
2994 (set_attr "trap" "yes")
2995 (set_attr "round_suffix" "normal")
2996 (set_attr "trap_suffix" "u_su_sui")])
2998 (define_insn "sqrtdf2"
2999 [(set (match_operand:DF 0 "register_operand" "=f")
3000 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
3001 "TARGET_FP && TARGET_FIX"
3003 [(set_attr "type" "fsqrt")
3004 (set_attr "trap" "yes")
3005 (set_attr "round_suffix" "normal")
3006 (set_attr "trap_suffix" "u_su_sui")])
3008 ;; Next are all the integer comparisons, and conditional moves and branches
3009 ;; and some of the related define_expand's and define_split's.
3011 (define_insn "*setcc_internal"
3012 [(set (match_operand 0 "register_operand" "=r")
3013 (match_operator 1 "alpha_comparison_operator"
3014 [(match_operand:DI 2 "register_operand" "r")
3015 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
3016 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3017 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3018 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3020 [(set_attr "type" "icmp")])
3022 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
3023 ;; but that's non-canonical rtl and allowing that causes inefficiencies
3025 (define_insn "*setcc_swapped_internal"
3026 [(set (match_operand 0 "register_operand" "=r")
3027 (match_operator 1 "alpha_swapped_comparison_operator"
3028 [(match_operand:DI 2 "register_operand" "r")
3029 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
3030 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3031 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3032 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3034 [(set_attr "type" "icmp")])
3036 ;; Use match_operator rather than ne directly so that we can match
3037 ;; multiple integer modes.
3038 (define_insn "*setne_internal"
3039 [(set (match_operand 0 "register_operand" "=r")
3040 (match_operator 1 "signed_comparison_operator"
3041 [(match_operand:DI 2 "register_operand" "r")
3043 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3044 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3045 && GET_CODE (operands[1]) == NE
3046 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3048 [(set_attr "type" "icmp")])
3050 ;; The mode folding trick can't be used with const_int operands, since
3051 ;; reload needs to know the proper mode.
3053 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
3054 ;; in order to create more pairs of constants. As long as we're allowing
3055 ;; two constants at the same time, and will have to reload one of them...
3057 (define_insn "*movqicc_internal"
3058 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
3060 (match_operator 2 "signed_comparison_operator"
3061 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3062 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3063 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
3064 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
3065 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3071 [(set_attr "type" "icmov")])
3073 (define_insn "*movhicc_internal"
3074 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
3076 (match_operator 2 "signed_comparison_operator"
3077 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3078 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3079 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
3080 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
3081 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3087 [(set_attr "type" "icmov")])
3089 (define_insn "*movsicc_internal"
3090 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
3092 (match_operator 2 "signed_comparison_operator"
3093 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3094 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3095 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
3096 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
3097 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3103 [(set_attr "type" "icmov")])
3105 (define_insn "*movdicc_internal"
3106 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
3108 (match_operator 2 "signed_comparison_operator"
3109 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3110 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3111 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
3112 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
3113 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3119 [(set_attr "type" "icmov")])
3121 (define_insn "*movqicc_lbc"
3122 [(set (match_operand:QI 0 "register_operand" "=r,r")
3124 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3128 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3129 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3134 [(set_attr "type" "icmov")])
3136 (define_insn "*movhicc_lbc"
3137 [(set (match_operand:HI 0 "register_operand" "=r,r")
3139 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3143 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3144 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3149 [(set_attr "type" "icmov")])
3151 (define_insn "*movsicc_lbc"
3152 [(set (match_operand:SI 0 "register_operand" "=r,r")
3154 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3158 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3159 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3164 [(set_attr "type" "icmov")])
3166 (define_insn "*movdicc_lbc"
3167 [(set (match_operand:DI 0 "register_operand" "=r,r")
3169 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3173 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3174 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3179 [(set_attr "type" "icmov")])
3181 (define_insn "*movqicc_lbs"
3182 [(set (match_operand:QI 0 "register_operand" "=r,r")
3184 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3188 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3189 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3194 [(set_attr "type" "icmov")])
3196 (define_insn "*movhicc_lbs"
3197 [(set (match_operand:HI 0 "register_operand" "=r,r")
3199 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3203 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3204 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3209 [(set_attr "type" "icmov")])
3211 (define_insn "*movsicc_lbs"
3212 [(set (match_operand:SI 0 "register_operand" "=r,r")
3214 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3218 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3219 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3224 [(set_attr "type" "icmov")])
3226 (define_insn "*movdicc_lbs"
3227 [(set (match_operand:DI 0 "register_operand" "=r,r")
3229 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3233 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3234 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3239 [(set_attr "type" "icmov")])
3241 ;; For ABS, we have two choices, depending on whether the input and output
3242 ;; registers are the same or not.
3243 (define_expand "absdi2"
3244 [(set (match_operand:DI 0 "register_operand" "")
3245 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3248 if (rtx_equal_p (operands[0], operands[1]))
3249 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
3251 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
3255 (define_expand "absdi2_same"
3256 [(set (match_operand:DI 1 "register_operand" "")
3257 (neg:DI (match_operand:DI 0 "register_operand" "")))
3259 (if_then_else:DI (ge (match_dup 0) (const_int 0))
3265 (define_expand "absdi2_diff"
3266 [(set (match_operand:DI 0 "register_operand" "")
3267 (neg:DI (match_operand:DI 1 "register_operand" "")))
3269 (if_then_else:DI (lt (match_dup 1) (const_int 0))
3276 [(set (match_operand:DI 0 "register_operand" "")
3277 (abs:DI (match_dup 0)))
3278 (clobber (match_operand:DI 1 "register_operand" ""))]
3280 [(set (match_dup 1) (neg:DI (match_dup 0)))
3281 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
3282 (match_dup 0) (match_dup 1)))]
3286 [(set (match_operand:DI 0 "register_operand" "")
3287 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3288 "! rtx_equal_p (operands[0], operands[1])"
3289 [(set (match_dup 0) (neg:DI (match_dup 1)))
3290 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
3291 (match_dup 0) (match_dup 1)))]
3295 [(set (match_operand:DI 0 "register_operand" "")
3296 (neg:DI (abs:DI (match_dup 0))))
3297 (clobber (match_operand:DI 1 "register_operand" ""))]
3299 [(set (match_dup 1) (neg:DI (match_dup 0)))
3300 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
3301 (match_dup 0) (match_dup 1)))]
3305 [(set (match_operand:DI 0 "register_operand" "")
3306 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
3307 "! rtx_equal_p (operands[0], operands[1])"
3308 [(set (match_dup 0) (neg:DI (match_dup 1)))
3309 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
3310 (match_dup 0) (match_dup 1)))]
3313 (define_insn "sminqi3"
3314 [(set (match_operand:QI 0 "register_operand" "=r")
3315 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3316 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3319 [(set_attr "type" "mvi")])
3321 (define_insn "uminqi3"
3322 [(set (match_operand:QI 0 "register_operand" "=r")
3323 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3324 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3327 [(set_attr "type" "mvi")])
3329 (define_insn "smaxqi3"
3330 [(set (match_operand:QI 0 "register_operand" "=r")
3331 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3332 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3335 [(set_attr "type" "mvi")])
3337 (define_insn "umaxqi3"
3338 [(set (match_operand:QI 0 "register_operand" "=r")
3339 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3340 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3343 [(set_attr "type" "mvi")])
3345 (define_insn "sminhi3"
3346 [(set (match_operand:HI 0 "register_operand" "=r")
3347 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3348 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3351 [(set_attr "type" "mvi")])
3353 (define_insn "uminhi3"
3354 [(set (match_operand:HI 0 "register_operand" "=r")
3355 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3356 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3359 [(set_attr "type" "mvi")])
3361 (define_insn "smaxhi3"
3362 [(set (match_operand:HI 0 "register_operand" "=r")
3363 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3364 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3367 [(set_attr "type" "mvi")])
3369 (define_insn "umaxhi3"
3370 [(set (match_operand:HI 0 "register_operand" "=r")
3371 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3372 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3375 [(set_attr "type" "mvi")])
3377 (define_expand "smaxdi3"
3379 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3380 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3381 (set (match_operand:DI 0 "register_operand" "")
3382 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3383 (match_dup 1) (match_dup 2)))]
3385 { operands[3] = gen_reg_rtx (DImode); })
3388 [(set (match_operand:DI 0 "register_operand" "")
3389 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3390 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3391 (clobber (match_operand:DI 3 "register_operand" ""))]
3392 "operands[2] != const0_rtx"
3393 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3394 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3395 (match_dup 1) (match_dup 2)))]
3398 (define_insn "*smax_const0"
3399 [(set (match_operand:DI 0 "register_operand" "=r")
3400 (smax:DI (match_operand:DI 1 "register_operand" "0")
3404 [(set_attr "type" "icmov")])
3406 (define_expand "smindi3"
3408 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3409 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3410 (set (match_operand:DI 0 "register_operand" "")
3411 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3412 (match_dup 1) (match_dup 2)))]
3414 { operands[3] = gen_reg_rtx (DImode); })
3417 [(set (match_operand:DI 0 "register_operand" "")
3418 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3419 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3420 (clobber (match_operand:DI 3 "register_operand" ""))]
3421 "operands[2] != const0_rtx"
3422 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3423 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3424 (match_dup 1) (match_dup 2)))]
3427 (define_insn "*smin_const0"
3428 [(set (match_operand:DI 0 "register_operand" "=r")
3429 (smin:DI (match_operand:DI 1 "register_operand" "0")
3433 [(set_attr "type" "icmov")])
3435 (define_expand "umaxdi3"
3437 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3438 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3439 (set (match_operand:DI 0 "register_operand" "")
3440 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3441 (match_dup 1) (match_dup 2)))]
3443 "operands[3] = gen_reg_rtx (DImode);")
3446 [(set (match_operand:DI 0 "register_operand" "")
3447 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3448 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3449 (clobber (match_operand:DI 3 "register_operand" ""))]
3450 "operands[2] != const0_rtx"
3451 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3452 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3453 (match_dup 1) (match_dup 2)))]
3456 (define_expand "umindi3"
3458 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3459 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3460 (set (match_operand:DI 0 "register_operand" "")
3461 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3462 (match_dup 1) (match_dup 2)))]
3464 "operands[3] = gen_reg_rtx (DImode);")
3467 [(set (match_operand:DI 0 "register_operand" "")
3468 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3469 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3470 (clobber (match_operand:DI 3 "register_operand" ""))]
3471 "operands[2] != const0_rtx"
3472 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3473 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3474 (match_dup 1) (match_dup 2)))]
3477 (define_insn "*bcc_normal"
3480 (match_operator 1 "signed_comparison_operator"
3481 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3483 (label_ref (match_operand 0 "" ""))
3487 [(set_attr "type" "ibr")])
3489 (define_insn "*bcc_reverse"
3492 (match_operator 1 "signed_comparison_operator"
3493 [(match_operand:DI 2 "register_operand" "r")
3497 (label_ref (match_operand 0 "" ""))))]
3500 [(set_attr "type" "ibr")])
3502 (define_insn "*blbs_normal"
3505 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3509 (label_ref (match_operand 0 "" ""))
3513 [(set_attr "type" "ibr")])
3515 (define_insn "*blbc_normal"
3518 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3522 (label_ref (match_operand 0 "" ""))
3526 [(set_attr "type" "ibr")])
3532 (match_operator 1 "comparison_operator"
3533 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3535 (match_operand:DI 3 "const_int_operand" ""))
3537 (label_ref (match_operand 0 "" ""))
3539 (clobber (match_operand:DI 4 "register_operand" ""))])]
3540 "INTVAL (operands[3]) != 0"
3542 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3544 (if_then_else (match_op_dup 1
3545 [(zero_extract:DI (match_dup 4)
3549 (label_ref (match_dup 0))
3553 ;; The following are the corresponding floating-point insns. Recall
3554 ;; we need to have variants that expand the arguments from SFmode
3557 (define_insn "*cmpdf_ieee"
3558 [(set (match_operand:DF 0 "register_operand" "=&f")
3559 (match_operator:DF 1 "alpha_fp_comparison_operator"
3560 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3561 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3562 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3563 "cmp%-%C1%/ %R2,%R3,%0"
3564 [(set_attr "type" "fadd")
3565 (set_attr "trap" "yes")
3566 (set_attr "trap_suffix" "su")])
3568 (define_insn "*cmpdf_internal"
3569 [(set (match_operand:DF 0 "register_operand" "=f")
3570 (match_operator:DF 1 "alpha_fp_comparison_operator"
3571 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3572 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3573 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3574 "cmp%-%C1%/ %R2,%R3,%0"
3575 [(set_attr "type" "fadd")
3576 (set_attr "trap" "yes")
3577 (set_attr "trap_suffix" "su")])
3579 (define_insn "*cmpdf_ieee_ext1"
3580 [(set (match_operand:DF 0 "register_operand" "=&f")
3581 (match_operator:DF 1 "alpha_fp_comparison_operator"
3583 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3584 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3585 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3586 "cmp%-%C1%/ %R2,%R3,%0"
3587 [(set_attr "type" "fadd")
3588 (set_attr "trap" "yes")
3589 (set_attr "trap_suffix" "su")])
3591 (define_insn "*cmpdf_ext1"
3592 [(set (match_operand:DF 0 "register_operand" "=f")
3593 (match_operator:DF 1 "alpha_fp_comparison_operator"
3595 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3596 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3597 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3598 "cmp%-%C1%/ %R2,%R3,%0"
3599 [(set_attr "type" "fadd")
3600 (set_attr "trap" "yes")
3601 (set_attr "trap_suffix" "su")])
3603 (define_insn "*cmpdf_ieee_ext2"
3604 [(set (match_operand:DF 0 "register_operand" "=&f")
3605 (match_operator:DF 1 "alpha_fp_comparison_operator"
3606 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3608 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3609 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3610 "cmp%-%C1%/ %R2,%R3,%0"
3611 [(set_attr "type" "fadd")
3612 (set_attr "trap" "yes")
3613 (set_attr "trap_suffix" "su")])
3615 (define_insn "*cmpdf_ext2"
3616 [(set (match_operand:DF 0 "register_operand" "=f")
3617 (match_operator:DF 1 "alpha_fp_comparison_operator"
3618 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3620 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3621 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3622 "cmp%-%C1%/ %R2,%R3,%0"
3623 [(set_attr "type" "fadd")
3624 (set_attr "trap" "yes")
3625 (set_attr "trap_suffix" "su")])
3627 (define_insn "*cmpdf_ieee_ext3"
3628 [(set (match_operand:DF 0 "register_operand" "=&f")
3629 (match_operator:DF 1 "alpha_fp_comparison_operator"
3631 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3633 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3634 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3635 "cmp%-%C1%/ %R2,%R3,%0"
3636 [(set_attr "type" "fadd")
3637 (set_attr "trap" "yes")
3638 (set_attr "trap_suffix" "su")])
3640 (define_insn "*cmpdf_ext3"
3641 [(set (match_operand:DF 0 "register_operand" "=f")
3642 (match_operator:DF 1 "alpha_fp_comparison_operator"
3644 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3646 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3647 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3648 "cmp%-%C1%/ %R2,%R3,%0"
3649 [(set_attr "type" "fadd")
3650 (set_attr "trap" "yes")
3651 (set_attr "trap_suffix" "su")])
3653 (define_insn "*movdfcc_internal"
3654 [(set (match_operand:DF 0 "register_operand" "=f,f")
3656 (match_operator 3 "signed_comparison_operator"
3657 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3658 (match_operand:DF 2 "const0_operand" "G,G")])
3659 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3660 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3664 fcmov%D3 %R4,%R5,%0"
3665 [(set_attr "type" "fcmov")])
3667 (define_insn "*movsfcc_internal"
3668 [(set (match_operand:SF 0 "register_operand" "=f,f")
3670 (match_operator 3 "signed_comparison_operator"
3671 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3672 (match_operand:DF 2 "const0_operand" "G,G")])
3673 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3674 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3678 fcmov%D3 %R4,%R5,%0"
3679 [(set_attr "type" "fcmov")])
3681 (define_insn "*movdfcc_ext1"
3682 [(set (match_operand:DF 0 "register_operand" "=f,f")
3684 (match_operator 3 "signed_comparison_operator"
3685 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3686 (match_operand:DF 2 "const0_operand" "G,G")])
3687 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3688 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3692 fcmov%D3 %R4,%R5,%0"
3693 [(set_attr "type" "fcmov")])
3695 (define_insn "*movdfcc_ext2"
3696 [(set (match_operand:DF 0 "register_operand" "=f,f")
3698 (match_operator 3 "signed_comparison_operator"
3700 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3701 (match_operand:DF 2 "const0_operand" "G,G")])
3702 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3703 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3707 fcmov%D3 %R4,%R5,%0"
3708 [(set_attr "type" "fcmov")])
3710 (define_insn "*movdfcc_ext3"
3711 [(set (match_operand:SF 0 "register_operand" "=f,f")
3713 (match_operator 3 "signed_comparison_operator"
3715 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3716 (match_operand:DF 2 "const0_operand" "G,G")])
3717 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3718 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3722 fcmov%D3 %R4,%R5,%0"
3723 [(set_attr "type" "fcmov")])
3725 (define_insn "*movdfcc_ext4"
3726 [(set (match_operand:DF 0 "register_operand" "=f,f")
3728 (match_operator 3 "signed_comparison_operator"
3730 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3731 (match_operand:DF 2 "const0_operand" "G,G")])
3732 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3733 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3737 fcmov%D3 %R4,%R5,%0"
3738 [(set_attr "type" "fcmov")])
3740 (define_expand "maxdf3"
3742 (le:DF (match_operand:DF 1 "reg_or_0_operand" "")
3743 (match_operand:DF 2 "reg_or_0_operand" "")))
3744 (set (match_operand:DF 0 "register_operand" "")
3745 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3746 (match_dup 1) (match_dup 2)))]
3749 operands[3] = gen_reg_rtx (DFmode);
3750 operands[4] = CONST0_RTX (DFmode);
3753 (define_expand "mindf3"
3755 (lt:DF (match_operand:DF 1 "reg_or_0_operand" "")
3756 (match_operand:DF 2 "reg_or_0_operand" "")))
3757 (set (match_operand:DF 0 "register_operand" "")
3758 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3759 (match_dup 1) (match_dup 2)))]
3762 operands[3] = gen_reg_rtx (DFmode);
3763 operands[4] = CONST0_RTX (DFmode);
3766 (define_expand "maxsf3"
3768 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3769 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3770 (set (match_operand:SF 0 "register_operand" "")
3771 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3772 (match_dup 1) (match_dup 2)))]
3775 operands[3] = gen_reg_rtx (DFmode);
3776 operands[4] = CONST0_RTX (DFmode);
3779 (define_expand "minsf3"
3781 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3782 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3783 (set (match_operand:SF 0 "register_operand" "")
3784 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3785 (match_dup 1) (match_dup 2)))]
3788 operands[3] = gen_reg_rtx (DFmode);
3789 operands[4] = CONST0_RTX (DFmode);
3792 (define_insn "*fbcc_normal"
3795 (match_operator 1 "signed_comparison_operator"
3796 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3797 (match_operand:DF 3 "const0_operand" "G")])
3798 (label_ref (match_operand 0 "" ""))
3802 [(set_attr "type" "fbr")])
3804 (define_insn "*fbcc_ext_normal"
3807 (match_operator 1 "signed_comparison_operator"
3809 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3810 (match_operand:DF 3 "const0_operand" "G")])
3811 (label_ref (match_operand 0 "" ""))
3815 [(set_attr "type" "fbr")])
3817 ;; These are the main define_expand's used to make conditional branches
3820 (define_expand "cmpdf"
3821 [(set (cc0) (compare (match_operand:DF 0 "reg_or_0_operand" "")
3822 (match_operand:DF 1 "reg_or_0_operand" "")))]
3825 alpha_compare.op0 = operands[0];
3826 alpha_compare.op1 = operands[1];
3827 alpha_compare.fp_p = 1;
3831 (define_expand "cmptf"
3832 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3833 (match_operand:TF 1 "general_operand" "")))]
3834 "TARGET_HAS_XFLOATING_LIBS"
3836 alpha_compare.op0 = operands[0];
3837 alpha_compare.op1 = operands[1];
3838 alpha_compare.fp_p = 1;
3842 (define_expand "cmpdi"
3843 [(set (cc0) (compare (match_operand:DI 0 "some_operand" "")
3844 (match_operand:DI 1 "some_operand" "")))]
3847 alpha_compare.op0 = operands[0];
3848 alpha_compare.op1 = operands[1];
3849 alpha_compare.fp_p = 0;
3853 (define_expand "beq"
3855 (if_then_else (match_dup 1)
3856 (label_ref (match_operand 0 "" ""))
3859 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3861 (define_expand "bne"
3863 (if_then_else (match_dup 1)
3864 (label_ref (match_operand 0 "" ""))
3867 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3869 (define_expand "blt"
3871 (if_then_else (match_dup 1)
3872 (label_ref (match_operand 0 "" ""))
3875 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3877 (define_expand "ble"
3879 (if_then_else (match_dup 1)
3880 (label_ref (match_operand 0 "" ""))
3883 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3885 (define_expand "bgt"
3887 (if_then_else (match_dup 1)
3888 (label_ref (match_operand 0 "" ""))
3891 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3893 (define_expand "bge"
3895 (if_then_else (match_dup 1)
3896 (label_ref (match_operand 0 "" ""))
3899 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3901 (define_expand "bltu"
3903 (if_then_else (match_dup 1)
3904 (label_ref (match_operand 0 "" ""))
3907 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3909 (define_expand "bleu"
3911 (if_then_else (match_dup 1)
3912 (label_ref (match_operand 0 "" ""))
3915 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3917 (define_expand "bgtu"
3919 (if_then_else (match_dup 1)
3920 (label_ref (match_operand 0 "" ""))
3923 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3925 (define_expand "bgeu"
3927 (if_then_else (match_dup 1)
3928 (label_ref (match_operand 0 "" ""))
3931 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3933 (define_expand "bunordered"
3935 (if_then_else (match_dup 1)
3936 (label_ref (match_operand 0 "" ""))
3939 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
3941 (define_expand "bordered"
3943 (if_then_else (match_dup 1)
3944 (label_ref (match_operand 0 "" ""))
3947 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
3949 (define_expand "seq"
3950 [(set (match_operand:DI 0 "register_operand" "")
3953 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
3955 (define_expand "sne"
3956 [(set (match_operand:DI 0 "register_operand" "")
3959 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
3961 (define_expand "slt"
3962 [(set (match_operand:DI 0 "register_operand" "")
3965 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
3967 (define_expand "sle"
3968 [(set (match_operand:DI 0 "register_operand" "")
3971 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
3973 (define_expand "sgt"
3974 [(set (match_operand:DI 0 "register_operand" "")
3977 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
3979 (define_expand "sge"
3980 [(set (match_operand:DI 0 "register_operand" "")
3983 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
3985 (define_expand "sltu"
3986 [(set (match_operand:DI 0 "register_operand" "")
3989 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
3991 (define_expand "sleu"
3992 [(set (match_operand:DI 0 "register_operand" "")
3995 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
3997 (define_expand "sgtu"
3998 [(set (match_operand:DI 0 "register_operand" "")
4001 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
4003 (define_expand "sgeu"
4004 [(set (match_operand:DI 0 "register_operand" "")
4007 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
4009 (define_expand "sunordered"
4010 [(set (match_operand:DI 0 "register_operand" "")
4013 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
4015 (define_expand "sordered"
4016 [(set (match_operand:DI 0 "register_operand" "")
4019 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
4021 ;; These are the main define_expand's used to make conditional moves.
4023 (define_expand "movsicc"
4024 [(set (match_operand:SI 0 "register_operand" "")
4025 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4026 (match_operand:SI 2 "reg_or_8bit_operand" "")
4027 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
4030 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
4034 (define_expand "movdicc"
4035 [(set (match_operand:DI 0 "register_operand" "")
4036 (if_then_else:DI (match_operand 1 "comparison_operator" "")
4037 (match_operand:DI 2 "reg_or_8bit_operand" "")
4038 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
4041 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
4045 (define_expand "movsfcc"
4046 [(set (match_operand:SF 0 "register_operand" "")
4047 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4048 (match_operand:SF 2 "reg_or_8bit_operand" "")
4049 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
4052 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
4056 (define_expand "movdfcc"
4057 [(set (match_operand:DF 0 "register_operand" "")
4058 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4059 (match_operand:DF 2 "reg_or_8bit_operand" "")
4060 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
4063 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
4067 ;; These define_split definitions are used in cases when comparisons have
4068 ;; not be stated in the correct way and we need to reverse the second
4069 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
4070 ;; comparison that tests the result being reversed. We have one define_split
4071 ;; for each use of a comparison. They do not match valid insns and need
4072 ;; not generate valid insns.
4074 ;; We can also handle equality comparisons (and inequality comparisons in
4075 ;; cases where the resulting add cannot overflow) by doing an add followed by
4076 ;; a comparison with zero. This is faster since the addition takes one
4077 ;; less cycle than a compare when feeding into a conditional move.
4078 ;; For this case, we also have an SImode pattern since we can merge the add
4079 ;; and sign extend and the order doesn't matter.
4081 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
4082 ;; operation could have been generated.
4085 [(set (match_operand:DI 0 "register_operand" "")
4087 (match_operator 1 "comparison_operator"
4088 [(match_operand:DI 2 "reg_or_0_operand" "")
4089 (match_operand:DI 3 "reg_or_cint_operand" "")])
4090 (match_operand:DI 4 "reg_or_cint_operand" "")
4091 (match_operand:DI 5 "reg_or_cint_operand" "")))
4092 (clobber (match_operand:DI 6 "register_operand" ""))]
4093 "operands[3] != const0_rtx"
4094 [(set (match_dup 6) (match_dup 7))
4096 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4098 enum rtx_code code = GET_CODE (operands[1]);
4099 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4101 /* If we are comparing for equality with a constant and that constant
4102 appears in the arm when the register equals the constant, use the
4103 register since that is more likely to match (and to produce better code
4106 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
4107 && rtx_equal_p (operands[4], operands[3]))
4108 operands[4] = operands[2];
4110 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
4111 && rtx_equal_p (operands[5], operands[3]))
4112 operands[5] = operands[2];
4114 if (code == NE || code == EQ
4115 || (extended_count (operands[2], DImode, unsignedp) >= 1
4116 && extended_count (operands[3], DImode, unsignedp) >= 1))
4118 if (GET_CODE (operands[3]) == CONST_INT)
4119 operands[7] = gen_rtx_PLUS (DImode, operands[2],
4120 GEN_INT (- INTVAL (operands[3])));
4122 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4124 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
4127 else if (code == EQ || code == LE || code == LT
4128 || code == LEU || code == LTU)
4130 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4131 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
4135 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4136 operands[2], operands[3]);
4137 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
4142 [(set (match_operand:DI 0 "register_operand" "")
4144 (match_operator 1 "comparison_operator"
4145 [(match_operand:SI 2 "reg_or_0_operand" "")
4146 (match_operand:SI 3 "reg_or_cint_operand" "")])
4147 (match_operand:DI 4 "reg_or_8bit_operand" "")
4148 (match_operand:DI 5 "reg_or_8bit_operand" "")))
4149 (clobber (match_operand:DI 6 "register_operand" ""))]
4150 "operands[3] != const0_rtx
4151 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4152 [(set (match_dup 6) (match_dup 7))
4154 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4156 enum rtx_code code = GET_CODE (operands[1]);
4157 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4160 if ((code != NE && code != EQ
4161 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
4162 && extended_count (operands[3], DImode, unsignedp) >= 1)))
4165 if (GET_CODE (operands[3]) == CONST_INT)
4166 tem = gen_rtx_PLUS (SImode, operands[2],
4167 GEN_INT (- INTVAL (operands[3])));
4169 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4171 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
4172 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4173 operands[6], const0_rtx);
4176 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
4179 [(set (match_operand 0 "register_operand" "")
4180 (if_then_else (match_operator 1 "signed_comparison_operator"
4181 [(match_operand:DI 2 "reg_or_0_operand" "")
4183 (match_operand 3 "const_int_operand" "")
4184 (match_operand 4 "const_int_operand" "")))]
4188 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
4189 operands[2], operands[3], operands[4]))
4195 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
4196 ;; Oh well, we match it in movcc, so it must be partially our fault.
4198 [(set (match_operand 0 "register_operand" "")
4199 (if_then_else (match_operator 1 "signed_comparison_operator"
4201 (match_operand:DI 2 "reg_or_0_operand" "")])
4202 (match_operand 3 "const_int_operand" "")
4203 (match_operand 4 "const_int_operand" "")))]
4207 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
4208 operands[0], operands[2], operands[3],
4215 (define_insn_and_split "*cmp_sadd_di"
4216 [(set (match_operand:DI 0 "register_operand" "=r")
4217 (plus:DI (if_then_else:DI
4218 (match_operator 1 "alpha_zero_comparison_operator"
4219 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4221 (match_operand:DI 3 "const48_operand" "I")
4223 (match_operand:DI 4 "sext_add_operand" "rIO")))
4224 (clobber (match_scratch:DI 5 "=r"))]
4227 "! no_new_pseudos || reload_completed"
4229 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4231 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4234 if (! no_new_pseudos)
4235 operands[5] = gen_reg_rtx (DImode);
4236 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4237 operands[5] = operands[0];
4240 (define_insn_and_split "*cmp_sadd_si"
4241 [(set (match_operand:SI 0 "register_operand" "=r")
4242 (plus:SI (if_then_else:SI
4243 (match_operator 1 "alpha_zero_comparison_operator"
4244 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4246 (match_operand:SI 3 "const48_operand" "I")
4248 (match_operand:SI 4 "sext_add_operand" "rIO")))
4249 (clobber (match_scratch:SI 5 "=r"))]
4252 "! no_new_pseudos || reload_completed"
4254 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4256 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4259 if (! no_new_pseudos)
4260 operands[5] = gen_reg_rtx (DImode);
4261 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4262 operands[5] = operands[0];
4265 (define_insn_and_split "*cmp_sadd_sidi"
4266 [(set (match_operand:DI 0 "register_operand" "=r")
4268 (plus:SI (if_then_else:SI
4269 (match_operator 1 "alpha_zero_comparison_operator"
4270 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4272 (match_operand:SI 3 "const48_operand" "I")
4274 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4275 (clobber (match_scratch:SI 5 "=r"))]
4278 "! no_new_pseudos || reload_completed"
4280 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4282 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4285 if (! no_new_pseudos)
4286 operands[5] = gen_reg_rtx (DImode);
4287 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4288 operands[5] = operands[0];
4291 (define_insn_and_split "*cmp_ssub_di"
4292 [(set (match_operand:DI 0 "register_operand" "=r")
4293 (minus:DI (if_then_else:DI
4294 (match_operator 1 "alpha_zero_comparison_operator"
4295 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4297 (match_operand:DI 3 "const48_operand" "I")
4299 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4300 (clobber (match_scratch:DI 5 "=r"))]
4303 "! no_new_pseudos || reload_completed"
4305 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4307 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4310 if (! no_new_pseudos)
4311 operands[5] = gen_reg_rtx (DImode);
4312 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4313 operands[5] = operands[0];
4316 (define_insn_and_split "*cmp_ssub_si"
4317 [(set (match_operand:SI 0 "register_operand" "=r")
4318 (minus:SI (if_then_else:SI
4319 (match_operator 1 "alpha_zero_comparison_operator"
4320 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4322 (match_operand:SI 3 "const48_operand" "I")
4324 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4325 (clobber (match_scratch:SI 5 "=r"))]
4328 "! no_new_pseudos || reload_completed"
4330 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4332 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4335 if (! no_new_pseudos)
4336 operands[5] = gen_reg_rtx (DImode);
4337 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4338 operands[5] = operands[0];
4341 (define_insn_and_split "*cmp_ssub_sidi"
4342 [(set (match_operand:DI 0 "register_operand" "=r")
4344 (minus:SI (if_then_else:SI
4345 (match_operator 1 "alpha_zero_comparison_operator"
4346 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4348 (match_operand:SI 3 "const48_operand" "I")
4350 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4351 (clobber (match_scratch:SI 5 "=r"))]
4354 "! no_new_pseudos || reload_completed"
4356 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4358 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4361 if (! no_new_pseudos)
4362 operands[5] = gen_reg_rtx (DImode);
4363 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4364 operands[5] = operands[0];
4367 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4368 ;; work differently, so we have different patterns for each.
4370 ;; On Unicos/Mk a call information word (CIW) must be generated for each
4371 ;; call. The CIW contains information about arguments passed in registers
4372 ;; and is stored in the caller's SSIB. Its offset relative to the beginning
4373 ;; of the SSIB is passed in $25. Handling this properly is quite complicated
4374 ;; in the presence of inlining since the CIWs for calls performed by the
4375 ;; inlined function must be stored in the SSIB of the function it is inlined
4376 ;; into as well. We encode the CIW in an unspec and append it to the list
4377 ;; of the CIWs for the current function only when the instruction for loading
4378 ;; $25 is generated.
4380 (define_expand "call"
4381 [(use (match_operand:DI 0 "" ""))
4382 (use (match_operand 1 "" ""))
4383 (use (match_operand 2 "" ""))
4384 (use (match_operand 3 "" ""))]
4387 if (TARGET_ABI_WINDOWS_NT)
4388 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4389 else if (TARGET_ABI_OPEN_VMS)
4390 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4391 else if (TARGET_ABI_UNICOSMK)
4392 emit_call_insn (gen_call_umk (operands[0], operands[2]));
4394 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4398 (define_expand "sibcall"
4399 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4400 (match_operand 1 "" ""))
4401 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4404 if (GET_CODE (operands[0]) != MEM)
4406 operands[0] = XEXP (operands[0], 0);
4409 (define_expand "call_osf"
4410 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4411 (match_operand 1 "" ""))
4413 (clobber (reg:DI 26))])]
4416 if (GET_CODE (operands[0]) != MEM)
4419 operands[0] = XEXP (operands[0], 0);
4420 if (! call_operand (operands[0], Pmode))
4421 operands[0] = copy_to_mode_reg (Pmode, operands[0]);
4424 (define_expand "call_nt"
4425 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4426 (match_operand 1 "" ""))
4427 (clobber (reg:DI 26))])]
4430 if (GET_CODE (operands[0]) != MEM)
4433 operands[0] = XEXP (operands[0], 0);
4434 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4435 operands[0] = force_reg (DImode, operands[0]);
4438 ;; Calls on Unicos/Mk are always indirect.
4439 ;; op 0: symbol ref for called function
4440 ;; op 1: CIW for $25 represented by an unspec
4442 (define_expand "call_umk"
4443 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4444 (match_operand 1 "" ""))
4446 (clobber (reg:DI 26))])]
4449 if (GET_CODE (operands[0]) != MEM)
4452 /* Always load the address of the called function into a register;
4453 load the CIW in $25. */
4455 operands[0] = XEXP (operands[0], 0);
4456 if (GET_CODE (operands[0]) != REG)
4457 operands[0] = force_reg (DImode, operands[0]);
4459 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4463 ;; call openvms/alpha
4464 ;; op 0: symbol ref for called function
4465 ;; op 1: next_arg_reg (argument information value for R25)
4467 (define_expand "call_vms"
4468 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4469 (match_operand 1 "" ""))
4473 (clobber (reg:DI 27))])]
4476 if (GET_CODE (operands[0]) != MEM)
4479 operands[0] = XEXP (operands[0], 0);
4481 /* Always load AI with argument information, then handle symbolic and
4482 indirect call differently. Load RA and set operands[2] to PV in
4485 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4486 if (GET_CODE (operands[0]) == SYMBOL_REF)
4488 alpha_need_linkage (XSTR (operands[0], 0), 0);
4490 operands[2] = const0_rtx;
4494 emit_move_insn (gen_rtx_REG (Pmode, 26),
4495 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4496 operands[2] = operands[0];
4501 (define_expand "call_value"
4502 [(use (match_operand 0 "" ""))
4503 (use (match_operand:DI 1 "" ""))
4504 (use (match_operand 2 "" ""))
4505 (use (match_operand 3 "" ""))
4506 (use (match_operand 4 "" ""))]
4509 if (TARGET_ABI_WINDOWS_NT)
4510 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4511 else if (TARGET_ABI_OPEN_VMS)
4512 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4514 else if (TARGET_ABI_UNICOSMK)
4515 emit_call_insn (gen_call_value_umk (operands[0], operands[1],
4518 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4523 (define_expand "sibcall_value"
4524 [(parallel [(set (match_operand 0 "" "")
4525 (call (mem:DI (match_operand 1 "" ""))
4526 (match_operand 2 "" "")))
4527 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4530 if (GET_CODE (operands[1]) != MEM)
4532 operands[1] = XEXP (operands[1], 0);
4535 (define_expand "call_value_osf"
4536 [(parallel [(set (match_operand 0 "" "")
4537 (call (mem:DI (match_operand 1 "" ""))
4538 (match_operand 2 "" "")))
4540 (clobber (reg:DI 26))])]
4543 if (GET_CODE (operands[1]) != MEM)
4546 operands[1] = XEXP (operands[1], 0);
4547 if (! call_operand (operands[1], Pmode))
4548 operands[1] = copy_to_mode_reg (Pmode, operands[1]);
4551 (define_expand "call_value_nt"
4552 [(parallel [(set (match_operand 0 "" "")
4553 (call (mem:DI (match_operand 1 "" ""))
4554 (match_operand 2 "" "")))
4555 (clobber (reg:DI 26))])]
4558 if (GET_CODE (operands[1]) != MEM)
4561 operands[1] = XEXP (operands[1], 0);
4562 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4563 operands[1] = force_reg (DImode, operands[1]);
4566 (define_expand "call_value_vms"
4567 [(parallel [(set (match_operand 0 "" "")
4568 (call (mem:DI (match_operand:DI 1 "" ""))
4569 (match_operand 2 "" "")))
4573 (clobber (reg:DI 27))])]
4576 if (GET_CODE (operands[1]) != MEM)
4579 operands[1] = XEXP (operands[1], 0);
4581 /* Always load AI with argument information, then handle symbolic and
4582 indirect call differently. Load RA and set operands[3] to PV in
4585 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4586 if (GET_CODE (operands[1]) == SYMBOL_REF)
4588 alpha_need_linkage (XSTR (operands[1], 0), 0);
4590 operands[3] = const0_rtx;
4594 emit_move_insn (gen_rtx_REG (Pmode, 26),
4595 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4596 operands[3] = operands[1];
4600 (define_expand "call_value_umk"
4601 [(parallel [(set (match_operand 0 "" "")
4602 (call (mem:DI (match_operand 1 "" ""))
4603 (match_operand 2 "" "")))
4605 (clobber (reg:DI 26))])]
4608 if (GET_CODE (operands[1]) != MEM)
4611 operands[1] = XEXP (operands[1], 0);
4612 if (GET_CODE (operands[1]) != REG)
4613 operands[1] = force_reg (DImode, operands[1]);
4615 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4618 (define_insn "*call_osf_1_er"
4619 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4620 (match_operand 1 "" ""))
4622 (clobber (reg:DI 26))]
4623 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4625 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
4626 bsr $26,%0\t\t!samegp
4627 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
4628 [(set_attr "type" "jsr")
4629 (set_attr "length" "12,*,16")])
4631 ;; We must use peep2 instead of a split because we need accurate life
4632 ;; information for $gp. Consider the case of { bar(); while (1); }.
4634 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4635 (match_operand 1 "" ""))
4637 (clobber (reg:DI 26))])]
4638 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4639 && ! samegp_function_operand (operands[0], Pmode)
4640 && (peep2_regno_dead_p (1, 29)
4641 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
4642 [(parallel [(call (mem:DI (match_dup 2))
4644 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4645 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4647 (use (match_dup 3))])]
4649 if (CONSTANT_P (operands[0]))
4651 operands[2] = gen_rtx_REG (Pmode, 27);
4652 operands[3] = GEN_INT (alpha_next_sequence_number++);
4653 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4654 operands[0], operands[3]));
4658 operands[2] = operands[0];
4659 operands[0] = const0_rtx;
4660 operands[3] = const0_rtx;
4665 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4666 (match_operand 1 "" ""))
4668 (clobber (reg:DI 26))])]
4669 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4670 && ! samegp_function_operand (operands[0], Pmode)
4671 && ! (peep2_regno_dead_p (1, 29)
4672 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
4673 [(parallel [(call (mem:DI (match_dup 2))
4675 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4676 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4678 (use (match_dup 4))])
4680 (unspec_volatile:DI [(reg:DI 26) (match_dup 3)] UNSPECV_LDGP1))
4682 (unspec:DI [(reg:DI 29) (match_dup 3)] UNSPEC_LDGP2))]
4684 if (CONSTANT_P (operands[0]))
4686 operands[2] = gen_rtx_REG (Pmode, 27);
4687 operands[4] = GEN_INT (alpha_next_sequence_number++);
4688 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4689 operands[0], operands[4]));
4693 operands[2] = operands[0];
4694 operands[0] = const0_rtx;
4695 operands[4] = const0_rtx;
4697 operands[3] = GEN_INT (alpha_next_sequence_number++);
4700 ;; We add a blockage unspec_volatile to prevent insns from moving down
4701 ;; from above the call to in between the call and the ldah gpdisp.
4703 (define_insn "*call_osf_2_er"
4704 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4705 (match_operand 1 "" ""))
4706 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4707 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4708 (use (match_operand 2 "" ""))
4709 (use (match_operand 3 "const_int_operand" ""))]
4710 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4711 "jsr $26,(%0),%2%J3"
4712 [(set_attr "type" "jsr")
4713 (set_attr "cannot_copy" "true")])
4715 ;; We output a nop after noreturn calls at the very end of the function to
4716 ;; ensure that the return address always remains in the caller's code range,
4717 ;; as not doing so might confuse unwinding engines.
4719 ;; The potential change in insn length is not reflected in the length
4720 ;; attributes at this stage. Since the extra space is only actually added at
4721 ;; the very end of the compilation process (via final/print_operand), it
4722 ;; really seems harmless and not worth the trouble of some extra computation
4723 ;; cost and complexity.
4725 (define_insn "*call_osf_1_noreturn"
4726 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4727 (match_operand 1 "" ""))
4729 (clobber (reg:DI 26))]
4730 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4731 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4736 [(set_attr "type" "jsr")
4737 (set_attr "length" "*,*,8")])
4739 (define_insn "*call_osf_1"
4740 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4741 (match_operand 1 "" ""))
4743 (clobber (reg:DI 26))]
4744 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4746 jsr $26,($27),0\;ldgp $29,0($26)
4748 jsr $26,%0\;ldgp $29,0($26)"
4749 [(set_attr "type" "jsr")
4750 (set_attr "length" "12,*,16")])
4752 ;; Note that the DEC assembler expands "jmp foo" with $at, which
4753 ;; doesn't do what we want.
4754 (define_insn "*sibcall_osf_1_er"
4755 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4756 (match_operand 1 "" ""))
4757 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4758 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4760 br $31,%0\t\t!samegp
4761 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#"
4762 [(set_attr "type" "jsr")
4763 (set_attr "length" "*,8")])
4765 (define_insn "*sibcall_osf_1"
4766 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4767 (match_operand 1 "" ""))
4768 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4769 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4772 lda $27,%0\;jmp $31,($27),%0"
4773 [(set_attr "type" "jsr")
4774 (set_attr "length" "*,8")])
4776 (define_insn "*call_nt_1"
4777 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,s"))
4778 (match_operand 1 "" ""))
4779 (clobber (reg:DI 26))]
4780 "TARGET_ABI_WINDOWS_NT"
4785 [(set_attr "type" "jsr")
4786 (set_attr "length" "*,*,12")])
4788 ; GAS relies on the order and position of instructions output below in order
4789 ; to generate relocs for VMS link to potentially optimize the call.
4790 ; Please do not molest.
4791 (define_insn "*call_vms_1"
4792 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
4793 (match_operand 1 "" ""))
4794 (use (match_operand:DI 2 "nonmemory_operand" "r,n"))
4797 (clobber (reg:DI 27))]
4798 "TARGET_ABI_OPEN_VMS"
4800 switch (which_alternative)
4803 return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)";
4805 operands [2] = alpha_use_linkage (operands [0], cfun->decl, 1, 0);
4806 operands [3] = alpha_use_linkage (operands [0], cfun->decl, 0, 0);
4807 return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)";
4812 [(set_attr "type" "jsr")
4813 (set_attr "length" "12,16")])
4815 (define_insn "*call_umk_1"
4816 [(call (mem:DI (match_operand:DI 0 "call_operand" "r"))
4817 (match_operand 1 "" ""))
4819 (clobber (reg:DI 26))]
4820 "TARGET_ABI_UNICOSMK"
4822 [(set_attr "type" "jsr")])
4824 ;; Call subroutine returning any type.
4826 (define_expand "untyped_call"
4827 [(parallel [(call (match_operand 0 "" "")
4829 (match_operand 1 "" "")
4830 (match_operand 2 "" "")])]
4835 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4837 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4839 rtx set = XVECEXP (operands[2], 0, i);
4840 emit_move_insn (SET_DEST (set), SET_SRC (set));
4843 /* The optimizer does not know that the call sets the function value
4844 registers we stored in the result block. We avoid problems by
4845 claiming that all hard registers are used and clobbered at this
4847 emit_insn (gen_blockage ());
4852 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4853 ;; all of memory. This blocks insns from being moved across this point.
4855 (define_insn "blockage"
4856 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
4859 [(set_attr "length" "0")
4860 (set_attr "type" "none")])
4864 (label_ref (match_operand 0 "" "")))]
4867 [(set_attr "type" "ibr")])
4869 (define_expand "return"
4874 (define_insn "*return_internal"
4878 [(set_attr "type" "ibr")])
4880 (define_insn "indirect_jump"
4881 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4884 [(set_attr "type" "ibr")])
4886 (define_expand "tablejump"
4887 [(parallel [(set (pc)
4888 (match_operand 0 "register_operand" ""))
4889 (use (label_ref:DI (match_operand 1 "" "")))])]
4892 if (TARGET_ABI_WINDOWS_NT)
4894 rtx dest = gen_reg_rtx (DImode);
4895 emit_insn (gen_extendsidi2 (dest, operands[0]));
4898 else if (TARGET_ABI_OSF)
4900 rtx dest = gen_reg_rtx (DImode);
4901 emit_insn (gen_extendsidi2 (dest, operands[0]));
4902 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest));
4907 (define_insn "*tablejump_osf_nt_internal"
4909 (match_operand:DI 0 "register_operand" "r"))
4910 (use (label_ref:DI (match_operand 1 "" "")))]
4911 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
4912 && alpha_tablejump_addr_vec (insn)"
4914 operands[2] = alpha_tablejump_best_label (insn);
4915 return "jmp $31,(%0),%2";
4917 [(set_attr "type" "ibr")])
4919 (define_insn "*tablejump_internal"
4921 (match_operand:DI 0 "register_operand" "r"))
4922 (use (label_ref (match_operand 1 "" "")))]
4925 [(set_attr "type" "ibr")])
4927 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
4928 ;; want to have to include pal.h in our .s file.
4930 ;; Technically the type for call_pal is jsr, but we use that for determining
4931 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
4934 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
4937 [(set_attr "type" "callpal")])
4939 ;; BUGCHK is documented common to OSF/1 and VMS PALcode.
4940 ;; NT does not document anything at 0x81 -- presumably it would generate
4941 ;; the equivalent of SIGILL, but this isn't that important.
4942 ;; ??? Presuming unicosmk uses either OSF/1 or VMS PALcode.
4944 [(trap_if (const_int 1) (const_int 0))]
4945 "!TARGET_ABI_WINDOWS_NT"
4947 [(set_attr "type" "callpal")])
4949 ;; For userland, we load the thread pointer from the TCB.
4950 ;; For the kernel, we load the per-cpu private value.
4952 (define_insn "load_tp"
4953 [(set (match_operand:DI 0 "register_operand" "=v")
4954 (unspec:DI [(const_int 0)] UNSPEC_TP))]
4957 if (TARGET_TLS_KERNEL)
4958 return "call_pal 0x32";
4960 return "call_pal 0x9e";
4962 [(set_attr "type" "callpal")])
4964 ;; For completeness, and possibly a __builtin function, here's how to
4965 ;; set the thread pointer. Since we don't describe enough of this
4966 ;; quantity for CSE, we have to use a volatile unspec, and then there's
4967 ;; not much point in creating an R16_REG register class.
4969 (define_expand "set_tp"
4970 [(set (reg:DI 16) (match_operand:DI 0 "input_operand" ""))
4971 (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
4975 (define_insn "*set_tp"
4976 [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
4979 if (TARGET_TLS_KERNEL)
4980 return "call_pal 0x31";
4982 return "call_pal 0x9f";
4984 [(set_attr "type" "callpal")])
4986 ;; Finally, we have the basic data motion insns. The byte and word insns
4987 ;; are done via define_expand. Start with the floating-point insns, since
4988 ;; they are simpler.
4990 (define_insn "*movsf_nofix"
4991 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4992 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4993 "TARGET_FPREGS && ! TARGET_FIX
4994 && (register_operand (operands[0], SFmode)
4995 || reg_or_0_operand (operands[1], SFmode))"
5003 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5005 (define_insn "*movsf_fix"
5006 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5007 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5008 "TARGET_FPREGS && TARGET_FIX
5009 && (register_operand (operands[0], SFmode)
5010 || reg_or_0_operand (operands[1], SFmode))"
5020 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5022 (define_insn "*movsf_nofp"
5023 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
5024 (match_operand:SF 1 "input_operand" "rG,m,r"))]
5026 && (register_operand (operands[0], SFmode)
5027 || reg_or_0_operand (operands[1], SFmode))"
5032 [(set_attr "type" "ilog,ild,ist")])
5034 (define_insn "*movdf_nofix"
5035 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5036 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5037 "TARGET_FPREGS && ! TARGET_FIX
5038 && (register_operand (operands[0], DFmode)
5039 || reg_or_0_operand (operands[1], DFmode))"
5047 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5049 (define_insn "*movdf_fix"
5050 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5051 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5052 "TARGET_FPREGS && TARGET_FIX
5053 && (register_operand (operands[0], DFmode)
5054 || reg_or_0_operand (operands[1], DFmode))"
5064 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5066 (define_insn "*movdf_nofp"
5067 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
5068 (match_operand:DF 1 "input_operand" "rG,m,r"))]
5070 && (register_operand (operands[0], DFmode)
5071 || reg_or_0_operand (operands[1], DFmode))"
5076 [(set_attr "type" "ilog,ild,ist")])
5078 ;; Subregs suck for register allocation. Pretend we can move TFmode
5079 ;; data between general registers until after reload.
5081 (define_insn_and_split "*movtf_internal"
5082 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
5083 (match_operand:TF 1 "input_operand" "roG,rG"))]
5084 "register_operand (operands[0], TFmode)
5085 || reg_or_0_operand (operands[1], TFmode)"
5088 [(set (match_dup 0) (match_dup 2))
5089 (set (match_dup 1) (match_dup 3))]
5091 alpha_split_tfmode_pair (operands);
5092 if (reg_overlap_mentioned_p (operands[0], operands[3]))
5095 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
5096 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
5100 (define_expand "movsf"
5101 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5102 (match_operand:SF 1 "general_operand" ""))]
5105 if (GET_CODE (operands[0]) == MEM
5106 && ! reg_or_0_operand (operands[1], SFmode))
5107 operands[1] = force_reg (SFmode, operands[1]);
5110 (define_expand "movdf"
5111 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5112 (match_operand:DF 1 "general_operand" ""))]
5115 if (GET_CODE (operands[0]) == MEM
5116 && ! reg_or_0_operand (operands[1], DFmode))
5117 operands[1] = force_reg (DFmode, operands[1]);
5120 (define_expand "movtf"
5121 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5122 (match_operand:TF 1 "general_operand" ""))]
5125 if (GET_CODE (operands[0]) == MEM
5126 && ! reg_or_0_operand (operands[1], TFmode))
5127 operands[1] = force_reg (TFmode, operands[1]);
5130 (define_insn "*movsi"
5131 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m")
5132 (match_operand:SI 1 "input_operand" "rJ,K,L,n,m,rJ"))]
5133 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK)
5134 && (register_operand (operands[0], SImode)
5135 || reg_or_0_operand (operands[1], SImode))"
5143 [(set_attr "type" "ilog,iadd,iadd,multi,ild,ist")])
5145 (define_insn "*movsi_nt_vms"
5146 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m")
5147 (match_operand:SI 1 "input_operand" "rJ,K,L,s,n,m,rJ"))]
5148 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5149 && (register_operand (operands[0], SImode)
5150 || reg_or_0_operand (operands[1], SImode))"
5159 [(set_attr "type" "ilog,iadd,iadd,ldsym,multi,ild,ist")])
5161 (define_insn "*movhi_nobwx"
5162 [(set (match_operand:HI 0 "register_operand" "=r,r")
5163 (match_operand:HI 1 "input_operand" "rJ,n"))]
5165 && (register_operand (operands[0], HImode)
5166 || register_operand (operands[1], HImode))"
5170 [(set_attr "type" "ilog,iadd")])
5172 (define_insn "*movhi_bwx"
5173 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
5174 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
5176 && (register_operand (operands[0], HImode)
5177 || reg_or_0_operand (operands[1], HImode))"
5183 [(set_attr "type" "ilog,iadd,ild,ist")])
5185 (define_insn "*movqi_nobwx"
5186 [(set (match_operand:QI 0 "register_operand" "=r,r")
5187 (match_operand:QI 1 "input_operand" "rJ,n"))]
5189 && (register_operand (operands[0], QImode)
5190 || register_operand (operands[1], QImode))"
5194 [(set_attr "type" "ilog,iadd")])
5196 (define_insn "*movqi_bwx"
5197 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
5198 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
5200 && (register_operand (operands[0], QImode)
5201 || reg_or_0_operand (operands[1], QImode))"
5207 [(set_attr "type" "ilog,iadd,ild,ist")])
5209 ;; We do two major things here: handle mem->mem and construct long
5212 (define_expand "movsi"
5213 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5214 (match_operand:SI 1 "general_operand" ""))]
5217 if (alpha_expand_mov (SImode, operands))
5221 ;; Split a load of a large constant into the appropriate two-insn
5225 [(set (match_operand:SI 0 "register_operand" "")
5226 (match_operand:SI 1 "non_add_const_operand" ""))]
5230 if (alpha_split_const_mov (SImode, operands))
5236 ;; Split the load of an address into a four-insn sequence on Unicos/Mk.
5237 ;; Always generate a REG_EQUAL note for the last instruction to facilitate
5238 ;; optimizations. If the symbolic operand is a label_ref, generate REG_LABEL
5239 ;; notes and update LABEL_NUSES because this is not done automatically.
5240 ;; Labels may be incorrectly deleted if we don't do this.
5242 ;; Describing what the individual instructions do correctly is too complicated
5243 ;; so use UNSPECs for each of the three parts of an address.
5246 [(set (match_operand:DI 0 "register_operand" "")
5247 (match_operand:DI 1 "symbolic_operand" ""))]
5248 "TARGET_ABI_UNICOSMK && reload_completed"
5251 rtx insn1, insn2, insn3;
5253 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1]));
5254 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5255 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
5256 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
5257 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
5259 if (GET_CODE (operands[1]) == LABEL_REF)
5263 label = XEXP (operands[1], 0);
5264 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5266 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5268 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5270 LABEL_NUSES (label) += 3;
5275 ;; Instructions for loading the three parts of an address on Unicos/Mk.
5277 (define_insn "umk_laum"
5278 [(set (match_operand:DI 0 "register_operand" "=r")
5279 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5281 "TARGET_ABI_UNICOSMK"
5283 [(set_attr "type" "iadd")])
5285 (define_insn "umk_lalm"
5286 [(set (match_operand:DI 0 "register_operand" "=r")
5287 (plus:DI (match_operand:DI 1 "register_operand" "r")
5288 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5290 "TARGET_ABI_UNICOSMK"
5292 [(set_attr "type" "iadd")])
5294 (define_insn "umk_lal"
5295 [(set (match_operand:DI 0 "register_operand" "=r")
5296 (plus:DI (match_operand:DI 1 "register_operand" "r")
5297 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5299 "TARGET_ABI_UNICOSMK"
5301 [(set_attr "type" "iadd")])
5303 ;; Add a new call information word to the current function's list of CIWs
5304 ;; and load its index into $25. Doing it here ensures that the CIW will be
5305 ;; associated with the correct function even in the presence of inlining.
5307 (define_insn "*umk_load_ciw"
5309 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))]
5310 "TARGET_ABI_UNICOSMK"
5312 operands[0] = unicosmk_add_call_info_word (operands[0]);
5313 return "lda $25,%0";
5315 [(set_attr "type" "iadd")])
5317 (define_insn "*movdi_er_low_l"
5318 [(set (match_operand:DI 0 "register_operand" "=r")
5319 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
5320 (match_operand:DI 2 "local_symbolic_operand" "")))]
5321 "TARGET_EXPLICIT_RELOCS"
5323 if (true_regnum (operands[1]) == 29)
5324 return "lda %0,%2(%1)\t\t!gprel";
5326 return "lda %0,%2(%1)\t\t!gprellow";
5328 [(set_attr "usegp" "yes")])
5331 [(set (match_operand:DI 0 "register_operand" "")
5332 (match_operand:DI 1 "small_symbolic_operand" ""))]
5333 "TARGET_EXPLICIT_RELOCS && reload_completed"
5335 (lo_sum:DI (match_dup 2) (match_dup 1)))]
5336 "operands[2] = pic_offset_table_rtx;")
5339 [(set (match_operand:DI 0 "register_operand" "")
5340 (match_operand:DI 1 "local_symbolic_operand" ""))]
5341 "TARGET_EXPLICIT_RELOCS && reload_completed"
5343 (plus:DI (match_dup 2) (high:DI (match_dup 1))))
5345 (lo_sum:DI (match_dup 0) (match_dup 1)))]
5346 "operands[2] = pic_offset_table_rtx;")
5349 [(match_operand 0 "some_small_symbolic_operand" "")]
5352 "operands[0] = split_small_symbolic_operand (operands[0]);")
5354 ;; Accepts any symbolic, not just global, since function calls that
5355 ;; don't go via bsr still use !literal in hopes of linker relaxation.
5356 (define_insn "movdi_er_high_g"
5357 [(set (match_operand:DI 0 "register_operand" "=r")
5358 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5359 (match_operand:DI 2 "symbolic_operand" "")
5360 (match_operand 3 "const_int_operand" "")]
5362 "TARGET_EXPLICIT_RELOCS"
5364 if (INTVAL (operands[3]) == 0)
5365 return "ldq %0,%2(%1)\t\t!literal";
5367 return "ldq %0,%2(%1)\t\t!literal!%3";
5369 [(set_attr "type" "ldsym")])
5372 [(set (match_operand:DI 0 "register_operand" "")
5373 (match_operand:DI 1 "global_symbolic_operand" ""))]
5374 "TARGET_EXPLICIT_RELOCS && reload_completed"
5376 (unspec:DI [(match_dup 2)
5378 (const_int 0)] UNSPEC_LITERAL))]
5379 "operands[2] = pic_offset_table_rtx;")
5381 (define_insn "movdi_er_tlsgd"
5382 [(set (match_operand:DI 0 "register_operand" "=r")
5383 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5384 (match_operand:DI 2 "symbolic_operand" "")
5385 (match_operand 3 "const_int_operand" "")]
5389 if (INTVAL (operands[3]) == 0)
5390 return "lda %0,%2(%1)\t\t!tlsgd";
5392 return "lda %0,%2(%1)\t\t!tlsgd!%3";
5395 (define_insn "movdi_er_tlsldm"
5396 [(set (match_operand:DI 0 "register_operand" "=r")
5397 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5398 (match_operand 2 "const_int_operand" "")]
5402 if (INTVAL (operands[2]) == 0)
5403 return "lda %0,%&(%1)\t\t!tlsldm";
5405 return "lda %0,%&(%1)\t\t!tlsldm!%2";
5408 (define_insn "*movdi_er_gotdtp"
5409 [(set (match_operand:DI 0 "register_operand" "=r")
5410 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5411 (match_operand:DI 2 "symbolic_operand" "")]
5414 "ldq %0,%2(%1)\t\t!gotdtprel"
5415 [(set_attr "type" "ild")
5416 (set_attr "usegp" "yes")])
5419 [(set (match_operand:DI 0 "register_operand" "")
5420 (match_operand:DI 1 "gotdtp_symbolic_operand" ""))]
5421 "HAVE_AS_TLS && reload_completed"
5423 (unspec:DI [(match_dup 2)
5424 (match_dup 1)] UNSPEC_DTPREL))]
5426 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5427 operands[2] = pic_offset_table_rtx;
5430 (define_insn "*movdi_er_gottp"
5431 [(set (match_operand:DI 0 "register_operand" "=r")
5432 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5433 (match_operand:DI 2 "symbolic_operand" "")]
5436 "ldq %0,%2(%1)\t\t!gottprel"
5437 [(set_attr "type" "ild")
5438 (set_attr "usegp" "yes")])
5441 [(set (match_operand:DI 0 "register_operand" "")
5442 (match_operand:DI 1 "gottp_symbolic_operand" ""))]
5443 "HAVE_AS_TLS && reload_completed"
5445 (unspec:DI [(match_dup 2)
5446 (match_dup 1)] UNSPEC_TPREL))]
5448 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5449 operands[2] = pic_offset_table_rtx;
5452 (define_insn "*movdi_er_nofix"
5453 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,*f,*f,Q")
5454 (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,n,m,rJ,*fJ,Q,*f"))]
5455 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
5456 && (register_operand (operands[0], DImode)
5457 || reg_or_0_operand (operands[1], DImode))"
5470 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst")
5471 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*")])
5473 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
5474 ;; have been split up by the rules above but we shouldn't reject the
5475 ;; possibility of them getting through.
5477 (define_insn "*movdi_nofix"
5478 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,*f,*f,Q")
5479 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,n,m,rJ,*fJ,Q,*f"))]
5481 && (register_operand (operands[0], DImode)
5482 || reg_or_0_operand (operands[1], DImode))"
5487 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
5495 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,multi,ild,ist,fcpys,fld,fst")
5496 (set_attr "length" "*,*,*,16,*,*,*,*,*,*,*")])
5498 (define_insn "*movdi_er_fix"
5499 [(set (match_operand:DI 0 "nonimmediate_operand"
5500 "=r,r,r,r,r,r,r, m, *f,*f, Q, r,*f")
5501 (match_operand:DI 1 "input_operand"
5502 "rJ,K,L,T,s,n,m,rJ,*fJ, Q,*f,*f, r"))]
5503 "TARGET_EXPLICIT_RELOCS && TARGET_FIX
5504 && (register_operand (operands[0], DImode)
5505 || reg_or_0_operand (operands[1], DImode))"
5520 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst,ftoi,itof")
5521 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*,*")])
5523 (define_insn "*movdi_fix"
5524 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q,r,*f")
5525 (match_operand:DI 1 "input_operand" "rJ,K,L,s,n,m,rJ,*fJ,Q,*f,*f,r"))]
5526 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
5527 && (register_operand (operands[0], DImode)
5528 || reg_or_0_operand (operands[1], DImode))"
5542 [(set_attr "type" "ilog,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst,ftoi,itof")])
5544 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
5545 ;; often appears dead to the life analysis code, at which point we
5546 ;; abort for emitting dead prologue instructions. Force this live.
5548 (define_insn "force_movdi"
5549 [(set (match_operand:DI 0 "register_operand" "=r")
5550 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
5551 UNSPECV_FORCE_MOV))]
5554 [(set_attr "type" "ilog")])
5556 ;; We do three major things here: handle mem->mem, put 64-bit constants in
5557 ;; memory, and construct long 32-bit constants.
5559 (define_expand "movdi"
5560 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5561 (match_operand:DI 1 "general_operand" ""))]
5564 if (alpha_expand_mov (DImode, operands))
5568 ;; Split a load of a large constant into the appropriate two-insn
5572 [(set (match_operand:DI 0 "register_operand" "")
5573 (match_operand:DI 1 "non_add_const_operand" ""))]
5577 if (alpha_split_const_mov (DImode, operands))
5583 ;; These are the partial-word cases.
5585 ;; First we have the code to load an aligned word. Operand 0 is the register
5586 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5587 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5588 ;; number of bits within the word that the value is. Operand 3 is an SImode
5589 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5590 ;; same register. It is allowed to conflict with operand 1 as well.
5592 (define_expand "aligned_loadqi"
5593 [(set (match_operand:SI 3 "register_operand" "")
5594 (match_operand:SI 1 "memory_operand" ""))
5595 (set (match_operand:DI 0 "register_operand" "")
5596 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5598 (match_operand:DI 2 "const_int_operand" "")))]
5603 (define_expand "aligned_loadhi"
5604 [(set (match_operand:SI 3 "register_operand" "")
5605 (match_operand:SI 1 "memory_operand" ""))
5606 (set (match_operand:DI 0 "register_operand" "")
5607 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5609 (match_operand:DI 2 "const_int_operand" "")))]
5614 ;; Similar for unaligned loads, where we use the sequence from the
5615 ;; Alpha Architecture manual. We have to distinguish between little-endian
5616 ;; and big-endian systems as the sequences are different.
5618 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5619 ;; operand 3 can overlap the input and output registers.
5621 (define_expand "unaligned_loadqi"
5622 [(use (match_operand:DI 0 "register_operand" ""))
5623 (use (match_operand:DI 1 "address_operand" ""))
5624 (use (match_operand:DI 2 "register_operand" ""))
5625 (use (match_operand:DI 3 "register_operand" ""))]
5628 if (WORDS_BIG_ENDIAN)
5629 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
5630 operands[2], operands[3]));
5632 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
5633 operands[2], operands[3]));
5637 (define_expand "unaligned_loadqi_le"
5638 [(set (match_operand:DI 2 "register_operand" "")
5639 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5641 (set (match_operand:DI 3 "register_operand" "")
5643 (set (match_operand:DI 0 "register_operand" "")
5644 (zero_extract:DI (match_dup 2)
5646 (ashift:DI (match_dup 3) (const_int 3))))]
5647 "! WORDS_BIG_ENDIAN"
5650 (define_expand "unaligned_loadqi_be"
5651 [(set (match_operand:DI 2 "register_operand" "")
5652 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5654 (set (match_operand:DI 3 "register_operand" "")
5656 (set (match_operand:DI 0 "register_operand" "")
5657 (zero_extract:DI (match_dup 2)
5661 (ashift:DI (match_dup 3) (const_int 3)))))]
5665 (define_expand "unaligned_loadhi"
5666 [(use (match_operand:DI 0 "register_operand" ""))
5667 (use (match_operand:DI 1 "address_operand" ""))
5668 (use (match_operand:DI 2 "register_operand" ""))
5669 (use (match_operand:DI 3 "register_operand" ""))]
5672 if (WORDS_BIG_ENDIAN)
5673 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
5674 operands[2], operands[3]));
5676 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
5677 operands[2], operands[3]));
5681 (define_expand "unaligned_loadhi_le"
5682 [(set (match_operand:DI 2 "register_operand" "")
5683 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5685 (set (match_operand:DI 3 "register_operand" "")
5687 (set (match_operand:DI 0 "register_operand" "")
5688 (zero_extract:DI (match_dup 2)
5690 (ashift:DI (match_dup 3) (const_int 3))))]
5691 "! WORDS_BIG_ENDIAN"
5694 (define_expand "unaligned_loadhi_be"
5695 [(set (match_operand:DI 2 "register_operand" "")
5696 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5698 (set (match_operand:DI 3 "register_operand" "")
5699 (plus:DI (match_dup 1) (const_int 1)))
5700 (set (match_operand:DI 0 "register_operand" "")
5701 (zero_extract:DI (match_dup 2)
5705 (ashift:DI (match_dup 3) (const_int 3)))))]
5709 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5710 ;; aligned SImode MEM. Operand 1 is the register containing the
5711 ;; byte or word to store. Operand 2 is the number of bits within the word that
5712 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5714 (define_expand "aligned_store"
5715 [(set (match_operand:SI 3 "register_operand" "")
5716 (match_operand:SI 0 "memory_operand" ""))
5717 (set (subreg:DI (match_dup 3) 0)
5718 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5719 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5720 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5721 (match_operand:DI 2 "const_int_operand" "")))
5722 (set (subreg:DI (match_dup 4) 0)
5723 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5724 (set (match_dup 0) (match_dup 4))]
5727 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5728 << INTVAL (operands[2])));
5731 ;; For the unaligned byte and halfword cases, we use code similar to that
5732 ;; in the ;; Architecture book, but reordered to lower the number of registers
5733 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5734 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5735 ;; be the same temporary, if desired. If the address is in a register,
5736 ;; operand 2 can be that register.
5738 (define_expand "unaligned_storeqi"
5739 [(use (match_operand:DI 0 "address_operand" ""))
5740 (use (match_operand:QI 1 "register_operand" ""))
5741 (use (match_operand:DI 2 "register_operand" ""))
5742 (use (match_operand:DI 3 "register_operand" ""))
5743 (use (match_operand:DI 4 "register_operand" ""))]
5746 if (WORDS_BIG_ENDIAN)
5747 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
5748 operands[2], operands[3],
5751 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
5752 operands[2], operands[3],
5757 (define_expand "unaligned_storeqi_le"
5758 [(set (match_operand:DI 3 "register_operand" "")
5759 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5761 (set (match_operand:DI 2 "register_operand" "")
5764 (and:DI (not:DI (ashift:DI (const_int 255)
5765 (ashift:DI (match_dup 2) (const_int 3))))
5767 (set (match_operand:DI 4 "register_operand" "")
5768 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5769 (ashift:DI (match_dup 2) (const_int 3))))
5770 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5771 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5773 "! WORDS_BIG_ENDIAN"
5776 (define_expand "unaligned_storeqi_be"
5777 [(set (match_operand:DI 3 "register_operand" "")
5778 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5780 (set (match_operand:DI 2 "register_operand" "")
5783 (and:DI (not:DI (ashift:DI (const_int 255)
5784 (minus:DI (const_int 56)
5785 (ashift:DI (match_dup 2) (const_int 3)))))
5787 (set (match_operand:DI 4 "register_operand" "")
5788 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5789 (minus:DI (const_int 56)
5790 (ashift:DI (match_dup 2) (const_int 3)))))
5791 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5792 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5797 (define_expand "unaligned_storehi"
5798 [(use (match_operand:DI 0 "address_operand" ""))
5799 (use (match_operand:HI 1 "register_operand" ""))
5800 (use (match_operand:DI 2 "register_operand" ""))
5801 (use (match_operand:DI 3 "register_operand" ""))
5802 (use (match_operand:DI 4 "register_operand" ""))]
5805 if (WORDS_BIG_ENDIAN)
5806 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
5807 operands[2], operands[3],
5810 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
5811 operands[2], operands[3],
5816 (define_expand "unaligned_storehi_le"
5817 [(set (match_operand:DI 3 "register_operand" "")
5818 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5820 (set (match_operand:DI 2 "register_operand" "")
5823 (and:DI (not:DI (ashift:DI (const_int 65535)
5824 (ashift:DI (match_dup 2) (const_int 3))))
5826 (set (match_operand:DI 4 "register_operand" "")
5827 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5828 (ashift:DI (match_dup 2) (const_int 3))))
5829 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5830 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5832 "! WORDS_BIG_ENDIAN"
5835 (define_expand "unaligned_storehi_be"
5836 [(set (match_operand:DI 3 "register_operand" "")
5837 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5839 (set (match_operand:DI 2 "register_operand" "")
5840 (plus:DI (match_dup 0) (const_int 1)))
5842 (and:DI (not:DI (ashift:DI
5844 (minus:DI (const_int 56)
5845 (ashift:DI (match_dup 2) (const_int 3)))))
5847 (set (match_operand:DI 4 "register_operand" "")
5848 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5849 (minus:DI (const_int 56)
5850 (ashift:DI (match_dup 2) (const_int 3)))))
5851 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5852 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5857 ;; Here are the define_expand's for QI and HI moves that use the above
5858 ;; patterns. We have the normal sets, plus the ones that need scratch
5859 ;; registers for reload.
5861 (define_expand "movqi"
5862 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5863 (match_operand:QI 1 "general_operand" ""))]
5867 ? alpha_expand_mov (QImode, operands)
5868 : alpha_expand_mov_nobwx (QImode, operands))
5872 (define_expand "movhi"
5873 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5874 (match_operand:HI 1 "general_operand" ""))]
5878 ? alpha_expand_mov (HImode, operands)
5879 : alpha_expand_mov_nobwx (HImode, operands))
5883 ;; Here are the versions for reload. Note that in the unaligned cases
5884 ;; we know that the operand must not be a pseudo-register because stack
5885 ;; slots are always aligned references.
5887 (define_expand "reload_inqi"
5888 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5889 (match_operand:QI 1 "any_memory_operand" "m")
5890 (match_operand:TI 2 "register_operand" "=&r")])]
5895 if (aligned_memory_operand (operands[1], QImode))
5897 seq = gen_reload_inqi_help (operands[0], operands[1],
5898 gen_rtx_REG (SImode, REGNO (operands[2])));
5904 /* It is possible that one of the registers we got for operands[2]
5905 might coincide with that of operands[0] (which is why we made
5906 it TImode). Pick the other one to use as our scratch. */
5907 if (REGNO (operands[0]) == REGNO (operands[2]))
5908 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5910 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5912 addr = get_unaligned_address (operands[1], 0);
5913 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
5914 seq = gen_unaligned_loadqi (operands[0], addr, scratch, operands[0]);
5915 alpha_set_memflags (seq, operands[1]);
5921 (define_expand "reload_inhi"
5922 [(parallel [(match_operand:HI 0 "register_operand" "=r")
5923 (match_operand:HI 1 "any_memory_operand" "m")
5924 (match_operand:TI 2 "register_operand" "=&r")])]
5929 if (aligned_memory_operand (operands[1], HImode))
5931 seq = gen_reload_inhi_help (operands[0], operands[1],
5932 gen_rtx_REG (SImode, REGNO (operands[2])));
5938 /* It is possible that one of the registers we got for operands[2]
5939 might coincide with that of operands[0] (which is why we made
5940 it TImode). Pick the other one to use as our scratch. */
5941 if (REGNO (operands[0]) == REGNO (operands[2]))
5942 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5944 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5946 addr = get_unaligned_address (operands[1], 0);
5947 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
5948 seq = gen_unaligned_loadhi (operands[0], addr, scratch, operands[0]);
5949 alpha_set_memflags (seq, operands[1]);
5955 (define_expand "reload_outqi"
5956 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
5957 (match_operand:QI 1 "register_operand" "r")
5958 (match_operand:TI 2 "register_operand" "=&r")])]
5961 if (aligned_memory_operand (operands[0], QImode))
5963 emit_insn (gen_reload_outqi_help
5964 (operands[0], operands[1],
5965 gen_rtx_REG (SImode, REGNO (operands[2])),
5966 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5970 rtx addr = get_unaligned_address (operands[0], 0);
5971 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5972 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5973 rtx scratch3 = scratch1;
5976 if (GET_CODE (addr) == REG)
5979 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
5980 scratch2, scratch3);
5981 alpha_set_memflags (seq, operands[0]);
5987 (define_expand "reload_outhi"
5988 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
5989 (match_operand:HI 1 "register_operand" "r")
5990 (match_operand:TI 2 "register_operand" "=&r")])]
5993 if (aligned_memory_operand (operands[0], HImode))
5995 emit_insn (gen_reload_outhi_help
5996 (operands[0], operands[1],
5997 gen_rtx_REG (SImode, REGNO (operands[2])),
5998 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6002 rtx addr = get_unaligned_address (operands[0], 0);
6003 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6004 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6005 rtx scratch3 = scratch1;
6008 if (GET_CODE (addr) == REG)
6011 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
6012 scratch2, scratch3);
6013 alpha_set_memflags (seq, operands[0]);
6019 ;; Helpers for the above. The way reload is structured, we can't
6020 ;; always get a proper address for a stack slot during reload_foo
6021 ;; expansion, so we must delay our address manipulations until after.
6023 (define_insn_and_split "reload_inqi_help"
6024 [(set (match_operand:QI 0 "register_operand" "=r")
6025 (match_operand:QI 1 "memory_operand" "m"))
6026 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6027 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6029 "! TARGET_BWX && reload_completed"
6032 rtx aligned_mem, bitnum;
6033 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6034 operands[0] = gen_lowpart (DImode, operands[0]);
6035 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
6040 (define_insn_and_split "reload_inhi_help"
6041 [(set (match_operand:HI 0 "register_operand" "=r")
6042 (match_operand:HI 1 "memory_operand" "m"))
6043 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6044 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6046 "! TARGET_BWX && reload_completed"
6049 rtx aligned_mem, bitnum;
6050 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6051 operands[0] = gen_lowpart (DImode, operands[0]);
6052 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
6057 (define_insn_and_split "reload_outqi_help"
6058 [(set (match_operand:QI 0 "memory_operand" "=m")
6059 (match_operand:QI 1 "register_operand" "r"))
6060 (clobber (match_operand:SI 2 "register_operand" "=r"))
6061 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6062 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6064 "! TARGET_BWX && reload_completed"
6067 rtx aligned_mem, bitnum;
6068 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6069 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6070 operands[2], operands[3]));
6074 (define_insn_and_split "reload_outhi_help"
6075 [(set (match_operand:HI 0 "memory_operand" "=m")
6076 (match_operand:HI 1 "register_operand" "r"))
6077 (clobber (match_operand:SI 2 "register_operand" "=r"))
6078 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6079 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6081 "! TARGET_BWX && reload_completed"
6084 rtx aligned_mem, bitnum;
6085 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6086 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6087 operands[2], operands[3]));
6091 ;; Vector operations
6093 (define_mode_macro VEC [V8QI V4HI V2SI])
6095 (define_expand "mov<mode>"
6096 [(set (match_operand:VEC 0 "nonimmediate_operand" "")
6097 (match_operand:VEC 1 "general_operand" ""))]
6100 if (alpha_expand_mov (<MODE>mode, operands))
6105 [(set (match_operand:VEC 0 "register_operand" "")
6106 (match_operand:VEC 1 "non_zero_const_operand" ""))]
6110 if (alpha_split_const_mov (<MODE>mode, operands))
6117 (define_expand "movmisalign<mode>"
6118 [(set (match_operand:VEC 0 "nonimmediate_operand" "")
6119 (match_operand:VEC 1 "general_operand" ""))]
6122 alpha_expand_movmisalign (<MODE>mode, operands);
6126 (define_insn "*mov<mode>_fix"
6127 [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m,r,*f")
6128 (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f,*f,r"))]
6130 && (register_operand (operands[0], <MODE>mode)
6131 || reg_or_0_operand (operands[1], <MODE>mode))"
6142 [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof")])
6144 (define_insn "*mov<mode>_nofix"
6145 [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m")
6146 (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f"))]
6148 && (register_operand (operands[0], <MODE>mode)
6149 || reg_or_0_operand (operands[1], <MODE>mode))"
6158 [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst")])
6160 (define_insn "uminv8qi3"
6161 [(set (match_operand:V8QI 0 "register_operand" "=r")
6162 (umin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6163 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6166 [(set_attr "type" "mvi")])
6168 (define_insn "sminv8qi3"
6169 [(set (match_operand:V8QI 0 "register_operand" "=r")
6170 (smin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6171 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6174 [(set_attr "type" "mvi")])
6176 (define_insn "uminv4hi3"
6177 [(set (match_operand:V4HI 0 "register_operand" "=r")
6178 (umin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6179 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6182 [(set_attr "type" "mvi")])
6184 (define_insn "sminv4hi3"
6185 [(set (match_operand:V4HI 0 "register_operand" "=r")
6186 (smin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6187 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6190 [(set_attr "type" "mvi")])
6192 (define_insn "umaxv8qi3"
6193 [(set (match_operand:V8QI 0 "register_operand" "=r")
6194 (umax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6195 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6198 [(set_attr "type" "mvi")])
6200 (define_insn "smaxv8qi3"
6201 [(set (match_operand:V8QI 0 "register_operand" "=r")
6202 (smax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6203 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6206 [(set_attr "type" "mvi")])
6208 (define_insn "umaxv4hi3"
6209 [(set (match_operand:V4HI 0 "register_operand" "=r")
6210 (umax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6211 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6214 [(set_attr "type" "mvi")])
6216 (define_insn "smaxv4hi3"
6217 [(set (match_operand:V4HI 0 "register_operand" "=r")
6218 (smax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6219 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6222 [(set_attr "type" "mvi")])
6224 (define_insn "one_cmpl<mode>2"
6225 [(set (match_operand:VEC 0 "register_operand" "=r")
6226 (not:VEC (match_operand:VEC 1 "register_operand" "r")))]
6229 [(set_attr "type" "ilog")])
6231 (define_insn "and<mode>3"
6232 [(set (match_operand:VEC 0 "register_operand" "=r")
6233 (and:VEC (match_operand:VEC 1 "register_operand" "r")
6234 (match_operand:VEC 2 "register_operand" "r")))]
6237 [(set_attr "type" "ilog")])
6239 (define_insn "*andnot<mode>3"
6240 [(set (match_operand:VEC 0 "register_operand" "=r")
6241 (and:VEC (not:VEC (match_operand:VEC 1 "register_operand" "r"))
6242 (match_operand:VEC 2 "register_operand" "r")))]
6245 [(set_attr "type" "ilog")])
6247 (define_insn "ior<mode>3"
6248 [(set (match_operand:VEC 0 "register_operand" "=r")
6249 (ior:VEC (match_operand:VEC 1 "register_operand" "r")
6250 (match_operand:VEC 2 "register_operand" "r")))]
6253 [(set_attr "type" "ilog")])
6255 (define_insn "*iornot<mode>3"
6256 [(set (match_operand:VEC 0 "register_operand" "=r")
6257 (ior:VEC (not:DI (match_operand:VEC 1 "register_operand" "r"))
6258 (match_operand:VEC 2 "register_operand" "r")))]
6261 [(set_attr "type" "ilog")])
6263 (define_insn "xor<mode>3"
6264 [(set (match_operand:VEC 0 "register_operand" "=r")
6265 (xor:VEC (match_operand:VEC 1 "register_operand" "r")
6266 (match_operand:VEC 2 "register_operand" "r")))]
6269 [(set_attr "type" "ilog")])
6271 (define_insn "*xornot<mode>3"
6272 [(set (match_operand:VEC 0 "register_operand" "=r")
6273 (not:VEC (xor:VEC (match_operand:VEC 1 "register_operand" "r")
6274 (match_operand:VEC 2 "register_operand" "r"))))]
6277 [(set_attr "type" "ilog")])
6279 ;; Bit field extract patterns which use ext[wlq][lh]
6281 (define_expand "extv"
6282 [(set (match_operand:DI 0 "register_operand" "")
6283 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
6284 (match_operand:DI 2 "immediate_operand" "")
6285 (match_operand:DI 3 "immediate_operand" "")))]
6290 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6291 if (INTVAL (operands[3]) % 8 != 0
6292 || (INTVAL (operands[2]) != 16
6293 && INTVAL (operands[2]) != 32
6294 && INTVAL (operands[2]) != 64))
6297 /* From mips.md: extract_bit_field doesn't verify that our source
6298 matches the predicate, so we force it to be a MEM here. */
6299 if (GET_CODE (operands[1]) != MEM)
6302 /* The bit number is relative to the mode of operand 1 which is
6303 usually QImode (this might actually be a bug in expmed.c). Note
6304 that the bit number is negative in big-endian mode in this case.
6305 We have to convert that to the offset. */
6306 if (WORDS_BIG_ENDIAN)
6307 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6308 - INTVAL (operands[2]) - INTVAL (operands[3]);
6310 ofs = INTVAL (operands[3]);
6314 alpha_expand_unaligned_load (operands[0], operands[1],
6315 INTVAL (operands[2]) / 8,
6320 (define_expand "extzv"
6321 [(set (match_operand:DI 0 "register_operand" "")
6322 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
6323 (match_operand:DI 2 "immediate_operand" "")
6324 (match_operand:DI 3 "immediate_operand" "")))]
6327 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6328 if (INTVAL (operands[3]) % 8 != 0
6329 || (INTVAL (operands[2]) != 8
6330 && INTVAL (operands[2]) != 16
6331 && INTVAL (operands[2]) != 32
6332 && INTVAL (operands[2]) != 64))
6335 if (GET_CODE (operands[1]) == MEM)
6339 /* Fail 8 bit fields, falling back on a simple byte load. */
6340 if (INTVAL (operands[2]) == 8)
6343 /* The bit number is relative to the mode of operand 1 which is
6344 usually QImode (this might actually be a bug in expmed.c). Note
6345 that the bit number is negative in big-endian mode in this case.
6346 We have to convert that to the offset. */
6347 if (WORDS_BIG_ENDIAN)
6348 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6349 - INTVAL (operands[2]) - INTVAL (operands[3]);
6351 ofs = INTVAL (operands[3]);
6355 alpha_expand_unaligned_load (operands[0], operands[1],
6356 INTVAL (operands[2]) / 8,
6362 (define_expand "insv"
6363 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
6364 (match_operand:DI 1 "immediate_operand" "")
6365 (match_operand:DI 2 "immediate_operand" ""))
6366 (match_operand:DI 3 "register_operand" ""))]
6371 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6372 if (INTVAL (operands[2]) % 8 != 0
6373 || (INTVAL (operands[1]) != 16
6374 && INTVAL (operands[1]) != 32
6375 && INTVAL (operands[1]) != 64))
6378 /* From mips.md: store_bit_field doesn't verify that our source
6379 matches the predicate, so we force it to be a MEM here. */
6380 if (GET_CODE (operands[0]) != MEM)
6383 /* The bit number is relative to the mode of operand 1 which is
6384 usually QImode (this might actually be a bug in expmed.c). Note
6385 that the bit number is negative in big-endian mode in this case.
6386 We have to convert that to the offset. */
6387 if (WORDS_BIG_ENDIAN)
6388 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
6389 - INTVAL (operands[1]) - INTVAL (operands[2]);
6391 ofs = INTVAL (operands[2]);
6395 alpha_expand_unaligned_store (operands[0], operands[3],
6396 INTVAL (operands[1]) / 8, ofs);
6400 ;; Block move/clear, see alpha.c for more details.
6401 ;; Argument 0 is the destination
6402 ;; Argument 1 is the source
6403 ;; Argument 2 is the length
6404 ;; Argument 3 is the alignment
6406 (define_expand "movmemqi"
6407 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6408 (match_operand:BLK 1 "memory_operand" ""))
6409 (use (match_operand:DI 2 "immediate_operand" ""))
6410 (use (match_operand:DI 3 "immediate_operand" ""))])]
6413 if (alpha_expand_block_move (operands))
6419 (define_expand "movmemdi"
6420 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6421 (match_operand:BLK 1 "memory_operand" ""))
6422 (use (match_operand:DI 2 "immediate_operand" ""))
6423 (use (match_operand:DI 3 "immediate_operand" ""))
6425 (clobber (reg:DI 25))
6426 (clobber (reg:DI 16))
6427 (clobber (reg:DI 17))
6428 (clobber (reg:DI 18))
6429 (clobber (reg:DI 19))
6430 (clobber (reg:DI 20))
6431 (clobber (reg:DI 26))
6432 (clobber (reg:DI 27))])]
6433 "TARGET_ABI_OPEN_VMS"
6435 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$MOVE");
6436 alpha_need_linkage (XSTR (operands[4], 0), 0);
6439 (define_insn "*movmemdi_1"
6440 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6441 (match_operand:BLK 1 "memory_operand" "m,m"))
6442 (use (match_operand:DI 2 "nonmemory_operand" "r,i"))
6443 (use (match_operand:DI 3 "immediate_operand" ""))
6444 (use (match_operand:DI 4 "call_operand" "i,i"))
6445 (clobber (reg:DI 25))
6446 (clobber (reg:DI 16))
6447 (clobber (reg:DI 17))
6448 (clobber (reg:DI 18))
6449 (clobber (reg:DI 19))
6450 (clobber (reg:DI 20))
6451 (clobber (reg:DI 26))
6452 (clobber (reg:DI 27))]
6453 "TARGET_ABI_OPEN_VMS"
6455 operands [5] = alpha_use_linkage (operands [4], cfun->decl, 0, 1);
6456 switch (which_alternative)
6459 return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6461 return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6466 [(set_attr "type" "multi")
6467 (set_attr "length" "28")])
6469 (define_expand "clrmemqi"
6470 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6472 (use (match_operand:DI 1 "immediate_operand" ""))
6473 (use (match_operand:DI 2 "immediate_operand" ""))])]
6476 if (alpha_expand_block_clear (operands))
6482 (define_expand "clrmemdi"
6483 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6485 (use (match_operand:DI 1 "immediate_operand" ""))
6486 (use (match_operand:DI 2 "immediate_operand" ""))
6488 (clobber (reg:DI 25))
6489 (clobber (reg:DI 16))
6490 (clobber (reg:DI 17))
6491 (clobber (reg:DI 26))
6492 (clobber (reg:DI 27))])]
6493 "TARGET_ABI_OPEN_VMS"
6495 operands[3] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO");
6496 alpha_need_linkage (XSTR (operands[3], 0), 0);
6499 (define_insn "*clrmemdi_1"
6500 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6502 (use (match_operand:DI 1 "nonmemory_operand" "r,i"))
6503 (use (match_operand:DI 2 "immediate_operand" ""))
6504 (use (match_operand:DI 3 "call_operand" "i,i"))
6505 (clobber (reg:DI 25))
6506 (clobber (reg:DI 16))
6507 (clobber (reg:DI 17))
6508 (clobber (reg:DI 26))
6509 (clobber (reg:DI 27))]
6510 "TARGET_ABI_OPEN_VMS"
6512 operands [4] = alpha_use_linkage (operands [3], cfun->decl, 0, 1);
6513 switch (which_alternative)
6516 return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6518 return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6523 [(set_attr "type" "multi")
6524 (set_attr "length" "24")])
6527 ;; Subroutine of stack space allocation. Perform a stack probe.
6528 (define_expand "probe_stack"
6529 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
6532 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
6533 INTVAL (operands[0])));
6534 MEM_VOLATILE_P (operands[1]) = 1;
6536 operands[0] = const0_rtx;
6539 ;; This is how we allocate stack space. If we are allocating a
6540 ;; constant amount of space and we know it is less than 4096
6541 ;; bytes, we need do nothing.
6543 ;; If it is more than 4096 bytes, we need to probe the stack
6545 (define_expand "allocate_stack"
6547 (plus:DI (reg:DI 30)
6548 (match_operand:DI 1 "reg_or_cint_operand" "")))
6549 (set (match_operand:DI 0 "register_operand" "=r")
6553 if (GET_CODE (operands[1]) == CONST_INT
6554 && INTVAL (operands[1]) < 32768)
6556 if (INTVAL (operands[1]) >= 4096)
6558 /* We do this the same way as in the prologue and generate explicit
6559 probes. Then we update the stack by the constant. */
6563 emit_insn (gen_probe_stack (GEN_INT (- probed)));
6564 while (probed + 8192 < INTVAL (operands[1]))
6565 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
6567 if (probed + 4096 < INTVAL (operands[1]))
6568 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
6571 operands[1] = GEN_INT (- INTVAL (operands[1]));
6572 operands[2] = virtual_stack_dynamic_rtx;
6577 rtx loop_label = gen_label_rtx ();
6578 rtx want = gen_reg_rtx (Pmode);
6579 rtx tmp = gen_reg_rtx (Pmode);
6582 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
6583 force_reg (Pmode, operands[1])));
6584 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
6586 if (GET_CODE (operands[1]) != CONST_INT)
6588 out_label = gen_label_rtx ();
6589 emit_insn (gen_cmpdi (want, tmp));
6590 emit_jump_insn (gen_bgeu (out_label));
6593 emit_label (loop_label);
6594 memref = gen_rtx_MEM (DImode, tmp);
6595 MEM_VOLATILE_P (memref) = 1;
6596 emit_move_insn (memref, const0_rtx);
6597 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
6598 emit_insn (gen_cmpdi (tmp, want));
6599 emit_jump_insn (gen_bgtu (loop_label));
6601 memref = gen_rtx_MEM (DImode, want);
6602 MEM_VOLATILE_P (memref) = 1;
6603 emit_move_insn (memref, const0_rtx);
6606 emit_label (out_label);
6608 emit_move_insn (stack_pointer_rtx, want);
6609 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6614 ;; This is used by alpha_expand_prolog to do the same thing as above,
6615 ;; except we cannot at that time generate new basic blocks, so we hide
6616 ;; the loop in this one insn.
6618 (define_insn "prologue_stack_probe_loop"
6619 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
6620 (match_operand:DI 1 "register_operand" "r")]
6624 operands[2] = gen_label_rtx ();
6625 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6626 CODE_LABEL_NUMBER (operands[2]));
6628 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
6630 [(set_attr "length" "16")
6631 (set_attr "type" "multi")])
6633 (define_expand "prologue"
6634 [(clobber (const_int 0))]
6637 alpha_expand_prologue ();
6641 ;; These take care of emitting the ldgp insn in the prologue. This will be
6642 ;; an lda/ldah pair and we want to align them properly. So we have two
6643 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
6644 ;; and the second of which emits nothing. However, both are marked as type
6645 ;; IADD (the default) so the alignment code in alpha.c does the right thing
6648 (define_expand "prologue_ldgp"
6650 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6652 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
6655 operands[0] = pic_offset_table_rtx;
6656 operands[1] = gen_rtx_REG (Pmode, 27);
6657 operands[2] = (TARGET_EXPLICIT_RELOCS
6658 ? GEN_INT (alpha_next_sequence_number++)
6662 (define_insn "*ldgp_er_1"
6663 [(set (match_operand:DI 0 "register_operand" "=r")
6664 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6665 (match_operand 2 "const_int_operand" "")]
6667 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6668 "ldah %0,0(%1)\t\t!gpdisp!%2"
6669 [(set_attr "cannot_copy" "true")])
6671 (define_insn "*ldgp_er_2"
6672 [(set (match_operand:DI 0 "register_operand" "=r")
6673 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6674 (match_operand 2 "const_int_operand" "")]
6676 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6677 "lda %0,0(%1)\t\t!gpdisp!%2"
6678 [(set_attr "cannot_copy" "true")])
6680 (define_insn "*prologue_ldgp_er_2"
6681 [(set (match_operand:DI 0 "register_operand" "=r")
6682 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6683 (match_operand 2 "const_int_operand" "")]
6685 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6686 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:"
6687 [(set_attr "cannot_copy" "true")])
6689 (define_insn "*prologue_ldgp_1"
6690 [(set (match_operand:DI 0 "register_operand" "=r")
6691 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6692 (match_operand 2 "const_int_operand" "")]
6695 "ldgp %0,0(%1)\n$%~..ng:"
6696 [(set_attr "cannot_copy" "true")])
6698 (define_insn "*prologue_ldgp_2"
6699 [(set (match_operand:DI 0 "register_operand" "=r")
6700 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6701 (match_operand 2 "const_int_operand" "")]
6706 ;; The _mcount profiling hook has special calling conventions, and
6707 ;; does not clobber all the registers that a normal call would. So
6708 ;; hide the fact this is a call at all.
6710 (define_insn "prologue_mcount"
6711 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
6714 if (TARGET_EXPLICIT_RELOCS)
6715 /* Note that we cannot use a lituse_jsr reloc, since _mcount
6716 cannot be called via the PLT. */
6717 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount";
6719 return "lda $28,_mcount\;jsr $28,($28),_mcount";
6721 [(set_attr "type" "multi")
6722 (set_attr "length" "8")])
6724 (define_insn "init_fp"
6725 [(set (match_operand:DI 0 "register_operand" "=r")
6726 (match_operand:DI 1 "register_operand" "r"))
6727 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
6731 (define_expand "epilogue"
6735 alpha_expand_epilogue ();
6738 (define_expand "sibcall_epilogue"
6742 alpha_expand_epilogue ();
6746 (define_expand "builtin_longjmp"
6747 [(use (match_operand:DI 0 "register_operand" "r"))]
6750 /* The elements of the buffer are, in order: */
6751 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6752 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6753 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
6754 rtx pv = gen_rtx_REG (Pmode, 27);
6756 /* This bit is the same as expand_builtin_longjmp. */
6757 emit_move_insn (hard_frame_pointer_rtx, fp);
6758 emit_move_insn (pv, lab);
6759 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6760 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6761 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6763 /* Load the label we are jumping through into $27 so that we know
6764 where to look for it when we get back to setjmp's function for
6765 restoring the gp. */
6766 emit_jump_insn (gen_builtin_longjmp_internal (pv));
6771 ;; This is effectively a copy of indirect_jump, but constrained such
6772 ;; that register renaming cannot foil our cunning plan with $27.
6773 (define_insn "builtin_longjmp_internal"
6775 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
6779 [(set_attr "type" "ibr")])
6781 (define_expand "builtin_setjmp_receiver"
6782 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6786 (define_insn_and_split "*builtin_setjmp_receiver_1"
6787 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR)]
6790 if (TARGET_EXPLICIT_RELOCS)
6793 return "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)";
6795 "&& TARGET_EXPLICIT_RELOCS && reload_completed"
6797 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
6799 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
6801 if (prev_nonnote_insn (curr_insn) != XEXP (operands[0], 0))
6802 emit_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, operands[0]),
6803 UNSPECV_SETJMPR_ER));
6804 operands[1] = pic_offset_table_rtx;
6805 operands[2] = gen_rtx_REG (Pmode, 27);
6806 operands[3] = GEN_INT (alpha_next_sequence_number++);
6808 [(set_attr "length" "12")
6809 (set_attr "type" "multi")])
6811 (define_insn "*builtin_setjmp_receiver_er_sl_1"
6812 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR_ER)]
6813 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS && TARGET_AS_CAN_SUBTRACT_LABELS"
6814 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
6816 (define_insn "*builtin_setjmp_receiver_er_1"
6817 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR_ER)]
6818 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS"
6819 "br $27,$LSJ%=\n$LSJ%=:"
6820 [(set_attr "type" "ibr")])
6822 (define_expand "exception_receiver"
6823 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
6826 if (TARGET_LD_BUGGY_LDGP)
6827 operands[0] = alpha_gp_save_rtx ();
6829 operands[0] = const0_rtx;
6832 (define_insn "*exception_receiver_2"
6833 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)]
6834 "TARGET_ABI_OSF && TARGET_LD_BUGGY_LDGP"
6836 [(set_attr "type" "ild")])
6838 (define_insn_and_split "*exception_receiver_1"
6839 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
6842 if (TARGET_EXPLICIT_RELOCS)
6843 return "ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*";
6845 return "ldgp $29,0($26)";
6847 "&& TARGET_EXPLICIT_RELOCS && reload_completed"
6849 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6851 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
6853 operands[0] = pic_offset_table_rtx;
6854 operands[1] = gen_rtx_REG (Pmode, 26);
6855 operands[2] = GEN_INT (alpha_next_sequence_number++);
6857 [(set_attr "length" "8")
6858 (set_attr "type" "multi")])
6860 (define_expand "nonlocal_goto_receiver"
6861 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6862 (set (reg:DI 27) (mem:DI (reg:DI 29)))
6863 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6865 "TARGET_ABI_OPEN_VMS"
6868 (define_insn "arg_home"
6869 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6884 (clobber (mem:BLK (const_int 0)))
6885 (clobber (reg:DI 24))
6886 (clobber (reg:DI 25))
6887 (clobber (reg:DI 0))]
6888 "TARGET_ABI_OPEN_VMS"
6889 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
6890 [(set_attr "length" "16")
6891 (set_attr "type" "multi")])
6893 ;; Load the CIW into r2 for calling __T3E_MISMATCH
6895 (define_expand "umk_mismatch_args"
6896 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
6897 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
6898 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
6899 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
6902 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
6903 "TARGET_ABI_UNICOSMK"
6905 operands[1] = gen_reg_rtx (DImode);
6906 operands[2] = gen_reg_rtx (DImode);
6907 operands[3] = gen_reg_rtx (DImode);
6910 (define_insn "arg_home_umk"
6911 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6926 (clobber (mem:BLK (const_int 0)))
6928 (clobber (reg:DI 22))
6929 (clobber (reg:DI 23))
6930 (clobber (reg:DI 24))
6931 (clobber (reg:DI 0))
6932 (clobber (reg:DI 1))
6933 (clobber (reg:DI 2))
6934 (clobber (reg:DI 3))
6935 (clobber (reg:DI 4))
6936 (clobber (reg:DI 5))
6937 (clobber (reg:DI 6))
6938 (clobber (reg:DI 7))
6939 (clobber (reg:DI 8))])]
6940 "TARGET_ABI_UNICOSMK"
6941 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)"
6942 [(set_attr "length" "16")
6943 (set_attr "type" "multi")])
6947 ;; On EV4, these instructions are nops -- no load occurs.
6949 ;; On EV5, these instructions act as a normal load, and thus can trap
6950 ;; if the address is invalid. The OS may (or may not) handle this in
6951 ;; the entMM fault handler and suppress the fault. If so, then this
6952 ;; has the effect of a read prefetch instruction.
6954 ;; On EV6, these become official prefetch instructions.
6956 (define_insn "prefetch"
6957 [(prefetch (match_operand:DI 0 "address_operand" "p")
6958 (match_operand:DI 1 "const_int_operand" "n")
6959 (match_operand:DI 2 "const_int_operand" "n"))]
6960 "TARGET_FIXUP_EV5_PREFETCH || TARGET_CPU_EV6"
6962 /* Interpret "no temporal locality" as this data should be evicted once
6963 it is used. The "evict next" alternatives load the data into the cache
6964 and leave the LRU eviction counter pointing to that block. */
6965 static const char * const alt[2][2] = {
6967 "ldq $31,%a0", /* read, evict next */
6968 "ldl $31,%a0", /* read, evict last */
6971 "ldt $f31,%a0", /* write, evict next */
6972 "lds $f31,%a0", /* write, evict last */
6976 bool write = INTVAL (operands[1]) != 0;
6977 bool lru = INTVAL (operands[2]) != 0;
6979 return alt[write][lru];
6981 [(set_attr "type" "ild")])
6983 ;; Close the trap shadow of preceding instructions. This is generated
6986 (define_insn "trapb"
6987 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
6990 [(set_attr "type" "misc")])
6992 ;; No-op instructions used by machine-dependent reorg to preserve
6993 ;; alignment for instruction issue.
6994 ;; The Unicos/Mk assembler does not support these opcodes.
7000 [(set_attr "type" "ilog")])
7005 "cpys $f31,$f31,$f31"
7006 [(set_attr "type" "fcpys")])
7013 ;; On Unicos/Mk we use a macro for aligning code.
7015 (define_insn "realign"
7016 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
7020 if (TARGET_ABI_UNICOSMK)
7021 return "gcc@code@align %0";
7023 return ".align %0 #realign";
7026 ;; Instructions to be emitted from __builtins.
7028 (define_insn "builtin_cmpbge"
7029 [(set (match_operand:DI 0 "register_operand" "=r")
7030 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ")
7031 (match_operand:DI 2 "reg_or_8bit_operand" "rI")]
7035 ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't
7036 ;; actually differentiate between ILOG and ICMP in the schedule.
7037 [(set_attr "type" "icmp")])
7039 (define_expand "builtin_extbl"
7040 [(match_operand:DI 0 "register_operand" "")
7041 (match_operand:DI 1 "reg_or_0_operand" "")
7042 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7045 rtx (*gen) (rtx, rtx, rtx, rtx);
7046 if (WORDS_BIG_ENDIAN)
7050 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (8), operands[2]));
7054 (define_expand "builtin_extwl"
7055 [(match_operand:DI 0 "register_operand" "")
7056 (match_operand:DI 1 "reg_or_0_operand" "")
7057 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7060 rtx (*gen) (rtx, rtx, rtx, rtx);
7061 if (WORDS_BIG_ENDIAN)
7065 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (16), operands[2]));
7069 (define_expand "builtin_extll"
7070 [(match_operand:DI 0 "register_operand" "")
7071 (match_operand:DI 1 "reg_or_0_operand" "")
7072 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7075 rtx (*gen) (rtx, rtx, rtx, rtx);
7076 if (WORDS_BIG_ENDIAN)
7080 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (32), operands[2]));
7084 (define_expand "builtin_extql"
7085 [(match_operand:DI 0 "register_operand" "")
7086 (match_operand:DI 1 "reg_or_0_operand" "")
7087 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7090 rtx (*gen) (rtx, rtx, rtx, rtx);
7091 if (WORDS_BIG_ENDIAN)
7095 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (64), operands[2]));
7099 (define_expand "builtin_extwh"
7100 [(match_operand:DI 0 "register_operand" "")
7101 (match_operand:DI 1 "reg_or_0_operand" "")
7102 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7105 rtx (*gen) (rtx, rtx, rtx);
7106 if (WORDS_BIG_ENDIAN)
7110 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7114 (define_expand "builtin_extlh"
7115 [(match_operand:DI 0 "register_operand" "")
7116 (match_operand:DI 1 "reg_or_0_operand" "")
7117 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7120 rtx (*gen) (rtx, rtx, rtx);
7121 if (WORDS_BIG_ENDIAN)
7125 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7129 (define_expand "builtin_extqh"
7130 [(match_operand:DI 0 "register_operand" "")
7131 (match_operand:DI 1 "reg_or_0_operand" "")
7132 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7135 rtx (*gen) (rtx, rtx, rtx);
7136 if (WORDS_BIG_ENDIAN)
7140 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7144 (define_expand "builtin_insbl"
7145 [(match_operand:DI 0 "register_operand" "")
7146 (match_operand:DI 1 "register_operand" "")
7147 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7150 rtx (*gen) (rtx, rtx, rtx);
7151 if (WORDS_BIG_ENDIAN)
7155 operands[1] = gen_lowpart (QImode, operands[1]);
7156 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7160 (define_expand "builtin_inswl"
7161 [(match_operand:DI 0 "register_operand" "")
7162 (match_operand:DI 1 "register_operand" "")
7163 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7166 rtx (*gen) (rtx, rtx, rtx);
7167 if (WORDS_BIG_ENDIAN)
7171 operands[1] = gen_lowpart (HImode, operands[1]);
7172 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7176 (define_expand "builtin_insll"
7177 [(match_operand:DI 0 "register_operand" "")
7178 (match_operand:DI 1 "register_operand" "")
7179 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7182 rtx (*gen) (rtx, rtx, rtx);
7183 if (WORDS_BIG_ENDIAN)
7187 operands[1] = gen_lowpart (SImode, operands[1]);
7188 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7189 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7193 (define_expand "builtin_insql"
7194 [(match_operand:DI 0 "register_operand" "")
7195 (match_operand:DI 1 "reg_or_0_operand" "")
7196 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7199 rtx (*gen) (rtx, rtx, rtx);
7200 if (WORDS_BIG_ENDIAN)
7204 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7208 (define_expand "builtin_inswh"
7209 [(match_operand:DI 0 "register_operand" "")
7210 (match_operand:DI 1 "register_operand" "")
7211 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7214 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7218 (define_expand "builtin_inslh"
7219 [(match_operand:DI 0 "register_operand" "")
7220 (match_operand:DI 1 "register_operand" "")
7221 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7224 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7228 (define_expand "builtin_insqh"
7229 [(match_operand:DI 0 "register_operand" "")
7230 (match_operand:DI 1 "register_operand" "")
7231 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7234 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7238 (define_expand "builtin_mskbl"
7239 [(match_operand:DI 0 "register_operand" "")
7240 (match_operand:DI 1 "reg_or_0_operand" "")
7241 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7244 rtx (*gen) (rtx, rtx, rtx, rtx);
7246 if (WORDS_BIG_ENDIAN)
7250 mask = GEN_INT (0xff);
7251 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7255 (define_expand "builtin_mskwl"
7256 [(match_operand:DI 0 "register_operand" "")
7257 (match_operand:DI 1 "reg_or_0_operand" "")
7258 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7261 rtx (*gen) (rtx, rtx, rtx, rtx);
7263 if (WORDS_BIG_ENDIAN)
7267 mask = GEN_INT (0xffff);
7268 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7272 (define_expand "builtin_mskll"
7273 [(match_operand:DI 0 "register_operand" "")
7274 (match_operand:DI 1 "reg_or_0_operand" "")
7275 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7278 rtx (*gen) (rtx, rtx, rtx, rtx);
7280 if (WORDS_BIG_ENDIAN)
7284 mask = immed_double_const (0xffffffff, 0, DImode);
7285 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7289 (define_expand "builtin_mskql"
7290 [(match_operand:DI 0 "register_operand" "")
7291 (match_operand:DI 1 "reg_or_0_operand" "")
7292 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7295 rtx (*gen) (rtx, rtx, rtx, rtx);
7297 if (WORDS_BIG_ENDIAN)
7302 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7306 (define_expand "builtin_mskwh"
7307 [(match_operand:DI 0 "register_operand" "")
7308 (match_operand:DI 1 "register_operand" "")
7309 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7312 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7316 (define_expand "builtin_msklh"
7317 [(match_operand:DI 0 "register_operand" "")
7318 (match_operand:DI 1 "register_operand" "")
7319 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7322 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7326 (define_expand "builtin_mskqh"
7327 [(match_operand:DI 0 "register_operand" "")
7328 (match_operand:DI 1 "register_operand" "")
7329 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7332 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7336 (define_expand "builtin_zap"
7337 [(set (match_operand:DI 0 "register_operand" "")
7339 [(match_operand:DI 2 "reg_or_cint_operand" "")]
7341 (match_operand:DI 1 "reg_or_cint_operand" "")))]
7344 if (GET_CODE (operands[2]) == CONST_INT)
7346 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7348 if (mask == const0_rtx)
7350 emit_move_insn (operands[0], const0_rtx);
7353 if (mask == constm1_rtx)
7355 emit_move_insn (operands[0], operands[1]);
7359 operands[1] = force_reg (DImode, operands[1]);
7360 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7364 operands[1] = force_reg (DImode, operands[1]);
7365 operands[2] = gen_lowpart (QImode, operands[2]);
7368 (define_insn "*builtin_zap_1"
7369 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
7371 [(match_operand:QI 2 "reg_or_cint_operand" "n,n,r,r")]
7373 (match_operand:DI 1 "reg_or_cint_operand" "n,r,J,r")))]
7380 [(set_attr "type" "shift,shift,ilog,shift")])
7383 [(set (match_operand:DI 0 "register_operand" "")
7385 [(match_operand:QI 2 "const_int_operand" "")]
7387 (match_operand:DI 1 "const_int_operand" "")))]
7391 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7392 if (HOST_BITS_PER_WIDE_INT >= 64 || GET_CODE (mask) == CONST_INT)
7393 operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode);
7396 HOST_WIDE_INT c_lo = INTVAL (operands[1]);
7397 HOST_WIDE_INT c_hi = (c_lo < 0 ? -1 : 0);
7398 operands[1] = immed_double_const (c_lo & CONST_DOUBLE_LOW (mask),
7399 c_hi & CONST_DOUBLE_HIGH (mask),
7402 emit_move_insn (operands[0], operands[1]);
7407 [(set (match_operand:DI 0 "register_operand" "")
7409 [(match_operand:QI 2 "const_int_operand" "")]
7411 (match_operand:DI 1 "register_operand" "")))]
7414 (and:DI (match_dup 1) (match_dup 2)))]
7416 operands[2] = alpha_expand_zap_mask (INTVAL (operands[2]));
7417 if (operands[2] == const0_rtx)
7419 emit_move_insn (operands[0], const0_rtx);
7422 if (operands[2] == constm1_rtx)
7424 emit_move_insn (operands[0], operands[1]);
7429 (define_expand "builtin_zapnot"
7430 [(set (match_operand:DI 0 "register_operand" "")
7432 [(not:QI (match_operand:DI 2 "reg_or_cint_operand" ""))]
7434 (match_operand:DI 1 "reg_or_cint_operand" "")))]
7437 if (GET_CODE (operands[2]) == CONST_INT)
7439 rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2]));
7441 if (mask == const0_rtx)
7443 emit_move_insn (operands[0], const0_rtx);
7446 if (mask == constm1_rtx)
7448 emit_move_insn (operands[0], operands[1]);
7452 operands[1] = force_reg (DImode, operands[1]);
7453 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7457 operands[1] = force_reg (DImode, operands[1]);
7458 operands[2] = gen_lowpart (QImode, operands[2]);
7461 (define_insn "*builtin_zapnot_1"
7462 [(set (match_operand:DI 0 "register_operand" "=r")
7464 [(not:QI (match_operand:QI 2 "register_operand" "r"))]
7466 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
7469 [(set_attr "type" "shift")])
7471 (define_insn "builtin_amask"
7472 [(set (match_operand:DI 0 "register_operand" "=r")
7473 (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")]
7477 [(set_attr "type" "ilog")])
7479 (define_insn "builtin_implver"
7480 [(set (match_operand:DI 0 "register_operand" "=r")
7481 (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))]
7484 [(set_attr "type" "ilog")])
7486 (define_insn "builtin_rpcc"
7487 [(set (match_operand:DI 0 "register_operand" "=r")
7488 (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))]
7491 [(set_attr "type" "ilog")])
7493 (define_expand "builtin_minub8"
7494 [(match_operand:DI 0 "register_operand" "")
7495 (match_operand:DI 1 "reg_or_0_operand" "")
7496 (match_operand:DI 2 "reg_or_0_operand" "")]
7499 alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0],
7500 operands[1], operands[2]);
7504 (define_expand "builtin_minsb8"
7505 [(match_operand:DI 0 "register_operand" "")
7506 (match_operand:DI 1 "reg_or_0_operand" "")
7507 (match_operand:DI 2 "reg_or_0_operand" "")]
7510 alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0],
7511 operands[1], operands[2]);
7515 (define_expand "builtin_minuw4"
7516 [(match_operand:DI 0 "register_operand" "")
7517 (match_operand:DI 1 "reg_or_0_operand" "")
7518 (match_operand:DI 2 "reg_or_0_operand" "")]
7521 alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0],
7522 operands[1], operands[2]);
7526 (define_expand "builtin_minsw4"
7527 [(match_operand:DI 0 "register_operand" "")
7528 (match_operand:DI 1 "reg_or_0_operand" "")
7529 (match_operand:DI 2 "reg_or_0_operand" "")]
7532 alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0],
7533 operands[1], operands[2]);
7537 (define_expand "builtin_maxub8"
7538 [(match_operand:DI 0 "register_operand" "")
7539 (match_operand:DI 1 "reg_or_0_operand" "")
7540 (match_operand:DI 2 "reg_or_0_operand" "")]
7543 alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0],
7544 operands[1], operands[2]);
7548 (define_expand "builtin_maxsb8"
7549 [(match_operand:DI 0 "register_operand" "")
7550 (match_operand:DI 1 "reg_or_0_operand" "")
7551 (match_operand:DI 2 "reg_or_0_operand" "")]
7554 alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0],
7555 operands[1], operands[2]);
7559 (define_expand "builtin_maxuw4"
7560 [(match_operand:DI 0 "register_operand" "")
7561 (match_operand:DI 1 "reg_or_0_operand" "")
7562 (match_operand:DI 2 "reg_or_0_operand" "")]
7565 alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0],
7566 operands[1], operands[2]);
7570 (define_expand "builtin_maxsw4"
7571 [(match_operand:DI 0 "register_operand" "")
7572 (match_operand:DI 1 "reg_or_0_operand" "")
7573 (match_operand:DI 2 "reg_or_0_operand" "")]
7576 alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0],
7577 operands[1], operands[2]);
7581 (define_insn "builtin_perr"
7582 [(set (match_operand:DI 0 "register_operand" "=r")
7583 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ")
7584 (match_operand:DI 2 "reg_or_8bit_operand" "rJ")]
7588 [(set_attr "type" "mvi")])
7590 (define_expand "builtin_pklb"
7591 [(set (match_operand:DI 0 "register_operand" "")
7594 (truncate:V2QI (match_operand:DI 1 "register_operand" ""))
7599 operands[0] = gen_lowpart (V8QImode, operands[0]);
7600 operands[1] = gen_lowpart (V2SImode, operands[1]);
7601 operands[2] = CONST0_RTX (V2QImode);
7602 operands[3] = CONST0_RTX (V4QImode);
7605 (define_insn "*pklb"
7606 [(set (match_operand:V8QI 0 "register_operand" "=r")
7609 (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r"))
7610 (match_operand:V2QI 2 "const0_operand" ""))
7611 (match_operand:V4QI 3 "const0_operand" "")))]
7614 [(set_attr "type" "mvi")])
7616 (define_expand "builtin_pkwb"
7617 [(set (match_operand:DI 0 "register_operand" "")
7619 (truncate:V4QI (match_operand:DI 1 "register_operand" ""))
7623 operands[0] = gen_lowpart (V8QImode, operands[0]);
7624 operands[1] = gen_lowpart (V4HImode, operands[1]);
7625 operands[2] = CONST0_RTX (V4QImode);
7628 (define_insn "*pkwb"
7629 [(set (match_operand:V8QI 0 "register_operand" "=r")
7631 (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r"))
7632 (match_operand:V4QI 2 "const0_operand" "")))]
7635 [(set_attr "type" "mvi")])
7637 (define_expand "builtin_unpkbl"
7638 [(set (match_operand:DI 0 "register_operand" "")
7640 (vec_select:V2QI (match_operand:DI 1 "register_operand" "")
7641 (parallel [(const_int 0) (const_int 1)]))))]
7644 operands[0] = gen_lowpart (V2SImode, operands[0]);
7645 operands[1] = gen_lowpart (V8QImode, operands[1]);
7648 (define_insn "*unpkbl"
7649 [(set (match_operand:V2SI 0 "register_operand" "=r")
7651 (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7652 (parallel [(const_int 0) (const_int 1)]))))]
7655 [(set_attr "type" "mvi")])
7657 (define_expand "builtin_unpkbw"
7658 [(set (match_operand:DI 0 "register_operand" "")
7660 (vec_select:V4QI (match_operand:DI 1 "register_operand" "")
7661 (parallel [(const_int 0)
7667 operands[0] = gen_lowpart (V4HImode, operands[0]);
7668 operands[1] = gen_lowpart (V8QImode, operands[1]);
7671 (define_insn "*unpkbw"
7672 [(set (match_operand:V4HI 0 "register_operand" "=r")
7674 (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7675 (parallel [(const_int 0)
7681 [(set_attr "type" "mvi")])
7683 (define_expand "builtin_cttz"
7684 [(set (match_operand:DI 0 "register_operand" "")
7685 (unspec:DI [(match_operand:DI 1 "register_operand" "")]
7690 (define_insn "builtin_ctlz"
7691 [(set (match_operand:DI 0 "register_operand" "=r")
7692 (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
7696 [(set_attr "type" "mvi")])
7698 (define_insn "builtin_ctpop"
7699 [(set (match_operand:DI 0 "register_operand" "=r")
7700 (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
7704 [(set_attr "type" "mvi")])
7706 ;; The call patterns are at the end of the file because their
7707 ;; wildcard operand0 interferes with nice recognition.
7709 (define_insn "*call_value_osf_1_er"
7710 [(set (match_operand 0 "" "")
7711 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7712 (match_operand 2 "" "")))
7714 (clobber (reg:DI 26))]
7715 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7717 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
7718 bsr $26,%1\t\t!samegp
7719 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
7720 [(set_attr "type" "jsr")
7721 (set_attr "length" "12,*,16")])
7723 ;; We must use peep2 instead of a split because we need accurate life
7724 ;; information for $gp. Consider the case of { bar(); while (1); }.
7726 [(parallel [(set (match_operand 0 "" "")
7727 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7728 (match_operand 2 "" "")))
7730 (clobber (reg:DI 26))])]
7731 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7732 && ! samegp_function_operand (operands[1], Pmode)
7733 && (peep2_regno_dead_p (1, 29)
7734 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
7735 [(parallel [(set (match_dup 0)
7736 (call (mem:DI (match_dup 3))
7738 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7739 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7741 (use (match_dup 4))])]
7743 if (CONSTANT_P (operands[1]))
7745 operands[3] = gen_rtx_REG (Pmode, 27);
7746 operands[4] = GEN_INT (alpha_next_sequence_number++);
7747 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7748 operands[1], operands[4]));
7752 operands[3] = operands[1];
7753 operands[1] = const0_rtx;
7754 operands[4] = const0_rtx;
7759 [(parallel [(set (match_operand 0 "" "")
7760 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7761 (match_operand 2 "" "")))
7763 (clobber (reg:DI 26))])]
7764 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7765 && ! samegp_function_operand (operands[1], Pmode)
7766 && ! (peep2_regno_dead_p (1, 29)
7767 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
7768 [(parallel [(set (match_dup 0)
7769 (call (mem:DI (match_dup 3))
7771 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7772 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7774 (use (match_dup 5))])
7776 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7778 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
7780 if (CONSTANT_P (operands[1]))
7782 operands[3] = gen_rtx_REG (Pmode, 27);
7783 operands[5] = GEN_INT (alpha_next_sequence_number++);
7784 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7785 operands[1], operands[5]));
7789 operands[3] = operands[1];
7790 operands[1] = const0_rtx;
7791 operands[5] = const0_rtx;
7793 operands[4] = GEN_INT (alpha_next_sequence_number++);
7796 ;; We add a blockage unspec_volatile to prevent insns from moving down
7797 ;; from above the call to in between the call and the ldah gpdisp.
7798 (define_insn "*call_value_osf_2_er"
7799 [(set (match_operand 0 "" "")
7800 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
7801 (match_operand 2 "" "")))
7803 (plus:DI (pc) (const_int 4)))
7804 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7805 (use (match_operand 3 "" ""))
7806 (use (match_operand 4 "" ""))]
7807 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7808 "jsr $26,(%1),%3%J4"
7809 [(set_attr "type" "jsr")
7810 (set_attr "cannot_copy" "true")])
7812 (define_insn "*call_value_osf_1_noreturn"
7813 [(set (match_operand 0 "" "")
7814 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7815 (match_operand 2 "" "")))
7817 (clobber (reg:DI 26))]
7818 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
7819 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7824 [(set_attr "type" "jsr")
7825 (set_attr "length" "*,*,8")])
7827 (define_insn_and_split "call_value_osf_tlsgd"
7828 [(set (match_operand 0 "" "")
7829 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
7831 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSGD_CALL)
7833 (clobber (reg:DI 26))]
7836 "&& reload_completed"
7838 (unspec:DI [(match_dup 5)
7840 (match_dup 2)] UNSPEC_LITERAL))
7841 (parallel [(set (match_dup 0)
7842 (call (mem:DI (match_dup 3))
7844 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7845 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
7847 (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL))])
7849 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7851 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
7853 operands[3] = gen_rtx_REG (Pmode, 27);
7854 operands[4] = GEN_INT (alpha_next_sequence_number++);
7855 operands[5] = pic_offset_table_rtx;
7857 [(set_attr "type" "multi")])
7859 (define_insn_and_split "call_value_osf_tlsldm"
7860 [(set (match_operand 0 "" "")
7861 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
7863 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSLDM_CALL)
7865 (clobber (reg:DI 26))]
7868 "&& reload_completed"
7870 (unspec:DI [(match_dup 5)
7872 (match_dup 2)] UNSPEC_LITERAL))
7873 (parallel [(set (match_dup 0)
7874 (call (mem:DI (match_dup 3))
7876 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7877 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
7879 (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL))])
7881 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7883 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
7885 operands[3] = gen_rtx_REG (Pmode, 27);
7886 operands[4] = GEN_INT (alpha_next_sequence_number++);
7887 operands[5] = pic_offset_table_rtx;
7889 [(set_attr "type" "multi")])
7891 (define_insn "*call_value_osf_1"
7892 [(set (match_operand 0 "" "")
7893 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7894 (match_operand 2 "" "")))
7896 (clobber (reg:DI 26))]
7897 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7899 jsr $26,($27),0\;ldgp $29,0($26)
7901 jsr $26,%1\;ldgp $29,0($26)"
7902 [(set_attr "type" "jsr")
7903 (set_attr "length" "12,*,16")])
7905 (define_insn "*sibcall_value_osf_1_er"
7906 [(set (match_operand 0 "" "")
7907 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
7908 (match_operand 2 "" "")))
7909 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
7910 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7912 br $31,%1\t\t!samegp
7913 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#"
7914 [(set_attr "type" "jsr")
7915 (set_attr "length" "*,8")])
7917 (define_insn "*sibcall_value_osf_1"
7918 [(set (match_operand 0 "" "")
7919 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
7920 (match_operand 2 "" "")))
7921 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
7922 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7925 lda $27,%1\;jmp $31,($27),%1"
7926 [(set_attr "type" "jsr")
7927 (set_attr "length" "*,8")])
7929 (define_insn "*call_value_nt_1"
7930 [(set (match_operand 0 "" "")
7931 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,s"))
7932 (match_operand 2 "" "")))
7933 (clobber (reg:DI 26))]
7934 "TARGET_ABI_WINDOWS_NT"
7939 [(set_attr "type" "jsr")
7940 (set_attr "length" "*,*,12")])
7942 ; GAS relies on the order and position of instructions output below in order
7943 ; to generate relocs for VMS link to potentially optimize the call.
7944 ; Please do not molest.
7945 (define_insn "*call_value_vms_1"
7946 [(set (match_operand 0 "" "")
7947 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
7948 (match_operand 2 "" "")))
7949 (use (match_operand:DI 3 "nonmemory_operand" "r,n"))
7952 (clobber (reg:DI 27))]
7953 "TARGET_ABI_OPEN_VMS"
7955 switch (which_alternative)
7958 return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)";
7960 operands [3] = alpha_use_linkage (operands [1], cfun->decl, 1, 0);
7961 operands [4] = alpha_use_linkage (operands [1], cfun->decl, 0, 0);
7962 return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)";
7967 [(set_attr "type" "jsr")
7968 (set_attr "length" "12,16")])
7970 (define_insn "*call_value_umk"
7971 [(set (match_operand 0 "" "")
7972 (call (mem:DI (match_operand:DI 1 "call_operand" "r"))
7973 (match_operand 2 "" "")))
7975 (clobber (reg:DI 26))]
7976 "TARGET_ABI_UNICOSMK"
7978 [(set_attr "type" "jsr")])