sys/dev/vme/xdreg.h

   1 /*      $NetBSD: xdreg.h,v 1.5 2005/12/11 12:24:07 christos Exp $       */
   2
   3 /*
   4  *
   5  * Copyright (c) 1995 Charles D. Cranor
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. All advertising materials mentioning features or use of this software
  17  *    must display the following acknowledgement:
  18  *      This product includes software developed by Charles D. Cranor.
  19  * 4. The name of the author may not be used to endorse or promote products
  20  *    derived from this software without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  25  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /*
  35  * x d r e g . h
  36  *
  37  * this file contains the description of the Xylogics 753/7053's hardware
  38  * data structures.
  39  *
  40  * author: Chuck Cranor <chuck@ccrc.wustl.edu>
  41  */
  42
  43 #define XDC_MAXDEV    4       /* max devices per controller */
  44 #define XDC_RESETUSEC 1000000 /* max time for xdc reset (page 21 says 1sec) */
  45 #define XDC_MAXIOPB   31      /* max number of iopbs that can be active */
  46 #define XDC_MAXTIME   4*1000000 /* four seconds before we give up and reset */
  47 #define XDC_MAXTRIES  4       /* max number of times to retry an operation */
  48 #define XDC_THROTTLE  32      /* DMA throttle */
  49 #define XDC_INTERLEAVE 0      /* interleave (for format param) */
  50 #define XDC_DPARAM     0      /* dparam (drive param) XDDP_EC32 or 0 */
  51
  52 /*
  53  * xdc device interface
  54  * (lives in VME address space)
  55  */
  56
  57 struct xdc {
  58   volatile u_char filler0;
  59   volatile u_char xdc_iopbaddr0;       /* iopb byte 0 (LSB) */
  60   volatile u_char filler1;
  61   volatile u_char xdc_iopbaddr1;       /* iopb byte 1 */
  62   volatile u_char filler2;
  63   volatile u_char xdc_iopbaddr2;       /* iopb byte 2 */
  64   volatile u_char filler3;
  65   volatile u_char xdc_iopbaddr3;       /* iopb byte 3 (MSB) */
  66   volatile u_char filler4;
  67   volatile u_char xdc_iopbamod;        /* iopb address modifier */
  68   volatile u_char filler5;
  69   volatile u_char xdc_csr;             /* control and status register */
  70   volatile u_char filler6;
  71   volatile u_char xdc_f_err;           /* fatal error register */
  72 };
  73
  74 /*
  75  * xdc_iopbamod: addressing modes
  76  * When doing DMA, if the maximum address of the buffer is greater than
  77  * 24 bits then you must use the 32 bit mode.   Note that on many systems
  78  * (e.g. sun-4/300) DVMA space is smaller than 24 bits, so there is no
  79  * need for the 32 bit mode.   However, the 32-bit mode hooks are in
  80  * the driver in case it ever gets ported to an environment that needs it.
  81  */
  82
  83 #define XDC_ADDRMOD   0x3d    /* standard address modifer, 24 bit max */
  84 #define XDC_ADDRMOD32 0x0d    /* 32 bit version above */
  85
  86 /*
  87  * xdc_csr
  88  */
  89
  90 #define XDC_RMAINTMD 0x80     /* reserved maintenance mode (write) */
  91 #define XDC_BUSY     0x80     /* busy (read) */
  92 #define XDC_F_ERROR  0x40     /* fatal error (read) */
  93 #define XDC_MAINTMOD 0x20     /* maintenance mode (read/write) */
  94 #define XDC_RESET    0x08     /* soft reset (read/write) */
  95 #define XDC_ADDIOPB  0x04     /* add iopb/add pending (write) */
  96 #define XDC_ADDING   0x04     /* iopb add is pending (read) */
  97 #define XDC_CLRRIO   0x02     /* clear RIO (remove iopb) request (write) */
  98 #define XDC_REMIOPB  0x02     /* remove iopb (read) */
  99 #define XDC_RBUSYSEM 0x01     /* register busy semaphore (read/write) */
 100
 101 /*
 102  * Input/Output Parameter Block (iopb)
 103  *
 104  * all controller commands are done via iopb's.   to start a command you
 105  * must do this:
 106  * [1] allocate space in DVMA space for the iopb
 107  * [2] fill out all the fields of the iopb
 108  * [3] check to see if controller can accept an iopb (XDC_ADDING bit clear)
 109  * [4] put the DVMA address of the iopb in the xdc registers (in vme space)
 110  * [5] set the XDC_ADDIOPB bit in the xdc csr
 111  * [6] <command started>
 112  *
 113  * when the controller is done with a command it may interrupt (if you
 114  * ask it to) and it will set the XDC_REMIOPB bit in the csr.   the address
 115  * of the finished iopb will be in the xdc registers.   after that is
 116  * read, set the XDC_CLRRIO to clear the iopb out of memory.
 117  *
 118  * the format of the iopb is described in section 4 of the manual.
 119  */
 120
 121 struct xd_iopb {
 122                                  /* section 4.1.1: byte 0 */
 123   volatile u_char errs:1;        /* error summary bit, only valid if
 124                                     "done" is set.  must clear "done"
 125                                     and "errs" bits before starting an
 126                                     operation */
 127   volatile u_char done:1;        /* "done" bit */
 128   volatile u_char chen:1;        /* chain enable, "next iopb" is valid,
 129                                     note xd returns one iopb at a time */
 130   volatile u_char sgm:1;         /* scatter/gather mode */
 131   volatile u_char comm:4;        /* command number (see table 4-2) */
 132 #define XDCMD_NOP 0x0            /* no-op */
 133 #define XDCMD_WR  0x1            /* write */
 134 #define XDCMD_RD  0x2            /* read */
 135 #define XDCMD_SK  0x3            /* seek */
 136 #define XDCMD_RST 0x4            /* drive reset */
 137 #define XDCMD_WRP 0x5            /* write params */
 138 #define XDCMD_RDP 0x6            /* read params */
 139 #define XDCMD_XWR 0x7            /* extended write */
 140 #define XDCMD_XRD 0x8            /* extended read */
 141 #define XDCMD_TST 0x9            /* diagnostic tests */
 142                                  /* 0xa to 0xf are reserved */
 143                                  /* section 4.1.2: byte 1 */
 144   volatile u_char errnum;        /* status byte 1 (non-zero if error) */
 145                                  /* section 4.1.3: byte 2 */
 146   volatile u_char status;        /* status byte 2 (see below) */
 147 #define XDST_SR   0x40           /* slipped revolution */
 148 #define XDST_CSE  0x20           /* count sectors executed */
 149 #define XDST_WRPT 0x10           /* write protected drive */
 150 #define XDST_DFLT 0x08           /* disk fault */
 151 #define XDST_SKER 0x04           /* seek error: >max, or timeout */
 152 #define XDST_ONCL 0x02           /* on-cylinder */
 153 #define XDST_DRDY 0x01           /* drive is ready! */
 154                                  /* section 4.1.4: byte 3 */
 155   volatile u_char istat;         /* internal status: reserved for xylogics */
 156                                  /* section 4.1.5: byte 4 */
 157   volatile u_char subfun;        /* sub-function of command (see below) */
 158 #define XDFUN_R   0x00           /* XDCMD_SK: report current addr */
 159 #define XDFUN_SR  0x01           /* XDCMD_SK: seek and report addr */
 160 #define XDFUN_SRI 0x02           /* XDCMD_SK: start seek, report comp imm */
 161 #define XDFUN_CTL 0x00           /* XDCMD_{WRP,RDP}: controller params */
 162 #define XDFUN_DRV 0x80           /* XDCMD_{WRP,RDP}: drive params */
 163 #define XDFUN_FMT 0x81           /* XDCMD_{WRP,RDP}: format params,XWR form.*/
 164 #define XDFUN_STX 0xa0           /* XDCMD_RDP: read drive status extended */
 165 #define XDFUN_THD 0x80           /* XDCMD_{XWR,XRD}: track headers */
 166 #define XDFUN_VFY 0x81           /* XDCMD_XRD: verify data */
 167 #define XDFUN_HDR 0x82           /* XDCMD_{XWR,XRD}: header, verify,data, ecc*/
 168 #define XDFUN_DM  0xa0           /* XDCMD_{XWR,XRD}: defect map */
 169 #define XDFUN_DMX 0xa1           /* XDCMD_{XWR,XRD}: defect map extended */
 170                                  /* section 4.1.6: byte 5 */
 171   volatile u_char fixd:1;        /* fixed media (vs removable) */
 172   volatile u_char reserved1:4;   /* reserved */
 173   volatile u_char unit:3;        /* unit number */
 174                                  /* note: 6 to 13 are overloaded (see below) */
 175                                  /* section 4.1.7: byte 6 */
 176   volatile u_char lll:5;         /* linked list length */
 177   volatile u_char intl:3;        /* interrupt level */
 178                                  /* section 4.1.8: byte 7 */
 179   volatile u_char intr_vec;      /* interrupt vector */
 180                                  /* section 4.1.9: bytes 8 and 9 */
 181   volatile u_short sectcnt;      /* sector count (# to xfer) */
 182                                  /* section 4.1.10: byte a and b */
 183   volatile u_short cylno;        /* cylinder number */
 184                                  /* section 4.1.11: byte c */
 185   volatile u_char headno;        /* head number */
 186                                  /* section 4.1.12: byte d */
 187   volatile u_char sectno;        /* sector number */
 188                                  /* section 4.1.13: byte e */
 189   volatile u_char addrmod;       /* addr modifier (bits 7,6 must be zero) */
 190                                  /* section 4.1.14: byte f */
 191   volatile u_char naddrmod;      /* next (in chain) address iobp ad. modifer */
 192                                  /* section 4.1.15: bytes 0x10 to 0x13 */
 193   volatile u_long daddr;         /* DMA data address */
 194                                  /* section 4.1.16: bytes 0x14 to 0x17 */
 195   volatile u_long nextiopb;      /* next iopb (in chain) address */
 196                                  /* section 4.1.17: bytes 0x18, 0x19 */
 197   volatile u_short cksum;        /* iopb checksum */
 198                                  /* section 4.1.18: bytes 0x1a, 0x1b */
 199   volatile u_short eccpattern;   /* ECC pattern word (ecc mode 0) */
 200                                  /* section 4.1.19: bytes 0x1c, 0x1d */
 201   volatile u_short eccoffword;   /* ECC offset word (ecc mode 0) */
 202 };
 203
 204 /*
 205  * some commands overload bytes 6 to 0x13 of the iopb with different meanings.
 206  * these commands include:
 207  *   section 4.2: controller parameters
 208  *   section 4.3: drive parameters
 209  *   sectino 4.4: format parameters
 210  *
 211  * note that the commands that overload the iopb are not part of the
 212  * "critical data path" of the driver.   so, we handle them by defining
 213  * alternate iopb structures for these commands... it only costs us an
 214  * extra pointer.
 215  */
 216
 217 /*
 218  * controller parameters iopb: redefines bytes: 8 -> 0xe, 0x10 -> 0x13
 219  */
 220
 221 struct xd_iopb_ctrl {
 222   volatile u_char same[8];       /* same as xd_iopb */
 223                                  /* section 4.2.1: byte 8 */
 224   volatile u_char param_a;       /* param A (see below) */
 225 #define XDPA_AUD  0x80           /* auto-update iopb fields when cmd done */
 226 #define XDPA_TMOD 0x40           /* long-word transfer mode (vs word) */
 227 #define XDPA_DACF 0x20           /* ignore vme ACFAIL signal */
 228 #define XDPA_ICS  0x10           /* checksum check (adds 100usec per xfer) */
 229 #define XDPA_EDT  0x08           /* enable on-board DMA timeout timer */
 230 #define XDPA_NPRM 0x04           /* enable VME non-priv request mode */
 231                                  /* rest must be zero */
 232                                  /* section 4.2.2: byte 9 */
 233   volatile u_char param_b;       /* param B (see below) */
 234 #define XDPB_TDT 0xc0            /* throttle dead time (see 8.11, below) */
 235 #define XDPB_ROR 0x10            /* release on request */
 236 #define XDPB_DRA 0x01            /* disable read ahead */
 237                                  /* TDT values: */
 238 #define XDPB_TDT_0USEC    0x00   /* no TDT */
 239 #define XDPB_TDT_3_2USEC  0x40   /* 3.2 usec */
 240 #define XDPB_TDT_6_4USEC  0x80   /* 6.4 usec */
 241 #define XDPB_TDT_12_8USEC 0xc0   /* 12.8 usec */
 242                                  /* section 4.2.3: byte a */
 243   volatile u_char param_c;       /* param C (see below) */
 244 #define XDPC_OVS  0x80           /* over-lapped seek */
 245 #define XDPC_COP  0x40           /* command optimiziation (elevator alg.) */
 246 #define XDPC_ASR  0x10           /* auto-seek retry */
 247 #define XDPC_RBC  0x04           /* retry before correction if ECC error */
 248 #define XDPC_ECCM 0x03           /* ECC mode (0, 1, and 2) */
 249 #define XDPC_ECC0 0x00           /* ECC mode 0 */
 250 #define XDPC_ECC1 0x01           /* ECC mode 1 */
 251 #define XDPC_ECC2 0x02           /* ECC mode 2 */
 252                                  /* section 4.2.4: byte b */
 253   volatile u_char throttle;      /* max DMA xfers per master (0==256) */
 254                                  /* section 4.2.5: byte c */
 255   volatile u_char eprom_lvl;     /* EPROM release level */
 256   volatile u_char delay;         /* delay (see note below) */
 257                                  /* section 4.2.6: byte e */
 258   volatile u_char ctype;         /* controller type */
 259 #define XDCT_753 0x53            /* xylogic 753/7053 */
 260   volatile u_char same2;         /* byte f: same as xd_iopb */
 261                                  /* section 4.2.7: byte 0x10, 0x11 */
 262   volatile u_short eprom_partno; /* eprom part number */
 263                                  /* section 4.2.8: byte 12 */
 264   volatile u_char eprom_rev;     /* eprom revision number */
 265 };
 266
 267 /*
 268  * Note on byte 0xd ("delay"): This byte is not documented in the
 269  * Xylogics manual.  However, I contacted Xylogics and found out what
 270  * it does.  The controller sorts read commands into groups of
 271  * contiguous sectors.  After it processes a group of contiguous
 272  * sectors rather than immediately going on to the next group of
 273  * contiguous sectors, the controller can delay for a certain amount
 274  * of time in hopes of getting another cluster of reads in the same
 275  * area of the disk (thus avoiding a long seek).  Byte 0xd controls
 276  * how long it waits before giving up and going on and doing the next
 277  * contiguous cluster.
 278  *
 279  * it is unclear what unit the delay is in, but it looks like sun
 280  * uses the value "20" for sun3's, and "0" for sparc, except for the
 281  * 4/300 (where it is "4").   [see /sys/sundev/xd_conf.c on any 4.1.3
 282  * machine for how sun configures its controller...]
 283  */
 284
 285 #define XDC_DELAY_SUN3  20
 286 #define XDC_DELAY_4_300 4
 287 #define XDC_DELAY_SPARC 0
 288
 289 /*
 290  * drive parameters iopb: redefines bytes: 6, 8, 9, a, b, c, d, e
 291  */
 292
 293 struct xd_iopb_drive {
 294   volatile u_char same[6];       /* same as xd_iopb */
 295                                  /* section 4.3.1: byte 6 */
 296   volatile u_char dparam_ipl;    /* drive params | interrupt level */
 297 #define XDDP_EC32 0x10           /* 32 bit ECC mode */
 298   volatile u_char same1;         /* byte 7: same */
 299                                  /* section 4.3.2: byte 8 */
 300   volatile u_char maxsect;       /* max sector/last head (<= byte d) */
 301                                  /* section 4.3.3: byte 9 */
 302   volatile u_char headoff;       /* head offset */
 303                                  /* section 4.3.4: bytes 0xa, 0xb */
 304   volatile u_short maxcyl;       /* max cyl (zero based!) */
 305                                  /* section 4.3.5: byte 0xc */
 306   volatile u_char maxhead;       /* max head (zero based!) */
 307                                  /* section 4.3.6: byte 0xd */
 308   volatile u_char maxsector;     /* max sector of disk (zero based!) */
 309                                  /* section 4.3.7: byte 0xe */
 310   volatile u_char sectpertrk;    /* sectors per track, not zero base, no runt*/
 311 };
 312
 313 /*
 314  * format parameters iopb: redefines bytes: 6, 8, 9, a, b, c, d, 0x10, 0x11
 315  */
 316
 317 struct xd_iopb_format {
 318   volatile u_char same[6];       /* smae as xd_iopb */
 319                                  /* section 4.4.1: byte 6 */
 320   volatile u_char interleave_ipl;/* (interleave << 4) | interrupt level */
 321                                  /* interleave ratio 1:1 to 16:1 */
 322   volatile u_char same1;         /* byte 7: same */
 323                                  /* section 4.4.2: byte 8 */
 324   volatile u_char field1;        /* >= 1, xylogic says should be 1 */
 325 #define XDFM_FIELD1 0x01         /* xylogic value */
 326                                  /* section 4.4.3: byte 9 */
 327   volatile u_char field2;        /* >0, field1+field2 <= 255 */
 328 #define XDFM_FIELD2 0x0a         /* xylogic value */
 329                                  /* section 4.4.4: byte a */
 330   volatile u_char field3;        /* >= field1+field2 */
 331 #define XDFM_FIELD3 0x1b         /* xylogic value */
 332                                  /* section 4.4.5: byte b */
 333   volatile u_char field4;        /* field4 */
 334 #define XDFM_FIELD4 0x14         /* xylogic value */
 335                                  /* section 4.4.6: bytes 0xc, 0xd */
 336   volatile u_short bytespersec;  /* bytes per sector */
 337 #define XDFM_BPS    0x200        /* must be 512! */
 338   volatile u_char same2[2];      /* bytes e, f */
 339                                  /* section 4.4.7: byte 0x10 */
 340   volatile u_char field6;        /* field 6 */
 341 #define XDFM_FIELD6 0x0a         /* xylogic value */
 342                                  /* section 4.4.8: byte 0x11 */
 343   volatile u_char field7;        /* field 7, >= 1 */
 344 #define XDFM_FIELD7 0x03         /* xylogic value */
 345 };
 346
 347
 348 /*
 349  * errors: errors come from either the fatal error register or the
 350  * iopb
 351  */
 352
 353 #define XD_ERA_MASK 0xf0         /* error action mask */
 354 #define XD_ERA_PROG 0x10         /* program error */
 355 #define XD_ERA_PRG2 0x20         /* program error */
 356 #define XD_ERA_SOFT 0x30         /* soft error: we recovered */
 357 #define XD_ERA_HARD 0x40         /* hard error: retry */
 358 #define XD_ERA_RSET 0x60         /* hard error: reset, then retry */
 359 #define XD_ERA_WPRO 0x90         /* write protected */
 360
 361 /* software error codes */
 362 #define XD_ERR_FAIL 0xff         /* general total failure */
 363 /* no error */
 364 #define XD_ERR_AOK  0x00         /* success */
 365 /* non-retryable programming error */
 366 #define XD_ERR_ICYL 0x10         /* illegal cyl */
 367 #define XD_ERR_IHD  0x11         /* illegal head */
 368 #define XD_ERR_ISEC 0x12         /* illegal sector */
 369 #define XD_ERR_CZER 0x13         /* count zero */
 370 #define XD_ERR_UIMP 0x14         /* unknown command */
 371 #define XD_ERR_IF1  0x15         /* illegal field 1 */
 372 #define XD_ERR_IF2  0x16         /* illegal field 2 */
 373 #define XD_ERR_IF3  0x17         /* illegal field 3 */
 374 #define XD_ERR_IF4  0x18         /* illegal field 4 */
 375 #define XD_ERR_IF5  0x19         /* illegal field 5 */
 376 #define XD_ERR_IF6  0x1a         /* illegal field 6 */
 377 #define XD_ERR_IF7  0x1b         /* illegal field 7 */
 378 #define XD_ERR_ISG  0x1c         /* illegal scatter/gather */
 379 #define XD_ERR_ISPT 0x1d         /* not enough sectors per track */
 380 #define XD_ERR_ALGN 0x1e         /* next iopb allignment error */
 381 #define XD_ERR_SGAL 0x1f         /* scatter gather address alignment error */
 382 #define XD_ERR_SGEC 0x20         /* scatter gather with auto ECC */
 383 /* successfully recovered soft errors */
 384 #define XD_ERR_SECC 0x30         /* soft ecc corrected */
 385 #define XD_ERR_SIGN 0x31         /* ecc ignored */
 386 #define XD_ERR_ASEK 0x32         /* auto-seek retry recovered */
 387 #define XD_ERR_RTRY 0x33         /* soft retry recovered */
 388 /* hard errors: please retry */
 389 #define XD_ERR_HECC 0x40         /* hard data ECC */
 390 #define XD_ERR_NHDR 0x41         /* header not found */
 391 #define XD_ERR_NRDY 0x42         /* drive not ready */
 392 #define XD_ERR_TOUT 0x43         /* timeout */
 393 #define XD_ERR_VTIM 0x44         /* VME DMA timeout */
 394 #define XD_ERR_DSEQ 0x45         /* disk sequencer error */
 395 #define XD_ERR_HDEC 0x48         /* header ECC error */
 396 #define XD_ERR_RVFY 0x49         /* ready verify */
 397 #define XD_ERR_VFER 0x4a         /* fatal VME DMA error */
 398 #define XD_ERR_VBUS 0x4b         /* VME bus error */
 399 /* hard error: reset and retry */
 400 #define XD_ERR_DFLT 0x60         /* drive fault */
 401 #define XD_ERR_HECY 0x61         /* header error/cyl */
 402 #define XD_ERR_HEHD 0x62         /* header error/head */
 403 #define XD_ERR_NOCY 0x63         /* not on cylinder */
 404 #define XD_ERR_SEEK 0x64         /* seek error */
 405 /* fatal hardware error */
 406 #define XD_ERR_ILSS 0x70         /* illegal sector size */
 407 /* misc */
 408 #define XD_ERR_SEC  0x80         /* soft ecc */
 409 /* requires manual intervention */
 410 #define XD_ERR_WPER 0x90         /* write protected */
 411 /* FATAL errors */
 412 #define XD_ERR_IRAM 0xe1         /* IRAM self test failed */
 413 #define XD_ERR_MT3  0xe3         /* maint test 3 failed (DSKCEL RAM) */
 414 #define XD_ERR_MT4  0xe4         /* maint test 4 failed (Header shift reg) */
 415 #define XD_ERR_MT5  0xe5         /* maint test 5 failed (VMEDMA regs) */
 416 #define XD_ERR_MT6  0xe6         /* maint test 6 failed (REGCEL chip) */
 417 #define XD_ERR_MT7  0xe7         /* maint test 7 failed (buff. parity) */
 418 #define XD_ERR_MT8  0xe8         /* maint test 8 failed (fifo) */
 419 #define XD_ERR_IOCK 0xf0         /* iopb checksume miscompare */
 420 #define XD_ERR_IODM 0xf1         /* iopb DMA fatal */
 421 #define XD_ERR_IOAL 0xf2         /* iopb allignment error */
 422 #define XD_ERR_FIRM 0xf3         /* firmware error n*/
 423 #define XD_ERR_MMOD 0xf5         /* illegal maint mode test number */
 424 #define XD_ERR_ACFL 0xf6         /* ACFAIL asserted */