1 /* disasm.c where all the _work_ gets done in the Netwide Disassembler
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the licence given in the file "Licence"
6 * distributed in the NASM archive.
8 * initial version 27/iii/95 by Simon Tatham
22 extern struct itemplate
**itable
[];
25 * Flags that go into the `segment' field of `insn' structures
28 #define SEG_RELATIVE 1
35 #define SEG_SIGNED 128
40 #define getu8(x) (*(uint8_t *)(x))
41 #if defined(__i386__) || defined(__x86_64__)
42 /* Littleendian CPU which can handle unaligned references */
43 #define getu16(x) (*(uint16_t *)(x))
44 #define getu32(x) (*(uint32_t *)(x))
45 #define getu64(x) (*(uint64_t *)(x))
47 static uint16_t getu16(uint8_t *data
)
49 return (uint16_t)data
[0] + ((uint16_t)data
[1] << 8);
51 static uint32_t getu32(uint8_t *data
)
53 return (uint32_t)getu16(data
) + ((uint32_t)getu16(data
+2) << 16);
55 static uint64_t getu64(uint8_t *data
)
57 return (uint64_t)getu32(data
) + ((uint64_t)getu32(data
+4) << 32);
61 #define gets8(x) ((int8_t)getu8(x))
62 #define gets16(x) ((int16_t)getu16(x))
63 #define gets32(x) ((int32_t)getu32(x))
64 #define gets64(x) ((int64_t)getu64(x))
66 /* Important: regval must already have been adjusted for rex extensions */
67 static int whichreg(int32_t regflags
, int regval
, int rex
)
69 if (!(REG_AL
& ~regflags
))
71 if (!(REG_AX
& ~regflags
))
73 if (!(REG_EAX
& ~regflags
))
75 if (!(REG_RAX
& ~regflags
))
77 if (!(REG_DL
& ~regflags
))
79 if (!(REG_DX
& ~regflags
))
81 if (!(REG_EDX
& ~regflags
))
83 if (!(REG_RDX
& ~regflags
))
85 if (!(REG_CL
& ~regflags
))
87 if (!(REG_CX
& ~regflags
))
89 if (!(REG_ECX
& ~regflags
))
91 if (!(REG_RCX
& ~regflags
))
93 if (!(FPU0
& ~regflags
))
95 if (!(REG_CS
& ~regflags
))
96 return (regval
== 1) ? R_CS
: 0;
97 if (!(REG_DESS
& ~regflags
))
98 return (regval
== 0 || regval
== 2
99 || regval
== 3 ? rd_sreg
[regval
] : 0);
100 if (!(REG_FSGS
& ~regflags
))
101 return (regval
== 4 || regval
== 5 ? rd_sreg
[regval
] : 0);
102 if (!(REG_SEG67
& ~regflags
))
103 return (regval
== 6 || regval
== 7 ? rd_sreg
[regval
] : 0);
105 /* All the entries below look up regval in an 16-entry array */
106 if (regval
< 0 || regval
> 15)
109 if (!((REGMEM
| BITS8
) & ~regflags
)) {
111 return rd_reg8_rex
[regval
];
113 return rd_reg8
[regval
];
115 if (!((REGMEM
| BITS16
) & ~regflags
))
116 return rd_reg16
[regval
];
117 if (!((REGMEM
| BITS32
) & ~regflags
))
118 return rd_reg32
[regval
];
119 if (!((REGMEM
| BITS64
) & ~regflags
))
120 return rd_reg64
[regval
];
121 if (!(REG_SREG
& ~regflags
))
122 return rd_sreg
[regval
& 7]; /* Ignore REX */
123 if (!(REG_CREG
& ~regflags
))
124 return rd_creg
[regval
];
125 if (!(REG_DREG
& ~regflags
))
126 return rd_dreg
[regval
];
127 if (!(REG_TREG
& ~regflags
)) {
129 return 0; /* TR registers are ill-defined with rex */
130 return rd_treg
[regval
];
132 if (!(FPUREG
& ~regflags
))
133 return rd_fpureg
[regval
& 7]; /* Ignore REX */
134 if (!(MMXREG
& ~regflags
))
135 return rd_mmxreg
[regval
& 7]; /* Ignore REX */
136 if (!(XMMREG
& ~regflags
))
137 return rd_xmmreg
[regval
];
142 static const char *whichcond(int condval
)
144 static int conds
[] = {
145 C_O
, C_NO
, C_C
, C_NC
, C_Z
, C_NZ
, C_NA
, C_A
,
146 C_S
, C_NS
, C_PE
, C_PO
, C_L
, C_NL
, C_NG
, C_G
148 return conditions
[conds
[condval
]];
152 * Process an effective address (ModRM) specification.
154 static uint8_t *do_ea(uint8_t *data
, int modrm
, int asize
,
155 int segsize
, operand
* op
, int rex
)
157 int mod
, rm
, scale
, index
, base
;
159 mod
= (modrm
>> 6) & 03;
162 if (mod
== 3) { /* pure register version */
163 op
->basereg
= rm
+(rex
& REX_B
? 8 : 0);
164 op
->segment
|= SEG_RMREG
;
172 * <mod> specifies the displacement size (none, byte or
173 * word), and <rm> specifies the register combination.
174 * Exception: mod=0,rm=6 does not specify [BP] as one might
175 * expect, but instead specifies [disp16].
177 op
->indexreg
= op
->basereg
= -1;
178 op
->scale
= 1; /* always, in 16 bits */
209 if (rm
== 6 && mod
== 0) { /* special case */
213 mod
= 2; /* fake disp16 */
217 op
->segment
|= SEG_NODISP
;
220 op
->segment
|= SEG_DISP8
;
221 op
->offset
= (int8_t)*data
++;
224 op
->segment
|= SEG_DISP16
;
225 op
->offset
= *data
++;
226 op
->offset
|= ((unsigned)*data
++) << 8;
232 * Once again, <mod> specifies displacement size (this time
233 * none, byte or *dword*), while <rm> specifies the base
234 * register. Again, [EBP] is missing, replaced by a pure
235 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
236 * and RIP-relative addressing in 64-bit mode.
239 * indicates not a single base register, but instead the
240 * presence of a SIB byte...
242 int a64
= asize
== 64;
247 op
->basereg
= rd_reg64
[rm
| ((rex
& REX_B
) ? 8 : 0)];
249 op
->basereg
= rd_reg32
[rm
| ((rex
& REX_B
) ? 8 : 0)];
251 if (rm
== 5 && mod
== 0) {
254 op
->segment
|= SEG_RELATIVE
;
255 mod
= 2; /* fake disp32 */
260 mod
= 2; /* fake disp32 */
264 if (rm
== 4) { /* process SIB */
265 scale
= (*data
>> 6) & 03;
266 index
= (*data
>> 3) & 07;
270 op
->scale
= 1 << scale
;
273 op
->indexreg
= -1; /* ESP/RSP/R12 cannot be an index */
275 op
->indexreg
= rd_reg64
[index
| ((rex
& REX_X
) ? 8 : 0)];
277 op
->indexreg
= rd_reg64
[index
| ((rex
& REX_X
) ? 8 : 0)];
279 if (base
== 5 && mod
== 0) {
281 mod
= 2; /* Fake disp32 */
283 op
->basereg
= rd_reg64
[base
| ((rex
& REX_B
) ? 8 : 0)];
285 op
->basereg
= rd_reg32
[base
| ((rex
& REX_B
) ? 8 : 0)];
290 op
->segment
|= SEG_NODISP
;
293 op
->segment
|= SEG_DISP8
;
294 op
->offset
= gets8(data
);
298 op
->segment
|= SEG_DISP32
;
299 op
->offset
= getu32(data
);
308 * Determine whether the instruction template in t corresponds to the data
309 * stream in data. Return the number of bytes matched if so.
311 static int matches(struct itemplate
*t
, uint8_t *data
, int asize
,
312 int osize
, int segsize
, int rep
, insn
* ins
,
313 int rex
, int *rexout
, int lock
)
315 uint8_t *r
= (uint8_t *)(t
->code
);
316 uint8_t *origdata
= data
;
317 int a_used
= FALSE
, o_used
= FALSE
;
322 if (t
->flags
& (segsize
== 64 ? IF_NOLONG
: IF_LONG
))
327 else if (rep
== 0xF3)
333 /* FIX: change this into a switch */
334 if (c
>= 01 && c
<= 03) {
338 } else if (c
== 04) {
341 ins
->oprs
[0].basereg
= 0;
344 ins
->oprs
[0].basereg
= 2;
347 ins
->oprs
[0].basereg
= 3;
352 } else if (c
== 05) {
355 ins
->oprs
[0].basereg
= 4;
358 ins
->oprs
[0].basereg
= 5;
363 } else if (c
== 06) {
366 ins
->oprs
[0].basereg
= 0;
369 ins
->oprs
[0].basereg
= 1;
372 ins
->oprs
[0].basereg
= 2;
375 ins
->oprs
[0].basereg
= 3;
380 } else if (c
== 07) {
383 ins
->oprs
[0].basereg
= 4;
386 ins
->oprs
[0].basereg
= 5;
391 } else if (c
>= 010 && c
<= 012) {
392 int t
= *r
++, d
= *data
++;
393 if (d
< t
|| d
> t
+ 7)
396 ins
->oprs
[c
- 010].basereg
= (d
-t
)+(rex
& REX_B
? 8 : 0);
397 ins
->oprs
[c
- 010].segment
|= SEG_RMREG
;
399 } else if (c
== 017) {
402 } else if (c
>= 014 && c
<= 016) {
403 ins
->oprs
[c
- 014].offset
= (int8_t)*data
++;
404 ins
->oprs
[c
- 014].segment
|= SEG_SIGNED
;
405 } else if (c
>= 020 && c
<= 022) {
406 ins
->oprs
[c
- 020].offset
= *data
++;
407 } else if (c
>= 024 && c
<= 026) {
408 ins
->oprs
[c
- 024].offset
= *data
++;
409 } else if (c
>= 030 && c
<= 032) {
410 ins
->oprs
[c
- 030].offset
= getu16(data
);
412 } else if (c
>= 034 && c
<= 036) {
414 ins
->oprs
[c
- 034].offset
= getu32(data
);
417 ins
->oprs
[c
- 034].offset
= getu16(data
);
420 if (segsize
!= asize
)
421 ins
->oprs
[c
- 034].addr_size
= asize
;
422 } else if (c
>= 040 && c
<= 042) {
423 ins
->oprs
[c
- 040].offset
= getu32(data
);
425 } else if (c
>= 044 && c
<= 046) {
428 ins
->oprs
[c
- 044].offset
= getu16(data
);
432 ins
->oprs
[c
- 044].offset
= getu32(data
);
436 ins
->oprs
[c
- 044].offset
= getu64(data
);
440 if (segsize
!= asize
)
441 ins
->oprs
[c
- 044].addr_size
= asize
;
442 } else if (c
>= 050 && c
<= 052) {
443 ins
->oprs
[c
- 050].offset
= gets8(data
++);
444 ins
->oprs
[c
- 050].segment
|= SEG_RELATIVE
;
445 } else if (c
>= 054 && c
<= 056) {
446 ins
->oprs
[c
- 054].offset
= getu64(data
);
448 } else if (c
>= 060 && c
<= 062) {
449 ins
->oprs
[c
- 060].offset
= gets16(data
);
451 ins
->oprs
[c
- 060].segment
|= SEG_RELATIVE
;
452 ins
->oprs
[c
- 060].segment
&= ~SEG_32BIT
;
453 } else if (c
>= 064 && c
<= 066) {
455 ins
->oprs
[c
- 064].offset
= getu16(data
);
457 ins
->oprs
[c
- 064].segment
&= ~(SEG_32BIT
|SEG_64BIT
);
458 } else if (osize
== 32) {
459 ins
->oprs
[c
- 064].offset
= getu32(data
);
461 ins
->oprs
[c
- 064].segment
&= ~SEG_64BIT
;
462 ins
->oprs
[c
- 064].segment
|= SEG_32BIT
;
464 if (segsize
!= osize
) {
465 ins
->oprs
[c
- 064].type
=
466 (ins
->oprs
[c
- 064].type
& ~SIZE_MASK
)
467 | ((osize
== 16) ? BITS16
: BITS32
);
469 } else if (c
>= 070 && c
<= 072) {
470 ins
->oprs
[c
- 070].offset
= getu32(data
);
472 ins
->oprs
[c
- 070].segment
|= SEG_32BIT
| SEG_RELATIVE
;
473 } else if (c
>= 0100 && c
< 0130) {
475 ins
->oprs
[c
& 07].basereg
= ((modrm
>> 3)&7)+(rex
& REX_R
? 8 : 0);
476 ins
->oprs
[c
& 07].segment
|= SEG_RMREG
;
477 data
= do_ea(data
, modrm
, asize
, segsize
,
478 &ins
->oprs
[(c
>> 3) & 07], rex
);
479 } else if (c
>= 0130 && c
<= 0132) {
480 ins
->oprs
[c
- 0130].offset
= getu16(data
);
482 } else if (c
>= 0140 && c
<= 0142) {
483 ins
->oprs
[c
- 0140].offset
= getu32(data
);
485 } else if (c
>= 0200 && c
<= 0277) {
487 if (((modrm
>> 3) & 07) != (c
& 07))
488 return FALSE
; /* spare field doesn't match up */
489 data
= do_ea(data
, modrm
, asize
, segsize
,
490 &ins
->oprs
[(c
>> 3) & 07], rex
);
491 } else if (c
>= 0300 && c
<= 0302) {
493 } else if (c
== 0310) {
498 } else if (c
== 0311) {
503 } else if (c
== 0312) {
504 if (asize
!= segsize
)
508 } else if (c
== 0313) {
513 } else if (c
== 0320) {
518 } else if (c
== 0321) {
523 } else if (c
== 0322) {
524 if (osize
!= (segsize
== 16) ? 16 : 32)
528 } else if (c
== 0323) {
529 rex
|= REX_W
; /* 64-bit only instruction */
531 } else if (c
== 0324) {
532 if (!(rex
& (REX_P
|REX_W
)) || osize
!= 64)
534 } else if (c
== 0330) {
535 int t
= *r
++, d
= *data
++;
536 if (d
< t
|| d
> t
+ 15)
539 ins
->condition
= d
- t
;
540 } else if (c
== 0331) {
543 } else if (c
== 0332) {
546 } else if (c
== 0333) {
550 } else if (c
== 0334) {
559 * Check for unused rep or a/o prefixes.
563 ins
->prefixes
[ins
->nprefix
++] = P_LOCK
;
565 ins
->prefixes
[ins
->nprefix
++] = drep
;
566 if (!a_used
&& asize
!= segsize
)
567 ins
->prefixes
[ins
->nprefix
++] = asize
== 16 ? P_A16
: P_A32
;
568 if (!o_used
&& osize
== ((segsize
== 16) ? 32 : 16))
569 ins
->prefixes
[ins
->nprefix
++] = osize
== 16 ? P_O16
: P_O32
;
571 /* Fix: check for redundant REX prefixes */
574 return data
- origdata
;
577 int32_t disasm(uint8_t *data
, char *output
, int outbufsize
, int segsize
,
578 int32_t offset
, int autosync
, uint32_t prefer
)
580 struct itemplate
**p
, **best_p
;
581 int length
, best_length
= 0;
583 int rep
, lock
, asize
, osize
, i
, slen
, colon
, rex
, rexout
, best_rex
;
587 uint32_t goodness
, best
;
593 osize
= (segsize
== 64) ? 32 : segsize
;
599 if (*data
== 0xF3 || *data
== 0xF2)
601 else if (*data
== 0xF0)
603 else if (*data
== 0x2E)
604 segover
= "cs", data
++;
605 else if (*data
== 0x36)
606 segover
= "ss", data
++;
607 else if (*data
== 0x3E)
608 segover
= "ds", data
++;
609 else if (*data
== 0x26)
610 segover
= "es", data
++;
611 else if (*data
== 0x64)
612 segover
= "fs", data
++;
613 else if (*data
== 0x65)
614 segover
= "gs", data
++;
615 else if (*data
== 0x66) {
616 osize
= (segsize
== 16) ? 32 : 16;
618 } else if (*data
== 0x67) {
619 asize
= (segsize
== 32) ? 16 : 32;
621 } else if (segsize
== 64 && (*data
& 0xf0) == REX_P
) {
625 break; /* REX is always the last prefix */
631 tmp_ins
.oprs
[0].segment
= tmp_ins
.oprs
[1].segment
=
632 tmp_ins
.oprs
[2].segment
=
633 tmp_ins
.oprs
[0].addr_size
= tmp_ins
.oprs
[1].addr_size
=
634 tmp_ins
.oprs
[2].addr_size
= (segsize
== 64 ? SEG_64BIT
:
635 segsize
== 32 ? SEG_32BIT
: 0);
636 tmp_ins
.condition
= -1;
637 best
= -1; /* Worst possible */
640 for (p
= itable
[*data
]; *p
; p
++) {
641 if ((length
= matches(*p
, data
, asize
, osize
, segsize
, rep
,
642 &tmp_ins
, rex
, &rexout
, lock
))) {
645 * Final check to make sure the types of r/m match up.
646 * XXX: Need to make sure this is actually correct.
648 for (i
= 0; i
< (*p
)->operands
; i
++) {
650 /* If it's a mem-only EA but we have a register, die. */
651 ((tmp_ins
.oprs
[i
].segment
& SEG_RMREG
) &&
652 !(MEMORY
& ~(*p
)->opd
[i
])) ||
653 /* If it's a reg-only EA but we have a memory ref, die. */
654 (!(tmp_ins
.oprs
[i
].segment
& SEG_RMREG
) &&
655 !(REG_EA
& ~(*p
)->opd
[i
]) &&
656 !((*p
)->opd
[i
] & REG_SMASK
)) ||
657 /* Register type mismatch (eg FS vs REG_DESS): die. */
658 ((((*p
)->opd
[i
] & (REGISTER
| FPUREG
)) ||
659 (tmp_ins
.oprs
[i
].segment
& SEG_RMREG
)) &&
660 !whichreg((*p
)->opd
[i
],
661 tmp_ins
.oprs
[i
].basereg
, rexout
))) {
668 goodness
= ((*p
)->flags
& IF_PFMASK
) ^ prefer
;
669 if (goodness
< best
) {
670 /* This is the best one found so far */
673 best_length
= length
;
682 return 0; /* no instruction was matched */
684 /* Pick the best match */
686 length
= best_length
;
688 if (best_rex
& REX_W
)
693 /* TODO: snprintf returns the value that the string would have if
694 * the buffer were long enough, and not the actual length of
695 * the returned string, so each instance of using the return
696 * value of snprintf should actually be checked to assure that
697 * the return value is "sane." Maybe a macro wrapper could
698 * be used for that purpose.
700 for (i
= 0; i
< ins
.nprefix
; i
++)
701 switch (ins
.prefixes
[i
]) {
703 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "lock ");
706 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "rep ");
709 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "repe ");
712 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "repne ");
715 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "a16 ");
718 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "a32 ");
721 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "o16 ");
724 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "o32 ");
728 for (i
= 0; i
< elements(ico
); i
++)
729 if ((*p
)->opcode
== ico
[i
]) {
731 snprintf(output
+ slen
, outbufsize
- slen
, "%s%s", icn
[i
],
732 whichcond(ins
.condition
));
735 if (i
>= elements(ico
))
737 snprintf(output
+ slen
, outbufsize
- slen
, "%s",
738 insn_names
[(*p
)->opcode
]);
740 length
+= data
- origdata
; /* fix up for prefixes */
741 for (i
= 0; i
< (*p
)->operands
; i
++) {
742 output
[slen
++] = (colon
? ':' : i
== 0 ? ' ' : ',');
744 if (ins
.oprs
[i
].segment
& SEG_RELATIVE
) {
745 ins
.oprs
[i
].offset
+= offset
+ length
;
747 * sort out wraparound
749 if (!(ins
.oprs
[i
].segment
& (SEG_32BIT
|SEG_64BIT
)))
750 ins
.oprs
[i
].offset
&= 0xffff;
752 * add sync marker, if autosync is on
755 add_sync(ins
.oprs
[i
].offset
, 0L);
758 if ((*p
)->opd
[i
] & COLON
)
763 if (((*p
)->opd
[i
] & (REGISTER
| FPUREG
)) ||
764 (ins
.oprs
[i
].segment
& SEG_RMREG
)) {
765 ins
.oprs
[i
].basereg
= whichreg((*p
)->opd
[i
],
766 ins
.oprs
[i
].basereg
, rex
);
767 if ((*p
)->opd
[i
] & TO
)
768 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "to ");
769 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "%s",
770 reg_names
[ins
.oprs
[i
].basereg
-
772 } else if (!(UNITY
& ~(*p
)->opd
[i
])) {
773 output
[slen
++] = '1';
774 } else if ((*p
)->opd
[i
] & IMMEDIATE
) {
775 if ((*p
)->opd
[i
] & BITS8
) {
777 snprintf(output
+ slen
, outbufsize
- slen
, "byte ");
778 if (ins
.oprs
[i
].segment
& SEG_SIGNED
) {
779 if (ins
.oprs
[i
].offset
< 0) {
780 ins
.oprs
[i
].offset
*= -1;
781 output
[slen
++] = '-';
783 output
[slen
++] = '+';
785 } else if ((*p
)->opd
[i
] & BITS16
) {
787 snprintf(output
+ slen
, outbufsize
- slen
, "word ");
788 } else if ((*p
)->opd
[i
] & BITS32
) {
790 snprintf(output
+ slen
, outbufsize
- slen
, "dword ");
791 } else if ((*p
)->opd
[i
] & BITS64
) {
793 snprintf(output
+ slen
, outbufsize
- slen
, "qword ");
794 } else if ((*p
)->opd
[i
] & NEAR
) {
796 snprintf(output
+ slen
, outbufsize
- slen
, "near ");
797 } else if ((*p
)->opd
[i
] & SHORT
) {
799 snprintf(output
+ slen
, outbufsize
- slen
, "short ");
802 snprintf(output
+ slen
, outbufsize
- slen
, "0x%"PRIx64
"",
804 } else if (!(MEM_OFFS
& ~(*p
)->opd
[i
])) {
806 snprintf(output
+ slen
, outbufsize
- slen
, "[%s%s%s0x%"PRIx64
"]",
807 ((const char*)segover
? (const char*)segover
: ""), /* placate type mistmatch warning */
808 ((const char*)segover
? ":" : ""), /* by using (const char*) instead of uint8_t* */
809 (ins
.oprs
[i
].addr_size
==
810 32 ? "dword " : ins
.oprs
[i
].addr_size
==
811 16 ? "word " : ""), ins
.oprs
[i
].offset
);
813 } else if (!(REGMEM
& ~(*p
)->opd
[i
])) {
815 if ((*p
)->opd
[i
] & BITS8
)
817 snprintf(output
+ slen
, outbufsize
- slen
, "byte ");
818 if ((*p
)->opd
[i
] & BITS16
)
820 snprintf(output
+ slen
, outbufsize
- slen
, "word ");
821 if ((*p
)->opd
[i
] & BITS32
)
823 snprintf(output
+ slen
, outbufsize
- slen
, "dword ");
824 if ((*p
)->opd
[i
] & BITS64
)
826 snprintf(output
+ slen
, outbufsize
- slen
, "qword ");
827 if ((*p
)->opd
[i
] & BITS80
)
829 snprintf(output
+ slen
, outbufsize
- slen
, "tword ");
830 if ((*p
)->opd
[i
] & FAR
)
831 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "far ");
832 if ((*p
)->opd
[i
] & NEAR
)
834 snprintf(output
+ slen
, outbufsize
- slen
, "near ");
835 output
[slen
++] = '[';
836 if (ins
.oprs
[i
].addr_size
)
837 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "%s",
838 (ins
.oprs
[i
].addr_size
== 64 ? "qword " :
839 ins
.oprs
[i
].addr_size
== 32 ? "dword " :
840 ins
.oprs
[i
].addr_size
== 16 ? "word " :
844 snprintf(output
+ slen
, outbufsize
- slen
, "%s:",
848 if (ins
.oprs
[i
].basereg
!= -1) {
849 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "%s",
850 reg_names
[(ins
.oprs
[i
].basereg
-
854 if (ins
.oprs
[i
].indexreg
!= -1) {
856 output
[slen
++] = '+';
857 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "%s",
858 reg_names
[(ins
.oprs
[i
].indexreg
-
860 if (ins
.oprs
[i
].scale
> 1)
862 snprintf(output
+ slen
, outbufsize
- slen
, "*%d",
866 if (ins
.oprs
[i
].segment
& SEG_DISP8
) {
868 int8_t offset
= ins
.oprs
[i
].offset
;
874 snprintf(output
+ slen
, outbufsize
- slen
, "%s0x%"PRIx8
"",
875 minus
? "-" : "+", offset
);
876 } else if (ins
.oprs
[i
].segment
& SEG_DISP16
) {
878 int16_t offset
= ins
.oprs
[i
].offset
;
884 snprintf(output
+ slen
, outbufsize
- slen
, "%s0x%"PRIx16
"",
885 minus
? "-" : started
? "+" : "", offset
);
886 } else if (ins
.oprs
[i
].segment
& SEG_DISP32
) {
888 int32_t offset
= ins
.oprs
[i
].offset
;
889 if (ins
.oprs
[i
].basereg
== R_RIP
) {
891 } else if (offset
< 0) {
895 prefix
= started
? "+" : "";
898 snprintf(output
+ slen
, outbufsize
- slen
,
899 "%s0x%"PRIx32
"", prefix
, offset
);
901 output
[slen
++] = ']';
904 snprintf(output
+ slen
, outbufsize
- slen
, "<operand%d>",
909 if (segover
) { /* unused segment override */
911 int count
= slen
+ 1;
913 p
[count
+ 3] = p
[count
];
914 strncpy(output
, segover
, 2);
920 int32_t eatbyte(uint8_t *data
, char *output
, int outbufsize
)
922 snprintf(output
, outbufsize
, "db 0x%02X", *data
);