BR3392199: Revert "insns: Add MOVD as aliases to MOVQ for compatibility with AMD"
[nasm/sigaren-mirror.git] / test / fpu.asm
blob4051fdddd02a2258b00d3797340815c370e35c17
1 ;Testname=test; Arguments=-fbin -ofpu.bin; Files=stdout stderr fpu.bin
3 ; relaxed encodings for FPU instructions, which NASM should support
4 ; -----------------------------------------------------------------
6 %define void
7 %define reg_fpu0 st0
8 %define reg_fpu st1
10 ; no operands instead of one operand:
12 ; F(U)COM(P), FCOM2, FCOMP3, FCOMP5
14 FCOM void
15 FCOMP void
16 FUCOM void
17 FUCOMP void
18 ; FCOM2 void
19 ; FCOMP3 void
20 ; FCOMP5 void
22 ; FLD, FST, FSTP, FSTP1, FSTP8, FSTP9
24 FLD void
25 FST void
26 FSTP void
27 ; FSTP1 void
28 ; FSTP8 void
29 ; FSTP9 void
31 ; FXCH, FXCH4, FXCH7, FFREE, FFREEP
33 FXCH void
34 ; FXCH4 void
35 ; FXCH7 void
36 FFREE void
37 FFREEP void
39 ; no operands instead of two operands:
41 ; FADD(P), FMUL(P), FSUBR(P), FSUB(P), FDIVR(P), FDIV(P)
43 FADD void
44 FADDP void
45 FMUL void
46 FMULP void
47 FSUBR void
48 FSUBRP void
49 FSUB void
50 FSUBP void
51 FDIVR void
52 FDIVRP void
53 FDIV void
54 FDIVP void
56 ; one operand instead of two operands:
58 ; FADD, FMUL, FSUB, FSUBR, FDIV, FDIVR
60 FADD reg_fpu
61 FMUL reg_fpu
62 FSUB reg_fpu
63 FSUBR reg_fpu
64 FDIV reg_fpu
65 FDIVR reg_fpu
67 ; FADD, FMUL, FSUBR, FSUB, FDIVR, FDIV (with TO qualifier)
69 FADD to reg_fpu
70 FMUL to reg_fpu
71 FSUBR to reg_fpu
72 FSUB to reg_fpu
73 FDIVR to reg_fpu
74 FDIV to reg_fpu
76 ; FADDP, FMULP, FSUBRP, FSUBP, FDIVRP, FDIVP
78 FADDP reg_fpu
79 FMULP reg_fpu
80 FSUBRP reg_fpu
81 FSUBP reg_fpu
82 FDIVRP reg_fpu
83 FDIVP reg_fpu
85 ; FCMOV(N)B, FCMOV(N)E, FCMOV(N)BE, FCMOV(N)U, and F(U)COMI(P)
87 FCMOVB reg_fpu
88 FCMOVNB reg_fpu
89 FCMOVE reg_fpu
90 FCMOVNE reg_fpu
91 FCMOVBE reg_fpu
92 FCMOVNBE reg_fpu
93 FCMOVU reg_fpu
94 FCMOVNU reg_fpu
95 FCOMI reg_fpu
96 FCOMIP reg_fpu
97 FUCOMI reg_fpu
98 FUCOMIP reg_fpu
100 ; two operands instead of one operand:
102 ; these don't really exist, and thus are _NOT_ supported:
104 ; FCOM reg_fpu,reg_fpu0
105 ; FCOM reg_fpu0,reg_fpu
106 ; FUCOM reg_fpu,reg_fpu0
107 ; FUCOM reg_fpu0,reg_fpu
108 ; FCOMP reg_fpu,reg_fpu0
109 ; FCOMP reg_fpu0,reg_fpu
110 ; FUCOMP reg_fpu,reg_fpu0
111 ; FUCOMP reg_fpu0,reg_fpu
113 ; FCOM2 reg_fpu,reg_fpu0
114 ; FCOM2 reg_fpu0,reg_fpu
115 ; FCOMP3 reg_fpu,reg_fpu0
116 ; FCOMP3 reg_fpu0,reg_fpu
117 ; FCOMP5 reg_fpu,reg_fpu0
118 ; FCOMP5 reg_fpu0,reg_fpu
120 ; FXCH reg_fpu,reg_fpu0
121 ; FXCH reg_fpu0,reg_fpu
122 ; FXCH4 reg_fpu,reg_fpu0
123 ; FXCH4 reg_fpu0,reg_fpu
124 ; FXCH7 reg_fpu,reg_fpu0
125 ; FXCH7 reg_fpu0,reg_fpu
127 ; EOF