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insns: add FXSAVE64/FXRSTOR64, drop np prefix
[nasm/sigaren-mirror.git] / disasm.c
blob561851abc2665a24de7ea0fb1c1fb12d08a5daeb
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2009 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * disasm.c where all the _work_ gets done in the Netwide Disassembler
36 */
37
38 #include "compiler.h"
39
40 #include <stdio.h>
41 #include <string.h>
42 #include <limits.h>
43 #include <inttypes.h>
44
45 #include "nasm.h"
46 #include "disasm.h"
47 #include "sync.h"
48 #include "insns.h"
49 #include "tables.h"
50 #include "regdis.h"
51
52 /*
53 * Flags that go into the `segment' field of `insn' structures
54 * during disassembly.
55 */
56 #define SEG_RELATIVE 1
57 #define SEG_32BIT 2
58 #define SEG_RMREG 4
59 #define SEG_DISP8 8
60 #define SEG_DISP16 16
61 #define SEG_DISP32 32
62 #define SEG_NODISP 64
63 #define SEG_SIGNED 128
64 #define SEG_64BIT 256
65
66 /*
67 * Prefix information
68 */
69 struct prefix_info {
70 uint8_t osize; /* Operand size */
71 uint8_t asize; /* Address size */
72 uint8_t osp; /* Operand size prefix present */
73 uint8_t asp; /* Address size prefix present */
74 uint8_t rep; /* Rep prefix present */
75 uint8_t seg; /* Segment override prefix present */
76 uint8_t wait; /* WAIT "prefix" present */
77 uint8_t lock; /* Lock prefix present */
78 uint8_t vex[3]; /* VEX prefix present */
79 uint8_t vex_c; /* VEX "class" (VEX, XOP, ...) */
80 uint8_t vex_m; /* VEX.M field */
81 uint8_t vex_v;
82 uint8_t vex_lp; /* VEX.LP fields */
83 uint32_t rex; /* REX prefix present */
84 };
85
86 #define getu8(x) (*(uint8_t *)(x))
87 #if X86_MEMORY
88 /* Littleendian CPU which can handle unaligned references */
89 #define getu16(x) (*(uint16_t *)(x))
90 #define getu32(x) (*(uint32_t *)(x))
91 #define getu64(x) (*(uint64_t *)(x))
92 #else
93 static uint16_t getu16(uint8_t *data)
94 {
95 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
96 }
97 static uint32_t getu32(uint8_t *data)
98 {
99 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
100 }
101 static uint64_t getu64(uint8_t *data)
102 {
103 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
104 }
105 #endif
106
107 #define gets8(x) ((int8_t)getu8(x))
108 #define gets16(x) ((int16_t)getu16(x))
109 #define gets32(x) ((int32_t)getu32(x))
110 #define gets64(x) ((int64_t)getu64(x))
111
112 /* Important: regval must already have been adjusted for rex extensions */
113 static enum reg_enum whichreg(opflags_t regflags, int regval, int rex)
114 {
115 if (!(regflags & (REGISTER|REGMEM)))
116 return 0; /* Registers not permissible?! */
117
118 regflags |= REGISTER;
119
120 if (!(REG_AL & ~regflags))
121 return R_AL;
122 if (!(REG_AX & ~regflags))
123 return R_AX;
124 if (!(REG_EAX & ~regflags))
125 return R_EAX;
126 if (!(REG_RAX & ~regflags))
127 return R_RAX;
128 if (!(REG_DL & ~regflags))
129 return R_DL;
130 if (!(REG_DX & ~regflags))
131 return R_DX;
132 if (!(REG_EDX & ~regflags))
133 return R_EDX;
134 if (!(REG_RDX & ~regflags))
135 return R_RDX;
136 if (!(REG_CL & ~regflags))
137 return R_CL;
138 if (!(REG_CX & ~regflags))
139 return R_CX;
140 if (!(REG_ECX & ~regflags))
141 return R_ECX;
142 if (!(REG_RCX & ~regflags))
143 return R_RCX;
144 if (!(FPU0 & ~regflags))
145 return R_ST0;
146 if (!(XMM0 & ~regflags))
147 return R_XMM0;
148 if (!(YMM0 & ~regflags))
149 return R_YMM0;
150 if (!(REG_CS & ~regflags))
151 return (regval == 1) ? R_CS : 0;
152 if (!(REG_DESS & ~regflags))
153 return (regval == 0 || regval == 2
154 || regval == 3 ? nasm_rd_sreg[regval] : 0);
155 if (!(REG_FSGS & ~regflags))
156 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
157 if (!(REG_SEG67 & ~regflags))
158 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
159
160 /* All the entries below look up regval in an 16-entry array */
161 if (regval < 0 || regval > 15)
162 return 0;
163
164 if (!(REG8 & ~regflags)) {
165 if (rex & (REX_P|REX_NH))
166 return nasm_rd_reg8_rex[regval];
167 else
168 return nasm_rd_reg8[regval];
169 }
170 if (!(REG16 & ~regflags))
171 return nasm_rd_reg16[regval];
172 if (!(REG32 & ~regflags))
173 return nasm_rd_reg32[regval];
174 if (!(REG64 & ~regflags))
175 return nasm_rd_reg64[regval];
176 if (!(REG_SREG & ~regflags))
177 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
178 if (!(REG_CREG & ~regflags))
179 return nasm_rd_creg[regval];
180 if (!(REG_DREG & ~regflags))
181 return nasm_rd_dreg[regval];
182 if (!(REG_TREG & ~regflags)) {
183 if (regval > 7)
184 return 0; /* TR registers are ill-defined with rex */
185 return nasm_rd_treg[regval];
186 }
187 if (!(FPUREG & ~regflags))
188 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
189 if (!(MMXREG & ~regflags))
190 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
191 if (!(XMMREG & ~regflags))
192 return nasm_rd_xmmreg[regval];
193 if (!(YMMREG & ~regflags))
194 return nasm_rd_ymmreg[regval];
195
196 return 0;
197 }
198
199 /*
200 * Process a DREX suffix
201 */
202 static uint8_t *do_drex(uint8_t *data, insn *ins)
203 {
204 uint8_t drex = *data++;
205 operand *dst = &ins->oprs[ins->drexdst];
206
207 if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
208 return NULL; /* OC0 mismatch */
209 ins->rex = (ins->rex & ~7) | (drex & 7);
210
211 dst->segment = SEG_RMREG;
212 dst->basereg = drex >> 4;
213 return data;
214 }
215
216
217 /*
218 * Process an effective address (ModRM) specification.
219 */
220 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
221 int segsize, operand * op, insn *ins)
222 {
223 int mod, rm, scale, index, base;
224 int rex;
225 uint8_t sib = 0;
226
227 mod = (modrm >> 6) & 03;
228 rm = modrm & 07;
229
230 if (mod != 3 && rm == 4 && asize != 16)
231 sib = *data++;
232
233 if (ins->rex & REX_D) {
234 data = do_drex(data, ins);
235 if (!data)
236 return NULL;
237 }
238 rex = ins->rex;
239
240 if (mod == 3) { /* pure register version */
241 op->basereg = rm+(rex & REX_B ? 8 : 0);
242 op->segment |= SEG_RMREG;
243 return data;
244 }
245
246 op->disp_size = 0;
247 op->eaflags = 0;
248
249 if (asize == 16) {
250 /*
251 * <mod> specifies the displacement size (none, byte or
252 * word), and <rm> specifies the register combination.
253 * Exception: mod=0,rm=6 does not specify [BP] as one might
254 * expect, but instead specifies [disp16].
255 */
256 op->indexreg = op->basereg = -1;
257 op->scale = 1; /* always, in 16 bits */
258 switch (rm) {
259 case 0:
260 op->basereg = R_BX;
261 op->indexreg = R_SI;
262 break;
263 case 1:
264 op->basereg = R_BX;
265 op->indexreg = R_DI;
266 break;
267 case 2:
268 op->basereg = R_BP;
269 op->indexreg = R_SI;
270 break;
271 case 3:
272 op->basereg = R_BP;
273 op->indexreg = R_DI;
274 break;
275 case 4:
276 op->basereg = R_SI;
277 break;
278 case 5:
279 op->basereg = R_DI;
280 break;
281 case 6:
282 op->basereg = R_BP;
283 break;
284 case 7:
285 op->basereg = R_BX;
286 break;
287 }
288 if (rm == 6 && mod == 0) { /* special case */
289 op->basereg = -1;
290 if (segsize != 16)
291 op->disp_size = 16;
292 mod = 2; /* fake disp16 */
293 }
294 switch (mod) {
295 case 0:
296 op->segment |= SEG_NODISP;
297 break;
298 case 1:
299 op->segment |= SEG_DISP8;
300 op->offset = (int8_t)*data++;
301 break;
302 case 2:
303 op->segment |= SEG_DISP16;
304 op->offset = *data++;
305 op->offset |= ((unsigned)*data++) << 8;
306 break;
307 }
308 return data;
309 } else {
310 /*
311 * Once again, <mod> specifies displacement size (this time
312 * none, byte or *dword*), while <rm> specifies the base
313 * register. Again, [EBP] is missing, replaced by a pure
314 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
315 * and RIP-relative addressing in 64-bit mode.
316 *
317 * However, rm=4
318 * indicates not a single base register, but instead the
319 * presence of a SIB byte...
320 */
321 int a64 = asize == 64;
322
323 op->indexreg = -1;
324
325 if (a64)
326 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
327 else
328 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
329
330 if (rm == 5 && mod == 0) {
331 if (segsize == 64) {
332 op->eaflags |= EAF_REL;
333 op->segment |= SEG_RELATIVE;
334 mod = 2; /* fake disp32 */
335 }
336
337 if (asize != 64)
338 op->disp_size = asize;
339
340 op->basereg = -1;
341 mod = 2; /* fake disp32 */
342 }
343
344 if (rm == 4) { /* process SIB */
345 scale = (sib >> 6) & 03;
346 index = (sib >> 3) & 07;
347 base = sib & 07;
348
349 op->scale = 1 << scale;
350
351 if (index == 4 && !(rex & REX_X))
352 op->indexreg = -1; /* ESP/RSP cannot be an index */
353 else if (a64)
354 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
355 else
356 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
357
358 if (base == 5 && mod == 0) {
359 op->basereg = -1;
360 mod = 2; /* Fake disp32 */
361 } else if (a64)
362 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
363 else
364 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
365
366 if (segsize == 16)
367 op->disp_size = 32;
368 }
369
370 switch (mod) {
371 case 0:
372 op->segment |= SEG_NODISP;
373 break;
374 case 1:
375 op->segment |= SEG_DISP8;
376 op->offset = gets8(data);
377 data++;
378 break;
379 case 2:
380 op->segment |= SEG_DISP32;
381 op->offset = gets32(data);
382 data += 4;
383 break;
384 }
385 return data;
386 }
387 }
388
389 /*
390 * Determine whether the instruction template in t corresponds to the data
391 * stream in data. Return the number of bytes matched if so.
392 */
393 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
394
395 static int matches(const struct itemplate *t, uint8_t *data,
396 const struct prefix_info *prefix, int segsize, insn *ins)
397 {
398 uint8_t *r = (uint8_t *)(t->code);
399 uint8_t *origdata = data;
400 bool a_used = false, o_used = false;
401 enum prefixes drep = 0;
402 enum prefixes dwait = 0;
403 uint8_t lock = prefix->lock;
404 int osize = prefix->osize;
405 int asize = prefix->asize;
406 int i, c;
407 int op1, op2;
408 struct operand *opx, *opy;
409 uint8_t opex = 0;
410 int s_field_for = -1; /* No 144/154 series code encountered */
411 bool vex_ok = false;
412 int regmask = (segsize == 64) ? 15 : 7;
413
414 for (i = 0; i < MAX_OPERANDS; i++) {
415 ins->oprs[i].segment = ins->oprs[i].disp_size =
416 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
417 }
418 ins->condition = -1;
419 ins->rex = prefix->rex;
420 memset(ins->prefixes, 0, sizeof ins->prefixes);
421
422 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
423 return false;
424
425 if (prefix->rep == 0xF2)
426 drep = P_REPNE;
427 else if (prefix->rep == 0xF3)
428 drep = P_REP;
429
430 dwait = prefix->wait ? P_WAIT : 0;
431
432 while ((c = *r++) != 0) {
433 op1 = (c & 3) + ((opex & 1) << 2);
434 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
435 opx = &ins->oprs[op1];
436 opy = &ins->oprs[op2];
437 opex = 0;
438
439 switch (c) {
440 case 01:
441 case 02:
442 case 03:
443 case 04:
444 while (c--)
445 if (*r++ != *data++)
446 return false;
447 break;
448
449 case 05:
450 case 06:
451 case 07:
452 opex = c;
453 break;
454
455 case4(010):
456 {
457 int t = *r++, d = *data++;
458 if (d < t || d > t + 7)
459 return false;
460 else {
461 opx->basereg = (d-t)+
462 (ins->rex & REX_B ? 8 : 0);
463 opx->segment |= SEG_RMREG;
464 }
465 break;
466 }
467
468 case4(014):
469 case4(0274):
470 opx->offset = (int8_t)*data++;
471 opx->segment |= SEG_SIGNED;
472 break;
473
474 case4(020):
475 opx->offset = *data++;
476 break;
477
478 case4(024):
479 opx->offset = *data++;
480 break;
481
482 case4(030):
483 opx->offset = getu16(data);
484 data += 2;
485 break;
486
487 case4(034):
488 if (osize == 32) {
489 opx->offset = getu32(data);
490 data += 4;
491 } else {
492 opx->offset = getu16(data);
493 data += 2;
494 }
495 if (segsize != asize)
496 opx->disp_size = asize;
497 break;
498
499 case4(040):
500 case4(0254):
501 opx->offset = getu32(data);
502 data += 4;
503 break;
504
505 case4(044):
506 switch (asize) {
507 case 16:
508 opx->offset = getu16(data);
509 data += 2;
510 if (segsize != 16)
511 opx->disp_size = 16;
512 break;
513 case 32:
514 opx->offset = getu32(data);
515 data += 4;
516 if (segsize == 16)
517 opx->disp_size = 32;
518 break;
519 case 64:
520 opx->offset = getu64(data);
521 opx->disp_size = 64;
522 data += 8;
523 break;
524 }
525 break;
526
527 case4(050):
528 opx->offset = gets8(data++);
529 opx->segment |= SEG_RELATIVE;
530 break;
531
532 case4(054):
533 opx->offset = getu64(data);
534 data += 8;
535 break;
536
537 case4(060):
538 opx->offset = gets16(data);
539 data += 2;
540 opx->segment |= SEG_RELATIVE;
541 opx->segment &= ~SEG_32BIT;
542 break;
543
544 case4(064):
545 opx->segment |= SEG_RELATIVE;
546 if (osize == 16) {
547 opx->offset = gets16(data);
548 data += 2;
549 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
550 } else if (osize == 32) {
551 opx->offset = gets32(data);
552 data += 4;
553 opx->segment &= ~SEG_64BIT;
554 opx->segment |= SEG_32BIT;
555 }
556 if (segsize != osize) {
557 opx->type =
558 (opx->type & ~SIZE_MASK)
559 | ((osize == 16) ? BITS16 : BITS32);
560 }
561 break;
562
563 case4(070):
564 opx->offset = gets32(data);
565 data += 4;
566 opx->segment |= SEG_32BIT | SEG_RELATIVE;
567 break;
568
569 case4(0100):
570 case4(0110):
571 case4(0120):
572 case4(0130):
573 {
574 int modrm = *data++;
575 opx->segment |= SEG_RMREG;
576 data = do_ea(data, modrm, asize, segsize, opy, ins);
577 if (!data)
578 return false;
579 opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0);
580 break;
581 }
582
583 case4(0140):
584 if (s_field_for == op1) {
585 opx->offset = gets8(data);
586 data++;
587 } else {
588 opx->offset = getu16(data);
589 data += 2;
590 }
591 break;
592
593 case4(0144):
594 case4(0154):
595 s_field_for = (*data & 0x02) ? op1 : -1;
596 if ((*data++ & ~0x02) != *r++)
597 return false;
598 break;
599
600 case4(0150):
601 if (s_field_for == op1) {
602 opx->offset = gets8(data);
603 data++;
604 } else {
605 opx->offset = getu32(data);
606 data += 4;
607 }
608 break;
609
610 case4(0160):
611 ins->rex |= REX_D;
612 ins->drexdst = op1;
613 break;
614
615 case4(0164):
616 ins->rex |= REX_D|REX_OC;
617 ins->drexdst = op1;
618 break;
619
620 case 0171:
621 data = do_drex(data, ins);
622 if (!data)
623 return false;
624 break;
625
626 case 0172:
627 {
628 uint8_t ximm = *data++;
629 c = *r++;
630 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
631 ins->oprs[c >> 3].segment |= SEG_RMREG;
632 ins->oprs[c & 7].offset = ximm & 15;
633 }
634 break;
635
636 case 0173:
637 {
638 uint8_t ximm = *data++;
639 c = *r++;
640
641 if ((c ^ ximm) & 15)
642 return false;
643
644 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
645 ins->oprs[c >> 4].segment |= SEG_RMREG;
646 }
647 break;
648
649 case 0174:
650 {
651 uint8_t ximm = *data++;
652 c = *r++;
653
654 ins->oprs[c].basereg = (ximm >> 4) & regmask;
655 ins->oprs[c].segment |= SEG_RMREG;
656 }
657 break;
658
659 case4(0200):
660 case4(0204):
661 case4(0210):
662 case4(0214):
663 case4(0220):
664 case4(0224):
665 case4(0230):
666 case4(0234):
667 {
668 int modrm = *data++;
669 if (((modrm >> 3) & 07) != (c & 07))
670 return false; /* spare field doesn't match up */
671 data = do_ea(data, modrm, asize, segsize, opy, ins);
672 if (!data)
673 return false;
674 break;
675 }
676
677 case4(0260):
678 {
679 int vexm = *r++;
680 int vexwlp = *r++;
681 ins->rex |= REX_V;
682 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
683 return false;
684
685 if ((vexm & 0x1f) != prefix->vex_m)
686 return false;
687
688 switch (vexwlp & 030) {
689 case 000:
690 if (prefix->rex & REX_W)
691 return false;
692 break;
693 case 010:
694 if (!(prefix->rex & REX_W))
695 return false;
696 ins->rex &= ~REX_W;
697 break;
698 case 020: /* VEX.W is a don't care */
699 ins->rex &= ~REX_W;
700 break;
701 case 030:
702 break;
703 }
704
705 if ((vexwlp & 007) != prefix->vex_lp)
706 return false;
707
708 opx->segment |= SEG_RMREG;
709 opx->basereg = prefix->vex_v;
710 vex_ok = true;
711 break;
712 }
713
714 case 0270:
715 {
716 int vexm = *r++;
717 int vexwlp = *r++;
718 ins->rex |= REX_V;
719 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
720 return false;
721
722 if ((vexm & 0x1f) != prefix->vex_m)
723 return false;
724
725 switch (vexwlp & 030) {
726 case 000:
727 if (ins->rex & REX_W)
728 return false;
729 break;
730 case 010:
731 if (!(ins->rex & REX_W))
732 return false;
733 break;
734 default:
735 break; /* Need to do anything special here? */
736 }
737
738 if ((vexwlp & 007) != prefix->vex_lp)
739 return false;
740
741 if (prefix->vex_v != 0)
742 return false;
743
744 vex_ok = true;
745 break;
746 }
747
748 case 0310:
749 if (asize != 16)
750 return false;
751 else
752 a_used = true;
753 break;
754
755 case 0311:
756 if (asize != 32)
757 return false;
758 else
759 a_used = true;
760 break;
761
762 case 0312:
763 if (asize != segsize)
764 return false;
765 else
766 a_used = true;
767 break;
768
769 case 0313:
770 if (asize != 64)
771 return false;
772 else
773 a_used = true;
774 break;
775
776 case 0314:
777 if (prefix->rex & REX_B)
778 return false;
779 break;
780
781 case 0315:
782 if (prefix->rex & REX_X)
783 return false;
784 break;
785
786 case 0316:
787 if (prefix->rex & REX_R)
788 return false;
789 break;
790
791 case 0317:
792 if (prefix->rex & REX_W)
793 return false;
794 break;
795
796 case 0320:
797 if (osize != 16)
798 return false;
799 else
800 o_used = true;
801 break;
802
803 case 0321:
804 if (osize != 32)
805 return false;
806 else
807 o_used = true;
808 break;
809
810 case 0322:
811 if (osize != (segsize == 16) ? 16 : 32)
812 return false;
813 else
814 o_used = true;
815 break;
816
817 case 0323:
818 ins->rex |= REX_W; /* 64-bit only instruction */
819 osize = 64;
820 o_used = true;
821 break;
822
823 case 0324:
824 if (!(ins->rex & (REX_P|REX_W)) || osize != 64)
825 return false;
826 o_used = true;
827 break;
828
829 case 0325:
830 ins->rex |= REX_NH;
831 break;
832
833 case 0330:
834 {
835 int t = *r++, d = *data++;
836 if (d < t || d > t + 15)
837 return false;
838 else
839 ins->condition = d - t;
840 break;
841 }
842
843 case 0331:
844 if (prefix->rep)
845 return false;
846 break;
847
848 case 0332:
849 if (prefix->rep != 0xF2)
850 return false;
851 drep = 0;
852 break;
853
854 case 0333:
855 if (prefix->rep != 0xF3)
856 return false;
857 drep = 0;
858 break;
859
860 case 0334:
861 if (lock) {
862 ins->rex |= REX_R;
863 lock = 0;
864 }
865 break;
866
867 case 0335:
868 if (drep == P_REP)
869 drep = P_REPE;
870 break;
871
872 case 0336:
873 case 0337:
874 break;
875
876 case 0340:
877 return false;
878
879 case 0341:
880 if (prefix->wait != 0x9B)
881 return false;
882 dwait = 0;
883 break;
884
885 case4(0344):
886 ins->oprs[0].basereg = (*data++ >> 3) & 7;
887 break;
888
889 case 0360:
890 if (prefix->osp || prefix->rep)
891 return false;
892 break;
893
894 case 0361:
895 if (!prefix->osp || prefix->rep)
896 return false;
897 o_used = true;
898 break;
899
900 case 0362:
901 if (prefix->osp || prefix->rep != 0xf2)
902 return false;
903 drep = 0;
904 break;
905
906 case 0363:
907 if (prefix->osp || prefix->rep != 0xf3)
908 return false;
909 drep = 0;
910 break;
911
912 case 0364:
913 if (prefix->osp)
914 return false;
915 break;
916
917 case 0365:
918 if (prefix->asp)
919 return false;
920 break;
921
922 case 0366:
923 if (!prefix->osp)
924 return false;
925 o_used = true;
926 break;
927
928 case 0367:
929 if (!prefix->asp)
930 return false;
931 a_used = true;
932 break;
933
934 default:
935 return false; /* Unknown code */
936 }
937 }
938
939 if (!vex_ok && (ins->rex & REX_V))
940 return false;
941
942 /* REX cannot be combined with DREX or VEX */
943 if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
944 return false;
945
946 /*
947 * Check for unused rep or a/o prefixes.
948 */
949 for (i = 0; i < t->operands; i++) {
950 if (ins->oprs[i].segment != SEG_RMREG)
951 a_used = true;
952 }
953
954 if (lock) {
955 if (ins->prefixes[PPS_LREP])
956 return false;
957 ins->prefixes[PPS_LREP] = P_LOCK;
958 }
959 if (drep) {
960 if (ins->prefixes[PPS_LREP])
961 return false;
962 ins->prefixes[PPS_LREP] = drep;
963 }
964 ins->prefixes[PPS_WAIT] = dwait;
965 if (!o_used) {
966 if (osize != ((segsize == 16) ? 16 : 32)) {
967 enum prefixes pfx = 0;
968
969 switch (osize) {
970 case 16:
971 pfx = P_O16;
972 break;
973 case 32:
974 pfx = P_O32;
975 break;
976 case 64:
977 pfx = P_O64;
978 break;
979 }
980
981 if (ins->prefixes[PPS_OSIZE])
982 return false;
983 ins->prefixes[PPS_OSIZE] = pfx;
984 }
985 }
986 if (!a_used && asize != segsize) {
987 if (ins->prefixes[PPS_ASIZE])
988 return false;
989 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
990 }
991
992 /* Fix: check for redundant REX prefixes */
993
994 return data - origdata;
995 }
996
997 /* Condition names for disassembly, sorted by x86 code */
998 static const char * const condition_name[16] = {
999 "o", "no", "c", "nc", "z", "nz", "na", "a",
1000 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
1001 };
1002
1003 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
1004 int32_t offset, int autosync, uint32_t prefer)
1005 {
1006 const struct itemplate * const *p, * const *best_p;
1007 const struct disasm_index *ix;
1008 uint8_t *dp;
1009 int length, best_length = 0;
1010 char *segover;
1011 int i, slen, colon, n;
1012 uint8_t *origdata;
1013 int works;
1014 insn tmp_ins, ins;
1015 uint32_t goodness, best;
1016 int best_pref;
1017 struct prefix_info prefix;
1018 bool end_prefix;
1019
1020 memset(&ins, 0, sizeof ins);
1021
1022 /*
1023 * Scan for prefixes.
1024 */
1025 memset(&prefix, 0, sizeof prefix);
1026 prefix.asize = segsize;
1027 prefix.osize = (segsize == 64) ? 32 : segsize;
1028 segover = NULL;
1029 origdata = data;
1030
1031 ix = itable;
1032
1033 end_prefix = false;
1034 while (!end_prefix) {
1035 switch (*data) {
1036 case 0xF2:
1037 case 0xF3:
1038 prefix.rep = *data++;
1039 break;
1040
1041 case 0x9B:
1042 prefix.wait = *data++;
1043 break;
1044
1045 case 0xF0:
1046 prefix.lock = *data++;
1047 break;
1048
1049 case 0x2E:
1050 segover = "cs", prefix.seg = *data++;
1051 break;
1052 case 0x36:
1053 segover = "ss", prefix.seg = *data++;
1054 break;
1055 case 0x3E:
1056 segover = "ds", prefix.seg = *data++;
1057 break;
1058 case 0x26:
1059 segover = "es", prefix.seg = *data++;
1060 break;
1061 case 0x64:
1062 segover = "fs", prefix.seg = *data++;
1063 break;
1064 case 0x65:
1065 segover = "gs", prefix.seg = *data++;
1066 break;
1067
1068 case 0x66:
1069 prefix.osize = (segsize == 16) ? 32 : 16;
1070 prefix.osp = *data++;
1071 break;
1072 case 0x67:
1073 prefix.asize = (segsize == 32) ? 16 : 32;
1074 prefix.asp = *data++;
1075 break;
1076
1077 case 0xC4:
1078 case 0xC5:
1079 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1080 prefix.vex[0] = *data++;
1081 prefix.vex[1] = *data++;
1082
1083 prefix.rex = REX_V;
1084 prefix.vex_c = RV_VEX;
1085
1086 if (prefix.vex[0] == 0xc4) {
1087 prefix.vex[2] = *data++;
1088 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1089 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1090 prefix.vex_m = prefix.vex[1] & 0x1f;
1091 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1092 prefix.vex_lp = prefix.vex[2] & 7;
1093 } else {
1094 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1095 prefix.vex_m = 1;
1096 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1097 prefix.vex_lp = prefix.vex[1] & 7;
1098 }
1099
1100 ix = itable_vex[RV_VEX][prefix.vex_m][prefix.vex_lp];
1101 }
1102 end_prefix = true;
1103 break;
1104
1105 case 0x8F:
1106 if ((data[1] & 030) != 0 &&
1107 (segsize == 64 || (data[1] & 0xc0) == 0xc0)) {
1108 prefix.vex[0] = *data++;
1109 prefix.vex[1] = *data++;
1110 prefix.vex[2] = *data++;
1111
1112 prefix.rex = REX_V;
1113 prefix.vex_c = RV_XOP;
1114
1115 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1116 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1117 prefix.vex_m = prefix.vex[1] & 0x1f;
1118 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1119 prefix.vex_lp = prefix.vex[2] & 7;
1120
1121 ix = itable_vex[RV_XOP][prefix.vex_m][prefix.vex_lp];
1122 }
1123 end_prefix = true;
1124 break;
1125
1126 case REX_P + 0x0:
1127 case REX_P + 0x1:
1128 case REX_P + 0x2:
1129 case REX_P + 0x3:
1130 case REX_P + 0x4:
1131 case REX_P + 0x5:
1132 case REX_P + 0x6:
1133 case REX_P + 0x7:
1134 case REX_P + 0x8:
1135 case REX_P + 0x9:
1136 case REX_P + 0xA:
1137 case REX_P + 0xB:
1138 case REX_P + 0xC:
1139 case REX_P + 0xD:
1140 case REX_P + 0xE:
1141 case REX_P + 0xF:
1142 if (segsize == 64) {
1143 prefix.rex = *data++;
1144 if (prefix.rex & REX_W)
1145 prefix.osize = 64;
1146 }
1147 end_prefix = true;
1148 break;
1149
1150 default:
1151 end_prefix = true;
1152 break;
1153 }
1154 }
1155
1156 best = -1; /* Worst possible */
1157 best_p = NULL;
1158 best_pref = INT_MAX;
1159
1160 if (!ix)
1161 return 0; /* No instruction table at all... */
1162
1163 dp = data;
1164 ix += *dp++;
1165 while (ix->n == -1) {
1166 ix = (const struct disasm_index *)ix->p + *dp++;
1167 }
1168
1169 p = (const struct itemplate * const *)ix->p;
1170 for (n = ix->n; n; n--, p++) {
1171 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1172 works = true;
1173 /*
1174 * Final check to make sure the types of r/m match up.
1175 * XXX: Need to make sure this is actually correct.
1176 */
1177 for (i = 0; i < (*p)->operands; i++) {
1178 if (!((*p)->opd[i] & SAME_AS) &&
1179 (
1180 /* If it's a mem-only EA but we have a
1181 register, die. */
1182 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1183 is_class(MEMORY, (*p)->opd[i])) ||
1184 /* If it's a reg-only EA but we have a memory
1185 ref, die. */
1186 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1187 !(REG_EA & ~(*p)->opd[i]) &&
1188 !((*p)->opd[i] & REG_SMASK)) ||
1189 /* Register type mismatch (eg FS vs REG_DESS):
1190 die. */
1191 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1192 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1193 !whichreg((*p)->opd[i],
1194 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1195 )) {
1196 works = false;
1197 break;
1198 }
1199 }
1200
1201 /*
1202 * Note: we always prefer instructions which incorporate
1203 * prefixes in the instructions themselves. This is to allow
1204 * e.g. PAUSE to be preferred to REP NOP, and deal with
1205 * MMX/SSE instructions where prefixes are used to select
1206 * between MMX and SSE register sets or outright opcode
1207 * selection.
1208 */
1209 if (works) {
1210 int i, nprefix;
1211 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1212 nprefix = 0;
1213 for (i = 0; i < MAXPREFIX; i++)
1214 if (tmp_ins.prefixes[i])
1215 nprefix++;
1216 if (nprefix < best_pref ||
1217 (nprefix == best_pref && goodness < best)) {
1218 /* This is the best one found so far */
1219 best = goodness;
1220 best_p = p;
1221 best_pref = nprefix;
1222 best_length = length;
1223 ins = tmp_ins;
1224 }
1225 }
1226 }
1227 }
1228
1229 if (!best_p)
1230 return 0; /* no instruction was matched */
1231
1232 /* Pick the best match */
1233 p = best_p;
1234 length = best_length;
1235
1236 slen = 0;
1237
1238 /* TODO: snprintf returns the value that the string would have if
1239 * the buffer were long enough, and not the actual length of
1240 * the returned string, so each instance of using the return
1241 * value of snprintf should actually be checked to assure that
1242 * the return value is "sane." Maybe a macro wrapper could
1243 * be used for that purpose.
1244 */
1245 for (i = 0; i < MAXPREFIX; i++) {
1246 const char *prefix = prefix_name(ins.prefixes[i]);
1247 if (prefix)
1248 slen += snprintf(output+slen, outbufsize-slen, "%s ", prefix);
1249 }
1250
1251 i = (*p)->opcode;
1252 if (i >= FIRST_COND_OPCODE)
1253 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1254 nasm_insn_names[i], condition_name[ins.condition]);
1255 else
1256 slen += snprintf(output + slen, outbufsize - slen, "%s",
1257 nasm_insn_names[i]);
1258
1259 colon = false;
1260 length += data - origdata; /* fix up for prefixes */
1261 for (i = 0; i < (*p)->operands; i++) {
1262 opflags_t t = (*p)->opd[i];
1263 const operand *o = &ins.oprs[i];
1264 int64_t offs;
1265
1266 if (t & SAME_AS) {
1267 o = &ins.oprs[t & ~SAME_AS];
1268 t = (*p)->opd[t & ~SAME_AS];
1269 }
1270
1271 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1272
1273 offs = o->offset;
1274 if (o->segment & SEG_RELATIVE) {
1275 offs += offset + length;
1276 /*
1277 * sort out wraparound
1278 */
1279 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1280 offs &= 0xffff;
1281 else if (segsize != 64)
1282 offs &= 0xffffffff;
1283
1284 /*
1285 * add sync marker, if autosync is on
1286 */
1287 if (autosync)
1288 add_sync(offs, 0L);
1289 }
1290
1291 if (t & COLON)
1292 colon = true;
1293 else
1294 colon = false;
1295
1296 if ((t & (REGISTER | FPUREG)) ||
1297 (o->segment & SEG_RMREG)) {
1298 enum reg_enum reg;
1299 reg = whichreg(t, o->basereg, ins.rex);
1300 if (t & TO)
1301 slen += snprintf(output + slen, outbufsize - slen, "to ");
1302 slen += snprintf(output + slen, outbufsize - slen, "%s",
1303 nasm_reg_names[reg-EXPR_REG_START]);
1304 } else if (!(UNITY & ~t)) {
1305 output[slen++] = '1';
1306 } else if (t & IMMEDIATE) {
1307 if (t & BITS8) {
1308 slen +=
1309 snprintf(output + slen, outbufsize - slen, "byte ");
1310 if (o->segment & SEG_SIGNED) {
1311 if (offs < 0) {
1312 offs *= -1;
1313 output[slen++] = '-';
1314 } else
1315 output[slen++] = '+';
1316 }
1317 } else if (t & BITS16) {
1318 slen +=
1319 snprintf(output + slen, outbufsize - slen, "word ");
1320 } else if (t & BITS32) {
1321 slen +=
1322 snprintf(output + slen, outbufsize - slen, "dword ");
1323 } else if (t & BITS64) {
1324 slen +=
1325 snprintf(output + slen, outbufsize - slen, "qword ");
1326 } else if (t & NEAR) {
1327 slen +=
1328 snprintf(output + slen, outbufsize - slen, "near ");
1329 } else if (t & SHORT) {
1330 slen +=
1331 snprintf(output + slen, outbufsize - slen, "short ");
1332 }
1333 slen +=
1334 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1335 offs);
1336 } else if (!(MEM_OFFS & ~t)) {
1337 slen +=
1338 snprintf(output + slen, outbufsize - slen,
1339 "[%s%s%s0x%"PRIx64"]",
1340 (segover ? segover : ""),
1341 (segover ? ":" : ""),
1342 (o->disp_size == 64 ? "qword " :
1343 o->disp_size == 32 ? "dword " :
1344 o->disp_size == 16 ? "word " : ""), offs);
1345 segover = NULL;
1346 } else if (is_class(REGMEM, t)) {
1347 int started = false;
1348 if (t & BITS8)
1349 slen +=
1350 snprintf(output + slen, outbufsize - slen, "byte ");
1351 if (t & BITS16)
1352 slen +=
1353 snprintf(output + slen, outbufsize - slen, "word ");
1354 if (t & BITS32)
1355 slen +=
1356 snprintf(output + slen, outbufsize - slen, "dword ");
1357 if (t & BITS64)
1358 slen +=
1359 snprintf(output + slen, outbufsize - slen, "qword ");
1360 if (t & BITS80)
1361 slen +=
1362 snprintf(output + slen, outbufsize - slen, "tword ");
1363 if (t & BITS128)
1364 slen +=
1365 snprintf(output + slen, outbufsize - slen, "oword ");
1366 if (t & BITS256)
1367 slen +=
1368 snprintf(output + slen, outbufsize - slen, "yword ");
1369 if (t & FAR)
1370 slen += snprintf(output + slen, outbufsize - slen, "far ");
1371 if (t & NEAR)
1372 slen +=
1373 snprintf(output + slen, outbufsize - slen, "near ");
1374 output[slen++] = '[';
1375 if (o->disp_size)
1376 slen += snprintf(output + slen, outbufsize - slen, "%s",
1377 (o->disp_size == 64 ? "qword " :
1378 o->disp_size == 32 ? "dword " :
1379 o->disp_size == 16 ? "word " :
1380 ""));
1381 if (o->eaflags & EAF_REL)
1382 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1383 if (segover) {
1384 slen +=
1385 snprintf(output + slen, outbufsize - slen, "%s:",
1386 segover);
1387 segover = NULL;
1388 }
1389 if (o->basereg != -1) {
1390 slen += snprintf(output + slen, outbufsize - slen, "%s",
1391 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1392 started = true;
1393 }
1394 if (o->indexreg != -1) {
1395 if (started)
1396 output[slen++] = '+';
1397 slen += snprintf(output + slen, outbufsize - slen, "%s",
1398 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1399 if (o->scale > 1)
1400 slen +=
1401 snprintf(output + slen, outbufsize - slen, "*%d",
1402 o->scale);
1403 started = true;
1404 }
1405
1406
1407 if (o->segment & SEG_DISP8) {
1408 const char *prefix;
1409 uint8_t offset = offs;
1410 if ((int8_t)offset < 0) {
1411 prefix = "-";
1412 offset = -offset;
1413 } else {
1414 prefix = "+";
1415 }
1416 slen +=
1417 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1418 prefix, offset);
1419 } else if (o->segment & SEG_DISP16) {
1420 const char *prefix;
1421 uint16_t offset = offs;
1422 if ((int16_t)offset < 0 && started) {
1423 offset = -offset;
1424 prefix = "-";
1425 } else {
1426 prefix = started ? "+" : "";
1427 }
1428 slen +=
1429 snprintf(output + slen, outbufsize - slen,
1430 "%s0x%"PRIx16"", prefix, offset);
1431 } else if (o->segment & SEG_DISP32) {
1432 if (prefix.asize == 64) {
1433 const char *prefix;
1434 uint64_t offset = (int64_t)(int32_t)offs;
1435 if ((int32_t)offs < 0 && started) {
1436 offset = -offset;
1437 prefix = "-";
1438 } else {
1439 prefix = started ? "+" : "";
1440 }
1441 slen +=
1442 snprintf(output + slen, outbufsize - slen,
1443 "%s0x%"PRIx64"", prefix, offset);
1444 } else {
1445 const char *prefix;
1446 uint32_t offset = offs;
1447 if ((int32_t) offset < 0 && started) {
1448 offset = -offset;
1449 prefix = "-";
1450 } else {
1451 prefix = started ? "+" : "";
1452 }
1453 slen +=
1454 snprintf(output + slen, outbufsize - slen,
1455 "%s0x%"PRIx32"", prefix, offset);
1456 }
1457 }
1458 output[slen++] = ']';
1459 } else {
1460 slen +=
1461 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1462 i);
1463 }
1464 }
1465 output[slen] = '\0';
1466 if (segover) { /* unused segment override */
1467 char *p = output;
1468 int count = slen + 1;
1469 while (count--)
1470 p[count + 3] = p[count];
1471 strncpy(output, segover, 2);
1472 output[2] = ' ';
1473 }
1474 return length;
1475 }
1476
1477 /*
1478 * This is called when we don't have a complete instruction. If it
1479 * is a standalone *single-byte* prefix show it as such, otherwise
1480 * print it as a literal.
1481 */
1482 int32_t eatbyte(uint8_t *data, char *output, int outbufsize, int segsize)
1483 {
1484 uint8_t byte = *data;
1485 const char *str = NULL;
1486
1487 switch (byte) {
1488 case 0xF2:
1489 str = "repne";
1490 break;
1491 case 0xF3:
1492 str = "rep";
1493 break;
1494 case 0x9B:
1495 str = "wait";
1496 break;
1497 case 0xF0:
1498 str = "lock";
1499 break;
1500 case 0x2E:
1501 str = "cs";
1502 break;
1503 case 0x36:
1504 str = "ss";
1505 break;
1506 case 0x3E:
1507 str = "ss";
1508 break;
1509 case 0x26:
1510 str = "es";
1511 break;
1512 case 0x64:
1513 str = "fs";
1514 break;
1515 case 0x65:
1516 str = "gs";
1517 break;
1518 case 0x66:
1519 str = (segsize == 16) ? "o32" : "o16";
1520 break;
1521 case 0x67:
1522 str = (segsize == 32) ? "a16" : "a32";
1523 break;
1524 case REX_P + 0x0:
1525 case REX_P + 0x1:
1526 case REX_P + 0x2:
1527 case REX_P + 0x3:
1528 case REX_P + 0x4:
1529 case REX_P + 0x5:
1530 case REX_P + 0x6:
1531 case REX_P + 0x7:
1532 case REX_P + 0x8:
1533 case REX_P + 0x9:
1534 case REX_P + 0xA:
1535 case REX_P + 0xB:
1536 case REX_P + 0xC:
1537 case REX_P + 0xD:
1538 case REX_P + 0xE:
1539 case REX_P + 0xF:
1540 if (segsize == 64) {
1541 snprintf(output, outbufsize, "rex%s%s%s%s%s",
1542 (byte == REX_P) ? "" : ".",
1543 (byte & REX_W) ? "w" : "",
1544 (byte & REX_R) ? "r" : "",
1545 (byte & REX_X) ? "x" : "",
1546 (byte & REX_B) ? "b" : "");
1547 break;
1548 }
1549 /* else fall through */
1550 default:
1551 snprintf(output, outbufsize, "db 0x%02x", byte);
1552 break;
1553 }
1554
1555 if (str)
1556 snprintf(output, outbufsize, "%s", str);
1557
1558 return 1;
1559 }
Netwide Assembler - Mirror