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insns.dat: Add hle flag for CMPXCHG instruction
[nasm/sigaren-mirror.git] / disasm.c
blobba4b8d2511393fe65e9017aeac61551818174e03
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2012 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * disasm.c where all the _work_ gets done in the Netwide Disassembler
36 */
37
38 #include "compiler.h"
39
40 #include <stdio.h>
41 #include <string.h>
42 #include <limits.h>
43 #include <inttypes.h>
44
45 #include "nasm.h"
46 #include "disasm.h"
47 #include "sync.h"
48 #include "insns.h"
49 #include "tables.h"
50 #include "regdis.h"
51
52 /*
53 * Flags that go into the `segment' field of `insn' structures
54 * during disassembly.
55 */
56 #define SEG_RELATIVE 1
57 #define SEG_32BIT 2
58 #define SEG_RMREG 4
59 #define SEG_DISP8 8
60 #define SEG_DISP16 16
61 #define SEG_DISP32 32
62 #define SEG_NODISP 64
63 #define SEG_SIGNED 128
64 #define SEG_64BIT 256
65
66 /*
67 * Prefix information
68 */
69 struct prefix_info {
70 uint8_t osize; /* Operand size */
71 uint8_t asize; /* Address size */
72 uint8_t osp; /* Operand size prefix present */
73 uint8_t asp; /* Address size prefix present */
74 uint8_t rep; /* Rep prefix present */
75 uint8_t seg; /* Segment override prefix present */
76 uint8_t wait; /* WAIT "prefix" present */
77 uint8_t lock; /* Lock prefix present */
78 uint8_t vex[3]; /* VEX prefix present */
79 uint8_t vex_c; /* VEX "class" (VEX, XOP, ...) */
80 uint8_t vex_m; /* VEX.M field */
81 uint8_t vex_v;
82 uint8_t vex_lp; /* VEX.LP fields */
83 uint32_t rex; /* REX prefix present */
84 };
85
86 #define getu8(x) (*(uint8_t *)(x))
87 #if X86_MEMORY
88 /* Littleendian CPU which can handle unaligned references */
89 #define getu16(x) (*(uint16_t *)(x))
90 #define getu32(x) (*(uint32_t *)(x))
91 #define getu64(x) (*(uint64_t *)(x))
92 #else
93 static uint16_t getu16(uint8_t *data)
94 {
95 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
96 }
97 static uint32_t getu32(uint8_t *data)
98 {
99 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
100 }
101 static uint64_t getu64(uint8_t *data)
102 {
103 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
104 }
105 #endif
106
107 #define gets8(x) ((int8_t)getu8(x))
108 #define gets16(x) ((int16_t)getu16(x))
109 #define gets32(x) ((int32_t)getu32(x))
110 #define gets64(x) ((int64_t)getu64(x))
111
112 /* Important: regval must already have been adjusted for rex extensions */
113 static enum reg_enum whichreg(opflags_t regflags, int regval, int rex)
114 {
115 if (!(regflags & (REGISTER|REGMEM)))
116 return 0; /* Registers not permissible?! */
117
118 regflags |= REGISTER;
119
120 if (!(REG_AL & ~regflags))
121 return R_AL;
122 if (!(REG_AX & ~regflags))
123 return R_AX;
124 if (!(REG_EAX & ~regflags))
125 return R_EAX;
126 if (!(REG_RAX & ~regflags))
127 return R_RAX;
128 if (!(REG_DL & ~regflags))
129 return R_DL;
130 if (!(REG_DX & ~regflags))
131 return R_DX;
132 if (!(REG_EDX & ~regflags))
133 return R_EDX;
134 if (!(REG_RDX & ~regflags))
135 return R_RDX;
136 if (!(REG_CL & ~regflags))
137 return R_CL;
138 if (!(REG_CX & ~regflags))
139 return R_CX;
140 if (!(REG_ECX & ~regflags))
141 return R_ECX;
142 if (!(REG_RCX & ~regflags))
143 return R_RCX;
144 if (!(FPU0 & ~regflags))
145 return R_ST0;
146 if (!(XMM0 & ~regflags))
147 return R_XMM0;
148 if (!(YMM0 & ~regflags))
149 return R_YMM0;
150 if (!(REG_CS & ~regflags))
151 return (regval == 1) ? R_CS : 0;
152 if (!(REG_DESS & ~regflags))
153 return (regval == 0 || regval == 2
154 || regval == 3 ? nasm_rd_sreg[regval] : 0);
155 if (!(REG_FSGS & ~regflags))
156 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
157 if (!(REG_SEG67 & ~regflags))
158 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
159
160 /* All the entries below look up regval in an 16-entry array */
161 if (regval < 0 || regval > 15)
162 return 0;
163
164 if (!(REG8 & ~regflags)) {
165 if (rex & (REX_P|REX_NH))
166 return nasm_rd_reg8_rex[regval];
167 else
168 return nasm_rd_reg8[regval];
169 }
170 if (!(REG16 & ~regflags))
171 return nasm_rd_reg16[regval];
172 if (!(REG32 & ~regflags))
173 return nasm_rd_reg32[regval];
174 if (!(REG64 & ~regflags))
175 return nasm_rd_reg64[regval];
176 if (!(REG_SREG & ~regflags))
177 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
178 if (!(REG_CREG & ~regflags))
179 return nasm_rd_creg[regval];
180 if (!(REG_DREG & ~regflags))
181 return nasm_rd_dreg[regval];
182 if (!(REG_TREG & ~regflags)) {
183 if (regval > 7)
184 return 0; /* TR registers are ill-defined with rex */
185 return nasm_rd_treg[regval];
186 }
187 if (!(FPUREG & ~regflags))
188 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
189 if (!(MMXREG & ~regflags))
190 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
191 if (!(XMMREG & ~regflags))
192 return nasm_rd_xmmreg[regval];
193 if (!(YMMREG & ~regflags))
194 return nasm_rd_ymmreg[regval];
195
196 return 0;
197 }
198
199 /*
200 * Process an effective address (ModRM) specification.
201 */
202 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
203 int segsize, enum ea_type type,
204 operand *op, insn *ins)
205 {
206 int mod, rm, scale, index, base;
207 int rex;
208 uint8_t sib = 0;
209
210 mod = (modrm >> 6) & 03;
211 rm = modrm & 07;
212
213 if (mod != 3 && asize != 16 && rm == 4)
214 sib = *data++;
215
216 rex = ins->rex;
217
218 if (mod == 3) { /* pure register version */
219 op->basereg = rm+(rex & REX_B ? 8 : 0);
220 op->segment |= SEG_RMREG;
221 return data;
222 }
223
224 op->disp_size = 0;
225 op->eaflags = 0;
226
227 if (asize == 16) {
228 /*
229 * <mod> specifies the displacement size (none, byte or
230 * word), and <rm> specifies the register combination.
231 * Exception: mod=0,rm=6 does not specify [BP] as one might
232 * expect, but instead specifies [disp16].
233 */
234
235 if (type != EA_SCALAR)
236 return NULL;
237
238 op->indexreg = op->basereg = -1;
239 op->scale = 1; /* always, in 16 bits */
240 switch (rm) {
241 case 0:
242 op->basereg = R_BX;
243 op->indexreg = R_SI;
244 break;
245 case 1:
246 op->basereg = R_BX;
247 op->indexreg = R_DI;
248 break;
249 case 2:
250 op->basereg = R_BP;
251 op->indexreg = R_SI;
252 break;
253 case 3:
254 op->basereg = R_BP;
255 op->indexreg = R_DI;
256 break;
257 case 4:
258 op->basereg = R_SI;
259 break;
260 case 5:
261 op->basereg = R_DI;
262 break;
263 case 6:
264 op->basereg = R_BP;
265 break;
266 case 7:
267 op->basereg = R_BX;
268 break;
269 }
270 if (rm == 6 && mod == 0) { /* special case */
271 op->basereg = -1;
272 if (segsize != 16)
273 op->disp_size = 16;
274 mod = 2; /* fake disp16 */
275 }
276 switch (mod) {
277 case 0:
278 op->segment |= SEG_NODISP;
279 break;
280 case 1:
281 op->segment |= SEG_DISP8;
282 op->offset = (int8_t)*data++;
283 break;
284 case 2:
285 op->segment |= SEG_DISP16;
286 op->offset = *data++;
287 op->offset |= ((unsigned)*data++) << 8;
288 break;
289 }
290 return data;
291 } else {
292 /*
293 * Once again, <mod> specifies displacement size (this time
294 * none, byte or *dword*), while <rm> specifies the base
295 * register. Again, [EBP] is missing, replaced by a pure
296 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
297 * and RIP-relative addressing in 64-bit mode.
298 *
299 * However, rm=4
300 * indicates not a single base register, but instead the
301 * presence of a SIB byte...
302 */
303 int a64 = asize == 64;
304
305 op->indexreg = -1;
306
307 if (a64)
308 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
309 else
310 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
311
312 if (rm == 5 && mod == 0) {
313 if (segsize == 64) {
314 op->eaflags |= EAF_REL;
315 op->segment |= SEG_RELATIVE;
316 mod = 2; /* fake disp32 */
317 }
318
319 if (asize != 64)
320 op->disp_size = asize;
321
322 op->basereg = -1;
323 mod = 2; /* fake disp32 */
324 }
325
326
327 if (rm == 4) { /* process SIB */
328 scale = (sib >> 6) & 03;
329 index = (sib >> 3) & 07;
330 base = sib & 07;
331
332 op->scale = 1 << scale;
333
334 if (type == EA_XMMVSIB)
335 op->indexreg = nasm_rd_xmmreg[index | ((rex & REX_X) ? 8 : 0)];
336 else if (type == EA_YMMVSIB)
337 op->indexreg = nasm_rd_ymmreg[index | ((rex & REX_X) ? 8 : 0)];
338 else if (index == 4 && !(rex & REX_X))
339 op->indexreg = -1; /* ESP/RSP cannot be an index */
340 else if (a64)
341 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
342 else
343 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
344
345 if (base == 5 && mod == 0) {
346 op->basereg = -1;
347 mod = 2; /* Fake disp32 */
348 } else if (a64)
349 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
350 else
351 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
352
353 if (segsize == 16)
354 op->disp_size = 32;
355 } else if (type != EA_SCALAR) {
356 /* Can't have VSIB without SIB */
357 return NULL;
358 }
359
360 switch (mod) {
361 case 0:
362 op->segment |= SEG_NODISP;
363 break;
364 case 1:
365 op->segment |= SEG_DISP8;
366 op->offset = gets8(data);
367 data++;
368 break;
369 case 2:
370 op->segment |= SEG_DISP32;
371 op->offset = gets32(data);
372 data += 4;
373 break;
374 }
375 return data;
376 }
377 }
378
379 /*
380 * Determine whether the instruction template in t corresponds to the data
381 * stream in data. Return the number of bytes matched if so.
382 */
383 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
384
385 static int matches(const struct itemplate *t, uint8_t *data,
386 const struct prefix_info *prefix, int segsize, insn *ins)
387 {
388 uint8_t *r = (uint8_t *)(t->code);
389 uint8_t *origdata = data;
390 bool a_used = false, o_used = false;
391 enum prefixes drep = 0;
392 enum prefixes dwait = 0;
393 uint8_t lock = prefix->lock;
394 int osize = prefix->osize;
395 int asize = prefix->asize;
396 int i, c;
397 int op1, op2;
398 struct operand *opx, *opy;
399 uint8_t opex = 0;
400 int s_field_for = -1; /* No 144/154 series code encountered */
401 bool vex_ok = false;
402 int regmask = (segsize == 64) ? 15 : 7;
403 enum ea_type eat = EA_SCALAR;
404
405 for (i = 0; i < MAX_OPERANDS; i++) {
406 ins->oprs[i].segment = ins->oprs[i].disp_size =
407 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
408 }
409 ins->condition = -1;
410 ins->rex = prefix->rex;
411 memset(ins->prefixes, 0, sizeof ins->prefixes);
412
413 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
414 return false;
415
416 if (prefix->rep == 0xF2)
417 drep = P_REPNE;
418 else if (prefix->rep == 0xF3)
419 drep = P_REP;
420
421 dwait = prefix->wait ? P_WAIT : 0;
422
423 while ((c = *r++) != 0) {
424 op1 = (c & 3) + ((opex & 1) << 2);
425 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
426 opx = &ins->oprs[op1];
427 opy = &ins->oprs[op2];
428 opex = 0;
429
430 switch (c) {
431 case 01:
432 case 02:
433 case 03:
434 case 04:
435 while (c--)
436 if (*r++ != *data++)
437 return false;
438 break;
439
440 case 05:
441 case 06:
442 case 07:
443 opex = c;
444 break;
445
446 case4(010):
447 {
448 int t = *r++, d = *data++;
449 if (d < t || d > t + 7)
450 return false;
451 else {
452 opx->basereg = (d-t)+
453 (ins->rex & REX_B ? 8 : 0);
454 opx->segment |= SEG_RMREG;
455 }
456 break;
457 }
458
459 case4(014):
460 case4(0274):
461 opx->offset = (int8_t)*data++;
462 opx->segment |= SEG_SIGNED;
463 break;
464
465 case4(020):
466 opx->offset = *data++;
467 break;
468
469 case4(024):
470 opx->offset = *data++;
471 break;
472
473 case4(030):
474 opx->offset = getu16(data);
475 data += 2;
476 break;
477
478 case4(034):
479 if (osize == 32) {
480 opx->offset = getu32(data);
481 data += 4;
482 } else {
483 opx->offset = getu16(data);
484 data += 2;
485 }
486 if (segsize != asize)
487 opx->disp_size = asize;
488 break;
489
490 case4(040):
491 case4(0254):
492 opx->offset = getu32(data);
493 data += 4;
494 break;
495
496 case4(044):
497 switch (asize) {
498 case 16:
499 opx->offset = getu16(data);
500 data += 2;
501 if (segsize != 16)
502 opx->disp_size = 16;
503 break;
504 case 32:
505 opx->offset = getu32(data);
506 data += 4;
507 if (segsize == 16)
508 opx->disp_size = 32;
509 break;
510 case 64:
511 opx->offset = getu64(data);
512 opx->disp_size = 64;
513 data += 8;
514 break;
515 }
516 break;
517
518 case4(050):
519 opx->offset = gets8(data++);
520 opx->segment |= SEG_RELATIVE;
521 break;
522
523 case4(054):
524 opx->offset = getu64(data);
525 data += 8;
526 break;
527
528 case4(060):
529 opx->offset = gets16(data);
530 data += 2;
531 opx->segment |= SEG_RELATIVE;
532 opx->segment &= ~SEG_32BIT;
533 break;
534
535 case4(064):
536 opx->segment |= SEG_RELATIVE;
537 if (osize == 16) {
538 opx->offset = gets16(data);
539 data += 2;
540 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
541 } else if (osize == 32) {
542 opx->offset = gets32(data);
543 data += 4;
544 opx->segment &= ~SEG_64BIT;
545 opx->segment |= SEG_32BIT;
546 }
547 if (segsize != osize) {
548 opx->type =
549 (opx->type & ~SIZE_MASK)
550 | ((osize == 16) ? BITS16 : BITS32);
551 }
552 break;
553
554 case4(070):
555 opx->offset = gets32(data);
556 data += 4;
557 opx->segment |= SEG_32BIT | SEG_RELATIVE;
558 break;
559
560 case4(0100):
561 case4(0110):
562 case4(0120):
563 case4(0130):
564 {
565 int modrm = *data++;
566 opx->segment |= SEG_RMREG;
567 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
568 if (!data)
569 return false;
570 opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0);
571 break;
572 }
573
574 case4(0140):
575 if (s_field_for == op1) {
576 opx->offset = gets8(data);
577 data++;
578 } else {
579 opx->offset = getu16(data);
580 data += 2;
581 }
582 break;
583
584 case4(0144):
585 case4(0154):
586 s_field_for = (*data & 0x02) ? op1 : -1;
587 if ((*data++ & ~0x02) != *r++)
588 return false;
589 break;
590
591 case4(0150):
592 if (s_field_for == op1) {
593 opx->offset = gets8(data);
594 data++;
595 } else {
596 opx->offset = getu32(data);
597 data += 4;
598 }
599 break;
600
601 case 0172:
602 {
603 uint8_t ximm = *data++;
604 c = *r++;
605 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
606 ins->oprs[c >> 3].segment |= SEG_RMREG;
607 ins->oprs[c & 7].offset = ximm & 15;
608 }
609 break;
610
611 case 0173:
612 {
613 uint8_t ximm = *data++;
614 c = *r++;
615
616 if ((c ^ ximm) & 15)
617 return false;
618
619 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
620 ins->oprs[c >> 4].segment |= SEG_RMREG;
621 }
622 break;
623
624 case4(0174):
625 {
626 uint8_t ximm = *data++;
627
628 opx->basereg = (ximm >> 4) & regmask;
629 opx->segment |= SEG_RMREG;
630 }
631 break;
632
633 case4(0200):
634 case4(0204):
635 case4(0210):
636 case4(0214):
637 case4(0220):
638 case4(0224):
639 case4(0230):
640 case4(0234):
641 {
642 int modrm = *data++;
643 if (((modrm >> 3) & 07) != (c & 07))
644 return false; /* spare field doesn't match up */
645 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
646 if (!data)
647 return false;
648 break;
649 }
650
651 case4(0250):
652 if (s_field_for == op1) {
653 opx->offset = gets8(data);
654 data++;
655 } else {
656 opx->offset = gets32(data);
657 data += 4;
658 }
659 break;
660
661 case4(0260):
662 case 0270:
663 {
664 int vexm = *r++;
665 int vexwlp = *r++;
666
667 ins->rex |= REX_V;
668 if ((prefix->rex & (REX_V|REX_P)) != REX_V)
669 return false;
670
671 if ((vexm & 0x1f) != prefix->vex_m)
672 return false;
673
674 switch (vexwlp & 060) {
675 case 000:
676 if (prefix->rex & REX_W)
677 return false;
678 break;
679 case 020:
680 if (!(prefix->rex & REX_W))
681 return false;
682 ins->rex &= ~REX_W;
683 break;
684 case 040: /* VEX.W is a don't care */
685 ins->rex &= ~REX_W;
686 break;
687 case 060:
688 break;
689 }
690
691 /* The 010 bit of vexwlp is set if VEX.L is ignored */
692 if ((vexwlp ^ prefix->vex_lp) & ((vexwlp & 010) ? 03 : 07))
693 return false;
694
695 if (c == 0270) {
696 if (prefix->vex_v != 0)
697 return false;
698 } else {
699 opx->segment |= SEG_RMREG;
700 opx->basereg = prefix->vex_v;
701 }
702 vex_ok = true;
703 break;
704 }
705
706 case 0264:
707 break;
708
709 case 0265:
710 if (prefix->rep == 0xF3)
711 drep = P_XRELEASE;
712 break;
713
714 case 0266:
715 if (prefix->rep == 0xF2)
716 drep = P_XACQUIRE;
717 else if (prefix->rep == 0xF3)
718 drep = P_XRELEASE;
719 break;
720
721 case 0267:
722 if (prefix->lock == 0xF0) {
723 if (prefix->rep == 0xF2)
724 drep = P_XACQUIRE;
725 else if (prefix->rep == 0xF3)
726 drep = P_XRELEASE;
727 }
728 break;
729
730 case 0310:
731 if (asize != 16)
732 return false;
733 else
734 a_used = true;
735 break;
736
737 case 0311:
738 if (asize != 32)
739 return false;
740 else
741 a_used = true;
742 break;
743
744 case 0312:
745 if (asize != segsize)
746 return false;
747 else
748 a_used = true;
749 break;
750
751 case 0313:
752 if (asize != 64)
753 return false;
754 else
755 a_used = true;
756 break;
757
758 case 0314:
759 if (prefix->rex & REX_B)
760 return false;
761 break;
762
763 case 0315:
764 if (prefix->rex & REX_X)
765 return false;
766 break;
767
768 case 0316:
769 if (prefix->rex & REX_R)
770 return false;
771 break;
772
773 case 0317:
774 if (prefix->rex & REX_W)
775 return false;
776 break;
777
778 case 0320:
779 if (osize != 16)
780 return false;
781 else
782 o_used = true;
783 break;
784
785 case 0321:
786 if (osize != 32)
787 return false;
788 else
789 o_used = true;
790 break;
791
792 case 0322:
793 if (osize != (segsize == 16) ? 16 : 32)
794 return false;
795 else
796 o_used = true;
797 break;
798
799 case 0323:
800 ins->rex |= REX_W; /* 64-bit only instruction */
801 osize = 64;
802 o_used = true;
803 break;
804
805 case 0324:
806 if (osize != 64)
807 return false;
808 o_used = true;
809 break;
810
811 case 0325:
812 ins->rex |= REX_NH;
813 break;
814
815 case 0330:
816 {
817 int t = *r++, d = *data++;
818 if (d < t || d > t + 15)
819 return false;
820 else
821 ins->condition = d - t;
822 break;
823 }
824
825 case 0331:
826 if (prefix->rep)
827 return false;
828 break;
829
830 case 0332:
831 if (prefix->rep != 0xF2)
832 return false;
833 drep = 0;
834 break;
835
836 case 0333:
837 if (prefix->rep != 0xF3)
838 return false;
839 drep = 0;
840 break;
841
842 case 0334:
843 if (lock) {
844 ins->rex |= REX_R;
845 lock = 0;
846 }
847 break;
848
849 case 0335:
850 if (drep == P_REP)
851 drep = P_REPE;
852 break;
853
854 case 0336:
855 case 0337:
856 break;
857
858 case 0340:
859 return false;
860
861 case 0341:
862 if (prefix->wait != 0x9B)
863 return false;
864 dwait = 0;
865 break;
866
867 case4(0344):
868 ins->oprs[0].basereg = (*data++ >> 3) & 7;
869 break;
870
871 case 0360:
872 if (prefix->osp || prefix->rep)
873 return false;
874 break;
875
876 case 0361:
877 if (!prefix->osp || prefix->rep)
878 return false;
879 o_used = true;
880 break;
881
882 case 0362:
883 if (prefix->osp || prefix->rep != 0xf2)
884 return false;
885 drep = 0;
886 break;
887
888 case 0363:
889 if (prefix->osp || prefix->rep != 0xf3)
890 return false;
891 drep = 0;
892 break;
893
894 case 0364:
895 if (prefix->osp)
896 return false;
897 break;
898
899 case 0365:
900 if (prefix->asp)
901 return false;
902 break;
903
904 case 0366:
905 if (!prefix->osp)
906 return false;
907 o_used = true;
908 break;
909
910 case 0367:
911 if (!prefix->asp)
912 return false;
913 a_used = true;
914 break;
915
916 case 0370:
917 case 0371:
918 break;
919
920 case 0374:
921 eat = EA_XMMVSIB;
922 break;
923
924 case 0375:
925 eat = EA_YMMVSIB;
926 break;
927
928 default:
929 return false; /* Unknown code */
930 }
931 }
932
933 if (!vex_ok && (ins->rex & REX_V))
934 return false;
935
936 /* REX cannot be combined with VEX */
937 if ((ins->rex & REX_V) && (prefix->rex & REX_P))
938 return false;
939
940 /*
941 * Check for unused rep or a/o prefixes.
942 */
943 for (i = 0; i < t->operands; i++) {
944 if (ins->oprs[i].segment != SEG_RMREG)
945 a_used = true;
946 }
947
948 if (lock) {
949 if (ins->prefixes[PPS_LOCK])
950 return false;
951 ins->prefixes[PPS_LOCK] = P_LOCK;
952 }
953 if (drep) {
954 if (ins->prefixes[PPS_REP])
955 return false;
956 ins->prefixes[PPS_REP] = drep;
957 }
958 ins->prefixes[PPS_WAIT] = dwait;
959 if (!o_used) {
960 if (osize != ((segsize == 16) ? 16 : 32)) {
961 enum prefixes pfx = 0;
962
963 switch (osize) {
964 case 16:
965 pfx = P_O16;
966 break;
967 case 32:
968 pfx = P_O32;
969 break;
970 case 64:
971 pfx = P_O64;
972 break;
973 }
974
975 if (ins->prefixes[PPS_OSIZE])
976 return false;
977 ins->prefixes[PPS_OSIZE] = pfx;
978 }
979 }
980 if (!a_used && asize != segsize) {
981 if (ins->prefixes[PPS_ASIZE])
982 return false;
983 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
984 }
985
986 /* Fix: check for redundant REX prefixes */
987
988 return data - origdata;
989 }
990
991 /* Condition names for disassembly, sorted by x86 code */
992 static const char * const condition_name[16] = {
993 "o", "no", "c", "nc", "z", "nz", "na", "a",
994 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
995 };
996
997 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
998 int32_t offset, int autosync, uint32_t prefer)
999 {
1000 const struct itemplate * const *p, * const *best_p;
1001 const struct disasm_index *ix;
1002 uint8_t *dp;
1003 int length, best_length = 0;
1004 char *segover;
1005 int i, slen, colon, n;
1006 uint8_t *origdata;
1007 int works;
1008 insn tmp_ins, ins;
1009 uint32_t goodness, best;
1010 int best_pref;
1011 struct prefix_info prefix;
1012 bool end_prefix;
1013
1014 memset(&ins, 0, sizeof ins);
1015
1016 /*
1017 * Scan for prefixes.
1018 */
1019 memset(&prefix, 0, sizeof prefix);
1020 prefix.asize = segsize;
1021 prefix.osize = (segsize == 64) ? 32 : segsize;
1022 segover = NULL;
1023 origdata = data;
1024
1025 ix = itable;
1026
1027 end_prefix = false;
1028 while (!end_prefix) {
1029 switch (*data) {
1030 case 0xF2:
1031 case 0xF3:
1032 prefix.rep = *data++;
1033 break;
1034
1035 case 0x9B:
1036 prefix.wait = *data++;
1037 break;
1038
1039 case 0xF0:
1040 prefix.lock = *data++;
1041 break;
1042
1043 case 0x2E:
1044 segover = "cs", prefix.seg = *data++;
1045 break;
1046 case 0x36:
1047 segover = "ss", prefix.seg = *data++;
1048 break;
1049 case 0x3E:
1050 segover = "ds", prefix.seg = *data++;
1051 break;
1052 case 0x26:
1053 segover = "es", prefix.seg = *data++;
1054 break;
1055 case 0x64:
1056 segover = "fs", prefix.seg = *data++;
1057 break;
1058 case 0x65:
1059 segover = "gs", prefix.seg = *data++;
1060 break;
1061
1062 case 0x66:
1063 prefix.osize = (segsize == 16) ? 32 : 16;
1064 prefix.osp = *data++;
1065 break;
1066 case 0x67:
1067 prefix.asize = (segsize == 32) ? 16 : 32;
1068 prefix.asp = *data++;
1069 break;
1070
1071 case 0xC4:
1072 case 0xC5:
1073 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1074 prefix.vex[0] = *data++;
1075 prefix.vex[1] = *data++;
1076
1077 prefix.rex = REX_V;
1078 prefix.vex_c = RV_VEX;
1079
1080 if (prefix.vex[0] == 0xc4) {
1081 prefix.vex[2] = *data++;
1082 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1083 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1084 prefix.vex_m = prefix.vex[1] & 0x1f;
1085 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1086 prefix.vex_lp = prefix.vex[2] & 7;
1087 } else {
1088 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1089 prefix.vex_m = 1;
1090 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1091 prefix.vex_lp = prefix.vex[1] & 7;
1092 }
1093
1094 ix = itable_vex[RV_VEX][prefix.vex_m][prefix.vex_lp & 3];
1095 }
1096 end_prefix = true;
1097 break;
1098
1099 case 0x8F:
1100 if ((data[1] & 030) != 0 &&
1101 (segsize == 64 || (data[1] & 0xc0) == 0xc0)) {
1102 prefix.vex[0] = *data++;
1103 prefix.vex[1] = *data++;
1104 prefix.vex[2] = *data++;
1105
1106 prefix.rex = REX_V;
1107 prefix.vex_c = RV_XOP;
1108
1109 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1110 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1111 prefix.vex_m = prefix.vex[1] & 0x1f;
1112 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1113 prefix.vex_lp = prefix.vex[2] & 7;
1114
1115 ix = itable_vex[RV_XOP][prefix.vex_m][prefix.vex_lp & 3];
1116 }
1117 end_prefix = true;
1118 break;
1119
1120 case REX_P + 0x0:
1121 case REX_P + 0x1:
1122 case REX_P + 0x2:
1123 case REX_P + 0x3:
1124 case REX_P + 0x4:
1125 case REX_P + 0x5:
1126 case REX_P + 0x6:
1127 case REX_P + 0x7:
1128 case REX_P + 0x8:
1129 case REX_P + 0x9:
1130 case REX_P + 0xA:
1131 case REX_P + 0xB:
1132 case REX_P + 0xC:
1133 case REX_P + 0xD:
1134 case REX_P + 0xE:
1135 case REX_P + 0xF:
1136 if (segsize == 64) {
1137 prefix.rex = *data++;
1138 if (prefix.rex & REX_W)
1139 prefix.osize = 64;
1140 }
1141 end_prefix = true;
1142 break;
1143
1144 default:
1145 end_prefix = true;
1146 break;
1147 }
1148 }
1149
1150 best = -1; /* Worst possible */
1151 best_p = NULL;
1152 best_pref = INT_MAX;
1153
1154 if (!ix)
1155 return 0; /* No instruction table at all... */
1156
1157 dp = data;
1158 ix += *dp++;
1159 while (ix->n == -1) {
1160 ix = (const struct disasm_index *)ix->p + *dp++;
1161 }
1162
1163 p = (const struct itemplate * const *)ix->p;
1164 for (n = ix->n; n; n--, p++) {
1165 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1166 works = true;
1167 /*
1168 * Final check to make sure the types of r/m match up.
1169 * XXX: Need to make sure this is actually correct.
1170 */
1171 for (i = 0; i < (*p)->operands; i++) {
1172 if (!((*p)->opd[i] & SAME_AS) &&
1173 (
1174 /* If it's a mem-only EA but we have a
1175 register, die. */
1176 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1177 is_class(MEMORY, (*p)->opd[i])) ||
1178 /* If it's a reg-only EA but we have a memory
1179 ref, die. */
1180 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1181 !(REG_EA & ~(*p)->opd[i]) &&
1182 !((*p)->opd[i] & REG_SMASK)) ||
1183 /* Register type mismatch (eg FS vs REG_DESS):
1184 die. */
1185 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1186 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1187 !whichreg((*p)->opd[i],
1188 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1189 )) {
1190 works = false;
1191 break;
1192 }
1193 }
1194
1195 /*
1196 * Note: we always prefer instructions which incorporate
1197 * prefixes in the instructions themselves. This is to allow
1198 * e.g. PAUSE to be preferred to REP NOP, and deal with
1199 * MMX/SSE instructions where prefixes are used to select
1200 * between MMX and SSE register sets or outright opcode
1201 * selection.
1202 */
1203 if (works) {
1204 int i, nprefix;
1205 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1206 nprefix = 0;
1207 for (i = 0; i < MAXPREFIX; i++)
1208 if (tmp_ins.prefixes[i])
1209 nprefix++;
1210 if (nprefix < best_pref ||
1211 (nprefix == best_pref && goodness < best)) {
1212 /* This is the best one found so far */
1213 best = goodness;
1214 best_p = p;
1215 best_pref = nprefix;
1216 best_length = length;
1217 ins = tmp_ins;
1218 }
1219 }
1220 }
1221 }
1222
1223 if (!best_p)
1224 return 0; /* no instruction was matched */
1225
1226 /* Pick the best match */
1227 p = best_p;
1228 length = best_length;
1229
1230 slen = 0;
1231
1232 /* TODO: snprintf returns the value that the string would have if
1233 * the buffer were long enough, and not the actual length of
1234 * the returned string, so each instance of using the return
1235 * value of snprintf should actually be checked to assure that
1236 * the return value is "sane." Maybe a macro wrapper could
1237 * be used for that purpose.
1238 */
1239 for (i = 0; i < MAXPREFIX; i++) {
1240 const char *prefix = prefix_name(ins.prefixes[i]);
1241 if (prefix)
1242 slen += snprintf(output+slen, outbufsize-slen, "%s ", prefix);
1243 }
1244
1245 i = (*p)->opcode;
1246 if (i >= FIRST_COND_OPCODE)
1247 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1248 nasm_insn_names[i], condition_name[ins.condition]);
1249 else
1250 slen += snprintf(output + slen, outbufsize - slen, "%s",
1251 nasm_insn_names[i]);
1252
1253 colon = false;
1254 length += data - origdata; /* fix up for prefixes */
1255 for (i = 0; i < (*p)->operands; i++) {
1256 opflags_t t = (*p)->opd[i];
1257 const operand *o = &ins.oprs[i];
1258 int64_t offs;
1259
1260 if (t & SAME_AS) {
1261 o = &ins.oprs[t & ~SAME_AS];
1262 t = (*p)->opd[t & ~SAME_AS];
1263 }
1264
1265 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1266
1267 offs = o->offset;
1268 if (o->segment & SEG_RELATIVE) {
1269 offs += offset + length;
1270 /*
1271 * sort out wraparound
1272 */
1273 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1274 offs &= 0xffff;
1275 else if (segsize != 64)
1276 offs &= 0xffffffff;
1277
1278 /*
1279 * add sync marker, if autosync is on
1280 */
1281 if (autosync)
1282 add_sync(offs, 0L);
1283 }
1284
1285 if (t & COLON)
1286 colon = true;
1287 else
1288 colon = false;
1289
1290 if ((t & (REGISTER | FPUREG)) ||
1291 (o->segment & SEG_RMREG)) {
1292 enum reg_enum reg;
1293 reg = whichreg(t, o->basereg, ins.rex);
1294 if (t & TO)
1295 slen += snprintf(output + slen, outbufsize - slen, "to ");
1296 slen += snprintf(output + slen, outbufsize - slen, "%s",
1297 nasm_reg_names[reg-EXPR_REG_START]);
1298 } else if (!(UNITY & ~t)) {
1299 output[slen++] = '1';
1300 } else if (t & IMMEDIATE) {
1301 if (t & BITS8) {
1302 slen +=
1303 snprintf(output + slen, outbufsize - slen, "byte ");
1304 if (o->segment & SEG_SIGNED) {
1305 if (offs < 0) {
1306 offs *= -1;
1307 output[slen++] = '-';
1308 } else
1309 output[slen++] = '+';
1310 }
1311 } else if (t & BITS16) {
1312 slen +=
1313 snprintf(output + slen, outbufsize - slen, "word ");
1314 } else if (t & BITS32) {
1315 slen +=
1316 snprintf(output + slen, outbufsize - slen, "dword ");
1317 } else if (t & BITS64) {
1318 slen +=
1319 snprintf(output + slen, outbufsize - slen, "qword ");
1320 } else if (t & NEAR) {
1321 slen +=
1322 snprintf(output + slen, outbufsize - slen, "near ");
1323 } else if (t & SHORT) {
1324 slen +=
1325 snprintf(output + slen, outbufsize - slen, "short ");
1326 }
1327 slen +=
1328 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1329 offs);
1330 } else if (!(MEM_OFFS & ~t)) {
1331 slen +=
1332 snprintf(output + slen, outbufsize - slen,
1333 "[%s%s%s0x%"PRIx64"]",
1334 (segover ? segover : ""),
1335 (segover ? ":" : ""),
1336 (o->disp_size == 64 ? "qword " :
1337 o->disp_size == 32 ? "dword " :
1338 o->disp_size == 16 ? "word " : ""), offs);
1339 segover = NULL;
1340 } else if (is_class(REGMEM, t)) {
1341 int started = false;
1342 if (t & BITS8)
1343 slen +=
1344 snprintf(output + slen, outbufsize - slen, "byte ");
1345 if (t & BITS16)
1346 slen +=
1347 snprintf(output + slen, outbufsize - slen, "word ");
1348 if (t & BITS32)
1349 slen +=
1350 snprintf(output + slen, outbufsize - slen, "dword ");
1351 if (t & BITS64)
1352 slen +=
1353 snprintf(output + slen, outbufsize - slen, "qword ");
1354 if (t & BITS80)
1355 slen +=
1356 snprintf(output + slen, outbufsize - slen, "tword ");
1357 if (t & BITS128)
1358 slen +=
1359 snprintf(output + slen, outbufsize - slen, "oword ");
1360 if (t & BITS256)
1361 slen +=
1362 snprintf(output + slen, outbufsize - slen, "yword ");
1363 if (t & FAR)
1364 slen += snprintf(output + slen, outbufsize - slen, "far ");
1365 if (t & NEAR)
1366 slen +=
1367 snprintf(output + slen, outbufsize - slen, "near ");
1368 output[slen++] = '[';
1369 if (o->disp_size)
1370 slen += snprintf(output + slen, outbufsize - slen, "%s",
1371 (o->disp_size == 64 ? "qword " :
1372 o->disp_size == 32 ? "dword " :
1373 o->disp_size == 16 ? "word " :
1374 ""));
1375 if (o->eaflags & EAF_REL)
1376 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1377 if (segover) {
1378 slen +=
1379 snprintf(output + slen, outbufsize - slen, "%s:",
1380 segover);
1381 segover = NULL;
1382 }
1383 if (o->basereg != -1) {
1384 slen += snprintf(output + slen, outbufsize - slen, "%s",
1385 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1386 started = true;
1387 }
1388 if (o->indexreg != -1) {
1389 if (started)
1390 output[slen++] = '+';
1391 slen += snprintf(output + slen, outbufsize - slen, "%s",
1392 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1393 if (o->scale > 1)
1394 slen +=
1395 snprintf(output + slen, outbufsize - slen, "*%d",
1396 o->scale);
1397 started = true;
1398 }
1399
1400
1401 if (o->segment & SEG_DISP8) {
1402 const char *prefix;
1403 uint8_t offset = offs;
1404 if ((int8_t)offset < 0) {
1405 prefix = "-";
1406 offset = -offset;
1407 } else {
1408 prefix = "+";
1409 }
1410 slen +=
1411 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1412 prefix, offset);
1413 } else if (o->segment & SEG_DISP16) {
1414 const char *prefix;
1415 uint16_t offset = offs;
1416 if ((int16_t)offset < 0 && started) {
1417 offset = -offset;
1418 prefix = "-";
1419 } else {
1420 prefix = started ? "+" : "";
1421 }
1422 slen +=
1423 snprintf(output + slen, outbufsize - slen,
1424 "%s0x%"PRIx16"", prefix, offset);
1425 } else if (o->segment & SEG_DISP32) {
1426 if (prefix.asize == 64) {
1427 const char *prefix;
1428 uint64_t offset = (int64_t)(int32_t)offs;
1429 if ((int32_t)offs < 0 && started) {
1430 offset = -offset;
1431 prefix = "-";
1432 } else {
1433 prefix = started ? "+" : "";
1434 }
1435 slen +=
1436 snprintf(output + slen, outbufsize - slen,
1437 "%s0x%"PRIx64"", prefix, offset);
1438 } else {
1439 const char *prefix;
1440 uint32_t offset = offs;
1441 if ((int32_t) offset < 0 && started) {
1442 offset = -offset;
1443 prefix = "-";
1444 } else {
1445 prefix = started ? "+" : "";
1446 }
1447 slen +=
1448 snprintf(output + slen, outbufsize - slen,
1449 "%s0x%"PRIx32"", prefix, offset);
1450 }
1451 }
1452 output[slen++] = ']';
1453 } else {
1454 slen +=
1455 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1456 i);
1457 }
1458 }
1459 output[slen] = '\0';
1460 if (segover) { /* unused segment override */
1461 char *p = output;
1462 int count = slen + 1;
1463 while (count--)
1464 p[count + 3] = p[count];
1465 strncpy(output, segover, 2);
1466 output[2] = ' ';
1467 }
1468 return length;
1469 }
1470
1471 /*
1472 * This is called when we don't have a complete instruction. If it
1473 * is a standalone *single-byte* prefix show it as such, otherwise
1474 * print it as a literal.
1475 */
1476 int32_t eatbyte(uint8_t *data, char *output, int outbufsize, int segsize)
1477 {
1478 uint8_t byte = *data;
1479 const char *str = NULL;
1480
1481 switch (byte) {
1482 case 0xF2:
1483 str = "repne";
1484 break;
1485 case 0xF3:
1486 str = "rep";
1487 break;
1488 case 0x9B:
1489 str = "wait";
1490 break;
1491 case 0xF0:
1492 str = "lock";
1493 break;
1494 case 0x2E:
1495 str = "cs";
1496 break;
1497 case 0x36:
1498 str = "ss";
1499 break;
1500 case 0x3E:
1501 str = "ss";
1502 break;
1503 case 0x26:
1504 str = "es";
1505 break;
1506 case 0x64:
1507 str = "fs";
1508 break;
1509 case 0x65:
1510 str = "gs";
1511 break;
1512 case 0x66:
1513 str = (segsize == 16) ? "o32" : "o16";
1514 break;
1515 case 0x67:
1516 str = (segsize == 32) ? "a16" : "a32";
1517 break;
1518 case REX_P + 0x0:
1519 case REX_P + 0x1:
1520 case REX_P + 0x2:
1521 case REX_P + 0x3:
1522 case REX_P + 0x4:
1523 case REX_P + 0x5:
1524 case REX_P + 0x6:
1525 case REX_P + 0x7:
1526 case REX_P + 0x8:
1527 case REX_P + 0x9:
1528 case REX_P + 0xA:
1529 case REX_P + 0xB:
1530 case REX_P + 0xC:
1531 case REX_P + 0xD:
1532 case REX_P + 0xE:
1533 case REX_P + 0xF:
1534 if (segsize == 64) {
1535 snprintf(output, outbufsize, "rex%s%s%s%s%s",
1536 (byte == REX_P) ? "" : ".",
1537 (byte & REX_W) ? "w" : "",
1538 (byte & REX_R) ? "r" : "",
1539 (byte & REX_X) ? "x" : "",
1540 (byte & REX_B) ? "b" : "");
1541 break;
1542 }
1543 /* else fall through */
1544 default:
1545 snprintf(output, outbufsize, "db 0x%02x", byte);
1546 break;
1547 }
1548
1549 if (str)
1550 snprintf(output, outbufsize, "%s", str);
1551
1552 return 1;
1553 }
Netwide Assembler - Mirror