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Fix op2 references that had not yet been converted; introduce opy
[nasm/perl-rewrite.git] / disasm.c
blob0c654edec28dfcc4fa626ddd4a9bdedf382fd1c4
1 /* disasm.c where all the _work_ gets done in the Netwide Disassembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
7 *
8 * initial version 27/iii/95 by Simon Tatham
9 */
10
11 #include "compiler.h"
12
13 #include <stdio.h>
14 #include <string.h>
15 #include <limits.h>
16 #include <inttypes.h>
17
18 #include "nasm.h"
19 #include "disasm.h"
20 #include "sync.h"
21 #include "insns.h"
22 #include "tables.h"
23 #include "regdis.h"
24
25 /*
26 * Flags that go into the `segment' field of `insn' structures
27 * during disassembly.
28 */
29 #define SEG_RELATIVE 1
30 #define SEG_32BIT 2
31 #define SEG_RMREG 4
32 #define SEG_DISP8 8
33 #define SEG_DISP16 16
34 #define SEG_DISP32 32
35 #define SEG_NODISP 64
36 #define SEG_SIGNED 128
37 #define SEG_64BIT 256
38
39 /*
40 * Prefix information
41 */
42 struct prefix_info {
43 uint8_t osize; /* Operand size */
44 uint8_t asize; /* Address size */
45 uint8_t osp; /* Operand size prefix present */
46 uint8_t asp; /* Address size prefix present */
47 uint8_t rep; /* Rep prefix present */
48 uint8_t seg; /* Segment override prefix present */
49 uint8_t lock; /* Lock prefix present */
50 uint8_t vex[3]; /* VEX prefix present */
51 uint8_t vex_m; /* VEX.M field */
52 uint8_t vex_v;
53 uint8_t vex_lp; /* VEX.LP fields */
54 uint32_t rex; /* REX prefix present */
55 };
56
57 #define getu8(x) (*(uint8_t *)(x))
58 #if X86_MEMORY
59 /* Littleendian CPU which can handle unaligned references */
60 #define getu16(x) (*(uint16_t *)(x))
61 #define getu32(x) (*(uint32_t *)(x))
62 #define getu64(x) (*(uint64_t *)(x))
63 #else
64 static uint16_t getu16(uint8_t *data)
65 {
66 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
67 }
68 static uint32_t getu32(uint8_t *data)
69 {
70 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
71 }
72 static uint64_t getu64(uint8_t *data)
73 {
74 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
75 }
76 #endif
77
78 #define gets8(x) ((int8_t)getu8(x))
79 #define gets16(x) ((int16_t)getu16(x))
80 #define gets32(x) ((int32_t)getu32(x))
81 #define gets64(x) ((int64_t)getu64(x))
82
83 /* Important: regval must already have been adjusted for rex extensions */
84 static enum reg_enum whichreg(int32_t regflags, int regval, int rex)
85 {
86 if (!(regflags & (REGISTER|REGMEM)))
87 return 0; /* Registers not permissible?! */
88
89 regflags |= REGISTER;
90
91 if (!(REG_AL & ~regflags))
92 return R_AL;
93 if (!(REG_AX & ~regflags))
94 return R_AX;
95 if (!(REG_EAX & ~regflags))
96 return R_EAX;
97 if (!(REG_RAX & ~regflags))
98 return R_RAX;
99 if (!(REG_DL & ~regflags))
100 return R_DL;
101 if (!(REG_DX & ~regflags))
102 return R_DX;
103 if (!(REG_EDX & ~regflags))
104 return R_EDX;
105 if (!(REG_RDX & ~regflags))
106 return R_RDX;
107 if (!(REG_CL & ~regflags))
108 return R_CL;
109 if (!(REG_CX & ~regflags))
110 return R_CX;
111 if (!(REG_ECX & ~regflags))
112 return R_ECX;
113 if (!(REG_RCX & ~regflags))
114 return R_RCX;
115 if (!(FPU0 & ~regflags))
116 return R_ST0;
117 if (!(XMM0 & ~regflags))
118 return R_XMM0;
119 if (!(YMM0 & ~regflags))
120 return R_YMM0;
121 if (!(REG_CS & ~regflags))
122 return (regval == 1) ? R_CS : 0;
123 if (!(REG_DESS & ~regflags))
124 return (regval == 0 || regval == 2
125 || regval == 3 ? nasm_rd_sreg[regval] : 0);
126 if (!(REG_FSGS & ~regflags))
127 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
128 if (!(REG_SEG67 & ~regflags))
129 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
130
131 /* All the entries below look up regval in an 16-entry array */
132 if (regval < 0 || regval > 15)
133 return 0;
134
135 if (!(REG8 & ~regflags)) {
136 if (rex & REX_P)
137 return nasm_rd_reg8_rex[regval];
138 else
139 return nasm_rd_reg8[regval];
140 }
141 if (!(REG16 & ~regflags))
142 return nasm_rd_reg16[regval];
143 if (!(REG32 & ~regflags))
144 return nasm_rd_reg32[regval];
145 if (!(REG64 & ~regflags))
146 return nasm_rd_reg64[regval];
147 if (!(REG_SREG & ~regflags))
148 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
149 if (!(REG_CREG & ~regflags))
150 return nasm_rd_creg[regval];
151 if (!(REG_DREG & ~regflags))
152 return nasm_rd_dreg[regval];
153 if (!(REG_TREG & ~regflags)) {
154 if (rex & REX_P)
155 return 0; /* TR registers are ill-defined with rex */
156 return nasm_rd_treg[regval];
157 }
158 if (!(FPUREG & ~regflags))
159 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
160 if (!(MMXREG & ~regflags))
161 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
162 if (!(XMMREG & ~regflags))
163 return nasm_rd_xmmreg[regval];
164 if (!(YMMREG & ~regflags))
165 return nasm_rd_ymmreg[regval];
166
167 return 0;
168 }
169
170 /*
171 * Process a DREX suffix
172 */
173 static uint8_t *do_drex(uint8_t *data, insn *ins)
174 {
175 uint8_t drex = *data++;
176 operand *dst = &ins->oprs[ins->drexdst];
177
178 if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
179 return NULL; /* OC0 mismatch */
180 ins->rex = (ins->rex & ~7) | (drex & 7);
181
182 dst->segment = SEG_RMREG;
183 dst->basereg = drex >> 4;
184 return data;
185 }
186
187
188 /*
189 * Process an effective address (ModRM) specification.
190 */
191 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
192 int segsize, operand * op, insn *ins)
193 {
194 int mod, rm, scale, index, base;
195 int rex;
196 uint8_t sib = 0;
197
198 mod = (modrm >> 6) & 03;
199 rm = modrm & 07;
200
201 if (mod != 3 && rm == 4 && asize != 16)
202 sib = *data++;
203
204 if (ins->rex & REX_D) {
205 data = do_drex(data, ins);
206 if (!data)
207 return NULL;
208 }
209 rex = ins->rex;
210
211 if (mod == 3) { /* pure register version */
212 op->basereg = rm+(rex & REX_B ? 8 : 0);
213 op->segment |= SEG_RMREG;
214 return data;
215 }
216
217 op->disp_size = 0;
218 op->eaflags = 0;
219
220 if (asize == 16) {
221 /*
222 * <mod> specifies the displacement size (none, byte or
223 * word), and <rm> specifies the register combination.
224 * Exception: mod=0,rm=6 does not specify [BP] as one might
225 * expect, but instead specifies [disp16].
226 */
227 op->indexreg = op->basereg = -1;
228 op->scale = 1; /* always, in 16 bits */
229 switch (rm) {
230 case 0:
231 op->basereg = R_BX;
232 op->indexreg = R_SI;
233 break;
234 case 1:
235 op->basereg = R_BX;
236 op->indexreg = R_DI;
237 break;
238 case 2:
239 op->basereg = R_BP;
240 op->indexreg = R_SI;
241 break;
242 case 3:
243 op->basereg = R_BP;
244 op->indexreg = R_DI;
245 break;
246 case 4:
247 op->basereg = R_SI;
248 break;
249 case 5:
250 op->basereg = R_DI;
251 break;
252 case 6:
253 op->basereg = R_BP;
254 break;
255 case 7:
256 op->basereg = R_BX;
257 break;
258 }
259 if (rm == 6 && mod == 0) { /* special case */
260 op->basereg = -1;
261 if (segsize != 16)
262 op->disp_size = 16;
263 mod = 2; /* fake disp16 */
264 }
265 switch (mod) {
266 case 0:
267 op->segment |= SEG_NODISP;
268 break;
269 case 1:
270 op->segment |= SEG_DISP8;
271 op->offset = (int8_t)*data++;
272 break;
273 case 2:
274 op->segment |= SEG_DISP16;
275 op->offset = *data++;
276 op->offset |= ((unsigned)*data++) << 8;
277 break;
278 }
279 return data;
280 } else {
281 /*
282 * Once again, <mod> specifies displacement size (this time
283 * none, byte or *dword*), while <rm> specifies the base
284 * register. Again, [EBP] is missing, replaced by a pure
285 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
286 * and RIP-relative addressing in 64-bit mode.
287 *
288 * However, rm=4
289 * indicates not a single base register, but instead the
290 * presence of a SIB byte...
291 */
292 int a64 = asize == 64;
293
294 op->indexreg = -1;
295
296 if (a64)
297 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
298 else
299 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
300
301 if (rm == 5 && mod == 0) {
302 if (segsize == 64) {
303 op->eaflags |= EAF_REL;
304 op->segment |= SEG_RELATIVE;
305 mod = 2; /* fake disp32 */
306 }
307
308 if (asize != 64)
309 op->disp_size = asize;
310
311 op->basereg = -1;
312 mod = 2; /* fake disp32 */
313 }
314
315 if (rm == 4) { /* process SIB */
316 scale = (sib >> 6) & 03;
317 index = (sib >> 3) & 07;
318 base = sib & 07;
319
320 op->scale = 1 << scale;
321
322 if (index == 4 && !(rex & REX_X))
323 op->indexreg = -1; /* ESP/RSP cannot be an index */
324 else if (a64)
325 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
326 else
327 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
328
329 if (base == 5 && mod == 0) {
330 op->basereg = -1;
331 mod = 2; /* Fake disp32 */
332 } else if (a64)
333 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
334 else
335 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
336
337 if (segsize == 16)
338 op->disp_size = 32;
339 }
340
341 switch (mod) {
342 case 0:
343 op->segment |= SEG_NODISP;
344 break;
345 case 1:
346 op->segment |= SEG_DISP8;
347 op->offset = gets8(data);
348 data++;
349 break;
350 case 2:
351 op->segment |= SEG_DISP32;
352 op->offset = gets32(data);
353 data += 4;
354 break;
355 }
356 return data;
357 }
358 }
359
360 /*
361 * Determine whether the instruction template in t corresponds to the data
362 * stream in data. Return the number of bytes matched if so.
363 */
364 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
365
366 static int matches(const struct itemplate *t, uint8_t *data,
367 const struct prefix_info *prefix, int segsize, insn *ins)
368 {
369 uint8_t *r = (uint8_t *)(t->code);
370 uint8_t *origdata = data;
371 bool a_used = false, o_used = false;
372 enum prefixes drep = 0;
373 uint8_t lock = prefix->lock;
374 int osize = prefix->osize;
375 int asize = prefix->asize;
376 int i, c;
377 int op1, op2;
378 struct operand *opx;
379 uint8_t opex = 0;
380 int s_field_for = -1; /* No 144/154 series code encountered */
381 bool vex_ok = false;
382 int regmask = (segsize == 64) ? 15 : 7;
383
384 for (i = 0; i < MAX_OPERANDS; i++) {
385 ins->oprs[i].segment = ins->oprs[i].disp_size =
386 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
387 }
388 ins->condition = -1;
389 ins->rex = prefix->rex;
390 memset(ins->prefixes, 0, sizeof ins->prefixes);
391
392 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
393 return false;
394
395 if (prefix->rep == 0xF2)
396 drep = P_REPNE;
397 else if (prefix->rep == 0xF3)
398 drep = P_REP;
399
400 while ((c = *r++) != 0) {
401 op1 = (c & 3) + ((opex & 1) << 2);
402 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
403 opx = &ins->oprs[op1];
404 opex = 0;
405
406 switch (c) {
407 case 01:
408 case 02:
409 case 03:
410 case 04:
411 while (c--)
412 if (*r++ != *data++)
413 return false;
414 break;
415
416 case 05:
417 case 06:
418 case 07:
419 opex = c;
420 break;
421
422 case4(010):
423 {
424 int t = *r++, d = *data++;
425 if (d < t || d > t + 7)
426 return false;
427 else {
428 opx->basereg = (d-t)+
429 (ins->rex & REX_B ? 8 : 0);
430 opx->segment |= SEG_RMREG;
431 }
432 break;
433 }
434
435 case4(014):
436 case4(0274):
437 opx->offset = (int8_t)*data++;
438 opx->segment |= SEG_SIGNED;
439 break;
440
441 case4(020):
442 opx->offset = *data++;
443 break;
444
445 case4(024):
446 opx->offset = *data++;
447 break;
448
449 case4(030):
450 opx->offset = getu16(data);
451 data += 2;
452 break;
453
454 case4(034):
455 if (osize == 32) {
456 opx->offset = getu32(data);
457 data += 4;
458 } else {
459 opx->offset = getu16(data);
460 data += 2;
461 }
462 if (segsize != asize)
463 opx->disp_size = asize;
464 break;
465
466 case4(040):
467 case4(0254):
468 opx->offset = getu32(data);
469 data += 4;
470 break;
471
472 case4(044):
473 switch (asize) {
474 case 16:
475 opx->offset = getu16(data);
476 data += 2;
477 if (segsize != 16)
478 opx->disp_size = 16;
479 break;
480 case 32:
481 opx->offset = getu32(data);
482 data += 4;
483 if (segsize == 16)
484 opx->disp_size = 32;
485 break;
486 case 64:
487 opx->offset = getu64(data);
488 opx->disp_size = 64;
489 data += 8;
490 break;
491 }
492 break;
493
494 case4(050):
495 opx->offset = gets8(data++);
496 opx->segment |= SEG_RELATIVE;
497 break;
498
499 case4(054):
500 opx->offset = getu64(data);
501 data += 8;
502 break;
503
504 case4(060):
505 opx->offset = gets16(data);
506 data += 2;
507 opx->segment |= SEG_RELATIVE;
508 opx->segment &= ~SEG_32BIT;
509 break;
510
511 case4(064):
512 opx->segment |= SEG_RELATIVE;
513 if (osize == 16) {
514 opx->offset = gets16(data);
515 data += 2;
516 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
517 } else if (osize == 32) {
518 opx->offset = gets32(data);
519 data += 4;
520 opx->segment &= ~SEG_64BIT;
521 opx->segment |= SEG_32BIT;
522 }
523 if (segsize != osize) {
524 opx->type =
525 (opx->type & ~SIZE_MASK)
526 | ((osize == 16) ? BITS16 : BITS32);
527 }
528 break;
529
530 case4(070):
531 opx->offset = gets32(data);
532 data += 4;
533 opx->segment |= SEG_32BIT | SEG_RELATIVE;
534 break;
535
536 case4(0100):
537 case4(0110):
538 case4(0120):
539 case4(0130):
540 {
541 int modrm = *data++;
542 opx->segment |= SEG_RMREG;
543 data = do_ea(data, modrm, asize, segsize, &ins->oprs[op2], ins);
544 if (!data)
545 return false;
546 opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0);
547 break;
548 }
549
550 case4(0140):
551 if (s_field_for == op1) {
552 opx->offset = gets8(data);
553 data++;
554 } else {
555 opx->offset = getu16(data);
556 data += 2;
557 }
558 break;
559
560 case4(0144):
561 case4(0154):
562 s_field_for = (*data & 0x02) ? op1 : -1;
563 if ((*data++ & ~0x02) != *r++)
564 return false;
565 break;
566
567 case4(0150):
568 if (s_field_for == op1) {
569 opx->offset = gets8(data);
570 data++;
571 } else {
572 opx->offset = getu32(data);
573 data += 4;
574 }
575 break;
576
577 case4(0160):
578 ins->rex |= REX_D;
579 ins->drexdst = op1;
580 break;
581
582 case4(0164):
583 ins->rex |= REX_D|REX_OC;
584 ins->drexdst = op1;
585 break;
586
587 case 0171:
588 data = do_drex(data, ins);
589 if (!data)
590 return false;
591 break;
592
593 case 0172:
594 {
595 uint8_t ximm = *data++;
596 c = *r++;
597 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
598 ins->oprs[c >> 3].segment |= SEG_RMREG;
599 ins->oprs[c & 7].offset = ximm & 15;
600 }
601 break;
602
603 case 0173:
604 {
605 uint8_t ximm = *data++;
606 c = *r++;
607
608 if ((c ^ ximm) & 15)
609 return false;
610
611 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
612 ins->oprs[c >> 4].segment |= SEG_RMREG;
613 }
614 break;
615
616 case 0174:
617 {
618 uint8_t ximm = *data++;
619 c = *r++;
620
621 ins->oprs[c].basereg = (ximm >> 4) & regmask;
622 ins->oprs[c].segment |= SEG_RMREG;
623 }
624 break;
625
626 case4(0200):
627 case4(0204):
628 case4(0210):
629 case4(0214):
630 case4(0220):
631 case4(0224):
632 case4(0230):
633 case4(0234):
634 {
635 int modrm = *data++;
636 if (((modrm >> 3) & 07) != (c & 07))
637 return false; /* spare field doesn't match up */
638 data = do_ea(data, modrm, asize, segsize, &ins->oprs[op2], ins);
639 if (!data)
640 return false;
641 break;
642 }
643
644 case4(0260):
645 {
646 int vexm = *r++;
647 int vexwlp = *r++;
648 ins->rex |= REX_V;
649 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
650 return false;
651
652 if ((vexm & 0x1f) != prefix->vex_m)
653 return false;
654
655 switch (vexwlp & 030) {
656 case 000:
657 if (prefix->rex & REX_W)
658 return false;
659 break;
660 case 010:
661 if (!(prefix->rex & REX_W))
662 return false;
663 ins->rex &= ~REX_W;
664 break;
665 case 020: /* VEX.W is a don't care */
666 ins->rex &= ~REX_W;
667 break;
668 case 030:
669 break;
670 }
671
672 if ((vexwlp & 007) != prefix->vex_lp)
673 return false;
674
675 opx->segment |= SEG_RMREG;
676 opx->basereg = prefix->vex_v;
677 vex_ok = true;
678 break;
679 }
680
681 case 0270:
682 {
683 int vexm = *r++;
684 int vexwlp = *r++;
685 ins->rex |= REX_V;
686 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
687 return false;
688
689 if ((vexm & 0x1f) != prefix->vex_m)
690 return false;
691
692 switch (vexwlp & 030) {
693 case 000:
694 if (ins->rex & REX_W)
695 return false;
696 break;
697 case 010:
698 if (!(ins->rex & REX_W))
699 return false;
700 break;
701 default:
702 break; /* Need to do anything special here? */
703 }
704
705 if ((vexwlp & 007) != prefix->vex_lp)
706 return false;
707
708 if (prefix->vex_v != 0)
709 return false;
710
711 vex_ok = true;
712 break;
713 }
714
715 case 0310:
716 if (asize != 16)
717 return false;
718 else
719 a_used = true;
720 break;
721
722 case 0311:
723 if (asize == 16)
724 return false;
725 else
726 a_used = true;
727 break;
728
729 case 0312:
730 if (asize != segsize)
731 return false;
732 else
733 a_used = true;
734 break;
735
736 case 0313:
737 if (asize != 64)
738 return false;
739 else
740 a_used = true;
741 break;
742
743 case 0314:
744 if (prefix->rex & REX_B)
745 return false;
746 break;
747
748 case 0315:
749 if (prefix->rex & REX_X)
750 return false;
751 break;
752
753 case 0316:
754 if (prefix->rex & REX_R)
755 return false;
756 break;
757
758 case 0317:
759 if (prefix->rex & REX_W)
760 return false;
761 break;
762
763 case 0320:
764 if (osize != 16)
765 return false;
766 else
767 o_used = true;
768 break;
769
770 case 0321:
771 if (osize != 32)
772 return false;
773 else
774 o_used = true;
775 break;
776
777 case 0322:
778 if (osize != (segsize == 16) ? 16 : 32)
779 return false;
780 else
781 o_used = true;
782 break;
783
784 case 0323:
785 ins->rex |= REX_W; /* 64-bit only instruction */
786 osize = 64;
787 o_used = true;
788 break;
789
790 case 0324:
791 if (!(ins->rex & (REX_P|REX_W)) || osize != 64)
792 return false;
793 o_used = true;
794 break;
795
796 case 0330:
797 {
798 int t = *r++, d = *data++;
799 if (d < t || d > t + 15)
800 return false;
801 else
802 ins->condition = d - t;
803 break;
804 }
805
806 case 0331:
807 if (prefix->rep)
808 return false;
809 break;
810
811 case 0332:
812 if (prefix->rep != 0xF2)
813 return false;
814 drep = 0;
815 break;
816
817 case 0333:
818 if (prefix->rep != 0xF3)
819 return false;
820 drep = 0;
821 break;
822
823 case 0334:
824 if (lock) {
825 ins->rex |= REX_R;
826 lock = 0;
827 }
828 break;
829
830 case 0335:
831 if (drep == P_REP)
832 drep = P_REPE;
833 break;
834
835 case 0336:
836 case 0337:
837 break;
838
839 case 0340:
840 return false;
841
842 case4(0344):
843 ins->oprs[0].basereg = (*data++ >> 3) & 7;
844 break;
845
846 case 0360:
847 if (prefix->osp || prefix->rep)
848 return false;
849 break;
850
851 case 0361:
852 if (!prefix->osp || prefix->rep)
853 return false;
854 o_used = true;
855 break;
856
857 case 0362:
858 if (prefix->osp || prefix->rep != 0xf2)
859 return false;
860 drep = 0;
861 break;
862
863 case 0363:
864 if (prefix->osp || prefix->rep != 0xf3)
865 return false;
866 drep = 0;
867 break;
868
869 case 0364:
870 if (prefix->osp)
871 return false;
872 break;
873
874 case 0365:
875 if (prefix->asp)
876 return false;
877 break;
878
879 case 0366:
880 if (!prefix->osp)
881 return false;
882 o_used = true;
883 break;
884
885 case 0367:
886 if (!prefix->asp)
887 return false;
888 a_used = true;
889 break;
890
891 default:
892 return false; /* Unknown code */
893 }
894 }
895
896 if (!vex_ok && (ins->rex & REX_V))
897 return false;
898
899 /* REX cannot be combined with DREX or VEX */
900 if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
901 return false;
902
903 /*
904 * Check for unused rep or a/o prefixes.
905 */
906 for (i = 0; i < t->operands; i++) {
907 if (ins->oprs[i].segment != SEG_RMREG)
908 a_used = true;
909 }
910
911 if (lock) {
912 if (ins->prefixes[PPS_LREP])
913 return false;
914 ins->prefixes[PPS_LREP] = P_LOCK;
915 }
916 if (drep) {
917 if (ins->prefixes[PPS_LREP])
918 return false;
919 ins->prefixes[PPS_LREP] = drep;
920 }
921 if (!o_used) {
922 if (osize != ((segsize == 16) ? 16 : 32)) {
923 enum prefixes pfx = 0;
924
925 switch (osize) {
926 case 16:
927 pfx = P_O16;
928 break;
929 case 32:
930 pfx = P_O32;
931 break;
932 case 64:
933 pfx = P_O64;
934 break;
935 }
936
937 if (ins->prefixes[PPS_OSIZE])
938 return false;
939 ins->prefixes[PPS_OSIZE] = pfx;
940 }
941 }
942 if (!a_used && asize != segsize) {
943 if (ins->prefixes[PPS_ASIZE])
944 return false;
945 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
946 }
947
948 /* Fix: check for redundant REX prefixes */
949
950 return data - origdata;
951 }
952
953 /* Condition names for disassembly, sorted by x86 code */
954 static const char * const condition_name[16] = {
955 "o", "no", "c", "nc", "z", "nz", "na", "a",
956 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
957 };
958
959 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
960 int32_t offset, int autosync, uint32_t prefer)
961 {
962 const struct itemplate * const *p, * const *best_p;
963 const struct disasm_index *ix;
964 uint8_t *dp;
965 int length, best_length = 0;
966 char *segover;
967 int i, slen, colon, n;
968 uint8_t *origdata;
969 int works;
970 insn tmp_ins, ins;
971 uint32_t goodness, best;
972 int best_pref;
973 struct prefix_info prefix;
974 bool end_prefix;
975
976 memset(&ins, 0, sizeof ins);
977
978 /*
979 * Scan for prefixes.
980 */
981 memset(&prefix, 0, sizeof prefix);
982 prefix.asize = segsize;
983 prefix.osize = (segsize == 64) ? 32 : segsize;
984 segover = NULL;
985 origdata = data;
986
987 ix = itable;
988
989 end_prefix = false;
990 while (!end_prefix) {
991 switch (*data) {
992 case 0xF2:
993 case 0xF3:
994 prefix.rep = *data++;
995 break;
996
997 case 0xF0:
998 prefix.lock = *data++;
999 break;
1000
1001 case 0x2E:
1002 segover = "cs", prefix.seg = *data++;
1003 break;
1004 case 0x36:
1005 segover = "ss", prefix.seg = *data++;
1006 break;
1007 case 0x3E:
1008 segover = "ds", prefix.seg = *data++;
1009 break;
1010 case 0x26:
1011 segover = "es", prefix.seg = *data++;
1012 break;
1013 case 0x64:
1014 segover = "fs", prefix.seg = *data++;
1015 break;
1016 case 0x65:
1017 segover = "gs", prefix.seg = *data++;
1018 break;
1019
1020 case 0x66:
1021 prefix.osize = (segsize == 16) ? 32 : 16;
1022 prefix.osp = *data++;
1023 break;
1024 case 0x67:
1025 prefix.asize = (segsize == 32) ? 16 : 32;
1026 prefix.asp = *data++;
1027 break;
1028
1029 case 0xC4:
1030 case 0xC5:
1031 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1032 prefix.vex[0] = *data++;
1033 prefix.vex[1] = *data++;
1034
1035 prefix.rex = REX_V;
1036
1037 if (prefix.vex[0] == 0xc4) {
1038 prefix.vex[2] = *data++;
1039 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1040 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1041 prefix.vex_m = prefix.vex[1] & 0x1f;
1042 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1043 prefix.vex_lp = prefix.vex[2] & 7;
1044 } else {
1045 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1046 prefix.vex_m = 1;
1047 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1048 prefix.vex_lp = prefix.vex[1] & 7;
1049 }
1050
1051 ix = itable_VEX[prefix.vex_m][prefix.vex_lp];
1052 }
1053 end_prefix = true;
1054 break;
1055
1056 case REX_P + 0x0:
1057 case REX_P + 0x1:
1058 case REX_P + 0x2:
1059 case REX_P + 0x3:
1060 case REX_P + 0x4:
1061 case REX_P + 0x5:
1062 case REX_P + 0x6:
1063 case REX_P + 0x7:
1064 case REX_P + 0x8:
1065 case REX_P + 0x9:
1066 case REX_P + 0xA:
1067 case REX_P + 0xB:
1068 case REX_P + 0xC:
1069 case REX_P + 0xD:
1070 case REX_P + 0xE:
1071 case REX_P + 0xF:
1072 if (segsize == 64) {
1073 prefix.rex = *data++;
1074 if (prefix.rex & REX_W)
1075 prefix.osize = 64;
1076 }
1077 end_prefix = true;
1078 break;
1079
1080 default:
1081 end_prefix = true;
1082 break;
1083 }
1084 }
1085
1086 best = -1; /* Worst possible */
1087 best_p = NULL;
1088 best_pref = INT_MAX;
1089
1090 if (!ix)
1091 return 0; /* No instruction table at all... */
1092
1093 dp = data;
1094 ix += *dp++;
1095 while (ix->n == -1) {
1096 ix = (const struct disasm_index *)ix->p + *dp++;
1097 }
1098
1099 p = (const struct itemplate * const *)ix->p;
1100 for (n = ix->n; n; n--, p++) {
1101 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1102 works = true;
1103 /*
1104 * Final check to make sure the types of r/m match up.
1105 * XXX: Need to make sure this is actually correct.
1106 */
1107 for (i = 0; i < (*p)->operands; i++) {
1108 if (!((*p)->opd[i] & SAME_AS) &&
1109 (
1110 /* If it's a mem-only EA but we have a
1111 register, die. */
1112 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1113 !(MEMORY & ~(*p)->opd[i])) ||
1114 /* If it's a reg-only EA but we have a memory
1115 ref, die. */
1116 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1117 !(REG_EA & ~(*p)->opd[i]) &&
1118 !((*p)->opd[i] & REG_SMASK)) ||
1119 /* Register type mismatch (eg FS vs REG_DESS):
1120 die. */
1121 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1122 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1123 !whichreg((*p)->opd[i],
1124 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1125 )) {
1126 works = false;
1127 break;
1128 }
1129 }
1130
1131 /*
1132 * Note: we always prefer instructions which incorporate
1133 * prefixes in the instructions themselves. This is to allow
1134 * e.g. PAUSE to be preferred to REP NOP, and deal with
1135 * MMX/SSE instructions where prefixes are used to select
1136 * between MMX and SSE register sets or outright opcode
1137 * selection.
1138 */
1139 if (works) {
1140 int i, nprefix;
1141 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1142 nprefix = 0;
1143 for (i = 0; i < MAXPREFIX; i++)
1144 if (tmp_ins.prefixes[i])
1145 nprefix++;
1146 if (nprefix < best_pref ||
1147 (nprefix == best_pref && goodness < best)) {
1148 /* This is the best one found so far */
1149 best = goodness;
1150 best_p = p;
1151 best_pref = nprefix;
1152 best_length = length;
1153 ins = tmp_ins;
1154 }
1155 }
1156 }
1157 }
1158
1159 if (!best_p)
1160 return 0; /* no instruction was matched */
1161
1162 /* Pick the best match */
1163 p = best_p;
1164 length = best_length;
1165
1166 slen = 0;
1167
1168 /* TODO: snprintf returns the value that the string would have if
1169 * the buffer were long enough, and not the actual length of
1170 * the returned string, so each instance of using the return
1171 * value of snprintf should actually be checked to assure that
1172 * the return value is "sane." Maybe a macro wrapper could
1173 * be used for that purpose.
1174 */
1175 for (i = 0; i < MAXPREFIX; i++)
1176 switch (ins.prefixes[i]) {
1177 case P_LOCK:
1178 slen += snprintf(output + slen, outbufsize - slen, "lock ");
1179 break;
1180 case P_REP:
1181 slen += snprintf(output + slen, outbufsize - slen, "rep ");
1182 break;
1183 case P_REPE:
1184 slen += snprintf(output + slen, outbufsize - slen, "repe ");
1185 break;
1186 case P_REPNE:
1187 slen += snprintf(output + slen, outbufsize - slen, "repne ");
1188 break;
1189 case P_A16:
1190 slen += snprintf(output + slen, outbufsize - slen, "a16 ");
1191 break;
1192 case P_A32:
1193 slen += snprintf(output + slen, outbufsize - slen, "a32 ");
1194 break;
1195 case P_A64:
1196 slen += snprintf(output + slen, outbufsize - slen, "a64 ");
1197 break;
1198 case P_O16:
1199 slen += snprintf(output + slen, outbufsize - slen, "o16 ");
1200 break;
1201 case P_O32:
1202 slen += snprintf(output + slen, outbufsize - slen, "o32 ");
1203 break;
1204 case P_O64:
1205 slen += snprintf(output + slen, outbufsize - slen, "o64 ");
1206 break;
1207 default:
1208 break;
1209 }
1210
1211 i = (*p)->opcode;
1212 if (i >= FIRST_COND_OPCODE)
1213 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1214 nasm_insn_names[i], condition_name[ins.condition]);
1215 else
1216 slen += snprintf(output + slen, outbufsize - slen, "%s",
1217 nasm_insn_names[i]);
1218
1219 colon = false;
1220 length += data - origdata; /* fix up for prefixes */
1221 for (i = 0; i < (*p)->operands; i++) {
1222 opflags_t t = (*p)->opd[i];
1223 const operand *o = &ins.oprs[i];
1224 int64_t offs;
1225
1226 if (t & SAME_AS) {
1227 o = &ins.oprs[t & ~SAME_AS];
1228 t = (*p)->opd[t & ~SAME_AS];
1229 }
1230
1231 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1232
1233 offs = o->offset;
1234 if (o->segment & SEG_RELATIVE) {
1235 offs += offset + length;
1236 /*
1237 * sort out wraparound
1238 */
1239 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1240 offs &= 0xffff;
1241 else if (segsize != 64)
1242 offs &= 0xffffffff;
1243
1244 /*
1245 * add sync marker, if autosync is on
1246 */
1247 if (autosync)
1248 add_sync(offs, 0L);
1249 }
1250
1251 if (t & COLON)
1252 colon = true;
1253 else
1254 colon = false;
1255
1256 if ((t & (REGISTER | FPUREG)) ||
1257 (o->segment & SEG_RMREG)) {
1258 enum reg_enum reg;
1259 reg = whichreg(t, o->basereg, ins.rex);
1260 if (t & TO)
1261 slen += snprintf(output + slen, outbufsize - slen, "to ");
1262 slen += snprintf(output + slen, outbufsize - slen, "%s",
1263 nasm_reg_names[reg-EXPR_REG_START]);
1264 } else if (!(UNITY & ~t)) {
1265 output[slen++] = '1';
1266 } else if (t & IMMEDIATE) {
1267 if (t & BITS8) {
1268 slen +=
1269 snprintf(output + slen, outbufsize - slen, "byte ");
1270 if (o->segment & SEG_SIGNED) {
1271 if (offs < 0) {
1272 offs *= -1;
1273 output[slen++] = '-';
1274 } else
1275 output[slen++] = '+';
1276 }
1277 } else if (t & BITS16) {
1278 slen +=
1279 snprintf(output + slen, outbufsize - slen, "word ");
1280 } else if (t & BITS32) {
1281 slen +=
1282 snprintf(output + slen, outbufsize - slen, "dword ");
1283 } else if (t & BITS64) {
1284 slen +=
1285 snprintf(output + slen, outbufsize - slen, "qword ");
1286 } else if (t & NEAR) {
1287 slen +=
1288 snprintf(output + slen, outbufsize - slen, "near ");
1289 } else if (t & SHORT) {
1290 slen +=
1291 snprintf(output + slen, outbufsize - slen, "short ");
1292 }
1293 slen +=
1294 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1295 offs);
1296 } else if (!(MEM_OFFS & ~t)) {
1297 slen +=
1298 snprintf(output + slen, outbufsize - slen,
1299 "[%s%s%s0x%"PRIx64"]",
1300 (segover ? segover : ""),
1301 (segover ? ":" : ""),
1302 (o->disp_size == 64 ? "qword " :
1303 o->disp_size == 32 ? "dword " :
1304 o->disp_size == 16 ? "word " : ""), offs);
1305 segover = NULL;
1306 } else if (!(REGMEM & ~t)) {
1307 int started = false;
1308 if (t & BITS8)
1309 slen +=
1310 snprintf(output + slen, outbufsize - slen, "byte ");
1311 if (t & BITS16)
1312 slen +=
1313 snprintf(output + slen, outbufsize - slen, "word ");
1314 if (t & BITS32)
1315 slen +=
1316 snprintf(output + slen, outbufsize - slen, "dword ");
1317 if (t & BITS64)
1318 slen +=
1319 snprintf(output + slen, outbufsize - slen, "qword ");
1320 if (t & BITS80)
1321 slen +=
1322 snprintf(output + slen, outbufsize - slen, "tword ");
1323 if (t & BITS128)
1324 slen +=
1325 snprintf(output + slen, outbufsize - slen, "oword ");
1326 if (t & BITS256)
1327 slen +=
1328 snprintf(output + slen, outbufsize - slen, "yword ");
1329 if (t & FAR)
1330 slen += snprintf(output + slen, outbufsize - slen, "far ");
1331 if (t & NEAR)
1332 slen +=
1333 snprintf(output + slen, outbufsize - slen, "near ");
1334 output[slen++] = '[';
1335 if (o->disp_size)
1336 slen += snprintf(output + slen, outbufsize - slen, "%s",
1337 (o->disp_size == 64 ? "qword " :
1338 o->disp_size == 32 ? "dword " :
1339 o->disp_size == 16 ? "word " :
1340 ""));
1341 if (o->eaflags & EAF_REL)
1342 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1343 if (segover) {
1344 slen +=
1345 snprintf(output + slen, outbufsize - slen, "%s:",
1346 segover);
1347 segover = NULL;
1348 }
1349 if (o->basereg != -1) {
1350 slen += snprintf(output + slen, outbufsize - slen, "%s",
1351 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1352 started = true;
1353 }
1354 if (o->indexreg != -1) {
1355 if (started)
1356 output[slen++] = '+';
1357 slen += snprintf(output + slen, outbufsize - slen, "%s",
1358 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1359 if (o->scale > 1)
1360 slen +=
1361 snprintf(output + slen, outbufsize - slen, "*%d",
1362 o->scale);
1363 started = true;
1364 }
1365
1366
1367 if (o->segment & SEG_DISP8) {
1368 const char *prefix;
1369 uint8_t offset = offs;
1370 if ((int8_t)offset < 0) {
1371 prefix = "-";
1372 offset = -offset;
1373 } else {
1374 prefix = "+";
1375 }
1376 slen +=
1377 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1378 prefix, offset);
1379 } else if (o->segment & SEG_DISP16) {
1380 const char *prefix;
1381 uint16_t offset = offs;
1382 if ((int16_t)offset < 0 && started) {
1383 offset = -offset;
1384 prefix = "-";
1385 } else {
1386 prefix = started ? "+" : "";
1387 }
1388 slen +=
1389 snprintf(output + slen, outbufsize - slen,
1390 "%s0x%"PRIx16"", prefix, offset);
1391 } else if (o->segment & SEG_DISP32) {
1392 if (prefix.asize == 64) {
1393 const char *prefix;
1394 uint64_t offset = (int64_t)(int32_t)offs;
1395 if ((int32_t)offs < 0 && started) {
1396 offset = -offset;
1397 prefix = "-";
1398 } else {
1399 prefix = started ? "+" : "";
1400 }
1401 slen +=
1402 snprintf(output + slen, outbufsize - slen,
1403 "%s0x%"PRIx64"", prefix, offset);
1404 } else {
1405 const char *prefix;
1406 uint32_t offset = offs;
1407 if ((int32_t) offset < 0 && started) {
1408 offset = -offset;
1409 prefix = "-";
1410 } else {
1411 prefix = started ? "+" : "";
1412 }
1413 slen +=
1414 snprintf(output + slen, outbufsize - slen,
1415 "%s0x%"PRIx32"", prefix, offset);
1416 }
1417 }
1418 output[slen++] = ']';
1419 } else {
1420 slen +=
1421 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1422 i);
1423 }
1424 }
1425 output[slen] = '\0';
1426 if (segover) { /* unused segment override */
1427 char *p = output;
1428 int count = slen + 1;
1429 while (count--)
1430 p[count + 3] = p[count];
1431 strncpy(output, segover, 2);
1432 output[2] = ' ';
1433 }
1434 return length;
1435 }
1436
1437 int32_t eatbyte(uint8_t *data, char *output, int outbufsize)
1438 {
1439 snprintf(output, outbufsize, "db 0x%02X", *data);
1440 return 1;
1441 }
rewrite Perl files