assemble.c

   1 /* assemble.c   code generation for the Netwide Assembler
   2  *
   3  * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
   4  * Julian Hall. All rights reserved. The software is
   5  * redistributable under the license given in the file "LICENSE"
   6  * distributed in the NASM archive.
   7  *
   8  * the actual codes (C syntax, i.e. octal):
   9  * \0            - terminates the code. (Unless it's a literal of course.)
  10  * \1, \2, \3    - that many literal bytes follow in the code stream
  11  * \4, \6        - the POP/PUSH (respectively) codes for CS, DS, ES, SS
  12  *                 (POP is never used for CS) depending on operand 0
  13  * \5, \7        - the second byte of POP/PUSH codes for FS, GS, depending
  14  *                 on operand 0
  15  * \10..\13      - a literal byte follows in the code stream, to be added
  16  *                 to the register value of operand 0..3
  17  * \14..\17      - a signed byte immediate operand, from operand 0..3
  18  * \20..\23      - a byte immediate operand, from operand 0..3
  19  * \24..\27      - an unsigned byte immediate operand, from operand 0..3
  20  * \30..\33      - a word immediate operand, from operand 0..3
  21  * \34..\37      - select between \3[0-3] and \4[0-3] depending on 16/32 bit
  22  *                 assembly mode or the operand-size override on the operand
  23  * \40..\43      - a long immediate operand, from operand 0..3
  24  * \44..\47      - select between \3[0-3], \4[0-3] and \5[4-7]
  25  *                 depending on the address size of the instruction.
  26  * \50..\53      - a byte relative operand, from operand 0..3
  27  * \54..\57      - a qword immediate operand, from operand 0..3
  28  * \60..\63      - a word relative operand, from operand 0..3
  29  * \64..\67      - select between \6[0-3] and \7[0-3] depending on 16/32 bit
  30  *                 assembly mode or the operand-size override on the operand
  31  * \70..\73      - a long relative operand, from operand 0..3
  32  * \74..\77       - a word constant, from the _segment_ part of operand 0..3
  33  * \1ab          - a ModRM, calculated on EA in operand a, with the spare
  34  *                 field the register value of operand b.
  35  * \140..\143    - an immediate word or signed byte for operand 0..3
  36  * \144..\147    - or 2 (s-field) into opcode byte if operand 0..3
  37  *                  is a signed byte rather than a word.  Opcode byte follows.
  38  * \150..\153     - an immediate dword or signed byte for operand 0..3
  39  * \154..\157    - or 2 (s-field) into opcode byte if operand 0..3
  40  *                  is a signed byte rather than a dword.  Opcode byte follows.
  41  * \160..\163    - this instruction uses DREX rather than REX, with the
  42  *                 OC0 field set to 0, and the dest field taken from
  43  *                 operand 0..3.
  44  * \164..\167    - this instruction uses DREX rather than REX, with the
  45  *                 OC0 field set to 1, and the dest field taken from
  46  *                 operand 0..3.
  47  * \171          - placement of DREX suffix in the absence of an EA
  48  * \172\ab       - the register number from operand a in bits 7..4, with
  49  *                 the 4-bit immediate from operand b in bits 3..0.
  50  * \173\xab      - the register number from operand a in bits 7..4, with
  51  *                 the value b in bits 3..0.
  52  * \174\a        - the register number from operand a in bits 7..4, and
  53  *                 an arbitrary value in bits 3..0 (assembled as zero.)
  54  * \2ab          - a ModRM, calculated on EA in operand a, with the spare
  55  *                 field equal to digit b.
  56  * \250..\253    - same as \150..\153, except warn if the 64-bit operand
  57  *                 is not equal to the truncated and sign-extended 32-bit
  58  *                 operand; used for 32-bit immediates in 64-bit mode.
  59  * \260..\263    - this instruction uses VEX rather than REX, with the
  60  *                 V field taken from operand 0..3.
  61  * \270          - this instruction uses VEX rather than REX, with the
  62  *                 V field set to 1111b.
  63  *
  64  * VEX prefixes are followed by the sequence:
  65  * \mm\wlp         where mm is the M field; and wlp is:
  66  *                 00 0ww lpp
  67  *                 [w0] ww = 0 for W = 0
  68  *                 [w1] ww = 1 for W = 1
  69  *                 [wx] ww = 2 for W don't care (always assembled as 0)
  70  *                 [ww] ww = 3 for W used as REX.W
  71  *
  72  *
  73  * \310          - indicates fixed 16-bit address size, i.e. optional 0x67.
  74  * \311          - indicates fixed 32-bit address size, i.e. optional 0x67.
  75  * \312          - (disassembler only) marker on LOOP, LOOPxx instructions.
  76  * \313          - indicates fixed 64-bit address size, 0x67 invalid.
  77  * \314          - (disassembler only) invalid with REX.B
  78  * \315          - (disassembler only) invalid with REX.X
  79  * \316          - (disassembler only) invalid with REX.R
  80  * \317          - (disassembler only) invalid with REX.W
  81  * \320          - indicates fixed 16-bit operand size, i.e. optional 0x66.
  82  * \321          - indicates fixed 32-bit operand size, i.e. optional 0x66.
  83  * \322          - indicates that this instruction is only valid when the
  84  *                 operand size is the default (instruction to disassembler,
  85  *                 generates no code in the assembler)
  86  * \323          - indicates fixed 64-bit operand size, REX on extensions only.
  87  * \324          - indicates 64-bit operand size requiring REX prefix.
  88  * \330          - a literal byte follows in the code stream, to be added
  89  *                 to the condition code value of the instruction.
  90  * \331          - instruction not valid with REP prefix.  Hint for
  91  *                 disassembler only; for SSE instructions.
  92  * \332          - REP prefix (0xF2 byte) used as opcode extension.
  93  * \333          - REP prefix (0xF3 byte) used as opcode extension.
  94  * \334          - LOCK prefix used instead of REX.R
  95  * \335          - disassemble a rep (0xF3 byte) prefix as repe not rep.
  96  * \336          - force a REP(E) prefix (0xF2) even if not specified.
  97  * \337          - force a REPNE prefix (0xF3) even if not specified.
  98  *                 \336-\337 are still listed as prefixes in the disassembler.
  99  * \340          - reserve <operand 0> bytes of uninitialized storage.
 100  *                 Operand 0 had better be a segmentless constant.
 101  * \360          - no SSE prefix (== \364\331)
 102  * \361          - 66 SSE prefix (== \366\331)
 103  * \362          - F2 SSE prefix (== \364\332)
 104  * \363          - F3 SSE prefix (== \364\333)
 105  * \364          - operand-size prefix (0x66) not permitted
 106  * \365          - address-size prefix (0x67) not permitted
 107  * \366          - operand-size prefix (0x66) used as opcode extension
 108  * \367          - address-size prefix (0x67) used as opcode extension
 109  * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
 110  *                 370 is used for Jcc, 371 is used for JMP.
 111  * \373          - assemble 0x03 if bits==16, 0x05 if bits==32;
 112  *                 used for conditional jump over longer jump
 113  */
 114
 115 #include "compiler.h"
 116
 117 #include <stdio.h>
 118 #include <string.h>
 119 #include <inttypes.h>
 120
 121 #include "nasm.h"
 122 #include "nasmlib.h"
 123 #include "assemble.h"
 124 #include "insns.h"
 125 #include "tables.h"
 126
 127 /* Initialized to zero by the C standard */
 128 static const uint8_t const_zero_buf[256];
 129
 130 typedef struct {
 131     int sib_present;                 /* is a SIB byte necessary? */
 132     int bytes;                       /* # of bytes of offset needed */
 133     int size;                        /* lazy - this is sib+bytes+1 */
 134     uint8_t modrm, sib, rex, rip;    /* the bytes themselves */
 135 } ea;
 136
 137 static uint32_t cpu;            /* cpu level received from nasm.c */
 138 static efunc errfunc;
 139 static struct ofmt *outfmt;
 140 static ListGen *list;
 141
 142 static int64_t calcsize(int32_t, int64_t, int, insn *, const uint8_t *);
 143 static void gencode(int32_t segment, int64_t offset, int bits,
 144                     insn * ins, const struct itemplate *temp,
 145                     int64_t insn_end);
 146 static int matches(const struct itemplate *, insn *, int bits);
 147 static int32_t regflag(const operand *);
 148 static int32_t regval(const operand *);
 149 static int rexflags(int, int32_t, int);
 150 static int op_rexflags(const operand *, int);
 151 static ea *process_ea(operand *, ea *, int, int, int, int32_t);
 152 static void add_asp(insn *, int);
 153
 154 static int has_prefix(insn * ins, enum prefix_pos pos, enum prefixes prefix)
 155 {
 156     return ins->prefixes[pos] == prefix;
 157 }
 158
 159 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
 160 {
 161     if (ins->prefixes[pos])
 162         errfunc(ERR_NONFATAL, "invalid %s prefix",
 163                 prefix_name(ins->prefixes[pos]));
 164 }
 165
 166 static const char *size_name(int size)
 167 {
 168     switch (size) {
 169     case 1:
 170         return "byte";
 171     case 2:
 172         return "word";
 173     case 4:
 174         return "dword";
 175     case 8:
 176         return "qword";
 177     case 10:
 178         return "tword";
 179     case 16:
 180         return "oword";
 181     case 32:
 182         return "yword";
 183     default:
 184         return "???";
 185     }
 186 }
 187
 188 static void warn_overflow(int size, int64_t data)
 189 {
 190     if (size < 8) {
 191         int64_t lim = ((int64_t)1 << (size*8))-1;
 192
 193         if (data < ~lim || data > lim)
 194             errfunc(ERR_WARNING | ERR_WARN_NOV,
 195                     "%s data exceeds bounds", size_name(size));
 196     }
 197 }
 198 /*
 199  * This routine wrappers the real output format's output routine,
 200  * in order to pass a copy of the data off to the listing file
 201  * generator at the same time.
 202  */
 203 static void out(int64_t offset, int32_t segto, const void *data,
 204                 enum out_type type, uint64_t size,
 205                 int32_t segment, int32_t wrt)
 206 {
 207     static int32_t lineno = 0;     /* static!!! */
 208     static char *lnfname = NULL;
 209     uint8_t p[8];
 210
 211     if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
 212         /*
 213          * This is a non-relocated address, and we're going to
 214          * convert it into RAWDATA format.
 215          */
 216         uint8_t *q = p;
 217
 218         if (size > 8) {
 219             errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
 220             return;
 221         }
 222
 223         WRITEADDR(q, *(int64_t *)data, size);
 224         data = p;
 225         type = OUT_RAWDATA;
 226     }
 227
 228     list->output(offset, data, type, size);
 229
 230     /*
 231      * this call to src_get determines when we call the
 232      * debug-format-specific "linenum" function
 233      * it updates lineno and lnfname to the current values
 234      * returning 0 if "same as last time", -2 if lnfname
 235      * changed, and the amount by which lineno changed,
 236      * if it did. thus, these variables must be static
 237      */
 238
 239     if (src_get(&lineno, &lnfname)) {
 240         outfmt->current_dfmt->linenum(lnfname, lineno, segto);
 241     }
 242
 243     outfmt->output(segto, data, type, size, segment, wrt);
 244 }
 245
 246 static bool jmp_match(int32_t segment, int64_t offset, int bits,
 247                      insn * ins, const uint8_t *code)
 248 {
 249     int64_t isize;
 250     uint8_t c = code[0];
 251
 252     if ((c != 0370 && c != 0371) || (ins->oprs[0].type & STRICT))
 253         return false;
 254     if (!optimizing)
 255         return false;
 256     if (optimizing < 0 && c == 0371)
 257         return false;
 258
 259     isize = calcsize(segment, offset, bits, ins, code);
 260     if (ins->oprs[0].segment != segment)
 261         return false;
 262
 263     isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
 264     return (isize >= -128 && isize <= 127); /* is it byte size? */
 265 }
 266
 267 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
 268               insn * instruction, struct ofmt *output, efunc error,
 269               ListGen * listgen)
 270 {
 271     const struct itemplate *temp;
 272     int j;
 273     int size_prob;
 274     int64_t insn_end;
 275     int32_t itimes;
 276     int64_t start = offset;
 277     int64_t wsize = 0;             /* size for DB etc. */
 278
 279     errfunc = error;            /* to pass to other functions */
 280     cpu = cp;
 281     outfmt = output;            /* likewise */
 282     list = listgen;             /* and again */
 283
 284     switch (instruction->opcode) {
 285     case -1:
 286         return 0;
 287     case I_DB:
 288         wsize = 1;
 289         break;
 290     case I_DW:
 291         wsize = 2;
 292         break;
 293     case I_DD:
 294         wsize = 4;
 295         break;
 296     case I_DQ:
 297         wsize = 8;
 298         break;
 299     case I_DT:
 300         wsize = 10;
 301         break;
 302     case I_DO:
 303         wsize = 16;
 304         break;
 305     case I_DY:
 306         wsize = 32;
 307         break;
 308     default:
 309         break;
 310     }
 311
 312     if (wsize) {
 313         extop *e;
 314         int32_t t = instruction->times;
 315         if (t < 0)
 316             errfunc(ERR_PANIC,
 317                     "instruction->times < 0 (%ld) in assemble()", t);
 318
 319         while (t--) {           /* repeat TIMES times */
 320             for (e = instruction->eops; e; e = e->next) {
 321                 if (e->type == EOT_DB_NUMBER) {
 322                     if (wsize == 1) {
 323                         if (e->segment != NO_SEG)
 324                             errfunc(ERR_NONFATAL,
 325                                     "one-byte relocation attempted");
 326                         else {
 327                             uint8_t out_byte = e->offset;
 328                             out(offset, segment, &out_byte,
 329                                 OUT_RAWDATA, 1, NO_SEG, NO_SEG);
 330                         }
 331                     } else if (wsize > 8) {
 332                         errfunc(ERR_NONFATAL,
 333                                 "integer supplied to a DT, DO or DY"
 334                                 " instruction");
 335                     } else
 336                         out(offset, segment, &e->offset,
 337                             OUT_ADDRESS, wsize, e->segment, e->wrt);
 338                     offset += wsize;
 339                 } else if (e->type == EOT_DB_STRING ||
 340                            e->type == EOT_DB_STRING_FREE) {
 341                     int align;
 342
 343                     out(offset, segment, e->stringval,
 344                         OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
 345                     align = e->stringlen % wsize;
 346
 347                     if (align) {
 348                         align = wsize - align;
 349                         out(offset, segment, const_zero_buf,
 350                             OUT_RAWDATA, align, NO_SEG, NO_SEG);
 351                     }
 352                     offset += e->stringlen + align;
 353                 }
 354             }
 355             if (t > 0 && t == instruction->times - 1) {
 356                 /*
 357                  * Dummy call to list->output to give the offset to the
 358                  * listing module.
 359                  */
 360                 list->output(offset, NULL, OUT_RAWDATA, 0);
 361                 list->uplevel(LIST_TIMES);
 362             }
 363         }
 364         if (instruction->times > 1)
 365             list->downlevel(LIST_TIMES);
 366         return offset - start;
 367     }
 368
 369     if (instruction->opcode == I_INCBIN) {
 370         const char *fname = instruction->eops->stringval;
 371         FILE *fp;
 372
 373         fp = fopen(fname, "rb");
 374         if (!fp) {
 375             error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
 376                   fname);
 377         } else if (fseek(fp, 0L, SEEK_END) < 0) {
 378             error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
 379                   fname);
 380         } else {
 381             static char buf[4096];
 382             size_t t = instruction->times;
 383             size_t base = 0;
 384             size_t len;
 385
 386             len = ftell(fp);
 387             if (instruction->eops->next) {
 388                 base = instruction->eops->next->offset;
 389                 len -= base;
 390                 if (instruction->eops->next->next &&
 391                     len > (size_t)instruction->eops->next->next->offset)
 392                     len = (size_t)instruction->eops->next->next->offset;
 393             }
 394             /*
 395              * Dummy call to list->output to give the offset to the
 396              * listing module.
 397              */
 398             list->output(offset, NULL, OUT_RAWDATA, 0);
 399             list->uplevel(LIST_INCBIN);
 400             while (t--) {
 401                 size_t l;
 402
 403                 fseek(fp, base, SEEK_SET);
 404                 l = len;
 405                 while (l > 0) {
 406                     int32_t m =
 407                         fread(buf, 1, (l > (int32_t) sizeof(buf) ? (int32_t) sizeof(buf) : l),
 408                               fp);
 409                     if (!m) {
 410                         /*
 411                          * This shouldn't happen unless the file
 412                          * actually changes while we are reading
 413                          * it.
 414                          */
 415                         error(ERR_NONFATAL,
 416                               "`incbin': unexpected EOF while"
 417                               " reading file `%s'", fname);
 418                         t = 0;  /* Try to exit cleanly */
 419                         break;
 420                     }
 421                     out(offset, segment, buf, OUT_RAWDATA, m,
 422                         NO_SEG, NO_SEG);
 423                     l -= m;
 424                 }
 425             }
 426             list->downlevel(LIST_INCBIN);
 427             if (instruction->times > 1) {
 428                 /*
 429                  * Dummy call to list->output to give the offset to the
 430                  * listing module.
 431                  */
 432                 list->output(offset, NULL, OUT_RAWDATA, 0);
 433                 list->uplevel(LIST_TIMES);
 434                 list->downlevel(LIST_TIMES);
 435             }
 436             fclose(fp);
 437             return instruction->times * len;
 438         }
 439         return 0;               /* if we're here, there's an error */
 440     }
 441
 442     /* Check to see if we need an address-size prefix */
 443     add_asp(instruction, bits);
 444
 445     size_prob = false;
 446
 447     for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++){
 448         int m = matches(temp, instruction, bits);
 449         if (m == 100 ||
 450             (m == 99 && jmp_match(segment, offset, bits,
 451                                   instruction, temp->code))) {
 452             /* Matches! */
 453             int64_t insn_size = calcsize(segment, offset, bits,
 454                                       instruction, temp->code);
 455             itimes = instruction->times;
 456             if (insn_size < 0)  /* shouldn't be, on pass two */
 457                 error(ERR_PANIC, "errors made it through from pass one");
 458             else
 459                 while (itimes--) {
 460                     for (j = 0; j < MAXPREFIX; j++) {
 461                         uint8_t c = 0;
 462                         switch (instruction->prefixes[j]) {
 463                         case P_LOCK:
 464                             c = 0xF0;
 465                             break;
 466                         case P_REPNE:
 467                         case P_REPNZ:
 468                             c = 0xF2;
 469                             break;
 470                         case P_REPE:
 471                         case P_REPZ:
 472                         case P_REP:
 473                             c = 0xF3;
 474                             break;
 475                         case R_CS:
 476                             if (bits == 64) {
 477                                 error(ERR_WARNING,
 478                                       "cs segment base generated, but will be ignored in 64-bit mode");
 479                             }
 480                             c = 0x2E;
 481                             break;
 482                         case R_DS:
 483                             if (bits == 64) {
 484                                 error(ERR_WARNING,
 485                                       "ds segment base generated, but will be ignored in 64-bit mode");
 486                             }
 487                             c = 0x3E;
 488                             break;
 489                         case R_ES:
 490                            if (bits == 64) {
 491                                 error(ERR_WARNING,
 492                                       "es segment base generated, but will be ignored in 64-bit mode");
 493                            }
 494                             c = 0x26;
 495                             break;
 496                         case R_FS:
 497                             c = 0x64;
 498                             break;
 499                         case R_GS:
 500                             c = 0x65;
 501                             break;
 502                         case R_SS:
 503                             if (bits == 64) {
 504                                 error(ERR_WARNING,
 505                                       "ss segment base generated, but will be ignored in 64-bit mode");
 506                             }
 507                             c = 0x36;
 508                             break;
 509                         case R_SEGR6:
 510                         case R_SEGR7:
 511                             error(ERR_NONFATAL,
 512                                   "segr6 and segr7 cannot be used as prefixes");
 513                             break;
 514                         case P_A16:
 515                             if (bits == 64) {
 516                                 error(ERR_NONFATAL,
 517                                       "16-bit addressing is not supported "
 518                                       "in 64-bit mode");
 519                             } else if (bits != 16)
 520                                 c = 0x67;
 521                             break;
 522                         case P_A32:
 523                             if (bits != 32)
 524                                 c = 0x67;
 525                             break;
 526                         case P_A64:
 527                             if (bits != 64) {
 528                                 error(ERR_NONFATAL,
 529                                       "64-bit addressing is only supported "
 530                                       "in 64-bit mode");
 531                             }
 532                             break;
 533                         case P_ASP:
 534                             c = 0x67;
 535                             break;
 536                         case P_O16:
 537                             if (bits != 16)
 538                                 c = 0x66;
 539                             break;
 540                         case P_O32:
 541                             if (bits == 16)
 542                                 c = 0x66;
 543                             break;
 544                         case P_O64:
 545                             /* REX.W */
 546                             break;
 547                         case P_OSP:
 548                             c = 0x66;
 549                             break;
 550                         case P_none:
 551                             break;
 552                         default:
 553                             error(ERR_PANIC, "invalid instruction prefix");
 554                         }
 555                         if (c != 0) {
 556                             out(offset, segment, &c, OUT_RAWDATA, 1,
 557                                 NO_SEG, NO_SEG);
 558                             offset++;
 559                         }
 560                     }
 561                     insn_end = offset + insn_size;
 562                     gencode(segment, offset, bits, instruction,
 563                             temp, insn_end);
 564                     offset += insn_size;
 565                     if (itimes > 0 && itimes == instruction->times - 1) {
 566                         /*
 567                          * Dummy call to list->output to give the offset to the
 568                          * listing module.
 569                          */
 570                         list->output(offset, NULL, OUT_RAWDATA, 0);
 571                         list->uplevel(LIST_TIMES);
 572                     }
 573                 }
 574             if (instruction->times > 1)
 575                 list->downlevel(LIST_TIMES);
 576             return offset - start;
 577         } else if (m > 0 && m > size_prob) {
 578             size_prob = m;
 579         }
 580     }
 581
 582     if (temp->opcode == -1) {   /* didn't match any instruction */
 583         switch (size_prob) {
 584         case 1:
 585             error(ERR_NONFATAL, "operation size not specified");
 586             break;
 587         case 2:
 588             error(ERR_NONFATAL, "mismatch in operand sizes");
 589             break;
 590         case 3:
 591             error(ERR_NONFATAL, "no instruction for this cpu level");
 592             break;
 593         case 4:
 594             error(ERR_NONFATAL, "instruction not supported in 64-bit mode");
 595             break;
 596         default:
 597             error(ERR_NONFATAL,
 598                   "invalid combination of opcode and operands");
 599             break;
 600         }
 601     }
 602     return 0;
 603 }
 604
 605 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
 606                insn * instruction, efunc error)
 607 {
 608     const struct itemplate *temp;
 609
 610     errfunc = error;            /* to pass to other functions */
 611     cpu = cp;
 612
 613     if (instruction->opcode == -1)
 614         return 0;
 615
 616     if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
 617         instruction->opcode == I_DD || instruction->opcode == I_DQ ||
 618         instruction->opcode == I_DT || instruction->opcode == I_DO ||
 619         instruction->opcode == I_DY) {
 620         extop *e;
 621         int32_t isize, osize, wsize = 0;   /* placate gcc */
 622
 623         isize = 0;
 624         switch (instruction->opcode) {
 625         case I_DB:
 626             wsize = 1;
 627             break;
 628         case I_DW:
 629             wsize = 2;
 630             break;
 631         case I_DD:
 632             wsize = 4;
 633             break;
 634         case I_DQ:
 635             wsize = 8;
 636             break;
 637         case I_DT:
 638             wsize = 10;
 639             break;
 640         case I_DO:
 641             wsize = 16;
 642             break;
 643         case I_DY:
 644             wsize = 32;
 645             break;
 646         default:
 647             break;
 648         }
 649
 650         for (e = instruction->eops; e; e = e->next) {
 651             int32_t align;
 652
 653             osize = 0;
 654             if (e->type == EOT_DB_NUMBER)
 655                 osize = 1;
 656             else if (e->type == EOT_DB_STRING ||
 657                      e->type == EOT_DB_STRING_FREE)
 658                 osize = e->stringlen;
 659
 660             align = (-osize) % wsize;
 661             if (align < 0)
 662                 align += wsize;
 663             isize += osize + align;
 664         }
 665         return isize * instruction->times;
 666     }
 667
 668     if (instruction->opcode == I_INCBIN) {
 669         const char *fname = instruction->eops->stringval;
 670         FILE *fp;
 671         size_t len;
 672
 673         fp = fopen(fname, "rb");
 674         if (!fp)
 675             error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
 676                   fname);
 677         else if (fseek(fp, 0L, SEEK_END) < 0)
 678             error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
 679                   fname);
 680         else {
 681             len = ftell(fp);
 682             fclose(fp);
 683             if (instruction->eops->next) {
 684                 len -= instruction->eops->next->offset;
 685                 if (instruction->eops->next->next &&
 686                     len > (size_t)instruction->eops->next->next->offset) {
 687                     len = (size_t)instruction->eops->next->next->offset;
 688                 }
 689             }
 690             return instruction->times * len;
 691         }
 692         return 0;               /* if we're here, there's an error */
 693     }
 694
 695     /* Check to see if we need an address-size prefix */
 696     add_asp(instruction, bits);
 697
 698     for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++) {
 699         int m = matches(temp, instruction, bits);
 700         if (m == 100 ||
 701             (m == 99 && jmp_match(segment, offset, bits,
 702                                   instruction, temp->code))) {
 703             /* we've matched an instruction. */
 704             int64_t isize;
 705             const uint8_t *codes = temp->code;
 706             int j;
 707
 708             isize = calcsize(segment, offset, bits, instruction, codes);
 709             if (isize < 0)
 710                 return -1;
 711             for (j = 0; j < MAXPREFIX; j++) {
 712                 switch (instruction->prefixes[j]) {
 713                 case P_A16:
 714                     if (bits != 16)
 715                         isize++;
 716                     break;
 717                 case P_A32:
 718                     if (bits != 32)
 719                         isize++;
 720                     break;
 721                 case P_O16:
 722                     if (bits != 16)
 723                         isize++;
 724                     break;
 725                 case P_O32:
 726                     if (bits == 16)
 727                         isize++;
 728                     break;
 729                 case P_A64:
 730                 case P_O64:
 731                 case P_none:
 732                     break;
 733                 default:
 734                     isize++;
 735                     break;
 736                 }
 737             }
 738             return isize * instruction->times;
 739         }
 740     }
 741     return -1;                  /* didn't match any instruction */
 742 }
 743
 744 static bool possible_sbyte(operand *o)
 745 {
 746     return !(o->opflags & OPFLAG_FORWARD) &&
 747         optimizing >= 0 && !(o->type & STRICT) &&
 748         o->wrt == NO_SEG && o->segment == NO_SEG;
 749 }
 750
 751 /* check that opn[op]  is a signed byte of size 16 or 32 */
 752 static bool is_sbyte16(operand *o)
 753 {
 754     int16_t v;
 755
 756     if (!possible_sbyte(o))
 757         return false;
 758
 759     v = o->offset;
 760     return v >= -128 && v <= 127;
 761 }
 762
 763 static bool is_sbyte32(operand *o)
 764 {
 765     int32_t v;
 766
 767     if (!possible_sbyte(o))
 768         return false;
 769
 770     v = o->offset;
 771     return v >= -128 && v <= 127;
 772 }
 773
 774 /* check that  opn[op]  is a signed byte of size 32; warn if this is not
 775    the original value when extended to 64 bits */
 776 static bool is_sbyte64(operand *o)
 777 {
 778     int64_t v64;
 779     int32_t v32;
 780
 781     /* dead in the water on forward reference or External */
 782     if (!possible_sbyte(o))
 783         return false;
 784
 785     v64 = o->offset;
 786     v32 = (int32_t)v64;
 787
 788     warn_overflow(32, v64);
 789
 790     return v32 >= -128 && v32 <= 127;
 791 }
 792 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
 793                      insn * ins, const uint8_t *codes)
 794 {
 795     int64_t length = 0;
 796     uint8_t c;
 797     int rex_mask = ~0;
 798     struct operand *opx;
 799
 800     ins->rex = 0;               /* Ensure REX is reset */
 801
 802     if (ins->prefixes[PPS_OSIZE] == P_O64)
 803         ins->rex |= REX_W;
 804
 805     (void)segment;              /* Don't warn that this parameter is unused */
 806     (void)offset;               /* Don't warn that this parameter is unused */
 807
 808     while (*codes) {
 809         c = *codes++;
 810         opx = &ins->oprs[c & 3];
 811         switch (c) {
 812         case 01:
 813         case 02:
 814         case 03:
 815             codes += c, length += c;
 816             break;
 817         case 04:
 818         case 05:
 819         case 06:
 820         case 07:
 821             length++;
 822             break;
 823         case 010:
 824         case 011:
 825         case 012:
 826         case 013:
 827             ins->rex |=
 828                 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
 829             codes++, length++;
 830             break;
 831         case 014:
 832         case 015:
 833         case 016:
 834         case 017:
 835             length++;
 836             break;
 837         case 020:
 838         case 021:
 839         case 022:
 840         case 023:
 841             length++;
 842             break;
 843         case 024:
 844         case 025:
 845         case 026:
 846         case 027:
 847             length++;
 848             break;
 849         case 030:
 850         case 031:
 851         case 032:
 852         case 033:
 853             length += 2;
 854             break;
 855         case 034:
 856         case 035:
 857         case 036:
 858         case 037:
 859             if (opx->type & (BITS16 | BITS32 | BITS64))
 860                 length += (opx->type & BITS16) ? 2 : 4;
 861             else
 862                 length += (bits == 16) ? 2 : 4;
 863             break;
 864         case 040:
 865         case 041:
 866         case 042:
 867         case 043:
 868             length += 4;
 869             break;
 870         case 044:
 871         case 045:
 872         case 046:
 873         case 047:
 874             length += ins->addr_size >> 3;
 875             break;
 876         case 050:
 877         case 051:
 878         case 052:
 879         case 053:
 880             length++;
 881             break;
 882         case 054:
 883         case 055:
 884         case 056:
 885         case 057:
 886             length += 8; /* MOV reg64/imm */
 887             break;
 888         case 060:
 889         case 061:
 890         case 062:
 891         case 063:
 892             length += 2;
 893             break;
 894         case 064:
 895         case 065:
 896         case 066:
 897         case 067:
 898             if (opx->type & (BITS16 | BITS32 | BITS64))
 899                 length += (opx->type & BITS16) ? 2 : 4;
 900             else
 901                 length += (bits == 16) ? 2 : 4;
 902             break;
 903         case 070:
 904         case 071:
 905         case 072:
 906         case 073:
 907             length += 4;
 908             break;
 909         case 074:
 910         case 075:
 911         case 076:
 912         case 077:
 913             length += 2;
 914             break;
 915         case 0140:
 916         case 0141:
 917         case 0142:
 918         case 0143:
 919             length += is_sbyte16(opx) ? 1 : 2;
 920             break;
 921         case 0144:
 922         case 0145:
 923         case 0146:
 924         case 0147:
 925             codes++;
 926             length++;
 927             break;
 928         case 0150:
 929         case 0151:
 930         case 0152:
 931         case 0153:
 932             length += is_sbyte32(opx) ? 1 : 4;
 933             break;
 934         case 0154:
 935         case 0155:
 936         case 0156:
 937         case 0157:
 938             codes++;
 939             length++;
 940             break;
 941         case 0160:
 942         case 0161:
 943         case 0162:
 944         case 0163:
 945             length++;
 946             ins->rex |= REX_D;
 947             ins->drexdst = regval(opx);
 948             break;
 949         case 0164:
 950         case 0165:
 951         case 0166:
 952         case 0167:
 953             length++;
 954             ins->rex |= REX_D|REX_OC;
 955             ins->drexdst = regval(opx);
 956             break;
 957         case 0171:
 958             break;
 959         case 0172:
 960         case 0173:
 961         case 0174:
 962             codes++;
 963             length++;
 964             break;
 965         case 0250:
 966         case 0251:
 967         case 0252:
 968         case 0253:
 969             length += is_sbyte64(opx) ? 1 : 4;
 970             break;
 971         case 0260:
 972         case 0261:
 973         case 0262:
 974         case 0263:
 975             ins->rex |= REX_V;
 976             ins->drexdst = regval(opx);
 977             ins->vex_m = *codes++;
 978             ins->vex_wlp = *codes++;
 979             break;
 980         case 0270:
 981             ins->rex |= REX_V;
 982             ins->drexdst = 0;
 983             ins->vex_m = *codes++;
 984             ins->vex_wlp = *codes++;
 985             break;
 986         case 0300:
 987         case 0301:
 988         case 0302:
 989         case 0303:
 990             break;
 991         case 0310:
 992             if (bits == 64)
 993                 return -1;
 994             length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
 995             break;
 996         case 0311:
 997             length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
 998             break;
 999         case 0312:
1000             break;
1001         case 0313:
1002             if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1003                 has_prefix(ins, PPS_ASIZE, P_A32))
1004                 return -1;
1005             break;
1006         case 0314:
1007         case 0315:
1008         case 0316:
1009         case 0317:
1010             break;
1011         case 0320:
1012             length += (bits != 16);
1013             break;
1014         case 0321:
1015             length += (bits == 16);
1016             break;
1017         case 0322:
1018             break;
1019         case 0323:
1020             rex_mask &= ~REX_W;
1021             break;
1022         case 0324:
1023             ins->rex |= REX_W;
1024             break;
1025         case 0330:
1026             codes++, length++;
1027             break;
1028         case 0331:
1029             break;
1030         case 0332:
1031         case 0333:
1032             length++;
1033             break;
1034         case 0334:
1035             ins->rex |= REX_L;
1036             break;
1037         case 0335:
1038             break;
1039         case 0336:
1040             if (!ins->prefixes[PPS_LREP])
1041                 ins->prefixes[PPS_LREP] = P_REP;
1042             break;
1043         case 0337:
1044             if (!ins->prefixes[PPS_LREP])
1045                 ins->prefixes[PPS_LREP] = P_REPNE;
1046             break;
1047         case 0340:
1048             if (ins->oprs[0].segment != NO_SEG)
1049                 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1050                         " quantity of BSS space");
1051             else
1052                 length += ins->oprs[0].offset;
1053             break;
1054         case 0360:
1055             break;
1056         case 0361:
1057         case 0362:
1058         case 0363:
1059             length++;
1060             break;
1061         case 0364:
1062         case 0365:
1063             break;
1064         case 0366:
1065         case 0367:
1066             length++;
1067             break;
1068         case 0370:
1069         case 0371:
1070         case 0372:
1071             break;
1072         case 0373:
1073             length++;
1074             break;
1075         default:               /* can't do it by 'case' statements */
1076             if (c >= 0100 && c <= 0277) {       /* it's an EA */
1077                 ea ea_data;
1078                 int rfield;
1079                 int32_t rflags;
1080                 ea_data.rex = 0;           /* Ensure ea.REX is initially 0 */
1081
1082                 if (c <= 0177) {
1083                     /* pick rfield from operand b */
1084                     rflags = regflag(&ins->oprs[c & 7]);
1085                     rfield = nasm_regvals[ins->oprs[c & 7].basereg];
1086                 } else {
1087                     rflags = 0;
1088                     rfield = c & 7;
1089                 }
1090
1091                 if (!process_ea
1092                     (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1093                      ins->addr_size, rfield, rflags)) {
1094                     errfunc(ERR_NONFATAL, "invalid effective address");
1095                     return -1;
1096                 } else {
1097                     ins->rex |= ea_data.rex;
1098                     length += ea_data.size;
1099                 }
1100             } else {
1101                 errfunc(ERR_PANIC, "internal instruction table corrupt"
1102                         ": instruction code 0x%02X given", c);
1103             }
1104         }
1105     }
1106
1107     ins->rex &= rex_mask;
1108
1109     if (ins->rex & REX_V) {
1110         int bad32 = REX_R|REX_W|REX_X|REX_B;
1111
1112         if (ins->rex & REX_H) {
1113             errfunc(ERR_NONFATAL, "cannot use high register in vex instruction");
1114             return -1;
1115         }
1116         switch (ins->vex_wlp & 030) {
1117         case 000:
1118         case 020:
1119             ins->rex &= ~REX_W;
1120             break;
1121         case 010:
1122             ins->rex |= REX_W;
1123             bad32 &= ~REX_W;
1124             break;
1125         case 030:
1126             /* Follow REX_W */
1127             break;
1128         }
1129
1130         if (bits != 64 && ((ins->rex & bad32) || ins->drexdst > 7)) {
1131             errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1132             return -1;
1133         }
1134         if (ins->vex_m != 1 || (ins->rex & (REX_W|REX_R|REX_B)))
1135             length += 3;
1136         else
1137             length += 2;
1138     } else if (ins->rex & REX_D) {
1139         if (ins->rex & REX_H) {
1140             errfunc(ERR_NONFATAL, "cannot use high register in drex instruction");
1141             return -1;
1142         }
1143         if (bits != 64 && ((ins->rex & (REX_R|REX_W|REX_X|REX_B)) ||
1144                            ins->drexdst > 7)) {
1145             errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1146             return -1;
1147         }
1148         length++;
1149     } else if (ins->rex & REX_REAL) {
1150         if (ins->rex & REX_H) {
1151             errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1152             return -1;
1153         } else if (bits == 64) {
1154             length++;
1155         } else if ((ins->rex & REX_L) &&
1156                    !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1157                    cpu >= IF_X86_64) {
1158             /* LOCK-as-REX.R */
1159             assert_no_prefix(ins, PPS_LREP);
1160             length++;
1161         } else {
1162             errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1163             return -1;
1164         }
1165     }
1166
1167     return length;
1168 }
1169
1170 #define EMIT_REX()                                                      \
1171     if (!(ins->rex & (REX_D|REX_V)) && (ins->rex & REX_REAL) && (bits == 64)) { \
1172         ins->rex = (ins->rex & REX_REAL)|REX_P;                         \
1173         out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1174         ins->rex = 0;                                                   \
1175         offset += 1; \
1176     }
1177
1178 static void gencode(int32_t segment, int64_t offset, int bits,
1179                     insn * ins, const struct itemplate *temp,
1180                     int64_t insn_end)
1181 {
1182     static char condval[] = {   /* conditional opcodes */
1183         0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1184         0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1185         0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1186     };
1187     uint8_t c;
1188     uint8_t bytes[4];
1189     int64_t size;
1190     int64_t data;
1191     struct operand *opx;
1192     const uint8_t *codes = temp->code;
1193
1194     while (*codes) {
1195         c = *codes++;
1196         opx = &ins->oprs[c & 3];
1197         switch (c) {
1198         case 01:
1199         case 02:
1200         case 03:
1201             EMIT_REX();
1202             out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1203             codes += c;
1204             offset += c;
1205             break;
1206
1207         case 04:
1208         case 06:
1209             switch (ins->oprs[0].basereg) {
1210             case R_CS:
1211                 bytes[0] = 0x0E + (c == 0x04 ? 1 : 0);
1212                 break;
1213             case R_DS:
1214                 bytes[0] = 0x1E + (c == 0x04 ? 1 : 0);
1215                 break;
1216             case R_ES:
1217                 bytes[0] = 0x06 + (c == 0x04 ? 1 : 0);
1218                 break;
1219             case R_SS:
1220                 bytes[0] = 0x16 + (c == 0x04 ? 1 : 0);
1221                 break;
1222             default:
1223                 errfunc(ERR_PANIC,
1224                         "bizarre 8086 segment register received");
1225             }
1226             out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1227             offset++;
1228             break;
1229
1230         case 05:
1231         case 07:
1232             switch (ins->oprs[0].basereg) {
1233             case R_FS:
1234                 bytes[0] = 0xA0 + (c == 0x05 ? 1 : 0);
1235                 break;
1236             case R_GS:
1237                 bytes[0] = 0xA8 + (c == 0x05 ? 1 : 0);
1238                 break;
1239             default:
1240                 errfunc(ERR_PANIC,
1241                         "bizarre 386 segment register received");
1242             }
1243             out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1244             offset++;
1245             break;
1246
1247         case 010:
1248         case 011:
1249         case 012:
1250         case 013:
1251             EMIT_REX();
1252             bytes[0] = *codes++ + ((regval(opx)) & 7);
1253             out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1254             offset += 1;
1255             break;
1256
1257         case 014:
1258         case 015:
1259         case 016:
1260         case 017:
1261             /* The test for BITS8 and SBYTE here is intended to avoid
1262                warning on optimizer actions due to SBYTE, while still
1263                warn on explicit BYTE directives.  Also warn, obviously,
1264                if the optimizer isn't enabled. */
1265             if (((opx->type & BITS8) ||
1266                  !(opx->type & temp->opd[c & 3] & BYTENESS)) &&
1267                 (opx->offset < -128 || opx->offset > 127)) {
1268                 errfunc(ERR_WARNING | ERR_WARN_NOV,
1269                         "signed byte value exceeds bounds");
1270             }
1271             if (opx->segment != NO_SEG) {
1272                 data = opx->offset;
1273                 out(offset, segment, &data, OUT_ADDRESS, 1,
1274                     opx->segment, opx->wrt);
1275             } else {
1276                 bytes[0] = opx->offset;
1277                 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1278                     NO_SEG);
1279             }
1280             offset += 1;
1281             break;
1282
1283         case 020:
1284         case 021:
1285         case 022:
1286         case 023:
1287             if (opx->offset < -256 || opx->offset > 255) {
1288                 errfunc(ERR_WARNING | ERR_WARN_NOV,
1289                         "byte value exceeds bounds");
1290             }
1291             if (opx->segment != NO_SEG) {
1292                 data = opx->offset;
1293                 out(offset, segment, &data, OUT_ADDRESS, 1,
1294                     opx->segment, opx->wrt);
1295             } else {
1296                 bytes[0] = opx->offset;
1297                 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1298                     NO_SEG);
1299             }
1300             offset += 1;
1301             break;
1302
1303         case 024:
1304         case 025:
1305         case 026:
1306         case 027:
1307             if (opx->offset < 0 || opx->offset > 255)
1308                 errfunc(ERR_WARNING | ERR_WARN_NOV,
1309                         "unsigned byte value exceeds bounds");
1310             if (opx->segment != NO_SEG) {
1311                 data = opx->offset;
1312                 out(offset, segment, &data, OUT_ADDRESS, 1,
1313                     opx->segment, opx->wrt);
1314             } else {
1315                 bytes[0] = opx->offset;
1316                 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1317                     NO_SEG);
1318             }
1319             offset += 1;
1320             break;
1321
1322         case 030:
1323         case 031:
1324         case 032:
1325         case 033:
1326             data = opx->offset;
1327             if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1328                 warn_overflow(2, data);
1329             out(offset, segment, &data, OUT_ADDRESS, 2,
1330                 opx->segment, opx->wrt);
1331             offset += 2;
1332             break;
1333
1334         case 034:
1335         case 035:
1336         case 036:
1337         case 037:
1338             if (opx->type & (BITS16 | BITS32))
1339                 size = (opx->type & BITS16) ? 2 : 4;
1340             else
1341                 size = (bits == 16) ? 2 : 4;
1342             data = opx->offset;
1343             if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1344                 warn_overflow(size, data);
1345             out(offset, segment, &data, OUT_ADDRESS, size,
1346                 opx->segment, opx->wrt);
1347             offset += size;
1348             break;
1349
1350         case 040:
1351         case 041:
1352         case 042:
1353         case 043:
1354             data = opx->offset;
1355             if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1356                 warn_overflow(4, data);
1357             out(offset, segment, &data, OUT_ADDRESS, 4,
1358                 opx->segment, opx->wrt);
1359             offset += 4;
1360             break;
1361
1362         case 044:
1363         case 045:
1364         case 046:
1365         case 047:
1366             data = opx->offset;
1367             size = ins->addr_size >> 3;
1368             if (opx->segment == NO_SEG &&
1369                 opx->wrt == NO_SEG)
1370                 warn_overflow(size, data);
1371             out(offset, segment, &data, OUT_ADDRESS, size,
1372                 opx->segment, opx->wrt);
1373             offset += size;
1374             break;
1375
1376         case 050:
1377         case 051:
1378         case 052:
1379         case 053:
1380             if (opx->segment != segment)
1381                 errfunc(ERR_NONFATAL,
1382                         "short relative jump outside segment");
1383             data = opx->offset - insn_end;
1384             if (data > 127 || data < -128)
1385                 errfunc(ERR_NONFATAL, "short jump is out of range");
1386             bytes[0] = data;
1387             out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1388             offset += 1;
1389             break;
1390
1391         case 054:
1392         case 055:
1393         case 056:
1394         case 057:
1395             data = (int64_t)opx->offset;
1396             out(offset, segment, &data, OUT_ADDRESS, 8,
1397                 opx->segment, opx->wrt);
1398             offset += 8;
1399             break;
1400
1401         case 060:
1402         case 061:
1403         case 062:
1404         case 063:
1405             if (opx->segment != segment) {
1406                 data = opx->offset;
1407                 out(offset, segment, &data,
1408                     OUT_REL2ADR, insn_end - offset,
1409                     opx->segment, opx->wrt);
1410             } else {
1411                 data = opx->offset - insn_end;
1412                 out(offset, segment, &data,
1413                     OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1414             }
1415             offset += 2;
1416             break;
1417
1418         case 064:
1419         case 065:
1420         case 066:
1421         case 067:
1422             if (opx->type & (BITS16 | BITS32 | BITS64))
1423                 size = (opx->type & BITS16) ? 2 : 4;
1424             else
1425                 size = (bits == 16) ? 2 : 4;
1426             if (opx->segment != segment) {
1427                 data = opx->offset;
1428                 out(offset, segment, &data,
1429                     size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1430                     insn_end - offset, opx->segment, opx->wrt);
1431             } else {
1432                 data = opx->offset - insn_end;
1433                 out(offset, segment, &data,
1434                     OUT_ADDRESS, size, NO_SEG, NO_SEG);
1435             }
1436             offset += size;
1437             break;
1438
1439         case 070:
1440         case 071:
1441         case 072:
1442         case 073:
1443             if (opx->segment != segment) {
1444                 data = opx->offset;
1445                 out(offset, segment, &data,
1446                     OUT_REL4ADR, insn_end - offset,
1447                     opx->segment, opx->wrt);
1448             } else {
1449                 data = opx->offset - insn_end;
1450                 out(offset, segment, &data,
1451                     OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1452             }
1453             offset += 4;
1454             break;
1455
1456         case 074:
1457         case 075:
1458         case 076:
1459         case 077:
1460             if (opx->segment == NO_SEG)
1461                 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1462                         " relocatable");
1463             data = 0;
1464             out(offset, segment, &data, OUT_ADDRESS, 2,
1465                 outfmt->segbase(1 + opx->segment),
1466                 opx->wrt);
1467             offset += 2;
1468             break;
1469
1470         case 0140:
1471         case 0141:
1472         case 0142:
1473         case 0143:
1474             data = opx->offset;
1475             if (is_sbyte16(opx)) {
1476                 bytes[0] = data;
1477                 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1478                     NO_SEG);
1479                 offset++;
1480             } else {
1481                 if (opx->segment == NO_SEG &&
1482                     opx->wrt == NO_SEG)
1483                     warn_overflow(2, data);
1484                 out(offset, segment, &data, OUT_ADDRESS, 2,
1485                     opx->segment, opx->wrt);
1486                 offset += 2;
1487             }
1488             break;
1489
1490         case 0144:
1491         case 0145:
1492         case 0146:
1493         case 0147:
1494             EMIT_REX();
1495             bytes[0] = *codes++;
1496             if (is_sbyte16(opx))
1497                 bytes[0] |= 2;  /* s-bit */
1498             out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1499             offset++;
1500             break;
1501
1502         case 0150:
1503         case 0151:
1504         case 0152:
1505         case 0153:
1506             data = opx->offset;
1507             if (is_sbyte32(opx)) {
1508                 bytes[0] = data;
1509                 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1510                     NO_SEG);
1511                 offset++;
1512             } else {
1513                 out(offset, segment, &data, OUT_ADDRESS, 4,
1514                     opx->segment, opx->wrt);
1515                 offset += 4;
1516             }
1517             break;
1518
1519         case 0154:
1520         case 0155:
1521         case 0156:
1522         case 0157:
1523             EMIT_REX();
1524             bytes[0] = *codes++;
1525             if (is_sbyte32(opx))
1526                 bytes[0] |= 2;  /* s-bit */
1527             out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1528             offset++;
1529             break;
1530
1531         case 0160:
1532         case 0161:
1533         case 0162:
1534         case 0163:
1535         case 0164:
1536         case 0165:
1537         case 0166:
1538         case 0167:
1539             break;
1540
1541         case 0171:
1542             bytes[0] =
1543                 (ins->drexdst << 4) |
1544                 (ins->rex & REX_OC ? 0x08 : 0) |
1545                 (ins->rex & (REX_R|REX_X|REX_B));
1546             ins->rex = 0;
1547             out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1548             offset++;
1549             break;
1550
1551         case 0172:
1552             c = *codes++;
1553             opx = &ins->oprs[c >> 3];
1554             bytes[0] = nasm_regvals[opx->basereg] << 4;
1555             opx = &ins->oprs[c & 7];
1556             if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1557                 errfunc(ERR_NONFATAL,
1558                         "non-absolute expression not permitted as argument %d",
1559                         c & 7);
1560             } else {
1561                 if (opx->offset & ~15) {
1562                     errfunc(ERR_WARNING | ERR_WARN_NOV,
1563                             "four-bit argument exceeds bounds");
1564                 }
1565                 bytes[0] |= opx->offset & 15;
1566             }
1567             out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1568             offset++;
1569             break;
1570
1571         case 0173:
1572             c = *codes++;
1573             opx = &ins->oprs[c >> 4];
1574             bytes[0] = nasm_regvals[opx->basereg] << 4;
1575             bytes[0] |= c & 15;
1576             out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1577             offset++;
1578             break;
1579
1580         case 0174:
1581             c = *codes++;
1582             opx = &ins->oprs[c];
1583             bytes[0] = nasm_regvals[opx->basereg] << 4;
1584             out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1585             offset++;
1586             break;
1587
1588         case 0250:
1589         case 0251:
1590         case 0252:
1591         case 0253:
1592             data = opx->offset;
1593             /* is_sbyte32() is right here, we have already warned */
1594             if (is_sbyte32(opx)) {
1595                 bytes[0] = data;
1596                 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1597                     NO_SEG);
1598                 offset++;
1599             } else {
1600                 out(offset, segment, &data, OUT_ADDRESS, 4,
1601                     opx->segment, opx->wrt);
1602                 offset += 4;
1603             }
1604             break;
1605
1606         case 0260:
1607         case 0261:
1608         case 0262:
1609         case 0263:
1610         case 0270:
1611             codes += 2;
1612             if (ins->vex_m != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1613                 bytes[0] = 0xc4;
1614                 bytes[1] = ins->vex_m | ((~ins->rex & 7) << 5);
1615                 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1616                     ((~ins->drexdst & 15)<< 3) | (ins->vex_wlp & 07);
1617                 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1618                 offset += 3;
1619             } else {
1620                 bytes[0] = 0xc5;
1621                 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1622                     ((~ins->drexdst & 15) << 3) | (ins->vex_wlp & 07);
1623                 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1624                 offset += 2;
1625             }
1626             break;
1627
1628         case 0300:
1629         case 0301:
1630         case 0302:
1631         case 0303:
1632             break;
1633
1634         case 0310:
1635             if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1636                 *bytes = 0x67;
1637                 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1638                 offset += 1;
1639             } else
1640                 offset += 0;
1641             break;
1642
1643         case 0311:
1644             if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1645                 *bytes = 0x67;
1646                 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1647                 offset += 1;
1648             } else
1649                 offset += 0;
1650             break;
1651
1652         case 0312:
1653             break;
1654
1655         case 0313:
1656             ins->rex = 0;
1657             break;
1658
1659         case 0314:
1660         case 0315:
1661         case 0316:
1662         case 0317:
1663             break;
1664
1665         case 0320:
1666             if (bits != 16) {
1667                 *bytes = 0x66;
1668                 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1669                 offset += 1;
1670             } else
1671                 offset += 0;
1672             break;
1673
1674         case 0321:
1675             if (bits == 16) {
1676                 *bytes = 0x66;
1677                 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1678                 offset += 1;
1679             } else
1680                 offset += 0;
1681             break;
1682
1683         case 0322:
1684         case 0323:
1685             break;
1686
1687         case 0324:
1688             ins->rex |= REX_W;
1689             break;
1690
1691         case 0330:
1692             *bytes = *codes++ ^ condval[ins->condition];
1693             out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1694             offset += 1;
1695             break;
1696
1697         case 0331:
1698             break;
1699
1700         case 0332:
1701         case 0333:
1702             *bytes = c - 0332 + 0xF2;
1703             out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1704             offset += 1;
1705             break;
1706
1707         case 0334:
1708             if (ins->rex & REX_R) {
1709                 *bytes = 0xF0;
1710                 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1711                 offset += 1;
1712             }
1713             ins->rex &= ~(REX_L|REX_R);
1714             break;
1715
1716         case 0335:
1717             break;
1718
1719         case 0336:
1720         case 0337:
1721             break;
1722
1723         case 0340:
1724             if (ins->oprs[0].segment != NO_SEG)
1725                 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1726             else {
1727                 int64_t size = ins->oprs[0].offset;
1728                 if (size > 0)
1729                     out(offset, segment, NULL,
1730                         OUT_RESERVE, size, NO_SEG, NO_SEG);
1731                 offset += size;
1732             }
1733             break;
1734
1735         case 0360:
1736             break;
1737
1738         case 0361:
1739             bytes[0] = 0x66;
1740             out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1741             offset += 1;
1742             break;
1743
1744         case 0362:
1745         case 0363:
1746             bytes[0] = c - 0362 + 0xf2;
1747             out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1748             offset += 1;
1749             break;
1750
1751         case 0364:
1752         case 0365:
1753             break;
1754
1755         case 0366:
1756         case 0367:
1757             *bytes = c - 0366 + 0x66;
1758             out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1759             offset += 1;
1760             break;
1761
1762         case 0370:
1763         case 0371:
1764         case 0372:
1765             break;
1766
1767         case 0373:
1768             *bytes = bits == 16 ? 3 : 5;
1769             out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1770             offset += 1;
1771             break;
1772
1773         default:               /* can't do it by 'case' statements */
1774             if (c >= 0100 && c <= 0277) {       /* it's an EA */
1775                 ea ea_data;
1776                 int rfield;
1777                 int32_t rflags;
1778                 uint8_t *p;
1779                 int32_t s;
1780
1781                 if (c <= 0177) {
1782                     /* pick rfield from operand b */
1783                     rflags = regflag(&ins->oprs[c & 7]);
1784                     rfield = nasm_regvals[ins->oprs[c & 7].basereg];
1785                 } else {
1786                     /* rfield is constant */
1787                     rflags = 0;
1788                     rfield = c & 7;
1789                 }
1790
1791                 if (!process_ea
1792                     (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1793                      ins->addr_size, rfield, rflags)) {
1794                     errfunc(ERR_NONFATAL, "invalid effective address");
1795                 }
1796
1797
1798                 p = bytes;
1799                 *p++ = ea_data.modrm;
1800                 if (ea_data.sib_present)
1801                     *p++ = ea_data.sib;
1802
1803                 /* DREX suffixes come between the SIB and the displacement */
1804                 if (ins->rex & REX_D) {
1805                     *p++ =
1806                         (ins->drexdst << 4) |
1807                         (ins->rex & REX_OC ? 0x08 : 0) |
1808                         (ins->rex & (REX_R|REX_X|REX_B));
1809                     ins->rex = 0;
1810                 }
1811
1812                 s = p - bytes;
1813                 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1814
1815                 /*
1816                  * Make sure the address gets the right offset in case
1817                  * the line breaks in the .lst file (BR 1197827)
1818                  */
1819                 offset += s;
1820                 s = 0;
1821
1822                 switch (ea_data.bytes) {
1823                 case 0:
1824                     break;
1825                 case 1:
1826                     if (ins->oprs[(c >> 3) & 7].segment != NO_SEG) {
1827                         data = ins->oprs[(c >> 3) & 7].offset;
1828                         out(offset, segment, &data, OUT_ADDRESS, 1,
1829                             ins->oprs[(c >> 3) & 7].segment,
1830                             ins->oprs[(c >> 3) & 7].wrt);
1831                     } else {
1832                         *bytes = ins->oprs[(c >> 3) & 7].offset;
1833                         out(offset, segment, bytes, OUT_RAWDATA, 1,
1834                             NO_SEG, NO_SEG);
1835                     }
1836                     s++;
1837                     break;
1838                 case 8:
1839                 case 2:
1840                 case 4:
1841                     data = ins->oprs[(c >> 3) & 7].offset;
1842                     warn_overflow(ea_data.bytes, data);
1843                     out(offset, segment, &data,
1844                         ea_data.rip ?  OUT_REL4ADR : OUT_ADDRESS,
1845                         ea_data.bytes,
1846                         ins->oprs[(c >> 3) & 7].segment,
1847                         ins->oprs[(c >> 3) & 7].wrt);
1848                     s += ea_data.bytes;
1849                     break;
1850                 }
1851                 offset += s;
1852             } else {
1853                 errfunc(ERR_PANIC, "internal instruction table corrupt"
1854                         ": instruction code 0x%02X given", c);
1855             }
1856         }
1857     }
1858 }
1859
1860 static int32_t regflag(const operand * o)
1861 {
1862     if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1863         errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1864     }
1865     return nasm_reg_flags[o->basereg];
1866 }
1867
1868 static int32_t regval(const operand * o)
1869 {
1870     if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1871         errfunc(ERR_PANIC, "invalid operand passed to regval()");
1872     }
1873     return nasm_regvals[o->basereg];
1874 }
1875
1876 static int op_rexflags(const operand * o, int mask)
1877 {
1878     int32_t flags;
1879     int val;
1880
1881     if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1882         errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1883     }
1884
1885     flags = nasm_reg_flags[o->basereg];
1886     val = nasm_regvals[o->basereg];
1887
1888     return rexflags(val, flags, mask);
1889 }
1890
1891 static int rexflags(int val, int32_t flags, int mask)
1892 {
1893     int rex = 0;
1894
1895     if (val >= 8)
1896         rex |= REX_B|REX_X|REX_R;
1897     if (flags & BITS64)
1898         rex |= REX_W;
1899     if (!(REG_HIGH & ~flags))   /* AH, CH, DH, BH */
1900         rex |= REX_H;
1901     else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1902         rex |= REX_P;
1903
1904     return rex & mask;
1905 }
1906
1907 static int matches(const struct itemplate *itemp, insn * instruction, int bits)
1908 {
1909     int i, size[MAX_OPERANDS], asize, oprs, ret;
1910
1911     ret = 100;
1912
1913     /*
1914      * Check the opcode
1915      */
1916     if (itemp->opcode != instruction->opcode)
1917         return 0;
1918
1919     /*
1920      * Count the operands
1921      */
1922     if (itemp->operands != instruction->operands)
1923         return 0;
1924
1925     /*
1926      * Check that no spurious colons or TOs are present
1927      */
1928     for (i = 0; i < itemp->operands; i++)
1929         if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
1930             return 0;
1931
1932     /*
1933      * Process size flags
1934      */
1935     if (itemp->flags & IF_ARMASK) {
1936         memset(size, 0, sizeof size);
1937
1938         i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
1939
1940         switch (itemp->flags & IF_SMASK) {
1941         case IF_SB:
1942             size[i] = BITS8;
1943             break;
1944         case IF_SW:
1945             size[i] = BITS16;
1946             break;
1947         case IF_SD:
1948             size[i] = BITS32;
1949             break;
1950         case IF_SQ:
1951             size[i] = BITS64;
1952             break;
1953         case IF_SO:
1954             size[i] = BITS128;
1955             break;
1956         case IF_SY:
1957             size[i] = BITS256;
1958             break;
1959         case IF_SZ:
1960             switch (bits) {
1961             case 16:
1962                 size[i] = BITS16;
1963                 break;
1964             case 32:
1965                 size[i] = BITS32;
1966                 break;
1967             case 64:
1968                 size[i] = BITS64;
1969                 break;
1970             }
1971             break;
1972         default:
1973             break;
1974         }
1975     } else {
1976         asize = 0;
1977         switch (itemp->flags & IF_SMASK) {
1978         case IF_SB:
1979             asize = BITS8;
1980             break;
1981         case IF_SW:
1982             asize = BITS16;
1983             break;
1984         case IF_SD:
1985             asize = BITS32;
1986             break;
1987         case IF_SQ:
1988             asize = BITS64;
1989             break;
1990         case IF_SO:
1991             asize = BITS128;
1992             break;
1993         case IF_SY:
1994             asize = BITS256;
1995             break;
1996         case IF_SZ:
1997             switch (bits) {
1998             case 16:
1999                 asize = BITS16;
2000                 break;
2001             case 32:
2002                 asize = BITS32;
2003                 break;
2004             case 64:
2005                 asize = BITS64;
2006                 break;
2007             }
2008             break;
2009         default:
2010             break;
2011         }
2012         for (i = 0; i < MAX_OPERANDS; i++)
2013             size[i] = asize;
2014     }
2015
2016     /*
2017      * Check that the operand flags all match up
2018      */
2019     for (i = 0; i < itemp->operands; i++) {
2020         int32_t type = instruction->oprs[i].type;
2021         if (!(type & SIZE_MASK))
2022             type |= size[i];
2023
2024         if (itemp->opd[i] & SAME_AS) {
2025             int j = itemp->opd[i] & ~SAME_AS;
2026             if (type != instruction->oprs[j].type ||
2027                 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
2028                 return 0;
2029         } else if (itemp->opd[i] & ~type ||
2030             ((itemp->opd[i] & SIZE_MASK) &&
2031              ((itemp->opd[i] ^ type) & SIZE_MASK))) {
2032             if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2033                 (type & SIZE_MASK))
2034                 return 0;
2035             else
2036                 return 1;
2037         }
2038     }
2039
2040     /*
2041      * Check operand sizes
2042      */
2043     if (itemp->flags & (IF_SM | IF_SM2)) {
2044         oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2045         asize = 0;
2046         for (i = 0; i < oprs; i++) {
2047             if ((asize = itemp->opd[i] & SIZE_MASK) != 0) {
2048                 int j;
2049                 for (j = 0; j < oprs; j++)
2050                     size[j] = asize;
2051                 break;
2052             }
2053         }
2054     } else {
2055         oprs = itemp->operands;
2056     }
2057
2058     for (i = 0; i < itemp->operands; i++) {
2059         if (!(itemp->opd[i] & SIZE_MASK) &&
2060             (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2061             return 2;
2062     }
2063
2064     /*
2065      * Check template is okay at the set cpu level
2066      */
2067     if (((itemp->flags & IF_PLEVEL) > cpu))
2068         return 3;
2069
2070     /*
2071      * Check if instruction is available in long mode
2072      */
2073     if ((itemp->flags & IF_NOLONG) && (bits == 64))
2074         return 4;
2075
2076     /*
2077      * Check if special handling needed for Jumps
2078      */
2079     if ((uint8_t)(itemp->code[0]) >= 0370)
2080         return 99;
2081
2082     return ret;
2083 }
2084
2085 static ea *process_ea(operand * input, ea * output, int bits,
2086                       int addrbits, int rfield, int32_t rflags)
2087 {
2088     bool forw_ref = !!(input->opflags & OPFLAG_FORWARD);
2089
2090     output->rip = false;
2091
2092     /* REX flags for the rfield operand */
2093     output->rex |= rexflags(rfield, rflags, REX_R|REX_P|REX_W|REX_H);
2094
2095     if (!(REGISTER & ~input->type)) {   /* register direct */
2096         int i;
2097         int32_t f;
2098
2099         if (input->basereg < EXPR_REG_START /* Verify as Register */
2100             || input->basereg >= REG_ENUM_LIMIT)
2101             return NULL;
2102         f = regflag(input);
2103         i = nasm_regvals[input->basereg];
2104
2105         if (REG_EA & ~f)
2106             return NULL;        /* Invalid EA register */
2107
2108         output->rex |= op_rexflags(input, REX_B|REX_P|REX_W|REX_H);
2109
2110         output->sib_present = false;             /* no SIB necessary */
2111         output->bytes = 0;  /* no offset necessary either */
2112         output->modrm = 0xC0 | ((rfield & 7) << 3) | (i & 7);
2113     } else {                    /* it's a memory reference */
2114         if (input->basereg == -1
2115             && (input->indexreg == -1 || input->scale == 0)) {
2116             /* it's a pure offset */
2117             if (bits == 64 && (~input->type & IP_REL)) {
2118               int scale, index, base;
2119               output->sib_present = true;
2120               scale = 0;
2121               index = 4;
2122               base = 5;
2123               output->sib = (scale << 6) | (index << 3) | base;
2124               output->bytes = 4;
2125               output->modrm = 4 | ((rfield & 7) << 3);
2126               output->rip = false;
2127             } else {
2128               output->sib_present = false;
2129               output->bytes = (addrbits != 16 ? 4 : 2);
2130               output->modrm = (addrbits != 16 ? 5 : 6) | ((rfield & 7) << 3);
2131               output->rip = bits == 64;
2132             }
2133         } else {                /* it's an indirection */
2134             int i = input->indexreg, b = input->basereg, s = input->scale;
2135             int32_t o = input->offset, seg = input->segment;
2136             int hb = input->hintbase, ht = input->hinttype;
2137             int t;
2138             int it, bt;
2139             int32_t ix, bx;     /* register flags */
2140
2141             if (s == 0)
2142                 i = -1;         /* make this easy, at least */
2143
2144             if (i >= EXPR_REG_START && i < REG_ENUM_LIMIT) {
2145                 it = nasm_regvals[i];
2146                 ix = nasm_reg_flags[i];
2147             } else {
2148                 it = -1;
2149                 ix = 0;
2150             }
2151
2152             if (b >= EXPR_REG_START && b < REG_ENUM_LIMIT) {
2153                 bt = nasm_regvals[b];
2154                 bx = nasm_reg_flags[b];
2155             } else {
2156                 bt = -1;
2157                 bx = 0;
2158             }
2159
2160             /* check for a 32/64-bit memory reference... */
2161             if ((ix|bx) & (BITS32|BITS64)) {
2162                 /* it must be a 32/64-bit memory reference. Firstly we have
2163                  * to check that all registers involved are type E/Rxx. */
2164                 int32_t sok = BITS32|BITS64;
2165
2166                 if (it != -1) {
2167                     if (!(REG64 & ~ix) || !(REG32 & ~ix))
2168                         sok &= ix;
2169                     else
2170                         return NULL;
2171                 }
2172
2173                 if (bt != -1) {
2174                     if (REG_GPR & ~bx)
2175                         return NULL; /* Invalid register */
2176                     if (~sok & bx & SIZE_MASK)
2177                         return NULL; /* Invalid size */
2178                     sok &= bx;
2179                 }
2180
2181                 /* While we're here, ensure the user didn't specify
2182                    WORD or QWORD. */
2183                 if (input->disp_size == 16 || input->disp_size == 64)
2184                     return NULL;
2185
2186                 if (addrbits == 16 ||
2187                     (addrbits == 32 && !(sok & BITS32)) ||
2188                     (addrbits == 64 && !(sok & BITS64)))
2189                     return NULL;
2190
2191                 /* now reorganize base/index */
2192                 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2193                     ((hb == b && ht == EAH_NOTBASE)
2194                      || (hb == i && ht == EAH_MAKEBASE))) {
2195                     /* swap if hints say so */
2196                     t = bt, bt = it, it = t;
2197                     t = bx, bx = ix, ix = t;
2198                 }
2199                 if (bt == it)     /* convert EAX+2*EAX to 3*EAX */
2200                     bt = -1, bx = 0, s++;
2201                 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2202                     /* make single reg base, unless hint */
2203                     bt = it, bx = ix, it = -1, ix = 0;
2204                 }
2205                 if (((s == 2 && it != REG_NUM_ESP
2206                       && !(input->eaflags & EAF_TIMESTWO)) || s == 3
2207                      || s == 5 || s == 9) && bt == -1)
2208                     bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2209                 if (it == -1 && (bt & 7) != REG_NUM_ESP
2210                     && (input->eaflags & EAF_TIMESTWO))
2211                     it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2212                 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2213                 if (s == 1 && it == REG_NUM_ESP) {
2214                     /* swap ESP into base if scale is 1 */
2215                     t = it, it = bt, bt = t;
2216                     t = ix, ix = bx, bx = t;
2217                 }
2218                 if (it == REG_NUM_ESP
2219                     || (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2220                     return NULL;        /* wrong, for various reasons */
2221
2222                 output->rex |= rexflags(it, ix, REX_X);
2223                 output->rex |= rexflags(bt, bx, REX_B);
2224
2225                 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2226                     /* no SIB needed */
2227                     int mod, rm;
2228
2229                     if (bt == -1) {
2230                         rm = 5;
2231                         mod = 0;
2232                     } else {
2233                         rm = (bt & 7);
2234                         if (rm != REG_NUM_EBP && o == 0 &&
2235                                 seg == NO_SEG && !forw_ref &&
2236                                 !(input->eaflags &
2237                                   (EAF_BYTEOFFS | EAF_WORDOFFS)))
2238                             mod = 0;
2239                         else if (input->eaflags & EAF_BYTEOFFS ||
2240                                  (o >= -128 && o <= 127 && seg == NO_SEG
2241                                   && !forw_ref
2242                                   && !(input->eaflags & EAF_WORDOFFS)))
2243                             mod = 1;
2244                         else
2245                             mod = 2;
2246                     }
2247
2248                     output->sib_present = false;
2249                     output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2250                     output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2251                 } else {
2252                     /* we need a SIB */
2253                     int mod, scale, index, base;
2254
2255                     if (it == -1)
2256                         index = 4, s = 1;
2257                     else
2258                         index = (it & 7);
2259
2260                     switch (s) {
2261                     case 1:
2262                         scale = 0;
2263                         break;
2264                     case 2:
2265                         scale = 1;
2266                         break;
2267                     case 4:
2268                         scale = 2;
2269                         break;
2270                     case 8:
2271                         scale = 3;
2272                         break;
2273                     default:   /* then what the smeg is it? */
2274                         return NULL;    /* panic */
2275                     }
2276
2277                     if (bt == -1) {
2278                         base = 5;
2279                         mod = 0;
2280                     } else {
2281                         base = (bt & 7);
2282                         if (base != REG_NUM_EBP && o == 0 &&
2283                                     seg == NO_SEG && !forw_ref &&
2284                                     !(input->eaflags &
2285                                       (EAF_BYTEOFFS | EAF_WORDOFFS)))
2286                             mod = 0;
2287                         else if (input->eaflags & EAF_BYTEOFFS ||
2288                                  (o >= -128 && o <= 127 && seg == NO_SEG
2289                                   && !forw_ref
2290                                   && !(input->eaflags & EAF_WORDOFFS)))
2291                             mod = 1;
2292                         else
2293                             mod = 2;
2294                     }
2295
2296                     output->sib_present = true;
2297                     output->bytes =  (bt == -1 || mod == 2 ? 4 : mod);
2298                     output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2299                     output->sib = (scale << 6) | (index << 3) | base;
2300                 }
2301             } else {            /* it's 16-bit */
2302                 int mod, rm;
2303
2304                 /* check for 64-bit long mode */
2305                 if (addrbits == 64)
2306                     return NULL;
2307
2308                 /* check all registers are BX, BP, SI or DI */
2309                 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI
2310                      && b != R_DI) || (i != -1 && i != R_BP && i != R_BX
2311                                        && i != R_SI && i != R_DI))
2312                     return NULL;
2313
2314                 /* ensure the user didn't specify DWORD/QWORD */
2315                 if (input->disp_size == 32 || input->disp_size == 64)
2316                     return NULL;
2317
2318                 if (s != 1 && i != -1)
2319                     return NULL;        /* no can do, in 16-bit EA */
2320                 if (b == -1 && i != -1) {
2321                     int tmp = b;
2322                     b = i;
2323                     i = tmp;
2324                 }               /* swap */
2325                 if ((b == R_SI || b == R_DI) && i != -1) {
2326                     int tmp = b;
2327                     b = i;
2328                     i = tmp;
2329                 }
2330                 /* have BX/BP as base, SI/DI index */
2331                 if (b == i)
2332                     return NULL;        /* shouldn't ever happen, in theory */
2333                 if (i != -1 && b != -1 &&
2334                     (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2335                     return NULL;        /* invalid combinations */
2336                 if (b == -1)    /* pure offset: handled above */
2337                     return NULL;        /* so if it gets to here, panic! */
2338
2339                 rm = -1;
2340                 if (i != -1)
2341                     switch (i * 256 + b) {
2342                     case R_SI * 256 + R_BX:
2343                         rm = 0;
2344                         break;
2345                     case R_DI * 256 + R_BX:
2346                         rm = 1;
2347                         break;
2348                     case R_SI * 256 + R_BP:
2349                         rm = 2;
2350                         break;
2351                     case R_DI * 256 + R_BP:
2352                         rm = 3;
2353                         break;
2354                 } else
2355                     switch (b) {
2356                     case R_SI:
2357                         rm = 4;
2358                         break;
2359                     case R_DI:
2360                         rm = 5;
2361                         break;
2362                     case R_BP:
2363                         rm = 6;
2364                         break;
2365                     case R_BX:
2366                         rm = 7;
2367                         break;
2368                     }
2369                 if (rm == -1)   /* can't happen, in theory */
2370                     return NULL;        /* so panic if it does */
2371
2372                 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2373                     !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2374                     mod = 0;
2375                 else if (input->eaflags & EAF_BYTEOFFS ||
2376                          (o >= -128 && o <= 127 && seg == NO_SEG
2377                           && !forw_ref
2378                           && !(input->eaflags & EAF_WORDOFFS)))
2379                     mod = 1;
2380                 else
2381                     mod = 2;
2382
2383                 output->sib_present = false;    /* no SIB - it's 16-bit */
2384                 output->bytes = mod;    /* bytes of offset needed */
2385                 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2386             }
2387         }
2388     }
2389
2390     output->size = 1 + output->sib_present + output->bytes;
2391     return output;
2392 }
2393
2394 static void add_asp(insn *ins, int addrbits)
2395 {
2396     int j, valid;
2397     int defdisp;
2398
2399     valid = (addrbits == 64) ? 64|32 : 32|16;
2400
2401     switch (ins->prefixes[PPS_ASIZE]) {
2402     case P_A16:
2403         valid &= 16;
2404         break;
2405     case P_A32:
2406         valid &= 32;
2407         break;
2408     case P_A64:
2409         valid &= 64;
2410         break;
2411     case P_ASP:
2412         valid &= (addrbits == 32) ? 16 : 32;
2413         break;
2414     default:
2415         break;
2416     }
2417
2418     for (j = 0; j < ins->operands; j++) {
2419         if (!(MEMORY & ~ins->oprs[j].type)) {
2420             int32_t i, b;
2421
2422             /* Verify as Register */
2423             if (ins->oprs[j].indexreg < EXPR_REG_START
2424                 || ins->oprs[j].indexreg >= REG_ENUM_LIMIT)
2425                 i = 0;
2426             else
2427                 i = nasm_reg_flags[ins->oprs[j].indexreg];
2428
2429             /* Verify as Register */
2430             if (ins->oprs[j].basereg < EXPR_REG_START
2431                 || ins->oprs[j].basereg >= REG_ENUM_LIMIT)
2432                 b = 0;
2433             else
2434                 b = nasm_reg_flags[ins->oprs[j].basereg];
2435
2436             if (ins->oprs[j].scale == 0)
2437                 i = 0;
2438
2439             if (!i && !b) {
2440                 int ds = ins->oprs[j].disp_size;
2441                 if ((addrbits != 64 && ds > 8) ||
2442                     (addrbits == 64 && ds == 16))
2443                     valid &= ds;
2444             } else {
2445                 if (!(REG16 & ~b))
2446                     valid &= 16;
2447                 if (!(REG32 & ~b))
2448                     valid &= 32;
2449                 if (!(REG64 & ~b))
2450                     valid &= 64;
2451
2452                 if (!(REG16 & ~i))
2453                     valid &= 16;
2454                 if (!(REG32 & ~i))
2455                     valid &= 32;
2456                 if (!(REG64 & ~i))
2457                     valid &= 64;
2458             }
2459         }
2460     }
2461
2462     if (valid & addrbits) {
2463         ins->addr_size = addrbits;
2464     } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2465         /* Add an address size prefix */
2466         enum prefixes pref = (addrbits == 32) ? P_A16 : P_A32;
2467         ins->prefixes[PPS_ASIZE] = pref;
2468         ins->addr_size = (addrbits == 32) ? 16 : 32;
2469     } else {
2470         /* Impossible... */
2471         errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2472         ins->addr_size = addrbits; /* Error recovery */
2473     }
2474
2475     defdisp = ins->addr_size == 16 ? 16 : 32;
2476
2477     for (j = 0; j < ins->operands; j++) {
2478         if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2479             (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp)
2480             != ins->addr_size) {
2481             /* mem_offs sizes must match the address size; if not,
2482                strip the MEM_OFFS bit and match only EA instructions */
2483             ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2484         }
2485     }
2486 }