insns.h

   1 /* insns.h   header file for insns.c
   2  *
   3  * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
   4  * Julian Hall. All rights reserved. The software is
   5  * redistributable under the license given in the file "LICENSE"
   6  * distributed in the NASM archive.
   7  */
   8
   9 #ifndef NASM_INSNS_H
  10 #define NASM_INSNS_H
  11
  12 #include "nasm.h"
  13 #include "tokens.h"
  14
  15 struct itemplate {
  16     enum opcode opcode;         /* the token, passed from "parser.c" */
  17     int operands;               /* number of operands */
  18     opflags_t opd[MAX_OPERANDS]; /* bit flags for operand types */
  19     const uint8_t *code;        /* the code it assembles to */
  20     uint32_t flags;             /* some flags */
  21 };
  22
  23 /* Disassembler table structure */
  24 /* If n == -1, then p points to another table of 256
  25    struct disasm_index, otherwise p points to a list of n
  26    struct itemplates to consider. */
  27 struct disasm_index {
  28     const void *p;
  29     int n;
  30 };
  31
  32 /* Tables for the assembler and disassembler, respectively */
  33 extern const struct itemplate * const nasm_instructions[];
  34 extern const struct disasm_index itable[256];
  35 extern const struct disasm_index * const itable_VEX[32][8];
  36
  37 /* Common table for the byte codes */
  38 extern const uint8_t nasm_bytecodes[];
  39
  40 /*
  41  * this define is used to signify the end of an itemplate
  42  */
  43 #define ITEMPLATE_END {-1,-1,{-1,-1,-1},NULL,0}
  44
  45 /*
  46  * Instruction template flags. These specify which processor
  47  * targets the instruction is eligible for, whether it is
  48  * privileged or undocumented, and also specify extra error
  49  * checking on the matching of the instruction.
  50  *
  51  * IF_SM stands for Size Match: any operand whose size is not
  52  * explicitly specified by the template is `really' intended to be
  53  * the same size as the first size-specified operand.
  54  * Non-specification is tolerated in the input instruction, but
  55  * _wrong_ specification is not.
  56  *
  57  * IF_SM2 invokes Size Match on only the first _two_ operands, for
  58  * three-operand instructions such as SHLD: it implies that the
  59  * first two operands must match in size, but that the third is
  60  * required to be _unspecified_.
  61  *
  62  * IF_SB invokes Size Byte: operands with unspecified size in the
  63  * template are really bytes, and so no non-byte specification in
  64  * the input instruction will be tolerated. IF_SW similarly invokes
  65  * Size Word, and IF_SD invokes Size Doubleword.
  66  *
  67  * (The default state if neither IF_SM nor IF_SM2 is specified is
  68  * that any operand with unspecified size in the template is
  69  * required to have unspecified size in the instruction too...)
  70  */
  71
  72 #define IF_SM     0x00000001UL  /* size match */
  73 #define IF_SM2    0x00000002UL  /* size match first two operands */
  74 #define IF_SB     0x00000004UL  /* unsized operands can't be non-byte */
  75 #define IF_SW     0x00000008UL  /* unsized operands can't be non-word */
  76 #define IF_SD     0x0000000CUL  /* unsized operands can't be non-dword */
  77 #define IF_SQ     0x00000010UL  /* unsized operands can't be non-qword */
  78 #define IF_SO     0x00000014UL  /* unsized operands can't be non-oword */
  79 #define IF_SY     0x00000018UL  /* unsized operands can't be non-yword */
  80 #define IF_SZ     0x0000001CUL  /* unsized operands must match the bitsize */
  81 #define IF_SMASK  0x0000001CUL  /* mask for unsized argument size */
  82 #define IF_AR0    0x00000020UL  /* SB, SW, SD applies to argument 0 */
  83 #define IF_AR1    0x00000040UL  /* SB, SW, SD applies to argument 1 */
  84 #define IF_AR2    0x00000060UL  /* SB, SW, SD applies to argument 2 */
  85 #define IF_AR3    0x00000080UL  /* SB, SW, SD applies to argument 3 */
  86 #define IF_ARMASK 0x000000E0UL  /* mask for unsized argument spec */
  87 #define IF_ARSHFT 5             /* LSB in IF_ARMASK */
  88 #define IF_PRIV   0x00000100UL  /* it's a privileged instruction */
  89 #define IF_SMM    0x00000200UL  /* it's only valid in SMM */
  90 #define IF_PROT   0x00000400UL  /* it's protected mode only */
  91 #define IF_NOLONG 0x00000800UL  /* it's not available in long mode */
  92 #define IF_UNDOC  0x00001000UL  /* it's an undocumented instruction */
  93 #define IF_FPU    0x00002000UL  /* it's an FPU instruction */
  94 #define IF_MMX    0x00004000UL  /* it's an MMX instruction */
  95 #define IF_3DNOW  0x00008000UL  /* it's a 3DNow! instruction */
  96 #define IF_SSE    0x00010000UL  /* it's a SSE (KNI, MMX2) instruction */
  97 #define IF_SSE2   0x00020000UL  /* it's a SSE2 instruction */
  98 #define IF_SSE3   0x00040000UL  /* it's a SSE3 (PNI) instruction */
  99 #define IF_VMX    0x00080000UL  /* it's a VMX instruction */
 100 #define IF_LONG   0x00100000UL  /* long mode instruction */
 101 #define IF_SSSE3  0x00200000UL  /* it's an SSSE3 instruction */
 102 #define IF_SSE4A  0x00400000UL  /* AMD SSE4a */
 103 #define IF_SSE41  0x00800000UL  /* it's an SSE4.1 instruction */
 104 #define IF_SSE42  0x00800000UL  /* HACK NEED TO REORGANIZE THESE BITS */
 105 #define IF_SSE5   0x00800000UL  /* HACK NEED TO REORGANIZE THESE BITS */
 106 #define IF_AVX    0x00800000UL  /* HACK NEED TO REORGANIZE THESE BITS */
 107 #define IF_FMA    0x00800000UL  /* HACK NEED TO REORGANIZE THESE BITS */
 108 #define IF_PMASK  0xFF000000UL  /* the mask for processor types */
 109 #define IF_PLEVEL 0x0F000000UL  /* the mask for processor instr. level */
 110                                 /* also the highest possible processor */
 111 #define IF_PFMASK 0xF01FFF00UL  /* the mask for disassembly "prefer" */
 112 #define IF_8086   0x00000000UL  /* 8086 instruction */
 113 #define IF_186    0x01000000UL  /* 186+ instruction */
 114 #define IF_286    0x02000000UL  /* 286+ instruction */
 115 #define IF_386    0x03000000UL  /* 386+ instruction */
 116 #define IF_486    0x04000000UL  /* 486+ instruction */
 117 #define IF_PENT   0x05000000UL  /* Pentium instruction */
 118 #define IF_P6     0x06000000UL  /* P6 instruction */
 119 #define IF_KATMAI 0x07000000UL  /* Katmai instructions */
 120 #define IF_WILLAMETTE 0x08000000UL      /* Willamette instructions */
 121 #define IF_PRESCOTT   0x09000000UL      /* Prescott instructions */
 122 #define IF_X86_64 0x0A000000UL  /* x86-64 instruction (long or legacy mode) */
 123 #define IF_NEHALEM 0x0B000000UL  /* Nehalem instruction */
 124 #define IF_WESTMERE 0x0C000000UL   /* Westmere instruction */
 125 #define IF_SANDYBRIDGE 0x0D000000UL /* Sandy Bridge instruction */
 126 #define IF_FUTURE 0x0E000000UL  /* Future processor (not yet disclosed) */
 127 #define IF_X64    (IF_LONG|IF_X86_64)
 128 #define IF_IA64   0x0F000000UL  /* IA64 instructions (in x86 mode) */
 129 #define IF_CYRIX  0x10000000UL  /* Cyrix-specific instruction */
 130 #define IF_AMD    0x20000000UL  /* AMD-specific instruction */
 131
 132 #endif