1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2009 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * assemble.c code generation for the Netwide Assembler
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - a signed byte immediate operand, from operand 0..3
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \140..\143 - an immediate word or signed byte for operand 0..3
64 * \144..\147 - or 2 (s-field) into opcode byte if operand 0..3
65 * is a signed byte rather than a word. Opcode byte follows.
66 * \150..\153 - an immediate dword or signed byte for operand 0..3
67 * \154..\157 - or 2 (s-field) into opcode byte if operand 0..3
68 * is a signed byte rather than a dword. Opcode byte follows.
69 * \160..\163 - this instruction uses DREX rather than REX, with the
70 * OC0 field set to 0, and the dest field taken from
72 * \164..\167 - this instruction uses DREX rather than REX, with the
73 * OC0 field set to 1, and the dest field taken from
75 * \171 - placement of DREX suffix in the absence of an EA
76 * \172\ab - the register number from operand a in bits 7..4, with
77 * the 4-bit immediate from operand b in bits 3..0.
78 * \173\xab - the register number from operand a in bits 7..4, with
79 * the value b in bits 3..0.
80 * \174\a - the register number from operand a in bits 7..4, and
81 * an arbitrary value in bits 3..0 (assembled as zero.)
82 * \2ab - a ModRM, calculated on EA in operand a, with the spare
83 * field equal to digit b.
84 * \250..\253 - same as \150..\153, except warn if the 64-bit operand
85 * is not equal to the truncated and sign-extended 32-bit
86 * operand; used for 32-bit immediates in 64-bit mode.
87 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
88 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
89 * V field taken from operand 0..3.
90 * \270 - this instruction uses VEX/XOP rather than REX, with the
91 * V field set to 1111b.
93 * VEX/XOP prefixes are followed by the sequence:
94 * \tmm\wlp where mm is the M field; and wlp is:
96 * [w0] ww = 0 for W = 0
97 * [w1] ww = 1 for W = 1
98 * [wx] ww = 2 for W don't care (always assembled as 0)
99 * [ww] ww = 3 for W used as REX.W
101 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
103 * \274..\277 - a signed byte immediate operand, from operand 0..3,
104 * which is to be extended to the operand size.
105 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
106 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
107 * \312 - (disassembler only) invalid with non-default address size.
108 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
109 * \314 - (disassembler only) invalid with REX.B
110 * \315 - (disassembler only) invalid with REX.X
111 * \316 - (disassembler only) invalid with REX.R
112 * \317 - (disassembler only) invalid with REX.W
113 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
114 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
115 * \322 - indicates that this instruction is only valid when the
116 * operand size is the default (instruction to disassembler,
117 * generates no code in the assembler)
118 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
119 * \324 - indicates 64-bit operand size requiring REX prefix.
120 * \325 - instruction which always uses spl/bpl/sil/dil
121 * \330 - a literal byte follows in the code stream, to be added
122 * to the condition code value of the instruction.
123 * \331 - instruction not valid with REP prefix. Hint for
124 * disassembler only; for SSE instructions.
125 * \332 - REP prefix (0xF2 byte) used as opcode extension.
126 * \333 - REP prefix (0xF3 byte) used as opcode extension.
127 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
128 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
129 * \336 - force a REP(E) prefix (0xF2) even if not specified.
130 * \337 - force a REPNE prefix (0xF3) even if not specified.
131 * \336-\337 are still listed as prefixes in the disassembler.
132 * \340 - reserve <operand 0> bytes of uninitialized storage.
133 * Operand 0 had better be a segmentless constant.
134 * \341 - this instruction needs a WAIT "prefix"
135 * \344,\345 - the PUSH/POP (respectively) codes for CS, DS, ES, SS
136 * (POP is never used for CS) depending on operand 0
137 * \346,\347 - the second byte of PUSH/POP codes for FS, GS, depending
139 * \360 - no SSE prefix (== \364\331)
140 * \361 - 66 SSE prefix (== \366\331)
141 * \362 - F2 SSE prefix (== \364\332)
142 * \363 - F3 SSE prefix (== \364\333)
143 * \364 - operand-size prefix (0x66) not permitted
144 * \365 - address-size prefix (0x67) not permitted
145 * \366 - operand-size prefix (0x66) used as opcode extension
146 * \367 - address-size prefix (0x67) used as opcode extension
147 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
148 * 370 is used for Jcc, 371 is used for JMP.
149 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
150 * used for conditional jump over longer jump
153 #include "compiler.h"
157 #include <inttypes.h>
161 #include "assemble.h"
167 * Matching errors. These should be sorted so that more specific
168 * errors come later in the sequence.
176 * Matching success; the conditional ones first
178 MOK_JUMP
, /* Matching OK but needs jmp_match() */
179 MOK_GOOD
/* Matching unconditionally OK */
183 int sib_present
; /* is a SIB byte necessary? */
184 int bytes
; /* # of bytes of offset needed */
185 int size
; /* lazy - this is sib+bytes+1 */
186 uint8_t modrm
, sib
, rex
, rip
; /* the bytes themselves */
189 static uint32_t cpu
; /* cpu level received from nasm.c */
190 static efunc errfunc
;
191 static struct ofmt
*outfmt
;
192 static ListGen
*list
;
194 static int64_t calcsize(int32_t, int64_t, int, insn
*, const uint8_t *);
195 static void gencode(int32_t segment
, int64_t offset
, int bits
,
196 insn
* ins
, const struct itemplate
*temp
,
198 static enum match_result
find_match(const struct itemplate
**tempp
,
200 int32_t segment
, int64_t offset
, int bits
);
201 static enum match_result
matches(const struct itemplate
*, insn
*, int bits
);
202 static opflags_t
regflag(const operand
*);
203 static int32_t regval(const operand
*);
204 static int rexflags(int, opflags_t
, int);
205 static int op_rexflags(const operand
*, int);
206 static ea
*process_ea(operand
*, ea
*, int, int, int, opflags_t
);
207 static void add_asp(insn
*, int);
209 static int has_prefix(insn
* ins
, enum prefix_pos pos
, enum prefixes prefix
)
211 return ins
->prefixes
[pos
] == prefix
;
214 static void assert_no_prefix(insn
* ins
, enum prefix_pos pos
)
216 if (ins
->prefixes
[pos
])
217 errfunc(ERR_NONFATAL
, "invalid %s prefix",
218 prefix_name(ins
->prefixes
[pos
]));
221 static const char *size_name(int size
)
243 static void warn_overflow(int pass
, int size
)
245 errfunc(ERR_WARNING
| pass
| ERR_WARN_NOV
,
246 "%s data exceeds bounds", size_name(size
));
249 static void warn_overflow_const(int64_t data
, int size
)
251 if (overflow_general(data
, size
))
252 warn_overflow(ERR_PASS1
, size
);
255 static void warn_overflow_opd(const struct operand
*o
, int size
)
257 if (o
->wrt
== NO_SEG
&& o
->segment
== NO_SEG
) {
258 if (overflow_general(o
->offset
, size
))
259 warn_overflow(ERR_PASS2
, size
);
264 * This routine wrappers the real output format's output routine,
265 * in order to pass a copy of the data off to the listing file
266 * generator at the same time.
268 static void out(int64_t offset
, int32_t segto
, const void *data
,
269 enum out_type type
, uint64_t size
,
270 int32_t segment
, int32_t wrt
)
272 static int32_t lineno
= 0; /* static!!! */
273 static char *lnfname
= NULL
;
276 if (type
== OUT_ADDRESS
&& segment
== NO_SEG
&& wrt
== NO_SEG
) {
278 * This is a non-relocated address, and we're going to
279 * convert it into RAWDATA format.
284 errfunc(ERR_PANIC
, "OUT_ADDRESS with size > 8");
288 WRITEADDR(q
, *(int64_t *)data
, size
);
293 list
->output(offset
, data
, type
, size
);
296 * this call to src_get determines when we call the
297 * debug-format-specific "linenum" function
298 * it updates lineno and lnfname to the current values
299 * returning 0 if "same as last time", -2 if lnfname
300 * changed, and the amount by which lineno changed,
301 * if it did. thus, these variables must be static
304 if (src_get(&lineno
, &lnfname
)) {
305 outfmt
->current_dfmt
->linenum(lnfname
, lineno
, segto
);
308 outfmt
->output(segto
, data
, type
, size
, segment
, wrt
);
311 static bool jmp_match(int32_t segment
, int64_t offset
, int bits
,
312 insn
* ins
, const uint8_t *code
)
317 if ((c
!= 0370 && c
!= 0371) || (ins
->oprs
[0].type
& STRICT
))
321 if (optimizing
< 0 && c
== 0371)
324 isize
= calcsize(segment
, offset
, bits
, ins
, code
);
326 if (ins
->oprs
[0].opflags
& OPFLAG_UNKNOWN
)
327 /* Be optimistic in pass 1 */
330 if (ins
->oprs
[0].segment
!= segment
)
333 isize
= ins
->oprs
[0].offset
- offset
- isize
; /* isize is delta */
334 return (isize
>= -128 && isize
<= 127); /* is it byte size? */
337 int64_t assemble(int32_t segment
, int64_t offset
, int bits
, uint32_t cp
,
338 insn
* instruction
, struct ofmt
*output
, efunc error
,
341 const struct itemplate
*temp
;
346 int64_t start
= offset
;
347 int64_t wsize
; /* size for DB etc. */
349 errfunc
= error
; /* to pass to other functions */
351 outfmt
= output
; /* likewise */
352 list
= listgen
; /* and again */
354 wsize
= idata_bytes(instruction
->opcode
);
360 int32_t t
= instruction
->times
;
363 "instruction->times < 0 (%ld) in assemble()", t
);
365 while (t
--) { /* repeat TIMES times */
366 list_for_each(e
, instruction
->eops
) {
367 if (e
->type
== EOT_DB_NUMBER
) {
369 errfunc(ERR_NONFATAL
,
370 "integer supplied to a DT, DO or DY"
373 out(offset
, segment
, &e
->offset
,
374 OUT_ADDRESS
, wsize
, e
->segment
, e
->wrt
);
377 } else if (e
->type
== EOT_DB_STRING
||
378 e
->type
== EOT_DB_STRING_FREE
) {
381 out(offset
, segment
, e
->stringval
,
382 OUT_RAWDATA
, e
->stringlen
, NO_SEG
, NO_SEG
);
383 align
= e
->stringlen
% wsize
;
386 align
= wsize
- align
;
387 out(offset
, segment
, zero_buffer
,
388 OUT_RAWDATA
, align
, NO_SEG
, NO_SEG
);
390 offset
+= e
->stringlen
+ align
;
393 if (t
> 0 && t
== instruction
->times
- 1) {
395 * Dummy call to list->output to give the offset to the
398 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
399 list
->uplevel(LIST_TIMES
);
402 if (instruction
->times
> 1)
403 list
->downlevel(LIST_TIMES
);
404 return offset
- start
;
407 if (instruction
->opcode
== I_INCBIN
) {
408 const char *fname
= instruction
->eops
->stringval
;
411 fp
= fopen(fname
, "rb");
413 error(ERR_NONFATAL
, "`incbin': unable to open file `%s'",
415 } else if (fseek(fp
, 0L, SEEK_END
) < 0) {
416 error(ERR_NONFATAL
, "`incbin': unable to seek on file `%s'",
419 static char buf
[4096];
420 size_t t
= instruction
->times
;
425 if (instruction
->eops
->next
) {
426 base
= instruction
->eops
->next
->offset
;
428 if (instruction
->eops
->next
->next
&&
429 len
> (size_t)instruction
->eops
->next
->next
->offset
)
430 len
= (size_t)instruction
->eops
->next
->next
->offset
;
433 * Dummy call to list->output to give the offset to the
436 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
437 list
->uplevel(LIST_INCBIN
);
441 fseek(fp
, base
, SEEK_SET
);
445 m
= fread(buf
, 1, l
> sizeof(buf
) ? sizeof(buf
) : l
, fp
);
448 * This shouldn't happen unless the file
449 * actually changes while we are reading
453 "`incbin': unexpected EOF while"
454 " reading file `%s'", fname
);
455 t
= 0; /* Try to exit cleanly */
458 out(offset
, segment
, buf
, OUT_RAWDATA
, m
,
463 list
->downlevel(LIST_INCBIN
);
464 if (instruction
->times
> 1) {
466 * Dummy call to list->output to give the offset to the
469 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
470 list
->uplevel(LIST_TIMES
);
471 list
->downlevel(LIST_TIMES
);
474 return instruction
->times
* len
;
476 return 0; /* if we're here, there's an error */
479 /* Check to see if we need an address-size prefix */
480 add_asp(instruction
, bits
);
482 m
= find_match(&temp
, instruction
, segment
, offset
, bits
);
486 int64_t insn_size
= calcsize(segment
, offset
, bits
,
487 instruction
, temp
->code
);
488 itimes
= instruction
->times
;
489 if (insn_size
< 0) /* shouldn't be, on pass two */
490 error(ERR_PANIC
, "errors made it through from pass one");
493 for (j
= 0; j
< MAXPREFIX
; j
++) {
495 switch (instruction
->prefixes
[j
]) {
513 error(ERR_WARNING
| ERR_PASS2
,
514 "cs segment base generated, but will be ignored in 64-bit mode");
520 error(ERR_WARNING
| ERR_PASS2
,
521 "ds segment base generated, but will be ignored in 64-bit mode");
527 error(ERR_WARNING
| ERR_PASS2
,
528 "es segment base generated, but will be ignored in 64-bit mode");
540 error(ERR_WARNING
| ERR_PASS2
,
541 "ss segment base generated, but will be ignored in 64-bit mode");
548 "segr6 and segr7 cannot be used as prefixes");
553 "16-bit addressing is not supported "
555 } else if (bits
!= 16)
565 "64-bit addressing is only supported "
589 error(ERR_PANIC
, "invalid instruction prefix");
592 out(offset
, segment
, &c
, OUT_RAWDATA
, 1,
597 insn_end
= offset
+ insn_size
;
598 gencode(segment
, offset
, bits
, instruction
,
601 if (itimes
> 0 && itimes
== instruction
->times
- 1) {
603 * Dummy call to list->output to give the offset to the
606 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
607 list
->uplevel(LIST_TIMES
);
610 if (instruction
->times
> 1)
611 list
->downlevel(LIST_TIMES
);
612 return offset
- start
;
616 case MERR_OPSIZEMISSING
:
617 error(ERR_NONFATAL
, "operation size not specified");
619 case MERR_OPSIZEMISMATCH
:
620 error(ERR_NONFATAL
, "mismatch in operand sizes");
623 error(ERR_NONFATAL
, "no instruction for this cpu level");
626 error(ERR_NONFATAL
, "instruction not supported in %d-bit mode",
631 "invalid combination of opcode and operands");
638 int64_t insn_size(int32_t segment
, int64_t offset
, int bits
, uint32_t cp
,
639 insn
* instruction
, efunc error
)
641 const struct itemplate
*temp
;
644 errfunc
= error
; /* to pass to other functions */
647 if (instruction
->opcode
== I_none
)
650 if (instruction
->opcode
== I_DB
|| instruction
->opcode
== I_DW
||
651 instruction
->opcode
== I_DD
|| instruction
->opcode
== I_DQ
||
652 instruction
->opcode
== I_DT
|| instruction
->opcode
== I_DO
||
653 instruction
->opcode
== I_DY
) {
655 int32_t isize
, osize
, wsize
;
658 wsize
= idata_bytes(instruction
->opcode
);
660 list_for_each(e
, instruction
->eops
) {
664 if (e
->type
== EOT_DB_NUMBER
) {
666 warn_overflow_const(e
->offset
, wsize
);
667 } else if (e
->type
== EOT_DB_STRING
||
668 e
->type
== EOT_DB_STRING_FREE
)
669 osize
= e
->stringlen
;
671 align
= (-osize
) % wsize
;
674 isize
+= osize
+ align
;
676 return isize
* instruction
->times
;
679 if (instruction
->opcode
== I_INCBIN
) {
680 const char *fname
= instruction
->eops
->stringval
;
685 fp
= fopen(fname
, "rb");
687 error(ERR_NONFATAL
, "`incbin': unable to open file `%s'",
689 else if (fseek(fp
, 0L, SEEK_END
) < 0)
690 error(ERR_NONFATAL
, "`incbin': unable to seek on file `%s'",
694 if (instruction
->eops
->next
) {
695 len
-= instruction
->eops
->next
->offset
;
696 if (instruction
->eops
->next
->next
&&
697 len
> (size_t)instruction
->eops
->next
->next
->offset
) {
698 len
= (size_t)instruction
->eops
->next
->next
->offset
;
701 val
= instruction
->times
* len
;
708 /* Check to see if we need an address-size prefix */
709 add_asp(instruction
, bits
);
711 m
= find_match(&temp
, instruction
, segment
, offset
, bits
);
713 /* we've matched an instruction. */
715 const uint8_t *codes
= temp
->code
;
718 isize
= calcsize(segment
, offset
, bits
, instruction
, codes
);
721 for (j
= 0; j
< MAXPREFIX
; j
++) {
722 switch (instruction
->prefixes
[j
]) {
748 return isize
* instruction
->times
;
750 return -1; /* didn't match any instruction */
754 static bool possible_sbyte(operand
*o
)
756 return o
->wrt
== NO_SEG
&& o
->segment
== NO_SEG
&&
757 !(o
->opflags
& OPFLAG_UNKNOWN
) &&
758 optimizing
>= 0 && !(o
->type
& STRICT
);
761 /* check that opn[op] is a signed byte of size 16 or 32 */
762 static bool is_sbyte16(operand
*o
)
766 if (!possible_sbyte(o
))
770 return v
>= -128 && v
<= 127;
773 static bool is_sbyte32(operand
*o
)
777 if (!possible_sbyte(o
))
781 return v
>= -128 && v
<= 127;
784 /* Common construct */
785 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
787 static int64_t calcsize(int32_t segment
, int64_t offset
, int bits
,
788 insn
* ins
, const uint8_t *codes
)
797 ins
->rex
= 0; /* Ensure REX is reset */
799 if (ins
->prefixes
[PPS_OSIZE
] == P_O64
)
802 (void)segment
; /* Don't warn that this parameter is unused */
803 (void)offset
; /* Don't warn that this parameter is unused */
807 op1
= (c
& 3) + ((opex
& 1) << 2);
808 op2
= ((c
>> 3) & 3) + ((opex
& 2) << 1);
809 opx
= &ins
->oprs
[op1
];
810 opex
= 0; /* For the next iteration */
817 codes
+= c
, length
+= c
;
828 op_rexflags(opx
, REX_B
|REX_H
|REX_P
|REX_W
);
843 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
844 length
+= (opx
->type
& BITS16
) ? 2 : 4;
846 length
+= (bits
== 16) ? 2 : 4;
854 length
+= ins
->addr_size
>> 3;
862 length
+= 8; /* MOV reg64/imm */
870 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
871 length
+= (opx
->type
& BITS16
) ? 2 : 4;
873 length
+= (bits
== 16) ? 2 : 4;
885 length
+= is_sbyte16(opx
) ? 1 : 2;
894 length
+= is_sbyte32(opx
) ? 1 : 4;
905 ins
->drexdst
= regval(opx
);
910 ins
->rex
|= REX_D
|REX_OC
;
911 ins
->drexdst
= regval(opx
);
925 length
+= is_sbyte32(opx
) ? 1 : 4;
934 ins
->drexdst
= regval(opx
);
935 ins
->vex_cm
= *codes
++;
936 ins
->vex_wlp
= *codes
++;
942 ins
->vex_cm
= *codes
++;
943 ins
->vex_wlp
= *codes
++;
956 length
+= (bits
!= 16) && !has_prefix(ins
, PPS_ASIZE
, P_A16
);
960 length
+= (bits
!= 32) && !has_prefix(ins
, PPS_ASIZE
, P_A32
);
967 if (bits
!= 64 || has_prefix(ins
, PPS_ASIZE
, P_A16
) ||
968 has_prefix(ins
, PPS_ASIZE
, P_A32
))
976 length
+= (bits
!= 16);
980 length
+= (bits
== 16);
1018 if (!ins
->prefixes
[PPS_LREP
])
1019 ins
->prefixes
[PPS_LREP
] = P_REP
;
1023 if (!ins
->prefixes
[PPS_LREP
])
1024 ins
->prefixes
[PPS_LREP
] = P_REPNE
;
1028 if (ins
->oprs
[0].segment
!= NO_SEG
)
1029 errfunc(ERR_NONFATAL
, "attempt to reserve non-constant"
1030 " quantity of BSS space");
1032 length
+= ins
->oprs
[0].offset
;
1036 if (!ins
->prefixes
[PPS_WAIT
])
1037 ins
->prefixes
[PPS_WAIT
] = P_WAIT
;
1087 struct operand
*opy
= &ins
->oprs
[op2
];
1089 ea_data
.rex
= 0; /* Ensure ea.REX is initially 0 */
1092 /* pick rfield from operand b (opx) */
1093 rflags
= regflag(opx
);
1094 rfield
= nasm_regvals
[opx
->basereg
];
1099 if (!process_ea(opy
, &ea_data
, bits
,
1100 ins
->addr_size
, rfield
, rflags
)) {
1101 errfunc(ERR_NONFATAL
, "invalid effective address");
1104 ins
->rex
|= ea_data
.rex
;
1105 length
+= ea_data
.size
;
1111 errfunc(ERR_PANIC
, "internal instruction table corrupt"
1112 ": instruction code \\%o (0x%02X) given", c
, c
);
1117 ins
->rex
&= rex_mask
;
1119 if (ins
->rex
& REX_NH
) {
1120 if (ins
->rex
& REX_H
) {
1121 errfunc(ERR_NONFATAL
, "instruction cannot use high registers");
1124 ins
->rex
&= ~REX_P
; /* Don't force REX prefix due to high reg */
1127 if (ins
->rex
& REX_V
) {
1128 int bad32
= REX_R
|REX_W
|REX_X
|REX_B
;
1130 if (ins
->rex
& REX_H
) {
1131 errfunc(ERR_NONFATAL
, "cannot use high register in vex instruction");
1134 switch (ins
->vex_wlp
& 030) {
1148 if (bits
!= 64 && ((ins
->rex
& bad32
) || ins
->drexdst
> 7)) {
1149 errfunc(ERR_NONFATAL
, "invalid operands in non-64-bit mode");
1152 if (ins
->vex_cm
!= 1 || (ins
->rex
& (REX_W
|REX_R
|REX_B
)))
1156 } else if (ins
->rex
& REX_D
) {
1157 if (ins
->rex
& REX_H
) {
1158 errfunc(ERR_NONFATAL
, "cannot use high register in drex instruction");
1161 if (bits
!= 64 && ((ins
->rex
& (REX_R
|REX_W
|REX_X
|REX_B
)) ||
1162 ins
->drexdst
> 7)) {
1163 errfunc(ERR_NONFATAL
, "invalid operands in non-64-bit mode");
1167 } else if (ins
->rex
& REX_REAL
) {
1168 if (ins
->rex
& REX_H
) {
1169 errfunc(ERR_NONFATAL
, "cannot use high register in rex instruction");
1171 } else if (bits
== 64) {
1173 } else if ((ins
->rex
& REX_L
) &&
1174 !(ins
->rex
& (REX_P
|REX_W
|REX_X
|REX_B
)) &&
1177 assert_no_prefix(ins
, PPS_LREP
);
1180 errfunc(ERR_NONFATAL
, "invalid operands in non-64-bit mode");
1188 #define EMIT_REX() \
1189 if (!(ins->rex & (REX_D|REX_V)) && (ins->rex & REX_REAL) && (bits == 64)) { \
1190 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1191 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1196 static void gencode(int32_t segment
, int64_t offset
, int bits
,
1197 insn
* ins
, const struct itemplate
*temp
,
1200 static char condval
[] = { /* conditional opcodes */
1201 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1202 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1203 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1210 struct operand
*opx
;
1211 const uint8_t *codes
= temp
->code
;
1216 op1
= (c
& 3) + ((opex
& 1) << 2);
1217 op2
= ((c
>> 3) & 3) + ((opex
& 2) << 1);
1218 opx
= &ins
->oprs
[op1
];
1219 opex
= 0; /* For the next iteration */
1227 out(offset
, segment
, codes
, OUT_RAWDATA
, c
, NO_SEG
, NO_SEG
);
1240 bytes
[0] = *codes
++ + (regval(opx
) & 7);
1241 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1246 /* The test for BITS8 and SBYTE here is intended to avoid
1247 warning on optimizer actions due to SBYTE, while still
1248 warn on explicit BYTE directives. Also warn, obviously,
1249 if the optimizer isn't enabled. */
1250 if (((opx
->type
& BITS8
) ||
1251 !(opx
->type
& temp
->opd
[op1
] & BYTENESS
)) &&
1252 (opx
->offset
< -128 || opx
->offset
> 127)) {
1253 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1254 "signed byte value exceeds bounds");
1256 if (opx
->segment
!= NO_SEG
) {
1258 out(offset
, segment
, &data
, OUT_ADDRESS
, 1,
1259 opx
->segment
, opx
->wrt
);
1261 bytes
[0] = opx
->offset
;
1262 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1269 if (opx
->offset
< -256 || opx
->offset
> 255) {
1270 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1271 "byte value exceeds bounds");
1273 if (opx
->segment
!= NO_SEG
) {
1275 out(offset
, segment
, &data
, OUT_ADDRESS
, 1,
1276 opx
->segment
, opx
->wrt
);
1278 bytes
[0] = opx
->offset
;
1279 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1286 if (opx
->offset
< 0 || opx
->offset
> 255)
1287 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1288 "unsigned byte value exceeds bounds");
1289 if (opx
->segment
!= NO_SEG
) {
1291 out(offset
, segment
, &data
, OUT_ADDRESS
, 1,
1292 opx
->segment
, opx
->wrt
);
1294 bytes
[0] = opx
->offset
;
1295 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1302 warn_overflow_opd(opx
, 2);
1304 out(offset
, segment
, &data
, OUT_ADDRESS
, 2,
1305 opx
->segment
, opx
->wrt
);
1310 if (opx
->type
& (BITS16
| BITS32
))
1311 size
= (opx
->type
& BITS16
) ? 2 : 4;
1313 size
= (bits
== 16) ? 2 : 4;
1314 warn_overflow_opd(opx
, size
);
1316 out(offset
, segment
, &data
, OUT_ADDRESS
, size
,
1317 opx
->segment
, opx
->wrt
);
1322 warn_overflow_opd(opx
, 4);
1324 out(offset
, segment
, &data
, OUT_ADDRESS
, 4,
1325 opx
->segment
, opx
->wrt
);
1331 size
= ins
->addr_size
>> 3;
1332 warn_overflow_opd(opx
, size
);
1333 out(offset
, segment
, &data
, OUT_ADDRESS
, size
,
1334 opx
->segment
, opx
->wrt
);
1339 if (opx
->segment
!= segment
)
1340 errfunc(ERR_NONFATAL
,
1341 "short relative jump outside segment");
1342 data
= opx
->offset
- insn_end
;
1343 if (data
> 127 || data
< -128)
1344 errfunc(ERR_NONFATAL
, "short jump is out of range");
1346 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1351 data
= (int64_t)opx
->offset
;
1352 out(offset
, segment
, &data
, OUT_ADDRESS
, 8,
1353 opx
->segment
, opx
->wrt
);
1358 if (opx
->segment
!= segment
) {
1360 out(offset
, segment
, &data
,
1361 OUT_REL2ADR
, insn_end
- offset
,
1362 opx
->segment
, opx
->wrt
);
1364 data
= opx
->offset
- insn_end
;
1365 out(offset
, segment
, &data
,
1366 OUT_ADDRESS
, 2, NO_SEG
, NO_SEG
);
1372 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
1373 size
= (opx
->type
& BITS16
) ? 2 : 4;
1375 size
= (bits
== 16) ? 2 : 4;
1376 if (opx
->segment
!= segment
) {
1378 out(offset
, segment
, &data
,
1379 size
== 2 ? OUT_REL2ADR
: OUT_REL4ADR
,
1380 insn_end
- offset
, opx
->segment
, opx
->wrt
);
1382 data
= opx
->offset
- insn_end
;
1383 out(offset
, segment
, &data
,
1384 OUT_ADDRESS
, size
, NO_SEG
, NO_SEG
);
1390 if (opx
->segment
!= segment
) {
1392 out(offset
, segment
, &data
,
1393 OUT_REL4ADR
, insn_end
- offset
,
1394 opx
->segment
, opx
->wrt
);
1396 data
= opx
->offset
- insn_end
;
1397 out(offset
, segment
, &data
,
1398 OUT_ADDRESS
, 4, NO_SEG
, NO_SEG
);
1404 if (opx
->segment
== NO_SEG
)
1405 errfunc(ERR_NONFATAL
, "value referenced by FAR is not"
1408 out(offset
, segment
, &data
, OUT_ADDRESS
, 2,
1409 outfmt
->segbase(1 + opx
->segment
),
1416 warn_overflow_opd(opx
, 2);
1417 if (is_sbyte16(opx
)) {
1419 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1423 out(offset
, segment
, &data
, OUT_ADDRESS
, 2,
1424 opx
->segment
, opx
->wrt
);
1431 bytes
[0] = *codes
++;
1432 if (is_sbyte16(opx
))
1433 bytes
[0] |= 2; /* s-bit */
1434 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1440 warn_overflow_opd(opx
, 4);
1441 if (is_sbyte32(opx
)) {
1443 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1447 out(offset
, segment
, &data
, OUT_ADDRESS
, 4,
1448 opx
->segment
, opx
->wrt
);
1455 bytes
[0] = *codes
++;
1456 if (is_sbyte32(opx
))
1457 bytes
[0] |= 2; /* s-bit */
1458 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1468 (ins
->drexdst
<< 4) |
1469 (ins
->rex
& REX_OC
? 0x08 : 0) |
1470 (ins
->rex
& (REX_R
|REX_X
|REX_B
));
1472 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1478 opx
= &ins
->oprs
[c
>> 3];
1479 bytes
[0] = nasm_regvals
[opx
->basereg
] << 4;
1480 opx
= &ins
->oprs
[c
& 7];
1481 if (opx
->segment
!= NO_SEG
|| opx
->wrt
!= NO_SEG
) {
1482 errfunc(ERR_NONFATAL
,
1483 "non-absolute expression not permitted as argument %d",
1486 if (opx
->offset
& ~15) {
1487 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1488 "four-bit argument exceeds bounds");
1490 bytes
[0] |= opx
->offset
& 15;
1492 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1498 opx
= &ins
->oprs
[c
>> 4];
1499 bytes
[0] = nasm_regvals
[opx
->basereg
] << 4;
1501 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1507 opx
= &ins
->oprs
[c
];
1508 bytes
[0] = nasm_regvals
[opx
->basereg
] << 4;
1509 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1515 if (opx
->wrt
== NO_SEG
&& opx
->segment
== NO_SEG
&&
1516 (int32_t)data
!= (int64_t)data
) {
1517 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1518 "signed dword immediate exceeds bounds");
1520 if (is_sbyte32(opx
)) {
1522 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1526 out(offset
, segment
, &data
, OUT_ADDRESS
, 4,
1527 opx
->segment
, opx
->wrt
);
1534 if (opx
->wrt
== NO_SEG
&& opx
->segment
== NO_SEG
&&
1535 (int32_t)data
!= (int64_t)data
) {
1536 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1537 "signed dword immediate exceeds bounds");
1539 out(offset
, segment
, &data
, OUT_ADDRESS
, 4,
1540 opx
->segment
, opx
->wrt
);
1547 if (ins
->vex_cm
!= 1 || (ins
->rex
& (REX_W
|REX_X
|REX_B
))) {
1548 bytes
[0] = (ins
->vex_cm
>> 6) ? 0x8f : 0xc4;
1549 bytes
[1] = (ins
->vex_cm
& 31) | ((~ins
->rex
& 7) << 5);
1550 bytes
[2] = ((ins
->rex
& REX_W
) << (7-3)) |
1551 ((~ins
->drexdst
& 15)<< 3) | (ins
->vex_wlp
& 07);
1552 out(offset
, segment
, &bytes
, OUT_RAWDATA
, 3, NO_SEG
, NO_SEG
);
1556 bytes
[1] = ((~ins
->rex
& REX_R
) << (7-2)) |
1557 ((~ins
->drexdst
& 15) << 3) | (ins
->vex_wlp
& 07);
1558 out(offset
, segment
, &bytes
, OUT_RAWDATA
, 2, NO_SEG
, NO_SEG
);
1568 if (ins
->rex
& REX_W
)
1570 else if (ins
->prefixes
[PPS_OSIZE
] == P_O16
)
1572 else if (ins
->prefixes
[PPS_OSIZE
] == P_O32
)
1577 um
= (uint64_t)2 << (s
-1);
1580 if (uv
> 127 && uv
< (uint64_t)-128 &&
1581 (uv
< um
-128 || uv
> um
-1)) {
1582 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1583 "signed byte value exceeds bounds");
1585 if (opx
->segment
!= NO_SEG
) {
1587 out(offset
, segment
, &data
, OUT_ADDRESS
, 1,
1588 opx
->segment
, opx
->wrt
);
1591 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1602 if (bits
== 32 && !has_prefix(ins
, PPS_ASIZE
, P_A16
)) {
1604 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1611 if (bits
!= 32 && !has_prefix(ins
, PPS_ASIZE
, P_A32
)) {
1613 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1632 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1641 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1659 *bytes
= *codes
++ ^ condval
[ins
->condition
];
1660 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1669 *bytes
= c
- 0332 + 0xF2;
1670 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1675 if (ins
->rex
& REX_R
) {
1677 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1680 ins
->rex
&= ~(REX_L
|REX_R
);
1691 if (ins
->oprs
[0].segment
!= NO_SEG
)
1692 errfunc(ERR_PANIC
, "non-constant BSS size in pass two");
1694 int64_t size
= ins
->oprs
[0].offset
;
1696 out(offset
, segment
, NULL
,
1697 OUT_RESERVE
, size
, NO_SEG
, NO_SEG
);
1708 switch (ins
->oprs
[0].basereg
) {
1723 "bizarre 8086 segment register received");
1725 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1732 switch (ins
->oprs
[0].basereg
) {
1741 "bizarre 386 segment register received");
1743 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1752 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1758 bytes
[0] = c
- 0362 + 0xf2;
1759 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1769 *bytes
= c
- 0366 + 0x66;
1770 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1780 *bytes
= bits
== 16 ? 3 : 5;
1781 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1804 struct operand
*opy
= &ins
->oprs
[op2
];
1807 /* pick rfield from operand b (opx) */
1808 rflags
= regflag(opx
);
1809 rfield
= nasm_regvals
[opx
->basereg
];
1811 /* rfield is constant */
1816 if (!process_ea(opy
, &ea_data
, bits
, ins
->addr_size
,
1818 errfunc(ERR_NONFATAL
, "invalid effective address");
1823 *p
++ = ea_data
.modrm
;
1824 if (ea_data
.sib_present
)
1827 /* DREX suffixes come between the SIB and the displacement */
1828 if (ins
->rex
& REX_D
) {
1829 *p
++ = (ins
->drexdst
<< 4) |
1830 (ins
->rex
& REX_OC
? 0x08 : 0) |
1831 (ins
->rex
& (REX_R
|REX_X
|REX_B
));
1836 out(offset
, segment
, bytes
, OUT_RAWDATA
, s
, NO_SEG
, NO_SEG
);
1839 * Make sure the address gets the right offset in case
1840 * the line breaks in the .lst file (BR 1197827)
1845 switch (ea_data
.bytes
) {
1855 if (opy
->segment
== segment
) {
1857 if (overflow_signed(data
, ea_data
.bytes
))
1858 warn_overflow(ERR_PASS2
, ea_data
.bytes
);
1859 out(offset
, segment
, &data
, OUT_ADDRESS
,
1860 ea_data
.bytes
, NO_SEG
, NO_SEG
);
1862 /* overflow check in output/linker? */
1863 out(offset
, segment
, &data
, OUT_REL4ADR
,
1864 insn_end
- offset
, opy
->segment
, opy
->wrt
);
1867 if (overflow_general(opy
->offset
, ins
->addr_size
>> 3) ||
1868 signed_bits(opy
->offset
, ins
->addr_size
) !=
1869 signed_bits(opy
->offset
, ea_data
.bytes
* 8))
1870 warn_overflow(ERR_PASS2
, ea_data
.bytes
);
1873 out(offset
, segment
, &data
, OUT_ADDRESS
,
1874 ea_data
.bytes
, opy
->segment
, opy
->wrt
);
1880 "Invalid amount of bytes (%d) for offset?!",
1889 errfunc(ERR_PANIC
, "internal instruction table corrupt"
1890 ": instruction code \\%o (0x%02X) given", c
, c
);
1896 static opflags_t
regflag(const operand
* o
)
1898 if (o
->basereg
< EXPR_REG_START
|| o
->basereg
>= REG_ENUM_LIMIT
) {
1899 errfunc(ERR_PANIC
, "invalid operand passed to regflag()");
1901 return nasm_reg_flags
[o
->basereg
];
1904 static int32_t regval(const operand
* o
)
1906 if (o
->basereg
< EXPR_REG_START
|| o
->basereg
>= REG_ENUM_LIMIT
) {
1907 errfunc(ERR_PANIC
, "invalid operand passed to regval()");
1909 return nasm_regvals
[o
->basereg
];
1912 static int op_rexflags(const operand
* o
, int mask
)
1917 if (o
->basereg
< EXPR_REG_START
|| o
->basereg
>= REG_ENUM_LIMIT
) {
1918 errfunc(ERR_PANIC
, "invalid operand passed to op_rexflags()");
1921 flags
= nasm_reg_flags
[o
->basereg
];
1922 val
= nasm_regvals
[o
->basereg
];
1924 return rexflags(val
, flags
, mask
);
1927 static int rexflags(int val
, opflags_t flags
, int mask
)
1932 rex
|= REX_B
|REX_X
|REX_R
;
1935 if (!(REG_HIGH
& ~flags
)) /* AH, CH, DH, BH */
1937 else if (!(REG8
& ~flags
) && val
>= 4) /* SPL, BPL, SIL, DIL */
1943 static enum match_result
find_match(const struct itemplate
**tempp
,
1945 int32_t segment
, int64_t offset
, int bits
)
1947 const struct itemplate
*temp
;
1948 enum match_result m
, merr
;
1949 opflags_t xsizeflags
[MAX_OPERANDS
];
1950 bool opsizemissing
= false;
1953 for (i
= 0; i
< instruction
->operands
; i
++)
1954 xsizeflags
[i
] = instruction
->oprs
[i
].type
& SIZE_MASK
;
1956 merr
= MERR_INVALOP
;
1958 for (temp
= nasm_instructions
[instruction
->opcode
];
1959 temp
->opcode
!= I_none
; temp
++) {
1960 m
= matches(temp
, instruction
, bits
);
1961 if (m
== MOK_JUMP
) {
1962 if (jmp_match(segment
, offset
, bits
, instruction
, temp
->code
))
1966 } else if (m
== MERR_OPSIZEMISSING
&&
1967 (temp
->flags
& IF_SMASK
) != IF_SX
) {
1969 * Missing operand size and a candidate for fuzzy matching...
1971 for (i
= 0; i
< temp
->operands
; i
++) {
1972 if ((temp
->opd
[i
] & SAME_AS
) == 0)
1973 xsizeflags
[i
] |= temp
->opd
[i
] & SIZE_MASK
;
1975 opsizemissing
= true;
1979 if (merr
== MOK_GOOD
)
1983 /* No match, but see if we can get a fuzzy operand size match... */
1987 for (i
= 0; i
< instruction
->operands
; i
++) {
1989 * We ignore extrinsic operand sizes on registers, so we should
1990 * never try to fuzzy-match on them. This also resolves the case
1991 * when we have e.g. "xmmrm128" in two different positions.
1993 if (is_class(REGISTER
, instruction
->oprs
[i
].type
))
1996 /* This tests if xsizeflags[i] has more than one bit set */
1997 if ((xsizeflags
[i
] & (xsizeflags
[i
]-1)))
1998 goto done
; /* No luck */
2000 instruction
->oprs
[i
].type
|= xsizeflags
[i
]; /* Set the size */
2003 /* Try matching again... */
2004 for (temp
= nasm_instructions
[instruction
->opcode
];
2005 temp
->opcode
!= I_none
; temp
++) {
2006 m
= matches(temp
, instruction
, bits
);
2007 if (m
== MOK_JUMP
) {
2008 if (jmp_match(segment
, offset
, bits
, instruction
, temp
->code
))
2015 if (merr
== MOK_GOOD
)
2024 static enum match_result
matches(const struct itemplate
*itemp
,
2025 insn
*instruction
, int bits
)
2027 int i
, size
[MAX_OPERANDS
], asize
, oprs
;
2028 bool opsizemissing
= false;
2033 if (itemp
->opcode
!= instruction
->opcode
)
2034 return MERR_INVALOP
;
2037 * Count the operands
2039 if (itemp
->operands
!= instruction
->operands
)
2040 return MERR_INVALOP
;
2043 * Check that no spurious colons or TOs are present
2045 for (i
= 0; i
< itemp
->operands
; i
++)
2046 if (instruction
->oprs
[i
].type
& ~itemp
->opd
[i
] & (COLON
| TO
))
2047 return MERR_INVALOP
;
2050 * Process size flags
2052 switch (itemp
->flags
& IF_SMASK
) {
2092 if (itemp
->flags
& IF_ARMASK
) {
2093 /* S- flags only apply to a specific operand */
2094 i
= ((itemp
->flags
& IF_ARMASK
) >> IF_ARSHFT
) - 1;
2095 memset(size
, 0, sizeof size
);
2098 /* S- flags apply to all operands */
2099 for (i
= 0; i
< MAX_OPERANDS
; i
++)
2104 * Check that the operand flags all match up,
2105 * it's a bit tricky so lets be verbose:
2107 * 1) Find out the size of operand. If instruction
2108 * doesn't have one specified -- we're trying to
2109 * guess it either from template (IF_S* flag) or
2112 * 2) If template operand (i) has SAME_AS flag [used for registers only]
2113 * (ie the same operand as was specified somewhere in template, and
2114 * this referred operand index is being achieved via ~SAME_AS)
2115 * we are to be sure that both registers (in template and instruction)
2118 * 3) If template operand do not match the instruction OR
2119 * template has an operand size specified AND this size differ
2120 * from which instruction has (perhaps we got it from code bits)
2122 * a) Check that only size of instruction and operand is differ
2123 * other characteristics do match
2124 * b) Perhaps it's a register specified in instruction so
2125 * for such a case we just mark that operand as "size
2126 * missing" and this will turn on fuzzy operand size
2127 * logic facility (handled by a caller)
2129 for (i
= 0; i
< itemp
->operands
; i
++) {
2130 opflags_t type
= instruction
->oprs
[i
].type
;
2131 if (!(type
& SIZE_MASK
))
2134 if (itemp
->opd
[i
] & SAME_AS
) {
2135 int j
= itemp
->opd
[i
] & ~SAME_AS
;
2136 if (type
!= instruction
->oprs
[j
].type
||
2137 instruction
->oprs
[i
].basereg
!= instruction
->oprs
[j
].basereg
)
2138 return MERR_INVALOP
;
2139 } else if (itemp
->opd
[i
] & ~type
||
2140 ((itemp
->opd
[i
] & SIZE_MASK
) &&
2141 ((itemp
->opd
[i
] ^ type
) & SIZE_MASK
))) {
2142 if ((itemp
->opd
[i
] & ~type
& ~SIZE_MASK
) || (type
& SIZE_MASK
)) {
2143 return MERR_INVALOP
;
2144 } else if (!is_class(REGISTER
, type
)) {
2146 * Note: we don't honor extrinsic operand sizes for registers,
2147 * so "missing operand size" for a register should be
2148 * considered a wildcard match rather than an error.
2150 opsizemissing
= true;
2156 return MERR_OPSIZEMISSING
;
2159 * Check operand sizes
2161 if (itemp
->flags
& (IF_SM
| IF_SM2
)) {
2162 oprs
= (itemp
->flags
& IF_SM2
? 2 : itemp
->operands
);
2163 for (i
= 0; i
< oprs
; i
++) {
2164 asize
= itemp
->opd
[i
] & SIZE_MASK
;
2166 for (i
= 0; i
< oprs
; i
++)
2172 oprs
= itemp
->operands
;
2175 for (i
= 0; i
< itemp
->operands
; i
++) {
2176 if (!(itemp
->opd
[i
] & SIZE_MASK
) &&
2177 (instruction
->oprs
[i
].type
& SIZE_MASK
& ~size
[i
]))
2178 return MERR_OPSIZEMISMATCH
;
2182 * Check template is okay at the set cpu level
2184 if (((itemp
->flags
& IF_PLEVEL
) > cpu
))
2188 * Verify the appropriate long mode flag.
2190 if ((itemp
->flags
& (bits
== 64 ? IF_NOLONG
: IF_LONG
)))
2191 return MERR_BADMODE
;
2194 * Check if special handling needed for Jumps
2196 if ((itemp
->code
[0] & 0374) == 0370)
2202 static ea
*process_ea(operand
* input
, ea
* output
, int bits
,
2203 int addrbits
, int rfield
, opflags_t rflags
)
2205 bool forw_ref
= !!(input
->opflags
& OPFLAG_UNKNOWN
);
2207 output
->rip
= false;
2209 /* REX flags for the rfield operand */
2210 output
->rex
|= rexflags(rfield
, rflags
, REX_R
|REX_P
|REX_W
|REX_H
);
2212 if (is_class(REGISTER
, input
->type
)) { /* register direct */
2216 if (input
->basereg
< EXPR_REG_START
/* Verify as Register */
2217 || input
->basereg
>= REG_ENUM_LIMIT
)
2220 i
= nasm_regvals
[input
->basereg
];
2223 return NULL
; /* Invalid EA register */
2225 output
->rex
|= op_rexflags(input
, REX_B
|REX_P
|REX_W
|REX_H
);
2227 output
->sib_present
= false; /* no SIB necessary */
2228 output
->bytes
= 0; /* no offset necessary either */
2229 output
->modrm
= 0xC0 | ((rfield
& 7) << 3) | (i
& 7);
2230 } else { /* it's a memory reference */
2231 if (input
->basereg
== -1
2232 && (input
->indexreg
== -1 || input
->scale
== 0)) {
2233 /* it's a pure offset */
2235 if (bits
== 64 && ((input
->type
& IP_REL
) == IP_REL
) &&
2236 input
->segment
== NO_SEG
) {
2237 nasm_error(ERR_WARNING
| ERR_PASS1
, "absolute address can not be RIP-relative");
2238 input
->type
&= ~IP_REL
;
2239 input
->type
|= MEMORY
;
2242 if (input
->eaflags
& EAF_BYTEOFFS
||
2243 (input
->eaflags
& EAF_WORDOFFS
&&
2244 input
->disp_size
!= (addrbits
!= 16 ? 32 : 16))) {
2245 nasm_error(ERR_WARNING
| ERR_PASS1
, "displacement size ignored on absolute address");
2248 if (bits
== 64 && (~input
->type
& IP_REL
)) {
2249 int scale
, index
, base
;
2250 output
->sib_present
= true;
2254 output
->sib
= (scale
<< 6) | (index
<< 3) | base
;
2256 output
->modrm
= 4 | ((rfield
& 7) << 3);
2257 output
->rip
= false;
2259 output
->sib_present
= false;
2260 output
->bytes
= (addrbits
!= 16 ? 4 : 2);
2261 output
->modrm
= (addrbits
!= 16 ? 5 : 6) | ((rfield
& 7) << 3);
2262 output
->rip
= bits
== 64;
2264 } else { /* it's an indirection */
2265 int i
= input
->indexreg
, b
= input
->basereg
, s
= input
->scale
;
2266 int32_t seg
= input
->segment
;
2267 int hb
= input
->hintbase
, ht
= input
->hinttype
;
2268 int t
, it
, bt
; /* register numbers */
2269 opflags_t x
, ix
, bx
; /* register flags */
2272 i
= -1; /* make this easy, at least */
2274 if (i
>= EXPR_REG_START
&& i
< REG_ENUM_LIMIT
) {
2275 it
= nasm_regvals
[i
];
2276 ix
= nasm_reg_flags
[i
];
2282 if (b
>= EXPR_REG_START
&& b
< REG_ENUM_LIMIT
) {
2283 bt
= nasm_regvals
[b
];
2284 bx
= nasm_reg_flags
[b
];
2290 /* check for a 32/64-bit memory reference... */
2291 if ((ix
|bx
) & (BITS32
|BITS64
)) {
2292 /* it must be a 32/64-bit memory reference. Firstly we have
2293 * to check that all registers involved are type E/Rxx. */
2294 int32_t sok
= BITS32
|BITS64
, o
= input
->offset
;
2297 if (!(REG64
& ~ix
) || !(REG32
& ~ix
))
2305 return NULL
; /* Invalid register */
2306 if (~sok
& bx
& SIZE_MASK
)
2307 return NULL
; /* Invalid size */
2311 /* While we're here, ensure the user didn't specify
2313 if (input
->disp_size
== 16 || input
->disp_size
== 64)
2316 if (addrbits
== 16 ||
2317 (addrbits
== 32 && !(sok
& BITS32
)) ||
2318 (addrbits
== 64 && !(sok
& BITS64
)))
2321 /* now reorganize base/index */
2322 if (s
== 1 && bt
!= it
&& bt
!= -1 && it
!= -1 &&
2323 ((hb
== b
&& ht
== EAH_NOTBASE
)
2324 || (hb
== i
&& ht
== EAH_MAKEBASE
))) {
2325 /* swap if hints say so */
2326 t
= bt
, bt
= it
, it
= t
;
2327 x
= bx
, bx
= ix
, ix
= x
;
2329 if (bt
== it
) /* convert EAX+2*EAX to 3*EAX */
2330 bt
= -1, bx
= 0, s
++;
2331 if (bt
== -1 && s
== 1 && !(hb
== it
&& ht
== EAH_NOTBASE
)) {
2332 /* make single reg base, unless hint */
2333 bt
= it
, bx
= ix
, it
= -1, ix
= 0;
2335 if (((s
== 2 && it
!= REG_NUM_ESP
2336 && !(input
->eaflags
& EAF_TIMESTWO
)) || s
== 3
2337 || s
== 5 || s
== 9) && bt
== -1)
2338 bt
= it
, bx
= ix
, s
--; /* convert 3*EAX to EAX+2*EAX */
2339 if (it
== -1 && (bt
& 7) != REG_NUM_ESP
2340 && (input
->eaflags
& EAF_TIMESTWO
))
2341 it
= bt
, ix
= bx
, bt
= -1, bx
= 0, s
= 1;
2342 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2343 if (s
== 1 && it
== REG_NUM_ESP
) {
2344 /* swap ESP into base if scale is 1 */
2345 t
= it
, it
= bt
, bt
= t
;
2346 x
= ix
, ix
= bx
, bx
= x
;
2348 if (it
== REG_NUM_ESP
2349 || (s
!= 1 && s
!= 2 && s
!= 4 && s
!= 8 && it
!= -1))
2350 return NULL
; /* wrong, for various reasons */
2352 output
->rex
|= rexflags(it
, ix
, REX_X
);
2353 output
->rex
|= rexflags(bt
, bx
, REX_B
);
2355 if (it
== -1 && (bt
& 7) != REG_NUM_ESP
) {
2364 if (rm
!= REG_NUM_EBP
&& o
== 0 &&
2365 seg
== NO_SEG
&& !forw_ref
&&
2367 (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2369 else if (input
->eaflags
& EAF_BYTEOFFS
||
2370 (o
>= -128 && o
<= 127 && seg
== NO_SEG
2372 && !(input
->eaflags
& EAF_WORDOFFS
)))
2378 output
->sib_present
= false;
2379 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2380 output
->modrm
= (mod
<< 6) | ((rfield
& 7) << 3) | rm
;
2383 int mod
, scale
, index
, base
;
2403 default: /* then what the smeg is it? */
2404 return NULL
; /* panic */
2412 if (base
!= REG_NUM_EBP
&& o
== 0 &&
2413 seg
== NO_SEG
&& !forw_ref
&&
2415 (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2417 else if (input
->eaflags
& EAF_BYTEOFFS
||
2418 (o
>= -128 && o
<= 127 && seg
== NO_SEG
2420 && !(input
->eaflags
& EAF_WORDOFFS
)))
2426 output
->sib_present
= true;
2427 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2428 output
->modrm
= (mod
<< 6) | ((rfield
& 7) << 3) | 4;
2429 output
->sib
= (scale
<< 6) | (index
<< 3) | base
;
2431 } else { /* it's 16-bit */
2433 int16_t o
= input
->offset
;
2435 /* check for 64-bit long mode */
2439 /* check all registers are BX, BP, SI or DI */
2440 if ((b
!= -1 && b
!= R_BP
&& b
!= R_BX
&& b
!= R_SI
2441 && b
!= R_DI
) || (i
!= -1 && i
!= R_BP
&& i
!= R_BX
2442 && i
!= R_SI
&& i
!= R_DI
))
2445 /* ensure the user didn't specify DWORD/QWORD */
2446 if (input
->disp_size
== 32 || input
->disp_size
== 64)
2449 if (s
!= 1 && i
!= -1)
2450 return NULL
; /* no can do, in 16-bit EA */
2451 if (b
== -1 && i
!= -1) {
2456 if ((b
== R_SI
|| b
== R_DI
) && i
!= -1) {
2461 /* have BX/BP as base, SI/DI index */
2463 return NULL
; /* shouldn't ever happen, in theory */
2464 if (i
!= -1 && b
!= -1 &&
2465 (i
== R_BP
|| i
== R_BX
|| b
== R_SI
|| b
== R_DI
))
2466 return NULL
; /* invalid combinations */
2467 if (b
== -1) /* pure offset: handled above */
2468 return NULL
; /* so if it gets to here, panic! */
2472 switch (i
* 256 + b
) {
2473 case R_SI
* 256 + R_BX
:
2476 case R_DI
* 256 + R_BX
:
2479 case R_SI
* 256 + R_BP
:
2482 case R_DI
* 256 + R_BP
:
2500 if (rm
== -1) /* can't happen, in theory */
2501 return NULL
; /* so panic if it does */
2503 if (o
== 0 && seg
== NO_SEG
&& !forw_ref
&& rm
!= 6 &&
2504 !(input
->eaflags
& (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2506 else if (input
->eaflags
& EAF_BYTEOFFS
||
2507 (o
>= -128 && o
<= 127 && seg
== NO_SEG
2509 && !(input
->eaflags
& EAF_WORDOFFS
)))
2514 output
->sib_present
= false; /* no SIB - it's 16-bit */
2515 output
->bytes
= mod
; /* bytes of offset needed */
2516 output
->modrm
= (mod
<< 6) | ((rfield
& 7) << 3) | rm
;
2521 output
->size
= 1 + output
->sib_present
+ output
->bytes
;
2525 static void add_asp(insn
*ins
, int addrbits
)
2530 valid
= (addrbits
== 64) ? 64|32 : 32|16;
2532 switch (ins
->prefixes
[PPS_ASIZE
]) {
2543 valid
&= (addrbits
== 32) ? 16 : 32;
2549 for (j
= 0; j
< ins
->operands
; j
++) {
2550 if (is_class(MEMORY
, ins
->oprs
[j
].type
)) {
2553 /* Verify as Register */
2554 if (ins
->oprs
[j
].indexreg
< EXPR_REG_START
2555 || ins
->oprs
[j
].indexreg
>= REG_ENUM_LIMIT
)
2558 i
= nasm_reg_flags
[ins
->oprs
[j
].indexreg
];
2560 /* Verify as Register */
2561 if (ins
->oprs
[j
].basereg
< EXPR_REG_START
2562 || ins
->oprs
[j
].basereg
>= REG_ENUM_LIMIT
)
2565 b
= nasm_reg_flags
[ins
->oprs
[j
].basereg
];
2567 if (ins
->oprs
[j
].scale
== 0)
2571 int ds
= ins
->oprs
[j
].disp_size
;
2572 if ((addrbits
!= 64 && ds
> 8) ||
2573 (addrbits
== 64 && ds
== 16))
2593 if (valid
& addrbits
) {
2594 ins
->addr_size
= addrbits
;
2595 } else if (valid
& ((addrbits
== 32) ? 16 : 32)) {
2596 /* Add an address size prefix */
2597 enum prefixes pref
= (addrbits
== 32) ? P_A16
: P_A32
;
2598 ins
->prefixes
[PPS_ASIZE
] = pref
;
2599 ins
->addr_size
= (addrbits
== 32) ? 16 : 32;
2602 errfunc(ERR_NONFATAL
, "impossible combination of address sizes");
2603 ins
->addr_size
= addrbits
; /* Error recovery */
2606 defdisp
= ins
->addr_size
== 16 ? 16 : 32;
2608 for (j
= 0; j
< ins
->operands
; j
++) {
2609 if (!(MEM_OFFS
& ~ins
->oprs
[j
].type
) &&
2610 (ins
->oprs
[j
].disp_size
? ins
->oprs
[j
].disp_size
: defdisp
)
2611 != ins
->addr_size
) {
2612 /* mem_offs sizes must match the address size; if not,
2613 strip the MEM_OFFS bit and match only EA instructions */
2614 ins
->oprs
[j
].type
&= ~(MEM_OFFS
& ~MEMORY
);