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preproc: Refactor smacro paramters expansion
[nasm/nasm.git] / assemble.c
blobed5ef8eaf6066b18eef3026879ae48997c742400
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2011 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - a signed byte immediate operand, from operand 0..3
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \140..\143 - an immediate word or signed byte for operand 0..3
64 * \144..\147 - or 2 (s-field) into opcode byte if operand 0..3
65 * is a signed byte rather than a word. Opcode byte follows.
66 * \150..\153 - an immediate dword or signed byte for operand 0..3
67 * \154..\157 - or 2 (s-field) into opcode byte if operand 0..3
68 * is a signed byte rather than a dword. Opcode byte follows.
69 * \160..\163 - this instruction uses DREX rather than REX, with the
70 * OC0 field set to 0, and the dest field taken from
71 * operand 0..3.
72 * \164..\167 - this instruction uses DREX rather than REX, with the
73 * OC0 field set to 1, and the dest field taken from
74 * operand 0..3.
75 * \171 - placement of DREX suffix in the absence of an EA
76 * \172\ab - the register number from operand a in bits 7..4, with
77 * the 4-bit immediate from operand b in bits 3..0.
78 * \173\xab - the register number from operand a in bits 7..4, with
79 * the value b in bits 3..0.
80 * \174\a - the register number from operand a in bits 7..4, and
81 * an arbitrary value in bits 3..0 (assembled as zero.)
82 * \2ab - a ModRM, calculated on EA in operand a, with the spare
83 * field equal to digit b.
84 * \250..\253 - same as \150..\153, except warn if the 64-bit operand
85 * is not equal to the truncated and sign-extended 32-bit
86 * operand; used for 32-bit immediates in 64-bit mode.
87 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
88 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
89 * V field taken from operand 0..3.
90 * \270 - this instruction uses VEX/XOP rather than REX, with the
91 * V field set to 1111b.
92 *
93 * VEX/XOP prefixes are followed by the sequence:
94 * \tmm\wlp where mm is the M field; and wlp is:
95 * 00 wwl lpp
96 * [l0] ll = 0 for L = 0 (.128, .lz)
97 * [l1] ll = 1 for L = 1 (.256)
98 * [lig] ll = 2 for L don't care (always assembled as 0)
99 *
100 * [w0] ww = 0 for W = 0
101 * [w1 ] ww = 1 for W = 1
102 * [wig] ww = 2 for W don't care (always assembled as 0)
103 * [ww] ww = 3 for W used as REX.W
104 *
105 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
106 *
107 * \274..\277 - a signed byte immediate operand, from operand 0..3,
108 * which is to be extended to the operand size.
109 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
110 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
111 * \312 - (disassembler only) invalid with non-default address size.
112 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
113 * \314 - (disassembler only) invalid with REX.B
114 * \315 - (disassembler only) invalid with REX.X
115 * \316 - (disassembler only) invalid with REX.R
116 * \317 - (disassembler only) invalid with REX.W
117 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
118 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
119 * \322 - indicates that this instruction is only valid when the
120 * operand size is the default (instruction to disassembler,
121 * generates no code in the assembler)
122 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
123 * \324 - indicates 64-bit operand size requiring REX prefix.
124 * \325 - instruction which always uses spl/bpl/sil/dil
125 * \330 - a literal byte follows in the code stream, to be added
126 * to the condition code value of the instruction.
127 * \331 - instruction not valid with REP prefix. Hint for
128 * disassembler only; for SSE instructions.
129 * \332 - REP prefix (0xF2 byte) used as opcode extension.
130 * \333 - REP prefix (0xF3 byte) used as opcode extension.
131 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
132 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
133 * \336 - force a REP(E) prefix (0xF2) even if not specified.
134 * \337 - force a REPNE prefix (0xF3) even if not specified.
135 * \336-\337 are still listed as prefixes in the disassembler.
136 * \340 - reserve <operand 0> bytes of uninitialized storage.
137 * Operand 0 had better be a segmentless constant.
138 * \341 - this instruction needs a WAIT "prefix"
139 * \344,\345 - the PUSH/POP (respectively) codes for CS, DS, ES, SS
140 * (POP is never used for CS) depending on operand 0
141 * \346,\347 - the second byte of PUSH/POP codes for FS, GS, depending
142 * on operand 0
143 * \360 - no SSE prefix (== \364\331)
144 * \361 - 66 SSE prefix (== \366\331)
145 * \362 - F2 SSE prefix (== \364\332)
146 * \363 - F3 SSE prefix (== \364\333)
147 * \364 - operand-size prefix (0x66) not permitted
148 * \365 - address-size prefix (0x67) not permitted
149 * \366 - operand-size prefix (0x66) used as opcode extension
150 * \367 - address-size prefix (0x67) used as opcode extension
151 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
152 * 370 is used for Jcc, 371 is used for JMP.
153 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
154 * used for conditional jump over longer jump
155 * \374 - this instruction takes an XMM VSIB memory EA
156 * \375 - this instruction takes an YMM VSIB memory EA
157 */
158
159 #include "compiler.h"
160
161 #include <stdio.h>
162 #include <string.h>
163 #include <inttypes.h>
164
165 #include "nasm.h"
166 #include "nasmlib.h"
167 #include "assemble.h"
168 #include "insns.h"
169 #include "tables.h"
170
171 enum match_result {
172 /*
173 * Matching errors. These should be sorted so that more specific
174 * errors come later in the sequence.
175 */
176 MERR_INVALOP,
177 MERR_OPSIZEMISSING,
178 MERR_OPSIZEMISMATCH,
179 MERR_BADCPU,
180 MERR_BADMODE,
181 /*
182 * Matching success; the conditional ones first
183 */
184 MOK_JUMP, /* Matching OK but needs jmp_match() */
185 MOK_GOOD /* Matching unconditionally OK */
186 };
187
188 typedef struct {
189 enum ea_type type; /* what kind of EA is this? */
190 int sib_present; /* is a SIB byte necessary? */
191 int bytes; /* # of bytes of offset needed */
192 int size; /* lazy - this is sib+bytes+1 */
193 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
194 } ea;
195
196 static uint32_t cpu; /* cpu level received from nasm.c */
197 static efunc errfunc;
198 static struct ofmt *outfmt;
199 static ListGen *list;
200
201 static int64_t calcsize(int32_t, int64_t, int, insn *, const uint8_t *);
202 static void gencode(int32_t segment, int64_t offset, int bits,
203 insn * ins, const struct itemplate *temp,
204 int64_t insn_end);
205 static enum match_result find_match(const struct itemplate **tempp,
206 insn *instruction,
207 int32_t segment, int64_t offset, int bits);
208 static enum match_result matches(const struct itemplate *, insn *, int bits);
209 static opflags_t regflag(const operand *);
210 static int32_t regval(const operand *);
211 static int rexflags(int, opflags_t, int);
212 static int op_rexflags(const operand *, int);
213 static void add_asp(insn *, int);
214
215 static enum ea_type process_ea(operand *, ea *, int, int, int, opflags_t);
216
217 static int has_prefix(insn * ins, enum prefix_pos pos, enum prefixes prefix)
218 {
219 return ins->prefixes[pos] == prefix;
220 }
221
222 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
223 {
224 if (ins->prefixes[pos])
225 errfunc(ERR_NONFATAL, "invalid %s prefix",
226 prefix_name(ins->prefixes[pos]));
227 }
228
229 static const char *size_name(int size)
230 {
231 switch (size) {
232 case 1:
233 return "byte";
234 case 2:
235 return "word";
236 case 4:
237 return "dword";
238 case 8:
239 return "qword";
240 case 10:
241 return "tword";
242 case 16:
243 return "oword";
244 case 32:
245 return "yword";
246 default:
247 return "???";
248 }
249 }
250
251 static void warn_overflow(int pass, int size)
252 {
253 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
254 "%s data exceeds bounds", size_name(size));
255 }
256
257 static void warn_overflow_const(int64_t data, int size)
258 {
259 if (overflow_general(data, size))
260 warn_overflow(ERR_PASS1, size);
261 }
262
263 static void warn_overflow_opd(const struct operand *o, int size)
264 {
265 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
266 if (overflow_general(o->offset, size))
267 warn_overflow(ERR_PASS2, size);
268 }
269 }
270
271 /*
272 * This routine wrappers the real output format's output routine,
273 * in order to pass a copy of the data off to the listing file
274 * generator at the same time.
275 */
276 static void out(int64_t offset, int32_t segto, const void *data,
277 enum out_type type, uint64_t size,
278 int32_t segment, int32_t wrt)
279 {
280 static int32_t lineno = 0; /* static!!! */
281 static char *lnfname = NULL;
282 uint8_t p[8];
283
284 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
285 /*
286 * This is a non-relocated address, and we're going to
287 * convert it into RAWDATA format.
288 */
289 uint8_t *q = p;
290
291 if (size > 8) {
292 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
293 return;
294 }
295
296 WRITEADDR(q, *(int64_t *)data, size);
297 data = p;
298 type = OUT_RAWDATA;
299 }
300
301 list->output(offset, data, type, size);
302
303 /*
304 * this call to src_get determines when we call the
305 * debug-format-specific "linenum" function
306 * it updates lineno and lnfname to the current values
307 * returning 0 if "same as last time", -2 if lnfname
308 * changed, and the amount by which lineno changed,
309 * if it did. thus, these variables must be static
310 */
311
312 if (src_get(&lineno, &lnfname))
313 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
314
315 outfmt->output(segto, data, type, size, segment, wrt);
316 }
317
318 static bool jmp_match(int32_t segment, int64_t offset, int bits,
319 insn * ins, const uint8_t *code)
320 {
321 int64_t isize;
322 uint8_t c = code[0];
323
324 if ((c != 0370 && c != 0371) || (ins->oprs[0].type & STRICT))
325 return false;
326 if (!optimizing)
327 return false;
328 if (optimizing < 0 && c == 0371)
329 return false;
330
331 isize = calcsize(segment, offset, bits, ins, code);
332
333 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
334 /* Be optimistic in pass 1 */
335 return true;
336
337 if (ins->oprs[0].segment != segment)
338 return false;
339
340 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
341 return (isize >= -128 && isize <= 127); /* is it byte size? */
342 }
343
344 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
345 insn * instruction, struct ofmt *output, efunc error,
346 ListGen * listgen)
347 {
348 const struct itemplate *temp;
349 int j;
350 enum match_result m;
351 int64_t insn_end;
352 int32_t itimes;
353 int64_t start = offset;
354 int64_t wsize; /* size for DB etc. */
355
356 errfunc = error; /* to pass to other functions */
357 cpu = cp;
358 outfmt = output; /* likewise */
359 list = listgen; /* and again */
360
361 wsize = idata_bytes(instruction->opcode);
362 if (wsize == -1)
363 return 0;
364
365 if (wsize) {
366 extop *e;
367 int32_t t = instruction->times;
368 if (t < 0)
369 errfunc(ERR_PANIC,
370 "instruction->times < 0 (%ld) in assemble()", t);
371
372 while (t--) { /* repeat TIMES times */
373 list_for_each(e, instruction->eops) {
374 if (e->type == EOT_DB_NUMBER) {
375 if (wsize > 8) {
376 errfunc(ERR_NONFATAL,
377 "integer supplied to a DT, DO or DY"
378 " instruction");
379 } else {
380 out(offset, segment, &e->offset,
381 OUT_ADDRESS, wsize, e->segment, e->wrt);
382 offset += wsize;
383 }
384 } else if (e->type == EOT_DB_STRING ||
385 e->type == EOT_DB_STRING_FREE) {
386 int align;
387
388 out(offset, segment, e->stringval,
389 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
390 align = e->stringlen % wsize;
391
392 if (align) {
393 align = wsize - align;
394 out(offset, segment, zero_buffer,
395 OUT_RAWDATA, align, NO_SEG, NO_SEG);
396 }
397 offset += e->stringlen + align;
398 }
399 }
400 if (t > 0 && t == instruction->times - 1) {
401 /*
402 * Dummy call to list->output to give the offset to the
403 * listing module.
404 */
405 list->output(offset, NULL, OUT_RAWDATA, 0);
406 list->uplevel(LIST_TIMES);
407 }
408 }
409 if (instruction->times > 1)
410 list->downlevel(LIST_TIMES);
411 return offset - start;
412 }
413
414 if (instruction->opcode == I_INCBIN) {
415 const char *fname = instruction->eops->stringval;
416 FILE *fp;
417
418 fp = fopen(fname, "rb");
419 if (!fp) {
420 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
421 fname);
422 } else if (fseek(fp, 0L, SEEK_END) < 0) {
423 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
424 fname);
425 } else {
426 static char buf[4096];
427 size_t t = instruction->times;
428 size_t base = 0;
429 size_t len;
430
431 len = ftell(fp);
432 if (instruction->eops->next) {
433 base = instruction->eops->next->offset;
434 len -= base;
435 if (instruction->eops->next->next &&
436 len > (size_t)instruction->eops->next->next->offset)
437 len = (size_t)instruction->eops->next->next->offset;
438 }
439 /*
440 * Dummy call to list->output to give the offset to the
441 * listing module.
442 */
443 list->output(offset, NULL, OUT_RAWDATA, 0);
444 list->uplevel(LIST_INCBIN);
445 while (t--) {
446 size_t l;
447
448 fseek(fp, base, SEEK_SET);
449 l = len;
450 while (l > 0) {
451 int32_t m;
452 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
453 if (!m) {
454 /*
455 * This shouldn't happen unless the file
456 * actually changes while we are reading
457 * it.
458 */
459 error(ERR_NONFATAL,
460 "`incbin': unexpected EOF while"
461 " reading file `%s'", fname);
462 t = 0; /* Try to exit cleanly */
463 break;
464 }
465 out(offset, segment, buf, OUT_RAWDATA, m,
466 NO_SEG, NO_SEG);
467 l -= m;
468 }
469 }
470 list->downlevel(LIST_INCBIN);
471 if (instruction->times > 1) {
472 /*
473 * Dummy call to list->output to give the offset to the
474 * listing module.
475 */
476 list->output(offset, NULL, OUT_RAWDATA, 0);
477 list->uplevel(LIST_TIMES);
478 list->downlevel(LIST_TIMES);
479 }
480 fclose(fp);
481 return instruction->times * len;
482 }
483 return 0; /* if we're here, there's an error */
484 }
485
486 /* Check to see if we need an address-size prefix */
487 add_asp(instruction, bits);
488
489 m = find_match(&temp, instruction, segment, offset, bits);
490
491 if (m == MOK_GOOD) {
492 /* Matches! */
493 int64_t insn_size = calcsize(segment, offset, bits,
494 instruction, temp->code);
495 itimes = instruction->times;
496 if (insn_size < 0) /* shouldn't be, on pass two */
497 error(ERR_PANIC, "errors made it through from pass one");
498 else
499 while (itimes--) {
500 for (j = 0; j < MAXPREFIX; j++) {
501 uint8_t c = 0;
502 switch (instruction->prefixes[j]) {
503 case P_WAIT:
504 c = 0x9B;
505 break;
506 case P_LOCK:
507 c = 0xF0;
508 break;
509 case P_REPNE:
510 case P_REPNZ:
511 c = 0xF2;
512 break;
513 case P_REPE:
514 case P_REPZ:
515 case P_REP:
516 c = 0xF3;
517 break;
518 case R_CS:
519 if (bits == 64) {
520 error(ERR_WARNING | ERR_PASS2,
521 "cs segment base generated, but will be ignored in 64-bit mode");
522 }
523 c = 0x2E;
524 break;
525 case R_DS:
526 if (bits == 64) {
527 error(ERR_WARNING | ERR_PASS2,
528 "ds segment base generated, but will be ignored in 64-bit mode");
529 }
530 c = 0x3E;
531 break;
532 case R_ES:
533 if (bits == 64) {
534 error(ERR_WARNING | ERR_PASS2,
535 "es segment base generated, but will be ignored in 64-bit mode");
536 }
537 c = 0x26;
538 break;
539 case R_FS:
540 c = 0x64;
541 break;
542 case R_GS:
543 c = 0x65;
544 break;
545 case R_SS:
546 if (bits == 64) {
547 error(ERR_WARNING | ERR_PASS2,
548 "ss segment base generated, but will be ignored in 64-bit mode");
549 }
550 c = 0x36;
551 break;
552 case R_SEGR6:
553 case R_SEGR7:
554 error(ERR_NONFATAL,
555 "segr6 and segr7 cannot be used as prefixes");
556 break;
557 case P_A16:
558 if (bits == 64) {
559 error(ERR_NONFATAL,
560 "16-bit addressing is not supported "
561 "in 64-bit mode");
562 } else if (bits != 16)
563 c = 0x67;
564 break;
565 case P_A32:
566 if (bits != 32)
567 c = 0x67;
568 break;
569 case P_A64:
570 if (bits != 64) {
571 error(ERR_NONFATAL,
572 "64-bit addressing is only supported "
573 "in 64-bit mode");
574 }
575 break;
576 case P_ASP:
577 c = 0x67;
578 break;
579 case P_O16:
580 if (bits != 16)
581 c = 0x66;
582 break;
583 case P_O32:
584 if (bits == 16)
585 c = 0x66;
586 break;
587 case P_O64:
588 /* REX.W */
589 break;
590 case P_OSP:
591 c = 0x66;
592 break;
593 case P_none:
594 break;
595 default:
596 error(ERR_PANIC, "invalid instruction prefix");
597 }
598 if (c != 0) {
599 out(offset, segment, &c, OUT_RAWDATA, 1,
600 NO_SEG, NO_SEG);
601 offset++;
602 }
603 }
604 insn_end = offset + insn_size;
605 gencode(segment, offset, bits, instruction,
606 temp, insn_end);
607 offset += insn_size;
608 if (itimes > 0 && itimes == instruction->times - 1) {
609 /*
610 * Dummy call to list->output to give the offset to the
611 * listing module.
612 */
613 list->output(offset, NULL, OUT_RAWDATA, 0);
614 list->uplevel(LIST_TIMES);
615 }
616 }
617 if (instruction->times > 1)
618 list->downlevel(LIST_TIMES);
619 return offset - start;
620 } else {
621 /* No match */
622 switch (m) {
623 case MERR_OPSIZEMISSING:
624 error(ERR_NONFATAL, "operation size not specified");
625 break;
626 case MERR_OPSIZEMISMATCH:
627 error(ERR_NONFATAL, "mismatch in operand sizes");
628 break;
629 case MERR_BADCPU:
630 error(ERR_NONFATAL, "no instruction for this cpu level");
631 break;
632 case MERR_BADMODE:
633 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
634 bits);
635 break;
636 default:
637 error(ERR_NONFATAL,
638 "invalid combination of opcode and operands");
639 break;
640 }
641 }
642 return 0;
643 }
644
645 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
646 insn * instruction, efunc error)
647 {
648 const struct itemplate *temp;
649 enum match_result m;
650
651 errfunc = error; /* to pass to other functions */
652 cpu = cp;
653
654 if (instruction->opcode == I_none)
655 return 0;
656
657 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
658 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
659 instruction->opcode == I_DT || instruction->opcode == I_DO ||
660 instruction->opcode == I_DY) {
661 extop *e;
662 int32_t isize, osize, wsize;
663
664 isize = 0;
665 wsize = idata_bytes(instruction->opcode);
666
667 list_for_each(e, instruction->eops) {
668 int32_t align;
669
670 osize = 0;
671 if (e->type == EOT_DB_NUMBER) {
672 osize = 1;
673 warn_overflow_const(e->offset, wsize);
674 } else if (e->type == EOT_DB_STRING ||
675 e->type == EOT_DB_STRING_FREE)
676 osize = e->stringlen;
677
678 align = (-osize) % wsize;
679 if (align < 0)
680 align += wsize;
681 isize += osize + align;
682 }
683 return isize * instruction->times;
684 }
685
686 if (instruction->opcode == I_INCBIN) {
687 const char *fname = instruction->eops->stringval;
688 FILE *fp;
689 int64_t val = 0;
690 size_t len;
691
692 fp = fopen(fname, "rb");
693 if (!fp)
694 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
695 fname);
696 else if (fseek(fp, 0L, SEEK_END) < 0)
697 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
698 fname);
699 else {
700 len = ftell(fp);
701 if (instruction->eops->next) {
702 len -= instruction->eops->next->offset;
703 if (instruction->eops->next->next &&
704 len > (size_t)instruction->eops->next->next->offset) {
705 len = (size_t)instruction->eops->next->next->offset;
706 }
707 }
708 val = instruction->times * len;
709 }
710 if (fp)
711 fclose(fp);
712 return val;
713 }
714
715 /* Check to see if we need an address-size prefix */
716 add_asp(instruction, bits);
717
718 m = find_match(&temp, instruction, segment, offset, bits);
719 if (m == MOK_GOOD) {
720 /* we've matched an instruction. */
721 int64_t isize;
722 const uint8_t *codes = temp->code;
723 int j;
724
725 isize = calcsize(segment, offset, bits, instruction, codes);
726 if (isize < 0)
727 return -1;
728 for (j = 0; j < MAXPREFIX; j++) {
729 switch (instruction->prefixes[j]) {
730 case P_A16:
731 if (bits != 16)
732 isize++;
733 break;
734 case P_A32:
735 if (bits != 32)
736 isize++;
737 break;
738 case P_O16:
739 if (bits != 16)
740 isize++;
741 break;
742 case P_O32:
743 if (bits == 16)
744 isize++;
745 break;
746 case P_A64:
747 case P_O64:
748 case P_none:
749 break;
750 default:
751 isize++;
752 break;
753 }
754 }
755 return isize * instruction->times;
756 } else {
757 return -1; /* didn't match any instruction */
758 }
759 }
760
761 static bool possible_sbyte(operand *o)
762 {
763 return o->wrt == NO_SEG && o->segment == NO_SEG &&
764 !(o->opflags & OPFLAG_UNKNOWN) &&
765 optimizing >= 0 && !(o->type & STRICT);
766 }
767
768 /* check that opn[op] is a signed byte of size 16 or 32 */
769 static bool is_sbyte16(operand *o)
770 {
771 int16_t v;
772
773 if (!possible_sbyte(o))
774 return false;
775
776 v = o->offset;
777 return v >= -128 && v <= 127;
778 }
779
780 static bool is_sbyte32(operand *o)
781 {
782 int32_t v;
783
784 if (!possible_sbyte(o))
785 return false;
786
787 v = o->offset;
788 return v >= -128 && v <= 127;
789 }
790
791 /* Common construct */
792 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
793
794 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
795 insn * ins, const uint8_t *codes)
796 {
797 int64_t length = 0;
798 uint8_t c;
799 int rex_mask = ~0;
800 int op1, op2;
801 struct operand *opx;
802 uint8_t opex = 0;
803 enum ea_type eat;
804
805 ins->rex = 0; /* Ensure REX is reset */
806 eat = EA_SCALAR; /* Expect a scalar EA */
807
808 if (ins->prefixes[PPS_OSIZE] == P_O64)
809 ins->rex |= REX_W;
810
811 (void)segment; /* Don't warn that this parameter is unused */
812 (void)offset; /* Don't warn that this parameter is unused */
813
814 while (*codes) {
815 c = *codes++;
816 op1 = (c & 3) + ((opex & 1) << 2);
817 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
818 opx = &ins->oprs[op1];
819 opex = 0; /* For the next iteration */
820
821 switch (c) {
822 case 01:
823 case 02:
824 case 03:
825 case 04:
826 codes += c, length += c;
827 break;
828
829 case 05:
830 case 06:
831 case 07:
832 opex = c;
833 break;
834
835 case4(010):
836 ins->rex |=
837 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
838 codes++, length++;
839 break;
840
841 case4(014):
842 case4(020):
843 case4(024):
844 length++;
845 break;
846
847 case4(030):
848 length += 2;
849 break;
850
851 case4(034):
852 if (opx->type & (BITS16 | BITS32 | BITS64))
853 length += (opx->type & BITS16) ? 2 : 4;
854 else
855 length += (bits == 16) ? 2 : 4;
856 break;
857
858 case4(040):
859 length += 4;
860 break;
861
862 case4(044):
863 length += ins->addr_size >> 3;
864 break;
865
866 case4(050):
867 length++;
868 break;
869
870 case4(054):
871 length += 8; /* MOV reg64/imm */
872 break;
873
874 case4(060):
875 length += 2;
876 break;
877
878 case4(064):
879 if (opx->type & (BITS16 | BITS32 | BITS64))
880 length += (opx->type & BITS16) ? 2 : 4;
881 else
882 length += (bits == 16) ? 2 : 4;
883 break;
884
885 case4(070):
886 length += 4;
887 break;
888
889 case4(074):
890 length += 2;
891 break;
892
893 case4(0140):
894 length += is_sbyte16(opx) ? 1 : 2;
895 break;
896
897 case4(0144):
898 codes++;
899 length++;
900 break;
901
902 case4(0150):
903 length += is_sbyte32(opx) ? 1 : 4;
904 break;
905
906 case4(0154):
907 codes++;
908 length++;
909 break;
910
911 case4(0160):
912 length++;
913 ins->rex |= REX_D;
914 ins->drexdst = regval(opx);
915 break;
916
917 case4(0164):
918 length++;
919 ins->rex |= REX_D|REX_OC;
920 ins->drexdst = regval(opx);
921 break;
922
923 case 0171:
924 break;
925
926 case 0172:
927 case 0173:
928 case 0174:
929 codes++;
930 length++;
931 break;
932
933 case4(0250):
934 length += is_sbyte32(opx) ? 1 : 4;
935 break;
936
937 case4(0254):
938 length += 4;
939 break;
940
941 case4(0260):
942 ins->rex |= REX_V;
943 ins->drexdst = regval(opx);
944 ins->vex_cm = *codes++;
945 ins->vex_wlp = *codes++;
946 break;
947
948 case 0270:
949 ins->rex |= REX_V;
950 ins->drexdst = 0;
951 ins->vex_cm = *codes++;
952 ins->vex_wlp = *codes++;
953 break;
954
955 case4(0274):
956 length++;
957 break;
958
959 case4(0300):
960 break;
961
962 case 0310:
963 if (bits == 64)
964 return -1;
965 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
966 break;
967
968 case 0311:
969 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
970 break;
971
972 case 0312:
973 break;
974
975 case 0313:
976 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
977 has_prefix(ins, PPS_ASIZE, P_A32))
978 return -1;
979 break;
980
981 case4(0314):
982 break;
983
984 case 0320:
985 {
986 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
987 if (pfx == P_O16)
988 break;
989 if (pfx != P_none)
990 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
991 else
992 ins->prefixes[PPS_OSIZE] = P_O16;
993 break;
994 }
995
996 case 0321:
997 {
998 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
999 if (pfx == P_O32)
1000 break;
1001 if (pfx != P_none)
1002 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1003 else
1004 ins->prefixes[PPS_OSIZE] = P_O32;
1005 break;
1006 }
1007
1008 case 0322:
1009 break;
1010
1011 case 0323:
1012 rex_mask &= ~REX_W;
1013 break;
1014
1015 case 0324:
1016 ins->rex |= REX_W;
1017 break;
1018
1019 case 0325:
1020 ins->rex |= REX_NH;
1021 break;
1022
1023 case 0330:
1024 codes++, length++;
1025 break;
1026
1027 case 0331:
1028 break;
1029
1030 case 0332:
1031 case 0333:
1032 length++;
1033 break;
1034
1035 case 0334:
1036 ins->rex |= REX_L;
1037 break;
1038
1039 case 0335:
1040 break;
1041
1042 case 0336:
1043 if (!ins->prefixes[PPS_LREP])
1044 ins->prefixes[PPS_LREP] = P_REP;
1045 break;
1046
1047 case 0337:
1048 if (!ins->prefixes[PPS_LREP])
1049 ins->prefixes[PPS_LREP] = P_REPNE;
1050 break;
1051
1052 case 0340:
1053 if (ins->oprs[0].segment != NO_SEG)
1054 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1055 " quantity of BSS space");
1056 else
1057 length += ins->oprs[0].offset;
1058 break;
1059
1060 case 0341:
1061 if (!ins->prefixes[PPS_WAIT])
1062 ins->prefixes[PPS_WAIT] = P_WAIT;
1063 break;
1064
1065 case4(0344):
1066 length++;
1067 break;
1068
1069 case 0360:
1070 break;
1071
1072 case 0361:
1073 case 0362:
1074 case 0363:
1075 length++;
1076 break;
1077
1078 case 0364:
1079 case 0365:
1080 break;
1081
1082 case 0366:
1083 case 0367:
1084 length++;
1085 break;
1086
1087 case 0370:
1088 case 0371:
1089 case 0372:
1090 break;
1091
1092 case 0373:
1093 length++;
1094 break;
1095
1096 case 0374:
1097 eat = EA_XMMVSIB;
1098 break;
1099
1100 case 0375:
1101 eat = EA_YMMVSIB;
1102 break;
1103
1104 case4(0100):
1105 case4(0110):
1106 case4(0120):
1107 case4(0130):
1108 case4(0200):
1109 case4(0204):
1110 case4(0210):
1111 case4(0214):
1112 case4(0220):
1113 case4(0224):
1114 case4(0230):
1115 case4(0234):
1116 {
1117 ea ea_data;
1118 int rfield;
1119 opflags_t rflags;
1120 struct operand *opy = &ins->oprs[op2];
1121
1122 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1123
1124 if (c <= 0177) {
1125 /* pick rfield from operand b (opx) */
1126 rflags = regflag(opx);
1127 rfield = nasm_regvals[opx->basereg];
1128 } else {
1129 rflags = 0;
1130 rfield = c & 7;
1131 }
1132 if (process_ea(opy, &ea_data, bits,ins->addr_size,
1133 rfield, rflags) != eat) {
1134 errfunc(ERR_NONFATAL, "invalid effective address");
1135 return -1;
1136 } else {
1137 ins->rex |= ea_data.rex;
1138 length += ea_data.size;
1139 }
1140 }
1141 break;
1142
1143 default:
1144 errfunc(ERR_PANIC, "internal instruction table corrupt"
1145 ": instruction code \\%o (0x%02X) given", c, c);
1146 break;
1147 }
1148 }
1149
1150 ins->rex &= rex_mask;
1151
1152 if (ins->rex & REX_NH) {
1153 if (ins->rex & REX_H) {
1154 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1155 return -1;
1156 }
1157 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1158 }
1159
1160 if (ins->rex & REX_V) {
1161 int bad32 = REX_R|REX_W|REX_X|REX_B;
1162
1163 if (ins->rex & REX_H) {
1164 errfunc(ERR_NONFATAL, "cannot use high register in vex instruction");
1165 return -1;
1166 }
1167 switch (ins->vex_wlp & 060) {
1168 case 000:
1169 case 040:
1170 ins->rex &= ~REX_W;
1171 break;
1172 case 020:
1173 ins->rex |= REX_W;
1174 bad32 &= ~REX_W;
1175 break;
1176 case 060:
1177 /* Follow REX_W */
1178 break;
1179 }
1180
1181 if (bits != 64 && ((ins->rex & bad32) || ins->drexdst > 7)) {
1182 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1183 return -1;
1184 }
1185 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1186 length += 3;
1187 else
1188 length += 2;
1189 } else if (ins->rex & REX_D) {
1190 if (ins->rex & REX_H) {
1191 errfunc(ERR_NONFATAL, "cannot use high register in drex instruction");
1192 return -1;
1193 }
1194 if (bits != 64 && ((ins->rex & (REX_R|REX_W|REX_X|REX_B)) ||
1195 ins->drexdst > 7)) {
1196 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1197 return -1;
1198 }
1199 length++;
1200 } else if (ins->rex & REX_REAL) {
1201 if (ins->rex & REX_H) {
1202 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1203 return -1;
1204 } else if (bits == 64) {
1205 length++;
1206 } else if ((ins->rex & REX_L) &&
1207 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1208 cpu >= IF_X86_64) {
1209 /* LOCK-as-REX.R */
1210 assert_no_prefix(ins, PPS_LREP);
1211 length++;
1212 } else {
1213 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1214 return -1;
1215 }
1216 }
1217
1218 return length;
1219 }
1220
1221 #define EMIT_REX() \
1222 if (!(ins->rex & (REX_D|REX_V)) && (ins->rex & REX_REAL) && (bits == 64)) { \
1223 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1224 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1225 ins->rex = 0; \
1226 offset += 1; \
1227 }
1228
1229 static void gencode(int32_t segment, int64_t offset, int bits,
1230 insn * ins, const struct itemplate *temp,
1231 int64_t insn_end)
1232 {
1233 static const char condval[] = { /* conditional opcodes */
1234 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1235 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1236 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1237 };
1238 uint8_t c;
1239 uint8_t bytes[4];
1240 int64_t size;
1241 int64_t data;
1242 int op1, op2;
1243 struct operand *opx;
1244 const uint8_t *codes = temp->code;
1245 uint8_t opex = 0;
1246 enum ea_type eat = EA_SCALAR;
1247
1248 while (*codes) {
1249 c = *codes++;
1250 op1 = (c & 3) + ((opex & 1) << 2);
1251 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1252 opx = &ins->oprs[op1];
1253 opex = 0; /* For the next iteration */
1254
1255 switch (c) {
1256 case 01:
1257 case 02:
1258 case 03:
1259 case 04:
1260 EMIT_REX();
1261 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1262 codes += c;
1263 offset += c;
1264 break;
1265
1266 case 05:
1267 case 06:
1268 case 07:
1269 opex = c;
1270 break;
1271
1272 case4(010):
1273 EMIT_REX();
1274 bytes[0] = *codes++ + (regval(opx) & 7);
1275 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1276 offset += 1;
1277 break;
1278
1279 case4(014):
1280 /*
1281 * The test for BITS8 and SBYTE here is intended to avoid
1282 * warning on optimizer actions due to SBYTE, while still
1283 * warn on explicit BYTE directives. Also warn, obviously,
1284 * if the optimizer isn't enabled.
1285 */
1286 if (((opx->type & BITS8) ||
1287 !(opx->type & temp->opd[op1] & BYTENESS)) &&
1288 (opx->offset < -128 || opx->offset > 127)) {
1289 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1290 "signed byte value exceeds bounds");
1291 }
1292 if (opx->segment != NO_SEG) {
1293 data = opx->offset;
1294 out(offset, segment, &data, OUT_ADDRESS, 1,
1295 opx->segment, opx->wrt);
1296 } else {
1297 bytes[0] = opx->offset;
1298 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1299 NO_SEG);
1300 }
1301 offset += 1;
1302 break;
1303
1304 case4(020):
1305 if (opx->offset < -256 || opx->offset > 255) {
1306 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1307 "byte value exceeds bounds");
1308 }
1309 if (opx->segment != NO_SEG) {
1310 data = opx->offset;
1311 out(offset, segment, &data, OUT_ADDRESS, 1,
1312 opx->segment, opx->wrt);
1313 } else {
1314 bytes[0] = opx->offset;
1315 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1316 NO_SEG);
1317 }
1318 offset += 1;
1319 break;
1320
1321 case4(024):
1322 if (opx->offset < 0 || opx->offset > 255)
1323 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1324 "unsigned byte value exceeds bounds");
1325 if (opx->segment != NO_SEG) {
1326 data = opx->offset;
1327 out(offset, segment, &data, OUT_ADDRESS, 1,
1328 opx->segment, opx->wrt);
1329 } else {
1330 bytes[0] = opx->offset;
1331 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1332 NO_SEG);
1333 }
1334 offset += 1;
1335 break;
1336
1337 case4(030):
1338 warn_overflow_opd(opx, 2);
1339 data = opx->offset;
1340 out(offset, segment, &data, OUT_ADDRESS, 2,
1341 opx->segment, opx->wrt);
1342 offset += 2;
1343 break;
1344
1345 case4(034):
1346 if (opx->type & (BITS16 | BITS32))
1347 size = (opx->type & BITS16) ? 2 : 4;
1348 else
1349 size = (bits == 16) ? 2 : 4;
1350 warn_overflow_opd(opx, size);
1351 data = opx->offset;
1352 out(offset, segment, &data, OUT_ADDRESS, size,
1353 opx->segment, opx->wrt);
1354 offset += size;
1355 break;
1356
1357 case4(040):
1358 warn_overflow_opd(opx, 4);
1359 data = opx->offset;
1360 out(offset, segment, &data, OUT_ADDRESS, 4,
1361 opx->segment, opx->wrt);
1362 offset += 4;
1363 break;
1364
1365 case4(044):
1366 data = opx->offset;
1367 size = ins->addr_size >> 3;
1368 warn_overflow_opd(opx, size);
1369 out(offset, segment, &data, OUT_ADDRESS, size,
1370 opx->segment, opx->wrt);
1371 offset += size;
1372 break;
1373
1374 case4(050):
1375 if (opx->segment != segment) {
1376 data = opx->offset;
1377 out(offset, segment, &data,
1378 OUT_REL1ADR, insn_end - offset,
1379 opx->segment, opx->wrt);
1380 } else {
1381 data = opx->offset - insn_end;
1382 if (data > 127 || data < -128)
1383 errfunc(ERR_NONFATAL, "short jump is out of range");
1384 out(offset, segment, &data,
1385 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1386 }
1387 offset += 1;
1388 break;
1389
1390 case4(054):
1391 data = (int64_t)opx->offset;
1392 out(offset, segment, &data, OUT_ADDRESS, 8,
1393 opx->segment, opx->wrt);
1394 offset += 8;
1395 break;
1396
1397 case4(060):
1398 if (opx->segment != segment) {
1399 data = opx->offset;
1400 out(offset, segment, &data,
1401 OUT_REL2ADR, insn_end - offset,
1402 opx->segment, opx->wrt);
1403 } else {
1404 data = opx->offset - insn_end;
1405 out(offset, segment, &data,
1406 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1407 }
1408 offset += 2;
1409 break;
1410
1411 case4(064):
1412 if (opx->type & (BITS16 | BITS32 | BITS64))
1413 size = (opx->type & BITS16) ? 2 : 4;
1414 else
1415 size = (bits == 16) ? 2 : 4;
1416 if (opx->segment != segment) {
1417 data = opx->offset;
1418 out(offset, segment, &data,
1419 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1420 insn_end - offset, opx->segment, opx->wrt);
1421 } else {
1422 data = opx->offset - insn_end;
1423 out(offset, segment, &data,
1424 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1425 }
1426 offset += size;
1427 break;
1428
1429 case4(070):
1430 if (opx->segment != segment) {
1431 data = opx->offset;
1432 out(offset, segment, &data,
1433 OUT_REL4ADR, insn_end - offset,
1434 opx->segment, opx->wrt);
1435 } else {
1436 data = opx->offset - insn_end;
1437 out(offset, segment, &data,
1438 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1439 }
1440 offset += 4;
1441 break;
1442
1443 case4(074):
1444 if (opx->segment == NO_SEG)
1445 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1446 " relocatable");
1447 data = 0;
1448 out(offset, segment, &data, OUT_ADDRESS, 2,
1449 outfmt->segbase(1 + opx->segment),
1450 opx->wrt);
1451 offset += 2;
1452 break;
1453
1454 case4(0140):
1455 data = opx->offset;
1456 warn_overflow_opd(opx, 2);
1457 if (is_sbyte16(opx)) {
1458 bytes[0] = data;
1459 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1460 NO_SEG);
1461 offset++;
1462 } else {
1463 out(offset, segment, &data, OUT_ADDRESS, 2,
1464 opx->segment, opx->wrt);
1465 offset += 2;
1466 }
1467 break;
1468
1469 case4(0144):
1470 EMIT_REX();
1471 bytes[0] = *codes++;
1472 if (is_sbyte16(opx))
1473 bytes[0] |= 2; /* s-bit */
1474 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1475 offset++;
1476 break;
1477
1478 case4(0150):
1479 data = opx->offset;
1480 warn_overflow_opd(opx, 4);
1481 if (is_sbyte32(opx)) {
1482 bytes[0] = data;
1483 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1484 NO_SEG);
1485 offset++;
1486 } else {
1487 out(offset, segment, &data, OUT_ADDRESS, 4,
1488 opx->segment, opx->wrt);
1489 offset += 4;
1490 }
1491 break;
1492
1493 case4(0154):
1494 EMIT_REX();
1495 bytes[0] = *codes++;
1496 if (is_sbyte32(opx))
1497 bytes[0] |= 2; /* s-bit */
1498 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1499 offset++;
1500 break;
1501
1502 case4(0160):
1503 case4(0164):
1504 break;
1505
1506 case 0171:
1507 bytes[0] =
1508 (ins->drexdst << 4) |
1509 (ins->rex & REX_OC ? 0x08 : 0) |
1510 (ins->rex & (REX_R|REX_X|REX_B));
1511 ins->rex = 0;
1512 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1513 offset++;
1514 break;
1515
1516 case 0172:
1517 c = *codes++;
1518 opx = &ins->oprs[c >> 3];
1519 bytes[0] = nasm_regvals[opx->basereg] << 4;
1520 opx = &ins->oprs[c & 7];
1521 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1522 errfunc(ERR_NONFATAL,
1523 "non-absolute expression not permitted as argument %d",
1524 c & 7);
1525 } else {
1526 if (opx->offset & ~15) {
1527 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1528 "four-bit argument exceeds bounds");
1529 }
1530 bytes[0] |= opx->offset & 15;
1531 }
1532 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1533 offset++;
1534 break;
1535
1536 case 0173:
1537 c = *codes++;
1538 opx = &ins->oprs[c >> 4];
1539 bytes[0] = nasm_regvals[opx->basereg] << 4;
1540 bytes[0] |= c & 15;
1541 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1542 offset++;
1543 break;
1544
1545 case 0174:
1546 c = *codes++;
1547 opx = &ins->oprs[c];
1548 bytes[0] = nasm_regvals[opx->basereg] << 4;
1549 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1550 offset++;
1551 break;
1552
1553 case4(0250):
1554 data = opx->offset;
1555 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1556 (int32_t)data != (int64_t)data) {
1557 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1558 "signed dword immediate exceeds bounds");
1559 }
1560 if (is_sbyte32(opx)) {
1561 bytes[0] = data;
1562 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1563 NO_SEG);
1564 offset++;
1565 } else {
1566 out(offset, segment, &data, OUT_ADDRESS, 4,
1567 opx->segment, opx->wrt);
1568 offset += 4;
1569 }
1570 break;
1571
1572 case4(0254):
1573 data = opx->offset;
1574 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1575 (int32_t)data != (int64_t)data) {
1576 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1577 "signed dword immediate exceeds bounds");
1578 }
1579 out(offset, segment, &data, OUT_ADDRESS, 4,
1580 opx->segment, opx->wrt);
1581 offset += 4;
1582 break;
1583
1584 case4(0260):
1585 case 0270:
1586 codes += 2;
1587 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1588 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1589 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1590 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1591 ((~ins->drexdst & 15)<< 3) | (ins->vex_wlp & 07);
1592 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1593 offset += 3;
1594 } else {
1595 bytes[0] = 0xc5;
1596 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1597 ((~ins->drexdst & 15) << 3) | (ins->vex_wlp & 07);
1598 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1599 offset += 2;
1600 }
1601 break;
1602
1603 case4(0274):
1604 {
1605 uint64_t uv, um;
1606 int s;
1607
1608 if (ins->rex & REX_W)
1609 s = 64;
1610 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1611 s = 16;
1612 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1613 s = 32;
1614 else
1615 s = bits;
1616
1617 um = (uint64_t)2 << (s-1);
1618 uv = opx->offset;
1619
1620 if (uv > 127 && uv < (uint64_t)-128 &&
1621 (uv < um-128 || uv > um-1)) {
1622 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1623 "signed byte value exceeds bounds");
1624 }
1625 if (opx->segment != NO_SEG) {
1626 data = uv;
1627 out(offset, segment, &data, OUT_ADDRESS, 1,
1628 opx->segment, opx->wrt);
1629 } else {
1630 bytes[0] = uv;
1631 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1632 NO_SEG);
1633 }
1634 offset += 1;
1635 break;
1636 }
1637
1638 case4(0300):
1639 break;
1640
1641 case 0310:
1642 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1643 *bytes = 0x67;
1644 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1645 offset += 1;
1646 } else
1647 offset += 0;
1648 break;
1649
1650 case 0311:
1651 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1652 *bytes = 0x67;
1653 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1654 offset += 1;
1655 } else
1656 offset += 0;
1657 break;
1658
1659 case 0312:
1660 break;
1661
1662 case 0313:
1663 ins->rex = 0;
1664 break;
1665
1666 case4(0314):
1667 break;
1668
1669 case 0320:
1670 case 0321:
1671 break;
1672
1673 case 0322:
1674 case 0323:
1675 break;
1676
1677 case 0324:
1678 ins->rex |= REX_W;
1679 break;
1680
1681 case 0325:
1682 break;
1683
1684 case 0330:
1685 *bytes = *codes++ ^ condval[ins->condition];
1686 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1687 offset += 1;
1688 break;
1689
1690 case 0331:
1691 break;
1692
1693 case 0332:
1694 case 0333:
1695 *bytes = c - 0332 + 0xF2;
1696 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1697 offset += 1;
1698 break;
1699
1700 case 0334:
1701 if (ins->rex & REX_R) {
1702 *bytes = 0xF0;
1703 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1704 offset += 1;
1705 }
1706 ins->rex &= ~(REX_L|REX_R);
1707 break;
1708
1709 case 0335:
1710 break;
1711
1712 case 0336:
1713 case 0337:
1714 break;
1715
1716 case 0340:
1717 if (ins->oprs[0].segment != NO_SEG)
1718 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1719 else {
1720 int64_t size = ins->oprs[0].offset;
1721 if (size > 0)
1722 out(offset, segment, NULL,
1723 OUT_RESERVE, size, NO_SEG, NO_SEG);
1724 offset += size;
1725 }
1726 break;
1727
1728 case 0341:
1729 break;
1730
1731 case 0344:
1732 case 0345:
1733 bytes[0] = c & 1;
1734 switch (ins->oprs[0].basereg) {
1735 case R_CS:
1736 bytes[0] += 0x0E;
1737 break;
1738 case R_DS:
1739 bytes[0] += 0x1E;
1740 break;
1741 case R_ES:
1742 bytes[0] += 0x06;
1743 break;
1744 case R_SS:
1745 bytes[0] += 0x16;
1746 break;
1747 default:
1748 errfunc(ERR_PANIC,
1749 "bizarre 8086 segment register received");
1750 }
1751 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1752 offset++;
1753 break;
1754
1755 case 0346:
1756 case 0347:
1757 bytes[0] = c & 1;
1758 switch (ins->oprs[0].basereg) {
1759 case R_FS:
1760 bytes[0] += 0xA0;
1761 break;
1762 case R_GS:
1763 bytes[0] += 0xA8;
1764 break;
1765 default:
1766 errfunc(ERR_PANIC,
1767 "bizarre 386 segment register received");
1768 }
1769 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1770 offset++;
1771 break;
1772
1773 case 0360:
1774 break;
1775
1776 case 0361:
1777 bytes[0] = 0x66;
1778 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1779 offset += 1;
1780 break;
1781
1782 case 0362:
1783 case 0363:
1784 bytes[0] = c - 0362 + 0xf2;
1785 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1786 offset += 1;
1787 break;
1788
1789 case 0364:
1790 case 0365:
1791 break;
1792
1793 case 0366:
1794 case 0367:
1795 *bytes = c - 0366 + 0x66;
1796 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1797 offset += 1;
1798 break;
1799
1800 case 0370:
1801 case 0371:
1802 case 0372:
1803 break;
1804
1805 case 0373:
1806 *bytes = bits == 16 ? 3 : 5;
1807 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1808 offset += 1;
1809 break;
1810
1811 case 0374:
1812 eat = EA_XMMVSIB;
1813 break;
1814
1815 case 0375:
1816 eat = EA_YMMVSIB;
1817 break;
1818
1819 case4(0100):
1820 case4(0110):
1821 case4(0120):
1822 case4(0130):
1823 case4(0200):
1824 case4(0204):
1825 case4(0210):
1826 case4(0214):
1827 case4(0220):
1828 case4(0224):
1829 case4(0230):
1830 case4(0234):
1831 {
1832 ea ea_data;
1833 int rfield;
1834 opflags_t rflags;
1835 uint8_t *p;
1836 int32_t s;
1837 enum out_type type;
1838 struct operand *opy = &ins->oprs[op2];
1839
1840 if (c <= 0177) {
1841 /* pick rfield from operand b (opx) */
1842 rflags = regflag(opx);
1843 rfield = nasm_regvals[opx->basereg];
1844 } else {
1845 /* rfield is constant */
1846 rflags = 0;
1847 rfield = c & 7;
1848 }
1849
1850 if (process_ea(opy, &ea_data, bits, ins->addr_size,
1851 rfield, rflags) != eat) {
1852 errfunc(ERR_NONFATAL, "invalid effective address");
1853 }
1854
1855
1856 p = bytes;
1857 *p++ = ea_data.modrm;
1858 if (ea_data.sib_present)
1859 *p++ = ea_data.sib;
1860
1861 /* DREX suffixes come between the SIB and the displacement */
1862 if (ins->rex & REX_D) {
1863 *p++ = (ins->drexdst << 4) |
1864 (ins->rex & REX_OC ? 0x08 : 0) |
1865 (ins->rex & (REX_R|REX_X|REX_B));
1866 ins->rex = 0;
1867 }
1868
1869 s = p - bytes;
1870 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1871
1872 /*
1873 * Make sure the address gets the right offset in case
1874 * the line breaks in the .lst file (BR 1197827)
1875 */
1876 offset += s;
1877 s = 0;
1878
1879 switch (ea_data.bytes) {
1880 case 0:
1881 break;
1882 case 1:
1883 case 2:
1884 case 4:
1885 case 8:
1886 data = opy->offset;
1887 s += ea_data.bytes;
1888 if (ea_data.rip) {
1889 if (opy->segment == segment) {
1890 data -= insn_end;
1891 if (overflow_signed(data, ea_data.bytes))
1892 warn_overflow(ERR_PASS2, ea_data.bytes);
1893 out(offset, segment, &data, OUT_ADDRESS,
1894 ea_data.bytes, NO_SEG, NO_SEG);
1895 } else {
1896 /* overflow check in output/linker? */
1897 out(offset, segment, &data, OUT_REL4ADR,
1898 insn_end - offset, opy->segment, opy->wrt);
1899 }
1900 } else {
1901 if (overflow_general(opy->offset, ins->addr_size >> 3) ||
1902 signed_bits(opy->offset, ins->addr_size) !=
1903 signed_bits(opy->offset, ea_data.bytes * 8))
1904 warn_overflow(ERR_PASS2, ea_data.bytes);
1905
1906 type = OUT_ADDRESS;
1907 out(offset, segment, &data, OUT_ADDRESS,
1908 ea_data.bytes, opy->segment, opy->wrt);
1909 }
1910 break;
1911 default:
1912 /* Impossible! */
1913 errfunc(ERR_PANIC,
1914 "Invalid amount of bytes (%d) for offset?!",
1915 ea_data.bytes);
1916 break;
1917 }
1918 offset += s;
1919 }
1920 break;
1921
1922 default:
1923 errfunc(ERR_PANIC, "internal instruction table corrupt"
1924 ": instruction code \\%o (0x%02X) given", c, c);
1925 break;
1926 }
1927 }
1928 }
1929
1930 static opflags_t regflag(const operand * o)
1931 {
1932 if (!is_register(o->basereg))
1933 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1934 return nasm_reg_flags[o->basereg];
1935 }
1936
1937 static int32_t regval(const operand * o)
1938 {
1939 if (!is_register(o->basereg))
1940 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1941 return nasm_regvals[o->basereg];
1942 }
1943
1944 static int op_rexflags(const operand * o, int mask)
1945 {
1946 opflags_t flags;
1947 int val;
1948
1949 if (!is_register(o->basereg))
1950 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1951
1952 flags = nasm_reg_flags[o->basereg];
1953 val = nasm_regvals[o->basereg];
1954
1955 return rexflags(val, flags, mask);
1956 }
1957
1958 static int rexflags(int val, opflags_t flags, int mask)
1959 {
1960 int rex = 0;
1961
1962 if (val >= 8)
1963 rex |= REX_B|REX_X|REX_R;
1964 if (flags & BITS64)
1965 rex |= REX_W;
1966 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1967 rex |= REX_H;
1968 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1969 rex |= REX_P;
1970
1971 return rex & mask;
1972 }
1973
1974 static enum match_result find_match(const struct itemplate **tempp,
1975 insn *instruction,
1976 int32_t segment, int64_t offset, int bits)
1977 {
1978 const struct itemplate *temp;
1979 enum match_result m, merr;
1980 opflags_t xsizeflags[MAX_OPERANDS];
1981 bool opsizemissing = false;
1982 int i;
1983
1984 for (i = 0; i < instruction->operands; i++)
1985 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
1986
1987 merr = MERR_INVALOP;
1988
1989 for (temp = nasm_instructions[instruction->opcode];
1990 temp->opcode != I_none; temp++) {
1991 m = matches(temp, instruction, bits);
1992 if (m == MOK_JUMP) {
1993 if (jmp_match(segment, offset, bits, instruction, temp->code))
1994 m = MOK_GOOD;
1995 else
1996 m = MERR_INVALOP;
1997 } else if (m == MERR_OPSIZEMISSING &&
1998 (temp->flags & IF_SMASK) != IF_SX) {
1999 /*
2000 * Missing operand size and a candidate for fuzzy matching...
2001 */
2002 for (i = 0; i < temp->operands; i++) {
2003 if ((temp->opd[i] & SAME_AS) == 0)
2004 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
2005 }
2006 opsizemissing = true;
2007 }
2008 if (m > merr)
2009 merr = m;
2010 if (merr == MOK_GOOD)
2011 goto done;
2012 }
2013
2014 /* No match, but see if we can get a fuzzy operand size match... */
2015 if (!opsizemissing)
2016 goto done;
2017
2018 for (i = 0; i < instruction->operands; i++) {
2019 /*
2020 * We ignore extrinsic operand sizes on registers, so we should
2021 * never try to fuzzy-match on them. This also resolves the case
2022 * when we have e.g. "xmmrm128" in two different positions.
2023 */
2024 if (is_class(REGISTER, instruction->oprs[i].type))
2025 continue;
2026
2027 /* This tests if xsizeflags[i] has more than one bit set */
2028 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2029 goto done; /* No luck */
2030
2031 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2032 }
2033
2034 /* Try matching again... */
2035 for (temp = nasm_instructions[instruction->opcode];
2036 temp->opcode != I_none; temp++) {
2037 m = matches(temp, instruction, bits);
2038 if (m == MOK_JUMP) {
2039 if (jmp_match(segment, offset, bits, instruction, temp->code))
2040 m = MOK_GOOD;
2041 else
2042 m = MERR_INVALOP;
2043 }
2044 if (m > merr)
2045 merr = m;
2046 if (merr == MOK_GOOD)
2047 goto done;
2048 }
2049
2050 done:
2051 *tempp = temp;
2052 return merr;
2053 }
2054
2055 static enum match_result matches(const struct itemplate *itemp,
2056 insn *instruction, int bits)
2057 {
2058 int i, size[MAX_OPERANDS], asize, oprs;
2059 bool opsizemissing = false;
2060
2061 /*
2062 * Check the opcode
2063 */
2064 if (itemp->opcode != instruction->opcode)
2065 return MERR_INVALOP;
2066
2067 /*
2068 * Count the operands
2069 */
2070 if (itemp->operands != instruction->operands)
2071 return MERR_INVALOP;
2072
2073 /*
2074 * Is it legal?
2075 */
2076 if (!(optimizing > 0) && (itemp->flags & IF_OPT))
2077 return MERR_INVALOP;
2078
2079 /*
2080 * Check that no spurious colons or TOs are present
2081 */
2082 for (i = 0; i < itemp->operands; i++)
2083 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2084 return MERR_INVALOP;
2085
2086 /*
2087 * Process size flags
2088 */
2089 switch (itemp->flags & IF_SMASK) {
2090 case IF_SB:
2091 asize = BITS8;
2092 break;
2093 case IF_SW:
2094 asize = BITS16;
2095 break;
2096 case IF_SD:
2097 asize = BITS32;
2098 break;
2099 case IF_SQ:
2100 asize = BITS64;
2101 break;
2102 case IF_SO:
2103 asize = BITS128;
2104 break;
2105 case IF_SY:
2106 asize = BITS256;
2107 break;
2108 case IF_SZ:
2109 switch (bits) {
2110 case 16:
2111 asize = BITS16;
2112 break;
2113 case 32:
2114 asize = BITS32;
2115 break;
2116 case 64:
2117 asize = BITS64;
2118 break;
2119 default:
2120 asize = 0;
2121 break;
2122 }
2123 break;
2124 default:
2125 asize = 0;
2126 break;
2127 }
2128
2129 if (itemp->flags & IF_ARMASK) {
2130 /* S- flags only apply to a specific operand */
2131 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
2132 memset(size, 0, sizeof size);
2133 size[i] = asize;
2134 } else {
2135 /* S- flags apply to all operands */
2136 for (i = 0; i < MAX_OPERANDS; i++)
2137 size[i] = asize;
2138 }
2139
2140 /*
2141 * Check that the operand flags all match up,
2142 * it's a bit tricky so lets be verbose:
2143 *
2144 * 1) Find out the size of operand. If instruction
2145 * doesn't have one specified -- we're trying to
2146 * guess it either from template (IF_S* flag) or
2147 * from code bits.
2148 *
2149 * 2) If template operand (i) has SAME_AS flag [used for registers only]
2150 * (ie the same operand as was specified somewhere in template, and
2151 * this referred operand index is being achieved via ~SAME_AS)
2152 * we are to be sure that both registers (in template and instruction)
2153 * do exactly match.
2154 *
2155 * 3) If template operand do not match the instruction OR
2156 * template has an operand size specified AND this size differ
2157 * from which instruction has (perhaps we got it from code bits)
2158 * we are:
2159 * a) Check that only size of instruction and operand is differ
2160 * other characteristics do match
2161 * b) Perhaps it's a register specified in instruction so
2162 * for such a case we just mark that operand as "size
2163 * missing" and this will turn on fuzzy operand size
2164 * logic facility (handled by a caller)
2165 */
2166 for (i = 0; i < itemp->operands; i++) {
2167 opflags_t type = instruction->oprs[i].type;
2168 if (!(type & SIZE_MASK))
2169 type |= size[i];
2170
2171 if (itemp->opd[i] & SAME_AS) {
2172 int j = itemp->opd[i] & ~SAME_AS;
2173 if (type != instruction->oprs[j].type ||
2174 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
2175 return MERR_INVALOP;
2176 } else if (itemp->opd[i] & ~type ||
2177 ((itemp->opd[i] & SIZE_MASK) &&
2178 ((itemp->opd[i] ^ type) & SIZE_MASK))) {
2179 if ((itemp->opd[i] & ~type & ~SIZE_MASK) || (type & SIZE_MASK)) {
2180 return MERR_INVALOP;
2181 } else if (!is_class(REGISTER, type)) {
2182 /*
2183 * Note: we don't honor extrinsic operand sizes for registers,
2184 * so "missing operand size" for a register should be
2185 * considered a wildcard match rather than an error.
2186 */
2187 opsizemissing = true;
2188 }
2189 }
2190 }
2191
2192 if (opsizemissing)
2193 return MERR_OPSIZEMISSING;
2194
2195 /*
2196 * Check operand sizes
2197 */
2198 if (itemp->flags & (IF_SM | IF_SM2)) {
2199 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2200 for (i = 0; i < oprs; i++) {
2201 asize = itemp->opd[i] & SIZE_MASK;
2202 if (asize) {
2203 for (i = 0; i < oprs; i++)
2204 size[i] = asize;
2205 break;
2206 }
2207 }
2208 } else {
2209 oprs = itemp->operands;
2210 }
2211
2212 for (i = 0; i < itemp->operands; i++) {
2213 if (!(itemp->opd[i] & SIZE_MASK) &&
2214 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2215 return MERR_OPSIZEMISMATCH;
2216 }
2217
2218 /*
2219 * Check template is okay at the set cpu level
2220 */
2221 if (((itemp->flags & IF_PLEVEL) > cpu))
2222 return MERR_BADCPU;
2223
2224 /*
2225 * Verify the appropriate long mode flag.
2226 */
2227 if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG)))
2228 return MERR_BADMODE;
2229
2230 /*
2231 * Check if special handling needed for Jumps
2232 */
2233 if ((itemp->code[0] & 0374) == 0370)
2234 return MOK_JUMP;
2235
2236 return MOK_GOOD;
2237 }
2238
2239 static enum ea_type process_ea(operand * input, ea * output, int bits,
2240 int addrbits, int rfield, opflags_t rflags)
2241 {
2242 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2243
2244 output->type = EA_SCALAR;
2245 output->rip = false;
2246
2247 /* REX flags for the rfield operand */
2248 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2249
2250 if (is_class(REGISTER, input->type)) { /* register direct */
2251 int i;
2252 opflags_t f;
2253
2254 if (!is_register(input->basereg))
2255 goto err;
2256 f = regflag(input);
2257 i = nasm_regvals[input->basereg];
2258
2259 if (REG_EA & ~f)
2260 goto err;
2261
2262 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2263
2264 output->sib_present = false; /* no SIB necessary */
2265 output->bytes = 0; /* no offset necessary either */
2266 output->modrm = 0xC0 | ((rfield & 7) << 3) | (i & 7);
2267 } else { /* it's a memory reference */
2268 if (input->basereg == -1 &&
2269 (input->indexreg == -1 || input->scale == 0)) {
2270 /* it's a pure offset */
2271
2272 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2273 input->segment == NO_SEG) {
2274 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2275 input->type &= ~IP_REL;
2276 input->type |= MEMORY;
2277 }
2278
2279 if (input->eaflags & EAF_BYTEOFFS ||
2280 (input->eaflags & EAF_WORDOFFS &&
2281 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2282 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2283 }
2284
2285 if (bits == 64 && (~input->type & IP_REL)) {
2286 int scale, index, base;
2287 output->sib_present = true;
2288 scale = 0;
2289 index = 4;
2290 base = 5;
2291 output->sib = (scale << 6) | (index << 3) | base;
2292 output->bytes = 4;
2293 output->modrm = 4 | ((rfield & 7) << 3);
2294 output->rip = false;
2295 } else {
2296 output->sib_present = false;
2297 output->bytes = (addrbits != 16 ? 4 : 2);
2298 output->modrm = (addrbits != 16 ? 5 : 6) | ((rfield & 7) << 3);
2299 output->rip = bits == 64;
2300 }
2301 } else { /* it's an indirection */
2302 int i = input->indexreg, b = input->basereg, s = input->scale;
2303 int32_t seg = input->segment;
2304 int hb = input->hintbase, ht = input->hinttype;
2305 int t, it, bt; /* register numbers */
2306 opflags_t x, ix, bx; /* register flags */
2307
2308 if (s == 0)
2309 i = -1; /* make this easy, at least */
2310
2311 if (is_register(i)) {
2312 it = nasm_regvals[i];
2313 ix = nasm_reg_flags[i];
2314 } else {
2315 it = -1;
2316 ix = 0;
2317 }
2318
2319 if (is_register(b)) {
2320 bt = nasm_regvals[b];
2321 bx = nasm_reg_flags[b];
2322 } else {
2323 bt = -1;
2324 bx = 0;
2325 }
2326
2327 /* if either one are a vector register... */
2328 if ((ix|bx) & (XMMREG|YMMREG) & ~REG_EA) {
2329 int32_t sok = BITS32 | BITS64;
2330 int32_t o = input->offset;
2331 int mod, scale, index, base;
2332
2333 printf("bt = %x, bx = %x, it = %x, ix = %x, s = %d\n",
2334 bt, bx, it, ix, s);
2335
2336 /*
2337 * For a vector SIB, one has to be a vector and the other,
2338 * if present, a GPR. The vector must be the index operand.
2339 */
2340 if (it == -1 || (bx & (XMMREG|YMMREG) & ~REG_EA)) {
2341 if (s == 0)
2342 s = 1;
2343 else if (s != 1)
2344 goto err;
2345
2346 t = bt, bt = it, it = t;
2347 x = bx, bx = ix, ix = x;
2348 }
2349
2350 if (bt != -1) {
2351 if (REG_GPR & ~bx)
2352 goto err;
2353 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2354 sok &= bx;
2355 else
2356 goto err;
2357 }
2358
2359 /*
2360 * While we're here, ensure the user didn't specify
2361 * WORD or QWORD
2362 */
2363 if (input->disp_size == 16 || input->disp_size == 64)
2364 goto err;
2365
2366 if (addrbits == 16 ||
2367 (addrbits == 32 && !(sok & BITS32)) ||
2368 (addrbits == 64 && !(sok & BITS64)))
2369 goto err;
2370
2371 output->type = (ix & YMMREG & ~REG_EA)
2372 ? EA_YMMVSIB : EA_XMMVSIB;
2373
2374 output->rex |= rexflags(it, ix, REX_X);
2375 output->rex |= rexflags(bt, bx, REX_B);
2376
2377 index = it & 7; /* it is known to be != -1 */
2378
2379 switch (s) {
2380 case 1:
2381 scale = 0;
2382 break;
2383 case 2:
2384 scale = 1;
2385 break;
2386 case 4:
2387 scale = 2;
2388 break;
2389 case 8:
2390 scale = 3;
2391 break;
2392 default: /* then what the smeg is it? */
2393 goto err; /* panic */
2394 }
2395
2396 if (bt == -1) {
2397 base = 5;
2398 mod = 0;
2399 } else {
2400 base = (bt & 7);
2401 if (base != REG_NUM_EBP && o == 0 &&
2402 seg == NO_SEG && !forw_ref &&
2403 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2404 mod = 0;
2405 else if (input->eaflags & EAF_BYTEOFFS ||
2406 (o >= -128 && o <= 127 &&
2407 seg == NO_SEG && !forw_ref &&
2408 !(input->eaflags & EAF_WORDOFFS)))
2409 mod = 1;
2410 else
2411 mod = 2;
2412 }
2413
2414 output->sib_present = true;
2415 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2416 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2417 output->sib = (scale << 6) | (index << 3) | base;
2418 } else if ((ix|bx) & (BITS32|BITS64)) {
2419 /*
2420 * it must be a 32/64-bit memory reference. Firstly we have
2421 * to check that all registers involved are type E/Rxx.
2422 */
2423 int32_t sok = BITS32 | BITS64;
2424 int32_t o = input->offset;
2425
2426 if (it != -1) {
2427 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2428 sok &= ix;
2429 else
2430 goto err;
2431 }
2432
2433 if (bt != -1) {
2434 if (REG_GPR & ~bx)
2435 goto err; /* Invalid register */
2436 if (~sok & bx & SIZE_MASK)
2437 goto err; /* Invalid size */
2438 sok &= bx;
2439 }
2440
2441 /*
2442 * While we're here, ensure the user didn't specify
2443 * WORD or QWORD
2444 */
2445 if (input->disp_size == 16 || input->disp_size == 64)
2446 goto err;
2447
2448 if (addrbits == 16 ||
2449 (addrbits == 32 && !(sok & BITS32)) ||
2450 (addrbits == 64 && !(sok & BITS64)))
2451 goto err;
2452
2453 /* now reorganize base/index */
2454 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2455 ((hb == b && ht == EAH_NOTBASE) ||
2456 (hb == i && ht == EAH_MAKEBASE))) {
2457 /* swap if hints say so */
2458 t = bt, bt = it, it = t;
2459 x = bx, bx = ix, ix = x;
2460 }
2461 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2462 bt = -1, bx = 0, s++;
2463 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2464 /* make single reg base, unless hint */
2465 bt = it, bx = ix, it = -1, ix = 0;
2466 }
2467 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2468 s == 3 || s == 5 || s == 9) && bt == -1)
2469 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2470 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2471 (input->eaflags & EAF_TIMESTWO))
2472 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2473 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2474 if (s == 1 && it == REG_NUM_ESP) {
2475 /* swap ESP into base if scale is 1 */
2476 t = it, it = bt, bt = t;
2477 x = ix, ix = bx, bx = x;
2478 }
2479 if (it == REG_NUM_ESP ||
2480 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2481 goto err; /* wrong, for various reasons */
2482
2483 output->rex |= rexflags(it, ix, REX_X);
2484 output->rex |= rexflags(bt, bx, REX_B);
2485
2486 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2487 /* no SIB needed */
2488 int mod, rm;
2489
2490 if (bt == -1) {
2491 rm = 5;
2492 mod = 0;
2493 } else {
2494 rm = (bt & 7);
2495 if (rm != REG_NUM_EBP && o == 0 &&
2496 seg == NO_SEG && !forw_ref &&
2497 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2498 mod = 0;
2499 else if (input->eaflags & EAF_BYTEOFFS ||
2500 (o >= -128 && o <= 127 &&
2501 seg == NO_SEG && !forw_ref &&
2502 !(input->eaflags & EAF_WORDOFFS)))
2503 mod = 1;
2504 else
2505 mod = 2;
2506 }
2507
2508 output->sib_present = false;
2509 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2510 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2511 } else {
2512 /* we need a SIB */
2513 int mod, scale, index, base;
2514
2515 if (it == -1)
2516 index = 4, s = 1;
2517 else
2518 index = (it & 7);
2519
2520 switch (s) {
2521 case 1:
2522 scale = 0;
2523 break;
2524 case 2:
2525 scale = 1;
2526 break;
2527 case 4:
2528 scale = 2;
2529 break;
2530 case 8:
2531 scale = 3;
2532 break;
2533 default: /* then what the smeg is it? */
2534 goto err; /* panic */
2535 }
2536
2537 if (bt == -1) {
2538 base = 5;
2539 mod = 0;
2540 } else {
2541 base = (bt & 7);
2542 if (base != REG_NUM_EBP && o == 0 &&
2543 seg == NO_SEG && !forw_ref &&
2544 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2545 mod = 0;
2546 else if (input->eaflags & EAF_BYTEOFFS ||
2547 (o >= -128 && o <= 127 &&
2548 seg == NO_SEG && !forw_ref &&
2549 !(input->eaflags & EAF_WORDOFFS)))
2550 mod = 1;
2551 else
2552 mod = 2;
2553 }
2554
2555 output->sib_present = true;
2556 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2557 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2558 output->sib = (scale << 6) | (index << 3) | base;
2559 }
2560 } else { /* it's 16-bit */
2561 int mod, rm;
2562 int16_t o = input->offset;
2563
2564 /* check for 64-bit long mode */
2565 if (addrbits == 64)
2566 goto err;
2567
2568 /* check all registers are BX, BP, SI or DI */
2569 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2570 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2571 goto err;
2572
2573 /* ensure the user didn't specify DWORD/QWORD */
2574 if (input->disp_size == 32 || input->disp_size == 64)
2575 goto err;
2576
2577 if (s != 1 && i != -1)
2578 goto err; /* no can do, in 16-bit EA */
2579 if (b == -1 && i != -1) {
2580 int tmp = b;
2581 b = i;
2582 i = tmp;
2583 } /* swap */
2584 if ((b == R_SI || b == R_DI) && i != -1) {
2585 int tmp = b;
2586 b = i;
2587 i = tmp;
2588 }
2589 /* have BX/BP as base, SI/DI index */
2590 if (b == i)
2591 goto err; /* shouldn't ever happen, in theory */
2592 if (i != -1 && b != -1 &&
2593 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2594 goto err; /* invalid combinations */
2595 if (b == -1) /* pure offset: handled above */
2596 goto err; /* so if it gets to here, panic! */
2597
2598 rm = -1;
2599 if (i != -1)
2600 switch (i * 256 + b) {
2601 case R_SI * 256 + R_BX:
2602 rm = 0;
2603 break;
2604 case R_DI * 256 + R_BX:
2605 rm = 1;
2606 break;
2607 case R_SI * 256 + R_BP:
2608 rm = 2;
2609 break;
2610 case R_DI * 256 + R_BP:
2611 rm = 3;
2612 break;
2613 } else
2614 switch (b) {
2615 case R_SI:
2616 rm = 4;
2617 break;
2618 case R_DI:
2619 rm = 5;
2620 break;
2621 case R_BP:
2622 rm = 6;
2623 break;
2624 case R_BX:
2625 rm = 7;
2626 break;
2627 }
2628 if (rm == -1) /* can't happen, in theory */
2629 goto err; /* so panic if it does */
2630
2631 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2632 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2633 mod = 0;
2634 else if (input->eaflags & EAF_BYTEOFFS ||
2635 (o >= -128 && o <= 127 && seg == NO_SEG &&
2636 !forw_ref && !(input->eaflags & EAF_WORDOFFS)))
2637 mod = 1;
2638 else
2639 mod = 2;
2640
2641 output->sib_present = false; /* no SIB - it's 16-bit */
2642 output->bytes = mod; /* bytes of offset needed */
2643 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2644 }
2645 }
2646 }
2647
2648 output->size = 1 + output->sib_present + output->bytes;
2649 return output->type;
2650
2651 err:
2652 return output->type = EA_INVALID;
2653 }
2654
2655 static void add_asp(insn *ins, int addrbits)
2656 {
2657 int j, valid;
2658 int defdisp;
2659
2660 valid = (addrbits == 64) ? 64|32 : 32|16;
2661
2662 switch (ins->prefixes[PPS_ASIZE]) {
2663 case P_A16:
2664 valid &= 16;
2665 break;
2666 case P_A32:
2667 valid &= 32;
2668 break;
2669 case P_A64:
2670 valid &= 64;
2671 break;
2672 case P_ASP:
2673 valid &= (addrbits == 32) ? 16 : 32;
2674 break;
2675 default:
2676 break;
2677 }
2678
2679 for (j = 0; j < ins->operands; j++) {
2680 if (is_class(MEMORY, ins->oprs[j].type)) {
2681 opflags_t i, b;
2682
2683 /* Verify as Register */
2684 if (!is_register(ins->oprs[j].indexreg))
2685 i = 0;
2686 else
2687 i = nasm_reg_flags[ins->oprs[j].indexreg];
2688
2689 /* Verify as Register */
2690 if (!is_register(ins->oprs[j].basereg))
2691 b = 0;
2692 else
2693 b = nasm_reg_flags[ins->oprs[j].basereg];
2694
2695 if (ins->oprs[j].scale == 0)
2696 i = 0;
2697
2698 if (!i && !b) {
2699 int ds = ins->oprs[j].disp_size;
2700 if ((addrbits != 64 && ds > 8) ||
2701 (addrbits == 64 && ds == 16))
2702 valid &= ds;
2703 } else {
2704 if (!(REG16 & ~b))
2705 valid &= 16;
2706 if (!(REG32 & ~b))
2707 valid &= 32;
2708 if (!(REG64 & ~b))
2709 valid &= 64;
2710
2711 if (!(REG16 & ~i))
2712 valid &= 16;
2713 if (!(REG32 & ~i))
2714 valid &= 32;
2715 if (!(REG64 & ~i))
2716 valid &= 64;
2717 }
2718 }
2719 }
2720
2721 if (valid & addrbits) {
2722 ins->addr_size = addrbits;
2723 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2724 /* Add an address size prefix */
2725 enum prefixes pref = (addrbits == 32) ? P_A16 : P_A32;
2726 ins->prefixes[PPS_ASIZE] = pref;
2727 ins->addr_size = (addrbits == 32) ? 16 : 32;
2728 } else {
2729 /* Impossible... */
2730 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2731 ins->addr_size = addrbits; /* Error recovery */
2732 }
2733
2734 defdisp = ins->addr_size == 16 ? 16 : 32;
2735
2736 for (j = 0; j < ins->operands; j++) {
2737 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2738 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2739 /*
2740 * mem_offs sizes must match the address size; if not,
2741 * strip the MEM_OFFS bit and match only EA instructions
2742 */
2743 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2744 }
2745 }
2746 }
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