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AVX-512: Fix instruction match function
[nasm/avx512.git] / assemble.c
blob83971f62697978961a4ebe321d20709e883e9682
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2013 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \20..\23 - a byte immediate operand, from operand 0..3
46 * \24..\27 - a zero-extended byte immediate operand, from operand 0..3
47 * \30..\33 - a word immediate operand, from operand 0..3
48 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
49 * assembly mode or the operand-size override on the operand
50 * \40..\43 - a long immediate operand, from operand 0..3
51 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
52 * depending on the address size of the instruction.
53 * \50..\53 - a byte relative operand, from operand 0..3
54 * \54..\57 - a qword immediate operand, from operand 0..3
55 * \60..\63 - a word relative operand, from operand 0..3
56 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
57 * assembly mode or the operand-size override on the operand
58 * \70..\73 - a long relative operand, from operand 0..3
59 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
60 * \1ab - a ModRM, calculated on EA in operand a, with the spare
61 * field the register value of operand b.
62 * \172\ab - the register number from operand a in bits 7..4, with
63 * the 4-bit immediate from operand b in bits 3..0.
64 * \173\xab - the register number from operand a in bits 7..4, with
65 * the value b in bits 3..0.
66 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
67 * an arbitrary value in bits 3..0 (assembled as zero.)
68 * \2ab - a ModRM, calculated on EA in operand a, with the spare
69 * field equal to digit b.
70 *
71 * \240..\243 - this instruction uses EVEX rather than REX or VEX/XOP, with the
72 * V field taken from operand 0..3.
73 * \250 - this instruction uses EVEX rather than REX or VEX/XOP, with the
74 * V field set to 1111b.
75 * EVEX prefixes are followed by the sequence:
76 * \cm\wlp\tup where cm is:
77 * cc 000 0mm
78 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
79 * and wlp is:
80 * 00 wwl lpp
81 * [l0] ll = 0 (.128, .lz)
82 * [l1] ll = 1 (.256)
83 * [l2] ll = 2 (.512)
84 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
85 *
86 * [w0] ww = 0 for W = 0
87 * [w1] ww = 1 for W = 1
88 * [wig] ww = 2 for W don't care (always assembled as 0)
89 * [ww] ww = 3 for W used as REX.W
90 *
91 * [p0] pp = 0 for no prefix
92 * [60] pp = 1 for legacy prefix 60
93 * [f3] pp = 2
94 * [f2] pp = 3
95 *
96 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
97 * (compressed displacement encoding)
98 *
99 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
100 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
101 * V field taken from operand 0..3.
102 * \270 - this instruction uses VEX/XOP rather than REX, with the
103 * V field set to 1111b.
104 *
105 * VEX/XOP prefixes are followed by the sequence:
106 * \tmm\wlp where mm is the M field; and wlp is:
107 * 00 wwl lpp
108 * [l0] ll = 0 for L = 0 (.128, .lz)
109 * [l1] ll = 1 for L = 1 (.256)
110 * [lig] ll = 2 for L don't care (always assembled as 0)
111 *
112 * [w0] ww = 0 for W = 0
113 * [w1 ] ww = 1 for W = 1
114 * [wig] ww = 2 for W don't care (always assembled as 0)
115 * [ww] ww = 3 for W used as REX.W
116 *
117 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
118 *
119 * \271 - instruction takes XRELEASE (F3) with or without lock
120 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
121 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
122 * \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
123 * to the operand size (if o16/o32/o64 present) or the bit size
124 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
125 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
126 * \312 - (disassembler only) invalid with non-default address size.
127 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
128 * \314 - (disassembler only) invalid with REX.B
129 * \315 - (disassembler only) invalid with REX.X
130 * \316 - (disassembler only) invalid with REX.R
131 * \317 - (disassembler only) invalid with REX.W
132 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
133 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
134 * \322 - indicates that this instruction is only valid when the
135 * operand size is the default (instruction to disassembler,
136 * generates no code in the assembler)
137 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
138 * \324 - indicates 64-bit operand size requiring REX prefix.
139 * \325 - instruction which always uses spl/bpl/sil/dil
140 * \326 - instruction not valid with 0xF3 REP prefix. Hint for
141 disassembler only; for SSE instructions.
142 * \330 - a literal byte follows in the code stream, to be added
143 * to the condition code value of the instruction.
144 * \331 - instruction not valid with REP prefix. Hint for
145 * disassembler only; for SSE instructions.
146 * \332 - REP prefix (0xF2 byte) used as opcode extension.
147 * \333 - REP prefix (0xF3 byte) used as opcode extension.
148 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
149 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
150 * \336 - force a REP(E) prefix (0xF3) even if not specified.
151 * \337 - force a REPNE prefix (0xF2) even if not specified.
152 * \336-\337 are still listed as prefixes in the disassembler.
153 * \340 - reserve <operand 0> bytes of uninitialized storage.
154 * Operand 0 had better be a segmentless constant.
155 * \341 - this instruction needs a WAIT "prefix"
156 * \360 - no SSE prefix (== \364\331)
157 * \361 - 66 SSE prefix (== \366\331)
158 * \364 - operand-size prefix (0x66) not permitted
159 * \365 - address-size prefix (0x67) not permitted
160 * \366 - operand-size prefix (0x66) used as opcode extension
161 * \367 - address-size prefix (0x67) used as opcode extension
162 * \370,\371 - match only if operand 0 meets byte jump criteria.
163 * 370 is used for Jcc, 371 is used for JMP.
164 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
165 * used for conditional jump over longer jump
166 * \374 - this instruction takes an XMM VSIB memory EA
167 * \375 - this instruction takes an YMM VSIB memory EA
168 * \376 - this instruction takes an ZMM VSIB memory EA
169 */
170
171 #include "compiler.h"
172
173 #include <stdio.h>
174 #include <string.h>
175 #include <inttypes.h>
176
177 #include "nasm.h"
178 #include "nasmlib.h"
179 #include "assemble.h"
180 #include "insns.h"
181 #include "tables.h"
182
183 enum match_result {
184 /*
185 * Matching errors. These should be sorted so that more specific
186 * errors come later in the sequence.
187 */
188 MERR_INVALOP,
189 MERR_OPSIZEMISSING,
190 MERR_OPSIZEMISMATCH,
191 MERR_BADCPU,
192 MERR_BADMODE,
193 MERR_BADHLE,
194 /*
195 * Matching success; the conditional ones first
196 */
197 MOK_JUMP, /* Matching OK but needs jmp_match() */
198 MOK_GOOD /* Matching unconditionally OK */
199 };
200
201 typedef struct {
202 enum ea_type type; /* what kind of EA is this? */
203 int sib_present; /* is a SIB byte necessary? */
204 int bytes; /* # of bytes of offset needed */
205 int size; /* lazy - this is sib+bytes+1 */
206 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
207 int8_t disp8; /* compressed displacement for EVEX */
208 } ea;
209
210 #define GEN_SIB(scale, index, base) \
211 (((scale) << 6) | ((index) << 3) | ((base)))
212
213 #define GEN_MODRM(mod, reg, rm) \
214 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
215
216 static uint32_t cpu; /* cpu level received from nasm.c */
217 static efunc errfunc;
218 static struct ofmt *outfmt;
219 static ListGen *list;
220
221 static int64_t calcsize(int32_t, int64_t, int, insn *,
222 const struct itemplate *);
223 static void gencode(int32_t segment, int64_t offset, int bits,
224 insn * ins, const struct itemplate *temp,
225 int64_t insn_end);
226 static enum match_result find_match(const struct itemplate **tempp,
227 insn *instruction,
228 int32_t segment, int64_t offset, int bits);
229 static enum match_result matches(const struct itemplate *, insn *, int bits);
230 static opflags_t regflag(const operand *);
231 static int32_t regval(const operand *);
232 static int rexflags(int, opflags_t, int);
233 static int op_rexflags(const operand *, int);
234 static int op_evexflags(const operand *, int, uint8_t);
235 static void add_asp(insn *, int);
236
237 static enum ea_type process_ea(operand *, ea *, int, int, opflags_t, insn *);
238
239 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
240 {
241 return ins->prefixes[pos] == prefix;
242 }
243
244 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
245 {
246 if (ins->prefixes[pos])
247 errfunc(ERR_NONFATAL, "invalid %s prefix",
248 prefix_name(ins->prefixes[pos]));
249 }
250
251 static const char *size_name(int size)
252 {
253 switch (size) {
254 case 1:
255 return "byte";
256 case 2:
257 return "word";
258 case 4:
259 return "dword";
260 case 8:
261 return "qword";
262 case 10:
263 return "tword";
264 case 16:
265 return "oword";
266 case 32:
267 return "yword";
268 default:
269 return "???";
270 }
271 }
272
273 static void warn_overflow(int pass, int size)
274 {
275 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
276 "%s data exceeds bounds", size_name(size));
277 }
278
279 static void warn_overflow_const(int64_t data, int size)
280 {
281 if (overflow_general(data, size))
282 warn_overflow(ERR_PASS1, size);
283 }
284
285 static void warn_overflow_opd(const struct operand *o, int size)
286 {
287 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
288 if (overflow_general(o->offset, size))
289 warn_overflow(ERR_PASS2, size);
290 }
291 }
292
293 /*
294 * This routine wrappers the real output format's output routine,
295 * in order to pass a copy of the data off to the listing file
296 * generator at the same time.
297 */
298 static void out(int64_t offset, int32_t segto, const void *data,
299 enum out_type type, uint64_t size,
300 int32_t segment, int32_t wrt)
301 {
302 static int32_t lineno = 0; /* static!!! */
303 static char *lnfname = NULL;
304 uint8_t p[8];
305
306 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
307 /*
308 * This is a non-relocated address, and we're going to
309 * convert it into RAWDATA format.
310 */
311 uint8_t *q = p;
312
313 if (size > 8) {
314 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
315 return;
316 }
317
318 WRITEADDR(q, *(int64_t *)data, size);
319 data = p;
320 type = OUT_RAWDATA;
321 }
322
323 list->output(offset, data, type, size);
324
325 /*
326 * this call to src_get determines when we call the
327 * debug-format-specific "linenum" function
328 * it updates lineno and lnfname to the current values
329 * returning 0 if "same as last time", -2 if lnfname
330 * changed, and the amount by which lineno changed,
331 * if it did. thus, these variables must be static
332 */
333
334 if (src_get(&lineno, &lnfname))
335 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
336
337 outfmt->output(segto, data, type, size, segment, wrt);
338 }
339
340 static void out_imm8(int64_t offset, int32_t segment, struct operand *opx)
341 {
342 if (opx->segment != NO_SEG) {
343 uint64_t data = opx->offset;
344 out(offset, segment, &data, OUT_ADDRESS, 1, opx->segment, opx->wrt);
345 } else {
346 uint8_t byte = opx->offset;
347 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
348 }
349 }
350
351 static bool jmp_match(int32_t segment, int64_t offset, int bits,
352 insn * ins, const struct itemplate *temp)
353 {
354 int64_t isize;
355 const uint8_t *code = temp->code;
356 uint8_t c = code[0];
357
358 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
359 return false;
360 if (!optimizing)
361 return false;
362 if (optimizing < 0 && c == 0371)
363 return false;
364
365 isize = calcsize(segment, offset, bits, ins, temp);
366
367 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
368 /* Be optimistic in pass 1 */
369 return true;
370
371 if (ins->oprs[0].segment != segment)
372 return false;
373
374 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
375 return (isize >= -128 && isize <= 127); /* is it byte size? */
376 }
377
378 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
379 insn * instruction, struct ofmt *output, efunc error,
380 ListGen * listgen)
381 {
382 const struct itemplate *temp;
383 int j;
384 enum match_result m;
385 int64_t insn_end;
386 int32_t itimes;
387 int64_t start = offset;
388 int64_t wsize; /* size for DB etc. */
389
390 errfunc = error; /* to pass to other functions */
391 cpu = cp;
392 outfmt = output; /* likewise */
393 list = listgen; /* and again */
394
395 wsize = idata_bytes(instruction->opcode);
396 if (wsize == -1)
397 return 0;
398
399 if (wsize) {
400 extop *e;
401 int32_t t = instruction->times;
402 if (t < 0)
403 errfunc(ERR_PANIC,
404 "instruction->times < 0 (%ld) in assemble()", t);
405
406 while (t--) { /* repeat TIMES times */
407 list_for_each(e, instruction->eops) {
408 if (e->type == EOT_DB_NUMBER) {
409 if (wsize > 8) {
410 errfunc(ERR_NONFATAL,
411 "integer supplied to a DT, DO or DY"
412 " instruction");
413 } else {
414 out(offset, segment, &e->offset,
415 OUT_ADDRESS, wsize, e->segment, e->wrt);
416 offset += wsize;
417 }
418 } else if (e->type == EOT_DB_STRING ||
419 e->type == EOT_DB_STRING_FREE) {
420 int align;
421
422 out(offset, segment, e->stringval,
423 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
424 align = e->stringlen % wsize;
425
426 if (align) {
427 align = wsize - align;
428 out(offset, segment, zero_buffer,
429 OUT_RAWDATA, align, NO_SEG, NO_SEG);
430 }
431 offset += e->stringlen + align;
432 }
433 }
434 if (t > 0 && t == instruction->times - 1) {
435 /*
436 * Dummy call to list->output to give the offset to the
437 * listing module.
438 */
439 list->output(offset, NULL, OUT_RAWDATA, 0);
440 list->uplevel(LIST_TIMES);
441 }
442 }
443 if (instruction->times > 1)
444 list->downlevel(LIST_TIMES);
445 return offset - start;
446 }
447
448 if (instruction->opcode == I_INCBIN) {
449 const char *fname = instruction->eops->stringval;
450 FILE *fp;
451
452 fp = fopen(fname, "rb");
453 if (!fp) {
454 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
455 fname);
456 } else if (fseek(fp, 0L, SEEK_END) < 0) {
457 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
458 fname);
459 fclose(fp);
460 } else {
461 static char buf[4096];
462 size_t t = instruction->times;
463 size_t base = 0;
464 size_t len;
465
466 len = ftell(fp);
467 if (instruction->eops->next) {
468 base = instruction->eops->next->offset;
469 len -= base;
470 if (instruction->eops->next->next &&
471 len > (size_t)instruction->eops->next->next->offset)
472 len = (size_t)instruction->eops->next->next->offset;
473 }
474 /*
475 * Dummy call to list->output to give the offset to the
476 * listing module.
477 */
478 list->output(offset, NULL, OUT_RAWDATA, 0);
479 list->uplevel(LIST_INCBIN);
480 while (t--) {
481 size_t l;
482
483 fseek(fp, base, SEEK_SET);
484 l = len;
485 while (l > 0) {
486 int32_t m;
487 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
488 if (!m) {
489 /*
490 * This shouldn't happen unless the file
491 * actually changes while we are reading
492 * it.
493 */
494 error(ERR_NONFATAL,
495 "`incbin': unexpected EOF while"
496 " reading file `%s'", fname);
497 t = 0; /* Try to exit cleanly */
498 break;
499 }
500 out(offset, segment, buf, OUT_RAWDATA, m,
501 NO_SEG, NO_SEG);
502 l -= m;
503 }
504 }
505 list->downlevel(LIST_INCBIN);
506 if (instruction->times > 1) {
507 /*
508 * Dummy call to list->output to give the offset to the
509 * listing module.
510 */
511 list->output(offset, NULL, OUT_RAWDATA, 0);
512 list->uplevel(LIST_TIMES);
513 list->downlevel(LIST_TIMES);
514 }
515 fclose(fp);
516 return instruction->times * len;
517 }
518 return 0; /* if we're here, there's an error */
519 }
520
521 /* Check to see if we need an address-size prefix */
522 add_asp(instruction, bits);
523
524 m = find_match(&temp, instruction, segment, offset, bits);
525
526 if (m == MOK_GOOD) {
527 /* Matches! */
528 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
529 itimes = instruction->times;
530 if (insn_size < 0) /* shouldn't be, on pass two */
531 error(ERR_PANIC, "errors made it through from pass one");
532 else
533 while (itimes--) {
534 for (j = 0; j < MAXPREFIX; j++) {
535 uint8_t c = 0;
536 switch (instruction->prefixes[j]) {
537 case P_WAIT:
538 c = 0x9B;
539 break;
540 case P_LOCK:
541 c = 0xF0;
542 break;
543 case P_REPNE:
544 case P_REPNZ:
545 case P_XACQUIRE:
546 c = 0xF2;
547 break;
548 case P_REPE:
549 case P_REPZ:
550 case P_REP:
551 case P_XRELEASE:
552 c = 0xF3;
553 break;
554 case R_CS:
555 if (bits == 64) {
556 error(ERR_WARNING | ERR_PASS2,
557 "cs segment base generated, but will be ignored in 64-bit mode");
558 }
559 c = 0x2E;
560 break;
561 case R_DS:
562 if (bits == 64) {
563 error(ERR_WARNING | ERR_PASS2,
564 "ds segment base generated, but will be ignored in 64-bit mode");
565 }
566 c = 0x3E;
567 break;
568 case R_ES:
569 if (bits == 64) {
570 error(ERR_WARNING | ERR_PASS2,
571 "es segment base generated, but will be ignored in 64-bit mode");
572 }
573 c = 0x26;
574 break;
575 case R_FS:
576 c = 0x64;
577 break;
578 case R_GS:
579 c = 0x65;
580 break;
581 case R_SS:
582 if (bits == 64) {
583 error(ERR_WARNING | ERR_PASS2,
584 "ss segment base generated, but will be ignored in 64-bit mode");
585 }
586 c = 0x36;
587 break;
588 case R_SEGR6:
589 case R_SEGR7:
590 error(ERR_NONFATAL,
591 "segr6 and segr7 cannot be used as prefixes");
592 break;
593 case P_A16:
594 if (bits == 64) {
595 error(ERR_NONFATAL,
596 "16-bit addressing is not supported "
597 "in 64-bit mode");
598 } else if (bits != 16)
599 c = 0x67;
600 break;
601 case P_A32:
602 if (bits != 32)
603 c = 0x67;
604 break;
605 case P_A64:
606 if (bits != 64) {
607 error(ERR_NONFATAL,
608 "64-bit addressing is only supported "
609 "in 64-bit mode");
610 }
611 break;
612 case P_ASP:
613 c = 0x67;
614 break;
615 case P_O16:
616 if (bits != 16)
617 c = 0x66;
618 break;
619 case P_O32:
620 if (bits == 16)
621 c = 0x66;
622 break;
623 case P_O64:
624 /* REX.W */
625 break;
626 case P_OSP:
627 c = 0x66;
628 break;
629 case P_none:
630 break;
631 default:
632 error(ERR_PANIC, "invalid instruction prefix");
633 }
634 if (c != 0) {
635 out(offset, segment, &c, OUT_RAWDATA, 1,
636 NO_SEG, NO_SEG);
637 offset++;
638 }
639 }
640 insn_end = offset + insn_size;
641 gencode(segment, offset, bits, instruction,
642 temp, insn_end);
643 offset += insn_size;
644 if (itimes > 0 && itimes == instruction->times - 1) {
645 /*
646 * Dummy call to list->output to give the offset to the
647 * listing module.
648 */
649 list->output(offset, NULL, OUT_RAWDATA, 0);
650 list->uplevel(LIST_TIMES);
651 }
652 }
653 if (instruction->times > 1)
654 list->downlevel(LIST_TIMES);
655 return offset - start;
656 } else {
657 /* No match */
658 switch (m) {
659 case MERR_OPSIZEMISSING:
660 error(ERR_NONFATAL, "operation size not specified");
661 break;
662 case MERR_OPSIZEMISMATCH:
663 error(ERR_NONFATAL, "mismatch in operand sizes");
664 break;
665 case MERR_BADCPU:
666 error(ERR_NONFATAL, "no instruction for this cpu level");
667 break;
668 case MERR_BADMODE:
669 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
670 bits);
671 break;
672 default:
673 error(ERR_NONFATAL,
674 "invalid combination of opcode and operands");
675 break;
676 }
677 }
678 return 0;
679 }
680
681 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
682 insn * instruction, efunc error)
683 {
684 const struct itemplate *temp;
685 enum match_result m;
686
687 errfunc = error; /* to pass to other functions */
688 cpu = cp;
689
690 if (instruction->opcode == I_none)
691 return 0;
692
693 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
694 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
695 instruction->opcode == I_DT || instruction->opcode == I_DO ||
696 instruction->opcode == I_DY) {
697 extop *e;
698 int32_t isize, osize, wsize;
699
700 isize = 0;
701 wsize = idata_bytes(instruction->opcode);
702
703 list_for_each(e, instruction->eops) {
704 int32_t align;
705
706 osize = 0;
707 if (e->type == EOT_DB_NUMBER) {
708 osize = 1;
709 warn_overflow_const(e->offset, wsize);
710 } else if (e->type == EOT_DB_STRING ||
711 e->type == EOT_DB_STRING_FREE)
712 osize = e->stringlen;
713
714 align = (-osize) % wsize;
715 if (align < 0)
716 align += wsize;
717 isize += osize + align;
718 }
719 return isize * instruction->times;
720 }
721
722 if (instruction->opcode == I_INCBIN) {
723 const char *fname = instruction->eops->stringval;
724 FILE *fp;
725 int64_t val = 0;
726 size_t len;
727
728 fp = fopen(fname, "rb");
729 if (!fp)
730 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
731 fname);
732 else if (fseek(fp, 0L, SEEK_END) < 0)
733 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
734 fname);
735 else {
736 len = ftell(fp);
737 if (instruction->eops->next) {
738 len -= instruction->eops->next->offset;
739 if (instruction->eops->next->next &&
740 len > (size_t)instruction->eops->next->next->offset) {
741 len = (size_t)instruction->eops->next->next->offset;
742 }
743 }
744 val = instruction->times * len;
745 }
746 if (fp)
747 fclose(fp);
748 return val;
749 }
750
751 /* Check to see if we need an address-size prefix */
752 add_asp(instruction, bits);
753
754 m = find_match(&temp, instruction, segment, offset, bits);
755 if (m == MOK_GOOD) {
756 /* we've matched an instruction. */
757 int64_t isize;
758 int j;
759
760 isize = calcsize(segment, offset, bits, instruction, temp);
761 if (isize < 0)
762 return -1;
763 for (j = 0; j < MAXPREFIX; j++) {
764 switch (instruction->prefixes[j]) {
765 case P_A16:
766 if (bits != 16)
767 isize++;
768 break;
769 case P_A32:
770 if (bits != 32)
771 isize++;
772 break;
773 case P_O16:
774 if (bits != 16)
775 isize++;
776 break;
777 case P_O32:
778 if (bits == 16)
779 isize++;
780 break;
781 case P_A64:
782 case P_O64:
783 case P_none:
784 break;
785 default:
786 isize++;
787 break;
788 }
789 }
790 return isize * instruction->times;
791 } else {
792 return -1; /* didn't match any instruction */
793 }
794 }
795
796 static void bad_hle_warn(const insn * ins, uint8_t hleok)
797 {
798 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
799 enum whatwarn { w_none, w_lock, w_inval } ww;
800 static const enum whatwarn warn[2][4] =
801 {
802 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
803 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
804 };
805 unsigned int n;
806
807 n = (unsigned int)rep_pfx - P_XACQUIRE;
808 if (n > 1)
809 return; /* Not XACQUIRE/XRELEASE */
810
811 ww = warn[n][hleok];
812 if (!is_class(MEMORY, ins->oprs[0].type))
813 ww = w_inval; /* HLE requires operand 0 to be memory */
814
815 switch (ww) {
816 case w_none:
817 break;
818
819 case w_lock:
820 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
821 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
822 "%s with this instruction requires lock",
823 prefix_name(rep_pfx));
824 }
825 break;
826
827 case w_inval:
828 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
829 "%s invalid with this instruction",
830 prefix_name(rep_pfx));
831 break;
832 }
833 }
834
835 /* Common construct */
836 #define case3(x) case (x): case (x)+1: case (x)+2
837 #define case4(x) case3(x): case (x)+3
838
839 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
840 insn * ins, const struct itemplate *temp)
841 {
842 const uint8_t *codes = temp->code;
843 int64_t length = 0;
844 uint8_t c;
845 int rex_mask = ~0;
846 int op1, op2;
847 struct operand *opx;
848 uint8_t opex = 0;
849 enum ea_type eat;
850 uint8_t hleok = 0;
851 bool lockcheck = true;
852
853 ins->rex = 0; /* Ensure REX is reset */
854 eat = EA_SCALAR; /* Expect a scalar EA */
855 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
856
857 if (ins->prefixes[PPS_OSIZE] == P_O64)
858 ins->rex |= REX_W;
859
860 (void)segment; /* Don't warn that this parameter is unused */
861 (void)offset; /* Don't warn that this parameter is unused */
862
863 while (*codes) {
864 c = *codes++;
865 op1 = (c & 3) + ((opex & 1) << 2);
866 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
867 opx = &ins->oprs[op1];
868 opex = 0; /* For the next iteration */
869
870 switch (c) {
871 case4(01):
872 codes += c, length += c;
873 break;
874
875 case3(05):
876 opex = c;
877 break;
878
879 case4(010):
880 ins->rex |=
881 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
882 codes++, length++;
883 break;
884
885 case4(020):
886 case4(024):
887 length++;
888 break;
889
890 case4(030):
891 length += 2;
892 break;
893
894 case4(034):
895 if (opx->type & (BITS16 | BITS32 | BITS64))
896 length += (opx->type & BITS16) ? 2 : 4;
897 else
898 length += (bits == 16) ? 2 : 4;
899 break;
900
901 case4(040):
902 length += 4;
903 break;
904
905 case4(044):
906 length += ins->addr_size >> 3;
907 break;
908
909 case4(050):
910 length++;
911 break;
912
913 case4(054):
914 length += 8; /* MOV reg64/imm */
915 break;
916
917 case4(060):
918 length += 2;
919 break;
920
921 case4(064):
922 if (opx->type & (BITS16 | BITS32 | BITS64))
923 length += (opx->type & BITS16) ? 2 : 4;
924 else
925 length += (bits == 16) ? 2 : 4;
926 break;
927
928 case4(070):
929 length += 4;
930 break;
931
932 case4(074):
933 length += 2;
934 break;
935
936 case 0172:
937 case 0173:
938 codes++;
939 length++;
940 break;
941
942 case4(0174):
943 length++;
944 break;
945
946 case4(0240):
947 ins->rex |= REX_EV;
948 ins->vexreg = regval(opx);
949 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
950 ins->vex_cm = *codes++;
951 ins->vex_wlp = *codes++;
952 ins->evex_tuple = (*codes++ - 0300);
953 break;
954
955 case 0250:
956 ins->rex |= REX_EV;
957 ins->vexreg = 0;
958 ins->vex_cm = *codes++;
959 ins->vex_wlp = *codes++;
960 ins->evex_tuple = (*codes++ - 0300);
961 break;
962
963 case4(0254):
964 length += 4;
965 break;
966
967 case4(0260):
968 ins->rex |= REX_V;
969 ins->vexreg = regval(opx);
970 ins->vex_cm = *codes++;
971 ins->vex_wlp = *codes++;
972 break;
973
974 case 0270:
975 ins->rex |= REX_V;
976 ins->vexreg = 0;
977 ins->vex_cm = *codes++;
978 ins->vex_wlp = *codes++;
979 break;
980
981 case3(0271):
982 hleok = c & 3;
983 break;
984
985 case4(0274):
986 length++;
987 break;
988
989 case4(0300):
990 break;
991
992 case 0310:
993 if (bits == 64)
994 return -1;
995 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
996 break;
997
998 case 0311:
999 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1000 break;
1001
1002 case 0312:
1003 break;
1004
1005 case 0313:
1006 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1007 has_prefix(ins, PPS_ASIZE, P_A32))
1008 return -1;
1009 break;
1010
1011 case4(0314):
1012 break;
1013
1014 case 0320:
1015 {
1016 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1017 if (pfx == P_O16)
1018 break;
1019 if (pfx != P_none)
1020 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1021 else
1022 ins->prefixes[PPS_OSIZE] = P_O16;
1023 break;
1024 }
1025
1026 case 0321:
1027 {
1028 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1029 if (pfx == P_O32)
1030 break;
1031 if (pfx != P_none)
1032 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1033 else
1034 ins->prefixes[PPS_OSIZE] = P_O32;
1035 break;
1036 }
1037
1038 case 0322:
1039 break;
1040
1041 case 0323:
1042 rex_mask &= ~REX_W;
1043 break;
1044
1045 case 0324:
1046 ins->rex |= REX_W;
1047 break;
1048
1049 case 0325:
1050 ins->rex |= REX_NH;
1051 break;
1052
1053 case 0326:
1054 break;
1055
1056 case 0330:
1057 codes++, length++;
1058 break;
1059
1060 case 0331:
1061 break;
1062
1063 case 0332:
1064 case 0333:
1065 length++;
1066 break;
1067
1068 case 0334:
1069 ins->rex |= REX_L;
1070 break;
1071
1072 case 0335:
1073 break;
1074
1075 case 0336:
1076 if (!ins->prefixes[PPS_REP])
1077 ins->prefixes[PPS_REP] = P_REP;
1078 break;
1079
1080 case 0337:
1081 if (!ins->prefixes[PPS_REP])
1082 ins->prefixes[PPS_REP] = P_REPNE;
1083 break;
1084
1085 case 0340:
1086 if (ins->oprs[0].segment != NO_SEG)
1087 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1088 " quantity of BSS space");
1089 else
1090 length += ins->oprs[0].offset;
1091 break;
1092
1093 case 0341:
1094 if (!ins->prefixes[PPS_WAIT])
1095 ins->prefixes[PPS_WAIT] = P_WAIT;
1096 break;
1097
1098 case 0360:
1099 break;
1100
1101 case 0361:
1102 length++;
1103 break;
1104
1105 case 0364:
1106 case 0365:
1107 break;
1108
1109 case 0366:
1110 case 0367:
1111 length++;
1112 break;
1113
1114 case3(0370):
1115 break;
1116
1117 case 0373:
1118 length++;
1119 break;
1120
1121 case 0374:
1122 eat = EA_XMMVSIB;
1123 break;
1124
1125 case 0375:
1126 eat = EA_YMMVSIB;
1127 break;
1128
1129 case 0376:
1130 eat = EA_ZMMVSIB;
1131 break;
1132
1133 case4(0100):
1134 case4(0110):
1135 case4(0120):
1136 case4(0130):
1137 case4(0200):
1138 case4(0204):
1139 case4(0210):
1140 case4(0214):
1141 case4(0220):
1142 case4(0224):
1143 case4(0230):
1144 case4(0234):
1145 {
1146 ea ea_data;
1147 int rfield;
1148 opflags_t rflags;
1149 struct operand *opy = &ins->oprs[op2];
1150 struct operand *oplast;
1151
1152 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1153
1154 if (c <= 0177) {
1155 /* pick rfield from operand b (opx) */
1156 rflags = regflag(opx);
1157 rfield = nasm_regvals[opx->basereg];
1158 /* find the last SIMD operand where ER decorator resides */
1159 oplast = &ins->oprs[op1 > op2 ? op1 : op2];
1160 } else {
1161 rflags = 0;
1162 rfield = c & 7;
1163 oplast = opy;
1164 }
1165
1166 if (oplast->decoflags & ER) {
1167 /* set EVEX.RC (rounding control) and b */
1168 ins->evex_p[2] |= (((ins->evex_rm - BRC_RN) << 5) & EVEX_P2LL) |
1169 EVEX_P2B;
1170 } else {
1171 /* set EVEX.L'L (vector length) */
1172 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1173 if ((oplast->decoflags & SAE) ||
1174 (opy->decoflags & BRDCAST_MASK)) {
1175 /* set EVEX.b */
1176 ins->evex_p[2] |= EVEX_P2B;
1177 }
1178 }
1179
1180 if (process_ea(opy, &ea_data, bits,
1181 rfield, rflags, ins) != eat) {
1182 errfunc(ERR_NONFATAL, "invalid effective address");
1183 return -1;
1184 } else {
1185 ins->rex |= ea_data.rex;
1186 length += ea_data.size;
1187 }
1188 }
1189 break;
1190
1191 default:
1192 errfunc(ERR_PANIC, "internal instruction table corrupt"
1193 ": instruction code \\%o (0x%02X) given", c, c);
1194 break;
1195 }
1196 }
1197
1198 ins->rex &= rex_mask;
1199
1200 if (ins->rex & REX_NH) {
1201 if (ins->rex & REX_H) {
1202 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1203 return -1;
1204 }
1205 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1206 }
1207
1208 if (ins->rex & (REX_V | REX_EV)) {
1209 int bad32 = REX_R|REX_W|REX_X|REX_B;
1210
1211 if (ins->rex & REX_H) {
1212 errfunc(ERR_NONFATAL, "cannot use high register in AVX instruction");
1213 return -1;
1214 }
1215 switch (ins->vex_wlp & 060) {
1216 case 000:
1217 case 040:
1218 ins->rex &= ~REX_W;
1219 break;
1220 case 020:
1221 ins->rex |= REX_W;
1222 bad32 &= ~REX_W;
1223 break;
1224 case 060:
1225 /* Follow REX_W */
1226 break;
1227 }
1228
1229 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1230 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1231 return -1;
1232 }
1233 if (ins->rex & REX_EV)
1234 length += 4;
1235 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1236 length += 3;
1237 else
1238 length += 2;
1239 } else if (ins->rex & REX_REAL) {
1240 if (ins->rex & REX_H) {
1241 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1242 return -1;
1243 } else if (bits == 64) {
1244 length++;
1245 } else if ((ins->rex & REX_L) &&
1246 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1247 cpu >= IF_X86_64) {
1248 /* LOCK-as-REX.R */
1249 assert_no_prefix(ins, PPS_LOCK);
1250 lockcheck = false; /* Already errored, no need for warning */
1251 length++;
1252 } else {
1253 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1254 return -1;
1255 }
1256 }
1257
1258 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1259 (!(temp->flags & IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1260 errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1261 "instruction is not lockable");
1262 }
1263
1264 bad_hle_warn(ins, hleok);
1265
1266 return length;
1267 }
1268
1269 static inline unsigned int emit_rex(insn *ins, int32_t segment, int64_t offset, int bits)
1270 {
1271 if (bits == 64) {
1272 if ((ins->rex & REX_REAL) && !(ins->rex & (REX_V | REX_EV))) {
1273 ins->rex = (ins->rex & REX_REAL) | REX_P;
1274 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1275 ins->rex = 0;
1276 return 1;
1277 }
1278 }
1279
1280 return 0;
1281 }
1282
1283 static void gencode(int32_t segment, int64_t offset, int bits,
1284 insn * ins, const struct itemplate *temp,
1285 int64_t insn_end)
1286 {
1287 uint8_t c;
1288 uint8_t bytes[4];
1289 int64_t size;
1290 int64_t data;
1291 int op1, op2;
1292 struct operand *opx;
1293 const uint8_t *codes = temp->code;
1294 uint8_t opex = 0;
1295 enum ea_type eat = EA_SCALAR;
1296
1297 while (*codes) {
1298 c = *codes++;
1299 op1 = (c & 3) + ((opex & 1) << 2);
1300 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1301 opx = &ins->oprs[op1];
1302 opex = 0; /* For the next iteration */
1303
1304 switch (c) {
1305 case 01:
1306 case 02:
1307 case 03:
1308 case 04:
1309 offset += emit_rex(ins, segment, offset, bits);
1310 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1311 codes += c;
1312 offset += c;
1313 break;
1314
1315 case 05:
1316 case 06:
1317 case 07:
1318 opex = c;
1319 break;
1320
1321 case4(010):
1322 offset += emit_rex(ins, segment, offset, bits);
1323 bytes[0] = *codes++ + (regval(opx) & 7);
1324 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1325 offset += 1;
1326 break;
1327
1328 case4(020):
1329 if (opx->offset < -256 || opx->offset > 255) {
1330 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1331 "byte value exceeds bounds");
1332 }
1333 out_imm8(offset, segment, opx);
1334 offset += 1;
1335 break;
1336
1337 case4(024):
1338 if (opx->offset < 0 || opx->offset > 255)
1339 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1340 "unsigned byte value exceeds bounds");
1341 out_imm8(offset, segment, opx);
1342 offset += 1;
1343 break;
1344
1345 case4(030):
1346 warn_overflow_opd(opx, 2);
1347 data = opx->offset;
1348 out(offset, segment, &data, OUT_ADDRESS, 2,
1349 opx->segment, opx->wrt);
1350 offset += 2;
1351 break;
1352
1353 case4(034):
1354 if (opx->type & (BITS16 | BITS32))
1355 size = (opx->type & BITS16) ? 2 : 4;
1356 else
1357 size = (bits == 16) ? 2 : 4;
1358 warn_overflow_opd(opx, size);
1359 data = opx->offset;
1360 out(offset, segment, &data, OUT_ADDRESS, size,
1361 opx->segment, opx->wrt);
1362 offset += size;
1363 break;
1364
1365 case4(040):
1366 warn_overflow_opd(opx, 4);
1367 data = opx->offset;
1368 out(offset, segment, &data, OUT_ADDRESS, 4,
1369 opx->segment, opx->wrt);
1370 offset += 4;
1371 break;
1372
1373 case4(044):
1374 data = opx->offset;
1375 size = ins->addr_size >> 3;
1376 warn_overflow_opd(opx, size);
1377 out(offset, segment, &data, OUT_ADDRESS, size,
1378 opx->segment, opx->wrt);
1379 offset += size;
1380 break;
1381
1382 case4(050):
1383 if (opx->segment != segment) {
1384 data = opx->offset;
1385 out(offset, segment, &data,
1386 OUT_REL1ADR, insn_end - offset,
1387 opx->segment, opx->wrt);
1388 } else {
1389 data = opx->offset - insn_end;
1390 if (data > 127 || data < -128)
1391 errfunc(ERR_NONFATAL, "short jump is out of range");
1392 out(offset, segment, &data,
1393 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1394 }
1395 offset += 1;
1396 break;
1397
1398 case4(054):
1399 data = (int64_t)opx->offset;
1400 out(offset, segment, &data, OUT_ADDRESS, 8,
1401 opx->segment, opx->wrt);
1402 offset += 8;
1403 break;
1404
1405 case4(060):
1406 if (opx->segment != segment) {
1407 data = opx->offset;
1408 out(offset, segment, &data,
1409 OUT_REL2ADR, insn_end - offset,
1410 opx->segment, opx->wrt);
1411 } else {
1412 data = opx->offset - insn_end;
1413 out(offset, segment, &data,
1414 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1415 }
1416 offset += 2;
1417 break;
1418
1419 case4(064):
1420 if (opx->type & (BITS16 | BITS32 | BITS64))
1421 size = (opx->type & BITS16) ? 2 : 4;
1422 else
1423 size = (bits == 16) ? 2 : 4;
1424 if (opx->segment != segment) {
1425 data = opx->offset;
1426 out(offset, segment, &data,
1427 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1428 insn_end - offset, opx->segment, opx->wrt);
1429 } else {
1430 data = opx->offset - insn_end;
1431 out(offset, segment, &data,
1432 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1433 }
1434 offset += size;
1435 break;
1436
1437 case4(070):
1438 if (opx->segment != segment) {
1439 data = opx->offset;
1440 out(offset, segment, &data,
1441 OUT_REL4ADR, insn_end - offset,
1442 opx->segment, opx->wrt);
1443 } else {
1444 data = opx->offset - insn_end;
1445 out(offset, segment, &data,
1446 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1447 }
1448 offset += 4;
1449 break;
1450
1451 case4(074):
1452 if (opx->segment == NO_SEG)
1453 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1454 " relocatable");
1455 data = 0;
1456 out(offset, segment, &data, OUT_ADDRESS, 2,
1457 outfmt->segbase(1 + opx->segment),
1458 opx->wrt);
1459 offset += 2;
1460 break;
1461
1462 case 0172:
1463 c = *codes++;
1464 opx = &ins->oprs[c >> 3];
1465 bytes[0] = nasm_regvals[opx->basereg] << 4;
1466 opx = &ins->oprs[c & 7];
1467 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1468 errfunc(ERR_NONFATAL,
1469 "non-absolute expression not permitted as argument %d",
1470 c & 7);
1471 } else {
1472 if (opx->offset & ~15) {
1473 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1474 "four-bit argument exceeds bounds");
1475 }
1476 bytes[0] |= opx->offset & 15;
1477 }
1478 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1479 offset++;
1480 break;
1481
1482 case 0173:
1483 c = *codes++;
1484 opx = &ins->oprs[c >> 4];
1485 bytes[0] = nasm_regvals[opx->basereg] << 4;
1486 bytes[0] |= c & 15;
1487 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1488 offset++;
1489 break;
1490
1491 case4(0174):
1492 bytes[0] = nasm_regvals[opx->basereg] << 4;
1493 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1494 offset++;
1495 break;
1496
1497 case4(0254):
1498 data = opx->offset;
1499 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1500 (int32_t)data != (int64_t)data) {
1501 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1502 "signed dword immediate exceeds bounds");
1503 }
1504 out(offset, segment, &data, OUT_ADDRESS, 4,
1505 opx->segment, opx->wrt);
1506 offset += 4;
1507 break;
1508
1509 case4(0240):
1510 case 0250:
1511 codes += 3;
1512 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1513 EVEX_P2Z | EVEX_P2AAA, 2);
1514 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1515 bytes[0] = 0x62;
1516 /* EVEX.X can be set by either REX or EVEX for different reasons */
1517 bytes[1] = (~(((ins->rex & 7) << 5) |
1518 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) & 0xf0) |
1519 (ins->vex_cm & 3);
1520 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1521 ((~ins->vexreg & 15) << 3) |
1522 (1 << 2) | (ins->vex_wlp & 3);
1523 bytes[3] = ins->evex_p[2];
1524 out(offset, segment, &bytes, OUT_RAWDATA, 4, NO_SEG, NO_SEG);
1525 offset += 4;
1526 break;
1527
1528 case4(0260):
1529 case 0270:
1530 codes += 2;
1531 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1532 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1533 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1534 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1535 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1536 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1537 offset += 3;
1538 } else {
1539 bytes[0] = 0xc5;
1540 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1541 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1542 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1543 offset += 2;
1544 }
1545 break;
1546
1547 case 0271:
1548 case 0272:
1549 case 0273:
1550 break;
1551
1552 case4(0274):
1553 {
1554 uint64_t uv, um;
1555 int s;
1556
1557 if (ins->rex & REX_W)
1558 s = 64;
1559 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1560 s = 16;
1561 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1562 s = 32;
1563 else
1564 s = bits;
1565
1566 um = (uint64_t)2 << (s-1);
1567 uv = opx->offset;
1568
1569 if (uv > 127 && uv < (uint64_t)-128 &&
1570 (uv < um-128 || uv > um-1)) {
1571 /* If this wasn't explicitly byte-sized, warn as though we
1572 * had fallen through to the imm16/32/64 case.
1573 */
1574 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1575 "%s value exceeds bounds",
1576 (opx->type & BITS8) ? "signed byte" :
1577 s == 16 ? "word" :
1578 s == 32 ? "dword" :
1579 "signed dword");
1580 }
1581 if (opx->segment != NO_SEG) {
1582 data = uv;
1583 out(offset, segment, &data, OUT_ADDRESS, 1,
1584 opx->segment, opx->wrt);
1585 } else {
1586 bytes[0] = uv;
1587 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1588 NO_SEG);
1589 }
1590 offset += 1;
1591 break;
1592 }
1593
1594 case4(0300):
1595 break;
1596
1597 case 0310:
1598 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1599 *bytes = 0x67;
1600 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1601 offset += 1;
1602 } else
1603 offset += 0;
1604 break;
1605
1606 case 0311:
1607 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1608 *bytes = 0x67;
1609 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1610 offset += 1;
1611 } else
1612 offset += 0;
1613 break;
1614
1615 case 0312:
1616 break;
1617
1618 case 0313:
1619 ins->rex = 0;
1620 break;
1621
1622 case4(0314):
1623 break;
1624
1625 case 0320:
1626 case 0321:
1627 break;
1628
1629 case 0322:
1630 case 0323:
1631 break;
1632
1633 case 0324:
1634 ins->rex |= REX_W;
1635 break;
1636
1637 case 0325:
1638 break;
1639
1640 case 0326:
1641 break;
1642
1643 case 0330:
1644 *bytes = *codes++ ^ get_cond_opcode(ins->condition);
1645 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1646 offset += 1;
1647 break;
1648
1649 case 0331:
1650 break;
1651
1652 case 0332:
1653 case 0333:
1654 *bytes = c - 0332 + 0xF2;
1655 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1656 offset += 1;
1657 break;
1658
1659 case 0334:
1660 if (ins->rex & REX_R) {
1661 *bytes = 0xF0;
1662 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1663 offset += 1;
1664 }
1665 ins->rex &= ~(REX_L|REX_R);
1666 break;
1667
1668 case 0335:
1669 break;
1670
1671 case 0336:
1672 case 0337:
1673 break;
1674
1675 case 0340:
1676 if (ins->oprs[0].segment != NO_SEG)
1677 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1678 else {
1679 int64_t size = ins->oprs[0].offset;
1680 if (size > 0)
1681 out(offset, segment, NULL,
1682 OUT_RESERVE, size, NO_SEG, NO_SEG);
1683 offset += size;
1684 }
1685 break;
1686
1687 case 0341:
1688 break;
1689
1690 case 0360:
1691 break;
1692
1693 case 0361:
1694 bytes[0] = 0x66;
1695 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1696 offset += 1;
1697 break;
1698
1699 case 0364:
1700 case 0365:
1701 break;
1702
1703 case 0366:
1704 case 0367:
1705 *bytes = c - 0366 + 0x66;
1706 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1707 offset += 1;
1708 break;
1709
1710 case 0370:
1711 case 0371:
1712 break;
1713
1714 case 0373:
1715 *bytes = bits == 16 ? 3 : 5;
1716 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1717 offset += 1;
1718 break;
1719
1720 case 0374:
1721 eat = EA_XMMVSIB;
1722 break;
1723
1724 case 0375:
1725 eat = EA_YMMVSIB;
1726 break;
1727
1728 case 0376:
1729 eat = EA_ZMMVSIB;
1730 break;
1731
1732 case4(0100):
1733 case4(0110):
1734 case4(0120):
1735 case4(0130):
1736 case4(0200):
1737 case4(0204):
1738 case4(0210):
1739 case4(0214):
1740 case4(0220):
1741 case4(0224):
1742 case4(0230):
1743 case4(0234):
1744 {
1745 ea ea_data;
1746 int rfield;
1747 opflags_t rflags;
1748 uint8_t *p;
1749 int32_t s;
1750 struct operand *opy = &ins->oprs[op2];
1751
1752 if (c <= 0177) {
1753 /* pick rfield from operand b (opx) */
1754 rflags = regflag(opx);
1755 rfield = nasm_regvals[opx->basereg];
1756 } else {
1757 /* rfield is constant */
1758 rflags = 0;
1759 rfield = c & 7;
1760 }
1761
1762 if (process_ea(opy, &ea_data, bits,
1763 rfield, rflags, ins) != eat)
1764 errfunc(ERR_NONFATAL, "invalid effective address");
1765
1766 p = bytes;
1767 *p++ = ea_data.modrm;
1768 if (ea_data.sib_present)
1769 *p++ = ea_data.sib;
1770
1771 s = p - bytes;
1772 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1773
1774 /*
1775 * Make sure the address gets the right offset in case
1776 * the line breaks in the .lst file (BR 1197827)
1777 */
1778 offset += s;
1779 s = 0;
1780
1781 switch (ea_data.bytes) {
1782 case 0:
1783 break;
1784 case 1:
1785 case 2:
1786 case 4:
1787 case 8:
1788 /* use compressed displacement, if available */
1789 data = ea_data.disp8 ? ea_data.disp8 : opy->offset;
1790 s += ea_data.bytes;
1791 if (ea_data.rip) {
1792 if (opy->segment == segment) {
1793 data -= insn_end;
1794 if (overflow_signed(data, ea_data.bytes))
1795 warn_overflow(ERR_PASS2, ea_data.bytes);
1796 out(offset, segment, &data, OUT_ADDRESS,
1797 ea_data.bytes, NO_SEG, NO_SEG);
1798 } else {
1799 /* overflow check in output/linker? */
1800 out(offset, segment, &data, OUT_REL4ADR,
1801 insn_end - offset, opy->segment, opy->wrt);
1802 }
1803 } else {
1804 if (overflow_general(data, ins->addr_size >> 3) ||
1805 signed_bits(data, ins->addr_size) !=
1806 signed_bits(data, ea_data.bytes * 8))
1807 warn_overflow(ERR_PASS2, ea_data.bytes);
1808
1809 out(offset, segment, &data, OUT_ADDRESS,
1810 ea_data.bytes, opy->segment, opy->wrt);
1811 }
1812 break;
1813 default:
1814 /* Impossible! */
1815 errfunc(ERR_PANIC,
1816 "Invalid amount of bytes (%d) for offset?!",
1817 ea_data.bytes);
1818 break;
1819 }
1820 offset += s;
1821 }
1822 break;
1823
1824 default:
1825 errfunc(ERR_PANIC, "internal instruction table corrupt"
1826 ": instruction code \\%o (0x%02X) given", c, c);
1827 break;
1828 }
1829 }
1830 }
1831
1832 static opflags_t regflag(const operand * o)
1833 {
1834 if (!is_register(o->basereg))
1835 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1836 return nasm_reg_flags[o->basereg];
1837 }
1838
1839 static int32_t regval(const operand * o)
1840 {
1841 if (!is_register(o->basereg))
1842 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1843 return nasm_regvals[o->basereg];
1844 }
1845
1846 static int op_rexflags(const operand * o, int mask)
1847 {
1848 opflags_t flags;
1849 int val;
1850
1851 if (!is_register(o->basereg))
1852 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1853
1854 flags = nasm_reg_flags[o->basereg];
1855 val = nasm_regvals[o->basereg];
1856
1857 return rexflags(val, flags, mask);
1858 }
1859
1860 static int rexflags(int val, opflags_t flags, int mask)
1861 {
1862 int rex = 0;
1863
1864 if (val >= 8)
1865 rex |= REX_B|REX_X|REX_R;
1866 if (flags & BITS64)
1867 rex |= REX_W;
1868 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1869 rex |= REX_H;
1870 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1871 rex |= REX_P;
1872
1873 return rex & mask;
1874 }
1875
1876 static int evexflags(int val, decoflags_t deco,
1877 int mask, uint8_t byte)
1878 {
1879 int evex = 0;
1880
1881 switch(byte) {
1882 case 0:
1883 if (val >= 16)
1884 evex |= (EVEX_P0RP | EVEX_P0X);
1885 break;
1886 case 2:
1887 if (val >= 16)
1888 evex |= EVEX_P2VP;
1889 if (deco & Z)
1890 evex |= EVEX_P2Z;
1891 if (deco & OPMASK_MASK)
1892 evex |= deco & EVEX_P2AAA;
1893 break;
1894 }
1895 return evex & mask;
1896 }
1897
1898 static int op_evexflags(const operand * o, int mask, uint8_t byte)
1899 {
1900 int val;
1901
1902 if (!is_register(o->basereg))
1903 errfunc(ERR_PANIC, "invalid operand passed to op_evexflags()");
1904
1905 val = nasm_regvals[o->basereg];
1906
1907 return evexflags(val, o->decoflags, mask, byte);
1908 }
1909
1910 static enum match_result find_match(const struct itemplate **tempp,
1911 insn *instruction,
1912 int32_t segment, int64_t offset, int bits)
1913 {
1914 const struct itemplate *temp;
1915 enum match_result m, merr;
1916 opflags_t xsizeflags[MAX_OPERANDS];
1917 bool opsizemissing = false;
1918 int8_t broadcast = -1;
1919 int i;
1920
1921 /* find the position of broadcasting operand */
1922 for (i = 0; i < instruction->operands; i++)
1923 if (instruction->oprs[i].decoflags & BRDCAST_MASK) {
1924 broadcast = i;
1925 break;
1926 }
1927
1928 /* broadcasting uses a different data element size */
1929 for (i = 0; i < instruction->operands; i++)
1930 if (i == broadcast)
1931 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
1932 else
1933 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
1934
1935 merr = MERR_INVALOP;
1936
1937 for (temp = nasm_instructions[instruction->opcode];
1938 temp->opcode != I_none; temp++) {
1939 m = matches(temp, instruction, bits);
1940 if (m == MOK_JUMP) {
1941 if (jmp_match(segment, offset, bits, instruction, temp))
1942 m = MOK_GOOD;
1943 else
1944 m = MERR_INVALOP;
1945 } else if (m == MERR_OPSIZEMISSING &&
1946 (temp->flags & IF_SMASK) != IF_SX) {
1947 /*
1948 * Missing operand size and a candidate for fuzzy matching...
1949 */
1950 for (i = 0; i < temp->operands; i++)
1951 if (i == broadcast)
1952 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
1953 else
1954 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
1955 opsizemissing = true;
1956 }
1957 if (m > merr)
1958 merr = m;
1959 if (merr == MOK_GOOD)
1960 goto done;
1961 }
1962
1963 /* No match, but see if we can get a fuzzy operand size match... */
1964 if (!opsizemissing)
1965 goto done;
1966
1967 for (i = 0; i < instruction->operands; i++) {
1968 /*
1969 * We ignore extrinsic operand sizes on registers, so we should
1970 * never try to fuzzy-match on them. This also resolves the case
1971 * when we have e.g. "xmmrm128" in two different positions.
1972 */
1973 if (is_class(REGISTER, instruction->oprs[i].type))
1974 continue;
1975
1976 /* This tests if xsizeflags[i] has more than one bit set */
1977 if ((xsizeflags[i] & (xsizeflags[i]-1)))
1978 goto done; /* No luck */
1979
1980 if (i == broadcast)
1981 instruction->oprs[i].decoflags |= xsizeflags[i];
1982 else
1983 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
1984 }
1985
1986 /* Try matching again... */
1987 for (temp = nasm_instructions[instruction->opcode];
1988 temp->opcode != I_none; temp++) {
1989 m = matches(temp, instruction, bits);
1990 if (m == MOK_JUMP) {
1991 if (jmp_match(segment, offset, bits, instruction, temp))
1992 m = MOK_GOOD;
1993 else
1994 m = MERR_INVALOP;
1995 }
1996 if (m > merr)
1997 merr = m;
1998 if (merr == MOK_GOOD)
1999 goto done;
2000 }
2001
2002 done:
2003 *tempp = temp;
2004 return merr;
2005 }
2006
2007 static enum match_result matches(const struct itemplate *itemp,
2008 insn *instruction, int bits)
2009 {
2010 opflags_t size[MAX_OPERANDS], asize;
2011 bool opsizemissing = false;
2012 int i, oprs;
2013
2014 /*
2015 * Check the opcode
2016 */
2017 if (itemp->opcode != instruction->opcode)
2018 return MERR_INVALOP;
2019
2020 /*
2021 * Count the operands
2022 */
2023 if (itemp->operands != instruction->operands)
2024 return MERR_INVALOP;
2025
2026 /*
2027 * Is it legal?
2028 */
2029 if (!(optimizing > 0) && (itemp->flags & IF_OPT))
2030 return MERR_INVALOP;
2031
2032 /*
2033 * Check that no spurious colons or TOs are present
2034 */
2035 for (i = 0; i < itemp->operands; i++)
2036 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2037 return MERR_INVALOP;
2038
2039 /*
2040 * Process size flags
2041 */
2042 switch (itemp->flags & IF_SMASK) {
2043 case IF_SB:
2044 asize = BITS8;
2045 break;
2046 case IF_SW:
2047 asize = BITS16;
2048 break;
2049 case IF_SD:
2050 asize = BITS32;
2051 break;
2052 case IF_SQ:
2053 asize = BITS64;
2054 break;
2055 case IF_SO:
2056 asize = BITS128;
2057 break;
2058 case IF_SY:
2059 asize = BITS256;
2060 break;
2061 case IF_SZ:
2062 asize = BITS512;
2063 break;
2064 case IF_SIZE:
2065 switch (bits) {
2066 case 16:
2067 asize = BITS16;
2068 break;
2069 case 32:
2070 asize = BITS32;
2071 break;
2072 case 64:
2073 asize = BITS64;
2074 break;
2075 default:
2076 asize = 0;
2077 break;
2078 }
2079 break;
2080 default:
2081 asize = 0;
2082 break;
2083 }
2084
2085 if (itemp->flags & IF_ARMASK) {
2086 /* S- flags only apply to a specific operand */
2087 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
2088 memset(size, 0, sizeof size);
2089 size[i] = asize;
2090 } else {
2091 /* S- flags apply to all operands */
2092 for (i = 0; i < MAX_OPERANDS; i++)
2093 size[i] = asize;
2094 }
2095
2096 /*
2097 * Check that the operand flags all match up,
2098 * it's a bit tricky so lets be verbose:
2099 *
2100 * 1) Find out the size of operand. If instruction
2101 * doesn't have one specified -- we're trying to
2102 * guess it either from template (IF_S* flag) or
2103 * from code bits.
2104 *
2105 * 2) If template operand do not match the instruction OR
2106 * template has an operand size specified AND this size differ
2107 * from which instruction has (perhaps we got it from code bits)
2108 * we are:
2109 * a) Check that only size of instruction and operand is differ
2110 * other characteristics do match
2111 * b) Perhaps it's a register specified in instruction so
2112 * for such a case we just mark that operand as "size
2113 * missing" and this will turn on fuzzy operand size
2114 * logic facility (handled by a caller)
2115 */
2116 for (i = 0; i < itemp->operands; i++) {
2117 opflags_t type = instruction->oprs[i].type;
2118 decoflags_t deco = instruction->oprs[i].decoflags;
2119 if (!(type & SIZE_MASK))
2120 type |= size[i];
2121
2122 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2123 (itemp->deco[i] & deco) != deco) {
2124 return MERR_INVALOP;
2125 } else if ((itemp->opd[i] & SIZE_MASK) &&
2126 (itemp->opd[i] & SIZE_MASK) != (type & SIZE_MASK)) {
2127 if (type & SIZE_MASK) {
2128 /*
2129 * when broadcasting, the element size depends on
2130 * the instruction type. decorator flag should match.
2131 */
2132 #define MATCH_BRSZ(bits) (((type & SIZE_MASK) == BITS##bits) && \
2133 ((itemp->deco[i] & BRSIZE_MASK) == BR_BITS##bits))
2134 if (!((deco & BRDCAST_MASK) &&
2135 (MATCH_BRSZ(32) || MATCH_BRSZ(64)))) {
2136 return MERR_INVALOP;
2137 }
2138 } else if (!is_class(REGISTER, type)) {
2139 /*
2140 * Note: we don't honor extrinsic operand sizes for registers,
2141 * so "missing operand size" for a register should be
2142 * considered a wildcard match rather than an error.
2143 */
2144 opsizemissing = true;
2145 }
2146 }
2147 }
2148
2149 if (opsizemissing)
2150 return MERR_OPSIZEMISSING;
2151
2152 /*
2153 * Check operand sizes
2154 */
2155 if (itemp->flags & (IF_SM | IF_SM2)) {
2156 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2157 for (i = 0; i < oprs; i++) {
2158 asize = itemp->opd[i] & SIZE_MASK;
2159 if (asize) {
2160 for (i = 0; i < oprs; i++)
2161 size[i] = asize;
2162 break;
2163 }
2164 }
2165 } else {
2166 oprs = itemp->operands;
2167 }
2168
2169 for (i = 0; i < itemp->operands; i++) {
2170 if (!(itemp->opd[i] & SIZE_MASK) &&
2171 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2172 return MERR_OPSIZEMISMATCH;
2173 }
2174
2175 /*
2176 * Check template is okay at the set cpu level
2177 */
2178 if (((itemp->flags & IF_PLEVEL) > cpu))
2179 return MERR_BADCPU;
2180
2181 /*
2182 * Verify the appropriate long mode flag.
2183 */
2184 if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG)))
2185 return MERR_BADMODE;
2186
2187 /*
2188 * If we have a HLE prefix, look for the NOHLE flag
2189 */
2190 if ((itemp->flags & IF_NOHLE) &&
2191 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2192 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2193 return MERR_BADHLE;
2194
2195 /*
2196 * Check if special handling needed for Jumps
2197 */
2198 if ((itemp->code[0] & ~1) == 0370)
2199 return MOK_JUMP;
2200
2201 return MOK_GOOD;
2202 }
2203
2204 /*
2205 * Check if offset is a multiple of N with corresponding tuple type
2206 * if Disp8*N is available, compressed displacement is stored in compdisp
2207 */
2208 static bool is_disp8n(operand *input, insn *ins, int8_t *compdisp)
2209 {
2210 const uint8_t fv_n[2][2][VLMAX] = {{{16, 32, 64}, {4, 4, 4}},
2211 {{16, 32, 64}, {8, 8, 8}}};
2212 const uint8_t hv_n[2][VLMAX] = {{8, 16, 32}, {4, 4, 4}};
2213 const uint8_t dup_n[VLMAX] = {8, 32, 64};
2214
2215 bool evex_b = input->decoflags & BRDCAST_MASK;
2216 enum ttypes tuple = ins->evex_tuple;
2217 /* vex_wlp composed as [wwllpp] */
2218 enum vectlens vectlen = (ins->vex_wlp & 0x0c) >> 2;
2219 /* wig(=2) is treated as w0(=0) */
2220 bool evex_w = (ins->vex_wlp & 0x10) >> 4;
2221 int32_t off = input->offset;
2222 uint8_t n = 0;
2223 int32_t disp8;
2224
2225 switch(tuple) {
2226 case FV:
2227 n = fv_n[evex_w][evex_b][vectlen];
2228 break;
2229 case HV:
2230 n = hv_n[evex_b][vectlen];
2231 break;
2232
2233 case FVM:
2234 /* 16, 32, 64 for VL 128, 256, 512 respectively*/
2235 n = 1 << (vectlen + 4);
2236 break;
2237 case T1S8: /* N = 1 */
2238 case T1S16: /* N = 2 */
2239 n = tuple - T1S8 + 1;
2240 break;
2241 case T1S:
2242 /* N = 4 for 32bit, 8 for 64bit */
2243 n = evex_w ? 8 : 4;
2244 break;
2245 case T1F32:
2246 case T1F64:
2247 /* N = 4 for 32bit, 8 for 64bit */
2248 n = (tuple == T1F32 ? 4 : 8);
2249 break;
2250 case T2:
2251 case T4:
2252 case T8:
2253 if (vectlen + 7 <= (evex_w + 5) + (tuple - T2 + 1))
2254 n = 0;
2255 else
2256 n = 1 << (tuple - T2 + evex_w + 4);
2257 break;
2258 case HVM:
2259 case QVM:
2260 case OVM:
2261 n = 1 << (OVM - tuple + vectlen + 1);
2262 break;
2263 case M128:
2264 n = 16;
2265 break;
2266 case DUP:
2267 n = dup_n[vectlen];
2268 break;
2269
2270 default:
2271 break;
2272 }
2273
2274 if (n && !(off & (n - 1))) {
2275 disp8 = off / n;
2276 /* if it fits in Disp8 */
2277 if (disp8 >= -128 && disp8 <= 127) {
2278 *compdisp = disp8;
2279 return true;
2280 }
2281 }
2282
2283 *compdisp = 0;
2284 return false;
2285 }
2286
2287 /*
2288 * Check if ModR/M.mod should/can be 01.
2289 * - EAF_BYTEOFFS is set
2290 * - offset can fit in a byte when EVEX is not used
2291 * - offset can be compressed when EVEX is used
2292 */
2293 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2294 (o >= -128 && o <= 127 && \
2295 seg == NO_SEG && !forw_ref && \
2296 !(input->eaflags & EAF_WORDOFFS) && \
2297 !(ins->rex & REX_EV)) || \
2298 (ins->rex & REX_EV && \
2299 is_disp8n(input, ins, &output->disp8)))
2300
2301 static enum ea_type process_ea(operand *input, ea *output, int bits,
2302 int rfield, opflags_t rflags, insn *ins)
2303 {
2304 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2305 int addrbits = ins->addr_size;
2306
2307 output->type = EA_SCALAR;
2308 output->rip = false;
2309
2310 /* REX flags for the rfield operand */
2311 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2312 /* EVEX.R' flag for the REG operand */
2313 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2314
2315 if (is_class(REGISTER, input->type)) {
2316 /*
2317 * It's a direct register.
2318 */
2319 if (!is_register(input->basereg))
2320 goto err;
2321
2322 if (!is_reg_class(REG_EA, input->basereg))
2323 goto err;
2324
2325 /* broadcasting is not available with a direct register operand. */
2326 if (input->decoflags & BRDCAST_MASK) {
2327 nasm_error(ERR_NONFATAL, "Broadcasting not allowed from a register");
2328 goto err;
2329 }
2330
2331 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2332 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2333 output->sib_present = false; /* no SIB necessary */
2334 output->bytes = 0; /* no offset necessary either */
2335 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2336 } else {
2337 /*
2338 * It's a memory reference.
2339 */
2340
2341 /* Embedded rounding or SAE is not available with a mem ref operand. */
2342 if (input->decoflags & (ER | SAE)) {
2343 nasm_error(ERR_NONFATAL,
2344 "Embedded rounding is available only with reg-reg op.");
2345 return -1;
2346 }
2347
2348 if (input->basereg == -1 &&
2349 (input->indexreg == -1 || input->scale == 0)) {
2350 /*
2351 * It's a pure offset.
2352 */
2353 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2354 input->segment == NO_SEG) {
2355 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2356 input->type &= ~IP_REL;
2357 input->type |= MEMORY;
2358 }
2359
2360 if (input->eaflags & EAF_BYTEOFFS ||
2361 (input->eaflags & EAF_WORDOFFS &&
2362 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2363 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2364 }
2365
2366 if (bits == 64 && (~input->type & IP_REL)) {
2367 output->sib_present = true;
2368 output->sib = GEN_SIB(0, 4, 5);
2369 output->bytes = 4;
2370 output->modrm = GEN_MODRM(0, rfield, 4);
2371 output->rip = false;
2372 } else {
2373 output->sib_present = false;
2374 output->bytes = (addrbits != 16 ? 4 : 2);
2375 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2376 output->rip = bits == 64;
2377 }
2378 } else {
2379 /*
2380 * It's an indirection.
2381 */
2382 int i = input->indexreg, b = input->basereg, s = input->scale;
2383 int32_t seg = input->segment;
2384 int hb = input->hintbase, ht = input->hinttype;
2385 int t, it, bt; /* register numbers */
2386 opflags_t x, ix, bx; /* register flags */
2387
2388 if (s == 0)
2389 i = -1; /* make this easy, at least */
2390
2391 if (is_register(i)) {
2392 it = nasm_regvals[i];
2393 ix = nasm_reg_flags[i];
2394 } else {
2395 it = -1;
2396 ix = 0;
2397 }
2398
2399 if (is_register(b)) {
2400 bt = nasm_regvals[b];
2401 bx = nasm_reg_flags[b];
2402 } else {
2403 bt = -1;
2404 bx = 0;
2405 }
2406
2407 /* if either one are a vector register... */
2408 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2409 opflags_t sok = BITS32 | BITS64;
2410 int32_t o = input->offset;
2411 int mod, scale, index, base;
2412
2413 /*
2414 * For a vector SIB, one has to be a vector and the other,
2415 * if present, a GPR. The vector must be the index operand.
2416 */
2417 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2418 if (s == 0)
2419 s = 1;
2420 else if (s != 1)
2421 goto err;
2422
2423 t = bt, bt = it, it = t;
2424 x = bx, bx = ix, ix = x;
2425 }
2426
2427 if (bt != -1) {
2428 if (REG_GPR & ~bx)
2429 goto err;
2430 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2431 sok &= bx;
2432 else
2433 goto err;
2434 }
2435
2436 /*
2437 * While we're here, ensure the user didn't specify
2438 * WORD or QWORD
2439 */
2440 if (input->disp_size == 16 || input->disp_size == 64)
2441 goto err;
2442
2443 if (addrbits == 16 ||
2444 (addrbits == 32 && !(sok & BITS32)) ||
2445 (addrbits == 64 && !(sok & BITS64)))
2446 goto err;
2447
2448 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2449 : ((ix & YMMREG & ~REG_EA)
2450 ? EA_YMMVSIB : EA_XMMVSIB));
2451
2452 output->rex |= rexflags(it, ix, REX_X);
2453 output->rex |= rexflags(bt, bx, REX_B);
2454 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2455
2456 index = it & 7; /* it is known to be != -1 */
2457
2458 switch (s) {
2459 case 1:
2460 scale = 0;
2461 break;
2462 case 2:
2463 scale = 1;
2464 break;
2465 case 4:
2466 scale = 2;
2467 break;
2468 case 8:
2469 scale = 3;
2470 break;
2471 default: /* then what the smeg is it? */
2472 goto err; /* panic */
2473 }
2474
2475 if (bt == -1) {
2476 base = 5;
2477 mod = 0;
2478 } else {
2479 base = (bt & 7);
2480 if (base != REG_NUM_EBP && o == 0 &&
2481 seg == NO_SEG && !forw_ref &&
2482 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2483 mod = 0;
2484 else if (IS_MOD_01())
2485 mod = 1;
2486 else
2487 mod = 2;
2488 }
2489
2490 output->sib_present = true;
2491 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2492 output->modrm = GEN_MODRM(mod, rfield, 4);
2493 output->sib = GEN_SIB(scale, index, base);
2494 } else if ((ix|bx) & (BITS32|BITS64)) {
2495 /*
2496 * it must be a 32/64-bit memory reference. Firstly we have
2497 * to check that all registers involved are type E/Rxx.
2498 */
2499 opflags_t sok = BITS32 | BITS64;
2500 int32_t o = input->offset;
2501
2502 if (it != -1) {
2503 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2504 sok &= ix;
2505 else
2506 goto err;
2507 }
2508
2509 if (bt != -1) {
2510 if (REG_GPR & ~bx)
2511 goto err; /* Invalid register */
2512 if (~sok & bx & SIZE_MASK)
2513 goto err; /* Invalid size */
2514 sok &= bx;
2515 }
2516
2517 /*
2518 * While we're here, ensure the user didn't specify
2519 * WORD or QWORD
2520 */
2521 if (input->disp_size == 16 || input->disp_size == 64)
2522 goto err;
2523
2524 if (addrbits == 16 ||
2525 (addrbits == 32 && !(sok & BITS32)) ||
2526 (addrbits == 64 && !(sok & BITS64)))
2527 goto err;
2528
2529 /* now reorganize base/index */
2530 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2531 ((hb == b && ht == EAH_NOTBASE) ||
2532 (hb == i && ht == EAH_MAKEBASE))) {
2533 /* swap if hints say so */
2534 t = bt, bt = it, it = t;
2535 x = bx, bx = ix, ix = x;
2536 }
2537 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2538 bt = -1, bx = 0, s++;
2539 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2540 /* make single reg base, unless hint */
2541 bt = it, bx = ix, it = -1, ix = 0;
2542 }
2543 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2544 s == 3 || s == 5 || s == 9) && bt == -1)
2545 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2546 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2547 (input->eaflags & EAF_TIMESTWO))
2548 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2549 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2550 if (s == 1 && it == REG_NUM_ESP) {
2551 /* swap ESP into base if scale is 1 */
2552 t = it, it = bt, bt = t;
2553 x = ix, ix = bx, bx = x;
2554 }
2555 if (it == REG_NUM_ESP ||
2556 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2557 goto err; /* wrong, for various reasons */
2558
2559 output->rex |= rexflags(it, ix, REX_X);
2560 output->rex |= rexflags(bt, bx, REX_B);
2561
2562 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2563 /* no SIB needed */
2564 int mod, rm;
2565
2566 if (bt == -1) {
2567 rm = 5;
2568 mod = 0;
2569 } else {
2570 rm = (bt & 7);
2571 if (rm != REG_NUM_EBP && o == 0 &&
2572 seg == NO_SEG && !forw_ref &&
2573 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2574 mod = 0;
2575 else if (IS_MOD_01())
2576 mod = 1;
2577 else
2578 mod = 2;
2579 }
2580
2581 output->sib_present = false;
2582 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2583 output->modrm = GEN_MODRM(mod, rfield, rm);
2584 } else {
2585 /* we need a SIB */
2586 int mod, scale, index, base;
2587
2588 if (it == -1)
2589 index = 4, s = 1;
2590 else
2591 index = (it & 7);
2592
2593 switch (s) {
2594 case 1:
2595 scale = 0;
2596 break;
2597 case 2:
2598 scale = 1;
2599 break;
2600 case 4:
2601 scale = 2;
2602 break;
2603 case 8:
2604 scale = 3;
2605 break;
2606 default: /* then what the smeg is it? */
2607 goto err; /* panic */
2608 }
2609
2610 if (bt == -1) {
2611 base = 5;
2612 mod = 0;
2613 } else {
2614 base = (bt & 7);
2615 if (base != REG_NUM_EBP && o == 0 &&
2616 seg == NO_SEG && !forw_ref &&
2617 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2618 mod = 0;
2619 else if (IS_MOD_01())
2620 mod = 1;
2621 else
2622 mod = 2;
2623 }
2624
2625 output->sib_present = true;
2626 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2627 output->modrm = GEN_MODRM(mod, rfield, 4);
2628 output->sib = GEN_SIB(scale, index, base);
2629 }
2630 } else { /* it's 16-bit */
2631 int mod, rm;
2632 int16_t o = input->offset;
2633
2634 /* check for 64-bit long mode */
2635 if (addrbits == 64)
2636 goto err;
2637
2638 /* check all registers are BX, BP, SI or DI */
2639 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2640 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2641 goto err;
2642
2643 /* ensure the user didn't specify DWORD/QWORD */
2644 if (input->disp_size == 32 || input->disp_size == 64)
2645 goto err;
2646
2647 if (s != 1 && i != -1)
2648 goto err; /* no can do, in 16-bit EA */
2649 if (b == -1 && i != -1) {
2650 int tmp = b;
2651 b = i;
2652 i = tmp;
2653 } /* swap */
2654 if ((b == R_SI || b == R_DI) && i != -1) {
2655 int tmp = b;
2656 b = i;
2657 i = tmp;
2658 }
2659 /* have BX/BP as base, SI/DI index */
2660 if (b == i)
2661 goto err; /* shouldn't ever happen, in theory */
2662 if (i != -1 && b != -1 &&
2663 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2664 goto err; /* invalid combinations */
2665 if (b == -1) /* pure offset: handled above */
2666 goto err; /* so if it gets to here, panic! */
2667
2668 rm = -1;
2669 if (i != -1)
2670 switch (i * 256 + b) {
2671 case R_SI * 256 + R_BX:
2672 rm = 0;
2673 break;
2674 case R_DI * 256 + R_BX:
2675 rm = 1;
2676 break;
2677 case R_SI * 256 + R_BP:
2678 rm = 2;
2679 break;
2680 case R_DI * 256 + R_BP:
2681 rm = 3;
2682 break;
2683 } else
2684 switch (b) {
2685 case R_SI:
2686 rm = 4;
2687 break;
2688 case R_DI:
2689 rm = 5;
2690 break;
2691 case R_BP:
2692 rm = 6;
2693 break;
2694 case R_BX:
2695 rm = 7;
2696 break;
2697 }
2698 if (rm == -1) /* can't happen, in theory */
2699 goto err; /* so panic if it does */
2700
2701 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2702 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2703 mod = 0;
2704 else if (IS_MOD_01())
2705 mod = 1;
2706 else
2707 mod = 2;
2708
2709 output->sib_present = false; /* no SIB - it's 16-bit */
2710 output->bytes = mod; /* bytes of offset needed */
2711 output->modrm = GEN_MODRM(mod, rfield, rm);
2712 }
2713 }
2714 }
2715
2716 output->size = 1 + output->sib_present + output->bytes;
2717 return output->type;
2718
2719 err:
2720 return output->type = EA_INVALID;
2721 }
2722
2723 static void add_asp(insn *ins, int addrbits)
2724 {
2725 int j, valid;
2726 int defdisp;
2727
2728 valid = (addrbits == 64) ? 64|32 : 32|16;
2729
2730 switch (ins->prefixes[PPS_ASIZE]) {
2731 case P_A16:
2732 valid &= 16;
2733 break;
2734 case P_A32:
2735 valid &= 32;
2736 break;
2737 case P_A64:
2738 valid &= 64;
2739 break;
2740 case P_ASP:
2741 valid &= (addrbits == 32) ? 16 : 32;
2742 break;
2743 default:
2744 break;
2745 }
2746
2747 for (j = 0; j < ins->operands; j++) {
2748 if (is_class(MEMORY, ins->oprs[j].type)) {
2749 opflags_t i, b;
2750
2751 /* Verify as Register */
2752 if (!is_register(ins->oprs[j].indexreg))
2753 i = 0;
2754 else
2755 i = nasm_reg_flags[ins->oprs[j].indexreg];
2756
2757 /* Verify as Register */
2758 if (!is_register(ins->oprs[j].basereg))
2759 b = 0;
2760 else
2761 b = nasm_reg_flags[ins->oprs[j].basereg];
2762
2763 if (ins->oprs[j].scale == 0)
2764 i = 0;
2765
2766 if (!i && !b) {
2767 int ds = ins->oprs[j].disp_size;
2768 if ((addrbits != 64 && ds > 8) ||
2769 (addrbits == 64 && ds == 16))
2770 valid &= ds;
2771 } else {
2772 if (!(REG16 & ~b))
2773 valid &= 16;
2774 if (!(REG32 & ~b))
2775 valid &= 32;
2776 if (!(REG64 & ~b))
2777 valid &= 64;
2778
2779 if (!(REG16 & ~i))
2780 valid &= 16;
2781 if (!(REG32 & ~i))
2782 valid &= 32;
2783 if (!(REG64 & ~i))
2784 valid &= 64;
2785 }
2786 }
2787 }
2788
2789 if (valid & addrbits) {
2790 ins->addr_size = addrbits;
2791 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2792 /* Add an address size prefix */
2793 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2794 ins->addr_size = (addrbits == 32) ? 16 : 32;
2795 } else {
2796 /* Impossible... */
2797 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2798 ins->addr_size = addrbits; /* Error recovery */
2799 }
2800
2801 defdisp = ins->addr_size == 16 ? 16 : 32;
2802
2803 for (j = 0; j < ins->operands; j++) {
2804 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2805 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2806 /*
2807 * mem_offs sizes must match the address size; if not,
2808 * strip the MEM_OFFS bit and match only EA instructions
2809 */
2810 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2811 }
2812 }
2813 }
Adding AVX-512 features