1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2009 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * assemble.c code generation for the Netwide Assembler
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - a signed byte immediate operand, from operand 0..3
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \140..\143 - an immediate word or signed byte for operand 0..3
64 * \144..\147 - or 2 (s-field) into opcode byte if operand 0..3
65 * is a signed byte rather than a word. Opcode byte follows.
66 * \150..\153 - an immediate dword or signed byte for operand 0..3
67 * \154..\157 - or 2 (s-field) into opcode byte if operand 0..3
68 * is a signed byte rather than a dword. Opcode byte follows.
69 * \160..\163 - this instruction uses DREX rather than REX, with the
70 * OC0 field set to 0, and the dest field taken from
72 * \164..\167 - this instruction uses DREX rather than REX, with the
73 * OC0 field set to 1, and the dest field taken from
75 * \171 - placement of DREX suffix in the absence of an EA
76 * \172\ab - the register number from operand a in bits 7..4, with
77 * the 4-bit immediate from operand b in bits 3..0.
78 * \173\xab - the register number from operand a in bits 7..4, with
79 * the value b in bits 3..0.
80 * \174\a - the register number from operand a in bits 7..4, and
81 * an arbitrary value in bits 3..0 (assembled as zero.)
82 * \2ab - a ModRM, calculated on EA in operand a, with the spare
83 * field equal to digit b.
84 * \250..\253 - same as \150..\153, except warn if the 64-bit operand
85 * is not equal to the truncated and sign-extended 32-bit
86 * operand; used for 32-bit immediates in 64-bit mode.
87 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
88 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
89 * V field taken from operand 0..3.
90 * \270 - this instruction uses VEX/XOP rather than REX, with the
91 * V field set to 1111b.
93 * VEX/XOP prefixes are followed by the sequence:
94 * \tmm\wlp where mm is the M field; and wlp is:
96 * [w0] ww = 0 for W = 0
97 * [w1] ww = 1 for W = 1
98 * [wx] ww = 2 for W don't care (always assembled as 0)
99 * [ww] ww = 3 for W used as REX.W
101 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
103 * \274..\277 - a signed byte immediate operand, from operand 0..3,
104 * which is to be extended to the operand size.
105 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
106 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
107 * \312 - (disassembler only) invalid with non-default address size.
108 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
109 * \314 - (disassembler only) invalid with REX.B
110 * \315 - (disassembler only) invalid with REX.X
111 * \316 - (disassembler only) invalid with REX.R
112 * \317 - (disassembler only) invalid with REX.W
113 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
114 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
115 * \322 - indicates that this instruction is only valid when the
116 * operand size is the default (instruction to disassembler,
117 * generates no code in the assembler)
118 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
119 * \324 - indicates 64-bit operand size requiring REX prefix.
120 * \325 - instruction which always uses spl/bpl/sil/dil
121 * \330 - a literal byte follows in the code stream, to be added
122 * to the condition code value of the instruction.
123 * \331 - instruction not valid with REP prefix. Hint for
124 * disassembler only; for SSE instructions.
125 * \332 - REP prefix (0xF2 byte) used as opcode extension.
126 * \333 - REP prefix (0xF3 byte) used as opcode extension.
127 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
128 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
129 * \336 - force a REP(E) prefix (0xF2) even if not specified.
130 * \337 - force a REPNE prefix (0xF3) even if not specified.
131 * \336-\337 are still listed as prefixes in the disassembler.
132 * \340 - reserve <operand 0> bytes of uninitialized storage.
133 * Operand 0 had better be a segmentless constant.
134 * \341 - this instruction needs a WAIT "prefix"
135 * \344,\345 - the PUSH/POP (respectively) codes for CS, DS, ES, SS
136 * (POP is never used for CS) depending on operand 0
137 * \346,\347 - the second byte of PUSH/POP codes for FS, GS, depending
139 * \360 - no SSE prefix (== \364\331)
140 * \361 - 66 SSE prefix (== \366\331)
141 * \362 - F2 SSE prefix (== \364\332)
142 * \363 - F3 SSE prefix (== \364\333)
143 * \364 - operand-size prefix (0x66) not permitted
144 * \365 - address-size prefix (0x67) not permitted
145 * \366 - operand-size prefix (0x66) used as opcode extension
146 * \367 - address-size prefix (0x67) used as opcode extension
147 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
148 * 370 is used for Jcc, 371 is used for JMP.
149 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
150 * used for conditional jump over longer jump
153 #include "compiler.h"
157 #include <inttypes.h>
161 #include "assemble.h"
167 * Matching errors. These should be sorted so that more specific
168 * errors come later in the sequence.
176 * Matching success; the conditional ones first
178 MOK_JUMP
, /* Matching OK but needs jmp_match() */
179 MOK_GOOD
/* Matching unconditionally OK */
183 int sib_present
; /* is a SIB byte necessary? */
184 int bytes
; /* # of bytes of offset needed */
185 int size
; /* lazy - this is sib+bytes+1 */
186 uint8_t modrm
, sib
, rex
, rip
; /* the bytes themselves */
189 static uint32_t cpu
; /* cpu level received from nasm.c */
190 static efunc errfunc
;
191 static struct ofmt
*outfmt
;
192 static ListGen
*list
;
194 static int64_t calcsize(int32_t, int64_t, int, insn
*, const uint8_t *);
195 static void gencode(int32_t segment
, int64_t offset
, int bits
,
196 insn
* ins
, const struct itemplate
*temp
,
198 static enum match_result
find_match(const struct itemplate
**tempp
,
200 int32_t segment
, int64_t offset
, int bits
);
201 static enum match_result
matches(const struct itemplate
*, insn
*, int bits
);
202 static int32_t regflag(const operand
*);
203 static int32_t regval(const operand
*);
204 static int rexflags(int, int32_t, int);
205 static int op_rexflags(const operand
*, int);
206 static ea
*process_ea(operand
*, ea
*, int, int, int, int32_t);
207 static void add_asp(insn
*, int);
209 static int has_prefix(insn
* ins
, enum prefix_pos pos
, enum prefixes prefix
)
211 return ins
->prefixes
[pos
] == prefix
;
214 static void assert_no_prefix(insn
* ins
, enum prefix_pos pos
)
216 if (ins
->prefixes
[pos
])
217 errfunc(ERR_NONFATAL
, "invalid %s prefix",
218 prefix_name(ins
->prefixes
[pos
]));
221 static const char *size_name(int size
)
243 static void warn_overflow(int size
, const struct operand
*o
)
245 if (size
< 8 && o
->wrt
== NO_SEG
&& o
->segment
== NO_SEG
) {
246 int64_t lim
= ((int64_t)1 << (size
*8))-1;
247 int64_t data
= o
->offset
;
249 if (data
< ~lim
|| data
> lim
)
250 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
251 "%s data exceeds bounds", size_name(size
));
255 * This routine wrappers the real output format's output routine,
256 * in order to pass a copy of the data off to the listing file
257 * generator at the same time.
259 static void out(int64_t offset
, int32_t segto
, const void *data
,
260 enum out_type type
, uint64_t size
,
261 int32_t segment
, int32_t wrt
)
263 static int32_t lineno
= 0; /* static!!! */
264 static char *lnfname
= NULL
;
267 if (type
== OUT_ADDRESS
&& segment
== NO_SEG
&& wrt
== NO_SEG
) {
269 * This is a non-relocated address, and we're going to
270 * convert it into RAWDATA format.
275 errfunc(ERR_PANIC
, "OUT_ADDRESS with size > 8");
279 WRITEADDR(q
, *(int64_t *)data
, size
);
284 list
->output(offset
, data
, type
, size
);
287 * this call to src_get determines when we call the
288 * debug-format-specific "linenum" function
289 * it updates lineno and lnfname to the current values
290 * returning 0 if "same as last time", -2 if lnfname
291 * changed, and the amount by which lineno changed,
292 * if it did. thus, these variables must be static
295 if (src_get(&lineno
, &lnfname
)) {
296 outfmt
->current_dfmt
->linenum(lnfname
, lineno
, segto
);
299 outfmt
->output(segto
, data
, type
, size
, segment
, wrt
);
302 static bool jmp_match(int32_t segment
, int64_t offset
, int bits
,
303 insn
* ins
, const uint8_t *code
)
308 if ((c
!= 0370 && c
!= 0371) || (ins
->oprs
[0].type
& STRICT
))
312 if (optimizing
< 0 && c
== 0371)
315 isize
= calcsize(segment
, offset
, bits
, ins
, code
);
317 if (ins
->oprs
[0].opflags
& OPFLAG_UNKNOWN
)
318 /* Be optimistic in pass 1 */
321 if (ins
->oprs
[0].segment
!= segment
)
324 isize
= ins
->oprs
[0].offset
- offset
- isize
; /* isize is delta */
325 return (isize
>= -128 && isize
<= 127); /* is it byte size? */
328 int64_t assemble(int32_t segment
, int64_t offset
, int bits
, uint32_t cp
,
329 insn
* instruction
, struct ofmt
*output
, efunc error
,
332 const struct itemplate
*temp
;
337 int64_t start
= offset
;
338 int64_t wsize
= 0; /* size for DB etc. */
340 errfunc
= error
; /* to pass to other functions */
342 outfmt
= output
; /* likewise */
343 list
= listgen
; /* and again */
345 switch (instruction
->opcode
) {
375 int32_t t
= instruction
->times
;
378 "instruction->times < 0 (%ld) in assemble()", t
);
380 while (t
--) { /* repeat TIMES times */
381 for (e
= instruction
->eops
; e
; e
= e
->next
) {
382 if (e
->type
== EOT_DB_NUMBER
) {
384 if (e
->segment
!= NO_SEG
)
385 errfunc(ERR_NONFATAL
,
386 "one-byte relocation attempted");
388 uint8_t out_byte
= e
->offset
;
389 out(offset
, segment
, &out_byte
,
390 OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
392 } else if (wsize
> 8) {
393 errfunc(ERR_NONFATAL
,
394 "integer supplied to a DT, DO or DY"
397 out(offset
, segment
, &e
->offset
,
398 OUT_ADDRESS
, wsize
, e
->segment
, e
->wrt
);
400 } else if (e
->type
== EOT_DB_STRING
||
401 e
->type
== EOT_DB_STRING_FREE
) {
404 out(offset
, segment
, e
->stringval
,
405 OUT_RAWDATA
, e
->stringlen
, NO_SEG
, NO_SEG
);
406 align
= e
->stringlen
% wsize
;
409 align
= wsize
- align
;
410 out(offset
, segment
, zero_buffer
,
411 OUT_RAWDATA
, align
, NO_SEG
, NO_SEG
);
413 offset
+= e
->stringlen
+ align
;
416 if (t
> 0 && t
== instruction
->times
- 1) {
418 * Dummy call to list->output to give the offset to the
421 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
422 list
->uplevel(LIST_TIMES
);
425 if (instruction
->times
> 1)
426 list
->downlevel(LIST_TIMES
);
427 return offset
- start
;
430 if (instruction
->opcode
== I_INCBIN
) {
431 const char *fname
= instruction
->eops
->stringval
;
434 fp
= fopen(fname
, "rb");
436 error(ERR_NONFATAL
, "`incbin': unable to open file `%s'",
438 } else if (fseek(fp
, 0L, SEEK_END
) < 0) {
439 error(ERR_NONFATAL
, "`incbin': unable to seek on file `%s'",
442 static char buf
[4096];
443 size_t t
= instruction
->times
;
448 if (instruction
->eops
->next
) {
449 base
= instruction
->eops
->next
->offset
;
451 if (instruction
->eops
->next
->next
&&
452 len
> (size_t)instruction
->eops
->next
->next
->offset
)
453 len
= (size_t)instruction
->eops
->next
->next
->offset
;
456 * Dummy call to list->output to give the offset to the
459 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
460 list
->uplevel(LIST_INCBIN
);
464 fseek(fp
, base
, SEEK_SET
);
468 m
= fread(buf
, 1, l
> sizeof(buf
) ? sizeof(buf
) : l
, fp
);
471 * This shouldn't happen unless the file
472 * actually changes while we are reading
476 "`incbin': unexpected EOF while"
477 " reading file `%s'", fname
);
478 t
= 0; /* Try to exit cleanly */
481 out(offset
, segment
, buf
, OUT_RAWDATA
, m
,
486 list
->downlevel(LIST_INCBIN
);
487 if (instruction
->times
> 1) {
489 * Dummy call to list->output to give the offset to the
492 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
493 list
->uplevel(LIST_TIMES
);
494 list
->downlevel(LIST_TIMES
);
497 return instruction
->times
* len
;
499 return 0; /* if we're here, there's an error */
502 /* Check to see if we need an address-size prefix */
503 add_asp(instruction
, bits
);
505 m
= find_match(&temp
, instruction
, segment
, offset
, bits
);
509 int64_t insn_size
= calcsize(segment
, offset
, bits
,
510 instruction
, temp
->code
);
511 itimes
= instruction
->times
;
512 if (insn_size
< 0) /* shouldn't be, on pass two */
513 error(ERR_PANIC
, "errors made it through from pass one");
516 for (j
= 0; j
< MAXPREFIX
; j
++) {
518 switch (instruction
->prefixes
[j
]) {
536 error(ERR_WARNING
| ERR_PASS2
,
537 "cs segment base generated, but will be ignored in 64-bit mode");
543 error(ERR_WARNING
| ERR_PASS2
,
544 "ds segment base generated, but will be ignored in 64-bit mode");
550 error(ERR_WARNING
| ERR_PASS2
,
551 "es segment base generated, but will be ignored in 64-bit mode");
563 error(ERR_WARNING
| ERR_PASS2
,
564 "ss segment base generated, but will be ignored in 64-bit mode");
571 "segr6 and segr7 cannot be used as prefixes");
576 "16-bit addressing is not supported "
578 } else if (bits
!= 16)
588 "64-bit addressing is only supported "
612 error(ERR_PANIC
, "invalid instruction prefix");
615 out(offset
, segment
, &c
, OUT_RAWDATA
, 1,
620 insn_end
= offset
+ insn_size
;
621 gencode(segment
, offset
, bits
, instruction
,
624 if (itimes
> 0 && itimes
== instruction
->times
- 1) {
626 * Dummy call to list->output to give the offset to the
629 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
630 list
->uplevel(LIST_TIMES
);
633 if (instruction
->times
> 1)
634 list
->downlevel(LIST_TIMES
);
635 return offset
- start
;
639 case MERR_OPSIZEMISSING
:
640 error(ERR_NONFATAL
, "operation size not specified");
642 case MERR_OPSIZEMISMATCH
:
643 error(ERR_NONFATAL
, "mismatch in operand sizes");
646 error(ERR_NONFATAL
, "no instruction for this cpu level");
649 error(ERR_NONFATAL
, "instruction not supported in %d-bit mode",
654 "invalid combination of opcode and operands");
661 int64_t insn_size(int32_t segment
, int64_t offset
, int bits
, uint32_t cp
,
662 insn
* instruction
, efunc error
)
664 const struct itemplate
*temp
;
667 errfunc
= error
; /* to pass to other functions */
670 if (instruction
->opcode
== -1)
673 if (instruction
->opcode
== I_DB
|| instruction
->opcode
== I_DW
||
674 instruction
->opcode
== I_DD
|| instruction
->opcode
== I_DQ
||
675 instruction
->opcode
== I_DT
|| instruction
->opcode
== I_DO
||
676 instruction
->opcode
== I_DY
) {
678 int32_t isize
, osize
, wsize
= 0; /* placate gcc */
681 switch (instruction
->opcode
) {
707 for (e
= instruction
->eops
; e
; e
= e
->next
) {
711 if (e
->type
== EOT_DB_NUMBER
)
713 else if (e
->type
== EOT_DB_STRING
||
714 e
->type
== EOT_DB_STRING_FREE
)
715 osize
= e
->stringlen
;
717 align
= (-osize
) % wsize
;
720 isize
+= osize
+ align
;
722 return isize
* instruction
->times
;
725 if (instruction
->opcode
== I_INCBIN
) {
726 const char *fname
= instruction
->eops
->stringval
;
730 fp
= fopen(fname
, "rb");
732 error(ERR_NONFATAL
, "`incbin': unable to open file `%s'",
734 else if (fseek(fp
, 0L, SEEK_END
) < 0)
735 error(ERR_NONFATAL
, "`incbin': unable to seek on file `%s'",
740 if (instruction
->eops
->next
) {
741 len
-= instruction
->eops
->next
->offset
;
742 if (instruction
->eops
->next
->next
&&
743 len
> (size_t)instruction
->eops
->next
->next
->offset
) {
744 len
= (size_t)instruction
->eops
->next
->next
->offset
;
747 return instruction
->times
* len
;
749 return 0; /* if we're here, there's an error */
752 /* Check to see if we need an address-size prefix */
753 add_asp(instruction
, bits
);
755 m
= find_match(&temp
, instruction
, segment
, offset
, bits
);
757 /* we've matched an instruction. */
759 const uint8_t *codes
= temp
->code
;
762 isize
= calcsize(segment
, offset
, bits
, instruction
, codes
);
765 for (j
= 0; j
< MAXPREFIX
; j
++) {
766 switch (instruction
->prefixes
[j
]) {
792 return isize
* instruction
->times
;
794 return -1; /* didn't match any instruction */
798 static bool possible_sbyte(operand
*o
)
800 return o
->wrt
== NO_SEG
&& o
->segment
== NO_SEG
&&
801 !(o
->opflags
& OPFLAG_UNKNOWN
) &&
802 optimizing
>= 0 && !(o
->type
& STRICT
);
805 /* check that opn[op] is a signed byte of size 16 or 32 */
806 static bool is_sbyte16(operand
*o
)
810 if (!possible_sbyte(o
))
814 return v
>= -128 && v
<= 127;
817 static bool is_sbyte32(operand
*o
)
821 if (!possible_sbyte(o
))
825 return v
>= -128 && v
<= 127;
828 /* Common construct */
829 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
831 static int64_t calcsize(int32_t segment
, int64_t offset
, int bits
,
832 insn
* ins
, const uint8_t *codes
)
841 ins
->rex
= 0; /* Ensure REX is reset */
843 if (ins
->prefixes
[PPS_OSIZE
] == P_O64
)
846 (void)segment
; /* Don't warn that this parameter is unused */
847 (void)offset
; /* Don't warn that this parameter is unused */
851 op1
= (c
& 3) + ((opex
& 1) << 2);
852 op2
= ((c
>> 3) & 3) + ((opex
& 2) << 1);
853 opx
= &ins
->oprs
[op1
];
854 opex
= 0; /* For the next iteration */
861 codes
+= c
, length
+= c
;
872 op_rexflags(opx
, REX_B
|REX_H
|REX_P
|REX_W
);
887 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
888 length
+= (opx
->type
& BITS16
) ? 2 : 4;
890 length
+= (bits
== 16) ? 2 : 4;
898 length
+= ins
->addr_size
>> 3;
906 length
+= 8; /* MOV reg64/imm */
914 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
915 length
+= (opx
->type
& BITS16
) ? 2 : 4;
917 length
+= (bits
== 16) ? 2 : 4;
929 length
+= is_sbyte16(opx
) ? 1 : 2;
938 length
+= is_sbyte32(opx
) ? 1 : 4;
949 ins
->drexdst
= regval(opx
);
954 ins
->rex
|= REX_D
|REX_OC
;
955 ins
->drexdst
= regval(opx
);
969 length
+= is_sbyte32(opx
) ? 1 : 4;
978 ins
->drexdst
= regval(opx
);
979 ins
->vex_cm
= *codes
++;
980 ins
->vex_wlp
= *codes
++;
986 ins
->vex_cm
= *codes
++;
987 ins
->vex_wlp
= *codes
++;
1000 length
+= (bits
!= 16) && !has_prefix(ins
, PPS_ASIZE
, P_A16
);
1004 length
+= (bits
!= 32) && !has_prefix(ins
, PPS_ASIZE
, P_A32
);
1011 if (bits
!= 64 || has_prefix(ins
, PPS_ASIZE
, P_A16
) ||
1012 has_prefix(ins
, PPS_ASIZE
, P_A32
))
1020 length
+= (bits
!= 16);
1024 length
+= (bits
== 16);
1062 if (!ins
->prefixes
[PPS_LREP
])
1063 ins
->prefixes
[PPS_LREP
] = P_REP
;
1067 if (!ins
->prefixes
[PPS_LREP
])
1068 ins
->prefixes
[PPS_LREP
] = P_REPNE
;
1072 if (ins
->oprs
[0].segment
!= NO_SEG
)
1073 errfunc(ERR_NONFATAL
, "attempt to reserve non-constant"
1074 " quantity of BSS space");
1076 length
+= ins
->oprs
[0].offset
;
1080 if (!ins
->prefixes
[PPS_WAIT
])
1081 ins
->prefixes
[PPS_WAIT
] = P_WAIT
;
1131 struct operand
*opy
= &ins
->oprs
[op2
];
1133 ea_data
.rex
= 0; /* Ensure ea.REX is initially 0 */
1136 /* pick rfield from operand b (opx) */
1137 rflags
= regflag(opx
);
1138 rfield
= nasm_regvals
[opx
->basereg
];
1143 if (!process_ea(opy
, &ea_data
, bits
,
1144 ins
->addr_size
, rfield
, rflags
)) {
1145 errfunc(ERR_NONFATAL
, "invalid effective address");
1148 ins
->rex
|= ea_data
.rex
;
1149 length
+= ea_data
.size
;
1155 errfunc(ERR_PANIC
, "internal instruction table corrupt"
1156 ": instruction code \\%o (0x%02X) given", c
, c
);
1161 ins
->rex
&= rex_mask
;
1163 if (ins
->rex
& REX_NH
) {
1164 if (ins
->rex
& REX_H
) {
1165 errfunc(ERR_NONFATAL
, "instruction cannot use high registers");
1168 ins
->rex
&= ~REX_P
; /* Don't force REX prefix due to high reg */
1171 if (ins
->rex
& REX_V
) {
1172 int bad32
= REX_R
|REX_W
|REX_X
|REX_B
;
1174 if (ins
->rex
& REX_H
) {
1175 errfunc(ERR_NONFATAL
, "cannot use high register in vex instruction");
1178 switch (ins
->vex_wlp
& 030) {
1192 if (bits
!= 64 && ((ins
->rex
& bad32
) || ins
->drexdst
> 7)) {
1193 errfunc(ERR_NONFATAL
, "invalid operands in non-64-bit mode");
1196 if (ins
->vex_cm
!= 1 || (ins
->rex
& (REX_W
|REX_R
|REX_B
)))
1200 } else if (ins
->rex
& REX_D
) {
1201 if (ins
->rex
& REX_H
) {
1202 errfunc(ERR_NONFATAL
, "cannot use high register in drex instruction");
1205 if (bits
!= 64 && ((ins
->rex
& (REX_R
|REX_W
|REX_X
|REX_B
)) ||
1206 ins
->drexdst
> 7)) {
1207 errfunc(ERR_NONFATAL
, "invalid operands in non-64-bit mode");
1211 } else if (ins
->rex
& REX_REAL
) {
1212 if (ins
->rex
& REX_H
) {
1213 errfunc(ERR_NONFATAL
, "cannot use high register in rex instruction");
1215 } else if (bits
== 64) {
1217 } else if ((ins
->rex
& REX_L
) &&
1218 !(ins
->rex
& (REX_P
|REX_W
|REX_X
|REX_B
)) &&
1221 assert_no_prefix(ins
, PPS_LREP
);
1224 errfunc(ERR_NONFATAL
, "invalid operands in non-64-bit mode");
1232 #define EMIT_REX() \
1233 if (!(ins->rex & (REX_D|REX_V)) && (ins->rex & REX_REAL) && (bits == 64)) { \
1234 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1235 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1240 static void gencode(int32_t segment
, int64_t offset
, int bits
,
1241 insn
* ins
, const struct itemplate
*temp
,
1244 static char condval
[] = { /* conditional opcodes */
1245 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1246 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1247 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1254 struct operand
*opx
;
1255 const uint8_t *codes
= temp
->code
;
1260 op1
= (c
& 3) + ((opex
& 1) << 2);
1261 op2
= ((c
>> 3) & 3) + ((opex
& 2) << 1);
1262 opx
= &ins
->oprs
[op1
];
1263 opex
= 0; /* For the next iteration */
1271 out(offset
, segment
, codes
, OUT_RAWDATA
, c
, NO_SEG
, NO_SEG
);
1284 bytes
[0] = *codes
++ + (regval(opx
) & 7);
1285 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1290 /* The test for BITS8 and SBYTE here is intended to avoid
1291 warning on optimizer actions due to SBYTE, while still
1292 warn on explicit BYTE directives. Also warn, obviously,
1293 if the optimizer isn't enabled. */
1294 if (((opx
->type
& BITS8
) ||
1295 !(opx
->type
& temp
->opd
[op1
] & BYTENESS
)) &&
1296 (opx
->offset
< -128 || opx
->offset
> 127)) {
1297 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1298 "signed byte value exceeds bounds");
1300 if (opx
->segment
!= NO_SEG
) {
1302 out(offset
, segment
, &data
, OUT_ADDRESS
, 1,
1303 opx
->segment
, opx
->wrt
);
1305 bytes
[0] = opx
->offset
;
1306 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1313 if (opx
->offset
< -256 || opx
->offset
> 255) {
1314 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1315 "byte value exceeds bounds");
1317 if (opx
->segment
!= NO_SEG
) {
1319 out(offset
, segment
, &data
, OUT_ADDRESS
, 1,
1320 opx
->segment
, opx
->wrt
);
1322 bytes
[0] = opx
->offset
;
1323 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1330 if (opx
->offset
< 0 || opx
->offset
> 255)
1331 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1332 "unsigned byte value exceeds bounds");
1333 if (opx
->segment
!= NO_SEG
) {
1335 out(offset
, segment
, &data
, OUT_ADDRESS
, 1,
1336 opx
->segment
, opx
->wrt
);
1338 bytes
[0] = opx
->offset
;
1339 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1346 warn_overflow(2, opx
);
1348 out(offset
, segment
, &data
, OUT_ADDRESS
, 2,
1349 opx
->segment
, opx
->wrt
);
1354 if (opx
->type
& (BITS16
| BITS32
))
1355 size
= (opx
->type
& BITS16
) ? 2 : 4;
1357 size
= (bits
== 16) ? 2 : 4;
1358 warn_overflow(size
, opx
);
1360 out(offset
, segment
, &data
, OUT_ADDRESS
, size
,
1361 opx
->segment
, opx
->wrt
);
1366 warn_overflow(4, opx
);
1368 out(offset
, segment
, &data
, OUT_ADDRESS
, 4,
1369 opx
->segment
, opx
->wrt
);
1375 size
= ins
->addr_size
>> 3;
1376 warn_overflow(size
, opx
);
1377 out(offset
, segment
, &data
, OUT_ADDRESS
, size
,
1378 opx
->segment
, opx
->wrt
);
1383 if (opx
->segment
!= segment
)
1384 errfunc(ERR_NONFATAL
,
1385 "short relative jump outside segment");
1386 data
= opx
->offset
- insn_end
;
1387 if (data
> 127 || data
< -128)
1388 errfunc(ERR_NONFATAL
, "short jump is out of range");
1390 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1395 data
= (int64_t)opx
->offset
;
1396 out(offset
, segment
, &data
, OUT_ADDRESS
, 8,
1397 opx
->segment
, opx
->wrt
);
1402 if (opx
->segment
!= segment
) {
1404 out(offset
, segment
, &data
,
1405 OUT_REL2ADR
, insn_end
- offset
,
1406 opx
->segment
, opx
->wrt
);
1408 data
= opx
->offset
- insn_end
;
1409 out(offset
, segment
, &data
,
1410 OUT_ADDRESS
, 2, NO_SEG
, NO_SEG
);
1416 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
1417 size
= (opx
->type
& BITS16
) ? 2 : 4;
1419 size
= (bits
== 16) ? 2 : 4;
1420 if (opx
->segment
!= segment
) {
1422 out(offset
, segment
, &data
,
1423 size
== 2 ? OUT_REL2ADR
: OUT_REL4ADR
,
1424 insn_end
- offset
, opx
->segment
, opx
->wrt
);
1426 data
= opx
->offset
- insn_end
;
1427 out(offset
, segment
, &data
,
1428 OUT_ADDRESS
, size
, NO_SEG
, NO_SEG
);
1434 if (opx
->segment
!= segment
) {
1436 out(offset
, segment
, &data
,
1437 OUT_REL4ADR
, insn_end
- offset
,
1438 opx
->segment
, opx
->wrt
);
1440 data
= opx
->offset
- insn_end
;
1441 out(offset
, segment
, &data
,
1442 OUT_ADDRESS
, 4, NO_SEG
, NO_SEG
);
1448 if (opx
->segment
== NO_SEG
)
1449 errfunc(ERR_NONFATAL
, "value referenced by FAR is not"
1452 out(offset
, segment
, &data
, OUT_ADDRESS
, 2,
1453 outfmt
->segbase(1 + opx
->segment
),
1460 warn_overflow(2, opx
);
1461 if (is_sbyte16(opx
)) {
1463 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1467 out(offset
, segment
, &data
, OUT_ADDRESS
, 2,
1468 opx
->segment
, opx
->wrt
);
1475 bytes
[0] = *codes
++;
1476 if (is_sbyte16(opx
))
1477 bytes
[0] |= 2; /* s-bit */
1478 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1484 warn_overflow(4, opx
);
1485 if (is_sbyte32(opx
)) {
1487 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1491 out(offset
, segment
, &data
, OUT_ADDRESS
, 4,
1492 opx
->segment
, opx
->wrt
);
1499 bytes
[0] = *codes
++;
1500 if (is_sbyte32(opx
))
1501 bytes
[0] |= 2; /* s-bit */
1502 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1512 (ins
->drexdst
<< 4) |
1513 (ins
->rex
& REX_OC
? 0x08 : 0) |
1514 (ins
->rex
& (REX_R
|REX_X
|REX_B
));
1516 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1522 opx
= &ins
->oprs
[c
>> 3];
1523 bytes
[0] = nasm_regvals
[opx
->basereg
] << 4;
1524 opx
= &ins
->oprs
[c
& 7];
1525 if (opx
->segment
!= NO_SEG
|| opx
->wrt
!= NO_SEG
) {
1526 errfunc(ERR_NONFATAL
,
1527 "non-absolute expression not permitted as argument %d",
1530 if (opx
->offset
& ~15) {
1531 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1532 "four-bit argument exceeds bounds");
1534 bytes
[0] |= opx
->offset
& 15;
1536 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1542 opx
= &ins
->oprs
[c
>> 4];
1543 bytes
[0] = nasm_regvals
[opx
->basereg
] << 4;
1545 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1551 opx
= &ins
->oprs
[c
];
1552 bytes
[0] = nasm_regvals
[opx
->basereg
] << 4;
1553 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1559 if (opx
->wrt
== NO_SEG
&& opx
->segment
== NO_SEG
&&
1560 (int32_t)data
!= (int64_t)data
) {
1561 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1562 "signed dword immediate exceeds bounds");
1564 if (is_sbyte32(opx
)) {
1566 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1570 out(offset
, segment
, &data
, OUT_ADDRESS
, 4,
1571 opx
->segment
, opx
->wrt
);
1578 if (opx
->wrt
== NO_SEG
&& opx
->segment
== NO_SEG
&&
1579 (int32_t)data
!= (int64_t)data
) {
1580 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1581 "signed dword immediate exceeds bounds");
1583 out(offset
, segment
, &data
, OUT_ADDRESS
, 4,
1584 opx
->segment
, opx
->wrt
);
1591 if (ins
->vex_cm
!= 1 || (ins
->rex
& (REX_W
|REX_X
|REX_B
))) {
1592 bytes
[0] = (ins
->vex_cm
>> 6) ? 0x8f : 0xc4;
1593 bytes
[1] = (ins
->vex_cm
& 31) | ((~ins
->rex
& 7) << 5);
1594 bytes
[2] = ((ins
->rex
& REX_W
) << (7-3)) |
1595 ((~ins
->drexdst
& 15)<< 3) | (ins
->vex_wlp
& 07);
1596 out(offset
, segment
, &bytes
, OUT_RAWDATA
, 3, NO_SEG
, NO_SEG
);
1600 bytes
[1] = ((~ins
->rex
& REX_R
) << (7-2)) |
1601 ((~ins
->drexdst
& 15) << 3) | (ins
->vex_wlp
& 07);
1602 out(offset
, segment
, &bytes
, OUT_RAWDATA
, 2, NO_SEG
, NO_SEG
);
1612 if (ins
->rex
& REX_W
)
1614 else if (ins
->prefixes
[PPS_OSIZE
] == P_O16
)
1616 else if (ins
->prefixes
[PPS_OSIZE
] == P_O32
)
1621 um
= (uint64_t)2 << (s
-1);
1624 if (uv
> 127 && uv
< (uint64_t)-128 &&
1625 (uv
< um
-128 || uv
> um
-1)) {
1626 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1627 "signed byte value exceeds bounds");
1629 if (opx
->segment
!= NO_SEG
) {
1631 out(offset
, segment
, &data
, OUT_ADDRESS
, 1,
1632 opx
->segment
, opx
->wrt
);
1635 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1646 if (bits
== 32 && !has_prefix(ins
, PPS_ASIZE
, P_A16
)) {
1648 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1655 if (bits
!= 32 && !has_prefix(ins
, PPS_ASIZE
, P_A32
)) {
1657 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1676 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1685 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1703 *bytes
= *codes
++ ^ condval
[ins
->condition
];
1704 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1713 *bytes
= c
- 0332 + 0xF2;
1714 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1719 if (ins
->rex
& REX_R
) {
1721 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1724 ins
->rex
&= ~(REX_L
|REX_R
);
1735 if (ins
->oprs
[0].segment
!= NO_SEG
)
1736 errfunc(ERR_PANIC
, "non-constant BSS size in pass two");
1738 int64_t size
= ins
->oprs
[0].offset
;
1740 out(offset
, segment
, NULL
,
1741 OUT_RESERVE
, size
, NO_SEG
, NO_SEG
);
1752 switch (ins
->oprs
[0].basereg
) {
1767 "bizarre 8086 segment register received");
1769 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1776 switch (ins
->oprs
[0].basereg
) {
1785 "bizarre 386 segment register received");
1787 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1796 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1802 bytes
[0] = c
- 0362 + 0xf2;
1803 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1813 *bytes
= c
- 0366 + 0x66;
1814 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1824 *bytes
= bits
== 16 ? 3 : 5;
1825 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1848 struct operand
*opy
= &ins
->oprs
[op2
];
1851 /* pick rfield from operand b (opx) */
1852 rflags
= regflag(opx
);
1853 rfield
= nasm_regvals
[opx
->basereg
];
1855 /* rfield is constant */
1860 if (!process_ea(opy
, &ea_data
, bits
, ins
->addr_size
,
1862 errfunc(ERR_NONFATAL
, "invalid effective address");
1867 *p
++ = ea_data
.modrm
;
1868 if (ea_data
.sib_present
)
1871 /* DREX suffixes come between the SIB and the displacement */
1872 if (ins
->rex
& REX_D
) {
1873 *p
++ = (ins
->drexdst
<< 4) |
1874 (ins
->rex
& REX_OC
? 0x08 : 0) |
1875 (ins
->rex
& (REX_R
|REX_X
|REX_B
));
1880 out(offset
, segment
, bytes
, OUT_RAWDATA
, s
, NO_SEG
, NO_SEG
);
1883 * Make sure the address gets the right offset in case
1884 * the line breaks in the .lst file (BR 1197827)
1889 switch (ea_data
.bytes
) {
1897 warn_overflow(ea_data
.bytes
, opy
);
1900 if (opy
->segment
== segment
) {
1902 out(offset
, segment
, &data
, OUT_ADDRESS
,
1903 ea_data
.bytes
, NO_SEG
, NO_SEG
);
1905 out(offset
, segment
, &data
, OUT_REL4ADR
,
1906 insn_end
- offset
, opy
->segment
, opy
->wrt
);
1910 out(offset
, segment
, &data
, OUT_ADDRESS
,
1911 ea_data
.bytes
, opy
->segment
, opy
->wrt
);
1917 "Invalid amount of bytes (%d) for offset?!",
1926 errfunc(ERR_PANIC
, "internal instruction table corrupt"
1927 ": instruction code \\%o (0x%02X) given", c
, c
);
1933 static int32_t regflag(const operand
* o
)
1935 if (o
->basereg
< EXPR_REG_START
|| o
->basereg
>= REG_ENUM_LIMIT
) {
1936 errfunc(ERR_PANIC
, "invalid operand passed to regflag()");
1938 return nasm_reg_flags
[o
->basereg
];
1941 static int32_t regval(const operand
* o
)
1943 if (o
->basereg
< EXPR_REG_START
|| o
->basereg
>= REG_ENUM_LIMIT
) {
1944 errfunc(ERR_PANIC
, "invalid operand passed to regval()");
1946 return nasm_regvals
[o
->basereg
];
1949 static int op_rexflags(const operand
* o
, int mask
)
1954 if (o
->basereg
< EXPR_REG_START
|| o
->basereg
>= REG_ENUM_LIMIT
) {
1955 errfunc(ERR_PANIC
, "invalid operand passed to op_rexflags()");
1958 flags
= nasm_reg_flags
[o
->basereg
];
1959 val
= nasm_regvals
[o
->basereg
];
1961 return rexflags(val
, flags
, mask
);
1964 static int rexflags(int val
, int32_t flags
, int mask
)
1969 rex
|= REX_B
|REX_X
|REX_R
;
1972 if (!(REG_HIGH
& ~flags
)) /* AH, CH, DH, BH */
1974 else if (!(REG8
& ~flags
) && val
>= 4) /* SPL, BPL, SIL, DIL */
1980 static enum match_result
find_match(const struct itemplate
**tempp
,
1982 int32_t segment
, int64_t offset
, int bits
)
1984 const struct itemplate
*temp
;
1985 enum match_result m
, merr
;
1986 int32_t xsizeflags
[MAX_OPERANDS
];
1987 bool opsizemissing
= false;
1990 for (i
= 0; i
< instruction
->operands
; i
++)
1991 xsizeflags
[i
] = instruction
->oprs
[i
].type
& SIZE_MASK
;
1993 merr
= MERR_INVALOP
;
1995 for (temp
= nasm_instructions
[instruction
->opcode
];
1996 temp
->opcode
!= I_none
; temp
++) {
1997 m
= matches(temp
, instruction
, bits
);
1998 if (m
== MOK_JUMP
) {
1999 if (jmp_match(segment
, offset
, bits
, instruction
, temp
->code
))
2003 } else if (m
== MERR_OPSIZEMISSING
&&
2004 (temp
->flags
& IF_SMASK
) != IF_SX
) {
2006 * Missing operand size and a candidate for fuzzy matching...
2008 for (i
= 0; i
< temp
->operands
; i
++)
2009 xsizeflags
[i
] |= temp
->opd
[i
] & SIZE_MASK
;
2011 opsizemissing
= true;
2015 if (merr
== MOK_GOOD
)
2019 /* No match, but see if we can get a fuzzy operand size match... */
2023 for (i
= 0; i
< instruction
->operands
; i
++) {
2024 /* This tests if xsizeflags[i] has more than one bit set */
2025 if ((xsizeflags
[i
] & (xsizeflags
[i
]-1)))
2026 goto done
; /* No luck */
2028 instruction
->oprs
[i
].type
|= xsizeflags
[i
]; /* Set the size */
2031 /* Try matching again... */
2032 for (temp
= nasm_instructions
[instruction
->opcode
];
2033 temp
->opcode
!= I_none
; temp
++) {
2034 m
= matches(temp
, instruction
, bits
);
2035 if (m
== MOK_JUMP
) {
2036 if (jmp_match(segment
, offset
, bits
, instruction
, temp
->code
))
2043 if (merr
== MOK_GOOD
)
2052 static enum match_result
matches(const struct itemplate
*itemp
,
2053 insn
*instruction
, int bits
)
2055 int i
, size
[MAX_OPERANDS
], asize
, oprs
, ret
;
2056 bool opsizemissing
= false;
2063 if (itemp
->opcode
!= instruction
->opcode
)
2064 return MERR_INVALOP
;
2067 * Count the operands
2069 if (itemp
->operands
!= instruction
->operands
)
2070 return MERR_INVALOP
;
2073 * Check that no spurious colons or TOs are present
2075 for (i
= 0; i
< itemp
->operands
; i
++)
2076 if (instruction
->oprs
[i
].type
& ~itemp
->opd
[i
] & (COLON
| TO
))
2077 return MERR_INVALOP
;
2080 * Process size flags
2082 if (itemp
->flags
& IF_ARMASK
) {
2083 memset(size
, 0, sizeof size
);
2085 i
= ((itemp
->flags
& IF_ARMASK
) >> IF_ARSHFT
) - 1;
2087 switch (itemp
->flags
& IF_SMASK
) {
2124 switch (itemp
->flags
& IF_SMASK
) {
2159 for (i
= 0; i
< MAX_OPERANDS
; i
++)
2164 * Check that the operand flags all match up
2166 for (i
= 0; i
< itemp
->operands
; i
++) {
2167 int32_t type
= instruction
->oprs
[i
].type
;
2168 if (!(type
& SIZE_MASK
))
2171 if (itemp
->opd
[i
] & SAME_AS
) {
2172 int j
= itemp
->opd
[i
] & ~SAME_AS
;
2173 if (type
!= instruction
->oprs
[j
].type
||
2174 instruction
->oprs
[i
].basereg
!= instruction
->oprs
[j
].basereg
)
2175 return MERR_INVALOP
;
2176 } else if (itemp
->opd
[i
] & ~type
||
2177 ((itemp
->opd
[i
] & SIZE_MASK
) &&
2178 ((itemp
->opd
[i
] ^ type
) & SIZE_MASK
))) {
2179 if ((itemp
->opd
[i
] & ~type
& ~SIZE_MASK
) || (type
& SIZE_MASK
))
2180 return MERR_INVALOP
;
2182 opsizemissing
= true;
2187 return MERR_OPSIZEMISSING
;
2190 * Check operand sizes
2192 if (itemp
->flags
& (IF_SM
| IF_SM2
)) {
2193 oprs
= (itemp
->flags
& IF_SM2
? 2 : itemp
->operands
);
2195 for (i
= 0; i
< oprs
; i
++) {
2196 if ((asize
= itemp
->opd
[i
] & SIZE_MASK
) != 0) {
2198 for (j
= 0; j
< oprs
; j
++)
2204 oprs
= itemp
->operands
;
2207 for (i
= 0; i
< itemp
->operands
; i
++) {
2208 if (!(itemp
->opd
[i
] & SIZE_MASK
) &&
2209 (instruction
->oprs
[i
].type
& SIZE_MASK
& ~size
[i
]))
2210 return MERR_OPSIZEMISMATCH
;
2214 * Check template is okay at the set cpu level
2216 if (((itemp
->flags
& IF_PLEVEL
) > cpu
))
2220 * Verify the appropriate long mode flag.
2222 if ((itemp
->flags
& (bits
== 64 ? IF_NOLONG
: IF_LONG
)))
2223 return MERR_BADMODE
;
2226 * Check if special handling needed for Jumps
2228 if ((uint8_t)(itemp
->code
[0]) >= 0370)
2234 static ea
*process_ea(operand
* input
, ea
* output
, int bits
,
2235 int addrbits
, int rfield
, int32_t rflags
)
2237 bool forw_ref
= !!(input
->opflags
& OPFLAG_UNKNOWN
);
2239 output
->rip
= false;
2241 /* REX flags for the rfield operand */
2242 output
->rex
|= rexflags(rfield
, rflags
, REX_R
|REX_P
|REX_W
|REX_H
);
2244 if (!(REGISTER
& ~input
->type
)) { /* register direct */
2248 if (input
->basereg
< EXPR_REG_START
/* Verify as Register */
2249 || input
->basereg
>= REG_ENUM_LIMIT
)
2252 i
= nasm_regvals
[input
->basereg
];
2255 return NULL
; /* Invalid EA register */
2257 output
->rex
|= op_rexflags(input
, REX_B
|REX_P
|REX_W
|REX_H
);
2259 output
->sib_present
= false; /* no SIB necessary */
2260 output
->bytes
= 0; /* no offset necessary either */
2261 output
->modrm
= 0xC0 | ((rfield
& 7) << 3) | (i
& 7);
2262 } else { /* it's a memory reference */
2263 if (input
->basereg
== -1
2264 && (input
->indexreg
== -1 || input
->scale
== 0)) {
2265 /* it's a pure offset */
2266 if (bits
== 64 && (~input
->type
& IP_REL
)) {
2267 int scale
, index
, base
;
2268 output
->sib_present
= true;
2272 output
->sib
= (scale
<< 6) | (index
<< 3) | base
;
2274 output
->modrm
= 4 | ((rfield
& 7) << 3);
2275 output
->rip
= false;
2277 output
->sib_present
= false;
2278 output
->bytes
= (addrbits
!= 16 ? 4 : 2);
2279 output
->modrm
= (addrbits
!= 16 ? 5 : 6) | ((rfield
& 7) << 3);
2280 output
->rip
= bits
== 64;
2282 } else { /* it's an indirection */
2283 int i
= input
->indexreg
, b
= input
->basereg
, s
= input
->scale
;
2284 int32_t o
= input
->offset
, seg
= input
->segment
;
2285 int hb
= input
->hintbase
, ht
= input
->hinttype
;
2288 int32_t ix
, bx
; /* register flags */
2291 i
= -1; /* make this easy, at least */
2293 if (i
>= EXPR_REG_START
&& i
< REG_ENUM_LIMIT
) {
2294 it
= nasm_regvals
[i
];
2295 ix
= nasm_reg_flags
[i
];
2301 if (b
>= EXPR_REG_START
&& b
< REG_ENUM_LIMIT
) {
2302 bt
= nasm_regvals
[b
];
2303 bx
= nasm_reg_flags
[b
];
2309 /* check for a 32/64-bit memory reference... */
2310 if ((ix
|bx
) & (BITS32
|BITS64
)) {
2311 /* it must be a 32/64-bit memory reference. Firstly we have
2312 * to check that all registers involved are type E/Rxx. */
2313 int32_t sok
= BITS32
|BITS64
;
2316 if (!(REG64
& ~ix
) || !(REG32
& ~ix
))
2324 return NULL
; /* Invalid register */
2325 if (~sok
& bx
& SIZE_MASK
)
2326 return NULL
; /* Invalid size */
2330 /* While we're here, ensure the user didn't specify
2332 if (input
->disp_size
== 16 || input
->disp_size
== 64)
2335 if (addrbits
== 16 ||
2336 (addrbits
== 32 && !(sok
& BITS32
)) ||
2337 (addrbits
== 64 && !(sok
& BITS64
)))
2340 /* now reorganize base/index */
2341 if (s
== 1 && bt
!= it
&& bt
!= -1 && it
!= -1 &&
2342 ((hb
== b
&& ht
== EAH_NOTBASE
)
2343 || (hb
== i
&& ht
== EAH_MAKEBASE
))) {
2344 /* swap if hints say so */
2345 t
= bt
, bt
= it
, it
= t
;
2346 t
= bx
, bx
= ix
, ix
= t
;
2348 if (bt
== it
) /* convert EAX+2*EAX to 3*EAX */
2349 bt
= -1, bx
= 0, s
++;
2350 if (bt
== -1 && s
== 1 && !(hb
== it
&& ht
== EAH_NOTBASE
)) {
2351 /* make single reg base, unless hint */
2352 bt
= it
, bx
= ix
, it
= -1, ix
= 0;
2354 if (((s
== 2 && it
!= REG_NUM_ESP
2355 && !(input
->eaflags
& EAF_TIMESTWO
)) || s
== 3
2356 || s
== 5 || s
== 9) && bt
== -1)
2357 bt
= it
, bx
= ix
, s
--; /* convert 3*EAX to EAX+2*EAX */
2358 if (it
== -1 && (bt
& 7) != REG_NUM_ESP
2359 && (input
->eaflags
& EAF_TIMESTWO
))
2360 it
= bt
, ix
= bx
, bt
= -1, bx
= 0, s
= 1;
2361 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2362 if (s
== 1 && it
== REG_NUM_ESP
) {
2363 /* swap ESP into base if scale is 1 */
2364 t
= it
, it
= bt
, bt
= t
;
2365 t
= ix
, ix
= bx
, bx
= t
;
2367 if (it
== REG_NUM_ESP
2368 || (s
!= 1 && s
!= 2 && s
!= 4 && s
!= 8 && it
!= -1))
2369 return NULL
; /* wrong, for various reasons */
2371 output
->rex
|= rexflags(it
, ix
, REX_X
);
2372 output
->rex
|= rexflags(bt
, bx
, REX_B
);
2374 if (it
== -1 && (bt
& 7) != REG_NUM_ESP
) {
2383 if (rm
!= REG_NUM_EBP
&& o
== 0 &&
2384 seg
== NO_SEG
&& !forw_ref
&&
2386 (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2388 else if (input
->eaflags
& EAF_BYTEOFFS
||
2389 (o
>= -128 && o
<= 127 && seg
== NO_SEG
2391 && !(input
->eaflags
& EAF_WORDOFFS
)))
2397 output
->sib_present
= false;
2398 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2399 output
->modrm
= (mod
<< 6) | ((rfield
& 7) << 3) | rm
;
2402 int mod
, scale
, index
, base
;
2422 default: /* then what the smeg is it? */
2423 return NULL
; /* panic */
2431 if (base
!= REG_NUM_EBP
&& o
== 0 &&
2432 seg
== NO_SEG
&& !forw_ref
&&
2434 (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2436 else if (input
->eaflags
& EAF_BYTEOFFS
||
2437 (o
>= -128 && o
<= 127 && seg
== NO_SEG
2439 && !(input
->eaflags
& EAF_WORDOFFS
)))
2445 output
->sib_present
= true;
2446 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2447 output
->modrm
= (mod
<< 6) | ((rfield
& 7) << 3) | 4;
2448 output
->sib
= (scale
<< 6) | (index
<< 3) | base
;
2450 } else { /* it's 16-bit */
2453 /* check for 64-bit long mode */
2457 /* check all registers are BX, BP, SI or DI */
2458 if ((b
!= -1 && b
!= R_BP
&& b
!= R_BX
&& b
!= R_SI
2459 && b
!= R_DI
) || (i
!= -1 && i
!= R_BP
&& i
!= R_BX
2460 && i
!= R_SI
&& i
!= R_DI
))
2463 /* ensure the user didn't specify DWORD/QWORD */
2464 if (input
->disp_size
== 32 || input
->disp_size
== 64)
2467 if (s
!= 1 && i
!= -1)
2468 return NULL
; /* no can do, in 16-bit EA */
2469 if (b
== -1 && i
!= -1) {
2474 if ((b
== R_SI
|| b
== R_DI
) && i
!= -1) {
2479 /* have BX/BP as base, SI/DI index */
2481 return NULL
; /* shouldn't ever happen, in theory */
2482 if (i
!= -1 && b
!= -1 &&
2483 (i
== R_BP
|| i
== R_BX
|| b
== R_SI
|| b
== R_DI
))
2484 return NULL
; /* invalid combinations */
2485 if (b
== -1) /* pure offset: handled above */
2486 return NULL
; /* so if it gets to here, panic! */
2490 switch (i
* 256 + b
) {
2491 case R_SI
* 256 + R_BX
:
2494 case R_DI
* 256 + R_BX
:
2497 case R_SI
* 256 + R_BP
:
2500 case R_DI
* 256 + R_BP
:
2518 if (rm
== -1) /* can't happen, in theory */
2519 return NULL
; /* so panic if it does */
2521 if (o
== 0 && seg
== NO_SEG
&& !forw_ref
&& rm
!= 6 &&
2522 !(input
->eaflags
& (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2524 else if (input
->eaflags
& EAF_BYTEOFFS
||
2525 (o
>= -128 && o
<= 127 && seg
== NO_SEG
2527 && !(input
->eaflags
& EAF_WORDOFFS
)))
2532 output
->sib_present
= false; /* no SIB - it's 16-bit */
2533 output
->bytes
= mod
; /* bytes of offset needed */
2534 output
->modrm
= (mod
<< 6) | ((rfield
& 7) << 3) | rm
;
2539 output
->size
= 1 + output
->sib_present
+ output
->bytes
;
2543 static void add_asp(insn
*ins
, int addrbits
)
2548 valid
= (addrbits
== 64) ? 64|32 : 32|16;
2550 switch (ins
->prefixes
[PPS_ASIZE
]) {
2561 valid
&= (addrbits
== 32) ? 16 : 32;
2567 for (j
= 0; j
< ins
->operands
; j
++) {
2568 if (!(MEMORY
& ~ins
->oprs
[j
].type
)) {
2571 /* Verify as Register */
2572 if (ins
->oprs
[j
].indexreg
< EXPR_REG_START
2573 || ins
->oprs
[j
].indexreg
>= REG_ENUM_LIMIT
)
2576 i
= nasm_reg_flags
[ins
->oprs
[j
].indexreg
];
2578 /* Verify as Register */
2579 if (ins
->oprs
[j
].basereg
< EXPR_REG_START
2580 || ins
->oprs
[j
].basereg
>= REG_ENUM_LIMIT
)
2583 b
= nasm_reg_flags
[ins
->oprs
[j
].basereg
];
2585 if (ins
->oprs
[j
].scale
== 0)
2589 int ds
= ins
->oprs
[j
].disp_size
;
2590 if ((addrbits
!= 64 && ds
> 8) ||
2591 (addrbits
== 64 && ds
== 16))
2611 if (valid
& addrbits
) {
2612 ins
->addr_size
= addrbits
;
2613 } else if (valid
& ((addrbits
== 32) ? 16 : 32)) {
2614 /* Add an address size prefix */
2615 enum prefixes pref
= (addrbits
== 32) ? P_A16
: P_A32
;
2616 ins
->prefixes
[PPS_ASIZE
] = pref
;
2617 ins
->addr_size
= (addrbits
== 32) ? 16 : 32;
2620 errfunc(ERR_NONFATAL
, "impossible combination of address sizes");
2621 ins
->addr_size
= addrbits
; /* Error recovery */
2624 defdisp
= ins
->addr_size
== 16 ? 16 : 32;
2626 for (j
= 0; j
< ins
->operands
; j
++) {
2627 if (!(MEM_OFFS
& ~ins
->oprs
[j
].type
) &&
2628 (ins
->oprs
[j
].disp_size
? ins
->oprs
[j
].disp_size
: defdisp
)
2629 != ins
->addr_size
) {
2630 /* mem_offs sizes must match the address size; if not,
2631 strip the MEM_OFFS bit and match only EA instructions */
2632 ins
->oprs
[j
].type
&= ~(MEM_OFFS
& ~MEMORY
);