?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ndisasm: handle instructions at offset zero
[nasm/autotest.git] / disasm.c
blob3b6040729d9b4d1650163dc30c6138c05d5033f3
1 /* disasm.c where all the _work_ gets done in the Netwide Disassembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the licence given in the file "Licence"
6 * distributed in the NASM archive.
7 *
8 * initial version 27/iii/95 by Simon Tatham
9 */
10
11 #include "compiler.h"
12
13 #include <stdio.h>
14 #include <string.h>
15 #include <limits.h>
16 #include <inttypes.h>
17
18 #include "nasm.h"
19 #include "disasm.h"
20 #include "sync.h"
21 #include "insns.h"
22
23 #include "names.c"
24
25 /*
26 * Flags that go into the `segment' field of `insn' structures
27 * during disassembly.
28 */
29 #define SEG_RELATIVE 1
30 #define SEG_32BIT 2
31 #define SEG_RMREG 4
32 #define SEG_DISP8 8
33 #define SEG_DISP16 16
34 #define SEG_DISP32 32
35 #define SEG_NODISP 64
36 #define SEG_SIGNED 128
37 #define SEG_64BIT 256
38
39 #include "regdis.c"
40
41 /*
42 * Prefix information
43 */
44 struct prefix_info {
45 uint8_t osize; /* Operand size */
46 uint8_t asize; /* Address size */
47 uint8_t osp; /* Operand size prefix present */
48 uint8_t asp; /* Address size prefix present */
49 uint8_t rep; /* Rep prefix present */
50 uint8_t seg; /* Segment override prefix present */
51 uint8_t lock; /* Lock prefix present */
52 uint8_t rex; /* Rex prefix present */
53 };
54
55 #define getu8(x) (*(uint8_t *)(x))
56 #if X86_MEMORY
57 /* Littleendian CPU which can handle unaligned references */
58 #define getu16(x) (*(uint16_t *)(x))
59 #define getu32(x) (*(uint32_t *)(x))
60 #define getu64(x) (*(uint64_t *)(x))
61 #else
62 static uint16_t getu16(uint8_t *data)
63 {
64 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
65 }
66 static uint32_t getu32(uint8_t *data)
67 {
68 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
69 }
70 static uint64_t getu64(uint8_t *data)
71 {
72 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
73 }
74 #endif
75
76 #define gets8(x) ((int8_t)getu8(x))
77 #define gets16(x) ((int16_t)getu16(x))
78 #define gets32(x) ((int32_t)getu32(x))
79 #define gets64(x) ((int64_t)getu64(x))
80
81 /* Important: regval must already have been adjusted for rex extensions */
82 static enum reg_enum whichreg(int32_t regflags, int regval, int rex)
83 {
84 if (!(regflags & (REGISTER|REGMEM)))
85 return 0; /* Registers not permissible?! */
86
87 regflags |= REGISTER;
88
89 if (!(REG_AL & ~regflags))
90 return R_AL;
91 if (!(REG_AX & ~regflags))
92 return R_AX;
93 if (!(REG_EAX & ~regflags))
94 return R_EAX;
95 if (!(REG_RAX & ~regflags))
96 return R_RAX;
97 if (!(REG_DL & ~regflags))
98 return R_DL;
99 if (!(REG_DX & ~regflags))
100 return R_DX;
101 if (!(REG_EDX & ~regflags))
102 return R_EDX;
103 if (!(REG_RDX & ~regflags))
104 return R_RDX;
105 if (!(REG_CL & ~regflags))
106 return R_CL;
107 if (!(REG_CX & ~regflags))
108 return R_CX;
109 if (!(REG_ECX & ~regflags))
110 return R_ECX;
111 if (!(REG_RCX & ~regflags))
112 return R_RCX;
113 if (!(FPU0 & ~regflags))
114 return R_ST0;
115 if (!(REG_CS & ~regflags))
116 return (regval == 1) ? R_CS : 0;
117 if (!(REG_DESS & ~regflags))
118 return (regval == 0 || regval == 2
119 || regval == 3 ? rd_sreg[regval] : 0);
120 if (!(REG_FSGS & ~regflags))
121 return (regval == 4 || regval == 5 ? rd_sreg[regval] : 0);
122 if (!(REG_SEG67 & ~regflags))
123 return (regval == 6 || regval == 7 ? rd_sreg[regval] : 0);
124
125 /* All the entries below look up regval in an 16-entry array */
126 if (regval < 0 || regval > 15)
127 return 0;
128
129 if (!(REG8 & ~regflags)) {
130 if (rex & REX_P)
131 return rd_reg8_rex[regval];
132 else
133 return rd_reg8[regval];
134 }
135 if (!(REG16 & ~regflags))
136 return rd_reg16[regval];
137 if (!(REG32 & ~regflags))
138 return rd_reg32[regval];
139 if (!(REG64 & ~regflags))
140 return rd_reg64[regval];
141 if (!(REG_SREG & ~regflags))
142 return rd_sreg[regval & 7]; /* Ignore REX */
143 if (!(REG_CREG & ~regflags))
144 return rd_creg[regval];
145 if (!(REG_DREG & ~regflags))
146 return rd_dreg[regval];
147 if (!(REG_TREG & ~regflags)) {
148 if (rex & REX_P)
149 return 0; /* TR registers are ill-defined with rex */
150 return rd_treg[regval];
151 }
152 if (!(FPUREG & ~regflags))
153 return rd_fpureg[regval & 7]; /* Ignore REX */
154 if (!(MMXREG & ~regflags))
155 return rd_mmxreg[regval & 7]; /* Ignore REX */
156 if (!(XMMREG & ~regflags))
157 return rd_xmmreg[regval];
158
159 return 0;
160 }
161
162 static const char *whichcond(int condval)
163 {
164 static int conds[] = {
165 C_O, C_NO, C_C, C_NC, C_Z, C_NZ, C_NA, C_A,
166 C_S, C_NS, C_PE, C_PO, C_L, C_NL, C_NG, C_G
167 };
168 return conditions[conds[condval]];
169 }
170
171 /*
172 * Process a DREX suffix
173 */
174 static uint8_t *do_drex(uint8_t *data, insn *ins)
175 {
176 uint8_t drex = *data++;
177 operand *dst = &ins->oprs[ins->drexdst];
178
179 if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
180 return NULL; /* OC0 mismatch */
181 ins->rex = (ins->rex & ~7) | (drex & 7);
182
183 dst->segment = SEG_RMREG;
184 dst->basereg = drex >> 4;
185 return data;
186 }
187
188
189 /*
190 * Process an effective address (ModRM) specification.
191 */
192 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
193 int segsize, operand * op, insn *ins)
194 {
195 int mod, rm, scale, index, base;
196 int rex;
197 uint8_t sib = 0;
198
199 mod = (modrm >> 6) & 03;
200 rm = modrm & 07;
201
202 if (mod != 3 && rm == 4 && asize != 16)
203 sib = *data++;
204
205 if (ins->rex & REX_D) {
206 data = do_drex(data, ins);
207 if (!data)
208 return NULL;
209 }
210 rex = ins->rex;
211
212 if (mod == 3) { /* pure register version */
213 op->basereg = rm+(rex & REX_B ? 8 : 0);
214 op->segment |= SEG_RMREG;
215 return data;
216 }
217
218 op->disp_size = 0;
219 op->eaflags = 0;
220
221 if (asize == 16) {
222 /*
223 * <mod> specifies the displacement size (none, byte or
224 * word), and <rm> specifies the register combination.
225 * Exception: mod=0,rm=6 does not specify [BP] as one might
226 * expect, but instead specifies [disp16].
227 */
228 op->indexreg = op->basereg = -1;
229 op->scale = 1; /* always, in 16 bits */
230 switch (rm) {
231 case 0:
232 op->basereg = R_BX;
233 op->indexreg = R_SI;
234 break;
235 case 1:
236 op->basereg = R_BX;
237 op->indexreg = R_DI;
238 break;
239 case 2:
240 op->basereg = R_BP;
241 op->indexreg = R_SI;
242 break;
243 case 3:
244 op->basereg = R_BP;
245 op->indexreg = R_DI;
246 break;
247 case 4:
248 op->basereg = R_SI;
249 break;
250 case 5:
251 op->basereg = R_DI;
252 break;
253 case 6:
254 op->basereg = R_BP;
255 break;
256 case 7:
257 op->basereg = R_BX;
258 break;
259 }
260 if (rm == 6 && mod == 0) { /* special case */
261 op->basereg = -1;
262 if (segsize != 16)
263 op->disp_size = 16;
264 mod = 2; /* fake disp16 */
265 }
266 switch (mod) {
267 case 0:
268 op->segment |= SEG_NODISP;
269 break;
270 case 1:
271 op->segment |= SEG_DISP8;
272 op->offset = (int8_t)*data++;
273 break;
274 case 2:
275 op->segment |= SEG_DISP16;
276 op->offset = *data++;
277 op->offset |= ((unsigned)*data++) << 8;
278 break;
279 }
280 return data;
281 } else {
282 /*
283 * Once again, <mod> specifies displacement size (this time
284 * none, byte or *dword*), while <rm> specifies the base
285 * register. Again, [EBP] is missing, replaced by a pure
286 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
287 * and RIP-relative addressing in 64-bit mode.
288 *
289 * However, rm=4
290 * indicates not a single base register, but instead the
291 * presence of a SIB byte...
292 */
293 int a64 = asize == 64;
294
295 op->indexreg = -1;
296
297 if (a64)
298 op->basereg = rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
299 else
300 op->basereg = rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
301
302 if (rm == 5 && mod == 0) {
303 if (segsize == 64) {
304 op->eaflags |= EAF_REL;
305 op->segment |= SEG_RELATIVE;
306 mod = 2; /* fake disp32 */
307 }
308
309 if (asize != 64)
310 op->disp_size = asize;
311
312 op->basereg = -1;
313 mod = 2; /* fake disp32 */
314 }
315
316 if (rm == 4) { /* process SIB */
317 scale = (sib >> 6) & 03;
318 index = (sib >> 3) & 07;
319 base = sib & 07;
320
321 op->scale = 1 << scale;
322
323 if (index == 4)
324 op->indexreg = -1; /* ESP/RSP/R12 cannot be an index */
325 else if (a64)
326 op->indexreg = rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
327 else
328 op->indexreg = rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
329
330 if (base == 5 && mod == 0) {
331 op->basereg = -1;
332 mod = 2; /* Fake disp32 */
333 } else if (a64)
334 op->basereg = rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
335 else
336 op->basereg = rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
337
338 if (segsize == 16)
339 op->disp_size = 32;
340 }
341
342 switch (mod) {
343 case 0:
344 op->segment |= SEG_NODISP;
345 break;
346 case 1:
347 op->segment |= SEG_DISP8;
348 op->offset = gets8(data);
349 data++;
350 break;
351 case 2:
352 op->segment |= SEG_DISP32;
353 op->offset = getu32(data);
354 data += 4;
355 break;
356 }
357 return data;
358 }
359 }
360
361 /*
362 * Determine whether the instruction template in t corresponds to the data
363 * stream in data. Return the number of bytes matched if so.
364 */
365 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
366
367 static int matches(const struct itemplate *t, uint8_t *data,
368 const struct prefix_info *prefix, int segsize, insn *ins)
369 {
370 uint8_t *r = (uint8_t *)(t->code);
371 uint8_t *origdata = data;
372 bool a_used = false, o_used = false;
373 enum prefixes drep = 0;
374 uint8_t lock = prefix->lock;
375 int osize = prefix->osize;
376 int asize = prefix->asize;
377 int i, c;
378 struct operand *opx;
379 int s_field_for = -1; /* No 144/154 series code encountered */
380
381 for (i = 0; i < MAX_OPERANDS; i++) {
382 ins->oprs[i].segment = ins->oprs[i].disp_size =
383 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
384 }
385 ins->condition = -1;
386 ins->rex = prefix->rex;
387 memset(ins->prefixes, 0, sizeof ins->prefixes);
388
389 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
390 return false;
391
392 if (prefix->rep == 0xF2)
393 drep = P_REPNE;
394 else if (prefix->rep == 0xF3)
395 drep = P_REP;
396
397 while ((c = *r++) != 0) {
398 opx = &ins->oprs[c & 3];
399
400 switch (c) {
401 case 01:
402 case 02:
403 case 03:
404 while (c--)
405 if (*r++ != *data++)
406 return false;
407 break;
408
409 case 04:
410 switch (*data++) {
411 case 0x07:
412 ins->oprs[0].basereg = 0;
413 break;
414 case 0x17:
415 ins->oprs[0].basereg = 2;
416 break;
417 case 0x1F:
418 ins->oprs[0].basereg = 3;
419 break;
420 default:
421 return false;
422 }
423 break;
424
425 case 05:
426 switch (*data++) {
427 case 0xA1:
428 ins->oprs[0].basereg = 4;
429 break;
430 case 0xA9:
431 ins->oprs[0].basereg = 5;
432 break;
433 default:
434 return false;
435 }
436 break;
437
438 case 06:
439 switch (*data++) {
440 case 0x06:
441 ins->oprs[0].basereg = 0;
442 break;
443 case 0x0E:
444 ins->oprs[0].basereg = 1;
445 break;
446 case 0x16:
447 ins->oprs[0].basereg = 2;
448 break;
449 case 0x1E:
450 ins->oprs[0].basereg = 3;
451 break;
452 default:
453 return false;
454 }
455 break;
456
457 case 07:
458 switch (*data++) {
459 case 0xA0:
460 ins->oprs[0].basereg = 4;
461 break;
462 case 0xA8:
463 ins->oprs[0].basereg = 5;
464 break;
465 default:
466 return false;
467 }
468 break;
469
470 case4(010):
471 {
472 int t = *r++, d = *data++;
473 if (d < t || d > t + 7)
474 return false;
475 else {
476 opx->basereg = (d-t)+
477 (ins->rex & REX_B ? 8 : 0);
478 opx->segment |= SEG_RMREG;
479 }
480 break;
481 }
482
483 case4(014):
484 opx->offset = (int8_t)*data++;
485 opx->segment |= SEG_SIGNED;
486 break;
487
488 case4(020):
489 opx->offset = *data++;
490 break;
491
492 case4(024):
493 opx->offset = *data++;
494 break;
495
496 case4(030):
497 opx->offset = getu16(data);
498 data += 2;
499 break;
500
501 case4(034):
502 if (osize == 32) {
503 opx->offset = getu32(data);
504 data += 4;
505 } else {
506 opx->offset = getu16(data);
507 data += 2;
508 }
509 if (segsize != asize)
510 opx->disp_size = asize;
511 break;
512
513 case4(040):
514 opx->offset = getu32(data);
515 data += 4;
516 break;
517
518 case4(044):
519 switch (asize) {
520 case 16:
521 opx->offset = getu16(data);
522 data += 2;
523 if (segsize != 16)
524 opx->disp_size = 16;
525 break;
526 case 32:
527 opx->offset = getu32(data);
528 data += 4;
529 if (segsize == 16)
530 opx->disp_size = 32;
531 break;
532 case 64:
533 opx->offset = getu64(data);
534 opx->disp_size = 64;
535 data += 8;
536 break;
537 }
538 break;
539
540 case4(050):
541 opx->offset = gets8(data++);
542 opx->segment |= SEG_RELATIVE;
543 break;
544
545 case4(054):
546 opx->offset = getu64(data);
547 data += 8;
548 break;
549
550 case4(060):
551 opx->offset = gets16(data);
552 data += 2;
553 opx->segment |= SEG_RELATIVE;
554 opx->segment &= ~SEG_32BIT;
555 break;
556
557 case4(064):
558 opx->segment |= SEG_RELATIVE;
559 if (osize == 16) {
560 opx->offset = getu16(data);
561 data += 2;
562 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
563 } else if (osize == 32) {
564 opx->offset = getu32(data);
565 data += 4;
566 opx->segment &= ~SEG_64BIT;
567 opx->segment |= SEG_32BIT;
568 }
569 if (segsize != osize) {
570 opx->type =
571 (opx->type & ~SIZE_MASK)
572 | ((osize == 16) ? BITS16 : BITS32);
573 }
574 break;
575
576 case4(070):
577 opx->offset = getu32(data);
578 data += 4;
579 opx->segment |= SEG_32BIT | SEG_RELATIVE;
580 break;
581
582 case4(0100):
583 case4(0110):
584 case4(0120):
585 case4(0130):
586 {
587 int modrm = *data++;
588 opx->segment |= SEG_RMREG;
589 data = do_ea(data, modrm, asize, segsize,
590 &ins->oprs[(c >> 3) & 3], ins);
591 if (!data)
592 return false;
593 opx->basereg = ((modrm >> 3)&7)+
594 (ins->rex & REX_R ? 8 : 0);
595 break;
596 }
597
598 case4(0140):
599 if (s_field_for == (c & 3)) {
600 opx->offset = gets8(data);
601 data++;
602 } else {
603 opx->offset = getu16(data);
604 data += 2;
605 }
606 break;
607
608 case4(0144):
609 case4(0154):
610 s_field_for = (*data & 0x02) ? c & 3 : -1;
611 if ((*data++ & ~0x02) != *r++)
612 return false;
613 break;
614
615 case4(0150):
616 if (s_field_for == (c & 3)) {
617 opx->offset = gets8(data);
618 data++;
619 } else {
620 opx->offset = getu32(data);
621 data += 4;
622 }
623 break;
624
625 case4(0160):
626 ins->rex |= REX_D;
627 ins->drexdst = c & 3;
628 break;
629
630 case4(0164):
631 ins->rex |= REX_D|REX_OC;
632 ins->drexdst = c & 3;
633 break;
634
635 case 0170:
636 if (*data++)
637 return false;
638 break;
639
640 case 0171:
641 data = do_drex(data, ins);
642 if (!data)
643 return false;
644 break;
645
646 case4(0200):
647 case4(0204):
648 case4(0210):
649 case4(0214):
650 case4(0220):
651 case4(0224):
652 case4(0230):
653 case4(0234):
654 {
655 int modrm = *data++;
656 if (((modrm >> 3) & 07) != (c & 07))
657 return false; /* spare field doesn't match up */
658 data = do_ea(data, modrm, asize, segsize,
659 &ins->oprs[(c >> 3) & 07], ins);
660 if (!data)
661 return false;
662 break;
663 }
664
665 case 0310:
666 if (asize != 16)
667 return false;
668 else
669 a_used = true;
670 break;
671
672 case 0311:
673 if (asize == 16)
674 return false;
675 else
676 a_used = true;
677 break;
678
679 case 0312:
680 if (asize != segsize)
681 return false;
682 else
683 a_used = true;
684 break;
685
686 case 0313:
687 if (asize != 64)
688 return false;
689 else
690 a_used = true;
691 break;
692
693 case 0314:
694 if (prefix->rex & REX_B)
695 return false;
696 break;
697
698 case 0315:
699 if (prefix->rex & REX_X)
700 return false;
701 break;
702
703 case 0316:
704 if (prefix->rex & REX_R)
705 return false;
706 break;
707
708 case 0317:
709 if (prefix->rex & REX_W)
710 return false;
711 break;
712
713 case 0320:
714 if (osize != 16)
715 return false;
716 else
717 o_used = true;
718 break;
719
720 case 0321:
721 if (osize != 32)
722 return false;
723 else
724 o_used = true;
725 break;
726
727 case 0322:
728 if (osize != (segsize == 16) ? 16 : 32)
729 return false;
730 else
731 o_used = true;
732 break;
733
734 case 0323:
735 ins->rex |= REX_W; /* 64-bit only instruction */
736 osize = 64;
737 o_used = true;
738 break;
739
740 case 0324:
741 if (!(ins->rex & (REX_P|REX_W)) || osize != 64)
742 return false;
743 o_used = true;
744 break;
745
746 case 0330:
747 {
748 int t = *r++, d = *data++;
749 if (d < t || d > t + 15)
750 return false;
751 else
752 ins->condition = d - t;
753 break;
754 }
755
756 case 0331:
757 if (prefix->rep)
758 return false;
759 break;
760
761 case 0332:
762 if (prefix->rep != 0xF2)
763 return false;
764 drep = 0;
765 break;
766
767 case 0333:
768 if (prefix->rep != 0xF3)
769 return false;
770 drep = 0;
771 break;
772
773 case 0334:
774 if (lock) {
775 ins->rex |= REX_R;
776 lock = 0;
777 }
778 break;
779
780 case 0335:
781 if (drep == P_REP)
782 drep = P_REPE;
783 break;
784
785 case 0340:
786 return false;
787
788 case 0364:
789 if (prefix->osp)
790 return false;
791 break;
792
793 case 0365:
794 if (prefix->asp)
795 return false;
796 break;
797
798 case 0366:
799 if (!prefix->osp)
800 return false;
801 o_used = true;
802 break;
803
804 case 0367:
805 if (!prefix->asp)
806 return false;
807 a_used = true;
808 break;
809
810 default:
811 return false; /* Unknown code */
812 }
813 }
814
815 /* REX cannot be combined with DREX */
816 if ((ins->rex & REX_D) && (prefix->rex))
817 return false;
818
819 /*
820 * Check for unused rep or a/o prefixes.
821 */
822 for (i = 0; i < t->operands; i++) {
823 if (ins->oprs[i].segment != SEG_RMREG)
824 a_used = true;
825 }
826
827 if (lock) {
828 if (ins->prefixes[PPS_LREP])
829 return false;
830 ins->prefixes[PPS_LREP] = P_LOCK;
831 }
832 if (drep) {
833 if (ins->prefixes[PPS_LREP])
834 return false;
835 ins->prefixes[PPS_LREP] = drep;
836 }
837 if (!o_used) {
838 if (osize != ((segsize == 16) ? 16 : 32)) {
839 enum prefixes pfx = 0;
840
841 switch (osize) {
842 case 16:
843 pfx = P_O16;
844 break;
845 case 32:
846 pfx = P_O32;
847 break;
848 case 64:
849 pfx = P_O64;
850 break;
851 }
852
853 if (ins->prefixes[PPS_OSIZE])
854 return false;
855 ins->prefixes[PPS_OSIZE] = pfx;
856 }
857 }
858 if (!a_used && asize != segsize) {
859 if (ins->prefixes[PPS_ASIZE])
860 return false;
861 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
862 }
863
864 /* Fix: check for redundant REX prefixes */
865
866 return data - origdata;
867 }
868
869 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
870 int32_t offset, int autosync, uint32_t prefer)
871 {
872 const struct itemplate * const *p, * const *best_p;
873 const struct disasm_index *ix;
874 uint8_t *dp;
875 int length, best_length = 0;
876 char *segover;
877 int i, slen, colon, n;
878 uint8_t *origdata;
879 int works;
880 insn tmp_ins, ins;
881 uint32_t goodness, best;
882 int best_pref;
883 struct prefix_info prefix;
884 bool end_prefix;
885
886 memset(&ins, 0, sizeof ins);
887
888 /*
889 * Scan for prefixes.
890 */
891 memset(&prefix, 0, sizeof prefix);
892 prefix.asize = segsize;
893 prefix.osize = (segsize == 64) ? 32 : segsize;
894 segover = NULL;
895 origdata = data;
896
897 for (end_prefix = false; !end_prefix; ) {
898 switch (*data) {
899 case 0xF2:
900 case 0xF3:
901 prefix.rep = *data++;
902 break;
903 case 0xF0:
904 prefix.lock = *data++;
905 break;
906 case 0x2E:
907 segover = "cs", prefix.seg = *data++;
908 break;
909 case 0x36:
910 segover = "ss", prefix.seg = *data++;
911 break;
912 case 0x3E:
913 segover = "ds", prefix.seg = *data++;
914 break;
915 case 0x26:
916 segover = "es", prefix.seg = *data++;
917 break;
918 case 0x64:
919 segover = "fs", prefix.seg = *data++;
920 break;
921 case 0x65:
922 segover = "gs", prefix.seg = *data++;
923 break;
924 case 0x66:
925 prefix.osize = (segsize == 16) ? 32 : 16;
926 prefix.osp = *data++;
927 break;
928 case 0x67:
929 prefix.asize = (segsize == 32) ? 16 : 32;
930 prefix.asp = *data++;
931 break;
932 default:
933 if (segsize == 64 && (*data & 0xf0) == REX_P) {
934 prefix.rex = *data++;
935 if (prefix.rex & REX_W)
936 prefix.osize = 64;
937 end_prefix = true;
938 } else {
939 end_prefix = true;
940 }
941 }
942 }
943
944 best = -1; /* Worst possible */
945 best_p = NULL;
946 best_pref = INT_MAX;
947
948 dp = data;
949 ix = itable + *dp++;
950 while (ix->n == -1) {
951 ix = (const struct disasm_index *)ix->p + *dp++;
952 }
953
954 p = (const struct itemplate * const *)ix->p;
955 for (n = ix->n; n; n--, p++) {
956 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
957 works = true;
958 /*
959 * Final check to make sure the types of r/m match up.
960 * XXX: Need to make sure this is actually correct.
961 */
962 for (i = 0; i < (*p)->operands; i++) {
963 if (!((*p)->opd[i] & SAME_AS) &&
964 (
965 /* If it's a mem-only EA but we have a
966 register, die. */
967 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
968 !(MEMORY & ~(*p)->opd[i])) ||
969 /* If it's a reg-only EA but we have a memory
970 ref, die. */
971 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
972 !(REG_EA & ~(*p)->opd[i]) &&
973 !((*p)->opd[i] & REG_SMASK)) ||
974 /* Register type mismatch (eg FS vs REG_DESS):
975 die. */
976 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
977 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
978 !whichreg((*p)->opd[i],
979 tmp_ins.oprs[i].basereg, tmp_ins.rex))
980 )) {
981 works = false;
982 break;
983 }
984 }
985
986 /*
987 * Note: we always prefer instructions which incorporate
988 * prefixes in the instructions themselves. This is to allow
989 * e.g. PAUSE to be preferred to REP NOP, and deal with
990 * MMX/SSE instructions where prefixes are used to select
991 * between MMX and SSE register sets or outright opcode
992 * selection.
993 */
994 if (works) {
995 int i, nprefix;
996 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
997 nprefix = 0;
998 for (i = 0; i < MAXPREFIX; i++)
999 if (tmp_ins.prefixes[i])
1000 nprefix++;
1001 if (nprefix < best_pref ||
1002 (nprefix == best_pref && goodness < best)) {
1003 /* This is the best one found so far */
1004 best = goodness;
1005 best_p = p;
1006 best_pref = nprefix;
1007 best_length = length;
1008 ins = tmp_ins;
1009 }
1010 }
1011 }
1012 }
1013
1014 if (!best_p)
1015 return 0; /* no instruction was matched */
1016
1017 /* Pick the best match */
1018 p = best_p;
1019 length = best_length;
1020
1021 slen = 0;
1022
1023 /* TODO: snprintf returns the value that the string would have if
1024 * the buffer were long enough, and not the actual length of
1025 * the returned string, so each instance of using the return
1026 * value of snprintf should actually be checked to assure that
1027 * the return value is "sane." Maybe a macro wrapper could
1028 * be used for that purpose.
1029 */
1030 for (i = 0; i < MAXPREFIX; i++)
1031 switch (ins.prefixes[i]) {
1032 case P_LOCK:
1033 slen += snprintf(output + slen, outbufsize - slen, "lock ");
1034 break;
1035 case P_REP:
1036 slen += snprintf(output + slen, outbufsize - slen, "rep ");
1037 break;
1038 case P_REPE:
1039 slen += snprintf(output + slen, outbufsize - slen, "repe ");
1040 break;
1041 case P_REPNE:
1042 slen += snprintf(output + slen, outbufsize - slen, "repne ");
1043 break;
1044 case P_A16:
1045 slen += snprintf(output + slen, outbufsize - slen, "a16 ");
1046 break;
1047 case P_A32:
1048 slen += snprintf(output + slen, outbufsize - slen, "a32 ");
1049 break;
1050 case P_A64:
1051 slen += snprintf(output + slen, outbufsize - slen, "a64 ");
1052 break;
1053 case P_O16:
1054 slen += snprintf(output + slen, outbufsize - slen, "o16 ");
1055 break;
1056 case P_O32:
1057 slen += snprintf(output + slen, outbufsize - slen, "o32 ");
1058 break;
1059 case P_O64:
1060 slen += snprintf(output + slen, outbufsize - slen, "o64 ");
1061 break;
1062 default:
1063 break;
1064 }
1065
1066 for (i = 0; i < (int)elements(ico); i++)
1067 if ((*p)->opcode == ico[i]) {
1068 slen +=
1069 snprintf(output + slen, outbufsize - slen, "%s%s", icn[i],
1070 whichcond(ins.condition));
1071 break;
1072 }
1073 if (i >= (int)elements(ico))
1074 slen +=
1075 snprintf(output + slen, outbufsize - slen, "%s",
1076 insn_names[(*p)->opcode]);
1077 colon = false;
1078 length += data - origdata; /* fix up for prefixes */
1079 for (i = 0; i < (*p)->operands; i++) {
1080 opflags_t t = (*p)->opd[i];
1081 const operand *o = &ins.oprs[i];
1082 int64_t offs;
1083
1084 if (t & SAME_AS) {
1085 o = &ins.oprs[t & ~SAME_AS];
1086 t = (*p)->opd[t & ~SAME_AS];
1087 }
1088
1089 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1090
1091 offs = o->offset;
1092 if (o->segment & SEG_RELATIVE) {
1093 offs += offset + length;
1094 /*
1095 * sort out wraparound
1096 */
1097 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1098 offs &= 0xffff;
1099 /*
1100 * add sync marker, if autosync is on
1101 */
1102 if (autosync)
1103 add_sync(offs, 0L);
1104 }
1105
1106 if (t & COLON)
1107 colon = true;
1108 else
1109 colon = false;
1110
1111 if ((t & (REGISTER | FPUREG)) ||
1112 (o->segment & SEG_RMREG)) {
1113 enum reg_enum reg;
1114 reg = whichreg(t, o->basereg, ins.rex);
1115 if (t & TO)
1116 slen += snprintf(output + slen, outbufsize - slen, "to ");
1117 slen += snprintf(output + slen, outbufsize - slen, "%s",
1118 reg_names[reg - EXPR_REG_START]);
1119 } else if (!(UNITY & ~t)) {
1120 output[slen++] = '1';
1121 } else if (t & IMMEDIATE) {
1122 if (t & BITS8) {
1123 slen +=
1124 snprintf(output + slen, outbufsize - slen, "byte ");
1125 if (o->segment & SEG_SIGNED) {
1126 if (offs < 0) {
1127 offs *= -1;
1128 output[slen++] = '-';
1129 } else
1130 output[slen++] = '+';
1131 }
1132 } else if (t & BITS16) {
1133 slen +=
1134 snprintf(output + slen, outbufsize - slen, "word ");
1135 } else if (t & BITS32) {
1136 slen +=
1137 snprintf(output + slen, outbufsize - slen, "dword ");
1138 } else if (t & BITS64) {
1139 slen +=
1140 snprintf(output + slen, outbufsize - slen, "qword ");
1141 } else if (t & NEAR) {
1142 slen +=
1143 snprintf(output + slen, outbufsize - slen, "near ");
1144 } else if (t & SHORT) {
1145 slen +=
1146 snprintf(output + slen, outbufsize - slen, "short ");
1147 }
1148 slen +=
1149 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1150 offs);
1151 } else if (!(MEM_OFFS & ~t)) {
1152 slen +=
1153 snprintf(output + slen, outbufsize - slen,
1154 "[%s%s%s0x%"PRIx64"]",
1155 (segover ? segover : ""),
1156 (segover ? ":" : ""),
1157 (o->disp_size == 64 ? "qword " :
1158 o->disp_size == 32 ? "dword " :
1159 o->disp_size == 16 ? "word " : ""), offs);
1160 segover = NULL;
1161 } else if (!(REGMEM & ~t)) {
1162 int started = false;
1163 if (t & BITS8)
1164 slen +=
1165 snprintf(output + slen, outbufsize - slen, "byte ");
1166 if (t & BITS16)
1167 slen +=
1168 snprintf(output + slen, outbufsize - slen, "word ");
1169 if (t & BITS32)
1170 slen +=
1171 snprintf(output + slen, outbufsize - slen, "dword ");
1172 if (t & BITS64)
1173 slen +=
1174 snprintf(output + slen, outbufsize - slen, "qword ");
1175 if (t & BITS80)
1176 slen +=
1177 snprintf(output + slen, outbufsize - slen, "tword ");
1178 if (t & BITS128)
1179 slen +=
1180 snprintf(output + slen, outbufsize - slen, "oword ");
1181 if (t & FAR)
1182 slen += snprintf(output + slen, outbufsize - slen, "far ");
1183 if (t & NEAR)
1184 slen +=
1185 snprintf(output + slen, outbufsize - slen, "near ");
1186 output[slen++] = '[';
1187 if (o->disp_size)
1188 slen += snprintf(output + slen, outbufsize - slen, "%s",
1189 (o->disp_size == 64 ? "qword " :
1190 o->disp_size == 32 ? "dword " :
1191 o->disp_size == 16 ? "word " :
1192 ""));
1193 if (o->eaflags & EAF_REL)
1194 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1195 if (segover) {
1196 slen +=
1197 snprintf(output + slen, outbufsize - slen, "%s:",
1198 segover);
1199 segover = NULL;
1200 }
1201 if (o->basereg != -1) {
1202 slen += snprintf(output + slen, outbufsize - slen, "%s",
1203 reg_names[(o->basereg -
1204 EXPR_REG_START)]);
1205 started = true;
1206 }
1207 if (o->indexreg != -1) {
1208 if (started)
1209 output[slen++] = '+';
1210 slen += snprintf(output + slen, outbufsize - slen, "%s",
1211 reg_names[(o->indexreg -
1212 EXPR_REG_START)]);
1213 if (o->scale > 1)
1214 slen +=
1215 snprintf(output + slen, outbufsize - slen, "*%d",
1216 o->scale);
1217 started = true;
1218 }
1219
1220
1221 if (o->segment & SEG_DISP8) {
1222 const char *prefix;
1223 uint8_t offset = offs;
1224 if ((int8_t)offset < 0) {
1225 prefix = "-";
1226 offset = -offset;
1227 } else {
1228 prefix = "+";
1229 }
1230 slen +=
1231 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1232 prefix, offset);
1233 } else if (o->segment & SEG_DISP16) {
1234 const char *prefix;
1235 uint16_t offset = offs;
1236 if ((int16_t)offset < 0 && started) {
1237 offset = -offset;
1238 prefix = "-";
1239 } else {
1240 prefix = started ? "+" : "";
1241 }
1242 slen +=
1243 snprintf(output + slen, outbufsize - slen,
1244 "%s0x%"PRIx16"", prefix, offset);
1245 } else if (o->segment & SEG_DISP32) {
1246 if (prefix.asize == 64) {
1247 const char *prefix;
1248 uint64_t offset = (int64_t)(int32_t)offs;
1249 if ((int32_t)offs < 0 && started) {
1250 offset = -offset;
1251 prefix = "-";
1252 } else {
1253 prefix = started ? "+" : "";
1254 }
1255 slen +=
1256 snprintf(output + slen, outbufsize - slen,
1257 "%s0x%"PRIx64"", prefix, offset);
1258 } else {
1259 const char *prefix;
1260 uint32_t offset = offs;
1261 if ((int32_t) offset < 0 && started) {
1262 offset = -offset;
1263 prefix = "-";
1264 } else {
1265 prefix = started ? "+" : "";
1266 }
1267 slen +=
1268 snprintf(output + slen, outbufsize - slen,
1269 "%s0x%"PRIx32"", prefix, offset);
1270 }
1271 }
1272 output[slen++] = ']';
1273 } else {
1274 slen +=
1275 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1276 i);
1277 }
1278 }
1279 output[slen] = '\0';
1280 if (segover) { /* unused segment override */
1281 char *p = output;
1282 int count = slen + 1;
1283 while (count--)
1284 p[count + 3] = p[count];
1285 strncpy(output, segover, 2);
1286 output[2] = ' ';
1287 }
1288 return length;
1289 }
1290
1291 int32_t eatbyte(uint8_t *data, char *output, int outbufsize)
1292 {
1293 snprintf(output, outbufsize, "db 0x%02X", *data);
1294 return 1;
1295 }
Automatic testing