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insns.pl: support operands that serve double duty
[nasm/autotest.git] / disasm.c
blob711304c03801ef1a1663d1d97926a279cb265280
1 /* disasm.c where all the _work_ gets done in the Netwide Disassembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
7 *
8 * initial version 27/iii/95 by Simon Tatham
9 */
10
11 #include "compiler.h"
12
13 #include <stdio.h>
14 #include <string.h>
15 #include <limits.h>
16 #include <inttypes.h>
17
18 #include "nasm.h"
19 #include "disasm.h"
20 #include "sync.h"
21 #include "insns.h"
22
23 #include "names.c"
24
25 /*
26 * Flags that go into the `segment' field of `insn' structures
27 * during disassembly.
28 */
29 #define SEG_RELATIVE 1
30 #define SEG_32BIT 2
31 #define SEG_RMREG 4
32 #define SEG_DISP8 8
33 #define SEG_DISP16 16
34 #define SEG_DISP32 32
35 #define SEG_NODISP 64
36 #define SEG_SIGNED 128
37 #define SEG_64BIT 256
38
39 #include "regdis.c"
40
41 /*
42 * Prefix information
43 */
44 struct prefix_info {
45 uint8_t osize; /* Operand size */
46 uint8_t asize; /* Address size */
47 uint8_t osp; /* Operand size prefix present */
48 uint8_t asp; /* Address size prefix present */
49 uint8_t rep; /* Rep prefix present */
50 uint8_t seg; /* Segment override prefix present */
51 uint8_t lock; /* Lock prefix present */
52 uint8_t vex[3]; /* VEX prefix present */
53 uint8_t vex_m; /* VEX.M field */
54 uint8_t vex_v;
55 uint8_t vex_lp; /* VEX.LP fields */
56 uint32_t rex; /* REX prefix present */
57 };
58
59 #define getu8(x) (*(uint8_t *)(x))
60 #if X86_MEMORY
61 /* Littleendian CPU which can handle unaligned references */
62 #define getu16(x) (*(uint16_t *)(x))
63 #define getu32(x) (*(uint32_t *)(x))
64 #define getu64(x) (*(uint64_t *)(x))
65 #else
66 static uint16_t getu16(uint8_t *data)
67 {
68 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
69 }
70 static uint32_t getu32(uint8_t *data)
71 {
72 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
73 }
74 static uint64_t getu64(uint8_t *data)
75 {
76 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
77 }
78 #endif
79
80 #define gets8(x) ((int8_t)getu8(x))
81 #define gets16(x) ((int16_t)getu16(x))
82 #define gets32(x) ((int32_t)getu32(x))
83 #define gets64(x) ((int64_t)getu64(x))
84
85 /* Important: regval must already have been adjusted for rex extensions */
86 static enum reg_enum whichreg(int32_t regflags, int regval, int rex)
87 {
88 if (!(regflags & (REGISTER|REGMEM)))
89 return 0; /* Registers not permissible?! */
90
91 regflags |= REGISTER;
92
93 if (!(REG_AL & ~regflags))
94 return R_AL;
95 if (!(REG_AX & ~regflags))
96 return R_AX;
97 if (!(REG_EAX & ~regflags))
98 return R_EAX;
99 if (!(REG_RAX & ~regflags))
100 return R_RAX;
101 if (!(REG_DL & ~regflags))
102 return R_DL;
103 if (!(REG_DX & ~regflags))
104 return R_DX;
105 if (!(REG_EDX & ~regflags))
106 return R_EDX;
107 if (!(REG_RDX & ~regflags))
108 return R_RDX;
109 if (!(REG_CL & ~regflags))
110 return R_CL;
111 if (!(REG_CX & ~regflags))
112 return R_CX;
113 if (!(REG_ECX & ~regflags))
114 return R_ECX;
115 if (!(REG_RCX & ~regflags))
116 return R_RCX;
117 if (!(FPU0 & ~regflags))
118 return R_ST0;
119 if (!(REG_CS & ~regflags))
120 return (regval == 1) ? R_CS : 0;
121 if (!(REG_DESS & ~regflags))
122 return (regval == 0 || regval == 2
123 || regval == 3 ? rd_sreg[regval] : 0);
124 if (!(REG_FSGS & ~regflags))
125 return (regval == 4 || regval == 5 ? rd_sreg[regval] : 0);
126 if (!(REG_SEG67 & ~regflags))
127 return (regval == 6 || regval == 7 ? rd_sreg[regval] : 0);
128
129 /* All the entries below look up regval in an 16-entry array */
130 if (regval < 0 || regval > 15)
131 return 0;
132
133 if (!(REG8 & ~regflags)) {
134 if (rex & REX_P)
135 return rd_reg8_rex[regval];
136 else
137 return rd_reg8[regval];
138 }
139 if (!(REG16 & ~regflags))
140 return rd_reg16[regval];
141 if (!(REG32 & ~regflags))
142 return rd_reg32[regval];
143 if (!(REG64 & ~regflags))
144 return rd_reg64[regval];
145 if (!(REG_SREG & ~regflags))
146 return rd_sreg[regval & 7]; /* Ignore REX */
147 if (!(REG_CREG & ~regflags))
148 return rd_creg[regval];
149 if (!(REG_DREG & ~regflags))
150 return rd_dreg[regval];
151 if (!(REG_TREG & ~regflags)) {
152 if (rex & REX_P)
153 return 0; /* TR registers are ill-defined with rex */
154 return rd_treg[regval];
155 }
156 if (!(FPUREG & ~regflags))
157 return rd_fpureg[regval & 7]; /* Ignore REX */
158 if (!(MMXREG & ~regflags))
159 return rd_mmxreg[regval & 7]; /* Ignore REX */
160 if (!(XMMREG & ~regflags))
161 return rd_xmmreg[regval];
162 if (!(YMMREG & ~regflags))
163 return rd_ymmreg[regval];
164
165 return 0;
166 }
167
168 static const char *whichcond(int condval)
169 {
170 static int conds[] = {
171 C_O, C_NO, C_C, C_NC, C_Z, C_NZ, C_NA, C_A,
172 C_S, C_NS, C_PE, C_PO, C_L, C_NL, C_NG, C_G
173 };
174 return conditions[conds[condval]];
175 }
176
177 /*
178 * Process a DREX suffix
179 */
180 static uint8_t *do_drex(uint8_t *data, insn *ins)
181 {
182 uint8_t drex = *data++;
183 operand *dst = &ins->oprs[ins->drexdst];
184
185 if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
186 return NULL; /* OC0 mismatch */
187 ins->rex = (ins->rex & ~7) | (drex & 7);
188
189 dst->segment = SEG_RMREG;
190 dst->basereg = drex >> 4;
191 return data;
192 }
193
194
195 /*
196 * Process an effective address (ModRM) specification.
197 */
198 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
199 int segsize, operand * op, insn *ins)
200 {
201 int mod, rm, scale, index, base;
202 int rex;
203 uint8_t sib = 0;
204
205 mod = (modrm >> 6) & 03;
206 rm = modrm & 07;
207
208 if (mod != 3 && rm == 4 && asize != 16)
209 sib = *data++;
210
211 if (ins->rex & REX_D) {
212 data = do_drex(data, ins);
213 if (!data)
214 return NULL;
215 }
216 rex = ins->rex;
217
218 if (mod == 3) { /* pure register version */
219 op->basereg = rm+(rex & REX_B ? 8 : 0);
220 op->segment |= SEG_RMREG;
221 return data;
222 }
223
224 op->disp_size = 0;
225 op->eaflags = 0;
226
227 if (asize == 16) {
228 /*
229 * <mod> specifies the displacement size (none, byte or
230 * word), and <rm> specifies the register combination.
231 * Exception: mod=0,rm=6 does not specify [BP] as one might
232 * expect, but instead specifies [disp16].
233 */
234 op->indexreg = op->basereg = -1;
235 op->scale = 1; /* always, in 16 bits */
236 switch (rm) {
237 case 0:
238 op->basereg = R_BX;
239 op->indexreg = R_SI;
240 break;
241 case 1:
242 op->basereg = R_BX;
243 op->indexreg = R_DI;
244 break;
245 case 2:
246 op->basereg = R_BP;
247 op->indexreg = R_SI;
248 break;
249 case 3:
250 op->basereg = R_BP;
251 op->indexreg = R_DI;
252 break;
253 case 4:
254 op->basereg = R_SI;
255 break;
256 case 5:
257 op->basereg = R_DI;
258 break;
259 case 6:
260 op->basereg = R_BP;
261 break;
262 case 7:
263 op->basereg = R_BX;
264 break;
265 }
266 if (rm == 6 && mod == 0) { /* special case */
267 op->basereg = -1;
268 if (segsize != 16)
269 op->disp_size = 16;
270 mod = 2; /* fake disp16 */
271 }
272 switch (mod) {
273 case 0:
274 op->segment |= SEG_NODISP;
275 break;
276 case 1:
277 op->segment |= SEG_DISP8;
278 op->offset = (int8_t)*data++;
279 break;
280 case 2:
281 op->segment |= SEG_DISP16;
282 op->offset = *data++;
283 op->offset |= ((unsigned)*data++) << 8;
284 break;
285 }
286 return data;
287 } else {
288 /*
289 * Once again, <mod> specifies displacement size (this time
290 * none, byte or *dword*), while <rm> specifies the base
291 * register. Again, [EBP] is missing, replaced by a pure
292 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
293 * and RIP-relative addressing in 64-bit mode.
294 *
295 * However, rm=4
296 * indicates not a single base register, but instead the
297 * presence of a SIB byte...
298 */
299 int a64 = asize == 64;
300
301 op->indexreg = -1;
302
303 if (a64)
304 op->basereg = rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
305 else
306 op->basereg = rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
307
308 if (rm == 5 && mod == 0) {
309 if (segsize == 64) {
310 op->eaflags |= EAF_REL;
311 op->segment |= SEG_RELATIVE;
312 mod = 2; /* fake disp32 */
313 }
314
315 if (asize != 64)
316 op->disp_size = asize;
317
318 op->basereg = -1;
319 mod = 2; /* fake disp32 */
320 }
321
322 if (rm == 4) { /* process SIB */
323 scale = (sib >> 6) & 03;
324 index = (sib >> 3) & 07;
325 base = sib & 07;
326
327 op->scale = 1 << scale;
328
329 if (index == 4)
330 op->indexreg = -1; /* ESP/RSP/R12 cannot be an index */
331 else if (a64)
332 op->indexreg = rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
333 else
334 op->indexreg = rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
335
336 if (base == 5 && mod == 0) {
337 op->basereg = -1;
338 mod = 2; /* Fake disp32 */
339 } else if (a64)
340 op->basereg = rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
341 else
342 op->basereg = rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
343
344 if (segsize == 16)
345 op->disp_size = 32;
346 }
347
348 switch (mod) {
349 case 0:
350 op->segment |= SEG_NODISP;
351 break;
352 case 1:
353 op->segment |= SEG_DISP8;
354 op->offset = gets8(data);
355 data++;
356 break;
357 case 2:
358 op->segment |= SEG_DISP32;
359 op->offset = gets32(data);
360 data += 4;
361 break;
362 }
363 return data;
364 }
365 }
366
367 /*
368 * Determine whether the instruction template in t corresponds to the data
369 * stream in data. Return the number of bytes matched if so.
370 */
371 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
372
373 static int matches(const struct itemplate *t, uint8_t *data,
374 const struct prefix_info *prefix, int segsize, insn *ins)
375 {
376 uint8_t *r = (uint8_t *)(t->code);
377 uint8_t *origdata = data;
378 bool a_used = false, o_used = false;
379 enum prefixes drep = 0;
380 uint8_t lock = prefix->lock;
381 int osize = prefix->osize;
382 int asize = prefix->asize;
383 int i, c;
384 struct operand *opx;
385 int s_field_for = -1; /* No 144/154 series code encountered */
386
387 for (i = 0; i < MAX_OPERANDS; i++) {
388 ins->oprs[i].segment = ins->oprs[i].disp_size =
389 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
390 }
391 ins->condition = -1;
392 ins->rex = prefix->rex;
393 memset(ins->prefixes, 0, sizeof ins->prefixes);
394
395 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
396 return false;
397
398 if (prefix->rep == 0xF2)
399 drep = P_REPNE;
400 else if (prefix->rep == 0xF3)
401 drep = P_REP;
402
403 while ((c = *r++) != 0) {
404 opx = &ins->oprs[c & 3];
405
406 switch (c) {
407 case 01:
408 case 02:
409 case 03:
410 while (c--)
411 if (*r++ != *data++)
412 return false;
413 break;
414
415 case 04:
416 switch (*data++) {
417 case 0x07:
418 ins->oprs[0].basereg = 0;
419 break;
420 case 0x17:
421 ins->oprs[0].basereg = 2;
422 break;
423 case 0x1F:
424 ins->oprs[0].basereg = 3;
425 break;
426 default:
427 return false;
428 }
429 break;
430
431 case 05:
432 switch (*data++) {
433 case 0xA1:
434 ins->oprs[0].basereg = 4;
435 break;
436 case 0xA9:
437 ins->oprs[0].basereg = 5;
438 break;
439 default:
440 return false;
441 }
442 break;
443
444 case 06:
445 switch (*data++) {
446 case 0x06:
447 ins->oprs[0].basereg = 0;
448 break;
449 case 0x0E:
450 ins->oprs[0].basereg = 1;
451 break;
452 case 0x16:
453 ins->oprs[0].basereg = 2;
454 break;
455 case 0x1E:
456 ins->oprs[0].basereg = 3;
457 break;
458 default:
459 return false;
460 }
461 break;
462
463 case 07:
464 switch (*data++) {
465 case 0xA0:
466 ins->oprs[0].basereg = 4;
467 break;
468 case 0xA8:
469 ins->oprs[0].basereg = 5;
470 break;
471 default:
472 return false;
473 }
474 break;
475
476 case4(010):
477 {
478 int t = *r++, d = *data++;
479 if (d < t || d > t + 7)
480 return false;
481 else {
482 opx->basereg = (d-t)+
483 (ins->rex & REX_B ? 8 : 0);
484 opx->segment |= SEG_RMREG;
485 }
486 break;
487 }
488
489 case4(014):
490 opx->offset = (int8_t)*data++;
491 opx->segment |= SEG_SIGNED;
492 break;
493
494 case4(020):
495 opx->offset = *data++;
496 break;
497
498 case4(024):
499 opx->offset = *data++;
500 break;
501
502 case4(030):
503 opx->offset = getu16(data);
504 data += 2;
505 break;
506
507 case4(034):
508 if (osize == 32) {
509 opx->offset = getu32(data);
510 data += 4;
511 } else {
512 opx->offset = getu16(data);
513 data += 2;
514 }
515 if (segsize != asize)
516 opx->disp_size = asize;
517 break;
518
519 case4(040):
520 opx->offset = getu32(data);
521 data += 4;
522 break;
523
524 case4(044):
525 switch (asize) {
526 case 16:
527 opx->offset = getu16(data);
528 data += 2;
529 if (segsize != 16)
530 opx->disp_size = 16;
531 break;
532 case 32:
533 opx->offset = getu32(data);
534 data += 4;
535 if (segsize == 16)
536 opx->disp_size = 32;
537 break;
538 case 64:
539 opx->offset = getu64(data);
540 opx->disp_size = 64;
541 data += 8;
542 break;
543 }
544 break;
545
546 case4(050):
547 opx->offset = gets8(data++);
548 opx->segment |= SEG_RELATIVE;
549 break;
550
551 case4(054):
552 opx->offset = getu64(data);
553 data += 8;
554 break;
555
556 case4(060):
557 opx->offset = gets16(data);
558 data += 2;
559 opx->segment |= SEG_RELATIVE;
560 opx->segment &= ~SEG_32BIT;
561 break;
562
563 case4(064):
564 opx->segment |= SEG_RELATIVE;
565 if (osize == 16) {
566 opx->offset = gets16(data);
567 data += 2;
568 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
569 } else if (osize == 32) {
570 opx->offset = gets32(data);
571 data += 4;
572 opx->segment &= ~SEG_64BIT;
573 opx->segment |= SEG_32BIT;
574 }
575 if (segsize != osize) {
576 opx->type =
577 (opx->type & ~SIZE_MASK)
578 | ((osize == 16) ? BITS16 : BITS32);
579 }
580 break;
581
582 case4(070):
583 opx->offset = gets32(data);
584 data += 4;
585 opx->segment |= SEG_32BIT | SEG_RELATIVE;
586 break;
587
588 case4(0100):
589 case4(0110):
590 case4(0120):
591 case4(0130):
592 {
593 int modrm = *data++;
594 opx->segment |= SEG_RMREG;
595 data = do_ea(data, modrm, asize, segsize,
596 &ins->oprs[(c >> 3) & 3], ins);
597 if (!data)
598 return false;
599 opx->basereg = ((modrm >> 3)&7)+
600 (ins->rex & REX_R ? 8 : 0);
601 break;
602 }
603
604 case4(0140):
605 if (s_field_for == (c & 3)) {
606 opx->offset = gets8(data);
607 data++;
608 } else {
609 opx->offset = getu16(data);
610 data += 2;
611 }
612 break;
613
614 case4(0144):
615 case4(0154):
616 s_field_for = (*data & 0x02) ? c & 3 : -1;
617 if ((*data++ & ~0x02) != *r++)
618 return false;
619 break;
620
621 case4(0150):
622 if (s_field_for == (c & 3)) {
623 opx->offset = gets8(data);
624 data++;
625 } else {
626 opx->offset = getu32(data);
627 data += 4;
628 }
629 break;
630
631 case4(0160):
632 ins->rex |= REX_D;
633 ins->drexdst = c & 3;
634 break;
635
636 case4(0164):
637 ins->rex |= REX_D|REX_OC;
638 ins->drexdst = c & 3;
639 break;
640
641 case 0171:
642 data = do_drex(data, ins);
643 if (!data)
644 return false;
645 break;
646
647 case 0172:
648 {
649 uint8_t ximm = *data++;
650 c = *r++;
651 ins->oprs[c >> 3].basereg = ximm >> 4;
652 ins->oprs[c >> 3].segment |= SEG_RMREG;
653 ins->oprs[c & 7].offset = ximm & 15;
654 }
655 break;
656
657 case 0173:
658 {
659 uint8_t ximm = *data++;
660 c = *r++;
661
662 if ((c ^ ximm) & 15)
663 return false;
664
665 ins->oprs[c >> 4].basereg = ximm >> 4;
666 ins->oprs[c >> 4].segment |= SEG_RMREG;
667 }
668 break;
669
670 case4(0200):
671 case4(0204):
672 case4(0210):
673 case4(0214):
674 case4(0220):
675 case4(0224):
676 case4(0230):
677 case4(0234):
678 {
679 int modrm = *data++;
680 if (((modrm >> 3) & 07) != (c & 07))
681 return false; /* spare field doesn't match up */
682 data = do_ea(data, modrm, asize, segsize,
683 &ins->oprs[(c >> 3) & 07], ins);
684 if (!data)
685 return false;
686 break;
687 }
688
689 case4(0260):
690 {
691 int vexm = *r++;
692 int vexwlp = *r++;
693 ins->rex |= REX_V;
694 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
695 return false;
696
697 if ((vexm & 0x1f) != prefix->vex_m)
698 return false;
699
700 switch (vexwlp & 030) {
701 case 000:
702 if (prefix->rex & REX_W)
703 return false;
704 break;
705 case 010:
706 if (!(prefix->rex & REX_W))
707 return false;
708 break;
709 default:
710 break; /* XXX: Need to do anything special here? */
711 }
712
713 if ((vexwlp & 007) != prefix->vex_lp)
714 return false;
715
716 opx->segment |= SEG_RMREG;
717 opx->basereg = prefix->vex_v;
718 break;
719 }
720
721 case 0270:
722 {
723 int vexm = *r++;
724 int vexwlp = *r++;
725 ins->rex |= REX_V;
726 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
727 return false;
728
729 if ((vexm & 0x1f) != prefix->vex_m)
730 return false;
731
732 switch (vexwlp & 030) {
733 case 000:
734 if (ins->rex & REX_W)
735 return false;
736 break;
737 case 010:
738 if (!(ins->rex & REX_W))
739 return false;
740 break;
741 default:
742 break; /* Need to do anything special here? */
743 }
744
745 if ((vexwlp & 007) != prefix->vex_lp)
746 return false;
747
748 if (prefix->vex_v != 0)
749 return false;
750
751 break;
752 }
753
754 case 0310:
755 if (asize != 16)
756 return false;
757 else
758 a_used = true;
759 break;
760
761 case 0311:
762 if (asize == 16)
763 return false;
764 else
765 a_used = true;
766 break;
767
768 case 0312:
769 if (asize != segsize)
770 return false;
771 else
772 a_used = true;
773 break;
774
775 case 0313:
776 if (asize != 64)
777 return false;
778 else
779 a_used = true;
780 break;
781
782 case 0314:
783 if (prefix->rex & REX_B)
784 return false;
785 break;
786
787 case 0315:
788 if (prefix->rex & REX_X)
789 return false;
790 break;
791
792 case 0316:
793 if (prefix->rex & REX_R)
794 return false;
795 break;
796
797 case 0317:
798 if (prefix->rex & REX_W)
799 return false;
800 break;
801
802 case 0320:
803 if (osize != 16)
804 return false;
805 else
806 o_used = true;
807 break;
808
809 case 0321:
810 if (osize != 32)
811 return false;
812 else
813 o_used = true;
814 break;
815
816 case 0322:
817 if (osize != (segsize == 16) ? 16 : 32)
818 return false;
819 else
820 o_used = true;
821 break;
822
823 case 0323:
824 ins->rex |= REX_W; /* 64-bit only instruction */
825 osize = 64;
826 o_used = true;
827 break;
828
829 case 0324:
830 if (!(ins->rex & (REX_P|REX_W)) || osize != 64)
831 return false;
832 o_used = true;
833 break;
834
835 case 0330:
836 {
837 int t = *r++, d = *data++;
838 if (d < t || d > t + 15)
839 return false;
840 else
841 ins->condition = d - t;
842 break;
843 }
844
845 case 0331:
846 if (prefix->rep)
847 return false;
848 break;
849
850 case 0332:
851 if (prefix->rep != 0xF2)
852 return false;
853 drep = 0;
854 break;
855
856 case 0333:
857 if (prefix->rep != 0xF3)
858 return false;
859 drep = 0;
860 break;
861
862 case 0334:
863 if (lock) {
864 ins->rex |= REX_R;
865 lock = 0;
866 }
867 break;
868
869 case 0335:
870 if (drep == P_REP)
871 drep = P_REPE;
872 break;
873
874 case 0340:
875 return false;
876
877 case 0360:
878 if (prefix->osp || prefix->rep)
879 return false;
880 break;
881
882 case 0361:
883 if (!prefix->osp || prefix->rep)
884 return false;
885 break;
886
887 case 0362:
888 if (prefix->osp || prefix->rep != 0xf2)
889 return false;
890 break;
891
892 case 0363:
893 if (prefix->osp || prefix->rep != 0xf3)
894 return false;
895 break;
896
897 case 0364:
898 if (prefix->osp)
899 return false;
900 break;
901
902 case 0365:
903 if (prefix->asp)
904 return false;
905 break;
906
907 case 0366:
908 if (!prefix->osp)
909 return false;
910 o_used = true;
911 break;
912
913 case 0367:
914 if (!prefix->asp)
915 return false;
916 a_used = true;
917 break;
918
919 default:
920 return false; /* Unknown code */
921 }
922 }
923
924 /* REX cannot be combined with DREX or VEX */
925 if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
926 return false;
927
928 /*
929 * Check for unused rep or a/o prefixes.
930 */
931 for (i = 0; i < t->operands; i++) {
932 if (ins->oprs[i].segment != SEG_RMREG)
933 a_used = true;
934 }
935
936 if (lock) {
937 if (ins->prefixes[PPS_LREP])
938 return false;
939 ins->prefixes[PPS_LREP] = P_LOCK;
940 }
941 if (drep) {
942 if (ins->prefixes[PPS_LREP])
943 return false;
944 ins->prefixes[PPS_LREP] = drep;
945 }
946 if (!o_used) {
947 if (osize != ((segsize == 16) ? 16 : 32)) {
948 enum prefixes pfx = 0;
949
950 switch (osize) {
951 case 16:
952 pfx = P_O16;
953 break;
954 case 32:
955 pfx = P_O32;
956 break;
957 case 64:
958 pfx = P_O64;
959 break;
960 }
961
962 if (ins->prefixes[PPS_OSIZE])
963 return false;
964 ins->prefixes[PPS_OSIZE] = pfx;
965 }
966 }
967 if (!a_used && asize != segsize) {
968 if (ins->prefixes[PPS_ASIZE])
969 return false;
970 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
971 }
972
973 /* Fix: check for redundant REX prefixes */
974
975 return data - origdata;
976 }
977
978 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
979 int32_t offset, int autosync, uint32_t prefer)
980 {
981 const struct itemplate * const *p, * const *best_p;
982 const struct disasm_index *ix;
983 uint8_t *dp;
984 int length, best_length = 0;
985 char *segover;
986 int i, slen, colon, n;
987 uint8_t *origdata;
988 int works;
989 insn tmp_ins, ins;
990 uint32_t goodness, best;
991 int best_pref;
992 struct prefix_info prefix;
993 bool end_prefix;
994
995 memset(&ins, 0, sizeof ins);
996
997 /*
998 * Scan for prefixes.
999 */
1000 memset(&prefix, 0, sizeof prefix);
1001 prefix.asize = segsize;
1002 prefix.osize = (segsize == 64) ? 32 : segsize;
1003 segover = NULL;
1004 origdata = data;
1005
1006 end_prefix = false;
1007 while (!end_prefix) {
1008 switch (*data) {
1009 case 0xF2:
1010 case 0xF3:
1011 prefix.rep = *data++;
1012 break;
1013 case 0xF0:
1014 prefix.lock = *data++;
1015 break;
1016 case 0x2E:
1017 segover = "cs", prefix.seg = *data++;
1018 break;
1019 case 0x36:
1020 segover = "ss", prefix.seg = *data++;
1021 break;
1022 case 0x3E:
1023 segover = "ds", prefix.seg = *data++;
1024 break;
1025 case 0x26:
1026 segover = "es", prefix.seg = *data++;
1027 break;
1028 case 0x64:
1029 segover = "fs", prefix.seg = *data++;
1030 break;
1031 case 0x65:
1032 segover = "gs", prefix.seg = *data++;
1033 break;
1034 case 0x66:
1035 prefix.osize = (segsize == 16) ? 32 : 16;
1036 prefix.osp = *data++;
1037 break;
1038 case 0x67:
1039 prefix.asize = (segsize == 32) ? 16 : 32;
1040 prefix.asp = *data++;
1041 break;
1042 case 0xC4:
1043 case 0xC5:
1044 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1045 prefix.vex[0] = *data++;
1046 prefix.vex[1] = *data++;
1047 if (prefix.vex[0] == 0xc4)
1048 prefix.vex[2] = *data++;
1049 }
1050 prefix.rex = REX_V;
1051 if (prefix.vex[0] == 0xc4) {
1052 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1053 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1054 prefix.vex_m = prefix.vex[1] & 0x1f;
1055 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1056 prefix.vex_lp = prefix.vex[2] & 7;
1057 } else {
1058 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1059 prefix.vex_m = 1;
1060 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1061 prefix.vex_lp = prefix.vex[1] & 7;
1062 }
1063 end_prefix = true;
1064 break;
1065 case REX_P + 0x0:
1066 case REX_P + 0x1:
1067 case REX_P + 0x2:
1068 case REX_P + 0x3:
1069 case REX_P + 0x4:
1070 case REX_P + 0x5:
1071 case REX_P + 0x6:
1072 case REX_P + 0x7:
1073 case REX_P + 0x8:
1074 case REX_P + 0x9:
1075 case REX_P + 0xA:
1076 case REX_P + 0xB:
1077 case REX_P + 0xC:
1078 case REX_P + 0xD:
1079 case REX_P + 0xE:
1080 case REX_P + 0xF:
1081 if (segsize == 64) {
1082 prefix.rex = *data++;
1083 if (prefix.rex & REX_W)
1084 prefix.osize = 64;
1085 }
1086 end_prefix = true;
1087 break;
1088 default:
1089 end_prefix = true;
1090 break;
1091 }
1092 }
1093
1094 best = -1; /* Worst possible */
1095 best_p = NULL;
1096 best_pref = INT_MAX;
1097
1098 dp = data;
1099 ix = itable + *dp++;
1100 while (ix->n == -1) {
1101 ix = (const struct disasm_index *)ix->p + *dp++;
1102 }
1103
1104 p = (const struct itemplate * const *)ix->p;
1105 for (n = ix->n; n; n--, p++) {
1106 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1107 works = true;
1108 /*
1109 * Final check to make sure the types of r/m match up.
1110 * XXX: Need to make sure this is actually correct.
1111 */
1112 for (i = 0; i < (*p)->operands; i++) {
1113 if (!((*p)->opd[i] & SAME_AS) &&
1114 (
1115 /* If it's a mem-only EA but we have a
1116 register, die. */
1117 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1118 !(MEMORY & ~(*p)->opd[i])) ||
1119 /* If it's a reg-only EA but we have a memory
1120 ref, die. */
1121 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1122 !(REG_EA & ~(*p)->opd[i]) &&
1123 !((*p)->opd[i] & REG_SMASK)) ||
1124 /* Register type mismatch (eg FS vs REG_DESS):
1125 die. */
1126 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1127 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1128 !whichreg((*p)->opd[i],
1129 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1130 )) {
1131 works = false;
1132 break;
1133 }
1134 }
1135
1136 /*
1137 * Note: we always prefer instructions which incorporate
1138 * prefixes in the instructions themselves. This is to allow
1139 * e.g. PAUSE to be preferred to REP NOP, and deal with
1140 * MMX/SSE instructions where prefixes are used to select
1141 * between MMX and SSE register sets or outright opcode
1142 * selection.
1143 */
1144 if (works) {
1145 int i, nprefix;
1146 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1147 nprefix = 0;
1148 for (i = 0; i < MAXPREFIX; i++)
1149 if (tmp_ins.prefixes[i])
1150 nprefix++;
1151 if (nprefix < best_pref ||
1152 (nprefix == best_pref && goodness < best)) {
1153 /* This is the best one found so far */
1154 best = goodness;
1155 best_p = p;
1156 best_pref = nprefix;
1157 best_length = length;
1158 ins = tmp_ins;
1159 }
1160 }
1161 }
1162 }
1163
1164 if (!best_p)
1165 return 0; /* no instruction was matched */
1166
1167 /* Pick the best match */
1168 p = best_p;
1169 length = best_length;
1170
1171 slen = 0;
1172
1173 /* TODO: snprintf returns the value that the string would have if
1174 * the buffer were long enough, and not the actual length of
1175 * the returned string, so each instance of using the return
1176 * value of snprintf should actually be checked to assure that
1177 * the return value is "sane." Maybe a macro wrapper could
1178 * be used for that purpose.
1179 */
1180 for (i = 0; i < MAXPREFIX; i++)
1181 switch (ins.prefixes[i]) {
1182 case P_LOCK:
1183 slen += snprintf(output + slen, outbufsize - slen, "lock ");
1184 break;
1185 case P_REP:
1186 slen += snprintf(output + slen, outbufsize - slen, "rep ");
1187 break;
1188 case P_REPE:
1189 slen += snprintf(output + slen, outbufsize - slen, "repe ");
1190 break;
1191 case P_REPNE:
1192 slen += snprintf(output + slen, outbufsize - slen, "repne ");
1193 break;
1194 case P_A16:
1195 slen += snprintf(output + slen, outbufsize - slen, "a16 ");
1196 break;
1197 case P_A32:
1198 slen += snprintf(output + slen, outbufsize - slen, "a32 ");
1199 break;
1200 case P_A64:
1201 slen += snprintf(output + slen, outbufsize - slen, "a64 ");
1202 break;
1203 case P_O16:
1204 slen += snprintf(output + slen, outbufsize - slen, "o16 ");
1205 break;
1206 case P_O32:
1207 slen += snprintf(output + slen, outbufsize - slen, "o32 ");
1208 break;
1209 case P_O64:
1210 slen += snprintf(output + slen, outbufsize - slen, "o64 ");
1211 break;
1212 default:
1213 break;
1214 }
1215
1216 for (i = 0; i < (int)elements(ico); i++)
1217 if ((*p)->opcode == ico[i]) {
1218 slen +=
1219 snprintf(output + slen, outbufsize - slen, "%s%s", icn[i],
1220 whichcond(ins.condition));
1221 break;
1222 }
1223 if (i >= (int)elements(ico))
1224 slen +=
1225 snprintf(output + slen, outbufsize - slen, "%s",
1226 insn_names[(*p)->opcode]);
1227 colon = false;
1228 length += data - origdata; /* fix up for prefixes */
1229 for (i = 0; i < (*p)->operands; i++) {
1230 opflags_t t = (*p)->opd[i];
1231 const operand *o = &ins.oprs[i];
1232 int64_t offs;
1233
1234 if (t & SAME_AS) {
1235 o = &ins.oprs[t & ~SAME_AS];
1236 t = (*p)->opd[t & ~SAME_AS];
1237 }
1238
1239 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1240
1241 offs = o->offset;
1242 if (o->segment & SEG_RELATIVE) {
1243 offs += offset + length;
1244 /*
1245 * sort out wraparound
1246 */
1247 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1248 offs &= 0xffff;
1249 else if (segsize != 64)
1250 offs &= 0xffffffff;
1251
1252 /*
1253 * add sync marker, if autosync is on
1254 */
1255 if (autosync)
1256 add_sync(offs, 0L);
1257 }
1258
1259 if (t & COLON)
1260 colon = true;
1261 else
1262 colon = false;
1263
1264 if ((t & (REGISTER | FPUREG)) ||
1265 (o->segment & SEG_RMREG)) {
1266 enum reg_enum reg;
1267 reg = whichreg(t, o->basereg, ins.rex);
1268 if (t & TO)
1269 slen += snprintf(output + slen, outbufsize - slen, "to ");
1270 slen += snprintf(output + slen, outbufsize - slen, "%s",
1271 reg_names[reg - EXPR_REG_START]);
1272 } else if (!(UNITY & ~t)) {
1273 output[slen++] = '1';
1274 } else if (t & IMMEDIATE) {
1275 if (t & BITS8) {
1276 slen +=
1277 snprintf(output + slen, outbufsize - slen, "byte ");
1278 if (o->segment & SEG_SIGNED) {
1279 if (offs < 0) {
1280 offs *= -1;
1281 output[slen++] = '-';
1282 } else
1283 output[slen++] = '+';
1284 }
1285 } else if (t & BITS16) {
1286 slen +=
1287 snprintf(output + slen, outbufsize - slen, "word ");
1288 } else if (t & BITS32) {
1289 slen +=
1290 snprintf(output + slen, outbufsize - slen, "dword ");
1291 } else if (t & BITS64) {
1292 slen +=
1293 snprintf(output + slen, outbufsize - slen, "qword ");
1294 } else if (t & NEAR) {
1295 slen +=
1296 snprintf(output + slen, outbufsize - slen, "near ");
1297 } else if (t & SHORT) {
1298 slen +=
1299 snprintf(output + slen, outbufsize - slen, "short ");
1300 }
1301 slen +=
1302 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1303 offs);
1304 } else if (!(MEM_OFFS & ~t)) {
1305 slen +=
1306 snprintf(output + slen, outbufsize - slen,
1307 "[%s%s%s0x%"PRIx64"]",
1308 (segover ? segover : ""),
1309 (segover ? ":" : ""),
1310 (o->disp_size == 64 ? "qword " :
1311 o->disp_size == 32 ? "dword " :
1312 o->disp_size == 16 ? "word " : ""), offs);
1313 segover = NULL;
1314 } else if (!(REGMEM & ~t)) {
1315 int started = false;
1316 if (t & BITS8)
1317 slen +=
1318 snprintf(output + slen, outbufsize - slen, "byte ");
1319 if (t & BITS16)
1320 slen +=
1321 snprintf(output + slen, outbufsize - slen, "word ");
1322 if (t & BITS32)
1323 slen +=
1324 snprintf(output + slen, outbufsize - slen, "dword ");
1325 if (t & BITS64)
1326 slen +=
1327 snprintf(output + slen, outbufsize - slen, "qword ");
1328 if (t & BITS80)
1329 slen +=
1330 snprintf(output + slen, outbufsize - slen, "tword ");
1331 if (t & BITS128)
1332 slen +=
1333 snprintf(output + slen, outbufsize - slen, "oword ");
1334 if (t & FAR)
1335 slen += snprintf(output + slen, outbufsize - slen, "far ");
1336 if (t & NEAR)
1337 slen +=
1338 snprintf(output + slen, outbufsize - slen, "near ");
1339 output[slen++] = '[';
1340 if (o->disp_size)
1341 slen += snprintf(output + slen, outbufsize - slen, "%s",
1342 (o->disp_size == 64 ? "qword " :
1343 o->disp_size == 32 ? "dword " :
1344 o->disp_size == 16 ? "word " :
1345 ""));
1346 if (o->eaflags & EAF_REL)
1347 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1348 if (segover) {
1349 slen +=
1350 snprintf(output + slen, outbufsize - slen, "%s:",
1351 segover);
1352 segover = NULL;
1353 }
1354 if (o->basereg != -1) {
1355 slen += snprintf(output + slen, outbufsize - slen, "%s",
1356 reg_names[(o->basereg -
1357 EXPR_REG_START)]);
1358 started = true;
1359 }
1360 if (o->indexreg != -1) {
1361 if (started)
1362 output[slen++] = '+';
1363 slen += snprintf(output + slen, outbufsize - slen, "%s",
1364 reg_names[(o->indexreg -
1365 EXPR_REG_START)]);
1366 if (o->scale > 1)
1367 slen +=
1368 snprintf(output + slen, outbufsize - slen, "*%d",
1369 o->scale);
1370 started = true;
1371 }
1372
1373
1374 if (o->segment & SEG_DISP8) {
1375 const char *prefix;
1376 uint8_t offset = offs;
1377 if ((int8_t)offset < 0) {
1378 prefix = "-";
1379 offset = -offset;
1380 } else {
1381 prefix = "+";
1382 }
1383 slen +=
1384 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1385 prefix, offset);
1386 } else if (o->segment & SEG_DISP16) {
1387 const char *prefix;
1388 uint16_t offset = offs;
1389 if ((int16_t)offset < 0 && started) {
1390 offset = -offset;
1391 prefix = "-";
1392 } else {
1393 prefix = started ? "+" : "";
1394 }
1395 slen +=
1396 snprintf(output + slen, outbufsize - slen,
1397 "%s0x%"PRIx16"", prefix, offset);
1398 } else if (o->segment & SEG_DISP32) {
1399 if (prefix.asize == 64) {
1400 const char *prefix;
1401 uint64_t offset = (int64_t)(int32_t)offs;
1402 if ((int32_t)offs < 0 && started) {
1403 offset = -offset;
1404 prefix = "-";
1405 } else {
1406 prefix = started ? "+" : "";
1407 }
1408 slen +=
1409 snprintf(output + slen, outbufsize - slen,
1410 "%s0x%"PRIx64"", prefix, offset);
1411 } else {
1412 const char *prefix;
1413 uint32_t offset = offs;
1414 if ((int32_t) offset < 0 && started) {
1415 offset = -offset;
1416 prefix = "-";
1417 } else {
1418 prefix = started ? "+" : "";
1419 }
1420 slen +=
1421 snprintf(output + slen, outbufsize - slen,
1422 "%s0x%"PRIx32"", prefix, offset);
1423 }
1424 }
1425 output[slen++] = ']';
1426 } else {
1427 slen +=
1428 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1429 i);
1430 }
1431 }
1432 output[slen] = '\0';
1433 if (segover) { /* unused segment override */
1434 char *p = output;
1435 int count = slen + 1;
1436 while (count--)
1437 p[count + 3] = p[count];
1438 strncpy(output, segover, 2);
1439 output[2] = ' ';
1440 }
1441 return length;
1442 }
1443
1444 int32_t eatbyte(uint8_t *data, char *output, int outbufsize)
1445 {
1446 snprintf(output, outbufsize, "db 0x%02X", *data);
1447 return 1;
1448 }
Automatic testing