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Move elements() to nasmlib.h
[nasm/autotest.git] / assemble.c
blob9f3b947085bd8b5a23b85cb6bb7c7308cb172b13
1 /* assemble.c code generation for the Netwide Assembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the licence given in the file "Licence"
6 * distributed in the NASM archive.
7 *
8 * the actual codes (C syntax, i.e. octal):
9 * \0 - terminates the code. (Unless it's a literal of course.)
10 * \1, \2, \3 - that many literal bytes follow in the code stream
11 * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
12 * (POP is never used for CS) depending on operand 0
13 * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
14 * on operand 0
15 * \10..\13 - a literal byte follows in the code stream, to be added
16 * to the register value of operand 0..3
17 * \14..\17 - a signed byte immediate operand, from operand 0..3
18 * \20..\23 - a byte immediate operand, from operand 0..3
19 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
20 * \30..\33 - a word immediate operand, from operand 0..3
21 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
22 * assembly mode or the operand-size override on the operand
23 * \40..\43 - a long immediate operand, from operand 0..3
24 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
25 * depending on the address size of the instruction.
26 * \50..\53 - a byte relative operand, from operand 0..3
27 * \54..\57 - a qword immediate operand, from operand 0..3
28 * \60..\63 - a word relative operand, from operand 0..3
29 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
30 * assembly mode or the operand-size override on the operand
31 * \70..\73 - a long relative operand, from operand 0..3
32 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
33 * \1ab - a ModRM, calculated on EA in operand a, with the spare
34 * field the register value of operand b.
35 * \140..\143 - an immediate word or signed byte for operand 0..3
36 * \144..\147 - or 2 (s-field) into next opcode byte if operand 0..3
37 * is a signed byte rather than a word.
38 * \150..\153 - an immediate dword or signed byte for operand 0..3
39 * \154..\157 - or 2 (s-field) into next opcode byte if operand 0..3
40 * is a signed byte rather than a dword.
41 * \160..\163 - this instruction uses DREX rather than REX, with the
42 * OC0 field set to 0, and the dest field taken from
43 * operand 0..3.
44 * \164..\167 - this instruction uses DREX rather than REX, with the
45 * OC0 field set to 1, and the dest field taken from
46 * operand 0..3.
47 * \170 - encodes the literal byte 0. (Some compilers don't take
48 * kindly to a zero byte in the _middle_ of a compile time
49 * string constant, so I had to put this hack in.)
50 * \171 - placement of DREX suffix in the absence of an EA
51 * \2ab - a ModRM, calculated on EA in operand a, with the spare
52 * field equal to digit b.
53 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
54 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
55 * \312 - (disassembler only) marker on LOOP, LOOPxx instructions.
56 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
57 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
58 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
59 * \322 - indicates that this instruction is only valid when the
60 * operand size is the default (instruction to disassembler,
61 * generates no code in the assembler)
62 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
63 * \324 - indicates 64-bit operand size requiring REX prefix.
64 * \330 - a literal byte follows in the code stream, to be added
65 * to the condition code value of the instruction.
66 * \331 - instruction not valid with REP prefix. Hint for
67 * disassembler only; for SSE instructions.
68 * \332 - REP prefix (0xF2 byte) used as opcode extension.
69 * \333 - REP prefix (0xF3 byte) used as opcode extension.
70 * \334 - LOCK prefix used instead of REX.R
71 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
72 * \340 - reserve <operand 0> bytes of uninitialized storage.
73 * Operand 0 had better be a segmentless constant.
74 * \364 - operand-size prefix (0x66) not permitted
75 * \365 - address-size prefix (0x67) not permitted
76 * \366 - operand-size prefix (0x66) used as opcode extension
77 * \367 - address-size prefix (0x67) used as opcode extension
78 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
79 * 370 is used for Jcc, 371 is used for JMP.
80 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
81 * used for conditional jump over longer jump
82 */
83
84 #include "compiler.h"
85
86 #include <stdio.h>
87 #include <string.h>
88 #include <inttypes.h>
89
90 #include "nasm.h"
91 #include "nasmlib.h"
92 #include "assemble.h"
93 #include "insns.h"
94 #include "preproc.h"
95 #include "regflags.c"
96 #include "regvals.c"
97
98 typedef struct {
99 int sib_present; /* is a SIB byte necessary? */
100 int bytes; /* # of bytes of offset needed */
101 int size; /* lazy - this is sib+bytes+1 */
102 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
103 } ea;
104
105 static uint32_t cpu; /* cpu level received from nasm.c */
106 static efunc errfunc;
107 static struct ofmt *outfmt;
108 static ListGen *list;
109
110 static int64_t calcsize(int32_t, int64_t, int, insn *, const char *);
111 static void gencode(int32_t, int64_t, int, insn *, const char *, int64_t);
112 static int matches(const struct itemplate *, insn *, int bits);
113 static int32_t regflag(const operand *);
114 static int32_t regval(const operand *);
115 static int rexflags(int, int32_t, int);
116 static int op_rexflags(const operand *, int);
117 static ea *process_ea(operand *, ea *, int, int, int, int32_t, int);
118 static void add_asp(insn *, int);
119
120 static int has_prefix(insn * ins, enum prefix_pos pos, enum prefixes prefix)
121 {
122 return ins->prefixes[pos] == prefix;
123 }
124
125 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
126 {
127 if (ins->prefixes[pos])
128 errfunc(ERR_NONFATAL, "invalid %s prefix",
129 prefix_name(ins->prefixes[pos]));
130 }
131
132 static const char *size_name(int size)
133 {
134 switch (size) {
135 case 1:
136 return "byte";
137 case 2:
138 return "word";
139 case 4:
140 return "dword";
141 case 8:
142 return "qword";
143 case 10:
144 return "tword";
145 case 16:
146 return "oword";
147 default:
148 return "???";
149 }
150 }
151
152 static void warn_overflow(int size, int64_t data)
153 {
154 if (size < 8) {
155 int64_t lim = ((int64_t)1 << (size*8))-1;
156
157 if (data < ~lim || data > lim)
158 errfunc(ERR_WARNING, "%s data exceeds bounds", size_name(size));
159 }
160 }
161 /*
162 * This routine wrappers the real output format's output routine,
163 * in order to pass a copy of the data off to the listing file
164 * generator at the same time.
165 */
166 static void out(int64_t offset, int32_t segto, const void *data,
167 uint64_t type, int32_t segment, int32_t wrt)
168 {
169 static int32_t lineno = 0; /* static!!! */
170 static char *lnfname = NULL;
171
172 if ((type & OUT_TYPMASK) == OUT_ADDRESS) {
173 if (segment != NO_SEG || wrt != NO_SEG) {
174 /*
175 * This address is relocated. We must write it as
176 * OUT_ADDRESS, so there's no work to be done here.
177 */
178 list->output(offset, data, type);
179 } else {
180 uint8_t p[8], *q = p;
181 /*
182 * This is a non-relocated address, and we're going to
183 * convert it into RAWDATA format.
184 */
185 if ((type & OUT_SIZMASK) == 4) {
186 WRITELONG(q, *(int32_t *)data);
187 list->output(offset, p, OUT_RAWDATA + 4);
188 } else if ((type & OUT_SIZMASK) == 8) {
189 WRITEDLONG(q, *(int64_t *)data);
190 list->output(offset, p, OUT_RAWDATA + 8);
191 } else {
192 WRITESHORT(q, *(int32_t *)data);
193 list->output(offset, p, OUT_RAWDATA + 2);
194 }
195 }
196 } else if ((type & OUT_TYPMASK) == OUT_RAWDATA) {
197 list->output(offset, data, type);
198 } else if ((type & OUT_TYPMASK) == OUT_RESERVE) {
199 list->output(offset, NULL, type);
200 } else if ((type & OUT_TYPMASK) == OUT_REL2ADR ||
201 (type & OUT_TYPMASK) == OUT_REL4ADR) {
202 list->output(offset, data, type);
203 }
204
205 /*
206 * this call to src_get determines when we call the
207 * debug-format-specific "linenum" function
208 * it updates lineno and lnfname to the current values
209 * returning 0 if "same as last time", -2 if lnfname
210 * changed, and the amount by which lineno changed,
211 * if it did. thus, these variables must be static
212 */
213
214 if (src_get(&lineno, &lnfname)) {
215 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
216 }
217
218 outfmt->output(segto, data, type, segment, wrt);
219 }
220
221 static int jmp_match(int32_t segment, int64_t offset, int bits,
222 insn * ins, const char *code)
223 {
224 int64_t isize;
225 uint8_t c = code[0];
226
227 if (c != 0370 && c != 0371)
228 return 0;
229 if (ins->oprs[0].opflags & OPFLAG_FORWARD) {
230 if ((optimizing < 0 || (ins->oprs[0].type & STRICT))
231 && c == 0370)
232 return 1;
233 else
234 return (pass0 == 0); /* match a forward reference */
235 }
236 isize = calcsize(segment, offset, bits, ins, code);
237 if (ins->oprs[0].segment != segment)
238 return 0;
239 isize = ins->oprs[0].offset - offset - isize; /* isize is now the delta */
240 if (isize >= -128L && isize <= 127L)
241 return 1; /* it is byte size */
242
243 return 0;
244 }
245
246 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
247 insn * instruction, struct ofmt *output, efunc error,
248 ListGen * listgen)
249 {
250 const struct itemplate *temp;
251 int j;
252 int size_prob;
253 int64_t insn_end;
254 int32_t itimes;
255 int64_t start = offset;
256 int64_t wsize = 0; /* size for DB etc. */
257
258 errfunc = error; /* to pass to other functions */
259 cpu = cp;
260 outfmt = output; /* likewise */
261 list = listgen; /* and again */
262
263 switch (instruction->opcode) {
264 case -1:
265 return 0;
266 case I_DB:
267 wsize = 1;
268 break;
269 case I_DW:
270 wsize = 2;
271 break;
272 case I_DD:
273 wsize = 4;
274 break;
275 case I_DQ:
276 wsize = 8;
277 break;
278 case I_DT:
279 wsize = 10;
280 break;
281 case I_DO:
282 wsize = 16;
283 break;
284 default:
285 break;
286 }
287
288 if (wsize) {
289 extop *e;
290 int32_t t = instruction->times;
291 if (t < 0)
292 errfunc(ERR_PANIC,
293 "instruction->times < 0 (%ld) in assemble()", t);
294
295 while (t--) { /* repeat TIMES times */
296 for (e = instruction->eops; e; e = e->next) {
297 if (e->type == EOT_DB_NUMBER) {
298 if (wsize == 1) {
299 if (e->segment != NO_SEG)
300 errfunc(ERR_NONFATAL,
301 "one-byte relocation attempted");
302 else {
303 uint8_t out_byte = e->offset;
304 out(offset, segment, &out_byte,
305 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
306 }
307 } else if (wsize > 8) {
308 errfunc(ERR_NONFATAL, "integer supplied to a DT or DO"
309 " instruction");
310 } else
311 out(offset, segment, &e->offset,
312 OUT_ADDRESS + wsize, e->segment, e->wrt);
313 offset += wsize;
314 } else if (e->type == EOT_DB_STRING) {
315 int align;
316
317 out(offset, segment, e->stringval,
318 OUT_RAWDATA + e->stringlen, NO_SEG, NO_SEG);
319 align = e->stringlen % wsize;
320
321 if (align) {
322 align = wsize - align;
323 out(offset, segment, "\0\0\0\0\0\0\0\0",
324 OUT_RAWDATA + align, NO_SEG, NO_SEG);
325 }
326 offset += e->stringlen + align;
327 }
328 }
329 if (t > 0 && t == instruction->times - 1) {
330 /*
331 * Dummy call to list->output to give the offset to the
332 * listing module.
333 */
334 list->output(offset, NULL, OUT_RAWDATA);
335 list->uplevel(LIST_TIMES);
336 }
337 }
338 if (instruction->times > 1)
339 list->downlevel(LIST_TIMES);
340 return offset - start;
341 }
342
343 if (instruction->opcode == I_INCBIN) {
344 static char fname[FILENAME_MAX];
345 FILE *fp;
346 int32_t len;
347 char *prefix = "", *combine;
348 char **pPrevPath = NULL;
349
350 len = FILENAME_MAX - 1;
351 if (len > instruction->eops->stringlen)
352 len = instruction->eops->stringlen;
353 strncpy(fname, instruction->eops->stringval, len);
354 fname[len] = '\0';
355
356 while (1) { /* added by alexfru: 'incbin' uses include paths */
357 combine = nasm_malloc(strlen(prefix) + len + 1);
358 strcpy(combine, prefix);
359 strcat(combine, fname);
360
361 if ((fp = fopen(combine, "rb")) != NULL) {
362 nasm_free(combine);
363 break;
364 }
365
366 nasm_free(combine);
367 pPrevPath = pp_get_include_path_ptr(pPrevPath);
368 if (pPrevPath == NULL)
369 break;
370 prefix = *pPrevPath;
371 }
372
373 if (fp == NULL)
374 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
375 fname);
376 else if (fseek(fp, 0L, SEEK_END) < 0)
377 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
378 fname);
379 else {
380 static char buf[2048];
381 int32_t t = instruction->times;
382 int32_t base = 0;
383
384 len = ftell(fp);
385 if (instruction->eops->next) {
386 base = instruction->eops->next->offset;
387 len -= base;
388 if (instruction->eops->next->next &&
389 len > instruction->eops->next->next->offset)
390 len = instruction->eops->next->next->offset;
391 }
392 /*
393 * Dummy call to list->output to give the offset to the
394 * listing module.
395 */
396 list->output(offset, NULL, OUT_RAWDATA);
397 list->uplevel(LIST_INCBIN);
398 while (t--) {
399 int32_t l;
400
401 fseek(fp, base, SEEK_SET);
402 l = len;
403 while (l > 0) {
404 int32_t m =
405 fread(buf, 1, (l > (int32_t) sizeof(buf) ? (int32_t) sizeof(buf) : l),
406 fp);
407 if (!m) {
408 /*
409 * This shouldn't happen unless the file
410 * actually changes while we are reading
411 * it.
412 */
413 error(ERR_NONFATAL,
414 "`incbin': unexpected EOF while"
415 " reading file `%s'", fname);
416 t = 0; /* Try to exit cleanly */
417 break;
418 }
419 out(offset, segment, buf, OUT_RAWDATA + m,
420 NO_SEG, NO_SEG);
421 l -= m;
422 }
423 }
424 list->downlevel(LIST_INCBIN);
425 if (instruction->times > 1) {
426 /*
427 * Dummy call to list->output to give the offset to the
428 * listing module.
429 */
430 list->output(offset, NULL, OUT_RAWDATA);
431 list->uplevel(LIST_TIMES);
432 list->downlevel(LIST_TIMES);
433 }
434 fclose(fp);
435 return instruction->times * len;
436 }
437 return 0; /* if we're here, there's an error */
438 }
439
440 /* Check to see if we need an address-size prefix */
441 add_asp(instruction, bits);
442
443 size_prob = false;
444
445 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++){
446 int m = matches(temp, instruction, bits);
447
448 if (m == 99)
449 m += jmp_match(segment, offset, bits, instruction, temp->code);
450
451 if (m == 100) { /* matches! */
452 const char *codes = temp->code;
453 int64_t insn_size = calcsize(segment, offset, bits,
454 instruction, codes);
455 itimes = instruction->times;
456 if (insn_size < 0) /* shouldn't be, on pass two */
457 error(ERR_PANIC, "errors made it through from pass one");
458 else
459 while (itimes--) {
460 for (j = 0; j < MAXPREFIX; j++) {
461 uint8_t c = 0;
462 switch (instruction->prefixes[j]) {
463 case P_LOCK:
464 c = 0xF0;
465 break;
466 case P_REPNE:
467 case P_REPNZ:
468 c = 0xF2;
469 break;
470 case P_REPE:
471 case P_REPZ:
472 case P_REP:
473 c = 0xF3;
474 break;
475 case R_CS:
476 if (bits == 64) {
477 error(ERR_WARNING,
478 "cs segment base generated, but will be ignored in 64-bit mode");
479 }
480 c = 0x2E;
481 break;
482 case R_DS:
483 if (bits == 64) {
484 error(ERR_WARNING,
485 "ds segment base generated, but will be ignored in 64-bit mode");
486 }
487 c = 0x3E;
488 break;
489 case R_ES:
490 if (bits == 64) {
491 error(ERR_WARNING,
492 "es segment base generated, but will be ignored in 64-bit mode");
493 }
494 c = 0x26;
495 break;
496 case R_FS:
497 c = 0x64;
498 break;
499 case R_GS:
500 c = 0x65;
501 break;
502 case R_SS:
503 if (bits == 64) {
504 error(ERR_WARNING,
505 "ss segment base generated, but will be ignored in 64-bit mode");
506 }
507 c = 0x36;
508 break;
509 case R_SEGR6:
510 case R_SEGR7:
511 error(ERR_NONFATAL,
512 "segr6 and segr7 cannot be used as prefixes");
513 break;
514 case P_A16:
515 if (bits == 64) {
516 error(ERR_NONFATAL,
517 "16-bit addressing is not supported "
518 "in 64-bit mode");
519 } else if (bits != 16)
520 c = 0x67;
521 break;
522 case P_A32:
523 if (bits != 32)
524 c = 0x67;
525 break;
526 case P_A64:
527 if (bits != 64) {
528 error(ERR_NONFATAL,
529 "64-bit addressing is only supported "
530 "in 64-bit mode");
531 }
532 break;
533 case P_ASP:
534 c = 0x67;
535 break;
536 case P_O16:
537 if (bits != 16)
538 c = 0x66;
539 break;
540 case P_O32:
541 if (bits == 16)
542 c = 0x66;
543 break;
544 case P_O64:
545 /* REX.W */
546 break;
547 case P_OSP:
548 c = 0x66;
549 break;
550 case P_none:
551 break;
552 default:
553 error(ERR_PANIC, "invalid instruction prefix");
554 }
555 if (c != 0) {
556 out(offset, segment, &c, OUT_RAWDATA + 1,
557 NO_SEG, NO_SEG);
558 offset++;
559 }
560 }
561 insn_end = offset + insn_size;
562 gencode(segment, offset, bits, instruction, codes,
563 insn_end);
564 offset += insn_size;
565 if (itimes > 0 && itimes == instruction->times - 1) {
566 /*
567 * Dummy call to list->output to give the offset to the
568 * listing module.
569 */
570 list->output(offset, NULL, OUT_RAWDATA);
571 list->uplevel(LIST_TIMES);
572 }
573 }
574 if (instruction->times > 1)
575 list->downlevel(LIST_TIMES);
576 return offset - start;
577 } else if (m > 0 && m > size_prob) {
578 size_prob = m;
579 }
580 // temp++;
581 }
582
583 if (temp->opcode == -1) { /* didn't match any instruction */
584 switch (size_prob) {
585 case 1:
586 error(ERR_NONFATAL, "operation size not specified");
587 break;
588 case 2:
589 error(ERR_NONFATAL, "mismatch in operand sizes");
590 break;
591 case 3:
592 error(ERR_NONFATAL, "no instruction for this cpu level");
593 break;
594 case 4:
595 error(ERR_NONFATAL, "instruction not supported in 64-bit mode");
596 break;
597 default:
598 error(ERR_NONFATAL,
599 "invalid combination of opcode and operands");
600 break;
601 }
602 }
603 return 0;
604 }
605
606 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
607 insn * instruction, efunc error)
608 {
609 const struct itemplate *temp;
610
611 errfunc = error; /* to pass to other functions */
612 cpu = cp;
613
614 if (instruction->opcode == -1)
615 return 0;
616
617 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
618 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
619 instruction->opcode == I_DT || instruction->opcode == I_DO) {
620 extop *e;
621 int32_t isize, osize, wsize = 0; /* placate gcc */
622
623 isize = 0;
624 switch (instruction->opcode) {
625 case I_DB:
626 wsize = 1;
627 break;
628 case I_DW:
629 wsize = 2;
630 break;
631 case I_DD:
632 wsize = 4;
633 break;
634 case I_DQ:
635 wsize = 8;
636 break;
637 case I_DT:
638 wsize = 10;
639 break;
640 case I_DO:
641 wsize = 16;
642 break;
643 default:
644 break;
645 }
646
647 for (e = instruction->eops; e; e = e->next) {
648 int32_t align;
649
650 osize = 0;
651 if (e->type == EOT_DB_NUMBER)
652 osize = 1;
653 else if (e->type == EOT_DB_STRING)
654 osize = e->stringlen;
655
656 align = (-osize) % wsize;
657 if (align < 0)
658 align += wsize;
659 isize += osize + align;
660 }
661 return isize * instruction->times;
662 }
663
664 if (instruction->opcode == I_INCBIN) {
665 char fname[FILENAME_MAX];
666 FILE *fp;
667 int32_t len;
668 char *prefix = "", *combine;
669 char **pPrevPath = NULL;
670
671 len = FILENAME_MAX - 1;
672 if (len > instruction->eops->stringlen)
673 len = instruction->eops->stringlen;
674 strncpy(fname, instruction->eops->stringval, len);
675 fname[len] = '\0';
676
677 /* added by alexfru: 'incbin' uses include paths */
678 while (1) {
679 combine = nasm_malloc(strlen(prefix) + len + 1);
680 strcpy(combine, prefix);
681 strcat(combine, fname);
682
683 if ((fp = fopen(combine, "rb")) != NULL) {
684 nasm_free(combine);
685 break;
686 }
687
688 nasm_free(combine);
689 pPrevPath = pp_get_include_path_ptr(pPrevPath);
690 if (pPrevPath == NULL)
691 break;
692 prefix = *pPrevPath;
693 }
694
695 if (fp == NULL)
696 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
697 fname);
698 else if (fseek(fp, 0L, SEEK_END) < 0)
699 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
700 fname);
701 else {
702 len = ftell(fp);
703 fclose(fp);
704 if (instruction->eops->next) {
705 len -= instruction->eops->next->offset;
706 if (instruction->eops->next->next &&
707 len > instruction->eops->next->next->offset) {
708 len = instruction->eops->next->next->offset;
709 }
710 }
711 return instruction->times * len;
712 }
713 return 0; /* if we're here, there's an error */
714 }
715
716 /* Check to see if we need an address-size prefix */
717 add_asp(instruction, bits);
718
719 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++) {
720 int m = matches(temp, instruction, bits);
721 if (m == 99)
722 m += jmp_match(segment, offset, bits, instruction, temp->code);
723
724 if (m == 100) {
725 /* we've matched an instruction. */
726 int64_t isize;
727 const char *codes = temp->code;
728 int j;
729
730 isize = calcsize(segment, offset, bits, instruction, codes);
731 if (isize < 0)
732 return -1;
733 for (j = 0; j < MAXPREFIX; j++) {
734 switch (instruction->prefixes[j]) {
735 case P_A16:
736 if (bits != 16)
737 isize++;
738 break;
739 case P_A32:
740 if (bits != 32)
741 isize++;
742 break;
743 case P_O16:
744 if (bits != 16)
745 isize++;
746 break;
747 case P_O32:
748 if (bits == 16)
749 isize++;
750 break;
751 case P_A64:
752 case P_O64:
753 case P_none:
754 break;
755 default:
756 isize++;
757 break;
758 }
759 }
760 return isize * instruction->times;
761 }
762 }
763 return -1; /* didn't match any instruction */
764 }
765
766 /* check that opn[op] is a signed byte of size 16 or 32,
767 and return the signed value*/
768 static int is_sbyte(insn * ins, int op, int size)
769 {
770 int32_t v;
771 int ret;
772
773 ret = !(ins->forw_ref && ins->oprs[op].opflags) && /* dead in the water on forward reference or External */
774 optimizing >= 0 &&
775 !(ins->oprs[op].type & STRICT) &&
776 ins->oprs[op].wrt == NO_SEG && ins->oprs[op].segment == NO_SEG;
777
778 v = ins->oprs[op].offset;
779 if (size == 16)
780 v = (int16_t)v; /* sign extend if 16 bits */
781
782 return ret && v >= -128L && v <= 127L;
783 }
784
785 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
786 insn * ins, const char *codes)
787 {
788 int64_t length = 0;
789 uint8_t c;
790 int rex_mask = ~0;
791 struct operand *opx;
792
793 ins->rex = 0; /* Ensure REX is reset */
794
795 if (ins->prefixes[PPS_OSIZE] == P_O64)
796 ins->rex |= REX_W;
797
798 (void)segment; /* Don't warn that this parameter is unused */
799 (void)offset; /* Don't warn that this parameter is unused */
800
801 while (*codes) {
802 c = *codes++;
803 opx = &ins->oprs[c & 3];
804 switch (c) {
805 case 01:
806 case 02:
807 case 03:
808 codes += c, length += c;
809 break;
810 case 04:
811 case 05:
812 case 06:
813 case 07:
814 length++;
815 break;
816 case 010:
817 case 011:
818 case 012:
819 case 013:
820 ins->rex |=
821 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
822 codes++, length++;
823 break;
824 case 014:
825 case 015:
826 case 016:
827 case 017:
828 length++;
829 break;
830 case 020:
831 case 021:
832 case 022:
833 case 023:
834 length++;
835 break;
836 case 024:
837 case 025:
838 case 026:
839 case 027:
840 length++;
841 break;
842 case 030:
843 case 031:
844 case 032:
845 case 033:
846 length += 2;
847 break;
848 case 034:
849 case 035:
850 case 036:
851 case 037:
852 if (opx->type & (BITS16 | BITS32 | BITS64))
853 length += (opx->type & BITS16) ? 2 : 4;
854 else
855 length += (bits == 16) ? 2 : 4;
856 break;
857 case 040:
858 case 041:
859 case 042:
860 case 043:
861 length += 4;
862 break;
863 case 044:
864 case 045:
865 case 046:
866 case 047:
867 length += ins->addr_size >> 3;
868 break;
869 case 050:
870 case 051:
871 case 052:
872 case 053:
873 length++;
874 break;
875 case 054:
876 case 055:
877 case 056:
878 case 057:
879 length += 8; /* MOV reg64/imm */
880 break;
881 case 060:
882 case 061:
883 case 062:
884 case 063:
885 length += 2;
886 break;
887 case 064:
888 case 065:
889 case 066:
890 case 067:
891 if (opx->type & (BITS16 | BITS32 | BITS64))
892 length += (opx->type & BITS16) ? 2 : 4;
893 else
894 length += (bits == 16) ? 2 : 4;
895 break;
896 case 070:
897 case 071:
898 case 072:
899 case 073:
900 length += 4;
901 break;
902 case 074:
903 case 075:
904 case 076:
905 case 077:
906 length += 2;
907 break;
908 case 0140:
909 case 0141:
910 case 0142:
911 case 0143:
912 length += is_sbyte(ins, c & 3, 16) ? 1 : 2;
913 break;
914 case 0144:
915 case 0145:
916 case 0146:
917 case 0147:
918 codes += 2;
919 length++;
920 break;
921 case 0150:
922 case 0151:
923 case 0152:
924 case 0153:
925 length += is_sbyte(ins, c & 3, 32) ? 1 : 4;
926 break;
927 case 0154:
928 case 0155:
929 case 0156:
930 case 0157:
931 codes += 2;
932 length++;
933 break;
934 case 0160:
935 case 0161:
936 case 0162:
937 case 0163:
938 length++;
939 ins->rex |= REX_D;
940 ins->drexdst = regval(&ins->oprs[c & 3]);
941 break;
942 case 0164:
943 case 0165:
944 case 0166:
945 case 0167:
946 length++;
947 ins->rex |= REX_D|REX_OC;
948 ins->drexdst = regval(&ins->oprs[c & 3]);
949 break;
950 case 0170:
951 length++;
952 break;
953 case 0171:
954 break;
955 case 0300:
956 case 0301:
957 case 0302:
958 case 0303:
959 break;
960 case 0310:
961 if (bits == 64)
962 return -1;
963 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
964 break;
965 case 0311:
966 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
967 break;
968 case 0312:
969 break;
970 case 0313:
971 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
972 has_prefix(ins, PPS_ASIZE, P_A32))
973 return -1;
974 break;
975 case 0320:
976 length += (bits != 16);
977 break;
978 case 0321:
979 length += (bits == 16);
980 break;
981 case 0322:
982 break;
983 case 0323:
984 rex_mask &= ~REX_W;
985 break;
986 case 0324:
987 ins->rex |= REX_W;
988 break;
989 case 0330:
990 codes++, length++;
991 break;
992 case 0331:
993 break;
994 case 0332:
995 case 0333:
996 length++;
997 break;
998 case 0334:
999 ins->rex |= REX_L;
1000 break;
1001 case 0335:
1002 break;
1003 case 0340:
1004 case 0341:
1005 case 0342:
1006 if (ins->oprs[0].segment != NO_SEG)
1007 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1008 " quantity of BSS space");
1009 else
1010 length += ins->oprs[0].offset << (c & 3);
1011 break;
1012 case 0364:
1013 case 0365:
1014 break;
1015 case 0366:
1016 case 0367:
1017 length++;
1018 break;
1019 case 0370:
1020 case 0371:
1021 case 0372:
1022 break;
1023 case 0373:
1024 length++;
1025 break;
1026 default: /* can't do it by 'case' statements */
1027 if (c >= 0100 && c <= 0277) { /* it's an EA */
1028 ea ea_data;
1029 int rfield;
1030 int32_t rflags;
1031 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1032
1033 if (c <= 0177) {
1034 /* pick rfield from operand b */
1035 rflags = regflag(&ins->oprs[c & 7]);
1036 rfield = regvals[ins->oprs[c & 7].basereg];
1037 } else {
1038 rflags = 0;
1039 rfield = c & 7;
1040 }
1041
1042 if (!process_ea
1043 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1044 ins->addr_size, rfield, rflags, ins->forw_ref)) {
1045 errfunc(ERR_NONFATAL, "invalid effective address");
1046 return -1;
1047 } else {
1048 ins->rex |= ea_data.rex;
1049 length += ea_data.size;
1050 }
1051 } else {
1052 errfunc(ERR_PANIC, "internal instruction table corrupt"
1053 ": instruction code 0x%02X given", c);
1054 }
1055 }
1056 }
1057
1058 ins->rex &= rex_mask;
1059
1060 if (ins->rex & REX_D) {
1061 if (ins->rex & REX_H) {
1062 errfunc(ERR_NONFATAL, "cannot use high register in drex instruction");
1063 return -1;
1064 }
1065 if (bits != 64 && ((ins->rex & (REX_W|REX_X|REX_B)) ||
1066 ins->drexdst > 7)) {
1067 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1068 return -1;
1069 }
1070 length++;
1071 } else if (ins->rex & REX_REAL) {
1072 if (ins->rex & REX_H) {
1073 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1074 return -1;
1075 } else if (bits == 64) {
1076 length++;
1077 } else if ((ins->rex & REX_L) &&
1078 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1079 cpu >= IF_X86_64) {
1080 /* LOCK-as-REX.R */
1081 assert_no_prefix(ins, PPS_LREP);
1082 length++;
1083 } else {
1084 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1085 return -1;
1086 }
1087 }
1088
1089 return length;
1090 }
1091
1092 #define EMIT_REX() \
1093 if (!(ins->rex & REX_D) && (ins->rex & REX_REAL) && (bits == 64)) { \
1094 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1095 out(offset, segment, &ins->rex, OUT_RAWDATA+1, NO_SEG, NO_SEG); \
1096 ins->rex = 0; \
1097 offset += 1; \
1098 }
1099
1100 static void gencode(int32_t segment, int64_t offset, int bits,
1101 insn * ins, const char *codes, int64_t insn_end)
1102 {
1103 static char condval[] = { /* conditional opcodes */
1104 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1105 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1106 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1107 };
1108 uint8_t c;
1109 uint8_t bytes[4];
1110 int64_t size;
1111 int64_t data;
1112 struct operand *opx;
1113
1114 while (*codes) {
1115 c = *codes++;
1116 opx = &ins->oprs[c & 3];
1117 switch (c) {
1118 case 01:
1119 case 02:
1120 case 03:
1121 EMIT_REX();
1122 out(offset, segment, codes, OUT_RAWDATA + c, NO_SEG, NO_SEG);
1123 codes += c;
1124 offset += c;
1125 break;
1126
1127 case 04:
1128 case 06:
1129 switch (ins->oprs[0].basereg) {
1130 case R_CS:
1131 bytes[0] = 0x0E + (c == 0x04 ? 1 : 0);
1132 break;
1133 case R_DS:
1134 bytes[0] = 0x1E + (c == 0x04 ? 1 : 0);
1135 break;
1136 case R_ES:
1137 bytes[0] = 0x06 + (c == 0x04 ? 1 : 0);
1138 break;
1139 case R_SS:
1140 bytes[0] = 0x16 + (c == 0x04 ? 1 : 0);
1141 break;
1142 default:
1143 errfunc(ERR_PANIC,
1144 "bizarre 8086 segment register received");
1145 }
1146 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1147 offset++;
1148 break;
1149
1150 case 05:
1151 case 07:
1152 switch (ins->oprs[0].basereg) {
1153 case R_FS:
1154 bytes[0] = 0xA0 + (c == 0x05 ? 1 : 0);
1155 break;
1156 case R_GS:
1157 bytes[0] = 0xA8 + (c == 0x05 ? 1 : 0);
1158 break;
1159 default:
1160 errfunc(ERR_PANIC,
1161 "bizarre 386 segment register received");
1162 }
1163 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1164 offset++;
1165 break;
1166
1167 case 010:
1168 case 011:
1169 case 012:
1170 case 013:
1171 EMIT_REX();
1172 bytes[0] = *codes++ + ((regval(opx)) & 7);
1173 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1174 offset += 1;
1175 break;
1176
1177 case 014:
1178 case 015:
1179 case 016:
1180 case 017:
1181 if (opx->offset < -128 || opx->offset > 127) {
1182 errfunc(ERR_WARNING, "signed byte value exceeds bounds");
1183 }
1184
1185 if (opx->segment != NO_SEG) {
1186 data = opx->offset;
1187 out(offset, segment, &data, OUT_ADDRESS + 1,
1188 opx->segment, opx->wrt);
1189 } else {
1190 bytes[0] = opx->offset;
1191 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG,
1192 NO_SEG);
1193 }
1194 offset += 1;
1195 break;
1196
1197 case 020:
1198 case 021:
1199 case 022:
1200 case 023:
1201 if (opx->offset < -256 || opx->offset > 255) {
1202 errfunc(ERR_WARNING, "byte value exceeds bounds");
1203 }
1204 if (opx->segment != NO_SEG) {
1205 data = opx->offset;
1206 out(offset, segment, &data, OUT_ADDRESS + 1,
1207 opx->segment, opx->wrt);
1208 } else {
1209 bytes[0] = opx->offset;
1210 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG,
1211 NO_SEG);
1212 }
1213 offset += 1;
1214 break;
1215
1216 case 024:
1217 case 025:
1218 case 026:
1219 case 027:
1220 if (opx->offset < 0 || opx->offset > 255)
1221 errfunc(ERR_WARNING, "unsigned byte value exceeds bounds");
1222 if (opx->segment != NO_SEG) {
1223 data = opx->offset;
1224 out(offset, segment, &data, OUT_ADDRESS + 1,
1225 opx->segment, opx->wrt);
1226 } else {
1227 bytes[0] = opx->offset;
1228 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG,
1229 NO_SEG);
1230 }
1231 offset += 1;
1232 break;
1233
1234 case 030:
1235 case 031:
1236 case 032:
1237 case 033:
1238 data = opx->offset;
1239 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1240 warn_overflow(2, data);
1241 out(offset, segment, &data, OUT_ADDRESS + 2,
1242 opx->segment, opx->wrt);
1243 offset += 2;
1244 break;
1245
1246 case 034:
1247 case 035:
1248 case 036:
1249 case 037:
1250 if (opx->type & (BITS16 | BITS32))
1251 size = (opx->type & BITS16) ? 2 : 4;
1252 else
1253 size = (bits == 16) ? 2 : 4;
1254 data = opx->offset;
1255 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1256 warn_overflow(size, data);
1257 out(offset, segment, &data, OUT_ADDRESS + size,
1258 opx->segment, opx->wrt);
1259 offset += size;
1260 break;
1261
1262 case 040:
1263 case 041:
1264 case 042:
1265 case 043:
1266 data = opx->offset;
1267 out(offset, segment, &data, OUT_ADDRESS + 4,
1268 opx->segment, opx->wrt);
1269 offset += 4;
1270 break;
1271
1272 case 044:
1273 case 045:
1274 case 046:
1275 case 047:
1276 data = opx->offset;
1277 size = ins->addr_size >> 3;
1278 if (opx->segment == NO_SEG &&
1279 opx->wrt == NO_SEG)
1280 warn_overflow(size, data);
1281 out(offset, segment, &data, OUT_ADDRESS + size,
1282 opx->segment, opx->wrt);
1283 offset += size;
1284 break;
1285
1286 case 050:
1287 case 051:
1288 case 052:
1289 case 053:
1290 if (opx->segment != segment)
1291 errfunc(ERR_NONFATAL,
1292 "short relative jump outside segment");
1293 data = opx->offset - insn_end;
1294 if (data > 127 || data < -128)
1295 errfunc(ERR_NONFATAL, "short jump is out of range");
1296 bytes[0] = data;
1297 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1298 offset += 1;
1299 break;
1300
1301 case 054:
1302 case 055:
1303 case 056:
1304 case 057:
1305 data = (int64_t)opx->offset;
1306 out(offset, segment, &data, OUT_ADDRESS + 8,
1307 opx->segment, opx->wrt);
1308 offset += 8;
1309 break;
1310
1311 case 060:
1312 case 061:
1313 case 062:
1314 case 063:
1315 if (opx->segment != segment) {
1316 data = opx->offset;
1317 out(offset, segment, &data,
1318 OUT_REL2ADR + insn_end - offset,
1319 opx->segment, opx->wrt);
1320 } else {
1321 data = opx->offset - insn_end;
1322 out(offset, segment, &data,
1323 OUT_ADDRESS + 2, NO_SEG, NO_SEG);
1324 }
1325 offset += 2;
1326 break;
1327
1328 case 064:
1329 case 065:
1330 case 066:
1331 case 067:
1332 if (opx->type & (BITS16 | BITS32 | BITS64))
1333 size = (opx->type & BITS16) ? 2 : 4;
1334 else
1335 size = (bits == 16) ? 2 : 4;
1336 if (opx->segment != segment) {
1337 int64_t reltype = (size == 2 ? OUT_REL2ADR : OUT_REL4ADR);
1338 data = opx->offset;
1339 out(offset, segment, &data, reltype + insn_end - offset,
1340 opx->segment, opx->wrt);
1341 } else {
1342 data = opx->offset - insn_end;
1343 out(offset, segment, &data,
1344 OUT_ADDRESS + size, NO_SEG, NO_SEG);
1345 }
1346 offset += size;
1347 break;
1348
1349 case 070:
1350 case 071:
1351 case 072:
1352 case 073:
1353 if (opx->segment != segment) {
1354 data = opx->offset;
1355 out(offset, segment, &data,
1356 OUT_REL4ADR + insn_end - offset,
1357 opx->segment, opx->wrt);
1358 } else {
1359 data = opx->offset - insn_end;
1360 out(offset, segment, &data,
1361 OUT_ADDRESS + 4, NO_SEG, NO_SEG);
1362 }
1363 offset += 4;
1364 break;
1365
1366 case 074:
1367 case 075:
1368 case 076:
1369 case 077:
1370 if (opx->segment == NO_SEG)
1371 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1372 " relocatable");
1373 data = 0L;
1374 out(offset, segment, &data, OUT_ADDRESS + 2,
1375 outfmt->segbase(1 + opx->segment),
1376 opx->wrt);
1377 offset += 2;
1378 break;
1379
1380 case 0140:
1381 case 0141:
1382 case 0142:
1383 case 0143:
1384 data = opx->offset;
1385 if (is_sbyte(ins, c & 3, 16)) {
1386 bytes[0] = data;
1387 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG,
1388 NO_SEG);
1389 offset++;
1390 } else {
1391 if (opx->segment == NO_SEG &&
1392 opx->wrt == NO_SEG)
1393 warn_overflow(2, data);
1394 out(offset, segment, &data, OUT_ADDRESS + 2,
1395 opx->segment, opx->wrt);
1396 offset += 2;
1397 }
1398 break;
1399
1400 case 0144:
1401 case 0145:
1402 case 0146:
1403 case 0147:
1404 EMIT_REX();
1405 codes++;
1406 bytes[0] = *codes++;
1407 if (is_sbyte(ins, c & 3, 16))
1408 bytes[0] |= 2; /* s-bit */
1409 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1410 offset++;
1411 break;
1412
1413 case 0150:
1414 case 0151:
1415 case 0152:
1416 case 0153:
1417 data = opx->offset;
1418 if (is_sbyte(ins, c & 3, 32)) {
1419 bytes[0] = data;
1420 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG,
1421 NO_SEG);
1422 offset++;
1423 } else {
1424 out(offset, segment, &data, OUT_ADDRESS + 4,
1425 opx->segment, opx->wrt);
1426 offset += 4;
1427 }
1428 break;
1429
1430 case 0154:
1431 case 0155:
1432 case 0156:
1433 case 0157:
1434 EMIT_REX();
1435 codes++;
1436 bytes[0] = *codes++;
1437 if (is_sbyte(ins, c & 3, 32))
1438 bytes[0] |= 2; /* s-bit */
1439 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1440 offset++;
1441 break;
1442
1443 case 0160:
1444 case 0161:
1445 case 0162:
1446 case 0163:
1447 case 0164:
1448 case 0165:
1449 case 0166:
1450 case 0167:
1451 break;
1452
1453 case 0170:
1454 EMIT_REX();
1455 bytes[0] = 0;
1456 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1457 offset += 1;
1458 break;
1459
1460 case 0171:
1461 bytes[0] =
1462 (ins->drexdst << 4) |
1463 (ins->rex & REX_OC ? 0x08 : 0) |
1464 (ins->rex & (REX_R|REX_X|REX_B));
1465 ins->rex = 0;
1466 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1467 offset++;
1468 break;
1469
1470 case 0300:
1471 case 0301:
1472 case 0302:
1473 case 0303:
1474 break;
1475
1476 case 0310:
1477 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1478 *bytes = 0x67;
1479 out(offset, segment, bytes,
1480 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1481 offset += 1;
1482 } else
1483 offset += 0;
1484 break;
1485
1486 case 0311:
1487 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1488 *bytes = 0x67;
1489 out(offset, segment, bytes,
1490 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1491 offset += 1;
1492 } else
1493 offset += 0;
1494 break;
1495
1496 case 0312:
1497 break;
1498
1499 case 0313:
1500 ins->rex = 0;
1501 break;
1502
1503 case 0320:
1504 if (bits != 16) {
1505 *bytes = 0x66;
1506 out(offset, segment, bytes,
1507 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1508 offset += 1;
1509 } else
1510 offset += 0;
1511 break;
1512
1513 case 0321:
1514 if (bits == 16) {
1515 *bytes = 0x66;
1516 out(offset, segment, bytes,
1517 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1518 offset += 1;
1519 } else
1520 offset += 0;
1521 break;
1522
1523 case 0322:
1524 case 0323:
1525 break;
1526
1527 case 0324:
1528 ins->rex |= REX_W;
1529 break;
1530
1531 case 0330:
1532 *bytes = *codes++ ^ condval[ins->condition];
1533 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1534 offset += 1;
1535 break;
1536
1537 case 0331:
1538 break;
1539
1540 case 0332:
1541 case 0333:
1542 *bytes = c - 0332 + 0xF2;
1543 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1544 offset += 1;
1545 break;
1546
1547 case 0334:
1548 if (ins->rex & REX_R) {
1549 *bytes = 0xF0;
1550 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1551 offset += 1;
1552 }
1553 ins->rex &= ~(REX_L|REX_R);
1554 break;
1555
1556 case 0335:
1557 break;
1558
1559 case 0340:
1560 case 0341:
1561 case 0342:
1562 if (ins->oprs[0].segment != NO_SEG)
1563 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1564 else {
1565 int64_t size = ins->oprs[0].offset << (c & 3);
1566 if (size > 0)
1567 out(offset, segment, NULL,
1568 OUT_RESERVE + size, NO_SEG, NO_SEG);
1569 offset += size;
1570 }
1571 break;
1572
1573 case 0364:
1574 case 0365:
1575 break;
1576
1577 case 0366:
1578 case 0367:
1579 *bytes = c - 0366 + 0x66;
1580 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1581 offset += 1;
1582 break;
1583
1584 case 0370:
1585 case 0371:
1586 case 0372:
1587 break;
1588
1589 case 0373:
1590 *bytes = bits == 16 ? 3 : 5;
1591 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1592 offset += 1;
1593 break;
1594
1595 default: /* can't do it by 'case' statements */
1596 if (c >= 0100 && c <= 0277) { /* it's an EA */
1597 ea ea_data;
1598 int rfield;
1599 int32_t rflags;
1600 uint8_t *p;
1601 int32_t s;
1602
1603 if (c <= 0177) {
1604 /* pick rfield from operand b */
1605 rflags = regflag(&ins->oprs[c & 7]);
1606 rfield = regvals[ins->oprs[c & 7].basereg];
1607 } else {
1608 /* rfield is constant */
1609 rflags = 0;
1610 rfield = c & 7;
1611 }
1612
1613 if (!process_ea
1614 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1615 ins->addr_size, rfield, rflags, ins->forw_ref)) {
1616 errfunc(ERR_NONFATAL, "invalid effective address");
1617 }
1618
1619
1620 p = bytes;
1621 *p++ = ea_data.modrm;
1622 if (ea_data.sib_present)
1623 *p++ = ea_data.sib;
1624
1625 /* DREX suffixes come between the SIB and the displacement */
1626 if (ins->rex & REX_D) {
1627 *p++ =
1628 (ins->drexdst << 4) |
1629 (ins->rex & REX_OC ? 0x08 : 0) |
1630 (ins->rex & (REX_R|REX_X|REX_B));
1631 ins->rex = 0;
1632 }
1633
1634 s = p - bytes;
1635 out(offset, segment, bytes, OUT_RAWDATA + s,
1636 NO_SEG, NO_SEG);
1637
1638 switch (ea_data.bytes) {
1639 case 0:
1640 break;
1641 case 1:
1642 if (ins->oprs[(c >> 3) & 7].segment != NO_SEG) {
1643 data = ins->oprs[(c >> 3) & 7].offset;
1644 out(offset, segment, &data, OUT_ADDRESS + 1,
1645 ins->oprs[(c >> 3) & 7].segment,
1646 ins->oprs[(c >> 3) & 7].wrt);
1647 } else {
1648 *bytes = ins->oprs[(c >> 3) & 7].offset;
1649 out(offset, segment, bytes, OUT_RAWDATA + 1,
1650 NO_SEG, NO_SEG);
1651 }
1652 s++;
1653 break;
1654 case 8:
1655 case 2:
1656 case 4:
1657 data = ins->oprs[(c >> 3) & 7].offset;
1658 warn_overflow(ea_data.bytes, data);
1659 out(offset, segment, &data,
1660 (ea_data.rip ? OUT_REL4ADR : OUT_ADDRESS)
1661 + ea_data.bytes,
1662 ins->oprs[(c >> 3) & 7].segment,
1663 ins->oprs[(c >> 3) & 7].wrt);
1664 s += ea_data.bytes;
1665 break;
1666 }
1667 offset += s;
1668 } else {
1669 errfunc(ERR_PANIC, "internal instruction table corrupt"
1670 ": instruction code 0x%02X given", c);
1671 }
1672 }
1673 }
1674 }
1675
1676 static int32_t regflag(const operand * o)
1677 {
1678 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1679 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1680 }
1681 return reg_flags[o->basereg];
1682 }
1683
1684 static int32_t regval(const operand * o)
1685 {
1686 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1687 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1688 }
1689 return regvals[o->basereg];
1690 }
1691
1692 static int op_rexflags(const operand * o, int mask)
1693 {
1694 int32_t flags;
1695 int val;
1696
1697 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1698 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1699 }
1700
1701 flags = reg_flags[o->basereg];
1702 val = regvals[o->basereg];
1703
1704 return rexflags(val, flags, mask);
1705 }
1706
1707 static int rexflags(int val, int32_t flags, int mask)
1708 {
1709 int rex = 0;
1710
1711 if (val >= 8)
1712 rex |= REX_B|REX_X|REX_R;
1713 if (flags & BITS64)
1714 rex |= REX_W;
1715 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1716 rex |= REX_H;
1717 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1718 rex |= REX_P;
1719
1720 return rex & mask;
1721 }
1722
1723 static int matches(const struct itemplate *itemp, insn * instruction, int bits)
1724 {
1725 int i, size[MAX_OPERANDS], asize, oprs, ret;
1726
1727 ret = 100;
1728
1729 /*
1730 * Check the opcode
1731 */
1732 if (itemp->opcode != instruction->opcode)
1733 return 0;
1734
1735 /*
1736 * Count the operands
1737 */
1738 if (itemp->operands != instruction->operands)
1739 return 0;
1740
1741 /*
1742 * Check that no spurious colons or TOs are present
1743 */
1744 for (i = 0; i < itemp->operands; i++)
1745 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
1746 return 0;
1747
1748 /*
1749 * Check that the operand flags all match up
1750 */
1751 for (i = 0; i < itemp->operands; i++) {
1752 if (itemp->opd[i] & SAME_AS) {
1753 int j = itemp->opd[i] & ~SAME_AS;
1754 if (instruction->oprs[i].type != instruction->oprs[j].type ||
1755 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
1756 return 0;
1757 } else if (itemp->opd[i] & ~instruction->oprs[i].type ||
1758 ((itemp->opd[i] & SIZE_MASK) &&
1759 ((itemp->opd[i] ^ instruction->oprs[i].type) & SIZE_MASK))) {
1760 if ((itemp->opd[i] & ~instruction->oprs[i].type & ~SIZE_MASK) ||
1761 (instruction->oprs[i].type & SIZE_MASK))
1762 return 0;
1763 else
1764 return 1;
1765 }
1766 }
1767
1768 /*
1769 * Check operand sizes
1770 */
1771 if (itemp->flags & IF_ARMASK) {
1772 memset(size, 0, sizeof size);
1773
1774 switch (itemp->flags & IF_ARMASK) {
1775 case IF_AR0:
1776 i = 0;
1777 break;
1778 case IF_AR1:
1779 i = 1;
1780 break;
1781 case IF_AR2:
1782 i = 2;
1783 break;
1784 case IF_AR3:
1785 i = 3;
1786 break;
1787 default:
1788 break; /* Shouldn't happen */
1789 }
1790 switch (itemp->flags & IF_SMASK) {
1791 case IF_SB:
1792 size[i] = BITS8;
1793 break;
1794 case IF_SW:
1795 size[i] = BITS16;
1796 break;
1797 case IF_SD:
1798 size[i] = BITS32;
1799 break;
1800 case IF_SQ:
1801 size[i] = BITS64;
1802 break;
1803 case IF_SO:
1804 size[i] = BITS128;
1805 break;
1806 default:
1807 break;
1808 }
1809 } else {
1810 asize = 0;
1811 switch (itemp->flags & IF_SMASK) {
1812 case IF_SB:
1813 asize = BITS8;
1814 oprs = itemp->operands;
1815 break;
1816 case IF_SW:
1817 asize = BITS16;
1818 oprs = itemp->operands;
1819 break;
1820 case IF_SD:
1821 asize = BITS32;
1822 oprs = itemp->operands;
1823 break;
1824 case IF_SQ:
1825 asize = BITS64;
1826 oprs = itemp->operands;
1827 break;
1828 case IF_SO:
1829 asize = BITS128;
1830 oprs = itemp->operands;
1831 break;
1832 default:
1833 break;
1834 }
1835 for (i = 0; i < MAX_OPERANDS; i++)
1836 size[i] = asize;
1837 }
1838
1839 if (itemp->flags & (IF_SM | IF_SM2)) {
1840 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
1841 asize = 0;
1842 for (i = 0; i < oprs; i++) {
1843 if ((asize = itemp->opd[i] & SIZE_MASK) != 0) {
1844 int j;
1845 for (j = 0; j < oprs; j++)
1846 size[j] = asize;
1847 break;
1848 }
1849 }
1850 } else {
1851 oprs = itemp->operands;
1852 }
1853
1854 for (i = 0; i < itemp->operands; i++) {
1855 if (!(itemp->opd[i] & SIZE_MASK) &&
1856 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
1857 return 2;
1858 }
1859
1860 /*
1861 * Check template is okay at the set cpu level
1862 */
1863 if (((itemp->flags & IF_PLEVEL) > cpu))
1864 return 3;
1865
1866 /*
1867 * Check if instruction is available in long mode
1868 */
1869 if ((itemp->flags & IF_NOLONG) && (bits == 64))
1870 return 4;
1871
1872 /*
1873 * Check if special handling needed for Jumps
1874 */
1875 if ((uint8_t)(itemp->code[0]) >= 0370)
1876 return 99;
1877
1878 return ret;
1879 }
1880
1881 static ea *process_ea(operand * input, ea * output, int bits,
1882 int addrbits, int rfield, int32_t rflags, int forw_ref)
1883 {
1884 output->rip = false;
1885
1886 /* REX flags for the rfield operand */
1887 output->rex |= rexflags(rfield, rflags, REX_R|REX_P|REX_W|REX_H);
1888
1889 if (!(REGISTER & ~input->type)) { /* register direct */
1890 int i;
1891 int32_t f;
1892
1893 if (input->basereg < EXPR_REG_START /* Verify as Register */
1894 || input->basereg >= REG_ENUM_LIMIT)
1895 return NULL;
1896 f = regflag(input);
1897 i = regvals[input->basereg];
1898
1899 if (REG_EA & ~f)
1900 return NULL; /* Invalid EA register */
1901
1902 output->rex |= op_rexflags(input, REX_B|REX_P|REX_W|REX_H);
1903
1904 output->sib_present = false; /* no SIB necessary */
1905 output->bytes = 0; /* no offset necessary either */
1906 output->modrm = 0xC0 | ((rfield & 7) << 3) | (i & 7);
1907 } else { /* it's a memory reference */
1908 if (input->basereg == -1
1909 && (input->indexreg == -1 || input->scale == 0)) {
1910 /* it's a pure offset */
1911 if (bits == 64 && (~input->type & IP_REL)) {
1912 int scale, index, base;
1913 output->sib_present = true;
1914 scale = 0;
1915 index = 4;
1916 base = 5;
1917 output->sib = (scale << 6) | (index << 3) | base;
1918 output->bytes = 4;
1919 output->modrm = 4 | ((rfield & 7) << 3);
1920 output->rip = false;
1921 } else {
1922 output->sib_present = false;
1923 output->bytes = (addrbits != 16 ? 4 : 2);
1924 output->modrm = (addrbits != 16 ? 5 : 6) | ((rfield & 7) << 3);
1925 output->rip = bits == 64;
1926 }
1927 } else { /* it's an indirection */
1928 int i = input->indexreg, b = input->basereg, s = input->scale;
1929 int32_t o = input->offset, seg = input->segment;
1930 int hb = input->hintbase, ht = input->hinttype;
1931 int t;
1932 int it, bt;
1933 int32_t ix, bx; /* register flags */
1934
1935 if (s == 0)
1936 i = -1; /* make this easy, at least */
1937
1938 if (i >= EXPR_REG_START && i < REG_ENUM_LIMIT) {
1939 it = regvals[i];
1940 ix = reg_flags[i];
1941 } else {
1942 it = -1;
1943 ix = 0;
1944 }
1945
1946 if (b >= EXPR_REG_START && b < REG_ENUM_LIMIT) {
1947 bt = regvals[b];
1948 bx = reg_flags[b];
1949 } else {
1950 bt = -1;
1951 bx = 0;
1952 }
1953
1954 /* check for a 32/64-bit memory reference... */
1955 if ((ix|bx) & (BITS32|BITS64)) {
1956 /* it must be a 32/64-bit memory reference. Firstly we have
1957 * to check that all registers involved are type E/Rxx. */
1958 int32_t sok = BITS32|BITS64;
1959
1960 if (it != -1) {
1961 if (!(REG64 & ~ix) || !(REG32 & ~ix))
1962 sok &= ix;
1963 else
1964 return NULL;
1965 }
1966
1967 if (bt != -1) {
1968 if (REG_GPR & ~bx)
1969 return NULL; /* Invalid register */
1970 if (~sok & bx & SIZE_MASK)
1971 return NULL; /* Invalid size */
1972 sok &= bx;
1973 }
1974
1975 /* While we're here, ensure the user didn't specify
1976 WORD or QWORD. */
1977 if (input->disp_size == 16 || input->disp_size == 64)
1978 return NULL;
1979
1980 if (addrbits == 16 ||
1981 (addrbits == 32 && !(sok & BITS32)) ||
1982 (addrbits == 64 && !(sok & BITS64)))
1983 return NULL;
1984
1985 /* now reorganize base/index */
1986 if (s == 1 && bt != it && bt != -1 && it != -1 &&
1987 ((hb == b && ht == EAH_NOTBASE)
1988 || (hb == i && ht == EAH_MAKEBASE))) {
1989 /* swap if hints say so */
1990 t = bt, bt = it, it = t;
1991 t = bx, bx = ix, ix = t;
1992 }
1993 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
1994 bt = -1, bx = 0, s++;
1995 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
1996 /* make single reg base, unless hint */
1997 bt = it, bx = ix, it = -1, ix = 0;
1998 }
1999 if (((s == 2 && it != REG_NUM_ESP
2000 && !(input->eaflags & EAF_TIMESTWO)) || s == 3
2001 || s == 5 || s == 9) && bt == -1)
2002 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2003 if (it == -1 && (bt & 7) != REG_NUM_ESP
2004 && (input->eaflags & EAF_TIMESTWO))
2005 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2006 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2007 if (s == 1 && it == REG_NUM_ESP) {
2008 /* swap ESP into base if scale is 1 */
2009 t = it, it = bt, bt = t;
2010 t = ix, ix = bx, bx = t;
2011 }
2012 if (it == REG_NUM_ESP
2013 || (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2014 return NULL; /* wrong, for various reasons */
2015
2016 output->rex |= rexflags(it, ix, REX_X);
2017 output->rex |= rexflags(bt, bx, REX_B);
2018
2019 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2020 /* no SIB needed */
2021 int mod, rm;
2022
2023 if (bt == -1) {
2024 rm = 5;
2025 mod = 0;
2026 } else {
2027 rm = (bt & 7);
2028 if (rm != REG_NUM_EBP && o == 0 &&
2029 seg == NO_SEG && !forw_ref &&
2030 !(input->eaflags &
2031 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2032 mod = 0;
2033 else if (input->eaflags & EAF_BYTEOFFS ||
2034 (o >= -128 && o <= 127 && seg == NO_SEG
2035 && !forw_ref
2036 && !(input->eaflags & EAF_WORDOFFS)))
2037 mod = 1;
2038 else
2039 mod = 2;
2040 }
2041
2042 output->sib_present = false;
2043 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2044 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2045 } else {
2046 /* we need a SIB */
2047 int mod, scale, index, base;
2048
2049 if (it == -1)
2050 index = 4, s = 1;
2051 else
2052 index = (it & 7);
2053
2054 switch (s) {
2055 case 1:
2056 scale = 0;
2057 break;
2058 case 2:
2059 scale = 1;
2060 break;
2061 case 4:
2062 scale = 2;
2063 break;
2064 case 8:
2065 scale = 3;
2066 break;
2067 default: /* then what the smeg is it? */
2068 return NULL; /* panic */
2069 }
2070
2071 if (bt == -1) {
2072 base = 5;
2073 mod = 0;
2074 } else {
2075 base = (bt & 7);
2076 if (base != REG_NUM_EBP && o == 0 &&
2077 seg == NO_SEG && !forw_ref &&
2078 !(input->eaflags &
2079 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2080 mod = 0;
2081 else if (input->eaflags & EAF_BYTEOFFS ||
2082 (o >= -128 && o <= 127 && seg == NO_SEG
2083 && !forw_ref
2084 && !(input->eaflags & EAF_WORDOFFS)))
2085 mod = 1;
2086 else
2087 mod = 2;
2088 }
2089
2090 output->sib_present = true;
2091 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2092 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2093 output->sib = (scale << 6) | (index << 3) | base;
2094 }
2095 } else { /* it's 16-bit */
2096 int mod, rm;
2097
2098 /* check for 64-bit long mode */
2099 if (addrbits == 64)
2100 return NULL;
2101
2102 /* check all registers are BX, BP, SI or DI */
2103 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI
2104 && b != R_DI) || (i != -1 && i != R_BP && i != R_BX
2105 && i != R_SI && i != R_DI))
2106 return NULL;
2107
2108 /* ensure the user didn't specify DWORD/QWORD */
2109 if (input->disp_size == 32 || input->disp_size == 64)
2110 return NULL;
2111
2112 if (s != 1 && i != -1)
2113 return NULL; /* no can do, in 16-bit EA */
2114 if (b == -1 && i != -1) {
2115 int tmp = b;
2116 b = i;
2117 i = tmp;
2118 } /* swap */
2119 if ((b == R_SI || b == R_DI) && i != -1) {
2120 int tmp = b;
2121 b = i;
2122 i = tmp;
2123 }
2124 /* have BX/BP as base, SI/DI index */
2125 if (b == i)
2126 return NULL; /* shouldn't ever happen, in theory */
2127 if (i != -1 && b != -1 &&
2128 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2129 return NULL; /* invalid combinations */
2130 if (b == -1) /* pure offset: handled above */
2131 return NULL; /* so if it gets to here, panic! */
2132
2133 rm = -1;
2134 if (i != -1)
2135 switch (i * 256 + b) {
2136 case R_SI * 256 + R_BX:
2137 rm = 0;
2138 break;
2139 case R_DI * 256 + R_BX:
2140 rm = 1;
2141 break;
2142 case R_SI * 256 + R_BP:
2143 rm = 2;
2144 break;
2145 case R_DI * 256 + R_BP:
2146 rm = 3;
2147 break;
2148 } else
2149 switch (b) {
2150 case R_SI:
2151 rm = 4;
2152 break;
2153 case R_DI:
2154 rm = 5;
2155 break;
2156 case R_BP:
2157 rm = 6;
2158 break;
2159 case R_BX:
2160 rm = 7;
2161 break;
2162 }
2163 if (rm == -1) /* can't happen, in theory */
2164 return NULL; /* so panic if it does */
2165
2166 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2167 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2168 mod = 0;
2169 else if (input->eaflags & EAF_BYTEOFFS ||
2170 (o >= -128 && o <= 127 && seg == NO_SEG
2171 && !forw_ref
2172 && !(input->eaflags & EAF_WORDOFFS)))
2173 mod = 1;
2174 else
2175 mod = 2;
2176
2177 output->sib_present = false; /* no SIB - it's 16-bit */
2178 output->bytes = mod; /* bytes of offset needed */
2179 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2180 }
2181 }
2182 }
2183
2184 output->size = 1 + output->sib_present + output->bytes;
2185 return output;
2186 }
2187
2188 static void add_asp(insn *ins, int addrbits)
2189 {
2190 int j, valid;
2191 int defdisp;
2192
2193 valid = (addrbits == 64) ? 64|32 : 32|16;
2194
2195 switch (ins->prefixes[PPS_ASIZE]) {
2196 case P_A16:
2197 valid &= 16;
2198 break;
2199 case P_A32:
2200 valid &= 32;
2201 break;
2202 case P_A64:
2203 valid &= 64;
2204 break;
2205 case P_ASP:
2206 valid &= (addrbits == 32) ? 16 : 32;
2207 break;
2208 default:
2209 break;
2210 }
2211
2212 for (j = 0; j < ins->operands; j++) {
2213 if (!(MEMORY & ~ins->oprs[j].type)) {
2214 int32_t i, b;
2215
2216 /* Verify as Register */
2217 if (ins->oprs[j].indexreg < EXPR_REG_START
2218 || ins->oprs[j].indexreg >= REG_ENUM_LIMIT)
2219 i = 0;
2220 else
2221 i = reg_flags[ins->oprs[j].indexreg];
2222
2223 /* Verify as Register */
2224 if (ins->oprs[j].basereg < EXPR_REG_START
2225 || ins->oprs[j].basereg >= REG_ENUM_LIMIT)
2226 b = 0;
2227 else
2228 b = reg_flags[ins->oprs[j].basereg];
2229
2230 if (ins->oprs[j].scale == 0)
2231 i = 0;
2232
2233 if (!i && !b) {
2234 int ds = ins->oprs[j].disp_size;
2235 if ((addrbits != 64 && ds > 8) ||
2236 (addrbits == 64 && ds == 16))
2237 valid &= ds;
2238 } else {
2239 if (!(REG16 & ~b))
2240 valid &= 16;
2241 if (!(REG32 & ~b))
2242 valid &= 32;
2243 if (!(REG64 & ~b))
2244 valid &= 64;
2245
2246 if (!(REG16 & ~i))
2247 valid &= 16;
2248 if (!(REG32 & ~i))
2249 valid &= 32;
2250 if (!(REG64 & ~i))
2251 valid &= 64;
2252 }
2253 }
2254 }
2255
2256 if (valid & addrbits) {
2257 ins->addr_size = addrbits;
2258 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2259 /* Add an address size prefix */
2260 enum prefixes pref = (addrbits == 32) ? P_A16 : P_A32;
2261 ins->prefixes[PPS_ASIZE] = pref;
2262 ins->addr_size = (addrbits == 32) ? 16 : 32;
2263 } else {
2264 /* Impossible... */
2265 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2266 ins->addr_size = addrbits; /* Error recovery */
2267 }
2268
2269 defdisp = ins->addr_size == 16 ? 16 : 32;
2270
2271 for (j = 0; j < ins->operands; j++) {
2272 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2273 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp)
2274 != ins->addr_size) {
2275 /* mem_offs sizes must match the address size; if not,
2276 strip the MEM_OFFS bit and match only EA instructions */
2277 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2278 }
2279 }
2280 }
Automatic testing