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Fix literal F2 and F3 prefixes
[nasm/autotest.git] / assemble.c
blob5452271297296e34bac346c64e389a8612a3209d
1 /* assemble.c code generation for the Netwide Assembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the licence given in the file "Licence"
6 * distributed in the NASM archive.
7 *
8 * the actual codes (C syntax, i.e. octal):
9 * \0 - terminates the code. (Unless it's a literal of course.)
10 * \1, \2, \3 - that many literal bytes follow in the code stream
11 * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
12 * (POP is never used for CS) depending on operand 0
13 * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
14 * on operand 0
15 * \10, \11, \12 - a literal byte follows in the code stream, to be added
16 * to the register value of operand 0, 1 or 2
17 * \17 - encodes the literal byte 0. (Some compilers don't take
18 * kindly to a zero byte in the _middle_ of a compile time
19 * string constant, so I had to put this hack in.)
20 * \14, \15, \16 - a signed byte immediate operand, from operand 0, 1 or 2
21 * \20, \21, \22 - a byte immediate operand, from operand 0, 1 or 2
22 * \24, \25, \26 - an unsigned byte immediate operand, from operand 0, 1 or 2
23 * \30, \31, \32 - a word immediate operand, from operand 0, 1 or 2
24 * \34, \35, \36 - select between \3[012] and \4[012] depending on 16/32 bit
25 * assembly mode or the operand-size override on the operand
26 * \37 - a word constant, from the _segment_ part of operand 0
27 * \40, \41, \42 - a long immediate operand, from operand 0, 1 or 2
28 * \44, \45, \46 - select between \3[012], \4[012] and \5[456]
29 * depending on assembly mode or the address-size override
30 * on the operand.
31 * \50, \51, \52 - a byte relative operand, from operand 0, 1 or 2
32 * \54, \55, \56 - a qword immediate operand, from operand 0, 1 or 2
33 * \60, \61, \62 - a word relative operand, from operand 0, 1 or 2
34 * \64, \65, \66 - select between \6[012] and \7[012] depending on 16/32 bit
35 * assembly mode or the operand-size override on the operand
36 * \70, \71, \72 - a long relative operand, from operand 0, 1 or 2
37 * \1ab - a ModRM, calculated on EA in operand a, with the spare
38 * field the register value of operand b.
39 * \130,\131,\132 - an immediate word or signed byte for operand 0, 1, or 2
40 * \133,\134,\135 - or 2 (s-field) into next opcode byte if operand 0, 1, or 2
41 * is a signed byte rather than a word.
42 * \140,\141,\142 - an immediate dword or signed byte for operand 0, 1, or 2
43 * \143,\144,\145 - or 2 (s-field) into next opcode byte if operand 0, 1, or 2
44 * is a signed byte rather than a dword.
45 * \150,\151,\152 - an immediate qword or signed byte for operand 0, 1, or 2
46 * \153,\154,\155 - or 2 (s-field) into next opcode byte if operand 0, 1, or 2
47 * is a signed byte rather than a qword.
48 * \2ab - a ModRM, calculated on EA in operand a, with the spare
49 * field equal to digit b.
50 * \30x - might be an 0x67 byte, depending on the address size of
51 * the memory reference in operand x.
52 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
53 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
54 * \312 - (disassembler only) marker on LOOP, LOOPxx instructions.
55 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
56 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
57 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
58 * \322 - indicates that this instruction is only valid when the
59 * operand size is the default (instruction to disassembler,
60 * generates no code in the assembler)
61 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
62 * \324 - indicates 64-bit operand size requiring REX prefix.
63 * \330 - a literal byte follows in the code stream, to be added
64 * to the condition code value of the instruction.
65 * \331 - instruction not valid with REP prefix. Hint for
66 * disassembler only; for SSE instructions.
67 * \332 - REP prefix (0xF2 byte) used as opcode extension.
68 * \333 - REP prefix (0xF3 byte) used as opcode extension.
69 * \334 - LOCK prefix used instead of REX.R
70 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
71 * \340 - reserve <operand 0> bytes of uninitialized storage.
72 * Operand 0 had better be a segmentless constant.
73 * \364 - operand-size prefix (0x66) not permitted
74 * \365 - address-size prefix (0x67) not permitted
75 * \366 - operand-size prefix (0x66) used as opcode extension
76 * \367 - address-size prefix (0x67) used as opcode extension
77 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
78 * 370 is used for Jcc, 371 is used for JMP.
79 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
80 * used for conditional jump over longer jump
81 */
82
83 #include <stdio.h>
84 #include <string.h>
85 #include <inttypes.h>
86
87 #include "nasm.h"
88 #include "nasmlib.h"
89 #include "assemble.h"
90 #include "insns.h"
91 #include "preproc.h"
92 #include "regflags.c"
93 #include "regvals.c"
94
95 typedef struct {
96 int sib_present; /* is a SIB byte necessary? */
97 int bytes; /* # of bytes of offset needed */
98 int size; /* lazy - this is sib+bytes+1 */
99 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
100 } ea;
101
102 static uint32_t cpu; /* cpu level received from nasm.c */
103 static efunc errfunc;
104 static struct ofmt *outfmt;
105 static ListGen *list;
106
107 static int32_t calcsize(int32_t, int32_t, int, insn *, const char *);
108 static void gencode(int32_t, int32_t, int, insn *, const char *, int32_t);
109 static int matches(const struct itemplate *, insn *, int bits);
110 static int32_t regflag(const operand *);
111 static int32_t regval(const operand *);
112 static int rexflags(int, int32_t, int);
113 static int op_rexflags(const operand *, int);
114 static ea *process_ea(operand *, ea *, int, int, int32_t, int);
115 static int chsize(operand *, int);
116
117 static void assert_no_prefix(insn * ins, int prefix)
118 {
119 int j;
120
121 for (j = 0; j < ins->nprefix; j++) {
122 if (ins->prefixes[j] == prefix) {
123 errfunc(ERR_NONFATAL, "invalid %s prefix", prefix_name(prefix));
124 break;
125 }
126 }
127 }
128
129 /*
130 * This routine wrappers the real output format's output routine,
131 * in order to pass a copy of the data off to the listing file
132 * generator at the same time.
133 */
134 static void out(int32_t offset, int32_t segto, const void *data,
135 uint32_t type, int32_t segment, int32_t wrt)
136 {
137 static int32_t lineno = 0; /* static!!! */
138 static char *lnfname = NULL;
139
140 if ((type & OUT_TYPMASK) == OUT_ADDRESS) {
141 if (segment != NO_SEG || wrt != NO_SEG) {
142 /*
143 * This address is relocated. We must write it as
144 * OUT_ADDRESS, so there's no work to be done here.
145 */
146 list->output(offset, data, type);
147 } else {
148 uint8_t p[8], *q = p;
149 /*
150 * This is a non-relocated address, and we're going to
151 * convert it into RAWDATA format.
152 */
153 if ((type & OUT_SIZMASK) == 4) {
154 WRITELONG(q, *(int32_t *)data);
155 list->output(offset, p, OUT_RAWDATA + 4);
156 } else if ((type & OUT_SIZMASK) == 8) {
157 WRITEDLONG(q, *(int64_t *)data);
158 list->output(offset, p, OUT_RAWDATA + 8);
159 } else {
160 WRITESHORT(q, *(int32_t *)data);
161 list->output(offset, p, OUT_RAWDATA + 2);
162 }
163 }
164 } else if ((type & OUT_TYPMASK) == OUT_RAWDATA) {
165 list->output(offset, data, type);
166 } else if ((type & OUT_TYPMASK) == OUT_RESERVE) {
167 list->output(offset, NULL, type);
168 } else if ((type & OUT_TYPMASK) == OUT_REL2ADR ||
169 (type & OUT_TYPMASK) == OUT_REL4ADR) {
170 list->output(offset, data, type);
171 }
172
173 /*
174 * this call to src_get determines when we call the
175 * debug-format-specific "linenum" function
176 * it updates lineno and lnfname to the current values
177 * returning 0 if "same as last time", -2 if lnfname
178 * changed, and the amount by which lineno changed,
179 * if it did. thus, these variables must be static
180 */
181
182 if (src_get(&lineno, &lnfname)) {
183 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
184 }
185
186 outfmt->output(segto, data, type, segment, wrt);
187 }
188
189 static int jmp_match(int32_t segment, int32_t offset, int bits,
190 insn * ins, const char *code)
191 {
192 int32_t isize;
193 uint8_t c = code[0];
194
195 if (c != 0370 && c != 0371)
196 return 0;
197 if (ins->oprs[0].opflags & OPFLAG_FORWARD) {
198 if ((optimizing < 0 || (ins->oprs[0].type & STRICT))
199 && c == 0370)
200 return 1;
201 else
202 return (pass0 == 0); /* match a forward reference */
203 }
204 isize = calcsize(segment, offset, bits, ins, code);
205 if (ins->oprs[0].segment != segment)
206 return 0;
207 isize = ins->oprs[0].offset - offset - isize; /* isize is now the delta */
208 if (isize >= -128L && isize <= 127L)
209 return 1; /* it is byte size */
210
211 return 0;
212 }
213
214 int32_t assemble(int32_t segment, int32_t offset, int bits, uint32_t cp,
215 insn * instruction, struct ofmt *output, efunc error,
216 ListGen * listgen)
217 {
218 const struct itemplate *temp;
219 int j;
220 int size_prob;
221 int32_t insn_end;
222 int32_t itimes;
223 int32_t start = offset;
224 int32_t wsize = 0; /* size for DB etc. */
225
226 errfunc = error; /* to pass to other functions */
227 cpu = cp;
228 outfmt = output; /* likewise */
229 list = listgen; /* and again */
230
231 switch (instruction->opcode) {
232 case -1:
233 return 0;
234 case I_DB:
235 wsize = 1;
236 break;
237 case I_DW:
238 wsize = 2;
239 break;
240 case I_DD:
241 wsize = 4;
242 break;
243 case I_DQ:
244 wsize = 8;
245 break;
246 case I_DT:
247 wsize = 10;
248 break;
249 default:
250 break;
251 }
252
253 if (wsize) {
254 extop *e;
255 int32_t t = instruction->times;
256 if (t < 0)
257 errfunc(ERR_PANIC,
258 "instruction->times < 0 (%ld) in assemble()", t);
259
260 while (t--) { /* repeat TIMES times */
261 for (e = instruction->eops; e; e = e->next) {
262 if (e->type == EOT_DB_NUMBER) {
263 if (wsize == 1) {
264 if (e->segment != NO_SEG)
265 errfunc(ERR_NONFATAL,
266 "one-byte relocation attempted");
267 else {
268 uint8_t out_byte = e->offset;
269 out(offset, segment, &out_byte,
270 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
271 }
272 } else if (wsize > 8) {
273 errfunc(ERR_NONFATAL, "integer supplied to a DT"
274 " instruction");
275 } else
276 out(offset, segment, &e->offset,
277 OUT_ADDRESS + wsize, e->segment, e->wrt);
278 offset += wsize;
279 } else if (e->type == EOT_DB_STRING) {
280 int align;
281
282 out(offset, segment, e->stringval,
283 OUT_RAWDATA + e->stringlen, NO_SEG, NO_SEG);
284 align = e->stringlen % wsize;
285
286 if (align) {
287 align = wsize - align;
288 out(offset, segment, "\0\0\0\0\0\0\0\0",
289 OUT_RAWDATA + align, NO_SEG, NO_SEG);
290 }
291 offset += e->stringlen + align;
292 }
293 }
294 if (t > 0 && t == instruction->times - 1) {
295 /*
296 * Dummy call to list->output to give the offset to the
297 * listing module.
298 */
299 list->output(offset, NULL, OUT_RAWDATA);
300 list->uplevel(LIST_TIMES);
301 }
302 }
303 if (instruction->times > 1)
304 list->downlevel(LIST_TIMES);
305 return offset - start;
306 }
307
308 if (instruction->opcode == I_INCBIN) {
309 static char fname[FILENAME_MAX];
310 FILE *fp;
311 int32_t len;
312 char *prefix = "", *combine;
313 char **pPrevPath = NULL;
314
315 len = FILENAME_MAX - 1;
316 if (len > instruction->eops->stringlen)
317 len = instruction->eops->stringlen;
318 strncpy(fname, instruction->eops->stringval, len);
319 fname[len] = '\0';
320
321 while (1) { /* added by alexfru: 'incbin' uses include paths */
322 combine = nasm_malloc(strlen(prefix) + len + 1);
323 strcpy(combine, prefix);
324 strcat(combine, fname);
325
326 if ((fp = fopen(combine, "rb")) != NULL) {
327 nasm_free(combine);
328 break;
329 }
330
331 nasm_free(combine);
332 pPrevPath = pp_get_include_path_ptr(pPrevPath);
333 if (pPrevPath == NULL)
334 break;
335 prefix = *pPrevPath;
336 }
337
338 if (fp == NULL)
339 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
340 fname);
341 else if (fseek(fp, 0L, SEEK_END) < 0)
342 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
343 fname);
344 else {
345 static char buf[2048];
346 int32_t t = instruction->times;
347 int32_t base = 0;
348
349 len = ftell(fp);
350 if (instruction->eops->next) {
351 base = instruction->eops->next->offset;
352 len -= base;
353 if (instruction->eops->next->next &&
354 len > instruction->eops->next->next->offset)
355 len = instruction->eops->next->next->offset;
356 }
357 /*
358 * Dummy call to list->output to give the offset to the
359 * listing module.
360 */
361 list->output(offset, NULL, OUT_RAWDATA);
362 list->uplevel(LIST_INCBIN);
363 while (t--) {
364 int32_t l;
365
366 fseek(fp, base, SEEK_SET);
367 l = len;
368 while (l > 0) {
369 int32_t m =
370 fread(buf, 1, (l > sizeof(buf) ? sizeof(buf) : l),
371 fp);
372 if (!m) {
373 /*
374 * This shouldn't happen unless the file
375 * actually changes while we are reading
376 * it.
377 */
378 error(ERR_NONFATAL,
379 "`incbin': unexpected EOF while"
380 " reading file `%s'", fname);
381 t = 0; /* Try to exit cleanly */
382 break;
383 }
384 out(offset, segment, buf, OUT_RAWDATA + m,
385 NO_SEG, NO_SEG);
386 l -= m;
387 }
388 }
389 list->downlevel(LIST_INCBIN);
390 if (instruction->times > 1) {
391 /*
392 * Dummy call to list->output to give the offset to the
393 * listing module.
394 */
395 list->output(offset, NULL, OUT_RAWDATA);
396 list->uplevel(LIST_TIMES);
397 list->downlevel(LIST_TIMES);
398 }
399 fclose(fp);
400 return instruction->times * len;
401 }
402 return 0; /* if we're here, there's an error */
403 }
404
405 size_prob = FALSE;
406
407 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++){
408 int m = matches(temp, instruction, bits);
409
410 if (m == 99)
411 m += jmp_match(segment, offset, bits, instruction, temp->code);
412
413 if (m == 100) { /* matches! */
414 const char *codes = temp->code;
415 int32_t insn_size = calcsize(segment, offset, bits,
416 instruction, codes);
417 itimes = instruction->times;
418 if (insn_size < 0) /* shouldn't be, on pass two */
419 error(ERR_PANIC, "errors made it through from pass one");
420 else
421 while (itimes--) {
422 for (j = 0; j < instruction->nprefix; j++) {
423 uint8_t c = 0;
424 switch (instruction->prefixes[j]) {
425 case P_LOCK:
426 c = 0xF0;
427 break;
428 case P_REPNE:
429 case P_REPNZ:
430 c = 0xF2;
431 break;
432 case P_REPE:
433 case P_REPZ:
434 case P_REP:
435 c = 0xF3;
436 break;
437 case R_CS:
438 if (bits == 64) {
439 error(ERR_WARNING,
440 "cs segment base ignored in 64-bit mode");
441 }
442 c = 0x2E;
443 break;
444 case R_DS:
445 if (bits == 64) {
446 error(ERR_WARNING,
447 "ds segment base ignored in 64-bit mode");
448 }
449 c = 0x3E;
450 break;
451 case R_ES:
452 if (bits == 64) {
453 error(ERR_WARNING,
454 "es segment base ignored in 64-bit mode");
455 }
456 c = 0x26;
457 break;
458 case R_FS:
459 c = 0x64;
460 break;
461 case R_GS:
462 c = 0x65;
463 break;
464 case R_SS:
465 if (bits == 64) {
466 error(ERR_WARNING,
467 "ss segment base ignored in 64-bit mode");
468 }
469 c = 0x36;
470 break;
471 case R_SEGR6:
472 case R_SEGR7:
473 error(ERR_NONFATAL,
474 "segr6 and segr7 cannot be used as prefixes");
475 break;
476 case P_A16:
477 if (bits == 64) {
478 error(ERR_NONFATAL,
479 "16-bit addressing is not supported "
480 "in 64-bit mode");
481 break;
482 }
483 if (bits != 16)
484 c = 0x67;
485 break;
486 case P_A32:
487 if (bits != 32)
488 c = 0x67;
489 break;
490 case P_O16:
491 if (bits != 16)
492 c = 0x66;
493 break;
494 case P_O32:
495 if (bits == 16)
496 c = 0x66;
497 break;
498 default:
499 error(ERR_PANIC, "invalid instruction prefix");
500 }
501 if (c != 0) {
502 out(offset, segment, &c, OUT_RAWDATA + 1,
503 NO_SEG, NO_SEG);
504 offset++;
505 }
506 }
507 insn_end = offset + insn_size;
508 gencode(segment, offset, bits, instruction, codes,
509 insn_end);
510 offset += insn_size;
511 if (itimes > 0 && itimes == instruction->times - 1) {
512 /*
513 * Dummy call to list->output to give the offset to the
514 * listing module.
515 */
516 list->output(offset, NULL, OUT_RAWDATA);
517 list->uplevel(LIST_TIMES);
518 }
519 }
520 if (instruction->times > 1)
521 list->downlevel(LIST_TIMES);
522 return offset - start;
523 } else if (m > 0 && m > size_prob) {
524 size_prob = m;
525 }
526 // temp++;
527 }
528
529 if (temp->opcode == -1) { /* didn't match any instruction */
530 switch (size_prob) {
531 case 1:
532 error(ERR_NONFATAL, "operation size not specified");
533 break;
534 case 2:
535 error(ERR_NONFATAL, "mismatch in operand sizes");
536 break;
537 case 3:
538 error(ERR_NONFATAL, "no instruction for this cpu level");
539 break;
540 case 4:
541 error(ERR_NONFATAL, "instruction not supported in 64-bit mode");
542 break;
543 default:
544 error(ERR_NONFATAL,
545 "invalid combination of opcode and operands");
546 break;
547 }
548 }
549 return 0;
550 }
551
552 int32_t insn_size(int32_t segment, int32_t offset, int bits, uint32_t cp,
553 insn * instruction, efunc error)
554 {
555 const struct itemplate *temp;
556
557 errfunc = error; /* to pass to other functions */
558 cpu = cp;
559
560 if (instruction->opcode == -1)
561 return 0;
562
563 if (instruction->opcode == I_DB ||
564 instruction->opcode == I_DW ||
565 instruction->opcode == I_DD ||
566 instruction->opcode == I_DQ || instruction->opcode == I_DT) {
567 extop *e;
568 int32_t isize, osize, wsize = 0; /* placate gcc */
569
570 isize = 0;
571 switch (instruction->opcode) {
572 case I_DB:
573 wsize = 1;
574 break;
575 case I_DW:
576 wsize = 2;
577 break;
578 case I_DD:
579 wsize = 4;
580 break;
581 case I_DQ:
582 wsize = 8;
583 break;
584 case I_DT:
585 wsize = 10;
586 break;
587 default:
588 break;
589 }
590
591 for (e = instruction->eops; e; e = e->next) {
592 int32_t align;
593
594 osize = 0;
595 if (e->type == EOT_DB_NUMBER)
596 osize = 1;
597 else if (e->type == EOT_DB_STRING)
598 osize = e->stringlen;
599
600 align = (-osize) % wsize;
601 if (align < 0)
602 align += wsize;
603 isize += osize + align;
604 }
605 return isize * instruction->times;
606 }
607
608 if (instruction->opcode == I_INCBIN) {
609 char fname[FILENAME_MAX];
610 FILE *fp;
611 int32_t len;
612 char *prefix = "", *combine;
613 char **pPrevPath = NULL;
614
615 len = FILENAME_MAX - 1;
616 if (len > instruction->eops->stringlen)
617 len = instruction->eops->stringlen;
618 strncpy(fname, instruction->eops->stringval, len);
619 fname[len] = '\0';
620
621 while (1) { /* added by alexfru: 'incbin' uses include paths */
622 combine = nasm_malloc(strlen(prefix) + len + 1);
623 strcpy(combine, prefix);
624 strcat(combine, fname);
625
626 if ((fp = fopen(combine, "rb")) != NULL) {
627 nasm_free(combine);
628 break;
629 }
630
631 nasm_free(combine);
632 pPrevPath = pp_get_include_path_ptr(pPrevPath);
633 if (pPrevPath == NULL)
634 break;
635 prefix = *pPrevPath;
636 }
637
638 if (fp == NULL)
639 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
640 fname);
641 else if (fseek(fp, 0L, SEEK_END) < 0)
642 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
643 fname);
644 else {
645 len = ftell(fp);
646 fclose(fp);
647 if (instruction->eops->next) {
648 len -= instruction->eops->next->offset;
649 if (instruction->eops->next->next &&
650 len > instruction->eops->next->next->offset) {
651 len = instruction->eops->next->next->offset;
652 }
653 }
654 return instruction->times * len;
655 }
656 return 0; /* if we're here, there's an error */
657 }
658
659 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++) {
660 int m = matches(temp, instruction, bits);
661 if (m == 99)
662 m += jmp_match(segment, offset, bits, instruction, temp->code);
663
664 if (m == 100) {
665 /* we've matched an instruction. */
666 int32_t isize;
667 const char *codes = temp->code;
668 int j;
669
670 isize = calcsize(segment, offset, bits, instruction, codes);
671 if (isize < 0)
672 return -1;
673 for (j = 0; j < instruction->nprefix; j++) {
674 if ((instruction->prefixes[j] != P_A16 &&
675 instruction->prefixes[j] != P_O16 && bits == 16) ||
676 (instruction->prefixes[j] != P_A32 &&
677 instruction->prefixes[j] != P_O32 && bits >= 32)) {
678 isize++;
679 }
680 }
681 return isize * instruction->times;
682 }
683 }
684 return -1; /* didn't match any instruction */
685 }
686
687 /* check that opn[op] is a signed byte of size 16 or 32,
688 and return the signed value*/
689 static int is_sbyte(insn * ins, int op, int size)
690 {
691 int32_t v;
692 int ret;
693
694 ret = !(ins->forw_ref && ins->oprs[op].opflags) && /* dead in the water on forward reference or External */
695 optimizing >= 0 &&
696 !(ins->oprs[op].type & STRICT) &&
697 ins->oprs[op].wrt == NO_SEG && ins->oprs[op].segment == NO_SEG;
698
699 v = ins->oprs[op].offset;
700 if (size == 16)
701 v = (int16_t)v; /* sign extend if 16 bits */
702
703 return ret && v >= -128L && v <= 127L;
704 }
705
706 static int32_t calcsize(int32_t segment, int32_t offset, int bits,
707 insn * ins, const char *codes)
708 {
709 int32_t length = 0;
710 uint8_t c;
711 int rex_mask = ~0;
712 ins->rex = 0; /* Ensure REX is reset */
713
714 (void)segment; /* Don't warn that this parameter is unused */
715 (void)offset; /* Don't warn that this parameter is unused */
716
717 while (*codes)
718 switch (c = *codes++) {
719 case 01:
720 case 02:
721 case 03:
722 codes += c, length += c;
723 break;
724 case 04:
725 case 05:
726 case 06:
727 case 07:
728 length++;
729 break;
730 case 010:
731 case 011:
732 case 012:
733 ins->rex |=
734 op_rexflags(&ins->oprs[c - 010], REX_B|REX_H|REX_P|REX_W);
735 codes++, length++;
736 break;
737 case 017:
738 length++;
739 break;
740 case 014:
741 case 015:
742 case 016:
743 length++;
744 break;
745 case 020:
746 case 021:
747 case 022:
748 length++;
749 break;
750 case 024:
751 case 025:
752 case 026:
753 length++;
754 break;
755 case 030:
756 case 031:
757 case 032:
758 length += 2;
759 break;
760 case 034:
761 case 035:
762 case 036:
763 if (ins->oprs[c - 034].type & (BITS16 | BITS32 | BITS64))
764 length += (ins->oprs[c - 034].type & BITS16) ? 2 : 4;
765 else
766 length += (bits == 16) ? 2 : 4;
767 break;
768 case 037:
769 length += 2;
770 break;
771 case 040:
772 case 041:
773 case 042:
774 length += 4;
775 break;
776 case 044:
777 case 045:
778 case 046:
779 length += ((ins->oprs[c - 044].addr_size ?
780 ins->oprs[c - 044].addr_size : bits) >> 3);
781 break;
782 case 050:
783 case 051:
784 case 052:
785 length++;
786 break;
787 case 054:
788 case 055:
789 case 056:
790 length += 8; /* MOV reg64/imm */
791 break;
792 case 060:
793 case 061:
794 case 062:
795 length += 2;
796 break;
797 case 064:
798 case 065:
799 case 066:
800 if (ins->oprs[c - 064].type & (BITS16 | BITS32 | BITS64))
801 length += (ins->oprs[c - 064].type & BITS16) ? 2 : 4;
802 else
803 length += (bits == 16) ? 2 : 4;
804 break;
805 case 070:
806 case 071:
807 case 072:
808 length += 4;
809 break;
810 case 0130:
811 case 0131:
812 case 0132:
813 length += is_sbyte(ins, c - 0130, 16) ? 1 : 2;
814 break;
815 case 0133:
816 case 0134:
817 case 0135:
818 codes += 2;
819 length++;
820 break;
821 case 0140:
822 case 0141:
823 case 0142:
824 length += is_sbyte(ins, c - 0140, 32) ? 1 : 4;
825 break;
826 case 0143:
827 case 0144:
828 case 0145:
829 codes += 2;
830 length++;
831 break;
832 case 0300:
833 case 0301:
834 case 0302:
835 length += chsize(&ins->oprs[c - 0300], bits);
836 break;
837 case 0310:
838 length += (bits != 16);
839 break;
840 case 0311:
841 length += (bits != 32);
842 break;
843 case 0312:
844 break;
845 case 0313:
846 break;
847 case 0320:
848 length += (bits != 16);
849 break;
850 case 0321:
851 length += (bits == 16);
852 break;
853 case 0322:
854 break;
855 case 0323:
856 rex_mask &= ~REX_W;
857 break;
858 case 0324:
859 ins->rex |= REX_W;
860 break;
861 case 0330:
862 codes++, length++;
863 break;
864 case 0331:
865 break;
866 case 0332:
867 case 0333:
868 length++;
869 break;
870 case 0334:
871 assert_no_prefix(ins, P_LOCK);
872 ins->rex |= REX_L;
873 break;
874 case 0335:
875 break;
876 case 0340:
877 case 0341:
878 case 0342:
879 if (ins->oprs[0].segment != NO_SEG)
880 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
881 " quantity of BSS space");
882 else
883 length += ins->oprs[0].offset << (c - 0340);
884 break;
885 case 0364:
886 case 0365:
887 break;
888 case 0366:
889 case 0367:
890 length++;
891 break;
892 case 0370:
893 case 0371:
894 case 0372:
895 break;
896 case 0373:
897 length++;
898 break;
899 default: /* can't do it by 'case' statements */
900 if (c >= 0100 && c <= 0277) { /* it's an EA */
901 ea ea_data;
902 int rfield;
903 int32_t rflags;
904 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
905
906 if (c <= 0177) {
907 /* pick rfield from operand b */
908 rflags = regflag(&ins->oprs[c & 7]);
909 rfield = regvals[ins->oprs[c & 7].basereg];
910 } else {
911 rflags = 0;
912 rfield = c & 7;
913 }
914
915 if (!process_ea
916 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
917 rfield, rflags, ins->forw_ref)) {
918 errfunc(ERR_NONFATAL, "invalid effective address");
919 return -1;
920 } else {
921 ins->rex |= ea_data.rex;
922 length += ea_data.size;
923 }
924 } else
925 errfunc(ERR_PANIC, "internal instruction table corrupt"
926 ": instruction code 0x%02X given", c);
927 }
928
929 ins->rex &= rex_mask;
930 if (ins->rex & REX_REAL) {
931 if (ins->rex & REX_H) {
932 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
933 return -1;
934 } else if (bits == 64 ||
935 ((ins->rex & REX_L) &&
936 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
937 cpu >= IF_X86_64)) {
938 length++;
939 } else {
940 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
941 return -1;
942 }
943 }
944
945 return length;
946 }
947
948 #define EMIT_REX() \
949 if((ins->rex & REX_REAL) && (bits == 64)) { \
950 ins->rex = (ins->rex & REX_REAL)|REX_P; \
951 out(offset, segment, &ins->rex, OUT_RAWDATA+1, NO_SEG, NO_SEG); \
952 ins->rex = 0; \
953 offset += 1; \
954 }
955
956 static void gencode(int32_t segment, int32_t offset, int bits,
957 insn * ins, const char *codes, int32_t insn_end)
958 {
959 static char condval[] = { /* conditional opcodes */
960 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
961 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
962 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
963 };
964 uint8_t c;
965 uint8_t bytes[4];
966 int32_t size;
967 int64_t data;
968
969 while (*codes)
970 switch (c = *codes++) {
971 case 01:
972 case 02:
973 case 03:
974 EMIT_REX();
975 out(offset, segment, codes, OUT_RAWDATA + c, NO_SEG, NO_SEG);
976 codes += c;
977 offset += c;
978 break;
979
980 case 04:
981 case 06:
982 switch (ins->oprs[0].basereg) {
983 case R_CS:
984 bytes[0] = 0x0E + (c == 0x04 ? 1 : 0);
985 break;
986 case R_DS:
987 bytes[0] = 0x1E + (c == 0x04 ? 1 : 0);
988 break;
989 case R_ES:
990 bytes[0] = 0x06 + (c == 0x04 ? 1 : 0);
991 break;
992 case R_SS:
993 bytes[0] = 0x16 + (c == 0x04 ? 1 : 0);
994 break;
995 default:
996 errfunc(ERR_PANIC,
997 "bizarre 8086 segment register received");
998 }
999 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1000 offset++;
1001 break;
1002
1003 case 05:
1004 case 07:
1005 switch (ins->oprs[0].basereg) {
1006 case R_FS:
1007 bytes[0] = 0xA0 + (c == 0x05 ? 1 : 0);
1008 break;
1009 case R_GS:
1010 bytes[0] = 0xA8 + (c == 0x05 ? 1 : 0);
1011 break;
1012 default:
1013 errfunc(ERR_PANIC,
1014 "bizarre 386 segment register received");
1015 }
1016 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1017 offset++;
1018 break;
1019
1020 case 010:
1021 case 011:
1022 case 012:
1023 EMIT_REX();
1024 bytes[0] = *codes++ + ((regval(&ins->oprs[c - 010])) & 7);
1025 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1026 offset += 1;
1027 break;
1028
1029 case 017:
1030 bytes[0] = 0;
1031 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1032 offset += 1;
1033 break;
1034
1035 case 014:
1036 case 015:
1037 case 016:
1038 if (ins->oprs[c - 014].offset < -128
1039 || ins->oprs[c - 014].offset > 127) {
1040 errfunc(ERR_WARNING, "signed byte value exceeds bounds");
1041 }
1042
1043 if (ins->oprs[c - 014].segment != NO_SEG) {
1044 data = ins->oprs[c - 014].offset;
1045 out(offset, segment, &data, OUT_ADDRESS + 1,
1046 ins->oprs[c - 014].segment, ins->oprs[c - 014].wrt);
1047 } else {
1048 bytes[0] = ins->oprs[c - 014].offset;
1049 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG,
1050 NO_SEG);
1051 }
1052 offset += 1;
1053 break;
1054
1055 case 020:
1056 case 021:
1057 case 022:
1058 if (ins->oprs[c - 020].offset < -256
1059 || ins->oprs[c - 020].offset > 255) {
1060 errfunc(ERR_WARNING, "byte value exceeds bounds");
1061 }
1062 if (ins->oprs[c - 020].segment != NO_SEG) {
1063 data = ins->oprs[c - 020].offset;
1064 out(offset, segment, &data, OUT_ADDRESS + 1,
1065 ins->oprs[c - 020].segment, ins->oprs[c - 020].wrt);
1066 } else {
1067 bytes[0] = ins->oprs[c - 020].offset;
1068 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG,
1069 NO_SEG);
1070 }
1071 offset += 1;
1072 break;
1073
1074 case 024:
1075 case 025:
1076 case 026:
1077 if (ins->oprs[c - 024].offset < 0
1078 || ins->oprs[c - 024].offset > 255)
1079 errfunc(ERR_WARNING, "unsigned byte value exceeds bounds");
1080 if (ins->oprs[c - 024].segment != NO_SEG) {
1081 data = ins->oprs[c - 024].offset;
1082 out(offset, segment, &data, OUT_ADDRESS + 1,
1083 ins->oprs[c - 024].segment, ins->oprs[c - 024].wrt);
1084 } else {
1085 bytes[0] = ins->oprs[c - 024].offset;
1086 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG,
1087 NO_SEG);
1088 }
1089 offset += 1;
1090 break;
1091
1092 case 030:
1093 case 031:
1094 case 032:
1095 if (ins->oprs[c - 030].segment == NO_SEG &&
1096 ins->oprs[c - 030].wrt == NO_SEG &&
1097 (ins->oprs[c - 030].offset < -65536L ||
1098 ins->oprs[c - 030].offset > 65535L)) {
1099 errfunc(ERR_WARNING, "word value exceeds bounds");
1100 }
1101 data = ins->oprs[c - 030].offset;
1102 out(offset, segment, &data, OUT_ADDRESS + 2,
1103 ins->oprs[c - 030].segment, ins->oprs[c - 030].wrt);
1104 offset += 2;
1105 break;
1106
1107 case 034:
1108 case 035:
1109 case 036:
1110 if (ins->oprs[c - 034].type & (BITS16 | BITS32))
1111 size = (ins->oprs[c - 034].type & BITS16) ? 2 : 4;
1112 else
1113 size = (bits == 16) ? 2 : 4;
1114 data = ins->oprs[c - 034].offset;
1115 if (size == 2 && (data < -65536L || data > 65535L))
1116 errfunc(ERR_WARNING, "word value exceeds bounds");
1117 out(offset, segment, &data, OUT_ADDRESS + size,
1118 ins->oprs[c - 034].segment, ins->oprs[c - 034].wrt);
1119 offset += size;
1120 break;
1121
1122 case 037:
1123 if (ins->oprs[0].segment == NO_SEG)
1124 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1125 " relocatable");
1126 data = 0L;
1127 out(offset, segment, &data, OUT_ADDRESS + 2,
1128 outfmt->segbase(1 + ins->oprs[0].segment),
1129 ins->oprs[0].wrt);
1130 offset += 2;
1131 break;
1132
1133 case 040:
1134 case 041:
1135 case 042:
1136 data = ins->oprs[c - 040].offset;
1137 out(offset, segment, &data, OUT_ADDRESS + 4,
1138 ins->oprs[c - 040].segment, ins->oprs[c - 040].wrt);
1139 offset += 4;
1140 break;
1141
1142 case 044:
1143 case 045:
1144 case 046:
1145 data = ins->oprs[c - 044].offset;
1146 size = ((ins->oprs[c - 044].addr_size ?
1147 ins->oprs[c - 044].addr_size : bits) >> 3);
1148 if (size == 2 && (data < -65536L || data > 65535L))
1149 errfunc(ERR_WARNING, "word value exceeds bounds");
1150 out(offset, segment, &data, OUT_ADDRESS + size,
1151 ins->oprs[c - 044].segment, ins->oprs[c - 044].wrt);
1152 offset += size;
1153 break;
1154
1155 case 050:
1156 case 051:
1157 case 052:
1158 if (ins->oprs[c - 050].segment != segment)
1159 errfunc(ERR_NONFATAL,
1160 "short relative jump outside segment");
1161 data = ins->oprs[c - 050].offset - insn_end;
1162 if (data > 127 || data < -128)
1163 errfunc(ERR_NONFATAL, "short jump is out of range");
1164 bytes[0] = data;
1165 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1166 offset += 1;
1167 break;
1168
1169 case 054:
1170 case 055:
1171 case 056:
1172 data = (int64_t)ins->oprs[c - 054].offset;
1173 out(offset, segment, &data, OUT_ADDRESS + 8,
1174 ins->oprs[c - 054].segment, ins->oprs[c - 054].wrt);
1175 offset += 8;
1176 break;
1177
1178 case 060:
1179 case 061:
1180 case 062:
1181 if (ins->oprs[c - 060].segment != segment) {
1182 data = ins->oprs[c - 060].offset;
1183 out(offset, segment, &data,
1184 OUT_REL2ADR + insn_end - offset,
1185 ins->oprs[c - 060].segment, ins->oprs[c - 060].wrt);
1186 } else {
1187 data = ins->oprs[c - 060].offset - insn_end;
1188 out(offset, segment, &data,
1189 OUT_ADDRESS + 2, NO_SEG, NO_SEG);
1190 }
1191 offset += 2;
1192 break;
1193
1194 case 064:
1195 case 065:
1196 case 066:
1197 if (ins->oprs[c - 064].type & (BITS16 | BITS32 | BITS64))
1198 size = (ins->oprs[c - 064].type & BITS16) ? 2 : 4;
1199 else
1200 size = (bits == 16) ? 2 : 4;
1201 if (ins->oprs[c - 064].segment != segment) {
1202 int32_t reltype = (size == 2 ? OUT_REL2ADR : OUT_REL4ADR);
1203 data = ins->oprs[c - 064].offset;
1204 out(offset, segment, &data, reltype + insn_end - offset,
1205 ins->oprs[c - 064].segment, ins->oprs[c - 064].wrt);
1206 } else {
1207 data = ins->oprs[c - 064].offset - insn_end;
1208 out(offset, segment, &data,
1209 OUT_ADDRESS + size, NO_SEG, NO_SEG);
1210 }
1211 offset += size;
1212 break;
1213
1214 case 070:
1215 case 071:
1216 case 072:
1217 if (ins->oprs[c - 070].segment != segment) {
1218 data = ins->oprs[c - 070].offset;
1219 out(offset, segment, &data,
1220 OUT_REL4ADR + insn_end - offset,
1221 ins->oprs[c - 070].segment, ins->oprs[c - 070].wrt);
1222 } else {
1223 data = ins->oprs[c - 070].offset - insn_end;
1224 out(offset, segment, &data,
1225 OUT_ADDRESS + 4, NO_SEG, NO_SEG);
1226 }
1227 offset += 4;
1228 break;
1229
1230 case 0130:
1231 case 0131:
1232 case 0132:
1233 data = ins->oprs[c - 0130].offset;
1234 if (is_sbyte(ins, c - 0130, 16)) {
1235 bytes[0] = data;
1236 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG,
1237 NO_SEG);
1238 offset++;
1239 } else {
1240 if (ins->oprs[c - 0130].segment == NO_SEG &&
1241 ins->oprs[c - 0130].wrt == NO_SEG &&
1242 (data < -65536L || data > 65535L)) {
1243 errfunc(ERR_WARNING, "word value exceeds bounds");
1244 }
1245 out(offset, segment, &data, OUT_ADDRESS + 2,
1246 ins->oprs[c - 0130].segment, ins->oprs[c - 0130].wrt);
1247 offset += 2;
1248 }
1249 break;
1250
1251 case 0133:
1252 case 0134:
1253 case 0135:
1254 EMIT_REX();
1255 codes++;
1256 bytes[0] = *codes++;
1257 if (is_sbyte(ins, c - 0133, 16))
1258 bytes[0] |= 2; /* s-bit */
1259 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1260 offset++;
1261 break;
1262
1263 case 0140:
1264 case 0141:
1265 case 0142:
1266 data = ins->oprs[c - 0140].offset;
1267 if (is_sbyte(ins, c - 0140, 32)) {
1268 bytes[0] = data;
1269 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG,
1270 NO_SEG);
1271 offset++;
1272 } else {
1273 out(offset, segment, &data, OUT_ADDRESS + 4,
1274 ins->oprs[c - 0140].segment, ins->oprs[c - 0140].wrt);
1275 offset += 4;
1276 }
1277 break;
1278
1279 case 0143:
1280 case 0144:
1281 case 0145:
1282 EMIT_REX();
1283 codes++;
1284 bytes[0] = *codes++;
1285 if (is_sbyte(ins, c - 0143, 32))
1286 bytes[0] |= 2; /* s-bit */
1287 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1288 offset++;
1289 break;
1290
1291 case 0300:
1292 case 0301:
1293 case 0302:
1294 if (chsize(&ins->oprs[c - 0300], bits)) {
1295 *bytes = 0x67;
1296 out(offset, segment, bytes,
1297 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1298 offset += 1;
1299 } else
1300 offset += 0;
1301 break;
1302
1303 case 0310:
1304 if (bits != 16) {
1305 *bytes = 0x67;
1306 out(offset, segment, bytes,
1307 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1308 offset += 1;
1309 } else
1310 offset += 0;
1311 break;
1312
1313 case 0311:
1314 if (bits != 32) {
1315 *bytes = 0x67;
1316 out(offset, segment, bytes,
1317 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1318 offset += 1;
1319 } else
1320 offset += 0;
1321 break;
1322
1323 case 0312:
1324 break;
1325
1326 case 0313:
1327 ins->rex = 0;
1328 break;
1329
1330 case 0320:
1331 if (bits != 16) {
1332 *bytes = 0x66;
1333 out(offset, segment, bytes,
1334 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1335 offset += 1;
1336 } else
1337 offset += 0;
1338 break;
1339
1340 case 0321:
1341 if (bits == 16) {
1342 *bytes = 0x66;
1343 out(offset, segment, bytes,
1344 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1345 offset += 1;
1346 } else
1347 offset += 0;
1348 break;
1349
1350 case 0322:
1351 case 0323:
1352 break;
1353
1354 case 0324:
1355 ins->rex |= REX_W;
1356 break;
1357
1358 case 0330:
1359 *bytes = *codes++ ^ condval[ins->condition];
1360 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1361 offset += 1;
1362 break;
1363
1364 case 0331:
1365 break;
1366
1367 case 0332:
1368 case 0333:
1369 *bytes = c - 0332 + 0xF2;
1370 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1371 offset += 1;
1372 break;
1373
1374 case 0334:
1375 if (ins->rex & REX_R) {
1376 *bytes = 0xF0;
1377 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1378 offset += 1;
1379 }
1380 ins->rex &= ~(REX_L|REX_R);
1381 break;
1382
1383 case 0335:
1384 break;
1385
1386 case 0340:
1387 case 0341:
1388 case 0342:
1389 if (ins->oprs[0].segment != NO_SEG)
1390 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1391 else {
1392 int32_t size = ins->oprs[0].offset << (c - 0340);
1393 if (size > 0)
1394 out(offset, segment, NULL,
1395 OUT_RESERVE + size, NO_SEG, NO_SEG);
1396 offset += size;
1397 }
1398 break;
1399
1400 case 0364:
1401 case 0365:
1402 break;
1403
1404 case 0366:
1405 case 0367:
1406 *bytes = c - 0366 + 0x66;
1407 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1408 offset += 1;
1409 break;
1410
1411 case 0370:
1412 case 0371:
1413 case 0372:
1414 break;
1415
1416 case 0373:
1417 *bytes = bits == 16 ? 3 : 5;
1418 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1419 offset += 1;
1420 break;
1421
1422 default: /* can't do it by 'case' statements */
1423 if (c >= 0100 && c <= 0277) { /* it's an EA */
1424 ea ea_data;
1425 int rfield;
1426 int32_t rflags;
1427 uint8_t *p;
1428 int32_t s;
1429
1430 if (c <= 0177) {
1431 /* pick rfield from operand b */
1432 rflags = regflag(&ins->oprs[c & 7]);
1433 rfield = regvals[ins->oprs[c & 7].basereg];
1434 } else {
1435 /* rfield is constant */
1436 rflags = 0;
1437 rfield = c & 7;
1438 }
1439
1440 if (!process_ea
1441 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1442 rfield, rflags, ins->forw_ref)) {
1443 errfunc(ERR_NONFATAL, "invalid effective address");
1444 }
1445
1446 p = bytes;
1447 *p++ = ea_data.modrm;
1448 if (ea_data.sib_present)
1449 *p++ = ea_data.sib;
1450
1451 s = p - bytes;
1452 out(offset, segment, bytes, OUT_RAWDATA + s,
1453 NO_SEG, NO_SEG);
1454
1455 switch (ea_data.bytes) {
1456 case 0:
1457 break;
1458 case 1:
1459 if (ins->oprs[(c >> 3) & 7].segment != NO_SEG) {
1460 data = ins->oprs[(c >> 3) & 7].offset;
1461 out(offset, segment, &data, OUT_ADDRESS + 1,
1462 ins->oprs[(c >> 3) & 7].segment,
1463 ins->oprs[(c >> 3) & 7].wrt);
1464 } else {
1465 *bytes = ins->oprs[(c >> 3) & 7].offset;
1466 out(offset, segment, bytes, OUT_RAWDATA + 1,
1467 NO_SEG, NO_SEG);
1468 }
1469 s++;
1470 break;
1471 case 8:
1472 case 2:
1473 case 4:
1474 data = ins->oprs[(c >> 3) & 7].offset;
1475 if (ea_data.rip && (ins->oprs[(c >> 3) & 7].segment == 0xFFFFFFFF))
1476 ea_data.rip = 0; /* Make distinction between Symbols and Immediates */
1477 out(offset, segment, &data, /* RIP = Relative, not Absolute */
1478 (ea_data.rip ? OUT_REL4ADR : OUT_ADDRESS) + ea_data.bytes,
1479 ins->oprs[(c >> 3) & 7].segment,
1480 ins->oprs[(c >> 3) & 7].wrt);
1481 s += ea_data.bytes;
1482 break;
1483 }
1484 offset += s;
1485 } else
1486 errfunc(ERR_PANIC, "internal instruction table corrupt"
1487 ": instruction code 0x%02X given", c);
1488 }
1489 }
1490
1491 static int32_t regflag(const operand * o)
1492 {
1493 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1494 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1495 }
1496 return reg_flags[o->basereg];
1497 }
1498
1499 static int32_t regval(const operand * o)
1500 {
1501 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1502 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1503 }
1504 return regvals[o->basereg];
1505 }
1506
1507 static int op_rexflags(const operand * o, int mask)
1508 {
1509 int32_t flags;
1510 int val;
1511
1512 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1513 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1514 }
1515
1516 flags = reg_flags[o->basereg];
1517 val = regvals[o->basereg];
1518
1519 return rexflags(val, flags, mask);
1520 }
1521
1522 static int rexflags(int val, int32_t flags, int mask)
1523 {
1524 int rex = 0;
1525
1526 if (val >= 8)
1527 rex |= REX_B|REX_X|REX_R;
1528 if (flags & BITS64)
1529 rex |= REX_W;
1530 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1531 rex |= REX_H;
1532 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1533 rex |= REX_P;
1534
1535 return rex & mask;
1536 }
1537
1538 static int matches(const struct itemplate *itemp, insn * instruction, int bits)
1539 {
1540 int i, size[3], asize, oprs, ret;
1541
1542 ret = 100;
1543
1544 /*
1545 * Check the opcode
1546 */
1547 if (itemp->opcode != instruction->opcode)
1548 return 0;
1549
1550 /*
1551 * Count the operands
1552 */
1553 if (itemp->operands != instruction->operands)
1554 return 0;
1555
1556 /*
1557 * Check that no spurious colons or TOs are present
1558 */
1559 for (i = 0; i < itemp->operands; i++)
1560 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
1561 return 0;
1562
1563 /*
1564 * Check that the operand flags all match up
1565 */
1566 for (i = 0; i < itemp->operands; i++) {
1567 if (itemp->opd[i] & ~instruction->oprs[i].type ||
1568 ((itemp->opd[i] & SIZE_MASK) &&
1569 ((itemp->opd[i] ^ instruction->oprs[i].type) & SIZE_MASK))) {
1570 if ((itemp->opd[i] & ~instruction->oprs[i].type & ~SIZE_MASK) ||
1571 (instruction->oprs[i].type & SIZE_MASK))
1572 return 0;
1573 else
1574 return 1;
1575 }
1576 }
1577
1578 /*
1579 * Check operand sizes
1580 */
1581 if (itemp->flags & IF_ARMASK) {
1582 size[0] = size[1] = size[2] = 0;
1583
1584 switch (itemp->flags & IF_ARMASK) {
1585 case IF_AR0:
1586 i = 0;
1587 break;
1588 case IF_AR1:
1589 i = 1;
1590 break;
1591 case IF_AR2:
1592 i = 2;
1593 break;
1594 default:
1595 break; /* Shouldn't happen */
1596 }
1597 if (itemp->flags & IF_SB) {
1598 size[i] = BITS8;
1599 } else if (itemp->flags & IF_SW) {
1600 size[i] = BITS16;
1601 } else if (itemp->flags & IF_SD) {
1602 size[i] = BITS32;
1603 } else if (itemp->flags & IF_SQ) {
1604 size[i] = BITS64;
1605 }
1606 } else {
1607 asize = 0;
1608 if (itemp->flags & IF_SB) {
1609 asize = BITS8;
1610 oprs = itemp->operands;
1611 } else if (itemp->flags & IF_SW) {
1612 asize = BITS16;
1613 oprs = itemp->operands;
1614 } else if (itemp->flags & IF_SD) {
1615 asize = BITS32;
1616 oprs = itemp->operands;
1617 } else if (itemp->flags & IF_SQ) {
1618 asize = BITS64;
1619 oprs = itemp->operands;
1620 }
1621 size[0] = size[1] = size[2] = asize;
1622 }
1623
1624 if (itemp->flags & (IF_SM | IF_SM2)) {
1625 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
1626 asize = 0;
1627 for (i = 0; i < oprs; i++) {
1628 if ((asize = itemp->opd[i] & SIZE_MASK) != 0) {
1629 int j;
1630 for (j = 0; j < oprs; j++)
1631 size[j] = asize;
1632 break;
1633 }
1634 }
1635 } else {
1636 oprs = itemp->operands;
1637 }
1638
1639 for (i = 0; i < itemp->operands; i++) {
1640 if (!(itemp->opd[i] & SIZE_MASK) &&
1641 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
1642 return 2;
1643 }
1644
1645 /*
1646 * Check template is okay at the set cpu level
1647 */
1648 if (((itemp->flags & IF_PLEVEL) > cpu))
1649 return 3;
1650
1651 /*
1652 * Check if instruction is available in long mode
1653 */
1654 if ((itemp->flags & IF_NOLONG) && (bits == 64))
1655 return 4;
1656
1657 /*
1658 * Check if special handling needed for Jumps
1659 */
1660 if ((uint8_t)(itemp->code[0]) >= 0370)
1661 return 99;
1662
1663 return ret;
1664 }
1665
1666 static ea *process_ea(operand * input, ea * output, int addrbits,
1667 int rfield, int32_t rflags, int forw_ref)
1668 {
1669 output->rip = FALSE;
1670
1671 /* REX flags for the rfield operand */
1672 output->rex |= rexflags(rfield, rflags, REX_R|REX_P|REX_W|REX_H);
1673
1674 if (!(REGISTER & ~input->type)) { /* register direct */
1675 int i;
1676 int32_t f;
1677
1678 if (input->basereg < EXPR_REG_START /* Verify as Register */
1679 || input->basereg >= REG_ENUM_LIMIT)
1680 return NULL;
1681 f = regflag(input);
1682 i = regvals[input->basereg];
1683
1684 if (REG_EA & ~f)
1685 return NULL; /* Invalid EA register */
1686
1687 output->rex |= op_rexflags(input, REX_B|REX_P|REX_W|REX_H);
1688
1689 output->sib_present = FALSE; /* no SIB necessary */
1690 output->bytes = 0; /* no offset necessary either */
1691 output->modrm = 0xC0 | ((rfield & 7) << 3) | (i & 7);
1692 } else { /* it's a memory reference */
1693 if (input->basereg == -1
1694 && (input->indexreg == -1 || input->scale == 0)) {
1695 /* it's a pure offset */
1696 if (input->addr_size)
1697 addrbits = input->addr_size;
1698
1699 if (globalbits == 64 && (~input->type & IP_REL)) {
1700 int scale, index, base;
1701 output->sib_present = TRUE;
1702 scale = 0;
1703 index = 4;
1704 base = 5;
1705 output->sib = (scale << 6) | (index << 3) | base;
1706 output->bytes = 4;
1707 output->modrm = 4 | ((rfield & 7) << 3);
1708 output->rip = FALSE;
1709 } else {
1710 output->sib_present = FALSE;
1711 output->bytes = (addrbits != 16 ? 4 : 2);
1712 output->modrm = (addrbits != 16 ? 5 : 6) | ((rfield & 7) << 3);
1713 output->rip = globalbits == 64;
1714 }
1715 } else { /* it's an indirection */
1716 int i = input->indexreg, b = input->basereg, s = input->scale;
1717 int32_t o = input->offset, seg = input->segment;
1718 int hb = input->hintbase, ht = input->hinttype;
1719 int t;
1720 int it, bt;
1721 int32_t ix, bx; /* register flags */
1722
1723 if (s == 0)
1724 i = -1; /* make this easy, at least */
1725
1726 if (i >= EXPR_REG_START && i < REG_ENUM_LIMIT) {
1727 it = regvals[i];
1728 ix = reg_flags[i];
1729 } else {
1730 it = -1;
1731 ix = 0;
1732 }
1733
1734 if (b != -1 && b >= EXPR_REG_START && b < REG_ENUM_LIMIT) {
1735 bt = regvals[b];
1736 bx = reg_flags[b];
1737 } else {
1738 bt = -1;
1739 bx = 0;
1740 }
1741
1742 /* check for a 32/64-bit memory reference... */
1743 if ((ix|bx) & (BITS32|BITS64)) {
1744 /* it must be a 32/64-bit memory reference. Firstly we have
1745 * to check that all registers involved are type E/Rxx. */
1746 int32_t sok = BITS32|BITS64;
1747
1748 if (it != -1) {
1749 if (!(REG64 & ~ix) || !(REG32 & ~ix))
1750 sok &= ix;
1751 else
1752 return NULL;
1753 }
1754
1755 if (bt != -1) {
1756 if (REG_GPR & ~bx)
1757 return NULL; /* Invalid register */
1758 if (~sok & bx & SIZE_MASK)
1759 return NULL; /* Invalid size */
1760 sok &= ~bx;
1761 }
1762
1763 /* While we're here, ensure the user didn't specify WORD. */
1764 if (input->addr_size == 16 ||
1765 (input->addr_size == 32 && !(sok & BITS32)) ||
1766 (input->addr_size == 64 && !(sok & BITS64)))
1767 return NULL;
1768
1769 /* now reorganize base/index */
1770 if (s == 1 && bt != it && bt != -1 && it != -1 &&
1771 ((hb == b && ht == EAH_NOTBASE)
1772 || (hb == i && ht == EAH_MAKEBASE))) {
1773 /* swap if hints say so */
1774 t = bt, bt = it, it = t;
1775 t = bx, bx = ix, ix = t;
1776 }
1777 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
1778 bt = -1, bx = 0, s++;
1779 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
1780 /* make single reg base, unless hint */
1781 bt = it, bx = ix, it = -1, ix = 0;
1782 }
1783 if (((s == 2 && it != REG_NUM_ESP
1784 && !(input->eaflags & EAF_TIMESTWO)) || s == 3
1785 || s == 5 || s == 9) && bt == -1)
1786 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
1787 if (it == -1 && (bt & 7) != REG_NUM_ESP
1788 && (input->eaflags & EAF_TIMESTWO))
1789 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
1790 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
1791 if (s == 1 && it == REG_NUM_ESP) {
1792 /* swap ESP into base if scale is 1 */
1793 t = it, it = bt, bt = t;
1794 t = ix, ix = bx, bx = t;
1795 }
1796 if (it == REG_NUM_ESP
1797 || (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
1798 return NULL; /* wrong, for various reasons */
1799
1800 output->rex |= rexflags(it, ix, REX_X);
1801 output->rex |= rexflags(bt, bx, REX_B);
1802
1803 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
1804 /* no SIB needed */
1805 int mod, rm;
1806
1807 if (bt == -1) {
1808 rm = 5;
1809 mod = 0;
1810 } else {
1811 rm = (bt & 7);
1812 if (rm != REG_NUM_EBP && o == 0 &&
1813 seg == NO_SEG && !forw_ref &&
1814 !(input->eaflags &
1815 (EAF_BYTEOFFS | EAF_WORDOFFS)))
1816 mod = 0;
1817 else if (input->eaflags & EAF_BYTEOFFS ||
1818 (o >= -128 && o <= 127 && seg == NO_SEG
1819 && !forw_ref
1820 && !(input->eaflags & EAF_WORDOFFS)))
1821 mod = 1;
1822 else
1823 mod = 2;
1824 }
1825
1826 output->sib_present = FALSE;
1827 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
1828 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
1829 } else {
1830 /* we need a SIB */
1831 int mod, scale, index, base;
1832
1833 if (it == -1)
1834 index = 4, s = 1;
1835 else
1836 index = (it & 7);
1837
1838 switch (s) {
1839 case 1:
1840 scale = 0;
1841 break;
1842 case 2:
1843 scale = 1;
1844 break;
1845 case 4:
1846 scale = 2;
1847 break;
1848 case 8:
1849 scale = 3;
1850 break;
1851 default: /* then what the smeg is it? */
1852 return NULL; /* panic */
1853 }
1854
1855 if (bt == -1) {
1856 base = 5;
1857 mod = 0;
1858 } else {
1859 base = (bt & 7);
1860 if (base != REG_NUM_EBP && o == 0 &&
1861 seg == NO_SEG && !forw_ref &&
1862 !(input->eaflags &
1863 (EAF_BYTEOFFS | EAF_WORDOFFS)))
1864 mod = 0;
1865 else if (input->eaflags & EAF_BYTEOFFS ||
1866 (o >= -128 && o <= 127 && seg == NO_SEG
1867 && !forw_ref
1868 && !(input->eaflags & EAF_WORDOFFS)))
1869 mod = 1;
1870 else
1871 mod = 2;
1872 }
1873
1874 output->sib_present = TRUE;
1875 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
1876 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
1877 output->sib = (scale << 6) | (index << 3) | base;
1878 }
1879 } else { /* it's 16-bit */
1880 int mod, rm;
1881
1882 /* check for 64-bit long mode */
1883 if (addrbits == 64)
1884 return NULL;
1885
1886 /* check all registers are BX, BP, SI or DI */
1887 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI
1888 && b != R_DI) || (i != -1 && i != R_BP && i != R_BX
1889 && i != R_SI && i != R_DI))
1890 return NULL;
1891
1892 /* ensure the user didn't specify DWORD/QWORD */
1893 if (input->addr_size == 32 || input->addr_size == 64)
1894 return NULL;
1895
1896 if (s != 1 && i != -1)
1897 return NULL; /* no can do, in 16-bit EA */
1898 if (b == -1 && i != -1) {
1899 int tmp = b;
1900 b = i;
1901 i = tmp;
1902 } /* swap */
1903 if ((b == R_SI || b == R_DI) && i != -1) {
1904 int tmp = b;
1905 b = i;
1906 i = tmp;
1907 }
1908 /* have BX/BP as base, SI/DI index */
1909 if (b == i)
1910 return NULL; /* shouldn't ever happen, in theory */
1911 if (i != -1 && b != -1 &&
1912 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
1913 return NULL; /* invalid combinations */
1914 if (b == -1) /* pure offset: handled above */
1915 return NULL; /* so if it gets to here, panic! */
1916
1917 rm = -1;
1918 if (i != -1)
1919 switch (i * 256 + b) {
1920 case R_SI * 256 + R_BX:
1921 rm = 0;
1922 break;
1923 case R_DI * 256 + R_BX:
1924 rm = 1;
1925 break;
1926 case R_SI * 256 + R_BP:
1927 rm = 2;
1928 break;
1929 case R_DI * 256 + R_BP:
1930 rm = 3;
1931 break;
1932 } else
1933 switch (b) {
1934 case R_SI:
1935 rm = 4;
1936 break;
1937 case R_DI:
1938 rm = 5;
1939 break;
1940 case R_BP:
1941 rm = 6;
1942 break;
1943 case R_BX:
1944 rm = 7;
1945 break;
1946 }
1947 if (rm == -1) /* can't happen, in theory */
1948 return NULL; /* so panic if it does */
1949
1950 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
1951 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
1952 mod = 0;
1953 else if (input->eaflags & EAF_BYTEOFFS ||
1954 (o >= -128 && o <= 127 && seg == NO_SEG
1955 && !forw_ref
1956 && !(input->eaflags & EAF_WORDOFFS)))
1957 mod = 1;
1958 else
1959 mod = 2;
1960
1961 output->sib_present = FALSE; /* no SIB - it's 16-bit */
1962 output->bytes = mod; /* bytes of offset needed */
1963 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
1964 }
1965 }
1966 }
1967
1968 output->size = 1 + output->sib_present + output->bytes;
1969 return output;
1970 }
1971
1972 static int chsize(operand * input, int addrbits)
1973 {
1974 if (!(MEMORY & ~input->type)) {
1975 int32_t i, b;
1976
1977 if (input->indexreg < EXPR_REG_START /* Verify as Register */
1978 || input->indexreg >= REG_ENUM_LIMIT)
1979 i = 0;
1980 else
1981 i = reg_flags[input->indexreg];
1982
1983 if (input->basereg < EXPR_REG_START /* Verify as Register */
1984 || input->basereg >= REG_ENUM_LIMIT)
1985 b = 0;
1986 else
1987 b = reg_flags[input->basereg];
1988
1989 if (input->scale == 0)
1990 i = 0;
1991
1992 if (!i && !b) /* pure offset */
1993 return (input->addr_size != 0 && input->addr_size != addrbits);
1994
1995 if (!(REG32 & ~i) || !(REG32 & ~b))
1996 return (addrbits != 32);
1997 else
1998 return (addrbits == 32);
1999 } else {
2000 return 0;
2001 }
2002 }
Automatic testing